Intel 815EG Design Manual
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Intel® 815EG Chipset Platform
For Use with Universal Socket 370
Design Guide
August 2002
Document Number: 298301-002
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applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
Implementations of the I
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Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Intel, Celeron, Pentium, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States
and other countries.
*Other names and brands may be claimed as the property of others.
Copyright
815 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
©
2001-2002, Intel Corporation
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
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Contents
1 Introduction ........................................................................................................................13
1.1 Design Guide and Chipset Basic Information .......................................................13
1.2 Terminology ..........................................................................................................14
1.3 Reference Documents ..........................................................................................16
1.4 System Overview ..................................................................................................17
1.4.1 System Features ...................................................................................18
1.4.2 Component Features.............................................................................19
1.4.2.1 Intel® 82815EG GMCH Features .........................................19
1.4.2.2 Intel® 815 to 815G/EG Signal Name Changes ....................20
1.4.2.3 Intel® 82801BA I/O Controller Hub 2 (ICH2) ........................21
1.4.2.4 Firmware Hub (FWH)...........................................................21
1.4.3 Platform Initiatives .................................................................................21
1.4.3.1 Universal Motherboard Design ............................................21
1.4.3.2 Intel® PC 133........................................................................22
1.4.3.3 Accelerated Hub Architecture Interface ...............................22
1.4.3.4 Internet Streaming SIMD Extensions...................................22
1.4.3.5 Integrated LAN Controller ....................................................22
1.4.3.6 Ultra ATA/100 Support .........................................................22
1.4.3.7 Expanded USB Support .......................................................22
1.4.3.8 Manageability and Other Enhancements ............................. 23
1.4.3.9 AC ’97 6-Channel Support ...................................................23
1.4.3.10 Low-Pin-Count (LPC) Interface ............................................26
2 General Design Considerations.........................................................................................27
2.1 Nominal Board Stack-Up ......................................................................................27
2.2 Future Designs Require Pull-Ups and Pull-Downs on Any Unused Input and
I/O Pins .................................................................................................................28
2.3 Support For P-MOS Kicker “ON”: SMAA[9] Is Strapped High by an Internal
50 kΩ Pull-Up Resistor .........................................................................................28
2.4 Electrostatic Discharge Platform Recommendations ...........................................28
3 Component Layouts...........................................................................................................31
4 Universal Socket 370 Design ............................................................................................35
4.1 Universal Socket 370 Definitions ..........................................................................35
4.2 Processor Design Requirements ..........................................................................37
4.2.1 Use of Universal Socket 370 Design with Incompatible GMCH............37
4.2.2 Identifying the Processor at the Socket .................................................38
4.2.3 Setting the Appropriate Processor VTT Level .......................................39
4.2.4 VTT Processor Pin AG1 ........................................................................40
4.2.5 Identifying the Processor at the GMCH.................................................41
4.2.6 Configuring Non-VTT Processor Pins ...................................................42
4.2.7 VCMOS Reference................................................................................43
4.2.8 Processor Signal PWRGOOD...............................................................44
4.2.9 APIC Clock Voltage Switching Requirements .......................................45
4.2.10 GTLREF Topology and Layout..............................................................46
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4.3
Power Sequencing on Wake Events ....................................................................47
4.3.1 Gating of Intel® CK-815 to VTTPWRGD ...............................................47
4.3.2 Gating of PWROK to Intel® ICH2 ..........................................................48
5 System Bus Design Guidelines .........................................................................................49
5.1 System Bus Routing Guidelines ...........................................................................49
5.1.1 Initial Timing Analysis ............................................................................ 49
5.2 General Topology and Layout Guidelines.............................................................52
5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signals ...........................53
5.2.1.1 Ground Reference ...............................................................53
5.2.1.2 Reference Plane Splits ........................................................53
5.2.1.3 Processor Connector Breakout............................................53
5.2.1.4 Minimizing Crosstalk ............................................................54
5.2.2 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals .....55
5.2.3 THRMDP and THRMDN .......................................................................56
5.2.4 Additional Routing and Placement Considerations ...............................56
5.3 Electrical Differences for Universal PGA370 Designs ..........................................57
5.3.1 THERMTRIP Circuit ..............................................................................57
5.3.1.1 THERMTRIP Timing ............................................................58
5.3.1.2 THERMTRIP Support for 0.13 Micron Technology
Processors, A-1 Stepping ....................................................58
5.4 PGA370 Socket Definition Details ........................................................................59
5.5 BSEL[1:0] Implementation Differences.................................................................62
5.6 CLKREF Circuit Implementation ...........................................................................63
5.7 Undershoot/Overshoot Requirements ..................................................................64
5.8 Processor Reset Requirements ............................................................................65
5.9 Processor PLL Filter Recommendations ..............................................................66
5.9.1 Topology................................................................................................ 66
5.9.2 Filter Specification .................................................................................66
5.9.3 Recommendation for Intel® Platforms ...................................................68
5.9.4 Custom Solutions ..................................................................................70
5.10 Voltage Regulation Guidelines..............................................................................70
5.11 Decoupling Guidelines for Universal PGA370 Designs ........................................70
5.11.1 VCC
Decoupling Design.................................................................70
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5.11.2 VTT Decoupling Design ........................................................................71
5.11.3 VREF Decoupling Design......................................................................71
5.12 Thermal Considerations........................................................................................72
5.12.1 Heatsink Volumetric Keep-Out Regions................................................72
5.12.2 Fan Heatsink Keep-Out Adherence for Future Boxed Intel® Celeron®
Processors ............................................................................................74
5.13 Debug Port Changes ............................................................................................75
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6 System Memory Design Guidelines...................................................................................77
6.1 System Memory Routing Guidelines.....................................................................77
6.2 System Memory 2-DIMM Design Guidelines ........................................................78
6.2.1 System Memory 2-DIMM Connectivity ..................................................78
6.2.2 System Memory 2-DIMM Layout Guidelines.........................................79
6.3 System Memory 3-DIMM Design Guidelines ........................................................81
6.3.1 System Memory 3-DIMM Connectivity ..................................................81
6.3.2 System Memory 3-DIMM Layout Guidelines.........................................82
6.4 System Memory Decoupling Guidelines ...............................................................83
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6.5
Compensation.......................................................................................................85
7 Display Cache Design Guidelines .....................................................................................87
7.1 Display Cache Interface........................................................................................87
7.2 GPA Card Considerations.....................................................................................87
7.3 GPA Mechanical Considerations ..........................................................................87
7.4 Display Cache Clocking ........................................................................................88
7.5 VDDQ Generation.................................................................................................88
8 Integrated Graphics Display Output...................................................................................89
8.1 Analog RGB/CRT..................................................................................................89
8.1.1 RAMDAC/Display Interface ...................................................................89
8.1.2 Reference Resistor (Rset) Calculation ..................................................91
8.1.3 RAMDAC Board Design Guidelines ......................................................91
8.1.4 RAMDAC Layout Recommendations ....................................................93
8.1.5 HSYNC/VSYNC Output Guidelines....................................................... 93
8.2 Intel® Digital Video Out..........................................................................................94
8.2.1 Intel® DVO Interface Routing Guidelines...............................................94
8.2.2 Intel® DVO I2C Interface Considerations ...............................................94
8.2.3 Leaving the Intel® DVO Port Unconnected............................................94
9 Hub Interface .....................................................................................................................97
9.1.1 Data Signals ..........................................................................................98
9.1.2 Strobe Signals .......................................................................................98
9.1.3 HREF Generation/Distribution...............................................................98
9.1.4 Compensation .......................................................................................99
10 I/O Controller Hub 2 (Intel® ICH2)....................................................................................101
10.1 Decoupling ..........................................................................................................101
10.2 Power Sequencing on Wake Events ..................................................................102
10.3 Power Supply PS_ON Considerations................................................................ 103
11 I/O Subsystem .................................................................................................................105
11.1 IDE Interface .......................................................................................................105
11.1.1 Cabling ................................................................................................105
11.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100.........................................105
11.2.1 Combination Host-Side/Device-Side Cable Detection ........................106
11.2.2 Device-Side Cable Detection...............................................................107
11.2.3 Primary IDE Connector Requirements ................................................108
11.2.4 Secondary IDE Connector Requirements ...........................................109
11.3 AC ’97 .................................................................................................................110
11.3.1 Communications Network Riser (CNR)...............................................111
11.3.2 AC ’97 Audio Codec Detect Circuit and Configuration Options...........112
11.3.2.1 Valid Codec Configurations ...............................................115
11.3.3 SPKR Pin Considerations....................................................................115
11.3.4 AC ’97 Routing ....................................................................................116
11.3.5 Motherboard Implementation ..............................................................117
11.4 USB.....................................................................................................................118
11.4.1 Using Native USB Interface.................................................................118
11.4.2 Disabling the Native USB Interface of ICH2........................................119
11.5 I/O APIC Design Recommendation ....................................................................119
11.5.1 PIRQ Routing Example .......................................................................120
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11.6
SMBus/SMLink Interface ....................................................................................121
11.6.1 SMBus Architecture and Design Considerations ................................122
11.6.1.1 General Design Issues and Notes .....................................122
11.7 PCI ......................................................................................................................125
11.8 RTC.....................................................................................................................126
11.8.1 RTC Crystal.........................................................................................126
11.8.2 External Capacitors .............................................................................127
11.8.3 RTC Layout Considerations ................................................................127
11.8.4 RTC External Battery Connection .......................................................127
11.8.5 RTC External RTCRST Circuit ............................................................129
11.8.6 Power-Well Isolation Control Requirements .......................................129
11.8.7 RTC Routing Guidelines...................................................................... 130
11.8.8 VBIAS DC Voltage and Noise Measurements ....................................131
11.9 LAN Layout Guidelines .......................................................................................131
11.9.1 Intel® ICH2 – LAN Interconnect Guidelines .........................................132
11.9.1.1 Bus Topologies ..................................................................133
11.9.1.2 Point-to-Point Interconnect ................................................133
11.9.1.3 LOM/CNR Interconnect......................................................134
11.9.1.4 Signal Routing and Layout .................................................135
11.9.1.5 Crosstalk Consideration.....................................................135
11.9.1.6 Impedances .......................................................................135
11.9.1.7 Line Termination ................................................................136
11.9.2 General LAN Routing Guidelines and Considerations ........................136
11.9.2.1 General Trace Routing Considerations..............................136
11.9.2.2 Power and Ground Connections........................................138
11.9.2.3 A 4-Layer Board Design.....................................................139
11.9.2.4 Common Physical Layout Issues .......................................139
11.9.3 Intel® 82562EH Home/PNA* Guidelines..............................................141
11.9.3.1 Power and Ground Connections........................................141
11.9.3.2 Guidelines for Intel® 82562EH Component Placement......141
11.9.3.3 Crystals and Oscillators .....................................................142
11.9.3.4 Phoneline HPNA Termination ............................................142
11.9.3.5 Critical Dimensions ............................................................143
11.9.4 Intel® 82562ET / Intel® 82562EM Guidelines ......................................144
11.9.4.1 Guidelines for Intel® 82562ET / Intel® 82562EM Component
Placement ..........................................................................144
11.9.4.2 Crystals and Oscillators .....................................................145
11.9.4.3 Intel® 82562ET / Intel® 82562EM Termination Resistors...145
11.9.4.4 Critical Dimensions ............................................................145
11.9.4.5 Reducing Circuit Inductance ..............................................147
11.9.5 Intel® 82562ET/82562EM Disable Guidelines .....................................148
11.9.6 Intel® 82562ET / Intel® 82562EH Dual Footprint Guidelines ...............149
11.10 LPC/FWH............................................................................................................151
11.10.1 In-Circuit FWH Programming ..............................................................151
11.10.2 FWH VPP Design Guidelines ...............................................................151
11.10.3 FWH Decoupling .................................................................................152
12 Clocking ...........................................................................................................................153
12.1 2-DIMM Clocking ................................................................................................153
12.2 3-DIMM Clocking ................................................................................................155
12.3 Clock Routing Guidelines.................................................................................... 157
12.4 Clock Driver Frequency Strapping ......................................................................159
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12.5
Clock Skew Assumptions ...................................................................................160
12.6 Intel® CK-815 Power Gating On Wake Events ...................................................161
13 Power Delivery.................................................................................................................163
13.1 Power Delivery Guidelines..................................................................................163
13.1.1 5V Dual Switch ....................................................................................165
13.1.2 VTT......................................................................................................165
13.1.3 1.85 V ..................................................................................................165
13.1.4 VDDQ ..................................................................................................165
13.1.5 3.3VSB ................................................................................................166
13.1.6 1.85VSB ..............................................................................................166
13.1.7 VCMOS ...............................................................................................166
13.2 Thermal Design Power .......................................................................................167
13.2.1 Pull-Up and Pull-Down Resistor Values ..............................................167
13.3 ATX Power Supply PWRGOOD Requirements..................................................168
13.4 Power Management Signals ...............................................................................168
13.4.1 Power Button Implementation .............................................................169
13.4.2 1.85 V/3.3 V Power Sequencing..........................................................170
13.4.3 V5REF/3.3 V Sequencing....................................................................171
13.5 Power Plane Splits ..............................................................................................172
13.6 Glue Chip 3 (ICH2 Glue Chip) ............................................................................173
14 System Design Checklist ................................................................................................. 175
14.1 Design Review Checklist ....................................................................................175
14.2 Processor Checklist ............................................................................................175
14.2.1 GTL Checklist......................................................................................175
14.2.2 CMOS Checklist ..................................................................................176
14.2.3 TAP Checklist for 370-Pin Socket Processors ....................................176
14.2.4 Miscellaneous Checklist for 370-Pin Socket Processors ....................177
14.3 GMCH Checklist .................................................................................................178
14.3.1 System Memory Interface Checklist....................................................178
14.3.2 Hub Interface Checklist .......................................................................178
14.3.3 Digital Video Output Port Checklist .....................................................179
14.4 Intel® ICH2 Checklist...........................................................................................179
14.4.1 PCI Interface .......................................................................................179
14.4.2 Hub Interface.......................................................................................179
14.4.3 LAN Interface ......................................................................................180
14.4.4 EEPROM Interface..............................................................................180
14.4.5 FWH/LPC Interface ............................................................................. 180
14.4.6 Interrupt Interface ................................................................................180
14.4.7 GPIO Checklist....................................................................................182
14.4.8 USB .....................................................................................................182
14.4.9 Power Management ............................................................................183
14.4.10 Processor Signals ...............................................................................184
14.4.11 System Management ..........................................................................184
14.4.12 RTC ...........................................................................................184
14.4.13 AC ’97 ...........................................................................................185
14.4.14 Miscellaneous Signals ......................................................................... 186
14.4.15 Power ...........................................................................................187
14.4.16 IDE Checklist .......................................................................................188
14.5 LPC Checklist .....................................................................................................190
14.6 System Checklist ................................................................................................191
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14.7
FWH Checklist .................................................................................................... 191
14.8 Clock Synthesizer Checklist................................................................................192
14.9 System Memory Checklist ..................................................................................193
14.10 Power Delivery Checklist ....................................................................................193
15 Third-Party Vendor Information .......................................................................................195
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Figures
Figure 1. System Block Diagram .......................................................................................18
Figure 2. Component Block Diagram ................................................................................19
Figure 3. AC ’97 Audio and Modem Connections .............................................................25
Figure 4. Board Construction Example for 60 Ω Nominal Stack-up .................................. 27
Figure 5. Top Signal Layer before the Ground Fill Near the I/O Layer ..............................29
Figure 6. Top Signal Layer after the Ground Fill Near the I/O Layer .................................29
Figure 7. Bottom Signal Layer before the Ground Fill Near the I/O Area ..........................30
Figure 8. Bottom Signal Layer after the Ground Fill Near the I/O......................................30
Figure 9. GMCH 544-Ball µBGA* CSP Quadrant Layout (Top View)................................31
Figure 10. ICH2 360-Ball EBGA Quadrant Layout (Top View) ..........................................32
Figure 11. Firmware Hub (FWH) Packages ......................................................................33
Figure 12. Future 0.13 Micron Socket 370 Processor Safeguard for Universal Socket 370
Designs Using A-2 GMCH..........................................................................................37
Figure 13. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit ................38
Figure 14. VTT Selection Switch ........................................................................................39
Figure 15. Switching Pin AG1............................................................................................40
Figure 16. Processor Identification Strap on GMCH .........................................................41
Figure 17. VTTPWRGD Configuration Circuit ...................................................................42
Figure 18. GTL_REF/VCMOS_REF Voltage Divider Network ..........................................43
Figure 19. Resistor Divider Network for Processor PWRGOOD....................................... 44
Figure 20 Voltage Switch for Processor APIC Clock .........................................................45
Figure 21. GTLREF Circuit Topology ................................................................................46
Figure 22. Gating Power to Intel® CK-815 .........................................................................47
Figure 23 PWROK Gating Circuit for Intel® ICH2..............................................................48
Figure 24. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)..52
Figure 25. AGTL/AGTL+ Trace Routing............................................................................53
Figure 26. Routing for THRMDP and THRMDN................................................................56
Figure 27. Example Implementation of THERMTRIP Circuit ............................................57
Figure 28 Thermtrip Support for A-1 Stepping 0.13 Micron Technology Processors........59
Figure 29. BSEL[1:0] Circuit Implementation for PGA370 Designs...................................63
Figure 30. Examples for CLKREF Divider Circuit..............................................................64
Figure 31. RESET#/RESET2# Routing Guidelines ...........................................................65
Figure 32. Filter Specification ............................................................................................67
Figure 33. Example PLL Filter Using a Discrete Resistor .................................................69
Figure 34. Example PLL Filter Using a Buried Resistor ....................................................69
Figure 35. Core Reference Model .....................................................................................70
Figure 36. Capacitor Placement on the Motherboard........................................................71
Figure 37. Heatsink Volumetric Keep-Out Regions ...........................................................73
Figure 38 Motherboard Component Keep-Out Regions .................................................... 73
Figure 39. Keep-Out Requirements for the 370-pin (Top View) ........................................ 74
Figure 40. TAP Connector Comparison ............................................................................75
Figure 41. System Memory Routing Guidelines ................................................................77
Figure 42. System Memory Connectivity (2 DIMM) ...........................................................78
Figure 43. System Memory 2-DIMM Routing Topologies..................................................79
Figure 44. System Memory Routing Example ...................................................................80
Figure 45. System Memory Connectivity (3 DIMM) ...........................................................81
Figure 46. System Memory 3-DIMM Routing Topologies..................................................82
Figure 47. Intel 815 Chipset Platform Decoupling Example ............................................83
Figure 48. Intel® 815 Chipset Decoupling Example...........................................................84
Figure 49. Display Cache Input Clocking...........................................................................88
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Figure 50. Schematic of RAMDAC Video Interface...........................................................90
Figure 51. Cross-Sectional View of a Four-Layer Board ...................................................91
Figure 52. Recommended RAMDAC Component Placement and Routing ......................92
Figure 53. Recommended RAMDAC Reference Resistor Placement and Connections ..93
Figure 54. Hub Interface Signal Routing Example ............................................................97
Figure 55. Single Hub Interface Reference Divider Circuit ................................................99
Figure 56. Locally Generated Hub Interface Reference Dividers ......................................99
Figure 57. Intel® ICH2 Decoupling Capacitor Layout.......................................................102
Figure 58. Combination Host-Side / Device-Side IDE Cable Detection ..........................106
Figure 59. Device-Side IDE Cable Detection...................................................................107
Figure 60. Connection Requirements for Primary IDE Connector...................................108
Figure 61. Connection Requirements for Secondary IDE Connector.............................. 109
Figure 62. Intel® ICH2 AC ’97– Codec Connection .........................................................110
Figure 63. CNR Interface.................................................................................................111
Figure 64. CDC_DN_ENAB# Support Circuitry for a Single Codec on Motherboard......112
Figure 65. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade..........113
Figure 66. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard /
One-Codec on CNR .................................................................................................114
Figure 67. CDC_DN_ENAB# Support for Two-Codecs on Motherboard /
Two-Codecs on CNR ...............................................................................................114
Figure 68. Example Speaker Circuit................................................................................116
Figure 69. USB Data Signals...........................................................................................119
Figure 70. Example PIRQ Routing ..................................................................................120
Figure 71. SMBus/SMLink Interface ................................................................................121
Figure 72. Unified VCC_Suspend Architecture ...............................................................123
Figure 73. Unified VCC
Figure 74. Mixed VCC_Suspend/VCC
Architecture......................................................................... 123
CORE
Architecture .................................................124
CORE
Figure 75. PCI Bus Layout Example................................................................................125
Figure 76. External Circuitry for the ICH2 RTC ...............................................................126
Figure 77. Diode Circuit to Connect RTC External Battery..............................................128
Figure 78. RTCRST External Circuit for ICH2 RTC ........................................................129
Figure 79. RTC Power Well Isolation Control..................................................................130
Figure 80. Intel® ICH2 / LAN Connect Section ................................................................132
Figure 81. Single-Solution Interconnect...........................................................................133
Figure 82. LOM/CNR Interconnect ..................................................................................134
Figure 83. LAN_CLK Routing Example ...........................................................................135
Figure 84. Trace Routing .................................................................................................137
Figure 85. Ground Plane Separation ...............................................................................138
Figure 86. Intel® 82562EH Termination ...........................................................................142
Figure 87. Critical Dimensions for Component Placement..............................................143
Figure 88. Intel® 82562ET/Intel® 82562EM Termination .................................................145
Figure 89. Critical Dimensions for Component Placement..............................................146
Figure 90. Termination Plane ..........................................................................................148
Figure 91. Intel® 82562ET/82562EM Disable Circuit.......................................................148
Figure 92. Dual-Footprint LAN Connect Interface ...........................................................149
Figure 93. Dual-Footprint Analog Interface .....................................................................149
Figure 94. FWH VPP Isolation Circuitry ..........................................................................151
Figure 95. Platform Clock Architecture for a 2-DIMM Solution........................................154
Figure 96. Platform Clock Architecture for a 3-DIMM Solution........................................156
Figure 97. Clock Routing Topologies ..............................................................................157
Figure 98. Power Delivery Map........................................................................................164
Figure 99. Pull-Up Resistor Example ..............................................................................167
Figure 100. Example 1.85 V/3.3 V Power Sequencing Circuit ........................................170
Figure 101. V5REF/3.3 V Sequencing Circuitry ..............................................................171
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Tables
Figure 102. Power Plane Split Example ..........................................................................172
Figure 103. USB Data Line Schematic ............................................................................183
Figure 104. Intel® ICH2 Oscillator Circuitry......................................................................185
Figure 105. SPKR Circuitry..............................................................................................186
Figure 106. V5REF Circuitry............................................................................................187
Figure 107. Host/Device Side Detection Circuitry............................................................189
Figure 108. Device Side Only Cable Detection ...............................................................189
Table 1. Intel® 82815 to Intel® 82815G Pin Name Changes..............................................20
Table 2. Processor Considerations for Universal Socket 370 Design...............................35
Table 3. GMCH Considerations for Universal Socket 370 Design ....................................36
Table 4. Intel® ICH2 Considerations for Universal Socket 370 Design .............................36
Table 5. Clock Synthesizer Considerations for Universal Socket 370 Design ..................37
Table 6. Determining the Installed Processor via Hardware Mechanisms ........................41
Table 7. Intel® Pentium® III Processor AGTL/AGTL+ Parameters for Example
Calculations ................................................................................................................50
Table 8. Example T
Table 9. Example T
Calculations for 133 MHz Bus ................................................51
FLT_MAX
Calculations (Frequency Independent) ....................................51
FLT_MIN
Table 10. Trace Guidelines for Figure 24..........................................................................52
Table 11. Trace Width: Space Guidelines ......................................................................... 52
Table 12. Routing Guidelines for Non-AGTL/AGTL+ Signals ...........................................55
Table 13. Processor Pin Definition Comparison................................................................ 59
Table 14. Resistor Values for CLKREF Divider (3.3 V Source)......................................... 64
Table 15. RESET#/RESET2# Routing Guidelines (see Figure 31)...................................65
Table 16. Component Recommendations – Inductor........................................................68
Table 17. Component Recommendations – Capacitor .....................................................68
Table 18. Component Recommendation – Resistor .........................................................68
Table 19. System Memory 2-DIMM Solution Space..........................................................79
Table 20. System Memory 3-DIMM Solution Space..........................................................82
Table 21. Decoupling Capacitor Recommendation .........................................................101
Table 22. Signal Descriptions ..........................................................................................115
Table 23. Codec Configurations ......................................................................................115
Table 24. IOAPIC Interrupt Inputs 16 thru 23 Usage.......................................................120
Table 25. Pull-Up Requirements for SMBus and SMLink................................................122
Table 26. LAN Connect ...................................................................................................131
Table 27. Single-Solution Interconnect Length Requirements (See Figure 81) ..............133
Table 28. LOM/CNR Length Requirements (See Figure 82)...........................................134
Table 29. Critical Dimensions for Component Placement (Refer to Figure 87) ..............143
Table 30. Critical Dimensions for Component Placement (see Figure 89) .....................146
Table 31. Intel® 82562ET Operating States.....................................................................149
Table 32. Intel® CK-815 (2-DIMM) Clocks ....................................................................... 153
Table 33. Intel® CK-815 (3-DIMM) Clocks ....................................................................... 155
Table 34. Simulated Clock Routing Solution Space ........................................................158
Table 35. Simulated Clock Skew Assumptions ...............................................................160
Table 36. Power Delivery Definitions...............................................................................163
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Revision History
Rev. No. Description Rev. Date
-001 • Initial Release. Sept 2001
-002 • Added Section 2.4, Electrostatic Discharge Platform
Recommendations
• Replaced Figure 98, Power Delivery Map, in Section 13, Power
Delivery
• Revised Section 13.4.3, 3.3V/V5REF Sequencing
• Revised Table 33. Intel
(3-DIMM) Clocks, in Section 12.2, 3-DIMM Clocking
• Revised Table 32, Intel
12.1, 2-DIMM Clocking
• Replaced Figure 79, RTC Power Well Isolation Control, in Section
11.8.6, Power Well Isolation Control Requirements
• Replaced Figure 84, Trace Routing, in Section 11.9.2.1, General
Trace Routing Considerations
• Revised Section 13.4.3, 3.3V/V5REF Sequencing
• Revised Checklist Recommendations for 5V_REF_SUS in
Section 14.4.15, Power
• Added SUSCLK to the RTC Checklist in Section 14.4.12
• Added Section 10.3 Power Supply PS_ON Considerations
®
CK-815 (3-DIMM) Clocks, Intel® CK-815
®
CK-815 (2-DIMM) Clocks, in Section
Aug 2002
R
®
12 Intel
815EG Chipset Platform Design Guide
Introduction
R
1 Introduction
1.1 Design Guide and Chipset Basic Information
This design guide organizes Intel design recommendations for the Intel® 815EG chipset platform
for use with universal socket 370. In addition to providing motherboard design recommendations
(e.g., layout and routing guidelines), this document also addresses system design issues (e.g.,
thermal requirements) for the chipset platform.
This design guide contains design recommendations, debug recommendations, and a system
checklist. These design guidelines are developed to ensure maximum flexibility for board
designers while reducing the risk of board-related issues.
Consult the debug recommendations when debugging your design. However, these debug
recommendations should be understood before completing board design to ensure that the debug
port, in addition to other debug features, are implemented correctly.
There is no AGP port capability in the Intel
®
82815EG GMCH. The 82815EG uses internal
graphics only.
There are six chipsets in the Intel
®
• Intel
• Intel
• Intel
82815 chipset: This chipset contains the Intel 82815 and the Intel® 82801AA ICH.
®
82815E chipset: This chipset contains the Intel 82815E and the Intel® 82801BA ICH2.
®
82815P chipset: This chipset contains the Intel 82815P and the 82801AA ICH. There is
815 chipset family:
no internal graphics capability. This GMCH uses an AGP port only.
®
• Intel
82815EP chipset: This chipset contains the Intel 82815EP and the 82801BA ICH2.
There is no internal graphics capability. This GMCH uses an AGP port only.
®
• Intel
82815G chipset: This chipset contains the 82815G GMCH and 82801AA ICH. There is
no AGP port capability. This GMCH uses internal graphics only.
®
• Intel
82815EG chipset. This chipset contains the 82815EG GMCH and Intel 82801BA
ICH2. There is no AGP port capability. This GMCH uses internal graphics only.
The only component difference between the 82815 GMCH and the 82815E GMCH is the I/O
Controller Hub. The only component difference between the 82815P GMCH and the 82815EP
GMCH is the I/O Controller Hub. The only component difference between the 82815G GMCH
and the 82815EG GMCH is the I/O Controller Hub.
The Intel 815EG chipset platform supports the following processors:
®
• Intel
• Intel
Pentium® III processor based on 0.18 micron technology (CPUID = 068xh).
®
Celeron® processor based on 0.18 micron technology (CPUID = 068xh). This applies to
Celeron 533A MHz and ≥566 MHz processors
• Future 0.13 micron socket 370 processors
®
815EG Chipset Platform Design Guide 13
Intel
Introduction
The system bus speed supported by the design is based on the capabilities of the processor,
chipset, and clock driver.
The 815 chipset for use with the universal socket 370 is not compatible with the
®
Intel
Pentium® II processor (CPUID = 066xh) 370-pin socket.
1.2 Terminology
This section describes some of the terms used in this document. Additional power delivery term
definitions are provided at the beginning of Chapter13, “Power Delivery”.
Term Description
AGP Accelerated Graphics Port
R
AGTL/AGTL+ Refers to processor bus signals that are implemented using either Assisted
Bus Agent A component or group of components that, when combined, represent a single load
Crosstalk The reception on a victim network of a signal imposed by aggressor network(s)
GMCH Graphics and Memory Controller Hub. A component of the Intel 815 chipset
ICH Intel 82801AA I/O Controller Hub component.
ISI Inter-symbol interference is the effect of a previous signal (or transition) on the
Gunning Transceiver Logic (AGTL+) or its lower voltage variant (AGTL), depending
on which processor is being used.
on the AGTL+ bus.
through inductive and capacitive coupling between the networks.
• Backward Crosstalk–coupling that creates a signal in a victim network that travels
in the opposite direction as the aggressor’s signal.
• Forward Crosstalk–coupling that creates a signal in a victim network that travels
in the same direction as the aggressor’s signal.
• Even Mode Crosstalk–coupling from single or multiple aggressors when all the
aggressors switch in the same direction that the victim is switching.
• Odd Mode Crosstalk–coupling from single or multiple aggressors when all the
aggressors switch in the opposite direction that the victim is switching.
platform for use with the Universal Socket 370
interconnect delay. For example, when a signal is transmitted down a line and the
reflections due to the transition have not completely dissipated, the following data
transition launched onto the bus is affected. ISI is dependent upon frequency, time
delay of the line, and the reflection coefficient at the driver and receiver. ISI can
impact both timing and signal integrity.
Network Length The distance between agent 0 pins and the agent pins at the far end of the bus.
Pad The electrical contact point of a semiconductor die to the package substrate. A pad
Pin The contact point of a component package to the traces on a substrate such as the
14 Intel
is only observable in simulation.
motherboard. Signal quality and timings can be measured at the pin.
®
815EG Chipset Platform Design Guide
Introduction
R
Term Description
Ringback The voltage that a signal rings back to after achieving its maximum absolute value.
Ringback may be due to reflections, driver oscillations, or other transmission line
phenomena.
Setup Window The time between the beginning of Setup to Clock (T
) and the arrival of a
SU_MIN
valid clock edge. This window may be different for each type of bus agent in the
system.
SSO Simultaneous Switching Output (SSO) Effects refers to the difference in electrical
timing parameters and degradation in signal quality caused by multiple signal
outputs simultaneously switching voltage levels (e.g., high-to-low) in the opposite
direction from a single signal (e.g., low-to-high) or in the same direction (e.g., highto-low). These are respectively called odd-mode switching and even-mode
switching. This simultaneous switching of multiple outputs creates higher current
swings that may cause additional propagation delay (or “push-out”), or a decrease
in propagation delay (or “pull-in”). These SSO effects may impact the setup and/or
hold times and are not always taken into account by simulations. System timing
budgets should include margin for SSO effects.
Stub The branch from the bus trunk terminating at the pad of an agent.
System Bus The system bus is the processor bus.
Trunk The main connection, excluding interconnect branches, from one end agent pad to
the other end agent pad.
Undershoot Minimum voltage observed for a signal to extend below VSS at the device pad.
Universal Socket 370 Refers to the Intel 815EG chipset using the “universal” PGA370 socket. In general,
these designs support 66/100/133 MHz system bus operation, Intel
guidelines for future 0.13 micron processors, and Celeron
(CPUID=068xh), Pentium
®
III processor (CPUID=068xh), and future Celeron and
®
®
VRM
processors
Pentium III processors using 0.13 micron technology in single-microprocessor
based designs.
Victim A network that receives a coupled crosstalk signal from another network is called
the victim network.
®
815EG Chipset Platform Design Guide 15
Intel
Introduction
1.3 Reference Documents
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Document Document Number /
Intel® 815 Chipset Family: 82815G/82815EG Graphic s and Memory Controller
Hub (GMCH) for use with the Univ ersal Socket 370 Datasheet
Intel® 82802AB/82802AC Firmware Hub (FWH) Datasheet Doc 290658
Intel® 82801BA I/O Controller Hub (ICH2) and Intel® 82801BAM I/O Controller
Hub (ICH2-M) Datasheet
Intel® Pentium® III Processor Specification Update (latest revision from website) http://developer.intel.co
AP 907 Intel® Pentium® III Processor Power Distribution Guidelines Doc 245085
AP-585 Intel® Pentium® II Processor AGTL+ Guidelines Doc 243330
AP-587 Intel® Pentium® II Processor Power Distribution Guidelines Doc 243332
Accelerated Graphics P ort Interface Specification, Revision 2.0 http://www.intel.com/te
Graphics Performance Accel erator Specification ftp://download.intel.co
PCI Local Bus Specification, Revision 2. 2 http://www.pcisig.com/s
AC ’97 Component Specification, Revision 2.2
Communication Network Riser Specification, Revision 1.1 http://developer.intel.co
Universal Serial Bus, Revision 2.0 Specification http://www.usb.org/dev
(1)
http://developer.intel.co
Location
Doc 290714
Intel developer website
Intel developer website
Doc 290687
Intel developer website
m/design/PentiumIII/sp
ecupdt/
Intel developer website
Intel developer website
Intel developer website
chnology/agp/agp_inde
x.htm)
m/technology/agp/dow
nloads/agp20.pdf
pecifications/conventio
nal_pci
m/ial/scalableplatforms
/audio/index.htm
m/technology/cnr/
elopers/usb20/
NOTES:
1. Throughout this document, this specification will be referred to as AC ’97 v2.2.
®
16 Intel
815EG Chipset Platform Design Guide
Introduction
R
1.4 System Overview
The 815EG chipset platform for use with the universal socket 370 contains a Graphics and
Memory Controller Hub (GMCH) component and I/O Controller Hub 2 (ICH2) component for
desktop platforms.
The GMCH provides the processor interface (optimized for future 0.13 micron Celeron processors
and Pentium III processors (socket 370) and the Pentium III processors (CPUID = 068xh), DRAM
interface, hub interface, and internal graphics. It does not provide support for an external AGP
port. This product provides flexibility and scalability in memory subsystem performance. PC100
SDRAM system memory may be scaled to PC133 system memory.
The Accelerated Hub Architecture interface (i.e., the chipset component interconnect) is designed
into the chipset to provide an efficient, high-bandwidth communication channel between the
GMCH and the I/O controller hub. The chipset architecture also enables a security and
manageability infrastructure through the Firmware Hub component.
An ACPI-compliant 815EG chipset platform can support the Full-on (S0), Stop Grant (S1),
Suspend to RAM (S3), Suspend to Disk (S4), and Soft-off (S5) power management states. The
chipset also supports wake-on-LAN for remote administration and troubleshooting. The chipset
architecture removes the requirement for the ISA expansion bus that was traditionally integrated
into the I/O subsystem of PCIsets/AGPsets. This removes many of the conflicts experienced when
installing hardware and drivers into legacy ISA systems. The elimination of ISA provides true
plug-and-play for the platform. Traditionally, the ISA interface was used for audio and modem
devices. The addition of AC ’97 allows the OEM to use software-configurable AC ’97 audio and
modem coder/decoders (codecs), instead of the traditional ISA devices.
®
815EG Chipset Platform Design Guide 17
Intel
Introduction
1.4.1 System Features
The 815EG chipset platform contains two components: the 82815EG Graphics and Memory
Controller Hub (GMCH) and the 82801BA I/O Controller Hub 2 (ICH2). The GMCH integrates a
66/100/133 MHz, P6 family system bus controller, integrated 2D/3D graphics accelerator,
100/133 MHz SDRAM controller, and a high-speed accelerated hub architecture interface for
communication with the ICH2. The ICH2 integrates an UltraATA/100 controller, 2 Universal
Serial Bus (USB) host controllers with a total of 4 ports, Low Pin Count (LPC) interface
controller, Firmware Hub (FWH) interface controller, PCI interface controller, AC-link, integrated
LAN controller, and a hub interface for communication with the GMCH.
Figure 1. System Block Diagram
Intel Celeron and Pentium III
Processors Using 0.13 Micron
Technology
R
Display Cache
AIMM
(AGP in-line memory module)
Analog display out
Digital video out
Audio codec
Modem codec
LAN connect
component
4x USB
2x IDE
AC97
LAN
connect
815EG
Chipset
82815EG B-0
GMCH
82801BA ICH2
FWH
Flash BIOS
66/100/133 MHz system bus
Hub interface
PCI bus
LPC I/F
Sys_Blk_815E_B0
100/133 MHz
SDRAM
PCI slots
KBC/SIO
®
18 Intel
815EG Chipset Platform Design Guide
Introduction
R
1.4.2 Component Features
Figure 2. Component Block Diagram
System bus (66/100/133 MHz)
Processor I/F
Data
stream
GPA or AIMM
Card
Local memory I/F
control &
dispatch
Hub I/F
Hub
1.4.2.1 Intel® 82815EG GMCH Features
• Processor/System Bus Support
Optimized for Celeron and Pentium III processors which use 0.13 micron technology at
133 MHz system bus frequency
Support for Celeron and Pentium III processors (CPUID = 068xh); at 66 MHz system bus
frequency
Supports 32-bit AGTL or AGTL+ bus addressing
Supports uniprocessor systems
Utilizes AGTL and AGTL+ bus driver technology (gated AGTL/AGTL+ receivers for
reduced power)
Primary display
Overlay
H/W cursor
3D pipeline
2D (blit engine)
System
memory I/F
RAMDAC
FP / TVout
Internal graphics
comp_blk_1
SDRAM
100/133
MHz, 64 bit
Monitor
Digital
video out
• Integrated DRAM controller
32 MB to 512 MB using 16-Mb/64-Mb/128-Mb technology
Supports up to three double-sided DIMMS (6 rows)
100 MHz, 133 MHz SDRAM interface
64-bit data interface
Standard Synchronous DRAM (SDRAM) support (x-1-1-1 access)
Supports only 3.3 V DIMM DRAM configurations
No registered DIMM support
Support for symmetrical and asymmetrical DRAM addressing
Support for x8, x16 DRAM device widths
Refresh mechanism: CAS-before-RAS only
Support for DIMM serial PD (presence detect) scheme via SMbus interface
Suspend-To-RAM (STR) power management support via self-refresh mode using CKE
®
815EG Chipset Platform Design Guide 19
Intel
Introduction
• Integrated Graphics Controller
Full 2D/3D/DirectX acceleration
Texture-mapped 3D with point sampled, bilinear, trilinear, and anisotropic filtering
Hardware setup with support for strips and fans
Hardware motion compensation assist for software MPEG/DVD decode
Digital Video Out interface for support of digital displays and TV-Out
PC99A/PC2001 compliant
Integrated 230 MHz DAC
• Integrated Local Graphics Memory Controller (Display Cache)
0 MB to 4 MB (via Graphics Performance Accelerator) using zero, one or two parts
32-bit data interface
133 MHz memory clock
Supports only 3.3 V SDRAMs
• Packaging/Power
544-ball mBGA CSP with local memory port
1.85 V core and mixed 3.3 V, 1.5 V, and AGTL+ IO. Note that the 82801BA ICH2 has a
1.8 V requirement and the 82815EG GMCH has a 1.85 V requirement. Instead of using
separate voltage regulators to meet these requirements, a single voltage regulator can be
set to 1.795 V to 1.910 V. See Figure 98. Power Delivery Map.
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1.4.2.2 Intel® 815 to 815G/EG Signal Name Changes
Intel 82815G/EG pins associated with AGP signals have name changes. The following table shows
the old Intel 82815 signal name, the ball number, and the new Intel 82815G/EG signal name. New
designs for new 815G/EG boards should use pull-ups or pull-downs as indicated by the 815G/EG
signal name. 815 boards using 815GEG devices may leave the associated 815 pins in the original
815 configuration.
Table 1. Intel
NOTES:
®
82815 to Intel® 82815G Pin Name Changes
Intel® 815 Signal
Name
WBF# AB24 PU
AD_STB0 M22 PD
AD_STB0# L23 PU
AD_STB1 U22 PD
AD_STB1# V23 PU
SB_STB Y23 PD
SB_STB# AA24 PU
GRCOMP J26 PD40
AGPREF J24 0.5VDDQ
G_GNT# AD25 NC
G_AD[24] V25 PD
NC = No Connect. These pins should float
PU = Pull-up to 3.3 V through a weak pull-up resistor. (8.2 kΩ to 10 kΩ resistor.)
PD = Pull-down. These pins should be pulled down to ground through a weak pull- down resistor.
(8.2 kΩ to 10 kΩ resistor.)
PD40 = Pull-down to VSS using a 40 resistor.
0.5VDDQ = Set to 50% of the VDDQ voltage supply level.
Ball# Intel® 815G/EG
Signal Name
®
20 Intel
815EG Chipset Platform Design Guide
Introduction
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1.4.2.3 Intel® 82801BA I/O Controller Hub 2 (ICH2)
The Intel® I/O Controller Hub 2 allows the I/O subsystem to access the rest of the system, as
follows:
• Upstream accelerated hub architecture interface for access to the GMCH
• PCI 2.2 interface (6 PCI Request/Grant pairs)
• 2 channel Ultra ATA/100 Bus Master IDE controller
• USB controller (Expanded capabilities for 4 ports)
• I/O APIC
• SMBus controller
• FWH interface
• LPC interface
• AC ’97 Component Specification, Revision 2.2 interface
• Integrated system management controller
• Alert-on-LAN*
• Integrated LAN controller
• Packaging/Power
360 EBGA
1.8 V (± 3% within margins of 1.795 V to 1.9 V) core and 3.3 V standby
1.4.2.4 Firmware Hub (FWH)
The hardware features of the firmware hub include:
• An integrated hardware Random Number Generator (RNG)
• Register-based locking
• Hardware-based locking
• Five General Purpose Interrupts (GPI)
• Packaging/Power
40L TSOP and 32L PLCC
3.3 V core and 3.3 V / 12V for fast programming
1.4.3 Platform Initiatives
1.4.3.1 Universal Motherboard Design
The 815EG chipset platform for use with the universal socket 370 allows systems designers to
build one system that is compatible with the Pentium III processor (CPUID=068xh), Celeron
processor (CPUID=068xh), and future 0.13 micron socket 370 processors. When implemented,
the 815EG chipset universal socket 370 platform can detect which processor is present in the
socket and function accordingly.
®
815EG Chipset Platform Design Guide 21
Intel
Introduction
1.4.3.2 Intel® PC 133
The PC133 initiative provides the memory bandwidth necessary to obtain high performance from
the processor and AGP graphics controller. The platform’s SDRAM interface supports 100 MHz
and 133 MHz operation. The latter delivers 1.066 GB/s of theoretical memory bandwidth
compared with the 800 MB/s theoretical memory bandwidth of 100 MHz SDRAM systems.
1.4.3.3 Accelerated Hub Architecture Interface
As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge becomes significant.
With the addition of AC ’97 and Ultra ATA/100, coupled with the existing USB, I/O requirements
could impact PCI bus performance. The 815EG platform’s accelerated hub architecture ensures
that the I/O subsystem, both PCI and the integrated I/O features (IDE, AC ’97, USB, LAN),
receives adequate bandwidth. By placing the I/O bridge on the accelerated hub architecture
interface instead of PCI, I/O functions integrated into the ICH2 and the PCI peripherals are
ensured the bandwidth necessary for peak performance.
1.4.3.4 Internet Streaming SIMD Extensions
R
The Pentium III processors provide 70 new SIMD (single instruction, multiple data) instructions.
The new extensions are floating-point SIMD extensions. Intel
integer SIMD instructions. The Internet Streaming SIMD extensions complement the MMX
technology SIMD instructions and provide a performance boost to floating-point-intensive 3D
applications.
1.4.3.5 Integrated LAN Controller
The 815EG chipset platform incorporates an ICH2 integrated LAN Controller. Its bus master
capabilities enable the component to process high-level commands and perform multiple
operations; this lowers processor utilization by off-loading communication tasks from the
processor.
The ICH2 functions with several options of LAN connect components to target the desired market
segment. The 82562EH provides a HomePNA 1 Mbit/sec connection. The 82562ET provides a
basic Ethernet 10/100 connection. The 82562EM provides an Ethernet 10/100 connection with the
added flexibility of Alert on LAN. More advanced LAN solutions can be implemented with the
82550 or other PCI based product offerings.
1.4.3.6 Ultra ATA/100 Support
The 815EG chipset platform incorporates an IDE controller with two sets of interface signals
(primary and secondary) that can be independently enabled, tri-stated or driven low. The
component supports Ultra ATA/100, Ultra ATA/66, Ultra ATA/33, and multiword PIO modes for
transfers up to 100 MB/sec.
®
MMX™ technology provides
1.4.3.7 Expanded USB Support
The 815EG chipset platform contains two USB Host Controllers. Each Host Controller includes a
root hub with two separate USB ports each, for a total of 4 USB ports. The addition of a second
USB Host Controller expands the functionality of the platform.
®
22 Intel
815EG Chipset Platform Design Guide
Introduction
R
1.4.3.8 Manageability and Other Enhancements
The 815EG chipset platform integrates several functions designed to manage the system and lower
the total cost of ownership (TCO) of the system. These system management functions are designed
to report errors, diagnose the system, and recover from system lockups, without the aid of an
external microcontroller.
SMBus
The ICH2 integrates an SMBus controller. The SMBus provides an interface for managing
peripherals such as serial presence detection (SPD) and thermal sensors. The slave interface allows
an external microcontroller to access system resources.
Interrupt Controller
The interrupt capabilities of the platform expand support for up to 8 PCI interrupt pins and
PCI 2.2 message-based interrupts. In addition, the ICH2 supports system bus interrupt delivery.
Firmware Hub (FWH)
The platform supports firmware hub BIOS memory sizes up to 8 MB for increased system
flexibility.
1.4.3.9 AC ’97 6-Channel Support
The AC ’97 v2.2 defines a digital interface that can be used to attach an audio codec (AC), a
modem codec (MC), an audio/modem codec (AMC), or both an AC and an MC. The AC ’97 v2.2
defines the interface between the system logic and the audio or modem codec known as the “AClink.”
The 815EG chipset platform’s AC ’97 (with the appropriate codecs) not only replaces ISA audio
and modem functionality, but also improves overall platform integration by incorporating the AClink. Using the platform’s integrated AC-link reduces cost and eases migration from ISA.
By using an audio codec, the AC-link allows for cost-effective, high-quality, integrated audio. In
addition, an AC ’97 soft modem can be implemented with the use of a modem codec. Several
system options exist when implementing AC ’97. The 815EG chipset platform’s integrated digital
link allows several external codecs to be connected to the ICH2. The system designer can provide
audio with an audio codec, a modem with a modem codec, or an integrated audio/modem codec
(Figure 3c). The digital link is expanded to support two audio codecs (Figure 3a) or a combination
of an audio and modem codec (Figure 3b).
®
815EG Chipset Platform Design Guide 23
Intel
Introduction
Modem implementation for different countries must be taken into consideration, as telephone
systems may vary. By implementing a split design, the audio codec can be on board, and the
modem codec can be placed on a riser. is developing an AC-link connector. With a single
integrated codec, or AMC, both audio and modem can be routed to a connector near the rear panel
where the external ports can be located.
The digital link in the ICH2 is AC ’97 v2.2 compliant, supporting two codecs with independent
PCI functions for audio and modem. Microphone input and left and right audio channels are
supported for a high-quality, two-speaker audio solution. Wake-on-ring-from-suspend also is
supported with the appropriate modem codec.
The 815EG chipset platform expands audio capability with support for up to six channels of PCM
audio output (i.e., full AC3 decode). Six-channel audio consists of Front Left, Front Right, Back
Left, Back Right, Center and Woofer, for a complete surround sound effect. ICH2 has expanded
support for two audio codecs on the AC-link.
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®
24 Intel
815EG Chipset Platform Design Guide
Introduction
®
®
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Figure 3. AC ’97 Audio and Modem Connections
a) AC'97 with Audio C odecs ( 4-Channel Secondary)
AC’97
Audio
Codec
ICH2
Intel
360 EBGA
AC-link
AC’97
Audio
Codec
Audio Port
Audio Port
b) AC'97 with Modem and Audio Codecs
Intel® ICH2
360 EBGA
c) AC'97 with Audio/Modem Codec
ICH2
Intel
360 EBGA
AC-link
AC-link
Modem Port
AC’97
Modem
Codec
AC’97
Audio
Codec
Audio Port
Modem Port
AC’97
Audio/
Modem
Codec
Audio Port
®
815EG Chipset Platform Design Guide 25
Intel
Introduction
1.4.3.10 Low-Pin-Count (LPC) Interface
In the 815EG chipset platform, the Super I/O (SIO) component has migrated to the Low-PinCount (LPC) interface. Migration to the LPC interface allows for lower-cost Super I/O designs.
The LPC Super I/O component requires the same feature set as traditional Super I/O components.
It should include a keyboard and mouse controller, floppy disk controller, and serial and parallel
ports. In addition to the Super I/O features, an integrated game port is recommended because the
AC ’97 interface does not provide support for a game port. In systems with ISA audio, the game
port typically existed on the audio card. The fifteen-pin game port connector provides for two
joysticks and a two-wire MPU-401 MIDI interface. Consult your preferred Super I/O vendor for a
comprehensive list of the devices offered and the features supported.
In addition, depending on system requirements, specific system I/O requirements may be
integrated into the LPC Super I/O. For example, a USB hub may be integrated to connect to the
ICH2 USB output and extend it to multiple USB connectors. Other SIO integration targets include
a device bay controller or an ISA-IRQ-to-serial-IRQ converter to support a PCI-to-ISA bridge.
Contact your Super I/O vendor to ensure the availability of desired LPC Super I/O features.
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®
26 Intel
815EG Chipset Platform Design Guide
General Design Considerations
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2 General Design Considerations
This design guide provides motherboard layout and routing guidelines for systems based on the
815EG chipset for use with the universal socket 370. The document does not discuss the functional
aspects of any bus or the layout guidelines for an add-in device.
If the guidelines listed in this document are not followed, it is very important that thorough signal
integrity and timing simulations be completed for each design. Even when the guidelines are
followed, critical signals should be simulated to ensure the proper signal integrity and flight time.
As bus speeds increase, it is imperative that the guidelines documented are followed precisely.
Any deviation from these guidelines should be simulated.
The trace impedance typically noted (i.e., 60 Ω ± 15%) is the “nominal” trace impedance for a
5 mil-wide trace. That is, it is the impedance of the trace when not subjected to the fields created
by changing current in neighboring traces. When calculating flight times, it is important to
consider the minimum and maximum impedance of a trace, based on the switching of neighboring
traces. The use of wider spaces between the traces can minimize this trace-to-trace coupling. In
addition, these wider spaces reduce crosstalk and settling time.
Coupling between two traces is a function of the coupled length, the distance separating the traces,
the signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects
of trace-to-trace coupling, follow the routing guidelines documented in this section.
The routing guidelines in this design guide have been created using a PCB stack-up similar to that
shown in Figure 4. If this stack-up is not used, extremely thorough simulations of every interface
must be completed. Using a thicker dielectric (prepreg) will make routing very difficult or
impossible.
2.1 Nominal Board Stack-Up
The 815EG chipset platform requires a board stack-up yielding a target impedance of 60 Ω ± 15%
with a 5-mil nominal trace width. Figure 4 shows an example stack-up that achieves this. It is a 4layer printed circuit board (PCB) construction using 53%-resin FR4 material.
Figure 4. Board Construction Example for 60 ΩΩΩΩ Nominal Stack-up
Component-side layer 1: ½ oz. Cu
4.5-mil prepreg
Power plane layer 2: 1 oz. Cu
~48-mil core
Ground layer 3: 1 oz. Cu
4.5-mil prepreg
Solder-side layer 4: ½ oz. Cu
Total thickness:
62 mils
board_4.5mil_stackup
®
815EG Chipset Platform Design Guide 27
Intel
General Design Considerations
2.2 Future Designs Require Pull-Ups and Pull-Downs on Any Unused Input and I/O Pins
Any new 815EG platform Universal Socket 370 design should insure no input or I/O pin is left
floating. For example, the TVCLKIN/INT# pin on many current 815 designs is left floating. This
pin should be pulled up to 1.8 V by a weak pull-up resistor (8.2 kΩ to 10 kΩ) on any future
815EG Universal Socket 370 design.
2.3 Support For P-MOS Kicker “ON”: SMAA[9] Is
Strapped High by an Internal 50 kΩΩΩΩ Pull-Up Resistor
The PSB P-MOS Kicker circuit should be enabled on all new, future 82815EG Universal Socket
370 designs. Use of the P-MOS Kicker circuit improves PSB timings by improving AGTL and
AGTL+ signal flight time. The 82815EG SMAA[9] is strapped high through an internal 50 kΩ
pull-up resistor to enable the PSB P-MOS Kicker.
Existing 815 designs which have implemented the pull-down resistor circuit on the SMAA[9]
signal as shown in the 815 Customer Reference Board schematics and populated the resistor site to
over-ride the internal pull-up resistor, may depopulate the site to enable the P-MOS Kicker circuit.
This activity should be based on timing analysis of the specific platform.
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P-MOS Kicker circuit “ON” is the recommended setting for 82815EG Universal Socket 370
designs using future 0.13 micron technology processors.
2.4 Electrostatic Discharge Platform Recommendations
Electrostatic discharge (ESD) into a system can lead to system instability, and possibly cause
functional failures when a system is in use. There are system level design methodologies that when
followed can lead to higher ESD immunity. Electromagnetic fields due to ESD are introduced into
a system through chassis openings such as the I/O back panel and PCI slots. These fields can
introduce noise into signals and cause the system to malfunction. One can reduce the potential for
issues at the I/O area by adding more ground plane on the motherboard around the I/O area. This
can lead to a higher ESD immunity.
Intel recommends that the I/O area on the top and bottom signal layers of a 4-layer motherboard
near the I/O back panel be filled with a ground fill as shown in Figures 1-4. In addition, a ground
fill cutout should be placed on the Vcc layer in the area where the ground fill is done on the top
and bottom layers. Intel recommends filling the I/O area as much as possible without effecting the
signal routing. The board designer should fill the entire I/O area along the board edge.
The spacing from the ground fill to other shapes/traces should be at least 20 mils. It is
recommended that these ground fill areas be connected to two chassis mounting holes (as seen in
Figure 2). This will allow ESD current to travel to the chassis instead of the board. Ground
stitching vias should be placed throughout the entire ground fill if possible. It is important that the
vias are placed along the board edge. Ground stitching vias for the ground fill should be 100-150
mils apart or less.
In conclusion, Intel recommends the following:
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28 Intel
815EG Chipset Platform Design Guide
General Design Considerations
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• 1. Fill the I/O area with the ground fill in all layers including signal layers whenever possible
• 2. Extend the ground fill along the entire back I/O area
• 3. Connect the ground fill to mounting holes
4. Place stitching vias 100-150 mils apart in the entire ground fill
Figure 5. Top Signal Layer before the Ground Fill Near the I/O Layer
Figure 6. Top Signal Layer after the Ground Fill Near the I/O Layer
Ground Fill
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815EG Chipset Platform Design Guide 29
Intel
General Design Considerations
Figure 7. Bottom Signal Layer before the Ground Fill Near the I/O Area
Figure 8. Bottom Signal Layer after the Ground Fill Near the I/O
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Ground Fill
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30 Intel
815EG Chipset Platform Design Guide
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