Intel 82555 User Manual

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82555 10/100 Mbps LAN Physical Layer

Interface

Networking Silicon

Datasheet

Product Features

Optimal integration for lower cost solutions Performance enhancements

Integrated 10/100 Mbps single chip physical layer interface solution

Complete 10/100 Mbps MII compliance with MDI support

Full duplex operation in 10 Mbps and 100 Mbps modes

IEEE 802.3u Auto-Negotiation support for 10BASE-T half and full duplex, 100BASE-TX half and full duplex, and 100BASE-T4 configurations

Parallel detection algorithm for legacy support of non-Auto-Negotiation enabled link partner

Integrated 10BASE-T transceiver with built in transmit and receive filters

Glueless interface to T4-PHY for combination TX/T4 designs with single magnetics

Glueless support for 4 LEDs: activity, link, speed, and duplex

LED function mapping support via MDI

Low external component count

Single 25 MHz clock support for 10 Mbps and 100 Mbps (crystal or oscillator)

Single magnetics for 10 Mbps and 100 Mbps operation

QFP 100-pin package

Flow control support for IEEE 802.3x Auto-Negotiation and Bay Technologies PHY Base* scheme

Adaptive Channel Equalizer for greater functionality over varying cable lengths

High tolerance to extreme noise conditions

Very low emissions

Jabber control circuitry to prevent data loss in 10 Mbps operation

Auto-polarity correction for 10BASE-T

Software compatible with 82557 drivers

Repeater functionality

Repeater mode operation

Support for forced speed of 10 Mbps

and 100 Mbps

Automatic carrier disconnect for IEEE 802.3u compliance

Auto-Negotiation enable/disable capability

Receive port enable function

Support for 32 configurable addresses

Narrow analog side (14 mm) for tight packing in repeater and switch designs

Notice:

Notice:

Document Number: 666252-004

Revision 2.0

March 1998

82555 — Networking Silicon

Low power consumption

Typical total solution power including all resistors and magnetics:

-275 mA 100BASE-TX

-230 mA 10BASE-T

-250 mA Auto-Negotiation

300 mA maximum total solution power in DTE (adapter) mode

Power-down of 10BASE-T/100BASE- TX sections when not in use

Revision History

Added modes for design, testing, and manufacturability

Test Access Port (TAP)

-NAND Tree

-Board Level Functional Test (BIST)

Programmable bypass for 4B/5B encoding/decoding and scrambler/ descrambler

Diagnostic loopback mode

Revision

Revision

Description

Date

 

 

 

 

 

Jan. 1997

1.0

First external release of the preliminary datasheet

 

 

 

Apr. 1997

1.1

First release edition

 

 

 

Mar. 1998

2.0

General editing

 

 

 

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82555 10/100 Mbps LAN Physical Layer Interface may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

P.O. Box 7641

Mt. Prospect IL 60056-7641

or call 1-800-879-4683.

Copyright © Intel Corporation, 1997

*Third-party brands and names are the property of their respective owners.

ii

Datasheet

 

 

 

Networking Silicon — 82555

 

 

 

 

Contents

 

 

 

 

1.0

INTRODUCTION..........................................................................................................................

 

1

 

1.1

Functional Overview ........................................................................................................

1

 

1.2

Compliance to Industry Standards ..................................................................................

1

2.0

ARCHITECTURAL OVERVIEW...................................................................................................

3

 

2.1

100 Mbps Mode...............................................................................................................

3

 

2.2

10 Mbps Mode.................................................................................................................

4

 

2.3

Media Independent Interface (MII) ..................................................................................

5

3.0

PIN DEFINITIONS........................................................................................................................

 

7

 

3.1

Pin Types .......................................................................................................................

 

8

 

3.2

Clock Pins ......................................................................................................................

 

8

 

3.3

Twisted Pair Ethernet (TPE) Pins ...................................................................................

8

 

3.4

Media Independent Interface (MII) Pins .........................................................................

8

 

3.5

Media Access Control/Repeater Interface Control Pins .................................................

9

 

3.6

LED Pins ......................................................................................................................

 

10

 

3.7

External Bias Pins ........................................................................................................

10

 

3.8

Miscellaneous Control Pins ..........................................................................................

11

 

3.9

Power and Ground Pins ...............................................................................................

12

4.0

100BASE-TX ADAPTER MODE OPERATION ..........................................................................

13

 

4.1

100BASE-TX Transmit Clock Generation .....................................................................

13

 

4.2

100BASE-TX Transmit Blocks ......................................................................................

13

 

 

4.2.1

100BASE-TX 4B/5B Encoder ....................................................................

13

 

 

4.2.2

100BASE-TX Scrambler and MLT-3 Encoder ...........................................

14

 

 

4.2.3

100BASE-TX Transmit Framing ................................................................

15

 

 

4.2.4

Transmit Driver ..........................................................................................

16

 

4.3

100BASE-TX Receive Blocks .......................................................................................

16

 

 

4.3.1

Adaptive Equalizer .....................................................................................

17

 

 

4.3.2

Receive Clock and Data Recovery ............................................................

17

 

 

4.3.3

MLT-3 Decoder, Descrambler, and Receive Digital Section......................

17

 

 

4.3.4

100BASE-TX Receive Framing .................................................................

17

 

 

4.3.5

100BASE-TX Receive Error Detection and Reporting ...............................

17

 

4.4

100BASE-TX Collision Detection ..................................................................................

17

 

4.5

100BASE-TX Link Integrity and Auto-Negotiation Solution ...........................................

18

 

 

4.5.1

Link Integrity...............................................................................................

18

 

 

4.5.2

Auto-Negotiation ........................................................................................

18

 

 

4.5.3

Combination Tx/T4 Auto-Negotiation Solution...........................................

18

 

4.6

Auto 10/100 Mbps Speed Selection ..............................................................................

19

 

4.7

Adapter Mode Addresses..............................................................................................

19

5.0

10BASE-T FUNCTIONALITY IN ADAPTER MODE ..................................................................

21

 

5.1

10BASE-T Transmit Clock Generation..........................................................................

21

 

5.2

10BASE-T Transmit Blocks...........................................................................................

21

 

 

5.2.1

10BASE-T Manchester Encoder................................................................

21

 

 

5.2.2

10BASE-T Driver and Filter .......................................................................

21

 

5.3

10BASE-T Receive Blocks............................................................................................

21

 

 

5.3.1

10BASE-T Manchester Decoder................................................................

21

 

 

5.3.2

10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter............

21

Datasheet

iii

82555 — Networking Silicon

Contents

 

 

5.3.3

10BASE - T Error Detection and Reporting .................................................

22

 

5.4

10BASE-T Collision Detection.......................................................................................

22

 

5.5

10BASE-T Link Integrity ................................................................................................

22

 

5.6

10BASE-T Jabber Control Function ..............................................................................

22

 

5.7

10BASE-T Full Duplex ..................................................................................................

23

6.0

REPEATER MODE

....................................................................................................................

25

 

6.1

Special Repeater Features............................................................................................

25

 

6.2

Connectivity...................................................................................................................

25

7.0

MANAGEMENT DATA ..........................................................................................INTERFACE

27

 

7.1

MDI Frame .....................................................................................................Structure

27

 

7.2

MDI Registers................................................................................................................

28

 

 

7.2.1 ....................................................................................

MDI Registers 0 - 7

28

 

 

7.2.2 ..................................................................................

MDI Registers 8 - 15

31

 

 

7.2.3 ................................................................................

MDI Registers 16 - 31

31

8.0

AUTO-NEGOTIATION ..................................................................................FUNCTIONALITY

35

 

8.1

Description ....................................................................................................................

 

35

 

8.2

Parallel Detect ............................................................................and Auto-Negotiation

36

9.0

LED DESCRIPTIONS ................................................................................................................

39

10.0

RESET AND MISCELLANEOUS .......................................................................TEST MODES

41

 

10.1

Reset.............................................................................................................................

 

41

 

10.2

Loopback.......................................................................................................................

 

41

 

10.3

Scrambler Bypass .........................................................................................................

41

 

10.4

Test Port........................................................................................................................

 

41

11.0

ELECTRICAL SPECIFICATIONS ..............................................AND TIMING PARAMETERS

43

 

11.1

Absolute Maximum ..........................................................................................Ratings

43

 

11.2

General Operating ......................................................................................Conditions

43

 

11.3

DC Characteristics ........................................................................................................

43

 

 

11.3.1 ..............................................................................

MII DC Characteristics

43

 

 

11.3.2 ........................................

10BASE - T Voltage/Current DC Characteristics

43

 

 

11.3.3 ...................................

100BASE - TX Voltage/Current DC Characteristics

44

 

11.4

AC Characteristics.........................................................................................................

45

 

 

11.4.1 .............................................................................

MII Clock Specifications

45

 

 

11.4.2 ..............................................................................

MII Timing Parameters

46

 

 

11.4.3 ..........................................................

Repeater Mode Timing Parameters

47

 

 

11.4.4 .........................................................

Transmit Packet Timing Parameters

48

 

 

11.4.5 ..............................................................

Squelch Test Timing Parameters

48

 

 

11.4.6 ........................................................................

Jabber Timing Parameters

49

 

 

11.4.7 ..........................................................

Receive Packet Timing Parameters

49

 

 

11.4.8 .........................

10BASE - T Normal Link Pulse (NLP) Timing Parameters

50

 

 

11.4.9 ....................

Auto - Negotiation Fast Link Pulse (FLP) Timing Parameters

50

 

 

11.4.10 .........................................................................

Reset Timing Parameters

51

 

 

11.4.11 ............................................................................

X1 Clock Specifications

51

 

 

11.4.12 ..............................................

100BASE - TX Transmitter AC Specification

52

12.0

82555 PACKAGE INFORMATION.............................................................................................

53

iv

Datasheet

Networking Silicon — 82555

1.0Introduction

The 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 Mbps Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX specifications. 100BASE-TX is an IEEE 802.3 physical layer specification for use over two pairs of Category 5 unshielded twisted pair or Type 1 shielded twisted pair cable. 100BASE-TX defines a signaling scheme not only for 100 Mbps, but also provides CSMA/CD compatibility with the 10 Mbps IEEE 802.3 10BASE-T signaling standard.

1.1Functional Overview

The 82555 is designed to work in two modes: Data Terminal Equipment (DTE) for adapters and repeater for hubs and switches. When configured to DTE (adapter) mode, the 82555 incorporates all active circuitry required to interface 10/100 Mbps Ethernet controllers and CSMA/CD MAC components to 10 Mbps and 100 Mbps networks. In this and other documents the 82555 may be referred to as the DTE, Physical Medium Device (PMD), or Physical Layer Medium (PLM). It supports a direct glueless interface to Intel components such as the 82557 Fast Ethernet controller. The 82555 also supports the Media Independent Interface (MII) signals as specified in the IEEE 802.3u standard. The figure below shows how the 82555 fits into a 10/100 Mbps Ethernet adapter design.

Pair 1

Intel 82555

Controller/MAC

Pair 2

Magnetics

System Bus Interface

Figure 1. 82555 10/100 Mbps Ethernet Solution

When configured to repeater mode, the 82555 incorporates several features that allow it to function as a Class I or MII level repeater. Section 6.0, “Repeater Mode” on page 25 describes the 82555 in a repeater type of application.

1.2Compliance to Industry Standards

When operating in 100 Mbps mode, the 82555 complies with IEEE 802.3u 100BASE-TX specification. The PMD section with the related changes established in 802.3u 100BASE-TX complies with ANSI X3.263:1995 TP-PMD, Revision 2.2.

When operating in the 10 Mbps mode, the 82555 complies with the IEEE 802.3 10BASE-T specification.

Datasheet

1

82555 — Networking Silicon

The 82555 also complies with the IEEE 802.3u Auto-Negotiation and the IEEE 802.3x Full Duplex Flow Control sections. The MAC interface on the 82555 is a superset of the IEEE 802.3u Media Independent Interface (MII) standard.

2

Datasheet

Networking Silicon — 82555

2.0Architectural Overview

The 82555 is an advanced combination of both digital and analog logic which combine to provide a functional stack between the Media Independent Interface (MII) and the wire through the magnetics. Figure 2 shows a general block diagram of the 82555 component.

Figure 2. 82555 Simplified Block Diagram

2.1100 Mbps Mode

In 100BASE-TX mode the 82555 digital subsection performs all signal processing of digital data obtained from the analog reception and the data to be driven into the analog transmit subsection. This includes 4B/5B encoding/decoding, scrambling/descrambling, carrier sense, collision detection, link detection, Auto-Negotiation, data validation, and providing MII to the Media Access Controller (MAC). The 82555 supports the IEEE defined MII as its MAC interface and expects the controller to drive the Management Data Input/Output and Management Data Clock signals to perform the management functions.

In 100BASE-TX mode, the analog subsection of the 82555 performs two functions:

Transmit: The 82555 converts a digital 125 Mbps stream into MLT-3 format and drives it through the transmit differential pair onto the physical medium.

Datasheet

3

82555 — Networking Silicon

Receive: The 82555 takes receive analog MLT-3 data from the receive differential pair and converts it into a digital 125 Mbps stream, recovering both clock and data signals.

MII TX Interface

 

 

 

 

MII RX Interface

4b/5b

 

 

 

 

 

 

4b/5b

Encoding

 

 

 

 

 

 

 

 

 

 

 

 

Decoding

 

 

 

 

 

 

 

Scrambler

 

 

 

 

 

 

De-scrambler

 

 

 

 

 

 

 

Serialization

 

 

 

 

 

 

Serial to 5B

 

 

 

 

 

 

 

NRZ to NRZI

 

 

 

 

 

 

NRZI to NRZ

 

 

 

 

 

 

 

NRZI to MLT3

 

 

 

 

 

MLT3 to NRZI

 

 

 

 

 

 

 

 

Magnetics Module

1

2

3

4

5

6

7

8

 

 

RJ-45 Connector

 

Figure 3. 82555 Analog Logic

2.210 Mbps Mode

The 82555 operation in 10BASE-T mode is similar to the 82555 operation in 100BASE-TX mode. Manchester encoding and decoding is used instead of 4B/5B encoding/decoding and scrambling/ descrambling. In addition, the Transmit Clock and Receive Clock (MII clock signals) provide 2.5 MHz instead of 25 MHz.

4

Datasheet

Networking Silicon — 82555

The 82555 provides a glueless interface to Intel components such as the 82557 Fast Ethernet Controller, as well as any MII compatible device. Figure 4 shows a schematic-level diagram of the 82557 Fast Ethernet controller implementation connected to the 82555 using the MII interface.

Flash

EEPR O M

 

(optional)

(optional)

 

 

RXD[3:0]

 

 

RXC

 

 

RXERR

 

 

RXDV

 

 

CRS

 

 

COL

 

82557

TXD[3:0]

82555

TXC

 

 

 

TXEN

 

 

MDC

 

 

MDIO

 

 

RESET

 

PCI Bus Signals

 

Figure 4. Intel 82557/82555 Solution

2.3Media Independent Interface (MII)

The 82555 supports the Media Independent Interface (MII) as its primary interface to the MAC. The MII Interface is summarized in Table 1.

Table 1. 82555 MII

Signal

Description

Direction

Clock

MII Signal Supported

Name

Reference

by the 82555?

 

 

 

 

 

 

 

TXC

Transmit Clock

From 82555

--

Yes

(adapter mode only)

 

 

 

 

 

 

 

 

 

TXD[3:0]

Transmit Data

From MAC

TXC

Yes

 

 

 

 

 

TXEN

Transmit Enable

From MAC

TXC

Yes

 

 

 

 

 

COL

Collision Detect

From 82555

Asynchronous

Yes

 

 

 

 

 

CRS

Carrier Sense

From 82555

Asynchronous

Yes

 

 

 

 

 

RXC

Receive Clock

From 82555

--

Yes

 

 

 

 

 

RXD[3:0]

Receive Data

From 82555

RXC

Yes

 

 

 

 

 

RXDV

Receive Data Valid

From 82555

RXC

Yes

 

 

 

 

 

RXERR

Receive Error

From 82555

RXC

Yes

 

 

 

 

 

MDC

Management Data

From manager

--

Yes

Clock

 

 

 

 

 

 

 

 

 

MDIO

Management Data

From manager

MDC

Yes

Input/Output

 

 

 

 

 

 

 

 

 

Datasheet

5

82555 — Networking Silicon

Table 1. 82555 MII

Signal

Description

Direction

Clock

MII Signal Supported

Name

Reference

by the 82555?

 

 

 

 

 

 

 

TXERR

Transmit Error

From RIC

TXC

Yes

(repeater mode only)

 

 

 

 

 

 

 

 

 

6

Datasheet

Networking Silicon — 82555

3.0Pin Definitions

All active digital pins are defined to have transistor-to-transistor logic voltage levels except the X1 and X2 crystal signals. The transmit differential and receive differential pins are specified as analog outputs and inputs, respectively.

The figure below show the pin locations on the 82555 component. The following subsections describe the pin functions.

Figure 5. 82555 Pin Numbers and Labels

Datasheet

7

82555 — Networking Silicon

Pin allocation is based on a 100-lead quad flat package. All pin locations are based on printed circuit board layout and other design constraints.

3.1Pin Types

Pin Type

Description

 

 

 

 

I

This type of pin is an input pin to the 82555.

 

 

O

This type of pin is an output pin from the 82555.

 

 

I/O

This type of pin is both an input and output pin for the 82555.

 

 

B

This pin is used as a bias pin. The bias pin is either pulled up or down with a resistor. The bias pin

 

may also be used as an external voltage reference.

 

 

3.2Clock Pins

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

X1

56

I

Crystal Input One. X1 and X2 can be driven by an external 25 MHz crystal.

 

 

 

Otherwise, X1 may be driven by an external MOS level 25 MHz oscillator

 

 

 

when X2 is left floating. (The crystal should have a tolerance of 50 PPM or

 

 

 

better.)

 

 

 

 

X2

55

O

Crystal Output Two. X1 and X2 can be driven by an external 25 MHz

 

 

 

crystal. Otherwise, X1 may be driven by an external MOS level 25 MHz

 

 

 

oscillator when this pin is left floating.

 

 

 

 

3.3Twisted Pair Ethernet (TPE) Pins

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

TDP

47

O

Transmit Differential Pair. These pins send the serial bitstream for

TDN

48

 

transmission on an unshielded twisted pair (UTP) cable. The current-driven

 

differential driver can be two-level (10BASE-T or Manchester) or three-level

 

 

 

 

 

 

(100BASE-TX or MLT-3) signals depending on the operating mode. These

 

 

 

signals interface directly with an isolation transformer.

 

 

 

 

RDP

33

I

Receive Differential Pair. These pins receive the serial bitstream from the

RDN

34

 

isolation transformer. The bitstream can be two-level (10BASE-T or

 

manchester) or three-level (100BASE-TX or MLT-3) signals depending on the

 

 

 

 

 

 

operating mode.

 

 

 

 

3.4Media Independent Interface (MII) Pins

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

RXD3

97

O

Receive Data. In 100 Mbps and 10 Mbps mode, data is transferred across

RXD2

96

 

these four lines one nibble at a time.

 

 

RXD1

95

 

 

RXD0

92

 

 

 

 

 

 

8

Datasheet

 

 

 

Networking Silicon — 82555

 

 

 

 

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

RXC

90

O

Receive Clock. The Receive Clock may be either 25 MHz or 2.5 MHz

 

 

 

depending on the 82555’s operating speed (25 MHz for 100 Mbps and 2.5

 

 

 

MHz for 10 Mbps). The Receive Clock is recovered directly from incoming

 

 

 

data and is continuous into the Media Access Controller (MAC). Thus, it must

 

 

 

be resynchronized in 10 Mbps mode at the start of each incoming packet.

 

 

 

 

RXDV

86

O

Receive Data Valid. This signal indicates that the incoming data on the

 

 

 

RSC[3:0] pins are valid.

 

 

 

 

RXERR

87

O

Receive Error. The RXERR signal indicates to the 82555 that an error has

 

 

 

occurred during frame reception.

 

 

 

 

TXD3

71

I

Transmit Data. In 100 Mbps and 10 Mbps mode, data is transferred across

TXD2

70

 

these four lines one nibble at a time.

 

 

TXD1

69

 

 

TXD0

68

 

 

 

 

 

 

TXC

60

I/O

Transmit Clock. The Transmit Clock may be either 25 MHz or 2.5 MHz

 

 

 

depending on the 82555’s operating speed (25 MHz for 100 Mbps and 2.5

 

 

 

MHz for 10 Mbps). The Transmit Clock outputs a continuous clock into the

 

 

 

MAC that is generated directly from the external clock source in DTE

 

 

 

(adapter) mode. In repeater mode, the TXC is an input signal operating at

 

 

 

either 25 MHz or 2.5 MHz depending on the operating speed, which is

 

 

 

typically clocked by a receiver interface device.

 

 

 

 

TXEN

79

I

Transmit Enable. The Transmit Enable signal indicates to the 82555 that

 

 

 

valid data is present on the TXD[3:0] pins.

 

 

 

 

TXERR

59

I

Transmit Error. The TXERR signal indicates to the 82555 that an error has

 

 

 

occurred during transmissions of a frame.

 

 

 

 

CRS

82

O

Carrier Sense. The Carrier Sense signal indicates to the 82555 that traffic is

 

 

 

present on the link. CRS is an asynchronous output signal.

 

 

 

 

COL

85

O

Collision Detect. The Collision Detect signal operates in half duplex mode

 

 

 

and indicates to the 82555 that a collision has occurred on the link. COL is an

 

 

 

asynchronous output signal to the controller.

 

 

 

 

MDIO

80

I/O

Management Data Input/Output. The MDIO signal is a bidirectional data pin

 

 

 

for the Management Data Interface (MDI).

 

 

 

 

MDC

81

II

Management Data Clock. The MDC signal functions as a clock reference for

 

 

 

the MDIO signal. MDC should operate at a maximum frequency of 2.5 MHz

 

 

 

 

3.5Media Access Control/Repeater Interface Control Pins

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

RXCONG

77

I

Receive Congestion. If the following conditions exist, the RXCONG is an

 

 

 

active high and indicates an overrun on the controller receive side:

 

 

 

• Full duplex PHY Base (Bay Technologies) flow control DTE (adapter)

 

 

 

mode

 

 

 

• Full duplex signal (FDX_N) is high

 

 

 

• Full duplex technology is active through Auto-Negotiation

 

 

 

 

PORTEN

76

I

Port Enable. In repeater mode when the PORTEN signal is low, the following

 

 

 

signals will be tri-stated: RXD[3:0], RXC, RXDV, and RXERR.

 

 

 

 

Datasheet

9

82555 — Networking Silicon

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

TXRDY

4

O

This pin is multiplexed and can be used for one of the following:

(TOUT)

 

 

Transmit Ready. If full duplex and PHY Base (Bay Technologies) flow control

 

 

 

modes are enabled, the TXRDY signal enables transmission while it is

 

 

 

asserted.

 

 

 

TOUT. When the Test Enable signal is activated, this signal functions as the

 

 

 

Test Output port.

 

 

 

 

FDX_N

5

I/O

Full Duplex. In DTE (adapter) mode, this active low output signal reports the

 

 

 

result of the duplex configuration to the MAC. This pin can also operate as

 

 

 

the LED driver and will be an active low for all technologies.

 

 

 

In repeater mode, this signal is used for Auto-Negotiation advertisement to

 

 

 

the 82555’s link partner and activates the PHY Base (Bay Technologies) flow

 

 

 

control if 100BASE-TX full duplex is the highest common technology between

 

 

 

the 82555 and its link partner.

 

 

 

 

3.6LED Pins

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

ACTLED

12

O

Activity LED. This signal indicates either transmit or receive activity. When

 

 

 

activity is present, the ACTLED is on. When no activity is present, the

 

 

 

ACTLED is off.

 

 

 

 

LILED

11

O

Link Integrity LED. This signal indicates the link integrity. If a valid link is

 

 

 

present in either 10 Mbps or 100 Mbps, the LILED is on; and if an invalid link

 

 

 

is preset, LILED is off.

 

 

 

For a combination design board, the LILED should be connected to the TX

 

 

 

technology LED.

 

 

 

 

SPEED-

13

O

Speed LED

LED

 

 

This signal is used to indicate the speed of operation. For 100 Mbps, the

 

 

 

 

 

 

SPEEDLED will be on; and for 10 Mbps, the SPEEDLED will be off.

 

 

 

 

3.7External Bias Pins

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

RBIAS100

44

B

Bias Reference Resistor 100. A 634 Ω resistor should be connected from

 

 

 

this pin to ground.

 

 

 

 

RBIAS10

43

B

Bias Reference Resistor 10. A 768 Ω resistor should be connected from

 

 

 

this pin to ground.

 

 

 

 

PD1

42

I

Pull Down One. A 10 KΩ resistor should be connected from this pin to

 

 

 

ground.

 

 

 

 

PD2

100

I

Pull Down One. A 1 KΩ resistor should be connected from this pin to

 

 

 

ground.

 

 

 

 

Note: The resistor values described for the external bias pins are only recommended values and may require to be fine tuned for various designs.

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Datasheet

Networking Silicon — 82555

3.8Miscellaneous Control Pins

Symbol

Pin

Type

Name and Function

 

 

 

 

 

 

 

 

RESET

1

I

Reset. The Reset signal is active high and resets the 82555. A reset pulse

 

 

 

width of at least 1 μs should be used.

 

 

 

 

FRC100

51

I

This pin is multiplexed and can be used for one of the following:

(MACTYP)

 

 

Force 100/10 Mbps. In repeater mode, this pin configures the repeater to

 

 

 

either 100 Mbps (active high) or to 10 Mbps (active low).

 

 

 

MAC Type. In DTE (adapter) full duplex mode, if this input signal is high, the

 

 

 

82555 drives 82557 mode. If this input signal is low, the 82555 drives a

 

 

 

generic MII MAC mode.

 

 

 

 

PHYA4

22

I

This pin is multiplexed and can be used for one of the following:

(TIN)

 

 

PHY Address 4. In repeater mode, this signal represents the fifth bit for

 

 

 

address port configuration.

 

 

 

TIN. If the Test Enable signal is active, this signal is used as the Test Input

 

 

 

data.

 

 

 

 

PHYA3

52

I/O

This pin is multiplexed and can be used for one of the following:

(SLVTRI)

 

 

PHY Address 3. In repeater mode, this signal represents the fourth bit for

 

 

 

address port configuration.

 

 

 

Slave Tri-state. In DTE (adapter) mode, this output operates in conjunction

 

 

 

with the T4 Advanced signal. When both are active, the slave PHY is inactive

 

 

 

and tri-states all its outputs.

 

 

 

 

PHYA2

6

I

This pin is multiplexed and can be used for one of the following:

(LISTAT)

 

 

PHY Address 2. In repeater mode, this signal represents the third bit for

 

 

 

address port configuration.

 

 

 

Link Status. In DTE (adapter) mode, if T4 Advance is active, the LISTAT_N

 

 

 

signal is active low and the slave PHY link is valid.

 

 

 

 

PHYA1

25

I

This pin is multiplexed and can be used for one of the following:

(TEXEC)

 

 

PHY Address 1. In repeater mode, this signal represents the second bit for

 

 

 

address port configuration.

 

 

 

Test Execute. If Test Enable is asserted, this signal acts as the test

 

 

 

execution command indicating that the pin 22 is being used as the Test Input

 

 

 

pin.

 

 

 

 

PHYA0

24

I

This pin is multiplexed and can be used for one of the following:

(TCK)

 

 

PHY Address 0. In repeater mode, this signal represents the first bit for

 

 

 

address port configuration.

 

 

 

Test Clock. If Test Enable is asserted, this signal acts as the Test Clock

 

 

 

signal.

 

 

 

 

ANDIS

54

I

This pin is multiplexed and can be used for one of the following:

(T4ADV)

 

 

Auto-Negotiation Disable. In repeater mode, the Auto-Negotiation operates

 

 

 

for management reasons. If this input signal is high, the Auto-Negotiation

 

 

 

operation will be disabled.

 

 

 

T4ADV. In DTE (adapter) mode, this pin enables the combo mode. This

 

 

 

allows the LISTAT and SLVTRI pins to be used as interface to the slave PHY.

 

 

 

 

SCRMBY

23

I

Scrambler/Descrambler Bypass. If SCRMBY is high, the scrambler/

 

 

 

descrambler of TP-PMD will be bypassed.

 

 

 

 

LPBK

2

I

Loopback. When the LPBK signal is high, the 82555 will perform a

 

 

 

diagnostic loopback function.

 

 

 

 

RPT

50

I

Repeater. When the RPT signal is high, the 82555 functions in repeater

 

 

 

mode. When this signal is low, the 82555 runs in DTE (adapter) mode.

 

 

 

 

TESTEN

21

I

Test. If the TESTEN signal is high, the 82555 enables the test ports.

 

 

 

 

Datasheet

11

82555 — Networking Silicon

3.9Power and Ground Pins

Symbol

Pin

 

Type

Name and Function

 

 

 

 

 

 

 

 

 

 

VCC

7, 9, 15, 17, 19, 27, 29, 31, 36, 38, 40, 45, 58, 62,

I

 

Power: +5 V ± 5%

 

64, 66, 73, 75, 83, 88, 93, 98

 

 

 

 

 

 

 

 

VSS

3, 8, 10, 14, 16, 18, 20, 26, 28, 30, 32, 35, 37, 39,

I

 

Ground: 0 V

 

41, 46, 49, 53, 57, 61, 63, 65, 67, 72, 74, 78, 84, 89,

 

 

 

 

91, 94, 99

 

 

 

 

 

 

 

 

12

Datasheet

Networking Silicon — 82555

4.0100BASE-TX Adapter Mode Operation

4.1100BASE-TX Transmit Clock Generation

A 25 MHz crystal or a 25 MHz oscillator is used to drive the 82555’s X1 and X2 pins. The 82555 derives its internal transmit digital clocks from this crystal or oscillator input. The Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be ± 0.0005% (50 PPM).

4.2100BASE-TX Transmit Blocks

The transmit subsection of the 82555 accepts nibble-wide data on the TXD[3:0] lines when TXEN is asserted (high). The transmit subsection passes data unconditionally to the 4B/5B encoder as long as TXEN is active.

The 4B/5B encoder accepts nibble-wide data (4 bits) from the MAC and compiles it into 5-bit-wide parallel symbols. These symbols are scrambled and serialized into a 125 Mbps bit stream, converted by the analog transmit driver into a MLT-3 waveform format, and transmitted onto the Unshielded Twisted Pair (UTP) or Shielded Twisted Pair (STP) wire.

4.2.1100BASE-TX 4B/5B Encoder

The 4B/5B encoder complies with the IEEE 802.3u 100BASE-TX standard. Four bits are encoded according to the transmit 4B/5B lookup table. The lookup table matches a 5-bit code to each 4-bit code.

The table below illustrates the 4B/5B encoding scheme associated with the given symbol.

Table 2. 4B/5B Encoder

Symbol

5B Symbol Code

4B Nibble Code

 

 

 

 

 

 

0

11110

0000

 

 

 

1

01001

0001

 

 

 

2

10100

0010

 

 

 

3

10101

0011

 

 

 

4

01010

0100

 

 

 

5

01011

0101

 

 

 

6

01110

0110

 

 

 

7

01111

0111

 

 

 

8

10010

1000

 

 

 

9

10011

1001

 

 

 

A

10110

1010

 

 

 

B

10111

1011

 

 

 

C

11010

1100

 

 

 

D

11011

1101

 

 

 

Datasheet

13

82555 — Networking Silicon

Table 2. 4B/5B Encoder

Symbol

5B Symbol Code

4B Nibble Code

 

 

 

E

11100

1110

 

 

 

F

11101

1111

 

 

 

I

11111

Inter Packet Idle Symbol

(No 4B)

 

 

 

 

 

J

11000

1st Start of Packet Symbol

0101

 

 

 

 

 

K

10001

2nd Start of Packet Symbol

0101

 

 

 

 

 

T

01101

1st End of Packet Symbol

 

 

 

R

00111

2nd End of Packet Symbol

and Flow Control

 

 

 

 

 

V

00000

INVALID

 

 

 

V

00001

INVALID

 

 

 

V

00010

INVALID

 

 

 

V

00011

INVALID

 

 

 

H

00100

INVALID

 

 

 

V

00101

INVALID

 

 

 

V

00110

INVALID

 

 

 

V

01000

INVALID

 

 

 

V

01100

INVALID

 

 

 

V

10000

Flow Control S

 

 

 

V

11001

INVALID

 

 

 

4.2.2100BASE-TX Scrambler and MLT-3 Encoder

Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The 82555 implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation. The cipher equation used is:

X[n] = X[n-11] + X[n-9] (mod 2)

The MLT-3 encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to NRZI coding, but three levels are output instead of two. There are three output levels: positive, negative and zero. When an NRZ “0” arrives at the input of the encoder, the last output level is

14

Datasheet

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