Intel 815E Schematic
A
B
C
D
E
Intel® Pentium® III and FC-PGA Celeron™ Processor/815E Chipset
Universal Socket 370 Platform
4 4
Customer Reference Board Schematics
Revision 1.05 - Fab C
PAGETITLE
1COVER SHEET
BLOCK DIAGRAM
PGA370 PART 1 & 2
AGTL TERMINATION
CLOCK GENERATO R
GMCH PART 1 & 2
DIMM 1 & 2
3 3
DIMM 3
AGP
ICH PART 1 & 2
PCI 1 & 2
PCI 3
VIDEO BUS & CONNECTOR
FWH & UDMA100 IDE 1 - 2
USB 0-3
AC97 CODEC
AUDIO I/O
LPC I/O CONTROLLER & FDCL
WOR, WOL & 2S1P
2 2
KB, MS, GAME & IR
FRONT PANEL & CNR
ATX POWER & H/W MONITOR
VREGS: VDDQ, VCC1_8, AND VTT
VREGS: VCCVID, V1_8SB
VREGS: DUALS, 3.3SB, 2.5, VCMOS
SYSTEM CONFIG U R AT IO N
PU/PDR & UNUSED GATES
DECOUPLING CAPACITORS
INTERNAL DEBUG HEADERS
THERMTRIP
2
3,4
5
6
7,8
9
10
11
12,13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or
otherwise , t o any in t ellectu al property rights is granted by this document. Except as provided in Intel's Terms and Conditions
of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating
to sale and/or use of Intel products including liability or warranties relating to fitn e ss fo r a p a rtic u la r p u rp o s e , m e rchantability,
or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical,
life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined."
Intel reserves these for future definition and shall have no responsibility whatsoev e r fo r c o n flic ts o r incompatibilities arising
from future changes to them.
The Intel® 815E chipset may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on r equest.
Contact your l ocal Int el sales office o r your distribut or to obt ain the l atest specifications and before placing your product
order.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2 C b u s /p ro to c o l and was
developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Ph ilips
Electronics N.V. and North American Philips Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Copies of documents which have an ordering number and are referenced in this document, or other Intel lite r a t u re, may be
obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel®, Pentium®, Pentiu m ® III, Ce le ro n ™, a re trademarks or registered trademarks of Intel Corporation or its subsidiar ies in
the United States and other countries.
*Other brands and names may be claimed as the property of others.
Copyright© 2001, Intel Corporation
**PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE
1 1
A
B
C
Document:
Page Name:
Last Revised:
D
Intel(R) 815E Chipset Universal Socket 370 CRB
Title Page
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
E
Revision:
1.05
Page No:
133
of
A
B
C
D
E
BLOCK DIAGRAM
4 4
VRM
370-PIN SOCKET PROCESSOR
ADDR
CTRL
DATA
CLOCK
GTL BUS
ADDR
AGP
Connector
3 3
Digital Video
Out Connector
IDE Primary
UDMA/100
IDE Secondary
USB PORT 1-4
2 2
FirmWare Hub
USB
CTRL
GMCH
ICH2
DATA
PCI ADDR/DATA
AC’97 LINK
3 DIMM
Modules
PCI CNTRL
CNR
Connector
PCI CONN 1
PCI CONN 2
Note: PCI3
Connector is
not populated
on the board
PCI CONN3
SIO
Audio
Codec
1 1
Floppy
Game Port Serial 1
Keyboard
ParallelSerial 2
Document:
Page Name:
Last Revised:
Mouse
A
B
C
D
Intel(R) 815E Chipset Universal Socket 370 CRB
Block Diagram
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
E
Revision:
1.05
Page No:
233
of
5
D D
C C
B B
RS#07
RS#17
RS#27
A A
5
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
U3A
W1
T4
N1
M6
U1
S3
T6
J1
S1
P6
Q3
M4
Q1
L1
N3
U3
H4
R4
P4
H6
L3
G1
F8
G3
K6
E3
E1
F12
A5
A3
J3
C5
F6
C1
C7
B2
C9
A9
D8
D10
C15
D14
D12
A7
A11
C11
A21
A15
A17
C13
C25
A13
D16
A23
C21
C19
C27
A19
C23
C17
A25
A27
E25
F16
AH26
AH22
AK28
Socket 370_9
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
RS#0
RS#1
RS#2
B26C3AK2
VCCVID
VCCVID
GND
GND
GND
GND
AM34
AH2
AD2Z2V2M2D18H2D2
AF2
AB2T2P2K2F4E5AM4
VCCVID
VCCVID
VCCVID
VCCVID
GND
GND
GND
GND
VCCVID
VCCVID
GND
GND
AL3
AE5
AA5W5S5N5J5F2D6B6AM8
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
GND
GND
GND
GND
GND
AG5
AC5Y5U5Q5L5G5D4B4AM6
4
AJ9E9B10
AM12
AJ13
E13
B14
AM16
AJ5
AJ17
E17
B18
AM20
AJ21
D20
F22
AM24
AJ25
D24
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
370 - Pin Socket Part 1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AJ7E7B8
AM10
AJ11
E11
B12
AM14
AJ15
E15
B16
AM18
AJ19
E19
F20
B20
AM22
AJ23
D22
F24
B24
4
F26
AM28
VCCVID
VCCVID
GND
GND
AM26
AJ27
AJ29
D28
VCCVID
VCCVID
GND
GND
D26
F28
3
AK34
F30
VCCVID
VCCVID
GND
GND
B28
AM30
3
B30
AM32
VCCVID
VCCVID
GND
GND
D30
AF32
AH32
Z32
VCCVID
VCCVID
GND
GND
AB32
X32
V32
R32
VCCVID
VCCVID
GND
GND
T32
P32
M32
H32
VCCVID
VCCVID
GND
GND
F32
B32
VTT
AF34
AB34
VCCVID
VCCVID
GND
GND
AH34
AD34
X34
T34
VCCVID
VCCVID
GND
GND
Z34
V34
P34
K34
VCCVID
VCCVID
GND
GND
R34
M34
F34
B34
VCCVID
VCCVID
GND
GND
H34
D34
AH36
B22
VCCVID
VCCVID
GND
V36
R36
VCCVID
VCCVID
GND
X36
T36
H36
D36
VCCVID
VCCVID
GND
GND
P36
K36
D32
AD32
VCCVID
VCCVID
GND
GND
F36
A37
AH24
F14
VCCVID
VCCVID
GND
GND
AC33
Y37
VCCVID
K32
AA37
VCCVID
VCCVID
GND
2
Y35
VCCVID
VCCVID
2
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35
VID0
VID1
VID2
VID3
GND/VID4
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
Document:
Page Name:
Last Revised:
AK8
AH12
AH8
AN9
AL15
AH10
AL9
AH6
AK10
AN5
AL7
AK14
AL5
AN7
AE1
Z6
AG3
AC3
AJ1
AE3
AB6
AB4
AF6
Y3
AA1
AK6
Z4
AA3
AD4
X6
AC1
W3
AF4
AL35
AM36
AL37
AJ37
AK36
AK18
AH16
AH18
AL19
AL17
C33
C31
A33
A31
E31
C29
E29
A29
AH20
AK16
AL21
AN11
AN15
G35
AL13
U37
U35
S37
S33
E23
AN21
AA35
AA33
HA#[3..31]
HD#[0..63]
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
VTT
HA#[3..31] 7
HD#[0..63] 7
VCC3_3
R371
10K
135
HREQ#0 7
HREQ#1 7
HREQ#2 7
HREQ#3 7
HREQ#4 7
642
RP3
7 8
10K/8P4R
R372 1k
RP4
1
3
5
7 8
Intel(R) 815E Chipset Universal Socket 370 CRB
370-pin Socket Part 1
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
1
1
1K/8P4R
JPR_VID0 29,32
2
JPR_VID1 29,32
4
JPR_VID2 29,32
6
JPR_VID3 29,32
JPR_VID4 29,32
Revision:
1.05
Page No:
333
of
5
a
No-stuff R199 - see p.33.
VTT VCC2_5
D D
DBRESET#25
C C
N639540333
B B
Stuff resistor
only on non-UMB
platforms.
A A
R315 0
ITPCLK6
ITPRDY#5
1k
Rds_on approx. 100
mOhm @5Vgs
R342 1k
FDN335N
VTTPWRGD26
APICD012
APICD112
APICCLK_CPU6
CPUHCLK6
CPU_PWGD12,33
CPURST#7,33
R406
TUAL56,7,26
ITP_DBRESET
VTT
Q27
5
R314
1K
ITP_VTT
J2
2 1
4 3
6 5
8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
XHEADER_15X2
ITP_CPURESET
R319
243,1%
R346
1k
21
43
65
87
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
PR6
150,1%
VCC2_5
R373330
PR4
150,1%
MC7
4.7UF
R199
1.8k
R15
150
BC7
0.1UF
4
Stuff either R5 or R415. See p33.
R5
R6
R13
R14
39
39
330
150
R317 0
R318 243,1%
VTT
R33
90.9,1%
R345 1k
R275
22
C12
10PF
4
Do Not stuff C
Place Site w/in 0.5"
of clock pin (W37)
C3
X18PF
R7
150
R316 0
VTT
AG1_VTT/NC
R8
330
VTT
R374
14
NCHCTRLP
R340
1k
DYN_OE
RESET2#
AN35
AN37
AN33
AL33
AK32
AM2
W35
AN3
AK4
W37
AK26
AH4
AG1
A35
G33
E37
C35
E35
N33
N35
N37
Q33
Q35
Q37
F10
G37
AL1
Y33
AJ3
C37
J37
Y1
R2
L33
X2
J35
L35
J33
X4
3
BC1
R9
Debug sites only.
1 2
C163
0.1uF
BC18
0.1UF
VTT
AB36
AD36
Z36
V1_5
V_CMOS
Part2
VTT
GTLREFA
BC17
0.1UF
0.1UF
680
U3B
TDI
TDO
TRST#
TCK
TMS
PREQ#
PRDY#
BP2#
BP3#
BPM0#
BPM1#
370 - Pin Socket
RSRVD6
RSRVD7
RSRVD8
RSRVD9
RSRVD10
RSRVD11
RSRVD13
RSRVD15
RSRVD16
RSRVD17
RSRVD18
RSRVD19
RSRVD20
RSRVD21
RESVD21(BR1#)
DYN_OE
VTTPWRGD
PICD0
PICD1
PICCLK
BCLK
CLKREF
PWRGOOD
RESET#
RESET2#
RSVD - NC
EDGCTRL/VRSEL
CPUPRES#
Socket 370_9
FB30BEAD
PR7
75,1%
PR8
150,1%
3
GTLREFA
CMOSREF
E33
F18K4R6V6AD6
AK12
AK22
BNR#
V2_5
VREF0
VREF1
VREF2
VREF3
VREF4
VREF5
VREF6
VREF7
BPRI#
TRDY#
DEFER#
LOCK#
DRDY#
HITM#
HIT#
DBSY#
ADS#
FLUSH#
BSEL0#
BSEL1#
RSRVD12/JBSEL1#
BR0#
THRMDP
THRMDN
THERMTRIP#
A20M#
STPCLK#
SLP#
SMI#
LINT0/INTR
LINT1/NMI
INIT#
FERR#
IGNNE#
IERR#
PLL1
PLL2
RSP#
AP0#
AP1#
BINIT#
AERR#
BERR#
TUALDET
SLEWCNTR
RTTCNTR
VCOREDET
RP#
GTLREF Generation Circuit
Use 0603 Packages and distribute
GTLREF Inputs ( 1 cap for every 2 inputs )
within 500 mils of processor
GTLREFA 32
GTLREF 7,32
GTLREFA to CPU.
GTLREF to GMCH.
BC16
0.1UF
R330 X0
Do not stuff R330
BC12
0.1UF
2
AH14
AN17
AN25
AN19
AK20
AN27
AL23
AL25
AL27
AN31
AE37
AJ33
AJ31
AK30
AN29
AL31
AL29
AH28
AE33
AG35
AH30
AJ35
M36
L37
AG33
AC35
AG37
AE35
W33
U33
AC37
AL11
AN13
AN23
B36
AK24
V4
AF36
E27
S35
E21
2
FLUSH#
PLL1
PLL2
TUALDET
SLEWCNTR
RTTCNTR
Document:
Page Name:
Last Revised:
BSEL#10BSEL#0
0
10
1
V3SB
R2
R1
150
150
33uF (C size)
+
C6
Debug only!
R375 0
PR1
PR5
56,%1
110,%1
V3SB
R3
1K
VTT
FSB
66M
0
100M
1
rsvd
1 133M
R4
150 1%
1K
L2
4.7UH/SMD-0805
R344
1k
JP6
JUMPER
R338
75 1%
R339
BNR# 7
BPRI# 7
HTRDY# 7
DEFER# 7
HLOCK# 7
DRDY# 7
HITM# 7
HIT# 7
DBSY# 7
HADS# 7
BSEL#0 29,32
BSEL#1 29,32
BR0# 5
VTIN2 21,25
THRMDN 21,25
THERMTRIP# 33
A20M# 12
STPCLK# 12
CPUSLP# 12
SMI# 12
INTR 12
NMI 12
INIT# 12,17
FERR# 12
IGNNE# 12
VCCVID
VCC5
Q26
2N3904
Debug only! Do NOT place
jumper before removing
R375
Intel(R) 815E Chipset Universal Socket 370 CRB
370-pin Socket Part 2
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
VCMOS
CMOSREF generation circuitPlace near AB36
R343
2.2k
1
BC228
0.1uF
1
CMOSREF
VCC5
Q25
2N7002
TUAL5#
Revision:
Page No:
433
R341
2.2k
TUAL5 6,7
1.05
of
Tu
5
D D
4
3
2
1
BC22
0.1UF
VTT
R12 150
BC9
0.1UF
BC15
0.1UF
ITPRDY# 4
BC2
0.1UF
BC13
0.1UF
BC3
0.1UF
R23 56
C C
VTT
MC23
MC22
BC34
BC35
BC36
BC37
BC38
BC24
0.1UF
0.1UF
0.1UF
0.1UF
4.7UF
4.7UF
VTT
Do not populate in assembly - debug sites only.
Debug cap sites - place near processor
C164
B B
820uF
0.1UF
0.1UF
BC23
0.1UF
BC5
0.1UF
BR0# 4
BC14
0.1UF
VTT Decoupling
A A
Document:
Page Name:
Last Revised:
5
4
3
2
Intel(R) 815E Chipset Universal Socket 370 CRB
VTT Decoupling
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
1
Revision:
1.05
Page No:
533
of
A
VCC_CLOCK
VCC_CLOCK
4 4
VCC2_5
1 2
PFB5
1 2
BEAD
1 2
PFB4
BEAD
PFB11
BEAD
BC56
0.1UF
4.7UF
MC21
4.7UF
MC28
BC25
0.1UF
BC55
0.01UF
MC29
4.7UF
BC26
0.01UF
FMOD129
ICH_CLK1413
ICH_3V6613
GMCH_3V668
AGPCLK_CONN11
3 3
PCLK_0/ICH12
R60 10
FMOD029
SLP_S3#13,21,28
R_SMBCLK32
R_SMBDATA32
C41
C40
C39
C29
X10PF
X10PF
X10PF
X10PF
VCC3_3
Q29
VTTPWRGD1226
2 2
Clock powe r g ate
FDN359AN
VCC_CLOCK
VCC3_3
1 2
Rds_on = 100 mOhm.
MEMCLK0
MEMCLK1
MEMCLK2
MEMCLK3 MEMCLK7
1 1
246
246
135
135
A
MEMCLK4
MEMCLK5
MEMCLK6
CN4
X10P/8P4C
78
7 8
246
246
135
135
BC62
BC61
0.01UF
0.1UF
C42
X10PF
PFB12
BEAD
CN5
X10P/8P4C
78
7 8
B
BC57
0.01UF
C35
18PF
C33
18PF
MC66
4.7UF
MEMCLK8
MEMCLK9
MEMCLK10
MEMCLK11
B
BC59
BC58
0.01UF
0.1UF
Y3
14.318MHZ
R64 33
R65 33
R66 33
R67 33
R290 33
R72 10
BC222
BC221
0.01UF
0.1UF
C34
X10PF
AV3 USBV3
R249 8.2K
BC60
0.1UF
L_VCC2_5
25914202531
56
U6
VDD
VDD
VDDL
VDDL
6
X1
7
X2
4
REF0
10
3V66-0
11
3V66-1
12
3V66-2
15
PCICLK0
16
PCICLK1
18
FS0
28
FS1
21
PD#
22
SCLK
23
SDATA
GNDL
GNDL
GND
GND
GND
3558131719243034
R303
C31
X10PF
R302
10K
C23
X10PF
10K
PCLK_REF
C22
X10PF
4
13
9
8
1 6
5
12
Ensure that the bu f f e r u s e d w ill d isab le
its PLL and trist a t e output s w hen no
refclk is present; othe r w is e , m u s t g a t e
power here, too.
C
35
404449
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDA
CPUCLK_0
CPUCLK_1
IOAPIC
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
48MHZ_0
48MHZ_1
GND
GND
GND
GND
GND
GND
GND
GND
39
434852
U29
VDD
VDD
CLKA1
CLKA2
CLKA3
FS1
CLKA4
FS2
REF CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
GND
GND
ICS9112B-17
C
MEMV3PCIV3
BC226
0.01UF
54
53
1
51
50
47
46
45
42
41
38
37
36
33
32
29
26
27
ICS9250-28
2
3
14
15
7
10
11
16
BC227
0.1UF
BC28
0.01UF
BC27
0.1UF
RN34
7
5
3
1
33/8P4R
R277 33
R312 X33
BC29
BC30
0.01UF
0.1UF
R320 33
R46 33
R45 33
R57 33
R58 33
7
8
5
6
3
4
1
2
RN19 22/8P4R
7
8
5
6
3
4
1
2
RN20 22/8P4R
R50 22
R51 22
R62 22
R63 22
R44 22
R48 33
R49 33
R47 33
8
6
4
2
X10P/8P4C
C132
X18PF
BC33
0.01UF
CN6
C19
X10PF
BC21
0.1UF
C21
X10PF
246
246
135
135
D
BC32
0.01UF
BC63
BC64
0.01UF
0.1UF
C20
C133
X10PF
X10PF
C120
X10PF
78
7 8
D
BC31
0.1UF
4.7UF
MC20
4.7UF
4.7UF
C25
C24
X10PF
X10PF
Document:
Page Name:
Last Revised:
E
PFB2
1 2
MC18
1 2
MC19
BEAD
PFB1
BEAD
VCC_CLOCK
VCC_CLOCK
R347
R348
0
130
2N7002
MEMCLK0
MEMCLK1
MEMCLK2
MEMCLK3
MEMCLK4
MEMCLK5
MEMCLK6
MEMCLK7
MEMCLK8
MEMCLK9
MEMCLK10
MEMCLK11
Q28
APICCLK_CPU 4
ITPCLK 4
CPUHCLK 4
GMCHHCLK 7
APICCLK_ICH 12
DCLK_WR 7
USBCLK 13
DOTCLK 8
SIO_CLK24 21
C28
X10PF
C30
X10PF
MEMCLK[0..7]
MEMCLK[8..11]
MEMCLK[0..7] 9
MEMCLK[8..11] 10
PCLK_1 14
PCLK_2 14
PCLK_3 15
PCLK_7 21
PCLK_8 17
Intel(R) 815E Chipset Universal Socket 370 CRB
Clock Generator
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
E
TUAL5 4,7,26
Revision:
1.05
Page No:
633
of
5
Debug sites only.
VTT
1 2
FB31BEAD
GTLREF
2
D D
HADS#
R407
Place
near GMCH
56
VTT
C C
B B
A A
HA#[3..31]3
0.1uF
C168
PR43
150,1%
HREQ#03
HREQ#13
HREQ#23
HREQ#33
HREQ#43
RS#03
RS#13
RS#23
PR42
63.4 1%
BC72
0.1UF
GMCHHCLK6
PCIRST#16,17,21,30
CPURST#4,33
HLOCK#4
DEFER#4
BNR#4
BPRI#4
DBSY#4
DRDY#4
HIT#4
HITM#4
HTRDY#4
HA#[3..31]
5
Place close
to GMCH
BC73
0.1UF
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
RS#0
RS#1
RS#2
Do Not Stuff C
Place Site w/in
0.5" of clock
ball(v6)
VTT
U7A
R61
90.9,1%
U6
GTLREFA
AA10
GTLREFB
AA7
HCLK
H3
AA5
M3
G1
N4
M5
R4
R3
N5
R1
U1
R5
W1
U4
W3
W4
U5
U3
W5
M1
N1
M2
N3
H1
C38
X18PF
L4
J3
J1
K1
L3
K3
P1
T2
P5
P2
T1
T3
P3
T5
V5
Y2
V3
V2
Y5
Y3
Y1
V1
L5
K2
L1
RESET#
CPURST#
HLOCK#
DEFER#
ADS#
BNR#
BPRI#
DBSY#
DRDY#
HIT#
HITM#
HTRDY#
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
RS#0
RS#1
RS#2
Host Interface
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
AA1
AB2
AF2
AD4
AB1
AB3
AA3
AC4
AC1
AF3
AD1
AE3
AD2
AD3
AF1
AA4
AD6
AC3
AE1
AB6
AF4
AE5
AC8
AB5
AF5
AC6
AF6
AD11
AF8
AD8
AD5
AB7
AF7
AD7
AB8
AE7
AE9
AB9
AF9
AD10
AF12
AB11
AB10
AD9
AC10
AF10
AD14
AD12
AB12
AE11
AE15
AF11
AF13
AB14
AF14
AB13
AB15
AE13
AC14
AD13
AD15
AF16
AF15
AC12
4
HD#[0..63]
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
4
HD#[0..63] 3
SM_MAC#[4..7]10
SM_MAA[0..12]9,10
SM_DQM[0..7]9,10
SM_CKE[0..3]9
SM_CKE[4..5]10
SM_CSA#[0..3]9
SM_CSA#[4..5]10
SM_CSB#[0..3]9
SM_CSB#[4..5]10
SM_BS09,10
SM_BS19,10
SM_RAS#9,10
SM_CAS#9,10
SM_WE#9,10
DCLK_WR6
VCC3SBY
3
SM_MAC#[4..7]
SM_MAB#[4..7]
SM_MAA[0..12]
SM_MAA0
SM_MAA1
SM_MAA2
SM_MAA3
SM_MAA4
SM_MAA5
SM_MAA6
SM_MAA7
SM_MAA8
SM_MAA9
SM_MAA10
SM_MAA11
SM_MAA12
RN38 10/8P4R
SM_MAB#4
SM_MAB#5
SM_MAB#6
SM_MAB#7
SM_MAC#4
SM_MAC#5
SM_MAC#6
SM_MAC#7
RN36 10/8P4R
SM_CSA#0
SM_CSA#1
SM_CSA#2
SM_CSA#3
SM_CSA#4
SM_CSA#5
SM_CSB#0
SM_CSB#1
SM_CSB#2
SM_CSB#3
SM_CSB#4
SM_CSB#5
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CKE4
SM_CKE5
SM_DQM[0..7]
SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7
PR9 40.2,1%
SM_CKE[0..3]
SM_CKE[4..5]
SM_CSA#[0..3]
SM_CSA#[4..5]
SM_CSB#[0..3]
SM_CSB#[4..5]
3
1
3
5
7
1
3
5
7
1
3
5
7
RN37
10/8P4R
C36
22PF
2
SM_MD[0..63]
U7B
D13
SMAA0
B16
SMAA1
F12
SMAA2
A16
SMAA3
2
B12
SMAA4
4
A12
SMAA5
6
C11
SMAA6
8
A11
SMAA7
D12
SMAA8
C13
SMAA9
E11
SMAA10
A13
SMAA11
B7
SMAA12
2
B15
SMAB#4
4
A15
SMAB#5
6
C14
SMAB#6
8
A14
SMAB#7
2
B10
SMAC4
4
A10
SMAC5
6
C10
SMAC6
8
A9
SMAC7
B13
SBS0
D11
SBS1
D15
SCSA#0
A17
SCSA#1
D14
SCSA#2
E14
SCSA#3
E13
SCSA#4
B17
SCSA#5
F9
SCSB#0
F8
SCSB#1
D10
SCSB#2
D9
SCSB#3
B9
SCSB#4
A8
SCSB#5
C16
SRAS#
D18
SCAS#
E16
SWE#
D8
SCKE0
E8
SCKE1
E9
SCKE2
D7
SCKE3
C8
SCKE4
C7
SCKE5
F7
SCLK
G10
RESVD
D16
SDQM0
F15
SDQM1
A7
SDQM2
A6
SDQM3
A18
SDQM4
C17
SDQM5
B6
SDQM6
A5
SDQM7
G7
SRCOMP
82815 GMCH
SYSTEM MEMORY
SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SMD8
SMD9
SMD10
SMD11
SMD12
SMD13
SMD14
SMD15
SMD16
SMD17
SMD18
SMD19
SMD20
SMD21
SMD22
SMD23
SMD24
SMD25
SMD26
SMD27
SMD28
SMD29
SMD30
SMD31
SMD32
SMD33
SMD34
SMD35
SMD36
SMD37
SMD38
SMD39
SMD40
SMD41
SMD42
SMD43
SMD44
SMD45
SMD46
SMD47
SMD48
SMD49
SMD50
SMD51
SMD52
SMD53
SMD54
SMD55
SMD56
SMD57
SMD58
SMD59
SMD60
SMD61
SMD62
SMD63
D23
C23
D22
F21
E21
G20
F20
D20
F19
E19
D19
E18
B18
F18
G18
D17
A3
A1
C1
F2
G3
D6
C5
B4
D4
C2
D3
E4
F5
G4
J6
K5
A26
A25
B24
A24
B23
A23
C22
A22
D21
B21
A21
C20
B20
A20
C19
A19
A4
A2
B1
E1
G2
E6
D5
C4
B3
D2
E3
F4
F6
G5
H4
J4
SM_MD[0..63] 9,10SM_MAB#[4..7]9
SM_MD0
SM_MD1
SM_MD2
SM_MD3
SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8
SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13
SM_MD14
SM_MD15
SM_MD16
SM_MD17
SM_MD18
SM_MD19
SM_MD20
SM_MD21
SM_MD22
SM_MD23
SM_MD24
SM_MD25
SM_MD26
SM_MD27
SM_MD28
SM_MD29
SM_MD30
SM_MD31
SM_MD32
SM_MD33
SM_MD34
SM_MD35
SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40
SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45
SM_MD46
SM_MD47
SM_MD48
SM_MD49
SM_MD50
SM_MD51
SM_MD52
SM_MD53
SM_MD54
SM_MD55
SM_MD56
SM_MD57
SM_MD58
SM_MD59
SM_MD60
SM_MD61
SM_MD62
SM_MD63
Document:
Page Name:
Last Revised:
BC188
X0.1UF
Backside decouping , should be
placed under chipset memory signal
field
BC192
X0.1UF
Backside decouping , should be
placed under chipset AGP signal
field
SM_MAA12
TUAL54,6,26
SM_WE#
R90 8.2K
R89 8.2K
SM_MAA9
R88 10K
R68 X10K
R77 X10K
Host Freq : HI=100 LO=66
FSB P-MOS Kicker : HI=NON-Cu LO=Cu
Host Freq : HI=133 LO=100/66
LM FREQ : HI=133 LO=100
SM/LM muxing strap , active low
ALLZ : LO=ALLZ HI=Normal
IOQ depth : HI=4 LO=1
LO = Future 0.13u Socket 370 processors
HI = Pentium(R) III Processor or Intel(R)
Celeron(tm) Processor w/CPUID = 068Xh
XOR chain : LO=XOR HI=Normal
SM_WE#
SM_MAA9
SM_CAS#
SBA7
SM_BS0
SM_BS1
SM_MAA10
SM_MAA11
SM_MAA12
SM_RAS#
SM_CAS#
Intel(R) 815E Chipset Universal Socket 370 CRB
GMCH Part 1
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
2
BC190
X0.1UF
BC193
X0.1UF
1
BC191
X0.1UF
BC194
X0.1UF
SM_MAA10
SM_RAS#
1
VCC3SBY
BC189
X0.1UF
VDDQ
BC195
X0.1UF
R349
10k
Q30
2N7002
R_BSEL#0 29
R_REFCLK 29
Revision:
Page No:
733
1.05
of
5
4
3
2
1
SBA[0..7]
HL[0..10]
GAD[0..31]
PR15
40.2,1%
CONN_AGPREF11,32
GAD[0..31]11
GCBE#011
GCBE#111
GCBE#211
GCBE#311
GFRAME#11
GDEVSEL#11
GIRDY#11
GTRDY#11
GSTOP#11
GPAR11
GREQ#11
GGNT#11
PIPE#11
ADSTB011
ADSTB0#11
ADSTB111
ADSTB1#11
SBSTB11
SBSTB#11
ST011
ST111
ST211
RBF#11
WBF#11
PR14 15.1%
BC89
0.1UF
NOTE :
5
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GRCOMP
OCLK
RCLK
OCLK = 0.5"
RCLK = 1.5"
K26
J22
K25
J21
L24
J20
L26
K23
K22
M25
M24
M26
M21
N24
N22
N26
T26
T22
U24
T23
U26
T24
V24
U21
V25
V21
V26
W21
W24
W22
W26
Y21
H23
N21
T25
Y26
R26
P26
P23
P21
P25
R24
AE26
AD25
AC26
M22
L23
U22
V23
Y23
AA24
AD24
AC24
AC23
AD26
AB24
J24
J26
R22
P22
C61
15PF/5%,MPO
D D
C C
B B
A A
U7C
GAD0/LDQM0
GAD1/LMD4
GAD2/LMD7
GAD3/LMD3
GAD4/LMD6
GAD5/LMD2
GAD6/LMD5
GAD7/LMD1
GAD8/LMD0
GAD9/LMA4
GAD10/LDQM1
GAD11/LMA2
GAD12/LMD8
GAD13/LMA5
GAD14/LMD9
GAD15/LMA1
GAD/16/LMA8
GAD17/LMD14
GAD18/LMA11
GAD19/LMD15
GAD20/LMA9
GAD21/LMD16
GAD22/LCS#
GAD23/LMD17
GAD24/LCKE
GAD25/LMD18
GAD26/LCAS#
GAD27/LMD19
GAD28/LTCLK1
GAD29/LMD20
GAD30/LTCLK0
GAD31/LMD21
GCBE#0/LMA3
GCBE#1/LMD10
GCBE#2/LMD13
GCBE#3/LRDS#
GFRAME#/LMA10
GDEVSEL#/LMD11
GIRDY#/LMD12
GTRDY#/LMA7
GSTOP#/LMA0
GPAR/LMA6
GREQ#/LMD27
GGNT#
PIPE#/LMD24
ADSTB0
ADSTB0#
ADSTB1
ADSTB1#
SBSTB
SBSTB#
ST0/LMD28
ST1/LDQM3
ST2/LMD29
RBF#/LMD30
WBF#
AGPREF
GRCOMP
OCLOCK
RCLOCK
82815 GMCH
Display Cache, Video, and
HUB Interface
LTVDATA0
LTVDATA1
LTVDATA2
LTVDATA3
LTVDATA4
LTVDATA5
LTVDATA6
LTVDATA7
LTVDATA8
LTVDATA9
LTVDATA10
LTVDATA11
BLANK#
TVCLKIN/SL_STALL
CLKOUT0
CLKOUT1
TVVSYNC
TVHSYNC
DCLKREF
IWASTE
HUBREF
HLSTB#
HCOMP
SBA0/LMD31
SBA1/LMD25
SBA2/LDQM2
SBA3/LMD26
SBA4/LMD23
SBA5/LWE#
SBA6/LMD22
SBA7/LGM_FREQ_SEL
LTVCK
LTVDA
DDDA
DDCK
IREF
VSYNC
HSYNC
RED
GREEN
BLUE
HCLK
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HLSTB
AD16
AF17
AE17
AD17
AF18
AD18
AF20
AD20
AC20
AF21
AE21
AD21
AB19
AC18
AE19
AF19
AC16
AB17
AB21
AA20
AA18
AB18
AE24
Y20
AD23
AF22
AF23
AD22
AE22
AE23
F22
H24
H26
H25
G24
F24
E26
E25
D26
D25
D24
C26
H21
G25
F26
H20
AB22
AB25
AB23
AB26
AA22
AA26
Y22
Y25
PR13
174,1%
4
FTD[0..11]
R251 22
Place as close as
Possible to GMCH
and via straight
to VSS plane
FTD0
FTD1
FTD2
FTD3
FTD4
FTD5
FTD6
FTD7
FTD8
FTD9
FTD10
FTD11
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HUBREF_GMCH
HCOMP
SBA[0..7] 11
HL[0..10] 12
FTD[0..11] 16
VCC1_8
L6 22nH
FTBLNK# 16
SL_STALL 16
FTCLK0 16
FTCLK1 16
FTVSYNC 16
FTHSYNC 16
3VFTSCL 16
3VFTSDA 16
3VDDCDA 16
3VDDCCL 16
DOTCLK 6
CRT_VSYNC 16
CRT_HSYNC 16
VID_RED 16
VID_GREEN 16
VID_BLUE 16
GMCH_3V66 6
HLSTB 12
HLSTB# 12
SBA0 11
SBA1 11
SBA2 11
SBA3 11
SBA4 11
SBA5 11
SBA6 11
SBA7 11
C169
33uF
0.1uF
C58
10PF
Do Not Stuff C
Place Site w/in 0.5"
of clock ball(AA21)
VCC1_8
Place R as
PR18
Close as
possible to
GMCH
40.2,1%
Place as close as
Possible to GMCH
and via straight
to VSS plane
C170
BC90
0.1UF
3
0.01uF
VCC1_8
C171
PR16
301,1%
PR17
301,1%
VCC1_8VCC3SBYVDDQ
W6
Y18
AA6
AA8
AA11
AA13
AA15
AA17
AA19
AB16
AB20
AC22
AD19
C25
E24
F23
G22
M6
G26
AA21
E23
AF26
AF25
B11
B14
B19
B22
B25
F10
F14
F17
G6
G8
G19
H2
H5
H7
K20
Y24
L21
M23
U25
N25
R21
U20
U23
W20
AF24
AE25
U7D
VCC_1.8
Y9
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
J7
VCC_1.8
K6
VCC_1.8
VCC_1.8
P6
VCC_1.8
T6
VCC_1.8
V7
VCC_1.8
VCC_1.8
VCC1_8
Y7
VCC1_8
VCC1_8
VCC1_8
VCC1_8
B2
VCC3SBY
B5
VCC3SBY
B8
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
E2
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
82815 GMCH
Power and Ground
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
AB4
E7
AC2
AC5
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC25
AE2
AE4
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
B26
C3
C6
C9
C12
C15
C18
C21
C24
D1
E5
E10
E12
E15
E17
E20
E22
F1
F3
F11
F13
T21
U2
U7
K24
V4
V6
V20
V22
W2
W7
W23
W25
Y4
Y6
Y8
Y10
Y17
Y19
AA2
AA9
AA12
AA14
AA16
Document:
Page Name:
Last Revised:
U7E
PR21
82,1%
PR24
82,1%
M11
M12
M13
M14
M15
M16
P11
P12
P13
P14
P15
P16
R11
R12
R13
R14
R15
R16
R23
R25
T11
T12
T13
T14
T15
T16
L15
L16
L22
L25
R2
R6
T4
M4
560PF
560PF
C69
C72
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Solano
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PR23
1K,1%
GMCH_AGPREF 11
PR22
1K,1%
N2
N6
N11
N12
N13
N14
N15
N16
N23
AA23
F16
F25
G9
G17
G21
G23
P24
H6
H22
J2
J5
J23
J25
K4
K7
K21
L2
L6
L11
L12
L13
L14
AA25
P4
Intel(R) 815E Chipset Universal Socket 370 CRB
GMCH Part 2
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
1
Revision:
1.05
Page No:
833
of
A
DIMM1
1
SM_MD0
SM_MD1
SM_MD2
SM_MD3
SM_MD4
4 4
3 3
2 2
1 1
SM_MD5
SM_MD6
SM_MD7
SM_MD8
SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13
SM_MD14
SM_MD15
SM_WE#
SM_DQM0
SM_DQM1
SM_CSA#0
SM_MAA0
SM_MAA2 SM_MAA2
SM_MAA4
SM_MAA6
SM_MAA8
SM_MAA10
SM_BS1
MEMCLK0
SM_CSB#0
SM_DQM2
SM_DQM3
SM_MD16
SM_MD17
SM_MD18
SM_MD19
SM_MD20
SM_CKE1
SM_MD21
SM_MD22
SM_MD23
SM_MD24
SM_MD25
SM_MD26
SM_MD27
SM_MD28
SM_MD29
SM_MD30
SM_MD31
MEMCLK2
SMBDATA
SMBCLK
A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VDD
WE#/WE0#
DQM0
DQM1
CS0#
DU/OE0#
VSS
A0
A2
A4
A6
A8
A10/AP
BA1/A12
VDD
VDD
CLK0/DU
VSS
DU/OE2#
CS2#
DQM2
DQM3
DU/WE2#
VDD
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
VREF/DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2/NC
NC
WP
SDA
SCL
VDD
DIMM168
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
CB12
CB13
VDD
CAS#/DU
DQM4
DQM5
CS1#
RAS#/DU
VSS
BA0/A11
A11/A13
VDD
CLK1/DU
A12/DU
VSS
CKE0/DU
CS3#
DQM6
DQM7
A13/DU
VDD
CB14
CB15
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
VREF/DU
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CLK3/NC
SA0
SA1
SA2
VDD
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
A1
118
A3
119
A5
120
A7
121
A9
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
NC
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
NC
165
166
167
168
B
B
SM_MD32
SM_MD34
SM_MD35
SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40
SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45
SM_MD46
SM_MD47
SM_CAS#
SM_DQM4
SM_DQM5
SM_CSA#1
SM_RAS#
SM_MAA1
SM_MAA3
SM_MAA5
SM_MAA7
SM_MAA9
SM_BS0
SM_MAA11
MEMCLK1
SM_MAA12
SM_CKE0
SM_CSB#1
SM_DQM6
SM_DQM7
SM_MD48
SM_MD49
SM_MD50
SM_MD51
SM_MD52
SM_MD53
SM_MD54
SM_MD55
SM_MD56
SM_MD57
SM_MD58
SM_MD59
SM_MD60
SM_MD61
SM_MD62
SM_MD63
C
VCC3SBY VCC3SBYVCC3SBYVCC3SBY
SM_MD0
SM_MD1SM_MD33
SM_MD2
SM_MD3
SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8
SM_MD9
SM_MD10
SM_MD11 SM_MD43
SM_MD12
SM_MD13
SM_MD14
SM_MD15
SM_WE#
SM_DQM0
SM_DQM1
SM_CSA#2
SM_MAA0
SM_MAB#4
SM_MAB#6
SM_MAA8
SM_MAA10
SM_BS1
MEMCLK4
SM_CSB#2
SM_DQM2
SM_DQM3
SM_MD16
SM_MD17
SM_MD18
SM_MD19
SM_MD20
SM_CKE3
SM_MD21
SM_MD22
SM_MD23
SM_MD24
SM_MD25
SM_MD26
SM_MD27
SM_MD28
SM_MD29
SM_MD30
SM_MD31
MEMCLK6
SMBDATA
SMBCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DIMM2
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VDD
WE#/WE0#
DQM0
DQM1
CS0#
DU/OE0#
VSS
A0
A2
A4
A6
A8
A10/AP
BA1/A12
VDD
VDD
CLK0/DU
VSS
DU/OE2#
CS2#
DQM2
DQM3
DU/WE2#
VDD
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
VREF/DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2/NC
NC
WP
SDA
SCL
VDD
DIMM168
C
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
CB12
CB13
VDD
CAS#/DU
DQM4
DQM5
CS1#
RAS#/DU
VSS
BA0/A11
A11/A13
VDD
CLK1/DU
A12/DU
VSS
CKE0/DU
CS3#
DQM6
DQM7
A13/DU
VDD
CB14
CB15
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
VREF/DU
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CLK3/NC
SA0
SA1
SA2
VDD
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
A1
118
A3
119
A5
120
A7
121
A9
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
NC
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
NC
165
166
167
168
SM_MD32
SM_MD33
SM_MD34
SM_MD35
SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40
SM_MD41
SM_MD42
SM_MD44
SM_MD45
SM_MD46
SM_MD47
SM_CAS#
SM_DQM4
SM_DQM5
SM_CSA#3
SM_RAS#
SM_MAA1
SM_MAA3
SM_MAB#5
SM_MAB#7
SM_MAA9
SM_BS0
SM_MAA11
MEMCLK5
SM_MAA12
SM_CKE2
SM_CSB#3
SM_DQM6
SM_DQM7
SM_MD48
SM_MD49
SM_MD50
SM_MD51
SM_MD52
SM_MD53
SM_MD54
SM_MD55
SM_MD56
SM_MD57
SM_MD58
SM_MD59
SM_MD60
SM_MD61
SM_MD62
SM_MD63
MEMCLK7MEMCLK3
D
D
R28
2.2K
Document:
Page Name:
Last Revised:
E
VCC3SBY
SM_MAA[0..12]
SM_MD[0..63]
SM_MAB#[4..7]
SM_DQM[0..7]
MEMCLK[0..7]
SM_CKE[0..3]
SM_CSA#[0..3]
SM_CSB#[0..3]
SM_WE#
SM_RAS#
SM_CAS#
SM_BS0
SM_BS1
SMBDATA
SMBCLK
DM_SA_PU 10
SM_MAA[0..12] 7,10
SM_MD[0..63] 7,10
SM_MAB#[4..7] 7
SM_DQM[0..7] 7,10
MEMCLK[0..7] 6
SM_CKE[0..3] 7
SM_CSA#[0..3] 7
SM_CSB#[0..3] 7
SM_WE# 7,10
SM_RAS# 7,10
SM_CAS# 7,10
SM_BS0 7,10
SM_BS1 7,10
SMBDATA 10,13,21,24,30,32
SMBCLK 10,13,21,24,30,32
Intel(R) 815E Chipset Universal Socket 370 CRB
DIMMs 1 and 2
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
E
Revision:
1.05
Page No:
933
of
CH6-12
A
SM_MAA[0..12]7,9
SM_MD[0..63]7,9
SM_MAC#[4..7]7
4 4
3 3
2 2
1 1
SM_DQM[0..7]7,9
MEMCLK[8..11]6
SM_CKE[4..5]7
SM_CSA#[4..5]7
SM_CSB#[4..5]7
SM_WE#7,9
SM_RAS#7,9
SM_CAS#7,9
SM_BS07,9
SM_BS17,9
SMBDATA9,13,21,24,30,32
SMBCLK9,13,21,24,30,32
DM_SA_PU9
A
SM_MAA[0..12]
SM_MD[0..63]
SM_MAC#[4..7]
SM_DQM[0..7]
MEMCLK[8..11]
SM_CKE[4..5]
SM_CSA#[4..5]
SM_CSB#[4..5]
SM_WE#
SM_RAS#
SM_CAS#
SM_BS0
SM_BS1
SMBDATA
SMBCLK
SM_MD0
SM_MD1
SM_MD2
SM_MD3
SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8
SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13
SM_MD14
SM_MD15
SM_WE#
SM_DQM0
SM_DQM1
SM_CSA#4
SM_MAA0
SM_MAA2
SM_MAC#4
SM_MAC#6
SM_MAA8
SM_MAA10
SM_BS1
MEMCLK8
SM_CSB#4
SM_DQM2
SM_DQM3
SM_MD16
SM_MD17
SM_MD18
SM_MD19
SM_MD20
SM_CKE5
SM_MD21
SM_MD22
SM_MD23
SM_MD24
SM_MD25
SM_MD26
SM_MD27
SM_MD28
SM_MD29
SM_MD30
SM_MD31
MEMCLK10
SMBDATA
SMBCLK
B
VCC3SBY VCC3SBY
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DIMM3
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VDD
WE#/WE0#
DQM0
DQM1
CS0#
DU/OE0#
VSS
A0
A2
A4
A6
A8
A10/AP
BA1/A12
VDD
VDD
CLK0/DU
VSS
DU/OE2#
CS2#
DQM2
DQM3
DU/WE2#
VDD
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
VREF/DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2/NC
NC
WP
SDA
SCL
VDD
DIMM168
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB12
CB13
VDD
CAS#/DU
DQM4
DQM5
CS1#
RAS#/DU
BA0/A11
A11/A13
VDD
CLK1/DU
A12/DU
CKE0/DU
CS3#
DQM6
DQM7
A13/DU
VDD
CB14
CB15
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
VREF/DU
REGE
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
CLK3/NC
VDD
VSS
VSS
CB4
CB5
VSS
VSS
VSS
CB6
CB7
VSS
VSS
VSS
VSS
SA0
SA1
SA2
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
A1
118
A3
119
A5
120
A7
121
A9
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
NC
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
NC
165
166
167
168
C
SM_MD32
SM_MD33
SM_MD34
SM_MD35
SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40
SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45
SM_MD46
SM_MD47
SM_CAS#
SM_DQM4
SM_DQM5
SM_CSA#5
SM_RAS#
SM_MAA1
SM_MAA3
SM_MAC#5
SM_MAC#7
SM_MAA9
SM_BS0
SM_MAA11
MEMCLK9
SM_MAA12
SM_CKE4
SM_CSB#5
SM_DQM6
SM_DQM7
SM_MD48
SM_MD49
SM_MD50
SM_MD51
SM_MD52
SM_MD53
SM_MD54
SM_MD55
SM_MD56
SM_MD57
SM_MD58
SM_MD59
SM_MD60
SM_MD61
SM_MD62
SM_MD63
MEMCLK11
C
D
D
Document:
Page Name:
Last Revised:
E
Intel(R) 815E Chipset Universal Socket 370 CRB
DIMM 3
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
E
Revision:
1.05
Page No:
10 33
of
A
B
C
D
E
VCC3_3
VCC5
4 4
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
RN49
8.2K/8P4R
RN48
8.2K/8P4R
RN42
8.2K/8P4R
RN43
8.2K/8P4R
RN44
8.2K/8P4R
RN46
8.2K/8P4R
RN45
8.2K/8P4R
A
GSERR#
GPAR
GPERR#
GDEVSEL#
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GREQ#
GGNT#
ST0
ST1
3 3
2 2
1 1
ST2
RBF#
PIPE#
WBF#
SBA0
SBA1
SBA2
SBA3
SBA7
SBA6
ADSTB0
ADSTB0#
ADSTB1
ADSTB1#
SBSTB#
SBSTB
SBA5
SBA4
VDDQ
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
R3328.2K
R3338.2K
R3348.2K
R3358.2K
2
4
6
8
AGP_OC#18
AGPUSBP18
PIRQ#B14,15,30
AGPCLK_CONN6
GREQ#8
SBSTB8
ADSTB18
GCBE#28
GIRDY#8
GDEVSEL#8
GCBE#18
ADSTB08
GMCH_AGPREF8
GAD[0..31]8
SBA[0..7]8
GREQ# GGNT#
ST0 ST1
ST08
ST2
ST28
RBF#
RBF#8
SBA0 SBA1
SBA2 SBA3
SBSTB SBSTB1#
SBA4 SBA5
SBA6 SBA7
GAD31
GAD29
GAD27
GAD25
ADSTB1 ADSTB1#
GAD23
GAD21
GAD19
GAD17
GIRDY# GFRAME#
GDEVSEL# GTRDY#
GPERR#
GSERR# GPAR
GAD14
GAD12
GAD10
GAD8
ADSTB0 ADSTB0#
GAD7
GAD5
GAD3
GAD1
GAD[0..31]
SBA[0..7]
B
V3SB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
AGP1
OVRCNT#
5V_A
5V_B
USB+
GND_K
INTB#
CLK
REQ#/DQ27
VCC3.3_F
ST0/DQ28
ST2/DQ29
RBF#/DQ30
GND_L
RESV_H
SBA0/DQ31
VCC3.3_G
SBA2/DQM2
SB_STB
GND_M
SBA4/DQ23
SBA6/DQ22
RESV
GND_N
3.3VAUX1
VCC3.3_H
AD31/DQ21
AD29/DQ20
VCC3.3_I
AD27/DQ19
AD25/DQ18
GND_O
AD_STB1
AD23/DQ17
VDDQ_F
AD21/DQ16
AD19/DQ15
GND_P
AD17/DQ14
C/BE2#/DQ13
VDDQ_G
IRDY#/DQ12
3.3VAUX2
GND_Q
RESV_K
VCC3.3_J
DEVSEL#/DQ11
VDDQ_H
PERR#
GND_R
SERR#
C/BE1#/DQ10
VDDQ_I
AD14/DQ9
AD12/DQ8
GND_S
AD10/DQM1
AD8/DQ0
VDDQ_J
AD_STB0
AD7/DQ1
GND_T
AD5/DQ2
AD3/DQ3
VDDQ_K
AD1/DQ4
VREF_CG
C
TYPEDET#
RESV_A
GND_A
INTA#
VCC3.3_A
DQM3/ST1
RESV_B
DQ24/PIPE#
GND_B
WBF#
DQ25/SBA1
VCC3.3_B
DQ26/SBA3
SB_STB#
GND_C
WE#/SBA5
M_FREQ_SEL/SBA7
RESV_C
GND_D
RESV_D
VCC3.3_C
TCLK0/AD30
TCLK1/AD28
VCC3.3_D
CAS#/AD26
GND_E
AD_STB1#
RAS#/C/BE3#
VDDQ_A
A0/AD22
A9/AD20
GND_F
A11/AD18
A8/AD16
VDDQ_B
A10/FRAME#
RESV_E
GND_G
RESV_F
VCC3.3_E
A7/TRDY#
CS#/STOP#
PME#
GND_H
A6/PAR
A1/AD15
VDDQ_C
A5/AD13
A2/AD11
GND_I
A4/AD9
A3/C/BE0#
VDDQ_D
AD_STB0#
DQ5/AD6
GND_J
DQ6/AD4
DQ7/AD2
VDDQ_E
DQM0/AD0
VREF_GC
AGP4XU_20
USB-
RST#
GNT#
AD24
VCC12
VCC12
VDDQ
R106
2.2K
A1
12V
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
PIPE#
WBF#
GAD30
GAD28
GAD26
GAD24
GAD22
GAD20
GAD18
GAD16
GSTOP#
GAD15
GAD13
GAD11
GAD9
GAD6
GAD4
GAD2
GAD0
TYPEDET# 26
AGPUSBN 18
PIRQ#A 14,15,30
PCI_RST# 14,15,30
GGNT# 8
ST1 8
PIPE# 8
WBF# 8
SBSTB# 8
ADSTB1# 8
GCBE#3 8
GFRAME# 8
GTRDY# 8
GSTOP# 8
PCI_PME# 12,14,15,22
GPAR 8
GCBE#0 8
ADSTB0# 8
CONN_AGPREF 8,32
Document:
Page Name:
Last Revised:
D
VDDQ
Place close
to GMCH
CON_AGPREF
Q13
2N7002
PR20
301,1%
PR19
200,1%
Intel(R) 815E Chipset Universal Socket 370 CRB
AGP
Thursday, November 29, 2001
Page:
Thursday, November 29, 2001
Doc:
Platform Applications Engineering
1900 Prairie City Road
Folsom, CA 95630
E
Revision:
1.05
Page No:
11 33
of
CH6-18
Loading...