Intel 815E Schematic

A

B

C

D

E

Intel® Pentium® III and FC-PGA Celeron™ Processor/815E Chipset
Universal Socket 370 Platform

4 4

Customer Reference Board Schematics

Revision 1.05 - Fab C

PAGETITLE

1COVER SHEET
BLOCK DIAGRAM
PGA370 PART 1 & 2
AGTL TERMINATION
CLOCK GENERATO R
GMCH PART 1 & 2
DIMM 1 & 2

3 3

DIMM 3
AGP
ICH PART 1 & 2
PCI 1 & 2
PCI 3

VIDEO BUS & CONNECTOR
FWH & UDMA100 IDE 1 - 2
USB 0-3
AC97 CODEC
AUDIO I/O
LPC I/O CONTROLLER & FDCL
WOR, WOL & 2S1P

2 2

KB, MS, GAME & IR
FRONT PANEL & CNR

ATX POWER & H/W MONITOR
VREGS: VDDQ, VCC1_8, AND VTT
VREGS: VCCVID, V1_8SB
VREGS: DUALS, 3.3SB, 2.5, VCMOS
SYSTEM CONFIG U R AT IO N
PU/PDR & UNUSED GATES
DECOUPLING CAPACITORS

INTERNAL DEBUG HEADERS
THERMTRIP

2

3,4

5

6

7,8

9

10

11

12,13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or

otherwise , t o any in t ellectu al property rights is granted by this document. Except as provided in Intel's Terms and Conditions
of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating
to sale and/or use of Intel products including liability or warranties relating to fitn e ss fo r a p a rtic u la r p u rp o s e , m e rchantability,
or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical,
life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined."
Intel reserves these for future definition and shall have no responsibility whatsoev e r fo r c o n flic ts o r incompatibilities arising
from future changes to them.

The Intel® 815E chipset may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on r equest.

Contact your l ocal Int el sales office o r your distribut or to obt ain the l atest specifications and before placing your product
order.

I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2 C b u s /p ro to c o l and was
developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Ph ilips
Electronics N.V. and North American Philips Corporation.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Copies of documents which have an ordering number and are referenced in this document, or other Intel lite r a t u re, may be

obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel®, Pentium®, Pentiu m ® III, Ce le ro n ™, a re trademarks or registered trademarks of Intel Corporation or its subsidiar ies in
the United States and other countries.

*Other brands and names may be claimed as the property of others.
Copyright© 2001, Intel Corporation

**PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE

1 1

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Document:
Page Name:

Last Revised:

D

Intel(R) 815E Chipset Universal Socket 370 CRB
Title Page

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

133

of

A

B

C

D

E

BLOCK DIAGRAM

4 4

VRM

370-PIN SOCKET PROCESSOR

ADDR

CTRL

DATA

CLOCK

GTL BUS

ADDR

AGP

Connector

3 3

Digital Video

Out Connector

IDE Primary

UDMA/100

IDE Secondary

USB PORT 1-4

2 2

FirmWare Hub

USB

CTRL

GMCH

ICH2

DATA

PCI ADDR/DATA

AC’97 LINK

3 DIMM

Modules

PCI CNTRL

CNR
Connector

PCI CONN 1

PCI CONN 2

Note: PCI3
Connector is
not populated
on the board

PCI CONN3

SIO

Audio
Codec

1 1

Floppy

Game Port Serial 1

Keyboard

ParallelSerial 2

Document:
Page Name:

Last Revised:

Mouse

A

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D

Intel(R) 815E Chipset Universal Socket 370 CRB
Block Diagram

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

233

of

5

D D

C C

B B

RS#07
RS#17
RS#27

A A

5

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

U3A

W1

T4
N1

M6

U1
S3
T6
J1
S1
P6

Q3

M4

Q1

L1
N3
U3
H4
R4
P4
H6

L3
G1

F8
G3
K6
E3
E1

F12

A5
A3

J3
C5

F6
C1
C7
B2
C9
A9
D8

D10
C15
D14
D12

A7

A11
C11
A21
A15
A17
C13
C25
A13
D16
A23
C21
C19
C27
A19
C23
C17
A25
A27
E25
F16

AH26
AH22
AK28

Socket 370_9

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

RS#0
RS#1
RS#2

B26C3AK2

VCCVID

VCCVID

GND

GND

GND

GND

AM34

AH2

AD2Z2V2M2D18H2D2

AF2

AB2T2P2K2F4E5AM4

VCCVID

VCCVID

VCCVID

VCCVID

GND

GND

GND

GND

VCCVID

VCCVID

GND

GND

AL3

AE5

AA5W5S5N5J5F2D6B6AM8

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

GND

GND

GND

GND

GND

AG5

AC5Y5U5Q5L5G5D4B4AM6

4

AJ9E9B10

AM12

AJ13

E13

B14

AM16

AJ5

AJ17

E17

B18

AM20

AJ21

D20

F22

AM24

AJ25

D24

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

VCCVID

370 - Pin Socket Part 1

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

AJ7E7B8

AM10

AJ11

E11

B12

AM14

AJ15

E15

B16

AM18

AJ19

E19

F20

B20

AM22

AJ23

D22

F24

B24

4

F26

AM28

VCCVID

VCCVID

GND

GND

AM26

AJ27

AJ29

D28

VCCVID

VCCVID

GND

GND

D26

F28

3

AK34

F30

VCCVID

VCCVID

GND

GND

B28

AM30

3

B30

AM32

VCCVID

VCCVID

GND

GND

D30

AF32

AH32

Z32

VCCVID

VCCVID

GND

GND

AB32

X32

V32

R32

VCCVID

VCCVID

GND

GND

T32

P32

M32

H32

VCCVID

VCCVID

GND

GND

F32

B32

VTT

AF34

AB34

VCCVID

VCCVID

GND

GND

AH34

AD34

X34

T34

VCCVID

VCCVID

GND

GND

Z34

V34

P34

K34

VCCVID

VCCVID

GND

GND

R34

M34

F34

B34

VCCVID

VCCVID

GND

GND

H34

D34

AH36

B22

VCCVID

VCCVID

GND

V36

R36

VCCVID

VCCVID

GND

X36

T36

H36

D36

VCCVID

VCCVID

GND

GND

P36

K36

D32

AD32

VCCVID

VCCVID

GND

GND

F36

A37

AH24

F14

VCCVID

VCCVID

GND

GND

AC33

Y37

VCCVID

K32

AA37

VCCVID

VCCVID

GND

2

Y35

VCCVID

VCCVID

2

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8

HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35

VID0
VID1
VID2
VID3

GND/VID4

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#

VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5
VTT1_5

Document:
Page Name:

Last Revised:

AK8
AH12
AH8
AN9
AL15
AH10
AL9
AH6
AK10
AN5
AL7
AK14
AL5
AN7
AE1
Z6
AG3
AC3
AJ1
AE3
AB6
AB4
AF6
Y3
AA1
AK6
Z4
AA3
AD4
X6
AC1
W3
AF4

AL35
AM36
AL37
AJ37
AK36
AK18
AH16
AH18
AL19
AL17
C33
C31
A33
A31
E31
C29
E29
A29

AH20
AK16
AL21
AN11
AN15
G35
AL13
U37
U35
S37
S33
E23
AN21
AA35
AA33

HA#[3..31]

HD#[0..63]

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

VTT

HA#[3..31] 7

HD#[0..63] 7

VCC3_3

R371
10K

135

HREQ#0 7
HREQ#1 7
HREQ#2 7
HREQ#3 7
HREQ#4 7

642

RP3

7 8

10K/8P4R

R372 1k

RP4

1
3
5
7 8

Intel(R) 815E Chipset Universal Socket 370 CRB
370-pin Socket Part 1

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

1

1

1K/8P4R

JPR_VID0 29,32

2

JPR_VID1 29,32

4

JPR_VID2 29,32

6

JPR_VID3 29,32
JPR_VID4 29,32

Revision:

1.05

Page No:

333

of

5

a

No-stuff R199 - see p.33.

VTT VCC2_5

D D

DBRESET#25

C C

N639540333

B B

Stuff resistor
only on non-UMB
platforms.

A A

R315 0

ITPCLK6

ITPRDY#5

1k

Rds_on approx. 100
mOhm @5Vgs

R342 1k

FDN335N

VTTPWRGD26

APICD012
APICD112

APICCLK_CPU6

CPUHCLK6

CPU_PWGD12,33

CPURST#7,33

R406

TUAL56,7,26

ITP_DBRESET

VTT

Q27

5

R314

1K
ITP_VTT

J2

2 1
4 3
6 5

8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29

XHEADER_15X2

ITP_CPURESET

R319

243,1%

R346

1k

21
43
65
87
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29

PR6

150,1%

VCC2_5

R373330

PR4
150,1%

MC7

4.7UF

R199

1.8k

R15

150

BC7

0.1UF

4

Stuff either R5 or R415. See p33.

R5

R6

R13

R14

39

39

330

150

R317 0

R318 243,1%

VTT

R33

90.9,1%

R345 1k

R275

22
C12
10PF

4

Do Not stuff C

Place Site w/in 0.5"
of clock pin (W37)

C3
X18PF

R7

150

R316 0

VTT

AG1_VTT/NC

R8

330

VTT

R374

14

NCHCTRLP

R340

1k
DYN_OE

RESET2#

AN35
AN37
AN33

AL33

AK32

AM2
W35

AN3
AK4

W37

AK26

AH4

AG1

A35
G33

E37
C35
E35

N33
N35
N37
Q33
Q35
Q37

F10

G37
AL1

Y33

AJ3

C37

J37

Y1
R2

L33

X2

J35
L35
J33

X4

3

BC1

R9

Debug sites only.

1 2

C163

0.1uF

BC18

0.1UF

VTT

AB36

AD36

Z36

V1_5

V_CMOS

Part2

VTT

GTLREFA

BC17

0.1UF

0.1UF

680

U3B
TDI

TDO
TRST#
TCK
TMS

PREQ#
PRDY#

BP2#
BP3#
BPM0#
BPM1#

370 - Pin Socket

RSRVD6
RSRVD7
RSRVD8
RSRVD9
RSRVD10
RSRVD11

RSRVD13
RSRVD15
RSRVD16
RSRVD17
RSRVD18
RSRVD19
RSRVD20
RSRVD21

RESVD21(BR1#)
DYN_OE

VTTPWRGD
PICD0
PICD1
PICCLK
BCLK
CLKREF
PWRGOOD
RESET#
RESET2#
RSVD - NC
EDGCTRL/VRSEL

CPUPRES#

Socket 370_9

FB30BEAD

PR7

75,1%

PR8

150,1%

3

GTLREFA

CMOSREF

E33

F18K4R6V6AD6

AK12

AK22

BNR#

V2_5

VREF0

VREF1

VREF2

VREF3

VREF4

VREF5

VREF6

VREF7

BPRI#

TRDY#

DEFER#

LOCK#
DRDY#

HITM#

HIT#

DBSY#

ADS#

FLUSH#

BSEL0#
BSEL1#

RSRVD12/JBSEL1#

BR0#
THRMDP
THRMDN

THERMTRIP#

A20M#

STPCLK#

SLP#

SMI#

LINT0/INTR

LINT1/NMI

INIT#

FERR#

IGNNE#

IERR#

PLL1
PLL2

RSP#

AP0#

AP1#

BINIT#
AERR#
BERR#

TUALDET

SLEWCNTR

RTTCNTR

VCOREDET

RP#

GTLREF Generation Circuit

Use 0603 Packages and distribute
GTLREF Inputs ( 1 cap for every 2 inputs )
within 500 mils of processor

GTLREFA 32

GTLREF 7,32

GTLREFA to CPU.
GTLREF to GMCH.

BC16

0.1UF

R330 X0
Do not stuff R330
BC12

0.1UF

2

AH14
AN17
AN25
AN19
AK20
AN27
AL23
AL25
AL27
AN31
AE37

AJ33
AJ31
AK30

AN29
AL31
AL29
AH28

AE33
AG35
AH30
AJ35
M36
L37
AG33
AC35
AG37
AE35

W33
U33

AC37
AL11
AN13
AN23

B36
AK24
V4
AF36
E27
S35
E21

2

FLUSH#

PLL1
PLL2

TUALDET
SLEWCNTR
RTTCNTR

Document:
Page Name:

Last Revised:

BSEL#10BSEL#0

0
10
1

V3SB

R2

R1

150

150

33uF (C size)

+

C6

Debug only!
R375 0

PR1

PR5

56,%1

110,%1

V3SB

R3
1K

VTT

FSB
66M

0

100M

1

rsvd

1 133M

R4

150 1%

1K

L2

4.7UH/SMD-0805

R344

1k

JP6

JUMPER

R338

75 1%

R339

BNR# 7
BPRI# 7
HTRDY# 7
DEFER# 7
HLOCK# 7
DRDY# 7
HITM# 7
HIT# 7
DBSY# 7
HADS# 7

BSEL#0 29,32
BSEL#1 29,32

BR0# 5
VTIN2 21,25
THRMDN 21,25
THERMTRIP# 33

A20M# 12
STPCLK# 12
CPUSLP# 12
SMI# 12
INTR 12
NMI 12
INIT# 12,17
FERR# 12
IGNNE# 12

VCCVID

VCC5

Q26
2N3904

Debug only! Do NOT place
jumper before removing
R375

Intel(R) 815E Chipset Universal Socket 370 CRB
370-pin Socket Part 2

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

VCMOS

CMOSREF generation circuitPlace near AB36

R343

2.2k

1

BC228

0.1uF

1

CMOSREF

VCC5

Q25
2N7002

TUAL5#

Revision:

Page No:

433

R341

2.2k

TUAL5 6,7

1.05

of

Tu

5

D D

4

3

2

1

BC22

0.1UF

VTT

R12 150

BC9

0.1UF

BC15

0.1UF

ITPRDY# 4

BC2

0.1UF

BC13

0.1UF

BC3

0.1UF

R23 56

C C

VTT

MC23

MC22

BC34

BC35

BC36

BC37

BC38

BC24

0.1UF

0.1UF

0.1UF

0.1UF

4.7UF

4.7UF

VTT

Do not populate in assembly - debug sites only.
Debug cap sites - place near processor

C164

B B

820uF

0.1UF

0.1UF

BC23

0.1UF

BC5

0.1UF

BR0# 4

BC14

0.1UF

VTT Decoupling

A A

Document:
Page Name:

Last Revised:

5

4

3

2

Intel(R) 815E Chipset Universal Socket 370 CRB
VTT Decoupling

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

1

Revision:

1.05

Page No:

533

of

A

VCC_CLOCK

VCC_CLOCK

4 4

VCC2_5

1 2

PFB5

1 2

BEAD

1 2

PFB4

BEAD

PFB11

BEAD

BC56

0.1UF

4.7UF

MC21

4.7UF

MC28

BC25

0.1UF

BC55

0.01UF

MC29

4.7UF

BC26

0.01UF

FMOD129

ICH_CLK1413

ICH_3V6613
GMCH_3V668
AGPCLK_CONN11

3 3

PCLK_0/ICH12

R60 10

FMOD029

SLP_S3#13,21,28
R_SMBCLK32
R_SMBDATA32

C41

C40

C39

C29

X10PF

X10PF

X10PF

X10PF

VCC3_3

Q29

VTTPWRGD1226

2 2

Clock powe r g ate

FDN359AN

VCC_CLOCK

VCC3_3

1 2

Rds_on = 100 mOhm.

MEMCLK0
MEMCLK1
MEMCLK2
MEMCLK3 MEMCLK7

1 1

246

246

135

135

A

MEMCLK4
MEMCLK5
MEMCLK6

CN4
X10P/8P4C

78

7 8

246

246

135

135

BC62

BC61

0.01UF

0.1UF

C42

X10PF

PFB12

BEAD

CN5
X10P/8P4C

78

7 8

B

BC57

0.01UF

C35

18PF

C33

18PF

MC66

4.7UF

MEMCLK8
MEMCLK9
MEMCLK10
MEMCLK11

B

BC59

BC58

0.01UF

0.1UF

Y3

14.318MHZ

R64 33
R65 33
R66 33

R67 33
R290 33

R72 10

BC222

BC221

0.01UF

0.1UF

C34

X10PF

AV3 USBV3

R249 8.2K

BC60

0.1UF

L_VCC2_5

25914202531

56

U6

VDD

VDD

VDDL

VDDL

6

X1

7

X2

4

REF0

10

3V66-0

11

3V66-1

12

3V66-2

15

PCICLK0

16

PCICLK1

18

FS0

28

FS1

21

PD#

22

SCLK

23

SDATA

GNDL

GNDL

GND

GND

GND

3558131719243034

R303

C31

X10PF

R302
10K

C23

X10PF

10K

PCLK_REF

C22

X10PF

4

13

9
8

1 6

5

12

Ensure that the bu f f e r u s e d w ill d isab le
its PLL and trist a t e output s w hen no
refclk is present; othe r w is e , m u s t g a t e
power here, too.

C

35

404449

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDDA

CPUCLK_0
CPUCLK_1

IOAPIC

SDRAM0
SDRAM1
SDRAM2
SDRAM3

SDRAM4
SDRAM5
SDRAM6
SDRAM7

SDRAM8

SDRAM9
SDRAM10
SDRAM11

SDRAM12

48MHZ_0
48MHZ_1

GND

GND

GND

GND

GND

GND

GND

GND

39

434852

U29

VDD
VDD

CLKA1
CLKA2
CLKA3

FS1

CLKA4

FS2
REF CLKB1

CLKB2
CLKB3
CLKB4

CLKOUT

GND
GND

ICS9112B-17

C

MEMV3PCIV3

BC226

0.01UF

54
53
1

51
50
47
46

45
42
41
38

37
36
33
32

29

26
27

ICS9250-28

2
3
14
15

7
10
11

16

BC227

0.1UF

BC28

0.01UF

BC27

0.1UF

RN34

7
5
3
1

33/8P4R
R277 33
R312 X33

BC29

BC30

0.01UF

0.1UF

R320 33
R46 33
R45 33
R57 33
R58 33

7

8

5

6

3

4

1

2

RN19 22/8P4R

7

8

5

6

3

4

1

2
RN20 22/8P4R
R50 22
R51 22
R62 22
R63 22

R44 22

R48 33
R49 33

R47 33

8

6

4

2

X10P/8P4C

C132

X18PF

BC33

0.01UF

CN6

C19

X10PF

BC21

0.1UF

C21

X10PF

246

246

135

135

D

BC32

0.01UF

BC63

BC64

0.01UF

0.1UF

C20

C133

X10PF

X10PF

C120

X10PF

78

7 8

D

BC31

0.1UF

4.7UF

MC20

4.7UF

4.7UF

C25

C24

X10PF

X10PF

Document:
Page Name:

Last Revised:

E

PFB2

1 2

MC18

1 2

MC19

BEAD

PFB1

BEAD

VCC_CLOCK

VCC_CLOCK

R347

R348

0

130

2N7002

MEMCLK0
MEMCLK1
MEMCLK2
MEMCLK3

MEMCLK4
MEMCLK5
MEMCLK6
MEMCLK7

MEMCLK8
MEMCLK9
MEMCLK10
MEMCLK11

Q28

APICCLK_CPU 4

ITPCLK 4
CPUHCLK 4
GMCHHCLK 7

APICCLK_ICH 12

DCLK_WR 7

USBCLK 13
DOTCLK 8

SIO_CLK24 21

C28

X10PF

C30

X10PF

MEMCLK[0..7]
MEMCLK[8..11]

MEMCLK[0..7] 9
MEMCLK[8..11] 10

PCLK_1 14
PCLK_2 14
PCLK_3 15
PCLK_7 21

PCLK_8 17

Intel(R) 815E Chipset Universal Socket 370 CRB
Clock Generator

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

TUAL5 4,7,26

Revision:

1.05

Page No:

633

of

5

Debug sites only.

VTT

1 2

FB31BEAD

GTLREF

2

D D

HADS#

R407

Place
near GMCH

56

VTT

C C

B B

A A

HA#[3..31]3

0.1uF

C168

PR43

150,1%

HREQ#03
HREQ#13
HREQ#23
HREQ#33
HREQ#43

RS#03
RS#13
RS#23

PR42

63.4 1%

BC72

0.1UF

GMCHHCLK6

PCIRST#16,17,21,30
CPURST#4,33
HLOCK#4
DEFER#4

BNR#4
BPRI#4
DBSY#4
DRDY#4
HIT#4
HITM#4
HTRDY#4

HA#[3..31]

5

Place close
to GMCH

BC73

0.1UF

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

RS#0
RS#1
RS#2

Do Not Stuff C
Place Site w/in

0.5" of clock
ball(v6)

VTT

U7A

R61

90.9,1%

U6

GTLREFA

AA10

GTLREFB

AA7

HCLK

H3

AA5

M3
G1
N4
M5

R4

R3
N5

R1
U1

R5

W1
U4

W3
W4
U5

U3
W5

M1
N1
M2

N3

H1

C38
X18PF

L4

J3
J1
K1
L3
K3

P1
T2

P5

P2
T1
T3
P3
T5

V5
Y2
V3

V2

Y5
Y3

Y1
V1

L5

K2
L1

RESET#
CPURST#
HLOCK#
DEFER#
ADS#
BNR#
BPRI#
DBSY#
DRDY#
HIT#
HITM#
HTRDY#

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

RS#0
RS#1
RS#2

Host Interface

HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9

AA1
AB2
AF2
AD4
AB1
AB3
AA3
AC4
AC1
AF3
AD1
AE3
AD2
AD3
AF1
AA4
AD6
AC3
AE1
AB6
AF4
AE5
AC8
AB5
AF5
AC6
AF6
AD11
AF8
AD8
AD5
AB7
AF7
AD7
AB8
AE7
AE9
AB9
AF9
AD10
AF12
AB11
AB10
AD9
AC10
AF10
AD14
AD12
AB12
AE11
AE15
AF11
AF13
AB14
AF14
AB13
AB15
AE13
AC14
AD13
AD15
AF16
AF15
AC12

4

HD#[0..63]

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

4

HD#[0..63] 3

SM_MAC#[4..7]10

SM_MAA[0..12]9,10

SM_DQM[0..7]9,10

SM_CKE[0..3]9
SM_CKE[4..5]10
SM_CSA#[0..3]9
SM_CSA#[4..5]10
SM_CSB#[0..3]9
SM_CSB#[4..5]10

SM_BS09,10
SM_BS19,10

SM_RAS#9,10
SM_CAS#9,10
SM_WE#9,10

DCLK_WR6

VCC3SBY

3

SM_MAC#[4..7]
SM_MAB#[4..7]
SM_MAA[0..12]
SM_MAA0

SM_MAA1
SM_MAA2
SM_MAA3
SM_MAA4
SM_MAA5
SM_MAA6
SM_MAA7
SM_MAA8
SM_MAA9
SM_MAA10
SM_MAA11
SM_MAA12

RN38 10/8P4R
SM_MAB#4
SM_MAB#5
SM_MAB#6
SM_MAB#7

SM_MAC#4
SM_MAC#5
SM_MAC#6
SM_MAC#7

RN36 10/8P4R

SM_CSA#0
SM_CSA#1
SM_CSA#2
SM_CSA#3
SM_CSA#4
SM_CSA#5

SM_CSB#0
SM_CSB#1
SM_CSB#2
SM_CSB#3
SM_CSB#4
SM_CSB#5

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CKE4
SM_CKE5

SM_DQM[0..7]
SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7

PR9 40.2,1%

SM_CKE[0..3]
SM_CKE[4..5]
SM_CSA#[0..3]
SM_CSA#[4..5]
SM_CSB#[0..3]
SM_CSB#[4..5]

3

1
3
5
7

1
3
5
7

1
3
5
7

RN37

10/8P4R

C36
22PF

2

SM_MD[0..63]

U7B

D13

SMAA0

B16

SMAA1

F12

SMAA2

A16

SMAA3

2

B12

SMAA4

4

A12

SMAA5

6

C11

SMAA6

8

A11

SMAA7

D12

SMAA8

C13

SMAA9

E11

SMAA10

A13

SMAA11

B7

SMAA12

2

B15

SMAB#4

4

A15

SMAB#5

6

C14

SMAB#6

8

A14

SMAB#7

2

B10

SMAC4

4

A10

SMAC5

6

C10

SMAC6

8

A9

SMAC7

B13

SBS0

D11

SBS1

D15

SCSA#0

A17

SCSA#1

D14

SCSA#2

E14

SCSA#3

E13

SCSA#4

B17

SCSA#5

F9

SCSB#0

F8

SCSB#1

D10

SCSB#2

D9

SCSB#3

B9

SCSB#4

A8

SCSB#5

C16

SRAS#

D18

SCAS#

E16

SWE#

D8

SCKE0

E8

SCKE1

E9

SCKE2

D7

SCKE3

C8

SCKE4

C7

SCKE5

F7

SCLK

G10

RESVD

D16

SDQM0

F15

SDQM1

A7

SDQM2

A6

SDQM3

A18

SDQM4

C17

SDQM5

B6

SDQM6

A5

SDQM7

G7

SRCOMP

82815 GMCH

SYSTEM MEMORY

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SMD8

SMD9
SMD10
SMD11
SMD12
SMD13
SMD14
SMD15
SMD16
SMD17
SMD18
SMD19
SMD20
SMD21
SMD22
SMD23
SMD24
SMD25
SMD26
SMD27
SMD28
SMD29
SMD30
SMD31
SMD32
SMD33
SMD34
SMD35
SMD36
SMD37
SMD38
SMD39
SMD40
SMD41
SMD42
SMD43
SMD44
SMD45
SMD46
SMD47
SMD48
SMD49
SMD50
SMD51
SMD52
SMD53
SMD54
SMD55
SMD56
SMD57
SMD58
SMD59
SMD60
SMD61
SMD62
SMD63

D23
C23
D22
F21
E21
G20
F20
D20
F19
E19
D19
E18
B18
F18
G18
D17
A3
A1
C1
F2
G3
D6
C5
B4
D4
C2
D3
E4
F5
G4
J6
K5
A26
A25
B24
A24
B23
A23
C22
A22
D21
B21
A21
C20
B20
A20
C19
A19
A4
A2
B1
E1
G2
E6
D5
C4
B3
D2
E3
F4
F6
G5
H4
J4

SM_MD[0..63] 9,10SM_MAB#[4..7]9

SM_MD0
SM_MD1
SM_MD2
SM_MD3
SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8
SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13
SM_MD14
SM_MD15
SM_MD16
SM_MD17
SM_MD18
SM_MD19
SM_MD20
SM_MD21
SM_MD22
SM_MD23
SM_MD24
SM_MD25
SM_MD26
SM_MD27
SM_MD28
SM_MD29
SM_MD30
SM_MD31
SM_MD32
SM_MD33
SM_MD34
SM_MD35
SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40
SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45
SM_MD46
SM_MD47
SM_MD48
SM_MD49
SM_MD50
SM_MD51
SM_MD52
SM_MD53
SM_MD54
SM_MD55
SM_MD56
SM_MD57
SM_MD58
SM_MD59
SM_MD60
SM_MD61
SM_MD62
SM_MD63

Document:
Page Name:

Last Revised:

BC188
X0.1UF

Backside decouping , should be
placed under chipset memory signal
field

BC192
X0.1UF

Backside decouping , should be
placed under chipset AGP signal
field

SM_MAA12

TUAL54,6,26

SM_WE#

R90 8.2K
R89 8.2K

SM_MAA9

R88 10K

R68 X10K

R77 X10K

Host Freq : HI=100 LO=66
FSB P-MOS Kicker : HI=NON-Cu LO=Cu
Host Freq : HI=133 LO=100/66
LM FREQ : HI=133 LO=100

SM/LM muxing strap , active low
ALLZ : LO=ALLZ HI=Normal
IOQ depth : HI=4 LO=1
LO = Future 0.13u Socket 370 processors
HI = Pentium(R) III Processor or Intel(R)

Celeron(tm) Processor w/CPUID = 068Xh

XOR chain : LO=XOR HI=Normal

SM_WE#
SM_MAA9
SM_CAS#
SBA7
SM_BS0
SM_BS1
SM_MAA10
SM_MAA11
SM_MAA12

SM_RAS#

SM_CAS#

Intel(R) 815E Chipset Universal Socket 370 CRB
GMCH Part 1

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

2

BC190
X0.1UF

BC193
X0.1UF

1

BC191
X0.1UF

BC194
X0.1UF

SM_MAA10

SM_RAS#

1

VCC3SBY

BC189
X0.1UF

VDDQ

BC195
X0.1UF

R349
10k

Q30
2N7002

R_BSEL#0 29
R_REFCLK 29

Revision:

Page No:

733

1.05

of

5

4

3

2

1

SBA[0..7]
HL[0..10]

GAD[0..31]

PR15

40.2,1%

CONN_AGPREF11,32

GAD[0..31]11

GCBE#011
GCBE#111
GCBE#211
GCBE#311

GFRAME#11
GDEVSEL#11
GIRDY#11
GTRDY#11
GSTOP#11
GPAR11
GREQ#11
GGNT#11
PIPE#11

ADSTB011
ADSTB0#11
ADSTB111
ADSTB1#11
SBSTB11
SBSTB#11

ST011
ST111
ST211

RBF#11
WBF#11

PR14 15.1%

BC89

0.1UF

NOTE :

5

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GRCOMP

OCLK
RCLK

OCLK = 0.5"
RCLK = 1.5"

K26

J22

K25

J21

L24

J20
L26
K23
K22

M25
M24
M26
M21
N24
N22
N26

T26
T22

U24

T23

U26

T24
V24

U21

V25
V21
V26

W21
W24
W22
W26

Y21

H23
N21

T25
Y26

R26

P26
P23
P21
P25

R24
AE26
AD25
AC26

M22

L23

U22

V23
Y23

AA24
AD24

AC24
AC23

AD26
AB24

J24
J26

R22

P22
C61
15PF/5%,MPO

D D

C C

B B

A A

U7C

GAD0/LDQM0
GAD1/LMD4
GAD2/LMD7
GAD3/LMD3
GAD4/LMD6
GAD5/LMD2
GAD6/LMD5
GAD7/LMD1
GAD8/LMD0
GAD9/LMA4
GAD10/LDQM1
GAD11/LMA2
GAD12/LMD8
GAD13/LMA5
GAD14/LMD9
GAD15/LMA1
GAD/16/LMA8
GAD17/LMD14
GAD18/LMA11
GAD19/LMD15
GAD20/LMA9
GAD21/LMD16
GAD22/LCS#
GAD23/LMD17
GAD24/LCKE
GAD25/LMD18
GAD26/LCAS#
GAD27/LMD19
GAD28/LTCLK1
GAD29/LMD20
GAD30/LTCLK0
GAD31/LMD21

GCBE#0/LMA3
GCBE#1/LMD10
GCBE#2/LMD13
GCBE#3/LRDS#

GFRAME#/LMA10
GDEVSEL#/LMD11
GIRDY#/LMD12
GTRDY#/LMA7
GSTOP#/LMA0
GPAR/LMA6
GREQ#/LMD27
GGNT#
PIPE#/LMD24

ADSTB0
ADSTB0#
ADSTB1
ADSTB1#
SBSTB
SBSTB#

ST0/LMD28
ST1/LDQM3
ST2/LMD29

RBF#/LMD30
WBF#
AGPREF
GRCOMP
OCLOCK
RCLOCK

82815 GMCH

Display Cache, Video, and
HUB Interface

LTVDATA0
LTVDATA1
LTVDATA2
LTVDATA3
LTVDATA4
LTVDATA5
LTVDATA6
LTVDATA7
LTVDATA8

LTVDATA9
LTVDATA10
LTVDATA11

BLANK#

TVCLKIN/SL_STALL

CLKOUT0

CLKOUT1
TVVSYNC
TVHSYNC

DCLKREF

IWASTE

HUBREF

HLSTB#
HCOMP

SBA0/LMD31
SBA1/LMD25

SBA2/LDQM2

SBA3/LMD26
SBA4/LMD23

SBA5/LWE#

SBA6/LMD22

SBA7/LGM_FREQ_SEL

LTVCK
LTVDA

DDDA
DDCK

IREF

VSYNC
HSYNC

RED

GREEN

BLUE
HCLK

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9

HL10

HLSTB

AD16
AF17
AE17
AD17
AF18
AD18
AF20
AD20
AC20
AF21
AE21
AD21
AB19
AC18
AE19
AF19
AC16
AB17

AB21
AA20

AA18
AB18

AE24
Y20
AD23

AF22
AF23
AD22
AE22
AE23

F22
H24
H26
H25
G24
F24
E26
E25
D26
D25
D24
C26
H21
G25
F26
H20

AB22
AB25
AB23
AB26
AA22
AA26
Y22
Y25

PR13
174,1%

4

FTD[0..11]

R251 22

Place as close as
Possible to GMCH
and via straight
to VSS plane

FTD0
FTD1
FTD2
FTD3
FTD4
FTD5
FTD6
FTD7
FTD8
FTD9
FTD10
FTD11

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HUBREF_GMCH

HCOMP

SBA[0..7] 11
HL[0..10] 12
FTD[0..11] 16

VCC1_8

L6 22nH

FTBLNK# 16
SL_STALL 16
FTCLK0 16
FTCLK1 16
FTVSYNC 16
FTHSYNC 16

3VFTSCL 16
3VFTSDA 16

3VDDCDA 16
3VDDCCL 16

DOTCLK 6

CRT_VSYNC 16
CRT_HSYNC 16
VID_RED 16
VID_GREEN 16
VID_BLUE 16

GMCH_3V66 6

HLSTB 12
HLSTB# 12

SBA0 11
SBA1 11
SBA2 11
SBA3 11
SBA4 11
SBA5 11
SBA6 11
SBA7 11

C169

33uF

0.1uF

C58
10PF

Do Not Stuff C
Place Site w/in 0.5"
of clock ball(AA21)

VCC1_8

Place R as

PR18

Close as
possible to
GMCH

40.2,1%

Place as close as
Possible to GMCH
and via straight
to VSS plane

C170

BC90

0.1UF

3

0.01uF

VCC1_8

C171

PR16
301,1%

PR17
301,1%

VCC1_8VCC3SBYVDDQ

W6

Y18
AA6
AA8

AA11
AA13
AA15
AA17
AA19
AB16
AB20
AC22
AD19

C25

E24

F23
G22

M6

G26

AA21

E23

AF26
AF25

B11

B14

B19

B22

B25

F10

F14

F17

G6
G8

G19

H2
H5
H7

K20

Y24

L21
M23

U25

N25

R21

U20

U23
W20

AF24
AE25

U7D

VCC_1.8

Y9

VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8
VCC_1.8

J7

VCC_1.8

K6

VCC_1.8
VCC_1.8

P6

VCC_1.8

T6

VCC_1.8

V7

VCC_1.8
VCC_1.8

VCC1_8

Y7

VCC1_8
VCC1_8
VCC1_8
VCC1_8

B2

VCC3SBY

B5

VCC3SBY

B8

VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY

E2

VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY
VCC3SBY

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

GND
GND

82815 GMCH

Power and Ground

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

2

AB4
E7
AC2
AC5
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC25
AE2
AE4
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
B26
C3
C6
C9
C12
C15
C18
C21
C24
D1
E5
E10
E12
E15
E17
E20
E22
F1
F3
F11
F13
T21
U2
U7
K24
V4
V6
V20
V22
W2
W7
W23
W25
Y4
Y6
Y8
Y10
Y17
Y19
AA2
AA9
AA12
AA14
AA16

Document:
Page Name:

Last Revised:

U7E

PR21
82,1%

PR24
82,1%

M11
M12
M13
M14
M15
M16

P11
P12
P13
P14
P15
P16

R11
R12
R13
R14
R15
R16
R23
R25

T11
T12
T13
T14
T15
T16
L15
L16
L22

L25

R2
R6

T4

M4

560PF

560PF

C69

C72

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

Solano

VDDQ

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

PR23
1K,1%

GMCH_AGPREF 11

PR22
1K,1%

N2
N6
N11
N12
N13
N14
N15
N16
N23
AA23
F16
F25
G9
G17
G21
G23
P24
H6
H22
J2
J5
J23
J25
K4
K7
K21
L2
L6
L11
L12
L13
L14
AA25
P4

Intel(R) 815E Chipset Universal Socket 370 CRB
GMCH Part 2

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

1

Revision:

1.05

Page No:

833

of

A

DIMM1

1
SM_MD0
SM_MD1
SM_MD2
SM_MD3

SM_MD4

4 4

3 3

2 2

1 1

SM_MD5
SM_MD6
SM_MD7
SM_MD8

SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13

SM_MD14
SM_MD15

SM_WE#
SM_DQM0
SM_DQM1
SM_CSA#0

SM_MAA0
SM_MAA2 SM_MAA2
SM_MAA4
SM_MAA6
SM_MAA8
SM_MAA10
SM_BS1

MEMCLK0

SM_CSB#0
SM_DQM2
SM_DQM3

SM_MD16
SM_MD17
SM_MD18
SM_MD19

SM_MD20

SM_CKE1
SM_MD21

SM_MD22
SM_MD23

SM_MD24
SM_MD25
SM_MD26
SM_MD27

SM_MD28
SM_MD29
SM_MD30
SM_MD31

MEMCLK2

SMBDATA
SMBCLK

A

2

3

4

5

6

7

8

9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VDD
WE#/WE0#
DQM0
DQM1
CS0#
DU/OE0#
VSS
A0
A2
A4
A6
A8
A10/AP
BA1/A12
VDD
VDD
CLK0/DU
VSS
DU/OE2#
CS2#
DQM2
DQM3
DU/WE2#
VDD
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
VREF/DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2/NC
NC
WP
SDA
SCL
VDD

DIMM168

VSS
DQ32
DQ33
DQ34
DQ35

VDD
DQ36
DQ37
DQ38
DQ39
DQ40

VSS
DQ41
DQ42
DQ43
DQ44
DQ45

VDD
DQ46
DQ47

CB4
CB5

VSS
CB12
CB13

VDD

CAS#/DU

DQM4
DQM5

CS1#

RAS#/DU

VSS

BA0/A11
A11/A13

VDD

CLK1/DU

A12/DU

VSS

CKE0/DU

CS3#

DQM6
DQM7

A13/DU

VDD
CB14
CB15

CB6
CB7

VSS
DQ48
DQ49
DQ50
DQ51

VDD

DQ52

VREF/DU

REGE

VSS
DQ53
DQ54
DQ55

VSS
DQ56
DQ57
DQ58
DQ59

VDD
DQ60
DQ61
DQ62
DQ63

VSS

CLK3/NC

SA0
SA1
SA2

VDD

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117

A1

118

A3

119

A5

120

A7

121

A9

122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145

NC

146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

NC

165
166
167
168

B

B

SM_MD32
SM_MD34

SM_MD35
SM_MD36

SM_MD37
SM_MD38
SM_MD39
SM_MD40

SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45

SM_MD46
SM_MD47

SM_CAS#
SM_DQM4
SM_DQM5
SM_CSA#1
SM_RAS#

SM_MAA1
SM_MAA3
SM_MAA5
SM_MAA7
SM_MAA9
SM_BS0
SM_MAA11

MEMCLK1
SM_MAA12

SM_CKE0
SM_CSB#1
SM_DQM6
SM_DQM7

SM_MD48
SM_MD49
SM_MD50
SM_MD51

SM_MD52

SM_MD53
SM_MD54
SM_MD55

SM_MD56
SM_MD57
SM_MD58
SM_MD59

SM_MD60
SM_MD61
SM_MD62
SM_MD63

C

VCC3SBY VCC3SBYVCC3SBYVCC3SBY

SM_MD0
SM_MD1SM_MD33
SM_MD2
SM_MD3

SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8

SM_MD9
SM_MD10
SM_MD11 SM_MD43
SM_MD12
SM_MD13

SM_MD14
SM_MD15

SM_WE#
SM_DQM0
SM_DQM1
SM_CSA#2

SM_MAA0
SM_MAB#4

SM_MAB#6
SM_MAA8
SM_MAA10
SM_BS1

MEMCLK4

SM_CSB#2
SM_DQM2
SM_DQM3

SM_MD16
SM_MD17
SM_MD18
SM_MD19

SM_MD20

SM_CKE3
SM_MD21

SM_MD22
SM_MD23

SM_MD24
SM_MD25
SM_MD26
SM_MD27

SM_MD28
SM_MD29
SM_MD30
SM_MD31

MEMCLK6

SMBDATA
SMBCLK

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

DIMM2

VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VDD
WE#/WE0#
DQM0
DQM1
CS0#
DU/OE0#
VSS
A0
A2
A4
A6
A8
A10/AP
BA1/A12
VDD
VDD
CLK0/DU
VSS
DU/OE2#
CS2#
DQM2
DQM3
DU/WE2#
VDD
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
VREF/DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2/NC
NC
WP
SDA
SCL
VDD

DIMM168

C

VSS
DQ32
DQ33
DQ34
DQ35

VDD
DQ36
DQ37
DQ38
DQ39
DQ40

VSS
DQ41
DQ42
DQ43
DQ44
DQ45

VDD
DQ46
DQ47

CB4
CB5

VSS
CB12
CB13

VDD

CAS#/DU

DQM4
DQM5

CS1#

RAS#/DU

VSS

BA0/A11

A11/A13

VDD

CLK1/DU

A12/DU

VSS

CKE0/DU

CS3#

DQM6
DQM7

A13/DU

VDD
CB14
CB15

CB6
CB7

VSS
DQ48
DQ49
DQ50
DQ51

VDD

DQ52

VREF/DU

REGE

VSS
DQ53
DQ54
DQ55

VSS
DQ56
DQ57
DQ58
DQ59

VDD
DQ60
DQ61
DQ62
DQ63

VSS

CLK3/NC

SA0
SA1
SA2

VDD

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117

A1

118

A3

119

A5

120

A7

121

A9

122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145

NC

146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

NC

165
166
167
168

SM_MD32
SM_MD33
SM_MD34
SM_MD35

SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40

SM_MD41
SM_MD42

SM_MD44
SM_MD45

SM_MD46
SM_MD47

SM_CAS#
SM_DQM4
SM_DQM5
SM_CSA#3
SM_RAS#

SM_MAA1
SM_MAA3
SM_MAB#5
SM_MAB#7
SM_MAA9
SM_BS0
SM_MAA11

MEMCLK5
SM_MAA12

SM_CKE2
SM_CSB#3
SM_DQM6
SM_DQM7

SM_MD48
SM_MD49
SM_MD50
SM_MD51

SM_MD52

SM_MD53
SM_MD54
SM_MD55

SM_MD56
SM_MD57
SM_MD58
SM_MD59

SM_MD60
SM_MD61
SM_MD62
SM_MD63

MEMCLK7MEMCLK3

D

D

R28

2.2K

Document:
Page Name:

Last Revised:

E

VCC3SBY

SM_MAA[0..12]
SM_MD[0..63]
SM_MAB#[4..7]
SM_DQM[0..7]
MEMCLK[0..7]
SM_CKE[0..3]
SM_CSA#[0..3]
SM_CSB#[0..3]
SM_WE#
SM_RAS#
SM_CAS#
SM_BS0
SM_BS1

SMBDATA
SMBCLK

DM_SA_PU 10

SM_MAA[0..12] 7,10
SM_MD[0..63] 7,10
SM_MAB#[4..7] 7
SM_DQM[0..7] 7,10
MEMCLK[0..7] 6
SM_CKE[0..3] 7
SM_CSA#[0..3] 7
SM_CSB#[0..3] 7
SM_WE# 7,10
SM_RAS# 7,10
SM_CAS# 7,10
SM_BS0 7,10
SM_BS1 7,10

SMBDATA 10,13,21,24,30,32
SMBCLK 10,13,21,24,30,32

Intel(R) 815E Chipset Universal Socket 370 CRB
DIMMs 1 and 2

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

933

of

CH6-12

A

SM_MAA[0..12]7,9

SM_MD[0..63]7,9

SM_MAC#[4..7]7

4 4

3 3

2 2

1 1

SM_DQM[0..7]7,9

MEMCLK[8..11]6

SM_CKE[4..5]7

SM_CSA#[4..5]7

SM_CSB#[4..5]7

SM_WE#7,9
SM_RAS#7,9

SM_CAS#7,9

SM_BS07,9

SM_BS17,9

SMBDATA9,13,21,24,30,32
SMBCLK9,13,21,24,30,32

DM_SA_PU9

A

SM_MAA[0..12]
SM_MD[0..63]

SM_MAC#[4..7]

SM_DQM[0..7]

MEMCLK[8..11]

SM_CKE[4..5]

SM_CSA#[4..5]

SM_CSB#[4..5]
SM_WE#
SM_RAS#
SM_CAS#
SM_BS0
SM_BS1

SMBDATA
SMBCLK

SM_MD0
SM_MD1
SM_MD2
SM_MD3

SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8

SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13

SM_MD14
SM_MD15

SM_WE#
SM_DQM0
SM_DQM1
SM_CSA#4

SM_MAA0
SM_MAA2
SM_MAC#4
SM_MAC#6
SM_MAA8
SM_MAA10
SM_BS1

MEMCLK8

SM_CSB#4
SM_DQM2
SM_DQM3

SM_MD16
SM_MD17
SM_MD18
SM_MD19

SM_MD20

SM_CKE5
SM_MD21

SM_MD22
SM_MD23

SM_MD24
SM_MD25
SM_MD26
SM_MD27

SM_MD28
SM_MD29
SM_MD30
SM_MD31

MEMCLK10

SMBDATA
SMBCLK

B

VCC3SBY VCC3SBY

B

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

DIMM3

VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VDD
WE#/WE0#
DQM0
DQM1
CS0#
DU/OE0#
VSS
A0
A2
A4
A6
A8
A10/AP
BA1/A12
VDD
VDD
CLK0/DU
VSS
DU/OE2#
CS2#
DQM2
DQM3
DU/WE2#
VDD
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
VREF/DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CLK2/NC
NC
WP
SDA
SCL
VDD

DIMM168

DQ32
DQ33
DQ34
DQ35

VDD
DQ36
DQ37
DQ38
DQ39
DQ40

DQ41
DQ42
DQ43
DQ44
DQ45

VDD
DQ46
DQ47

CB12
CB13

VDD

CAS#/DU

DQM4
DQM5

CS1#

RAS#/DU

BA0/A11

A11/A13

VDD

CLK1/DU

A12/DU

CKE0/DU

CS3#
DQM6
DQM7

A13/DU

VDD
CB14
CB15

DQ48
DQ49
DQ50
DQ51

VDD

DQ52

VREF/DU

REGE

DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59

VDD

DQ60
DQ61
DQ62
DQ63

CLK3/NC

VDD

VSS

VSS

CB4
CB5
VSS

VSS

VSS

CB6
CB7
VSS

VSS

VSS

VSS

SA0
SA1
SA2

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117

A1

118

A3

119

A5

120

A7

121

A9

122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145

NC

146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

NC

165
166
167
168

C

SM_MD32
SM_MD33
SM_MD34
SM_MD35

SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40

SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45

SM_MD46
SM_MD47

SM_CAS#
SM_DQM4
SM_DQM5
SM_CSA#5
SM_RAS#

SM_MAA1
SM_MAA3
SM_MAC#5
SM_MAC#7
SM_MAA9
SM_BS0
SM_MAA11

MEMCLK9
SM_MAA12

SM_CKE4
SM_CSB#5
SM_DQM6
SM_DQM7

SM_MD48
SM_MD49
SM_MD50
SM_MD51

SM_MD52

SM_MD53
SM_MD54
SM_MD55

SM_MD56
SM_MD57
SM_MD58
SM_MD59

SM_MD60
SM_MD61
SM_MD62
SM_MD63

MEMCLK11

C

D

D

Document:
Page Name:

Last Revised:

E

Intel(R) 815E Chipset Universal Socket 370 CRB
DIMM 3

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

10 33

of

A

B

C

D

E

VCC3_3

VCC5

4 4

1
3
5
7

1
3
5
7

1
3
5
7

1
3
5
7

1
3
5
7

1
3
5
7

1
3
5
7

RN49

8.2K/8P4R
RN48

8.2K/8P4R
RN42

8.2K/8P4R

RN43

8.2K/8P4R
RN44

8.2K/8P4R
RN46

8.2K/8P4R

RN45

8.2K/8P4R

A

GSERR#
GPAR
GPERR#
GDEVSEL#

GFRAME#
GIRDY#
GTRDY#
GSTOP#

GREQ#
GGNT#
ST0
ST1

3 3

2 2

1 1

ST2

RBF#
PIPE#
WBF#

SBA0
SBA1
SBA2
SBA3

SBA7
SBA6

ADSTB0
ADSTB0#
ADSTB1
ADSTB1#

SBSTB#
SBSTB
SBA5
SBA4

VDDQ

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

R3328.2K
R3338.2K
R3348.2K
R3358.2K

2
4
6
8

AGP_OC#18

AGPUSBP18

PIRQ#B14,15,30

AGPCLK_CONN6

GREQ#8

SBSTB8

ADSTB18

GCBE#28
GIRDY#8

GDEVSEL#8

GCBE#18

ADSTB08

GMCH_AGPREF8

GAD[0..31]8

SBA[0..7]8

GREQ# GGNT#
ST0 ST1

ST08

ST2

ST28

RBF#

RBF#8

SBA0 SBA1
SBA2 SBA3

SBSTB SBSTB1#
SBA4 SBA5

SBA6 SBA7

GAD31
GAD29

GAD27
GAD25

ADSTB1 ADSTB1#
GAD23

GAD21
GAD19

GAD17

GIRDY# GFRAME#

GDEVSEL# GTRDY#
GPERR#
GSERR# GPAR

GAD14
GAD12

GAD10
GAD8

ADSTB0 ADSTB0#
GAD7

GAD5
GAD3

GAD1

GAD[0..31]

SBA[0..7]

B

V3SB

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66

AGP1
OVRCNT#

5V_A
5V_B
USB+
GND_K
INTB#
CLK
REQ#/DQ27
VCC3.3_F
ST0/DQ28
ST2/DQ29
RBF#/DQ30
GND_L
RESV_H
SBA0/DQ31
VCC3.3_G
SBA2/DQM2
SB_STB
GND_M
SBA4/DQ23
SBA6/DQ22
RESV
GND_N

3.3VAUX1
VCC3.3_H
AD31/DQ21
AD29/DQ20
VCC3.3_I
AD27/DQ19
AD25/DQ18
GND_O
AD_STB1
AD23/DQ17
VDDQ_F
AD21/DQ16
AD19/DQ15
GND_P
AD17/DQ14
C/BE2#/DQ13
VDDQ_G
IRDY#/DQ12

3.3VAUX2
GND_Q
RESV_K
VCC3.3_J
DEVSEL#/DQ11
VDDQ_H
PERR#
GND_R
SERR#
C/BE1#/DQ10
VDDQ_I
AD14/DQ9
AD12/DQ8
GND_S
AD10/DQM1
AD8/DQ0
VDDQ_J
AD_STB0
AD7/DQ1
GND_T
AD5/DQ2
AD3/DQ3
VDDQ_K
AD1/DQ4
VREF_CG

C

TYPEDET#

RESV_A

GND_A

INTA#

VCC3.3_A

DQM3/ST1

RESV_B

DQ24/PIPE#

GND_B

WBF#

DQ25/SBA1

VCC3.3_B

DQ26/SBA3

SB_STB#

GND_C

WE#/SBA5

M_FREQ_SEL/SBA7

RESV_C

GND_D

RESV_D

VCC3.3_C
TCLK0/AD30
TCLK1/AD28

VCC3.3_D

CAS#/AD26

GND_E

AD_STB1#

RAS#/C/BE3#

VDDQ_A
A0/AD22
A9/AD20

GND_F

A11/AD18

A8/AD16
VDDQ_B

A10/FRAME#

RESV_E

GND_G

RESV_F
VCC3.3_E
A7/TRDY#

CS#/STOP#

PME#
GND_H
A6/PAR

A1/AD15
VDDQ_C
A5/AD13
A2/AD11

GND_I

A4/AD9

A3/C/BE0#

VDDQ_D

AD_STB0#

DQ5/AD6

GND_J
DQ6/AD4
DQ7/AD2

VDDQ_E

DQM0/AD0

VREF_GC

AGP4XU_20

USB-

RST#
GNT#

AD24

VCC12

VCC12

VDDQ

R106

2.2K

A1

12V

A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66

PIPE#
WBF#

GAD30
GAD28

GAD26
GAD24

GAD22
GAD20

GAD18
GAD16

GSTOP#

GAD15
GAD13

GAD11
GAD9

GAD6
GAD4

GAD2
GAD0

TYPEDET# 26
AGPUSBN 18
PIRQ#A 14,15,30

PCI_RST# 14,15,30
GGNT# 8

ST1 8
PIPE# 8
WBF# 8

SBSTB# 8

ADSTB1# 8
GCBE#3 8

GFRAME# 8

GTRDY# 8
GSTOP# 8
PCI_PME# 12,14,15,22

GPAR 8

GCBE#0 8
ADSTB0# 8

CONN_AGPREF 8,32

Document:
Page Name:

Last Revised:

D

VDDQ

Place close
to GMCH

CON_AGPREF

Q13

2N7002

PR20
301,1%

PR19
200,1%

Intel(R) 815E Chipset Universal Socket 370 CRB
AGP

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

11 33

of

CH6-18

5

U12A
82801BA ICH2

AD[0..31]14,15

D D

C C

PCLK_0/ICH6

C101
10PF

NPOP

B B

A A

FRAME#14,15,30
DEVSEL#14,15,30
IRDY#14,15,30
TRDY#14,15,30
STOP#14,15,30
ICHRST#30
PLOCK#14,15,30
PAR14,15
SERR#14,15,30
PERR#14,15,30
PCI_PME#11,14,15,22

PCI_REQ#A30

ICH_IRQ#E30
ICH_IRQ#F30
ICH_IRQ#G30
ICH_IRQ#H30

P66DET17
S66DET17

GPI830
EXTSMI#24
LPC_PME#21,30

GPIO2317

GPIO2730

PRI_DWN#24,29

5

AD[0..31]
AD0

AA4

AD1

AB4

AD2

Y4

AD3

W5

AD4

W4

AD5

Y5

AD6

AB3

AD7

AA5

AD8

AB5

AD9

Y3

AD10

W6

AD11

W3

AD12

Y6

AD13

Y2

AD14

AA6

AD15

Y1

AD16

V2

AD17

AA8

AD18

V1

AD19

AB8

AD20

U4

AD21

W9

AD22

U3

AD23

Y9

AD24

U2

AD25

AB9

AD26

U1

AD27

W10

AD28

T4

AD29

Y10

AD30

T3

AD31

AA10

C_BE#014,15
C_BE#114,15
C_BE#214,15
C_BE#314,15

AA3
AB6

AA9
W11
AB7

AA15

AA7

Y15

Y11

AA11

Y14
W14

AB15

A15
D14
C14

B14

A14
AB14
AA14

Y8

V3

W8

V4

W1

W2
W7

Y7

M3

L2

N3
N2
N1
M4

L1

E14

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C_BE#0
C_BE#1
C_BE#2
C_BE#3

PCICLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PCIRST#
PLOCK#
PAR
SERR#
PERR#
PCI_PME#

REQ#A/GPI0
GNT#A/GPO16

PIRQ#E/GPI2
PIRQ#F/GPI3
PIRQ#G/GPI4
PIRQ#H/GPI5
GPI6
GPI7
GPI8
GPI12
GPI13
GPO18
GPO19
GPO20
GPO21
GPOD22
GPO23
GPIOD27
GPIOD28

VSS0

VSS1

VSS2

A1

A10A2A21

E15

VCC3_3_2

VSS3

A22

E16

VCC3_3_3

VSS4

AA1

E17

VCC3_3_4

VSS5

AA2

VCC3_3_5

VSS6

E18

AA21

F18

VCC3_3_6

VSS7

AA22

G18

VCC3_3_7

VSS8

AB1

VCC3_3_8

VSS9

AB2

VSS10

H18

VCC3_3_10

VSS11

AB21

4

J18

P18

R18R5T5U5V5

V6V7V8

VCC3_3_11

VCC3_3_12

VCC3_3_13

VCC3_3_14

VCC3_3_15

VCC3_3_16

VCC3_3_17

VCC3_3_18

VCC3_3_19

VCC3_3_20

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

AB22B1B10B2B21

B22B3B9C2C3C4C9D3D5D6D7D8D9E6E7E8E9

4

VSS23

D10E5K19

VCC1_8_1

VSS24

VCC1_8_2

VSS25

L19P5V9

VCC1_8_3

VSS26

VCC1_8_4

VSS27

VCC1_8_5

VSS28

VCC1_8_6

VSS29

3

V1_8SBV3SB V3SBVCC1_8 V3SBVCC3_3 V1_8SBVCC1_8

D2

U18

T18F5G5

V17

V18

V14

V15

V16H5J5

VCCA

VCCPS1

VCCPS2

VCCPX1

VCCPX2

VCCUSB1

VCCUSB2

VSS30

VSS31

VSS32

VSS33

VSS34

VSS35

VSS36

VSS37

VSS38

VSS39

VSS40

VSS41

J10

J11

J12

J13

J14J9K1

K10

K11

VSS42

VSS43

K12

3

VCCCS1

VCCCS2

VSS44

VSS45

K13

K14K9L10

VCCAX1

VCCCS3

VSS46

VSS47

VSS48

L11

VCCAX2

VSS49

VSS50

L12

L13

VSS51

VSS52

L14L9M9

CPUPWRGOD

REQ#B/GPI1/REQ#5

GNT#B/GPO17/GNT#5

LAN_RXD0
LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

LAN_RSTSYNC

VSS53

VSS54

VSS55

VSS56

VSS57

VSS58

VSS59

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSS66

M10

M11

M12

M13

M14N9N10

N11

N12

N13

N14P9P10

A20M#

CPUSLP#

FERR#

IGNNE#

INIT#
INTR

STPCLK#

RCIN#

A20GATE

HL10
HL11

HLSTB
HLSTB#
HCOMP

HUBREF

PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D

IRQ14
IRQ15

APICCLK

APICD1
APICD0

SERIRQ

REQ#0

REQ#1

REQ#2

REQ#3

REQ#4

GNT#0

GNT#1

GNT#2

GNT#3

GNT#4

LAN_CLK

VSS67

VSS68

P11

P12

P13

NMI

SMI#

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9

VSS69

2

HL[0..10]

D11
A12
R22
A11
C12
C11
B11
B12
C10
B13
C13
A13

A4
B5
A5
B6
B7
A8
B8
A9
C8
C6
C7
C5
A6
A7
A3
B4

P1
P2
P3
N4

F21
C16
N20
N19
P22
N21

R2
R3
T1
AB10
P4
L3

M2
M1
R4
T2
R1
L4

G2
G1
H1

F3
F2
F1

H2
G3

VSS70

P14

Document:
Page Name:

Last Revised:

U12_RN69-1
U12_RN69-3
U12_RN69-5
U12_RN69-7

Intel(R) 815E Chipset Universal Socket 370 CRB
ICH2 Part 1

Page:
Doc:

HL[0..10] 8
A20M# 4

CPUSLP# 4
FERR# 4
IGNNE# 4
INIT# 4,17
INTR 4
NMI 4
SMI# 4
STPCLK# 4
KBRST# 21,30
A20GATE 21,30
CPU_PWGD 4,33

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10

HLSTB 8
HLSTB# 8

HUBREF_ICH

ICH_IRQ#A 30
ICH_IRQ#B 30
ICH_IRQ#C 30
ICH_IRQ#D 30

IRQ14 17
IRQ15 17
APICCLK_ICH 6
APICD1 4
APICD0 4
SERIRQ 21,30

PREQ#0 14,30
PREQ#1 14,30
PREQ#2 15,30
PREQ#3 30
PREQ#4 30
PREQ#5 30

PGNT#0 14
PGNT#1 14
PGNT#2 15

LAN_RXD0 24
LAN_RXD1 24
LAN_RXD2 24

Thursday, November 29, 2001
Thursday, November 29, 2001

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

2

1

VCC1_8

Place as close as
Possible to ICH
and via straight
to VSS plane

RN69 22/8P4R

1

2

3

4

5

6

7

8

1

Place R as

PR27

Close as

40.2,1%

possible to
ICH

HUBREF_ICH 32

VCC1_8

BC119

0.01UF

LAN_TXD0 24
LAN_TXD2 24
LAN_TXD1 24

LAN_RSTSYNC 24
LAN_CLK 24

PR25
301,1%

PR26
301,1%

Revision:

1.05

Page No:

12 33

of

A

VCC3_3 VCMOS

3

Target 20ms after
VCC_CLOCK is
powered

R376 43k

C172

1.0uF

PWROK21,25

2

2

4 4

VCC_CLOCK

3 3

2 2

1 1

3

ICH_CLK146

D19

VCC5

BAT54C

1

1

VCC3_3

5

U33

1

A

4

Vcc

Y

2

B

GND

741G08 AND

3

R377 0

Debug only - do
not stuff

USBP0P18
USBP0N18
USBP1P18
USBP1N18
USBP2P18
USBP2N18
USBP3P18
USBP3N18

USBOC#0-118
USBOC#2-318

EE_CS24
EE_DIN24
EE_DOUT24
EE_SHCLK24 SMLINK1 15,30

A

R134 1K

R325 1K

R174 15K

D12

SS12/SMD

R181 1K

BAT1

BATTERY

R162

10M

C103
18PF

Q16
2N7002

C104

1.0UF

C113

1.0UF

C110

0.047UF

R174_JP1

B

R141 10

R187
1K

R149 10M

Y2

32.768KHZ

RN71 15/8P4R
1
3
5
7

B

X10P

ICH_PWROK

JP1
1
2
3

CCM0S

2
4
6
8

R271

560K

C96

C102
18PF

RN70 15/8P4R
1
3
5
7

R164

560K

2
4
6
8

C88
X18PF

CP1

47PF/8P4C

SMBALERT#30
CASEOPEN#21,25

246

246

135

135

GPIO2530
OVT#21,30

SLP_S3#6,21,28
SLP_S5#28

PWRBTN#21,33
ICH_RI#22,30
RSMRST#21

SUSCLK21
SMBDATA9,10,21,24,30,32
SMBCLK9,10,21,24,30,32

USBCLK6
ICH_3V666

AC_RST#24,29
AC_SYNC19,24
AC_BITCLK19,24
AC_SDOUT19,24,29
AC_SDIN019,24,30
AC_SDIN124,30
ICH_SPKR19,24,29

LAD017,21
LAD117,21
LAD217,21
LAD317,21
LFRAME#17,21

LDRQ#021

VBIAS
RTCX1
RTCX2
RTCRST#

78

7 8

246

246

135

135

C

V3SB

D18
SS12/SMD

W15

AA13

W16

AB18

W21

AA17

AA18
AA16
AB16
AB17

M19

W22

W12
AB13
AB12
AB11

W13

W17
AB19

AA19

W18
AB20

AA20

W19

W20

CP2
47PF/8P4C

78

7 8

C

GPIO25

V21

GPIO24
THRM#
SLP_S3#
SLP_S5#

R20

PWROK

Y16

RSM_PWROK
PWRBTN#
RI#

R21

RSMRST#

Y17

SUS_STAT#
SUSCLK
SMBDATA
SMBCLK
SMBALTER#/GPI11

T19

INTRUDER#

CLK14

P20

CLK48

D4

CLK66

T21

VBIAS

U22

RTCX1

T22

RTCX2

T20

RTCRST#

V22

AC_RST#

P19

AC_SYNC

R19

AC_BITCLK

P21

AC_SDOUT

Y22

AC_SDIN0
AC_SDIN1

N22

SPKR

Y12

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LFRAME#/FWH4

Y13

LDRQ#0
LDRQ#1

USBP0P

Y18

USBP0N
USBP1P
USBP1N
USBP2P

Y19

USBP2N
USBP3P
USBP3N

OC#0

Y20

OC#1

Y21

OC#2
OC#3

K4

EE_CS

K3

EE_DIN

J4

EE_DOUT

J3

EE_SHCLK

U12B

82801BA ICH2

VCCRTC VCC5SBY

U21

D13

D12

VCPU2

VCPU1

VCCRTC

V5R_SUS

PDDREQ

SDDREQ
PDDACK#
SDDACK#

SMLINK0

SMLINK1

VRMPWRGD

M20K2V19

V5R1

V5R2

PDCS#1
SDCS#1
PDSC#3
SDCS#3

PDA0
PDA1
PDA2
SDA0
SDA1
SDA2

PDIOR#

SDIOR#
PDIOW#
SDIOW#
PIORDY
SIORDY

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8

PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

SDD0

SDD1

SDD2

SDD3

SDD4

SDD5

SDD6

SDD7

SDD8

SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

BC197

0.1UF

TP0
FS0

E21
C15
E19
D15

F20
F19
E22
A16
D16
B16

G22
B18
F22
B17
G19
D17
G21
C17
G20
A17

H19
H22
J19
J22
K21
L20
M21
M22
L22
L21
K22
K20
J21
J20
H21
H20

D18
B19
D19
A20
C20
C21
D22
E20
D21
C22
D20
B20
C19
A19
C18
A18

U19
V20
B15
U20
AA12

1.0UF

D

C91

PDA[0..2]

SDA[0..2]

PDD[0..15]

SDD[0..15]

D

BC125

0.1UF

PDCS#1 17
SDCS#1 17
PDCS#3 17
SDCS#3 17
PDA[0..2] 17

PDA0
PDA1
PDA2
SDA0
SDA1
SDA2

SDA[0..2] 17
PDREQ 17
SDREQ 17
PDDACK# 17
SDDACK# 17
PDIOR# 17
SDIOR# 17
PDIOW# 17
SDIOW# 17
PIORDY 17
SIORDY 17

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDD[0..15] 17

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

SDD[0..15] 17
SMLINK0 15,30

Document:
Page Name:

Last Revised:

E

VCC3_3

VCC5
VCC3_3

R403

1K

VRM_PWRGD 27

R324 1K

R129 1K

D8 SS12/SMD

Intel(R) 815E Chipset Universal Socket 370 CRB
ICH2 Part 2

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

V3SB

Revision:

1.05

Page No:

13 33

of

A

VCC3_3

VCC5

4 4

PIRQ#B11,15,30

PIRQ#D15,30

PCLK_16

PREQ#012,30

3 3

IRDY#12,15,30

DEVSEL#12,15,30

PLOCK#12,15,30
PERR#12,15,30

SERR#12,15,30

2 2

ACK64#15,30

1 1

AD[0..31]12,15

C_BE#[0..3]12,15

AD31
AD29

AD27
AD25

C_BE#3
AD23

AD21
AD19

AD17
C_BE#2

PERR#

C_BE#1
AD14

AD12
AD10

AD8
AD7

AD5
AD3

AD1
ACK64#

AD[0..31]

C_BE#[0..3]

A

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

PCI1

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
GND
GND
RESERVED
GND
CLK
GND
REQ#
+5V(I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE#3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE#2
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE#1
AD14
GND
AD12
AD10
GND

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V(I/O)
ACK64#
+5V
+5V

PCI_CON_32BIT

B

TRST#

+12V
TMS

INTA#
INTC#

RESERVED

+5V(I/O)

RESERVED

GND
GND

RESERVED

RST#

+5V(I/O)

GNT
GND

PME#

AD30

+3.3V

AD28
AD26

GND

AD24

IDSEL

AD22
AD20

GND
AD18
AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR
AD15

+3.3V

AD13
AD11

GND

C/BE#0

+3.3V

GND

+5V(I/O)
REQ64#

B

+5V

+5V

+3.3

AD9

AD6
AD4

AD2
AD0

+5V
+5V

C

V3SB

VCC3_3

VCC5

VCC12VCC12-

A1
A2
A3
A4

TDI

A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

AD30
AD28

AD26
AD24

AD22
AD20

AD18
AD16

AD15
AD13

AD11
AD9

C_BE#0
AD6

AD4
AD2

AD0

PIRQ#A 11,15,30

PIRQ#C 15,30

PCI_RST# 11,15,30
PGNT#0 12
PCI_PME# 11,12,15,22

R133
100

FRAME# 12,15,30
TRDY# 12,15,30
STOP# 12,15,30

PAR 12,15

REQ64#1 30 REQ64#2 30

C

PCLK_26

PREQ#112,30

PIRQ#C
PIRQ#A

AD31
AD29

AD27
AD25

C_BE#3
AD23

AD21
AD19

AD17
C_BE#2

IRDY#
DEVSEL#
PLOCK#

PERR#
SERR#
C_BE#1

AD14
AD12

AD10

AD8
AD7

AD5
AD3

AD1
ACK64#

VCC3_3

VCC5

VCC12-

D

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

D

PCI2

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
GND
GND
RESERVED
GND
CLK
GND
REQ#
+5V(I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE#3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE#2
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE#1
AD14
GND
AD12
AD10
GND

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V(I/O)
ACK64#
+5V
+5V

PCI_CON_32BIT

Document:
Page Name:

Last Revised:

E

V3SB

VCC5

VCC3_3

VCC12

A1

TRST#

A2

+12V

A3

TMS

A4

TDI

A5

INTA#
INTC#

RESERVED

+5V(I/O)

RESERVED

GND
GND

RESERVED

RST#

+5V(I/O)

GNT

GND

PME#

AD30

+3.3V

AD28
AD26

GND

AD24

IDSEL

AD22
AD20

GND
AD18
AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR

AD15

+3.3V

AD13
AD11

GND

C/BE#0

+3.3V

GND

+5V(I/O)
REQ64#

+5V

+5V

+3.3

AD9

AD6
AD4

AD2
AD0

+5V
+5V

A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

PIRQ#B
PIRQ#D

PCI_RST#

PCI_PME#

AD30
AD28

AD26
AD24

R_AD17
AD22

AD20
AD18

AD16

FRAME#

TRDY#
STOP#

PAR
AD15

AD13
AD11

AD9

C_BE#0
AD6

AD4
AD2

AD0

PGNT#1 12

R142
100

Intel(R) 815E Chipset Universal Socket 370 CRB
PCI 1 and 2

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

AD17R_AD16 AD16

Revision:

1.05

Page No:

14 33

of

A

VCC3_3

VCC5

4 4

PIRQ#D14,30

PIRQ#B11,14,30

PCLK_36

PREQ#212,30

3 3

IRDY#12,14,30

DEVSEL#12,14,30

PLOCK#12,14,30
PERR#12,14,30

SERR#12,14,30

2 2

ACK64#14,30

AD31
AD29

AD27
AD25

C_BE#3
AD23

AD21
AD19

AD17
C_BE#2

PERR#

C_BE#1
AD14

AD12
AD10

AD8
AD7

AD5
AD3

AD1
ACK64#

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

PCI3

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
GND
GND
RESERVED
GND
CLK
GND
REQ#
+5V(I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE#3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE#2
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE#1
AD14
GND
AD12
AD10
GND

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V(I/O)
ACK64#
+5V
+5V

PCI_CON_32BIT

B

TRST#

+12V
TMS

INTA#
INTC#

RESERVED

+5V(I/O)

RESERVED

GND
GND

RESERVED

RST#

+5V(I/O)

GNT
GND

PME#

AD30

+3.3V

AD28
AD26

GND

AD24

IDSEL

AD22
AD20

GND
AD18
AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR
AD15

+3.3V

AD13
AD11

GND

C/BE#0

+3.3V

GND

+5V(I/O)
REQ64#

+5V

+5V

+3.3

AD9

AD6
AD4

AD2
AD0

+5V
+5V

C

V3SB

VCC3_3

VCC5

VCC12VCC12-

A1
A2
A3
A4

TDI

A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

AD30
AD28

AD26
AD24

R_AD18
AD22

AD20
AD18

AD16

AD15
AD13

AD11
AD9

C_BE#0
AD6

AD4
AD2

AD0

PIRQ#C 14,30

PIRQ#A 11,14,30

PCI_RST# 11,14,30
PGNT#2 12
PCI_PME# 11,12,14,22

AD18

R148
100

FRAME# 12,14,30
TRDY# 12,14,30
STOP# 12,14,30
SMLINK0 13,30

SMLINK1 13,30
PAR 12,14

REQ64#3 30

D

E

1 1

AD[0..31]12,14

C_BE#[0..3]12,14

AD[0..31]

C_BE#[0..3]

A

B

C

Document:
Page Name:

Last Revised:

D

Intel(R) 815E Chipset Universal Socket 370 CRB
PCI 3

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

15 33

of

A

B

C

D

VCC5

E

VCC5 VCC1_8

BC68

0.22UF

R84
1K

RV
MONOPU

GV
DDCDA

BV
HS

MON2PU
VS

DDCCL

Place 100pF cap
near DVO pin 40

C136

0.01uF

VCC5

C137
100pF

6
1

11

7
2

12

8
3

13

9

4
14
10

5
15

VGA1

VGA_CONN

R73
1K

C48
10PF

BC86

0.1UF

VCC1_8

F5
FUSE_1.0A

F5_FB11

FB11
BEAD

1 2

C53
10PF

D4

1N4148

R350
1k

R351
1k

BC223

0.22UF

4 4

VID_RED8

PR12
75,1%

VID_GREEN8

PR11
75,1%

3 3

2 2

VID_BLUE8

PR10
75,1%

3VDDCDA8
3VDDCCL8
CRT_HSYNC8
CRT_VSYNC8

3VFTSDA8 VCC3SBY VCC1_8
3VFTSCL8

PCIRST#7,17,21,30

C50

3.3PF

C47

3.3PF

C43

3.3PF

VFB3

1 2

BEAD

VFB2

1 2

BEAD

VFB1

1 2

BEAD

U8
QST3384

3

1A1

4

1A2

7

1A3

8

1A4

11

1A5

14

2A1

17

2A2

18

2A3

21

2A4

22

2A5

1

BEA#

13

BEB#

VCC

1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5

GND

C49
X10PF

C46
X10PF

C45
X10PF

U28

1

VCC3

2

VCC1

3

VIDEO_1

4

VIDEO_2

5

VIDEO_3

6

GND

7

POWER_UP

8 9

VCC2 DDC_OUT1

BC225

BC224

0.22UF

0.22UF

24

5VDDCDA

2

5VDDCCL

5

5VHSYNC

6

5VVSYNC

9
10

5VFTSDA

15

5VFTSCL

16
19
20
23

12

R97

4.7K

R96

4.7K

SYNC_OUT2

SYNC_OUT1

DDC_OUT2

PAC-VGA201/QSOP

R326 22

VCC5

SYNC_IN2

SYNC_IN1

U8_VCC

16

SD2

15

SD1

14
13
12
11
10

R327 22

R85 33

C55

22PF

C135

C134

100PF

100PF

R321 10
R322 10
R87 33

C54

C57

10PF

22PF

1
3
5
7

RN41 2.2K/8P4R

R328 2.2K
R329 2.2K

FTVREF

FTVSYNC 8
FTHSYNC 8
SL_STALL 8

C56
10PF

2
4
6
8

R95

4.7K

Y

VCC5 VCC3_3 VCC1_8

C

FTD11
FTD10
FTD9
FTD8
FTD7
FTD6
FTD5
FTD4
FTD3
FTD2
FTD1
FTD0

D11G1D10

1 2

3 4

B

G1

C138

C139

C140

1.0uF

1 1

1.0uF

1.0uF

C141

2.2uF

FTD[0..11]8

A

C142

1.0uF

FTD[0..11]

C143

1.0uF

C144

2.2uF

CVBS

5 6

7 8

G2

SP2

SP0

SP1

SP3

G2

D9G3D8G4D7

9 10

11 12

13 14

15 16

G3

5V2

3V1

5V1

3V2

3V3

3V4

VDD1

VDD2

STBG6D5G7D4

D6G5ST#

17 18

19 20

21 22

23 24

25 26

27 28

29 30

G4

31 32

G5

G6

G7

PD#

VREF

VDD3

VDD4

G8

D3

33 34

35 36

37 38

39 40

41 42

G8

C

RST#

43 44

SCL5

SDA5

D2G9D1

45 46

G9

SCL

SDA

G10

G11

D0

47 48

49 50

51 52

53 54

G10

G11

J3

HS

VS

I/C

55 56

G12

D/B

57 58

G12

DVO CONNECTOR

59 60

FTCLK0 8
FTCLK1 8
FTBLNK# 8

D

Document:
Page Name:

Last Revised:

Intel(R) 815E Chipset Universal Socket 370 CRB
VGA Header and DVO Debug Header

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

16 33

of

8

7

6

5

4

3

2

1

IDE

FWH

VCC3_3VCC3_3

D D

PCIRST#7,16,21,30

GPIO2312

LAD013,21
LAD113,21

C C

B B

LAD213,21

BC173

0.1UF

R206 8.2K

R207
0

U23

1

VPP

2

RST#

3

FGPI3

4

FGPI2

5

FGPI1

6

FGPI0

7

WP#

8

TBL#

9

ID3

10

ID2

11

ID1

12

ID0

13

FWH0

14

FWH1

15

FWH2

16 17

GND FWH3
FWH32

VCC

CLK

FGPI4
GNDA

VCCA

GND
VCC

INIT#

FWH4

RFU
RFU
RFU
RFU
RFU

BC178

BC177

BC175

0.1UF

0.1UF

0.1UF

32
31

FPGI4

30
29

IC

28
27
26
25
24
23
22
21
20
19
18

R211 8.2K

PCLK_8 6

INIT# 4,12
LFRAME# 13,21

LAD3 13,21

PDD[0..15]13

IDERST#30

PDDACK#13

IDEACTP#24

SDD[0..15]13

SDDACK#13

IDEACTS#24

PDA[0..2]13

PDREQ13
PDIOW#13
PDIOR#13
PIORDY13

PDCS#113

SDA[0..2]13

SDREQ13
SDIOW#13
SDIOR#13
SIORDY13

SDCS#113

IRQ1412
VCC3_3

IRQ1512
VCC3_3

PDD[0..15]
PDA[0..2]

IDERST#

R83 8.2K

SDD[0..15]
SDA[0..2]

IDERST#

R75

VCC3_3

R112

VCC3_3

8.2K

R113

R79

4.7K

R76

4.7K

33

IDERST_IDE1_PIN1
PDD7
PDD6 PDD9
PDD5 PDD10
PDD4 PDD11
PDD3 PDD12
PDD2 PDD13
PDD1 PDD14
PDD0 PDD15

PDA1
PDA0

PDA2

C51
47PF

IDERST_IDE2_PIN1

33

SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

SDA1
SDA0

SDA2

C44
47PF

IDE1
1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

PIN_2X20

IDE2
1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

PIN_2X20

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

R80

R70

10K

10K

PDD8

SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

P66DET 12
PDCS#3 13

S66DET 12
SDCS#3 13

A A

Document:
Page Name:

Last Revised:

8

7

6

5

4

3

Intel(R) 815E Chipset Universal Socket 370 CRB
FWH and UDMA100 IDE

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

2

Revision:

Page No:

17 33

1

1.05

of

8

USBOC#0-113

D D

USBP0N13
USBP0P13
USBP1N13
USBP1P13

V3SB

R266

R267

330K

C C

330K

RN72
15K/8P4R

7

VCC5DUAL

F4 FUSE_1.0A

135

7

246

8

6

1 2

FB8 BEAD

+

EC18

100UF

BC4
470PF

5

4

1 2

FB24 BEAD

1 2

FB23 BEAD

1 2

FB22 BEAD

1 2

FB21 BEAD

3

246

246

CP3
47PF/8P4C

135

78

135

7 8

2

1
2
3
4
5
6
7
8

USB1
VCC0

DATA0­DATA0+
GND0
VCC1
DATA1­DATA1+
GND1

USB_CON2

1

CNR_OC#24
AGP_OC#11

USBOC#2-313

B B

A A

USBP2N13
USBP2P13
USBP3N13
USBP3P13

CNRUSBN24
CNRUSBP24

AGPUSBN11
AGPUSBP11

8

R268 X0
R269 X0 F7 FUSE_1.0A

RN73
15K/8P4R

7

135

246

7

8

VCC5DUAL

1 2

FB25 BEAD

1 2

+

EC39

100UF

6

C122
470PF

1 2

1 2

FB29 BEAD

5

FB28 BEAD

4

1 2

FB27 BEAD

FB26 BEAD

246

246

CP4
47PF/8P4C

135

78

135

7 8

Document:
Page Name:

Last Revised:

3

Intel(R) 815E Chipset Universal Socket 370 CRB
USB

Page:
Doc:

USB2
12

34
56
78
910

HEADER5X2

1

JP4

2
3

HEADER5

4
5

1
2
3
4
5

Thursday, November 29, 2001
Thursday, November 29, 2001

JP5

HEADER5

JP4 Pin 3 near USB2 Pin 5
JP4 Pin 4 near USB2 Pin 7

JP5 Pin 3 near USB2 Pin 6
JP5 Pin 4 near USB2 Pin 8

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

2

Revision:

Page No:

18 33

1

1.05

of

8

D D

7

6

5

VCC3_3 VCC5 VCC5_AUDIO

BC140

0.1UF

4

12

PFB6

BEAD

BC139

0.1UF

BC136

0.1UF

3

BC129

0.1UF

2

1

RESET#

BIT_CLK

2

C98
22PF

NC40

NC44

SYNC

CS1
CS0

EAPD

XTL_IN

XTAL_IN

Y1

43

NC43

U15

11
5
8
10
6

46
45
48
47

C99
X10PF

CS4299

R253 X0

C97
22PF

PRI_DWN_RST# 29
AC_SDOUT 13,24,29
AC_SDIN0 13,24,30
AC_SYNC 13,24

AC_BITCLK 13,24

EAPD 20

R252
1K

AUD_VREFOUT 20

R254
1K

4

1

7

9

38

42

25

264044

AVSS2

VREF

AVSS1

AVDD1

SDATA_OUT

SDATA_IN

CHAIN_CLK

VREFOUT

XTL_OUT

28

3

VREFOUT

XTAL_OUT

24.576MHZ

MC48

2.2UF

DVSS1

DVSS2

DVDD2

AC’97
CODEC

RX3D

CX3D

34

CX3D

RX3D

MC51

0.1uF NPOP

MC55

0.1UF

AVDD2

27

VREF

MC46

4.7UF

DVDD1

ICH_SPKR13,24,29
LINE_IN_R20
LINE_IN_L20

C C

B B

MIC_IN20
CD_R20

CD_L20
CD_REF20

AUX_L20
AUX_R20

AC97SPKR24
LNLVL_OUT_R20
LNLVL_OUT_L20

R336 1K

R154 100

R154_MC58

R337
220K

R155
220K

MC56 1UF

MC58 1UF

PC_BEEPR336_MC56

MONO_OUT

C95
2700PF

C94
2700PF

12

PC_BEEP

24

LINE_IN_R

23

LINE_IN_L

21

MIC1

22

MIC2

20

CD_R

18

CD_L

19

CD_REF

17

VIDEO_R

16

VIDEO_L

14

AUX_L

15

AUX_R

13

PHONE

37

MONO_OUT

36

LINE_OUT_R

35

LINE_OUT_L

41

LNLVL_OUT_R

39

LNLVL_OUT_L

MC53
1UF

AFILT1

AFILT2

FILT_L

FILT_R

2930323133

FILT_R

FILT_L

AFILT2

AFILT1

MC54

MC52

1UF

1UF

"SINGLE POINT CONNECTION"

A A

Document:
Page Name:

Last Revised:

8

7

6

5

4

3

Intel(R) 815E Chipset Universal Socket 370 CRB
AC’97 Codec

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

2

Revision:

Page No:

19 33

1

1.05

of

8

7

6

5

4

3

2

1

Stereo HP/Spkr out

R104

C77

C87_C77

+

22

100UF

R105

C78

U11_OUTA

1
2
3
4

+

100UF

U11
OUTA

INA
BYPASS
GND

LM4880

22

SHUTDN

D D

MC47

LNLVL_OUT_L19

LNLVL_OUT_R19

C C

EAPD19

MC47_R132

1UF

MC45

MC45_R127 U11_INA

1UF

R132

20K

R127

20K

C87 100PF

R126 20K

U11_BYPASS

MC40
1UF

VDD

OUTB

FB13

BEAD
FB14

BEAD

SPKROUT_R

SPKROUT_L

C75
100PF

VCC5_AUDIO

U11_OUTB
U11_INB

BC123

0.1UF

C74
100PF

C74_JK1

JK1

PHONEJACK

R128
20K

C90
100PF

1 2

1 2

8
7
6

INB

5

LINE_IN_R19

LINE_IN_L19

B B

AUD_VREFOUT19

MIC_IN19

A A

8

MC44

1UF
MC42

1UF

C80
100PF

MC41

R120_MC41 JK3_MICIN

1UF

C86
100PF

R119

R120
1K

C85

0.01UF

7

R122

R121

2.2K

R122_FB17MC44_R122

1K

R121_FB16MC42_R121

1K

R119_FB15

Line_In Analog Input

FB17

BEAD
FB16

BEAD

JK2_LINE_IN_R

JK2_LINE_IN_L

1 2

1 2

Microphone Input

FB15

1 2

BEAD

C76
100PF

6

JK2

PHONEJACK

JK3

PHONEJACK

"SINGLE POINT CONNECTION"

5

CD Analog Input

CD2

1
2
3
4

2.54_WAFER_4

CD1

1
2
3

AUX1

4

1
2
3
4

2mm_WAFER_4

2.54_WAFER_4

CD_INR CDIN_R
CD_ING

CD_INL

AUX_INL

AUX_INR

R115

1K

R117
1K

R116

1K

R125
220K

MC36

1UF

C81
100PF

MC37

1UF

R118
220K

CDIN_L

CDIN_REF

C79
100PF

Document:
Page Name:

Last Revised:

4

3

C83
100PF

R124
220K

C84
100PF

C82
100PF

MC43

1UF
MC39

1UF
MC38

1UF

CD_R 19

CD_L 19

CD_REF 19

AUX_L 19

AUX_R 19

Intel(R) 815E Chipset Universal Socket 370 CRB
Audio I/O

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

2

1

Revision:

1.05

Page No:

20 33

of

8

VTT_SENSE25

SMBDATA9,10,13,24,30,32
SMBCLK9,10,13,24,30,32

-5VIN25

-12VIN25
+12VIN25

D D

C C

+3.3VIN25
VCORE25

HM_VREF25
VTIN325

THRMDN4,25

VTIN24,25
VTIN125
OVT#13,30

VID327,29,32
VID227,29,32
VID127,29,32
VID027,29,32
FANIO325
FANIO225
FANIO125

FANPWM225
FANPWM125

BEEP24
MIDI_IN23
MIDI_OUT23
J1BUTTON223
J2BUTTON223
JOY1Y23
JOY2Y23
JOY2X23
JOY1X23
J2BUTTON123
J1BUTTON123

VCC5

VCCRTC

VCC5

7

FB19

1 2

BEAD

BC154

0.1UF

BC161

0.1UF

FB20

1 2

BEAD

IOAVCC

103

VTIN2

104

VTIN1

105

OVT#

106

VID4

107

VID3

108

VID2

109

VID1

110

VID0

111

FANIO3

112

FANIO2

113

FANIO1

114

VCC

115

FANPWM2

116

FANPWM1

117

VSS

118

BEEP

119

MSI/GP20

120

MSO/IRQIN0

121

GPSA2/GP17

122

GPSB2/GP16

123

GPY1/GP15

124

GPY2/P16/GP14

125

GPX2/P15/GP13

126

GPX1/P14/GP12

127

GPSB1/P13/GP11

128

GPSA1/P12/GP10

6

R185
300
R193
300

BC172

0.1UF

100

101

102

VREF

VTIN3

VCOREB

VCOREA

5

VSS

RIB#

-5VIN

AVCC

AGND

-12VIN

+12VIN

+3.3VIN

SCL/GP21

SDA/GP22

PLED/GP23

WDTO/GP24

SINB

DTRB#

DCDB#

SOUTB

IRTX/GP26

IRRX/GP25

W83627HF

RTSB#

DSRB#

VCC

CTSB#

CASEOPEN#

4

6566676869707172737475767778798081828384858687888990919293949596979899

VBAT

SUSCLKIN

SUSCIN/GP30

PWRCTL#/GP31

MCLK

MDAT

PSIN#

PSOUT#

CIRRX/GP34

PWROK/GP32

RSMRST#/GP33

SUSLED/GP35

R166
0

KBLOCK#

KDAT
KCLK

VSB
KBRST
GA20M

RIA#

DCDA#

VSS
SOUTA

SINA
DTRA#
RTSA#

DSRA#

CTSA#

VCC

STB#

AFD#
ERR#

INIT#

SLIN#

PD0
PD1
PD2
PD3

3

R157

VCC5SBY

10K

R167

V3SB

10K

U17

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

VCC5SBY

BC151

0.1UF

2

VCC5

IRRX 23
IRTX 23
RI#1 22
DCD#1 22
TXD1 22
RXD1 22
DTR#1 22
RTS#1 22
DSR#1 22
CTS#1 22

CASEOPEN# 13,25
SUSCLK 13
SLP_S3# 6,13,28
PS_ON 25
PWROK 13,25
RSMRST# 13
PANSWIN 24,32
PWRBTN# 13,33
MDAT 23

MCLK 23

SUSLED 24
KDAT 23
KCLK 23

KBRST# 12,30
A20GATE 12,30
KEYLOCK# 24
RI#0 22
DCD#0 22

TXD0 22
RXD0 22
DTR#0 22
RTS#0 22
DSR#0 22
CTS#0 22

STB# 22
AFD# 22
ERR# 22
PAR_INIT# 22
SLIN# 22

1

B B

DRVDEN1

INDEX#

MOA#

DSB#

DSA#

DIR#

MOB#

8

FDD Signals Trace 8 or 10 mil

FDC1
1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
313332

SIO_CLK246
LPC_PME#12,30

A A

8

PCLK_76
LDRQ#013

SERIRQ12,30
LAD313,17

LAD213,17
LAD113,17
LAD013,17
LFRAME#13,17

7

HEADER_17X2

RWC#

2
4

DS1#

6
8

MOA#

10

DSB#

12

DSA#

14

MOB#

16

DIR#

18

STEP#

20

WD#

22

WE#

24
26
28
30

HEAD#

34

6

DRVDEN0

12345679101112131416171819202122232425262728293031323334353637

STEP#

WD#

RDATA#

WE#

VCC

TRAK0#

WP#

HEAD#

DSKCHG#

CLKIN

PME#

VSS

PCICLK

LDRQ#

SERIRQ

LAD3

LAD2

LAD1

LAD0

VCC3V

LFRAME#

LRESET#

SLCTPEBUSY

ACK#

PD7

PD6

PD5

PD4

W83627HF

15

38

BC162
.1U

BC155
.1U

VCC5
VCC3_3

Document:
Page Name:

Last Revised:

Intel(R) 815E Chipset Universal Socket 370 CRB
Super I/O and FDC

Page:

Thursday, November 29, 2001

Doc:

Thursday, November 29, 2001

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

5

4

3

2

PDR0 22
PDR1 22
PDR2 22
PDR3 22
PDR4 22
PDR5 22
PDR6 22
PDR7 22
ACK# 22
BUSY 22
PE 22
SLCT 22

PCIRST# 7,16,17,30

Revision:

1.05

Page No:

21 33

1

of

A

B

C

D

E

WAKE ON LAN

VCC12-

VCC12 VCC5

COM1

VCC5SBY

4 4

PCI_PME#11,12,14,15

ICH_RI#13,30

3 3

AFD#21
ERR#21

PAR_INIT#21

2 2

1 1

SLIN#21
STB#21
PDR021
PDR121
PDR221
PDR321
SLCT21
PDR421
PE21
PDR521
BUSY21
PDR621
PDR721

ACK#21

A

WAKE ON MODEM

R107

RI0

10K

R109

RI1

10K

Q21

2N3904

R230

100

R229

4.7K

Q14

2N3904

R108

2.2K

Q15

2N3904

R110

2.2K

Parallel Port

U5

1

P1

2

P2

3 26

SI1 SO1

4

SI2

5

SI3

6

SI4

7

SI5

8

P3

9

SI6

10

P4

11

SI7

12

P5

13

SI8

14

SI9

PAC-S1284

WOL1

3
2
1

HEADER_3*1(2MM)

SO2
SO3
SO4

GND

SO5

VCC

SO6
SO7
SO8
SO9

B

DCD#021

DTR#021

CTS#021

TXD021

RTS#021

RXD021

DSR#021

RI#021

DCD#121

DTR#121

CTS#121

TXD121

RTS#121

RXD121

DSR#121

RI#121

28

P8

27

P7

25
24
23
22
21
20
19
18
17
16
15

P6

D6

SS12/SMD

VCC5

D2

SS12/SMD

BC49
.1U

LPT1

1

14

2

15

3

16

4

17

5

18

6

19

7

20

8

21

9
22
10
23
11
24
12
25
13

LPT

C

10
11

12
13
14
15
16
17
18
19

10
11

12
13
14
15
16
17
18
19

U9

-12V
GND

RY5
DA3
RY4
DA2
DA1
RY3
RY2
RY1

GD75232

U10

-12V
GND

RY5
DA3
RY4
DA2
DA1
RY3
RY2
RY1

GD75232

12V

RA5
DY3
RA4
DY2
DY1
RA3
RA2
RA1

12V

RA5
DY3
RA4
DY2
DY1
RA3
RA2
RA1

1
20

5V

9
8
7
6
5
4
3
2

1
20

5V

9
8
7
6
5
4
3
2

DCD0
DTR0
CTS0
TXDD0
RTS0
RXDD0
DSR0
RI0

DCD1
DTR1
CTS1
TXDD1
RTS1
RXDD1
DSR1
RI1

D7

SS12/SMD

D

DCD0
DSR0
RXDD0
RTS0
TXDD0
CTS0

BC99
.1U

DTR0
RI0

100PF/8P4C

CTS1
DSR1
DTR1
RXDD1

BC54
.1U

DCD1
TXDD1

RTS1
RI1

100PF/8P4C

Document:
Page Name:

Last Revised:

246

246

CN3

135

246

CN11

135

246

135

246

135

246

135

78

135

7 8

246

246

135

78

135

7 8

78

7 8

78

7 8

Intel(R) 815E Chipset Universal Socket 370 CRB
Serial, Parallel, WOL, and WOR

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

CN2

100PF/8P4C

COM2

CN9

100PF/8P4C

COM1

1
6
2
7
3
8
4
9
5

CONNECTOR_DB9

COM2

2

1

4

3

6

5

8

7

10

9
HEADER_5X2

E

Revision:

1.05

Page No:

22 33

of

A

4 4

J1BUTTON121
J2BUTTON121

JOY1X21
JOY2X21

MIDI_OUT21

JOY2Y21

JOY1Y21
J2BUTTON221
J1BUTTON221

MIDI_IN21

C60
1000PF

3 3

C64
1000PF

C63
22PF

C65
22PF

R92

4.7K

R91 47

C66
22PF

C68
22PF

C67
1000PF

C71
1000PF

R99

4.7K

R98

RN40 1K/8P4R

8
6
4
2

RN39 1K/8P4R

8
6
4
2

B

VCC5VCC5 VCC5VCC5 VCC5VCC5 VCC5

FB12

R93

4.7K

246

246

135

135

R102

4.7K

78

7 8

R94

4.7K

7
5
3
1

47

7
5
3
1

C62

C59

470PF

CN8

470PF
470PF/8P4C

78

7 8

R101

4.7K

246

246

CN10

135

470PF/8P4C

135

BEAD

1 2

C

R103 0

F6 XFUSE_1.0A

C70

470PF

1

J1BUT1
J2BUT1
JOY_1X
JOY_2X

MIDI_OUTPUT
JOY_2Y

JOY_1Y
J2BUT2
J1BUT2
MIDI_INPUT

C73

470PF

9
2

10

3

11

4

12

5

13

6

14

7

15

8

Game Port

J1

GAME_PORT

D

E

VCC5DUAL

KDAT21

2 2

1 1

KCLK21

MDAT21

MCLK21

VCC5

IRRX21

IRTX21

A

0

R17

F1 XFUSE_1.0A

R18 0

F2 XFUSE_1.0A

RN4 4.7K/8P4R

8
6
4
2

IR1
1
2
3
4
5

HEADER_1X5

IR

FB1

1 2

BEAD

FB3

1 2

BEAD
FB5

1 2

BEAD

7
5
3
1

B

6
4
2

1 2

1 2

1 2

CN1

6
4
2

470PF8P4C

78
5
3
1

FB2

BEAD
FB4

BEAD
FB6

BEAD

78
5
3
1

CN1_U1

C1

2.2UFC22.2UF

U1
1

2
3
4
5
6

13
14
15

16
17

7
8
9
10
11
12

KB/MOUSE

Keyboard
Mouse

C

D

Document:
Page Name:

Last Revised:

Intel(R) 815E Chipset Universal Socket 370 CRB
PS/2, Game, and IR

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

23 33

of

8

7

6

5

4

3

2

1

Power
Switch

SW2

1 2

12

3 4

34

D D

C C

B B

A A

SW_4

KEYLOCK#21

EXTSMI#12

PANSWIN21,32

IDEACTP#17

IDEACTS#17

VCC5

R255
10K

HWRST#25,32

SUSLED21

BEEP21

ICH_SPKR13,19,29

AC97SPKR19

8

R256 0

R241
10K

VCC5

R223

10K

JP2
12

34
XHEADER 2X2

BC185

0.1UF

SW3

1 2

12

3 4

34

SW_4

Reset
Switch

R226 2.2K

7

JP2

1-2 ON
3-4 ON

VCC5SBY VCC5

V3SB

R244

R242

R233

10K

C119

0.1UF

R235
10K

Q19

2N3904

PC_BEEP SELECTION
TRADITIONAL
CONTROLLED by AC97 CODEC

10K

220

R242_PN1

R240

0

D15 1N4148

D14 1N4148

VCC5SBY

R234

150

Q22
2N3904

R232 68

R231 68

Q20
2N3904

R243_PN1
D15_PN1

R240_PN1

6

R243

150

R237_PN2

R237
0

R237_2

R238_PN1

VCC5

R236

33

BC184

0.1UF

R238
220

VCC5

PN1
1

2
3

KEYLOCK

4
5
6
7

HDD LED

8
9
10

PWR_SW

11
12
13

SMI_SW

14
HEADER_14

PN2
1

RESET

2
3
4
5

SPEAKER

6
7
8
9

GREEN LED

10
11
12

RESERVE

13
14

HEADER_14

SP1

BUZZER

5

LAN_RSTSYNC12

LAN_TXD112

LAN_RXD212
LAN_RXD012

CNR_OC#18

EE_SHCLK13

SMBCLK9,10,13,21,30,32
PRI_DWN#12,29

AC_SYNC13,19
AC_SDOUT13,19,29
AC_BITCLK13,19

VCC5SBY

VCC3_3

R246

2.2K

SMBCLK
SMBDATA

R247
20K

R239 330

4

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19

B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30

D16

LED

CNRSLOT1

RESERVED
RESERVED
RESERVED
GND
RESERVED
RESERVED
GND
LAN_TXD1
LAN_RSTSYNC
GND
LAN_RXD2
LAN_RXD0
GND
RESERVED
+5VDUAL
USB_OC#
GND

-12V
+3.3VD

GND
EE_DOUT
EE_SHCLK
GND
SMB_A0
SMB_SCL
PRIMARY_DN#
GND
AC97_SYNC
AC97_SD_OUT
AC97_BITCLK

CNR

SMB2
1
2
3
4
5

SMBCON

RESERVED
RESERVED

GND
RESERVED
RESERVED

GND

LAN_TXD2
LAN_TXD0

GND

LAN_CLK

LAN_RXD1

RESERVED

USB+

GND

USB­+12V

GND

+3.3VDUAL

+5VD

GND

EE_DIN

EE_CS
SMB_A1
SMB_A2

SMB_SDA

AC97_RESET#

RESERVED
AC97_SD_IN1
AC97_SD_IN0

GND

VCC5VCC5

3

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30

SMB1
1
2
3
4
5

SMBCON

Document:
Page Name:

Last Revised:

VCC12VCC5SBYVCC12- VCC5V3SB

LAN_TXD2 12
LAN_TXD0 12

LAN_CLK 12
LAN_RXD1 12

CNRUSBP 18
CNRUSBN 18

R272

C125

R273

47PF

C126

15K

47PF

SMBDATA 9,10,13,21,30,32
AC_RST# 13,29

AC_SDIN1 13,30
AC_SDIN0 13,19,30

EE_DOUT 13EE_DIN13

EE_CS 13

15K

Intel(R) 815E Chipset Universal Socket 370 CRB
Front Panel Headers and CNR

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

2

1

Revision:

1.05

Page No:

24 33

of

A

VCC3_3 VCC5VCC5SBY V3SB

ATXPR1

11

VCC12-

PS_ON21

4 4

HWRST#24,32

DBRESET#4

3 3

VCC_5-

VCC5

12
13
14
15
16
17
18
19
20

3.3V

-12V
GND
PS_ON
GND
GND
GND

-5V
+5V
+5V

ATX_PWCON

GND
GND
GND

PWROK

AUX5V

+12V

3.3V

3.3V
+5V
+5V

B

1
2
3
4
5
6
7
8
9
10

R245 100

R323

1K

ATXPWROK

V3SBV3SB

BC165
.1U

U20C

VCC5SBY
VCC12

74LVC14A

U20F

74LVC14A

V3SB VCC5SBY

U20A

14

7

74LVC14A

65

1213

21

BC164
.1U

VCC5SBY

1 2

7 14

VCC5SBY

13 12

3 4

C

U19A

74LVC06A

U19F

74LVC06A

U19B

74LVC06A

D10
1N4148

C115

2.2UF

D

R190

15K

R192

33K

U20D

89

74LVC14A

Temperature Sensing

VCC5SBY

U19E

11 10

74LVC06A

R189

4.7K

1

JP3

2

HEADER_2

E

PWROK 13,21

VTIN321

HM_VREF21

THRMDN4,21

VCC12

VCCVID

VTT

VCC3_3

VTIN121

VTIN24,21

C118
3300PF

28K,1%

56K,1%

56K,1%

R210
30K

PR37

PR35

PR33

D

4.7K

VCC12

Q18

EC38
22UF

EC3
22UF

EC35
22UF

VCC12

VCC12

2N2907

+

Q2
2N2907

+

+

+12CHFAN

FAN3

3
2
1

HEADER_3

+12CPUFAN

FAN1

3
2
1

HEADER_3

FAN2

3
2
1

HEADER_3

1K

1K

R218

R217

Q17

FANPWM121

2 2

FANPWM221

VCCRTC

CASEOPEN#13,21

If case is opened,
this switch should be closed.

1 1

R216

R16

R213 10M

HEADER_2PIN

A

2N7002

510

R11

4.7K

R10

Q1
2N7002

510

S1

1N4148

1N4148

1N4148

B

D13

D1

D5

VCC5

R212
1K

VCC5

R19
1K

VCC5

R100
1K

CHASSIS FAN

FANIO1 21

CPU FAN

FANIO2 21

PWR FAN

FANIO3 21

C

PR38

10K,1%

PR39

10K,1%

PR36

10K,1%

R209
10K

R208
10K

R214
10K

PR34

232K,1%

PR32

120K,1%

Document:
Page Name:

Last Revised:

RT2

t

X10K_1%-THRM/0603

"system use"

RT1

t

10K_1%-THRM/0603

"power use"

Voltage Sensing

+12VIN 21
VCORE 21

VTT_SENSE 21

+3.3VIN 21

VCC12-

-12VIN 21

-5VIN 21
VCC_5-

Intel(R) 815E Chipset Universal Socket 370 CRB
ATX Power and HW Monitor

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

25 33

of

A

7

B

VCC12VCC5SBY

C

VCC3_3

D

E

VCC5

R354

4 4

TYPEDET#11

3 3

2 2

VCC3_3

3

C174
10 uF

VR1

VOUT

VIN

LT1587-ADJ

ADJ

3.3k

R356

3.3k

VCC3_3

VTT

2

1

R359
10k

VR1_FB

U31_SHDN2#

C162

0.1uF

C148

0.1uF

U31_SHDN1#

R364

49.9 1%

1

2

2

D23 BAT54C

1

3

3

R355_C147

R355
0

8
5
3
4

ADM1051A

C160
22uF Tantalum

V1_8SB

C147

1.0uF

U31

VCC
SHDN1#
SHDN2#
GND

VCC5

FORCE 1

SENSE 1

FORCE 2

SENSE 2

7
6
1
2

BAT54C

U32A

8

VCC

3

IN+ 1

2

IN- 1

4

GND

LM393 Ch1

D24

U31_SENSE2
VCC5

2

2

OUT 1

U31_FORCE1

U31_SENSE1

U31_FORCE2

3

3

1

VCC5

1

1

D24_U32

Q39
PHD55N03LT

R357
0

R358
1M - NPOP

VCC3_3

Q40
MTD3055VLT4

R360
100 1%

R361
5620 1%

R380
20k

V1_8SB

C173

0.1 uF

2.0ms delay
nominal

C155

0.1uF

C156
100uF

VCC3_3

C150
100uF

Target is
really 1.85V

ASSERTED LOW!

U32B

5

IN+ 2

OUT 2

6

IN- 2

LM393 Ch2

VDDQ
C157
100uF

R401

220

Q49_B

R402

470

C151
100uF

VCC5

R381
1k

7

C158

4.7uF

Q49
NPN

Empty for ADM1051AJR

C152

4.7uF
VCC12

Q43
2N7002

C159

4.7uF

R400

Q48_B

C153

4.7uF

R378

2.2k

VTTPWRGD12 6

VTTPWRGD5# 27

220

C149

0.1uF

VTT

Q48
PNP

VCC1_8

R379
1k

VTTPWRGD 4

Q44
2N7002

R366

Q41
FDN335N

TUAL5

,6,

1 1

R367

10 1%

732 1%

R368
1k 1%

U32-2

Document:
Page Name:

Last Revised:

Intel(R) 815E Chipset Universal Socket 370 CRB
VRegs: Vddq, Vcc1_8, and Vtt

Page:

Thursday, November 29, 2001

Doc:

Thursday, November 29, 2001

Revision:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

A

B

C

D

Page No:

26 33

E

1.05

of

A

2

L7

C176

0.1uF

C184

4.7uF

1.7uH

U34_R391

C188

100pF

R393

154k 1%

VID3
VID2
VID1
VID0
VID4

U34_C188

VCC5

C175
10uF

4 4

VCC12

R382 10 (805)

0.1uF

VID[0:4]

9,3

VTTPWRGD5#26

VCC5

R390

3 3

25.5k 1%

R391 0

0.001uF

R382_U34

C183

C193

C177
3300uF

16

1
2
3
4
5
8

7
13
12
20

B

C178
3300uF

U34

VCC
VID3
VID2
VID1
VID0
VID25
SD
REF
COMP
CT
GND

ADP3170

CS+

CS­PGND
DRVH

DRVL

PWRGD

LRDRV

LRFB

FB

C179

0.1uF

11
10
19
18
17
9
6

14
15

C180

4.7uF

U34-18

R385 4.7 (805)
R386 2.2 (805)

U34-17

VCCVID_FB

U34_1415

C

Q45_L7

C181

4.7uF

Q45

SUD50N03-07

VRM_PWRGD 13

SUD50N03-07

Q45_L8

Q46_R386

Q46

C194

0.1uF

U34_R384
U34_C182

L8

R388

2.2 (805)

C189
4700pF

R392 0

C182 0.001uF

R383
220

1.2uH
R389 2 mOhm (2512)

D

R384
220

C190
820uF

C185
820uF

C191
820uF

C186
820uF

E

C192
1000uF

VCCVID

C187
1000uF

V3SB

R404

2 2

Document:
Page Name:

1 1

Last Revised:

32.4 1%

R405

38.3 1%

Intel(R) 815E Chipset Universal Socket 370 CRB
VRegs: VCCVID, V1_8SB

Page:

Thursday, November 29, 2001

Doc:

Thursday, November 29, 2001

V1_8SB

New V1_SB Circuitry

This takes the place of
the old V1_8SB circuit.

C197

Revision:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

A

B

C

D

Page No:

27 33

E

1.05

of

A

B

C

D

E

VCC3_3VCC12VCC5SBY

U2_Q4

U2_R20

R20

10K

EC15

+

100UF

U2_C4

C4

0.1UF

EC17

+

100UF

13

3

3V3DLSB

4

3V3DL

9

FAULT/MSET

6

S3

7

S5

5

EN5VDL

2

EN3VDL
SS

RT9641

4 5
3

2
1

C18
1UF

C7

0.1UF

Q4

EC22

+

100UF

4 4

NZT651/SOT223

V3SB

SLP_S3#6,13,21
SLP_S5#13

3 3

2 2

VCC5SBY

VCC3_3

VCC5

EC20

+

10UF

EC11

+

10UF

14

1

12V

5VSB

DRV2

VSEN2

5VDLSB

5VDL

DLA

GND

8

U2_Q8

Q8

G2 D2
S2

D2

G1

D1

S1

D1

FDS8936 / SI9936

EC19

+

100UF

U2

U2_Q7

15

16

C5

11

12
10

6

7
8

1UF

+

1500UF

U2_Q5

C8

1UF

EC14

Q7

HUF76121D3S/TO252

VCC5SBY

Q5
NDS356AP/SOT23

VCC3SBY

EC10

+

100UF

VCC5DUAL

VCC5 VCC2_5

Q3

3

VIN

EC6

+

10UF

VOUT

ADJ

LM1117ADJ

1

Q3_Feedback

2

PR3
100,1%

PR2
100,1%

+

Stuff this box

2

PR44

49.9 1%

PR45
10 1%

VCMOSVCC3_3

+

+

EC42
10UF

3

Q42

VIN

VOUT

ADJ

LT1117ADJ

1

Q42_Feedback

EC5
100UF

Do not stuff this box.

VCC1_8

EC43
10UF

R369

1.13 1%
1206 pack

R370

9.31 1%
1210 pack

Debug note:
Stuff only one box.

1 1

Document:
Page Name:

Last Revised:

A

B

C

D

Intel(R) 815E Chipset Universal Socket 370 CRB
VRegs: Duals, 3.3SB, 2.5, V C MOS

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

28 33

of

A

4 4

B

VCC3_3

SW1 DIPSW-8

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

RN59

2.2K/8P4R

V3SB

246

135

C

8

7

SW1_R262
SW1_R263

R262 8.2K
R263 8.2K

D

AC_SDOUT 13,19,24
ICH_SPKR 13,19,24

E

642

7 8

VCC5SBY

5 6

RP6
1K/8P4R

R394 8.2k

D17

1N4148

U19C

74LVC06A

2

J5

1

2

456

789

10 11 12

13 14 15

16 17 18

19 20 21

7x3 JPR HDR

R395 8.2k

23

1
3
45
6
78

9
1011
12
1314
15
1617
18
1920
21

1
3
45
6
78
9
1011
12
1314
15
1617
18
1920
21

FMOD1 6
FMOD0 6

VCC3_3 V3SB

C

PRI_DWN_RST# 19

Document:
Page Name:

Last Revised:

D

SW 7

ON BOARD AC97 CODEC

OFF

PRIMARY CODEC

ON

DISABLE

SW 5
ON
OFF FORCE CPU FREQ STRAP TO SAFE MODE(1111)

SW 6
OFF REBOOT ON 2ND WATCHDOG TIMEOUT

AC_SDOUT

USE CPU FREQ STRAP IN ICH REGISTER

STRAP(SPKR)

NO REBOOT ON 2ND WATCHDOG TIMEOUTON

Intel(R) 815E Chipset Universal Socket 370 CRB
System Config DIP Switches

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

29 33

of

AC_RST#13,24

3 3

PRI_DWN#12,24

R153

10K

2 2

1 1

A

JPR_VID03,32
JPR_VID13,32
JPR_VID23,32
JPR_VID33,32
JPR_VID43,32
BSEL#14,32
BSEL#04,32

642

RP5

1K/8P4R

135

7 8

135

VID021,27,32
VID121,27,32
VID221,27,32
VID321,27,32
VID427,32
R_REFCLK7
R_BSEL#07

B

A

PERR#12,14,15
SERR#12,14,15
PLOCK#12,14,15
STOP#12,14,15
DEVSEL#12,14,15
TRDY#12,14,15
IRDY#12,14,15

4 4

3 3

2 2

FRAME#12,14,15

PREQ#212,15
PREQ#112,14
PREQ#012,14

PREQ#312
PREQ#512
PREQ#412

ACK64#14,15
REQ64#114
REQ64#214
REQ64#315

PIRQ#A11,14,15
PIRQ#B11,14,15
PIRQ#C14,15
PIRQ#D14,15

ICH_IRQ#A12
ICH_IRQ#B12
ICH_IRQ#C12
ICH_IRQ#D12

ICH_IRQ#E12
ICH_IRQ#F12
ICH_IRQ#G12
ICH_IRQ#H12

PCI ICH2

RP2

1

R1

2

R2

3

R3

4

R4

6

R5

7

R6

8

R7

9

R8

2.7K/10P8R
RN58

1

2

3

4

5

6

7

8

2.7K/8P4R
RN64

1

2

3

4

5

6

7

8

2.7K/8P4R
RN66

1

2

3

4

5

6

7

8

2.7K/8P4R

RN74

1

2

3

4

5

6

7

8

0/8P4R
RN76

1

2

3

4

5

6

7

8

X0/8P4R

VCC5 V3SB

5

C

10

C

B

SMBALERT#13
ICH_RI#13,22
SMBCLK9,10,13,21,24,32
SMBDATA9,10,13,21,24,32

LPC_PME#12,21
SMLINK013,15

SMLINK113,15

GPI812
GPIO2513
GPIO2712

PCI_REQ#A12
OVT#13,21
KBRST#12,21
A20GATE12,21

SERIRQ12,21
AC_SDIN013,19,24
AC_SDIN113,24

RN55
1
3
5
7

8.2K/8P4R

RN60
1
3
5
7

4.7K/8P4R

RN54
1
3
5
7

8.2K/8P4R

RN51
1
3
5
7

8.2K/8P4R

R276 8.2K
R147 10K
R152 10K

RN75
1
3
5
7

8.2K/8P4R

RN77
1
3
5
7

8.2K/8P4R

C

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

V3SB

V3SB

VCC3_3

VCC3_3

VCC3_3

ICHRST#12

VCC5SBY

U19D

9 8

74LVC06A

9 8

D

VCC3_3

BC163
.1U

VCC3_3 VCC3_3

147

U18D

74LVC07A

VCC3_3

R188
1K

VCC3_3

147

U18E

11 10

74LVC07A

VCC3_3

147

U18F

13 12

74LVC07A

R188_U18

VCC3_3 VCC5

147

U18A

1 2

74LVC07A

VCC3_3

147

U18B

3 4

74LVC07A

147

U18C

5 6

74LVC07A

U20B

74LVC14A

U20E

74LVC14A

VCC3_3

VCC3_3

R196
1K

R197
1K

R198
1K

43

1011

E

IDERST# 17

PCI_RST# 11,14,15

PCIRST# 7,16,17,21

1 1

Document:
Page Name:

Last Revised:

A

B

C

D

Intel(R) 815E Chipset Universal Socket 370 CRB
Pullup/Pulldown Rs and Unused Gates

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

30 33

of

A

" ATX POWER " " ATX POWER " " ATX POWER "

VCC3_3 VCC5 VCC_5-

EC33

BC85

BC83

EC27

BC41

22UF

4 4

0.1UF

22UF

0.1UF

0.1UF

0.1UF

BC53

EC28
22UF

BC69

0.1UF

BC70

0.1UF

B

BC168

0.1UF

BC180

0.1UF

BC143

0.1UF

BC157

0.1UF

EC26

22UF

C

" ATX POWER "" ATX POWER "

VCC12-VCC12

BC156

BC142

EC36
22UF

0.1UF

0.1UF

BC167

0.1UF

BC179

0.1UF

D

E

VCCVID

MC5

MC6

MC3

4.7UF/X7R

MC4

4.7UF/X7R

MC2

4.7UF/X7R

MC1

4.7UF/X7R

4.7UF/X7R

4.7UF/X7R

MC8

4.7UF/X7R

MC9

4.7UF/X7R

MC10

4.7UF/X7R

MC13

4.7UF/X7R

MC14

4.7UF/X7R

MC15

4.7UF/X7R

MC49

4.7UF/X7R

MC50

4.7UF/X7R

MC64

4.7UF/X7R

MC65

4.7UF/X7R

" DIMM0 : Near Power Pins "

VCC3SBY

BC76

0.1UF

BC71

0.1UF

BC74

0.01UF

BC121

0.1UF

BC109

0.1UF

BC66

0.1UF

BC50

0.1UF

BC88

0.01UF

BC150

0.01UF

BC122

0.1UF

8
7
6

BC19

BC39

0.1UF

0.1UF

BC42

0.1UF

BC65

0.01UF

BC149

0.01UF

BC128

0.1UF

H4 HOLE A
1
2
3
4 5

BC43

0.1UF

BC48

0.01UF

BC147

0.01UF

BC145

0.1UF

8
7
6

BC10

BC8

0.1UF

0.1UF

BC44

0.1UF

BC51

0.01UF

BC124

0.01UF

BC146

0.1UF

H5 HOLE A
1
2
3
4 5

MC16

MC31

4.7UF

3 3

VCC1_8

MC26

4.7UF

VCC3SBY

BC87

0.01UF

2 2

BC131

0.1UF

VCC3_3

BC100

0.1UF

H1 HOLE A

1

1 1

2
3
4 5

MC11

MC30

4.7UF

4.7UF

4.7UF

" GMCH : 0.1U//0.01U at each conner and each side-center "

MC24

BC78

0.1UF

4.7UF

" GMCH : Near System Mem Quadrant "

BC82

BC80

0.01UF

0.01UF

" ICH : 0.1U//0.01U at each conner " " ICH : Near Power Pins "" ICH : Near Power Pins "

BC138

BC132

0.1UF

0.1UF

" misc. "

BC106

BC107

0.1UF

0.1UF

H3 HOLE A

1

8

2

7

3

6

4 5

A

" Display Cache : Near the Power Pins "

VDDQ

MC35

MC34

4.7UF

4.7UF

BC81

BC45

0.1UF

0.1UF

VDDQ

BC52

BC94

0.01UF

0.01UF

MC57

MC59

2.2UF

2.2UF

BC158

BC144

0.01UF

0.01UF

H6 HOLE A

8

1

7

2

6

3
4 5

B

MC32

4.7UF

H7 HOLE A

BC105

0.01UF

BC92

0.01UF

BC206

0.1UF

BC169

0.01UF

BC101

0.1UF

8
7
6

MC33

4.7UF

BC75

BC114

0.01UF

0.01UF

" GMCH : Near Display Cache Quadrant "
" Within 70 mils of GMCH "

BC91

BC97

0.01UF

0.01UF

BC205

BC204

0.1UF

0.1UF

BC160

BC159

0.01UF

0.01UF

8

1

7

2

6

3
4 5

BC102

0.1UF

BC95

0.01UF

BC93

0.01UF

VCC1_8V3SBVCC3_3

BC207

0.1UF

BC170

0.01UF

H8
1
2
3
4 5

BC96

0.01UF

BC98

0.01UF

BC115

0.1UF

BC171

0.01UF

HOLE A

BC103

0.1UF

C

BC79

0.01UF

VCC3SBY

4.7UF

BC113

0.1UF

BC183

0.01UF

8
7
6

BC104

0.1UF

MC12

H9 HOLE A
1
2
3
4 5

BC112

BC111

0.1UF

0.1UF

BC46

BC47

0.01UF

0.01UF

" DIMM1 : Near Power Pins "

MC27

MC17

4.7UF

4.7UF

MC25

4.7UF

V1_8SB

BC116

BC208

0.1UF

0.1UF

BC182

BC181

0.01UF

0.01UF

8
7
6

BC110

0.1UF

BC11

0.1UF

" ICH : Near Power Pins "

BC210

BC209

0.1UF

0.1UF

BC186

BC187

0.01UF

0.01UF

BC20

0.1UF

BC108

0.1UF

BC40

BC67

0.1UF

0.1UF

BC212

BC211

0.1UF

0.1UF

" DIMM2 : Near Power Pins "

VCC3SBY

MC60

4.7UF

4.7UF

D

BC77

0.1UF

MC61

MC62

4.7UF

Document:
Page Name:

Last Revised:

BC84

0.1UF

4.7UF

MC63

BC213

0.1UF

BC214

0.1UF

BC215

0.1UF

BC216

0.1UF

BC217

0.1UF

Intel(R) 815E Chipset Universal Socket 370 CRB
Decoupling Caps

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

BC218

0.1UF

Revision:

1.05

Page No:

31 33

of

A

B

C

D

E

4 4

3 3

J6

HEADER_3

2 2

VID[4:0]21,27,29

JPR_VID1
JPR_VID3

VID0
VID2
VID4

JPR_VID[4:0]3,29

PANSWIN21,24

HWRST#24,25

VTT VTT VCC1_8 VCC3SBY VDDQ

3
2
1

GTLREF 4,7 GTLREFA 4 HUBREF_ICH 12 CONN_AGPREF 8,11

J7

3
2
1

HEADER_3

J4

1 2

12

3 4

34

5 6

56

7 8

78

9 10

910

11 12

11 12

13 14

13 14

15 16

15 16

17 18

17 18

19 20

19 20

21 22

21 22

23 24

23 24

25 26

25 26

27 28

27 28

29 30

29 30
2x15 HDR

J8

3
2
1

HEADER_3

VID1
VID3

R_SMBDATA

R_SMBCLK
JPR_VID0
JPR_VID2
JPR_VID4

J9

3
2
1

HEADER_3

BSEL#1 4,29
BSEL#0 4,29

R396 0

R_SMBDATA 6
R_SMBCLK 6

R397 0

J10

3
2
1

HEADER_3

SMBDATA 9,10,13,21,24,30
SMBCLK 9,10,13,21,24,30

Document:
Page Name:

1 1

Last Revised:

Intel(R) 815E Chipset Universal Socket 370 CRB
Internal Debug headers

Page:

Thursday, November 29, 2001

Doc:

Thursday, November 29, 2001

Revision:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

A

B

C

D

Page No:

32 33

E

1.05

of

A

B

C

D

E

4 4

THERMTRIP#4

3 3

2 2

VCC1_8 VCC1_8 V3SB

R409

4.7k

R408

0

R410

1K

Q50

2N3904

R412 1K

R416

CPURST#4,7

Q52_R416

2.2k

R411

20k

Q51
2N3904

Q51_Q52

Q52
2N3904

PWRBTN# 13,21

CPU_PWGD4,12

1 1

A

R413
510

R414

1.3k

N6395404

Stuff either R5 or R415. See p4.

R415 0

C198
X0.01uF

No-stuff C198 - debug site only

B

N6395403 4

Document:
Page Name:

Last Revised:

C

D

Intel(R) 815E Chipset Universal Socket 370 CRB
Thermtrip

Thursday, November 29, 2001

Page:

Thursday, November 29, 2001

Doc:

Platform Applications Engineering

1900 Prairie City Road
Folsom, CA 95630

E

Revision:

1.05

Page No:

33 33

of