Intel 815 User Manual

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Intel® 815 Chipset Platform

For Use with Universal Socket 370

Design Guide

April 2001

Document Number: 298349-001

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The Intel Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM

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Intel, Pentium II, Pentium III, Celeron, and MMX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

815 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.

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C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

2 Intel

815 Chipset Platform Design Guide

Introduction ........................................................................................................................13

1.1 Terminology ..........................................................................................................14

1.2 Reference Documents ..........................................................................................16

1.3 System Overview ..................................................................................................16

1.3.1 System Features ...................................................................................17

1.3.2 Component Features.............................................................................18

1.3.2.1 Graphics Memory Controller Hub (GMCH) ..........................18

1.3.2.2 Intel® 82801AA I/O Controller Hub (ICH) .............................20

1.3.2.3 Firmware Hub (FWH)...........................................................20

1.3.3 Platform Initiatives .................................................................................21

1.3.3.1 Universal Socket 370 Design ............................................... 21

1.3.3.2 PC 133 .................................................................................21

1.3.3.3 Accelerated Hub Architecture Interface ...............................21

1.3.3.4 Internet Streaming SIMD Extensions ...................................21

1.3.3.5 AGP 2.0................................................................................21

1.3.3.6 Manageability ....................................................................... 22

1.3.3.7 AC’97 ...................................................................................23

1.3.3.8 Low-Pin-Count (LPC) Interface ............................................23

2 General Design Considerations.........................................................................................25

2.1 Nominal Board Stackup ........................................................................................25

3 Component Quadrant Layouts...........................................................................................27

4 Universal Socket 370 Design ............................................................................................29

4.1 Universal Socket 370 Definitions ..........................................................................29

4.2 Processor Design Requirements ..........................................................................31

4.2.1 Use of Universal Socket 370 Design with Incompatible GMCH ............31

4.2.2 Identifying the Processor at the Socket .................................................32

4.2.3 Setting the Appropriate Processor VTT Level .......................................33

4.2.4 VTT Processor Pin AG1 ........................................................................34

4.2.5 Identifying the Processor at the GMCH.................................................34

4.2.6 Configuring Non-VTT Processor Pins ...................................................36

4.2.7 VCMOS Reference................................................................................37

4.2.8 Processor Signal PWRGOOD...............................................................38

4.2.9 APIC Clock Voltage Switching Requirements .......................................39

4.2.10 GTLREF Topology and Layout..............................................................40

4.3 Power Sequencing on Wake Events ....................................................................41

4.3.1 Gating of Intel® CK-815 to VTTPWRGD ...............................................41

4.3.2 Gating of PWROK to ICH......................................................................42

5 System Bus Design Guidelines .........................................................................................43

5.1 System Bus Routing Guidelines ...........................................................................43

5.1.1 Initial Timing Analysis ............................................................................43

815 Chipset Platform Design Guide 3

Intel

5.2

General Topology and Layout Guidelines.............................................................46

5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signals ...........................47

5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS)

Signals .................................................................................49

5.2.1.2 THRMDP and THRMDN ......................................................50

5.2.1.3 Additional Routing and Placement Considerations ..............50

5.3 Electrical Differences for Universal PGA370 Designs ..........................................51

5.3.1 THERMTRIP Circuit ..............................................................................51

5.3.1.1 THERMTRIP Timing ............................................................51

5.4 PGA370 Socket Definition Details ........................................................................52

5.5 BSEL[1:0] Implementation Differences.................................................................56

5.6 CLKREF Circuit Implementation ...........................................................................57

5.7 Undershoot/Overshoot Requirements ..................................................................57

5.8 Processor Reset Requirements ............................................................................58

5.9 Processor PLL Filter Recommendations ..............................................................59

5.9.1 Topology................................................................................................ 59

5.9.2 Filter Specification .................................................................................59

5.9.3 Recommendation for Intel Platforms.....................................................61

5.9.4 Custom Solutions ..................................................................................63

5.10 Voltage Regulation Guidelines..............................................................................63

5.11 Decoupling Guidelines for Universal PGA370 Designs ........................................63

5.11.1 VCC

Decoupling Design.................................................................63

CORE

5.11.2 VTT Decoupling Design ........................................................................64

5.11.3 VREF Decoupling Design......................................................................64

5.12 Thermal Considerations........................................................................................65

5.12.1 Heatsink Volumetric Keepout Regions .................................................. 65

5.13 Debug Port Changes ............................................................................................67

6 System Memory Design Guidelines...................................................................................69

6.1 System Memory Routing Guidelines.....................................................................69

6.2 System Memory 2-DIMM Design Guidelines ........................................................70

6.2.1 System Memory 2-DIMM Connectivity ..................................................70

6.2.2 System Memory 2-DIMM Layout Guidelines.........................................71

6.3 System Memory 3-DIMM Design Guidelines ........................................................73

6.3.1 System Memory 3-DIMM Connectivity ..................................................73

6.3.2 System Memory 3-DIMM Layout Guidelines.........................................74

6.4 System Memory Decoupling Guidelines ...............................................................75

6.5 Compensation.......................................................................................................77

7 AGP/Display Cache Design Guidelines.............................................................................79

7.1 AGP Interface .......................................................................................................79

7.1.1 Graphics Performance Accelerator (GPA) ............................................80

7.1.2 AGP Universal Retention Mechanism (RM) ..........................................80

7.2 AGP 2.0 ................................................................................................................82

7.2.1 AGP Interface Signal Groups ................................................................83

7.3 Standard AGP Routing Guidelines .......................................................................84

7.3.1 1X Timing Domain Routing Guidelines .................................................84

7.3.1.1 Flexible Motherboard Guidelines .........................................84

7.3.1.2 AGP-Only Motherboard Guidelines......................................84

7.3.2 2X/4X Timing Domain Routing Guidelines............................................84

7.3.2.1 Flexible Motherboard Guidelines .........................................85

4 Intel

815 Chipset Platform Design Guide

7.3.2.2

AGP-Only Motherboard Guidelines......................................86

7.3.3 AGP Routing Guideline Considerations and Summary.........................87

7.3.4 AGP Clock Routing ...............................................................................88

7.3.5 AGP Signal Noise Decoupling Guidelines.............................................88

7.3.6 AGP Routing Ground Reference...........................................................89

7.4 AGP Down Routing Guidelines.............................................................................90

7.4.1 1X AGP Down Option Timing Domain Routing Guidelines ................... 90

7.4.2 2X/4X AGP Down Timing Domain Routing Guidelines .........................90

7.4.3 AGP Routing Guideline Considerations and Summary.........................91

7.4.4 AGP Clock Routing ...............................................................................92

7.4.5 AGP Signal Noise Decoupling Guidelines.............................................92

7.4.6 AGP Routing Ground Reference...........................................................92

7.5 AGP 2.0 Power Delivery Guidelines .....................................................................93

7.5.1 VDDQ Generation and TYPEDET#....................................................... 93

7.5.2 VREF Generation for AGP 2.0 (2X and 4X) ..........................................95

7.6 Additional AGP Design Guidelines........................................................................97

7.6.1 Compensation .......................................................................................97

7.6.2 AGP Pull-Ups ........................................................................................97

7.6.2.1 AGP Signal Voltage Tolerance List......................................98

7.7 Motherboard / Add-in Card Interoperability ...........................................................98

7.8 AGP / Display Cache Shared Interface.................................................................99

7.8.1 GPA Card Considerations .....................................................................99

7.8.1.1 AGP and GPA Mechanical Considerations..........................99

7.8.2 Display Cache Clocking.......................................................................100

7.9 Designs That Do Not Use The AGP Port............................................................100

8 Integrated Graphics Display Output.................................................................................101

8.1 Analog RGB/CRT................................................................................................101

8.1.1 RAMDAC/Display Interface .................................................................101

8.1.2 Reference Resistor (Rset) Calculation ................................................103

8.1.3 RAMDAC Board Design Guidelines ....................................................103

8.1.4 RAMDAC Layout Recommendations ..................................................105

8.1.5 HSYNC/VSYNC Output Guidelines..................................................... 105

8.2 Digital Video Out .................................................................................................106

8.2.1 DVO Interface Routing Guidelines ......................................................106

8.2.2 DVO I2C Interface Considerations.......................................................106

8.2.3 Leaving the DVO Port Unconnected ...................................................106

9 Hub Interface ...................................................................................................................107

9.1.1 Data Signals ........................................................................................108

9.1.2 Strobe Signals .....................................................................................108

9.1.3 HREF Generation/Distribution.............................................................108

9.1.4 Compensation .....................................................................................109

10 I/O Subsystem .................................................................................................................111

10.1 IDE Interface .......................................................................................................111

10.1.1 Cabling and Motherboard Requirements ............................................111

10.2 Cable Detection for Ultra ATA/66........................................................................113

10.2.1 Host Side Cable Detection ..................................................................114

10.2.2 Device Side Cable Detection............................................................... 115

10.2.3 Primary IDE Connector Requirements ................................................116

10.2.4 Secondary IDE Connector Requirements ...........................................117

815 Chipset Platform Design Guide 5

Intel

10.2.5

Layout for Both Host-Side and Device-Side Cable Detection .............118

10.3 AC’97 ..................................................................................................................119

10.3.1 AC’97 Routing .....................................................................................119

10.3.2 AC’97 Signal Quality Requirements ....................................................121

10.3.3 Motherboard Implementation ..............................................................121

10.4 Using Native USB Interface ................................................................................122

10.5 I/O APIC (I/O Advanced Programmable Interrupt Controller) .............................123

10.6 SMBus ................................................................................................................124

10.7 PCI ......................................................................................................................124

10.8 LPC/FWH............................................................................................................125

10.8.1 In-Circuit FWH Programming .............................................................. 125

10.8.2 FWH VPP Design Guidelines ...............................................................125

10.9 RTC.....................................................................................................................125

10.9.1 RTC Crystal.........................................................................................126

10.9.2 External Capacitors .............................................................................126

10.9.3 RTC Layout Considerations ................................................................127

10.9.4 RTC External Battery Connection .......................................................127

10.9.5 RTC External RTCRESET Circuit .......................................................128

10.9.6 RTC-Well Input Strap Requirements...................................................128

10.9.7 RTC Routing Guidelines...................................................................... 129

10.9.8 Guidelines to Minimize ESD Events ....................................................129

10.9.9 VBIAS and DC Voltage and Noise Measurements .............................129

11 Clocking ...........................................................................................................................131

11.1 2-DIMM Clocking ................................................................................................131

11.2 3-DIMM Clocking ................................................................................................133

11.3 Clock Routing Guidelines.................................................................................... 135

11.4 Clock Decoupling ................................................................................................137

11.5 Clock Driver Frequency Strapping ......................................................................137

11.6 Clock Skew Assumptions ...................................................................................138

11.7 Intel® CK-815 Power Gating On Wake Events ...................................................139

12 Power Delivery.................................................................................................................141

12.1 Thermal Design Power .......................................................................................144

12.1.1 Pull-Up and Pull-Down Resistor Values ..............................................144

12.2 ATX Power Supply PWRGOOD Requirements..................................................145

12.3 Power Management Signals ...............................................................................146

12.3.1 Power Button Implementation .............................................................147

12.4 1.85V/3.3V Power Sequencing ...........................................................................148

12.4.1 VDDQ/VCC1_85 Power Sequencing ..................................................152

12.4.2 1.85V/3.3V Power Sequencing............................................................152

12.4.3 3.3V/V5REF Sequencing.....................................................................154

13 System Design Checklist ................................................................................................. 155

13.1 Design Review Checklist ....................................................................................155

13.2 Processor Checklist ............................................................................................155

13.2.1 GTL Checklist......................................................................................155

13.2.2 CMOS Checklist ..................................................................................156

13.2.3 TAP Checklist for 370-Pin Socket Processors ....................................156

13.2.4 Miscellaneous Checklist for 370-Pin Socket Processors ....................156

13.3 GMCH Checklist .................................................................................................158

6 Intel

815 Chipset Platform Design Guide

13.3.1

AGP Interface 1X Mode Checklist.......................................................158

13.3.2 Designs That Do Not Use the AGP Port .............................................159

13.3.3 System Memory Interface Checklist....................................................160

13.3.4 Hub Interface Checklist .......................................................................160

13.3.5 Digital Video Output Port Checklist .....................................................160

13.4 ICH Checklist ......................................................................................................161

13.4.1 PCI Checklist.......................................................................................161

13.4.2 USB Checklist .....................................................................................162

13.4.3 AC ‘97 Checklist ..................................................................................162

13.4.4 IDE Checklist.......................................................................................163

13.4.5 Miscellaneous ICH Checklist ............................................................... 163

13.5 LPC Checklist .....................................................................................................165

13.6 System Checklist ................................................................................................166

13.7 FWH Checklist ....................................................................................................166

13.8 Clock Synthesizer Checklist................................................................................167

13.9 LAN Checklist .....................................................................................................168

13.10 Power Delivery Checklist ....................................................................................168

13.10.1 Power 169

14 Third-Party Vendor Information .......................................................................................171

Appendix A: Customer Reference Board (CRB).....................................................................................173

815 Chipset Platform Design Guide 7

Intel

Figures

Figure 1. System Block Diagram .......................................................................................17

Figure 2. GMCH Block Diagram ........................................................................................18

Figure 3. Board Construction Example for 60 Ω Nominal Stackup ...................................25

Figure 4. GMCH 544-Ball µBGA* CSP Quadrant Layout (Top View)................................27

Figure 5. ICH 241-Ball µBGA* CSP Quadrant Layout (Top View).....................................28

Figure 6. Firmware Hub (FWH) Packages ........................................................................28

Figure 7. Future 0.13 Micron Socket 370 Processor Safeguard for Universal Socket 370

Designs Using A-2 GMCH..........................................................................................31

Figure 8. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit .................. 32

Figure 9. VTT Selection Switch .........................................................................................33

Figure 10. Switching Pin AG1............................................................................................34

Figure 11. Processor Identification Strap on GMCH .........................................................35

Figure 12. VTTPWRGD Configuration Circuit ...................................................................36

Figure 13. GTL_REF/VCMOS_REF Voltage Divider Network ..........................................37

Figure 14. Resistor Divider Network for Processor PWRGOOD....................................... 38

Figure 15. Voltage Switch For APIC Clock from Clock Synthesizer to Processor.............39

Figure 16. GTLREF Circuit Topology ................................................................................40

Figure 17. Gating Power to Intel

CK-815 .........................................................................41

Figure 18. PWROK Gating Circuit For ICH .......................................................................42

Figure 19. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)..46

Figure 20. AGTL/AGTL+ Trace Routing............................................................................47

Figure 21. Routing for THRMDP and THRMDN................................................................50

Figure 22. Example Implementation of THERMTRIP Circuit ............................................51

Figure 23. BSEL[1:0] Circuit Implementation for PGA370 Designs...................................56

Figure 24. Examples for CLKREF Divider Circuit..............................................................57

Figure 25. RESET#/RESET2# Routing Guidelines ...........................................................58

Figure 26. Filter Specification ............................................................................................60

Figure 27. Example PLL Filter Using a Discrete Resistor .................................................62

Figure 28. Example PLL Filter Using a Buried Resistor ....................................................62

Figure 29. Core Reference Model .....................................................................................63

Figure 30. Capacitor Placement on the Motherboard........................................................64

Figure 31. Heatsink Volumetric Keepout Regions .............................................................66

Figure 32. Motherboard Component Keepout Regions ..................................................... 66

Figure 33. TAP Connector Comparison ............................................................................67

Figure 34. System Memory Routing Guidelines ................................................................69

Figure 35. System Memory Connectivity (2 DIMM) ...........................................................70

Figure 36. System Memory 2-DIMM Routing Topologies..................................................71

Figure 37. System Memory Routing Example ...................................................................72

Figure 38. System Memory Connectivity (3 DIMM) ...........................................................73

Figure 39. System Memory 3-DIMM Routing Topologies..................................................74

Figure 40. Intel Figure 41. Intel

815 Chipset Platform Decoupling Example ............................................76

815 Chipset Platform Decoupling Example ............................................77

Figure 42. AGP Left-Handed Retention Mechanism .........................................................81

Figure 43. AGP Left-Handed Retention Mechanism Keepout Information........................81

Figure 44. AGP 2X/4X Routing Example for Interfaces < 6 Inches and GPA/AGP

Solutions.....................................................................................................................85

Figure 45. AGP Decoupling Capacitor Placement Example .............................................89

Figure 46. AGP VDDQ Generation Example Circuit .........................................................94

Figure 47. AGP 2.0 VREF Generation and Distribution.....................................................96

Figure 48. Display Cache Input Clocking.........................................................................100

8 Intel

815 Chipset Platform Design Guide

Figure 49. Schematic of RAMDAC Video Interface.........................................................102

Figure 50. Cross-Sectional View of a Four-Layer Board .................................................103

Figure 51. Recommended RAMDAC Component Placement & Routing ........................104

Figure 52. Recommended RAMDAC Reference Resistor Placement and Connections 105

Figure 53. Hub Interface Signal Routing Example ..........................................................107

Figure 54. Single-Hub-Interface Reference Divider Circuit .............................................109

Figure 55. Locally Generated Hub Interface Reference Dividers ....................................109

Figure 56. IDE Minimum/Maximum Routing and Cable Lengths ....................................112

Figure 57. Ultra ATA/66 Cable.........................................................................................112

Figure 58. Host-Side IDE Cable Detection ......................................................................114

Figure 59. Drive-Side IDE Cable Detection .....................................................................115

Figure 60. Resistor Schematic for Primary IDE Connectors ...........................................116

Figure 61. Resistor Schematic for Secondary IDE Connectors.......................................117

Figure 62. Flexible IDE Cable Detection..........................................................................118

Figure 63. Recommended USB Schematic..................................................................... 123

Figure 64. PCI Bus Layout Example for Four PCI Connectors .......................................124

Figure 65. External Circuitry of RTC Oscillator................................................................126

Figure 66. Diode Circuit to Connect RTC External Battery..............................................127

Figure 67. RTCRESET External Circuit for the ICH RTC................................................128

Figure 68. Platform Clock Architecture (2 DIMMs)..........................................................132

Figure 69. Universal Platform Clock Architecture (3 DIMMs)..........................................134

Figure 70. Clock Routing Topologies ..............................................................................135

Figure 71. Power Delivery Map........................................................................................142

Figure 72. Pull-Up Resistor Example ..............................................................................145

Figure 73. G3-S0 Transition ............................................................................................148

Figure 74. S0-S3-S0 Transition .......................................................................................149

Figure 75. S0-S5-S0 Transition .......................................................................................150

Figure 76. VDDQ Power Sequencing Circuit...................................................................152

Figure 77. Example 1.85V/3.3V Power Sequencing Circuit ............................................153

Figure 78. 3.3V/V5REF Sequencing Circuitry .................................................................154

Figure 79. V5REF Circuitry.............................................................................................. 169

815 Chipset Platform Design Guide 9

Intel

Tables

Table 1. Processor Considerations for Universal Socket 370 Design...............................29

Table 2. GMCH Considerations for Universal Socket 370 Design ....................................30

Table 3. ICH Considerations for Universal Socket 370 Design .........................................30

Table 4. Clock Synthesizer Considerations for Universal Socket 370 Design ..................31

Table 5. Determining the Installed Processor via Hardware Mechanisms ........................35

Table 6. Intel® Pentium® III Processor AGTL/AGTL+ Parameters for Example

Calculations ................................................................................................................44

Table 7. Example T Table 8. Example T

Table 9. Trace Guidelines for Figure 19

Calculations for 133 MHz Bus

FLT_MAX

Calculations (Frequency Independent) ....................................45

FLT_MIN

1, 2, 3

....................................................................46

..............................................45

Table 10. Trace Width:Space Guidelines ..........................................................................46

Table 11. Routing Guidelines for Non-AGTL/Non-AGTL+ Signals....................................49

Table 12. Processor Pin Definition Comparison................................................................52

Table 13. Resistor Values for CLKREF Divider (3.3V Source).......................................... 57

Table 14. RESET#/RESET2# Routing Guidelines (see Figure 25)...................................58

Table 15. Component Recommendations – Inductor ........................................................61

Table 16. Component Recommendations – Capacitor .....................................................61

Table 17. Component Recommendation – Resistor .........................................................61

Table 18. System Memory 2-DIMM Solution Space..........................................................71

Table 19. System Memory 3-DIMM Solution Space..........................................................74

Table 20. AGP 2.0 Signal Groups .....................................................................................83

Table 21. AGP 2.0 Data/Strobe Associations....................................................................83

Table 22. AGP 2.0 Routing Summary ...............................................................................87

Table 23. AGP 2.0 Routing Summary ...............................................................................91

Table 24. TYPDET#/VDDQ Relationship ..........................................................................93

Table 25. Connector/Add-in Card Interoperability .............................................................98

Table 26. Voltage/Data Rate Interoperability.....................................................................98

Table 27. AC’97 Configuration Combinations .................................................................119

Table 28. Intel Table 29. Intel

CK-815 (2-DIMM) Clocks .......................................................................131

CK-815 (3-DIMM) Clocks .......................................................................133

Table 30. Simulated Clock Routing Solution Space ........................................................136

Table 31. Simulated Clock Skew Assumptions ...............................................................138

Table 32. Power Delivery Terminology............................................................................141

Table 33. Power Sequencing Timing Definitions .............................................................151

Table 34. Recommendations For Unused AGP Port ......................................................159

10 Intel

815 Chipset Platform Design Guide

Revision History

Rev. No. Description Date

-001 Initial Release. April 2001

815 Chipset Platform Design Guide 11

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12 Intel

815 Chipset Platform Design Guide

Introduction

1 Introduction

This design guid e organizes Int el’s design reco mmendat ions for the Intel® 815 chipset platform for use with the Universal Socket 370. In addition to providing motherboard design recommendations (e.g., layout and routing guid elines), this document also addresses system design issues (e.g., thermal requirements).

This document contains design recommendations, board schematics, debug recommendatio ns, and a system checklist. These design guidelines have been developed to ensure maximum flexibility for board designers, while reducing the risk of board-related issues.

Board designers can use the schematics in Appendix A: Customer Reference Board (CRB) as a reference. While the schematics cover specific designs, the core schematics will remain the same for most Intel 815 chipset designs for use with the Universal Socket 370. Consult the debug recommendations when debugging your design. However, these debug recommendations should be understood before completing board design, to ensure that the debug port, in addition to other debug features, are implemented correctly.

The Intel 815 chipset platform supports the following processors:

• Intel

Pentium® III processor based on 0.18 micron technology (CPUID = 068xh).

Celeron™ processor based on 0.18 micron technology (CPUID = 068xh). This applies

to Celeron 533A MHz and ≥566 MHz processors

• Future 0.13 micron socket 370 processors

Note: The system bus speed supported by the design is based on the capabilities of the processor,

chipset, and clock driver.

Note: The Intel 815 chipset for use with the universal socket 370 is not compatible with the

Intel

Pentium® II processor (CPUID = 066xh) 370-pin socket.

815 Chipset Platform Design Guide 13

Intel

Introduction

1.1 Terminology

This section describes some of the terms used in this document. Additional power delivery term definitions are provided at the beginning of Chapter 12, Power Delivery.

Term Description

Aggressor A network that transmits a coupled signal to another network is called the

AGP Accelerated Graphics Port

AGTL/AGTL+ Refers to processor bus signals that are implemented using either Assisted

Bus Agent A component or group of components that, when combined, represent a single

Crosstalk The reception on a victim network of a signal imposed by aggressor network(s)

GMCH Graphics and Memory Controller Hub. A component of the Intel® 815 chipset

aggressor network.

Gunning Transceiver Logic (AGTL+) or its lower voltage variant (AGTL), depending on which processor is being used.

load on the AGTL+ bus.

through inductive and capacitive coupling between the networks.

• Backward Crosstalk–coupling that creates a signal in a victim network that

travels in the opposite direction as the aggressor’s signal.

• Forward Crosstalk–coupling that creates a signal in a victim network that travels

in the same direction as the aggressor’s signal.

• Even Mode Crosstalk–coupling from single or multiple aggressors when all the

aggressors switch in the same direction that the victim is switching.

• Odd Mode Crosstalk–coupling from single or multiple aggressors when all the

aggressors switch in the opposite direction that the victim is switching.

platform for use with the Universal Socket 370

ICH Intel® 82801AA I/O Controller Hub component.

ISI Inter-symbol interference is the effect of a previous signal (or transition) on the

Network Length The distance between agent 0 pins and the agent pins at the far end of the bus.

Pad The electrical contact point of a semiconductor die to the package substrate. A

Pin The contact point of a component package to the traces on a substrate such as

14 Intel

interconnect delay. For example, when a signal is transmitted down a line and the reflections due to the transition have not completely dissipated, the following data transition launched onto the bus is affected. ISI is dependent upon frequency, time delay of the line, and the reflection coefficient at the driver and receiver. ISI can impact both timing and signal integrity.

pad is only observable in simulation.

the motherboard. Signal quality and timings can be measured at the pin.

815 Chipset Platform Design Guide

Introduction

Term Description

Ringback The voltage that a signal rings back to after achieving its maximum absolute

Setup Window The time between the beginning of Setup to Clock (T

SSO Simultaneous Switching Output (SSO) Effects refers to the difference in electrical

Stub The branch from the bus trunk terminating at the pad of an agent.

System Bus The system bus is the processor bus.

Trunk The main connection, excluding interconnect branches, from one end agent pad

Undershoot Minimum voltage observed for a signal to extend below VSS at the device pad.

Universal Socket 370 Refers to the Intel 815 chipset using the “universal” PGA370 socket. In general,

value. Ringback may be due to reflections, driver oscillations, or other transmission line phenomena.

) and the arrival of a valid clock edge. This window may be different for each type of bus agent in the system.

timing parameters and degradation in signal quality caused by multiple signal outputs simultaneously switching voltage levels (e.g., high-to-low) in the opposite direction from a single signal (e.g., low-to-high) or in the same direction (e.g., high-to-low). These are respectively called odd-mode switching and even-mode switching. This simultaneous switching of multiple outputs creates higher current swings that may cause additional propagation delay (or “push-out”), or a decrease in propagation delay (or “pull-in”). These SSO effects may impact the setup and/or hold times and are not always taken into account by simulations. System timing budgets should include margin for SSO effects.

to the other end agent pad.

these designs support 66/100/133 MHz system bus operation, VRM 8.5 DC-DC converter guidelines, and Intel Pentium® III processor (CPUID=068xh), and future Pentium III processors in single-microprocessor based designs.

Celeron™ processors (CPUID=068xh), Intel

SU_MIN

Victim A network that receives a coupled crosstalk signal from another network is called

the victim network.

815 Chipset Platform Design Guide 15

Intel

Introduction

1.2 Reference Documents

Document Document Number

Intel® 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet

Intel® 82802AB/82802AC Firmware Hub (FWH) Datasheet 290658 Intel® 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub Datasheet 290655 Pentium® II Processor Developer’s Manual 243341

Pentium® III Processor Specification Update (latest revision from website) (http://developer.intel

AP 907 Pentium® III Processor Power Distribution Guidelines 245085 AP-585 Pentium® II Processor AGTL+ Guidelines 243330 AP-587 Pentium® II Processor Pow er Di stribution Guidelines 243332 Accelerated Graphics P ort Specification, Revision 2.0 (ftp://download.intel.c

PCI Local Bus Specification, Revision 2.2 Universal Serial Bus S pecification, Revision 1.0

/ Location

298351

.com/design/Pentium III/specupdt/)

om/technology/agp/d ownloads/agp20.pdf)

1.3 System Overview

The Intel 815 chipset for use with the Universal Socket 370 contains a Graphics Memory Controller Hub (GMCH) component and I/O Controller Hub (ICH) component for desktop platforms.

The GMCH provides the processor interface (optimized for the Pentium 068xh) and future 0.13 micron 370 socket processors), DRAM interface, hub interface, and an accelerated Graphics Port (AGP) interface or internal graphics. This product provides flexibility and scalability in graphics and memory subsystem performance. Competitive internal graphics may be scaled via an AGP card interface, and PC100 SDRAM system memory may be scaled to PC133 system memory.

The Accelerated Hub Architecture interface (i.e., the chipset component interconnect) is designed into the chipset to provide an efficient, high-bandwidth communication channel between the GMCH and the I/O controller hub. The chipset architecture also enables a security and manageability infrastructure through the Firmware Hub component.

An ACPI-compliant Intel 815 chipset platform for use with the universal socket 370 can support the Full-on (S0), Stop Grant (S1), Suspend to RAM (S3), Suspend to Disk (S4), and Soft-off (S5) power management states. The chipset also supports Wake-on-LAN troubleshooting. The chipset architecture removes the requirement of the ISA expansion bus that was traditionally integrated into the I/O subsystem of PCIsets/AGPsets. This removes many of the conflicts experienced when installing hardware and drivers into legacy ISA systems. The

III processor (CPUID =

for remote administration and

16 Intel

815 Chipset Platform Design Guide

Introduction

elimination of ISA provides true plug-and-play for the platform. Traditionally, the ISA interface was used for audio and modem devices. The addition of AC’97 allows the OEM to use software- configurable AC’97 audio and modem coder/decoders (codecs), instead of the traditional ISA devices.

1.3.1 System Features

The Intel 815 chipset for use with the Universal Socket 370 platform contains two components: the Intel

82815 Graphics and Memory Controller Hub (GMCH) and the Intel® 82801AA I/O Controller Hub (ICH). The GMCH integrates a 66/100/133 MHz, P6 family system bus controller, integrated 2D/3D graphics accelerator or AGP (2X/4X) discrete graphics card, 100/133 MHz SDRAM controller, and a high-speed accelerated hub architecture interface for communication with the ICH. The ICH integrates an Ultra ATA/66 controller, USB host controller, LPC interface controller, FWH interface controller, PCI interface controller, AC’97 digital controller, and a hub interface for communication with the GMCH.

Figure 1. System Block Diagram

AGP G raphics Card

Display Cache

(AGP in-line m emory

module)

Analog display out

Digital video out

Audio codec

Modem codec

AGP 2X/4X

2x USB

2x ID E

AC97

Chipset

Processor

66/100/133 MHz system bus

GMCH

(544 BGA)

Hub interface

ICH

PCI bus

LPC I/F

100/133 MHz

SDRAM

PCI slots

KBC /SIO

FWH Flash

BIOS

sys_blk

815 Chipset Platform Design Guide 17

Intel

Introduction

1.3.2 Component Features

Figure 2. GMCH Block Diagram

GPA

or AGP

2X/4X

card

AGP I/F

Local memory I/F

System bus (66/100/133 MHz)

Processor I/F

Data

stream

control & dispatch

Hub I/F

Hub

Primary display

Overlay

H/W cursor

3D pipelin e

2D (blit engine)

1.3.2.1 Graphics Memory Controller Hub (GMCH)

• Processor/System Bus Support  Optimized for Intel

frequency

 Support for Intel  Supports 32-bit AGTL or AGTL+ bus addressing  Supports uniprocessor systems  Utilizes AGTL and AGTL+ bus driver technology (gated AGTL/AGTL+ receivers for

reduced power)

Pentium® III processors (CPUID = 068xh) at 133 MHz system bus

Celeron™ processors (CPUID = 068xh); 66 MHz system bus

System

memory I/F

RAMDAC

FP / TVout

Internal graphics

comp_blk_1

SDRAM

100/133 MHz, 64 bit

Monitor

Digital

video out

• Integrated DRAM controller  32 MB to 512 MB using 16-Mb/64-Mb/128-Mb technology  Supports up to three double-sided DIMMS (six rows)  100 MHz, 133 MHz SDRAM interface  64-bit data interface  Standard Synchronous DRAM (SDRAM) support (x-1-1-1 access)  Supports only 3.3V DIMM DRAM configurations  No registered DIMM support  Support for symmetrical and asymmetrical DRAM addressing  Support for x8, x16 DRAM device width  Refresh mechanism: CAS-before-RAS only  Support for DIMM serial PD (presence detect) scheme via SMbus interface  STR power management support via self-refresh mode using CKE

18 Intel

815 Chipset Platform Design Guide

Introduction

• Accelerated Graphics Port (AGP) Interface  Supports AGP 2.0, including 4X AGP data transfers, but not the 2X/4X Fast Write

protocol

 AGP universal connector support via dual-mode buffers to allow AGP 2.0 3.3V or 1.5V

signaling

 32-deep AGP request queue  AGP address translation mechanism with integrated fully associative 20-entry TLB  High-priority access support  Delayed transaction support for AGP reads that can not be serviced immediately  AGP semantic traffic to the DRAM is not snooped on the system bus and is therefore not

coherent with the processor caches

• Integrated Graphics Controller  Full 2D/3D/DirectX acceleration  Texture-mapped 3D with point sampled, bilinear, trilinear, and anisotropic filtering  Hardware setup with support for strips and fans  Hardware motion compensation assist for software MPEG/DVD decode  Digital Video Out interface adds support for digital displays and TV-Out  PC99A/PC2001 compliant  Integrated 230 MHz DAC

• Integrated Local Graphics Memory Controller (Display Cache)  0 MB to 4 MB (via Graphics Performance Accelerator) using zero, one, or two parts  32-bit data interface  133 MHz memory clock  Supports ONLY 3.3V SDRAMs

• Packaging/Power  544 BGA with local memory port  1.85V (± 3% within margins of 1.795V to 1.9V) core and mixed 3.3V, 1.5V, and

AGTL/AGTL+ I/O

815 Chipset Platform Design Guide 19

Intel

Introduction

1.3.2.2 Intel® 82801AA I/O Controller Hub (ICH)

The I/O Controller Hub provides the I/O subsystem with access to the rest of the system, as follows:

• Upstream accelerated hub architecture interface for access to the GMCH

• PCI 2.2 interface (6 PCI Request/Grant pairs)

• Bus master IDE controller; supports Ultra ATA/66

• USB controller

• I/O APIC

• SMBus controller

• FWH interface

• LPC interface

• AC’97 2.1 interface

• Integrated system management controller

• Alert on LAN*

• IRQ controller

• Packaging/Power  241 BGA  3.3V core and 1.8V and 3.3V standby

1.3.2.3 Firmware Hub (FWH)

The hardware features of the firmware hub include:

• An integrated hardware Random Number Generator (RNG)

• Register-based locking

• Hardware-based locking

• 5 GPIs

• Packaging/Power  40-L TSOP and 32-L PLCC  3.3V core and 3.3V / 12V for fast programming

20 Intel

815 Chipset Platform Design Guide

Introduction

1.3.3 Platform Initiatives

1.3.3.1 Universal Socket 370 Design

The Intel 815 chipset platform for use with the Universal Socket 370 allows systems designers to build one system that is compatible with the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors. When implemented, the Intel 815 chipset platform for use with the Universal Socket 370 can detect which processor is present in the socket and function accordingly.

1.3.3.2 PC 133

The Intel PC133 initiative provides the memory bandwidth necessary to obtain high performance from the processor and AGP graphics controllers. The platform’s SDRAM interface supports 100 MHz and 133 MHz operations. The latter delivers 1.066 GB/s of theoretical memory bandwidth compared with the 800-MB/s theoretical memory bandwidth of 100 MHz SDRAM systems.

1.3.3.3 Accelerated Hub Architecture Interface

As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge becomes significant. With the addition of AC’97 and Ultra ATA/66, coupled with the existing USB, I/O requirements could affect PCI bus performance. The chipset platform’s accelerated hub architecture ensures that the I/O subsystem, both PCI and integrated I/O features (IDE, AC’97, USB), receives adequate bandwidth. By placing the I/O bridge on the accelerated hub architecture interface instead of PCI, I/O functions integrated into the ICH and the PCI peripherals are ensured the bandwidth necessary for peak performance.

1.3.3.4 Internet Streaming SIMD Extensions

The Pentium III processor (CPUID = 068xh) provides 70 new SIMD (single-instruction, multipledata) instructions. The new extensions are floating-point SIMD extensions. Intel technology provides integer SIMD instructions. The Internet Streaming SIMD extensions complement the MMX technology SIMD instructions and provide a performance boost to floatingpoint-intensive 3D applications.

1.3.3.5 AGP 2.0

The AGP 2.0 interface allows graphics controllers to access main memory at more than 1 GB/s, which is twice the bandwidth of previous AGP platforms. AGP 2.0 provides the infrastructure necessary for photorealistic 3D. In conjunction with the Internet Streaming SIMD Extensions, AGP 2.0 delivers the next level of 3D graphics performance.

MMX™

815 Chipset Platform Design Guide 21

Intel

Introduction

1.3.3.6 Manageability

The Intel 815 chipset platform integrates several functions designed to manage the system and lower the system’s total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lock-ups, without the aid of an external microcontroller.

TCO Timer

The ICH integrates a programmable TCO Timer. This timer is used to detect system locks. The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the timer causes a system reset to recover from a hardware lock.

Processor Present Indicator

The ICH looks for the processor to fetch the first instruction after reset. If the processor does not fetch the first instruction, the ICH will reboot the system.

Function Disable

The ICH provides the ability to disable the following functions: AC’97 Modem, AC’97 Audio, IDE, USB, and SMBus. Once disabled, these functions no longer decode I/O, memory or PCI configuration space. Also, no interrupts or power management events are generated by the disabled funct ions.

Intruder Detect

The ICH provides an input signal (INTRUDER#) that can be attached to a switch that is activated when the system case is opened. The ICH can be programmed to generate an SMI# or TCO event as the result of an active INTRUDER# signal.

Alert on LAN*

The ICH supports Alert on LAN. In response to a TCO event (intruder detect, thermal event, processor boot failure), the ICH sends a hard-coded message over the SMBus. A LAN controller supporting the Alert on LAN protocol can decode this SMBus message and send a message over the network to alert the network manager.

22 Intel

815 Chipset Platform Design Guide

Introduction

1.3.3.7 AC’97

The Audio Codec ’97 (AC’97) specification defines a digital interface that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC) or both an AC and an

MC. The AC’97 specification defines the interface between the system logic and the audio or modem codec, known as the AC’97 Digital Link.

The chipset platform’s AC’97 (with the appropriate codecs) not only replaces ISA audio and modem functionality, but also improves overall platform integration by incorporating the AC’97 digital link. Using the chipset’s integrated AC’97 digital link reduces cost and eases migration from ISA.

The ICH is an AC’97-compliant controller that supports up to two codecs, with independent PCI functions for audio and modem. The ICH communicates with the codec(s) via a digital serial link called the AC-link. All digital audio/modem streams and command/status information are communicated over the AC-link. Microphone input and left and right audio channels are supported for a high-quality, two-speaker audio solution. Wake-on-ring-from-suspend also is supported with an appropriate modem codec.

By using an audio codec, the AC’97 digital link allows for cost-effective, high-quality, integrated audio. In addition, an AC’97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC’97. The chipset platform’s integrated digital link allows two external codecs to be connected to the ICH. The system designer can provide audio with an audio codec or a modem with a modem codec. For systems requiring both audio and a modem, there are two solutions: the audio codec and the modem codec can be integrated into an AMC, or separate audio and modem codecs can be connected to the ICH.

Modem implementation for different countries must be taken into consideration, as telephone systems may vary. By implementing a split design, the audio codec can be on board and the modem codec can be placed on a riser. Intel is developing an AC’97 digital link connector. With a single integrated codec, or AMC, both audio and modem can be routed to a connector near the rear panel where the external ports can be located.

1.3.3.8 Low-Pin-Count (LPC) Interface

In the Intel 815 chipset platform, the Super I/O (SIO) component has migrated to the Low-PinCount (LPC) interface. Migration to the LPC interface allows for lower-cost Super I/O designs. The LPC Super I/O component requires the same feature set as traditional Super I/O components. It should include a keyboard and mouse controller, floppy disk controller, and serial and parallel ports. In addition to the Super I/O features, an integrated game port is recommended, because the AC’97 interface does not provide support for a game port. In systems with ISA audio, the game port typically existed on the audio card. The fifteen-pin game port connector provides for two joysticks and a two-wire MPU-401 MIDI interface. Consult your preferred Super I/O vendor for a comprehensive list of the devices offered and the features supported.

In addition, depending on system requirements, specific system I/O requirements may be integrated into the LPC Super I/O. For example, a USB hub may be integrated to connect to the ICH USB output and extend it to multiple USB connectors. Other SIO integration targets include a device bay controller or an ISA-IRQ-to-serial-IRQ converter to support a PCI-to-ISA bridge. Contact your Super I/O vendor to ensure the availability of the desired LPC Super I/O features.

815 Chipset Platform Design Guide 23

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Introduction

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24 Intel

815 Chipset Platform Design Guide

General Design Considerations

2 General Design Considerations

This document provides motherboard layout and routing guidelines for systems based on the Intel 815 chipset platform for use with the Universal Socket 370. The document does not discuss the functional aspects of any bus or the layout guidelines for an add-in device.

If the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations be completed for each design. Even when the guidelines are followed, it is recommended that critical signals be simulated to ensure proper signal integrity and flight time. Any deviation from these guidelines should be simulated.

The trace impedance typically noted (i.e., 60 Ω ± 15%) is the “nominal” trace impedance for a 5-mil-wide trace. That is, it is the impedance of the trace when not subjected to the fields created by changing current in neighboring traces. When calculating flight times, it is important to consider the minimum and maximum impedance of a trace, based on the switching of neighboring traces. Using wider spaces between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce the settling time.

Coupling between two traces is a function of the coupled length, the distance separating the traces, the signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects of trace-to-trace coupling, the routing guidelines documented in this section should be followed.

Additionally, the routing guidelines in this document are created using a PCB stack-up similar to that described in the following section.

2.1 Nominal Board Stackup

The Intel 815 chipset platform requires a board stack-up yielding a target impedance of 60 Ω ± 15%, with a 5-mil nominal trace width. Figure 3 shows an example stack-up that achieves this. It is a 4-layer printed circuit board (PCB) construction using 53%-resin, FR4 material.

Figure 3. Board Construction Example for 60 ΩΩΩΩ Nominal Stackup

Component-side layer 1: ½ oz. Cu

4.5-mil prepreg

Power plane layer 2: 1 oz. Cu

~48-mil Core

Ground layer 3: 1 oz. Cu

4.5-mil prepreg

Solder-side layer 4: ½ oz. Cu

Total thickness:

62 mils

board_4.5mil_stackup

815 Chipset Platform Design Guide 25

Intel

General Design Considerations

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26 Intel

815 Chipset Platform Design Guide

Component Quadrant Layouts

3 Component Quadrant Layouts

Figure 4 illustrates the relative signal quadrant locations on the GMCH ballout. It does not represent the actual ballout. Refer to the Intel

815 Chipset Family: 82815 Graphics and Memory

Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for the actual ballout.

Figure 4. GMCH 544-Ball µµµµBGA* CSP Quadrant Layout (Top View)

Pin 1

corner

System Memory

GMCH

Hub Interface

AGP / Display

Cache

System Bus

Video

quad_GMCH

815 Chipset Platform Design Guide 27

Intel

Component Quadrant Layouts

Figure 5 illustrates the relative signal quadrant locations on the ICH ballout. It does not represent the actual ballout. Refer to the Intel

82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub

Datasheet for the actual ballout.

Figure 5. ICH 241-Ball µµµµBGA* CSP Quadrant Layout (Top View)

Pin 1 corner

PCI

ICH

AC'97,

SMBus

Processor

Hub interface

Figure 6. Firmware Hub (FWH) Packages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

FWH interface

(40-lead TSOP)

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

LPC

IDE

1234323130

14 15 16 17 18 19 20

FWH interface

(32-lead PLCC,

0.450" x 0.550")

Top view

quad_ICH

28 Intel

pkg_FWH

815 Chipset Platform Design Guide

Universal Socket 370 Design

4 Universal Socket 370 Design

4.1 Universal Socket 370 Definitions

The universal socket 370 platform supports Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) as well as future 0.13 micron socket 370 processors. The Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) have different requirements for functioning properly in a platform than the future 0.13 micron socket 370 processors. It is necessary to understand these differences and how they affect the design of the platform. Refer to Table 1 through Table 4 for a high-level description of the differenc es that require additional circuitry on the motherboard. Specific details on implementing this circuitry are discussed further in this chapter. For a detailed description of the differences between the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processor pins, refer to Section 5.4.

Table 1. Processor Considerations for Universal Socket 370 Design

Signal

Name or

Number

AF36 VSS No connect Addition of circuitry that generates a

AG1 VSS VTT Addition of FET switch to ground or VTT,

AJ3 VSS RESET Addition of stuffing option for pull-down to

AK22 GTL_REF VCMOS_REF Addition of resistor-divider network to provide

PICCLK Requires 2.5V Requires 2.0V Addition of FET switch to provide proper

Function In

Pentium®

Intel

III Processor

(CPUID=068xh)

and Intel Celeron™

Processor

(CPUID=068xh)

Function In

Future

0.13 Micron Socket 370

Processors

Universal Socket 370 Design

processor identification signal used to configure board-level operation.

controlled by processor identification signal. Note: FET must have no more than 100

milliohms resistance between source and drain.

ground, which lets designer prevent future

0.13 micron socket 370 processors from being used with incompatible stepping of

Intel

82815 GMCH.

1.0V, which will satisfy voltage tolerance requirements of the Intel processor (CPUID=068xh) and Intel Celeron™ processor (CPUID=068xh) as well as future 0.13 micron socket 370 processors.

voltage, controlled by processor identification signal.

Implementation for

Pentium® III

815 Chipset Platform Design Guide 29

Intel

Universal Socket 370 Design

Signal

Name or

Number

Function In

Pentium®

Intel

III Processor

(CPUID=068xh)

and Intel Celeron™

Processor

(CPUID=068xh)

Function In

Future

0.13 Micron Socket 370

Processors

Implementation for

Universal Socket 370 Design

PWRGOOD Requires 2.5V Requires 1.8V Addition of resistor-divider network to provide

VTT Requires 1.5V Requires 1.25V Modification to VTT generation circuit to

VTTPWRGD Not used Input signal to

future

0.13 micron socket 370 processors to indicate that VID signals are stable

2.1V, which will satisfy voltage tolerance requirements of the Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) as well as future 0.13 micron socket 370 processors.

switch between 1.5V or 1.25V, controlled by processor identification signal.

Addition of VTTPWRGD generation circuit.

Table 2. GMCH Considerations for Universal Socket 370 Design

Name/Number

SMAA12 New strap required for determining

Pentium (CPUID=068xh) and Intel Processor (CPUID=068xh)

Future 0.13 micron socket 370 processors

Issue Implementation For

Addition of FET switch controlled by

III Processor

Celeron™

processor identification signal.

Universal Socket 370 Design

Table 3. ICH Considerations for Universal Socket 370 Design

Signal Issue Implementation For

PWROK GMCH and Intel® CK-815 must not

sample BSEL[1:0] until VTTPWRGD asserted. ICH must not initialize before Intel CK-815 clocks stabilize

30 Intel

Universal Socket 370 Design

Addition of circuitry to have VTTPWRGD gate PWROK from power supply to ICH. The ICH will hold the GMCH in reset until VTTPWRGD asserted plus 20 ms time delay to allow Intel CK-815 clocks to stabilize.

815 Chipset Platform Design Guide

Universal Socket 370 Design

Table 4. Clock Synthesizer Considerations for Universal Socket 370 Design

Signal Issue Implementation For

VDD Intel® CK-815 does not support

VTTPWRGD

Universal Socket 370 Design

Addition of FET switch which supplies power to VDD only when VTTPWRGD is asserted.

Note: FET must have no more than

100 milliohms resistance between source and drain.

4.2 Processor Design Requirements

4.2.1 Use of Universal Socket 370 Design with Incompatible GMCH

The universal socket 370 design is intended for use with the Intel 815 chipset platform for use with the universal socket 370. A universal socket 370 design populated with an earlier stepping of the GMCH is not compatible with future 0.13 micron socket 370 processors and, if used, will cause eventual failure of these processors. To prevent a future 0.13 micron socket 370 processor from being used with an incompatible stepping of the GMCH, the recommendation is to lay out the site for a 0 Ω pull-down to ground on processor pin AJ3. This pin is a RESET# signal on future

0.13 micron socket 370 processors and, by populating the resistor, these future processors will be prevented from functioning when placed in a board with an incompatible stepping of the GMCH. All Pentium III (CPUID=068xh) and Celeron (CPUID=068xh) processors will continue to boot normally. Not populating the resistor will allow future 0.13 micron socket 370 processors to boot. Refer to Figure 7 for an example implementation.

Figure 7. Future 0.13 Micron Socket 370 Processor Safeguard for Universal Socket 370

Designs Using A-2 GMCH

Future 0.13 Micron

Socket 370 Processors

AJ3

Ω

Tual_pin_aj3

815 Chipset Platform Design Guide 31

Intel

Universal Socket 370 Design

4.2.2 Identifying the Processor at the Socket

For the platform to configure for the requirements of the processor in the socket, it must first identify whether the processor is a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), or a future 0.13 micron socket 370 processors. Pin AF36 is a ground pin on a Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh); pin AF36 is an unconnected pin on future 0.13 micron Socket 370 processors. Referring to Figure 8, the platform uses a detect circuit connected to this processor pin. If a future 0.13 micron Socket 370 processor is present in the socket, the TUAL5 reference schematic signal will be pulled to the 5V rail and the TUAL5# reference schematic signal will be pulled to ground. Otherwise, for a Pentium III processor (CPUID=068xh) or Celeron processor (CPUID=068xh), the TUAL5 reference schematic signal will be pulled to ground and the TUAL5# will be pulled to the 5V rail.

Figure 8. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit

VCC5

Processor Pin

AF36

1 KΩ

VTT

VCC5

2.2 KΩ

NPN

2.2 KΩ

MOSFET N

TUAL5#

Proc_Detect

TUAL5

32 Intel

815 Chipset Platform Design Guide

Universal Socket 370 Design

4.2.3 Setting the Appropriate Processor VTT Level

Because the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors require different VTT levels, the platform must be able to provide the appropriate voltage level after determining which processor is in the socket. Referring to Figure 9, the TUAL5 reference schematic signal serves to control the FET, and by doing so determines whether the voltage regulator supplies 1.25V or 1.5V to VTT for AGTL or AGTL+, respectively.

Figure 9. VTT

Selection Switch

VCC3_3

µF

LT1587-ADJ

Vin

TUAL5

Vout

ADJ

µF

0.1

MOSFET N

49.9 1%

10 1%

VTT

Ω

µF

Tantalum

Ω

Vtt_Sel_Sw

815 Chipset Platform Design Guide 33

Intel

Universal Socket 370 Design

4.2.4 VTT Processor Pin AG1

Processor pin AG1 requires additional attention since it is a ground pin on a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) and a VTT pin on a future 0.13 micron socket 370 processor. A separate switch controlled by the TUAL5 reference schematic signal determines whether pin AG1 is pulled to ground or VTT. Refer to Figure 10 for an example implementation.

Figure 10. Switching Pin AG1

TUAL5

VTT

1 KΩ

Note: The FET must have no m ore than 100 milliohms resistance between the source and the drain.

4.2.5 Identifying the Processor at the GMCH

The GMCH determines whether the socket contains a future 0.13 micron socket 370 processor or Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) based on the input to pin SMAA12 on the GMCH. In a system using future 0.13 micron socket 370 processors, SMAA12 will be pulled down during reset to indicate to the GMCH that a future 0.13 micron socket 370 processor is in the socket. Refer to Figure 11. for an example implementation.

Processor Pin AG1

AG1_Switch

34 Intel

815 Chipset Platform Design Guide

Universal Socket 370 Design

Figure 11. Processor Identification Strap on GMCH

SMAA[12]

10 KΩ

TUAL5

Proc_ID_Strap

Table 5 provides the logic decoding to determine which processor is installed in a PGA370 design.

Table 5. Determining the Installed Processor via Hardware Mechanisms

Processor

Pin AF36

Hi-Z 0 Future 0.13 micron socket 370 processor installed.

Low 0 Intel® Pentium® III processor (CPUID=068xh) or Intel® Celeron™

X 1 No processor installed.

CPUPRES# Notes

processor (CPUID=068xh) installed.

815 Chipset Platform Design Guide 35

Intel

Universal Socket 370 Design

4.2.6 Configuring Non-VTT Processor Pins

When asserted, the VTTPWGRD signal must be level-shifted to 12V to properly drive the gating circuitry of the Intel

CK-815. Furthermore, while the VTTPWRGD signal is connected to the VTTPWRGD pin on a future 0.13 micron socket 370 processor, on a Pentium III processor (CPUID=068xh) or Celeron processor (CPUID=068xh) that same pin is a ground. To provide proper functionality, a 1.0 kΩ resistor must be placed in series between the circuitry that generates the signal VTTPWRGD and the processor pin VTTPWRGD. Refer to Figure 12 for an example implementation. Voltage regulators that generate the standard VTTPWRGD signal are available.

Figure 12. VTTPWRGD Configuration Circuit

VCC5

BAT54C

231

V1_8SB

732 1%

1 1%

ΚΩ

Ω

VTT

VCC5

Vcc

IN+ 1

Out 1

IN- 1

Gnd

LM393 Ch 1

20 K

VCC5

Ω

2.0 ms de lay nominal

V1_8SB

µF

0.1

ASSERTED

LOW

IN+ 2

Out 2

IN- 2

LM393 Ch2

1 K

VCC5

Ω

2.2 K

MOSFET N

VCC12

Ω

MOSFET N

VTTPW RGD12

VTT

1 KΩ

VTTPWRGD5#

VTTPWRGD

1 K

Ω

VTTPWRGD_Config

NOTE: The diode is included so that repeated pressing of the reset or power button does not cause the

capacitor to build up enough charge to circumvent the 20 ms delay.

36 Intel

815 Chipset Platform Design Guide

Universal Socket 370 Design

4.2.7 VCMOS Reference

In previous platforms supporting the Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh), VCMOS was generated by the processor itself. The future 0.13 micron socket 370 processors do not generate VCMOS, and the universal platform is required to generate this separately on the motherboard. Processor pin AK22, which is a GTL_REF pin on a Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh), has been changed to a VCMOS_REF pin on future 0.13 micron socket 370 processors. Referring to Figure 13, a network of resistors and a capacitor must be added so that this pin operates appropriately for whichever processor is in the socket.

Figure 13. GTL_REF/VCMOS_REF Voltage Divider Network

VCMOS

75 Ω 1%

150 1%

Processor Pin AK22

Ω

0.1

µF

GTL_CMOS_Ref

815 Chipset Platform Design Guide 37

Intel

Universal Socket 370 Design

4.2.8 Processor Signal PWRGOOD

The processor signal PWRGOOD is specified at different voltage levels depending on whether it is a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), or whether it is a future 0.13 micron socket 370 processor. As there is an overlap between the ranges of accepted voltage levels for these two processor groups, a resistor divider network that provides 2.1V will satisfy the requirements of all supported processors. See Figure 14 for an example implementation.

Figure 14. Resistor Divider Network for Processor PWRGOOD

VCC2_5

330

Ω

PW RGOO D from ICH 2

1.8 ΚΩ

PWRGOOD to Processor

PWRGOO D_Divider

38 Intel

815 Chipset Platform Design Guide

Universal Socket 370 Design

4.2.9 APIC Clock Voltage Switching Requirements

The processor’s APIC clock is also specified at different voltage levels depending on whether it is for the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) or whether it is for a future 0.13 micron socket 370 processor. There is no overlap in the range of accepted voltage levels for the two processor groups, so a voltage switch is required to ensure proper operation. Figure 15 shows an example implementation.

Figure 15. Voltage Switch For APIC Clock from Clock Synthesizer to Processor

IOAPIC

30 Ω

APICCLK_CPU

130 Ω

MOSFET N

NOTE: The 30 Ω resistor represents the series resistor typically used in connecting the APIC clock to the

processor.

TUAL5

API_CLK_SW

815 Chipset Platform Design Guide 39

Intel

Universal Socket 370 Design

4.2.10 GTLREF Topology and Layout

In a platform supporting the future 0.13 micron socket 370 processors, the voltage requirements for GTLREF are different for the processor and the chipset. The GTLREF on the processor is specified to be 2/3 * VTT, while the GTLREF on the chipset is 0.7 * VTT. This difference requires that separate resistor sites be added to the layout to split the GTLREF sources. In a universal motherb oard design, a Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) will be unaffected by the difference in GTLREF. The recommended GTLREF circuit topology is shown in Figure 16.

Note: If an A-2 stepping of the GMCH is used with the universal motherboard design, the GTLREF for

the GMCH should be set at 2/3 * VTT. This requires changing the 63.4 Ω, 1% resistor on the GMCH side to 75 Ω, 1%.

Figure 16. GTLREF Circuit Topology

VTT

63.4 Ω 75 Ω

ProcessorGMCH

150 Ω 150 Ω

gtlref_circuit

GTLREF Layout and Routing Guidelines

• Place all resistor sites for GTLREF generation close to the GMCH.

• Route GTLREF with as wide a trace as possible.

• Use one 0.1 µF decoupling capacitor for every two GTLREF pins at the processor (four

capacitors total). Place as close as possible (within 500 mils) to the Socket 370 GTLREF pins.

• Use one 0.1 µF decoupling capacitor for each of the two GTLREF pins at the GMCH

(two capacitors total). Place as close as possible to the GMCH GTLREF balls.

Given the higher GTLREF level fo r the GMCH, a debug test hook should be added for validation purposes. The debug test hook should be placed on the processor signal ADS# and consists of laying down the site for a 56 Ω pull-up to VTT. The resistor site should be located within 150 mils of the GMCH, and placed as close to the ADS# signal trace as possible.

40 Intel

815 Chipset Platform Design Guide

Universal Socket 370 Design

4.3 Power Sequencing on Wake Events

In addition to the mechanism for identifying the processor in the socket, special handling of wake events is required for the Intel 815 chipset platform that support functionality of the future

0.13 micron socket 370 processors. When a wake event is triggered, the GMCH and the Intel CK-815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by setting up the following sequence of events:

1. Power is not connected to the Intel CK-815-compliant clock driver until VTTPWRGD12 is

asserted.

2. Clocks to the ICH stabilize before the power supply asserts PWROK to the ICH. There is no

guarantee this will occur as the implementation for the previous step relies on the 12V supply. Thus, it is necessary to gate PWROK to the ICH from the power supply while the Intel CK-815 is given sufficient time for the clocks to become stable. The amount of time required is a minimum 20 ms.

3. ICH takes the GMCH out of reset.

4. GMCH samples BSEL[1:0]. Intel CK-815 will have sampled BSEL[1:0] much earlier.

4.3.1 Gating of Intel® CK-815 to VTTPWRGD

System designers must ensure that the VTTPWRGD signal is asserted before the Intel CK-815compliant clock driver receives power. This is handled by having the 3.3V rail of the clock driver gated by the VTTPWRGD12 reference schematic signal. Unlike previous Intel 815 chipset designs, the 3.3V standby rail is not used to power the clock as the VTTPWRGD12 reference schematic signal will cut power to the clock when going into any sleep state. Refer to Figure 17 for an example implementation.

Figure 17. Gating Power to Intel

VTTPW RGD12

Note: The FET must have no more than 100 milliohm s resistan ce between the source and the drain.

CK-815

VCC3_3

MOSFET N

VDD on CK-815

Gating_Pwr

815 Chipset Platform Design Guide 41

Intel

Universal Socket 370 Design

4.3.2 Gating of PWROK to ICH

With power being gated to the Intel CK-815 by the signal VTTPWRGD12, it is important that the clocks to the ICH are stable before the power supply asserts PWROK to the ICH. As the clocking power gating circuitry relies on the 12V supply, there is no guarantee that these conditions will be met. This is why an estimated minimum time delay of 20 ms must be added after power is connected to the Intel CK-815 to give the clock driver sufficient time to stabilize. This time delay will gate the power supply’s assertion of PWROK to the ICH. After the time delay, the power supply can safely assert PWROK to the ICH, with the ICH subsequently taking the GMCH out of reset. Refer to Figure 18 for an example implementation.

Figure 18. PWROK Gating Circuit For ICH

VDD on CK-815

43 kΩ

1.0 µF

NOTE: The diode is included so that repeated pressing of the reset or power button does not cause the

capacitor to build up enough charge to circumvent the 20 ms delay.

VCC3_3

PWROK

Note: Delay 20 ms after VDD on CK-815 is powered

ICH_PWROK

8.2 kΩ

ICH_PWROK_GATING

42 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

5 System Bus Design Guidelines

The Pentium III processor delivers higher performance by integrating the Level-2 cache into the processor a nd running it at the pr ocessor’s core speed. T he Pentium III processor runs at higher core and system bus speeds than previous-generation Intel hardware and software compatibility with earlier Pentium III processors. The new Flip Chip-Pin Grid Array 2 (FC-PGA2) package technology enables compatibility with previous Flip Chip-Pin Grid Array (FC-PGA) packages using the PGA370 socket.

This section presents the considerations for designs capable of using the Intel 815 chipset platform with the full range of Pentium III processors using the PGA370 socket.

5.1 System Bus Routing Guidelines

IA-32 processors while maintaining

The following layout guide supports designs using Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors with the Intel 815 chipset platform for use with the universal socket 370. The solution covers system bus speeds of 66/100/133 MHz for the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors. All processors must also be configured to 56 Ω on-die termination.

5.1.1 Initial Timing Analysis

Table 6 lists the AGTL/AGTL+ component timings of the processors and GMCH defined at the pins.

Note: These timings are for reference only. Obtain each processor’s specifications from the respective

processor datasheet and the chipset values from the appropriate Intel 815 chipset datasheet.

815 Chipset Platform Design Guide 43

Intel

System Bus Design Guidelines

Table 6. Intel

NOTES:

Table 7 contains an example AGTL+ initial maximum flight time, and Table 8 contains an example minimum flight time calculation for a 133 MHz, uniprocessor system using the Pentium III processor and the Intel 815 chipset platform’s system bus. Note that assumed values were used for the clock skew and clock jitter.

Pentium® III Processor AGTL/AGTL+ Parameters for Example Calculations

IC Parameters Intel® Pentium® III Processor at 133 MHz System

Clock to Output maximum (T

Clock to Output minimum (T

Setup time (T

Hold time (T

)

CO_MAX

)

CO_MIN

) • 1.20 ns (for BREQ Lines)

SU_MIN

) • 1.0 ns (for 66/100/133 MHz system bus speeds) 0.10 ns 1

HOLD

1. All times in nanoseconds.

2. Numbers in table are for reference only. These timing parameters are subject to change. Check the

appropriate component datasheet for the valid timing parameter values.

3. T

= 2.65 ns assumes that the GMCH sees a minimum edge rate equal to 0.3 V/ns.

SU_MIN

• 3.25 ns (for 66/100/133 MHz system bus speeds) 4.1 ns 1, 2

• 0.40 ns (for 66/100/133 MHz system bus) 1.05 ns 1, 2

• 0.95 ns (for all other AGTL/AGTL+ Lines @

133 MHz)

• 1.20 ns (for all other AGTL/AGTL+ Lines @

66/100 MHz)

Bus

GMCH Notes

2.65 ns 1, 2,3

Note: The clock skew and clock jitter values depend on the clock components and the distribution

method chosen for a particular design and must be budgeted into the initial timing equations, as appropriate for each design.

Table 7and Table 8 were derived assuming the following:

• CLK

= 0.20 ns (Note: This assumes that the clock driver pin-to-pin skew is reduced to

SKEW

50 ps by tying the two host clock outputs t ogether (i.e., “ganging”) at t he clock driver output pins, and that the PCB clock routing skew is 150 ps. The system timing budget must assume

0.175 ns of clock driver skew if outputs are not tied together as well as the use of a clock driver that meets the Intel CK-815 Clock Synthesizer/Driver Specification.)

• CLK

See the respective processor’s datasheet, the appropriate Intel 815 chipset platform documentation, and the Intel

= 0.250 ns

JITTER

CK-815 Clock Synthesizer/Driver Specification for details on clock skew and jitter

specifications. Exact details regarding the host clock routing topology are provided with the platform design gui deline.

44 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

Table 7. Example T

Driver Receiver Clk Period2T

Processor GMCH 7.50 3.25 2.65 0.20 0.25 0.40 1.1

GMCH Processor 7.50 4.1 1.20 0.20 0.25 0.40 1.35

NOTES:

1. All times in nanoseconds

2. BCLK period = 7.50 ns at 133.33 MHz

Table 8. Example T

Driver Receiver T

Processor GMCH 0.10 0.20 0.40 0.10

GMCH Processor 1.00 0.20 1.05 0.15

NOTES: All times in nanoseconds

The flight times in Table 7 include margin to account for the following phenomena that Intel observed when multiple bits are switching simultaneously. These multi-bit effects can adversely affect the flight time and signal quality and sometimes are not accounted for during simulation. Accordingly, the maximum flight times depend on the baseboard design, and additional adjustment factors or margins are recommended.

Calculations for 133 MHz Bus 1

FLT_MAX

CO_MAXTSU_MIN

Calculations (Frequency Independent)

FLT_MIN

Clk

HOLD

SKEW TCO_MIN

Clk

SKEW

Recommended

FLT_MIN

JITTER MADJ

Recommended

FLT_MAX

• SSO push-out or pull-in

• Rising or falling edge rate degradation at the receiver caused by inductance in the current

return path, requiring extrapolation that causes additional delay

• Cross-talk on the PCB and inside the package which can cause variation in the signals

Additional effects exist that may not necessarily be covered by the multi-bit adjustment factor and should be budgeted as appropriate to the baseboard design. These effects are included as M in the example calculations in Table 7. Examples include:

• The effective board propagation constant (S

), which is a function of:

EFF

 Dielectric constant (εr) of the PCB material  Type of trace connecting the components (stripline or microstrip)

 Length of the trace and the load of the components on the trace. Note that the board

propagation constant multiplied by the trace length is a component of the flight time, but not necessarily equal to the flight time.

ADJ

815 Chipset Platform Design Guide 45

Intel

System Bus Design Guidelines

5.2 General Topology and Layout Guidelines

Figure 19. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)

GMCH

L(1): Z

= 60 Ω ± 15%

Table 9. Trace Guidelines for Figure 19

Description Min. Length (inches) Max. Length (inches)

GMCH to PGA370 socket trace 1.90 4.50

NOTES:

1. All AGTL/AGTL+ bus signals should be referenced to the ground plane for the entire route.

2. Use an intragroup AGTL/AGTL+ spacing : line width : dielectric thickness ratio of at least 2:1:1 for microstrip geometry. If routing could use 10-mil spacing, 5-mil traces, and a 5-mil prepreg between the signal layer and the plane it references (assuming a 4-layer motherboard design).

3. The recommended trace width is 5 mils, but not greater than 6 mils.

= 4.5, this should limit coupling to 3.4%. For example, intragroup AGTL+

Table 10 contains the trace width space ratios assumed for this topology. Three types of cross-talk are considered in this guideline: Intragroup AGTL/AGTL+, Intergroup AGTL/AGTL+, and AGTL/AGTL+ to non-AGTL/AGTL+. Intragroup AGTL/AGTL+ cross-talk involves interference between AGTL/AGTL+ signals within the same group. Intergroup AGTL/AGTL+ cross-talk involves interference from AGTL/AGTL+ signals in a particular group to AGTL/AGTL+ signals in a different group. An examp le o f AGTL/AGTL+ to non-AGTL/AGTL+ cross-talk is when CMOS and AGTL/AGTL+ signals interfere with each other. The AGTL/AGTL+ signals consist of the following groups: data signals, control signals, c lock signals, and address signals.

1, 2, 3

PGA370 socket

sys_bus_topo_PG A370

Table 10. Trace Width:Space Guidelines

Cross-Talk Type Trace Width:Space Ratios

Intragroup AGTL/AGTL+ signals (same group AGTL/AGTL+) 5:10 or 6:12

Intergroup AGTL/AGTL+ signals (different group AGTL/AGTL+) 5:15 or 6:18

AGTL/AGTL+ to System Memory Signals 5:30 or 6:36

AGTL/AGTL+ to non-AGTL/AGTL+ 5:25 or 6:24

NOTES:

1. Edge-to-edge spacing.

2. Units are in mils.

1, 2

46 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signal s

Ground Reference

It is strongly recommended that AGTL/AGTL+ signals be routed on the signal layer next to the ground layer (referenced to ground). It is important to provide an effective signal return path with low inductance. The best signal routing is directly adjacent to a solid GND plane with no splits or cuts. Eliminate parallel traces between layers not separated by a power or ground plane. If a signal has to go through routing layers, the recommendations a re in the following list.

Note: Following these layout rules is critical for AGTL/AGTL+ signal integrity, particularly for

0.18-micron and smaller process technology.

• For signals going from a ground reference to a power reference, add capacitors between

ground and power near the vias to provide an AC return path. One capacitor should be used for every three signal lines that change reference layers. Capacitor requirements are as follows: C=100 nF, ESR=80 mΩ, ESL=0.6 nH. Refer to Figure 20 for an example of switching reference layers.

• For signals going fr om one ground re ference to another, separate ground reference, add vias

between the two ground planes to provide a better return path.

Figure 20. AGTL/AGTL+ Trace Routing

GMCH Processor

Layer 2

Layer 3

Reference Plane Splits

Splits in reference planes disrupt signal return paths and increase overshoot/undershoot due to significantly increased inductance.

Processor Connector Breakout

It is strongly recommended that AGTL/AGTL+ signals do not traverse multiple signal layers. Intel recommends breaking out all signals from the connector on the same layer. If ro uting is tight, break out from the connector on the opposite routing layer over a ground reference and cross over to main signal layer near the processor connector.

0-500 mils

1.2V Power Plane

Ground Plane

1.5-3.5 inches

Socket Pin

AGTL_trace_route

815 Chipset Platform Design Guide 47

Intel

System Bus Design Guidelines

Minimizing Cross-Talk

The following general rules minimize the impact of cross-talk in a high-speed AGTL/AGTL+ bus design:

• Maximize the space between traces. Where possible, maintain a minimum of 10 mils

(assuming a 5-mil trace) between trace edges. It may be necessary to use tighter spacing when routing between component pins. When traces must be close and parallel to each other, minimize the distance that they are close together and maximize the distance between the sections when the spacing restrictions are relaxed.

• Avoid parallelism between signals on adjacent layers, if there is no AC reference plane

between them. As a rule of thumb, route adjacent layers orthogonally.

• Since AGTL/AGTL+ is a low-signal-swing technology, it is important to isolate

AGTL/AGTL+ signals from other signals by at least 25 mils. This will avoid coupling from signals that have lar ger voltage swings (e.g. , 5V PCI).

• AGTL/AGTL+ signals must be well isolated from system memory signals. AGTL/AGTL+

signal trace edges must be at least 30 mils from system memory trace edges within 100 mils of the ball of the GMCH.

• Select a board stack-up that minimizes the coupling between adjacent signals. Minimize the

nominal characteristic impedance within the AGTL/AGTL+ specification. This can be done by minimizing the height of the trace from its reference plane, which minimizes cross-talk.

• Route AGTL/AGTL+ address, data, and control signals in separate groups to minimize cross-

talk between groups. Keep at least 15 mils between each group of signals.

• Minimize the dielectric used in the system. This makes the traces closer to their reference

plane and thus reduces the cross-talk magnitude.

• Minimize the dielectric process variation used in the PCB fabrication.

• Minimize the cross-sectional area of the traces. This can be done by means of narrower traces

and/or by using thinner copper, but the trade-off for this smaller cross-sectional area is higher trace resistivity, which can reduce the falling-edge noise margin because of the I*R loss along the trace.

48 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals

Table 11. Routing Guidelines for Non-AGTL/Non-AGTL+ Signals

Signal Trace Width Spacing to Other Traces Trace Length

A20M# 5 mils 10 mils 1” to 9”

FERR# 5 mils 10 mils 1” to 9”

FLUSH# 5 mils 10 mils 1” to 9”

IERR# 5 mils 10 mils 1” to 9”

IGNNE# 5 mils 10 mils 1” to 9”

INIT# 5 mils 10 mils 1” to 9”

LINT[0] (INTR) 5 mils 10 mils 1” to 9”

LINT[1] (NMI) 5 mils 10 mils 1” to 9”

PICD[1:0] 5 mils 10 mils 1” to 9”

PREQ# 5 mils 10 mils 1” to 9”

PWRGOOD 5 mils 10 mils 1” to 9”

SLP# 5 mils 10 mils 1” to 9”

SMI# 5 mils 10 mils 1” to 9”

STPCLK 5 mils 10 mils 1” to 9”

THERMTRIP# 5 mils 10 mils 1” to 9”

NOTE: Route these signals on any layer or combination of layers.

815 Chipset Platform Design Guide 49

Intel

System Bus Design Guidelines

5.2.1.2 THRMDP and THRMDN

These traces (THRMDP and THRMDN) route the processor’s thermal diode connections. The thermal diode operates at very low currents and may be susceptible to cross-talk. T he traces should be routed close together to reduce loop area and inductance.

Figure 21. Routing for THRMDP and THRMDN

Signal Y

THRMDP

1 — Maximize (min. – 20 mils)

2 — Minimize

THRMDN

NOTES:

1. Route these traces parallel and equalize lengths within

2. Route THRMDP and THRMDN on the same layer.

1 — Maximize (min. – 20 mils)

Signal Z

bus_routing_thrmdp-thrmdn

±0.5 inch.

5.2.1.3 Additional Routing and Placement Considerations

• Distribute VTT with a wide trace. A 0.050 inch minimum trace is recommended to minimize

DC losses. Route the VTT trace to all components on the host bus. Be sure to include decoupling capacitors.

• The VTT voltage should be 1.5V ± 3% for static conditions, and 1.5V ± 9% for worst-case

transient conditions when the Pentium III processor (CPUID=068xh) or Celeron processor (CPUID=068xh) is present in the socket. If a future 0.13 micron so cket 370 processor is being used, the VTT voltage should then be 1.25V ± 3% for static conditions, and 1.25V ± 9% for worst-case transient conditions.

• Place resistor divider pairs for VREF generation at the GMCH component. VREF also is

delivered to the processor.

50 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

5.3 Electrical Differences for Universal PGA370 Designs

There are several electrical changes between previous PGA370 designs and the universal PGA370 design, as follows:

• Changes to the PGA370 socket pin definitions.

• Addition of VTTPWRGD signal to ensure stable VID selection for future 0.13 micron socket

370 processors.

• Addition of THERMTRIP circuit to allow processor to detect catastrophic overheat.

• Addition of VID[25 mV] signal to support future 0.13 micron socket 370 processors.

• Processor VTT level is switchable to 1.25V or 1.5V, depending on which processor is present

in the socket.

• In designs using future 0.13 micron socket 370 processors, the processor does not generate

_REF.

CMOS

5.3.1 THERMTRIP Circuit

Figure 22. Example Implementation of THERMTRIP Circuit

VCC1_8SB

R10

Ω

1 K

Thermtrip#

1.6 K

5.3.1.1 THERMTRIP Timing

When the THERMTRIP signal is asserted, both the VCC and VTT supplies to the processor must be turned off to prevent thermal runaway of the processor. The time required from THERMTRIP asserted to VCC rail at ½ nominal is 5 sec and THERMTRIP asserted to VTT rail at ½ nominal is 5 sec. System designers must ensure that the decoupling scheme used on these rails does not violate the THERMTRIP timing specifications.

VCC1.8

R11

Ω

1 K

Ω

Q2N3904

Can Use MBT3904 Dual XSTR Part

VCC3_3SB

R12

Ω

22 K

Ω

1 K

Q2N3904

Connect to ICH

SW_ ON#

Thermstrip

815 Chipset Platform Design Guide 51

Intel

System Bus Design Guidelines

5.4 PGA370 Socket Definition Details

The following table compares the pin names and functions of the Intel processors supported in the Intel 815 chipset platform for use with the universal socket 370.

Table 12. Processor Pin Definition Comparison

Pin # Pin Name

AA33 Reserved VTT VTT • AGTL/AGTL+ termination

AA35 Reserved VTT VTT • AGTL/AGTL+ termination

AB36 VCC

Intel

Celeron™

Processor

(CPUID=068xh)

VCC

CMOS

Pin Name

Intel® Pentium®

III Processor

(CPUID=068xh)

VTT • CMOS voltage level for Intel

CMOS

Pin Name

Future 0.13

Micron

Socket 370

Processors

Function

voltage

Pentium® III processor (CPUID=068xh) and Intel Celeron™ processor (CPUID=068xh).

• AGTL termination voltage for

future 0.13 micron socket 370 processors.

AD36 VCC1.5 VCC1.5 VTT • VCC1.5 for Pentium III

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• VTT for future 0.13 micron

socket 370 processors.

AF36 VSS VSS NC • Ground for Pentium III

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• No connect for future 0.13

micron socket 370 processors.

AG1

VSS VSS VTT • Ground for Pentium III

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• VTT for future 0.13 micron

socket 370 processors

AH4 Reserved RESET# RESET# • Processor reset for the

AH20 Reserved VTT VTT • AGTL/AGTL+ termination

Pentium III processor (068xh) and Future 0.13 micron socket 370 processors

voltage

52 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

Pin # Pin Name

AJ3

VSS VSS RESET • Ground for Pentium III

AK4 VSS VSS VTTPWRGD • Ground for Pentium III

AK16 Reserved VTT VTT • AGTL/AGTL+ termination

AK22 GTL_REF GTL_REF VCMOS_REF • GTL reference voltage for

AK36 VSS VSS VID[25mV] • Ground for Pentium III

AL13 Reserved VTT VTT • AGTL/AGTL+ termination

AL21 Reserved VTT VTT • AGTL/AGTL+ termination

AN3 GND GND DYN_OE • Ground for Pentium III

AN11 Reserved VTT VTT • AGTL/AGTL+ termination

AN15 Reserved VTT VTT • AGTL/AGTL+ termination

AN21 Reserved VTT VTT • AGTL/AGTL+ termination

Intel

Celeron™

Processor

(CPUID=068xh)

Pin Name

Intel® Pentium®

III Processor

(CPUID=068xh)

Pin Name

Future 0.13

Micron

Socket 370

Processors

Function

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• RESET for future 0.13 micron

socket 370 processors

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• VID control signal on future

0.13 micron socket 370 processors.

voltage

Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• CMOS reference voltage for

future 0.13 micron socket 370 processors

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• 25mV step VID select bit for

future 0.13 micron socket 370 processors

voltage

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• Dynamic output enable for

future 0.13 micron socket 370 processors

voltage

815 Chipset Platform Design Guide 53

Intel

System Bus Design Guidelines

Pin # Pin Name

Intel® Celeron™

Processor

(CPUID=068xh)

Pin Name

Intel® Pentium®

III Processor

(CPUID=068xh)

Pin Name

Future 0.13

Micron

Socket 370

Processors

Function

E23 Reserved VTT VTT • AGTL/AGTL+ termination

G35 Reserved VTT VTT • AGTL/AGTL+ termination

G37 Reserved Reserved VTT • Reserved for Pentium III

voltage

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• AGTL termination voltage for

future 0.13 micron socket 370 processors

N37

NC NC NCHCTRL • No connect for Pentium III

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• NCHCTRL for future 0.13

micron socket 370 processors

S33 Reserved VTT VTT • AGTL/AGTL+ termination

S37 Reserved VTT VTT • AGTL/AGTL+ termination

U35 Reserved VTT VTT • AGTL/AGTL+ termination

U37 Reserved VTT VTT • AGTL/AGTL+ termination

W3 Reserved A34# A34# • Additional AGTL/AGTL+

RESET# RESET2# VSS • Processor reset for Pentium III

voltage

address

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• Ground for future 0.13 micron

socket 370 processors

X6 Reserved A32# A32# • Additional AGTL/AGTL+

X342 VCC

VCC

CORE

VTT • Reserved for Pentium III

CORE

address

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• AGTL termination voltage for

future 0.13 micron socket 370 processors

54 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

Pin # Pin Name

Intel

Celeron™

Processor

(CPUID=068xh)

Pin Name

Intel® Pentium®

III Processor

(CPUID=068xh)

Pin Name

Future 0.13

Micron

Socket 370

Processors

Function

Y1 Reserved Reserved NC • Reserved for Pentium III

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• No connect for future 0.13

micron socket 370 processors

Y33 Reserved CLKREF CLKREF • 1.25V PLL reference

Z36

VCC2.5 VCC2.5 NC • VCC2.5 for Pentium III

processor (CPUID=068xh) and Celeron processor (CPUID=068xh).

• No connect for future 0.13

micron socket 370 processors

NOTES:

1. Refer to Chapter 4.

2. Refer to Section 13.2

815 Chipset Platform Design Guide 55

Intel

System Bus Design Guidelines

5.5 BSEL[1:0] Implementation Differences

A future 0.13 micron socket 370 processor will select the 133 MHz system bus frequency setting from the clock synthesizer. A Pentium III processor (CPUID=068xh) utilizes the BSEL1 pin to select either the 100 MHz or 133 MHz system bus frequency setting from the clock synthesizer. An Celeron processor (CPUID=068xh) will use both BSEL pins to select 66 MHz system bus frequency from the clock synthesizer. Processors in an FC-PGA or an FC-PGA2 are 3.3V tolerant for these signals, as are the clock and chipset.

Intel CK-815 has been designed to support selections of 66 MHz, 100 MHz, and 133 MHz. The REF input pin has been redefined to be a frequency selection strap (BSEL1) during power-on and then becomes a 14 MHz reference clock output. The following figure details the new BSEL[1:0] circuit design for universal PGA370 designs. Note that BSEL[1:0] now are pulled up using 1 kΩ resistors. Also refer to Figure 24 for more details.

Note: In a design supporting future 0.13 micron socket 370 processors, the BSEL[1:0] lines are not valid

until VTTPWRGD is asserted. Refer to Section 4.2.10 for details.

Figure 23. BSEL[1:0] Circuit Implementation for PGA370 Designs

3.3V

Processor

1 kΩ1 kΩ

BSEL0 BSEL1

Chipset

Clock Driver

sys_ bus_BSEL_PGA370

56 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

5.6 CLKREF Circuit Implementation

The CLKREF input (used by the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors) requires a 1.25V source. It can be generated from a voltage divider on the VCC2.5 or VCC3.3 sources using 1% to l erant resistors. A

4.7 µF decoupling capacitor should be included on this input. See Figure 24 and Table 13 for example CLKREF circuits. Do not use VTT as the source for this reference!

Figure 24. Examples for CLKREF Divider Circuit

Vcc2.5

150

PGA370

CLKREF

Y33

Ω

4.7 µF

Vcc3.3

PGA370

CLKREF

Y33

4.7 µF

sys_bus_CLKREF_divider

Table 13. Resistor Values for CLKREF Divider (3.3V Source)

R1 (Ω)

Ω), 1% R2 (Ω)

Ω)Ω)

182 110 1.243

301 182 1.243

374 221 1.226

499 301 1.242

Ω), 1% CLKREF Voltage (V)

Ω)Ω)

5.7 Undershoot/Overshoot Requirements

Undershoot and overshoot specifications become more critical as the process technology for microprocessors shrinks due to thinner gate oxide. Violating these undershoot and overshoot limits will degrade the life expectancy of the processor.

The Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future

0.13 micron socket 370 processo rs have more restrictive overshoot and undershoot requirements for system bus signals than previous processors. These requirements stipulate that a signal at the output of the driver buffer and at the input of the receiver buffer must not exceed the maximum absolute overshoot voltage limit or the minimum absolute undershoot voltage limit. Exceeding either of these limits will dama ge the pro cessor. There is also a time-dependent, non-linear overshoot and undershoot requirement that depends on the amplitude and duration of the overshoot/undershoot. See the appropriate processor datasheet for more details on the processor overshoot/undershoot specifications.

815 Chipset Platform Design Guide 57

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System Bus Design Guidelines

5.8 Processor Reset Requirements

Universal PGA370 designs must route the AGTL/AGTL+ reset signal from the chipset to two pins on the processor as well as to the debug port connector. This reset signal is connected to the following pins at the PGA370 socket:

• AH4 (RESET#). The reset signal is connected to this pin for the Pentium III processor

(CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors

• X4 (Reset2# or GND, depending on processor). The X4 pin is RESET2# for Pentium III

processor (CPUID=068xh) and Celeron processor (CPUID=068 xh). X4 is GND for future

0.13 micron socket 370 processors. An additional 1kΩ resistor is connected in series with pin X4 to the reset circuitry since pin X4 is a ground pin in future 0.13 micron socket 370 processors.

Note: The AGTL/AGTL+ reset signal must always terminate to VTT on the motherboard.

Designs that do not support the debug port will not utilize the 240 Ω series resistor or the connection of RESET# to the debug port connector. RESET2# is not required for platforms that do not support the Celeron processor (CPUID=068xh). Pin X4 should then be connected to ground.

The routing rules for the AGTL/AGTL+ reset signal are shown in Figure 25.

Figure 25. RESET#/RESET2# Routing Guidelines

lenITP

Chipset

VTT

Ω

cs_rtt_stub

240

Ω

lenCPUlenCS

VTT

10 pF

cpu_rtt_stub

Table 14. RESET#/RESET2# Routing Guidelines (see Figure 25)

Parameter Minimum (in) Maximum (in)

LenCS 0.5 1.5

LenITP 1 3

LenCPU 0.5 1.5

cs_rtt_stub 0.5 1.5

cpu_rtt_stub 0.5 1.5

ITP

Ω

Daisy c hain

Ω

1 k

Pin X4

Ω

Processor

Pin AH4

sys_bus_reset_routin

58 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

5.9 Processor PLL Filter Recommendations

Intel PGA370 processors have internal phase lock loop (PLL) clock generators that are analog and require quiet power supplies to minimize jitter.

5.9.1 Topology

The general desired topology for these PLLs is shown in Figure 27. Not shown are the parasitic routing and local decoupling capacitors. Excluded from the external circuitry are parasitics associated with each component.

5.9.2 Filter Specification

The function of the filter is to protect the PLL from external noise through low-pass attenuation. The low-pass specification, with input at VCC follows:

and output measured across the capacitor, is as

CORE

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band (see DC drop in next set of requirements)

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter specification is graphically shown in Figure 26.

815 Chipset Platform Design Guide 59

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System Bus Design Guidelines

Figure 26. Filter Specification

0.2dB

0dB

-0.5 dB

-28dB

-34dB

Forbidden

Zone

Forbidden

Zone

1 MHz 66 MHz fcorefpeak1HzDC

passband

high frequency

band

filter_spec

NOTES:

1. Diagram not to scale.

2. No specification for frequencies beyond fcore.

3. fpeak should be less than 0.05 MHz.

Other requirements:

• Use shielded-type inductor to minimize magnetic pickup.

• Filter should support DC current > 30 mA.

• DC voltage drop from VCC to PLL1 should be < 60 mV, which in practice implies series

R < 2 Ω. This also means pass-band (from DC to 1 Hz) attenuation < 0.5 dB for VCC = 1.1V, and < 0.35 dB for VCC = 1.5V.

60 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

5.9.3 Recommendation for Intel Platforms

The following tables contain examples of components that meet Intel’s recommendations, when configured in the topology of Figure 27.

Table 15. Component Recommendations – Inductor

Part Number Value Tol. SRF Rated

TDK MLF2012A4R7KT 4.7 µH 10% 35 MHz 30 mA 0.56 Ω (1 Ω max.) Murata LQG21N4R7K00T1 4.7 µH 10% 47 MHz 30 mA 0.7 Ω (± 50%) Murata LQG21C4R7N00 4.7 µH 30% 35 MHz 30 mA 0.3 Ω max.

Table 16. Component Recommendations – Capacitor

Part Number Value Tolerance ESL ESR

Kemet T495D336M016AS 33 µF 20% 2.5 nH 0.225 Ω AVX TPSD336M020S0200 33 µF 20% 2.5 nH 0.2 Ω

Table 17. Component Recommendation – Resistor

Value Tolerance Power Note

1 Ω 10% 1/16 W Resistor may be implemented with trace resistance,

in which case a discrete R is not needed. See Figure 28.

To satisfy damping requirements, total series resistance in the filter (from VCC of the capacitor) must be at least 0.35 Ω. This resistor can be in the form of a discrete component or routing or both. For example, if the chosen inductor has a minimum DCR of 0.25 Ω, then a routing resistance of at least 0.10 Ω is required. Be careful not to exceed the maximum resistance rule (2 Ω). For example, if using discrete R1 (1 Ω ± 1%), the maximum DCR of the L (trace plus inductor) should be less than 2.0 - 1.1 = 0.9 Ω; this preclud es the use of some inductors and sets a maximum trace length.

Current

DCR (Typical)

to the top plate

CORE

Other routing requirements:

• The capacitor (C) should be close to the PLL1 and PLL2 pins, < 0.1 Ω per route. These routes

do not count towards the minimum damping R requirement.

• The PLL2 route should be parallel and next to the PLL1 route (i.e., minimize loop area).

• The inductor (L) should be close to C. Any routing resistance should be inserted between

CORE

and L.

CORE

and L.

VCC

• Any discrete resistor (R) should be inse rted between VCC

815 Chipset Platform Design Guide 61

Intel

System Bus Design Guidelines

Figure 27. Example PLL Filter Using a Discrete Resistor

VCC

CORE

<0.1 Ω route

Discrete resistor

<0.1

Figure 28. Example PLL Filter Using a Buried Resistor

VCC

CORE

Trace resistance

<0.1 Ω route

<0.1

PLL1

Processor

PLL2

Ω route

PLL_filter_1

PLL1

Processor

PLL2

Ω route

PLL_filter_2

62 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

5.9.4 Custom Solutions

As long as designers satisfy filter performance and requirements as specified and outlined in Section 5.9.2, other solutions are acceptable. Custom solutions should be simulated against a standard reference core model (see Figure 29).

Figure 29. Core Reference Model

0.1

Ω

120 pF 1 k

Ω

PLL1

PLL2

NOTES:

Ω resistors represent package routing.

1. 0.1

2. 120 pF capacitor represents internal decoupling capacitor.

3. 1 k

Ω resistor represents small signal PLL resistance.

4. Be sure to include all component and routing parasitics.

5. Sweep across component/parasitic tolerances.

6. To observe IR drop, use DC current of 30 mA and minimum VCC

7. For other modules (interposer, DMM, etc.), adjust routing resistor if desired, but use minimum numbers.

5.10 Voltage Regulation Guidelines

A universal PGA370 design will need the voltage regulation module (VRM) or on-board voltage regulator (VR) to be compliant with Intel VRM 8.5 DC-DC Converter Design Guidelines.

Ω

sys_bus_core_ref_ mo del

level.

CORE

Processor

5.11 Decoupling Guidelines for Universal PGA370 Designs

These preliminary decoupling guidelines for universal PGA370 designs are estimated to meet the specifications of VRM 8.5 DC-DC Converter Design Guidelines.

5.11.1 VCC

• Sixteen or more 4.7 µF capacitors in 1206 packages.

All capacitors should be placed within the PGA370 socket cavity and mounted on the primary side of the motherboard. The capacitors are arranged to minimize the overall inductance between the VCC

CORE

815 Chipset Platform Design Guide 63

Intel

Decoupling Design

CORE

/VSS power pins, as shown in Figure 30.

System Bus Design Guidelines

Figure 30. Capacitor Placement on the Motherboard

5.11.2 VTT Decoupling Design

For Itt = 2.3 A (maximum)

• Twenty 0.1 µF capacitors in 0603 packages placed as closed as possible to the processor VTT

pins. The capacitors are shown on the exterior of the previous figure.

5.11.3 VREF Decoupling Design

• Four 0.1 µF capacitors in 0603 package placed near VREF pins (within 500 mils).

64 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

5.12 Thermal Considerations

5.12.1 Heatsink Volumetric Keepout Regions

Current heatsink recommendations are only valid for supported Celeron and Pentium III processor frequencies.

Figure 31 shows the system component keepout volume above the socket connector required for the reference design thermal sol ut ion for high frequency processo rs. This keepout envelop e provides adequate room for the heatsink, fan and attach hardware under static conditions as well as room for installation of these components on the socket. The heatsink must be compatible with the Integrated Heat Spreader (IHS) used by higher frequency Pentium III processors.

Figure 32 shows component keepouts on the motherboard required to prevent interference with the reference design thermal solution. Note portions of the heatsink and attach hardware hang over the motherboard.

Adhering to these keepout areas will ensure compatibility with Intel boxed processor products and Intel enabled third party vendor thermal solutions for high frequency processors. While the keepout requirements should provide adequate space for the reference design thermal solution, systems integrators should check with their vendors to ensure their specific thermal solutions fit within their specific system designs. Ensure that the thermal solutions under analysis comprehend the specific thermal design requirements for higher frequency Pentium III processors.

While thermal solutions for lower frequency processors may not require the full keepout area, larger thermal solutions will be required for higher frequency processors, and failure to adhere to the guidelines will result in mechanical interference.

815 Chipset Platform Design Guide 65

Intel

System Bus Design Guidelines

Figure 31. Heatsink Volumetric Keepout Regions

Figure 32. Motherboard Component Keepout Regions

66 Intel

815 Chipset Platform Design Guide

System Bus Design Guidelines

5.13 Debug Port Changes

Due to the lower voltage technology employed with newer processors, changes are required to support the debug port. Previously, test access port (TAP) signals used 2.5V logic, as is the case with the Intel Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors utilize 1.5V logic levels on the TAP. As a result, the type of debug port connecter used in universal PGA370 designs is dependent on the processor that is currently in the socket. The 1.5V connector is a mirror image of the older 2.5V connector. Either connector will fit into the same printed circuit board layout. Only the pin numbers change (see Figure 33). Also requi red, along with the ne w connector, is an In-Target Probe* (ITP) that is capable of communicating with the TAP at the appropriate logic levels.

Figure 33. TAP Connector Compa rison

Celeron processor in the PPGA package. Pentium III processor (CPUID=068xh),

2.5 V connector, AMP 104068-3 vertical plug, top view

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

RESET#

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

1.5 V connector, AMP 104078-4 vertical receptacle, top view

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

sys_bus_TAP_conn

Caution: Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) require an in-

target probe (ITP) compatible with 1.5V signal levels on the TAP. Previous ITPs were designed to work with higher voltages and may damage the processor if connected to any of these specified processors.

See the processor datasheet for more information regarding the debug port.

815 Chipset Platform Design Guide 67

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System Bus Design Guidelines

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68 Intel

815 Chipset Platform Design Guide

System Memory Design Guidelines

6 System Memory Design

Guidelines

6.1 System Memory Routing Guidelines

Ground plane reference all system memory signals. To provide a good current return path and limit noise on the system memory signals, the signals should be ground referenced from the GMCH to the DIMM connectors and from DIMM connector-to-DIMM connector. If ground referencing is not possible, system memory signals sho uld be, at a minimum, refer enced to a single plane. If single plane referencing is not possible, stitching capacitors should be added no more than 200 mils from the signal via field. System memory signals may via to the backside of the PCB under the GMCH without a stitching capacitor as long as the trace on the topside of the PCB is less than 200 mils.

Note: Intel recommends that a parallel p late capacitor between VCC3.3SUS and GND be added to

account for the current return path discontinuity (See decoupling section). Use one 0.01 µF X7R capacitor per every five system memory signals that switch plane references. No more than two vias are allowed on any system memory signal.

If a group of system memory signals must to change layers, a via field should be created and a decoupling capacitor should be added at the end of the via field. Do not route signals in the middle of a via field; this causes noise to be generated on the current return path of these signals and can lead to issues on these signals (see Figure 34). The traces shown are on layer 1 only. The figure shows signals that are changing layer and two signals that are not changing layer.

Note: The two signals around the via field create a keepout zone where no signals that do not change

layer should be routed.

Figure 34. System Memory Routing Guidelines

Do not route any signal in

the middle of the via field

that do not change layers

Add (1) 0.01 uf capacitor

X7R (5) signals that via

Stagger vias in via field to avoid

power/ground plane cut off because

of the antipad on the internal layers

sys-mem-route

815 Chipset Platform Design Guide 69

Intel

System Memory Design Guidelines

6.2 System Memory 2-DIMM Design Guidelines

6.2.1 System Memory 2-DIMM Connectivity

Figure 35. System Memory Connectivity (2 DIMM)

Double-Sided, Unbuffered Pinout without ECC

SCSA[3:2]#

SCSA[1:0]#

82815

CK815

ICH

SCKE[1:0]

SCKE[3:2]

SCSB[3:2]#

SCSB[1:0]#

SRAS#

SCAS#

SWE#

SBS[1:0]

SMAA[12:8,3:0]

SMAA[7:4]

SMAB[7:4]#

SDQM[7:0]

SMD[63:0]

DIMM_CLK[3:0]

DIMM_CLK[7:4]

SMB_CLK

SMB_DATA

DIMM 0 & 1

Notes:

Min. (16 Mbit) 8 MB Max. (64 Mbit) 256 MB Max. (128 Mbit) 512 MB

sys_mem_conn_2DIMM

70 Intel

815 Chipset Platform Design Guide

System Memory Design Guidelines

6.2.2 System Memory 2-DIMM Layout Guidelines

Figure 36. System Memory 2-DIMM Routing Topologies

Topology 1

Topology 2

Topology 3

Topology 4

Topology 5

82815

Ω

DIMM 0 DIMM 1

sys_mem_2DIMM_routing_topo

Table 18. System Memory 2-DIMM Solution Space

Signal Top.

A B C D E F

Width Spacing Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

SCS[3:2]# 3 5 10 1 4.5

SCS[1:0]# 2 5 10 1 4.5

SMAA[7:4] 4 10 10 0.4 0.5 2 4

SMAB[7:4]# 5 10 10 0.4 0.5 2 4

SCKE[3:2] 3 10 10 3 4

SCKE[1:0] 2 10 10 3 4

SMD[63:0] 1 5 10 1.75 4 0.4 0.5

SDQM[7:0] 1 10 10 1.5 3.5 0.4 0.5

SCAS#, SRAS#,

SWE#

SBS[1:0],

SMAA[12:8,3:0]

1 5 10 1 4.0 0.4 0.5

Trace Lengths (inches) Trace (mils)

In addition to meeting the spacing requirements outlined in Table 18, system memory signal trace edges must be at least 30 mils from any other non-system memo ry signal trace edge.

815 Chipset Platform Design Guide 71

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System Memory Design Guidelines

Figure 37. System Memory Routing Example

sys_mem_routing_ex

NOTE: Routing in this figure is for example purposes only. It does not necessarily represent complete and

correct routing for this interface.

72 Intel

815 Chipset Platform Design Guide

System Memory Design Guidelines

6.3 System Memory 3-DIMM Design Guidelines

6.3.1 System Memory 3-DIMM Connectivity

Figure 38. System Memory Connectivity (3 DIMM)

Double-Sided, Unbuffered Pinout without ECC

SCSA[5:4]# SCSA[3:2]# SCSA[1:0]#

Notes:

Min. (16 Mbit) 8 MB Max. (64 Mbit) 256 MB Max. (128 Mbit) 512 MB

82815

CK815

SCKE[1:0] SCKE[3:2] SCKE[5:4]

SCSB[5:4]# SCSB[3:2]# SCSB[1:0]#

SRAS#

SCAS#

SWE#

SBS[1:0]

SMAA[12:8,3:0]

SMAA[7:4]

SMAB[7:4]#

SMAC[7:4]#

SDQM[7:0]

SMD[63:0]

DIMM_CLK[3:0] DIMM_CLK[7:4]

DIMM_CLK[11:8]

ICH

815 Chipset Platform Design Guide 73

Intel

SMB_CLK

SMB_DATA

DIMM 0 & 1 & 2

sys_mem_conn_3DIMM

System Memory Design Guidelines

6.3.2 System Memory 3-DIMM Layout Guidelines

Figure 39. System Memory 3-DIMM Routing Topologies

82815

Topology 1

Topology 2

Topology 3

Topology 4 E

Topology 5

Topology 6

Topology 7

Topology 8 E

Ω

In addition to meeting the spacing requirements outlined in Table 19, system memory signal trace edges must be at least 30 mils from any other non-system memory signal trace edge.

Table 19. System Memory 3-DIMM Solution Space

Signal

A B C D E F G

Top. Width Spacing Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

DIMM 0 DIMM 1

sys_mem_3DIMM_routing_topo

Trace Lengths (inches) Trace (mils)

DIMM 2

SCS[5:4]# 4 5 10 1 4.5

SCS[3:2]# 3 5 10 1 4.5

SCS[1:0]# 2 5 10 1 4.5

SMAA[7:4] 6 10 10 2 4 0.4 0.5

SMAB[7:4]# 7 10 10 2 4 0.4 0.5

SMAC[7:4} 8 10 10 2 4 0.4 0.5

SCKE[5:4] 4 10 10 3 4

SCKE[3:2] 3 10 10 3 4

SCKE[1:0] 2 10 10 3 4

SMD[63:0] 1 5 10 1.75 4 0.4 0.5

SDQM[7:0] 1 10 10 1.5 3.5 0.4 0.5

SCAS#,

SRAS#, SWE#

SBS[1:0],

SMAA[12:8,3:0]

74 Intel

5 5 10 0.4 0.5 1 4

815 Chipset Platform Design Guide

System Memory Design Guidelines

6.4 System Memory Decoupling Guidelines

A minimu m of eight 0.1 µF low-ESL ceramic capacitors (e.g., 0603 body type, X7R dielectric) are required and must be as close as possible to the GMCH. They should be placed within at most 70 mils to the edge of the GMCH package edge for VSUS_3.3 decoupling, and they should be evenly distributed around the system memory interface signal field including the side of the GMCH where the system memory interface meets the host interface. There are power and GND balls throughout the system memory ball field of the GMCH that need good local decoupling. Make sure to use at least 14 mil drilled vias and wide traces from the pads of the capacitor to the power or ground plane to create a low-inductance path. If possible, multiple vias per capacitor pad are recommended to further reduce inductance. To add the decoupling capacitors within 70 mils of the GMCH and/or close to the vias, the trace spacing may be reduced as the traces go around each capacitor. The narrowing of space between traces should be minimal and for as short a distance as possible (500 mils maximum).

To further decouple the GMCH and provide a solid current return path for the system memory interface signals it is recommended that a parallel plate capacitor be added under the GMCH. Add a topside or bottom side copper flood under center of the GMCH to create a parallel plate capacitor between VCC3.3 and GND, see following figure. The dashed lines indicate power plane splits on layer 2 or layer 3 depending on stack-up. The filled region in the mid dle of the GMCH indicates a ground plate (on layer 1 if the power plane is on layer 2 or on layer 4 if the power layer is on layer 3).

815 Chipset Platform Design Guide 75

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System Memory Design Guidelines

Figure 40. Intel

815 Chipset Platform Decoupling Example

Yellow lines in Figure 40 show layer-two plane splits. (Printed versions of this document will show the layer two plane splits in the left-side, bottom, right-side, and upper-right-side quadrants enclosed in gray lines.) Note that the layer 1 shapes do NOT cross the plane splits. The bottom shape is a VSS fill over VddSDRAM. The left-side shape is a VSS fill over VddAGP. The larger upper-right-side shape is a VSS fill over VddCORE.

Additional decoupling capacitors shown in Figure 41 should be added between the DIMM connectors to provide a current return path for the reference plane discontinuity created by the DIMM connectors themselves. One 0.01 µF X7R capacitor should be added per every ten SDRAM signals. Capacitors should be placed between the DIMM connectors and evenly spread out across the SDRAM interface.

For debug purposes, four or more 0603 capacitor sites should be placed on the backside of the board, evenly distributed under the Intel 815 chipset platform’s system memory interface signal field.

76 Intel

815 Chipset Platform Design Guide

System Memory Design Guidelines

Figure 41. Intel

815 Chipset Platform Decoupling Example

6.5 Compensation

A system memory compensation resistor (SRCOMP) is used by the GMCH to adjust the buffer characteristics to specific board and operating environment characteristics. Refer to the Intel

Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for details on compensation. Tie the SRCOMP pin of the GMCH to

40 Ω 1% or 2% pull-up resistor to 3.3 Vsus (3.3Volt standby) via a 10-mil-wide, 0.5 inch trace (targeted for a nominal impedance of 40 Ω).

815

815 Chipset Platform Design Guide 77

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System Memory Design Guidelines

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78 Intel

815 Chipset Platform Design Guide

AGP/Display Cache Design Guidelines

7 AGP/Display Cache Design

Guidelines

For the detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms) refer to the latest AGP Interface Specification, Revision 2.0, which can be obtained from

http://www.agpforum.org

recommendations and covers both standard add-in card AGP and down AGP solutions.

7.1 AGP Interface

A single AGP connector is supported by the GMCH’s AGP interface. LOCK# and SERR#/PERR# are not supported. See the display cache discussion for a display cache/AGP muxing description and a description of the Graphics Performance Accelerator (GPA).

. This design guide focuses only on specific Intel 815 chipset platform

The AGP buffers operate in one of two selectable modes to support the AGP universal connector:

• 3.3V drive, not 5V safe. This mode is compliant with the AGP 1.0 66 MHz specification.

• 1.5V drive, not 3.3V safe. This mode is compliant with the AGP 2.0 specification.

The AGP 4X must operate at 1.5V and only use differential clocking mode. The AGP 2X can operate at 3.3V or 1.5V. The AGP interface supports up to 4X AGP signaling, though 4X fast writes are not supported. AGP semantic cycles to DRAM are not snooped on the host bus.

The GMCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. The GMCH contains a 32-deep AGP request queue. High-priority accesses are supported. All AGP semantic accesses hitting the graphics aperture pass through an address translation mechanism with a fully-associative 20-entry TLB.

Accesses between AGP and the hub interface are limited to hub interface-originated memory writes to AGP. Cacheable accesses from the IOQ queue flow through one path, while aperture accesses follow another path. Cacheable AGP (SBA, PIPE#, and FRAME#) reads to DRAM all snoop the cacheable global write buffer (GWB) for system data coherency. Aperture AGP (SBA, PIPE#) reads to DRAM snoop the aperture queue (GCMCRWQ). Aperture AGP (FRAME#) reads and writes to DRAM proceed through a FIFO and there is no RAW capability, so no snoop is required.

The AGP interface is clocked from the 66 MHz clock (3V66). T he AGP-to-host/memory interface is synchronous with a clock ratio of 1:1 (66 MHz : 66 MHz), 2:3 (66 MHz : 100 MHz) and 1:2 (66 MHz : 133 MHz).

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7.1.1 Graphics Performance Accelerator (GPA)

The GMCH multiplexes the AGP signal interface with the integrated graphics’ display cache interface. As a result, for a universal motherboard that supports both integrated graphics and addin AGP video cards, display cache (for integrated graphics) must be populated on a card in the universal AGP slot. The card is called a Graphics Performance Accelerator (GPA) card. Intel provides a specification for this card in a separate document (Graphics Performance Accelerator Specification).

AGP guidelines are presented in this section for motherboards that support the population of a GPA card in their AGP slot, as well as for those that do not. Where there are distinct guidelines dependent on whether or not a motherboard will support a GPA card, the section detailing routing guidelines is divided into subsections, as follows:

• If the motherboard supports a GPA card populated in the AGP slot, then the guidelines in the

Flexible Motherboard subsections are to be followed.

• If the motherboard will NOT support a GPA card populated in the AGP slot, then the

guidelines in the AGP-Only Motherboard subsections are to be followed.

7.1.2 AGP Universal Retention Mechanism (RM)

Environmental testing and field reports indicate that AGP cards and Graphics Performance Accelerator (GPA) cards may come unseated during system shipping and handling without proper retention. To avoid disengaged AGP cards and GPA modules, Intel recommends that AGP-based platforms use the AGP retention mechanism (RM).

The AGP RM is a mounting bracket that is used to properly locate the card with respect to the chassis and to assist with card retention. The AGP RM is available in two different handle orientations: left-handed (see Figure 42) and right-handed. Most system boards accommodate the left-handed AGP RM. The manufacturing capacity of the left-handed RM currently exceeds the right-handed capacity, and as a result Intel recommends that customers design their systems to insure they can use the left-handed version of the AGP RM (see Figure 42). The right-handed AGP RM is identical to the left-handed AGP RM, except for the position of the actuation handle. This handle is located on the same end as the primary design, but extends from the opposite side (mirrored a bout the center axis running parallel to the length of the part) . Figure 43 co ntains keepout information for the left hand AGP retention mechanism. Use this information to ensure the motherboard design leaves adequate space to install the retention mechanism.

The AGP interconnect design requires that the AGP card must be retained to the extent that the card not back out more than 0.99 mm (0.039 in) within the AGP connector. To accomplish this it is recommended that new cards implement an additional notch feature in the mechanical keying tab to allow an anchor point on the AGP card for interfacing with an AGP RM. The retention mechanism’s round peg engages with the AGP or GPA card’s retention tab and prevents the card from disengaging during dynamic loading. The additional notch feature in the mechanical keying tab is required for 1.5V AGP cards and is recommended for the new 3.3V AGP cards.

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Figure 42. AGP Left-Handed Retention Mechanism

Figure 43. AGP Left-Handed Retention Mechanism Keepout Information

Engineering Change Request number 48 (ECR #48) of the AGP specification details the AGP RM, which is recommended for all AGP cards. These are approved changes to the Accelerated Graphics Port (AGP) Interface Specification, Revision 2.0. Intel intends to incorporate the AGP RM changes into later revisions of the AGP Interface Specification. In addition, Intel has defined a reference design of a mechanical device to utilize the features defined in ECR #48.

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ECR #48 can be viewed on the Intel Web site at:

http://developer.intel.com/technology/agp/ecr.htm

More information regarding this component (AGP RM) is available from the following vendors.

Resin Color Supplier Part

Number

AMP P/N 136427-1 136427-2 Black

Foxconn P/N 006-0002-939 006-0001-939

Green Foxconn P/N 009-0004-008 009-0003-008

7.2 AGP 2.0

The AGP Interface Specification, Revision 2.0 enhances the functionality of the original AGP Interface Specification, Revision 1.0 by allowing 4X data transfers (4 data samples per clock) and

1.5V operation. The 4X operation of the AGP interface provides for “quad-pumping” of the AGP AD (address/data) and SBA (side-band addressing) buses. That is, data is sampled four times during each 66 MHz AGP clock, which means that each data cycle is ¼ of a 15 ns (66 MHz) clock, or 3.75 ns. Note that 3.75 ns is the data cycle time, not the clock cycle time. During 2X operation, data is sampled twice during a 66 MHz clock cycle, so the data cycle time is 7.5 ns. To allow for such high-speed data transfers, the 2X mode of AGP operation uses source-synchronous data strobing. During 4X operation, the AGP interface uses differential source-synchronous strobing.

“Left Handed” Orientation

(Preferred)

“Right Handed” Orientation

(Alternate)

With data cycle times as small as 3.75 ns and setup/hold times of 1 ns, propagation delay mismatch is critical. In addition to reducing propagation delay mismatch, it is important to minimize noise. Noise on the data lines causes the settling time to be long. If the mismatch between a data line and the associated strobe is too great or if there is noise on the interface, incorrect data will be sampled. The low-voltage operation on the AGP (1.5V) requires even more noise immunity. For example, during 1.5V operation, V

is 570 mV. Without proper isolation,

max

cross-talk could create signal integrity issues.

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7.2.1 AG P I nter face Si gnal Groups

The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X timing domain signals, and miscellaneous signals. Each group ha s different ro uting requirements.

In addition, within the 2X/4X timing domain signals, there are three sets of signals. All signals in the 2X/4X timing domain must meet minimum and maximum trace length requirements as well as trace width and spacing requirements. However, trace length matching requirements only need to be met within each set of 2X/4X timing domain signals. The signal groups are listed in Table 20.

Table 20. AGP 2.0 Signal Groups

Group Signal

1X timing domain • CLK (3.3V), RBF#, WBF#, ST[2:0], PIPE#, REQ#, GNT#, PAR,

2X / 4X timing domain • Set #1: AD[15:0], C/BE[1:0]#, AD_STB0, AD_STB0#1

Miscellaneous, async • USB+, USB-, OVRCNT#, PME#, TYPDET#, PERR#, SERR#, INTA#,

NOTES:

1. These signals are used in 4X AGP mode ONLY.

FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#

• Set #2: AD[31:16], C/BE[3:2]#, AD_STB1, AD_STB1#

• Set #3: SBA[7:0], SB_STB, SB_STB#1

INTB#

Table 21. AGP 2.0 Data/Strobe Associations

Data Associated Strobe in 1X Associated

AD[15:0] and C/BE[1:0]# Strobes are not used in 1X mode.

AD[31:16] and C/BE[3:2]# Strobes are not used in 1X mode.

SBA[7:0] Strobes are not used in 1X mode.

All data is sampled on rising clock edges.

Strobe in 2X

AD_STB0 AD_STB0,

AD_STB1 AD_STB1,

SB_STB SB_STB,

Associated

Strobes in 4X

AD_STB0#

AD_STB1#

SB_STB#

Throughout thi s section, the te rm data refers to AD[31:0], C/BE[3:0]#, and SBA[7:0]. The term strobe refers to AD_STB[1:0], AD_STB[1:0]#, SB_STB, and SB_STB#. When the term data is

used, it refers to one of the three sets of data signals, as listed in Table 21. When the term strobe is used, it refers to one of the strobes as it relates to the data in its associated group.

The routing guidelines for each group of signals (1X timing domain signals, 2X/4 X timing domain signals, and miscellaneous signals) will b e addressed separately.

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7.3 Standard AGP Routing Guidelines

These routing guidelines cover a standard AGP solution. This utilizes an AGP compliant device on an external add-in card that plugs into a connector on the motherboard.

7.3.1 1X Timing Domain Routing Guidelines

7.3.1.1 Flexible Motherboard Guidelines

• The AGP 1X timing domain signals (Table 20) have a maximum trace length of 4 inches for

motherboards that support a Graphics Performance Accelerator (GPA) card. This maximum applies to ALL signals listed as 1X timing domain signals in Table 20.

• AGP 1X signals multiplexed with display cached signals (listed in the following table) should

be routed with a 1:3 trace width-to-spacing ratio. All other AGP 1X timing domain signals can be routed with 5-mil minimum trace separation.

• There are no trace length matching requirements for 1X timing domain signals.

The following are multiplexed AGP1X Signals on Flexible Motherboards

• RBF# • FRAME#

• ST[2:0] • IRDY#

• PIPE# • TRDY#

• REQ# • STOP#

• GNT# • DEVSEL#

• PAR

7.3.1.2 AGP-Only Motherboard Guidelines

• The AGP 1X timing domain signals (refer to Table 20) have a maximum trace length of

7.5 inches for motherboards that will not support a Graphics Performance Accelerator (GPA) card. This maximum applies to ALL signa ls listed as 1X timing domain signals in Table 20.

• All AGP 1X timing domain signals can be routed with 5-mil minimum trace separation.

• There are no trace length matching requirements for 1X timing domain signals.

7.3.2 2X/4X Timing Domain Routing Guidelines

These trace length guidelines apply to ALL signals listed in Table 20 as 2X/4X timing domain signals. These signals should be routed using 5 mil (60 Ω) traces.

The maximum line length and lengt h mismatch requirements depend on the routing rules used on the motherboard. These routing rules were created to provide design freedom by making tradeoffs between signal coupling (trace spacing) and line lengths. The maximum length of the AGP interface defines which set of routing guidelines must be used. Guidelines for short AGP interfaces (e.g., < 6 inches) and long AGP interfaces (e.g., > 6 inches and < 7.25 inches) are documented

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separately. The maximum length allowed for the AGP interface (on AGP-only motherboards) is

7.25 inches.

7.3.2.1 Flexible Motherboard Guidelines

• For motherboards that support either an AGP card or a GPA card in the AGP slot, the

maximum length of AGP 2X/4X ti ming d omain signals is 4 inche s .

• 1:3 trace width-to-spacing is required for AGP 2X/4X signal traces.

• AGP 2X/4X signals must be matched their associated strobe (as outlined in Table 20), within

±0.5 inch.

For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) is 3.7 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) can be

3.2 inches to 4 inches long (since there is a 4 inch maximum length). Another strobe set (e.g., SB_STB and SB_STB#) could be 3.1 inches long, so that the associated data signals (e.g., SBA[7:0]) can be 2.6 inches to 3.6 inches long.

The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Since each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed using 5-mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matche d to less than ±0.1 inch (i.e., a strobe and its complement must be the same length within 0.1 inch).

Figure 44. AGP 2X/4X Routing Example for Interfaces < 6 Inches and GPA/AGP Solutions

5-mil trace

15 mils

5-mil trace

20 mils

5-mil trace

15 mils

5-mil trace

20 mils

5-mil trace

15 mils

Associated AGP 2X/4X data signal length

2X/4X signal

AGP STB#

AGP STB

2X/4X signal

STB/STB# length

0.5" 0.5"

Min. Max.

AGP_2x-4x_routing

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7.3.2.2 AGP-Only Motherboard Guidelines

For motherboards that will no t support a GPA card populated in the AGP slot, the maximum AGP 2X/4X signal trace length is 7.25 inches. However, there are different guidelines for AGP interfaces shorter than 6 inches (e.g., all AGP 2X/4X signals are less than 6 inches long) and those longer than 6 inches but shorter than the 7.25 inches maximum.

AGP Interfaces Shorter Than 6 Inches

These guidelines are for designs that require less than 6 inches between the AGP connector and the GMCH:

• 1:3 trace width-to-spacing is required for AGP 2X/4X timing domain signal traces.

• AGP 2X/4X signals must be matched with their associated strobe (as outlined in Table 20),

within ±0.5 inch.

For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) is 5.3 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) can be

4.8 inches to 5.8 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be

4.2 inches long, and the data signals associated with those strobe signals (e.g., SBA[7:0]) could be

3.7 inches to 4.7 inches long.

The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5-mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matche d to less than ±0.1 inch (i.e., a strobe and its complement must be the same length, within 0.1 inch).

AGP Interfaces Longer Than 6 Inches

Since longer lines have more cross-talk, they require wider spacing between traces to reduce the skew. The following guidelines are for designs that require more than 6 inches (but less than the

7.25 inches maximum) between the AGP connector and the GMCH:

• 1:4 trace width-to-spacing is required for AGP 2X/4X timing domain signal traces.

• AGP 2X/4X signals must be matched with their associated strobe (as outlined in Table 20),

within ±0.125 inch.

For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) is 6.5 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) could be

6.475 inches to 6.625 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be

6.2 inches long, and the data signals associated with those strobe signals (e.g., SBA[7:0]) could be

6.075 inches to 6.325 inches long. The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#)

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between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matche d to less than ±0.1 inch (i.e., a strobe and its complement must be the same length, within 0.1 inch).

7.3.3 AGP Routing Guideline Considerations and Summary

This section applies to all AGP signals in any motherboard support configuration (e.g., “flexible” or “AGP only”), as follows:

• The 2X/4X timing domain signals can be routed with 5-mil spacing, when breaking out of the

GMCH. The routing must widen to the documented requirements, within 0.3 inch of the GMCH package.

• When matching trace length for the AGP 4X interface, all traces should be matched from the

ball of the GMCH to the pin on the AGP connector. It is not necessary to compensate for the lengths of the AGP signals on the GMCH package.

• Reduce line length mismatch to ensure added margin. Trace length mismatch for all signals

within a signal group should be as close to zero as possible, to provide timing margin.

• To reduce trace-to-trace coupling (cross-talk), separate the traces as much as possible.

• All signals in a signal group should be routed on the same layer.

• The trace length and trace spacing requirements must not be violated b y any signal.

Table 22. AGP 2.0 Routing Summary

Signal

1X Timing Domain

2X/4X Timing Domain Set 1

2X/4X Timing Domain Set 2

2X/4X Timing Domain Set 3

2X/4X Timing Domain Set 1

2X/4X Timing Domain Set 2

2X/4X Timing Domain Set 3

Max.

Length

7.5” 4 5 mils No

7.25” 4 20 mils ±0.125” AD_STB0

7.25” 4 20 mils ±0.125” AD_STB1

7.25”4 20 mils ±0.125” SB_STB and

6” 3 15 mils1 ±0.5” AD_STB0

6”3 15 mils1 ±0.5” AD_STB1

6”3 15 mils1 ±0.5” SB_STB and

Trace Spacing

(5-mil Traces)

Length

Mismatch

requirement

Relative to Notes

N/A None

and AD_STB0#

and AD_STB1#

SB_STB#

and AD_STB0#

and AD_STB1#

SB_STB#

AD_STB0, AD_STB0# must be the same length

AD_STB1, AD_STB1# must be the same length

SB_STB, SB_STB# must be the same length

AD_STB0, AD_STB0# must be the same length

AD_STB1, AD_STB1# must be the same length

SB_STB, SB_STB# must be the same length

NOTES:

1. Each strobe pair must be separated from other signals by at least 20 mils.

2. These guidelines apply to board stack-ups with 15% impedance tolerance.

3. 4 inches is the maximum length for a flexible motherboards.

4. Solution valid for AGP-only motherboards.

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AGP/Display Cache Design Guidelines

7.3.4 AGP Clock Routing

The maximum total AGP clock skew, between the GMCH and the graphics component, is 1 ns for all data transfer modes. This 1 ns includes skew and jitter that originates on the motherboard, addin card, and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but at all points on the clock edge that fall within the switching range. The 1 ns skew budget is divided such that the motherboard is allotted 0.9 ns of clock skew. (The motherboard designer shall determine how the 0.9 ns is allocated between the board and the synthesizer.)

7.3.5 AGP Signal Noise Decoupling Guidelines

The following routing guidelines are recommended for an optimal system design. The main focus of these guidelines is to minimize signal integrity problems on the AGP interface of the GMCH. The following guidelines are not intended to rep lace thorough system validation for products based on the Intel 815 chipset platform.

• A minimum of six 0.01 µF capacitors are required and must be as close as possible to the

GMCH. These should be placed within 70 mils of the outer row of balls on the GMCH for VDDQ decoupling. The closer the placement, the better.

• The designer should evenly distribute placement of decoupling capacitors in the AGP

interface signal field.

• It is recommended that the designer use a low-ESL ceramic capacitor (e.g., with a 0603 body-

type X7R dielectric).

• To add the decoupling capacitors within 70 mils of the GMCH and/or close to the vias, the

trace spacing may be reduced as the traces go around each capacitor. The narrowing of space between traces should be minimal and for as short a distance as possible (1 inch maximum).

• In addition to the minimum decoupling capacitors, the designer should place bypass

capacitors at vias that transition the AGP signal from one reference signal plane to another.

On a typical four layer PCB design, the signals transition from one side of the board to the other. One extra 0.01 µF capacitor is required per 10 vias. The capacitor should be placed as

close as possible to the center of the via field.

The designer should ensure that the AGP connector is well decoupled, as described in the AGP Design Guide, Revision 1.0, Section 1.5.3.3.

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Figure 45. AGP Decoupling Capacitor Placement Example

NOTE: This figure is for example purposes only. It does not necessarily represent complete and correct

routing for this interface.

7.3.6 AGP Routing Ground Reference

It is strongly recommended that, at a minimum, the following critical signals be referenced to ground from the GMCH to an AGP connector (or to an AGP video controller if implemented as a “down” solution on an AGP-only motherboard), using a minimum number of vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_GTRY#, G_IRDY#, G_GNT#, and ST[2:0].

In addition to the minimum signal set listed previously, it is strongly recommended that half of all AGP signals be reference to ground, depending on board layout. In a n ideal design, the entire AGP interface signal field would be referenced to ground. This recommendation is not specific to any particular PCB stack-up, but should be applied to all designs using the Intel 815 chipset platform for use with the universal socket 370.

AGP_decoupling_ca p_placement

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7.4 AGP Down Routing Guidelines

These routing guidelines cover an AGP down solution. This allows for an AGP compliant device to be implemented directly on the motherboard without the need for a connector or add-in card.

7.4.1 1X AGP Down Option Timing Domain Routing Guidelines

Routing guidelines for an AGP device on the motherboard are very similar to those when the device is implemented with an AGP connector.

• AGP 1X timing domain signals (Table 20) have a maximum trace length of 7.5 inches. This

maximum applies to ALL signals listed as 1 X timing domain signals in Table 20.

• All AGP 1X timing domain signals can be routed with 5-mil minimum trace separation

• There are no trace length matching requirements for 1X timing domain signals

7.4.2 2X/4X AGP Down Timing Domain Routing Guidelines

These trace length guidelines apply to ALL signals listed in Table 20 as 2X/4X timing domain signals. These signals should be routed using 5-mil (60 Ω) traces.

• The maximum AGP 2X/4X signal trace length is 6 inches.

• 1:3 trace width-to-spacing is required for AGP 2X/4X timing domain signal traces.

• AGP 2X/4X signals must be matched with their associated strobe (as outlined in Table 20),

within ± 0.5 inch.

For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) is 5.3 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) could be

4.8 inches to 5.8 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be

4.2 inches long, and the data signals associated with those strobe signals (e.g., SBA[7:0]) could be

3.7 inches to 4.7 inches long. The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#)

act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5-mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matche d to less than ±0.2 inch (i.e., a strobe and its complement must be the same length, within 0.2 inch).

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Figure 1. AGP Down 2X/4X Routing Recommendations

AGP Compliant

Graphics Device

Length: 0.5" - 6.0" Width to spacing: 1:3 Strobe-to-Data

Mismatch: ±0.5"

Signals

Strobes

Length: Dependent on Data Width : 5 mil

Spacing: 15 mils Strobe-to-Strobe Mi sm atch: ±0.2"

Intel® 82815

AGP_Down_1x-2x

7.4.3 AGP Routing Guideline Considerations and Summary

This section applies to all AGP signals, as follows:

• The 2X/4X timing domain signals can be routed with 5-mil spacing, when breaking out of the

GMCH. The routing must widen to the documented requirements, within 0.3 of the GMCH package.

• When matching the trace length for the AGP 4X interface, all traces should be matched from

the ball of the GMCH to the ball on the AGP compliant device. It is not necessary to compensate for the lengths of the AGP signals on the GMCH package.

• Reduce line length mismatch to ensure added margin. Trace length mismatch for all signals

within a signal group should be as close to zero as possible, to provide timing margin.

• To reduce trace-to-trace coupling (cross-talk), separate the traces as much as possible.

• All signals in a signal group should be routed on the same layer.

• The trace length and trace spacing requirements must not be violated by any signal.

Table 23. AGP 2.0 Routing Summary

Signal

1X Timing

Max.

Length

7.5” 5 mils No

Domain

2X/4X Timing

6” 15 mils

Domain Set 1

2X/4X Timing

6” 15 mils

Domain Set 2

2X/4X Timing

6” 15 mils

Domain Set 3

NOTES:

1. Each strobe pair must be separated from other signals by at least 20 mils.

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Trace Spacing

(5-mil Traces)

Length

Mismatch

Relative to Notes

N/A None

requirement

±0.5” AD_STB0

and AD_STB0#

±0.5” AD_STB1

and AD_STB1#

±0.5” SB_STB

and SB_STB#

AD_STB0, AD_STB0# must be the same length

AD_STB1, AD_STB1# must be the same length

SB_STB, SB_STB# must be the same length

AGP/Display Cache Design Guidelines

7.4.4 AGP Clock Routing

For AGP clock routing guidelines for the Intel 815 chipset platform, refer to Section 11.3.

7.4.5 AGP Signal Noise Decoupling Guidelines

The following routing guidelines are recommended for the optimal system design. The main focus of these guidelines is to minimize signal integrity problems on the AGP interface of the GMCH. The following guidelines are not intended to rep l ace thorough system validation for products based on the Intel 815 chipset platform.

• A minimum of six 0.01 µF capacitors are required and must be as close as possible to the

GMCH. These should be placed within 70 mils of the outer row of balls on the GMCH for VDDQ decoupling. The closer the placement, the better.

• The designer should evenly distribute placement of decoupling capacitors in the AGP

interface signal field.

• It is recommended that the designer use a low-ESL ceramic capacitor, such as with a 0603

body-type X7R dielectric.

• To add the decoupling capacitors within 70 mils of the GMCH and/or close to the vias, the

trace spacing may be reduced as the traces go around each capacitor. The narrowing of space between traces should be minimal and for as short a distance as possible (1 inch maximum).

• In addition to the minimum decoupling capacitors, the designer should place bypass

capacitors at vias that transition the AGP signal from one reference signal plane to another.

On a typical four-layer PCB design, the signals transition from one side of the board to the other. One extra 0.01 µF capacitor is required per ten vias. The capacitor should be placed as

close as possible to the center of the via field.

7.4.6 AGP Routing Ground Reference

It is strongly recommended that at least the following critical signals be referenced to ground from the GMCH to an AGP video controller on an AGP-only motherboard, using a minimum number of vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_GTRY#, G_IRDY#, G_GNT#, and ST[2:0].

In addition to the minimum signal set listed previously, it is strongly recommended that half of all AGP signals be referenced to ground, depending on the board layout . In an ideal design, the complete AGP interface signal field would be referenced to gr ound. This recommendation is not specific to any particular PCB stack-up, but should be applied to all designs using the Intel 815 chipset platform.

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AGP/Display Cache Design Guidelines

7.5 AGP 2.0 Power Delivery Guidelines

7.5.1 VDDQ Generation and TYPEDET#

AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics controller. This voltage i s always 3.3V. VDDQ is the interface voltage. In AGP 1.0 implementations, VDDQ was also 3.3V. For the designer developing an AGP 1.0 motherboard, there is no distinction between VCC and VDDQ, as both are tied to the 3.3V power plane on the motherboard.

AGP 2.0 requires that these power planes be separate. In conjunction with the 4X data rate, the AGP 2.0 Interface Specification provides for low-voltage (1.5V) operation. The AGP 2.0 specification implements a TYPEDET# (type detect) signal on the AGP connector that determines the operating voltage of the AGP 2.0 interface (VDDQ). The motherboard must provide either

1.5V or 3.3V to the add-in card, depending on the state of the TYPEDET# signal. (see Table 24).

1.5V low-voltage operation applies only to the AGP interface (VDDQ). VCC is always 3.3V.

Note: The motherboard provides 3.3V to the VCC pins of the AGP connector. If the graphics controller

needs a lower voltage, then the add-in card must regulate the 3.3VCC voltage to the controller’s requirements. The graphics controller may only power AGP I/O buffers with the VDDQ power pins.

The TYPEDET# signal indicates whether the AGP 2.0 interface operates at 1.5V or 3.3V. If TYPEDET# is floating (i.e., No Connect) on an AGP add-in card, the interface is 3.3V. If TYPEDET# is shorted to ground, the interface is 1.5V.

Table 24. TYPDET#/VDDQ Relationship

TYPEDET#

(on add-in card)

GND 1.5V

N/C 3.3V

As a result of this requirement, the motherboard must provide a flexible voltage regulator or key the slot to preclude add-in cards with voltage requirements incompatible with the motherboard. This regulator must supply the appropriate voltage to the VDDQ pins on the AGP connector. For specific design recommendations, refer to the schematics in Appendix A. VDDQ generation and AGP VREF generation must be considered together. Before developing VDDQ generation circuitry, refer to both the above requirements and the AGP 2.0 Interface Specification.

VDDQ

(supplied by MB)

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Figure 46. AGP VDDQ Generation Example Circuit

TYPEDET#

+3.3V

+12V

LT1575

SHDN IPOS

VIN INEG

2.2 k

Ω

1 µF

GND GATE

FB COMP

.001 µF

7.5 k

10 pF

Ω

- 1%

47 µF

301 - 1%

Ω

- 1%

1.21 k

VDDQ

220 µF

AGP_VDDQ_gen_ex_circ

The previous figure demonstrates one way to design the VDDQ voltage regulator. This regulator is a linear regulator with an external, low-Rds

FET. The source of the FET is connected to 3.3V.

This regulator converts 3.3V to 1.5V or passes 3.3V, depending on the state of TYPEDET#. If a linear regulator is used, it must draw power from 3.3V (not 5V) to control thermals (i.e., 5V regulated down to 1.5V with a linear regulator will dissipate approximately 7 W at 2 A). Because it must draw power from 3.3V and, in some situations, must simply pass that 3.3V to VDDQ (when a 3.3V add-in card is placed in the system), the regulator MUST use a low-Rds

FET. AGP 1.0 ECR #44 modified VDDQ 3.3

3.3 V to a FET with an Rds

is 3.168V. Therefore, 68 mV of drop is allowed across the FET at 2 A. This corresponds

min

of 34 mΩ.

to 3.1V. When an ATX power supply is used, the

min

How does the regulator switch? The feedback resistor divider is set to 1.5V. When a 1.5V card is placed in the system, the transistor is Off and the regulator regulates to 1.5V. When a 3.3V card is placed in the system, the transistor is On, and the feedback will be pulled to ground. When this happens, the regulator will drive the gate of the FET to nearly 12V. This will turn the FET on and pass 3.3V – (2 A * Rds

94 Intel

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7.5.2 VREF Generation for AGP 2.0 (2X and 4X)

VREF generation for AGP 2.0 is different, depending on the AGP card type used. The 3.3V AGP cards generate VREF locally. That is, they have a resistor divider on the card that divides VDDQ down to VREF the GMCH and graphics controller, 1.5V cards use source-generated VREF. That is, the VREF signal is generated at the graphi cs controlle r and sent to the GMCH, and another VREF is generated at the GMCH and sent to the graphics controller (see Figure 47).

Both the grap hics controller and the GMCH must generate VREF and distribute it through the connector (1.5V add-in cards only). The following two pins defined on the AGP 2.0 universal connector allow this VREF passing:

• VREFGC : VREF from the graphics controller to the chipset

• VREFCG : VREF from the chipset to the graphics controller

To preserve the common mode relationship between the VREF and data signals, the routing of the two VREF signals must be matched in length to the strobe lines, within 0.5 inch on the motherboard and within 0.25 inch on the add-in card.

(see Figure 47). To account for potential differences between VDDQ and GND at

The voltage divider networks consist of AC and DC ele ments, as shown in Figure 47. The VREF divider network should be placed as close as practical to the AGP interface, to get the

benefit of the common-mode power supply effects. However, the trace spacing around the VREF signals must be a minimum of 25 mils to reduce cross-talk and maintain signal integrity.

During 3.3V AGP 2.0 operation, VREF must be 0.4 VDDQ. However, during 1.5V AGP 2.0 operation, VREF must be 0.5 VDDQ. This requires a flexible voltage divider for VREF. Various methods of accomplishing this exist, and one such example is shown in Figure 47.

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Figure 47. AGP 2.0 VREF Generation and Distribution

a) 1.5V AGP Car

+12V

(See note 2)

Ω

1.5V AGP Card

1 K

TYPEDET#

VrefGC

300

200

VDDQ

500 pF

Ω

VDDQ

AGP

REF

Device

GND

VrefCG

Notes:

1. The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 10 mils from adjacent signals.

2. R7 is the same resistor seen in AGP VDDQ generation example circuit figure (R1)

mosfet

0.1 uF

REF

VDDQ

GMCH

GND

1 K

Ω

b) 3.3V AGP Card

+12V

(See note 2)

3.3V AGP Card

VDDQ

AGP

Device

GND

REF

1 K

VrefGC

Ω

TYPEDET#

mosfet

300

200

C10

0.1 uF

Ω

REF

VDDQ

GMCH

GND

VDDQ

1 K

Ω

500 pF

Ω

500 pF

Ω

VrefCG

The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 25 mils from adjacent signals.

agp_2.0ref_gen_dist

The flexible VREF divider shown in Figure 47 uses a FET switch to switch be tween the locally generated VREF (for 3.3V add-in cards) and the source-generated VREF (for 1.5V add-in cards).

Use of the source-generated VREF at the receiver is optional and is a product implementation issue beyond the scope of this document.

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7.6 Additional AGP Design Guidelines

7.6.1 Compensation

The GMCH AGP interface supports resistive buffer compensation (RCOMP). Tie the GRCOMP pin to a 40 Ω, 2% (or 39 Ω, 1%) pull-down resistor (to ground) via a 10-mil-wide, very short (<0.5 inch) trace.

7.6.2 AGP Pull-Ups

AGP control signals require pull-up resistors to VDDQ on the motherboard, to ensure that they contain stable values when no agent is actively driving the bus.

1X Timing Domain Signals Requiring Pull-Up Resist ors

The signals requiring pull-up resistors are:

• FRAME# • RBF#

• TRDY# • PIPE#

• IRDY# • REQ#

• DEVSEL# • WBF#

• STOP# • GNT#

• SERR# • ST[2:0]

• PERR#

Note: It is critical that these signals be pulled up to VDDQ, not 3.3V.

The trace stub to the pull-up resistor on 1X timing domain signals should be kept at less than

0.5 inch, to avoid signal reflections from the stub.

Note: The strobe signals require pull-ups/pull-downs on the motherboard to ensure that they contain

stable values when no agent is driving the bus.

Note: INTA# and INTB# should be pulled to 3.3V, not VDDQ.

2X/4X Timing Domain Signals

• AD_STB[1:0] (pull-up to VDDQ)

• SB_STB (pull-up to VDDQ)

• AD_STB[1:0]# (pull-down to ground)

• SB_STB# (pull-down to ground)

The trace stub to the pull-up/pull-down resistor on 2X/4X timing domain signals should be kept to less than 0.1 inch to avoid signal reflections from the stub.

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The pull-up/pull-down resistor value requirements are Rmin = 4 kΩ and Rmax = 16 kΩ. The recommended AGP pull-up/pull-down resistor value is 8.2 kΩ

7.6.2.1 AGP Signal Voltage Tolerance List

The following signals on the AGP interface are 3.3V tolerant during 1.5V operation:

• PME#

• INTA#

• INTB#

• GPERR#

• GSERR#

• CLK

• RST

The following signals on the AGP interface are 5V tolerant (refer to the USB specification):

• USB+

• USB-

• OVRCNT#

The following special AGP signal is either GROUNDED or NOT CONNECTED on an AGP card.

• TYPEDET#

Note: All other signals on the AGP interface are in the VDDQ group. They are not 3.3V tolerant during

1.5V operation.

7.7 Motherboard / Add-in Card Interoperability

There are three AGP connectors: 3.3V AGP connector, 1.5V AGP connector, and Universal AGP connector. To maximize add-in flexibility, it is highly advisable to implement the universal connector in a system based on the Intel 815 chipset platform. All add-in cards are either 3.3V or

1.5V cards. The 4X transfers at 3.3V are not allowed due to timings.

Table 25. Connector/Add-in Card Interoperability

Card 1.5V Connector 3.3V Connector Universal Connector

1.5V Card Yes No Yes

3.3V Card No Yes Yes

Table 26. Voltage/Data Rate Interoperability

Voltage 1X 2X 4X

1.5V VDDQ Yes Yes Yes

3.3V VDDQ Yes Yes No

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7.8 AGP / Display Cache Shared Interface

As described earlier, the AGP and display cache interfaces of the Intel 815 chipset platform are multiplexed or shared. In other words, the same component pins (balls) are used for both interfaces, although obviously only one interface can be supported at any given time. As a result, almost all display cache interface signals are mapped onto the new AGP interface. The Intel 815 chipset platform can be configured in either AGP mode or Graphics mode. In the AGP mode, the interface supports a full AGP 4X interface. In the Graphics mode, the interface becomes a display cache interface similar to the Intel display cache is optional. There do not have to be any SDRAM devices connected to the interface. The only dedicated display cache signals are OCLK and RCLK, which need not connect directly to the SDRAM devices. These are not mapped onto existing AGP signals.

7.8.1 GPA Card Considerations

To support the fullest flexibility, the display cache exists on an add-in card (Graphics Performance Accelerator, or GPA) that complies with the AGP connector form factor. If the motherboard designer follows the flexible routing guidelines for the AGP interface detailed in previous sections, the customer can choose to populate the AGP slot in a system based on the Intel 815 chipset platform with either an AGP graphics card, with a GPA card to enable the highest-possible internal graphics performance, or with nothing to get the lowest-cost internal graphics solution. Some of the GPA/ Intel 815 chipset platform for use with the universal socket 370 interfacing implications are listed below. For a complete description of the GPA card design, refer to the Graphics Performance Accelerator Card Specification available from Intel.

810E chipset. Note, however, that in the Graphics mode, the

• A strap is required to determine which frequency to select for display cache operation. This is

the L_FSEL pin of the GMCH. The GPA card will pull this signal up or down, as appropriate to communicate to the appropriate operating frequency to the Intel 815 chipset platform. The platform will sample this pin on the deasserting edge of reset.

• Since current SDRAM technology is always 3.3V rather than the 1.5V option also supported

by AGP, the GPA card should set the TYPEDET# signal correctly to indicate that it requires a

3.3V power supply. Furthermore, the GPA card should have only the 3.3V key and not the

1.5V key, thereby preventing it from being inserted into a 1.5V-only connector.

• The pad buffers on the chip will be the normal AGP buffers and will wo rk for both interfaces.

• In internal graphics mode, the AGPREF signal, which is required for the AGP mo de, should

remain functional as a reference voltage for sampling 3.3V LMD inputs. The voltage level on AGPREF should remain exactly the same as in the AGP mode, as opposed to VCC/2 used fo r previous products.

7.8.1.1 AGP and GPA Mechanical Considerations

The GPA card will be designed with a notch on the PCB to go around the AGP universal retention mechanism. To guarantee that the GPA card will meet all shock and vibration requirements of the system, the AGP universal retention mechanism will be req uired on all AGP sockets that are to support a GPA card.

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7.8.2 Display Cache Clocking

The display cache is clocked source-synchronously from a clock generated by the GMCH. The display cache clocking scheme uses three clock signals.

• LTCLK clocks the SDRAM devices, is muxed with an AGP signal, and should be routed

according to the flexible AGP guidelines.

• LOCLK and LRCLK clock the input buffers of the universal platform. LOCLK is an output

of the GMCH and is a buffered copy of LTCLK. LOCLK should be connected to LRCLK at the GMCH, with a length of PCB trace to create the appropriate clock skew relationship between the clock input (LRCLK) and the SDRAM capacitor clock input(s).

The guidelines are illustrated in Figure 48.

Figure 48. Display Cache Input Clocking

GMCH

LOCL

0.5"

Ω 1%

LRCL

15 pF 5%

1.5"

disp_cache_in_clk

The capacitor should be placed as close as possible to the GMCH LRCLK pin. To minimize skew variation, Intel recommends a 1% series termination resistor and a 5% NP0 (also known as C0G) capacitor, to stabilize the value across temperatures. In addition to the 15 Ω, 1% resistor and the 15 pF, 5% NP0 capacitor. The following combination also can be used: 10 Ω, 1% and 22 pF, 5% NP0.

7.9 Designs That Do Not Use The AGP Port

Universal platform designs that do not use the AGP port should terminate the AGP pins of the GMCH. Except for the GPAR pin (that requires a 100 kΩ pull-down resistor to ground), the pullup or pull-down resistor value should be 8.2 kΩ. Any external graphics implementation not using the AGP port should terminate the GMCH AGP control and strobe signals as recommend ed in Section 13.3.2.

100 Intel

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Intel 815 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Figures

Tables

Revision History

Introduction

1.3.2.1 Graphics Memory Controller Hub (GMCH)

1.3.2.3 Firmware Hub (FWH)

1.3.3.1 Universal Socket 370 Design

1.3.3.3 Accelerated Hub Architecture Interface

1.3.3.4 Internet Streaming SIMD Extensions

1.3.3.8 Low-Pin-Count (LPC) Interface

General Design Considerations

2.1 Nominal Board Stackup

Component Quadrant Layouts

4.1 Universal Socket 370 Definitions

Universal Socket 370 Design

4.2.1 Use of Universal Socket 370 Design with Incompatible GMCH

4.2.2 Identifying the Processor at the Socket

4.2.3 Setting the Appropriate Processor VTT Level

4.2.4 VTT Processor Pin AG1

4.2.5 Identifying the Processor at the GMCH

4.2.6 Configuring Non-VTT Processor Pins

4.2.8 Processor Signal PWRGOOD

4.2.9 APIC Clock Voltage Switching Requirements

4.2.10 GTLREF Topology and Layout

4.3 Power Sequencing on Wake Events

4.3.1 Gating of Intel® CK-815 to VTTPWRGD

4.3.2 Gating of PWROK to ICH

System Bus Design Guidelines

5.1 System Bus Routing Guidelines

5.1.1 Initial Timing Analysis

5.2 General Topology and Layout Guidelines

5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signal s

5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals

5.2.1.2 THRMDP and THRMDN

5.2.1.3 Additional Routing and Placement Considerations

5.3 Electrical Differences for Universal PGA370 Designs

5.4 PGA370 Socket Definition Details

5.5 BSEL[1:0] Implementation Differences

5.6 CLKREF Circuit Implementation

5.8 Processor Reset Requirements

5.9 Processor PLL Filter Recommendations

5.9.3 Recommendation for Intel Platforms

5.10 Voltage Regulation Guidelines

5.11 Decoupling Guidelines for Universal PGA370 Designs

5.11.2 VTT Decoupling Design

5.11.3 VREF Decoupling Design

5.12.1 Heatsink Volumetric Keepout Regions

5.13 Debug Port Changes

System Memory Design Guidelines

6.1 System Memory Routing Guidelines

6.2 System Memory 2-DIMM Design Guidelines

6.2.1 System Memory 2-DIMM Connectivity

6.2.2 System Memory 2-DIMM Layout Guidelines

6.3 System Memory 3-DIMM Design Guidelines

6.3.1 System Memory 3-DIMM Connectivity

6.3.2 System Memory 3-DIMM Layout Guidelines

6.4 System Memory Decoupling Guidelines

AGP/Display Cache Design Guidelines

7.1.1 Graphics Performance Accelerator (GPA)

7.1.2 AGP Universal Retention Mechanism (RM)

7.2.1 AG P I nter face Si gnal Groups

7.3 Standard AGP Routing Guidelines

7.3.1 1X Timing Domain Routing Guidelines

7.3.1.1 Flexible Motherboard Guidelines

7.3.1.2 AGP-Only Motherboard Guidelines

7.3.2 2X/4X Timing Domain Routing Guidelines

7.3.2.1 Flexible Motherboard Guidelines

7.3.2.2 AGP-Only Motherboard Guidelines

7.3.3 AGP Routing Guideline Considerations and Summary

7.3.4 AGP Clock Routing

7.3.5 AGP Signal Noise Decoupling Guidelines

7.3.6 AGP Routing Ground Reference

7.4 AGP Down Routing Guidelines

7.4.1 1X AGP Down Option Timing Domain Routing Guidelines

7.4.2 2X/4X AGP Down Timing Domain Routing Guidelines