INTEL 80C186EB, 80C188EB, 80L188EB, 80L186EB User Manual

查询TS80C186EB20供应商

80C186EB/80C188EBAND80L186EB/80L188EB

16-BITHIGH-INTEGRATIONEMBEDDEDPROCESSORS

IntegratedFeatureSet ÐLow-PowerStaticCPUCore ÐTwoIndependentUARTseachwith

anIntegralBaudRateGenerator ÐTwo8-BitMultiplexedI/OPorts ÐProgrammableInterruptController ÐThreeProgrammable16-Bit

Timer/Counters ÐClockGenerator ÐTenProgrammableChipSelectswith

IntegralWait-StateGenerator ÐMemoryRefreshControlUnit ÐSystemLevelTestingSupport(ONCE

Mode)

DirectAddressingCapabilityto1Mbyte Memoryand64KbyteI/O

SpeedVersionsAvailable(5V): Ð25MHz(80C186EB25/80C188EB25) Ð20MHz(80C186EB20/80C188EB20) Ð13MHz(80C186EB13/80C188EB13)

FullStaticOperation

TrueCMOSInputsandOutputs

AvailableinExtendedTemperature Range(

SpeedVersionsAvailable(3V): Ð16MHz(80L186EB16/80L188EB16) Ð13MHz(80L186EB13/80L188EB13)

Low-Power Operating Modes: Ð Idle Mode Freezes CPU Clocks but

keeps Peripherals Active

Ð Powerdown Mode Freezes All

Internal Clocks

Supports 80C187 Numeric Coprocessor Interface (80C186EB PLCC Only)

Available In: Ð 80-Pin Quad Flat Pack (QFP) Ð 84-Pin Plastic Leaded Chip Carrier

(PLCC)

Ð 80-Pin Shrink Quad Flat Pack (SQFP)

40§Ctoa85§C)

The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.

272433– 1

*Otherbrandsandnamesarethepropertyoftheirrespectiveowners. InformationinthisdocumentisprovidedinconnectionwithIntelproducts.Intelassumesnoliabilitywhatsoever,includinginfringementofanypatentor copyright,forsaleanduseofIntelproductsexceptasprovidedinIntel’sTermsandConditionsofSaleforsuchproducts.Intelretainstherighttomake changestothesespecificationsatanytime,withoutnotice.MicrocomputerProductsmayhaveminorvariationstothisspecificationknownaserrata.

©INTELCORPORATION,2002

June, 2002

OrderNumber:272433-005

80C186EB/80C188EB and 80L186EB/80L188EB

16-Bit High-Integration Embedded Processors

CONTENTS PAGE

INTRODUCTION ААААААААААААААААААААААААААА 4

CORE ARCHITECTURE ААААААААААААААААААА 4

Bus Interface Unit АААААААААААААААААААААААААА 4 Clock Generator ААААААААААААААААААААААААААА 4

80C186EC PERIPHERAL

ARCHITECTURE АААААААААААААААААААААААА 5

Interrupt Control Unit ААААААААААААААААААААААА 5 Timer/Counter Unit АААААААААААААААААААААААА 5 Serial Communications Unit АААААААААААААААА 7 Chip-Select Unit АААААААААААААААААААААААААААА 7 I/O Port Unit ААААААААААААААААААААААААААААААА 7 Refresh Control Unit ААААААААААААААААААААААА 7 Power Management Unit ААААААААААААААААААА 7 80C187 Interface (80C186EB Only) ААААААААА 7 ONCE Test Mode АААААААААААААААААААААААААА 7

PACKAGE INFORMATION АААААААААААААААА 8

Prefix Identification ААААААААААААААААААААААААА 8 Pin Descriptions АААААААААААААААААААААААААААА 8

80C186EB PINOUT ААААААААААААААААААААААА 14

PACKAGE THERMAL

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS ААААААААА 23

Absolute Maximum Ratings ААААААААААААААА 23

АААААААААААААААААААААА 22

CONTENTS PAGE

Recommended Connections

DC SPECIFICATIONS АААААААААААААААААААА 24

ICCversus Frequency and Voltage ААААААААА 27 PDTMR Pin Delay Calculation ААААААААААААА 27

AC SPECIFICATIONS АААААААААААААААААААА 28

AC CharacteristicsÐ80C186EB25 ААААААААА 28 AC CharacteristicsÐ80C186EB20/13 ААААА 30 AC CharacteristicsÐ80L186EB16 ААААААААА 32 Relative Timings АААААААААААААААААААААААААА 36 Serial Port Mode 0 Timings АААААААААААААААА 37

AC TEST CONDITIONS АААААААААААААААААА 38

AC TIMING WAVEFORMS ААААААААААААААА 38

DERATING CURVES ААААААААААААААААААААА 41

RESET ААААААААААААААААААААААААААААААААААА 42

BUS CYCLE WAVEFORMS АААААААААААААА 45

EXECUTION TIMINGS ААААААААААААААААААА 52

INSTRUCTION SET SUMMARY АААААААААА 53

ERRATA ААААААААААААААААААААААААААААААААА 59

REVISION HISTORY ААААААААААААААААААААА 59

АААААААААААААА 23

80C186EB/80C188EB, 80L186EB/80L188EB

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB

Figure 1. 80C186EB/80C188EB Block Diagram

272433– 2

80C186EB/80C188EB, 80L186EB/80L188EB

INTRODUCTION

Unless specifically noted, all references to the 80C186EB apply to the 80C188EB, 80L186EB, and 80L188EB. References to pins that differ between the 80C186EB/80L186EB and the 80C188EB/ 80L188EB are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physically and functionally, the ‘‘C’’ and ‘‘L’’ devices are identical.

The 80C186EB is the first product in a new generation of low-power, high-integration microprocessors. It enhances the existing 186 family by offering new features and new operating modes. The 80C186EB is object code compatible with the 80C186XL/ 80C188XL microprocessors.

The 80L186EB is the 3V version of the 80C186EB. The 80L186EB is functionally identical to the 80C186EB embedded processor. Current 80C186EB users can easily upgrade their designs to use the 80L186EB and benefit from the reduced power consumption inherent in 3V operation.

The feature set of the 80C186EB meets the needs of low power, space critical applications. Low-Power applications benefit from the static design of the CPU core and the integrated peripherals as well as low voltage operation. Minimum current consumption is achieved by providing a Powerdown mode that halts operation of the device, and freezes the clock circuits. Peripheral design enhancements ensure that non-initialized peripherals consume little current.

Space critical applications benefit from the integration of commonly used system peripherals. Two serial channels are provided for services such as diagnostics, inter-processor communication, modem interface, terminal display interface, and many others. A flexible chip select unit simplifies memory and peripheral interfacing. The interrupt unit provides sources for up to 129 external interrupts and will prioritize these interrupts with those generated from the on-chip peripherals. Three general purpose timer/counters and sixteen multiplexed I/O port pins round out the feature set of the 80C186EB.

Figure 1 shows a block diagram of the 80C186EB/ 80C188EB. The Execution Unit (EU) is an enhanced 8086 CPU core that includes: dedicated hardware to speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate instructions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instruction, and fully static operation. The Bus Interface Unit (BIU) is the same as that found on the original 186 family products, ex-

cept the queue status mode has been deleted and buffer interface control has been changed to ease system design timings. An independent internal bus is used to allow communication between the BIU and internal peripherals.

CORE ARCHITECTURE

Bus Interface Unit

The 80C186EB core incorporates a bus controller that generates local bus control signals. In addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters.

The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information, and data (for write operations) information. It is also responsible for reading data off the local bus during a read operation. A READY input pin is provided to extend a bus cycle beyond the minimum four states (clocks).

The local bus controller also generates two control signals (DEN nal transceiver chips. (Both DEN available on the PLCC devices, only DEN able on the QFP and SQFP devices.) This capability allows the addition of transceivers for simple buffering of the multiplexed address/data bus.

and DT/R) when interfacing to exter-

and DT/R are

is avail-

Clock Generator

The processor provides an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divideby-two counter, and two low-power operating modes.

The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-overtone mode crystal network. Alternatively, the oscillator circuit may be driven from an external clock source. Figure 2 shows the various operating modes of the oscillator circuit.

The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and the external CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to drive other system components. All AC timings are referenced to CLKOUT.

80C186EB/80C188EB, 80L186EB/80L188EB

272433– 4

(A) Crystal Connection

NOTE:

The L overtone crystal.

The following parameters are recommended when choosing a crystal:

Temperature Range: Application Specific ESR (Equivalent Series Resistance): 40X max C0 (Shunt Capacitance of Crystal): 7.0 pF max C

Drive Level: 1 mW max

network is only required when using a third-

1C1

(Load Capacitance): 20 pFg2pF

272433– 3

Figure 2. Clock Configurations

80C186EB PERIPHERAL ARCHITECTURE

The 80C186EB has integrated several common system peripherals with a CPU core to create a compact, yet powerful system. The integrated peripherals are designed to be flexible and provide logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt requests from the timer/counters or serial channels).

The list of integrated peripherals includes:

7-Input Interrupt Control Unit

3-Channel Timer/Counter Unit

2-Channel Serial Communications Unit

10-Output Chip-Select Unit

I/O Port Unit

Refresh Control Unit

Power Management Unit

The registers associated with each integrated periheral are contained within a 128 x 16 register file called the Peripheral Control Block (PCB). The PCB can be located in either memory or I/O space on any 256 Byte address boundary.

(B) Clock Connection

Figure 3 provides a list of the registers associated with the PCB. The Register Bit Summary at the end of this specification individually lists all of the registers and identifies each of their programming attributes.

Interrupt Control Unit

The 80C186EB can receive interrupts from a number of sources, both internal and external. The interrupt control unit serves to merge these requests on a priority basis, for individual service by the CPU. Each interrupt source can be independently masked by the Interrupt Control Unit (ICU) or all interrupts can be globally masked by the CPU.

Internal interrupt sources include the Timers and Serial channel 0. External interrupt sources come from the five input pins INT4:0. The NMI interrupt pin is not controlled by the ICU and is passed directly to the CPU. Although the Timer and Serial channel each have only one request input to the ICU, separate vector types are generated to service individual interrupts within the Timer and Serial channel units.

Timer/Counter Unit

The 80C186EB Timer/Counter Unit (TCU) provides three 16-bit programmable timers. Two of these are highly flexible and are connected to external pins for control or clocking. A third timer is not connected to any external pins and can only be clocked internally. However, it can be used to clock the other two timer channels. The TCU can be used to count external events, time external events, generate non-repetitive waveforms, generate timed interrupts. etc.

80C186EB/80C188EB, 80L186EB/80L188EB

PCB

Offset

00H Reserved

02H End Of Interrupt

04H Poll

06H Poll Status

08H Interrupt Mask

0AH Priority Mask

0CH In-Service

0EH Interrupt Request

10H Interrupt Status

12H Timer Control

14H Serial Control

16H INT4 Control

18H INT0 Control

1AH INT1 Control

1CH INT2 Control

1EH INT3 Control

20H Reserved

22H Reserved

24H Reserved

26H Reserved

28H Reserved

2AH Reserved

2CH Reserved

2EH Reserved

30H Timer0 Count

32H Timer0 Compare A

34H Timer0 Compare B

36H Timer0 Control

38H Timer1 Count

3AH Timer1 Compare A

3CH Timer1 Compare B

3EH Timer1 Control

Function

PCB

Offset

40H Timer2 Count

42H Timer2 Compare

44H Reserved

46H Timer2 Control

48H Reserved

4AH Reserved

4CH Reserved

4EH Reserved

50H Port 1 Direction

52H Port 1 Pin

54H Port 1 Control

56H Port 1 Latch

58H Port 2 Direction

5AH Port 2 Pin

5CH Port 2 Control

5EH Port 2 Latch

60H Serial0 Baud

62H Serial0 Count

64H Serial0 Control

66H Serial0 Status

68H Serial0 RBUF

6AH Serial0 TBUF

6CH Reserved

6EH Reserved

70H Serial1 Baud

72H Serial1 Count

74H Serial1 Control

76H Serial1 Status

78H Serial1 RBUF

7AH Serial1 TBUF

7CH Reserved

7EH Reserved

Function

PCB

Offset

80H GCS0 Start

82H GCS0 Stop

84H GCS1 Start

86H GCS1 Stop

88H GCS2 Start

8AH GCS2 Stop

8CH GCS3 Start

8EH GCS3 Stop

90H GCS4 Start

92H GCS4 Stop

94H GCS5 Start

96H GCS5 Stop

98H GCS6 Start

9AH GCS6 Stop

9CH GCS7 Start

9EH GCS7 Stop

A0H LCS Start

A2H LCS Stop

A4H UCS Start

A6H UCS Stop

A8H Relocation

AAH Reserved

ACH Reserved

AEH Reserved

B0H Refresh Base

B2H Refresh Time

B4H Refresh Control

B6H Reserved

B8H Power Control

BAH Reserved

BCH Step ID

BEH Reserved

Function

Figure 3. Peripheral Control Block Registers

PCB

Offset

C0H Reserved

C2H Reserved

C4H Reserved

C6H Reserved

C8H Reserved

CAH Reserved

CCH Reserved

CEH Reserved

D0H Reserved

D2H Reserved

D4H Reserved

D6H Reserved

D8H Reserved

DAH Reserved

DCH Reserved

DEH Reserved

E0H Reserved

E2H Reserved

E4H Reserved

E6H Reserved

E8H Reserved

EAH Reserved

ECH Reserved

EEH Reserved

F0H Reserved

F2H Reserved

F4H Reserved

F6H Reserved

F8H Reserved

FAH Reserved

FCH Reserved

FEH Reserved

Function

80C186EB/80C188EB, 80L186EB/80L188EB

Serial Communications Unit

The Serial Control Unit (SCU) of the 80C186EB contains two independent channels. Each channel is identical in operation except that only channel 0 is supported by the integrated interrupt controller (channel 1 has an external interrupt pin). Each channel has its own baud rate generator that is independent of the Timer/Counter Unit, and can be internally or externally clocked at up to one half the 80C186EB operating frequency.

Independent baud rate generators are provided for each of the serial channels. For the asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit register logic. A 1x baud clock is provided in the synchronous mode.

Chip-Select Unit

The 80C186EB Chip-Select Unit (CSU) integrates logic which provides up to ten programmable chipselects to access both memories and peripherals. In addition, each chip-select can be programmed to automatically insert additional clocks (wait-states) into the current bus cycle and automatically terminate a bus cycle independent of the condition of the READY input pin.

I/O Port Unit

The I/O Port Unit (IPU) on the 80C186EB supports two 8-bit channels of input, output, or input/output operation. Port 1 is multiplexed with the chip select pins and is output only. Most of Port 2 is multiplexed with the serial channel pins. Port 2 pins are limited to either an output or input function depending on the operation of the serial pin it is multiplexed with.

Refresh Control Unit

The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks between refresh requests.

A 12-bit address generator is maintained by the RCU and is presented on the A12:1 address lines during the refresh bus cycle. Address bits A19:13 are programmable to allow the refresh address block to be located on any 8 Kbyte boundary.

Power Management Unit

The 80C186EB Power Management Unit (PMU) is provided to control the power consumption of the device. The PMU provides three power modes: Active, Idle, and Powerdown.

Active Mode indicates that all units on the 80C186EB are functional and the device consumes maximum power (depending on the level of peripheral operation). Idle Mode freezes the clocks of the Execution and Bus units at a logic zero state (all peripherals continue to operate normally).

The Powerdown mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. All internal registers hold their values provided V is maintained. Current consumption is reduced to just transistor junction leakage.

80C187 Interface (80C186EB Only)

The 80C186EB (PLCC package only) supports the direct connection of the 80C187 Numerics Coprocessor.

ONCE Test Mode

To facilitate testing and inspection of devices when fixed into a target system, the 80C186EB has a test mode available which forces all output and input/ output pins to be placed in the high-impedance state. ONCE stands for ‘‘ON Circuit Emulation’’. The ONCE mode is selected by forcing the A19/ONCE pin LOW (0) during a processor reset (this pin is weakly held to a HIGH (1) level) while RESIN tive.

is ac-

80C186EB/80C188EB, 80L186EB/80L188EB

PACKAGE INFORMATION

This section describes the pins, pinouts, and thermal characteristics for the 80C186EB in the Plastic Leaded Chip Carrier (PLCC) package, Shrink Quad Flat Pack (SQFP), and Quad Flat Pack (QFP) package. For complete package specifications and information, see the Intel Packaging Outlines and Dimensions Guide (Order Number: 231369).

Prefix Identification

With the extended temperature range, operational characteristics are guaranteed over the temperature range corresponding to Package types are identified by a two-letter prefix to the part number. The prefixes are listed in Table 1.

Table 1. Prefix Identification

Prefix Note

TN PLCC Extended

TS QFP (EIAJ) Extended

SB 1 SQFP Extended/Commercial

N 1 PLCC Commercial

S 1 QFP (EIAJ) Commercial

NOTE:

1. The 5V 25 MHz and 3V 16 MHz versions are only available in commercial temperature range corresponding to

Ctoa70§C ambient.

40§Ctoa85§C ambient.

Package Temperature

Type Type

Pin Descriptions

Each pin or logical set of pins is described in Table

3. There are three columns for each entry in the Pin

Description Table.

The Pin Type column contains two kinds of information. The first symbol indicates whether a pin is power (P), ground (G), input only (I), output only (O) or input/output (I/O). Some pins have multiplexed functions (for example, A19/S6). Additional symbols indicate additional characteristics for each pin. Table 2 lists all the possible symbols for this column.

The Input Type column indicates the type of input (Asynchronous or Synchronous).

Asynchronous pins require that setup and hold times be met only in order to guarantee particular clock edge. Synchronous pins require that setup and hold times be met to guarantee proper

operation.

time for the SRDY pin (a synchronous input) will result in a system failure or lockup. Input pins may also be edge- or level-sensitive. The possible characteristics for input pins are S(E), S(L), A(E) and A(L).

The Output States column indicates the output state as a function of the device operating mode. Output states are dependent upon the current activity of the processor. There are four operational states that are different from regular operation: bus hold, reset, Idle Mode and Powerdown Mode. Appropriate characteristics for these states are also indicated in this column, with the legend for all possible characteristics in Table 2.

The Pin Description column contains a text description of each pin.

As an example, consider AD15:0. I/O signifies the pins are bidirectional. S(L) signifies that the input function is synchronous and level-sensitive. H(Z) signifies that, as outputs, the pins are high-impedance upon acknowledgement of bus hold. R(Z) signifies that the pins float during reset. P(X) signifies that the pins retain their states during Powerdown Mode.

For example, missing the setup or hold

recognition

at a

The Pin Name column contains a mnemonic that describes the pin function. Negation of the signal name (for example, RESIN active low.

) denotes a signal that is

80C186EB/80C188EB, 80L186EB/80L188EB

Table 2. Pin Description Nomenclature

Symbol Description

P Power Pin (ApplyaVCCVoltage) G Ground (Connect to V I Input Only Pin O Output Only Pin I/O Input/Output Pin

S(E) Synchronous, Edge Sensitive S(L) Synchronous, Level Sensitive A(E) Asynchronous, Edge Sensitive A(L) Asynchronous, Level Sensitive

H(1) Output Driven to VCCduring Bus Hold H(0) Output Driven to V H(Z) Output Floats during Bus Hold H(Q) Output Remains Active during Bus Hold H(X) Output Retains Current State during Bus Hold

R(WH) Output Weakly Held at VCCduring Reset R(1) Output Driven to V R(0) Output Driven to V R(Z) Output Floats during Reset R(Q) Output Remains Active during Reset R(X) Output Retains Current State during Reset

I(1) Output Driven to VCCduring Idle Mode I(0) Output Driven to V I(Z) Output Floats during Idle Mode I(Q) Output Remains Active during Idle Mode I(X) Output Retains Current State during Idle Mode

P(1) Output Driven to VCCduring Powerdown Mode P(0) Output Driven to V P(Z) Output Floats during Powerdown Mode P(Q) Output Remains Active during Powerdown Mode P(X) Output Retains Current State during Powerdown Mode

)

during Bus Hold

during Reset

during Idle Mode

during Powerdown Mode

80C186EB/80C188EB, 80L186EB/80L188EB

Table 3. Pin Descriptions

Pin Pin Input Output

Name Type Type States

PÐ ÐPOWER connections consist of four pins which must be

shorted externally to a V

GÐ ÐGROUND connections consist of six pins which must be

shorted externally to a V

CLKIN I A(E) Ð CLocK INput is an input for an external clock. An external

oscillator operating at two times the required processor operating frequency can be connected to CLKIN. For crystal operation, CLKIN (along with OSCOUT) are the crystal connections to an internal Pierce oscillator.

OSCOUT O Ð H(Q) OSCillator OUTput is only used when using a crystal to

R(Q) P(Q)

generate the external clock. OSCOUT (along with CLKIN) are the crystal connections to an internal Pierce oscillator. This pin is not to be used as 2X clock output for non-crystal applications (i.e., this pin is N.C. for non-crystal applications). OSCOUT does not float in ONCE mode.

CLKOUT O Ð H(Q) CLocK OUTput provides a timing reference for inputs and

R(Q) P(Q)

outputs of the processor, and is one-half the input clock (CLKIN) frequency. CLKOUT has a 50% duty cycle and transistions every falling edge of CLKIN.

RESIN I A(L) Ð RESet IN causes the processor to immediately terminate

any bus cycle in progress and assume an initialized state. All pins will be driven to a known state, and RESOUT will also be driven active. The rising edge (low-to-high) transition synchronizes CLKOUT with CLKIN before the processor begins fetching opcodes at memory location 0FFFF0H.

RESOUT O Ð H(0) RESet OUTput that indicates the processor is currently in

R(1) P(0)

the reset state. RESOUT will remain active as long as RESIN remains active.

PDTMR I/O A(L) H(WH) Power-Down TiMeR pin (normally connected to an external

R(Z)

P(1)

capacitor) that determines the amount of time the processor waits after an exit from power down before resuming normal operation. The duration of time required will depend on the startup characteristics of the crystal oscillator.

NMI I A(E) Ð Non-Maskable Interrupt input causes a TYPE-2 interrupt to

be serviced by the CPU. NMI is latched internally.

TEST/BUSY I A(E) Ð TEST is used during the execution of the WAIT instruction to (TEST

)

suspend CPU operation until the pin is sampled active (LOW). TEST is alternately known as BUSY when interfacing with an 80C187 numerics coprocessor (80C186EB only).

AD15:0 I/O S(L) H(Z) These pins provide a multiplexed Address and Data bus. (AD7:0) R(Z)

P(X)

During the address phase of the bus cycle, address bits 0 through 15 (0 through 7 on the 80C188EB) are presented on the bus and can be latched using ALE. 8- or 16-bit data information is transferred during the data phase of the bus cycle.

Description

board plane.

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

80C186EB/80C188EB, 80L186EB/80L188EB

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

A18:16 I/O A(L) H(Z) These pins provide multiplexed Address during the address A19/ONCE

R(WH) (A15:A8) P(X) (A18:16) (A19/ONCE)

phase of the bus cycle. Address bits 16 through 19 are presented on these pins and can be latched using ALE. These pins are driven to a logic 0 during the data phase of the bus cycle. On the 80C188EB, A15–A8 provide valid address information for the entire bus cycle. During a processor reset (RESIN ONCE

is used to enable ONCE mode. A18:16 must not be driven

low during reset or improper operation may result.

S2:0 O Ð H(Z) Bus cycle Status are encoded on these pins to provide bus

transaction information. S2:0

R(Z) P(1)

S1 S0 Bus Cycle Initiated

0 0 0 Interrupt Acknowledge 0 0 1 Read I/O 0 1 0 Write I/O 0 1 1 Processor HALT 1 0 0 Queue Instruction Fetch 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive (no bus activity)

ALE O Ð H(0) Address Latch Enable output is used to strobe address

information into a transparent type latch during the address phase

R(0)

of the bus cycle.

P(0)

BHE O Ð H(Z) Byte High Enable output to indicate that the bus cycle in progress

) R(Z)

(RFSH

is transferring data over the upper half of the data bus. BHE A0 have the following logical encoding

P(X)

A0 BHE Encoding (for the 80C186EB/80L186EB only)

0 0 Word Transfer 0 1 Even Byte Transfer 1 0 Odd Byte Transfer 1 1 Refresh Operation

On the 80C188EB/80L188EB, RFSH is asserted low to indicate a refresh bus cycle.

RD O Ð H(Z) ReaD output signals that the accessed memory or I/O device

must drive data information onto the data bus.

R(Z) P(1)

WR O Ð H(Z) WRite output signals that data available on the data bus are to be

written into the accessed memory or I/O device.

R(Z) P(1)

READY I A(L) Ð READY input to signal the completion of a bus cycle. READY

S(L)

must be active to terminate any bus cycle, unless it is ignored by correctly programming the Chip-Select Unit.

DEN O Ð H(Z) Data ENable output to control the enable of bi-directional

transceivers in a buffered system. DEN

R(Z)

to be transferred on the bus.

P(1)

Description

active), A19/

are encoded as follows:

and

is active only when data is

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

80C186EB/80C188EB, 80L186EB/80L188EB

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

DT/R O Ð H(Z) Data Transmit/Receive output controls the direction of a

R(Z) P(X)

bi-directional buffer in a buffered system. DT/R available for the PLCC package.

LOCK O Ð H(Z) LOCK output indicates that the bus cycle in progress is not

R(WH)

P(1)

to be interrupted. The processor will not service other bus requests (such as HOLD) while LOCK configured as a weakly held high input while RESIN active and must not be driven low.

HOLD I A(L) Ð HOLD request input to signal that an external bus master

wishes to gain control of the local bus. The processor will relinquish control of the local bus between instruction boundaries not conditioned by a LOCK prefix.

HLDA O Ð H(1) HoLD Acknowledge output to indicate that the processor

R(0)

P(0)

has relinquished control of the local bus. When HLDA is asserted, the processor will (or has) floated its data bus and control signals allowing another bus master to drive the signals directly.

NCS O Ð H(1) Numerics Coprocessor Select output is generated when (N.C.) R(1)

P(1)

accessing a numerics coprocessor. NCS is not provided on the QFP or SQFP packages. This signal does not exist on the 80C188EB/80L188EB.

ERROR I A(L) Ð ERROR input that indicates the last numerics coprocessor (N.C.)

operation resulted in an exception condition. An interrupt TYPE 16 is generated if ERROR beginning of a numerics operation. ERROR on the QFP or SQFP packages. This signal does not exist on the 80C188EB/80L188EB.

PEREQ I A(L) Ð CoProcessor REQuest signals that a data transfer (N.C.)

between an External Numerics Coprocessor and Memory is pending. PEREQ is not provided on the QFP or SQFP packages. This signal does not exist on the 80C188EB/ 80L188EB.

UCS O Ð H(1) Upper Chip Select will go active whenever the address of

R(1)

P(1)

a memory or I/O bus cycle is within the address limitations programmed by the user. After reset, UCS be active for memory accesses between 0FFC00H and 0FFFFFH.

LCS O Ð H(1) Lower Chip Select will go active whenever the address of

R(1)

P(1)

a memory bus cycle is within the address limitations programmed by the user. LCS

P1.0/GCS0 O Ð H(X)/H(1) These pins provide a multiplexed function. If enabled, each P1.1/GCS1 P1.2/GCS2 P1.3/GCS3 P1.4/GCS4 P1.5/GCS5 P1.6/GCS6

R(1)

P(X)/P(1)

pin can provide a Generic Chip Select output which will go active whenever the address of a memory or I/O bus cycle is within the address limitations programmed by the user. When not programmed as a Chip-Select, each pin may be used as a general purpose output Port. As an output port pin, the value of the pin can be read internally.

P1.7/GCS7

Description

is only

is active. This pin is

is sampled active at the

is not provided

is configured to

is inactive after a reset.

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

80C186EB/80C188EB, 80L186EB/80L188EB

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

T0OUT O Ð H(Q) Timer OUTput pins can be programmed to provide a T1OUT R(1)

P(Q)

single clock or continuous waveform generation, depending on the timer mode selected.

T0IN I A(L) Ð Timer INput is used either as clock or control signals, T1IN A(E)

depending on the timer mode selected.

INT0 I A(E,L) Ð Maskable INTerrupt input will cause a vector to a INT1 INT4

specific Type interrupt routine. To allow interrupt expansion, INT0 and/or INT1 can be used with INTA0

and INTA1 to interface with an external slave

controller.

INT2/INTA0 I/O A(E,L) H(1) These pins provide a multiplexed function. As inputs, INT3/INTA1

R(Z)

P(1)

they provide a maskable INTerrupt that will cause the CPU to vector to a specific Type interrupt routine. As outputs, each is programmatically controlled to provide an INTERRUPT ACKNOWLEDGE handshake signal to allow interrupt expansion.

P2.7 I/O A(L) H(X) BI-DIRECTIONAL, open-drain Port pins. P2.6 R(Z)

P(X)

CTSO I A(L) Ð Clear-To-Send input is used to prevent the P2.4/CTS1

transmission of serial data on their respective TXD signal pin. CTS1 is multiplexed with an input only port function.

TXD0 O Ð H(X)/H(Q) Transmit Data output provides serial data P2.1/TXD1 R(1)

P(X)/P(Q)

information. TXD1 is multiplexed with an output only Port function. During synchronous serial communications, TXD will function as a clock output.

RXD0 I/O A(L) R(Z) Receive Data input accepts serial data information. P2.0/RXD1 H(Q)

P(X)

RXD1 is multiplexed with an input only Port function. During synchronous serial communications, RXD is bi-directional and will become an output for transmission or data (TXD becomes the clock).

P2.5/BCLK0 I A(L)/A(E) Ð Baud CLocK input can be used as an alternate clock P2.2/BCLK1

source for each of the integrated serial channels. BCLKx is multiplexed with an input only Port function, and cannot exceed a clock rate greater than one-half the operating frequency of the processor.

P2.3/SINT1 O Ð H(X)/H(Q) Serial INTerrupt output will go active to indicate

R(0)

P(X)/P(X)

serial channel 1 requires service. SINT1 is multiplexed with an output only Port function.

Description

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

80C186EB/80C188EB, 80L186EB/80L188EB

80C186EB PINOUT

Tables 4 and 5 list the 80C186EB/80C188EB pin names with package location for the 84-pin Plastic Leaded Chip Carrier (PLCC) component. Figure 5 depicts the complete 80C186EB/80C188EB pinout (PLCC package) as viewed from the top side of the component (i.e., contacts facing down).

Table 4. PLCC Pin Names with Package Location

Address/Data Bus

Name Location

AD0 61 AD1 66 AD2 68 AD3 70 AD4 72 AD5 74 AD6 76 AD7 78 AD8 (A8) 62 AD9 (A9) 67 AD10 (A10) 69 AD11 (A11) 71 AD12 (A12) 73 AD13 (A13) 75 AD14 (A14) 77 AD15 (A15) 79 A16 80 A17 81 A18 82 A19/ONCE

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

Bus Control

Name Location

ALE 6 BHE

(RFSH)7

S0 S1 S2 8

RD 4 WR

READY 18

DEN DT/R

LOCK 15

HOLD 13 HLDA 12

Power

Name Location

11 16

2, 22, 43

63, 65, 84

1, 23

42, 64

Tables 6 and 7 list the 80C186EB/80C188EB pin names with package location for the 80-pin Quad Flat Pack (QFP) component. Figure 6 depicts the complete 80C186EB/80C188EB (QFP package) as viewed from the top side of the component (i.e., contacts facing down).

Tables 8 and 9 list the 80186EB/80188EB pin names with package location for the 80-pin Shrink Quad Flat Pack (SQFP) component. Figure 7 depicts the complete 80C186EB/80C188EB (SQFP package) as viewed from the top side of the component (i.e., contacts facing down).

Processor Control

Name Location

RESIN 37 RESOUT 38

CLKIN 41 OSCOUT 40 CLKOUT 44

TEST/BUSY 14

(N.C.) 60

NCS PEREQ (N.C.) 39 ERROR

(N.C.) 3

PDTMR 36

NMI 17 INT0 31 INT1 32 INT2/INTA0 INT3/INTA1 INT4 35

33 34

UCS 30 LCS P1.0/GCS0 P1.1/GCS1 P1.2/GCS2 26 P1.3/GCS3 25 P1.4/GCS4 P1.5/GCS5 P1.6/GCS6 P1.7/GCS7

T0OUT 45 T0IN 46 T1OUT 47 T1IN 48

RXD0 53 TXD0 52 P2.5/BCLK0 54 CTS0

P2.0/RXD1 57 P2.1/TXD1 58 P2.2/BCLK1 59 P2.3/SINT1 55 P2.4/CTS1

P2.6 50 P2.7 49

I/O

Name Location

29 28 27

24 21 20 19

Table 5. PLCC Package Locations with Pin Name

Location Name

3 ERROR (N.C.) 4RD 5WR 6 ALE 7 BHE

(RFSH) 8S2 9S1

10 S0 11 DEN 12 HLDA 13 HOLD 14 TEST

/BUSY 15 LOCK 16 DT/R 17 NMI 18 READY 19 P1.7/GCS7 20 P1.6/GCS6 21 P1.5/GCS5

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

Location Name

22 V 23 V

24 P1.4/GCS4 25 P1.3/GCS3 26 P1.2/GCS2 27 P1.1/GCS1 28 P1.0/GCS0 29 LCS 30 UCS 31 INT0 32 INT1 33 INT2/INTA0 34 INT3/INTA1 35 INT4 36 PDTMR 37 RESIN 38 RESOUT 39 PEREQ (N.C.) 40 OSCOUT 41 CLKIN 42 V

80C186EB/80C188EB, 80L186EB/80L188EB

Location Name

43 V

44 CLKOUT 45 T0OUT 46 T0IN 47 T1OUT 48 T1IN 49 P2.7 50 P2.6 51 CTS0 52 TXD0 53 RXD0 54 P2.5/BCLK0 55 P2.3/SINT1 56 P2.4/CTS1 57 P2.0/RXD1 58 P2.1/TXD1 59 P2.2/BCLK1 60 NCS

(N.C.) 61 AD0 62 AD8 (A8) 63 V

Location Name

64 V 65 V

66 AD1 67 AD9 (A9) 68 AD2 69 AD10 (A10) 70 AD3 71 AD11 (A11) 72 AD4 73 AD12 (A12) 74 AD5 75 AD13 (A13) 76 AD6 77 AD14 (A14) 78 AD7 79 AD15 (A15) 80 A16 81 A17 82 A18 83 A19/ONCE 84 V

80C186EB/80C188EB, 80L186EB/80L188EB

NOTE:

This is the FPO number location (indicated by X’s). Pin names in parentheses apply to the 80C188EB/80L188EB.

Figure 4. 84-Pin Plastic Leaded Chip Carrier Pinout Diagram

272433– 5

Table 6. QFP Pin Name with Package Location

Address/Data Bus

Name Location

AD0 10 AD1 15 AD2 17 AD3 19 AD4 21 AD5 23 AD6 25 AD7 27 AD8 (A8) 11 AD9 (A9) 16 AD10 (A10) 18 AD11 (A11) 20 AD12 (A12) 22

Bus Control

Name Location

ALE 38 BHE

(RFSH)39

S0 S1

42 41

S2 40

RD 36 WR

READY 49

DEN

LOCK

HOLD 45

HLDA 44 AD13 (A13) 24 AD14 (A14) 26 AD15 (A15) 28 A16 29 A17 30 A18 31 A19/ONCE

Power

Name Location

12, 14, 33 35, 53, 73

13, 34 54, 72

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

80C186EB/80C188EB, 80L186EB/80L188EB

Processor Control

Name Location

RESIN 68 RESOUT 69 CLKIN 71 OSCOUT 70 CLKOUT 74 TEST 46 PDTMR 67 NMI 48 INT0 62 INT1 63 INT2/INTA0

64 INT3/INTA1 65 INT4 66

UCS 61 LCS P1.0/GCS0 P1.1/GCS1 P1.2/GCS2 57 P1.3/GCS3 56 P1.4/GCS4 P1.5/GCS5 P1.6/GCS6 P1.7/GCS7 T0OUT 75 T0IN 76 T1OUT 77 T1IN 78 RXD0 3 TXD0 2 P2.5/BCLK0 4 CTS0 P2.0/RXD1 7 P2.1/TXD1 8 P2.2/BCLK1 9 P2.3/SINT1 5 P2.4/CTS1

P2.6 80 P2.7 79

I/O

Name Location

60 59 58

55 52 51 50

80C186EB/80C188EB, 80L186EB/80L188EB

Table 7. QFP Package Location with Pin Names

Location Name

1 CTS0 2 TXD0 3 RXD0 4 P2.5/BCLK0 5 P2.3/SINT1 6 P2.4/CTS1 7 P2.0/RXD1 8 P2.1/TXD1

9 P2.2/BCLK1 10 AD0 11 AD8 (A8) 12 V 13 V 14 V

15 AD1 16 AD9 (A9) 17 AD2 18 AD10 (A10) 19 AD3 20 AD11 (A11)

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

Location Name

21 AD4 22 AD12 (A12) 23 AD5 24 AD13 (A13) 25 AD6 26 AD14 (A14) 27 AD7 28 AD15 (A15) 29 A16 30 A17 31 A18 32 A19/ONCE 33 V 34 V 35 V

36 RD 37 WR 38 ALE 39 BHE

(RFSH)

40 S2

Location Name

41 S1 42 S0 43 DEN 44 HLDA 45 HOLD 46 TEST 47 LOCK 48 NMI 49 READY 50 P1.7/GCS7 51 P1.6/GCS6 52 P1.5/GCS5 53 V 54 V

55 P1.4/GCS4 56 P1.3/GCS3 57 P1.2/GCS2 58 P1.1/GCS1 59 P1.0/GCS0 60 LCS

Location Name

61 UCS 62 INT0 63 INT1 64 INT2/INTA0 65 INT3/INTA1 66 INT4 67 PDTMR 68 RESIN 69 RESOUT 70 OSCOUT 71 CLKIN 72 V 73 V

74 CLKOUT 75 T0OUT 76 T0IN 77 T1OUT 78 T1IN 79 P2.7 80 P2.6

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