80C186XL/80C188XL
Microprocessor
User’s Manual
80C186XL/80C188XL
Microprocessor
User’s Manual
1995
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including
infringement of any patent or copy righ t, for sale and use of In tel pro du cts exce pt as pr ovid ed in Int el’s Ter ms and Con ditio ns
of Sale for such products.
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear
in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
MDS is an ordering code only and is not used as a product name or trademark of Intel Corpo rat ion.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark
or products.
*Other brands and names are the property of their respective owners.
Additional copies of this document or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
© INTEL CORPORATION, 1995
CONTENTS
CHAPTER 1
INTRODUCTION
1.1 HOW TO USE THIS MANUAL....................................................................................... 1-2
1.2 RELATED DOCUMENTS.............................................................................................. 1-3
1.3 ELECTRONIC SUPPORT SYSTEMS........................................................................... 1-4
1.3.1 FaxBack Service .......................................................................................................1-4
1.3.2 Bulletin Board System (BBS) ....................................................................................1-5
1.3.2.1 How to Find
1.3.3 CompuServe Forums ................................................................................................1-6
1.3.4 World Wide Web .......................................................................................................1-6
1.4 TECHNICAL SUPPORT................................................................................................ 1-6
1.5 PRODUCT LITERATURE.............................................................................................. 1-7
1.6 TRAINING CLASSES.............................................................. ................................. ..... 1-7
CHAPTER 2
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1 ARCHITECTURAL OVERVIEW.................................................................................... 2-1
2.1.1 Execution Unit .............................................................. ...... ................................. ......2-2
2.1.2 Bus Interface Unit .....................................................................................................2-3
2.1.3 General Registers .....................................................................................................2-4
2.1.4 Segment Registers ...................................................................................................2-5
2.1.5 Instruction Pointer .....................................................................................................2-6
2.1.6 Flags .........................................................................................................................2-7
2.1.7 Memory Segmentation ..............................................................................................2-8
2.1.8 Logical Addresses ...................................................................................................2-10
2.1.9 Dynamically Relocatable Code ...............................................................................2-13
2.1.10 Stack Implementation .............................................................................................2-15
2.1.11 Reserved Memory and I/O Space ...........................................................................2-15
2.2 SOFTWARE OVERVIEW............................................................................................ 2-17
2.2.1 Instruction Set .........................................................................................................2-17
2.2.1.1 Data Transfer Instructions .............................................................................2-18
2.2.1.2 Arithmetic Instructions ........................................ .................................. .........2-19
2.2.1.3 Bit Manipulation Instructions .........................................................................2-21
2.2.1.4 String Instructions ..........................................................................................2-22
2.2.1.5 Program Transfer Instructions .......................................................................2-23
2.2.1.6 Processor Control Instructions ......................................................................2-27
2.2.2 Addressing Modes ..................................................................................................2-27
2.2.2.1 Register and Immediate Operand Addressing Modes ...................................2-27
2.2.2.2 Memory Addressing Modes ...........................................................................2-28
2.2.2.3 I/O Port Addressing .......................................................................................2-36
2.2.2.4 Data Types Used in the 80C186 Modular Core Family .................................2-37
Ap
BUILDER Software and Hypertext Documents on the BBS ...1-6
iii
CONTENTS
2.3 INTERRUPTS AND EXCEPTION HANDLING............................................................ 2-39
2.3.1 Interrupt/Exception Processing ...............................................................................2-39
2.3.1.1 Non-Maskable Interrupts ................................................................ ...... .........2-42
2.3.1.2 Maskable Interrupts .......................................................................................2-43
2.3.1.3 Exceptions .....................................................................................................2-43
2.3.2 Software Interrupts ..................................................................................................2-45
2.3.3 Interrupt Latency ......................................... ...... ..... .................................. ...............2-45
2.3.4 Interrupt Response Time ........................................................ ................................2-46
2.3.5 Interrupt and Exception Pri orit y .......................................................... .....................2-46
CHAPTER 3
BUS INTERFACE UNIT
3.1 MULTIPLEXED ADDRESS AND DATA BUS................................................................ 3-1
3.2 ADDRESS AND DATA BUS CONCEPTS..................................................................... 3-1
3.2.1 16-Bit Data Bus .........................................................................................................3-1
3.2.2 8-Bit Data Bus ...........................................................................................................3-5
3.3 MEMORY AND I/O INTERFACES................................................................................. 3-6
3.3.1 16-Bit Bus Memory and I/O Requirements ...............................................................3-7
3.3.2 8-Bit Bus Memory and I/O Requirements ............................... ...... ............................3-7
3.4 BUS CYCLE OPERATION............................................................................................ 3-7
3.4.1 Address/Status Phase ................................................. ...... ................................. ....3-10
3.4.2 Data Phase .............................................................................................................3-13
3.4.3 Wait States ..............................................................................................................3-13
3.4.4 Idle States ...............................................................................................................3-18
3.5 BUS CYCLES.............................................................................................................. 3-20
3.5.1 Read Bus Cycles ....................................................................................................3-20
3.5.1.1 Refresh Bus Cycles .......................................................................................3-22
3.5.2 Write Bus Cycles .....................................................................................................3-22
3.5.3 Interrupt Acknowledg e Bus Cycle .................................................................. ..... ....3-25
3.5.3.1 System Design Considerations .....................................................................3-27
3.5.4 HALT Bus Cycle ......................................................................................................3-28
3.5.5 Temporarily Exiting the HALT Bus State ....................................... ..... .....................3-30
3.5.6 Exiting HALT ...........................................................................................................3-32
3.6 SYSTEM DESIGN ALTERNATIVES.................................................. ......................... 3-33
3.6.1 Buffering the Data Bus ............................................................................................3-34
3.6.2 Synchronizing Software and Hardware Events .......................................................3-36
3.6.3 Using a Locked Bus ................................................................................................3-37
3.6.4 Using the Queue Status Signals .............................................................................3-38
3.7 MULTI-MASTER BUS SYSTEM DESIGNS................................................................. 3-39
3.7.1 Entering Bus HOLD ................... ...... ...... ................................. ................................3-39
3.7.1.1 HOLD Bus Latency ........................................................................................3-40
3.7.1.2 Refresh Operation During a Bus HOLD ........................................................3-41
3.7.2 Exiting HOLD ..........................................................................................................3-43
3.8 BUS CYCLE PRIORITIES........................................................................................... 3-44
iv
CONTENTS
CHAPTER 4
PERIPHERAL CONTROL BLOCK
4.1 PERIPHERAL CONTROL REGISTERS........................................................................ 4-1
4.2 PCB RELOCATION REGISTER.................................................................................... 4-1
4.3 RESERVED LOCATIONS............................................................................................. 4-4
4.4 ACCESSING THE PERIPHERAL CONTROL BLOCK.................................................. 4-4
4.4.1 Bus Cycles ...............................................................................................................4-4
4.4.2 READY Signals and Wait States .............................................................................4-4
4.4.3 F-Bus Operation .......................................................................................................4-5
4.4.3.1 Writing the PCB Relocation Register ...............................................................4-6
4.4.3.2 Accessing the Peripheral Control Registers ....................................................4-6
4.4.3.3 Accessing Reserved Locations .......................................................................4-6
4.5 SETTING THE PCB BASE LOCATION......................................................................... 4-6
4.5.1 Considerations for the 80C187 Math Coprocessor Interface ....................................4-7
CHAPTER 5
CLOCK GENERATION AND POWER MANAGEMENT
5.1 CLOCK GENERATION.................................................................................................. 5-1
5.1.1 Crystal Oscillator .......................................................................................................5-1
5.1.1.1 Oscillator Operation .........................................................................................5-2
5.1.1.2 Selecting Crystals ............................................................................................5-5
5.1.2 Using an External Oscillator ......................................................................................5-6
5.1.3 Output from the Clock Generator ................................. ...... ..... ..................................5-6
5.1.4 Reset and Clock Synchronization .............................................................................5-6
5.2 POWER MANAGEMENT.................................. ...... ................................. ...... ...... ..... ... 5-10
5.2.1 Power-Save Mode ................ ..... ...... .................................. ................................. ....5-11
5.2.1.1 Entering Power-Save Mode ................................................ ..........................5-11
5.2.1.2 Leaving Power-Save Mode ...........................................................................5-13
5.2.1.3 Example Power-Save Initialization Code .......................................................5-13
CHAPTER 6
CHIP-SELECT UNIT
6.1 COMMON METHODS FOR GENERATING CHIP-SELECTS....................................... 6-1
6.2 CHIP-SELECT UNIT FEATURES AND BENEFITS...................................................... 6-1
6.3 CHIP-SELECT UNIT FUNCTIONAL OVERVIEW......................................................... 6-2
6.4 PROGRAMMING........................................................................................................... 6-6
6.4.1 Initialization Sequence ..............................................................................................6-6
6.4.2 Programming the Active Ranges ............................................................................6-12
6.4.2.1 UCS
6.4.2.2 LCS
6.4.2.3 MCS
6.4.2.4 PCS
6.4.3 Bus Wait State and Ready Control .........................................................................6-15
6.4.4 Overlapping Chip-Selects .......................................................................................6-16
Active Range ........................................................................................6-12
Active Range .........................................................................................6-13
Active Range ........................................................................................6-13
Active Range .........................................................................................6-15
v
CONTENTS
6.4.5 Memory or I/O Bus Cycle Decoding ........................................................................6-17
6.4.6 Programming Considerations ..................................................................................6-17
6.5 CHIP-SELECTS AND BUS HOLD............................................................................... 6-18
6.6 EXAMPLES ................................................................................................................. 6-18
6.6.1 Example 1: Typical System Configuration ..............................................................6-18
CHAPTER 7
REFRESH CONTROL UNIT
7.1 THE ROLE OF THE REFRESH CONTROL UNIT......................................................... 7-2
7.2 REFRESH CONTROL UNIT CAPABILITIES........................... ................................. ..... 7-2
7.3 REFRESH CONTROL UNIT OPERATION.............................. ..... ...... ........................... 7-2
7.4 REFRESH ADDRESSES......................................................... ..... ................................. 7-4
7.5 REFRESH BUS CYCLES....................................... ..... .................................. ...... .......... 7-5
7.6 GUIDELINES FOR DESIGNING DRAM CONTROLLERS............................................ 7-5
7.7 PROGRAMMING THE REFRESH CONTROL UNIT..................................................... 7-7
7.7.1 Calculating the Refresh Interval ................................................................................7-7
7.7.2 Refresh Control Unit Registers .................................................................................7-7
7.7.2.1 Refresh Base Address Register ......................................................................7-8
7.7.2.2 Refresh Clock Interval Register .......................................................................7-8
7.7.2.3 Refresh Control Register .................................................................................7-9
7.7.3 Programming Example ...........................................................................................7-10
7.8 REFRESH OPERATION AND BUS HOLD................................... ...... ......................... 7-12
CHAPTER 8
INTERRUPT CONTROL UNIT
8.1 FUNCTIONAL OVERVIEW............................................................................................ 8-1
8.2 MASTER MODE............................................................................................................ 8-2
8.2.1 Generic Functions in Master Mode ...........................................................................8-2
8.2.1.1 Interrupt Masking ............................... .................................. ..... .......................8-3
8.2.1.2 Interrupt Priority ........................................................ ..... ..................................8-3
8.2.1.3 Interrupt Nesting ....................................................... ................................. ......8-4
8.3 FUNCTIONAL OPERATION IN MASTER MODE ......................................................... 8-5
8.3.1 Typical Interrupt Sequence .......................................................................................8-5
8.3.2 Priority Resolution .....................................................................................................8-5
8.3.2.1 Priority Resolution Example ............................................................................8-6
8.3.2.2 Interrupts That Share a Single Source ............................................................8-7
8.3.3 Cascading with External 8259 As ............................................................. .................8-7
8.3.3.1 Special Fully Nested Mode ..............................................................................8-8
8.3.4 Interrupt Acknowledg e Seque nc e ...................................... ..... ..................................8-9
8.3.5 Polling .......................................................................................................................8-9
8.3.6 Edge and Level Triggerin g ................................................. ..... ................................8-10
8.3.7 Additional Latency and Respon se Time ........................................................ ..... ....8-10
vi
CONTENTS
8.4 PROGRAMMING THE INTERRUPT CONTROL UNIT............................................... 8-11
8.4.1 Interrupt Control Registers ................................................. ................................. ....8-12
8.4.2 Interrupt Request Register ........................................... ...... ..... ................................8-16
8.4.3 Interrupt Mask Register ............................... .................................. ..... .....................8-16
8.4.4 Priority Mask Register .............................................................................................8-17
8.4.5 In-Service Register .................................................................................................8-18
8.4.6 Poll and Poll Status Registers .................................................................................8-19
8.4.7 End-of-Interrupt (EOI) Register ...............................................................................8-21
8.4.8 Interrupt Status Register ........................................ ...... ...... ................................. ....8-22
8.5 SLAVE MODE ............................................................................................................. 8-23
8.5.1 Slave Mode Programming ......................................................................................8-25
8.5.1.1 Interrupt Vector Register .............................. ...... .................................. .........8-26
8.5.1.2 End-Of-Interrupt Register ..............................................................................8-27
8.5.1.3 Other Registers .............................................................................................8-28
8.5.2 Interrupt Vectoring in Slave Mode .......................... ...... .................................. ..... ....8-29
8.5.3 Initializing the Interrupt Control Unit for Master Mode .............................................8-30
CHAPTER 9
TIMER/COUNTER UNIT
9.1 FUNCTIONAL OVERVIEW............................................................................................ 9-1
9.2 PROGRAMMING THE TIMER/COUNTER UNIT .......................................................... 9-6
9.2.1 Initialization Sequence ............................................................................................9-11
9.2.2 Clock Sources .........................................................................................................9-12
9.2.3 Counting Modes ......................................................................................................9-12
9.2.3.1 Retriggering ...................................................................................................9-13
9.2.4 Pulsed and Variable Duty Cycle Output ..................................................................9-14
9.2.5 Enabling/Disabling Counters ...................................................................................9-15
9.2.6 Timer Interrupts .......................................................................................................9-16
9.2.7 Programming Considerations ..................................................................................9-16
9.3 TIMING........................................................................................................................ 9-16
9.3.1 Input Setup and Hold Timings .................................................................................9-16
9.3.2 Synchronization and Maximum Frequency ............................. ...... ..........................9-17
9.3.2.1 Timer/Counter Unit Application Examples .....................................................9-17
9.3.3 Real-Time Clock .....................................................................................................9-17
9.3.4 Square-Wave Generator .............................................. ...... ................................. ....9-17
9.3.5 Digital One-Shot ......................................................................................................9-17
CHAPTER 10
DIRECT MEMORY ACCESS UNIT
10.1 FUNCTIONAL OVERVIEW.......................................................................................... 10-1
10.1.1 The DMA Transfer ..................................................................................................10-1
10.1.1.1 DMA Transfer Directions ...............................................................................10-3
10.1.1.2 Byte and Word Transfers ..............................................................................10-3
10.1.2 Source and Destination Pointers ............................................................................10-3
vii
CONTENTS
10.1.3 DMA Requests ........................................................................................................10-3
10.1.4 External Requests ...................................................................................................10-4
10.1.4.1 Source Synchronization ................................................................................10-5
10.1.4.2 Destination Synchronization ..........................................................................10-5
10.1.5 Internal Requests ....................................................................................................10-6
10.1.5.1 Timer 2-Initiated Transfers ............................................................................10-6
10.1.5.2 Unsynchronized Transfe rs .................................................. ..... .....................10-6
10.1.6 DMA Transfer Counts .............................................................................................10-7
10.1.7 Termination and Suspension of DMA Transfers .....................................................10-7
10.1.7.1 Termination at Terminal Count ......................................................................10-7
10.1.7.2 Software Termination ....................................................................................10-7
10.1.7.3 Suspension of DMA During NMI ...................................................................10-7
10.1.7.4 Software Suspension ....................................................................................10-7
10.1.8 DMA Unit Interrupts ................................................................................................10-8
10.1.9 DMA Cycles and the BIU ........................................................................................10-8
10.1.10 The Two-Channel DMA Unit ...................................................................................10-8
10.1.10.1 DMA Channel Arbitration ...............................................................................10-8
10.2 PROGRAMMING THE DMA UNIT ............................................................................ 10-10
10.2.1 DMA Channel Parameters ....................................................................................10-10
10.2.1.1 Programming the Source and Destination Pointers ....................................10-10
10.2.1.2 Selecting Byte or Word Size Transfers ........................................................10-14
10.2.1.3 Selecting the Source of DMA Requests ......................................................10-17
10.2.1.4 Arming the DMA Channel ............................................................................10-18
10.2.1.5 Selecting Channel Synchronization .............................................................10-18
10.2.1.6 Programming the Transfer Count Options ...................................................10-18
10.2.1.7 Generating Interrupts on Terminal Count ....................................... ...... ..... ..10-19
10.2.1.8 Setting the Relative Priority of a Channel ....................................................10-19
10.2.2 Suspension of DMA Transfers ..............................................................................10-20
10.2.3 Initializing the DMA Unit ................................................................................. .......10-20
10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT ......................................... 10-20
10.3.1 DRQ Pin Timing Requirements .............................................................................10-20
10.3.2 DMA Latency ........................................................................................................10-21
10.3.3 DMA Transfer Rates .............................................................................................10-21
10.3.4 Generating a DMA Acknowledge ..........................................................................10-22
10.4 DMA UNIT EXAMPLES............................................................................................. 10-22
CHAPTER 11
MATH COPROCESSING
11.1 OVERVIEW OF MATH COPROCESSING.................................................................. 11-1
11.2 AVAILABILITY OF MATH COPROCESSING.............................................................. 11-1
11.3 THE 80C187 MATH COPROCESSOR.............................. ...... ..... ............................... 11-2
11.3.1 80C187 Instruction Set ...........................................................................................11-2
11.3.1.1 Data Transfer Instructions .............................................................................11-3
11.3.1.2 Arithmetic Instructions ........................................ ...... ..... ................................11-3
11.3.1.3 Comparison Instructions ................................................................................11-5
viii
CONTENTS
11.3.1.4 Transcendental Instructions ..........................................................................11-5
11.3.1.5 Constant Instructions .....................................................................................11-6
11.3.1.6 Processor Control Instructions ......................................................................11-6
11.3.2 80C187 Data Types ................................................................................................11-7
11.4 MICROPROCESSOR AND COPROCESSOR OPERATION...................................... 11-7
11.4.1 Clocking the 80C187 .............................................................................................11-10
11.4.2 Processor Bus Cycles Accessing the 80C187 ......................................................11-10
11.4.3 System Design Tips ..............................................................................................11-11
11.4.4 Exception Trapping ..................................... .................................. ........................11-13
11.5 EXAMPLE MATH COPROCESSOR ROUTINES...................................................... 11-13
CHAPTER 12
ONCE MODE
12.1 ENTERING/LEAVING ONCE MODE........................................................................... 12-1
APPENDIX A
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
A.1 80C186 INSTRUCTION SET ADDITIONS................................................................... A-1
A.1.1 Data Transfer Instructions ......................................................................................A-1
A.1.2 String Instructions ...................................................................................................A-2
A.1.3 High-Level Instructions ......................................... ...... .................................. ..........A-2
A.2 80C186 INSTRUCTION SET ENHANCEMENTS......................................................... A-8
A.2.1 Data Transfer Instructions ......................................................................................A-8
A.2.2 Arithmetic Instructions .......................... ................................. .................................A-9
A.2.3 Bit Manipulation Instructions ...................................................................................A-9
A.2.3.1 Shift Instructions ................................................. ...... ................................. .....A-9
A.2.3.2 Rotate Instructions .......................................................................................A-10
APPENDIX B
INPUT SYNCHRONIZATION
B.1 WHY SYNCHRONIZERS ARE REQUIRED................................................................. B-1
B.2 ASYNCHRONOUS PINS..................................................................................... ..... .... B-2
APPENDIX C
INSTRUCTION SET DESCRIPTIONS
APPENDIX D
INSTRUCTION SET OPCODES AND CLOCK CYCLES
INDEX
ix
CONTENTS
FIGURES
Figure Page
2-1 Simplified Function al Bloc k Diag ram of the 80C186 Family CPU................................2-2
2-2 Physical Address Generation............................... ..... ...... .................................. ...........2-3
2-3 General Registers ........................................................................................................2-4
2-4 Segment Registers.......................................................................................................2-6
2-5 Processor Status Word ................................................................................................2-9
2-6 Segment Locations in Physical Memory.....................................................................2-10
2-7 Currently Addressable Segments...............................................................................2-11
2-8 Logical and Physical Address ....................................................................................2-12
2-9 Dynamic Code Relocation..........................................................................................2-14
2-10 Stack Operation..........................................................................................................2-16
2-11 Flag Storage Format ..................................................................................................2-19
2-12 Memory Address Computation...................................................................................2-29
2-13 Direct Addressing.......................................................................................................2-30
2-14 Register Indirect Addressing................................................................. ...... ...............2-31
2-15 Based Addressing......................................................................................................2-31
2-16 Accessing a Structure with Based Addressing ...........................................................2-32
2-17 Indexed Addressing....................................................................................................2-33
2-18 Accessing an Array with Indexed Addressing............................................................2-33
2-19 Based Index Addressing ............................................................................................2-34
2-20 Accessing a Stacked Array with Based Index Addressing.........................................2-35
2-21 String Operand...........................................................................................................2-36
2-22 I/O Port Addressing.................................................................... ...... ..........................2-36
2-23 80C186 Modular Core Family Supported Data Types................................................2-38
2-24 Interrupt Control Unit........................... ...... ..... .................................. ..........................2-39
2-25 Interrupt Vector Table........................................... ..... .................................. ...............2-40
2-26 Interrupt Sequence................................................................ ................................. ....2-42
2-27 Interrupt Response Factors........................................................ ................................2-46
2-28 Simultaneous NMI and Exception..............................................................................2-47
2-29 Simultaneous NMI and Single Step Interrupts............................................................2-48
2-30 Simultaneous NMI, Single Step and Maskable Interrupt............................................2-49
3-1 Physical Data Bus Models..................................................................... ...... ...... ...........3-2
3-2 16-Bit Data Bus Byte Transfers....................................................................................3-3
3-3 16-Bit Data Bus Even Word Transfers.........................................................................3-4
3-4 16-Bit Data Bus Odd Word Transfers...........................................................................3-5
3-5 8-Bit Data Bus Word Transfers.....................................................................................3-6
3-6 Typical Bus Cycle.........................................................................................................3-8
3-7 T-State Relation to CLKOUT........................................................................................3-8
3-8 BIU State Diagram ........................ ...... .................................. ..... ..................................3-9
3-9 T-State and Bus Phases............................................................................................3-10
3-10 Address/Status Phase Signal Relationships..............................................................3-11
3-11 Demultiplexing Address Information...........................................................................3-12
3-12 Data Phase Signal Relationships...............................................................................3-14
3-13 Typical Bus Cycle with Wait States............................................................................3-15
3-14 ARDY and SRDY Pin Block Diagram.........................................................................3-15
x
CONTENTS
FIGURES
Figure Page
3-15 Generating a Normally Not-Ready Bus Signal...........................................................3-16
3-16 Generating a Normally Ready Bus Signal..................................................................3-17
3-17 Normally Not-Ready System Timing..........................................................................3-18
3-18 Normally Ready System Timings...............................................................................3-19
3-19 Typical Read Bus Cycle.............................................................................................3-21
3-20 Read-Only Device Interface ....................................................... ...... ..... ...... ...............3-22
3-21 Typical Write Bus Cycle..............................................................................................3-23
3-22 16-Bit Bus Read/Write Device Interface.....................................................................3-24
3-23 Interrupt Acknowledge Bus Cycle.............. ..... .................................. ..........................3-26
3-24 Typical 82C59A Interface...........................................................................................3-27
3-25 HALT Bus Cycle.........................................................................................................3-29
3-26 Returning to HALT After a HOLD/HLDA Bus Exchange............................................3-30
3-27 Returning to HALT After a Refresh Bus Cycle...........................................................3-31
3-28 Returning to HALT After a DMA Bus Cycle........................................... ...... ...............3-32
3-29 Exiting HALT ..............................................................................................................3-33
3-30 DEN and DT/R Timing Relationships.........................................................................3-34
3-31 Buffered AD Bus System............................................................ ................................3-35
3-32 Qualifying DEN with Chip-Selects..............................................................................3-36
3-33 Queue Status Timing................................................. ...... .................................. .........3-39
3-34 Timing Sequence Entering HOLD..............................................................................3-40
3-35 Refresh Request During HOLD..................................................................................3-42
3-36 Latching HLDA ...........................................................................................................3-43
3-37 Exiting HOLD..............................................................................................................3-44
4-1 PCB Relocation Register..............................................................................................4-2
5-1 Clock Generator...........................................................................................................5-1
5-2 Ideal Operation of Pierce Oscillator..............................................................................5-2
5-3 Crystal Connections to Microprocessor........................................................................5-3
5-4 Equations for Crystal Calculations................................................................................5-4
5-5 Simple RC Circuit for Powerup Reset............................................................... ...........5-7
5-6 Cold Reset Waveform..................................................................................................5-8
5-7 Warm Reset Waveform................................................................................................5-9
5-8 Clock Synchronization at Reset..................................................................................5-10
5-9 Power-Save Register .................................................................................. ...............5-12
5-10 Power-Save Clock Transition................................................ ..... ................................5-13
6-1 Common Chip-Select Generation Methods..................................................................6-2
6-2 Chip-Select Block Diagram...........................................................................................6-3
6-3 Chip-Select Relative Timings.......................................................................................6-4
6-4 UCS
6-5 UMCS Register Definition.............................................................................................6-7
6-6 LMCS Register Definition.............................................................................................6-8
6-7 MMCS Register Definition........................................................................... ...... ..... ......6-9
6-8 PACS Register Definition..................................... ..... ...... ...... ................................. ....6-10
6-9 MPCS Register Definition...........................................................................................6-11
6-10 MCS3:0
Reset Configuration.............................................................................................6-5
Active Ranges..............................................................................................6-14
xi
CONTENTS
FIGURES
Figure Page
6-11 Wait State and Ready Control Functions...................................................................6-16
6-12 Using Chip-Selects During HOLD..............................................................................6-18
6-13 Typical System...........................................................................................................6-19
7-1 Refresh Control Unit Block Diagram.............................................................................7-1
7-2 Refresh Control Unit Operation Flow Chart..................................................................7-3
7-3 Refresh Address Formation..........................................................................................7-4
7-4 Suggested DRAM Control Signal Timing Relationships...............................................7-6
7-5 Formula for Calculating Refresh Interval for RFTIME Register....................................7-7
7-6 Refresh Base Address Register...................................................................................7-8
7-7 Refresh Clock Interval Register....................................................................................7-9
7-8 Refresh Control Register............................................................................................7-10
7-9 Regaining Bus Control to Run a DRAM Refresh Bus Cycle.......................................7-13
8-1 Interrupt Control Unit in Master Mode..........................................................................8-2
8-2 Using External 8259A Modules in Cascade Mode.......................................................8-8
8-3 Interrupt Control Unit Latency and Response Time...................................................8-11
8-4 Interrupt Control Register for Internal Sources...........................................................8-13
8-5 Interrupt Control Register for Noncas cad ab le External Pins.................................. ....8-14
8-6 Interrupt Control Register for Cascadabl e Interrupt Pins....................... ...... ...... .........8-15
8-7 Interrupt Request Register............................. .................................. ..........................8-16
8-8 Interrupt Mask Register........................................ ..... .................................. ...............8-17
8-9 Priority Mask Register ................................................................................................8-18
8-10 In-Service Register.....................................................................................................8-19
8-11 Poll Register.................................. .................................. .................................. .........8-20
8-12 Poll Status Register........................................ .................................. ..........................8-21
8-13 End-of-Interrupt Register............................................................................................8-22
8-14 Interrupt Status Register ........................... ................................. ...... ..........................8-23
8-15 Interrupt Control Unit in Slave Mode..........................................................................8-24
8-16 Interrupt Sources in Slave Mode...................................................... ..... .....................8-25
8-17 Interrupt Vector Register (Slave Mode Only)........ ..... ...... .................................. .........8-27
8-18 End-of-Interrupt Register in Slave Mode....................................................................8-28
8-19 Request, Mask, and In-Service Registers..................................................................8-28
8-20 Interrupt Vectoring in Slave Mode.................................................... ..... .....................8-29
8-21 Interrupt Response Time in Slave Mode..................................................... ...... .........8-30
9-1 Timer/Counter Unit Block Diagram...............................................................................9-2
9-2 Counter Element Multip lex in g and Timer I npu t Synchronization............................ ......9-3
9-3 Timers 0 and 1 Flow Chart...........................................................................................9-4
9-4 Timer/Counter Unit Output Modes................................................................................9-6
9-5 Timer 0 and Timer 1 Control Registers........................................................................9-7
9-6 Timer 2 Control Register..............................................................................................9-9
9-7 Timer Count Registers................................................................................................9-10
9-8 Timer Maxcount Compare Registers..........................................................................9-11
9-9 TxOUT Signal Timing.................................................................................................9-15
10-1 Typical DMA Transfer.................................................................................................10-2
10-2 DMA Request Minimum Response Time...................................................................10-4
xii
CONTENTS
FIGURES
Figure Page
10-3 Source-Synchronized Transfers............................................................................. ....10-5
10-4 Destination-Synchronized Transfers..........................................................................10-6
10-5 Two-Channel DMA Module ........................................................................................10-9
10-6 Examples of DMA Priority.........................................................................................10-10
10-7 DMA Source Pointer (High-Order Bits).....................................................................10-11
10-8 DMA Source Pointer (Low-Order Bits).....................................................................10-12
10-9 DMA Destination Pointer (High-Order Bits)..............................................................10-13
10-10 DMA Destination Pointer (Low-Order Bits)...............................................................10-14
10-11 DMA Control Register...............................................................................................10-15
10-12 Transfer Count Register............................................................. ..............................10-19
11-1 80C187-Supported Data Types....................................... ...... ................................. ....11-8
11-2 80C186 Modular Core Family/80C187 System Configuration....................................11-9
11-3 80C187 Configuration with a Partially Buffered Bus.................................................11-12
11-4 80C187 Exception Trapping via Processor Interrupt Pin..........................................11-14
12-1 Entering/Leaving ONCE Mode...................................................................................12-2
A-1 Formal Definition of ENTER........................................................................................A-3
A-2 Variable Access in Nested Procedures.......................................................................A-4
A-3 Stack Frame for Main at Level 1..................................................................................A-4
A-4 Stack Frame for Procedure A at Level 2.....................................................................A-5
A-5 Stack Frame for Procedure B at Level 3 Called from A...............................................A-6
A-6 Stack Frame for Procedure C at Level 3 Called from B..............................................A-7
B-1 Input Synchronization Circuit.......................................................................................B-1
xiii
CONTENTS
TABLES
Table Page
1-1 Comparison of 80C186 Modular Core Family Products...............................................1-2
1-2 Related Documents and Software................................................................................1-3
2-1 Implicit Use of General Registers.................................................................................2-5
2-2 Logical Address Sources............................................................................................2-13
2-3 Data Transfer Instructions..........................................................................................2-18
2-4 Arithmetic Instructions................................................................ ................................2-20
2-5 Arithmetic Interpretation of 8-Bit Numb ers.................................................. ...... ..... ....2-21
2-6 Bit Manipulation Instructions ......................................................................................2-21
2-7 String Instructions.......................................................................................................2-22
2-8 String Instruction Register and Flag Use.......................................... ..... .....................2-23
2-9 Program Transfer Instructions....................................................................................2-25
2-10 Interpretation of Conditional Transfers.......................................................................2-26
2-11 Processor Control Instructions...................................................................................2-27
2-12 Supported Data Types ...............................................................................................2-37
3-1 Bus Cycle Types . .......................................................................................................3-12
3-2 Read Bus Cycle Types.................................................... .................................. .........3-20
3-3 Read Cycle Critical Timing Parameters......................................................................3-20
3-4 Write Bus Cycle Types...............................................................................................3-23
3-5 Write Cycle Critical Timing Paramete rs..................... .................................. ...............3-25
3-6 HALT Bus Cycle Pin States........................................................................................3-29
3-7 Queue Status Signal Decoding..................................................................................3-38
3-8 Signal Condition Entering HOLD................................................................................3-40
4-1 Peripheral Control Block...............................................................................................4-3
5-1 Suggested Values for Inductor L1 in Third Overtone Oscillator Circuit........................5-4
6-1 Chip-Select Unit Registers...........................................................................................6-6
6-2 UCS
6-3 LCS
6-4 MCS
6-5 MCS
6-6 PCS
7-1 Identification of Refresh Bus Cycles.............................................................................7-5
8-1 Default Interrupt Priorities.............................................................................................8-3
8-2 Fixed Interrupt Types ...................................................................................................8-9
8-3 Interrupt Control Unit Registers in Master Mode........................................................8-11
8-4 Interrupt Control Unit Register Comparison...............................................................8-26
8-5 Slave Mode Fixed Interrupt Type Bits........................................................................8-26
9-1 Timer 0 and 1 Clock Sources.....................................................................................9-12
9-2 Timer Retriggering......................................................................................................9-13
11-1 80C187 Data Transfer Instructions.............................................................................11-3
11-2 80C187 Arithmetic Instructions...................................................................................11-4
11-3 80C187 Comparison Instructions...............................................................................11-5
11-4 80C187 Transcendental Instructions..........................................................................11-5
11-5 80C187 Constant Instructions....................................................................................11-6
11-6 80C187 Processor Control Instructions......................................................................11-6
11-7 80C187 I/O Port Assignments..................................................................................11-10
Block Size and Starting Address........................................................................6-12
Active Range......................................................................................................6-13
Active Range.....................................................................................................6-13
Block Size and Start Address Restrictions........................................................6-14
Active Range......................................................................................................6-15
xiv
CONTENTS
TABLES
Table Page
C-1 Instruction Format Variables........................................................................................C-1
C-2 Instruction Operands...................................................................................................C-2
C-3 Flag Bit Functions........................................................................................................C-3
C-4 Instruction Set .............................................................................................................C-4
D-1 Operand Variables ......................................................................................................D-1
D-2 Instruction Set Summary.............................................................................................D-2
D-3 Machine Instruction Decoding Guide...........................................................................D-9
D-4 Mnemonic Encoding Matrix (Left Half) ......................................................................D-20
D-5 Abbreviations for Mnemonic Encoding Matrix...........................................................D-22
xv
CONTENTS
EXAMPLES
Example Page
5-1 Initializing the Power Manag ement Unit for Power-Save Mode............................. ....5-14
6-1 Initializing the Chip-Select Unit...................................................................................6-20
7-1 Initializing the Refresh Control Unit............................................................................7-11
8-1 Initializing the Interrupt Control Unit for Master Mode................................................8-31
9-1 Configuring a Real-Time Clock...................................................................................9-18
9-2 Configuring a Square-Wav e Genera tor......................................................................9-21
9-3 Configuring a Digital One-Shot................................................... ................................9-22
10-1 Initializing the DMA Unit.................................................. .................................. .......10-23
10-2 Timed DMA Transfers ..............................................................................................10-26
11-1 Initialization Sequence for 80C187 Math Coprocessor............................................11-15
11-2 Floating Point Math Routine Using FSINCOS..........................................................11-16
xvi
Introduction
1
CHAPTER 1
INTRODUCTION
The 8086 microprocessor was first introduced in 1978 and g ained rapid support as the microco mputer engine of choice. There are literally millions of 8086/8088-based systems in the world today. The amount of software written for the 8086/8088 is rivaled by no other architecture.
By the early 1980’s, however, it was clear that a replacement for the 8086/8088 was necessary.
An 8086/8088 system required dozens of suppo rt chips to implement even a moder ately com plex
design. Intel recognized the need to integrate commonly used system peripherals onto the same
silicon die as the CPU. In 1982 Intel addressed this need by introducing the 80186/80188 family
of embedded microprocessors. The original 80186/80188 integrated an enhanced 8086/8088
CPU with six commonly used system peripherals. A parallel effort within Intel also gave rise to
the 80286 microprocessor in 1982 . The 802 86 began the trend toward the ver y hig h perfor mance
Intel architecture that today includes the Intel386, I ntel486 and Pentium microprocessors.
As technology advanced and turned toward small geometry CMOS processes, it became clear
that a new 80186 was needed . In 1987 Intel announced the second generation of the 80186 family:
the 80C186/C188. The 80C186 family is pin co mpatible with the 8 0186 family , while adding an
enhanced feature set. The high-performance CHMOS III process allowed the 80C186 to run at
twice the clock rate of the NMOS 80186, while consuming less than one-fourth the power.
The 80186 family took another major step in 1990 with the introduction of the 80C186EB family.
The 80C186EB heralded man y changes for the 8018 6 family. First, th e enhanced 8086/808 8 CPU
was redesigned as a static, stand-alone module known as the 80C186 Modular Core. Second, the
80186 family peripherals were also redesigned as static modules with standard interfaces. The
goal behind this redesign effort was to give Intel the capability to proliferate the 80186 family
rapidly, in order to provide solutions for an even wider range of customer applications.
The 80C186EB/C188EB was the first product to use the new modular capability. The
80C186EB/C188EB includes a different peripheral set than the original 80186 family. Power
consumption was dramatically reduced as a direct result of the static design, power manag ement
features and advanced CHMOS IV process. The 80C186EB/C188EB has found acceptance in a
wide array of portable equipment ranging from cellular phones to personal organizers.
In 1991 the 80C186 Modular Core family was again extended with the introduction of three new
products: the 80C186XL, the 80C186E A and the 80C186EC. T he 80C186XL/C188XL is a higher performance, lower power replacement for the 80C186/C188. The 80C186EA/C188EA combines the feature set of the 80C186 with new power management features for power-critical
applications. The 80C186EC/C188EC offers the highest level of integration of any of the 80C186
Modular Core family products, with 14 on-chip peripherals (see Table 1-1).
1-1
INTRODUCTION
The 80C186 Modular Core family is the direct result of ten years of Intel development. It offers
the designer the peace of mind of a well-established architecture with the benefits of state-of- theart technology.
Table 1-1. Comparison of 80C186 Modular Core Family Products
Feature 80C186XL 80C186EA 80C186EB 80C186EC
Enhanced 8086 Instruction Set
Low-Power Static Modular CPU
Power-Save (Clock Divide) Mode
Powerdown and Idle Modes
80C187 Interface
ONCE Mode
Interrupt Control Unit 8259
Timer/Counter Unit
Chip-Select Unit Enhanced Enhanced
DMA Unit
Serial Communications Unit
Refresh Control Unit Enhanced Enhanced
Watchdog Timer Unit
I/O Ports 16 Total 22 Total
2 Channel 2 Channel 4 Channel
Compatible
1.1 HOW TO USE THIS MANUAL
This manual uses phrases such as 80C186 Modular Core Family or 80C188 Modular Core, as
well as references to specific products such as 80C188EA. Each phrase refers to a specific set of
80C186 family products. The phrases and the products they refer to are as follows:
80C186 Modular Core Family: This phrase refers to any device that uses the modular
80C186/C188 CPU core architecture. At this time these include the 80C186EA/C188EA,
80C186EB/C188EB, 80C186EC/C188EC and 80C186XL/C188XL.
80C186 Modular Core: Without the word family, this phrase refers only to the 16-bit bus mem-
bers of the 80C186 Modular Core Family.
80C188 Modular Core: This phrase refers to the 8-bit bus products.
80C188EC: A specific product reference refers only to the named device. For example, On the
80C188EC… refers strictly to the 80C188EC and not to any other device.
1-2
INTRODUCTION
Each chapter covers a specific section of the device, beginning with the CPU core. Each peripheral chapter includes programmin g ex amples intend ed to aid in you r under standing of d evice operation. Please read the comments carefully, as not all of the examples include all the code
necessary for a specific application.
This user’s guide is a supplement to the device data sheet. Specific timing values are not discussed in this guide. When designing a system, always consult the most recent version of the device data sheet for up-to-date specifications.
1.2 RELATED DOCUMENTS
The following table lists documents and software that are useful in designing systems that incorporate the 80C186 Modular Core Family. These documents are available throug h Intel Literature.
To order a document, call the number listed for your area in “Product Literature” on page 1-7.
NOTE
If you will be transferring a design from the 80186/80188 or 80C186/80C188
to the 80C186XL/80C188XL, refer to FaxBack Document No. 2132.
Table 1-2. Related Documents and Software
Document/Software Title
Embedded Microprocessors (includes 186 family data sheets) 272396
186 Embedded Microprocessor Line Card 272079
80186/80188 High-Integration 16-Bit Microprocessor Data Sheet 272430
80C186XL/C188XL-20, -12 16-Bit High-Integration Embedded Microprocessor
Data Sheet
80C186EA/80C188EA-20, -12 and 80L186EA/80L188EA-13, -8 (low power
versions) 16-Bit High-Integration Embedded Microprocess or Data Sheet
80C186EB/80C188EB-20, -13 and 80L186EB/80L188EB-13, -8 (low power
versions) 16-Bit High-Integration Embedded Microprocess or Data Sheet
80C186EC/80C188EC-20, -13 and 80L186EC/80L188EC-13, -8 (low power
versions) 16-Bit High-Integration Embedded Microprocess or Data Sheet
80C187 80-Bit Math Coprocessor Data Sheet 270640
Low Voltage Embedded Design 272324
80C186/C188, 80C186XL/C188XL Microprocessor User’s Manual 272164
80C186EA/80C188EA Microprocessor User’s Manual 270950
80C186EB/80C188EB Microprocessor User’s Manual 270830
80C186EC/80C188EC Microprocessor User’s Manual 272047
8086/8088/8087/80186/80188 Programmer’s Pocket Reference Guide 231017
8086/8088 User’s Manual Programmer’s and Hardware Reference Manual 240487
Document
Order No.
272431
272432
272433
272434
1-3
INTRODUCTION
Table 1-2. Related Documents and Software (Continued)
Document/Software Title
Ap
BUILDER Software 272216
80C186EA Hypertext Manual 272275
80C186EB Hypertext Manual 272296
80C186EC Hypertext Manual 272298
80C186XL Hypertext Manual 272630
ZCON - Z80 Code Converter Available on BBS
Document
Order No.
1.3 ELECTRONIC SUPPORT SYSTEMS
Intel’s FaxBack* service and application BBS provide up-to-date technical information. Intel
also maintains several forums on CompuServe and offers a variety of information on the World
Wide Web. These systems are available 24 hours a day, 7 days a week, p roviding technical information whenever you need it.
1.3.1 FaxBack Service
FaxBack is an on-demand publishing system that sends documents to your fax machine. You can
get product announcements, change notifications, product literature, device characteristics, design recommendations, and quality and reliability information from FaxBack 24 hours a day, 7
days a week.
1-800-628-2283 U.S. and Canada
916-356-3105 U.S., Canada, Japan, APac
44(0)1793-496646 Europe
Think of the FaxBack service as a library of technical documents that you can access with your
phone. Just dial the telephone number and respo nd to the system prompts. After you select a document, the system sends a copy to your fax machine.
Each document has an order number and is listed in a subject catalog. The first time you use FaxBack, you should order the appropriate subject catalogs to get a complete list of document order
numbers. Catalogs are updated twice monthly. In addition, d aily update catalogs list the title, status, and order number of each document that has been added, revised, or deleted during the past
eight weeks. To recieve the update for a subject catalog, enter the subject catalog number followed by a zero. For example, for the complete microcontroller and flash catalog, request document number 2; for the daily update to the microcontroller and flash catalog, request document
number 20.
1-4
INTRODUCTION
The following catalogs and information are available at the time of publication:
1. Solutions OEM subscription form
2. Microcontroller and flash catalog
3. Development tools catalog
4. Systems catalog
5. Multimedia catalog
6. Multib us and iRM X
®
software catalog and BBS file listings
7. Microprocessor, PCI, and peripheral catalog
8. Quality and reliability and change notificatio n catalog
9. iAL (Intel Architecture Labs) technology catalog
1.3.2 Bulletin Board System (BBS)
The bulletin board system (BBS) lets you download files to your co mputer. The ap plication BBS
has the latest ApBUILDER software, hypertext manuals and datasheets, software drivers, firmware upgrades, application notes and utilities, and quality and reliability data.
916-356-3600 U.S., Canada, Japan, APac (up to 19.2 Kbaud)
916-356-7209 U.S., Ca nada, Japan, APac (24 00 baud onl y)
44(0)1793-496340 Europe
The toll-free BBS (available in the U.S. and Canada) offers lists of documents available from
FaxBack, a master list of files available from the application BBS, and a BBS user’s guide. The
BBS file listing is also available from FaxBack (catalog number 6; see page 1-4 for phone numbers and a description of the FaxBack service).
1-800-897-2536 U.S. and Canada only
Any customer with a modem and computer can access the BBS. The system provides automatic
configuration support for 1200 - through 19200-baud modem s. Typical modem settings are 14400
baud, no parity, 8 data bits, and 1 stop bit (14400, N, 8, 1).
To access the BBS, just dial the telephone number and respond to the system prompts. During
your first session, the system asks you to register with the system operator by entering your name
and location. The system operator will set up your access account within 24 hours. At that time,
you can access the files on the BBS.
NOTE
If you encounter any difficulty accessing the high-speed modem, try the
dedicated 2400-baud modem. Use these modem settings: 2400, N, 8, 1.
1-5
INTRODUCTION
1.3.2.1 How to Find ApBUILDER Software and Hypertext Documents on the BBS
The latest ApBUILDER files and hypertext manuals and data sheets are available first from the
BBS. To access the files, complete these steps:
1. Type F from the BBS Main menu. The BBS displays the Intel Apps Files menu.
2. Type L and press <Enter>. The BBS displays the list of areas and prompts for the area
number.
3. Type 25 and press <Enter> to select ApBUILDER/Hypertext. The BBS displays several
options: one for ApBUILDER software and the others for hypertext documents for
specific product families.
4. Type 1 and press <Enter> to list the latest ApBUILDER files, or type the number of the
appropriate product family sublevel and press <Enter> for a list of available hypertext
manuals and datasheets.
5. Type the file numbers to select the files you wish to download (for ex ample, 1,6 for files 1
and 6 or 3-7 for files 3, 4, 5, 6, and 7) and press <Enter>. The BBS displays the approx-
imate time required to download the selected files and gives you the option to download
them.
1.3.3 CompuServe Forums
The CompuServe forums provide a means for you to gather information, share discoveries, and
debate issues. Type “go intel” for access. For information about CompuServ e access an d service
fees, call CompuServe at 1-800-848-8199 (U.S.) or 614-529-1340 (outside the U.S.).
1.3.4 World Wide Web
Intel offers a variety of information through the World Wide Web (http://www.intel.co m/). Select
“Embedded Design Products” from the Intel home page.
1.4 TECHNICAL SUPPORT
In the U.S. and Canada, technical support representatives are available to answer your questions
between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice
telephone number and indicate whether you prefer a response by phone or by fax). Outside the
U.S. and Canada, please contact your local distributor.
1-800-628-8686 U.S. and Canada
916-356-7599 U.S. and Canada
916-356-6100 (fax) U.S. and Canada
1-6
INTRODUCTION
1.5 PRODUCT LITERATURE
You can order product literature from the following Intel literature centers.
1-800-468-8118, ext. 283 U.S. and Canada
708-296-9333 U.S. (from overseas)
44(0)1793-431155 Europe (U.K.)
44(0)1793-421333 Germany
44(0)1793-421777 France
81(0)120-47-88-32 Japan (fax only)
1.6 TRAINING CLASSES
In the U.S. and Canada, you can register for training classes through the Intel customer training
center. Classes are held in the U.S.
1-800-234-8806 U.S. and Canada
1-7
Overview of the
80C186 Family
Architecture
2
CHAPTER 2
OVERVIEW OF THE 80C186 FAMILY
ARCHITECTURE
The 80C186 Modular Microprocessor Core shares a common base architecture with the 8086,
8088, 80186, 80188, 80286, Intel386™ and Intel486™ processors. The 80C186 Modular Core
maintains full object-code compatibility with the 8086/8088 family of 16-bit microprocessors,
while adding hardware and software perfo rmance enhancements. Most instructions require fewer
clocks to execute on the 80C186 Modular Core because of hardware enhancements in the Bus
Interface Unit and the Execution Unit. Several addition al instructions simp lify prog ramming an d
reduce code size (see Appendix A, “80C186 Instruction Set Additions and Extensions”).
2.1 ARCHITECTURAL OVERVIEW
The 80C186 Modular Microprocessor Core incorporates two separate processing units: an Execution Unit (EU) and a Bus Interface Unit (BIU). The Execution Unit is functionally identical
among all family members. The Bus Interface Unit is configured for a 16-bit external data bus
for the 80C186 core and an 8-bit external data bus for the 80C188 core. The two units interface
via an instruction prefetch queue.
The Execution Unit executes instructions; the Bus Interface Unit fetches instructions, reads operands and writes results. Whenever the Ex ecution Unit requ ires another opcod e byte, it takes the
byte out of the prefetch queue. The two units can operate independently of one another and are
able, under most circumstances, to overlap instruction fetches and execution.
The 80C186 Modular Core family has a 16-bit Arithmetic Logic Unit (ALU). The Arithmetic
Logic Unit performs 8-bit or 16-bit arithmetic and logical operations. It provides for data movement between registers, memory and I/O space.
The 80C186 Modular Core family CPU allows for high-speed data transfer from one area of
memory to another using string move instructions and between an I/O port and memory using
block I/O instructions. The CPU also provides many conditional branch and control instr uctions.
The 80C186 Modular Core architecture features 14 basic registers grouped as general registers,
segment registers, pointer registers and status and control registers. The four 16-bit general-purpose registers (AX, BX, CX and DX) can be used as operands for most arithmetic operations as
either 8- or 16-bit units. The four 16-bit p ointer registers (SI, DI, BP and SP) can b e used in arithmetic operations and in accessing memory-based variables. Four 16-bit segment registers (CS,
DS, SS and ES) allow simple memory partitioning to aid modular programming. The status and
control registers consist of an Instruction Pointer (IP) and the Pr ocessor Status Word (PSW) register, which contains flag bits. Figure 2-1 is a simplified CPU block diagram.
2-1
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Address Bus (20 Bits)
General
Registers
AH
BH
CH
DH
Temporary
Registers
ALU
Flags
SP
BP
SI
DI
AL
BL
CL
DL
ALU Data Bus
(16 Bits)
EU
Control
System
Σ
CS
DS
SS
ES
IP
Internal
Communications
Registers
Control
Instruction Queue
123456
Q Bus
(8 Bits)
Bus
Logic
Data
Bus
(16 Bits)
External
Bus
Execution Unit
(EU)
Figure 2-1. Simplified Functional Block Diagram of the 80C186 Family CPU
Bus Interface Unit
(BIU)
A1012-0A
2.1.1 Execution Unit
The Execution Unit executes all instructions, provides data and addresses to the Bus Interface
Unit and manipulates the general registers and the Processor Status Word. The 16-bit ALU within
the Execution Unit maintains the CPU status and control flags and manipulates the general registers and instruction operands. All registers and data paths in the Execution Unit are 16 bits wide
for fast internal transfers.
2-2
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
The Execution Unit does not connect directly to the system bus. It obtains instructions from a
queue maintained by the Bus Interface Unit. When an instruction req uires access to memory or a
peripheral device, the Execution Unit requests the Bus Interf ace Unit to read and wr ite da ta. Addresses manipulated by the Execution Unit are 16 bits wide. The Bus Interface Unit, however,
performs an address calculation that allows the Execution Unit to access the full megabyte of
memory space.
To execute an instruction, the Execution Unit must first fetch the object code byte from the instruction queue and then execute the instruction. If the queue is empty when the Execution Unit
is ready to fetch an instruction byte, the Execution Unit waits for the Bus Interface Unit to fetch
the instruction byte.
2.1.2 Bus Interface Unit
The 80C186 Modular Co re and 8 0C188 Modular Core Bus In terface Un its are fun ctionally id entical. They are implemented differently to match th e stru cture and perf ormance char acteristics of
their respective system buses. The Bus Interface Unit executes all external bus cycles. This unit
consists of the segment registers, the Instruction Pointer, the instruction code queue and several
miscellaneous registers. The Bus Interface Unit transfers data to and fro m the Ex ecution Un it on
the ALU data bus.
The Bus Interface Unit generates a 20- bit ph ysical address in a dedicated adder. The adder shif ts
a 16-bit segment value left 4 bits and then adds a 16-bit offset. This offset is derived from combinations of the pointer registers, the Instruction Pointer and immediate values (see Figure 2-2).
Any carry from this addition is ignored.
Shift left 4 bits
21
15
21 340
19
+
00
15
0
22
0
00
15
=11923620Physical Address
To Memory
Figure 2-2. Physical Address Generation
43
Segment Base
0
Offset
22
0
Logical
Address
A1500-0A
2-3
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
During periods when the Execution Unit is busy executing instructions, the Bus Interface Unit
sequentially prefetches instructions from memory. As long as the prefetch queue is partially full,
the Execution Unit fetches instructions.
2.1.3 General Registers
The 80C186 Modular Core family CPU has eight 16-bit general registers (see Figure 2-3). The
general registers are subdivided into two sets of four registers. These sets are the data registers
(also called the H & L group for high and low) and the po inter and index registers (also called the
P & I group).
HL
15
AX
AH AL
087
Accumulator
Data
Group
Pointer
and
Index
Group
BX
BH
CX
CH
DX
DH
SP
BP
SI
DI
Figure 2-3. General Registers
BL
CL
DL
Base
Count
Data
Stack Pointer
Base Pointer
Source Index
Destination Index
A1033-0A
2-4
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
The data registers can be addressed by their upper or lower halves. Each data regi ster can be used
interchangeably as a 16-bit register or two 8-bit reg isters. The pointer registers are always accessed as 16-bit values. The CPU can use data registers without constraint in most arithmetic and logic operations. Arithmetic and logic operations can also use the pointer and ind ex reg isters. Some
instructions use certain registers implicitly (see Table 2-1), allowing compact encoding.
Table 2-1. Implicit Use of General Registers
Register Operations
AX Word Multiply, Word Divide, Wor d I/O
AL Byte Multiply, Byte Divide, Byte I/O, Translate, Decimal Arithm et ic
AH Byte Multiply, Byte Divide
BX Translate
CX String Operations, Loops
CL Variable Shift and Rotate
DX Word Multiply, Word Divide, Indirect I/O
SP Stack Operations
SI String Operations
DI String Operations
The contents of the general-purpose registers are undefined following a processor reset.
2.1.4 Segment Registers
The 80C186 Modular Core family memory space is 1 Mby te in size an d div ided into logical segments of up to 64 Kbytes each. The CPU has dir ect access to four segments at a time. Th e segment
registers contain the base addresses (starting locations) of these memory segments (see Figure
2-4). The CS register points to the current code segment, which contains instructions to be
fetched. The SS register points to the curren t stack segment, which is used for all stack operations.
The DS register points to the current data segment, which generally contains program variables.
The ES register points to the current extra segment, which is typically used for d ata storag e. The
CS register initializes to 0FFFFH, and the SS, DS and ES registers initialize to 0000H. Programs
can access and manipulate the segment registers with several instructions.
2-5
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
15 0
CS Code Segment
DS Data Segment
SS Stack Segment
ES Extra Segment
Figure 2-4. Segment Registers
2.1.5 Instruction Pointer
The Bus Interface Unit updates the 16-bit Instruction Pointer (IP) register so it contains the offset
of the next instruction to be fetched. Programs do not have direct access to the Instruction Pointer,
but it can change, be saved or be restored as a result of program execution. For example, if the
Instruction Pointer is saved on the stack, it is first automatically adjusted to point to the next instruction to be executed.
Reset initializes the Instruction Pointer to 0000H. The CS and IP values comprise a starting execution address of 0FFFF0H (see “Logical Addresses” on page 2-10 for a description of address
formation).
2-6
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1.6 Flags
The 80C186 Modular Core family has six status flags (see Figure 2-5) that the Execution Unit
posts as the result of arithmetic or logical operations. Program branch instructions allow a program to alter its execution depending on conditions flagged by a prior operation. Different instructions affect the status flags differently, generally reflecting the following states:
• If the Auxiliary Flag (AF) is set, there has been a carry out from the low nibble in to the h igh
nibble or a borrow from the high nibble into the low nibble of an 8-bit quantity (low-order
byte of a 16-bit quantity). This flag is used by decimal arithmetic instructions.
• If the Carry Flag (CF) is set, there has been a carry out of or a borrow into the high-order bit
of the instruction result (8- or 16-bit). This flag is used by instructions that add or subtract
multibyte numbers. Rotate instructions can also isolate a bit in memory or a register by
placing it in the Carry Flag.
• If the Overflow Flag (OF) is set, an arithmetic overflow has occurred. A significant digit
has been lost because the size of the result exceeded the capacity of its destination location.
An Interrupt On Overflow instruction is available that will generate an interrupt in this
situation.
• If the Sign Flag (SF) is set, the high-order bit of the result is a 1. Since negative binary
numbers are represented in standard two’s complement notation, SF indicates the sign of
the result (0 = positive, 1 = negative).
• If the Parity Flag (PF) is set, the result has even parity, an even number of 1 bits. This flag
can be used to check for data transmission errors.
• If the Zero Flag (ZF) is set, the result of the operation is zero.
Additional control flags (see Figure 2-5) can be set or cleared b y programs to alter p rocessor operations:
• Setting the Direction Flag (DF) causes string operations to auto-decrement. Strings are
processed from high address to low address (or “right to left”). Clearing DF causes string
operations to auto-increment. Strings are processed from low address to high address (or
“left to right”).
• Setting the Interrupt Enable Flag (IF) allows the CPU to recognize maskable external or
internal interrupt requests. Clearing IF disables these interrupts. The Interrupt Enable Flag
has no effect on software interrupts or non-maskable interrupts.
• Setting the Trap Flag (TF) bit puts the processor into single-step mode for debugging. In
this mode, the CPU automatically generates an interrupt after each instruction. This allows
a program to be inspected instruction by instruction during execution.
The status and control flags are contained in a 16-bit Processor Status Word (see Figure 2-5). Reset initializes the Processor Status Word to 0F000H.
2-7
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1.7 Memory Segmentation
Programs for the 80C186 Modular Core family view the 1 Mbyte memory space as a group of
user-defined segments. A segment is a logical unit of memory that can be up to 64 Kbytes long.
Each segment is compo sed of contiguous memory locations. Segments are independent and separately addressable. Software assigns every segment a base address (starting location) in memory
space. All segments begin on 16-byte memor y boundaries. There ar e no other restrictions on segment locations. Segments can be adjacent, disjoint, partially overlapped or fully overlapped (see
Figure 2-6). A physical memory location can be mapped into (covered by) one or more logical
segments.
2-8
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Register Name: Processor Status Word
Register Mnemonic: PSW (FLAGS)
Register Function: Posts CPU status information.
15 0
OFDFIFTFSFZ
F
A
F
P
F
C
F
A1035-0A
Bit
Mnemonic
OF Overflow Flag 0 If OF is set, an arithmetic overflow has occurred.
DF Direction Flag 0
IF
TF Trap Flag 0 I f TF is set, the processor enter s single-step mode.
SF Sign Flag 0
ZF Z ero Flag 0 If ZF is set, the result of an operation is zero.
AF Auxiliary Flag 0
PF Parity Flag 0
CF Carry Flag 0
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.
Bit Name
Interrupt
Enable Flag
Reset
State
0
Function
If DF is set, string instructions are processed high
address to low address. If DF is clear, strings are
processed low address to high address.
If IF is set, the CPU recognizes maskable interrupt
requests. If IF is clear, maskable interrupts are
ignored.
If SF is set, the high-order bit of the result of an
operation is 1, indicating it is negative.
If AF is set, there has been a carry from the low
nibble to the high or a borrow from the high nibble
to the low nibble of an 8-bit quantity. Used in BCD
operations.
If PF is set, the result of an operation has even
parity.
If CF is set, there has been a carry out of, or a
borrow into, the high-order bit of the result of an
instruction.
Figure 2-5. Processor Status Word
2-9
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Fully
Overlapped
Partly
Overlapped
Contiguous
Segment A
Segment B
Segment D
Segment C
Disjoint
Logical
Segments
Segment E
Physical
Memory
0H 10000H 20000H 30000H
A1036-0A
Figure 2-6. Segment Locations in Physical Memory
The four segment registers point to four “currently addressable” segments (see Figure 2-7). The
currently addressable segments provide a work space consisting of 64 Kbytes for code, a 64
Kbytes for stack and 128 Kby tes f or data storage. Programs access code and data in another segment by updating the segment register to point to the new segment.
2.1.8 Logical Addresses
It is useful to think of every memory location as having two kinds of add resses, physical and logical. A physical address is a 20-bit value that identifies a unique byte location in the memory
space. Physical addresses range from 0H to 0FFFFFH. All exchanges between the CPU and
memory use physical addresses.
Programs deal with logical rather than ph ysical addresses. Program code can b e dev eloped without prior knowledge of where the code will be located in memory. A logical address consists of
a segment base value and an offset value. For any given memory location , the segment base value
locates the first byte of the segment. The offset value represents the distance, in b ytes, of the target location from the beginning of the seg ment. Segment base an d offset valu es are unsigned 1 6bit quantities. Many different logical addresses can map to the same physical location. In Figure
2-8, physical memory location 2C3H is contained in two differen t overlapping segments, on e beginning at 2B0H and the other at 2C0H.
2-10
Data:
DS:
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
FFFFFH
A
B
B
C
Code:
CS:
E
D
Stack:
Extra:
SS:
ES:
H
J
E
F
G
H
I
J
K
0H
A1037-0A
Figure 2-7. Currently Addressable Segments
The segment register is automatically selected according to the rules in Tab le 2-2. All information
in one segment type generally shares the same lo gical attributes ( e.g., code or data). This leads to
programs that are shorter, faster and better structured.
The Bus Interface Unit must obtain the logical address before generating the physical address.
The logical address of a mem ory location can come from different sou rces, depending o n the type
of reference that is being made (see Table 2-2).
Segment registers always hold the segment base addresses. The Bus Interface Unit determines
which segment register contains the base address according to the type of memory reference
made. However, the programmer can explicitly direct the Bus Interface Unit to use any cur rently
addressable segment (except for the destination operand of a string instruction) . In assembly language, this is done by preceding an instruction with a segment override prefix.
2-11
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Physical
Address
Offset
(3H)
Segment
Base
Logical
Addresses
Offset
(13H)
2C4H
2C3H
2C2H
2C1H
2C0H
2BFH
2BEH
2BDH
2BCH
2BBH
2BAH
2B9H
2-12
Segment
Base
Figure 2-8. Logical and Physical Address
2B8H
2B7H
2B6H
2B5H
2B4H
2B3H
2B2H
2B1H
2B0H
A1038-0A
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-2. Logical Address Sources
Type of Memory Reference
Instruction Fetch CS NONE IP
Stack Operation SS NONE SP
Variable (except following) DS CS, ES, SS Effective Address
String Source DS CS, ES, SS SI
String Destination ES NONE DI
BP Used as Base Register SS CS, DS, ES Effective Address
Default
Segment Base
Alternate
Segment Base
Offset
Instructions are always fetched from the current code segment. The IP register contains the instruction’s offset from the beginning of the segment. Stack instructions always o perate on the current stack segment. The Stack Pointer (SP) register contains the offset of the top of the stack from
the base of the stack. Most variables (memory operand s) are assumed to r eside in the current data
segment, but a program can instruct the Bus Interface Unit to override this assumption. Often, the
offset of a memory variable is not directly available and must be calculated at execution time. The
addressing mode specified in the instruction determines how this offset is calculated (see “Addressing Modes” on page 2-27). The result is called the operand’s Effective Address (EA).
Strings are addressed differently than other variables. The source operand of a string instruction
is assumed to lie in the current data segment. However, the program can use another currently
addressable segment. The operand’s offset is taken from the Sou rce I ndex (SI) register. The destination operand of a string instruction always resides in the current extra segment. The destination’s offset is taken from the Destination Index (DI) register. The string instructions
automatically adjust the SI and DI registers as they process the strings one byte or word at a time.
When an instruction designates the Base Pointer (BP) register as a base register, the variable is
assumed to reside in the current stack segment. The BP register pr ovide s a convenient way to access data on the stack. The BP register can also be used to access data in any other currently addressable segment.
2.1.9 Dynamically Relocatable Code
The segmented memory structure of the 80C1 86 Modular Core family allows creation of dynamically relocatable (position-independent) programs. Dynamic relocation allows a multiprogramming or multitasking system to make effective use of available m emory. Th e processor can write
inactive programs to a disk and reallocate the space they occupied to oth er progr ams. A disk-resident program can then be read back into available memory locations and restarted whenever it
is needed. If a progr am needs a larg e contiguous block of storage and the total amount is available
only in non-adjacent fragments, other program segments can be compacted to free enough continuous space. This process is illustrated in Figure 2-9.
2-13
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Before
Relocation
Code
Segment
Stack
Segment
Data
Segment
Extra
Segment
CS
SS
DS
ES
After
Relocation
CS
SS
DS
ES
Code
Segment
Stack
Segment
Data
Segment
Extra
Segment
Free Space
A1039-0A
Figure 2-9. Dynamic Code Relocation
To be dynamically relocatable, a program must not load or alter its segment registers and must
not transfer directly to a location outside the current code segment. All program offsets must be
relative to the segment registers. This allows the program to be moved anywhere in memory, pr ovided that the segment registers are updated to point to the new base addresses.
2-14
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1.10 Stack Implementation
Stacks in the 80C186 Modular Core family reside in memory space. They are located b y the Stack
Segment register (SS) and the Stack Pointer (SP). A system can have multiple stacks, but only
one stack is directly addressable at a time. A stack can be up to 64 Kbytes long, the maximum
length of a segment. Growing a stack segment beyo nd 64 Kby tes overwrites the beginn ing of the
segment. The SS register contains the base address of the current stack. The top of the stack, not
the base address, is the origination point of the stack. The SP register contains an offset that points
to the Top of Stack (TOS).
Stacks are 16 bits wide. Instructions operating on a stack add and remove stack elements one
word at a time. An element is pushed onto the stack (see Figure 2-10) by first decrementing the
SP register by 2 and then writing the data word. An element is popped off the stack by copying
it from the top of the stack and then incrementing the SP register by 2. The stack grows down in
memory toward its base address. Stack operations never m ove or erase elemen ts on the stack. The
top of the stack changes only as a result of updating the stack pointer.
2.1.11 Reserved Memory and I/O Space
Two specific areas in memory and one area in I /O spa ce are reserved in the 80C18 6 Core family.
• Locations 0H through 3FFH in low memory are used for the Interrupt Vector Table.
Programs should not be loaded here.
• Locations 0FFFF0H through 0FFFFFH in high memory are used for system reset code
because the processor begins execution at 0FFFF0H.
• Locations 0F8H through 0FFH in I/O space are reserved f or co mmunicatio n with other Intel
hardware products and must not be used. On the 80C186 core, these addresses are used as
I/O ports for the 80C187 numerics processor extension.
2-15
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
PUSH AX
Existing
Stack
12
34
POP AX
POP BX
10
BB
50
AA
TOS
1062
1060
105E
105B
105A
1058
1056
1054
1052
1050
00
22
44
66
88
AA
01
45
89
CD
10
00
11
33
55
77
99
BB
23
67
AB
EF
50
08
1062
1060
105E
105B
Bottom of stack
105A
1058
00
22
44
66
88
AA
11
33
55
77
99
BB
TOS
34
45
89
CD
10
00
12
67
AB
EF
50
06
on stack
Not presently
SS
SP
1056
1054
1052
1050
Stack operation for code sequence
PUSH AX
POP AX
POP BX
SS
SP
TOS
1062
1060
105E
105B
105A
1058
1056
1054
1052
1050
00
22
44
66
88
AA
34
45
89
CD
10
00
11
33
55
77
99
BB
12
67
AB
EF
50
0A
SS
SP
2-16
A1013-0A
Figure 2-10. Stack Operation
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2 SOFTWARE OVERVIEW
All 80C186 Modular Core family members execute the same instructions. This includes all the
8086/8088 instructions plus several additions and enhancements (see Appendix A, “80C186 Instruction Set Additions and Extensions”). The following sections describe the instruction s by category and provide a detailed discussion of the operand addressing modes.
Software for 80C186 core family systems need not be written in assembly lang uage. The p rocessor provides direct hardware support for programs written in the many high-level languages
available. The hardware addressing modes provide straightforward implementations of based
variables, arrays, arrays of structures and other high-level language data constructs. A powerful
set of memory-to-memory string operations allow efficient char acter data manipulation. Finally,
routines with critical performance requirements can be written in assembly language and linked
with high-level code.
2.2.1 Instruction Set
The 80C186 Modular Core family instru ctions treat different types of operan ds uniformly. Nearly
every instruction can operate on either byte or word data. Register, memory and immediate operands can be specified interchangeably in most instructions. Immediate values are exceptions:
they must serve as source operands and not destination operands. Memory variables can be manipulated (added to, subtracted fr om, shifted, compared) without b eing moved into and out of r egisters. This saves instructions, registers and execution time in assembly language programs. In
high-level languages, where most variab les are memo ry-ba sed, co mpilers can prod uce faster an d
shorter object programs.
The 80C186 Modular Core family instruction set can be viewed as exi sting on two levels. One is
the assembly level and the other is the machine level. To the assembly language pro grammer, the
80C186 Modular Core family appears to have about 100 instructions. One MOV (data move) instruction, for example, transfers a byte or a word fr om a register, a mem ory location or an immediate value to either a register or a memory location. The 80C186 Modular Core family CPUs,
however, recognize 28 different machine versions of the MOV instruction.
The two levels of instruction sets address two requirements: efficiency and simplicity. Approximately 300 forms of machine-level instruction s make v ery ef ficient use of s torage. For example,
the machine instruction that increments a memo ry operan d is three or four bytes long because the
address of the operand must be encoded in the instruction. Incrementin g a register , ho wever, requires less information, so the instruction can be shorter. The 8 0C186 Core family h as eigh t single-byte machine-level instructions that increment different 16-bit registers.
The assembly level instructions simplify the programmer’s view of the instruction set. The programmer writes one form of an INC (increment) instruction and the assembler examines the operand to determine which machine level instruction to generate. The following paragraphs
provide a functional description of the assembly-level instructions.
2-17
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.1 Data Transfer Instructions
The instruction set contains 14 data transfer instructions. These instructions move single bytes
and words between memory and registers. They also move single bytes and words between the
AL or AX register and I/O ports. Table 2-3 lists the four types of data transfer instructions and
their functions.
Table 2-3. Data Transfer Instructions
General-Purpose
MOV Move byte or word
PUSH Push word onto stack
POP Pop word off stack
PUSHA Push registers onto stack
POPA Pop registers off stack
XCHG Exchange byte or word
XLAT Translate byte
Input/Output
IN Input byte or word
OUT Output byte or word
Address Object and Stack Frame
LEA Load effective address
LDS Load pointer using DS
LES Load pointer using ES
ENTER Bu ild stack fra me
LEAVE Tear down stack frame
Flag Transfer
LAHF Load AH register from flags
SAHF Store AH register in flags
PUSHF Push flags from stack
POPF Pop flags off stack
Data transfer instructions are categorized as general purpose, input/output, address object and
flag transfer. The stack manip ulation instru ctions, used for transferr ing flag con tents and instructions used for loading segment registers are also included in this group. Figure 2-11 shows the
flag storage formats. The address object instructions manipulate the addresses of variables instead of the values of the variables.
2-18
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
PUSHF
POPF
2.2.1.2 Arithmetic Instructions
U
15
U = Undefined; Value is indeterminate
O = Overflow Flag
D = Direction Flag
I = Interrupt Enable Flag
T = Trap Flag
S = Sign Flag
Z = Zero Flag
A = Auxiliary Carry Flag
P = Parity Flag
C = Carry Flag
U
U
U
12
13
14
Figure 2-11. Flag Storage Format
O
11
LAHF
SAHF
10
ZUAUPUCS
65432107
Z6U5A4U3P2U1C
S7T8I9D
0
The arithmetic instructions (see Table 2-4) operate on four types of numbers:
• Unsigned binary
A1014-0A
• Signed binary (integers)
• Unsigned packed decimal
• Unsigned unpacked decimal
2-19
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-5 shows the interpretations of various bit pattern s according to number type. Bin ary numbers can be 8 or 16 bits long. Decimal numbers are stor ed in bytes, two digits per by te for pack ed
decimal and one digit per byte for unpacked decimal. The proc essor assumes that the operand s in
arithmetic instructions contain data th at represents valid n umbers for that instruction. Invalid data
may produce unpredictable results. The Execution Unit analyze s the results of arithmetic instructions and adjusts status flags accordingly.
Table 2-4. Arithmetic Instructions
Addition
ADD Add byte or word
ADC Add byte or word with carry
INC Increment byte or word by 1
AAA ASCII adjust for addition
DAA Decimal adjust for addition
Subtraction
SUB S ubtrac t byte or word
SBB Subtract byte or word with borrow
DEC Decrement byte or word by 1
NEG Negat e byte or word
CMP Compare byte or word
AAS ASCII adjust for subtraction
DAS Decimal adjust for subtraction
Multiplication
MUL Multiply byte or word unsigned
IMUL Integer multiply byte or word
AAM ASCII adjust for multiplication
Division
DIV Divide byte or word unsigned
IDIV Integer divide byte or word
AAD A SCI I adjust for division
CBW Conv ert byt e to word
CWD Convert word to double-word
2-20
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-5. Arithmetic Interpretation of 8-Bit Numbers
Hex Bit Pattern
07 0 0 0 0 0 1 1 1 7 +7 7 7
89 1 0 0 0 1 0 0 1 137 –119 invalid 89
C5 1 1 0 0 0 1 0 1 197 –59 invalid invalid
Unsigned
Binary
Signed
Binary
Unpacked
Decimal
Packed
Decimal
2.2.1.3 Bit Manipulation Instructions
There are three groups of instructions for manipulating bits within bytes and words. These three
groups are logical, shifts and rotates. Table 2-6 lists the bit manipulation instructions and their
functions.
Table 2-6. Bit Manipulation Instructions
Logicals
NOT “Not” byte or word
AND “And” byte or word
OR “Inclusive or” byt e or word
XOR “Exclusive or” byte or word
TEST “Test” byte or word
Shifts
SHL/SAL Shift logical/arithmetic left byte or word
SHR Shift logical right byte or word
SAR Shift arithmetic right byte or word
Rotates
ROL Rotate left byte or word
ROR Rotate right byt e or word
RCL Rotate through carry left byte or word
RCR Rotate through carry right byte or word
Logical instructions include the Boolean operators NOT, AND, OR and exclusive OR (XOR), as
well as a TEST instruction. The TEST instruction sets the f lags as a r esult of a Boolean AND o peration but does not alter either of its operands.
Individual bits in bytes and words can be shifted either arithmetically or logically. Up to 32 shif ts
can be performed, according to the valu e of the coun t operand coded in the instruction . The co unt
can be specified as an immediate value or as a variable in the CL register. This allows the shift
count to be a supplied at execution time. Arithmetic shifts can be used to multiply and divide binary numbers by powers of two. Logical shifts can be used to isolate bits in bytes or words.
2-21
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Individual bits in bytes and words can also be rotated. The processor does not discard the bits rotated out of an operand. The bits circle back to the other end of the operand. The number of bits
to be rotated is taken from the count op erand , which can specify either an immediate value o r the
CL register. The carry flag can act as an extension of the operand in two of the rotate instructions.
This allows a bit to be isolated in the Carry Flag (CF) and then tested by a JC (jump if carry) or
JNC (jump if not carry) instruction.
2.2.1.4 String Instructions
Five basic string operations process strings of bytes or words, one element (byte or word) at a
time. Strings of up to 64 Kbytes can be manipulated with these instructions. Instruction s are available to move, compare or scan for a value, as well as to move string elements to and from the
accumulator. Table 2-7 lists the string instructions. These basic operations can be preceded by a
one-byte prefix that causes the instruction to be repeated by the hardware, allowing long strings
to be processed much faster than is possible with a software loop. The repetitions can be terminated by a variety of conditions. Repeated operations can be interrupted and resumed.
Table 2-7. String Instructions
REP Repeat
REPE/REPZ Repeat while equal/zero
REPNE/REPNZ Repeat while not equal/not zero
MOVSB/MOVSW Move byte string/w ord string
MOVS Move byte or word string
INS Input byte or word string
OUTS Output byte or word string
CMPS Compare byte or word string
SCAS S can byte or word str ing
LODS Load byt e or word string
STOS Store byte or word string
String instructions operate similarly in many respects (see Table 2-8). A string instruction can
have a source operand, a destination oper and, or both. The hardware assumes that a sou rce string
resides in the current data segment. A segment prefix can override this assumptio n. A destination
string must be in the curren t extra segmen t. Th e assemb ler does not use th e operan d names to address strings. Instead, the contents of the Sou rce Index (SI) register are used as an offset to address
the current element of the source string. The contents of the Destination Index (DI) register are
taken as the offset of the current destination string element. These registers must be initialized to
point to the source and destination strings before executing the string instr uctions. The LDS, LES
and LEA instructions are useful in performing this function.
2-22
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
String instructions automatically update the SI reg ister, the DI register, or both , before processing
the next string element. The Direction Flag (DF) determines whether the ind ex registers are autoincremented (DF = 0) or auto-decremented (DF = 1). The processor adjusts the DI, SI, or both
registers by one for byte strings or by two for word strings.
If a repeat prefix is used, the count register (CX) is decremented by one after each repetition of
the string instruction. The CX register must be initialized to the number of repetitions before the
string instruction is executed. If the CX register is 0, the string instruction is not executed and
control goes to the following instruction.
Table 2-8. String Instruction Register and Flag Use
SI Index (offset) for source string
DI Index (offset) for destination string
CX Repetition counter
AL/AX Scan value
Destination for LODS
Source for STOS
DF Direction Flag
0 = auto-increment SI, DI
1 = auto-decrement SI, DI
ZF Scan/compare terminator
2.2.1.5 Program Transfer Instructions
The contents of the Code Segment (CS) and Instruction Pointer (IP) registers determine the instruction execution sequence in the 80C186 Modular Core family. The CS register contains the
base address of the current code segment. The Instruction Pointer register points to the memory
location of the next instruction to be fetched. In most operating conditions, the next instruction
will already have been fetched and will be waiting in the CPU instruction queue. Program transfer
instructions operate on the IP and CS registers. Changing the contents of these registers causes
normal sequential operation to be altered. When a program transfer occurs, the queue no longer
contains the correct instruction. The Bus Interface Unit obtains the nex t instruction fr om memo ry
using the new IP and CS values. It then passes the instruction directly to the Execution Unit and
begins refilling the queue from the new location.
The 80C186 Modular Core family offers four groups of program tr ansfer instructions (see Table
2-9). These are unconditional transfers, conditional transf ers, iteration control instructions and interrupt-related instructions.
2-23
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Unconditional transfer instructions can transfer control either to a target instruction within the
current code segment (intrasegment transfer) or to a different code segment (intersegment transfer). The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment transfer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and
JMP are all unconditional transfers.
CALL is used to transfer the program to a procedure. A CALL can be NEAR or FAR. A NEAR
CALL stacks only the Instruction Pointer, while a FAR CALL stack s both the Instruction Pointer
and the Code Segment register. The RET instruction uses the information pushed onto the stack
to determine where to return when the proced ure fin ishes. Note that the RET and CALL instr uctions must be the same type. This can be a problem when the CALL and RET instructions are in
separately assembled programs. The JMP instruction does not push any information onto the
stack. A JMP instruction can be NEAR or FAR.
Conditional transfer instructions are jumps that may or may not transfer control, depending on
the state of the CPU flags when the instruction is executed. Each conditional transfer instruction
tests a different combination of flags for a condition (see Table 2-10 ). If the condition is logically
TRUE, control is transferred to the target specified in the instruction. If the condition is FALSE,
control passes to the instruction following the conditional jump. All conditional jumps are
SHORT. The target must be in the current code segment within –128 to +127 bytes of the next
instruction’s first byte. For example, JMP 00H causes a jump to the first byte of the next instruction. Jumps are made by adding the relative displacement of the target to the Instructio n Po inter.
All conditional jumps are self-relative and are appropriate for position-independent routines.
2-24
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-9. Program Transfer Instructions
Conditional Transfers
JA/JNBE Jump if above/not below nor equal
JAE/JNB Jump if above or equal/not below
JB/JNAE Jump if below/not above nor equal
JBE/JNA Jump if below or equal/not above
JC Jump if carry
JE/JZ Jump if equal/zero
JG/JNLE Jump if greater/not less nor equal
JGE/JNL Jump if greater or equal/not less
JL/JNGE Jump if less/not greater nor equal
JLE/JNG Jump if less or equal/not greater
JNC Jump if not carry
JNE/JNZ Jump if not equal/not zero
JNO Jump if not overflow
JNP/JPO Jump if not parity/parity odd
JNS Jump if not sign
JO Jump if overflow
JP/JPE Jump if parity/parity even
JS Jump if sign
Unconditional Transfers
CALL Call procedure
RET Return from procedure
JMP Jump
Iteration Control
LOOP Loop
LOOPE/LOOPZ Loop if equal/zero
LOOPNE/LOOPNZ Loop if not equal/not zero
JCXZ Jump if register CX=0
Interrupts
INT Interrupt
INTO Interrupt if overflow
BOUND Interrupt if out of array bounds
IRET Interrupt return
2-25
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Iteration control instructions can be used to regulate the repetition of software loops. These instructions use the CX register as a counter. Like the conditional transfers, the iteration control instructions are self-relative and can transfer only to targets that are within –128 to +127 bytes of
themselves. They are SHORT transfers.
The interrupt instructions allow pro grams and external hardware devices to activate interrupt service routines. The effect of a software interrupt is similar to that of a hardware-initiated interru pt.
The processor cannot execute an interrupt acknowledge bus cycle if the interrupt originates in
software or with an NMI (Non-Maskable Interrupt).
Table 2-10. Interpretation of Conditional Transfers
Mnemonic Condition Tested “Jump if…”
JA/JNBE (CF or ZF)=0 above/not below nor equal
JAE/JNB CF=0 above or equal/not below
JB/JNAE CF=1 below/not above nor equal
JBE/JNA (CF or ZF)=1 below or equal/not above
JC CF=1 carry
JE/JZ ZF=1 equal/zero
JG/JNLE ((SF xor OF) or ZF)=0 great er/ not less nor equal
JGE/JNL (SF xor OF)=0 greater or equal/not less
JL/JNGE (SF xor OF)=1 less/not greater nor equal
JLE/JNG ((SF xor OF) or ZF)=1 less or equal/not greater
JNC CF=0 not carry
JNE/JNZ ZF=0 not equal/not zero
JNO OF=0 not overflow
JNP/JPO PF=0 not parity/parity odd
JNS SF=0 not sign
JO OF=1 overflow
JP/JPE PF=1 parity/parity equal
JS SF=1 sign
above
and
below
NOTE: The terms
greater
and
less
refer to the relationship of two signed values.
refer to the relationship of two unsigned values;
2-26
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.6 Processor Control Instructions
Processor control instructions (see Table 2-11) allow programs to control var ious CPU functions.
Seven of these instructions update flags, fo ur of them are used to synchronize th e microprocessor
with external events, and the remaining instruction causes the CPU to do nothing. Ex cept for flag
operations, processor control instructions do not affect the flags.
Table 2-11. Processor Control Instructions
Flag Operations
STC Set Carry flag
CLC Clear Carry flag
CMC Complement Carry flag
STD Set Direction flag
CLD Clear Direction flag
STI Set Interrupt Enable flag
CLI Clear Interrupt Enable flag
External Synchronization
HLT Halt until interrupt or reset
WAIT Wait for TEST
ESC Escape to external processor
LOCK Lock bus during next instruction
No Operation
NOP No operation
pin active
2.2.2 Addressing Modes
The 80C186 Modular Core family members access instruction operands in several ways. Operands can be contained either in registers, in the instruction itself, in memory or at I/O ports. Addresses of memory and I/O port operands can be calculated in many ways. These addressing
modes greatly extend the flexibility and convenience of the instruction set. The following paragraphs briefly describe register and immediate modes of operand addressing. A detailed description of the memory and I/O addressing modes is also provided.
2.2.2.1 Register and Immediate Operand Addressing Modes
Usually, the fastest, most compact operand addr essing forms specif y only register operands. Thi s
is because the register operand addresses are encod ed in in structio ns in just a few bits and no bus
cycles are run (the operation occurs within the CPU). Registers can serve as source operands, destination operands, or both.
2-27
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Immediate operands are constant data contained in an instruction. Immediate data can be either
8 or 16 bits in length. Immediate operands are available directly from the instruction queue and
can be accessed quickly. As with a register operand, no bus cycles need to be run to get an immediate operand. Immediate operands can be only source operands and must have a constant value.
2.2.2.2 Memory Addressing Modes
Although the Execution Unit has direct access to register and immediate operands, memory operands must be transferred to and from the CPU over the bus. When the Ex ecution Unit needs to
read or write a memory operand, it must pass an offset value to the Bus Interface Unit. The Bus
Interface Unit adds the offset to the shifted contents of a segment register, producing a 20-bit
physical address. One or more bus cycles are then run to access the operand.
The offset that the Execution Unit calculates for memory operand is called the operand’s Effective Address (EA). This address is an unsigned 16-bit number that expresses the operand’s distance, in bytes, from the beginning of the segment in which it resides. The Execution Unit can
calculate the effective address in several ways. Infor mation en coded in the secon d byte of the instruction tells the Execution Unit how to calculate th e effective add ress of each m emory operand.
A compiler or assembler derives this information from the instruction written by the programmer.
Assembly language programmers have access to all addressing modes.
The Execution Unit calculates the Effective Address by summing a displacement, the contents of
a base register and the contents of an index register (see Figure 2-12). Any combination of these
can be present in a given instruction. This allows a variety of memory addressing modes.
2-28
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Single Index Double Index
Encoded
in the
Instruction
Explicit
in the
Instruction
Assumed Unless
Overridden
by Prefix
BX
or
BP
or
SI
or
DI
BX
or
BP
Displacement
0000
CS
or
0000
SS
or
0000
DS
or
0000
ES
+
Effective
++
Address
++
SI
or
DI
EU
BIU
Physical Addr
A1015-0A
Figure 2-12. Memory Address Computation
The displacement is an 8- or 16-bit number contained in the instruction. The displacement generally is derived from th e position of th e operand’s name (a variable or label) in the program. The
programmer can modify this value or explicitly specify the displacement.
2-29
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
The BX or BP register can be specified as the base register for an effective address calculation.
Similarly, either the SI or the DI register can be specified as the index register. The displacement
value is a constant. The contents of the base an d index registers can chan ge during execution. Th is
allows one instruction to access different memory locations depending u pon the current values in
the base or base and index registers. The default base register for effective address calculations
with the BP register is SS, although DS or ES can be specified.
Direct addressing is the simplest memory addressing mode (see Figure 2-13 ). No registers are involved, and the effective address is taken directly from the displacement of the instruction. Programmers typically use direct addressing to access scalar variables.
With register indirect addressing, the effective address of a memory oper and can be taken directly
from one of the base or index registers (see Figure 2-14). One instruction can operate on variou s
memory locations if the base o r index register is u pdated accor dingly. Any 1 6-bit gener al register
can be used for register indirect addressing with the JMP or CALL instructions.
In based addressing, the effective address is the sum of a displacement value and the contents of
the BX or BP register (see Figure 2-15). Specifying the BP register as a base register directs the
Bus Interface Unit to obtain the operand from the current stack segment (unless a segment override prefix is present). This makes based addressing with the BP register a conven ient way to access stack data.
2-30
Opcode Mod R/M
Figure 2-13. Direct Addressing
Displacement
EA
A1016-0A
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Opcode Mod R/M
BX
or
BP
or
SI
or
DI
Figure 2-14. Register Indirect Addressing
EA
A1017-0A
Opcode
Mod R/M
Displacement
BX
or
+
BP
EA
A1018-0A
Figure 2-15. Based Addressing
Based addressing provides a simple way to ad dress data structures that may be located in diff erent
places in memory (see Figure 2-16). A base register can be pointed at the structure. Elements of
the structure can then be ad dressed by their displacements. Different cop ies of the same stru cture
can be accessed by simply changing the base register.
2-31
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Displacement
(Rate)
+
Base
Register
EA
High Address
Age
Status
Rate
Vac
Sick
Dept Div
Employee
Age
Status
Rate
Vac
Sick
Dept Div
Employee
Low Address
Displacement
(Rate)
+
Base Register
EA
A1019-0A
Figure 2-16. Accessing a Structure with Based Addressing
With indexed addressing, the effective address is calculated by summing a displacement and the
contents of an index register (SI or DI, see Figure 2-17). Indexed addressing is often used to access elements in an array (see Figure 2-18). The displacement locates the beginn ing of the arr ay,
and the value of the index register selects one element. If the index register contains 0000H, the
processor selects the first element. Since all array elements are the same length, simple arithmetic
on the register can select any element.
2-32
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Opcode
Displacement
+ +
Index Register
14
Mod R/M
Displacement
SI
or
DI
Figure 2-17. Indexed Addressing
High Address
Array (8)
Array (7)
Array (6)
Array (5)
Array (4)
Array (3)
+
EA
A1020-0A
Displacement
Index Register
2
Array (2)
EA
Array (1)
EA
Array (0)
1 Word
Low Address
Figure 2-18. Accessing an Array with Indexed Addressing
A1021-0A
2-33
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Based index addressing generates an effective address that is the sum of a base r egister , an index
register and a displacement (see Figure 2-19). The two ad dress componen ts can be determ ined at
execution time, making this a very flexible addressing mode.
Opcode
Mod R/M
Displacement
BX
or
+
BP
SI
or
+
DI
EA
A1022-0A
Figure 2-19. Based Index Addressing
Based index addressing provides a convenien t way for a procedure to add ress an array located on
a stack (see Figure 2-20). The BP register c an conta in the offset of a ref erence point o n the stack.
This is typically the top of the stack after the procedure has saved registers and allocated local
storage. The offset of the beginning of the array from the reference point can be expressed by a
displacement value. The index register can be used to access individual array elements. Arrays
contained in structures and matrices (two-dimensional arrays) can also be accessed with based
indexed addressing.
String instructions do not use normal memory add ressing modes to access operands. Instead, the
index registers are used implicitly (see Figure 2-21). When a string instruction executes, the SI
register must point to the first byte or word of the source string, and the DI r egister must po int to
the first byte or word of the destination string. In a repeated string operation, the CPU will automatically adjust the SI and DI registers to obtain subsequent bytes or words. For string instructions, the DS register is the default segment register for the SI register and the ES register is the
default segment register for the DI register. This allows string instructions to operate on data located anywhere within the 1 Mbyte address space.
2-34
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
High Address
Displacement
6
+
Base Register
+
Index Register
12
EA
(BP)
Parm 2
Parm 1
IP
Old BP
Old BX
Old AX
Array (6)
Array (5)
Array (4)
Array (3)
Array (2)
Array (1)
Array (0)
Count
Temp
Status
Displacement
Base Register
(BP)
Index Register
6
+
+
12
EA
1 Word
Low Address
Figure 2-20. Accessing a Stacked Array with Based Index Addressing
A1024-0A
2-35
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Opcode
SI
DI
Figure 2-21. String Operand
2.2.2.3 I/O Port Addressing
Source EA
Destination EA
A1025-0A
Any memory operand addressing modes can b e used to access an I/O port if the p ort is memorymapped. String instructions can also be used to transfer data to memory-mapped ports with an
appropriate hardware interface.
Two addressing modes can be used to access ports located in the I/O space (see Figure 2-22). For
direct I/O port addressing, the port number is an 8-bit immediate operand. This allows fixed access to ports numbered 0 to 255. Indirect I /O port addressing is similar to r egister indirect addressing of memory operands. The DX register contains the port number, which can range from 0 to
65,535. Adjusting the contents of the DX register allows one instruction to access any port in the
I/O space. A group of adjace nt ports can be accessed using a simple software loop that adjusts the
value of the DX register.
Opcode
Data
Opcode
2-36
Port Address
Direct Port
Addressing
Port AddressDX
Indirect Port
Addressing
A1026-0A
Figure 2-22. I/O Port Addressing
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.2.4 Data Types Used in the 80C186 Modular Core Family
The 80C186 Modular Co re family supp orts the data typ es described in Tab le 2-1 2 an d illustrated
in Figure 2-23. In general, individual data elements must fit within defined segment limits.
Table 2-12. Supported Data Types
Type Description
Integer
A signed 8- or 16-bit binary numeric value (signed byte or word). All operations assume
Ordinal
A n unsigned 8- or 16-bit binary numeric value (unsigned byte or word).
A byte (unpacked) representation of a single decimal digit (0-9).
BCD
A byte repres entat ion of alphanumeric and contr ol character s using the ASCI I
ASCII
Packed BCD
String
A contiguous sequence of byt es or words. A st ring can contain from 1 byte to 64
A 16- or 32-bit quantity. A 16-bit pointer consists of a 16-bit offset component; a 32-bit
Pointer
Floating Point
a 2’s complement representation.
The 80C187 numerics processor extension, when added to an 80C186 Modular Core
system, directly supports signed 32- and 64-bit integers (signed double-words and
quad-words). The 80C188 Modular Core does not support the 80C187.
standard.
A byte (packed) representation of two decimal digits (0-9).One digit is stored in each
nibble (4 bits) of the byte.
Kbytes.
pointer consists of the combination of a 16-bit base component (selector) plus a 16-bit
offset component.
A signed 32-, 64-, or 80-bit real num ber representat ion.
The 80C187 numerics processor extension, when added to an 80C186 Modular Core
system, directly supports floating point operands. The 80C188 Modular Core does not
support the 80C187.
2-37
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Signed Byte
Sign Bit
Signed Word
Sign Bit
Signed Double
Word*
Sign Bit
Signed Quad
Word*
Sign Bit
Binary Coded
Decimal (BCD)
ASCII
Packed BCD
String
Pointer
Floating
Point*
Sign Bit
70
Magnitude
+1
14
15
MSB
31
MSB
+7
63
MSB
70
BCD Digit n
70
ASCII Character n
70
Most
Significant Digit
70
Byte Word n
31
+9 +8 +7 +6 +5 +4 +3 +2 +1 +0
79
Magnitude
+3
+n
+n
+n
+n
+3
Exponent
87
23
24
48
47
2324
Selector
+2
+5+6
+2
0
Magnitude
+4
Magnitude
Unsigned Byte
0
Unsigned
+1
15
31
32
+1
7
BCD Digit 1
+1
7
ASCII Character 1
+1
7
+1
7
Byte Word 1
+1
15
Word
+2+3
16
Offset
7
MSB
Magnitude
15
MSB
87
+1
15
0
7
BCD Digit 0
0
7
ASCII Character 0
0
7
0
7
Byte Word 0
87
Magnitude
0
+1
87
Magnitude
0
016
0
0
0
0
0
0
0
0
Least
Significant Digit
0
0
0
016
0
0
0
2-38
NOTE: *Directly supported if the system contains an 80C187.
A1027-0B
Figure 2-23. 80C186 Modular Core Family Supported Data Types
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.3 INTERRUPTS AND EXCEPTION HANDLI NG
Interrupts and exceptions alter program execution in response to an external event or an error
condition. An interrupt handles asynchronous external events, for example an NMI. Exceptions
result directly from the execution of an instruction, usually an instruction fault. The user can
cause a software interrupt by executing an “INTn” instruction. The CPU processes software interrupts in the same way that it handles exceptions.
The 80C186 Modular Core responds to interrupts and exception s in th e sa me way for all devices
within the 80C186 Modular Core family. However, devices within the family may have diff erent
Interrupt Control Units. The Interrup t Control Un it handles all external interru pt sources and presents them to the 80C186 Modular Core via one maskable interrupt request (see Figure 2-24).
This discussion covers only those areas of interrupts and exceptions that are common to the
80C186 Modular Core family. The Interrupt Control Unit is proliferation-d ependent; see Chapter
8, “Interrupt Control Unit,” for additional information.
NMI
Maskable
Interrupt
Request
CPU
Interrupt
Control
Unit
External
Interrupt
Sources
Interrupt
Acknowledge
A1028-0A
Figure 2-24. Interrupt Control Unit
2.3.1 Interrupt/Exception Processing
The 80C186 Modular Core can ser vice up to 256 d ifferent interr upts and ex ceptions. A 256-entry
Interrupt Vector Table (Figure 2-25) contains the pointers to interrupt service routines. Each entry consists of four bytes, which contain the Code Segment (CS) and Instruction Pointer (IP) of
the first instruction in the interrupt service routine. Each interrupt or exception is given a type
number, 0 through 255, corresponding to its position in the Interrupt Vector Table. Note that interrupt types 0–31 are reserved for Intel and should not be used by an application program.
2-39
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Memory
Address
3FE
3FC
82
80
7E
7C
52
50
4E
4C
4A
48
46
44
42
40
3E
3C
3A
38
36
34
32
30
Table
Entry
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
2 Bytes
Vector
Definition
Type 255
User
Available
Type 32
Type 31
Reserved
Type 20
Type 19 - Timer 2
Type 18 - Timer 1
Type 17 - Reserved
Type 16 - Numerics
Type 15 - INT3
Type 14 - INT2
Type 13 - INT1
Type 12 - INT0
Memory
Address
2E
2C
2A
28
26
24
22
20
1E
1C
1A
18
16
14
12
10
0E
0C
0A
08
06
04
02
00
CS =Code Segment Value
IP = Instruction Pointer Value
Table
Entry
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
CS
IP
2 Bytes
Vector
Definition
Type 11 - DMA1
Type 10 - DMA0
Type 9 - Reserved
Type 8 - Timer 0
Type 7 - ESC Opcode
Type 6 - Unused
Opcode
Type 5 - Array
Bounds
Type 4 - Overflow
Type 3 - Breakpoint
Type 2 - NMI
Type 1 - Single-Step
Type 0 - Divide Error
A1009-02
Figure 2-25. Interrupt Vector Table
When an interrupt is acknowledged, a common event sequence (Figure 2-26) allows the processor to execute the interrupt service routine.
1. The processor saves a partial machine status by pushing the Processor Status Word onto
the stack.
2-40
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2. The Trap Flag bit and Interrupt Enable bit are cleared in the Processor Status Word. This
prevents maskable interrupts or single step exceptions from interrupting the processor
during the interrupt service routine.
3. The current CS and IP are pushed onto the stack.
4. The CPU fetches the new CS and IP for the interrupt vector routine from the Interrupt
Vector Table and begins executing from that point.
The CPU is now executing the interrupt service routine. The programmer must save (usually by
pushing onto the stack) all registers used in the interru pt service routine; o therwise, their con tents
will be lost. To allow nesting of maskable interrupts, the programmer must set the Interrupt Enable bit in the Processor Status Word.
When exiting an interrupt service routine, the programmer must restore (usually by popping off
the stack) the saved registers and execute an IRET instruction, which performs the following
steps.
1. Loads the return CS and IP by popping them off the stack.
2. Pops and restores the old Processor Status Word from the stack.
The CPU now executes from the point at which the interrupt or exception occurred.
2-41
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Stack
SP
PSW
CS
IP
CS
IP
Interrupt
Vector
Table
Interrupt Enable Bit
1
Trap Flag
00
3
4
Figure 2-26. Interrupt Sequence
2
Processor Status Word
Code Segment Register
Instruction Pointer
A1029-0A
2.3.1.1 Non-Maskable Interrupts
The Non-Maskable Interrupt (NMI) is the highest priority interrupt. It is usually reserved for a
catastrophic event such as impending power failure. An NMI cannot be prevented (or masked)
by software. When the NMI input is asserted, the interrupt processing sequence begins after execution of the current instruction completes (see “Interrupt Latency” on page 2-45). The CPU automatically generates a type 2 interrupt vector.
The NMI input is asy nchron ous. Setup an d hold times are given only to guar antee r ecogni tion o n
a specific clock edge. To be recognized, NMI must be asserted for at least one CLKOUT period
and meet the correct setup and hold times. NMI is edge-triggered and level-latched. Multiple
NMI requests cause multiple NMI service routines to be execu ted. NMI can be nested in th is manner an infinite number of times.
2-42
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.3.1.2 Maskable Interrupts
Maskable interrupts are the most common way to serv ice external har dware interrupts. Software
can globally enable or disable maskable interrupts. This is done by setting or clearing the Interrupt Enable bit in the Processor Status Word.
The Interrupt Control Unit processes the multiple sources of maskable interrupts and presents
them to the core via a single maskable interrupt input. The Interrupt Control Unit provides the
interrupt vector type to the 80C186 Modular Core. The Interrupt Control Unit differs among
members of the 80C186 Modular Cor e family; see Chap ter 8, “Interrupt Control Un it,” for info rmation.
2.3.1.3 Exceptions
Exceptions occur when an unusual condition preven ts further instru ction pro cessing until the exception is corrected. The CPU handles software interrupts and exceptions in the same way. The
interrupt type for an exception is either predefined or supplied by the instruction.
Exceptions are classified as either faults or traps, depending on when the exception is detected
and whether the instruction that caused the exception can be restarted. Faults are detected and serviced before the faulting instruction can be executed. The return address pushed onto the stack
in the interrupt processing instruction points to the beginning of the faulting instru ctio n. This allows the instruction to be restarted. Traps are detected and serviced immediately after th e instruction that caused the trap. The return address pushed o nto the stack during the inter rupt processing
points to the instruction following the trapping instruction.
Divide Error — Type 0
A Divide Error trap is invoked when the quotien t of an attempted division exceeds the max imum
value of the destination. A divide-by-zero is a common example.
Single Step — Type 1
The Single Step trap occurs after th e CPU executes one instruction with the Trap Flag (TF) bit set
in the Processor Status Word. This allows programs to execute one instruction at a time. Interrupts are not generated after prefix instruction s (e.g., REP), after instructions that modify segment
registers (e.g., POP DS) or after the WAIT instruction. Vectoring to the single-step interrupt service routine clears the Trap Flag bit. An IRET instruction in the interrupt service routine restores
the Trap Flag bit to logic “1” and transfers control to the next instruction to be single-stepped.
2-43
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Breakpoint Interrupt — Type 3
The Breakpoint Interrupt is a single-byte version of the INT instruction. It is commonly used by
software debuggers to set breakpoints in RAM. Because the instruction is only one byte long, it
can substitute for any instruction.
Interrupt on Overflow — Type 4
The Interrupt on Overflow trap occu rs if the Overf low Flag (OF) bit i s set in the Pro cessor S tatus
Word and the INT0 instruction is executed. Interrupt on Overflow is a common method for handling arithmetic overflows conditionally.
Array Bounds Check — Type 5
An Array Bounds trap occurs when the array index is outside the array bounds during execution
of the BOUND instruction (see Appendix A, “80C186 Instruction Set Additions and Extensions”).
Invalid Opcode — Type 6
Execution of an undefined opcode causes an Invalid Opcode trap.
Escape Opcode — Type 7
The Escape Opcode fault is used for floating p oint emulation. With 80C18 6 Modular Core family
members, this fault is enabled by setting the Escape Trap (ET) bit in the Relocation Reg ister (see
Chapter 4, “Peripheral Control Block”). When a floating point instruction is executed with the
Escape Trap bit set, the Escape Opcode fault occurs, and the E scap e Opcode serv ice routine emulates the floating point instruction. If the Escape Trap bit is cleared, the CPU sends the floating
point instruction to an external 80C187.
80C188 Modular Core Family members d o not support the 8 0C187 interface and always generate
the Escape Opcode Fault. The 80C186XL will generate the Escape Opcode Fault regardless of
the state of the Escape Trap bit unless it is in Numerics Mode.
Numerics Coprocessor Fault — Type 16
The Numerics Coprocessor fault is caused by an external 80C187 numerics coprocessor. The
80C187 reports the exception by asserting the ERROR
the ERROR
pin only when executing a numerics instruction. A Numerics Coprocessor Fault in-
pin. The 80C186 Modular Core checks
dicates that the previous numerics instruction caused the exception. The 80C187 saves the address of the floating point instruction that caused the exception. The return address pushed onto
the stack during the interrupt processing points to the numerics instruction that detected the exception. This way, the last numerics instruction can be restarted.
2-44
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.3.2 Software Interrupts
A Software Interrupt is caused by execu ting an “I NTn” instruction. The n p arameter corr espond s
to the specific interrupt type to be executed. The interrupt type can be any number between 0 and
255. If the n parameter corresponds to an interrupt type associated with a hardware interrupt
(NMI, Timers), the vectors are fetched and the routine is executed, but the corresponding bits in
the Interrupt Status register are not altered.
The CPU processes software interrupts and exceptions in the same way. Software interrupts, exceptions and traps cannot be masked.
2.3.3 Interrupt Latency
Interrupt latency is the amount of time it takes for the CPU to recog nize the existence of an interrupt. The CPU generally recognizes interrupts only between instructions or on instruction boundaries. Therefore, the current instruction must finish executing before an interrupt can be
recognized.
The worst-case 80C186 instruction execution time is an integer divide instruction with segment
override prefix. The instruction takes 69 clocks, assuming an 80C186 Modular Core family member and a zero wait-state external bus. The execution time for an 80C188 Modular Core family
member may be longer, depending on the queue.
This is one factor in determining interrupt latency. In addition, the following are also factors in
determining maximum latency:
1. The CPU does not recognize the Maskable Interrupt unless the Interrupt Enable bit is set.
2. The CPU does not recognize interrupts during HOLD.
3. Once communication is completely established with an 80C187, the CPU does not
recognize interrupts until the numerics instruction is finished.
The CPU can recognize interrupts only on valid instruction boundaries. A valid instruction
boundary usually occurs when the current instruction finishes. The following is a list of exceptions:
1. MOVs and POPs referencing a segment register delay the servicing of interrupts until
after the following instruction. The delay allows a 32-bit load to the SS and SP without an
interrupt occurring between the two loads.
2. The CPU allows interrupts between repeated string instructions. If multiple prefixes
precede a string instruction and the instruction is interrupted, only the one prefix
preceding the string primitive is restored.
3. The CPU can be interrupted during a WAIT instru ction. The CPU will return to the WAIT
instruction.
2-45
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.3.4 Interrupt Response Time
Interrupt response time is the time from the CPU recognizing an interru pt until the first instruction
in the service routine is executed. Interrupt response time is less for interrupts or exceptions
which supply their own vector type. The maskable interrupt has a longer response time because
the vector type must be supplied by the Interrupt Con trol Unit (see Chap ter 8, “Interrupt Control
Unit”).
Figure 2-27 shows the events that dictate interrupt response time for the interrupts that supply
their type. Note that an on-chip bus master, such as the DRAM Refresh Unit, can make use of
idle bus cycles. This can increase interrupt response time.
Clocks
Idle
Read IP
Idle
Read CS
Idle
Push Flags
Idle
Push CS
Push IP
Idle
5
4
5
4
4
4
3
4
4
5
First Instruction Fetch
From Interrupt Routine
Total 42
A1030-0A
Figure 2-27. Interrupt Response Factors
2.3.5 Interrupt and Exception Priority
Interrupts can be recognized only on valid instruction boundaries. If an NMI and a maskable interrupt are both recognized on the same instruction boundary, NMI has precedence. The
maskable interrupt will not be recognized until the Interrup t E nable bit is set and it is the high est
priority.
2-46
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Only the single step exception can occur concurrently with another exception. At most, two exceptions can occur at the same instructio n bou ndary and one of tho se excep tions must be the single step. Single step is a special case; it is discussed on page 2-48. Ignoring single step (for now),
only one exception can occur at any given instruction boundary.
An exception has priority over both NMI and the maskable interrupt. However, a pending NMI
can interrupt the CPU at any valid instruction boundary. Therefore, NMI can interrupt an exception service routine. If an excep tion and NMI occur simultan eously, the exception vector is taken,
then is followed immediately by the NMI vector (see Figure 2-28). Wh ile the exception has higher priority at the instruction boundary, the NMI interrupt service routine is executed first.
F = 1
NMI
Divide
Divide Error
Push PSW, CS, IP
Fetch Divide Error Vector
Push PSW, CS, IP
Fetch NMI Vector
Execute NMI
Service Routine
IRET
Execute Divide
Service Routine
IRET
Figure 2-28. Simultaneous NMI and Exception
A1031-0A
2-47
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Single step priority is a special case. If an interrupt (NMI or maskable) occu rs at the same instruction boundary as a sing le s tep , the interrupt vector is taken first, then is followed immediately by
the single step vector. However, the single step service routine is executed before the interrupt
service routine (see Figure 2-29). If the single step service routine re-enables single step by executing the IRET, the interrupt service routine will also be single stepped. This can severely limit
the real-time response of the CPU to an interrupt.
To prevent the single-step routine from executing before a maskable interrupt, disable in terrupts
while single stepping an in struction, then enable interrup t s in the sing le step service routine. The
maskable interrupt is serviced from within the single step service routine and that interrupt service routine is not single-stepped. To prevent single stepping before an NMI, the sing le-step service routine must compare the return address on the stack to the NMI vector. I f they are the same,
return to the NMI service routine immediately without executing the single step service routine.
NMI
Instruction
Trap Flag = 1
Push PSW, CS, IP
Fetch Divide Error Vector
Trap Flag = 0
Push PSW, CS, IP
Fetch Single Step Vector
Execute Single Step
Service Routine
IRET
Trap Flag = ???
Figure 2-29. Simultaneous NMI and Single Step Interrupts
A1032-0A
The most complicated case is when an NMI, a maskable interrupt, a single step and another exception are pending on the same instruction boundary. Figure 2-30 shows how this case is prio ritized by the CPU. Note that if the single-step routine sets the Trap Flag ( TF) bit befo re executing
the IRET instruction, the NMI routine will also be single stepped.
2-48
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Interrupt Enable Bit (IE) = 1
Trap Flag (TF) = 1
NMI
Divide
Push PSW, CS, IP
Fetch Divide Error Vector
Push PSW, CS, IP
Fetch NMI Vector
Fetch Single Step Vector
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = ???
Interrupt Enable Bit (IE) = 1
Trap Flag (TF) = X
Timer Interrupt
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = 0
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = 0
Push PSW, CS, IP
Execute Single Step
Service Routine
IRET
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = 0
Push PSW, CS, IP
Fetch Single Step Vector
Interrupt Enable Bit (IE) = 1
Trap Flag (TF) = X
Execute Single Step Service Routine
IRET
Figure 2-30. Simultaneous NMI, Single Step and Maskable Interrupt
A1034-0A
2-49
Bus Interface Unit
3
CHAPTER 3
BUS INTERFACE UNIT
The Bus Interface Unit (BIU) generates bus cycles that prefetch instructions from memory, pass
data to and from the execution unit, and pass data to and from the integrated peripheral units.
The BIU drives address, data, status and control information to define a bus cycle. The start of a
bus cycle presents the address of a memory or I/O location and status information defining the
type of bus cycle. Read or write control signals follow the addr ess and define the direction of data
flow. A read cycle requires data to flow fro m the selected memo ry or I/O device to the BIU. In a
write cycle, the data flows from the BIU to the selected mem ory or I/O dev ice. Upon term ination
of the bus cycle, the BIU latches read data or removes write data.
3.1 MULTIPLEXED ADDRESS AND DATA BUS
The BIU has a combined add ress and data bu s, commo nly ref erred to as a time-multiplexed bus.
Time multiplexing address and data information makes the most efficient use of device package
pins. A system with address latching provided within the memory and I/O devices can directly
connect to the address/data bus (or local bus). The local bus can be demultiplexed with a single
set of address latches to provide non-multiplexed address and data information to the system.
3.2 ADDRESS AND DATA BUS CONCEPTS
The programmer views the memory or I/O addr ess space as a sequ ence o f bytes. Memo ry space
consists of 1 Mbyte, while I/O space consists of 64 Kbytes. Any byte can contain an 8-bit data
element, and any two consecutive bytes can contain a 16-bit data element (identified as a word).
The discussions in this section apply to both memory and I/O bus cycles. For brevity, memory
bus cycles are used for examples and illustration.
3.2.1 16-Bit Data Bus
The memory address space on a 16-b it data bus is physically implemented by dividing the address
space into two banks of up to 512 Kbytes each (see Figure 3-1). One bank connects to the lower
half of the data bus and contains even-addressed bytes (A0=0). The other bank connects to the
upper half of the data bus and contains odd-addressed bytes (A0=1). Address lines A19:1 select
a specific byte within each bank. A0 and Byte High Enable (BHE
or both banks participate in the data transfer.
) determine whether one bank
3-1
BUS INTERFACE UNIT
Physical Implementation
of the Address Space for
8-Bit Systems
1 MByte
FFFFF
FFFFE
2
1
0
D7:0 D15:8A19:1A19:0 D7:0
Figure 3-1. Physical Data Bus Models
512 KBytes
Physical Implementation
of the Address Space for
16-Bit Systems
FFFFF
FFFFD
5
3
1
BHE A0
512 KBytes
FFFFE
FFFFC
4
2
0
A1100-0A
Byte transfers to even addresses transfer inf orm ation over the lower half of the data b us (see Figure 3-2). A0 low enables the lower bank, while BHE
from the upper ban k is ignored during a bus read cycle. BHE
high disables the upper bank. The data value
high prevents a write operation fr om
destroying data in the upper bank.
Byte transfers to odd addresses transfer info rmation over the upper half of the data bus (see Figure
3-2). BHE
low enables the upper bank, while A0 high disables the lower bank. The data value
from the lower bank is ignored during a bus read cycle. A0 high prevents a write operation from
destroying data in the lower bank.
To access even-addressed 16-bit words (two consecutive bytes with the least-significant byte at
an even address), information is transferred over both halves of the data bus (see Figure 3-3).
A19:1 select the appropriate byte within each bank. A0 and BHE
drive low to enable both bank s
simultaneously.
Odd-addressed word accesses require the BIU to split the transfer into two byte operations (see
Figure 3-4). The first operation transfers data over the upper half of the bus, while the second operation transfers data over the lower half o f the bus. The BIU automatically executes the two- byte
sequence whenever an odd-addressed word access is performed.
3-2
Y + 1
X + 1
BUS INTERFACE UNIT
Even Byte Transfer
Y
(X)
A19:1 D15:8 D7:0
BHE
(High)
Odd Byte Transfer
A19:1
Y + 1
(X + 1)
D15:8
BHE
Y
X
D7:0
(Low)
Figure 3-2. 16-Bit Data Bus Byte Transfers
A0
(Low)
A0
(High)
A1104-0A
3-3
BUS INTERFACE UNIT
(X + 1)
A19:1 D15:8 D7:0
BHE
(Low)
Figure 3-3. 16-Bit Data Bus Even Word Transfers
(X)
A0
(Low)
A1107-0A
During a byte read operation, the BIU floats the entire 16-bit data bus, even though the transfer
occurs on only one half of the bus. This action simplifies the decoding r equirements for read-o nly
devices (e.g., ROM, EPROM, Flash). During the byte read, an external device can drive both
halves of the bus, and the BIU automatically accesses the correct half. During the byte write operation, the BIU drives both halves of the bus. Information on the ha lf of the bus no t involved in
the transfer is indeterminate. This action requires that the appropriate bank (defined by BHE
or
A0 high) be disabled to prevent destroying data.
3-4
(X + 1)
BUS INTERFACE UNIT
First Bus Cycle
Y
X
A19:1 D15:8 D7:0
BHE
(Low)
A0
(High)
Second Bus Cycle
Y + 1
X + 1
A19:1 D15:8 D7:0
BHE
(High)
Figure 3-4. 16-Bit Data Bus Odd Word Transfers
(Y)
X
A0
(Low)
A1108-0A
3.2.2 8-Bit Data Bus
The memory address space on an 8-b it data bus is physically implemented as one bank of 1 Mbyte
(see Figure 3-1 on page 3-2). Address lines A19:0 select a specific byte within the bank. Unlike
transfers with a 16-bit bus, byte and word transfers (to even or odd addresses) all transfer data
over the same 8-bit bus.
Byte transfers to even or odd addresses transfer information in one bus cycle. Word transfers to
even or odd addresses transfer information in two bus cy cles. The BIU automatically converts the
word access into two consecutive byte accesses, making the operation transparent to the progr ammer.
3-5
BUS INTERFACE UNIT
For word transfers, the word address defines the first byte transferred. The second byte transfer
occurs from the word address plus one. Figure 3-5 illustrates a word transfer on an 8-bit bus interface.
First Bus Cycle
Second Bus Cycle
(X + 1)
(X)
A19:0 D7:0 D7:0
Figure 3-5. 8-Bit Data Bus Word Transfers
A19:0
A1109-0A
3.3 MEMORY AND I/O INTERFACES
The CPU can interface with 8- and 16-bit memory and I/O devices. Memory devices exchange
information with the CPU during memory read, memory write and instruction fetch bus cycles.
I/O (peripheral) devices exchange information with the CPU during memory read, memory write,
I/O read, I/O write and interrupt acknowledge bus cycles. Memory-mapped I/O refers to peripheral devices that exchange information during memory cycles. Memory-mapped I/O allows the
full power of the instruction set to be used when communicating with peripheral devices.
I/O read and I/O write bus cycles use a separate I/O address space. Only IN and OUT instructions
can access I/O address space, and information must be transferred between the per ipheral device
and the AX register. The first 256 bytes (0–255) of I/O space can be accessed directly by the I/O
instructions. The entire 64 Kbyte I/O address space can be accessed only indirectly, through the
DX register. I/O instructions always force address bits A19:16 to zero.
Interrupt acknowledge, or INTA
input capability. Valid address information is not generated as part of the INTA
, bus cycles access an I/O device intended to increase interrupt
bus cycle, and
data is transferred only over the lower bank (16-bit device).
3-6
BUS INTERFACE UNIT
3.3.1 16-Bit Bus Memory and I/O Requirements
A 16-bit bus has certain assumptions that must be met to operate pr operly. Memor y used to store
instruction operands (i.e., the program) and immediate data must be 16 bits wide. Instruction
prefetch bus cycles require that both banks be used. The lower bank contains the even bytes of
code and the upper bank contains the odd bytes of code.
Memory used to store interrupt vectors and stack data must be 16 bits wide. Memory address
space between 0H and 3FFH (1 Kbyte) holds the starting location of an interrupt routine. In response to an interrupt, the BIU fetches two consecutive, even-addressed word s from this 1 Kbyte
address space. Stack pushes and pops always write or read even-addressed word data.
3.3.2 8-Bit Bus Memory and I/O Requirements
An 8-bit bus interface has no restrictions on implementing the memory or I/O interfaces. All
transfers, bytes and words, occur over the single 8-bit bus. Operations requiring word transfers
automatically execute two consecutive byte transfers.
3.4 BUS CYCLE OPERATION
The BIU executes a bus cycle to transfer data b etween any of the integ rated units and any external
memory or I/O devices (see Figure 3-6). A bus cycle consists of a minimum of four CPU clocks
known as “T-states.” A T-state is bounded by one falling edge of CLKOUT to the next falling
edge of CLKOUT (see Figure 3-7). Phase 1 represents the low time of the T-state and starts at the
high-to-low transition of CLKOUT. Phase 2 represents the high time of the T-state and starts at
the low-to-high transition of CLKOUT. Address, data and control signals generated by the BIU
go active and inactive at different phases within a T-state.
3-7
BUS INTERFACE UNIT
CLKOUT
ALE
T4 T1 T2 T3 T4
S2:0
AD15:0
RD / WR
CLKOUT
Valid Status
Address
Figure 3-6. Typical Bus Cycle
Data
TN
Falling
Edge
Rising
Edge
Phase 1 Phase 2
(Low Phase)
Figure 3-7. T-State Relation to CLKOUT
(High Phase)
A1507-0A
A1111-0A
Figure 3-8 shows the BIU state diagram. Typically a bus cycle consists of four consecutive Tstates labeled T1, T2, T3 and T4. A TI (idle) state occurs when no bus cycle is pendin g. Multiple
T3 states occur to generate wait states. The TW symbol represents a wait state.
The operation of a bus cycle can be separated into two phases:
• Address/Status Phase
• Data Phase
3-8
BUS INTERFACE UNIT
The address/status phase starts just before T1 and continues through T1. The data phase starts at
T2 and continues through T4. Figure 3-9 illustrates the T-state relationship of the two phases.
T4
Bus Ready
Request Pending
HOLD Deasserted
Halt Bus Cycle
T2T1 T3
Bus Not
Ready
Request Pending
HOLD Deasserted
TI
RES#
Asserted
HOLD Asserted
Figure 3-8. BIU State Diagram
Bus Ready
No Request Pending
HOLD Deasserted
A1533-02
3-9
BUS INTERFACE UNIT
T4
or TI
T1 T2
T3
or TW
T4
or TI
CLKOUT
Address/
Status Phase
Figure 3-9. T-State and Bus Phases
Data Phase
A1113-0A
3.4.1 Address/Status Phase
Figure 3-10 shows signal timing relationships for the address/status phase of a bus cycle. A bus
cycle begins with the transition of ALE and S2:0
. These signals transition during phase 2 of the
T-state just prior to T1. Either T4 or TI precedes T1, depending on the operation of the previous
bus cycle (see Figure 3-8 on page 3-9).
ALE provides a strobe to latch physical address information. Address is presented on the multiplexed address/data bus during T1 (see Figure 3-10). The falling edge of ALE occurs during the
middle of T1 and provides a strobe to latch the address. Figur e 3-11 presents a typical circu it for
latching addresses.
The status signals (S2:0
) define the type of bus cycle (Table 3-1). S2:0 remain valid until phase
1 of T3 (or the last TW, when wait states occur). The circuit shown in Fi gure 3-11 can also be
used to extend S2:0
3-10
beyond the T3 (or TW) state.
CLKOUT
T4
or TI
BUS INTERFACE UNIT
T1 T2
ALE
AD15:0
A19:16
S2:0
BHE
NOTES:
1. T
CHLH TCHSV
2. T
CLAV
3. T
AVLL
4. T
CHLL
5. T
CLAZ
6. T
LLAX
1
4
2
3
Valid
Address
Valid
Valid
: Clock high to ALE high, S2:0 valid.
: Clock low to address valid, BHE valid.
: Address valid to ALE low (address setup to ALE).
: Clock high to ALE low.
: Clock low to address invalid (address hold from clock low).
: ALE low to address invalid (address hold from ALE).
5
6
Figure 3-10. Address/Status Phase Signal Relationships
A1509-0A
3-11
BUS INTERFACE UNIT
Signals From CPU
Latched
Address Signals
A19:16
S2:0
AD15:8
AD7:0
ALE
4
3
I
I
STB
4
O
3
O
LA19:16
LS2:0
OE
8
I
STB
8
O
LA15:8
OE
8
I
STB
8
O
LA7:0
OE
Figure 3-11. Demultiplexing Address Information
A1102-0A
3-12
Table 3-1. Bus Cycle Types
Status Bit
Operation
S2 S1 S0
0 0 0 Interrupt Acknowledge
001I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Instruction Prefetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Idle (passive)
BUS INTERFACE UNIT
3.4.2 Data Phase
Figure 3-12 shows the timing relationships for the data phase of a bus cycle. The only bus cycle
type that does not have a data phase is a bus halt. During the data phase, the bus transfers information between the internal units and the memory or peripheral device selected during the address/status phase. Appropriate control signals become active to coordinate the transfer of data.
The data phase begins at phase 1 of T2 and continues until phase 2 of T4 or TI. The length of the
data phase varies depending on the number of wait states. Wait states occur after T3 and before
T4 or TI.
3.4.3 Wait States
Wait states extend the data phase of the bus cycle. Memory and I/O devices that cannot provide
or accept data in the minimum four CPU clocks require wait states. Figure 3-13 shows a typical
bus cycle with wait states inserted.
The bus ready inputs (ARDY and SRDY) an d th e Chip-Select Un it con trol b us cy cle wait states.
Only the bus ready inputs are described in this chapter. (See Chapter 6, “Chip-Select Unit,” for
additional information.)
Figure 3-14 shows a simplified block diagram of the ARDY and SRDY inputs. Either ARDY or
SRDY active signals a bus ready condition; therefore, both pins must be inactive to signal a notready condition. Depending on the size and characteristics of the system, ready implementation
can take one of two approaches: normally not-ready or normally ready.
3-13
BUS INTERFACE UNIT
CLKOUT
RD/ WR
AD15:0
Write
AD15:0
Read
S2:0
NOTES:
1. T
2. T
3. T
4. T
5. T
6. T
7. T
T2
1
Valid Write Data
CLRL/CLWL, TCLOV
: Clock low to status inactive.
CLSH
: Data input valid to clock low.
DVCL
CLRH/CLWH
: Data input HOLD from clock low.
CLDX
: Output data HOLD from WR high.
WHDX
: Bus no longer floating from RD high.
RHAV
: Clock low to valid RD/WR active, write data valid.
: Clock valid to RD/WR inactive.
3
T3
or TW
2
Read Data
T4
or TI
4
6
7
5
Valid
3-14
Figure 3-12. Data Phase Signal Relationships
CLKOUT
ALE
BUS INTERFACE UNIT
T1 T2 T3 TW TW T4
ARDY
CLKOUT
S2:0
A19:16
AD15:0
WR
READY
Valid
Address
Address Valid Write Data
Figure 3-13. Typical Bus Cycle with Wait States
DQ
Rising
Edge
DQ
Falling
Edge
A1040-0A
BUS READY
SRDY
A1041-0A
Figure 3-14. ARDY and SRDY Pin Block Diagram
3-15
BUS INTERFACE UNIT
A normally not-ready system is one in which ARDY and SRDY remain low at all times except
to signal a ready condition. For any bus cycle, only the selected device drives either ready input
high to complete the bus cycle. The circuit shown in Figure 3-15 illustrates a simple circuit to
generate a normally not-ready signal. Note that if no device is selected the bus remains not-
ready indefinitely. Systems with many slow devices that cannot operate at the maximum bus
bandwidth usually implement a normally not-ready signal.
The start of a bus cycle clears the wait state module and forces ARDY l ow. After every rising
edge of CLKOUT, INPUT1 and INPUT2 are shifted through the module and eventually drive
ARDY high. Assuming INPUT1 and INPUT2 are valid prior to phase 2 of T2, no delay through
the module causes one wait state. Each additional clock delay through the module generates one
additional wait state. Two inputs are used to establish different wait state conditions. The same
circuit works for SRDY, but no delay through the module results in no wait states.
CS1
Wait State Module
CS2
Input 1
Input 2
CS3
CS4
ALE
CLKOUT
Figure 3-15. Generating a Normally Not-Ready Bus Signal
Clear
Clock
Out
READY
A1080-0A
A normally ready signal remains high at all times except when the selected device needs to signal
a not-ready condition. For any bus cycle, only the selected device drives the ready input (or inputs) low to delay the completion of the bus cycle. The circuit shown in Figure 3-16 illustrates a
simple circuit to generate a normally ready signal. Note that if no device is selected the bus re-
mains ready. Systems that have few or no devices requiring wait states usually implement a normally ready signal.
The start of a bus cycle preloads a zero shifter and forces SRDY active (high). SRDY remains
active if neither CS1
or CS2 goes low. Should either CS1 or CS2 go low, zeros are shif ted out on
every rising edge of CLKOUT, causing SRDY to go inactive. At the end of the shift pattern,
SRDY is forced active again. Assuming CS1
and CS2 are active just prior to phase 2 of T2, shifting one zero through the module causes one wait state. Each additional zero shifted through the
module generates one wait state. The same circuit works for ARDY, but shifting one zero through
the module generates two wait states.
3-16
Wait State Module
BUS INTERFACE UNIT
CS1
CS2
ALE
CLKOUT
Figure 3-16. Generating a Normally Ready Bus Signal
The ARDY input has two major timing concerns that can affect whethe r a normally ready or normally not-ready signal may be required. Two latches capture the state of the ARDY input (see
Figure 3-14 on page 3-15). The first latch captures ARDY on the phase 2 clock edge. The second
latch captures ARDY and the result of first latch on the phase 1 clock edge. The following items
define the requirements of the ARDY input to meet ready or not-ready bus conditions.
Enable
Load
Clock
Out
READY
A1081-0A
• The bus is ready if both of these two conditions are true:
— ARDY is active prior to the phase 2 clock edge, and
— ARDY remains active after the phase 1 clock edge.
• The bus is not-ready if either of these two conditions is true:
— ARDY is inactive prior to the phase 2 clock edge, or
— ARDY is inactive prior to the phase 1 clock edge.
A single latch captures the state of the SRDY input (see Figure 3-14 on page 3-15). SRDY must
be valid by the phase 1 clock edge. The following items define the requirements of the SRDY
input to meet ready or not-ready bus conditions.
• The bus is ready if SRDY is active prior to the phase 1 clock edge.
• The bus is not-ready if SRDY is inactive prior to the phase 1 clock edge.
A normally not-ready system m ust generate a valid ARDY input at phase 2 of T2 or a valid SRDY
input at phase 1 of T3 to prevent wait states. If it cannot, then running without wait states requires
a normally ready system. Figure 3-17 illustrates the timing necessary to prevent wait states in a
normally not-ready system. Figure 3-17 also shows how to terminate a bus cycle with wait states
in a normally not-ready system.
3-17
BUS INTERFACE UNIT
T2
or T3
or TW
T3
or TW
T4
CLKOUT
1
2
3
ARDY
SRDY
In a Normally-Not-Ready system, wait states are inserted until (1 or 2) and 3 are met.
1. T
2. T
3. T
!
: ARDY active to clock high (assumes ARDY remains active until 3).
ARYCH
: SRDY active to clock low.
SRYCL
CLARX, TCLSRY
Failure to meet SRDY setup and hold can cause a device failure
(i.e., the bus hangs or operates inappropriately).
Figure 3-17. Normally Not-Ready System Timing
: ARDY and SRDY hold from clock low.
A1511-0A
A valid not-ready input can be generated as late as phase 1 of T3 to insert wait states in a normally
ready system. A normally not-ready system must run wait states if the not-ready condition can not
be met in time. Figure 3-18 illustrates the minimum and maximum timing necessary to insert wait
states in a normally ready system. Figure 3-18 also shows how to terminate a bus cycle with wait
states in a normally ready system.
The BIU can execute an indefin ite number of wait states. However , bus cycles with large numbers
of wait states limit the performance of the CPU and the integrated peripherals. CPU performance
suffers because the instruction prefetch queue cannot be kept full. Integrated peripheral performance suffers because the maximum bus bandwidth decreases.
3.4.4 Idle States
Under most operating condi tions, the BIU executes consecu tive (back -to-back) bus cycles. However, several conditions cause the BIU to become idle. An idle condition oc curs between bu s cycles (see Figure 3-8 on page 3-9) and may last an indefinite period of time, depending on the
instruction sequence.
3-18
BUS INTERFACE UNIT
T2 T3 TW
CLKOUT
1
2
ARDY
In a Normally-Ready system, a wait state will be inserted when 1 & 2 are met.
(Assumes SRDY is low.)
1. T
2. T
: ARDY low to clock high
ARYCH
ARYCHL
: Clock high to ARDY high (ARDY inactive hold time)
T2 T3 TW
CLKOUT
1
2
ARDY
SRDY
Alternatively, in a Normally-Ready system, a wait state will be inserted
when1 & 2 are met for SRDY and ARDY.
1. T
2. T
!
, T
ARYCL
, T
CHARX
Failure to meet ARDY and SRDY setup and hold can cause a device failure
(i.e., the bus hangs or operates inappropriately).
: ARDY and SRDY low to clock low
SRYCL
: ARDY and SRDY low from clock low
CLSRY
T4
T4
A1512-0A
Figure 3-18. Normally Ready System Timings
Conditions causing the BIU to become idle include the following.
• The instruction prefetch queue is full.
• An effective address calculation is in progress.
• The bus cycle inherently requires idle states (e.g., interrupt acknowledge, locked opera-
tions).
• Instruction execution forces idle states (e.g., HLT, WAIT).
3-19
Loading...