Intel 80C188EA, 80L186EA, 80C186EA, 80L188EA User Manual

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80C186EA/80C188EA AND 80L186EA/80L188EA

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186 Upgrade for Power Critical Applications

Fully Static Operation

True CMOS Inputs and Outputs

Integrated Feature Set Ð Static 186 CPU Core Ð Power Save, Idle and Powerdown

Modes Ð Clock Generator Ð 2 Independent DMA Channels Ð 3 Programmable 16-Bit Timers Ð Dynamic RAM Refresh Control Unit Ð Programmable Memory and

Peripheral Chip Select Logic Ð Programmable Wait State Generator Ð Local Bus Controller Ð System-Level Testing Support

(High Impedance Test Mode)

Speed Versions Available (5V): Ð 25 MHz (80C186EA25/80C188EA25) Ð 20 MHz (80C186EA20/80C188EA20) Ð 13 MHz (80C186EA13/80C188EA13)

The 80C186EA is a CHMOS high integration embedded microprocessor. The 80C186EA includes all of the features of an ‘‘Enhanced Mode’’ 80C186 while adding the additional capabilities of Idle and Powerdown Modes. In Numerics Mode, the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor.

Speed Versions Available (3V): Ð 13 MHz (80L186EA13/80L188EA13) Ð 8 MHz (80L186EA8/80L188EA8)

Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O

Supports 80C187 Numeric Coprocessor Interface (80C186EA only)

Available in the Following Packages: Ð 68-Pin Plastic Leaded Chip Carrier

(PLCC) Ð 80-Pin EIAJ Quad Flat Pack (QFP) Ð 80-Pin Shrink Quad Flat Pack (SQFP)

Available in Extended Temperature Range (

40§Ctoa85§C)

272432– 1

*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

INTEL CORPORATION, 1995

October 1995

Order Number: 272432-003

80C186EA/80C188EA, 80L186EA/80L188EA

80C186EA/80C188EA AND 80L186EA/80L188EA

16-Bit High Integration Embedded Processor

CONTENTS PAGE

INTRODUCTION

80C186EA CORE ARCHITECTURE ААААААА 4

Bus Interface Unit АААААААААААААААААААААААААА 4 Clock Generator ААААААААААААААААААААААААААА 4

80C186EA PERIPHERAL

ARCHITECTURE АААААААААААААААААААААААА 5

Interrupt Control Unit ААААААААААААААААААААААА 5 Timer/Counter Unit АААААААААААААААААААААААА 5 DMA Control Unit АААААААААААААААААААААААААА 7 Chip-Select Unit АААААААААААААААААААААААААААА 7 Refresh Control Unit ААААААААААААААААААААААА 7 Power Management АААААААААААААААААААААААА 7 80C187 Interface (80C186EA Only) ААААААААА 8 ONCE Test Mode АААААААААААААААААААААААААА 8

DIFFERENCES BETWEEN THE

80C186XL AND THE 80C186EA

Pinout Compatibility АААААААААААААААААААААААА 8 Operating Modes ААААААААААААААААААААААААААА 8 TTL vs CMOS Inputs ААААААААААААААААААААААА 8 Timing Specifications ААААААААААААААААААААААА 8

PACKAGE INFORMATION АААААААААААААААА 9

Prefix Identification ААААААААААААААААААААААААА 9 Pin Descriptions АААААААААААААААААААААААААААА 9 80C186EA Pinout ААААААААААААААААААААААААА 15

ААААААААААААААААААААААААААА 4

АААААААА 8

CONTENTS PAGE

PACKAGE THERMAL

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS ААААААААА 21

Absolute Maximum Ratings ААААААААААААААА 21 Recommended Connections АААААААААААААА 21

DC SPECIFICATIONS АААААААААААААААААААА 22

ICCversus Frequency and Voltage ААААААААА 24 PDTMR Pin Delay Calculation ААААААААААААА 24

AC SPECIFICATIONS АААААААААААААААААААА 25

AC CharacteristicsÐ80C186EA20/13 ААААА 25 AC CharacteristicsÐ80L186EA13/8 ААААААА 27 Relative Timings АААААААААААААААААААААААААА 29

AC TEST CONDITIONS АААААААААААААААААА 30

AC TIMING WAVEFORMS ААААААААААААААА 30

DERATING CURVES ААААААААААААААААААААА 33

RESET ААААААААААААААААААААААААААААААААААА 33

BUS CYCLE WAVEFORMS АААААААААААААА 36

EXECUTION TIMINGS ААААААААААААААААААА 43

INSTRUCTION SET SUMMARY АААААААААА 44

REVISION HISTORY ААААААААААААААААААААА 50

ERRATA ААААААААААААААААААААААААААААААААА 50

АААААААААААААААААААААА 20

80C186EA/80C188EA, 80L186EA/80L188EA

272432– 2

NOTE:

Pin names in parentheses apply to the 80C186EA/80L188EA

Figure 1. 80C186EA/80C188EA Block Diagram

80C186EA/80C188EA, 80L186EA/80L188EA

INTRODUCTION

Unless specifically noted, all references to the 80C186EA apply to the 80C188EA, 80L186EA, and 80L188EA. References to pins that differ between the 80C186EA/80L186EA and the 80C188EA/ 80L188EA are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physically and functionally, the ‘‘C’’ and ‘‘L’’ devices are identical.

The 80C186EA is the second product in a new generation of low-power, high-integration microprocessors. It enhances the existing 80C186XL family by offering new features and operating modes. The 80C186EA is object code compatible with the 80C186XL embedded processor.

The 80L186EA is the 3V version of the 80C186EA. The 80L186EA is functionally identical to the 80C186EA embedded processor. Current 80C186EA customers can easily upgrade their designs to use the 80L186EA and benefit from the reduced power consumption inherent in 3V operation.

The feature set of the 80C186EA/80L186EA meets the needs of low-power, space-critical applications. Low-power applications benefit from the static design of the CPU core and the integrated peripherals as well as low voltage operation. Minimum current consumption is achieved by providing a Powerdown Mode that halts operation of the device, and freezes the clock circuits. Peripheral design enhancements ensure that non-initialized peripherals consume little current.

Space-critical applications benefit from the integration of commonly used system peripherals. Two flexible DMA channels perform CPU-independent data transfers. A flexible chip select unit simplifies memory and peripheral interfacing. The interrupt unit provides sources for up to 128 external interrupts and will prioritize these interrupts with those generated from the on-chip peripherals. Three general purpose timer/counters round out the feature set of the 80C186EA.

Figure 1 shows a block diagram of the 80C186EA/ 80C188EA. The Execution Unit (EU) is an enhanced 8086 CPU core that includes: dedicated hardware to speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate instructions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instructions, and static operation. The Bus Interface Unit (BIU) is the same as that found on the original 80C186 family products. An independent internal bus is used to allow communication between the BIU and internal peripherals.

80C186EA CORE ARCHITECTURE

Bus Interface Unit

The 80C186EA core incorporates a bus controller that generates local bus control signals. In addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters.

The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information and data (for write operations) information. It is also responsible for reading data off the local bus during a read operation. SRDY and ARDY input pins are provided to extend a bus cycle beyond the minimum four states (clocks).

The local bus controller also generates two control signals (DEN nal transceiver chips. This capability allows the addition of transceivers for simple buffering of the mulitplexed address/data bus.

and DT/R) when interfacing to exter-

Clock Generator

The processor provides an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divideby-two counter, and two low-power operating modes.

The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-overtone mode crystal network. Alternatively, the oscillator circuit may be driven from an external clock source. Figure 2 shows the various operating modes of the oscillator circuit.

The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and the external CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to drive other system components. All AC timings are referenced to CLKOUT.

The following parameters are recommended when choosing a crystal:

Temperature Range: Application Specific ESR (Equivalent Series Resistance): 60X max C0 (Shunt Capacitance of Crystal): 7.0 pF max C

(Load Capacitance): 20 pFg2pF

Drive Level: 2 mW max

80C186EA/80C188EA, 80L186EA/80L188EA

272432– 4

272432– 3

Figure 2. Clock Configurations

NOTE:

The L

(A) Crystal Connection

network is only required when using a third-overtone crystal.

1C1

80C186EA PERIPHERAL ARCHITECTURE

The 80C186EA has integrated several common system peripherals with a CPU core to create a compact, yet powerful system. The integrated peripherals are designed to be flexible and provide logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt requests from the timer/counters or DMA channels).

The list of integrated peripherals include:

4-Input Interrupt Control Unit

3-Channel Timer/Counter Unit

2-Channel DMA Unit

13-Output Chip-Select Unit

Refresh Control Unit

Power Management logic

The registers associated with each integrated periheral are contained within a 128 x 16 register file called the Peripheral Control Block (PCB). The PCB can be located in either memory or I/O space on any 256 byte address boundary.

Figure 3 provides a list of the registers associated with the PCB when the processor’s Interrupt Control Unit is in Master Mode. In Slave Mode, the definitions of some registers change. Figure 4 provides register definitions specific to Slave Mode.

(B) Clock Connection

Interrupt Control Unit

The 80C186EA can receive interrupts from a number of sources, both internal and external. The Interrupt Control Unit (ICU) serves to merge these requests on a priority basis, for individual service by the CPU. Each interrupt source can be independently masked by the Interrupt Control Unit or all interrupts can be globally masked by the CPU.

Internal interrupt sources include the Timers and DMA channels. External interrupt sources come from the four input pins INT3:0. The NMI interrupt pin is not controlled by the ICU and is passed directly to the CPU. Although the timers only have one request input to the ICU, separate vector types are generated to service individual interrupts within the Timer Unit.

Timer/Counter Unit

The 80C186EA Timer/Counter Unit (TCU) provides three 16-bit programmable timers. Two of these are highly flexible and are connected to external pins for control or clocking. A third timer is not connected to any external pins and can only be clocked internally. However, it can be used to clock the other two timer channels. The TCU can be used to count external events, time external events, generate non-repetitive waveforms, generate timed interrupts, etc.

80C186EA/80C188EA, 80L186EA/80L188EA

PCB

Offset

00H Reserved

02H Reserved

04H Reserved

06H Reserved

08H Reserved

0AH Reserved

0CH Reserved

0EH Reserved

10H Reserved

12H Reserved

14H Reserved

16H Reserved

18H Reserved

1AH Reserved

1CH Reserved

1EH Reserved

20H Reserved

22H End of Interrupt

24H Poll

26H Poll Status

28H Interrupt Mask

2AH Priority Mask

2CH In-Service

2EH Interrupt Request

30H Interrupt Status

32H Timer Control

34H DMA0 Int. Control

36H DMA1 Int. Control

38H INT0 Control

3AH INT1 Control

3CH INT2 Control

3EH INT3 Control

Function

PCB

Offset

40H Reserved

42H Reserved

44H Reserved

46H Reserved

48H Reserved

4AH Reserved

4CH Reserved

4EH Reserved

50H Timer 0 Count

52H Timer 0 Compare A

54H Timer 0 Compare B

56H Timer 0 Control

58H Timer 1 Count

5AH Timer 1 Compare A

5CH Timer 1 Compare B

5EH Timer 1 Control

60H Timer 2 Count

62H Timer 2 Compare

64H Reserved

66H Timer 2 Control

68H Reserved

6AH Reserved

6CH Reserved

6EH Reserved

70H Reserved

72H Reserved

74H Reserved

76H Reserved

78H Reserved

7AH Reserved

7CH Reserved

7EH Reserved

Function

PCB

Offset

80H Reserved

82H Reserved

84H Reserved

86H Reserved

88H Reserved

8AH Reserved

8CH Reserved

8EH Reserved

90H Reserved

92H Reserved

94H Reserved

96H Reserved

98H Reserved

9AH Reserved

9CH Reserved

9EH Reserved

A0H UMCS

A2H LMCS

A4H PACS

A6H MMCS

A8H MPCS

AAH Reserved

ACH Reserved

AEH Reserved

B0H Reserved

B2H Reserved

B4H Reserved

B6H Reserved

B8H Reserved

BAH Reserved

BCH Reserved

BEH Reserved

Figure 3. Peripheral Control Block Registers

Function

PCB

Offset

C0H DMA0 Src. Lo

C2H DMA0 Src. Hi

C4H DMA0 Dest. Lo

C6H DMA0 Dest. Hi

C8H DMA0 Count

CAH DMA0 Control

CCH Reserved

CEH Reserved

D0H DMA1 Src. Lo

D2H DMA1 Src. Hi

D4H DMA1 Dest. Lo

D6H DMA1 Dest. Hi

D8H DMA1 Count

DAH DMA1 Control

DCH Reserved

DEH Reserved

E0H Refresh Base

E2H Refresh Time

E4H Refresh Control

E6H Reserved

E8H Reserved

EAH Reserved

ECH Reserved

EEH Reserved

F0H Power-Save

F2H Power Control

F4H Reserved

F6H Step ID

F8H Reserved

FAH Reserved

FCH Reserved

FEH Relocation

Function

80C186EA/80C188EA, 80L186EA/80L188EA

PCB

Offset

20H Interrupt Vector

22H Specific EOI

24H Reserved

26H Reserved

28H Interrupt Mask

2AH Priority Mask

2C In-Service

2E Interrupt Request

30 Interrupt Status

32 TMR0 Interrupt Control

34 DMA0 Interrupt Control

36 DMA1 Interrupt Control

38 TMR1 Interrupt Control

3A TMR2 Interrupt Control

3C Reserved

3E Reserved

Function

Figure 4. 80C186EA Slave Mode Peripheral

Control Block Registers

DMA Control Unit

The 80C186EA DMA Contol Unit provides two independent high-speed DMA channels. Data transfers can occur between memory and I/O space in any combination: memory to memory, memory to I/O, I/O to I/O or I/O to memory. Data can be transferred either in bytes or words. Transfers may proceed to or from either even or odd addresses, but even-aligned word transfers proceed at a faster rate. Each data transfer consumes two bus cycles (a minimum of eight clocks), one cycle to fetch data and the other to store data. The chip-select/ready logic may be programmed to point to the memory or I/O space subject to DMA transfers in order to provide hardware chip select lines. DMA cycles run at higher priority than general processor execution cycles.

Chip-Select Unit

The 80C186EA Chip-Select Unit integrates logic which provides up to 13 programmable chip-selects to access both memories and peripherals. In addition, each chip-select can be programmed to automatically terminate a bus cycle independent of the condition of the SRDY and ARDY input pins. The chip-select lines are available for all memory and I/O bus cycles, whether they are generated by the CPU, the DMA unit, or the Refresh Control Unit.

Refresh Control Unit

The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks between refresh requests.

A 9-bit address generator is maintained by the RCU with the address presented on the A9:1 address lines during the refresh bus cycle. Address bits A19:13 are programmable to allow the refresh address block to be located on any 8 Kbyte boundary.

Power Management

The 80C186EA has three operational modes to control the power consumption of the device. They are Power Save Mode, Idle Mode, and Powerdown Mode.

Power Save Mode divides the processor clock by a programmable value to take advantage of the fact that current is linearly proportional to frequency. An unmasked interrupt, NMI, or reset will cause the 80C186EA to exit Power Save Mode.

Idle Mode freezes the clocks of the Execution Unit and the Bus Interface Unit at a logic zero state while all peripherals operate normally.

Powerdown Mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. All internal registers hold their values provided V maintained. Current consumption is reduced to transistor leakage only.

80C186EA/80C188EA, 80L186EA/80L188EA

80C187 Interface (80C186EA Only)

The 80C187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to include floating point and advanced integer instructions. Connecting the 80C186EA RESOUT and TEST BUSY pins to the 80C187 enables Numerics Mode operation. In Numerics Mode, three of the four MidRange Chip Select (MCS pins for the interface. The exchange of data and control information proceeds through four dedicated I/O ports.

If an 80C187 is not present, the 80C186EA configures itself for regular operation at reset.

The 80C187 is not specified for 3V operation and therefore does not interface directly to the 80L186EA.

) pins become handshaking

NOTE:

ONCE Test Mode

To facilitate testing and inspection of devices when fixed into a target system, the 80C186EA has a test mode available which forces all output and input/ output pins to be placed in the high-impedance state. ONCE stands for ‘‘ON Circuit Emulation’’. The ONCE mode is selected by forcing the UCS pins LOW (0) during a processor reset (these pins are weakly held to a HIGH (1) level) while RESIN active.

and LCS

DIFFERENCES BETWEEN THE 80C186XL AND THE 80C186EA

The 80C186EA is intended as a direct functional upgrade for 80C186XL designs. In many cases, it will be possible to replace an existing 80C186XL with little or no hardware redesign. The following sections describe differences in pinout, operating modes, and AC and DC specifications to keep in mind.

Pinout Compatibility

The 80C186EA requires a PDTMR pin to time the processor’s exit from Powerdown Mode. The original pin arrangement for the 80C186XL in the PLCC package did not have any spare leads to use for PDTMR, so the DT/R rangement of all the other leads in the 68-lead PLCC is identical between the 80C186XL and the 80C186EA. DT/R

status output. Therefore, upgrading a PLCC

the S1 80C186XL to PLCC 80C186EA is straightforward.

pin was sacrificed. The ar-

may be synthesized by latching

The 80-lead QFP (EIAJ) pinouts are different between the 80C186XL and the 80C186EA. In addition to the PDTMR pin, the 80C186EA has more power and ground pins and the overall arrangement of pins was shifted. A new circuit board layout for the 80C186EA is required.

Operating Modes

The 80C186XL has two operating modes, Compatible and Enhanced. Compatible Mode is a pin-to-pin replacement for the NMOS 80186, except for numerics coprocessing. In Enhanced Mode, the processor has a Refresh Control Unit, the Power-Save feature and an interface to the 80C187 Numerics Coprocessor. The MCS0 change their functions to constitute handshaking pins for the 80C187.

The 80C186EA allows all non-80C187 users to use all the MCS tion, all 80C186EA features (including those of the Enhanced Mode 80C186) are present except for the interface to the 80C187. Numerics Mode disables the three chip-select pins and reconfigures them for connection to the 80C187.

pins for chip-selects. In regular opera-

, MCS1, and MCS3 pins

TTL vs CMOS Inputs

The inputs of the 80C186EA are rated for CMOS

switching levels for improved noise immunity, but the 80C186XL inputs are rated for TTL switching levels. In particular, the 80C186EA requires a minimum V of 3.5V to recognize a logic one while the 80C186XL requires a minimum V operation). The solution is to drive the 80C186EA with true CMOS devices, such as those from the HC and AC logic families, or to use pullup resistors where the added current draw is not a problem.

of only 1.9V (assuming 5.0V

Timing Specifications

80C186EA timing relationships are expressed in a simplified format over the 80C186XL. The AC performance of an 80C186EA at a specified frequency will be very close to that of an 80C186XL at the same frequency. Check the timings applicable to your design prior to replacing the 80C186XL.

80C186EA/80C188EA, 80L186EA/80L188EA

PACKAGE INFORMATION

This section describes the pins, pinouts, and thermal characteristics for the 80C186EA in the Plastic Leaded Chip Carrier (PLCC) package, Shrink Quad Flat Pack (SQFP), and Quad Flat Pack (QFP) package. For complete package specifications and information, see the Intel Packaging Outlines and Dimensions Guide (Order Number: 231369).

With the extended temperature range operational characteristics are guaranteed over a temperature range corresponding to

40§Ctoa85§C ambient. Package types are identified by a two-letter prefix to the part number. The prefixes are listed in Table 1.

Table 1. Prefix Identification

Prefix Note

Package Temperature

Type Range

TN PLCC Extended

TS QFP (EIAJ) Extended

SB 1 SQFP Extended/Commercial

N 1 PLCC Commercial

S 1 QFP (EIAJ) Commercial

NOTE:

1. The 25 MHz version is only available in commercial tem-

perature range corresponding to 0

Ctoa70§C ambient.

Pin Descriptions

Each pin or logical set of pins is described in Table

3. There are three columns for each entry in the Pin Description Table.

The Pin Name column contains a mnemonic that describes the pin function. Negation of the signal name (for example, RESIN active low.

) denotes a signal that is

input/output (I/O). Some pins have multiplexed functions (for example, A19/S6). Additional symbols indicate additional characteristics for each pin. Table 3 lists all the possible symbols for this column.

The Input Type column indicates the type of input (asynchronous or synchronous).

Asynchronous pins require that setup and hold times be met only in order to guarantee

recognition

at a particular clock edge. Synchronous pins require that setup and hold times be met to guarantee proper

operation.

For example, missing the setup or hold time for the SRDY pin (a synchronous input) will result in a system failure or lockup. Input pins may also be edge- or level-sensitive. The possible characteristics for input pins are S(E), S(L), A(E) and A(L).

The Output States column indicates the output state as a function of the device operating mode. Output states are dependent upon the current activity of the processor. There are four operational states that are different from regular operation: bus hold, reset, Idle Mode and Powerdown Mode. Appropriate characteristics for these states are also indicated in this column, with the legend for all possible characteristics in Table 2.

The Pin Description column contains a text description of each pin.

As an example, consider AD15:0. I/O signifies the pins are bidirectional. S(L) signifies that the input function is synchronous and level-sensitive. H(Z) signifies that, as outputs, the pins are high-impedance upon acknowledgement of bus hold. R(Z) signifies that the pins float during reset. P(X) signifies that the pins retain their states during Powerdown Mode.

The Pin Type column contains two kinds of information. The first symbol indicates whether a pin is power (P), ground (G), input only (I), output only (O) or

80C186EA/80C188EA, 80L186EA/80L188EA

Table 2. Pin Description Nomenclature

Symbol Description

P Power Pin (ApplyaVCCVoltage) G Ground (Connect to V I Input Only Pin O Output Only Pin I/O Input/Output Pin

S(E) Synchronous, Edge Sensitive S(L) Synchronous, Level Sensitive A(E) Asynchronous, Edge Sensitive A(L) Asynchronous, Level Sensitive

H(1) Output Driven to VCCduring Bus Hold H(0) Output Driven to V H(Z) Output Floats during Bus Hold H(Q) Output Remains Active during Bus Hold H(X) Output Retains Current State during Bus Hold

R(WH) Output Weakly Held at VCCduring Reset R(1) Output Driven to V R(0) Output Driven to V R(Z) Output Floats during Reset R(Q) Output Remains Active during Reset R(X) Output Retains Current State during Reset

I(1) Output Driven to VCCduring Idle Mode I(0) Output Driven to V I(Z) Output Floats during Idle Mode I(Q) Output Remains Active during Idle Mode I(X) Output Retains Current State during Idle Mode

P(1) Output Driven to VCCduring Powerdown Mode P(0) Output Driven to V P(Z) Output Floats during Powerdown Mode P(Q) Output Remains Active during Powerdown Mode P(X) Output Retains Current State during Powerdown Mode

)

during Bus Hold

during Reset

during Idle Mode

during Powerdown Mode

80C186EA/80C188EA, 80L186EA/80L188EA

Table 3. Pin Descriptions

Pin Pin Input Output

Name Type Type States

P POWER connections consist of six pins which must be shorted

externally to a V

G GROUND connections consist of five pins which must be shorted

externally to a V

CLKIN I A(E) CLocK INput is an input for an external clock. An external

oscillator operating at two times the required processor operating frequency can be connected to CLKIN. For crystal operation, CLKIN (along with OSCOUT) are the crystal connections to an internal Pierce oscillator.

OSCOUT O H(Q) OSCillator OUTput is only used when using a crystal to generate

R(Q) P(Q)

the external clock. OSCOUT (along with CLKIN) are the crystal connections to an internal Pierce oscillator. This pin is not to be used as 2X clock output for non-crystal applications (i.e., this pin is N.C. for non-crystal applications). OSCOUT does not float in ONCE mode.

CLKOUT O H(Q) CLocK OUTput provides a timing reference for inputs and outputs

R(Q) P(Q)

of the processor, and is one-half the input clock (CLKIN) frequency. CLKOUT has a 50% duty cycle and transistions every falling edge of CLKIN.

RESIN I A(L) RESet IN causes the processor to immediately terminate any bus

cycle in progress and assume an initialized state. All pins will be driven to a known state, and RESOUT will also be driven active. The rising edge (low-to-high) transition synchronizes CLKOUT with CLKIN before the processor begins fetching opcodes at memory location 0FFFF0H.

RESOUT O H(0) RESet OUTput that indicates the processor is currently in the

reset state. RESOUT will remain active as long as RESIN remains

R(1)

active. When tied to the TEST

P(0)

80C186EA into Numerics Mode.

PDTMR I/O A(L) H(WH) Power-Down TiMeR pin (normally connected to an external

R(Z)

capacitor) that determines the amount of time the processor waits after an exit from power down before resuming normal operation.

P(1)

The duration of time required will depend on the startup characteristics of the crystal oscillator.

NMI I A(E) Non-Maskable Interrupt input causes a Type 2 interrupt to be

serviced by the CPU. NMI is latched internally.

Description

board plane.

/BUSY pin, RESOUT forces the

TEST/BUSY I A(E) TEST/BUSY is sampled upon reset to determine whether the (TEST

)

80C186EA is to enter Numerics Mode. In regular operation, the pin

. TEST is used during the execution of the WAIT

is TEST instruction to suspend CPU operation until the pin is sampled active (low). In Numerics Mode, the pin is BUSY. BUSY notifies the 80C186EA of 80C187 Numerics Coprocessor activity.

AD15:0 I/O S(L) H(Z) These pins provide a multiplexed Address and Data bus. During (AD7:0) R(Z)

the address phase of the bus cycle, address bits 0 through 15 (0 through 7 on the 8-bit bus versions) are presented on the bus and

P(X)

can be latched using ALE. 8- or 16-bit data information is transferred during the data phase of the bus cycle.

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

80C186EA/80C188EA, 80L186EA/80L188EA

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

A18:16 O H(Z) These pins provide multiplexed Address during the address A19/S6–A16 R(Z) (A19–A8) P(X)

phase of the bus cycle. Address bits 16 through 19 are presented on these pins and can be latched using ALE. A18:16 are driven to a logic 0 during the data phase of the bus cycle. On the 8-bit bus versions, A15 – A8 provide valid address information for the entire bus cycle. Also during the data phase, S6 is driven to a logic 0 to indicate a CPU-initiated bus cycle or logic 1 to indicate a DMA-initiated bus cycle or a refresh cycle.

S2:0 O H(Z) Bus cycle Status are encoded on these pins to provide bus

R(Z) P(1)

transaction information. S2:0

S2 S1 S0 Bus Cycle Initiated

0 0 0 Interrupt Acknowledge 0 0 1 Read I/O 0 1 0 Write I/O 0 1 1 Processor HALT 1 0 0 Queue Instruction Fetch 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive (no bus activity)

ALE/QS0 O H(0) Address Latch Enable output is used to strobe address

R(0) P(0)

information into a transparent type latch during the address phase of the bus cycle. In Queue Status Mode, QS0 provides queue status information along with QS1.

BHE O H(Z) Byte High Enable output to indicate that the bus cycle in

) R(Z)

(RFSH

P(X)

progress is transferring data over the upper half of the data bus. BHE and A0 have the following logical encoding:

A0 BHE Encoding (For 80C186EA/80L186EA Only)

0 0 Word Transfer 0 1 Even Byte Transfer 1 0 Odd Byte Transfer 1 1 Refresh Operation

On the 80C188EA/80L188EA, RFSH is asserted low to indicate a Refresh bus cycle.

RD/QSMD O H(Z) ReaD output signals that the accessed memory or I/O device

R(WH)

P(1)

must drive data information onto the data bus. Upon reset, this pin has an alternate function. As QSMD Status Mode when grounded. In Queue Status Mode, the ALE/QS0 and WR/QS1 pins provide the following information about processor/instruction queue interaction:

QS1 QS0 Queue Operation

0 0 No Queue Operation 0 1 First Opcode Byte Fetched from the Queue 1 1 Subsequent Byte Fetched from the Queue 1 0 Empty the Queue

Description

are encoded as follows:

, it enables Queue

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

80C186EA/80C188EA, 80L186EA/80L188EA

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

WR/QS1 O H(Z) WRite output signals that data available on the data bus are to be

R(Z)

written into the accessed memory or I/O device. In Queue Status Mode, QS1 provides queue status information along with QS0.

P(1)

ARDY I A(L) Asychronous ReaDY is an input to signal for the end of a bus cycle.

S(L)

ARDY is asynchronous on rising CLKOUT and synchronous on falling CLKOUT. ARDY or SRDY must be active to terminate any processor bus cycle, unless they are ignored due to correct programming of the Chip Select Unit.

SRDY I S(L) Synchronous ReaDY is an input to signal for the end of a bus cycle.

ARDY or SRDY must be active to terminate any processor bus cycle, unless they are ignored due to correct programming of the Chip Select Unit.

DEN O H(Z) Data ENable output to control the enable of bidirectional transceivers

R(Z) P(1)

when buffering a system. DEN transferred on the bus.

DT/R O H(Z) Data Transmit/Receive output controls the direction of a bi-

R(Z)

directional buffer in a buffered system. DT/R QFP (EIAJ) package and the SQFP package.

P(X)

LOCK O H(Z) LOCK output indicates that the bus cycle in progress is not to be

R(WH)

interrupted. The processor will not service other bus requests (such as HOLD) while LOCK

P(1)

held high input while RESIN

HOLD I A(L) HOLD request input to signal that an external bus master wishes to

gain control of the local bus. The processor will relinquish control of the local bus between instruction boundaries not conditioned by a LOCK prefix.

HLDA O H(1) HoLD Acknowledge output to indicate that the processor has

relinquished control of the local bus. When HLDA is asserted, the

R(0)

processor will (or has) floated its data bus and control signals allowing

P(0)

another bus master to drive the signals directly.

UCS O H(1) Upper Chip Select will go active whenever the address of a memory

or I/O bus cycle is within the address limitations programmed by the

R(1)

user. After reset, UCS is configured to be active for memory accesses

P(1)

between 0FFC00H and 0FFFFFH. During a processor reset, UCS

are used to enable ONCE Mode.

LCS

LCS O H(1) Lower Chip Select will go active whenever the address of a memory

bus cycle is within the address limitations programmed by the user.

R(1)

LCS

P(1)

is inactive after a reset. During a processor reset, UCS and LCS

are used to enable ONCE Mode.

Description

is active only when data is to be

is only available on the

is active. This pin is configured as a weakly

is active and must not be driven low.

and

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

80C186EA/80C188EA, 80L186EA/80L188EA

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

MCS0/PEREQ I/O A(L) H(1) These pins provide a multiplexed function. If enabled,

/ERROR R(1)

MCS1 MCS2 MCS3

/NCS

P(1)

these pins normally comprise a block of Mid-Range Chip Select outputs which will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user. In Numerics Mode (80C186EA only), three of the pins become handshaking pins for the 80C187. The CoProcessor REQuest input signals that a data transfer is pending. ERROR indicates that the previous numerics coprocessor operation resulted in an exception condition. An interrupt Type 16 is generated when ERROR the beginning of a numerics operation. Numerics Coprocessor Select is an output signal generated when the processor accesses the 80C187.

PCS4:0 O H(1) Peripheral Chip Selects go active whenever the address

R(1) P(1)

of a memory or I/O bus cycle is within the address limitations programmed by the user.

PCS5/A1 O H(1)/H(X) These pins provide a multiplexed function. As additional PCS6

/A2 R(1)

P(1)

Peripheral Chip Selects, they go active whenever the address of a memory or I/O bus cycle is within the address limitations by the user. They may also be programmed to provide latched Address A2:1 signals.

T0OUT O H(Q) Timer OUTput pins can be programmed to provide a T1OUT R(1)

P(Q)

single clock or continuous waveform generation, depending on the timer mode selected.

T0IN I A(L) Timer INput is used either as clock or control signals, T1IN A(E)

depending on the timer mode selected.

DRQ0 I A(L) DMA ReQuest is asserted by an external request when it DRQ1

is prepared for a DMA transfer.

INT0 I A(E,L) Maskable INTerrupt input will cause a vector to a specific INT1/SELECT

Type interrupt routine. To allow interrupt expansion, INT0 and/or INT1 can be used with INTA0 and INTA1 to interface with an external slave controller. INT1 becomes SELECT

when the ICU is configured for Slave Mode.

INT2/INTA0 I/O A(E,L) H(1) These pins provide multiplexed functions. As inputs, they INT3/INTA1

/IRQ R(Z)

P(1)

provide a maskable INTerrupt that will cause the CPU to vector to a specific Type interrupt routine. As outputs, each is programmatically controlled to provide an INTerrupt Acknowledge handshake signal to allow interrupt expansion. INT3/INTA1 ICU is configured for Slave Mode.

N.C. No Connect. For compatibility with future products, do not

connect to these pins.

Description

is an input which

is sampled active at

becomes IRQ when the

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

80C186EA/80C188EA, 80L186EA/80L188EA

80C186EA PINOUT

Tables 4 and 5 list the 80C186EA pin names with package location for the 68-pin Plastic Leaded Chip Carrier (PLCC) component. Figure 9 depicts the complete 80C186EA/80L186EA pinout (PLCC package) as viewed from the top side of the component (i.e., contacts facing down).

Tables 6 and 7 list the 80C186EA pin names with package location for the 80-pin Quad Flat Pack (EIAJ) component. Figure 6 depicts the complete

Table 4. PLCC Pin Names with Package Location

Address/Data Bus

Name Location

AD0 17 AD1 15 AD2 13 AD3 11 AD4 8 AD5 6 AD6 4 AD7 2 AD8 (A8) 16 AD9 (A9) 14 AD10 (A10) 12 AD11 (A11) 10 AD12 (A12) 7 AD13 (A13) 5 AD14 (A14) 3 AD15 (A15) 1

A16 68 A17 67 A18 66 A19/S6 65

Bus Control

Name Location

ALE/QS0 61 BHE

(RFSH)64

S0 S1 S2 54

RD/QSMD 62 WR

/QS1 63

ARDY 55 SRDY 49

DEN LOCK 48

HOLD 50 HLDA 51

Power

Name Location

26, 60

9, 43

52 53

80C186EA/80C188EA (EIAJ QFP package) as viewed from the top side of the component (i.e., contacts facing down).

Tables 8 and 9 list the 80C186EA/80C188EA pin names with package location for the 80-pin Shrink Quad Flat Pack (SQFP) component. Figure 7 depicts the complete 80C186EA/80C188EA (SQFP) as viewed from the top side of the component (i.e., contacts facing down).

Processor Control

Name Location

RESIN 24 RESOUT 57

CLKIN 59 OSCOUT 58 CLKOUT 56

TEST/BUSY 47

PDTMR 40

NMI 46 INT0 45 INT1/SELECT 44 INT2/INTA0 42 INT3/INTA1 IRQ

/41

UCS 34 LCS MCS0 MCS1 MCS2 36 MCS3/NCS 35

PCS0 PCS1 PCS2 PCS3 PCS4 PCS5/A1 31 PCS6/A2 32

T0OUT 22 T0IN 20 T1OUT 23 T1IN 21

DRQ0 18 DRQ1 19

I/O

Name Location

33 /PEREQ 38 /ERROR 37

NOTE:

Pin names in parentheses apply to the 80C188EA/80L188EA.

80C186EA/80C188EA, 80L186EA/80L188EA

Table 5. PLCC Package Location with Pin Names

Location Name

1 AD15 (A15) 2 AD7 3 AD14 (A14) 4 AD6 5 AD13 (A13) 6 AD5 7 AD12 (A12) 8 AD4 9V

10 AD11 (A11) 11 AD3 12 AD10 (A10) 13 AD2 14 AD9 (A9) 15 AD1 16 AD8 (A8) 17 AD0

NOTE:

Pin names in parentheses apply to the 80C186EA/80L188EA.

Location Name

18 DRQ0 19 DRQ1 20 T0IN 21 T1IN 22 T0OUT 23 T1OUT 24 RESIN 25 PCS0 26 V

27 PCS1 28 PCS2 29 PCS3 30 PCS4 31 PCS5/A1 32 PCS6 33 LCS 34 UCS

/A2

Location Name

35 MCS3/NCS 36 MCS2 37 MCS1/ERROR 38 MCS0/PEREQ 39 DEN 40 PDTMR 41 INT3/INTA1

IRQ 42 INT2/INTA0 43 V

44 INT1/SELECT 45 INT0 46 NMI 47 TEST

/BUSY 48 LOCK 49 SRDY 50 HOLD 51 HLDA

Location Name

52 S0 53 S1 54 S2 55 ARDY 56 CLKOUT 57 RESOUT

58 OSCOUT 59 CLKIN 60 V 61 ALE/QS0 62 RD 63 WR/QS1 64 BHE (RFSH) 65 A19/S6 66 A18 67 A17 68 A16

/QSMD

NOTES: 272432– 5

1. The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number.

2. Pin names in parentheses apply to the 80C186EA/80L188EA.

Figure 5. 68-Lead PLCC Pinout Diagram

80C186EA/80C188EA, 80L186EA/80L188EA

Table 6. QFP (EIAJ) Pin Names with Package Location

Address/Data Bus Bus Control Processor Control I/O

Name Location Name Location Name Location Name Location

AD0 64 ALE/QS0 10 RESIN 55 UCS 45 AD1 66 BHE AD2 68 S0 AD3 70 S1 AD4 74 S2 21 CLKOUT 19 MCS2 42 AD5 76 RD/QSMD 9 TEST/BUSY 29 MCS3/NCS 43 AD6 78 WR AD7 80 ARDY 20 NMI 30 PCS1 AD8 (A8) 65 SRDY 27 INT0 31 PCS2 AD9 (A9) 67 DT/R AD10 (A10) 69 DEN AD11 (A11) 71 LOCK 28 INT3/INTA1/ 36 PCS5/A1 48 AD12 (A12) 75 HOLD 26 IRQ PCS6/A2 47 AD13 (A13) 77 HLDA 25 N.C. 11, 14, T0OUT 57 AD14 (A14) 79 15, 63 T0IN 59 AD15 (A15) 1 T1OUT 56 A16 3 A17 4 A18 5 A19/S6 6

(RFSH) 7 RESOUT 18 LCS 46

23 CLKIN 16 MCS0/PEREQ 40 22 OSCOUT 17 MCS1/ERROR 41

/QS1 8 PDTMR 38 PCS0 54

37 INT1/SELECT 32 PCS3 50 39 INT2/INTA0 35 PCS4 49

Power

Name Location

12, 13, 24,

T1IN 58 DRQ0 61 DRQ1 60

53,62

2, 33, 34,

44, 72, 73

52 51

NOTE:

Pin names in parentheses apply to the 80C186EA/80L188EA.

80C186EA/80C188EA, 80L186EA/80L188EA

Table 7. QFP (EIAJ) Package Location with Pin Names

Location Name Location Name Location Name Location Name

1 AD15 (A15) 21 S2 41 MCS1/ERROR 61 DRQ0 2V

3 A16 23 S0 43 MCS3/NCS 63 N.C. 4 A17 24 V 5 A18 25 HLDA 45 UCS 6 A19/S6 26 HOLD 46 LCS 66 AD1 7 BHE 8WR 9RD

(RFSH) 27 SRDY 47 PCS6/A2 67 AD9 (A9)

/QS1 28 LOCK 48 PCS5/A1 68 AD2

/QSMD 29 TEST/BUSY 49 PCS4 69 AD10 (A10) 10 ALE/QS0 30 NMI 50 PCS3 11 N.C. 31 INT0 51 PCS2 12 V 13 V

14 N.C. 34 V 15 N.C. 35 INT2/INTA0 16 CLKIN 36 INT3/INTA1 17 OSCOUT IRQ 57 T0OUT 77 AD13 (A13) 18 RESOUT 37 DT/R 19 CLKOUT 38 PDTMR 59 T0IN 79 AD14 (A14) 20 ARDY 39 DEN

NOTE:

Pin names in parentheses apply to the 80C186EA/80L188EA.

22 S1 42 MCS2 62 V

44 V

64 AD0 65 AD8 (A8)

70 AD3

71 AD11 (A11) 32 INT1/SELECT 52 PCS1 72 V 33 V

53 V

73 V

54 PCS0 74 AD4 55 RESIN 75 AD12 (A12)

/ 56 T1OUT 76 AD5

58 T1IN 78 AD6

60 DRQ1 80 AD7

40 MCS0/PEREQ

NOTES: 272432– 6

1. The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number.

2. Pin names in parentheses apply to the 80C186EA/80L188EA.

Figure 6. Quad Flat Pack (EIAJ) Pinout Diagram

Table 8. SQFP Pin Functions with Package Location

AD Bus

AD0 1 AD1 3 AD2 6 AD3 8 AD4 12 AD5 14 AD6 16 AD7 18 AD8 (A8) 2 AD9 (A9) 5 AD10 (A10) 7 AD11 (A11) 9 AD12 (A12) 13 AD13 (A13) 15 AD14 (A14) 17 AD15 (A15) 19 A16/S3 21 A17/S4 22 A18/S5 23 A19/S6 24

NOTE:

Pin names in parentheses apply to the 80C186EA/80L188EA.

Bus Control

ALE/QS0 29

/(RFSH)26

BHE S0 S1 S2

/QSMD 28

RD WR/QS1 27 ARDY 37 SRDY 44 DEN DT/R LOCK HOLD 43 HLDA 42

No Connection

N.C. 4 N.C. 25 N.C. 35 N.C. 72

40 39 38

56 54 45

80C186EA/80C188EA, 80L186EA/80L188EA

Processor Control

RESIN 73 RESOUT 34 CLKIN 32 OSCOUT 33 CLKOUT 36

/BUSY 46

TEST NMI 47 INT0 48 INT1/SELECT INT2/INTA0 INT3/INTA1 PDTMR 55

Power and Ground

10 11 20 50 51 61 30 31 41 70 80

49 52 53

UCS 62 LCS

MCS0 MCS1 MCS2 MCS3/NPS 60

PCS0 71 PCS1 PCS2 PCS3 PCS4 PCS5/A1 65 PCS6

TMR IN 0 77 TMR IN 1 76 TMR OUT 0 75 TMR OUT 1 74

DRQ0 79 DRQ1 78

I/O

/PEREQ 57 /ERROR 58

69 68 67 66

/A2 64

Table 9. SQFP Pin Locations with Pin Names

1 AD0 2 AD8 (A8) 3 AD1 4 N.C. 5 AD9 (A9) 6 AD2 7 AD10 (A10) 8 AD3

9 AD11 (A11) 10 V 11 V 12 AD4 13 AD12 (A12) 14 AD5 15 AD13 (A13) 16 AD6 17 AD14 (A14) 18 AD7 19 AD15 (A15) 20 V

NOTE:

Pin names in parentheses apply to the 80C186EA/80L188EA.

21 A16/S3 22 A17/S4 23 A18/S5 24 A19/S6 25 N.C. 26 BHE 27 WR 28 RD/QSMD 29 ALE/QS0 30 V 31 V 32 X1 33 X2 34 RESET 35 N.C. 36 CLKOUT 37 ARDY 38 S2 39 S1 40 S0

/(RFSH)

/QS1

41 V

42 HLDA 43 HOLD 44 SRDY 45 LOCK 46 TEST/BUSY 47 NMI 48 INT0 49 INT1/SELECT 50 V

51 V

52 INT2/INTA0 53 INT3/INTA1 54 DT/R 55 PDTMR 56 DEN 57 MCS0/PEREQ 58 MCS1

/ERROR 59 MCS2 60 MCS3/NPS

61 V 62 UCS

63 LCS 64 PCS6/A2 65 PCS5

/A1 66 PCS4 67 PCS3 68 PCS2 69 PCS1 70 V 71 PCS0

72 N.C. 73 RES 74 TMR OUT 1 75 TMR OUT 0 76 TMR IN 1 77 TMR IN 0 78 DRQ1 79 DRQ0 80 V

80C186EA/80C188EA, 80L186EA/80L188EA

Figure 7. Shrink Quad Flat Pack (SQFP) Pinout Diagram

NOTES:

1. XXXXXXXXD indicates the Intel FPO number.

2. Pin names in parentheses apply to the 80C188EA.

PACKAGE THERMAL SPECIFICATIONS

The 80C186EA/80L186EA is specified for operation when T of 0 (QFP-EIAJ) package. T environment to determine whether the processor is within the specified operating range. The case temperature must be measured at the center of the top surface.

(the case temperature) is within the range

Cto85§C (PLCC package) or 0§Cto106§C

may be measured in any

Table 10. Thermal Resistance (i

Airflow Linear ft/min (m/sec)

0 200 400 600 800 1000

(0) (1.01) (2.03) (3.04) (4.06) (5.07)

iCA(PLCC) 29 25 21 19 17 16.5

iCA(QFP) 66 63 60.5 59 58 57

iCA(SQFP) 70

272432– 7

(the ambient temperature) can be calculated

from i ent) with the following equation:

(thermal resistance from the case to ambi-

TC-Pci

Typical values for iCAat various airflows are given in Table 10.

P (the maximum power consumption, specified in watts) is calculated by using the maximum ICC as tabulated in the DC specifications and V

) at Various Airflows (in§C/Watt)

of 5.5V.

80C186EA/80C188EA, 80L186EA/80L188EA

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings*

Storage Temperature ААААААААААb65§Ctoa150§C

Case Temperature under Bias ÀÀÀb65§Ctoa150§C

Supply Voltage with Respect

to V

АААААААААААААААААААААААb0.5V toa6.5V

Voltage on Other Pins with Respect

ААААААААААААААААААb0.5V to V

to V

0.5V

Recommended Connections

Power and ground connections must be made to multiple V circuit board should contain separate power (V and ground (V be connected to the appropriate plane. Pins identified as ‘‘N.C.’’ must not be connected in the system. Decoupling capacitors should be placed near the processor. The value and type of decoupling capac-

and VSSpins. Every 80C186EA based

) planes. All VCCand VSSpins must

NOTICE: This data sheet contains preliminary information on new products in production. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability.

itors is application and board layout dependent. The processor can cause transient power surges when its output buffers transition, particularly when connected to large capacitive loads.

)

Always connect any unused input pins to an appropriate signal level. In particular, unused interrupt pins (NMI, INT3:0) should be connected to V unwanted interrupts. Leave any unused output pin

or any ‘‘N.C.’’ pin unconnected.

to avoid

80C186EA/80C188EA, 80L186EA/80L188EA

DC SPECIFICATIONS (80C186EA/80C188EA)

Symbol Parameter Min Max Units Conditions

HYR

IL1

IL2

OUT

NOTES:

1. RD vated during RESET. Loading these pins above I operation.

2. Output pins are floated using HOLD or ONCE Mode.

3. Measured at worst case temperature and V device in RESET (RESIN

4. Output capacitance is the capacitive load of a floating output pin.

5. Operating conditions for 25 MHz are 0

Supply Voltage 4.5 5.5 V

Input Low Voltage for All Pins

Input High Voltage for All Pins 0.7 V

Output Low Voltage 0.45 V I

Output High Voltage V

0.5 0.3 V

CCVCC

0.5 V I

0.5 V

3 mA (min)

2 mA (min)

Input Hysterisis on RESIN 0.30 V

Input Leakage Current (except

10 mA0VsV

RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1

/ERROR, LOCK and TEST/BUSY)

Input Leakage Current

275 mAV

0.7 V

(RD/QSMD, UCS, LCS, MCS0/PEREQ, (Note 1) MCS1

, ERROR, LOCK and TEST/BUSY

Output Leakage Current

10 mA

0.45 (Note 2)

OUT

Supply Current Cold (RESET)

80C186EA25/80C188EA25 105 mA (Notes 3, 5) 80C186EA20/80C188EA20 90 mA 80C186EA13/80C188EA13 65 mA

Supply Current In Idle Mode

80C186EA25/80C188EA25 90 mA (Note 5) 80C186EA20/80C188EA20 70 mA 80C186EA13/80C188EA13 46 mA

Supply Current In Powerdown Mode

80C186EA25/80C188EA25 100 mA (Note 5) 80C186EA20/80C188EA20 100 mA 80C186EA13/80C188EA13 100 mA

Output Pin Capacitance 0 15 pF T

Input Pin Capacitance 0 15 pF T

/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR, LOCK and TEST/BUSY have internal pullups that are only acti-

held low). RESET is worst case for ICC.

Ctoa70§C, V

275 mA will cause the processor to enter alternate modes of

with all outputs loaded as specified in the AC Test Conditions, and with the

5.0Vg10%.

1 MHz (Note 4)

1 MHz

80C186EA/80C188EA, 80L186EA/80L188EA

DC SPECIFICATIONS (80L186EA/80L188EA)

Symbol Parameter Min Max Units Conditions

HYR

IL1

IL2

CC5

CC3

ID5

PD5

PD3

OUT

NOTES:

1. RD Loading these pins above I

2. Output pins are floated using HOLD or ONCE Mode.

3. Measured at worst case temperature and V device in RESET (RESIN

4. Output capacitance is the capacitive load of a floating output pin.

Supply Voltage 2.7 5.5 V

Input Low Voltage for All Pins

Input High Voltage for All Pins 0.7 V

Output Low Voltage 0.45 V I

Output High Voltage V

0.5 0.3 V

CCVCC

0.5 V I

0.5 V

1.6 mA (min)

1 mA (min)

Input Hysterisis on RESIN 0.30 V

Input Leakage Current (except

10 mA0VsV

RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1

, LOCK and TEST)

Input Leakage Current

275 mAV

0.7 V

(RD/QSMD, UCS, LCS, MCS0, (Note 1) MCS1

, LOCK and TEST)

Output Leakage Current

10 mA

0.45 (Note 2)

OUT

Supply Current (RESET, 5.5V)

80L186EA-13 65 mA (Note 3) 80L186EA-8 40 mA (Note 3)

Supply Current (RESET, 2.7V)

80L186EA-13 34 mA (Note 3) 80L186EA-8 20 mA (Note 3)

Supply Current Idle (5.5V)

80L186EA-13 46 mA 80L186EA-8 28 mA

Supply Current Idle (2.7V)

80L186EA-13 24 mA 80L186EA-8 14 mA

Supply Current Powerdown (5.5V)

80L186EA-13 100 mA 80L186EA-8 100 mA

Supply Current Powerdown (2.7V)

80L186EA-13 50 mA 80L186EA-8 50 mA

Output Pin Capacitance 0 15 pF T

Input Pin Capacitance 0 15 pF T

/QSMD, UCS, LCS, MCS0, MCS1, LOCK and TEST have internal pullups that are only activated during RESET.

held low).

275 mA will cause the processor to enter alternate modes of operation.

with all outputs loaded as specified in the AC Test Conditions, and with the

1 MHz (Note 4)

1 MHz

80C186EA/80C188EA, 80L186EA/80L188EA

ICCVERSUS FREQUENCY AND VOLTAGE

The current (ICC) consumption of the processor is essentially composed of two components; I I

CCS

is the quiescent current that represents internal

device leakage, and is measured with all inputs or floating outputs at GND or V the device). I and is typically less than 50 mA.

is the switching current used to charge and

CCS

discharge parasitic device capacitance when changing logic levels. Since I than I

PD,IPD

is related to the voltage and frequency at which

CCS

the device is operating. It is given by the formula:

is equal to the Powerdown current

VcIeV

CCS

can often be ignored when calculating

Power

... IeI

(no clock applied to

is typically much greater

DEV

VcC

CCS

DEV

and

Where: VeDevice operating voltage (VCC)

Device capacitance

DEV

feDevice operating frequency

CCS

Measuring C would be difficult. Instead, C the above formula by measuring I and frequency (see Table 11). Using this C ue, I

can be calculated at any voltage and fre-

quency within the specified operating range.

EXAMPLE: Calculate the typical I at 20 MHz, 4.8V.

CCS

Device current

on a device like the 80C186EA

DEV

4.8c0.515c20&49 mA

is calculated using

DEV

at a known V

when operating

DEV

val-

PDTMR PIN DELAY CALCULATION

The PDTMR pin provides a delay between the assertion of NMI and the enabling of the internal clocks when exiting Powerdown. A delay is required only when using the on-chip oscillator to allow the crystal or resonator circuit time to stabilize.

NOTE:

The PDTMR pin function does not apply when

is asserted (i.e., a device reset during Pow-

RESIN erdown is similar to a cold reset and RESIN

must remain active until after the oscillator has stabilized).

To calculate the value of capacitor required to provide a desired delay, use the equation:

440

teCPD(5V, 25§C)

Where: t

EXAMPLE: To get a delay of 300 ms, a capacitor value of C required. Round up to standard (available) capaci-

desired delay in seconds

capacitive load on PDTMR in mi-

crofarads

440c(300c10

)e0.132 mFis

tive values.

NOTE:

The above equation applies to delay times greater than 10 ms and will compute the TYPICAL capacitance needed to achieve the desired delay. A delay variance of

50% orb25% can occur due to temperature, voltage, and device process extremes. In general, higher V perature will decrease delay time, while lower V and/or higher temperature will increase delay time.

and/or lower tem-

Table 11. C

DEV

Values

Parameter Typ Max Units Notes

(Device in Reset) 0.515 0.905 mA/V*MHz 1, 2

DEV

(Device in Idle) 0.391 0.635 mA/V*MHz 1, 2

DEV

1. Max C outputs loaded to 50 pF (including CLKOUT and OSCOUT).

2. Typical C OSCOUT, which are not loaded.

is calculated atb40§C, all floating outputs driven to VCCor GND, and all

DEV

is calculated at 25§C with all outputs loaded to 50 pF except CLKOUT and

DEV

80C186EA/80C188EA, 80L186EA/80L188EA

AC SPECIFICATIONS

AC CharacteristicsÐ80C186EA25/80C186EA20/80C186EA13

Symbol Parameter Min Max Min Max Min Max Units Notes

INPUT CLOCK 25 MHz

T T T T T T

CLKIN Frequency 0 50 0 40 0 26 MHz 1

CLKIN Period 20

CLKIN High Time 10

CLKIN Low Time 10

CLKIN Rise Time 1 8 1 8 1 8 ns 1, 3

CLKIN Fall Time 1 8 1 8 1 8 ns 1, 3

OUTPUT CLOCK

T T CLKOUT Period 2T T T TPRCLKOUT Rise Time 1 6 1 6 1 6 ns 1, 5 T

CLKIN to CLKOUT Delay 0 15 0 17 0 23 ns 1, 4

CLKOUT High Time (T/2)b5 (T/2)b5 (T/2)b5ns1

CLKOUT Low Time (T/2)b5 (T/2)b5 (T/2)b5ns1

CLKOUT Fall Time 1 6 1 6 1 6 ns 1, 5

OUTPUT DELAYS

ALE, S2:0, DEN, DT/R, 3 20 3 22 3 25 ns 1, 4, 6, 7

CHOV1

CHOV2

CLOV1

, (RFSH), LOCK, A19:16

BHE

MCS3:0, LCS, UCS, PCS6:0, 3 25 3 27 3 30 ns 1, 4, 6, 8 NCS,RD,WR

BHE (RFSH), DEN, LOCK, 3 20 3 22 3 25 ns 1, 4, 6 RESOUT, HLDA, T0OUT, T1OUT, A19:16

RD,WR, MCS3:0, LCS, 3 25 3 27 3 30 ns 1, 4, 6

CLOV2

, PCS6:0, AD15:0

UCS (A15:8, AD7:0), NCS, INTA1:0, S2:0

RD,WR, BHE (RFSH), DT/R, 0 25 0 25 0 25 ns 1

CHOF

LOCK

DEN, AD15:0 (A15:8, AD7:0) 0 25 0 25 0 25 ns 1

CLOF

, S2:0

, A19:16

(12)

20 MHz 13 MHz

% % %

25 10 10

% % %

2*T

38.5 12 12

ns 1

ns 1, 2

2*TCns 1

80C186EA/80C188EA, 80L186EA/80L188EA

AC SPECIFICATIONS (Continued)

AC CharacteristicsÐ80C186EA25/80C186EA20/80C186EA13

Symbol Parameter Min Max Min Max Min Max Units Notes

SYNCHRONOUS INPUTS 25 MHz

CHIS

CHIH

CLIS

CLIH

CLIS

CLIH

CLIS

CLIH

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measured at V

3. Only required to guarantee I

4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.

6. See Figure 14 for rise and fall times.

7. T

CHOV1

8. T

CHOV2

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

11. T

CHOVS

12. Operating conditions for 25 MHz are 0 Pin names in parentheses apply to the 80C188EA/80L188EA.

TEST, NMI, INT3:0, 8 10 10 ns 1, 9 T1:0IN, ARDY

TEST, NMI, INT3:0, 3 3 3 ns 1, 9 T1:0IN, ARDY

AD15:0 (AD7:0), ARDY, 10 10 10 ns 1, 10 SRDY, DRQ1:0

AD15:0 (AD7:0), ARDY, 3 3 3 ns 1, 10 SRDY, DRQ1:0

HOLD, PEREQ, ERROR 10 10 10 ns 1, 9 (80C186EA Only)

HOLD, PEREQ, ERROR 333 ns1,9 (80C186EA Only)

RESIN (to CLKIN) 10 10 10 ns 1, 9

RESIN (from CLKIN) 3 3 3 ns 1, 9

for high time, VILfor low time.

applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. applies to RD and WR only after a HOLD release.

applies to BHE (RFSH) and A19:16 only after a HOLD release.

. Maximum limits are bounded by TC,TCHand TCL.

Ctoa70§C, V

(12)

20 MHz 13 MHz

5.0Vg10%.

80C186EA/80C188EA, 80L186EA/80L188EA

AC SPECIFICATIONS

AC CharacteristicsÐ80L186EA13/80L186EA8

Symbol Parameter Min Max Min Max Units Notes

INPUT CLOCK 13 MHz 8 MHz

OUTPUT CLOCK

T CLKOUT Period 2*T T

TPRCLKOUT Rise Time 1 12 1 12 ns 1, 5 T

OUTPUT DELAYS

CHOV1

CHOV2

CHOV3

CLOV1

CLOV2

CLOV3

CLOV4

CLOV5

CHOF

CLOF

CLKIN Frequency 0 26 0 16 MHz 1 CLKIN Period 38.5 CLKIN High Time 12 CLKIN Low Time 12

% % %

62.5 12 12

% % %

ns 1 ns 1, 2

ns 1, 2 CLKIN Rise Time 1 8 1 8 ns 1, 3 CLKIN Fall Time 1 8 1 8 ns 1, 3

CLKIN to CLKOUT Delay 0 45 0 95 ns 1, 4

CLKOUT High Time (T/2)b5 (T/2)b5ns1

2*T

ns 1

CLKOUT Low Time (T/2)b5 (T/2)b5ns1

CLKOUT Fall Time 1 12 1 12 ns 1, 5

ALE, LOCK 3 27 3 27 ns 1,4,6,7

MCS3:0, LCS, UCS, 332332ns1,4,

,RD,WR 6, 8

PCS6:0

S2:0 (DEN), DT/R, 330330ns1

(RFSH), A19:16

BHE

LOCK, RESOUT, HLDA, 3 27 3 27 ns 1, 4, 6 T0OUT, T1OUT

RD,WR, MCS3:0, LCS, 3 32 3 35 ns 1,4,6

, PCS6:0, INTA1:0

UCS

BHE (RFSH), DEN, A19:16 3 30 3 30 ns 1, 4, 6

AD15:0 (A15:8, AD7:0) 3 34 3 35 ns 1, 4, 6

S2:0 3 38 3 40 ns 1,4,6

RD,WR, BHE (RFSH), 027027ns1

, LOCK,

DT/R

, A19:16

S2:0

DEN, AD15:0 (A15:8, AD7:0) 0 27 0 27 ns 1

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measured at V

3. Only required to guarantee I

4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.

6. See Figure 14 for rise and fall times.

7. T

CHOV1

8. T

CHOV2

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

11. T

CHOVS

12. Pin names in parentheses apply to the 80C188EA/80L188EA.

for high time, VILfor low time.

applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. applies to RD and WR only after a HOLD release.

applies to BHE (RFSH) and A19:16 only after a HOLD release.

. Maximum limits are bounded by TC,TCHand TCL.

80C186EA/80C188EA, 80L186EA/80L188EA

AC SPECIFICATIONS

AC CharacteristicsÐ80L186EA13/80L186EA8

Symbol Parameter Min Max Min Max Units Notes

SYNCHRONOUS INPUTS 13 MHz 8 MHz

CHIS

CHIH

CLIS

CLIH

CLIS

CLIH

CLIS

CLIH

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measured at V

3. Only required to guarantee I

4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.

6. See Figure 14 for rise and fall times.

7. T

CHOV1

8. T

CHOV2

9. Setup and Hold are required to guarantee recognition.

10. Setup and Hold are required for proper operation.

11. T

CHOVS

12. Pin names in parentheses apply to the 80C188EA/80L188EA.

TEST, NMI, INT3:0, T1:0IN, ARDY 22 22 ns 1, 9

TEST, NMI, INT3:0, T1:0IN, ARDY 3 3 ns 1, 9

AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0 22 22 ns 1, 10

AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0 3 3 ns 1, 10

HOLD 22 22 ns 1, 9

HOLD 3 3 ns 1, 9

RESIN (to CLKIN) 22 22 ns 1, 9

RESIN (from CLKIN) 3 3 ns 1, 9

for high time, VILfor low time.

applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. applies to RD and WR only after a HOLD release.

applies to BHE (RFSH) and A19:16 only after a HOLD release.

. Maximum limits are bounded by TC,TCHand TCL.

80C186EA/80C188EA, 80L186EA/80L188EA

AC SPECIFICATIONS (Continued)

Relative Timings (80C186EA25/20/13, 80L186EA13/8)

Symbol Parameter Min Max Unit Notes

RELATIVE TIMINGS

LHLL

AVLL

PLLL

LLAX

LLWL

LLRL

RHLH

WHLH

AFRL

RLRH

WLWH

RHAV

WHDX

WHDEX

WHPH

RHPH

PHPL

DXDL

OVRH

RHOX

NOTES:

1. Assumes equal loading on both pins.

2. Can be extended using wait states.

3. Not tested.

4. Not applicable to latched A2:1. These signals change only on falling T

5. For write cycle followed by read cycle.

6. Operating conditions for 25 MHz are 0

ALE Rising to ALE Falling Tb15 ns

Address Valid to ALE Falling (/2Tb10 ns

Chip Selects Valid to ALE Falling (/2Tb10 ns 1

Address Hold from ALE Falling (/2Tb10 ns

ALE Falling to WR Falling (/2Tb15 ns 1

ALE Falling to RD Falling (/2Tb15 ns 1

RD Rising to ALE Rising (/2Tb10 ns 1

Rising to ALE Rising (/2T

10 ns 1

Address Float to RD Falling 0 ns

RD Falling to RD Rising (2*T)b5ns2

WR Falling to WR Rising (2*T)b5ns2

RD Rising to Address Active Tb15 ns

Output Data Hold after WR Rising Tb15 ns

WR Rising to DEN Rising (/2Tb10 ns 1

WR Rising to Chip Select Rising (/2Tb10 ns 1, 4

RD Rising to Chip Select Rising (/2Tb10 ns 1, 4

CS Inactive to CS Active (/2Tb10 ns 1

DEN Inactive to DT/R Low 0 ns 5

ONCE (UCS, LCS) Active to RESIN Rising T ns 3

ONCE (UCS, LCS) to RESIN Rising T ns 3

Ctoa70§C, V

5.0Vg10%.

80C186EA/80C188EA, 80L186EA/80L188EA

AC TEST CONDITIONS

The AC specifications are tested with the 50 pF load shown in Figure 8. See the Derating Curves section to see how timings vary with load capacitance.

Specifications are measured at the V point, unless otherwise specified. See AC Timing

/2 crossing

Waveforms, for AC specification definitions, test pins, and illustrations.

AC TIMING WAVEFORMS

Figure 9. Input and Output Clock Waveform

50 pF for all signals.

272432– 8

Figure 8. AC Test Load

272432– 9

NOTE:

20% V

Floatk80% V

80C186EA/80C188EA, 80L186EA/80L188EA

272432– 10

Figure 10. Output Delay and Float Waveform

NOTE:

measured to CLKIN, not CLKOUT

RESIN

272432– 11

Figure 11. Input Setup and Hold

80C186EA/80C188EA, 80L186EA/80L188EA

NOTES:

1. T

2. Pin names in parentheses apply to tthe 80C188EA.

for write cycle followed by read cycle.

DXDL

Figure 12. Relative Signal Waveform

272432– 12

DERATING CURVES

80C186EA/80C188EA, 80L186EA/80L188EA

272432– 13

Figure 13. Typical Output Delay Variations

Versus Load Capacitance

RESET

The processor performs a reset operation any time the RESIN synchronized before it is presented internally, which means that the clock must be operating before a reset can take effect. From a power-on state, RESIN must be held active (low) in order to guarantee correct initialization of the processor. Failure to pro-

vide RESIN result in unspecified operation of the device.

Figure 15 shows the correct reset sequence when first applying power to the processor. An external clock connected to CLKIN must not exceed the V threshold being applied to the processor. This is normally not a problem if the clock driver is supplied with the same V When attaching a crystal to the device, RESIN remain active until both V (the length of time is application specific and depends on the startup characteristics of the crystal circuit). The RESIN rectly using an RC reset circuit, but the designer

pin is active. The RESIN pin is actually

while the device is powering up will

that supplies the processor.

and CLKOUT are stable

must

pin is designed to operate cor-

272432– 14

Figure 14. Typical Rise and Fall Variations

Versus Load Capacitance

must ensure that the ramp time for V long that RESIN low level when V conditions.

is never really sampled at a logic

reaches minimum operating

is not so

Figure 16 shows the timing sequence when RESIN is applied after VCCis stable and the device has been operating. Note that a reset will terminate all activity and return the processor to a known operating state. Any bus operation that is in progress at the time RESIN is asserted will terminate immediately (note that most control signals will be driven to their inactive state first before floating).

While RESIN

, MCS0/PEREQ, MCS1/ERROR, LOCK, and

LCS TEST

/BUSY are configured as inputs and weakly

is active, signals RD/QSMD, UCS,

held high by internal pullup transistors. Forcing UCS and LCS low selects ONCE Mode. Forcing QSMD low selects Queue Status Mode. Forcing TEST/ BUSY high at reset and low four clocks later enables Numerics Mode. Forcing LOCK

low is prohibited and

results in unspecified operation.

80C186EA/80C188EA, 80L186EA/80L188EA

272432– 15

Figure 15. Powerup Reset Waveforms

is sampled low.

NOTES:

1. CLKOUT synchronization occurs approximately 1(/2 CLKIN periods after RESIN

2. Pin names in parentheses apply to the 80C188EA.

80C186EA/80C188EA, 80L186EA/80L188EA

272432– 16

is sampled low. If RESIN is sampled low while CLKOUT is transitioning high,

Figure 16. Warm Reset Waveforms

is sampled low while CLKOUT is transitioning high, then CLKOUT will not be affected.

NOTES:

1. CLKOUT resynchronization occurs approximately 1(/2 CLKIN periods after RESIN

then CLKOUT will remain high for two CLKIN periods. If RESIN

2. Pin names in parentheses apply to the 80C188EA.

80C186EA/80C188EA, 80L186EA/80L188EA

BUS CYCLE WAVEFORMS

Figures 17 through 23 present the various bus cycles that are generated by the processor. What is shown in the figure is the relationship of the various bus signals to CLKOUT. These figures along with the information present in AC Specifications allow the user to determine all the critical timing analysis needed for a given application.

NOTES:

1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA or refresh cycle.

2. Pin names in parentheses apply to the 80C188EA.

Figure 17. Read, Fetch and Refresh Cycle Waveform

272432-17

80C186EA/80C188EA, 80L186EA/80L188EA

NOTES:

1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA cycle.

2. Pin names in parentheses apply to the 80C188EA.

Figure 18. Write Cycle Waveform

272432-18

80C186EA/80C188EA, 80L186EA/80L188EA

NOTES:

1. The processor drives these pins to 0 during Idle and Powerdown Modes.

2. Pin names in parentheses apply to the 80C188EA.

Figure 19. Halt Cycle Waveform

272432– 19

80C186EA/80C188EA, 80L186EA/80L188EA

NOTES: 272432– 20

1. INTA occurs one clock later in Slave Mode.

2. Pin names in parentheses apply to the 80C188EA.

Figure 20. INTA Cycle Waveform

80C186EA/80C188EA, 80L186EA/80L188EA

NOTE:

1. Pin names in parentheses apply to the 80C188EA.

Figure 21. HOLD/HLDA Waveform

272432– 21

80C186EA/80C188EA, 80L186EA/80L188EA

NOTE:

1. Pin names in parentheses apply to the 80C188EA.

Figure 22. DRAM Refresh Cycle During Hold Acknowledge

272432– 22

80C186EA/80C188EA, 80L186EA/80L188EA

NOTES:

1. Generalized diagram for READ or WRITE.

2. ARDY low by either edge causes a wait state. Only rising ARDY is fully synchronized.

3. SRDY low causes a wait state. SRDY must meet setup and hold times to ensure correct device operation.

4. Either ARDY or SRDY active high will terminate a bus cycle.

5. Pin names in parentheses apply to the 80C188EA.

Figure 23. Ready Waveform

272432– 23

80C186EA/80C188EA, 80L186EA/80L188EA

80C186EA/80C188EA EXECUTION TIMINGS

A determination of program exeuction timing must consider the bus cycles necessary to prefetch instructions as well as the number of execution unit cycles necessary to execute instructions. The following instruction timings represent the minimum execution time in clock cycle for each instruction. The timings given are based on the following assumptions:

The opcode, along with any data or displacement

required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed.

No wait states or bus HOLDs occur.

All word-data is located on even-address bound-

aries. (80C186EA only)

All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address.

All instructions which involve memory accesses can require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit.

With a 16-bit BIU, the 80C186EA has sufficient bus performance to endure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. Therefore, actual program exeuction time will not be substanially greater than that derived from adding the instruction timings shown.

The 80C188EA 8-bit BIU is limited in its performance relative to the execution unit. A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. Therefore, actual program execution time will be substantially greater than that derived from adding the instruction timings shown.

80C186EA/80C188EA, 80L186EA/80L188EA

INSTRUCTION SET SUMMARY

Function Format

DATA TRANSFER

Move:

MOV

Immediate to register/memory 1100011w mod000 r/m data data if we1 12– 13 12 –13 8/16-bit

Immediate to register 1011w reg data data if we1 3– 4 3–4 8/16-bit

Memory to accumulator 1010000w addr-low addr-high 8 8*

Accumulator to memory 1010001w addr-low addr-high 9 9*

Segment register to register/memory 10001100 mod0reg r/m 2/11 2/15

PUSHePush:

Memory 11111111 mod110 r/m 16 20

Segment register 000reg110 9 13

Immediate 011010s0 data data if se01014

PUSHAePush All 01100000 36 68

POPePop:

Memory 10001111 mod000 r/m 20 24

Segment register 000reg111 (regi01) 8 12

POPAePopAll 01100001 51 83

XCHGeExchange:

INeInput from:

Fixed port 1110010w port 10 10*

Variable port 1110110w 8 7*

OUTeOutput to:

Fixed port 1110011w port 9 9*

Variable port 1110111w 7 7*

XLATeTranslate byte to AL 11010111 11 15

LEAeLoad EA to register 10001101 modreg r/m 6 6

LDSeLoad pointer to DS 11000101 modreg r/m (modi11) 18 26

LESeLoad pointer to ES 11000100 modreg r/m (modi11) 18 26

LAHFeLoad AH with flags 10011111 2 2

SAHFeStore AH into flags 10011110 3 3

PUSHFePush flags 10011100 9 13

POPFePop flags 10011101 8 12

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

80C186EA 80C188EA

Clock Clock

Cycles Cycles

Comments

80C186EA/80C188EA, 80L186EA/80L188EA

INSTRUCTION SET SUMMARY (Continued)

Function Format

DATA TRANSFER (Continued)

SEGMENT

CS 00101110 2 2

SS 00110110 2 2

DS 00111110 2 2

ES 00100110 2 2

ARITHMETIC ADD

Reg/memory with register to either 000000dw modreg r/m 3/10 3/10

Immediate to register/memory 100000sw mod000 r/m data data if s we01 4/16 4/16

Immediate to accumulator 0000010w data data if we1 3/4 3/4 8/16-bit

ADCeAdd with carry:

Reg/memory with register to either 000100dw modreg r/m 3/10 3/10

Immediate to register/memory 100000sw mod010 r/m data data if s we01 4/16 4/16

Immediate to accumulator 0001010w data data if we1 3/4 3/4 8/16-bit

INCeIncrement:

SUBeSubtract:

Reg/memory and register to either 001010dw modreg r/m 3/10 3/10

Immediate from register/memory 100000sw mod101 r/m data data if s we01 4/16 4/16

Immediate from accumulator 0010110w data data if we1 3/4 3/4 8/16-bit

SBBeSubtract with borrow:

Reg/memory and register to either 000110dw modreg r/m 3/10 3/10

Immediate from register/memory 100000sw mod011 r/m data data if s we01 4/16 4/16

Immediate from accumulator 0001110w data data if we1 3/4 3/4

DECeDecrement

CMPeCompare:

Immediate with register/memory 100000sw mod111 r/m data data if s we01 3/10 3/10

Immediate with accumulator 0011110w data data if we1 3/4 3/4 8/16-bit

NEGeChange sign register/memory 1111011w mod011 r/m 3/10

AAAeASCII adjust for add 00110111 8 8

DAAeDecimal adjust for add 00100111 4 4

AASeASCII adjust for subtract 00111111 7 7

DASeDecimal adjust for subtract 00101111 4 4

MULeMultiply (unsigned): 1111011w mod100 r/m

Add:

Segment Override:

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

80C186EA 80C188EA

Clock Clock

Cycles Cycles

3/10

Comments

8/16-bit

80C186EA/80C188EA, 80L186EA/80L188EA

INSTRUCTION SET SUMMARY (Continued)

Function Format

ARITHMETIC (Continued)

IMULeInteger multiply (signed): 1111011w mod101 r/m

IMULeInteger Immediate multiply 011010s1 modreg r/m data data if se0 22– 25 22-25

(signed)

DIVeDivide (unsigned): 1111011w mod110 r/m

IDIVeInteger divide (signed): 1111011w mod111 r/m

AAMeASCII adjust for multiply 11010100 00001010 19 19

AADeASCII adjust for divide 11010101 00001010 15 15

CBWeConvert byte to word 10011000 2 2

CWDeConvert word to double word 10011001 4 4

LOGIC Shift/Rotate Instructions:

TTT Instruction

000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHL/SAL 101 SHR

AND

And:

Reg/memory and register to either 001000dw modreg r/m 3/10 3/10*

Immediate to register/memory 1000000w mod100 r/m data data if we1 4/16 4/16*

Immediate to accumulator 0010010w data data if we1 3/4 3/4* 8/16-bit

TESTeAnd function to flags, no result:

Immediate data and register/memory 1111011w mod000 r/m data data if we1 4/10 4/10*

Immediate data and accumulator 1010100w data data if we1 3/4 3/4 8/16-bit

OReOr:

Reg/memory and register to either 000010dw modreg r/m 3/10 3/10*

Immediate to register/memory 1000000w mod001 r/m data data if we1 4/16 4/16

Immediate to accumulator 0000110w data data if we1 3/4 3/4* 8/16-bit

111 SAR

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

80C186EA 80C188EA

Clock Clock

Cycles Cycles

29–32 29–32

Comments

80C186EA/80C188EA, 80L186EA/80L188EA

INSTRUCTION SET SUMMARY (Continued)

Function Format

LOGIC (Continued)

Exclusive or:

XOR

Reg/memory and register to either 001100dw modreg r/m 3/10 3/10*

Immediate to register/memory 1000000w mod110 r/m data data if we1 4/16 4/16*

Immediate to accumulator 0011010w data data if we1 3/4 3/4 8/16-bit

NOTeInvert register/memory 1111011w mod010 r/m 3/10 3/10*

STRING MANIPULATION

MOVSeMove byte/word 1010010w 14 14*

CMPSeCompare byte/word 1010011w 22 22*

SCASeScan byte/word 1010111w 15 15*

LODSeLoad byte/wd to AL/AX 1010110w 12 12*

STOSeStore byte/wd from AL/AX 1010101w 10 10*

INSeInput byte/wd from DX port 0110110w 14 14

OUTSeOutput byte/wd to DX port 0110111w 14 14

Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)

MOVSeMove string 11110010 1010010w 8a8n 8a8n

CMPSeCompare string 1111001z 1010011w 5a22n 5a22n

SCASeScan string 1111001z 1010111w 5a15n 5a15n*

LODSeLoad string 11110010 1010110w 6a11n 6a11n*

STOSeStore string 11110010 1010101w 6a9n 6a9n*

INSeInput string 11110010 0110110w 8a8n 8a8n*

OUTSeOutput string 11110010 0110111w 8a8n 8a8n*

CONTROL TRANSFER

CALL

Call:

Direct within segment 11101000 disp-low disp-high 15 19

Direct intersegment 10011010 segment offset 23 31

segment selector

Indirect intersegment 11111111 mod011 r/m (modi11) 38 54

JMPeUnconditional jump:

Short/long 11101011 disp-low 14 14

Direct within segment 11101001 disp-low disp-high 14 14

Direct intersegment 11101010 segment offset 14 14

segment selector

Indirect intersegment 11111111 mod101 r/m (modi11) 26 34

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

80C186EA 80C188EA

Clock Clock

Cycles Cycles

Comments

80C186EA/80C188EA, 80L186EA/80L188EA

INSTRUCTION SET SUMMARY (Continued)

Function Format

CONTROL TRANSFER (Continued)

Return from CALL:

RET

Within segment 11000011 16 20

Within seg adding immed to SP 11000010 data-low data-high 18 22

Intersegment 11001011 22 30

Intersegment adding immediate to SP 11001010 data-low data-high 25 33

JE/JZeJump on equal/zero 01110100 disp 4/13 4/13 JMP not

JL/JNGEeJump on less/not greater or equal 01111100 disp 4/13 4/13

JLE/JNGeJump on less or equal/not greater 01111110 disp 4/13 4/13

JB/JNAEeJump on below/not above or equal 01110010 disp 4/13 4/13

JBE/JNAeJump on below or equal/not above 01110110 disp 4/13 4/13

JP/JPEeJump on parity/parity even 01111010 disp 4/13 4/13

JOeJump on overflow 01110 000 disp 4/13 4/13

JSeJump on sign 01111000 disp 4/13 4/13

JNE/JNZeJump on not equal/not zero 01110101 disp 4/13 4/13

JNL/JGEeJump on not less/greater or equal 01111101 disp 4/13 4/13

JNLE/JGeJump on not less or equal/greater 01111111 disp 4/13 4/13

JNB/JAEeJump on not below/above or equal 01110011 disp 4/13 4/13

JNBE/JAeJump on not below or equal/above 01110111 disp 4/13 4/13

JNP/JPOeJump on not par/par odd 01111011 disp 4/13 4/13

JNOeJump on not overflow 01110001 disp 4/13 4/13

JNSeJump on not sign 01111001 disp 4/13 4/13

JCXZeJump on CX zero 11100011 disp 5/15 5/15

LOOPeLoop CX times 11100010 disp 6/16 6/16 LOOP not

LOOPZ/LOOPEeLoop while zero/equal 11100001 disp 6/16 6/16

LOOPNZ/LOOPNEeLoop while not zero/equal 11100000 disp 6/16 6/16

ENTEReEnter Procedure 11001000 data-low data-high L

Le0 15 19

1 25 29

LEAVEeLeave Procedure 11001001 8 8

INTeInterrupt:

Type specified 11001101 type 47 47

Type 3 11001100 45 45 ifINT. taken/

INTOeInterrupt on overflow 11001110 48/4 48/4

80C186EA 80C188EA

Clock Clock

Cycles Cycles

22a16(nb1) 26a20(nb1)

Comments

taken/JMP

taken

taken/LOOP

taken

if INT. not

taken

IRETeInterrupt return 11001111 28 28

BOUNDeDetect value out of range 01100010 modreg r/m 33–35 33–35

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

80C186EA/80C188EA, 80L186EA/80L188EA

INSTRUCTION SET SUMMARY (Continued)

Function Format

PROCESSOR CONTROL

CLCeClear carry 11111000 2 2

CMCeComplement carry 11110101 2 2

STCeSet carry 11111001 2 2

CLDeClear direction 11111100 2 2

STDeSet direction 11111101 2 2

CLIeClear interrupt 11111010 2 2

STIeSet interrupt 11111011 2 2

HLTeHalt 11110100 2 2

WAITeWait 10011011 6 6 ifTESTe0

LOCKeBus lock prefix 11110000 2 2

NOPeNo Operation 10010000 3 3

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

The Effective Address (EA) of the memory operand

(TTT LLL are opcode to processor extension)

reg is assigned according to the following:

is computed according to the mod and r/m fields:

if mod if mod

if mod

if mod if r/m if r/m if r/m if r/m if r/m if r/m if r/m if r/m

DISP follows 2nd byte of instruction (before data if required)

*except if mod disp-high: disp-low.

EA calculation time is 4 clock cycles for all modes, and is included in the execution times given whenever appropriate.

11 then r/m is treated as a REG field

00 then DISPe0*, disp-low and disphigh are absent

01 then DISPedisp-low sign-extended to 16-bits, disp-high is absent

10 then DISPedisp-high: disp-low

000 then EAe(BX)a(SI)aDISP

001 then EAe(BX)a(DI)aDISP

010 then EAe(BP)a(SI)aDISP

011 then EAe(BP)a(DI)aDISP

100 then EAe(SI)aDISP

101 then EAe(DI)aDISP

110 then EAe(BP)aDISP*

111 then EAe(BX)aDISP

00 and r/me110 then EA

Segment Override Prefix

reg Register

REG is assigned according to the following table:

16-Bit (w

000 AX 000 AL 001 CX 001 CL 010 DX 010 DL 011 BX 011 BL 100 SP 100 AH 101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

The physical addresses of all operands addressed by the BP register are computed using the SS segment register. The physical addresses of the destination operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden.

0 0 1 reg 1 1 0

80C186EA 80C188EA

Clock Clock

Cycles Cycles

Segment

00 ES 01 CS 10 SS 11 DS

1) 8-Bit (we0)

Comments

80C186EA/80C188EA, 80L186EA/80L188EA

REVISION HISTORY

Intel 80C186EA/80L186EA devices are marked with a 9-character alphanumeric Intel FPO number underneath the product number. This data sheet update is valid for devices with an ‘‘A’’, ‘‘B’’, ‘‘C’’, ‘‘D’’, or ‘‘E’’ as the ninth character in the FPO number, as illustrated in Figure 5 for the 68-lead PLCC package, Figure 6 for the 84-lead QFP (EIAJ) package, and Figure 7 for the 80-lead SQFP device. Such devices may also be identified by reading a value of 01H, 02H, 03H from the STEPID register.

This data sheet replaces the following data sheets:

272019-002Ð80C186EA 272020-002Ð80C188EA 272021-002Ð80L186EA 272022-002Ð80L188EA 272307-001ÐSB80C186EA/SB80L186EA 272308-001ÐSB80C188EA/SB80L188EA

ERRATA

An 80C186EA/80L186EA with a STEPID value of 01H or 02H has the following known errata. A device with a STEPID of 01H or 02H can be visually identified by noting the presence of an ‘‘A’’, ‘‘B’’, or ‘‘C’’ alpha character, next to the FPO number. The FPO number location is shown in Figures 5, 6, and 7.

1. An internal condition with the interrupt controller can cause no acknowledge cycle on the INTA1 line in response to INT1. This errata only occurs when Interrupt 1 is configured in cascade mode and a higher priority interrupt exists. This errata will not occur consistantly, it is dependent on interrupt timing.

An 80C186EA/80L186EA with a STEPID value of 03H has no known errata. A device with a STEPID of 03H can be visually identified by noting the presence of a ‘‘D’’ or ‘‘E’’ alpha character next to the FPO number. The FPO number location is shown in Figures 5, 6, and 7.

Intel 80C188EA, 80L186EA, 80C186EA, 80L188EA User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual