INTEL 80C186XL, 80C188XL User Manual

查询R80C186XL12供应商查询R80C186XL12供应商

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186XL/80C188XL

Y

Low Power, Fully Static Versions of
80C186/80C188

Y

Operation Modes:
Ð Enhanced Mode

Ð DRAM Refresh Control Unit
Ð Power-Save Mode
Ð Direct Interface to 80C187

(80C186XL Only)

Ð Compatible Mode

Ð NMOS 80186/80188 Pin-for-Pin

Replacement for Non-Numerics
Applications

Y

Integrated Feature Set
Ð Static, Modular CPU
Ð Clock Generator
Ð 2 Independent DMA Channels
Ð Programmable Interrupt Controller
Ð 3 Programmable 16-Bit Timers
Ð Dynamic RAM Refresh Control Unit
Ð Programmable Memory and

Peripheral Chip Select Logic

Ð Programmable Wait State Generator

Y

Completely Object Code Compatible
with Existing 8086/8088 Software and
Has 10 Additional Instructions over
8086/8088

Y

Speed Versions Available
Ð 25 MHz (80C186XL25/80C188XL25)
Ð 20 MHz (80C186XL20/80C188XL20)
Ð 12 MHz (80C186XL12/80C188XL12)

Y

Direct Addressing Capability to
1 MByte Memory and 64 Kbyte I/O

Y

Available in 68-Pin:
Ð Plastic Leaded Chip Carrier (PLCC)
Ð Ceramic Pin Grid Array (PGA)
Ð Ceramic Leadless Chip Carrier

(JEDEC A Package)

Y

Available in 80-Pin:
Ð Quad Flat Pack (EIAJ)
Ð Shrink Quad Flat Pack (SGFP)

Y

Available in Extended Temperature
Range (

b

40§Ctoa85§C)

Ð Local Bus Controller
Ð Power-Save Mode
Ð System-Level Testing Support (High

Impedance Test Mode)

The Intel 80C186XL is a Modular Core re-implementation of the 80C186 microprocessor. It offers higher speed
and lower power consumption than the standard 80C186 but maintains 100% clock-for-clock functional com­patibility. Packaging and pinout are also identical.

272431-1

*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

COPYRIGHT

©INTELCORPORATION,2002

June, 2002

OrderNumber:272431-005

80C186XL/80C188XL

16-Bit High-Integration Embedded Processors

CONTENTS PAGE

INTRODUCTION ААААААААААААААААААААААААААА 4

80C186XL CORE ARCHITECTURE АААААААА 4

80C186XL Clock Generator АААААААААААААААА 4
Bus Interface Unit АААААААААААААААААААААААААА 5

80C186XL PERIPHERAL

ARCHITECTURE АААААААААААААААААААААААА 5

Chip-Select/Ready Generation Logic ААААААА 5
DMA Unit АААААААААААААААААААААААААААААААААА 6
Timer/Counter Unit АААААААААААААААААААААААА 6
Interrupt Control Unit ААААААААААААААААААААААА 6
Enhanced Mode Operation ААААААААААААААААА 6
Queue-Status Mode АААААААААААААААААААААААА 6
DRAM Refresh Control Unit АААААААААААААААА 7
Power-Save Control АААААААААААААААААААААААА 7
Interface for 80C187 Math Coprocessor

(80C186XL Only) АААААААААААААААААААААААА 7

ONCE Test Mode АААААААААААААААААААААААААА 7

PACKAGE INFORMATION АААААААААААААААА 8

Pin Descriptions АААААААААААААААААААААААААААА 8
80C186XL/80C188XL Pinout

Diagrams

ELECTRICAL SPECIFICATIONS ААААААААА 22

Absolute Maximum Ratings ААААААААААААААА 22

DC SPECIFICATIONS АААААААААААААААААААА 22

Power Supply Current ААААААААААААААААААААА 23

ААААААААААААААААААААААААААААААА 16

CONTENTS PAGE

AC SPECIFICATIONS АААААААААААААААААААА 24

Major Cycle Timings (Read Cycle) ААААААААА 24
Major Cycle Timings (Write Cycle) ААААААААА 26
Major Cycle Timings (Interrupt

Acknowledge Cycle) АААААААААААААААААААА 27
Software Halt Cycle Timings ААААААААААААААА 28
Clock Timings ААААААААААААААААААААААААААААА 29
Ready, Peripheral and Queue Status

Timings
Reset and Hold/HLDA Timings АААААААААААА 31

AC TIMING WAVEFORMS ААААААААААААААА 36

AC CHARACTERISTICS ААААААААААААААААА 37

EXPLANATION OF THE AC

SYMBOLS

DERATING CURVES ААААААААААААААААААААА 40

80C186XL/80C188XL EXPRESS ААААААААА 41

80C186XL/80C188XL EXECUTION

TIMINGS ААААААААААААААААААААААААААААААА 41

INSTRUCTION SET SUMMARY АААААААААА 42

REVISION HISTORY ААААААААААААААААААААА 48

ERRATA ААААААААААААААААААААААААААААААААА 48

PRODUCT IDENTIFICATION ААААААААААААА 48

ААААААААААААААААААААААААААААААААА 30

АААААААААААААААААААААААААААААА 39

2

80C186XL/80C188XL

272431– 2

NOTE:

Pin names in parentheses applies to 80C188XL.

Figure 1. 80C186XL/80C188XL Block Diagram

3

80C186XL/80C188XL

(2a)

272431– 3

Figure 2. Oscillator Configurations (see text)

INTRODUCTION

Unless specifically noted, all references to the
80C186XL apply to the 80C188XL. References to
pins that differ between the 80C186XL and the
80C188XL are given in parentheses.

The following Functional Description describes the
base architecture of the 80C186XL. The 80C186XL
is a very high integration 16-bit microprocessor. It
combines 15 –20 of the most common microproces­sor system components onto one chip. The
80C186XL is object code compatible with the
8086/8088 microprocessors and adds 10 new in­struction types to the 8086/8088 instruction set.

The 80C186XL has two major modes of operation,
Compatible and Enhanced. In Compatible Mode the
80C186XL is completely compatible with NMOS
80186, with the exception of 8087 support. The En­hanced mode adds three new features to the system
design. These are Power-Save control, Dynamic
RAM refresh, and an asynchronous Numerics Co­processor interface (80C186XL only).

272431– 4

(2b)

Note 1:

XTAL Frequency L1 Value

20 MHz 12.0 mH
25 MHz 8.2 mH
32 MHz 4.7 mH

40 MHz 3.0 mH
LC network is only required when using a third
overtone crystal.

g

20%

g

20%

g

20%

g

20%

The 80C186XL oscillator circuit is designed to be
used either with a parallel resonant fundamental or
third-overtone mode crystal, depending upon the
frequency range of the application. This is used as
the time base for the 80C186XL.

The output of the oscillator is not directly available
outside the 80C186XL. The recommended crystal
configuration is shown in Figure 2b. When used in
third-overtone mode, the tank circuit is recommend­ed for stable operation. Alternately, the oscillator
may be driven from an external source as shown in
Figure 2a.

The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide by two counter. This counter is
used to drive all internal phase clocks and the exter­nal CLKOUT signal. CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys­tem components. All AC Timings are referenced to
CLKOUT.

Intel recommends the following values for crystal se­lection parameters.

80C186XL CORE ARCHITECTURE

80C186XL Clock Generator

The 80C186XL provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divide­by-two counter, synchronous and asynchronous
ready inputs, and reset circuitry.

4

Temperature Range: Application Specific

ESR (Equivalent Series Resistance): 60X max

(Shunt Capacitance of Crystal): 7.0 pF max

C

0

C1(Load Capacitance): 20 pFg2pF

Drive Level: 2 mW max

80C186XL/80C188XL

Bus Interface Unit

The 80C186XL provides a local bus controller to
generate the local bus control signals. In addition, it
employs a HOLD/HLDA protocol for relinquishing
the local bus to other bus masters. It also provides
outputs that can be used to enable external buffers
and to direct the flow of data on and off the local
bus.

The bus controller is responsible for generating 20
bits of address, read and write strobes, bus cycle
status information and data (for write operations) in­formation. It is also responsible for reading data
from the local bus during a read operation. Synchro­nous and asynchronous ready input pins are provid­ed to extend a bus cycle beyond the minimum four
states (clocks).

The 80C186XL bus controller also generates two
control signals (DEN
external transceiver chips. This capability allows the
addition of transceivers for simple buffering of the
multiplexed address/data bus.

During RESET the local bus controller will perform
the following action:

Drive DEN

#

cle, then float them.

Drive S0–S2 to the inactive state (all HIGH) and

#

then float.

Drive LOCK HIGH and then float.

#

Float AD0 – 15 (AD0–8), A16 – 19 (A9–A19), BHE

#

(RFSH), DT/R.

Drive ALE LOW

#

Drive HLDA LOW.

#

RD

/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/

ERROR

and TEST/BUSY pins have internal pullup
devices which are active while RES
cessive loading or grounding certain of these pins
causes the 80C186XL to enter an alternative mode
of operation:

RD/QSMD low results in Queue Status Mode.

#

UCS and LCS low results in ONCE Mode.

#

TEST/BUSY low (and high later) results in En-

#

hanced Mode.

and DT/R) when interfacing to

,RDand WR HIGH for one clock cy-

is applied. Ex-

spond to bus cycles. An offset map of the 256-byte
control register block is shown in Figure 3.

Chip-Select/Ready Generation Logic

The 80C186XL contains logic which provides
programmable chip-select generation for both mem­ories and peripherals. In addition, it can be
programmed to provide READY (or WAIT state) gen­eration. It can also provide latched address bits A1
and A2. The chip-select lines are active for all mem­ory and I/O cycles in their programmed areas,
whether they be generated by the CPU or by the
integrated DMA unit.

The 80C186XL provides 6 memory chip select out­puts for 3 address areas; upper memory, lower
memory, and midrange memory. One each is provid­ed for upper memory and lower memory, while four
are provided for midrange memory.

OFFSET

Relocation Register FEH

DMA Descriptors Channel 1

DMA Descriptors Channel 0

Chip-Select Control Registers

Time 2 Control Registers

Time 1 Control Registers

Time 0 Control Registers

Interrupt Controller Registers

DAH

D0H

CAH

C0H

A8H

A0H

66H

60H

5EH

58H

56H

50H

3EH

20H

80C186XL PERIPHERAL
ARCHITECTURE

All the 80C186XL integrated peripherals are con­trolled by 16-bit registers contained within an inter­nal 256-byte control block. The control block may be
mapped into either memory or I/O space. Internal
logic will recognize control block addresses and re-

Figure 3. Internal Register Map

The 80C186XL provides a chip select, called UCS
for the top of memory. The top of memory is usually
used as the system memory because after reset the
80C186XL begins executing at memory location
FFFF0H.

,

5

80C186XL/80C188XL

The 80C186XL provides a chip select for low memo­ry called LCS
interrupt vector table, starting at location 00000H.

The 80C186XL provides four MCS
active within a user-locatable memory block. This
block can be located within the 80C186XL 1 Mbyte
memory address space exclusive of the areas de­fined by UCS
size of this memory block are programmable.

The 80C186XL can generate chip selects for up to
seven peripheral devices. These chip selects are ac­tive for seven contiguous blocks of 128 bytes above
a programmable base address. The base address
may be located in either memory or I/O space.

The 80C186XL can generate a READY signal inter­nally for each of the memory or peripheral CS
The number of WAIT states to be inserted for each
peripheral or memory is programmable to provide
0–3 wait states for all accesses to the area for
which the chip select is active. In addition, the
80C186XL may be programmed to either ignore ex­ternal READY for each chip-select range individually
or to factor external READY with the integrated
ready generator.

Upon RESET, the Chip-Select/Ready Logic will per­form the following actions:

All chip-select outputs will be driven HIGH.

#

Upon leaving RESET, the UCS line will be pro-

#

grammed to provide chip selects to a 1K block
with the accompanying READY control bits set at
011 to insert 3 wait states in conjunction with ex­ternal READY (i.e., UMCS resets to FFFBH).

No other chip select or READY control registers

#

have any predefined values after RESET. They
will not become active until the CPU accesses
their control registers.

. The bottom of memory contains the

lines which are

and LCS. Both the base address and

lines.

DMA Unit

The 80C186XL DMA controller provides two inde­pendent high-speed DMA channels. Data transfers
can occur between memory and I/O spaces (e.g.,
Memory to I/O) or within the same space (e.g.,
Memory to Memory or I/O to I/O). Data can be
transferred either in bytes (8 bits) or in words (16
bits) to or from even or odd addresses.

mum of 8 clocks), one cycle to fetch data and the
other to store data.

Timer/Counter Unit

The 80C186XL provides three internal 16-bit pro­grammable timers. Two of these are highly flexible
and are connected to four external pins (2 per timer).
They can be used to count external events, time ex­ternal events, generate nonrepetitive waveforms,
etc. The third timer is not connected to any external
pins, and is useful for real-time coding and time de­lay applications. In addition, the third timer can be
used as a prescaler to the other two, or as a DMA
request source.

Interrupt Control Unit

The 80C186XL can receive interrupts from a number
of sources, both internal and external. The
80C186XL has 5 external and 2 internal interrupt
sources (Timer/Couners and DMA). The internal in­terrupt controller serves to merge these requests on
a priority basis, for individual service by the CPU.

Enhanced Mode Operation

In Compatible Mode the 80C186XL operates with all
the features of the NMOS 80186, with the exception
of 8087 support (i.e. no math coprocessing is possi­ble in Compatible Mode). Queue-Status information
is still available for design purposes other than 8087
support.

All the Enhanced Mode features are completely
masked when in Compatible Mode. A write to any of
the Enhanced Mode registers will have no effect,
while a read will not return any valid data.

In Enhanced Mode, the 80C186XL will operate with
Power-Save, DRAM refresh, and numerics coproc­essor support (80C186XL only) in addition to all the
Compatible Mode features.

If connected to a math coprocessor (80C186XL
only), this mode will be invoked automatically. With­out an NPX, this mode can be entered by tying the
RESET output signal from the 80C186XL to the
TEST

/BUSY input.

Only byte transfers are possible on the 80C188XL.

NOTE:

Each DMA channel maintains both a 20-bit source
and destination pointer which can be optionally in­cremented or decremented after each data transfer
(by one or two depending on byte or word transfers).
Each data transfer consumes 2 bus cycles (a mini-

6

Queue-Status Mode

The queue-status mode is entered by strapping the

pin low. RD is sampled at RESET and if LOW,

RD
the 80C186XL will reconfigure the ALE and WR
to be QS0 and QS1 respectively. This mode is avail­able on the 80C186XL in both Compatible and En­hanced Modes.

pins

80C186XL/80C188XL

DRAM Refresh Control Unit

The Refresh Control Unit (RCU) automatically gen­erates DRAM refresh bus cycles. The RCU operates
only in Enhanced Mode. After a programmable peri­od of time, the RCU generates a memory read re­quest to the BIU. If the address generated during a
refresh bus cycle is within the range of a properly
programmed chip select, that chip select will be acti­vated when the BIU executes the refresh bus cycle.

Power-Save Control

The 80C186XL, when in Enhanced Mode, can enter
a power saving state by internally dividing the proc­essor clock frequency by a programmable factor.
This divided frequency is also available at the
CLKOUT pin.

All internal logic, including the Refresh Control Unit
and the timers, have their clocks slowed down by
the division factor. To maintain a real time count or a
fixed DRAM refresh rate, these peripherals must be
re-programmed when entering and leaving the pow­er-save mode.

Interface for 80C187 Math
Coprocessor (80C186XL Only)

In Enhanced Mode, three of the mid-range memory
chip selects are redefined according to Table 1 for
use with the 80C187. The fourth chip select, MCS2

functions as in compatible mode, and may be pro­grammed for activity with ready logic and wait states
accordingly. As in Compatible Mode, MCS2
tion for one-fourth a programmed block size.

Table 1. MCS

Compatible

Mode

MCS0 PEREQ Processor Extension Request
MCS1
MCS2
MCS3

ERROR NPX Error
MCS2 Mid-Range Chip Select
NPS Numeric Processor Select

Assignments

Enhanced Mode

will func-

ONCE Test Mode

To facilitate testing and inspection of devices when
fixed into a target system, the 80C186XL has a test
mode available which allows all pins to be placed in
a high-impedance state. ONCE stands for ‘‘ON Cir­cuit Emulation’’. When placed in this mode, the
80C186XL will put all pins in the high-impedance
state until RESET.

The ONCE mode is selected by tying the UCS
the LCS
pled on the low-to-high transition of the RES
The UCS
up resistors similar to the RD
to guarantee ONCE Mode is not entered inadver­tently during normal operation. LCS
be held low at least one clock after RES
to guarantee entrance into ONCE Mode.

LOW during RESET. These pins are sam-

and the LCS pins have weak internal pull-

and TEST/BUSY pins

and UCS must

and

pin.

goes high

7

80C186XL/80C188XL

PACKAGE INFORMATION

This section describes the pin functions, pinout and
thermal characteristics for the 80C186XL in the
Quad Flat Pack (QFP), Plastic Leaded Chip Carrier
(PLCC), Leadless Chip Carrier (LCC) and the Shrink
Quad Flat Pack (SQFP). For complete package
specifications and information, see the Intel Packag­ing Outlines and Dimensions Guide (Order Number:

231369).

Pin Descriptions

Each pin or logical set of pins is described in Table

3. There are four columns for each entry in the Pin
Description Table. The following sections describe
each column.

Column 1: Pin Name

In this column is a mnemonic that de­scribes the pin function. Negation of the
signal name (i.e., RESIN
the signal is active low.

Column 2: Pin Type

A pin may be either power (P), ground
(G), input only (I), output only (O) or in­put/output (I/O). Please note that some
pins have more than one function.

Column 3: Input Type (for I and I/O types only)

These are two different types of input
pins on the 80C186XL: asynchronous
and synchronous. Asynchronous pins
require that setup and hold times be met
only to

guarantee recognition.

nous input pins require that the setup
and hold times be met to

) implies that

Synchro-

guarantee

proper operation.

a setup or hold on an asynchronous pin
will result in something minor (i.e., a tim­er count will be missed) whereas miss­ing a setup or hold on a synchronous pin
result in system failure (the system will
‘‘lock up’’).

An input pin may also be edge or level
sensitive.

Column 4: Output States (for O and I/O types

only)

The state of an output or I/O pin is de­pendent on the operating mode of the
device. There are four modes of opera­tion that are different from normal active
mode: Bus Hold, Reset, Idle Mode, Pow­erdown Mode. This column describes
the output pin state in each of these
modes.

The legend for interpreting the information in the Pin
Descriptions is shown in Table 2.

As an example, please refer to the table entry for
AD7:0. The ‘‘I/O’’ signifies that the pins are bidirec­tional (i.e., have both an input and output function).
The ‘‘S’’ indicates that, as an input the signal must
be synchronized to CLKOUT for proper operation.
The ‘‘H(Z)’’ indicates that these pins will float while
the processor is in the Hold Acknowledge state.
R(Z) indicates that these pins will float while RESIN
is low.

All pins float while the processor is in the ONCE
Mode (with the exception of X2).

Stated simply, missing

8

Table 2. Pin Description Nomenclature

Symbol Description

P Power Pin (applyaVCCvoltage)
G Ground (connect to V

SS

)
I Input only pin
O Output only pin
I/O Input/Output pin

S(E) Synchronous, edge sensitive
S(L) Synchronous, level sensitive
A(E) Asynchronous, edge sensitive
A(L) Asynchronous, level sensitive

H(1) Output driven to VCCduring bus hold
H(0) Output driven to V

during bus hold

SS

H(Z) Output floats during bus hold
H(Q) Output remains active during bus hold
H(X) Output retains current state during bus hold

R(WH) Output weakly held at VCCduring reset
R(1) Output driven to V
R(0) Output driven to V

during reset

CC

during reset

SS

R(Z) Output floats during reset
R(Q) Output remains active during reset
R(X) Output retains current state during reset

80C186XL/80C188XL

9

80C186XL/80C188XL

Table 3. Pin Descriptions

Pin Pin Input Output

Name Type Type States

V

CC

V

SS

P System Power:a5 volt power supply.

G System Ground.

RESET O H(0) RESET Output indicates that the CPU is being reset, and can

R(1)

be used as a system reset. It is active HIGH, synchronized
with the processor clock, and lasts an integer number of
clock periods corresponding to the length of the RES
Reset goes inactive 2 clockout periods after RES
inactive. When tied to the TEST
the processor into enhanced mode. RESET is not floated
during bus hold.

X1 I A(E) Crystal Inputs X1 and X2 provide external connections for a

X2 O H(Q)

R(Q)

fundamental mode or third overtone parallel resonant crystal
for the internal oscillator. X1 can connect to an external
clock instead of a crystal. In this case, minimize the
capacitance on X2. The input or oscillator frequency is
internally divided by two to generate the clock signal
(CLKOUT).

CLKOUT O H(Q) Clock Output provides the system with a 50% duty cycle

R(Q)

waveform. All device pin timings are specified relative to
CLKOUT. CLKOUT is active during reset and bus hold.

RES I A(L) An active RES causes the processor to immediately

terminate its present activity, clear the internal logic, and
enter a dormant state. This signal may be asynchronous to
the clock. The processor begins fetching instructions
approximately 6(/2 clock cycles after RES
For proper initialization, V
and the clock signal must be stable for more than 4 clocks
with RES

held LOW. RES is internally synchronized. This
input is provided with a Schmitt-trigger to facilitate power-on
RES

generation via an RC network.

TEST/BUSY I A(E) The TEST pin is sampled during and after reset to determine
(TEST

)

whether the processor is to enter Compatible or Enhanced
Mode. Enhanced Mode requires TEST to be HIGH on the
rising edge of RES and LOW four CLKOUT cycles later. Any
other combination will place the processor in Compatible
Mode. During power-up, active RES

/BUSY as an input. A weak internal pullup ensures a

TEST
HIGH state when the input is not externally driven.

TEST

ÐIn Compatible Mode this pin is configured to operate
as TEST
TEST

. This pin is examined by the WAIT instruction. If the

input is HIGH when WAIT execution begins, instruction
execution will suspend. TEST will be resampled every five
clocks until it goes LOW, at which time execution will
resume. If interrupts are enabled while the processor is
waiting for TEST

BUSY (80C186XL Only)ÐIn Enhanced Mode, this pin is
configured to operate as BUSY. The BUSY input is used to
notify the 80C186XL of Math Coprocessor activity. Floating
point instructions executing in the 80C186XL sample the
BUSY pin to determine when the Math Coprocessor is ready
to accept a new command. BUSY is active HIGH.

Pin Description

/BUSY pin, RESET forces

must be within specifications

CC

is required to configure

, interrupts will be serviced.

signal.

goes

is returned HIGH.

NOTE:

Pin names in parentheses apply to the 80C188XL.

10

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

TMR IN 0 I A(L) Timer Inputs are used either as clock or control signals,
TMR IN 1 A(E)

depending upon the programmed timer mode. These
inputs are active HIGH (or LOW-to-HIGH transitions are
counted) and internally synchronized. Timer Inputs must
be tied HIGH when not being used as clock or retrigger
inputs.

TMR OUT 0 O H(Q) Timer outputs are used to provide single pulse or
TMR OUT 1 R(1)

continuous waveform generation, depending upon the
timer mode selected. These outputs are not floated
during a bus hold.

DRQ0 I A(L) DMA Request is asserted HIGH by an external device
DRQ1

when it is ready for DMA Channel 0 or 1 to perform a
transfer. These signals are level-triggered and internally
synchronized.

NMI I A(E) The Non-Maskable Interrupt input causes a Type 2

interrupt. An NMI transition from LOW to HIGH is
latched and synchronized internally, and initiates the
interrupt at the next instruction boundary. NMI must be
asserted for at least one CLKOUT period. The Non­Maskable Interrupt cannot be avoided by programming.

INT0 I A(E) Maskable Interrupt Requests can be requested by
INT1/SELECT

INT2/INTA0
INT3/INTA1

A(L)

I/O A(E) H(1)

/IRQ A(L) R(Z)

activating one of these pins. When configured as inputs,
these pins are active HIGH. Interrupt Requests are
synchronized internally. INT2 and INT3 may be
configured to provide active-LOW interrupt­acknowledge output signals. All interrupt inputs may be
configured to be either edge- or level-triggered. To
ensure recognition, all interrupt requests must remain
active until the interrupt is acknowledged. When Slave
Mode is selected, the function of these pins changes
(see Interrupt Controller section of this data sheet).

A19/S6 O H(Z) Address Bus Outputs and Bus Cycle Status (3 – 6)
A18/S5 R(Z)
A17/S4
A16/S3 During T
(A8–A15)

indicate the four most significant address bits during T
These signals are active HIGH.

2,T3,TW

a CPU-initiated bus cycle or HIGH to indicate a DMA­initiated or refresh bus cycle. During the same T-states,
S3, S4 and S5 are always LOW. On the 80C188XL,
A15–A8 provide valid address information for the entire
bus cycle.

AD0–AD15 I/O S(L) H(Z) Address/Data Bus signals constitute the time
(AD0–AD7) R(Z)

multiplexed memory or I/O address (T1) and data (T2,

and T4) bus. The bus is active HIGH. For the

T

3,TW

80C186XL, A
the data bus, pins D
when a byte is to be transferred onto the lower portion
of the bus in memory or I/O operations.

Pin Description

and T4, the S6 pin is LOW to indicate

is analogous to BHE for the lower byte of

0

through D0. It is LOW during T

7

1

.

1

NOTE:

Pin names in parentheses apply to the 80C188XL.

11

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

BHE O H(Z) The BHE (Bus High Enable) signal is analogous to A0 in that it is

) R(Z)

(RFSH

used to enable data on to the most significant half of the data bus,
pins D15 –D8. BHE will be LOW during T1when the upper byte is
transferred and will remain LOW through T
need to be latched. On the 80C188XL, RFSH
indicate a refresh bus cycle.

In Enhanced Mode, BHE
refresh cycles. A refresh cycle is indicated by both BHE
A0 being HIGH.

80C186XL BHE and A0 Encodings

BHE A0

Value Value

0 0 Word Transfer
0 1 Byte Transfer on upper half of data bus

(D15–D8)
1 0 Byte Transfer on lower half of data bus (D
1 1 Refresh

ALE/QS0 O H(0) Address Latch Enable/Queue Status 0 is provided by the processor

to latch the address. ALE is active HIGH, with addresses guaranteed

R(0)

valid on the trailing edge.

WR/QS1 O H(Z) Write Strobe/Queue Status 1 indicates that the data on the bus is to

be written into a memory or an I/O device. It is active LOW. When

R(Z)

the processor is in Queue Status Mode, the ALE/QS0 and WR
pins provide information about processor/instruction queue
interaction.

QS1 QS0 Queue Operation

0 0 No queue operation
0 1 First opcode byte fetched from the queue
1 1 Subsequent byte fetched from the queue
1 0 Empty the queue

RD/QSMD O H(Z) Read Strobe is an active LOW signal which indicates that the

processor is performing a memory or I/O read cycle. It is guaranteed

R(1)

not to go LOW before the A/D bus is floated. An internal pull-up
ensures that RD

/QSMD is HIGH during RESET. Following RESET
the pin is sampled to determine whether the processor is to provide
ALE, RD

, and WR, or queue status information. To enable Queue

Status Mode, RD

ARDY I A(L) Asynchronous Ready informs the processor that the addressed

S(L)

memory space or I/O device will complete a data transfer. The
ARDY pin accepts a rising edge that is asynchronous to CLKOUT
and is active HIGH. The falling edge of ARDY must be synchronized
to the processor clock. Connecting ARDY HIGH will always assert
the ready condition to the CPU. If this line is unused, it should be tied
LOW to yield control to the SRDY pin.

Pin Description

and TW. BHE does not

3

is asserted LOW to

(RFSH) will also be used to signify DRAM

Function

must be connected to GND.

(RFSH) and

7–D0

/QS1

)

NOTE:

Pin names in parentheses apply to the 80C188XL.

12

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

SRDY I S(L) Ð Synchronous Ready informs the processor that the addressed

memory space or I/O device will complete a data transfer. The
SRDY pin accepts an active-HIGH input synchronized to CLKOUT.
The use of SRDY allows a relaxed system timing over ARDY. This
is accomplished by elimination of the one-half clock cycle required
to internally synchonize the ARDY input signal. Connecting SRDY
high will always assert the ready condition to the CPU. If this line is
unused, it should be tied LOW to yield control to the ARDY pin.

LOCK O Ð H(Z) LOCK output indicates that other system bus masters are not to

R(Z)

gain control of the system bus. LOCK
signal is requested by the LOCK prefix instruction and is activated
at the beginning of the first data cycle associated with the
instruction immediately following the LOCK prefix. It remains active
until the completion of that instruction. No instruction prefetching
will occur while LOCK

S0 O Ð H(Z) Bus cycle status S0–S2 are encoded to provide bus-transaction
S1

R(1)

information:

S2

S2 S1 S0 Bus Cycle Initiated

0 0 0 Interrupt Acknowledge
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 Halt
1 0 0 Instruction Fetch
1 0 1 Read Data from Memory
1 1 0 Write Data to Memory
1 1 1 Passive (no bus cycle)

S2 may be used as a logical M/IO indicator, and S1 as a DT/R
indicator.

HOLD I A(L) Ð HOLD indicates that another bus master is requesting the local bus.

HLDA O Ð H(1)

R(0)

The HOLD input is active HIGH. The processor generates HLDA
(HIGH) in response to a HOLD request. Simultaneous with the
issuance of HLDA, the processor will float the local bus and control
lines. After HOLD is detected as being LOW, the processor will
lower HLDA. When the processor needs to run another bus cycle, it
will again drive the local bus and control lines.

In Enhanced Mode, HLDA will go low when a DRAM refresh cycle
is pending in the processor and an external bus master has control
of the bus. It will be up to the external master to relinquish the bus
by lowering HOLD so that the processor may execute the refresh
cycle.

Pin Description

is active LOW. The LOCK

is asserted.

Bus Cycle Status Information

NOTE:

Pin names in parentheses apply to the 80C188XL.

13

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

UCS I/O A(L) H(1) Upper Memory Chip Select is an active LOW output

R(WH)

whenever a memory reference is made to the defined
upper portion (1K – 256K block) of memory. The
address range activating UCS
programmable.

UCS and LCS are sampled upon the rising edge of
RES

. If both pins are held low, the processor will enter
ONCE Mode. In ONCE Mode all pins assume a high
impedance state and remain so until a subsequent
RESET. UCS
during RESET to ensure that the processor does not
enter ONCE Mode inadvertently.

LCS I/O A(L) H(1) Lower Memory Chip Select is active LOW whenever a

R(WH)

memory reference is made to the defined lower portion
(1K–256K) of memory. The address range activating
LCS

is software programmable.

UCS

and LCS

RES

. If both pins are held low, the processor will enter
ONCE Mode. In ONCE Mode all pins assume a high
impedance state and remain so until a subsequent
RESET. LCS
only during RESET to ensure that the processor does
not enter ONCE mode inadvertently.

MCS0/PEREQ I/O A(L) H(1) Mid-Range Memory Chip Select signals are active LOW
MCS1

/ERROR R(WH)

MCS2

O H(1)

MCS3/NPS R(1)

when a memory reference is made to the defined mid­range portion of memory (8K–512K). The address
ranges activating MCS0 – 3

On the 80C186XL, in Enhanced Mode, MCS0
a PEREQ input (Processor Extension Request). When
connected to the Math Coprocessor, this input is used
to signal the 80C186XL when to make numeric data
transfers to and from the coprocessor. MCS3 becomes
NPS

(Numeric Processor Select) which may only be
activated by communication to the 80C187. MCS1
becomes ERROR in Enhanced Mode and is used to
signal numerics coprocessor errors.

PCS0 O H(1) Peripheral Chip Select signals 0–4 are active LOW
PCS1
PCS2
PCS3
PCS4

R(1)

when a reference is made to the defined peripheral
area (64 Kbyte I/O or 1 MByte memory space). The
address ranges activating PCS0 – 4 are software
programmable.

PCS5/A1 O H(1)/H(X) Peripheral Chip Select 5 or Latched A1 may be

R(1)

programmed to provide a sixth peripheral chip select, or
to provide an internally latched A1 signal. The address
range activating PCS5

/A1 does not float during bus HOLD. When

PCS5
programmed to provide latched A1, this pin will retain
the previously latched value during HOLD.

Pin Description

is software

has a weak internal pullup that is active

are sampled upon the rising edge of

has a weak internal pullup that is active

are software programmable.

becomes

is software-programmable.

NOTE:

Pin names in parentheses apply to the 80C188XL.

14

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

PCS6/A2 O Ð H(1)/H(X) Peripheral Chip Select 6 or Latched A2 may be programmed

R(1)

to provide a seventh peripheral chip select, or to provide an
internally latched A2 signal. The address range activating
PCS6

is software-programmable. PCS6/A2 does not float
during bus HOLD. When programmed to provide latched A2,
this pin will retain the previously latched value during HOLD.

DT/R O Ð H(Z) Data Transmit/Receive controls the direction of data flow

R(Z)

through an external data bus transceiver. When LOW, data is
transferred to the procesor. When HIGH the processor
places write data on the data bus.

DEN O Ð H(Z) Data Enable is provided as a data bus transceiver output

R(1,Z)

enable. DEN is active LOW during each memory and I/O
access (including 80C187 access). DEN

changes state. During RESET, DEN is driven HIGH for

DT/R
one clock, then floated.

N.C. Ð Ð Ð Not connected. To maintain compatibility with future

products, do not connect to these pins.

NOTE:

Pin names in parentheses apply to the 80C188XL.

Pin Description

is HIGH whenever

15