INTEL 80C186XL, 80C188XL User Manual

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16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186XL/80C188XL

Y

Low Power, Fully Static Versions of
80C186/80C188

Y

Operation Modes:
Ð Enhanced Mode

Ð DRAM Refresh Control Unit
Ð Power-Save Mode
Ð Direct Interface to 80C187

(80C186XL Only)

Ð Compatible Mode

Ð NMOS 80186/80188 Pin-for-Pin

Replacement for Non-Numerics
Applications

Y

Integrated Feature Set
Ð Static, Modular CPU
Ð Clock Generator
Ð 2 Independent DMA Channels
Ð Programmable Interrupt Controller
Ð 3 Programmable 16-Bit Timers
Ð Dynamic RAM Refresh Control Unit
Ð Programmable Memory and

Peripheral Chip Select Logic

Ð Programmable Wait State Generator

Y

Completely Object Code Compatible
with Existing 8086/8088 Software and
Has 10 Additional Instructions over
8086/8088

Y

Speed Versions Available
Ð 25 MHz (80C186XL25/80C188XL25)
Ð 20 MHz (80C186XL20/80C188XL20)
Ð 12 MHz (80C186XL12/80C188XL12)

Y

Direct Addressing Capability to
1 MByte Memory and 64 Kbyte I/O

Y

Available in 68-Pin:
Ð Plastic Leaded Chip Carrier (PLCC)
Ð Ceramic Pin Grid Array (PGA)
Ð Ceramic Leadless Chip Carrier

(JEDEC A Package)

Y

Available in 80-Pin:
Ð Quad Flat Pack (EIAJ)
Ð Shrink Quad Flat Pack (SGFP)

Y

Available in Extended Temperature
Range (

b

40§Ctoa85§C)

Ð Local Bus Controller
Ð Power-Save Mode
Ð System-Level Testing Support (High

Impedance Test Mode)

The Intel 80C186XL is a Modular Core re-implementation of the 80C186 microprocessor. It offers higher speed
and lower power consumption than the standard 80C186 but maintains 100% clock-for-clock functional com­patibility. Packaging and pinout are also identical.

272431-1

*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

COPYRIGHT

©INTELCORPORATION,2002

June, 2002

OrderNumber:272431-005

80C186XL/80C188XL

16-Bit High-Integration Embedded Processors

CONTENTS PAGE

INTRODUCTION ААААААААААААААААААААААААААА 4

80C186XL CORE ARCHITECTURE АААААААА 4

80C186XL Clock Generator АААААААААААААААА 4
Bus Interface Unit АААААААААААААААААААААААААА 5

80C186XL PERIPHERAL

ARCHITECTURE АААААААААААААААААААААААА 5

Chip-Select/Ready Generation Logic ААААААА 5
DMA Unit АААААААААААААААААААААААААААААААААА 6
Timer/Counter Unit АААААААААААААААААААААААА 6
Interrupt Control Unit ААААААААААААААААААААААА 6
Enhanced Mode Operation ААААААААААААААААА 6
Queue-Status Mode АААААААААААААААААААААААА 6
DRAM Refresh Control Unit АААААААААААААААА 7
Power-Save Control АААААААААААААААААААААААА 7
Interface for 80C187 Math Coprocessor

(80C186XL Only) АААААААААААААААААААААААА 7

ONCE Test Mode АААААААААААААААААААААААААА 7

PACKAGE INFORMATION АААААААААААААААА 8

Pin Descriptions АААААААААААААААААААААААААААА 8
80C186XL/80C188XL Pinout

Diagrams

ELECTRICAL SPECIFICATIONS ААААААААА 22

Absolute Maximum Ratings ААААААААААААААА 22

DC SPECIFICATIONS АААААААААААААААААААА 22

Power Supply Current ААААААААААААААААААААА 23

ААААААААААААААААААААААААААААААА 16

CONTENTS PAGE

AC SPECIFICATIONS АААААААААААААААААААА 24

Major Cycle Timings (Read Cycle) ААААААААА 24
Major Cycle Timings (Write Cycle) ААААААААА 26
Major Cycle Timings (Interrupt

Acknowledge Cycle) АААААААААААААААААААА 27
Software Halt Cycle Timings ААААААААААААААА 28
Clock Timings ААААААААААААААААААААААААААААА 29
Ready, Peripheral and Queue Status

Timings
Reset and Hold/HLDA Timings АААААААААААА 31

AC TIMING WAVEFORMS ААААААААААААААА 36

AC CHARACTERISTICS ААААААААААААААААА 37

EXPLANATION OF THE AC

SYMBOLS

DERATING CURVES ААААААААААААААААААААА 40

80C186XL/80C188XL EXPRESS ААААААААА 41

80C186XL/80C188XL EXECUTION

TIMINGS ААААААААААААААААААААААААААААААА 41

INSTRUCTION SET SUMMARY АААААААААА 42

REVISION HISTORY ААААААААААААААААААААА 48

ERRATA ААААААААААААААААААААААААААААААААА 48

PRODUCT IDENTIFICATION ААААААААААААА 48

ААААААААААААААААААААААААААААААААА 30

АААААААААААААААААААААААААААААА 39

2

80C186XL/80C188XL

272431– 2

NOTE:

Pin names in parentheses applies to 80C188XL.

Figure 1. 80C186XL/80C188XL Block Diagram

3

80C186XL/80C188XL

(2a)

272431– 3

Figure 2. Oscillator Configurations (see text)

INTRODUCTION

Unless specifically noted, all references to the
80C186XL apply to the 80C188XL. References to
pins that differ between the 80C186XL and the
80C188XL are given in parentheses.

The following Functional Description describes the
base architecture of the 80C186XL. The 80C186XL
is a very high integration 16-bit microprocessor. It
combines 15 –20 of the most common microproces­sor system components onto one chip. The
80C186XL is object code compatible with the
8086/8088 microprocessors and adds 10 new in­struction types to the 8086/8088 instruction set.

The 80C186XL has two major modes of operation,
Compatible and Enhanced. In Compatible Mode the
80C186XL is completely compatible with NMOS
80186, with the exception of 8087 support. The En­hanced mode adds three new features to the system
design. These are Power-Save control, Dynamic
RAM refresh, and an asynchronous Numerics Co­processor interface (80C186XL only).

272431– 4

(2b)

Note 1:

XTAL Frequency L1 Value

20 MHz 12.0 mH
25 MHz 8.2 mH
32 MHz 4.7 mH

40 MHz 3.0 mH
LC network is only required when using a third
overtone crystal.

g

20%

g

20%

g

20%

g

20%

The 80C186XL oscillator circuit is designed to be
used either with a parallel resonant fundamental or
third-overtone mode crystal, depending upon the
frequency range of the application. This is used as
the time base for the 80C186XL.

The output of the oscillator is not directly available
outside the 80C186XL. The recommended crystal
configuration is shown in Figure 2b. When used in
third-overtone mode, the tank circuit is recommend­ed for stable operation. Alternately, the oscillator
may be driven from an external source as shown in
Figure 2a.

The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide by two counter. This counter is
used to drive all internal phase clocks and the exter­nal CLKOUT signal. CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys­tem components. All AC Timings are referenced to
CLKOUT.

Intel recommends the following values for crystal se­lection parameters.

80C186XL CORE ARCHITECTURE

80C186XL Clock Generator

The 80C186XL provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divide­by-two counter, synchronous and asynchronous
ready inputs, and reset circuitry.

4

Temperature Range: Application Specific

ESR (Equivalent Series Resistance): 60X max

(Shunt Capacitance of Crystal): 7.0 pF max

C

0

C1(Load Capacitance): 20 pFg2pF

Drive Level: 2 mW max

80C186XL/80C188XL

Bus Interface Unit

The 80C186XL provides a local bus controller to
generate the local bus control signals. In addition, it
employs a HOLD/HLDA protocol for relinquishing
the local bus to other bus masters. It also provides
outputs that can be used to enable external buffers
and to direct the flow of data on and off the local
bus.

The bus controller is responsible for generating 20
bits of address, read and write strobes, bus cycle
status information and data (for write operations) in­formation. It is also responsible for reading data
from the local bus during a read operation. Synchro­nous and asynchronous ready input pins are provid­ed to extend a bus cycle beyond the minimum four
states (clocks).

The 80C186XL bus controller also generates two
control signals (DEN
external transceiver chips. This capability allows the
addition of transceivers for simple buffering of the
multiplexed address/data bus.

During RESET the local bus controller will perform
the following action:

Drive DEN

#

cle, then float them.

Drive S0–S2 to the inactive state (all HIGH) and

#

then float.

Drive LOCK HIGH and then float.

#

Float AD0 – 15 (AD0–8), A16 – 19 (A9–A19), BHE

#

(RFSH), DT/R.

Drive ALE LOW

#

Drive HLDA LOW.

#

RD

/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/

ERROR

and TEST/BUSY pins have internal pullup
devices which are active while RES
cessive loading or grounding certain of these pins
causes the 80C186XL to enter an alternative mode
of operation:

RD/QSMD low results in Queue Status Mode.

#

UCS and LCS low results in ONCE Mode.

#

TEST/BUSY low (and high later) results in En-

#

hanced Mode.

and DT/R) when interfacing to

,RDand WR HIGH for one clock cy-

is applied. Ex-

spond to bus cycles. An offset map of the 256-byte
control register block is shown in Figure 3.

Chip-Select/Ready Generation Logic

The 80C186XL contains logic which provides
programmable chip-select generation for both mem­ories and peripherals. In addition, it can be
programmed to provide READY (or WAIT state) gen­eration. It can also provide latched address bits A1
and A2. The chip-select lines are active for all mem­ory and I/O cycles in their programmed areas,
whether they be generated by the CPU or by the
integrated DMA unit.

The 80C186XL provides 6 memory chip select out­puts for 3 address areas; upper memory, lower
memory, and midrange memory. One each is provid­ed for upper memory and lower memory, while four
are provided for midrange memory.

OFFSET

Relocation Register FEH

DMA Descriptors Channel 1

DMA Descriptors Channel 0

Chip-Select Control Registers

Time 2 Control Registers

Time 1 Control Registers

Time 0 Control Registers

Interrupt Controller Registers

DAH

D0H

CAH

C0H

A8H

A0H

66H

60H

5EH

58H

56H

50H

3EH

20H

80C186XL PERIPHERAL
ARCHITECTURE

All the 80C186XL integrated peripherals are con­trolled by 16-bit registers contained within an inter­nal 256-byte control block. The control block may be
mapped into either memory or I/O space. Internal
logic will recognize control block addresses and re-

Figure 3. Internal Register Map

The 80C186XL provides a chip select, called UCS
for the top of memory. The top of memory is usually
used as the system memory because after reset the
80C186XL begins executing at memory location
FFFF0H.

,

5

80C186XL/80C188XL

The 80C186XL provides a chip select for low memo­ry called LCS
interrupt vector table, starting at location 00000H.

The 80C186XL provides four MCS
active within a user-locatable memory block. This
block can be located within the 80C186XL 1 Mbyte
memory address space exclusive of the areas de­fined by UCS
size of this memory block are programmable.

The 80C186XL can generate chip selects for up to
seven peripheral devices. These chip selects are ac­tive for seven contiguous blocks of 128 bytes above
a programmable base address. The base address
may be located in either memory or I/O space.

The 80C186XL can generate a READY signal inter­nally for each of the memory or peripheral CS
The number of WAIT states to be inserted for each
peripheral or memory is programmable to provide
0–3 wait states for all accesses to the area for
which the chip select is active. In addition, the
80C186XL may be programmed to either ignore ex­ternal READY for each chip-select range individually
or to factor external READY with the integrated
ready generator.

Upon RESET, the Chip-Select/Ready Logic will per­form the following actions:

All chip-select outputs will be driven HIGH.

#

Upon leaving RESET, the UCS line will be pro-

#

grammed to provide chip selects to a 1K block
with the accompanying READY control bits set at
011 to insert 3 wait states in conjunction with ex­ternal READY (i.e., UMCS resets to FFFBH).

No other chip select or READY control registers

#

have any predefined values after RESET. They
will not become active until the CPU accesses
their control registers.

. The bottom of memory contains the

lines which are

and LCS. Both the base address and

lines.

DMA Unit

The 80C186XL DMA controller provides two inde­pendent high-speed DMA channels. Data transfers
can occur between memory and I/O spaces (e.g.,
Memory to I/O) or within the same space (e.g.,
Memory to Memory or I/O to I/O). Data can be
transferred either in bytes (8 bits) or in words (16
bits) to or from even or odd addresses.

mum of 8 clocks), one cycle to fetch data and the
other to store data.

Timer/Counter Unit

The 80C186XL provides three internal 16-bit pro­grammable timers. Two of these are highly flexible
and are connected to four external pins (2 per timer).
They can be used to count external events, time ex­ternal events, generate nonrepetitive waveforms,
etc. The third timer is not connected to any external
pins, and is useful for real-time coding and time de­lay applications. In addition, the third timer can be
used as a prescaler to the other two, or as a DMA
request source.

Interrupt Control Unit

The 80C186XL can receive interrupts from a number
of sources, both internal and external. The
80C186XL has 5 external and 2 internal interrupt
sources (Timer/Couners and DMA). The internal in­terrupt controller serves to merge these requests on
a priority basis, for individual service by the CPU.

Enhanced Mode Operation

In Compatible Mode the 80C186XL operates with all
the features of the NMOS 80186, with the exception
of 8087 support (i.e. no math coprocessing is possi­ble in Compatible Mode). Queue-Status information
is still available for design purposes other than 8087
support.

All the Enhanced Mode features are completely
masked when in Compatible Mode. A write to any of
the Enhanced Mode registers will have no effect,
while a read will not return any valid data.

In Enhanced Mode, the 80C186XL will operate with
Power-Save, DRAM refresh, and numerics coproc­essor support (80C186XL only) in addition to all the
Compatible Mode features.

If connected to a math coprocessor (80C186XL
only), this mode will be invoked automatically. With­out an NPX, this mode can be entered by tying the
RESET output signal from the 80C186XL to the
TEST

/BUSY input.

Only byte transfers are possible on the 80C188XL.

NOTE:

Each DMA channel maintains both a 20-bit source
and destination pointer which can be optionally in­cremented or decremented after each data transfer
(by one or two depending on byte or word transfers).
Each data transfer consumes 2 bus cycles (a mini-

6

Queue-Status Mode

The queue-status mode is entered by strapping the

pin low. RD is sampled at RESET and if LOW,

RD
the 80C186XL will reconfigure the ALE and WR
to be QS0 and QS1 respectively. This mode is avail­able on the 80C186XL in both Compatible and En­hanced Modes.

pins

80C186XL/80C188XL

DRAM Refresh Control Unit

The Refresh Control Unit (RCU) automatically gen­erates DRAM refresh bus cycles. The RCU operates
only in Enhanced Mode. After a programmable peri­od of time, the RCU generates a memory read re­quest to the BIU. If the address generated during a
refresh bus cycle is within the range of a properly
programmed chip select, that chip select will be acti­vated when the BIU executes the refresh bus cycle.

Power-Save Control

The 80C186XL, when in Enhanced Mode, can enter
a power saving state by internally dividing the proc­essor clock frequency by a programmable factor.
This divided frequency is also available at the
CLKOUT pin.

All internal logic, including the Refresh Control Unit
and the timers, have their clocks slowed down by
the division factor. To maintain a real time count or a
fixed DRAM refresh rate, these peripherals must be
re-programmed when entering and leaving the pow­er-save mode.

Interface for 80C187 Math
Coprocessor (80C186XL Only)

In Enhanced Mode, three of the mid-range memory
chip selects are redefined according to Table 1 for
use with the 80C187. The fourth chip select, MCS2

functions as in compatible mode, and may be pro­grammed for activity with ready logic and wait states
accordingly. As in Compatible Mode, MCS2
tion for one-fourth a programmed block size.

Table 1. MCS

Compatible

Mode

MCS0 PEREQ Processor Extension Request
MCS1
MCS2
MCS3

ERROR NPX Error
MCS2 Mid-Range Chip Select
NPS Numeric Processor Select

Assignments

Enhanced Mode

will func-

ONCE Test Mode

To facilitate testing and inspection of devices when
fixed into a target system, the 80C186XL has a test
mode available which allows all pins to be placed in
a high-impedance state. ONCE stands for ‘‘ON Cir­cuit Emulation’’. When placed in this mode, the
80C186XL will put all pins in the high-impedance
state until RESET.

The ONCE mode is selected by tying the UCS
the LCS
pled on the low-to-high transition of the RES
The UCS
up resistors similar to the RD
to guarantee ONCE Mode is not entered inadver­tently during normal operation. LCS
be held low at least one clock after RES
to guarantee entrance into ONCE Mode.

LOW during RESET. These pins are sam-

and the LCS pins have weak internal pull-

and TEST/BUSY pins

and UCS must

and

pin.

goes high

7

80C186XL/80C188XL

PACKAGE INFORMATION

This section describes the pin functions, pinout and
thermal characteristics for the 80C186XL in the
Quad Flat Pack (QFP), Plastic Leaded Chip Carrier
(PLCC), Leadless Chip Carrier (LCC) and the Shrink
Quad Flat Pack (SQFP). For complete package
specifications and information, see the Intel Packag­ing Outlines and Dimensions Guide (Order Number:

231369).

Pin Descriptions

Each pin or logical set of pins is described in Table

3. There are four columns for each entry in the Pin
Description Table. The following sections describe
each column.

Column 1: Pin Name

In this column is a mnemonic that de­scribes the pin function. Negation of the
signal name (i.e., RESIN
the signal is active low.

Column 2: Pin Type

A pin may be either power (P), ground
(G), input only (I), output only (O) or in­put/output (I/O). Please note that some
pins have more than one function.

Column 3: Input Type (for I and I/O types only)

These are two different types of input
pins on the 80C186XL: asynchronous
and synchronous. Asynchronous pins
require that setup and hold times be met
only to

guarantee recognition.

nous input pins require that the setup
and hold times be met to

) implies that

Synchro-

guarantee

proper operation.

a setup or hold on an asynchronous pin
will result in something minor (i.e., a tim­er count will be missed) whereas miss­ing a setup or hold on a synchronous pin
result in system failure (the system will
‘‘lock up’’).

An input pin may also be edge or level
sensitive.

Column 4: Output States (for O and I/O types

only)

The state of an output or I/O pin is de­pendent on the operating mode of the
device. There are four modes of opera­tion that are different from normal active
mode: Bus Hold, Reset, Idle Mode, Pow­erdown Mode. This column describes
the output pin state in each of these
modes.

The legend for interpreting the information in the Pin
Descriptions is shown in Table 2.

As an example, please refer to the table entry for
AD7:0. The ‘‘I/O’’ signifies that the pins are bidirec­tional (i.e., have both an input and output function).
The ‘‘S’’ indicates that, as an input the signal must
be synchronized to CLKOUT for proper operation.
The ‘‘H(Z)’’ indicates that these pins will float while
the processor is in the Hold Acknowledge state.
R(Z) indicates that these pins will float while RESIN
is low.

All pins float while the processor is in the ONCE
Mode (with the exception of X2).

Stated simply, missing

8

Table 2. Pin Description Nomenclature

Symbol Description

P Power Pin (applyaVCCvoltage)
G Ground (connect to V

SS

)
I Input only pin
O Output only pin
I/O Input/Output pin

S(E) Synchronous, edge sensitive
S(L) Synchronous, level sensitive
A(E) Asynchronous, edge sensitive
A(L) Asynchronous, level sensitive

H(1) Output driven to VCCduring bus hold
H(0) Output driven to V

during bus hold

SS

H(Z) Output floats during bus hold
H(Q) Output remains active during bus hold
H(X) Output retains current state during bus hold

R(WH) Output weakly held at VCCduring reset
R(1) Output driven to V
R(0) Output driven to V

during reset

CC

during reset

SS

R(Z) Output floats during reset
R(Q) Output remains active during reset
R(X) Output retains current state during reset

80C186XL/80C188XL

9

80C186XL/80C188XL

Table 3. Pin Descriptions

Pin Pin Input Output

Name Type Type States

V

CC

V

SS

P System Power:a5 volt power supply.

G System Ground.

RESET O H(0) RESET Output indicates that the CPU is being reset, and can

R(1)

be used as a system reset. It is active HIGH, synchronized
with the processor clock, and lasts an integer number of
clock periods corresponding to the length of the RES
Reset goes inactive 2 clockout periods after RES
inactive. When tied to the TEST
the processor into enhanced mode. RESET is not floated
during bus hold.

X1 I A(E) Crystal Inputs X1 and X2 provide external connections for a

X2 O H(Q)

R(Q)

fundamental mode or third overtone parallel resonant crystal
for the internal oscillator. X1 can connect to an external
clock instead of a crystal. In this case, minimize the
capacitance on X2. The input or oscillator frequency is
internally divided by two to generate the clock signal
(CLKOUT).

CLKOUT O H(Q) Clock Output provides the system with a 50% duty cycle

R(Q)

waveform. All device pin timings are specified relative to
CLKOUT. CLKOUT is active during reset and bus hold.

RES I A(L) An active RES causes the processor to immediately

terminate its present activity, clear the internal logic, and
enter a dormant state. This signal may be asynchronous to
the clock. The processor begins fetching instructions
approximately 6(/2 clock cycles after RES
For proper initialization, V
and the clock signal must be stable for more than 4 clocks
with RES

held LOW. RES is internally synchronized. This
input is provided with a Schmitt-trigger to facilitate power-on
RES

generation via an RC network.

TEST/BUSY I A(E) The TEST pin is sampled during and after reset to determine
(TEST

)

whether the processor is to enter Compatible or Enhanced
Mode. Enhanced Mode requires TEST to be HIGH on the
rising edge of RES and LOW four CLKOUT cycles later. Any
other combination will place the processor in Compatible
Mode. During power-up, active RES

/BUSY as an input. A weak internal pullup ensures a

TEST
HIGH state when the input is not externally driven.

TEST

ÐIn Compatible Mode this pin is configured to operate
as TEST
TEST

. This pin is examined by the WAIT instruction. If the

input is HIGH when WAIT execution begins, instruction
execution will suspend. TEST will be resampled every five
clocks until it goes LOW, at which time execution will
resume. If interrupts are enabled while the processor is
waiting for TEST

BUSY (80C186XL Only)ÐIn Enhanced Mode, this pin is
configured to operate as BUSY. The BUSY input is used to
notify the 80C186XL of Math Coprocessor activity. Floating
point instructions executing in the 80C186XL sample the
BUSY pin to determine when the Math Coprocessor is ready
to accept a new command. BUSY is active HIGH.

Pin Description

/BUSY pin, RESET forces

must be within specifications

CC

is required to configure

, interrupts will be serviced.

signal.

goes

is returned HIGH.

NOTE:

Pin names in parentheses apply to the 80C188XL.

10

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

TMR IN 0 I A(L) Timer Inputs are used either as clock or control signals,
TMR IN 1 A(E)

depending upon the programmed timer mode. These
inputs are active HIGH (or LOW-to-HIGH transitions are
counted) and internally synchronized. Timer Inputs must
be tied HIGH when not being used as clock or retrigger
inputs.

TMR OUT 0 O H(Q) Timer outputs are used to provide single pulse or
TMR OUT 1 R(1)

continuous waveform generation, depending upon the
timer mode selected. These outputs are not floated
during a bus hold.

DRQ0 I A(L) DMA Request is asserted HIGH by an external device
DRQ1

when it is ready for DMA Channel 0 or 1 to perform a
transfer. These signals are level-triggered and internally
synchronized.

NMI I A(E) The Non-Maskable Interrupt input causes a Type 2

interrupt. An NMI transition from LOW to HIGH is
latched and synchronized internally, and initiates the
interrupt at the next instruction boundary. NMI must be
asserted for at least one CLKOUT period. The Non­Maskable Interrupt cannot be avoided by programming.

INT0 I A(E) Maskable Interrupt Requests can be requested by
INT1/SELECT

INT2/INTA0
INT3/INTA1

A(L)

I/O A(E) H(1)

/IRQ A(L) R(Z)

activating one of these pins. When configured as inputs,
these pins are active HIGH. Interrupt Requests are
synchronized internally. INT2 and INT3 may be
configured to provide active-LOW interrupt­acknowledge output signals. All interrupt inputs may be
configured to be either edge- or level-triggered. To
ensure recognition, all interrupt requests must remain
active until the interrupt is acknowledged. When Slave
Mode is selected, the function of these pins changes
(see Interrupt Controller section of this data sheet).

A19/S6 O H(Z) Address Bus Outputs and Bus Cycle Status (3 – 6)
A18/S5 R(Z)
A17/S4
A16/S3 During T
(A8–A15)

indicate the four most significant address bits during T
These signals are active HIGH.

2,T3,TW

a CPU-initiated bus cycle or HIGH to indicate a DMA­initiated or refresh bus cycle. During the same T-states,
S3, S4 and S5 are always LOW. On the 80C188XL,
A15–A8 provide valid address information for the entire
bus cycle.

AD0–AD15 I/O S(L) H(Z) Address/Data Bus signals constitute the time
(AD0–AD7) R(Z)

multiplexed memory or I/O address (T1) and data (T2,

and T4) bus. The bus is active HIGH. For the

T

3,TW

80C186XL, A
the data bus, pins D
when a byte is to be transferred onto the lower portion
of the bus in memory or I/O operations.

Pin Description

and T4, the S6 pin is LOW to indicate

is analogous to BHE for the lower byte of

0

through D0. It is LOW during T

7

1

.

1

NOTE:

Pin names in parentheses apply to the 80C188XL.

11

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

BHE O H(Z) The BHE (Bus High Enable) signal is analogous to A0 in that it is

) R(Z)

(RFSH

used to enable data on to the most significant half of the data bus,
pins D15 –D8. BHE will be LOW during T1when the upper byte is
transferred and will remain LOW through T
need to be latched. On the 80C188XL, RFSH
indicate a refresh bus cycle.

In Enhanced Mode, BHE
refresh cycles. A refresh cycle is indicated by both BHE
A0 being HIGH.

80C186XL BHE and A0 Encodings

BHE A0

Value Value

0 0 Word Transfer
0 1 Byte Transfer on upper half of data bus

(D15–D8)
1 0 Byte Transfer on lower half of data bus (D
1 1 Refresh

ALE/QS0 O H(0) Address Latch Enable/Queue Status 0 is provided by the processor

to latch the address. ALE is active HIGH, with addresses guaranteed

R(0)

valid on the trailing edge.

WR/QS1 O H(Z) Write Strobe/Queue Status 1 indicates that the data on the bus is to

be written into a memory or an I/O device. It is active LOW. When

R(Z)

the processor is in Queue Status Mode, the ALE/QS0 and WR
pins provide information about processor/instruction queue
interaction.

QS1 QS0 Queue Operation

0 0 No queue operation
0 1 First opcode byte fetched from the queue
1 1 Subsequent byte fetched from the queue
1 0 Empty the queue

RD/QSMD O H(Z) Read Strobe is an active LOW signal which indicates that the

processor is performing a memory or I/O read cycle. It is guaranteed

R(1)

not to go LOW before the A/D bus is floated. An internal pull-up
ensures that RD

/QSMD is HIGH during RESET. Following RESET
the pin is sampled to determine whether the processor is to provide
ALE, RD

, and WR, or queue status information. To enable Queue

Status Mode, RD

ARDY I A(L) Asynchronous Ready informs the processor that the addressed

S(L)

memory space or I/O device will complete a data transfer. The
ARDY pin accepts a rising edge that is asynchronous to CLKOUT
and is active HIGH. The falling edge of ARDY must be synchronized
to the processor clock. Connecting ARDY HIGH will always assert
the ready condition to the CPU. If this line is unused, it should be tied
LOW to yield control to the SRDY pin.

Pin Description

and TW. BHE does not

3

is asserted LOW to

(RFSH) will also be used to signify DRAM

Function

must be connected to GND.

(RFSH) and

7–D0

/QS1

)

NOTE:

Pin names in parentheses apply to the 80C188XL.

12

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

SRDY I S(L) Ð Synchronous Ready informs the processor that the addressed

memory space or I/O device will complete a data transfer. The
SRDY pin accepts an active-HIGH input synchronized to CLKOUT.
The use of SRDY allows a relaxed system timing over ARDY. This
is accomplished by elimination of the one-half clock cycle required
to internally synchonize the ARDY input signal. Connecting SRDY
high will always assert the ready condition to the CPU. If this line is
unused, it should be tied LOW to yield control to the ARDY pin.

LOCK O Ð H(Z) LOCK output indicates that other system bus masters are not to

R(Z)

gain control of the system bus. LOCK
signal is requested by the LOCK prefix instruction and is activated
at the beginning of the first data cycle associated with the
instruction immediately following the LOCK prefix. It remains active
until the completion of that instruction. No instruction prefetching
will occur while LOCK

S0 O Ð H(Z) Bus cycle status S0–S2 are encoded to provide bus-transaction
S1

R(1)

information:

S2

S2 S1 S0 Bus Cycle Initiated

0 0 0 Interrupt Acknowledge
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 Halt
1 0 0 Instruction Fetch
1 0 1 Read Data from Memory
1 1 0 Write Data to Memory
1 1 1 Passive (no bus cycle)

S2 may be used as a logical M/IO indicator, and S1 as a DT/R
indicator.

HOLD I A(L) Ð HOLD indicates that another bus master is requesting the local bus.

HLDA O Ð H(1)

R(0)

The HOLD input is active HIGH. The processor generates HLDA
(HIGH) in response to a HOLD request. Simultaneous with the
issuance of HLDA, the processor will float the local bus and control
lines. After HOLD is detected as being LOW, the processor will
lower HLDA. When the processor needs to run another bus cycle, it
will again drive the local bus and control lines.

In Enhanced Mode, HLDA will go low when a DRAM refresh cycle
is pending in the processor and an external bus master has control
of the bus. It will be up to the external master to relinquish the bus
by lowering HOLD so that the processor may execute the refresh
cycle.

Pin Description

is active LOW. The LOCK

is asserted.

Bus Cycle Status Information

NOTE:

Pin names in parentheses apply to the 80C188XL.

13

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

UCS I/O A(L) H(1) Upper Memory Chip Select is an active LOW output

R(WH)

whenever a memory reference is made to the defined
upper portion (1K – 256K block) of memory. The
address range activating UCS
programmable.

UCS and LCS are sampled upon the rising edge of
RES

. If both pins are held low, the processor will enter
ONCE Mode. In ONCE Mode all pins assume a high
impedance state and remain so until a subsequent
RESET. UCS
during RESET to ensure that the processor does not
enter ONCE Mode inadvertently.

LCS I/O A(L) H(1) Lower Memory Chip Select is active LOW whenever a

R(WH)

memory reference is made to the defined lower portion
(1K–256K) of memory. The address range activating
LCS

is software programmable.

UCS

and LCS

RES

. If both pins are held low, the processor will enter
ONCE Mode. In ONCE Mode all pins assume a high
impedance state and remain so until a subsequent
RESET. LCS
only during RESET to ensure that the processor does
not enter ONCE mode inadvertently.

MCS0/PEREQ I/O A(L) H(1) Mid-Range Memory Chip Select signals are active LOW
MCS1

/ERROR R(WH)

MCS2

O H(1)

MCS3/NPS R(1)

when a memory reference is made to the defined mid­range portion of memory (8K–512K). The address
ranges activating MCS0 – 3

On the 80C186XL, in Enhanced Mode, MCS0
a PEREQ input (Processor Extension Request). When
connected to the Math Coprocessor, this input is used
to signal the 80C186XL when to make numeric data
transfers to and from the coprocessor. MCS3 becomes
NPS

(Numeric Processor Select) which may only be
activated by communication to the 80C187. MCS1
becomes ERROR in Enhanced Mode and is used to
signal numerics coprocessor errors.

PCS0 O H(1) Peripheral Chip Select signals 0–4 are active LOW
PCS1
PCS2
PCS3
PCS4

R(1)

when a reference is made to the defined peripheral
area (64 Kbyte I/O or 1 MByte memory space). The
address ranges activating PCS0 – 4 are software
programmable.

PCS5/A1 O H(1)/H(X) Peripheral Chip Select 5 or Latched A1 may be

R(1)

programmed to provide a sixth peripheral chip select, or
to provide an internally latched A1 signal. The address
range activating PCS5

/A1 does not float during bus HOLD. When

PCS5
programmed to provide latched A1, this pin will retain
the previously latched value during HOLD.

Pin Description

is software

has a weak internal pullup that is active

are sampled upon the rising edge of

has a weak internal pullup that is active

are software programmable.

becomes

is software-programmable.

NOTE:

Pin names in parentheses apply to the 80C188XL.

14

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Pin Pin Input Output

Name Type Type States

PCS6/A2 O Ð H(1)/H(X) Peripheral Chip Select 6 or Latched A2 may be programmed

R(1)

to provide a seventh peripheral chip select, or to provide an
internally latched A2 signal. The address range activating
PCS6

is software-programmable. PCS6/A2 does not float
during bus HOLD. When programmed to provide latched A2,
this pin will retain the previously latched value during HOLD.

DT/R O Ð H(Z) Data Transmit/Receive controls the direction of data flow

R(Z)

through an external data bus transceiver. When LOW, data is
transferred to the procesor. When HIGH the processor
places write data on the data bus.

DEN O Ð H(Z) Data Enable is provided as a data bus transceiver output

R(1,Z)

enable. DEN is active LOW during each memory and I/O
access (including 80C187 access). DEN

changes state. During RESET, DEN is driven HIGH for

DT/R
one clock, then floated.

N.C. Ð Ð Ð Not connected. To maintain compatibility with future

products, do not connect to these pins.

NOTE:

Pin names in parentheses apply to the 80C188XL.

Pin Description

is HIGH whenever

15

80C186XL/80C188XL

Contacts Facing Up Contacts Facing Down

Pins Facing Up Pins Facing Down

Ceramic Leadless Chip Carrier (JEDEC Type A)

272431– 5

Ceramic Pin Grid Array

NOTE:

XXXXXXXXC indicates the Intel FPO number.

Figure 4. 80C186XL/80C188XL Pinout Diagrams

16

272431– 6

Shrink Quad Flat Pack

80C186XL/80C188XL

NOTE:

XXXXXXXXC indicates the Intel FPO number.

Figure 4. 80C186XL/80C188XL Pinout Diagrams (Continued)

272431– 22

17

80C186XL/80C188XL

Contacts Facing Up Contacts Facing Down

Plastic Leaded Chip Carrier

272431– 7

80-Pin Quad Flat Pack (EIAJ)

Contacts Contacts

Facing Up Facing Down

NOTE:

XXXXXXXXA indicates the Intel FPO number.

Figure 4. 80C186XL/80C288XL Pinout Diagrams (Continued)

18

272431– 8

Table 4. LCC/PLCC Pin Functions with Location

AD Bus

AD0 17
AD1 15
AD2 13
AD3 11
AD4 8
AD5 6
AD6 4
AD7 2
AD8 (A8) 16
AD9 (A9) 14
AD10 (A10) 12
AD11 (A11) 10
AD12 (A12) 7
AD13 (A13) 5

Bus Control

ALE/QS0 61
BHE

(RFSH)64
S0
S1
S2
RD/QSMD 62
WR

/QS1 63
ARDY 55
SRDY 49
DEN
DT/R
LOCK
HOLD 50
HLDA 51

AD14 (A14) 3
AD15 (A15) 1
A16/S3 68
A17/S4 67
A18/S5 66
A19/S6 65

NOTE:

Pin names in parentheses apply to the 80C188XL.

52
53
54

39
40
48

Processor Control

RES 24
RESET 57
X1 59
X2 58
CLKOUT 56
TEST/BUSY 47
NMI 46
INT0 45
INT1/SELECT
INT2/INTA0
INT3/INTA1

44
42
41

Power and Ground

V

CC

V

CC

V

SS

V

SS

43
26
60

80C186XL/80C188XL

I/O

UCS 34
LCS

MCS0/PEREQ 38
MCS1

/ERROR 37
MCS2 36
MCS3

/NPS 35

PCS0 25
PCS1
PCS2
PCS3
PCS4 30

/A1 31

PCS5

9

PCS6/A2 32

TMR IN 0 20
TMR IN 1 21
TMR OUT 0 22
TMR OUT 1 23

DRQ0 18
DRQ1 19

33

27
28
29

Table 5. LCC/PGA/PLCC Pin Locations with Pin Names

1 AD15 (A15)
2 AD7
3 AD14 (A14)
4 AD6
5 AD13 (A13)
6 AD5
7 AD12 (A12)
8 AD4
9V

CC

10 AD11 (A11)
11 AD3
12 AD10 (A10)
13 AD2
14 AD9 (A9)
15 AD1
16 AD8 (A8)
17 AD0

NOTE:

Pin names in parentheses apply to the 80C188XL.

18 DRQ0
19 DRQ1
20 TMR IN 0
21 TMR IN 1
22 TMR OUT 0
23 TMR OUT 1
24 RES
25 PCS0
26 V

SS

27 PCS1
28 PCS2
29 PCS3
30 PCS4
31 PCS5/A1
32 PCS6/A2
33 LCS
34 UCS

35 MCS3

/NPS
36 MCS2
37 MCS1/ERROR
38 MCS0/PEREQ
39 DEN
40 DT/R
41 INT3/INTA1
42 INT2/INTA0
43 V

CC

44 INT1/SELECT
45 INT0
46 NMI
47 TEST/BUSY
48 LOCK
49 SRDY
50 HOLD
51 HLDA

52 S0
53 S1
54 S2
55 ARDY
56 CLKOUT
57 RESET
58 X2
59 X1
60 V

SS

61 ALE/QS0
62 RD
63 WR
64 BHE

/QSMD

/QS1

(RFSH)
65 A19/S2
66 A18/S3
67 A17/S4
68 A16/S3

19

80C186XL/80C188XL

Table 6. QFP Pin Functions with Location

AD Bus

AD0 64
AD1 66
AD2 68
AD3 70
AD4 74
AD5 76
AD6 78
AD7 80
AD8 (A8) 65
AD9 (A9) 67
AD10 (A10) 69
AD11 (A11) 71
AD12 (A12) 75
AD13 (A13) 77
AD14 (A14) 79
AD15 (A15) 1
A16/S3 3
A17/S4 4
A18/S5 5
A19/S6 6

NOTE:

Pin names in parentheses apply to the 80C188XL.

1 AD15 (A15)
2 N.C.
3 A16/S3
4 A17/S4
5 A18/S5
6 A19/S6
7 BHE/(RFSH)
8WR/QS1
9RD

/QSMD
10 ALE/QS0
11 N.C.
12 V

SS

13 V

SS

14 N.C.
15 N.C.
16 X1
17 X2
18 RESET
19 CLKOUT
20 ARDY

Bus Control

ALE/QS0 10
BHE

(RFSH)7
S0
S1
S2
RD/QSMD 9
WR

/QS1 8
ARDY 20
SRDY 27
DEN 38
DT/R
LOCK
HOLD 26
HLDA 25

No Connection

N.C. 2
N.C. 11
N.C. 14
N.C. 15
N.C. 24
N.C. 43
N.C. 44
N.C. 62
N.C. 63

Table 7. QFP Pin Locations with Pin Names

21 S2
22 S1
23 S0
24 N.C.
25 HLDA
26 HOLD
27 SRDY
28 LOCK
29 TEST/BUSY
30 NMI
31 INT0
32 INT1/SELECT
33 V

CC

34 V

CC

35 INT2/INTA0
36 INT3/INTA1
37 DT/R
38 DEN
39 MCS0/PEREQ
40 MCS1

/ERROR

23
22
21

37
28

Processor Control

RES 55
RESET 18
X1 16
X2 17
CLKOUT 19
TEST/BUSY 29
NMI 30
INT0 31
INT1/SELECT
INT2/INTA0
INT3/INTA1

32
35
36

Power and Ground

V

CC

V

CC

V

CC

V

CC

V

SS

V

SS

V

SS

33
34
72
73
12
13
53

41 MCS2
42 MCS3/NPS
43 N.C.
44 N.C.
45 UCS
46 LCS
47 PCS6/A2
48 PCS5/A1
49 PCS4
50 PCS3
51 PCS2
52 PCS1
53 V

SS

54 PCS0
55 RES
56 TMR OUT 1
57 TMR OUT 0
58 TMR IN 1
59 TMR IN 0
60 DRQ1

I/O

UCS 45
LCS

46

MCS0/PEREQ 39
MCS1

/ERROR 40
MCS2 41
MCS3

/NPS 42

PCS0 54
PCS1
PCS2
PCS3

52
51
50

PCS4 49

/A1 48

PCS5
PCS6/A2 47

TMR IN 0 59
TMR IN 1 58
TMR OUT 0 57
TMR OUT 1 56

DRQ0 61
DRQ1 60

61 DRQ0
62 N.C.
63 N.C.
64 AD0
65 AD8 (A8)
66 AD1
67 AD9 (A9)
68 AD2
69 AD10 (A10)
70 AD3
71 AD11 (A11)
72 V

CC

73 V

CC

74 AD4
75 AD12 (A12)
76 AD5
77 AD13 (A13)
78 AD6
79 AD14 (A14)
80 AD7

NOTE:

Pin names in parentheses apply to the 80C188XL.

20

Table 8. SQFP Pin Functions with Location

AD Bus

AD0 1
AD1 3
AD2 6
AD3 8
AD4 12
AD5 14
AD6 16
AD7 18
AD8 (A8) 2
AD9 (A9) 5
AD10 (A10) 7
AD11 (A11) 9
AD12 (A12) 13
AD13 (A13) 15

Bus Control

ALE/QS0 29
BHE

(RFSH)26
S0
S1
S2
RD/QSMD 28
WR

/QS1 27
ARDY 37
SRDY 44
DEN
DT/R
LOCK
HOLD 43
HLDA 42

AD14 (A14) 17
AD15 (A15) 19
A16/S3 21
A17/S4 22
A18/S5 23
A19/S6 24

No Connection

N.C. 4
N.C. 25
N.C. 35
N.C. 55
N.C. 72

NOTE:

Pin names in parentheses apply to the 80C188XL.

40
39
38

56
54
45

Processor Control

RES 73
RESET 34
X1 32
X2 33
CLKOUT 36
TEST/BUSY 46
NMI 47
INT0 48
INT1/SELECT
INT2/INTA0
INT3/INTA1

49
52
53

Power and Ground

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

10
11
20
50
51
61
30
31
41
70
80

80C186XL/80C188XL

I/O

UCS 62
LCS

MCS0/PEREQ 57
MCS1

/ERROR 58
MCS2 59
MCS3

/NPS 60

PCS0 71
PCS1
PCS2
PCS3
PCS4 66

/A1 65

PCS5
PCS6/A2 64

TMR IN 0 77
TMR IN 1 76
TMR OUT 0 75
TMR OUT 1 74

DRQ0 79
DRQ1 78

63

69
68
67

Table 9. SQFP Pin Locations with Pin Names

1 AD0
2 AD8 (A8)
3 AD1
4 N.C.
5 AD9 (A9)
6 AD2
7 AD10 (A10)
8 AD3
9 AD11 (A11)

10 V

CC

11 V

CC

12 AD4
13 AD12 (A12)
14 AD5
15 AD13 (A13)
16 AD6
17 AD14 (A14)
18 AD7
19 AD15 (A15)
20 V

CC

NOTE:

Pin names in parentheses apply to the 80C188XL.

21 A16/S3
22 A17/S4
23 A18/S5
24 A19/S6
25 N.C.
26 BHE
27 WR

(RFSH)

/QS1
28 RD/QSMD
29 ALE/QS0
30 V

SS

31 V

SS

32 X1
33 X2
34 RESET
35 N.C.
36 CLKOUT
37 ARDY
38 S2
39 S1
40 S0

41 V

SS

42 HLDA
43 HOLD
44 SRDY
45 LOCK
46 TEST/BUSY
47 NMI
48 INT0
49 INT1/SELECT
50 V

CC

51 V

CC

52 INT2/INTA0
53 INT3/INTA1
54 DT/R
55 N.C.
56 DEN
57 MCS0/PEREQ
58 MCS1

/ERROR
59 MCS2
60 MCS3/NPS

61 V

CC

62 UCS
63 LCS
64 PCS6/A2
65 PCS5

/A1
66 PCS4
67 PCS3
68 PCS2
69 PCS1
70 V

SS

71 PCS0
72 N.C.
73 RES
74 TMR OUT 1
75 TMR OUT 0
76 TMR IN 1
77 TMR IN 0
78 DRQ1
79 DRQ0
80 V

SS

21

80C186XL/80C188XL

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings*

Ambient Temperature under Bias ÀÀÀÀ0§Ctoa70§C

Storage Temperature ААААААААААb65§Ctoa150§C

Voltage on Any Pin with

Respect to Ground АААААААААААА

Package Power Dissipation ААААААААААААААААААА1W
Not to exceed the maximum allowable die tempera­ture based on thermal resistance of the package.

b

1.0V toa7.0V

NOTICE: This data sheet contains preliminary infor­mation on new products in production. The specifica­tions are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.

*

WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex­tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.

NOTICE: The specifications are subject to change
without notice.

DC SPECIFICATIONS T

e

0§Ctoa70§C, V

A

CC

e

5Vg10%

Symbol Parameter Min Max Units Test Conditions

V

IL

Input Low Voltage

b

0.5 0.2 V

CC

b

0.3 V

(Except X1)

V

IL1

Clock Input Low

b

0.5 0.6 V

Voltage (X1)

V

V

V

Input High Voltage 0.2 V

IH

(All except X1 and RES

Input High Voltage (RES) 3.0 V

IH1

Clock Input High 3.9 V

IH2

)

CC

a

0.9 V

CC

CC

CC

a

0.5 V

a

0.5 V

a

0.5 V

Voltage (X1)

V

V

I

CC

Output Low Voltage 0.45 V I

OL

Output High Voltage 2.4 V

OH

V

CC

b

0.5 V

CC

CC

VI

VI

Power Supply Current 100 mA@25 MHz, 0§C

e

2.5 mA (S0, 1, 2)

OL

e

I

2.0 mA (others)

OL

eb

OH

eb

OH

e

V

CC

2.4 mA@2.4V

200 mA@V

(3)

5.5V

90 mA@20 MHz, 0§C

(3)

e

V

5.5V

CC

62.5 mA@12 MHz, 0§C

(3)

e

5.5V

V

CC

100 mA@DC 0§C

e

V

5.5V

CC

I

I

V

LI

LO

Input Leakage Current

Output Leakage Current

Clock Output Low 0.45 V I

CLO

g

10 mA@0.5 MHz,

0.45VsV

g

10 mA@0.5 MHz,

0.45V

CLO

s

e

IN

V

OUT

4.0 mA

s

V

CC

s

V

CC

CC

(1)

(4)

b

0.5

(4)

22

80C186XL/80C188XL

DC SPECIFICATIONS (Continued) T

e

0§Ctoa70§C, V

A

CC

e

5Vg10%

Symbol Parameter Min Max Units Test Conditions

V

CHO

C

IN

C

IO

NOTES:

1. Pins being floated during HOLD or by invoking the ONCE Mode.

2. Characterization conditions are a) Frequency
parameter is not tested.

3. Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open.
/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR and TEST/BUSY pins have internal pullup devices. Loading some

4. RD

of these pins above I
Local Bus Controller and Reset for details.

Clock Output High V

Input Capacitance 10 pF

Output or I/O Capacitance 20 pF

e

eb

200 mA can cause the processor to go into alternative modes of operation. See the section on

OH

b

0.5 V I

CC

1 MHz; b) Unmeasured pins at GND; c) VINata5.0V or 0.45V. This

CHO

@

@

eb

1 MHz

1 MHz

(2)

(2)

Power Supply Current

Current is linearly proportional to clock frequency
and is measured with the device in RESET with X1
and X2 driven and all other non-power pins open.

Maximum current is given by I

a

(MHz)

I

QL

is static. I

IQL.

is the quiescent leakage current when the clock

is typically less than 100 mA.

QL

CC

e

5mAcfreq.

500 mA

Figure 5. ICCvs Frequency

272431– 9

23

80C186XL/80C188XL

AC SPECIFICATIONS

MAJOR CYCLE TIMINGS (READ CYCLE)

e

0§Ctoa70§C, V

T

A

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with C
For AC tests, input V

Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit

80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

T

T

Data in Setup (A/D) 8 10 15 ns

DVCL

Data in Hold (A/D) 3 3 3 ns

CLDX

80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

T

T

T

T

T

T

T

T

T

T

T

Status Active Delay 3 20 3 25 3 35 ns

CHSV

Status Inactive Delay 3 20 3 25 3 35 ns

CLSH

Address Valid Delay 3 20 3 27 3 36 ns

CLAV

Address Hold 0 0 0 ns

CLAX

Data Valid Delay 3 20 3 27 3 36 ns

CLDV

Status Hold Time 10 10 10 ns

CHDX

ALE Active Delay 20 20 25 ns

CHLH

ALE Width T

LHLL

ALE Inactive Delay 20 20 25 ns

CHLL

Address Valid to ALE Low T

AVLL

Address Hold from ALE T

LLAX

Inactive Loading

T

T

T

T

Address Valid to Clock High 0 0 0 ns

AVCH

Address Float Delay T

CLAZ

Chip-Select Active Delay 3 20 3 25 3 33 ns

CLCSV

Chip-Select Hold from T

CXCSX

Command Inactive Loading

T

T

T

T

T

T

Chip-Select Inactive Delay 3 17 3 20 3 30 ns

CHCSX

DEN Inactive to DT/R Low 0 0 0 ns Equal

DXDL

Control Active Delay 1 3 17 3 22 3 37 ns

CVCTV

DEN Inactive Delay 3 17 3 22 3 37 ns

CVDEX

Control Active Delay 2 3 20 3 22 3 37 ns

CHCTV

LOCK Valid/Invalid Delay 3 17 3 22 3 37 ns

CLLV

CC

e

IL

e

5Vg10%

0.45V and V

L

e

50 pF.

e

2.4V except at X1 where V

IH

e

V

IH

CC

Values

Min Max Min Max Min Max

CLCL

CLCH

CHCL

CLCH

b

15 T

b

10 T

b

8T

CLAX

b

10 T

20 T

CLCL

CLCH

CHCL

CLCH

b

CLAX

15 T

b

10 T

b

10 T

b

10 T

CLCL

CLCH

CHCL

20 T

CLCH

b

b

b

CLAX

b

b

0.5V.

15 ns

15 ns Equal

15 ns Equal

25 ns

10 ns Equal

Test

Conditions

Loading

Loading

24

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

MAJOR CYCLE TIMINGS (READ CYCLE) (Continued)

e

T

0§Ctoa70§C, V

A

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with C
For AC tests, input V

Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit

80C186XL TIMING RESPONSES (Read Cycle)

T

Address Float 0 0 0 ns

AZRL

to RD Active

T

T

T

T

RD Active Delay 3 20 3 27 3 37 ns

CLRL

RD Pulse Width 2T

RLRH

RD Inactive Delay 3 20 3 27 3 37 ns

CLRH

RD Inactive T

RHLH

to ALE High Loading

T

RD Inactive to T

RHAV

Address Active Loading

CC

e

IL

e

5Vg10%

e

50 pF.

L

0.45V and V

e

2.4V except at X1 where V

IH

IH

Values

Min Max Min Max Min Max

CLCL

CLCH

CLCL

b

15 2T

b

14 T

b

15 T

CLCL

CLCH

CLCL

b

20 2T

b

14 T

b

15 T

e

b

V

0.5V.

CC

b

25 ns

CLCL

b

CLCH

CLCL

14 ns Equal

b

15 ns Equal

Test

Conditions

25

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

MAJOR CYCLE TIMINGS (WRITE CYCLE)

e

T

0§Ctoa70§C, V

A

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with C
For AC tests, input V

Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit

80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

T

T

T

T

T

T

T

T

T

T

T

Status Active Delay 3 20 3 25 3 35 ns

CHSV

Status Inactive Delay 3 20 3 25 3 35 ns

CLSH

Address Valid Delay 3 20 3 27 3 36 ns

CLAV

Address Hold 0 0 0 ns

CLAX

Data Valid Delay 3 20 3 27 3 36 ns

CLDV

Status Hold Time 10 10 10 ns

CHDX

ALE Active Delay 20 20 25 ns

CHLH

ALE Width T

LHLL

ALE Inactive Delay 20 20 25 ns

CHLL

Address Valid to ALE Low T

AVLL

Address Hold from ALE T

LLAX

Inactive Loading

T

T

T

T

T

T

Address Valid to Clock High 0 0 0 ns

AVCH

Data Hold Time 3 3 3 ns

CLDOX

Control Active Delay 1 3 20 3 25 3 37 ns

CVCTV

Control Inactive Delay 3 17 3 25 3 37 ns

CVCTX

Chip-Select Active Delay 3 20 3 25 3 33 ns

CLCSV

Chip-Select Hold from T

CXCSX

Command Inactive Loading

T

T

T

Chip-Select Inactive Delay 3 17 3 20 3 30 ns

CHCSX

DEN Inactive to DT/R Low 0 0 0 ns Equal

DXDL

LOCK Valid/Invalid Delay 3 17 3 22 3 37 ns

CLLV

80C186XL TIMING RESPONSES (Write Cycle)

T

T

T

T

WR Pulse Width 2T

WLWH

WR Inactive to ALE High T

WHLH

Data Hold after WR T

WHDX

WR Inactive to DEN Inactive T

WHDEX

CC

e

IL

e

5Vg10%

0.45V and V

L

e

50 pF.

e

2.4V except at X1 where V

IH

e

V

IH

CC

Values

Min Max Min Max Min Max

CLCL

CLCH

CHCL

CLCH

CLCL

CLCH

CLCL

CLCH

b

15 T

b

10 T

b

10 T

b

10 T

b

15 2T

b

14 T

b

10 T

b

10 T

CLCL

CLCH

CHCL

CLCH

CLCL

CLCH

CLCL

CLCH

b

15 T

b

10 T

b

10 T

b

10 T

b

20 2T

b

14 T

b

15 T

b

10 T

CLCL

CLCH

CHCL

CLCH

CLCL

CLCH

CLCL

CLCH

b

b

b

b

b

b

b

b

b

0.5V.

15 ns

15 ns Equal

15 ns Equal

10 ns Equal

25 ns

14 ns Equal

20 ns Equal

10 ns Equal

Test

Conditions

Loading

Loading

Loading

Loading

Loading

26

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

MAJOR CYCLE TIMINGS (INTERRUPT ACKNOWLEDGE CYCLE)

e

T

0§Ctoa70§C, V

A

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with C
For AC tests, input V

Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit

80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

T

T

Data in Setup (A/D) 8 10 15 ns

DVCL

Data in Hold (A/D) 3 3 3 ns

CLDX

80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

T

T

T

T

T

T

T

T

T

T

T

T

Status Active Delay 3 20 3 25 3 35 ns

CHSV

Status Inactive Delay 3 20 3 25 3 35 ns

CLSH

Address Valid Delay 3 20 3 27 3 36 ns

CLAV

Address Valid to Clock High 0 0 0 ns

AVCH

Address Hold 0 0 0 ns

CLAX

Data Valid Delay 3 20 3 27 3 36 ns

CLDV

Status Hold Time 10 10 10 ns

CHDX

ALE Active Delay 20 20 25 ns

CHLH

ALE Width T

LHLL

ALE Inactive Delay 20 20 25 ns

CHLL

Address Valid to ALE Low T

AVLL

Address Hold to ALE T

LLAX

Inactive Loading

T

T

T

T

T

T

Address Float Delay T

CLAZ

Control Active Delay 1 3 17 3 25 3 37 ns

CVCTV

Control Inactive Delay 3 17 3 25 3 37 ns

CVCTX

DEN Inactive to DT/R Low 0 0 0 ns Equal

DXDL

Control Active Delay 2 3 20 3 22 3 37 ns

CHCTV

DEN Inactive Delay 3 17 3 22 3 37 ns

CVDEX

(Non-Write Cycles)

T

LOCK Valid/Invalid Delay 3 17 3 22 3 37 ns

CLLV

CC

e

IL

e

5Vg10%

0.45V and V

L

e

50 pF.

e

2.4V except at X1 where V

IH

e

V

IH

CC

Values

Min Max Min Max Min Max

CLCL

CLCH

CHCL

CLAX

b

15 T

b

10 T

b

10 T

20 T

CLCL

CLCH

CHCL

b

CLAX

15 T

b

10 T

b

10 T

CLCL

CLCH

CHCL

20 T

b

b

b

CLAX

b

0.5V.

15 ns

15 ns Equal

15 ns Equal

25 ns

Test

Conditions

Loading

Loading

27

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

SOFTWARE HALT CYCLE TIMINGS

e

T

0§Ctoa70§C, V

A

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with C
For AC tests, input V

Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit

80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

T

T

T

T

T

T

T

T

Status Active Delay 3 20 3 25 3 35 ns

CHSV

Status Inactive Delay 3 20 3 25 3 35 ns

CLSH

Address Valid Delay 3 20 3 27 3 36 ns

CLAV

ALE Active Delay 20 20 25 ns

CHLH

ALE Width T

LHLL

ALE Inactive Delay 20 20 25 ns

CHLL

DEN Inactive to DT/R Low 0 0 0 ns Equal

DXDL

Control Active Delay 2 3 20 3 22 3 37 ns

CHCTV

CC

e

IL

e

5Vg10%

0.45V and V

L

e

50 pF.

e

2.4V except at X1 where V

IH

e

V

IH

CC

Values

Min Max Min Max Min Max

CLCL

b

15 T

CLCL

b

15 T

CLCL

b

b

0.5V.

15 ns

Test

Conditions

Loading

28

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

CLOCK TIMINGS

e

T

0§Ctoa70§C, V

A

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with C
For AC tests, input V

Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit

80C186XL CLKIN REQUIREMENTS

T

T

T

T

T

CLKIN Period 20

CKIN

CLKIN Low Time 8

CLCK

CLKIN High Time 8

CHCK

CLKIN Fall Time 5 5 5 ns 3.5 to 1.0V

CKHL

CLKIN Rise Time 5 5 5 ns 1.0 to 3.5V

CKLH

80C186XL CLKOUT TIMING

T

CLKIN to 17 17 21 ns

CICO

CLKOUT Skew

T

T

CLKOUT Period 40

CLCL

CLKOUT 0.5 T

CLCH

Low Time

T

CLKOUT 0.5 T

CHCL

High Time

T

CLKOUT 6 8 10 ns 1.0 to 3.5V

CH1CH2

Rise Time

T

CLKOUT 6 8 10 ns 3.5 to 1.0V

CL2CL1

Fall Time

CC

e

IL

e

5Vg10%

e

50 pF.

L

0.45V and V

e

2.4V except at X1 where V

IH

IH

Values

Min Max Min Max Min Max

(1)

CLCL

CLCL

%

%

%

%

b

5 0.5 T

b

5 0.5 T

25

10

10

50 80

CLCL

CLCL

%

%

%

b

5 0.5 T

b

5 0.5 T

e

b

V

CC

40

16

16

b

5nsC

CLCL

b

5nsC

CLCL

0.5V.

%

%

%

%

Conditions

ns

ns 1.5V

ns 1.5V

ns

L

L

Test

(2)

(2)

e

100 pF

e

100 pF

(3)

(4)

NOTES:

1. External clock applied to X1 and X2 not connected.

2. T

3. Tested under worst case conditions: V

4. Tested under worst case conditions: V

CLCK

and T

(CLKIN Low and High times) should not have a duration less than 40% of T

CHCK

CC
CC

e
e

5.5V. T

4.5V. T

.

e

70§C.

A

e

0§C.

A

CKIN

29

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

READY, PERIPHERAL AND QUEUE STATUS TIMINGS

e

T

0§Ctoa70§C, V

A

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with C
For AC tests, input V

Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit

80C186XL READY AND PERIPHERAL TIMING REQUIREMENTS (Listed More Than Once)

T

SRYCL

Synchronous Ready (SRDY) 8 10 15 ns
Transition Setup Time

T

CLSRY

T

ARYCH

SRDY Transition Hold Time

ARDY Resolution Transition 8 10 15 ns
Setup Time

T

CLARX

T

ARYCHL

T

ARYLCL

ARDY Active Hold Time

ARDY Inactive Holding Time 8 10 15 ns

Asynchronous Ready 10 15 25 ns
(ARDY) Setup Time

T

INVCH

INTx, NMI, TEST/BUSY, 8 10 15 ns
TMR IN Setup Time

T

INVCL

DRQ0, DRQ1 Setup Time

80C186XL PERIPHERAL AND QUEUE STATUS TIMING RESPONSES

T

CLTMV

T

CHQSV

NOTES:

1. To guarantee proper operation.

2. To guarantee recognition at clock edge.

Timer Output Delay 17 22 33 ns

Queue Status Delay 22 27 32 ns

CC

e

IL

(2)

e

5Vg10%

0.45V and V

L

(1)

(1)

(1)

(2)

(2)

e

50 pF.

e

2.4V except at X1 where V

IH

e

b

V

CC

0.5V.

IH

Values

Min Max Min Max Min Max

(1)

81015ns

81015ns

81015ns

Test

Conditions

30

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

RESET AND HOLD/HLDA TIMINGS

e

T

0§Ctoa70§C, V

A

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
All output test conditions are with C
For AC tests, input V

Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit

80C186XL RESET AND HOLD/HLDA TIMING REQUIREMENTS

T

RESIN

T

HVCL

RES Setup 15 15 15 ns

HOLD Setup

80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

T

T

CLAZ

CLAV

Address Float Delay T

Address Valid Delay 3 20 3 22 3 36 ns

80C186XL RESET AND HOLD/HLDA TIMING RESPONSES

T

CLRO

T

CLHAV

T

CHCZ

T

CHCV

Reset Delay 17 22 33 ns

HLDA Valid Delay 3 17 3 22 3 33 ns

Command Lines Float Delay 22 25 33 ns

Command Lines Valid Delay 20 26 36 ns
(after Float)

CC

e

IL

(1)

e

5Vg10%

0.45V and V

L

e

50 pF.

e

2.4V except at X1 where V

IH

e

b

V

CC

0.5V.

IH

Values

Min Max Min Max Min Max

81015ns

CLAX

20 T

CLAX

20 T

CLAX

25 ns

Test

Conditions

NOTE:

1. To guarantee recognition at next clock.

31

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

NOTES:

1. Status inactive in state preceding T

2. If latched A

3. For write cycle followed by read cycle.
of next bus cycle.

4. T

1

5. Changes in T-state preceding next bus cycle if followed by write.

Pin names in parentheses apply to the 80C188XL.

and A2are selected instead of PCS5 and PCS6, only T

1

.

4

Figure 6. Read Cycle Waveforms

32

CLCSV

272431– 10

is applicable.

AC SPECIFICATIONS (Continued)

80C186XL/80C188XL

NOTES:

1. Status inactive in state preceding T

2. If latched A

3. For write cycle followed by read cycle.

4. T1of next bus cycle.

5. Changes in T-state preceding next bus cycle if followed by read, INTA, or halt.

Pin names in parentheses apply to the 80C188XL.

and A2are selected instead of PCS5 and PCS6, only T

1

.

4

CLCSV

is applicable.

Figure 7. Write Cycle Waveforms

272431– 11

33

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

NOTES:

1. Status inactive in state preceding T

2. The data hold time lasts only until INTA

occurs one clock later in Slave Mode.

3. INTA

4. For write cycle followed by interrupt acknowledge cycle.

is active upon T1of the first interrupt acknowledge cycle and inactive upon T2of the second interrupt acknowl-

5. LOCK

edge cycle.

6. Changes in T-state preceding next bus cycle if followed by write.

Pin names in parentheses apply to the 80C188XL.

.

4

goes inactive, even if the INTA transition occurs prior to T

Figure 8. Interrupt Acknowledge Cycle Waveforms

34

CLDX

272431– 12

(min).

AC SPECIFICATIONS (Continued)

NOTE:

1. For write cycle followed by halt cycle.

Pin names in parentheses apply to the 80C188XL.

Figure 9. Software Halt Cycle Waveforms

80C186XL/80C188XL

272431– 13

35

80C186XL/80C188XL

WAVEFORMS

272431– 14

Figure 10. Clock Waveforms

36

272431– 15

Figure 11. Reset Waveforms

272431– 16

Figure 12. Synchronous Ready (SRDY) Waveforms

AC CHARACTERISTICS

Figure 13. Asynchronous Ready (ARDY) Waveforms

80C186XL/80C188XL

272431– 23

Figure 14. Peripheral and Queue Status Waveforms

272431– 17

37

80C186XL/80C188XL

AC CHARACTERISTICS (Continued)

Figure 15. HOLDA/HLDA Waveforms (Entering Hold)

272431– 24

38

272431– 18

Figure 16. HOLD/HLDA Waveforms (Leaving Hold)

80C186XL/80C188XL

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has from 5 to 7 characters. The first character is always a ‘T’ (stands for time). The other
characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The
following is a list of all the characters and what they stand for.

A: Address

ARY: Asynchronous Ready Input

C: Clock Output

CK: Clock Input

CS: Chip Select

CT: Control (DT/R

D: Data Input

DE: DEN

H: Logic Level High

OUT: Input (DRQ0, TIM0, . . . )

L: Logic Level Low or ALE

O: Output

QS: Queue Status (QS1, QS2)

R: RD Signal, RESET Signal

S: Status (S0

SRY: Synchronous Ready Input

V: Valid

W: WR Signal

X: No Longer a Valid Logic Level

Z: Float

Examples:

T

T

T

Ð Time from Clock low to Address valid

CLAV

Ð Time from Clock high to ALE high

CHLH

Ð Time from Clock low to Chip Select valid

CLCSV

, DEN,...)

,S1,S2)

39

80C186XL/80C188XL

DERATING CURVES

Typical Output Delay Capacitive Derating

272431– 19

Figure 17. Capacitive Derating Curve

Typical Rise and Fall Times for TTL Voltage Levels

40

272431– 20

Figure 18. TTL Level Rise and Fall Times for Output Buffers

Typical Rise and Fall Times for CMOS Voltage Levels

272431– 21

Figure 19. CMOS Level Rise and Fall Times for Output Buffers

80C186XL/80C188XL

80C186XL/80C188XL EXPRESS

The Intel EXPRESS system offers enhancements to
the operational specifications of the 80C186XL mi­croprocessor. EXPRESS products are designed to
meet the needs of those applications whose operat­ing requirements exceed commercial standards.

The 80C186XL EXPRESS program includes an ex­tended temperature range. With the commercial
standard temperature range, operational character­istics are guaranteed over the temperature range of
0

Ctoa70§C. With the extended temperature range

§

option, operational characteristics are guaranteed
over the range of

Package types and EXPRESS versions are identified
by a one or two-letter prefix to the part number. The
prefixes are listed in Table 10. All AC and DC specifi­cations not mentioned in this section are the same
for both commercial and EXPRESS parts.

Prefix

A PGA Commercial

N PLCC Commercial

R LCC Commercial

S QFP Commercial

SB SQFP Commercial

TA PGA Extended

TN PLCC Extended

TR LCC Extended

TS QFP Extended

b

40§Ctoa85§C.

Table 10. Prefix Identification

Package Temperature

Type Range

80C186XL/80C188XL EXECUTION
TIMINGS

A determination of program execution timing must
consider the bus cycles necessary to prefetch in­structions as well as the number of execution unit
cycles necessary to execute instructions. The fol­lowing instruction timings represent the minimum ex­ecution time in clock cycles for each instruction. The
timings given are based on the following assump­tions:

The opcode, along with any data or displacement

#

required for execution of a particular instruction,
has been prefetched and resides in the queue at
the time it is needed.

No wait states or bus HOLDs occur.

#

All word-data is located on even-address bound-

#

aries (80C186XL only).

All jumps and calls include the time required to fetch
the opcode of the next instruction at the destination
address.

All instructions which involve memory accesses can
require one or two additional clocks above the mini­mum timings shown due to the asynchronous hand­shake between the bus interface unit (BIU) and exe­cution unit.

With a 16-bit BIU, the 80C186XL has sufficient bus
performance to ensure that an adequate number of
prefetched bytes will reside in the queue (6 bytes)
most of the time. Therefore, actual program execu­tion time will not be substantially greater than that
derived from adding the instruction timings shown.

The 80C188XL 8-bit BIU is limited in its performance
relative to the execution unit. A sufficient number of
prefetched bytes may not reside in the prefetch
queue (4 bytes) much of the time. Therefore, actual
program execution time will be substantially greater
than that derived from adding the instruction timings
shown.

41

80C186XL/80C188XL

INSTRUCTION SET SUMMARY

Function Format Clock Clock Comments

DATA TRANSFER

e

Move:

MOV

Register to Register/Memory 1000100w modreg r/m 2/12 2/12*

Register/memory to register 1000101w modreg r/m 2/9 2/9*

Immediate to register/memory 1100011w mod000 r/m data data if we1 12/13 12/13 8/16-bit

Immediate to register 1011w reg data data if we1 3/4 3/4 8/16-bit

Memory to accumulator 1010000w addr-low addr-high 8 8*

Accumulator to memory 1010001w addr-low addr-high 9 9*

Register/memory to segment register 10001110 mod0reg r/m 2/9 2/13

Segment register to register/memory 10001100 mod0reg r/m 2/11 2/15

PUSHePush:

Memory 11111111 mod110 r/m 16 20

Register 01010 reg 10 14

Segment register 000reg110 9 13

Immediate 011010s0 data data if se01014

PUSHAePush All 01100000 36 68

POPePop:

Memory 10001111 mod000 r/m 20 24

Register 01011 reg 10 14

Segment register 000reg111 (regi01) 8 12

POPAePopAll 01100001 51 83

XCHGeExchange:

Register/memory with register 1000011w modreg r/m 4/17 4/17*

Register with accumulator 10010 reg 3 3

INeInput from:

Fixed port 1110010w port 10 10*

Variable port 1110110w 8 8*

OUTeOutput to:

Fixed port 1110011w port 9 9*

Variable port 1110111w 7 7*

XLATeTranslate byte to AL 11010111 11 15

LEAeLoad EA to register 10001101 modreg r/m 6 6

LDSeLoad pointer to DS 11000101 modreg r/m (modi11) 18 26

LESeLoad pointer to ES 11000100 modreg r/m (modi11) 18 26

LAHFeLoad AH with flags 10011111 2 2

SAHFeStore AH into flags 10011110 3 3

PUSHFePush flags 10011100 9 13

POPFePop flags 10011101 8 12

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

80C186XL 80C188XL

Cycles Cycles

42

80C186XL/80C188XL

INSTRUCTION SET SUMMARY (Continued)

Function Format Clock Clock Comments

DATA TRANSFER (Continued)

e

SEGMENT

CS 00101110 2 2

SS 00110110 2 2

DS 00111110 2 2

ES 00100110 2 2

ARITHMETIC
ADD

Reg/memory with register to either 000000dw modreg r/m 3/10 3/10*

Immediate to register/memory 100000sw mod000 r/m data data if s we01 4/16 4/16*

Immediate to accumulator 0000010w data data if we1 3/4 3/4 8/16-bit

ADCeAdd with carry:

Reg/memory with register to either 000100dw modreg r/m 3/10 3/10*

Immediate to register/memory 100000sw mod010 r/m data data if s we01 4/16 4/16*

Immediate to accumulator 0001010w data data if we1 3/4 3/4 8/16-bit

INCeIncrement:

Register/memory 1111111w mod000 r/m 3/15 3/15*

Register 01000 reg 3 3

SUBeSubtract:

Reg/memory and register to either 001010dw modreg r/m 3/10 3/10*

Immediate from register/memory 100000sw mod101 r/m data data if s we01 4/16 4/16*

Immediate from accumulator 0010110w data data if we1 3/4 3/4 8/16-bit

SBBeSubtract with borrow:

Reg/memory and register to either 000110dw modreg r/m 3/10 3/10*

Immediate from register/memory 100000sw mod011 r/m data data if s we01 4/16 4/16*

Immediate from accumulator 0001110w data data if we1 3/4 3/4* 8/16-bit

DECeDecrement

Register/memory 1111111w mod001 r/m 3/15 3/15*

Register 01001 reg 3 3

CMPeCompare:

Register/memory with register 0011101w modreg r/m 3/10 3/10*

Register with register/memory 0011100w modreg r/m 3/10 3/10*

Immediate with register/memory 100000sw mod111 r/m data data if s we01 3/10 3/10*

Immediate with accumulator 0011110w data data if we1 3/4 3/4 8/16-bit

NEGeChange sign register/memory 1111011w mod011 r/m 3/10 3/10*

AAAeASCII adjust for add 00110111 8 8

DAAeDecimal adjust for add 00100111 4 4

AASeASCII adjust for subtract 00111111 7 7

DASeDecimal adjust for subtract 00101111 4 4

MULeMultiply (unsigned): 1111011w mod100 r/m

Register-Byte 26–28 26–28
Register-Word 35–37 35–37
Memory-Byte 32–34 32–34
Memory-Word 41–43 41–43*

e

Add:

Segment Override:

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

80C186XL 80C188XL

Cycles Cycles

43

80C186XL/80C188XL

INSTRUCTION SET SUMMARY (Continued)

Function Format Clock Clock Comments

ARITHMETIC (Continued)

IMULeInteger multiply (signed): 1111011w mod101 r/m

Register-Byte 25–28 25–28
Register-Word 34–37 34–37
Memory-Byte 31–34 32–34
Memory-Word 40–43 40–43*

IMULeInteger Immediate multiply 011010s1 modreg r/m data data if se0 22 –25/ 22 –25/

(signed)

DIVeDivide (unsigned): 1111011w mod110 r/m

Register-Byte 29 29
Register-Word 38 38
Memory-Byte 35 35
Memory-Word 44 44*

IDIVeInteger divide (signed): 1111011w mod111 r/m

Register-Byte 44– 52 44-52
Register-Word 53–61 53–61
Memory-Byte 50–58 50–58
Memory-Word 59–67 59–67*

AAMeASCII adjust for multiply 11010100 00001010 19 19

AADeASCII adjust for divide 11010101 00001010 15 15

CBWeConvert byte to word 10011000 2 2

CWDeConvert word to double word 10011001 4 4

LOGIC
Shift/Rotate Instructions:

Register/Memory by 1 1101000w modTTTr/m 2/15 2/15

Register/Memory by CL 1101001w modTTTr/m

Register/Memory by Count 1100000w modTTTr/m count

TTT Instruction

000 ROL
001 ROR
010 RCL
011 RCR
1 0 0 SHL/SAL
101 SHR

e

AND

And:

Reg/memory and register to either 001000dw modreg r/m 3/10 3/10*

Immediate to register/memory 1000000w mod100 r/m data data if we1 4/16 4/16*

Immediate to accumulator 0010010w data data if we1 3/4 3/4* 8/16-bit

TESTeAnd function to flags, no result:

Register/memory and register 1000010w modreg r/m 3/10 3/10*

Immediate data and register/memory 1111011w mod000 r/m data data if we1 4/10 4/10*

Immediate data and accumulator 1010100w data data if we1 3/4 3/4 8/16-bit

OReOr:

Reg/memory and register to either 000010dw modreg r/m 3/10 3/10*

Immediate to register/memory 1000000w mod001 r/m data data if we1 4/16 4/16*

Immediate to accumulator 0000110w data data if we1 3/4 3/4* 8/16-bit

111 SAR

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

80C186XL 80C188XL

Cycles Cycles

29–32 29–32

5an/17an5an/17an

5an/17an5an/17an

44

80C186XL/80C188XL

INSTRUCTION SET SUMMARY (Continued)

Function Format Clock Clock Comments

LOGIC (Continued)

e

Exclusive or:

XOR

Reg/memory and register to either 001100dw modreg r/m 3/10 3/10*

Immediate to register/memory 1000000w mod110 r/m data data if we1 4/16 4/16*

Immediate to accumulator 0011010w data data if we1 3/4 3/4 8/16-bit

NOTeInvert register/memory 1111011w mod010 r/m 3/10 3/10*

STRING MANIPULATION

MOVSeMove byte/word 1010010w 14 14*

CMPSeCompare byte/word 1010011w 22 22*

SCASeScan byte/word 1010111w 15 15*

LODSeLoad byte/wd to AL/AX 1010110w 12 12*

STOSeStore byte/wd from AL/AX 1010101w 10 10*

INSeInput byte/wd from DX port 0110110w 14 14

OUTSeOutput byte/wd to DX port 0110111w 14 14

Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)

MOVSeMove string 11110010 1010010w 8a8n 8a8n*

CMPSeCompare string 1111001z 1010011w 5a22n 5a22n*

SCASeScan string 1111001z 1010111w 5a15n 5a15n*

LODSeLoad string 11110010 1010110w 6a11n 6a11n*

STOSeStore string 11110010 1010101w 6a9n 6a9n*

INSeInput string 11110010 0110110w 8a8n 8a8n*

OUTSeOutput string 11110010 0110111w 8a8n 8a8n*

CONTROL TRANSFER

e

CALL

Call:

Direct within segment 11101000 disp-low disp-high 15 19

Register/memory 11111111 mod010 r/m 13/19 17/27
indirect within segment

Direct intersegment 10011010 segment offset 23 31

segment selector

Indirect intersegment 11111111 mod011 r/m (modi11) 38 54

JMPeUnconditional jump:

Short/long 11101011 disp-low 14 14

Direct within segment 11101001 disp-low disp-high 14 14

Register/memory 11111111 mod100 r/m 11/17 11/21
indirect within segment

Direct intersegment 11101010 segment offset 14 14

segment selector

Indirect intersegment 11111111 mod101 r/m (modi11) 26 34

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

80C186XL 80C188XL

Cycles Cycles

45

80C186XL/80C188XL

INSTRUCTION SET SUMMARY (Continued)

Function Format Clock Clock Comments

CONTROL TRANSFER (Continued)

e

Return from CALL:

RET

Within segment 11000011 16 20

Within seg adding immed to SP 11000010 data-low data-high 18 22

Intersegment 11001011 22 30

Intersegment adding immediate to SP 11001010 data-low data-high 25 33

JE/JZeJump on equal/zero 01110100 disp 4/13 4/13 JMP not

JL/JNGEeJump on less/not greater or equal 01111100 disp 4/13 4/13

JLE/JNGeJump on less or equal/not greater 01111110 disp 4/13 4/13

JB/JNAEeJump on below/not above or equal 01110010 disp 4/13 4/13

JBE/JNAeJump on below or equal/not above 01110110 disp 4/13 4/13

JP/JPEeJump on parity/parity even 01111010 disp 4/13 4/13

JOeJump on overflow 01110 000 disp 4/13 4/13

JSeJump on sign 01111000 disp 4/13 4/13

JNE/JNZeJump on not equal/not zero 01110101 disp 4/13 4/13

JNL/JGEeJump on not less/greater or equal 01111101 disp 4/13 4/13

JNLE/JGeJump on not less or equal/greater 01111111 disp 4/13 4/13

JNB/JAEeJump on not below/above or equal 01110011 disp 4/13 4/13

JNBE/JAeJump on not below or equal/above 01110111 disp 4/13 4/13

JNP/JPOeJump on not par/par odd 01111011 disp 4/13 4/13

JNOeJump on not overflow 01110001 disp 4/13 4/13

JNSeJump on not sign 01111001 disp 4/13 4/13

JCXZeJump on CX zero 11100011 disp 5/15 5/15

LOOPeLoop CX times 11100010 disp 6/16 6/16 LOOP not

LOOPZ/LOOPEeLoop while zero/equal 11100001 disp 6/16 6/16

LOOPNZ/LOOPNEeLoop while not zero/equal 11100000 disp 6/16 6/16

ENTEReEnter Procedure 11001000 data-low data-high L

Le0 15 19

e

1 25 29

L

l

1

L

LEAVEeLeave Procedure 11001001 8 8

INTeInterrupt:

Type specified 11001101 type 47 47

Type 3 11001100 45 45 ifINT. taken/

INTOeInterrupt on overflow 11001110 48/4 48/4

80C186XL 80C188XL

Cycles Cycles

22a16(nb1) 26a20(nb1)

taken/JMP

taken

taken/LOOP

taken

if INT. not

taken

IRETeInterrupt return 11001111 28 28

BOUNDeDetect value out of range 01100010 modreg r/m 33–35 33–35

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

46

80C186XL/80C188XL

INSTRUCTION SET SUMMARY (Continued)

Function Format Clock Clock Comments

PROCESSOR CONTROL

CLCeClear carry 11111000 2 2

CMCeComplement carry 11110101 2 2

STCeSet carry 11111001 2 2

CLDeClear direction 11111100 2 2

STDeSet direction 11111101 2 2

CLIeClear interrupt 11111010 2 2

STIeSet interrupt 11111011 2 2

HLTeHalt 11110100 2 2

WAITeWait 10011011 6 6 ifTESTe0

LOCKeBus lock prefix 11110000 2 2

NOPeNo Operation 10010000 3 3

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

(TTT LLL are opcode to processor extension)

80C186XL 80C188XL

Cycles Cycles

The Effective Address (EA) of the memory operand
is computed according to the mod and r/m fields:

e

if mod
if mod

if mod

if mod
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m

11 then r/m is treated as a REG field

e

00 then DISPe0*, disp-low and disp­high are absent

e

01 then DISPedisp-low sign-ex­tended to 16-bits, disp-high is absent

e

10 then DISPedisp-high: disp-low

e

000 then EAe(BX)a(SI)aDISP

e

001 then EAe(BX)a(DI)aDISP

e

010 then EAe(BP)a(SI)aDISP

e

011 then EAe(BP)a(DI)aDISP

e

100 then EAe(SI)aDISP

e

101 then EAe(DI)aDISP

e

110 then EAe(BP)aDISP*

e

111 then EAe(BX)aDISP

DISP follows 2nd byte of instruction (before data if
required)

*except if mod

e

00 and r/me110 then EA

e

disp-high: disp-low.

EA calculation time is 4 clock cycles for all modes,
and is included in the execution times given whenev­er appropriate.

Segment Override Prefix

0 0 1 reg 1 1 0

reg is assigned according to the following:

Segment

reg Register

00 ES
01 CS
10 SS
11 DS

REG is assigned according to the following table:

16-Bit (w

e

1) 8-Bit (we0)

000 AX 000 AL
001 CX 001 CL
010 DX 010 DL
011 BX 011 BL
100 SP 100 AH
101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

The physical addresses of all operands addressed
by the BP register are computed using the SS seg­ment register. The physical addresses of the desti­nation operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment, which may not be overridden.

47

80C186XL/80C188XL

REVISION HISTORY

This data sheet replaces the following data sheets:

272031-002 80C186XL

#

270975-002 80C188XL

#

272309-001 SB80C186XL

#

272310-001 SB80C188XL

#

ERRATA

An A or B step 80C186XL/80C188XL has the follow­ing errata. The A or B step 80C186XL/80C188XL
can be identified by the presence of an ‘‘A’’ or ‘‘B’’
alpha character, respectively, next to the FPO num­ber. The FPO number location is shown in Figure 4.

1. An internal condition with the interrupt controller
can cause no acknowledge cycle on the INTA1
line in response to INT1. This errata only occurs
when Interrupt 1 is configured in cascade mode
and a higher priority interrupt exists. This errata
will not occur consistently, it is dependent on in­terrupt timing.

The C step 80C186XL/80C188XL has no known er­rata. The C step can be identified by the presence of
a ‘‘C’’ or ‘‘D’’ alpha character next to the FPO num­ber. The FPO number location is shown in Figure 4.

PRODUCT IDENTIFICATION

Intel 80C186XL devices are marked with a 9-charac­ter alphanumeric Intel FPO number underneath the
product number. This data sheet (272431-001) is
valid for devices with an ‘‘A’’, ‘‘B’’, ‘‘C’’, or ‘‘D’’ as
the ninth character in the FPO number, as illustrated
in Figure 4.

48