Intel 8051 User Manual

Architectural Specification

May 1980

©

INTEL

CORPORATION, 1980.

AFN-01488A-01

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may appear in

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and shall remain the property
disclosure is subject to restrictions stated in Intel's software license,
Corporation assumes no responsibility for the use

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any circuitry other than circuitry embodied in

product. No other circuit patent licenses are implied.
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part

of

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consent

of

Intel Corporation.

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i

Intel Corporation and may only be used to identify Intel products:

or

reproduced in any form

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Intelevision
and the combinations
Additional copies of this

of

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or

other Intel literature may be obtained from:

or

RMX and a numerical suffix.

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Intel Corporation

3065 Bowers Avenue

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no

responsibility for any enors which

of

Intel Corporation. Use, duplication

or

as

defined in ASPR 7-104.9

or

by any means without the prior wr:itten

J,lScope

.

(a)

(9).

an

or
Intel
Intel

f·INTEL CORPORATION.

1980

8051

Architectural Specification and Functional Description

8031/8051/8751

SINGLE-COMPONENT 8-BIT MICROCOMPUTER

•

803t

- Control Oriented CPU With RAM and

•

8051

- An

8031

With Factory Mask- Programmable ROM

•

8751 -An

8031

With User Programmable/Erasable EPROM

I/O

• 4K x 8 ROM/EPROM

• 128 x 8 RAM

• Four 8-Bit Ports, 32 I/O Lines

• Two 16-Bit Timer/Event Counters

• High-Performance Full-Duplex Serial
Channel

• Boolean Processor

•

Compatible

with

MCS-80™/MCS-85TM

Peripherals

The Intel® 8031/8051/8751
+5

Volt, depletion-load, N-Channel, silicon-gate HMOS technology and packaged in a 40-pin DIP. It provides the

is

a stand-alone, high-performance single-chip computer fabricated with Intel's highly-reliable

• External

• MCS-48™ Architecture Enhanced with:

• Non-Paged Jumps

• Direct Addressing

• Four 8-Register Banks

• Stack Depth

• Multiply, Divide, Subtract, Compare

• Most Instructions Execute

•

411s

Memory

Multiply

hardware features, architectural enhancements and new instructions that are necessary to make

of

effective controller for applications requiring up to 64K bytes
The

8051/8751 contains a non-volatile 4K x 8 read only program memory; a volatile

32

I/O

lines; two 16-bit timer/counters; a five-source, two-priority-Ievel, nested interrupt structure; a serial

I/O

either multi-processor communications,
The

8031

is

identical, except that

be

expanded using standard TTL compatible memories and the byte oriented MCS-80 and MCS-85 peripherals.

The

8051

microcomputer, like its 8048 predecessor,

8051

has extensive facilities for binary and BCD arithmetic and excels in bit-handling capabilities. Efficient

memory results from

12

MHz crystal, 58%

a

an

instruction set consisting

of

the instructions execute in Ills, 40% in

it

lacks the program memory.

the many instructions added to the standard

expansion,

is

efficient both as a controller and as an arithmetic processor. The

of

44% one-byte,

8048 instruction set are multiply, divide, subtract and compare.

program memory and /

or

full duplex UART; and on-chip oscillator and clock circuits.

For

systems that require extra capability, the

41%

two-byte, and

2f1s

and mUltiply and divide require only

Expandable

Up

to 128-Bytes

and Divide

or

up to 64K bytes

128

x 8 read/write data memory;

15%

three-byte instructions. With

to

128K

in

111S

it

a powerful and cost

of

data

I/O

use

of

411S.

storage.

port for

8051

can

program

Among

P1.0

P1,1

P1.2
P1.3

P1.4

P1.5
P1.6
P1.7

RST/VPO
RXD P3.0

TXO P3.1

INTO P3.2

uin

P3.3

TO

P3.4

T1

P3.5 P2.5

\VA

P3.6

RD

P3.7

XTAL2

XTAL1

VSS

Figure

1.

Pin

Configuration

Intel

Corporation

© INTEL CORPORATION.

Assumes

vee

PO.o
PO.1
PO.2
PO.3
PO.4
PO.S
PO.S

PO.7

EAtVDO

ALEIPROG

PSEN

P2.7

P2.S

P2."

P2.3

P2.2

P2.1

P2.D

No

Responsibility

1980.

PSEN

ALE/PROG

TXO

.....

.m_

{{

INTO

......

INT'......

TO-'

n........

WA~

AD"-

:

g

Q.

Figure 2.

for

the

Use

Logic

of

Any

AST/VPD

Circuitry

FREQUENCY
REFERENCE

r

Than

BUS

Circuitry

I

I

I

I

I

I
I
I

I

L-

INTERRUPTS

Embodied

INTERRUPTS

in

•

an Intel

64K-SYTE

EXPANSION

CONTROL

CONTROL

Figure

Product.

8US

PARALLEL
ADDRESS/DATA
AND

3.

Block Diagram

No

Other

Circuit

DATA

110

ADDRESS

AND

}-.

OATA

}-,

ADDRESS

BUS

}~"'.

Symbol

Other

128

BYTES
MEMORY

PORTS.

PINS

Patent

BUS,

licenses

COUNTERS

,...----'---'---,

TWO

16-BIT

TIMER/EVENT

COUNTERS

PROGRAMMABLE

SERIAL

PORT

•

FULL

DUPLEX

UART

•

SYNCHRONOUS

SHIFTER

SERIAL SERIAL

IN

OUT

Are

Implied.

AFN-01488A-02

-1

I
I

I

I
I
I
I

I

I

8051 Single-Chip

Contents

Microcomputer

Architectural Specification

and

Functional Description

©Intel Corporation 1980. All rights reserved.

CHAPTER 1 INTRODUCTION

1.0

1.1

1.2

CHAPTER 2 ARCHITECTURAL OVERVIEW AND

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Abstract. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Intel's Complete Line
Microcomputers
Enhancing the 8048 Architecture for
the

80's

................................

FUNCTIONAL DESCRIPTION
The

8051

Family

Macro-view

2.1: 1 8051

2.1.2

On-Chip Peripheral Functions. . . . .

2.1.2.1

2.1.2.2

2.1.2.3 Timer/Event Counters

2.1.2.4 Serial Communications. . . .

CPU Hardware.

2.2.1

Instruction

2.2.2' Program

2.2.3 Internal Data Memory

2.2.3.1

2.2.3.2 Register Banks

2.2.3.3 Special Function Registers

2.2.3.4 A Register. . . . . . . . . . . . . . . .

2.2.3.5 B Register. . . . . . . . . . . . . . . .

2.2.3.6

2.2.3.7 Stack Pointer . . . . . . . . . . . . .

2.2.3.8 Data Pointer

2.2.4 Arithmetic Section

2.2.5

Program Control Section

2.2.6

Oscillator and Timing Circuitry

2.2.7 Boolean Processor
Memory Organization
Operand Addressing
Data Manipulation

2.5.1

Data Transfer Operations

2.5.2

logic

2.5.3

Arithmetic Operations
Control Transfer
I nstruction Set

2.7.1

What the Instruction Set Is

2.7.2 Organization

2.7.3 Operand Addressing Modes and

Associated Operations
Interrupt System

2.8.1

External Interrupts

2.8.1.1

2.8.1.2 level-Activated Interrupts

Ports and I/O Pins

of

CPU Architecture . . . . . . . . . . .

2.1.2.2.1

2.1.2.2.2 Quasi-Bidirectional

2.1.2.2.3 Microprocessor Bus

Operations

..... .-..

........................

........................

the

8051

Interrupt System

I/O Facilities. . . . . . . . . . . . . .

Open Drain I/O
I/O Pins

.. . .. . ..

Decoder.

Counter

Internal Data RAM

PSW

Register.

...............

........................

...........................

of

........................

Transition-Activated
Interrupts

.......................

.. .. .. .. .. ..

of

Single-Chip

...........

Architecture

..

. . . . . . . .

Pins. . ..

...............

..

.. . ..

.. .. . ..

. . . . . . . . . . . . .

.........

................

.................

.................

...................

....................

..................

the Instruction Set

..................

..................

. . . . . . . .

..............

...........

.•...........

.. ..

.. .. ..

...........

"

...........

..............

...........

.............

......

..

.......

....

......

......

....

.... 1

..

..

..
..
..
..

..
..

...

..
..

...

..
..

..

11
11
11
11
11
11
12
14
14
15
16
17
18
18

".

18

21
22
24

24
24
24

1
1
1

2
2
2
2
3
3
4
4

4
5
6
7
9
9
9
9
9
9
9
9
9
9
9

AFN-Q1488A·03

CHAPTER 2 ARCHITECTURAL OVERVIEW AND

FUNCTIONAL

DESCRIPTION (Continued)

2.10 Accessing External

2.10.1 Operation

2.10.2 Bus Cycle Timing

2.11

TimerlCounter

2.11.1 TIC Mode Selection

2.11.2 Configuring the

2.11.3 TIC Operation

2.11.4 Reading and

2.12

Serial Channel

2.12.1

Serial Port Control Register and
Serial Data Registers

2.12.2 Operating Modes

2.12.2.1 Operating Mode O

2.12.2.2 Operating Modes 1

2.12.3 The

2.12.4 Transmission Rate Generation

2.12.5 UART Message Error Conditions

2.13

External Interface

2.13.1

Processor Reset and

Initialization

2.13.2

Power Down Operation

Internal RAM

Table

2.14

2.15

2.16

2.17

2.1

EPROM Programming
The

8051

Development System and Software
Support
8051

................................

Pin Description

Instruction Set Summary

Memory

of

Ports

..........................

TIC Input

....................

Reloading the TIC

..........................

through 3

Serial Frame

.......................

......................

.....................

....................

as

an

Evolution of the 8048

....................

..............

................

.................

...............

.........

.......... ' ....

.................

•....•••.

................

.................

of

.................

....

.....

......

...

25
26
26
28
28
28
29
29
29

31
31
31

32
32
32
33

33
33
33

34
34

34
35

37

AFN-01488A-04

8051

Architectural Specification and Functional Description

1.0 ABSTRACT

The 8031, 8051,

of

line

single-chip microcomputers. The CPU architec­ture and on-chip peripheral functions
described in this document. A user familiar with the

MCS-48 family should be able to evaluate and design-in

the

8051

A detailed description
expand the
memory,
processor configurations

User's Manual.

1.1

INTEL'S COMPLETE LINE OF

and

8751

are the latest additions to Inters

of

the

using the information included herein.

of

the

hardware required to

8051

with more program memory,

I/O,

specialized peripherals and into multi-

is

described in the

8051

8051

data

Family

are

SINGLE-CHIP MICROCOMPUTERS

In

1976

Intel introduced the 8748 microcomputer. This
marked the first time in history that technology permitted
a complete 8-bit computer
silicon die. This single chip can control a limitless variety
of

products ranging from appliances to automobiles to

computer terminals.

Since

1976

Intel has offered products for the full range
single-chip microcomputer applications by pushing the
8048's architecture in several directions. The 8049 ran
nearly twice as fast
amount

of

on-chip program memory and

as

Applications requiring solely external program memory
were satisfied with the
less

I/O

intensive applications incorporated the
which executed a subset
slower speed. Finally, the
converter onto the

8021

directly to a world in which most signals are analog.

I.

Figure

I positions these products on a performance

versus die-size curve.

10

9

8

7

iu

il 6

c

~

5

o

...

ffi

4

...

3

2

0~------*X----~~1~.5~X------~2~X------.~2.5X

-Based on execution speed, memory size and peripheral functions.

Figure 1.1. Performance Versus Cost

to

be fabricated on a single

of

the 8748/8048 while doubling the

data

memory.

8035 and 8039. Cost sensitive and

8021

of

the 8048's instruction set

8022 integrated an 8-bit

at

A/D

die to allow the chip to interface

•

8051

8022.

8048

8021.

DIE SIZE

•

a

Now, thanks to the density
once again permitted the

to

performance
achieves a
8048

by packing 60,000 transistors onto a die 230 mils

leap into new product areas. The

lOX

function/speed improvement over the

of

HMOS, technology has

birth

of

a microcomputer with

square.

The

8051

family addresses the high-end

computer market.

It

is

the highest performance micfo-

computer family in the world

and

of

the single-chip

out-performs all micro-

processors and microcomputers in control oriented

It

applications.

for

8048 users with ten times the power

shown in Table

offers an upward compatible growth path

of

1.1.

•

4X

Program Memory (4k Bytes)

•

2X

Data Memory (128 Bytes)

•

2X

Register Banks (4

•

2X

Timers (Two 16-bit Timers)

• New Full-Duplex Serial

• More

I/O

Pins (32

vs.

vs.

27)

2)
I/O

Port

the

• Enhanced MCS-48 Architecture

•

Table

21/2 X To

1.4X Die Size

•

1.1:

10X

Execution Speed

8051

Functions/Speed/Cost Relative

to

8048

1.2 ENHANCING THE 8048 ARCHITEC­TURE FOR THE 80's

The goal
industry standard
the
CPU

of

on-chip CPU peripherals.

The
applications demanding a low-cost microcomputer because
of

its hardware simplicity and resulting silicon efficiency.

A

simpleALU
metic, logic,
data
internal data path. The
of

Register-, Register-Indirect- and Immediate-Address-

ing minimize hardware. The conditional branch logic

simply concatenates
bits
results in page boundaries. The simplicity
look-up circuitry also results in page boundaries. The
user flags and test pins provided for monitoring program
and external status in an efficient manner are limited to
two of each. This architecture, and the choice
tion encodings that it permits, results

programs

1

of

the

8051

is

to extend the architecture

8048 single-chip microcomputer into

80's. This meant increasing the power

of

the 8048's

as well as increasing the power, variety and quantity

8048's CPU architecture

is

used in virtually all operations: arith-

data

moves, bit testing and I/O. Since all

is

moved through the ALU this also simplifies the

is

ideal for control-oriented

8048's simple addressing methods

an

immediate value to the upper

of

the program counter to economize on silicon, but

of

the table-

of

In

1,024 byte

of

unsurpassed byte efficiency.

AFN-01488A-05

8051

8048

of

the

instruc-

as

8051

Architectural Specification and Functional Description

The silicon economic architecture of the
some inconvenience to the programmer but the relatively
short programs (one or two kilobytes) keep frustration
levels in check. The
ware and feature compatibility with the
providing a more powerful microcomputer that
to program and
using the
tecting
knowledge he gained by designing with the

Some of the achievements
maximum program memory address space to 64K-bytes,
extending on-chip peripheral functions (counters, serial
ports and parallel ports) to satisfy emerging single-chip
applications, and enhancing a paged architecture to
make
generated
were reassigned to add new high-power operations and to
permit
operations more orthogonal. During this process special
care
maximum execution speed. The
more code efficient than the 8049 for programs longer
than
from an instruction set consisting of 44% one-byte,
two-byte and

M

Hz

in

2;,Is

2.0 THE

The
computer intended for use
applications such as instrumentation, industrial control
and intelligent computer peripherals. It provides the
hardware features, architectural enhancements and new
instructions that make it a powerful and cost effective
controller for applications requiring up to 64K-bytes of
program memory
A Block Diagram

The

program memory.
Program Memory in addition to 64K-bytes

Data Memory.
each member of the
standard memories

MCS-85 peripherals. The
4K-bytes

programmable

light-erasable/ electrically-programmable ROM.

8048

his

investment in algorithm development and the

it

suitable for the relocatable and re-entrant code

by

modern programming techniques. Op codes

new

was

taken to provide optimum byte efficiency and

2048

bytes. Efficient use of program memory results

crystal,

and multiply and divide require 'only 4tis.

8051

8051

is

a stand-alone high-performance single-chip

8031

is

of

Program Memory filled with on-chip mask

8051

challenge

use.

This allows a designer currently

to easily upgrade to the

of

addressing modes which make the old

15%

three-byte instructions. With a

58%

of the instructions execute

the

was

8051

8051

FAMILY

in

sophisticated real-time

and/

or

up to 64K-bytes

is

shown in Figure

a control-oriented

It

can address 64K-bytes

For

systems requiring extra capability,

8051

family can

and

the byte oriented MCS-80 and

8051

ROM while the

CPU

is

an

8031

8751

has 4K-bytes

8048

causes

to maintain soft-

8048

while

is

easier

8051

while pro-

8048.

were to extend the

is

typically 20%

41

%
12

in

ltis, 40%

of

data storage.

3.

without on-chip

of

external

of

External

be

expanded using

with the lower

ofUV-

ment, prototyping, low-volume production
tions requiring field updates; the
high-volume production and the
desiring the flexibility
which can be easily modified

2.1

MACRO-VIEW OF THE

of

external Program Memory

8051

8031

and

updated in the field.

and

applica-

for low-cost,

for applications

8051

ARCHI-

TECTURE

On a single die the
non-volatile 4K x 8 read-only program memory; volatile

128

x 8 read/write data memory;
timer / event counters; a five-source, two-priority-Ievel,
nested interrupt structure; serial
processor communications,
UART; and on-chip oscillator and clock circuits. This
section will provide an overview
a high-level description
architecture and the on-chip functions peripheral to the

CPU. The generic term "8051"
tively to the

2.1.1

The

8051

spaces. These are the 64K-byte Program Memory, 64K-

byte External
Memory and 16-bit Program Counter spaces. The Inter­nal

Data
256-byte Internal
Function Register

2.1. Four Register Banks (each with eight registers),
addressable bits, and the stack reside in the Internal
RAM. The stack depth
Internal Data
8-bit
Counter and the four 8-Register Banks reside in the
Special Function Register address space. These memory
mapped registers include arithmetic registers, pointers,
I/O

ports, and registers for the interrupt system, timers
and serial channel.
space are addressable as bits. The

of Internal Data RAM and

The
address space to accommodate relocatable code.
ditional branches are performed relative to the Program
Counter. The register-indirect
relative to a 16-bit base register with
an 8-bit index register. Sixteen-bit jumps and calls permit
branching to any location in the contiguous 64K

Memory address space.

8031,

8051

CPU

Memory address space

Stack Pointer.

8051

provides a non-paged Program Memory

8051

microcomputer combines CPU;

32

I/O

lines; two 16-bit

I/O

port for either multi-

I/O

8051,

expansion,

of

the

of

its major elements: the

is

also used to refer collec-

and

8751.

or

8051

by providing

full duplex

CPU Architecture

manipulates

Data

Memory, 384-byte Internal

Data

(SFR) address spaces shown in Figure

RAM

and its location

All

128

operands

is

RAM

is

limited only by the available

registers except the Program

bit locations in the

20

SFRs.

jump

in

four

further divided into the
and 128-byte Special

is

determined by the

SFR

8051

contains

permits branching

an

offset provided by

CPU

memory

Data

128

Data

address

128

bytes

Con-

Program

The three pin-compatible versions
reduce development problems to a minimum and provide
maximum flexibility. The

8751

of

this component

is

well

suited for develop-

The

8051

has

five

methods for addressing source oper-

ands: Register, Direct, Register-Indirect, Immediate, and

Base-Register- plus Index-Register- Indirect Addressing.

AFN-01488A-06

2

8051

Architectural Speciffcation ancrFunctionaJ Descrlpfion

64K

t

EXTERNAl-

------

4095

I

INTERNAl-

,

I I

,

-

PROGRAM
COUNTER

The first three methods can
destination operands. Most instructions have a
nation,source" field that specifies the data type, address­ing methods
other than moves, the destination operand
operand.

Registers

through Register, Direct,
dressing; the
Direct or Register-Indirect Addressing; and the

Function Registers through Direct Addressing. External

Data Memory

Addressing. Look-Up-Tables resident in Program

Memory can

Index-Register- Indirect Addressing.

The

80S

internal

Arithmeticl

bits wide. The

byte and double-byte data types.

and

operands

in the four 8-Register Banks can

128

bytes of Internal Data RAM through

is

accessed through Register-Indirect

be

accessed through Base-Register- plus

1

is

classified as an 8-bit machine since the

ROM, RAM, Special Function Registers,

Logic Unit and external data bus are each

80S

1 performs operations on bit, nibble,

be

involved.

or

0

,

,

PROGRAM
MEMORY

Figure 2.1.

used for addressing

For

is

also a source

Register-Indirect Ad-

-"Lr-----A

J

8051

Family Memory Organization

"desti-

operations

be

accessed

Special

8-

64K

OYERl-APPED SPACE

255 I I

1~1..

,

INTERNAl­DATA RAM

INTERNAL

single-byte,
When using a
in

IlJs
instructions (multiply and divide) require only
number of bytes
oscillator periods required for execution are listed in the
appended

I

,

-

DATA MEMORY

and

4S

80S

25S

128

,

SPECIAL
FUNCTION
REGISTERS

4S

two-byte and

12

MHz oscillator, 64 instructions execute

instructions execute in

in

I Instruction Set Summary.

'l

,

each instruction and the number

,

EXTERNAL
DATA
MEMORY

17

three-byte instructions.

4ls.

The remaining

2.1.2 On-Chip Peripheral Functions

Thus

far

only

the

CPU

and

memory

have been described. In addition to the CPU and
memories, an interrupt system, extensive
and several peripheral functions are integrated on-chipto
relieve the CPU
critical tasks and to permit stringent real-time control
external system interfaces. The extensive 110 facilities
include the
address/data bus and the serial port for
The CPU peripheral functions integrated on-chip are the
two 16-bit counters and the serial port. All

together to greatly boost system performance.

of

repetitious, complicated

110 pins, parallel 110 ports, bidirectional

spaces

I/O

I/O

of

,

~s.

The

of

the

80S 1

facilities,

or

time-

expansion.

these work

of

of

The

80S1

has extensive facilities for byte transfer, logic,

at

and integer arithmetic operations. It excels
since data transfer, logic and conditional branch
operations· can be performed directly on Boolean
variables.

The

80S

I's instruction set
instruction set familiar to
allow expansion of
optimize byte efficiency and execution speed.
were reassigned to add new high-power operations and to
permit
operations more orthogonal. Efficient use
memory results from an instruction set consisting of

new

addressing modes which make the old

on-chip· CPU peripherals and to

is

an

enhancement

MCS-48 users.

bit handling

It

is

enhanced to

Op codes

of

of

the

program

49

2.1.2.1

External events and the
peripherals require service by the CPU asynchronous to
the execution
asynchronous activities of these functions to normal
program execution, a sophisticated multiple-source,
priority-level, nested interrupt system
terrupt response latency ranges from
using a

The

sources:
INTI pins, one from each

3

INTERRUPT SYSTEM

real~time-driven

of

any particular section

12

MHz crystal.

80S

I acknowledges interrupt requests from
Two

from external sour.res

of

the two internal counters and

of

3IJs

via

code.

is

the

To

provided. In-

to

7IJs

INTO

AFN-Ol488A-D7

on-chip

tie the

two~

when

five
and

8051

Architectural Specification and Functional Description

one from the serial
separate location
program. Each
of two priority levels and can
and disabled. Additionally all enabled sources can
globally disabled
programmable as either level-

is

active-low to allow the "wire or-ing" of several interrupt

sources

.to

the input pin. The interrupt system

I/O

port. Each interrupt vectors to a

in

Program Memory for its service

of

the

five

sources can

or

enabled. Each external interrupt

be

assigned to either

be

independently enabled

or

transition-activated and

is

shown

be

is

diagrammatically in Figure 2.2.

2.1.2.2 1/0 FACILITIES

The

8051

has instructions that treat its

32

I/O

lines as

32
individually addressable bits and as four parallel 8-bit
ports addressable as

can also assume other functions.

multiplexed low-order address and data bus

expanding the

peripherals.

Port 2 provides the high-order address bus

when expanding the

or

more than

pins of

Port 3 can

256

Ports 0,

1,2

and

3.

Ports

Port 0 provides the

8051

with standard memories and

8051

with external Program Memory

bytes

of

External Data Memory. The

be

configured individually to provide

0,2

used,

and 3

for

external interrupt request inputs, counter inputs, the
serial port's receiver input and transmitter output, and to

generate the control signals used for reading and writing

External Data Memory. The generation
alternate function

on

a Port 3 pin

is

done automatically by

or

use

of

an

the

8051

as

long as the pin is configured as an input. The

configuration

Logic

Symbol

2.1.2.2.1 Open Drain 1/0 Pins

Each pin
output
microcomputer programs each pin as
a one (I) to the pin.
becomes configured as

of

the ports is shown

of

Figure

of

Port 0 can be configured as

or

as a high impedance input. Resetting the

Ifa

2.

zero

(0)

an

output and will continuously

on

the

8051

an

open drain

an

input

by

is later written to the pin it

Family

writing

sink current. Re-writing the pin to a one (I) will place its
output driver in a high-impedance state and configure the
pin

as

an

input. Each

I/O

pin

of

Port 0 can sink two TTL

loads.

2.1.2.2.2 Quasi-Bidirectional

Ports

1,2

and 3 are quasi-bidirectional buffers. Resetting

the microcomputer programs each pin as

(l)

writing a one

to the pin. If a zero (0)

the pin it becomes configured as an output and

1/0

Pins

an

is

later written to

input by

will
continuously sink current. Any pin that is configured as
an

output will

is

written to the pin. Simultaneous to this reconfiguration
the output driver
source current for two oscillator periods. Since current
sourced only when a bit previously written to a zero

be

reconfigured as

of

the quasi-bidirectional port

an

input when a one (I)

will

(0)

is
is

INPUT LEVEL AND
INTERRUPT

FLAG

INTO

......

tNT1

......

REQUEST INTERRUPT ENABLE

REGISTERS:

eXTERNAL

INTRQST0

INTERNAL

TIMER 0

EXTERNAL

INT

RQST 1

INTERNAL

TIMER 1

INTERNAL~

SERIAL

PORT R

• FIVE INTERRUPT SOURCES

•

EACH INTERRUPT CAN BE INDIVIDUALLY ENABLED/DISABLED
ENABLED INTERRUPTS CAN BE GLOBALLY ENABLED/DISABLED

•

•

EACH INTERRUPT CAN BE ASSIGNED TO EITHER OF TWO PRIORITY LEVELS

• EACH INTERRUPT VECTORS TO A SEPARATE LOCATION IN PROGRAM MEMORY
INTERRUPT NESTING TO TWO LEVELS

•
EXTERNAL INTERRUPT REQUESTS CAN BE PROGRAMMED

•
TRANSITION-ACTIVATED

REGISTER:

SOURCE
ENABLE

.....

-

,..

GLOBAL
ENABLE

..AI'"

...AI"'"

I"'"

I'"

r:.

TO

INTERRUPT
PRIORITY
REGISTER:

BE LEVEL-

-

OR

POLLING
HARDWARE

V

1-----

SOURCE

I.D.

V

-----

SOURCE

I.D.

HIGH PRIORITY
INTERRUPT
REQUEST

------

VECTOR

=>

LOW PRIORITY
INTERRUPT

r--

REQUEST

VECTOR

~

Figure 2.2. 8051

Interrupt

4

System

AFN-01488A-08

8051

Architectural Specification and Functional Description

updated to a one (1), a pin programmed as
not

source current into the

pin is

later written with

bidirectional

output
oscillator periods,
proximately 20K- to 4OK-ohms

external

and

2.1.2.2.3

driver's loading

3 can sink/ source one TTL load.

Microprocessor

TTL

gate

that

another

one (1). Since

driver sources current for only two

an

internal pullup resistor

is

provided to hold the

at a TTL

high level. Ports

Bus

A microprocessor bus is provided to permit the
solve a wide range
growth
data

of

user products. This multiplexed address

bus provides
memories,
memories
and

that

timing functions. These are summarized in the

of

problems

an

interface compatible with standard

MCS-80 peripherals

and

to allow the upward

and

include on-chip programmable

Microcomputer Expansion Components

an

input will

is driving

the

it

quasi-

of

80S

the MCS-8S

I/O

chart

of

Figure

if

the

ap-

1,

1

to

and

ports

80S

2.3.
When accessing external memory the high-order address

is

emitted

on

I/O

Expander

Port 2 and

Category

the low-order address

1.0.

8 Line

on

Port

O.

Description

I/O

Expander (Shift Register)

The ALE signal is provided
an

external latch.
signal is provided for enabling
to

Port

0 during a read from the Program Memory
address space. When the
Port

3 automatically generates the read

2

enabling

an

External
generates the write
memory device with the
emits the address
through a push/ pull driver
loads. At the end
automatically reprogrammed
and

Port

2 is returned

cycle. The

80S

1 generates the address,

signals needed by memory

1

that

minimize the requirements placed

program and

data

Memory cycle time is
from stable address
and

lSOns

respectively. The External

for

strobing the address into

The

program store enable (PSEN)

an

external memory device

MOVX instruction is executed

Data

Memory device

(WR)

signal for strobing the external

data

emitted by

and

data

to

the external memory

that

can sink/ source two

of

the read/write bus cycle

to

its high impedance state

to

the state it had

and

I/O

memories.

SOOns

and

Low Cost

and

PSEN

Comments

I/O

At

12

the access times required

are

Expander

(RD)

signal

for

to

Port 0 or

Port

O.

Port

0

TTL

Port

0 is

prior

to

the bus

data

and

control

devices in a manner

on

external

MHz, the Program

approximately 320ns

Data

Memory cycle

Standard

Standard

Multiplexed Address/
Da.ta

'"

C

c

'"

0

Q,

e

0

U

on

QO

Q

QO

•

ell

U

~

'"

;§

;

Q,

e

0

U

RAMs

Standard

Standard

Universal Peripheral

Interfaces 8741A

EPROMs

RAMs 2114A

I/O

Peripherals 8205

2758 I K x 8 450 ns Light Erasable
2716-1 2K x 8 350 ns Light Erasable
2732
2732A

2148
2142-2

8185A

8212
8282
8283
8255A Programmable Peripheral Interface Three 8-bit porgrammable
8251

8286
8287
8253A

8279

8291

8292
8041

4K x 8 450 ns Light Erasable
4K

x 8 250 ns Light Erasable

IK

x 4

100

ns

lK

x 4 70 ns

I K x 4

200 ns

I K x 8

300

ns

A

A

8-Bit Ii 0

8-Bit
8-Bit

Programmable Communications

Interface

I

of
Bi-directional Bus Driver are compatible with the
Bi-directional Bus Driver (Inverting) easy addition

Programmable Interval Timer
Programmable Keyboard/ Display compatible.

GPIB
GPIB Controller

ROM
EPROM

Port

I/O

Port

I/O

Port

8 Binary Decoder MCS-80 and MCS-85 peripheral devices

Interface (128 Keys)

Talker/Listener

Program

Program

User programmable

RAM

RAM

RAM
RAM

.

Memory User programmable to perform custom

Memory

Data

memory can be easily expanded

using standard

Serves as Address Latch

Serial Communcations Receiver/

Transmitter .

Future

I/O

MCS-80/85 devices will also be

and control functions.

and

erasable.

NMOS

of

RAMs.

or

I/O

I/O

ports.

8051·

allowing

specialized interfaces.

port.

Memories with

on-chip

Peripheral 8755-2
Functions.

I/O

and

8155-2
8355-2 2K x 8 300 ns ROM

Figure 2.3.

256 x 8 330 ns

2K x 8

300 ns

8051

Microcomputer Expansion Components

RAM

EPROM

5

AFN-Q1488A-09

8051

Architectural Specification and Functional Description

time

is

IllS

and the access times required from stable
address and from read (RD) or write (WR) command are
approximately 600ns and 250ns respectively.

CRYSTAL
OSCILLATOR

2.1.2.3 TIMER/EVENT COUNTERS

The

8051

contains two 16-bit counters for measuring time
intervals, measuring pulse widths, counting events and
generating precise, periodic interrupt requests. Each can

be programmed independently to operate similar to an

8048

8-bit timer with divide

counter with divide by

32

time-interval or event counter (Mode I), or

by

32

prescaler or 8-bit

prescaler (Mode 0), as a 16-bit

as

an 8-bit

time-interval or event counter with automatic reload

upon overflow (Mode

2).

Additionally, counter 0 can be programmed to a mode

or

or

generate

I's

event

3).

over-

that divides it into one 8-bit time-interval
counter and one 8-bit time-interval counter (Mode

When counter 0
programmed to any

is

in Mode

of

the three aforementioned modes,

3,

counter I can be

although it cannot set an interrupt request flag

is

useful

an interrupt. This mode
flow

can be

used

to pulse the serial port's transmission-rate

because counter

generator. Along with their multiple operating modes and

16-bit precision, the counters can also handle very high

input frequencies. These range from

1.2

(for

MHz to
an input that
and from
(for

0 Hz to an upper limit

1.2

MHz to
external inputs.

12

MHz

crystal) when programmed for

is

a division by

12

of the oscillator frequency

of

12

MHz crystal) when programmed for

Both· internal and external inputs can be

MHzto

50

KHz to 0.5 MHz

1.0

MHz

0.1

gated to the counter by a second external source for
directly measuring pulse widths.

EXTERNAL-.

SOURCE
8048 TIMER/COUNTER

•

• 16-BIT TIMER/COUNTER

• 8-BIT AUTO-RELOAD

EXTSOEURRNCALE

8048 TIMER/COUNTER

•

• 16-BIT TIMER/COUNTER

• 8-BIT AUTO-RELOAD TIMER/COUNTER

$

TIMER/COUNTER

CRYSTAL

°ii~O,.R

-.

__

~~~~~

Figure 2.4.A. Timer/Event Counter

Modes

CRYSTAL
OSCilLATOR

EXTERNAL

SOURCE

• 8-BIT TIMER/COUNTER

$

___

CRYSTAL
OSCilLATOR

CRYSTAL

OSCILLATOR

L--

• 8-BIT

~_--I~

__

~

1---4t----I~

0,

1,

and 2

____

--I~ (INTERRUPT

TIMER

OVERFLOW
(INTERRUPT

REQUEST)
FLAG 0

OVERFLOW
(INTERRUPT

REQUEST)
FLAG 1

PULSE TO
SERIAL PORT

OVERFLOW
(INTERRUPT
REQUEST)
FLAG

1

OVERFLOW
REQUEST)

FLAG 0

The counters are started and stopped under software
control. Each counter sets its interrupt request flag when

aU

it overflows from all ones to

zeros (or auto-reload
value). The operating modes and input sources are
summarized

in Figures 2.4A and 2.4B. The effects

of

the

configuration flags and the status flags are shown in

Figures 2.5A and 2.5B.

GATE

INTO

--~=-~l:'~>-"t"--r-\--J====j~:J

TO------~

XTAl1

COUNTER/TIMER RUN

Figure

2.S.A.

Timer/Counter 0 Control and Status Flag Circuitry

$

EX;5~:~~'"

• 8048 TIMER/COUNTER

• 16-BIT TIMER/COUNTER

• 8-BIT AUTO-RELOAD TIMER/COUNTER

Figure 2.4.8. Timer/Event Counter Mode 3

COUNTER 0

MODE

0:

8-BIT TIMER WITH PRESCALER/8-BIT COUNTER

>----f

6

WITH PRESCAlER

MODE

1:

16-BIT TIMER/COUNTER

2:

8-BIT AUTO-RELOAD TIMER/COUNTER

MODE

3:

8-BIT TIMER/COUNTER (TlO)

MODE

INTERRUPT
REQUEST

PULSE TO

SERIAL PORT

AFN-01488A-l0

8051

Architectural Specification and Functional Description

TIMERI
COUNTER
OIN
MODE 3

INT1

T1

XTAL1

GATE

--

1"'"

~r~

COUNTERI

TIMER

RUN

~

G

Hn

COUNTER 1

MODE

0:

8-BIT TIMER WITH PRESCALERI
8-BIT COUNTER WITH PRESCALER-

MODE

1: 16-BIT TIMER/COUNTER

MODE 2: 8-BIT AUTO-RELOAD TIC
MODE

3:

PREVENTS INCREMENTING
OF TIC 1

J

>-

~

-

1

"'

+12

Figure 2.5.8. Timer/Counter 1 Control and Status Flag Circuitry

-

~

r-r-

-r-

~

~

:=fJ-

-

PULSE

TO
SERIAL
PORT

COUNTER 0

-

J

8-8ITTIMER

(THO)

INTERRUPT
REQUEST

•

)-

• 100r11

Bit

Frame r - - -

• Baud

Rate

from Oscillator

Timer 1 I

• Address Frame

Recognition I

Generetlon I INTERRUPT

or

I

--

- -

SCON

(SERIAL CONTROL)

--

I

I

CONTROL"

TIMING CIRCUITRY

I

g:~~~~t.,.OR

TIMER 1
OVERFLOW

2.1.2.4 SERIAL COMMUNICATIONS

The

8051

has a serial
linking peripheral devices as
through standard asynchronous protocols with full­duplex operatiori. The serial port also has a synchronous
mode for expansion of
shift registers. This hardware serial communications
interface saves

transmission rate than could be achieved through

software. In response

CPU has only to read/write the serial port's buffer to

-

....

1 .....

-:-16

L

______________

Figure 2.6. Serial

I/O

port that

I/O

lines using CMOS and TTL

ROM code and permits a much higher

to

a serial port interrupt request the

is

useful for serially

well

as

multiple805ls

Port~UART

-

--

7

-

---:;:R:;:;S;.-TT-;;-----l

I-

___

~-~-----~

RECEIVER

~~

Modes 1, 2, and 3

service the serial link. A block diagram
shown in Figure 2.6. Methods for linking U
sal asynchronous receiver / transmitter) devices are shown

2.7

in Figure
Figure 2.8.

The full-duplex serial

o modes to facilitate communications with standard U

devices, such as printers and
munications with other

and a method for

___

I/O

I/O

port provides asynchronous

CRT

8051s in multi-processor systems.

-:-

__

_

of

the serial port

ART

expansion

terminals, or com-

~~~~SMIT

RECEIVE
DATA

(univer-

is

shown in

ART

AFN-01488A-11

is

8051 Architectural Specification and Functional Description

I

I

TXD RXD

8051 8051

A. MULTI-80S1

The receiver

is

that would occur if the

TXD RXD TXD

INTERCONNECT

double buffered to eliminate the overrun

CPU
receiver's interrupt before the beginning
frame. Double buffering

8051

since the

can generally maintain the serial link

of

.~

RXD

8051 8051

-HALF

DUPLEX B. MULTI-80S1

Figure 2.7.

RXD TXD

UART

failed to respond to the

of

the next

the transmitter is not needed

at

its
maximum rate without it. A minor degradation in
transmission rate can occur in rare events such as when

of

the servicing

the transmitter has to wait for a lengthy

interrupt service program to complete. In asynchronous

is

modes, false start-bit rejection

For

frames.

noise rejection a best two-out-of-three vote

taken on three samples near the center

provided on received

is

of

each received

bit.

When interfacing with standard UART devices the serial

1)

channel can be programmed to a mode (Mode

or

transmits/ receives a ten-bit frame

or

3)

mode (Mode 2
frame as shown in Figure 2

or

bit, eight

3,

the transmission-rate timing circuitry receives a pulse

nine data bits and a stop bit. In Modes 1 and

from counter
input to counter 1 can

12

of the oscillator frequency. The auto-reload mode

by
of

the counter provides communication rates

that transmits/receives an eleven-bit

..

9.

The frame consists

I each time the counter overflows. The

be

an

external source

programmed

or

that
to

of

a start

a division

of

122

to
31,250 bits per second (including start and stop bits) for a
12

MHz crystal. In Mode 2 the communication rate

of

division by 64

transmission rate of
start and stop bits) for a

the oscillator frequency yielding a

187,500 bits per second (including

12

MHz crystal.

is

~

TXD

RXD TXD RXD

8051

INTERCONNECT

-FULL

Interfacing Schemes

A.1I0INPUT
EXPANSION

B.

a

EXPANSION

Figure 2.8. I/O Expansion Technique

TTY

TYPICAL

a

CRT

RXD

r-----

TXD
CTS

~.

8251

OS
EN

MODE

8051

DUPLEX

8051

DATA

CLOCK

PORT

8051

DATA

CLOCK

PORT

110

OUTPUT

PIN

PIN

TXD
RXD

PORT PIN

8051

C.

8051-8251 INTERFACE

~~~--------~--~--~---'I~

START

START

START 8-BIT

7-BIT

7·BIT

DATA

PARITY'

DATA MARK STOP

DATA

2

PARITY

,

STOP

STOP

Distributed processing offers a faster, more powerful

be

system than can

provided by a single
This results from a hierarchy
processors, each with its own memories and

8051

multiprocessing, a host

of

8051

multiplicity
lyon

separate portions

portion

of

the overall process. The interconnected

s configured to operate simultaneous-

microcomputer controls a

of

the program, each controlling a

reduce the load on the host processor and result in a
cost system

of

data transmission. This form

CPU

processor.

of

interconnected

of

distributed

1/

O.

8051

low-

In

2&3

MULTI­PROCESSOR
COMMUNICA­TIONS

1/0

s

EXPANSION

START

START

....

------------'

a-BIT DATA

a·BITS

9-BIT DATA

j..DATA

__

~~~:I

STOP

STOP

ClK

2&3

o

Figure 2.9. Typical Frame Formats

AFN-01488A-12

8

8051

Architectural Specification and Functional Description

processing
in a complex process are required

is

especially effective in systems where controls

at

physically separated

locations.

and

In Modes 2

3 the automatic wake-up of slave
processors through interrupt driven address-frame
recognition

is

provided

to

facilitate interprocessor com­munications. The protocol for interprocessor com­munications

1.

Slaves

2.

Master-Transmit

3.

Slaves - Serial port interrupts

4.

Master-Transmit

Figure 2.10. Protocol for Multi-Processor

In synchronous mode (Mode
provides
lines using standard

is

shown in Figure 2.10.

-Configure
received ninth

data
data

frame
compares received address to its address.
The slave which has been addressed recon­figures its serial

all subsequent transmissions.

(these will

addressed slave.)

an

efficient, low-cost method

serial

port

to

data

frame containing address in first 8

bits

and

bit designates address frame).

is

Communications

set ninth

received. Interrupt service program

port

control frames and

be

accepted only by the previously

TTL

and CMOS shift registers. The

interrupt

bit

is

a one (I).

data

bit (i.e., ninth

CPU

when address

to interrupt the

0)

the high-speed serial port

of

expanding

CPU

data

if the

CPU

frames

on

I/O

serial channel provides a clock output for synchronizing

. the shifting

rate

is

I M bits

of

bits

a.division

p(:r

second

to/from

by

an

external register. The

12

of the oscillator frequency

at

12

MHz.

data

and

2.2 CPU HARDWARE

This section describes the hardware architecture of the
8051's

CPU

in

detaiL The interrupt system and on-chip
functions peripheral to the
subsequent sections. A detailed
Diagram

2.2.1

is

displayed in Figure

Instruction Decoder

Each program instruction
decoder. This unit generates the internal signals that

control the functions of each unit within the
tion. These signals control the sources and destination
of data, as

well

as the function of the Arithmetic/Logic

Unit (ALU).

CPU are described

8051

Functional Block

2.

II.

is

decoded by the instruction

CPU sec-

in

is

2.2.3 Internal Data Memory

The

8051

contains a I 28-byte Internal

includes registers

R7-RO

twenty memory-mapped

2.2.3.1 INTERNAL

The Internal

Data

RAM provides a convenient 128-byte

in e'ach of four Banks), and

Special Functional Registers.

DATA

RAM

scratch pad memory.

2.2.3.2 REGISTER BANKS

There are four 8-Register Banks within the Internal Data

RAM, each containing registers

2.2.3.3 SPECIAL

FUNCTION

The Special Function Registers include arithmetic registers
(A ,

B,

PSW), pointers (SP,

that provide

an

interface between the CPU and the

DPH,

on-chip peripheral functions.

2.2.3.4 A REGISTER

The A register
location

2.2.3.5 B REGISTER

of

The B register

is

the accumulator register. ACC

the accumulator in the Internal Data Memory.

is

dedicated during multiply and divide and
serves as both a source and a destination. During all other
operations the B register

is

simply another location of

the Internal Data Memory.

2.2.3.6 PSW REGISTER

The carry (CY), auxialiary carry (AC), user flag 0 (FO),
register bank select I (RS I), register bank select 0 (RSO),
overflow (OV) and parity (P) flags reside in the Program
Status Word (PSW) Register. These flags are bit­memory-mapped within the byte-memory-mapped
The PSW flags record processor status information and
control the operation of the processor.

The CY, AC, and

OV

flags generally reflect the status of
the latest arithmetic operation. The P flag
the parity of the A register. The carry flag
Boolean accumulator for bit operations.
are provided in the

"Flag Register Settings" section

2.7.2.
FO

is

a general purpose flag which

stack as

part

of

a PSW save.

The two Register Bank select bits
mine which of the four 8-Register Banks

Data

RAM

R7-RO.

REGISTERS

DPL) and registers

always reflects

Specific details

is

pushed onto the

(RS I 'and

is

selected.

is

RSO)

(which

is

the

PSW.

also a

of

deter-

2.2.2 Program Counter

The I6-bit Program Counter (PC) controls the sequence in
which the instructions stored in program memory are
executed.
instructions listed in section 2.7.2.

It

is

manipulated with the Control Transfer

2.2.3.7 STACK POINTER

The 8-bit Stack Pointer (SP) contains the address at
which the last byte
also the address of the next byte that
is

updatable under software control.

was

pushed onto the stack. This

will

be

popped.

AFN·01488A-13

9

is

SP

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8051 Architectural Specification and Functional Description

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REGISTER BANK 3

REGISTER BANK 2
REGISTER BANK 1
REGISTER BANK 0

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TIMING

CIRCUITRY

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IPC
IEC

SBUF

SCON

TH1
TL1

THO

TLO

TMOD
TCON

DPH
DPL

SP

128·8

RAM

DRIVERS

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PORT 1

PARITY, I

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ROTATE

CONTROLP

INTERRUP

CONTROL

CONTROL

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SERIAL

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PORT

TIMER

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PORT 3

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PROGRAM

CONTROL

CONTROL

ENGINE

INSTRUCTION

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PORTO

4K

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NONE

(8031)

ROM

(8051V

EPROM (87511

DRIVERS

~~

I

~

7-

1

~

R V V

C

S

S

T C S

/

V

P

D

Figure 2.11. 8051 Family Functional Block Diagram

10

AFN-01488A-14

8051 Architectural Specification and Functional Description

2.2.3.8 DATA POINTER

The 16-bit Data Pointer (DPTR) register

of

tion

DPL

Register-Indire91 Addressing to move Program Memory
constants, to move External Data Memory variables, and
to branch over the 64K

registers

(data pointer's low-order byte). The

DPH

(data pointer's high-order byte) and

Program Memory address space.

is

the concatina-

DPTR

is

used in

2.2.4 Arithmetic Section

The arithmetic section of the processor performs many
data

manipulation functions and
Arithmetic/Logic
PSW register.

The AL

sources and generates

of the instruction decoder. The
metic operations
ment, decrement, BCD-decimal-add-adjust and compare

and .the logic operations of and, or, exclusive-or,

complement and rotate [right, left,
four)].

U accepts 8-bit data words from one or two

Unit (ALU), A register, B register and

an

8-bit result under the control

of

add, subtract, multiply, divide, incre-

is

comprised

ALU performs the arith-

or

nibble swap (left

of

the

2.2.5 'Program Control Section

The program control section controls the sequence in
which the instructions stored in program memory are
executed. The conditional branch logic enables conditions
internal and external to the processor to cause a change
in the sequence of program execution.

2.2.6 Oscillator and Timing Circuitry

Timing generation for the

contained, except for the frequency reference which can

be a crystal or external clock source. The on-board
oscillator

frequency range

output of a high-gain amplifier, while XT AL I
A crystal connected between XT AL I and XT AL2
provides the feedback and phase shift required for
oscillation. The
when an external TTL compatible clock
XT AL 1 as the frequency source.

is

a parallel anti-resonant circuit with a

of

1.2

to

t.2 to

12

8051

is

completely self-

12

MHz. The XTAL2 pin

MHz range

is

also accomodated

is

its input.

is

applied to

is

the

2.2.7 Boolean Processor

Although the Boolean processor

8051's architecture, it may
bit processor since it has its own instruction set, its own
accumulator (the carry flag), and its own bit-addressable

RAM and
The bit-manipulation instructions allow the Direct

Addressing of

and

Special Function Registers with an address evenly
divisable
IPC, PSW,

I/O.

128

bits within the Internal

128

bits within the Special Function Registers. The

by

eighqpO, TCON,

A.

and

B)

contain Direct Addressable bits.

is

an integral part of the

be

considered an independent

Data

PI,

SCON, P2, IEC, P3,

RA M

On any addressable bit, the Boolean processor can per­form the bit operations of set, clear, complement,
jump-if-set, jump-if-not-set,

move to/from carry. Between any addressable bit (or its

complement) and the carry flag

operation of logical and or logical
returned to the carry flag.

The bit-manipulation instructions provide optimum code
and speed efficiency in
the control of the
processor also provides a straightforward means of con-

verting
logic design) directly into software. Complex combina­torial-logic functions can be resolved without extensive
data movement, byte masking and test-and-branch trees.

2.3

In the

address spaces and the program counter. The memory

spaces shown in Figure

• 16-bit Program Counter

• 64K-byte Program Memory address space

• 64K-byte External Data Memory address space

• 384-byte Internal Data Memory address space

The 16-bit
with its 64K addressing capabilities. The Program Counter
allows the user to execute calls and branches
tion within the
instructions that permit program execution to move from
the
spaces.

In the

Memory address space

EPROM,
processor can be forced to fetch from the internal

ROM/EPROM
through 4K. Bus expansion for accessing Program

Memory beyond 4K
struction fetches occur automatically when the

Counter increases above 4095.

Program Memory fetches are from external memory.
The execution speed of the
whether fetches are from internal

Memory. If all program storage

4095

prefetch from external Program Memory address 4096.
Certain locations in

specific programs. Locations
reserved for the initialization program. Following reset,
the

Locations
interrupt-request service programs. Each resource that
can request an interrupt requires that its service program
be

11

logic

equations

MEMORY

8051

family the memory

Program Counter register provides the

Program Memory space to any of the data memory

8051

and

respectively.

should

CPU always begins execution at location 0000.

stored at its reserved location.

be left

0003

"bit-banging" applications such as

8051's on-chip peripherals. The Boolean

ORGANIZATION

Program Memory space. There are no

8751

the lower 4K of the 64K Program

for Program Memory addresses 0

vacant

Program Memory are reserved for

through 0042 are reserved for the

j~mp-if-set-then-clear

it

can perform the bit

or

with the result

(like

those

used in

is

organized ever three

2.1

are the:

to

any loca-

is

filled by internal ROM and

By

trying the EA pin high, the

is

automatic since external in-

Program

If

the EA pin

8051

is

an same regardless

or

is

on-chip, byte location

to

prevent

0000 through

is

tied low all

external Program

an

undesired

0002

AFN-01488A-15

and

random

8051

of

are

five

8051

Architectural Specification and Functional Description

The 64K-byte External Data Memory address space.is
automatically accessed when the

MOVX instruction

is

executed.

Functionally the Internal Data Memory

is

the most flex­ible of the address spaces. The Internal Data Memory
space

is

subdivided into a 256-byte Internal Data RAM
address space and a 128-byte
address space as shown in Figure

DATA

INTERNAL

( A ,,------A--,

255

128

55-

ADORE
ABLE
BITS IN
RAM
(128

BIT

S)

REGISTE

RS

-<

~

RAM REGISTERS

255 255

128

-~

127

48

-

127 120

7

32

R7

BANK 3

RO

24

-

R7

16

INTERNAL SPECIAL FUNCTION
DATA

BANK 2

RD
R7

BANK 1

8

RO
R7

BANKO

RO

0

RAM REGISTERS

Figure 2.12. Internal Data

Special Function

2.

12.

SPECIAL
FUNCTION

F8H

248

FOH
E8H
EOH
D8H
DOH
C8H
COH
B8H
BOH
A8H
AOH
98H
90H

135 128

0

88H
80H

Memory

Register"'

ADDRESS­ABLE
BITS IN
SFRs
(128 BITS)

Address Space

The Internal Data
8-Register Banks occupy locations 0 through
stack can

be

address space. In addition,

RAM

address space

is

0 to

255.

31.

Four

The

located anywhere in the Internal Data RAM

128

bit locations of the on-chip

RAM are accessible through Direct Addressing. These
bits reside in Internal Data RAM at byte locations
through

47.

Currently locations 0 through

127

of

32

the
Internal Data RAM address space are filled with on-chip
RAM. Locations

128

through

255

may be filled on later

products without affecting existing software.

is

The stack depth

limited only

Data RAM, thanks to an 8-bit reloadable

The stack

is

used for storing the Program Counter during

by

the available Internal

Stack Pointer.

subroutine calls and may be used for passing parameters.

Any byte of Internal Data RAM or

Special Function

Register accessible through Direct Addressing can be
pushed

The

I popped.

Special Function Register address space

is

128
All registers except the Program Counter and the four
8-Register Banks reside here. Memory mapping the
Special Function Registers allows them to be accessed as
easily as internal RAM. As such, they can
by most instructions. In addition,
the

Special Function Register address space can be

128

be

operated on

bit locations within

accessed using Direct Addressing. These bits reside in the

Special Function Register byte locations divisible

eight. The twenty Special Function Registers are listed

2.

13.

in Figure

Register address space

ARITHMETIC

Their mapping in the Special Function

is

shown in Figure

2.14.

REGISTERS:
ACCumulator*, B register*,
Program Status Word*

POINTERS:

Stack Pointer, Data Pointer (high & low)

PARALLEL I/O PORTS:

Port

3*,

Port

2*,

Port

1*,

Port 0*

INTERRUPT SYSTEM:

Interrupt Priority Control*,
Interrupt Enable Control*

TIMERS:

Timer MODe, Timer CONtrol*, Timer 1
(high & low), Timer 0 (high & low)

SERIAL 1/0 PORT:

Serial

*Bits

CONtrol*,

in

these registers are

Serial data

bit

addressable

BUFfer

Figure 2.13. Special Function Registers

Performing a read from a location of the Internal Data

Memory where neither a byte

RAM

addresses 128-255) nor a Special Function Register

exists

will

access data of indeterminable value.

Architecturally, each-memory space
of

8-bit wide bytes.

By

of

Internal Data RAM (i.e.

is

a linear sequence

Intel convention the storage of
multi-byte address and data operands in program and
data memories

address and the most significant byte

is

least significant byte

at

the low-order

at

the high-order
address. Within byte X, the most significant bit
sented by X.7 while the least significant bit
deviation from these conventions

in

the text.

will

is

be explicitly stated

2.4 OPERAND ADDRESSING

There are five methods of addressing source operands.

They

are

Register

Register-Indirect Addressing, Immediate Addressing,and

Base-Register- plus Index-Register- Indirect Addressing.

The first three of these methods can also

12

Addressing,

Direct

Addressing,

be

AFN-01488A-16

to

is

repre-

X.O.

Any

used to

255.

by

8051

Architectural Specification and Functional Description

SYMBOLIC

ADDRESS

~(

ACC

psw

IPC 1

IEC

SBUF I

SCON

TH1

THO

Tl1
TlO

TMOD

TCON

:~

BIT

ADDRESS

A.

B

'F

231

A

I

215

P3 I 191

183

1

P2 I 175

167

P1

I 159 152 I 144

151

~143 136

SP 129 (81H)

PO 128 (SOH)

135 128

BYTE

ADDRESS

\~

2481

~I:

224 I 208
208 I 184

184

176 I 168

168

160 I 160

144

(FOH)

(EOH)

(DOH)

(B8H)

1

176

(BOH)

(ASH)

(AOH)

(99H)

153

(98H)

152

1

(9OH)

141

(8DH)
140 (8CH)
139 (8BH)
138 (BAH)
137

(89H)
136 (88H)

~:

::::

SFR's
CONTAINING
DIRECT
ADDRESSABLE
BITS

Figure 2.14. Mapping Of Special Function Registers

address a destination operand.
8051

require 0

(NOP

only), I,

Since operations in the

2, 3 or

4 operands, these

five addressing methods are used in combinations to

.8051

provide the

with its

Most instructions have a

data

specifies the

involved.

For

tion operand

type, addressing methods and operands

operations other than moves, the destina-

is

also a source operand.

"subtract-with-borrow

of

result

the value in register A minus

21

addressing modes.

"destination, source'" field that

For

example, in

A,#5" the A register receives the

5,

minus

C.

Most operations involve operands that are located in

Internal Data Memory. The selection of the Program

or

Memory space

second operand

is

unless it
Internal

an immediate operand. The subset

Data

the addressing method and address value.

Special Function Registers can be accessed only

the
thorugh Direct Addressing with an address
summary

of

the operand addressing methods

External Data Memory space for a

is

determined by the operation mnemonic

Memory being addressed

is

determined by

For

example,

of

128-255. A

is

shown in

of

the

Figure 2.15. The following paragraphs describe the five

addressing methods.

Register Addressing permits access to the eight registers

• Register Addressing
R7-RO

--

A,

B,

C (bit), AB (two bytes),

DPTR (double byte)

• Direct Addressing
of

Lower 128 bytes

Internal Data RAM
Special Function Registers
128

bits in subset

of

Internal Data RAM
address space
128

bits in subset

of

Special Function
Register address space

• Register-Indirect Addressing
Internal Data RAM [@R1,

@RO,

@SP
(PUSH and POP only))
Least Significant Nibbles in Internal
Data RAM (@R1,
External Data Memory

@RO)

(@R1,

@RO,

@DPTR)

• Immediate Addressing

--

Program Memory (tn-code constant)

• Base - Register- plus Index-Register- Indirect
Addressing

Program Memory

(@

DPTR+A,

@PC+A)

Figure 2.15. Operand Addressing Methods

7-RO)

(R
four 8-Register Banks

PSW. The registers may also be accessed

of the selected Register Bank (RB). One

is

selected

by

a two-bit field in the

through

Addressing and Register-Indirect Addressing since the
four Register Banks are mapped into the lowest
of Internal

Iflternal

registers are
Direct Addressing provides the only means

the memory-mapped byte-wide
and memory mapped bits within the

Registers and Internal

Data

RAM

as shown in Figure

Data

Memory locations that are addressed as

A,

B,

C,

AB

and

DPTR.

Special Function Registers

Special Function

Data

RAM. Direct Addressing

2.16.

of

bytes may also be used to access the lower
of Internal
access to a

128

bit subset

in Figures

RAM. Direct Addressing

128

bit subset of the Internal Data RAM and

of

the Special Function Registers as shown

2.

12,

2.

14

and

2.

16.

of

Data

Register-Indirect Addressing using the content
RO

in the selected Register Bank,
the Stack Pointer
Internal

Data

(PUSH

and

RAM. Register-Indirect Addressing
used for accessing the External
case, either R 1

or

RO

in

the selected Register Bank may.be

or

using the content

POP

only), addresses the

Data

Memory. In this

used for accessing locations within a 256-byte block. The
block number can be preselected
port. The 16-bit

Data

Pointer may

by

the contents

be

used for accessing

any location within the full 64K external address space.
Immediate Addressing allows constants which are part

AFN'01488A-17

13

of

the

Direct

32

bytes

Other

accessing

of

128

bytes

bits gains

of

R I

or

of

is

also

of

a

8051

Architectural Specification and Functional Description

of the instruction to be accessed from the Program
Memory.

Base-Register- plus Index-Register- Indirect Addressing
simplifies accessing look-up-tables
Program Memory. A byte may
via an indirect move from a location whose address
sum

of

a base register (the

DPTR

(LUT) resident in

be

accessed from a LUT

or PC) and the index·

is

the

register (A).

INTERNAL
DATA

RAMI

STACK

SPECIAL
FUNCTION
REGISTERS

~~

255 255

248
240
232
224

216

208

200

192

164
176
168
160
152
144
136

128 135 128

248

F8H
FOH
E8H
EOH
D8H
DOH
C8H
COH
B8H
BOH
ASH
AOH
98H

90H

88H
80H

DIRECT

ADDRESS-

ING
(BITS)

..,.....:::.-

DIRECT
ADDRESSING
(BITS)

REGISTER
ADDRESSING

STACK-POINTER REGISTER-INDIRECT
REGISTER-INDIRECT ADDRESSING

Figure

2.5

DATA MANIPULATION

The

8051

~

127

7 0

.E.

R7

BANK 3

24

RO
R7

BANK2

RO

.!!

R7

,

BANK

8

RO
R7

BANKO

RO

'-

0

"~--~y

2.16.

~

Addressing Operands In
Internal Data Memory

microcomputer

120

1

) DIRECT ADDRESSING

AND

is

efficient both as an arith­metic processor and as a controller. In addition to the
capabilities of its
with improved data transfer, logic manipulation,

8048

predecessor, the

8051

was

enhanced

arith­metic processing, and real-time control capabilities. The
8051

performs operations on bit, nibble (4-bit), byte
(8-bit) and double-byte (l6-bit) data types.
as an 8-bit machine since the internal

Special Function Registers, Arithmetic/ Logic

It

is

classified

ROM, RAM,

Unit (ALU)

and the external data bus are each 8-bits wide. The

is

double-byte data type
and the

manipulated

Program Counter. The

as

a single double-byte register (DPTR)

used only

by

the Data Pointer

Data

Pointer can

be
or

as two locations

DPL). The Program Counter

in

Internal Data Memory

is

always manipulated as a

single double-byte register.

8051

While the

has extensive facilities for byte logic
operations as well as byte binary and two-digit BCD
arithmetic, it excels in its bit handling capabilities.
bits in the Special Function Registers and

128
flags in the Internal Data RAM are all supported
orthogonally

by

the logic operations of and, or, set, clear,

and complement; the conditional branch operations

jump-if-bit-set, jump-if-bit-not-set, and jump-if-bit-set-

then-clear-bit; and the transfer operation

of

move bit.
Performing conditional branch, logical, and transfer
erations directly on Boolean variables
for microcomputers, since this makes the

is

a breakthrough

8051

byte processor and a Boolean processor.

2.5.1 Data Transfer Operations

Look-up-tables resident
accessed

by

indirect moves. A byte constant can be
transferred to the A register
Program Memory location whose address
base register (the PC
(A). This provides a convenient means for programming
translation algorithms such as
conversions. The Program Memory move operations are
shown diagrammatically in Figure

BASE-REGISTER- PLUS

INDEX-REGISTER-INDIRECT

@PC+A

(PROG MEM 0-64K)

Figure 2.17 Program

A byte location within a 256-byte block of External Data

Memory can

be

accessed using R I or
Indirect Addressing. Any location within the full 64K
External Data Memory address space can

through Register-Indirect Addressing using a 16-bit bas
register (i.e. the Data Pointer). These moves are shown

in Figure

2.18.

The byte in-code-constant (immediate) moves and byte
variable moves within the
detailed

in

Figure

accumulator and the registers in the Register Banks can

be

Direct Addressed, the two-operand data transfer
operations allow a byte to
the

RB

registers, Internal Data, RAM, accumulator and

Special Function Registers. Also, immediate operands

14

in

Program Memory can be

(Le.

accumulator) from the

is

or

DPTR)

and the index register

ASCII to seven segment

2.

17.

REGISTER

A

BASE-REGISTER- PLUS

INDEX-REGISTER-INDIRECT

@OPTR+A

(PROG MEM 0-64K)

Memory

Move Operations

RO

8051

are highly orthogonal as

2.

19.

When one considers that the

be

moved between any two

the sum

in

be

AFN-01488A-18

(DPH

128

software

op-

both a

of

Register-

accessed

&

of

a

..

of

8051

Architectural Specification and Functional Description

REGISTER

A

REGISTER·INDIRECT

(EXT DATA 0-255)

Figure

can

2.18.

be

interest

@R1,@RO

External Data Memory Move Operations

moved to any

is

the Direct Address to Direct Address move

of

these locations.

REGISTER-INDIRECT

@DP

(EXT DATA 0-64K)

Of

particular

which permits the value in a port to be moved to the
Internal
the accumulator. The

with a double-byte immediate value. Also, the

Data

RAM without using any RB registers

Data

Pointer register can

be

or

loaded

8051's
Boolean Processor can move any Direct Addressed bit to
or

from the carry flag.

The A register can be exchanged with a register in the
selected Register Bank, with a Register-Indirect Addressed
byte in the Internal Data RAM or with a Direct Addressed
byte in the Internal
ister. The least significant nibble
be

exchanged with the least significant nibble

Data

RAM

or

Special Function Reg-

of

the A registt;r can also

of

a Register­Indirect Addressed byte in the Internal Data RAM. The
exchange operation

is

shown in Figure 2.20

REGISTER

R7-RO

REGISTER-INDIRECT

@R1,@RO

REGISTER

A

DIRECT

Data

Figure 2.20. Internal Data Memory Exchange

Operations

2.5.2 Logic Operations

The

8051

permits the logic operations
exlusive-or to be performed on the A register by a second
operand which can be immediate value, a register in the
selected Register Bank, a Register-Indirect Addressed
byte

of

Internal

Internal

Data

Data

RAM

ora

Direct Addressed byte

RAM

or Special Function Register. In
addition, these logic operations can be performed on a
Direct Addressed byte

of

the Internal
Special Function Register using the A register as the
second operand. Also, use

of

Immediate Addressing with

Direct Addressing permits these logic operations to set,

clear

or

complement any bit anywhere in the Internal

Data

RAM

or

Special Function Registers without

of

and, or, and

Data

RAM

of

or

REGISTER

C

REGISTER

R7-RO

REGISTER

A

DIRECT

Data

DIRECT

Data

REGISTER-INDIRECT

@R1,@RO

Figure 2.19. Internal Data Memory Move Operations

15

REGISTER

DPTR

16

IMMEDIATE

# data

REGISTER-INDIRECT

@SP

AFN-01488A-19

affecting the
one takes into account that registers R

PSW,RB

registers

or

accumulator. When

7-RO

and the
accumulator can be Direct Addressed, the two-operand
logic operations allow the destination (first operand) to
be a byte

Register, RB registers
the choice
aforementioned or an immediate value. The
also perform a logical or,
Boolean accumulator (i.e. the carry flag) and any bit,

in

the Internal Data RAM, a Special Function

(R

7-RO)

or

the accumulator while

of

the second operand can

be

any

of

8051

or

a logical and, between the

the

can

or
its complement, that can be accessed through Direct
Addressing. The and, or, and exclusive-or logic opera­tions are summarized in Figure 2.21.

• And

(ANL)

.Or(ORL)

• Exclusive-or (XRL)

IMMEDtATE

# data

Figure 2.21. Internal Data Memory

Logic

Operations

In addition to the logic operations that are performed on
Internal

Data

Memory as shown in Figure 2.21, there are
also logic operations that are performed specifically on
the A register. These are summarized in Figure

• Clear

• Complement
Rotate-Laft

•

• Rotate-Laft-Through-Carry

• Rotate-Right

• Rotate-Rlght-Through-Carry

• Swep-NlbbI

..

(Rotate Left Four)

Figure 2.22. Internal Data Memory

REGISTER

A

Logic

2.22.

Operations

(Register A Specific)

Logic

REGISTER

C

(SETB,

ClR,CPL)

Operations

•

Set(SETB)

• Clear

(ClR)

• Complement (CPL)

• Jump-It-BII-Set-Then-Clear-BII (JBC)

Figure 2.23. Internal Data Memory

(Bit-Specific)

add, increment, decrement, compare-to-zero, decrement­and-compare-to-zero, and decimal-add-adjust, the

8051
implemented subtract-with-borrow, compare, mUltiply
and divide.

Only unsigned binary integar arithmetic
the ArithmetiC/Logic

Unit. In the two-operand opera-

is

performed in

tions of add, add-with-carry and subtract-with-borrow,
the A register

is

the first operand and receives the result

of
the operatjon. The second operand can be an immediate
byte, a register

in

the selected Register Bank, a Register-

Indirect Addressed byte or a Direct Addressed byte.
These instructions affect the overflow, carry, auxiliary­carry and parity flags in the Program

Status Word
(PSW). The carry flag facilitates nonsigned integer and
multi-precision addition and subtraction and multi­precision rotation. Handling two's-complement-integer
(signed) addition and subtraction can easily
dated with software's monitoring

ofthe

be

PSWs

accomo-

overflow

flag. The auxiliary-carry flag simplifies BCD arithmetic.

An operation that has an arithmetic aspect similar to a
subtract
tion. This operation

register in the selected Register Bank,

is

the

compare-and-j~mp-if-not-equal

opera-

perforros a conditional branch if a

or

an Indirect
Addressed byte of Internal Data RAM, does not equal an
immediate value;

or

if the A register does not equal a byte
in the Direct Addressable Internal Data RAM, or a
Special Function Register. While the destination operand
is

not updated and neither source operand
the compare operation, the carry flag
the two-operand add/subtract operations

is

affected

is.

A summary of

is

shown in

by

Figure 2.24.

• Add

• Add-With-Carry

• Subtract-With·Borrow

• Compare-And-Jump-II·Not·Equal

DIRECT

Data

(

••••

)

In addition to the and

andor

bit logicals shown in Figure

2.21, there are logicals that can operate exclusively on a
Direct Addressed bit. These operations are listed in
Figure 2.23. The carry flag
and can

be

set, cleared

is

also addressed

or

complemented with one-byte

as

a register

instructions.

2.5.3 Arithmetic Operations

Along with the existing

8048

arithmetic operations of

16

"

,

"

,

,/

'"

,/

,/

,/

,/

'"

REGISTER

R7·RO

Figure 2:24. Internal Data Memory Arithmetic

Operations

REGISTER·INDIRECT

@Rl,@RO

AFN·01488A·20

8051 Architectural Specification and Functional Description

There are three arithmetic operations that operate
exclusively on the
adjust for BCD addition and the two test conditions
shown in Figure 2.25. The decimal-adjust operation
converts the result from a binary addition

BCD values to yield the correct two-digit BCD result.

During this operation the auxiliary-carry flag helps effect
the proper adjustment. Conditional branches may be
taken based on the value in the A register being zero
not zero.

• Declmal-Add-Adjust

• Jump-lf-A-ls.Zero

• Jump-I'·A-Is-Nol·Zero

Figure 2.25. Internal Data Memory Arithmetic

The

805

I simplifies the implementation
counters since the increment and decrement operations
can be performed on the A register, a register in the
selected Register Bank,
Internal Data RAM
Internal Data RAM or Special Function Register. The

16-bit

Data
loop control the decrement-and-jump-if-not-zero opera­tion

is

provided. This operation can test a register in the
selected Register Bank, any Special Function Register
any byte

of

Internal Data RAM accessible through Direct
Addressing and force a branch if it
ment

I decrement operations are summarized in Figure

2.26.

• Increment (INC)

• Decremeilt

• Decremenl-And.Jump-tf-Nol-Zero
(DJNZ)

(DEC)

A· register. These are the decimal-

of

[:EJ

REG~TER

Operations (Register A Specific)

an

Indirect Addressed byte in the

or

a byte in the Direct Addressed

Pointer can

be

incremented.

is

not zero. The incre-

two two-digit

or

of

software

For

efficient

or

::':

Figure 2.27. Internal Data Memory Arithmetic

modate relocatable code. The advantage
memory
a shift
page boundary readjustments to
makes relocation possible. Relocation
permits several programmers to write relocatable modules
in various assembly and high-level languages which can
later

Sixteen-bit jumps and calls are provided to allow branch­ing to any location in the contiguous 64K Program
Memory address space and preempt the need for Program

Memory bank switching. Eleven-bit jumps and calls are
also provided to maintain compatibility with the
and to provide

module.

not push the Program
along with the Program Counter, since many subroutines
written for the
8051
8051

grammatically in Figures 2.28 , 2.29 and

is

that a minor change to a program

of

the code's position in memory will not cause

be

linked together to form the machine object code.

Unlike the 8048, the 8051's call operations do

return operations pop only the Program Counter. The

's branch, call and return operations are shown dia-

REGplSCTER

r

REGISTERT

A I B

REGISTER 1

Operations (Register A with

B Specific)

of

a non-paged

tha(

causes

be

necessary. This also

is

desirable since it

8048

an

efficient

jump

within a 2K program

Status Word (PSW) to the stack

8051

do not affect the PSW. Hence the

2.3f>

respectively.

1"'"4e-_-I-(~_--I~I_MM_E_D_'A_:r_E

_

/16

_ Addr16

,.j

DIRECT

Dala

DEC, DJNZ)

(INC,

REGISTER

R7-RO

(INC, DEC, DJNZ)

REGISTER

A

(INC, DEC)

REGISTER

DPTR

.

(INC)

REGISTER-INDIRECT

@R1,@RO

(INC, DEC)

Figure 2.26. Internal Data Memory Arithmetic

Operations

The mUltiply operation multiplies the one-byte A register
by the one-byte B register and returns a double-byte result
(MSB in

B,

LSB in

A).

The divide operation divides the
one-byte A register by the one-byte B register and returns
a byte quotient to the A register and a byte remainder to
the B register. These are shown in Figure 2.27.

2.6

CONTROL TRANSFER

The

805

I has a non-paged Program Memory to accom-

17

11

Figure 2.28. Unconditional Branch Operations

16

·SP

is pre-incremented.

.

11

*SP

is

pre

..

incremented.

Figure 2.29. Call Operations

AFN-Ol488A-21

8051

Architectural Specification and Functional Description

The

REG~~TER

805

I also provides a method for performing condi-

...

141---I/'-16---t1

Figure 2.30. Return Operation

REGIST:~~~DIRECT

'SP

Is post-dec:remented.

I

tional and unconditional branching relative to the starting

address

bit test operations allow a conditional branch to

on the condition

of

the next instruction (PC -

of

a Direct Addressed bit being set

128

to PC +

127).
be

The

taken

or

not set.· The accumulator test operations allow a
conditional branch based on the accumulator being zero
or

non-zero. Also provided are compare-and-jump-if-

not-equal and decrement-and-compare-to-zero. These are
shown in Figure

• Short Jump

• Jump-If-Blt-Sel

• Jump-If-Blt-Not-Set

• Jump-If-Bil-Set-Then-Clear-Sit

Figure 2.31. Unconditional Short Branch and

The register-indirect
relative to a base register

2.31.

• Jump-If-A-Zero

• Jump-If-A-Not-Zero

•

Dec:remenl-And-Jump-If-Nol-Zero

• Compare-And-Jump-ll-Not-Equal

Conditional Branch Operations

jump

in the

8051

permits branching

(DPTR)

with

an

offset provided
by the non-signed integer value in the index register (A).
This accommodates N-way branching. The indirect jump

is

shown in Figure 2.32.

. Figure 2.32. Unconditional Branch

(Indirect) Operation

2.7

INSTRUCTION

2.7.1

An instruction set
to perform its operations. The ease
instruction set does not depend upon the structure

What the Instruction Set

is

a set

SeT

Is

of

codes that directs a computer

of

understanding the

of

the

machine codes that the computer recognizes,
it depends upon the structure
that

is

used to describe the machine codes.

The

8051

assembly language needs only forty-two mne-

monics to specify the

8051

of

the symbolic language

's thirty-three functions. A

so

function may have several mnemonics (e.g., MOV,

MOVX,
when the Program Memory
is

MOVq

since the function mnemonic specifies

or

External Data Memory

used in conjunction with the Internal Data Memory.

When the function mnemonics are combined with unique
address combinations specified in the

"destination, source"
field, III instructions are possible. The "destination,
source" field specifies the data type and the combination

of

addressing methods to be used to address the destina-

tion and source operands. A summary

instruction set

The syntax

is

provided in Table

of

most

805

2-1.

I assembly language instructions

of

consists of a function mnemonic followed by a
tion, source" operand field. Thus "MOV

be interpreted as "The content

@RO,

of

the Internal

Data" may

Memory location addressed by the content of Register 0

receives the content

of

the Internal

Data

Memory loca­tion addressed by Data." In two operand instructions, the
destination address also serves as the address of the first
source.
interpreted as

example

"The content of the Internal

of

this, "ANL Data, #5" may be

As

an

Memory location addressed by Data receives the result

of

the operation when the content

specified by Data

The

8051

's instruction set

is

and-ed with the immediate 5."

instruction set familiar to MCS-48 users. It
to allow expansion

of

on-chip

of

the memory location

is

an enhancement

CPU

peripherals and to

is

optimize byte efficiency and execution speed. Efficient
use

of

program memory results from

consisting

of

49

single-byte,

45

an

instruction set

two-byte and

byte instructions. Most arithmetic, logical and branching

be

operations can
appends either a short address

performed using an instruction

or

a long address.

example, Register Addressing allows a two byte equiva-

lent

of

the three byte Direct Addressing instructions.
Also, short branches are more code efficient than long
branches.
periods,

64

instructions execute in twelve oscillator

45

instructions execute in twenty-four oscillator

periods, and mUltiply and divide take only forty-eight

of

oscillator periods. The number
tion and the number

of

oscillator periods required for

execution are listed in Table

bytes in each instruc-

2-1.

2.7.2 Organization of the Instruction Set

Instructions are described here in four functional groups:

• Data Transfer

• Arithmetic

• Logic

• Control Transfer

18

AFN-01488A-22

much as

the

8051

"destina-

Data

Data

of

the

enhanced

17

three-

that

For

8051

Architectural Specification and Functional Description

The Data Transfer, Arithmetic and Logic groups men­tioned in the preceding list are further subdivided into an .
array

of

codes that specify whether the operation

act upon immediate, RB register, accumulator,

is

SFR

to

or
memory locations; whether bits, nibbles, bytes or double­bytes are to be processed; and what addressing methods
are to be employed.

DATA

TRANSFER

.

Data

transfer operations are divided into three classes:

• General Purpose

• Accumulator-Specific

• Address-Object

None affect the flag settings except a

PSW.

the

~~~:·~~·.;·1'··:

...

General Purpose Transfers. Three general purpose

POP

or MOV into

data
transfer operations are provided. These may be applied
to most operands, though there are specific exceptions.

MOV performs a bit or a byte transfer from the
source operand to the destination operand.
PUSH increments the

SP

register and then trans­fers a byte from the source operand to the stack
element currently addressed by

POP

transfers a byte operand from the stack

element addressed

by

destination operand and then decrements

the

SP.

SP

register to the

SP.

Accumulator-Specific Transfers. Four accumulator-specific
transfer operations are provided:

XCH exchanges the byte source operand with
register A (accumulator).
XCHD

exchanges the low-order nibble

of

the
byte source operand with the low-order nibble of
register

A.
MOVX performs a byte move between the
External Data Memory and the A register. The

external address can be specified by the

register (16-bit)

or

the

Rl

or

RO

register (8-bit).

DPTR

MOVC performs the move of a byte from the
Program Memory to register A as follows. The
operand in the A register

is

used as an index into
a 256-byte table pointed to by the base register
(DPTR
transferred to

or PC). The byte operand accessed

A.

MOVC

is

used for table-look-up

is

byte translation and for accessing operands from
code-in-line tables.

Address-Object Transfer

MOV DPTR,#data loads 16-bits of immediate

data into a pair of destination registers,

DPL

(DPH from low-order address,

DPH

DPL

and

from

high-order address).

LOGIC

The

8051

performs the basic logic operations on both bit

and byte operands.

Single-Operand Operations. Seven single-operand logical
operations are provided:

CLR

is

used to set eitber the A register, the C

register, or any Direct Addressed bit

SETB sets either the C register

Addressed bit to one
CPL

either forms the one's complement

(1).

to

or

any Direct

operand in the A register and returns the result
to the A register without affecting flags or forms
the one's complement

of

the C register or any

Direct Addressed bit.

RL, RLC, RR, RRC,

SWAP. Five rotate opera­tions can be performed on the A register; RL
(rotate left), RR (rotate right), RLC (rotate left
through C), RRC (rotate right through C) and
SW

AP

(rotate left four).

For

RLC and RRC the C
flag becomes equal to the last bit rotated out.
SWAP rotates the A register left four places to
exchange bits 3 through

0 with bits 7 through

Two-Operand Operations. Three two-operand logical

operations are provided:
ANL performs the bitwise logical conjunction

two source operands (for both bit and byte oper­ands) and returns the result to the location
first operand.

ORL

performs the bitwise logical inclusive dis-

junction

of

two source operands (for both bit and
byte operands) and returns the result to the
tion

of

the first operand.
XRL performs the bitwise logical exclusive
tion of the two source oPerands (byte operands)

and returns the result to the location of the first
operand.

ARITHMETIC

The

8051

provides the four basic mathematical operations.
Only 8-bit operations using unsigned arithmetic are sup­ported directly. The overflow flag permits the addition
and subtraction operations to serve for both unsigned and
signed binary integers. A correction operation
provided to allow arithmetic to

be

peiformed directly on

packed decimal (BCD) representations.

Flag Register
or cleared by arithmetic operations to

Settings. Three one-bit flag registers are set

refl\!ct certain
properties of the result of the operation. These flags are
not affected
tions. A fourth flag (P) denotes the parity

by

the increment and decrement instruc-

of

accumulator bits. These flag registers are located in the

Program

Status Word (PSW) register. Their bit assign-

ment are shown below. A list of the instructions that
affect these flags
Summary"

is

provided in the

"8051

Instruction Set

in Table 2-\' .

AFN-01488A-23

19

zero

(0).

of

the

of

the

loca-

disjunc-

is

also

the eight

4.

of

8051 Architectural Specification and Functional Description

DECIMAL
CARRY

.....

,....--r--P..,

USER

REGISTER BANK
SELECT

FLAG

CY:

Carry Flag (also the C register)

RESERVED

AC: Auxiliary-Carry Flag

OV:

Overflow Flag

P: Parity Flag

FO:

User Flag 0

reserved

RSI: Register Select MSb

RSO:

Register Select LSb

is

set if the operation results in a carry out

or

a borrow into (during sub-

of

the result; otherwise

is

cleared.

is

set if the operation results in a carry

PARITY

out

SYMBOLIC
ADDRESS:

REGISTER:

Unless

CARRY

,...:::.:-....,...I.,...;;:....,....;.,;....,.....;.;.;;.;..-r-..;.;.;..;..,.....;.

PSW.7:
PSW.6:
PSW.2:
PSW.O:
PSW.5:
PSW.I:
PSW.4:
PSW.3:

otherwise stated, the instructions obey these rules:

CY

(during addition)

traction) the high-order bit
CY
AC
the low-order four bits of the result (during addi­tion)

or

a borrow from the high-order bits into
the low-order 4 bits (during subtraction); otherwise
AC

is

cleared.

o V

is

set if the operation results in a carry into the
high-order bit
the high-order bit,
cleared.

OV

of

the result but not a carry out

or

vice versa; otherwise OV

is

of

use in two's-complement arith-

metic, since it becomes set when the signed result

in

cannot be represented

P
accumulator
cleared (even parity). When a value
the
it always reflects the parity

Addition.

INC (increment) performs
source operand and one

is

set if the module 2 sum of the eight bits in the

is

I (odd parity); otherwise P

PSW register, the P bit remains unchanged, as

Four

addition operations are provided:

8 bits.

is

written to

of

A.

an

addition of the

(I)

and returns the result
to the operand.
ADD

performs an addition between the A register
and the second source operand and returns the
result to the A register.
ADDC
between the A register
operand; adds one
viously set and returns the result to register
DA

(add with carry) performs an addition

and

the second source

(1) if the C flag

is

found pre-

A.

(decimal-add-adjust for BCD addition) per­forms a correction to the sum which resulted from
the binary addition of two two-digit decimal
operands. The packed decimal sum formed

DA

is

returned to A. The carry flag

is

BCD result

greater than

99;

else it

is

set if the

is

cleared.

Subtraction. Two subtraction operations are provided:

SUBB (subtract with borrow) performs a subtrac-

tion

of

the second source operand from the first

by

of

of

of

is

is

operand (the accumulator), subtracts one
the C flag

is

found previously set and returns the
result to the A register.
DEC

(decrement) performs a subtraction

(1) from the source operand and returns the

results to the operand.

Multiplication.

MUL performs

an

unsigned multiplication of the
A register by the B register, returning a double­byte result. Register A receives the low-order
byte, B receives the high-order byte.

of

if the top half
is

non-zero. C

the result

is

cleared. AC remains unaltered.

is

OV

zero and

Division.

DIV performs an unsigned division of the A
register by the B register and returns the integer

quotient to register A and returns the fractional

remainder to the B register. Division by zero leaves

indeterminate

OV,

otherwise

data

in registers A and B and sets

OV

is

cleared. C

is

cleared. AC

remains unaltered.

CONTROL TRANSFER

There are' three classes of control transfer operations:

unconditional calls, returns and jumps; conditional jumps;
and interrupts. All control transfer operations cause, some
upon a specific condition, the program execution
continue

at

a noIf-sequential location in program

memory.
Unconditional Calls, Returns and Jumps. Unconditional

calls, returns and jumps transfer control from the current
value

of

the Program Counter to the target address. Both
direct and indirect transfers are supported. The three
transfer operations are described below.

ACALL and LCALL push the address of the next
instruction onto the stack (PCL to low-order
address, PCH to high-order address) and then
transfer control to the target address. Absolute Call
is

a 2-byte instruction used when the target address

is

in the current

instruction that addresses the full

2K

page. Long Call

is

64K

space. In ACALL, immediate data (i.e. an II bit

is

address field)
significant bits
next instruction). If ACALL
a 2K page then the call
page since the

concatenated to the

of

the

PC

(which

is

in the last 2 bytes

will

be

PC

will

have been incremented to

is

pointing to the

made to the next

the next instruction prior to execution.
RET transfers control to the return address saved

on the stack by a previous

SP

decrements the
SP

for the popped address.

AJMP,

LJMP

register by two

and

SJMP
target operand. The operation
LJMP

are analogous to ACALL and LCALL.

call operation and

(2)

to adjust the

transfer control

of

AJ M P and

20

(I)

if

of

one

is

cleared

is

set if it

to

a 3-byte

program

five

most

of

tothe

AFN-01488A-24

8051

Architectural Specification and Functional Description

The

SJMP

transfers within a

(short jump) instruction provides for

256

byte range centered about
the starting address of the next instruction (-128
to + 127).

The PC-relative short jump facilitates

relocatable code.

JMP@

DPTR

A+DPTR

performs

ajump

relative to the

register. The operand in the A register

is
used as the offset (0-255) to the address in the
DPTR
a
space. This

register. Thus, the effective destination for

jump

can be anywhere in the Program Memory

indirect'

jump

is

also useful for

implementing N-way branches.

Conditional Jumps. In the control transfer group, the

con­ditional jumps perform a jump contingent upon a specific
condition. The destination

will

be

within a 256-byte range
centered about the starting address of the next instruction
(-128 to

+127).

JZ

performs a jump

JNZ

performs a jump

if

the accumulator

if

the accumulator

is

zero.

is

not

zero.

JC

performs a jump

JNC

performs a jump

JB performs a jump

is

set.

JNB performs a jump

is

not set.
JBC performs a jump
is

set and then clears the Direct Addressed bit.

CJNE

compares the first operand to the second
operand and performs a jump
C

is

set

if

the first operand

operand;

else

it

if

the carry flag

if

if

if
if

is

cleared.

is

set.

the carry flag

is

not set.

the Direct Addressed bit

the Direct Addressed bit

the Direct Addressed bit

if

they are not equal.

is

less

than the second

Comparis"ons

can

be
made between the A register and Direct Address­able bytes

in

the Internal Data Memory

or

between

an immediate value and either the A register, an

RB register in the selected Register Bank, or a
Register-Indirect addressed byte

Data

RAM.

DJNZ

decrements the source operand and returns
the result to the operand. A jump
the result

is

not zero. The DJNZ instruction makes

of

the Internal

is

performed

if

a RAM location efficient for use as a program
loop counter

by

allowing the programmer to
decrement and test the counter in a single
instruction. The source operand
instruction may be any byte in the Internal

of

the

DJNZ

Data

Memory. Either Direct or Register Addressing

may

be

used to address the source operand.

stack to avoid corruption. Only one interrupt transfer

operation

is

necessary:

RETI transfers control in a manner identical to '
RET. In addition, RET! reenables interrupts for

the current priority

See section

2.8

for further details on the operation and

level.

control of the interrupt system.

2.

7.3

Operand Addressing Modes &

Associated Operations

In section 2.4 the instruction set was explained from the
point

of

view

of

which operands could be used with each
operation. This section lists the operations that can be
used with each addressing method.

As

an

introduction, Figure 2.33.A tabulates the total

addressing mode combinations for one-, two-, three-, and
four-operand operations. The various combinations give
the

8051

programmer great flexibility in writing code.

The following pages provide a handy reference for
mining which function mnemonic can be combined with
the various operand addressing methods. The format
permits a quick reference to how the 8051's memory
spaces may be manipulated.

•

SIngte.O_d

-

DIRECTA_g

- REGISTER AddntooIng

- REGISTER-INDIRECT

• Tw ....

DIRECT,

­DIRECT,
DIRECT.
DIRECT,
REGISTER, DIRECT
REGISTER, REGISTER
REGISTER, REGISTER-INDIRECT
REGISTER,
REGISTER-INDIRECT, DIRECT
REGISTER-INDIRECT, REGISTER
REGISTER-INDIRECT,

• Th ...... Ope<and Opendlona

- REGISTER, BASE REGISTER PLUS

- REGISTER,

- REGISTER,

- REGISTER.

• Four-Operand

- REGISTER,

- REGISTER,

- REGISTER,

Addreoolng

O_allon.

Ad_1ng

O_

... d Operallon.

DIRECT

A_lng
REGISTER Addreoolng
REGISTER-INDIRECT Addreoolng
IMMEDIATE

IMMEDIATE

IMMEDIATE,
IMMEDIATE,
IMMEDIATE,

OperatIons

IMMEDIATE,

IMMEDIATE,

IMMEDIATE,

A_V

A_g

Add_g

IMMEDIATE

Figure 2.33.A.

(O_d

1) - OPERATION

(Operand 1) _ (Operand

A-.ng

Add_g

Addreulng

Add.-ng

Add

.....

1ng

INDEX
DIRECT Addreoolng
REGISTER
REGISTER-INDIRECT

REGISTER, DIRECT Addreoolng
REGISTER.
REGISTER-INDIRECT,

REGISTER INDIRECT Addr

Ad_lng

A_g

IMMEDIATE

8051

Ad_ng

IMMEDIATE

Operand

(Operud

11

OPERATION (Ope<and 2)

Addressing Modes

1)

..

deter-

slng

Interrupts. Program execution control may

by

means of internal and external interrupts.

perform a transfer

stack and then branching to programs located at

the
absolute locations

Memory.
will

be

altered by

The

by

pushing the Program Counter onto

3,

II,

19,

27,

and

programmer must push all registers that

his

interrupt service program onto the

be

transferred

All

35

in the Program

interrupts

'-OperaHon

NOP

Figure 2.33.B. Operand Addressing-

No-Operand Operations

AFN-01488A-25

21

8051

Architectural Specification and Functional Description

• DIRECT

• REGISTER Addressing

• REGISTER-INDIRECT Acldrealng

Note,

Adchuing

- Opet'llnd

RAM

(I11III

RAM (0-127)

Operand

C

A

R7oRO
DPTR

- Opet'llnd
@R1.

@RO

SFR

= Special Funcllon

0-127) or

SFA

or

SFR

(128-255)

[I

•••• RAM (0-255)]

(I11III

Regia'"

128-255)

OperaUon

SETB.CLR.CPL
INC. DEC

Operation

SETB.CLR.CPL

INC. DEC. DA, CLR.

CPL. RL, RLC.
SWAP
INC. DEC

INC

Operation

INC. DEC

Figure 2.33.C. Operand Addressing

Single-Operand Operations

• DIRECT, DIRECT

- Opet'llnd 1 Operand 2

RAM or SFA RAM or

• DIRECT. REGISTER
Opet'llnd 1 OperMCI 2
RAM

C~RAM(IIIIII)

or

SFR

RAMorSFA
RAM or SFR

• DIRECT. REGISTER-INDIRECT AcIdreUIng

- Operand 1 -

RAM

• DIRECT. IMMEDIATE Addressing

-

Opmmd1
RAM

Note:

PM

= Progr

(I11III)

(I11III1

or

SFR

or

SFA

Ad~g

or

SFR

.... M ....

Adchuing

(bI")

ory

SFA

C
C

A
RT-RD

Operand

@R1.

@RD

OperMCl2

PM

(ImmedI"')

. MOV. ANL, ORL, XRL

2

Operation

MOV

Operation

MOV.

ANL, ORL

ANL,ORL

MOV

Operation

MOV

Operation
MOV,

ANL, ORL, XRL

RR.

RRC.

• REGISTER-INDIRECT. DIRECT Addressing
Operand 1 Operand 2
@R1,

@RO[RAM (0-255)]

@SP

[RAM (0-255)]

• REGISTER-INDIRECT, REGISTER Addressing

• REGISTER-INDIRECT. IMMEDIATE Addressing

Figure

1

Operand
@R1,

@RO

[RAM (0-255)] A

@R1.

@RO

[EXT DATA (0-255)] A

@DPTR[EXT

Operand 1
@R1,

@RO

[RAM (0-255)]

2.33.F.

DATA(o-64K)] A

Operand Addressing

RAM

or

SFA

RAM

or

SFR

Opera~2

Opera~

2

PM

(immediate)

Two-Operand Operations

• REGISTER, BASE-REGISTERopIus-INDEX-REGISTER-INDIRECT
Operand 1 Operand 2 • ­A @ DPTR+A MOVC
A @PC+A MOVC
PC @ DPTR+A JMP (IndINcI)

•

REGISTER. IMMEDIATE, REGISTER-INDIRECT

- Operand 1 - Operand 2 - Operand 3
PC

• REGISTER, IMMEDIATE, DIRECT AcIdeuIng

Oper~

PC
PC

• REGISTER, IMMEDIATE, REGISTER Addrasling
Operand'
PC
PC
PC

PM

(Immediate) @SP

1

Operand

2 Operand 3

PM

PM

Operand 2 Operand 3
PM

PM
PM

Operand

AddressIng

RAM

(I11III)

SFR(IIIIII)

RAM •

C

A

RT-RO

3 . Opsrmlon

OperatIon

LCALL,

ACALL

Opsrmlon

or

JB,JNB,
JBC

SFA

DJNZ

0

JC,JNC

JZ.JNZ

DJNZ

Operation

MOV
PUSH.

Operation

MOV
MOYX
MOYX

Operation

MOV

AddressIng

...........

POP

Figure 2.33.D. Operand Addressing

Two-Operand Operations

• REGISTER, DIRECT Addressing
Operand 1 Operand 2
C
A

RT-RO

• REGISTER, REGISTER Addressing
Operand 1 Operand 2
A

R7-RO

A B

• REGISTER, REGISTER-INDIRECT Addressing
Operand 1 Operand 2
A

A @Rl,@RO [EXT DATA
A

PC

• REGISTER, IMMEDIATE Addressing
Operand 1 Operand 2
A

R7-RO
DPTR
PC

Note:

PM

= Program Memory

RAM

(bils)

or

or

SFR

@RO

[RAM (0-255)]

[EXT

(Immedlale)

(Immediate)
(Immedlale)
(Immediate)

SFR

DATA

RAMorSFR

RAM

R7-RD

A

@R1,

(0-255)]
@OPTR
@SP[RAM (0-255)]

PM

PM

PM

PM

(bl")

(o-64K)]

Operalion
MOV
MOV,

ADDC, SUBB,JI.NL,

ORL,

MOV

Operation
MOV,

ADDC, SUBB,ANL,

ORL.
MOV
MUL,DIV

Operation

MOV,
ADDC, SUBB, ANL.
ORL,
MOVX

MOVX
RET,

Operation
MOV,
SUBB, ANL, ORL,
XRL
MOV
MOV
WMP,AJMP,
SJMP

Figure 2.33.E. Operand Addressing

Two-Operand Operations

XCH. ADD,

XRL

XCH,

ADD,

XRL

XCH,

ADD,

XRL,

XCHD

RETI

ADD, ADDC,

Figure 2.33.G. Operand Addressin'g

Three-Operand Operations

• REGISTER, IMMEDIATe, REGISTER. DIRECT

- Operand 1 - Operand 2 - Operand 3 - Operand 4 - Operation
PC

• REGISTER. IMMEDIATE. REGISTER. IMMEDIATE Addressing

- Operand 1 - Operand 2 -
PC
PC PM

• REGISTER, IMMEDIATE, REGISTER-INDIRECT, IMMEDIATE Addressing

- Operand 1 - Operand 2 - Operand 3 - Operand 4 - Operation

PC

PM

PM

PM

AcIdnuIng

A

Oper~

A

RT-RO

@R1.

RAM

3 - Operand 4 - Operation

PM

PM CJNE

@RO

PM

or

SFA

Figure 2.33.H. Operand AddreSSing

FourmOperand Operations

2.8 INTERRUPT SYSTEM

Interrupts result in a transfer of control to a new program
location. The program servicing the request begins
address. In the
can generate
the interrupt service program for each interrupt source
shown in Figure

A resource requests an interrupt by setting its associated
interrupt request flag

detailed

22

8051

there are five hardware resources that

an

interrupt request. The starting address of

2.34.

in

the TCON or SCON register, as

in

Figure 2.35. The interrupt request will be

AFN-Ol488A-26

CJNE

CJNE

CJNE

at

this

is

8051 Architectural Specification and Functional Description

Interrupt Source

External Request 0
Internal Timer/Counter 0
External Request I
Internal Timer/ Counter I
Internal Serial Port

Figure 2.34. Program Memory Location of Interrupt

Service

Programs

Starting Address

3

(0003

H)

II

(OOOB

H)

19

(0013

H)

27

(OOIB

H)

35

(0023

H)

acknowledged if its interrupt enable bit in the Interrupt
Enable register (shown in Figure 2.36)

is

set and if it
the highest priority resource requesting an interrupt. A
resource's interrupt priority level

is

established as high
or low by the polarity of a bit in the Interrupt Priority
register. These bit assignments are shown in Figure

2.37.
Setting the resource's associated bit to a one (1) programs
it to the higher level. The priority of

mUltiple interrupt
requests occurring simultaneously and assigned to the
same priority

The servicing of a resource's interrupt request occurs

level

is

also shown in Figure

2.37.
at

the end of the instruction-in-progress. The processor
transfers control to the starting address of this resource's
interrupt service program and begins execution.

Request Bit

Interrupt Source

External Request 0
Internal Timer/ Counter 0
External Request I
Internal

Internal Serial
Internal

Timer/ Counter I

Port (xmit)

Serial Port (rcvr)

Figure 2.35. Interrupt Request Flags

Interrupt Source Flag Location

External Request 0
Internal Timer / Counter 0

Flag

lEO

TFO

lEI

TFI

TI
RI

Enable

EXO
ETO

External Request I EXI

Location

TCON

.1

TCON.5
TCON.3
TCON.7

SCON.I
SCON.O

Bit

lE.O
IE.!

1E.2
Internal Timer/ Counter 1 ETI IE.3
Internal Serial
Reserved None
Reserved None
All

Enabled

Figure 2.36. Interrupt Enable Flags

Port

ES

EA

1E.4

1E.5

1E.6

1E.7

Within the Interrupt Enable register (IE) there are six

addressable flags. Five flags enable / disable the

five

inter­rupt sources when set/cleared. Setting/clearing the sixth
flag permits a global enable

I disable of each enabled

interrupt request.

Setting/ clearing a bit in the Interrupt Priority register

(IP) establishes its associated interrupt request as a

high/low priority.

If

a low-priority level interrupt

serviced, a high-priority level interrupt will interrupt it.

However, an interrupt source cannot interrupt a service
program of the same or higher level.

Priority

Priority Within

Interrupt Source Flag Level

External Request 0

PXO

.0 (highest)

Internal Timer /

is

Counter

0

External Request 1

PTO

PXl

.1

.2

Internal Timer /

Counter I

Internal Serial

Reserved

PTI

Port

None

PS

.3

.4

(lowest) IP.4

Reserved None
Reserved None

Figure 2.37. Interrupt Priority Flags

The processor records the active priority level(s)
internal flip-flop(s).
flops

is

set while a low-level interrupt

The other flip-flop

One of these non-addressable flip-

is

is

set while the high-level interrupt
being serviced. The appropriate flip-flop
processor transfers control to the service program. The

flip-flop corresponding to the interrupt level being
serviced

is

reset when the processor executes an RETI

Instruction.

To

summarize, the sequence of events for an interrupt

A resource provokes an interrupt

by
associated interrupt request bit to let the processor know
an interrupt condition has occurred. The

hardware latches the interrupt request near the falling-

edge of ALE in the tenth, twenty-second, thirty-fourth

and forty-sixth oscillator period of the instruction-in­progress. The Interrupt request

is

conditioned
the interrupt enable and interrupt priority registers. The
processor acknowledges the interrupt
the two internal

"priority-level active" flip-flops and per-

by

forming a hardware subroutine call. This call pushes the

PC (but not the PSW) onto the stack and, for most
sources, clears the interrupt request flag. The service
program
program when the RETI instruction

is

then executed. Control

is

returned to the main

is
RETI instruction also clears one of the internal
level active" flip-flops.

(lEO,

lEt,

Most interrupt request flags

TFO
cleared when the processor transfers control to the firstl
instruction of the interrupt service program. The TI and

RI interrupt request flags are the exceptions and must be

cleared as part of the serial port's interrupt service

program.

23

is

being

Bit

Location

IP.O
IP.l

IP.2

IP.J

IP.5
IP.6
IP.7

by

setting

being serviced.

is

set when the

is:

setting its

CPU's internal

by

bits in

setting one of

executed. The

"priority-

and

TFl)

are

AFN-01488A-27

is

8051

Architectural Specification and Functional Description

The process whereby a high-level interrupt request inter­rupts a low-level interrupt service program
nesting. In this case the address
in the low-priority service program

stack, the stack pointer

processor control
location

program. The last instruction of the high-priority inter­rupt service program must be an RETI instruction. This
instruction clears the higher
flop. RETI also returns processor control to the next
instruction

Since the lower "priority-level-active" flip-flop has
remained set, high priority interrupts are re-enabled
while further low priority interrupts remain disabled.

The highest-priority interrupt request gets serviced at the
end of the instruction-in-progress unless the request
made in the last fourteen oscillator periods
instruction-in-progress.
instruction
routine call
program will begin execution twenty-four oscillator

periods (the time required for the hardware subroutine
call) after
or, under the circumstances mentioned earlier, twenty­four oscillator periods after the next instruction .

Thus, the greatest delay in response to an interrupt
request

12

are illustrated in Figure 2.38.

Figure 2.38. Best and Worst Case Response

of

the

is

86

MHz). Examples

Instruction

1)

External interrupt request
generated immediately
before (best) / after (worst)
the pin
until end

2)

Current
finishes in

periods

3)

Next instruction
or

DIV

4)

Internal latency for hard­ware subroutine call

is

the first instruction

of

the low-level interrupt service program.

will

also execute before the interrupt's sub-

is

made. The first instruction of the service

completion

oscillator periods (approximately 7

is

sampled. (Time

of

bus cycle.)

or

next instruction

12

rupt Request

is

transferred to the Program Memory

Under this circumstance, the next

of

of

the best and worst case conditions

oscillator

is

MUL don't

of

the next instruction

is

pushed onto the

incremented by two

of

the high-level service

"priority-level-active" flip-

the instruction-in-progress

.

(Oscillator Periods)

Best

Case

+ E

2

12

care

24 24

38

Time

is

called

(2)

and

of

f.JSec

Worst

Case

2-E

12

48

86

to

Inter-

the

@

2.8.1 External Interrupts

The external interrupt request inputs

(INTO

and INTI)

is

can be programmed for either transition-activated or
level-activated operation. Control
rupts

is

provided

External Interrupt Request Flag I
Input INTI Transition-Activated ITI TCON.2
External Interrupt Request Flag
Input

INTO

Figure 2.39. Function

When

ITO

and IT I are set to one (I), interrupt requests on

INTO

and INTI are transition-activated (high-to-Iow);

else they are low-level activated.

interrupt request flags. These flags are set when their

~sponding

INTI,
and the transition-activated scheme
and ITI. When
activated interrupts, the

by

2.8.1.1

The external. interrupt request inputs
can be programmed for high-to-Iow transition-activated
operation. For transition-activated operation, the input

must remain low for greater than twelve oscillator periods,

but need not be synchronous with the oscillator.

internally latched
during an instruction's tenth, twenty-second, thirty-fourth
and forty-sixth oscillator periods and, if the input

lEO
activated input may occur
oscillator period latching time, but the input must remain
high for twelve oscillator periods before reactivation.

2.8.1.2 LEVEL-ACTIVATED INTERRUPTS

The external interrupt request inputs
can be programmed for level-activated operation. The
input
during the instruction's tenth, twenty-second, thirty-fourth
and forty-sixth oscillator periods.
during the sampling that occurs fourteen oscillator periods
before the end of
rupt subroutine call
need be low only during the sampling that occurs fourteen
oscillator periods before the end of the instruction-in­progress and may remain
of the service program. However, the input must
before the service program completes to
envoking a second interrupt.

respectively, are low when sampled

the inputs

TRANSITION-ACTIVATED INTERRUPTS

or

lEI

is

sampled by the

2.9 PORTS

There are 32

pin can

be

by

the four low-order bits of TCON.

Function Flag Location

Transition Activated

(Lower Nibble)

interrupt request inputs

ITO

and ITI are programmed for level-

lEO

and IE I flags are not affected

at

INTO

and INTI respectively.

by

the

8051

is

set. The upward transition of a transition-

at

8051

near the falling-edge

the"

instruction

is

made. The level-activated input

low during the entire execution

AND

I/O

individually and independently programmed

I/O

PINS

pins configured as four 8-bit ports. Each

of

the external inter-

lEI

0

lEO
ITO

of

Bits in TCON

lEO

is

(INTO

near the falling-edge of ALE

any time after the twelve

(INTO

If

the input

in

progress, an inter-

TCON.3

TCON.I
TCON.O

and

lEI

at

INTO

by

selected by

and INTI)

and INTI)

avoid possibly

AFN-01488A-28

24

Bit

are the

the

is

of

ALE

is

be

raised

and

8051

ITO

It

is

low,

low

.

8051

Architectural Specification and Functional Description

as

an

input

or

an

output and each can be reconfigured

dynamically (i.e., on-the-fly) under software control.

An instruction that
operand reads a value that

a port's bit/byte

is

the logical and

as

a source

of

the last

uses

value written to the bit / byte and the polarity being
applied to the pin/pins by an external device (this

of

assumes that none

the 8051's electrical specs are being
violated). An instruction that reads a bit/byte, operates
on the content, and writes the result back to the bit/byte,

reads the last value written to the bit/byte instead
logic level

at

the pin/pins. Pins comprising a single port

ofthe

can be made a mixed collection of inputs and outputs by,
writing a

"one" to each pin that
time an instruction uses a port
operation must write

"ones" to those bits
to the input pins. An input to a port pin need not
synchronized to the oscillator. Each port pin

of

near the falling-edge

or

tenth

twenty-second oscillator period. If an input

transition when it

will

be read as an indeterminate value.

it

ALE during the read instruction's

is

sampled near the falling-edge

The instructions that perform a read

is

to be an input. Each

as

the destination, the

that

correspond

is

sampled

of

of,operation on, and

be

is

in

ALE

write to a port's bit/byte are INC, DEC, CPL, JBC,
CJNE, DJNZ, ANL,
these operations

0 RL, and XRL. The source read by

is

the last value that was written to the

port, without regard to the levels being applied at the

(I)

pins. This insures that bits written to a one
inputs are not inadvertently cleared.

.

When used as a port, Port 0 has

See Figure 2.40.

an

open-drain output.

for use as

When used as a bus, it has a standard three-state driver.

The Port

0 output driver can sink/source two

TTL

loads.

Ports I, 2 and 3 have quasi-bidirectional output drivers
which incorporate a pullup resistor of
as shown in Figure 2.40.B. In Ports

20K- to 40K-Ohms

1,

2 and 3 the output

READ (READ­MODIFY-WRITE)

INTERNAL

BUS

WRITE

ZERO TO ,
TRANSITION

READ
(NON READ­MODIFY­WRITE)

driver provides
if,

and only if, software updates the bit in the output latch

from a zero

----,

+5V

Q

D

o

FLIP
FLOP

Q

1--+-+----1

CLK

PULSE-+--..----'

Figure 2.40.B. "Quasi-Bidirectional"

Port

Structure

s01,lrce

(0)

to a one (I). Sourcing current only on a

current for two oscillator periods

- 2OK-40K

1/0

PIN

PORT",

20R3

"zero to one" transition prevents.a pin, programmed as
an

input, from sourcing current into the external device

is

driving the input pin. The output drivers in Ports

that

1,2

and 3 can sink/source one TTL load.

3.

indi-

Port 3

Secondary functions (RD, WR, etc.) can be selected
vidually and independently for the pins of Port
generates these secondary control signals automatically
as long as the pin corresponding to the appropriate signal
is

programmed as

an

input.

READ (READ-

MODIFY-WRITE)

INTERNAL
BUS

WRITE PULSE

BUS
TIMING

READ

(NON READ­MODIFY-WRITE)

Figure 2.40.A. "Bidirectional" Port Structure

CYCLE

-----,

0

0

FLIP

FLOP

CLK

Q

Q

+5V

":"

2.10

ACCESSING

When accessing external memory the

EXTERNAL

MEMORY

8051

emits the

upper address byte from Port 2 and the lower address

O.

byte, as well as the data, from Port
and two pins from Port 3

is

control. ALE

used for latching the address into the
external memory. The
Program Memory to Port

(RD

PSEN signal enables the external

0,

External Data Memory to Port

latches the data byte emitted by Port

Data Memory. Externally the

It uses ALE, PSEN

and WR) for memory

the

RD

signal enables

0 and the WR signal

0 into the External

PSEN and

RD

signals can
be combined logically if a contiguous external program
and data memory space (similar to a

machine)
latches must
Memory
grammed

is

desired. The P3.7 (RD) and P3.6 (WR) output

be

programmed to a one

is

to

be accessed. When P3.7 and P3.6 are pro-

as

RD and WR respectively, the remaining pins

of Port 3 may be individually programmed

The

8051

can address 64K bytes

is

Memory when the EA pin

tied low. When EA

"von

(1)

if External Data

as

of

external Program

AFN-01488A-29

25

Ne1,lman"

desired.

is

high,

i

tsU~l

ArcnneCtural :specification and Functional Description

the

8051

fetches instructions from internal Program
Memory when the address
from external Program Memory when the addressed
memory location
Ports 2 and
bus based on the value
times are the same for code fetched from internal or

external Program Memory.

Up to 64K
using the
matically configure
external bus. The
RI
Memory. The 16-bit

sive accesses cover a wide range of the 64K space. The

8-bit
when successive accesses are constrained to a 256-byte

block of the External Data Memory space. When using

and
the output latch of Port.
execution
32K or less

Port 2 needs to
the remaining pins can be used for
using

latch

is

returned to its prior value. This permits efficient exter­nal block moves by interleaving MOVX instructions that
use

The ALE signal
during reads from either internal or external Program

Memory. The

lator period when reading from the external Program

Memory. When a read
Memory
WR signal

interval. The
from its Program Memory.
are executed prior to a branch or to an External Data

Memory access, the non-executed byte

8051.
for its execution than for its fetch, the first byte of the
next instruction
instruction completes execution.
address External Data Memory then ALE
every sixth oscillator period and can
external clock. When External Data Memory
external logic may

RD, WR, and ALE to generate an external clock with a

period equal to six oscillator periods.

2.10.1

MOVX instructions. These instructions auto-

or

RO

Rl

and

RO

a subsequent block can be accessed

of

DPTR

is

altered only during the external access and then

DPTR

is

If

an instruction requires more oscillator periods

Accessing External

is

between 4096 and 64K. In either case,

0 are automatically configured as an external

of

External Data Memory can

Port

MOVX instructions

register as a pointer into the External Data

DPTR

RO

registers provide greatest byte efficiency

a MOVX that

of

external memory

be

used for selecting the desired block;

is

executed, the value in Port

and

Rl

or

is

generated every sixth oscillator period

PSEN signal

being performed, a single ALE and a
is

generated during a twelve oscillator period

8051

always fetches an even number of bytes

is

fetched repeatedly while the first

be

is

between 0 and 4095 and

of

the

Pc.

Instruction

0, and often Port

register

2.
uses

RO.

is

or

write from External Data

If

used to combine the occurence

is

used when succes-

Port 2

generated every sixth oscil-

is

Rl

or

is

present, only part

I/O.

an odd number of bytes

is

If

the

executio[}o

be

accessed

2,

as an

use

the DPTR,

by

updating

not affected by

RO

such that, if

When a MOVX

2's

output

RD

ignored by the

CPU

does not

is

generated

be

used as an

is

present,

Memory-Opera-

or

Rl

of

a

of

tion of Ports

The Port 0 bus
both addresses and data. This bus
memory and peripheral devices that incorporate on-chip

is

time mUltiplexed to permit transfer

is

used directly

of

by

address latching (MCS-85 memories with peripherals),

or

it can be demultiplexed with an address latch

generate a non-multiple?Ced bus (MCS-80 peripherals

and memory). During an external access the low-order

byte

of

the address and the
by the Port
written to Port
the Port Ooutput latches will contain ones (I 's) at the end of
the bus cycle, Port
when a bus cycle

8-bits

DPTR
current for two oscillator periods when emitting the
address. Port
level.

0 output drivers. Ones (l's) are automatically

0

at

the very end of the bus cycle. Since

0 will

is

not

of

the address when a MOVX instruction using

is

executed. Port

2's

internal pullup resistors sustain the high

2.10.2 Accessing External

data

(for a write)

be

in its high impedance state

in

progress. Port 2 emits the upper

2's

output drivers provide source

is

Memory-Bus

Cycle Timing

Program Memory Read Sequence (Figure 2.11)

Each Program Memory bus cycle consists
lator periods. These are referred to as
and T6 on Figure 2.41. The address
processor during T3. Data transfer occurs on the bus
during T5, T6 and the following bus cycle's
fetching from external Program Memory, the
always fetch an even number of bytes.
of bytes are executed prior to a branch
Data

Memory access the non-executed byte will be

ignored

(each 6 oscillator periods in duration) can occur between

external bus cycles when the processor

internal Program Memory. The read cycle begins during
T2, with the assertion of address latch enable signal ALE

CD

address information, which
time
required. At T5, the address
bus and the processor's bus drivers go to the high­impedance
control signal (PSEN)

PSEN causes the addressed device to enable its bus
drivers to the now-released bus. At some later time, valid
instruction data will become available on the bus

When the

level
drivers, relinquishing the bus

For the MOVC instruction the op-code
first six-oscillator period, the first byte of the next
struction
iod, the table entry
period and the first byte of the next instruction
fetched

Each External Data Memory bus cycle consists of twelve

oscillator periods. These are shown as T I through T

26

by

the

8051.

An even number of idle bus cycles

. The falling edge

CD

,into

the 8282 latch if a non-multiplexed bus

sta~

8051

subsequently returns PSEN to the high

(})

• the addressed device will then float its bus

is

fetched during the second six-oscillator per-

in

the fourth six-oscillator period.

Data Memory Read Sequence (Figure 2.42)

of

ALE

is

is

. The program memory read

CD

is

is

fetched

is

(3)

present on the bus at this

removed from the

also asserted during T5.

again®.

in

a third six-oscillator

of

six oscil-

n,

T2, T3, T4, T5

emitted from the

Tl.

8051

If

an

odd number

or

an External

is

fetching from

is

used to latch the

is

fetched in the

AFN-Ol488A-30

to

emitted

When

will

is

Port

0

G)

in-

is

again

12

on

8051

Architectural Specification and Functional Description

T12

OSC

ALE

PORT 2

PORTO

ALE

RD

PORT 2

PORTO

ALE

Figure 2.41. Program Memory Read Cycle

CD

V

\0

V

~0

0

X

0 0

INST

Irl

FLOAT

I I I I I

G::

V

A7-Ao

Figure 2.42. Data Memory Read Cycle

\

II

I

FLOAT

ADDRESS A15-Aa

(6)

>(

DATA

Timing

IN

Timing

1/

CD

®

I

I

FLOAT

I

II

FLOAT

ADD RESS

LOAT

ORF

\0

®

PORT 2

PORTO

NOTE: In Figures 2.42 and 2.43 the Prior and Subsequent Machine Cycles access Program Memory.

INST

IN

I FLOAT

I

X

0

A7-Ao

I I

Figure 2.43. Data Memory Write Cycle Timing

~

D<

ADDRESS A15-Aa

27

DATA

I

OUT

@

II

0

ADD RESS

LOAT

OR

F

I

AFN-01488A-31

8051

Architectural Specification and Functional Description

Figure 2.42. The twelve period External
cycle allows the
slower
from the processor during T3.
the bus during T7 through T12.
during which the direction

assertion of address latch enable signal ALE
falling edge of ALE
information, which
into the 8282 latch if a non-multiplexed bus

state

device to enable its bus drivers to the now-released bus.

its bus drivers, relinquishing the bus again

The write cycle, like the read cycle, begins with the asser-

In T6, the processor emits the
addressed

T2

2.11

Two independent 16-bit timer/counters are on-board the

widths, counting events, and causing periodic (repeti­tious) interrupts.

2.11.1

than

read operation. The read cycle begins during T2, with the

At

TS, the address

the processor's bus drivers go

0.

CD

'

is

At some later time, valid
the bus
to

tion

valid on the bus until the end of the following bus cycle's

® . When the

the high level

Data

of

ALE

0.

remains active through

TIMER/COUNTER

80S

1 for use in measuring time intervals, measuring pulse

Timer/Counter Mode Selection

Counter I can be configured

Mode

0)

Mode I) Configures counter 1 as a 16-bit timer/counter.
Mode

2)

Mode

3)

80S 1 to

its program memories. The address

The

asserted during

CD

Memory

CD

data

memory location

The write signal WR goes low

Provides
prescaler
prescaler. A read/write

l's bits
counter
clear the prescaler (counter I's bits 4-0) before
setting the run flag.

Configures counter I
timer / counter. TH I holds the reload value. TL I

is

incremented. The value

TL I when

8048

compatible counter

ing to mode 2 after zero-ing TH
When counter I's mode
mode 3 (from mode
incrementing
providt;d as an alternative to using the
bit

(TCON.6) to start and stop counter I.

use peripherals that are relatively

Data

TS

of

the bus

Q)

is

used

is

present on the bus

is

removed from the

to

data

memor~ad

T7.

RD

data

will become available on

80S1

subsequently returns

' the addressed device will then float

Write Sequence (Figure 2.43)

and

the emission

data

CD

Tl2

® . '

in

one

an

8-bit counter with a divide-by-32

or

an

8-bit timer with a divide-by-32

ofTHI

12-S.

A read/write

l's bits

7-0.

TLt

overflows from

of

the counter. This mode

The programmer should

as

in

is

0, I

Data

Memory

is

emitted

transfer occurs on

and T6

to

the high-impedance

causes the addressed

of

to be written into the

an 8-bit auto-reload

achieved

is

or

is

the period

is

changed for the.

CD

. The

latch the address

at

this time

Port

control signal

CD

an address

. This

data

at

T6

of

four modes:

accesses counter

of

TLt

TH I

is

reloaded into

all

ones (I's). An

1.

reprogrammed to

2), it disables the

is

desired.

0 bus

.

remains

CD

by

configur-

CD

and

RD

RD

Q)

and

accesses

TR

The serial port receives a pulse each time that counter I

overflows. The standard
rate to generate the transmission rate.

Counter
Modes

Mode

'

2.11.2

The use
registers,

.

trol). The counter input circuitry

2.46A

from
the on-chip oscillator (for use as a timer), depending on
whether

When used
frequency
the counter circuitry. When
the external reference input (TI,
input

external input (INTO,

bit
unconditionally enabled. In either case, the normal
interrupt function
the counter's operation. If enabled, an interrupt will
occur when the input at
counters are enabled for incrementing when
TR
the
requests are generated. The functions
are shown in Figure 2.44.

Counter interrupt request and

Counter enable/disable bit
Counter interrupt request and

is

I

Counter enable/disable bit

0 can also

0-2) Modes 0-2 are the same as for counter I.

3)

In Mode
affected by the bits in
next section).
timer that
TCON's
TFI

flag gets set. Thus, neither

is

available to counter I when counter 0

Mode

3.
placing counter I in Mode
function
counter

8-bit timer/counter and

by the Gate
(TCON.4) and

Configuring the Timer/Counter Input

of

the timer/counters

TMOD

and 2.468. The input to the counter circuitry

an

external reference (for use as a counter),

TMOD's

is

is

gated to the counter conditional upon a second

is

zero (0), the external reference

I and

TRO

TFI

and

overflow Flag

overflow Flag

Figure 2.44. Function

(timer mode) and TCON (timer

CIT bit

as

a time base, the on-chip oscillator

divided

bits are set. When the counters overflow

TFO

Function

U

AR

T modes divide this pulse

be

configured in one

3,

the configuration

TMOD

It

is

configured solely as

is

enabled for incrementing by

TRI

bit. Upon THO's overflow the

The function of

of

TF I is

I.

In Mode

(TMOD.3), CIT (TMOD.2),

TFO

is

set

by

twelve (12) before being input to

TMOD's

INTI)

being high. When the Gate

of

INTO

and INT I

INTO

bits

in

TCON get set and interrupt

(Upper Nibble)

TR

I can be done

actually given up by

3,

TLO

is configured as

is

controlled, as usual,

(TCON.S) control bits.

is

determined by two 8-bit

is

shown

or

cleared, respectively.

Gate bit

TO)

or

or

oscillator input

is

not affected by

or INT I

of

the bits in TCON

Flag

TFI

TRI
TFO

TRO

of

Bits in

28

of

four modes:

of

THO

is

or

TCON (see

an

8-bit

TRI

nor

TFI
is

3,

so only the

TRO

con-"

in

Figures

or

from

is

set (I),

the oscillator

is

low. The

TCON's

Bit

Location

TCON.7

TCON.6
TCON.S

TCON.4

TeON

AFN-01488A-32

not

in

by

an

is

is

8051

Architectural Specification and Functional Description

The functions

2.45. Recall from section

of

the bits in

TMOD

2.3

that the bits in

are shown in Figure

TMOD

are

not bit addressable.

Bit

Function

Enable input
Counter

I/T

C

I/T

C

Enable input to

at

TI using INTI

1/

Timer 1 select
1 Mode select MSb
I Mode select LSb

TO

using

INTO

Counter 0/ Timer 0 select

OfT

0 Mode select MSb

C
C 0/ T 0 Mode select LSb

Figure 2.45. Functions of Bits

Flag

Location

Gate TMOD.7

CIT

Ml

MO

TMOD.6
TMOD.5
TMOD.4

Gate TMOD.3

-

in

TMOD

TMOD.2
TMOD.l
TMOD.O

CIT

Ml
MO

2.11.3 Operation

The counter circuitry counts up

O's

overflows to either
overflow,

TFI

or

TFO

changes the timer's mode

or

gets set. When an instruction

or
actual change occurs at the end
execution.

The T I and

TO

inputs are sampled near the falling-edge
of ALE in the tenth, twenty-second, thirty-fourth and
forty-sixth oscillator periods

progress.

oscillator period of

They are also sampled in the twenty-second

MOVX despite the absence of ALE.

Thus, an external reference's high and low times must each

of

be a minimum

is

There

a twelve oscillator period delay from when a

twelve oscillator periods in duration.

toggled input (transition from high to low)

is

when the counter

incremented.

to

all l's and then

the reload value. Upon

alters its control bits, the

of

the instruction's

of

the instruction-in-

is

sampled to

2.11.4 Reading and Reloading the Timer/
Counters

The timer/counters can be read and reloaded on the
However, the 16-bit timer/counters must be read and
loaded as two 8-bit bytes. During a read the potential
"phasing error" can be programmed around, as follows:

MOV

A,

A,

THO

TLO

THO,

RTC

RTC

MOVB,
CJNE

fly.

2.12 SERIAL CHANNEL

The

8051

has a serialchannel useful for serially linking

UART (universal asynchronous receiver/transmitter)

I/O.

devices and for expanding
I/O

port can be programmed to function in one

This full-duplex serial

of

four

operating modes.

0) Synchronous

Mode

I/O

expansion using

TIL

or

CMOS shift registers

1)

Mode

UART interface with to-bit frame
and variable transmission rate

2)

U

ART

Mode

interface with II-bit frame

and fixed transmission rate

Mode 3)

interface with

II-bit

frame

U

ART

and variable transmission rate
Modes 2 and 3 also provide automatic wake-up of slave
processors through interrupt driven address-frame
recognition for multiprocessor communications.
schemes
and an

2.12.1

of

UART interfacing are shown in Figure 2.47

I/O

expansion technique

is

shown in Figure 2.48.

Serial Port Control and Data Buffer

Several

Registers

Data for transmission and from reception reside in the

serial port buffer register

(SBUF). A write to SBUF

COUNTER 0

MODE

0:

8-8IT TIMER WITH PRESCALER/
8-BIT COUNTER WITH PRESCALER

MODE

1:

l8-BIT
MODE
MODE

TO-----'

XTAL1

Figure 2.46.A. Timer/Event Counter 0 Control and Status Flag Circuitry

29

TIMER/COUNTER

2:

8-BIT AUTO-RELOAD TIMER/COUNTER

3:

8-BIT TIMER/COUNTER

(TLO)

AFN-01488A-33

8051

Architectural Specification and Functional Description

COUNTER 1

MODE 0: 8-BIT TIMER WITH PRESCALER/
MODE

1:

2:

MODE
MODE 3: PREVENTS INCREMENTING

T1

___

--I

8-BIT

COUNTER WITH PRESCALER
16-BIT TIMER/COUNTER
8·BIT

AUTO·RELOAD TIC
OF

TIC

PULSE TO
SERIAL PORT

XTAL1

Figure 2.46.8. Timer/Event

TXD RXD TXD RXD TXD RXD RXD TXD TXD

8051 8051

A.

MULTI·8051

INTERCONNECT-HALF

8051

DUPLEX

Figure 2.47.

8051

DATA

CLOCK

PORT PIN

A.

IiOINPUT

EXPANSION

8051

.OATAt---

CLOCK

PORT PIN

B.

IiOOUTPUT

EXPANSION

Figure 2.48.

14----1

....

I/O

Expansion Technique

SIN

as

EN

Counter 1 Control

~

8051

B.

MULTI·8051

UART

COUNTER

and Status Flag

0

Circuitry

~

TXD

RXD

8051 8051 8051 8251

INTERCONNECT-FULL

RXD

DUPLEX

TXD

r----

RXD

PORT PIN

~

C.

8051·8251 INTERFACE

RXD
TXD

ffi

Interfacing Technique

updates the transmitter register, while a read from SBUF
reads a buffer that
if / when flag RI
eliminate the overrun that would occur

is

updated by the receiver register

is

reset. The receiver

is

double buffered

ifthe
to respond to the receiver's interrupt before the beginning
of the next frame. In general double buffering of the

is

transmitter

not needed for the high performance
to maintain the serial link at its maximum rate. A minor
degradation in data rate can occur in rare events. such as
when the servicing of the transmittter has to wait for a

to

lengthy interrupt service program

complete. In
asynchronous mode, false start-bit rejection
on received frames. A two-out-of-three vote
each received bit for noise rejection. The serial port's

is

control and the monitoring of its status

provided
serial port control register (SCON). The contents of the
8-bit SCON register are shown in Figure 2.49.

30

to

CPU failed

8051

is

provided

is

taken on

by

the

AFN·01488A·34

8051

Architectural Specification and Functional Description

Bit

Function

Serial Port Operation

Flag

SMO

Location

SCON.7

Mode (MSb)

Serial

Port Operation

SMI

SCON.6

Mode (LSb)

Conditional Receiver

SM2

SCON.5

Enable

Receiver Enable

Transmitter Data Bit 8

Received Data

Bit

8

Transmission Complete

REN

TB8

RB8

TI

SCON.4
SCON.3
SCON.2
SCON. I

Interrupt Flag

Reception Complete

RI

SCON.O

Interrupt Flag

Figure 2.49. Functions

Mode control hits S

in one

of

four operating modes. A detailed description

the modes

is.

provided in section 2.12.2. The receiver-

MO

and

of

Bits

in

SCaN

S M I program the serial port

of

enable bit (REN) resets the receiver's start/stop logic.

When software sets REN to one

transmission-rate generator

is

initialized and reception
enabled. REN must be set as part
initialization program. When REN
is

disabled.

The

CPU

is

informed

SB

UF

is

empty

or

respectively. TI and RI must

that

the transmitter portion .of

the receiver portion

be

(1), the receiver's

of

the serial channel's

is

cleared, reception

is

full by TI

cleared as part

and

of

is

RI

the
interrupt service program so as not to continuously
interrupt the
generate the serial port's interrupt request, they must

polled to determine· the source

CPU. Since TI and RI are or-ed together to

be

of

the interrupt.

2.12.2 Operating Modes

2.12.2.1

The
number
output
into or from

out each time a
data buffer (SBUF), even if TI
clears the RI flag, eight bits are shifted into

the RI flag

REN set to one (I)] for reception to occur.

The synchronizing clock is output

from high to low near the falling-edge

fifteenth oscillator period following execution

instruction
then toggles near the falling-edge

subsequent sixth oscillator period until 8-bits are

transferred. The eighth rising-edge of clock

RI or TI flag. At this point shifting
clock
at the beginning

OPERATING MODE 0

1/0

expansion mode, Mode 0,

of

input and output pins. In this mode, a clock

is

provided for synchronizing the shifting

an

external register. Eight bits
data

byte

is

written to the serial channel's

is

again set. The receiver must

that

updated SBUF

is

used to expand the

is

set. Each time software

be

on

pin P3.1

or

cleared the RI flag.

of

is

complete and the

is

once again high. The first bit

of

the eighteenth oscillator period

is

shifted out

of

bits

will

be

shifted

SBUF before

enabled [i.e.,

and

toggles

of

ALE in the

of

the

ALE in each

(P3.1) sets the

of

P3. 0

following the instruction that updated SBUF. The first

bit shifted in from

edge

in

the twenty-fourth oscillator period following the

instruction

that

P3.0

is

latohed by the clock's rising-

cleared the RI flag. One bit

every twelvth oscillator period until all eight bits have

been shifted.

2.12.2.2 OPERATING MODES

In the

UART

rate

is

sub-divided into

is

determined by taking a majority vote after it has

bit

Modes (i.e., I through 3), the transmission

16

"ticks." The value

1-3

been sampled during the seventh, eighth and
"ticks".
be given a one

If two

or

three ones (I's) are detected, the bit will

(I)

value; if two

or

three zeros

detected, the bit will be given a zero (0) value.
Until a start bit arrives, the receiver samples the

input pin (P3.0) every "tick". One-half bit time
(eight "ticks") after the start bit
input level was sampled on
checks its validity (majority vote from
and

nine) and accepts

of

false start bits.

The contents

of

or

rejects it. This provides rejection

the receiver's input shift register

to SBUF and RB8 (Modes 2 and

1)

a frame's ninth (Mode

received. Upon reception

tenth bit, the
ferred to
the RI flag.

data

bits in the shift register are again trans-

SBUF and RB8, but only if software has reset

If

RI has not been reset, then overrun

or

of

occur since the shift register

is

detected (i.e., a low

"tick" one), the serial port

"ticks" seven, eight

3),

and RI

tenth (Modes 2 and

a second frame's ninth

will

continue to accept bits.

Double buffering the receiver provides the

frame-time in which to empty the SBUF and
ters. The RI flag

ninth

"tick"

is

set and bit RB8

of

the received frame's ninth

is

loaded during the

The serial port begins looking for the next start bit

one-half bit time after the center of a stop bit
Data

is

transmitted from the

time a byte

at

the beginning

is

written to SBUF, even if TI

of

the transmitted tenth (Mode

eleventh (Modes 2 or

SBUF

is

written-to prior to the end

eleventh) bit, the transmission

bit

will

not begin until the end

In Modes 2 and 3,

ifSM2isset,

TXD

output pin (P3.1) each

3)

bit. After TI becomes set, if

of

the stop (tenth

of

the next frame's

of

the stop bit.

frames are received
interrupt request is generated only when the received
bit 8 (RB8)

is

a one (1). This feature permits interrupt

generated wake-up during interprocessor com-

It

munications when mUltiple
serial bus. Thus,
on

the serial bus only when the master

data

bit 8 (RB8) awakens all processors

8051

's are connected

is
address to a different processor. Each processor not
addressed then ignores the subsequent transmission
control information and data. A protocol for multi-80S I
serial communications
bit has no effect in Modes

31

is

shown in Figure 2.50. The SM2

0 and

l.

is

shifted

of

a received

ninth

(O's)

are

RXD

is

moved

is

set, when

3)

bit

is

or

will

CPU with one

RB8

regis-

or

tenth bit.

is

received.

is

set. TI

is

1)

set

or

or

start.

but

an

data

to

changing the

of

AFN-01488A-35

a

8051

Architectural Specification and Functional Description

1. The hardware In each slave's serial
begins
of
the slave's SM2
"Interrupt

by

listening

for

an addre88. Receipt

an addre88 frame will force an Interrupt

bit

Is set

to

one (1) to enable

on addre88 frame only".

2. The master then transmits a frame
taining the
to

receive the subsequent commands and

8-blt

address

of

the slave that Is

data. A transmitted addre88 frame has

ninth data

3.

When the addre88 frame Is received, each

s'ave's

bit

serial

(TB8) set equal

port

Interrupts its CPU. The

to

CPU then compares the addre88 sent

port

con-

one (1).

to

If

Its

Its

own.

4.

The

8051

stave which has been addressed

then resets

Its SM2
all subsequent transmissions.
8051's leave their SM2 bits at a one (1)

bit

to zero (0)

to

receive

All

other

to
Ignore transmissions until a new address
arrives.

5.

The master device then sends

matlon and data, which In
by the previously addressed
one that had set

Figure 2.50. Protocol

Its SM2 bit to zero (0)].

for

controllnfor-

tum

Is accepted

8051

[i.e., the

Multl- Processor

Communications

2.12.3 The Serial Frame

A frame
received in Mode 0
frame are transmitted

The frame transmitted and received in Mode

in length. The frame transmitted and received in Modes 2
and
start bit, eight

7 are loaded into SBUF.O-SBUF.7 respectively, and
bit 8 into RB8 (receive)

software overhead, the last

bit, as shown in Figure 2.51.

is

a string

3

is

eleven bits in length. These frames consist

or

of

bits. The frame transmitted

is

8 bits in length. The

nine

data

SBUF.O first

bits and a stop bit.

or

TB8 (transmit). With nominal

data

and

bit can

be

and

data

bits

of

SBUF.7 last.

1 is ten bits

of

one

Data

bits 0-

data

made a parity·

the

110BAUDTTV

I START I

I START I

I START 1

I STAAT IDATA.oj

DATA

.01

.1

1·21

TYPICAL ASCII TERMINAL

DATA

.01

.1

1·21

DATA.O

1

.1

I

.1

1.21.31.41.51.&1.71.81

OR
.21

.31

.41

.31 .41

.31

.41 .51

OR

.51

.51

.61

.61

.6 I .7 1

PARITY I STOP

PARITY

1 STOP I

PARITY j STOP

STOP I

I STOP I

I

Figur.e 2.52. Typical Frame Formats

2.12.4 Transmission Rate Generation

The proper timing for the serial
transmission-rate generator.
different methods

of

transmission rate generation are
provided. The transmission-rate achievable
upon the operating mode

In the

I/O

expansion mode (Mode 0) the oscillator
frequency is simply divdied by
transmission rate. This produces a transmission rate

1M bits per second

at

12
used, the transmission rate can be generated from the
oscillator frequency

or

from

quency. In these modes, either one-twelfth the oscillator

frequency

or

the

TI

input frequency
minus-the-value-in-TH I (counter
in auto-reload mode by software) and then divided by
32

to generate the transmission rate. When the oscillator
frequency input (rather than
produces a transmission rate

second (including start and stop bits)
external input

When Mode 2

is

selected by setting the

is

used, the oscillator frequency
divided by 64 to generate the transmission rate. This
produces

a transmission rate

(including start and stop bits)

I/O

On-board the

of

the serial port.

MHz.

If

Modes

an

external reference fre-

I must

TI)

is

of

122

of

187,500

at

12

data

is

provided by a

8051,

three

is

dependent

12

to generate the

lor

3 are being

is

divided by 256-

be

configured

selected, this method

to 31,250 bits per

at

12

MHz. The TI

C;Tbit

to one (1).

is

simply

bits per second

MHz.

of

MOV C, P ; Parity moved to carry (byte

already in

A).

MOV TB8, C ; Put carry into Transmitter Bit 8

MOV SBUF, A; Load Transmit Register

Figure

2.51.

Generating Parity and
Transmitting Frame

Figure 2.52 shows some typical frame formats for
different applications. The
transmitted least significant bit first

data

bits

of

the frame are

(SBUF.O) and TB8

last.

2.12.5 UART Error Conditions

There are two

accounted for when designing systems
channel.

First, the
a valid stop bit has been received. However, since a start
bit

is

detected as a high-level

UART

will

not received.
Second, the RI flag

from the receiver's input shift register when the received

UART

error conditions

that

that

should be

use the serial

805I's serial channel provides no indication

to

low-level transition, the

not

receive additional frames if a stop bit

is

set and

SBUF

and RB8 are loaded

AFN-01488A-36

32

that

is

8051

Architectural Specification and Functional Description

last data bit (i.e. ninth or tenth received bit)

As

long

as

RI

is

set, the loading of SBUF, the updating

RB8

and the generation

inhibited. Thus, overrun
does not reset RI before reception
data bit since the receiver's input shift register will shift in
a third frame.

of

further receiver interrupts

will

occur

if

of

the next frame's last

is

sampled.

of

is

the programmer

2.13 EXTERNAL INTERFACE

2.13.1 Processor Reset and Initialization

Processor initialization

of

the RST

should be held high for

periods.
high for

allow the oscillator to stabilize. Upon receipt of RST, the

processor ceases instruction execution and remains

dormant for the duration
transition then initiates a sequence which requires

approximately twelve oscillator periods
ALE

the instruction
ends with registers initialized as shown in Figure 2.53.

/VPO

Upon powering up, RST

at

least I

is

generated and normal operation commences with

at

is

accomplished with activation

pin. To reset the processor, this pin

at

least twenty-four oscillator

/VPO

ms

after the power supply stabilizes

of

the

pUlse.

absolute location

OOOOH.

should

The low-going

to

execute before

be

This sequence

held

to

The Schmitt-trigger input has a small internal pull down
resistor which permits power-on reset (as shown in Figure

VCe.

2.54) using only a small capacitor tied to
ventional external reset circuit, such as that in Figure

2.55, can also be used.

+5V

....

v

+5V

L

~o-~~-._R_S_TN_P_O;-

RSTNPD

8051

____

8051

~

A con-

t

Register

PC
SP
PSW, OPH, OPL,

IP, IE,
TMOO,
TLl,

SBUF

Port 3-PQrt 0

Internal RAM

In addition, certain of the control pins are driven to a
TTL high level during initialization. These are ALE/

PROG and PSEN. Thus, no ALE or PSEN signals are
generated while RST /
is

SCaN,

THl,

TLO

Figure 2.53 Register Initialization

reset all ports are immediately written with ones (l's).

A,

TCON,

THO,

VPD

+5V

Content

OOOOH
07H

B,

OOH
OOH
OOH
OOH

Indeterminate
FFH

(configures all

pins as inputs)

Unchanged if

applied; else
indeterminate

is

high. When the processor

8051

I/O

VPO

t

RSTNPD

Figure 2.54. Power-On Reset

Figure 2.55. External Reset

2.13.2 Power Down (Standby) Operation of
Internal RAM

Data can be maintained valid in the Internal Data RAM

8051

is

while the remainder of the

powered down, the
normal operating power. During normal operation, both

CPU

the

VCC. However, the internal RAM
from
a diode drop below that on

RSTNPO

When a power-supply failure
system generates a
processor via
must be early enough to allow the
that
operating limit. The program servicing the power-failure

interrupt request must save any important data and

machine status into the Internal Data RAM. The service

33

and the internal RAM derive their power from

RST/VPD

VCC

---------i'-

__

wro~~--------~~~~~I

(POWER·FAIL) INTERRUPT I I

--------_.

NORMAL OPERATION SERVICE

Figure 2.56. Power-Down Sequence

INTO

is

relevant for recovery before VCC falls below its

8051

consumes about

when the voltage on VCC

I I I

"power-failure" signal to interrupt the

or INTI. This power-failure signal

powered down. When

will

derive its power

RST/VPD.

......

___

I I

__

------+I

I I

I I

~i-----tl

PROGRAM

is

rffl----

NORMAL OPERATION

imminent, the user's

8051

to save all data

10%

is

more than

____

____

•

AFN-01488A-37

of its

----

__

8051

Architectural Specification and Functional Description

program must also enable the backup power supply to

RST/VPD

the
resets the
as the VCC power supply falls below limit. Normal opera­tion resumes when

2.56 shows the waveforms for the power-down sequence.

pin. Applying power to the RST/VPD pin

805

I and retains the internal RAM data valid

RST/VPD

is

returned

low.

Figure

2.14 EPROM PROGRAMMING

The

8751

is

programmed and the

verified using the

gramming and

Port pins 2.0-2.3. Pins P2.4 and P2.5 are held to a

and

low.

TTL

RST/VPD

at

a TTL low

gram,

ALE/PROG
PROG
Port pin
impedence state when held

at

will
state.

is

held

2.7

a TTL low

leave the EPROM programmed to an all one's (I's)

2.15 THE

UPP-851 programming card. For pro-

verification, address

Data

is

input and output through Port

is

held at a TTL high level and PSEN

level

during program and

is

held at a TTL low level. ALE/

at

a TTL high level to verify the program.

forces the Port 0 output drivers to the high

at

a TTL high level and

level

for verification. Erasure

8051

AS

AN EVOLUTION OF

8051

and

8751

is

input on Port I

verify.

To

of

an

is

is

are

held
pro-·

held

8751

THE 8048

For

every

8048

instruction there
instruction,
tions.
for the
addressing. Thus, while the
in its instruction coding, the functions

be

performed
a conversion program
assembly source code to

8051

the
field in the

pointer does not
but

will

that manipulates the stack pointer cannot

by

CONV-51. In translating
an unused RAM location can

PSW using the PUSH instruction with Direct Addressing

to keep the

8048
seven bits of RI and
use all eight bits. Thus, bit seven (and bit six for
programs) must

8048
8051
control the 8243
shift register for low-cost
longer necessary. However, the
8243
longer needed are the
tions. The

or

in rare cases, a short sequence

An

example of the latter

use the

the stack pointer has been changed from a 3-bit

increment to address

and

operations no longer necessary (and invalid) for the

are MOVD, ANLD and ORLD. These instructions

using standard instructions on its ports. Also no

8051

makes of PC- and DPTR-relative

by

the 8051. For this purpose Intel provides

(CONV-51) which translates

8051

PSW to

8051

8049

8051

an

8-bit register. Therefore, the stack

"roll-over" from address

's stack

programs using only the low-order six or

be

uses ALE (along with RD and

size

RO

in Indirect Addressing must now

zero.

I/O

expander chip. Since the

ENTO

is

a corresponding

of

instruc-

is

the adjustment required

8051

has new bit patterns

of

the

8048

assembly source code. In

23

to address

24.

In general,

8048

code, upon an interrupt,

be

used for storing the

equivalent to that of the

I/O

expansion, these are no

8051

can interface to an

CLK and SEL MBi instruc-

8048

be

translated

8051

WR

8048.

uses a

when

8051

may

8048

code

8048

necessary) as the
memory preempts the need for the

SEL RBi instructions are preempted by instructions

The
that manipulate the

s.ystem

PSW.

clock. The 64K contiguous

2.16 DEVELOPMENT SYSTEM AND
SOFTWARE SUPPORT

The

8051

is

supported by a total range
ment tools. This broad range
product development cycle and thus brings the product
to market sooner.

• ASM51 Absolute macro assembler for the

O.

• CONV51

• EM-51 8051/8751

•

ICE-5J™

• UPP-851

•

8048

assembly language source code to

assembly source code conversion program.

emulator

8051

modified
Real-time in-circuit emulator.
PROM
8051

Workshop.

and an EPROM.

programmer personality card.

8051 Software Development Package
(ASM51 and CONV51)

The

8051

software development package provides de-

. velopment system support for the powerful

of

single chip microcomputers. The package contains

a symbolic macro assembler and

code converter. This diskette-based software package

under

runs

Development

ISIS-II

System with 64K bytes

on any Intellec® Microcomputer

8051 Macro Assembler (ASM51)

The

8051

macro assembler translates symbolic

sembly language instructions into machine exectuable

object code. These assembly language mnemonics are

easier to program and are more readable than binary

8,

hexidecimal machine instructions. Also,
programmer to give symbolic names to memory loca­tions rather than absolute addresses, software design
and debug are performed more quickly and reliably.

ASM51 provides symbolic access for the many useful
addressing

features include referencing bit and byte locations, and

provide 4-bit operations for BCD arithmetic. The as­sembler also provides symbolic access to the bits and
bytes in the RAM and
spaces.

The assembler supports macro definitions and calls. This
provides a convenient means
ly

used code sequence only once. The assembler also
provides conditional assembly capabilities. Cross refer­encing
shows the user the lines in which each symbol was de­fined and referenced.

If

an

vides a comprehensive set

34

methods

is

provided in the symbol table listing, which

8051

program contains errors, the assembler pro-

in the 8051

Special Function Register address

of

of

error diagnostics, which are

SEL MBi instructions.

of

Intel develop-

of

support shortens the

8051.
8051

board

8.048

architecture.

programming a frequent-

to

of

memory.

by

that

uses a

8051

family

8051

source

8051

as-

or

allowing the

These

AFN-Ol488A-38

8051

Architectural Specification and Functional OescripUon

included in the assembly listing,
The object code generated may

8751

EPROM

fabricating the

can also

be

version

8051

debugged using the

of

RO M version. The assembler output

8048 to 8051 Assembly
Utility Program

The

8048

to

8051
to help users of the
upgrade
architecture.

source code, the investment

the

8048

their

By

is

maintained when the system

8051 Emulation

The EM-51

5.25;
computer using standard PROMs
of

the 8051's on-chip program memory. The board in­cludes a modified
circuits, and two sockets for program memory. The user
may select two

J:>ipolar

3636
and power requirements.

8051

board which emulates an 8031/8051/8751 micro-

PROMs depending on crystal frequency

(CONV51)

assembly language converter

MCS-48 family of microcomputers

designs

to

converting 8048 source code to

BO.ard

emulation board

8051

microcomputer,

2716

EPROMs, a 2732 EPROM,

or

on

another

be

used

t.o

the chip or sent

ICE-51

Langu~ge

the

in

in-circuit emulator.

Converter

high

performance

software developed for

is

upgraded.

(EM-51)

is

a small (2.85" x

or

EPROMs in place

file.

program the

to

Intel for

is

a utility

8051

8051

supporting

or

two

8051 In-Circuit Emulator (ICE-51™)

The

8051

In-Circuit
development system. The development system interfaces
with the user's
with the cable terminating in an
plug. Together these replace. the
tem. With the emulator plug in place, the designer can

the.

exercise
instruction cycles of real-time data. In addition,

single step the system program.

available in the ICE-51 module to emulate the 8051's
internal and external program memories and external
data memory. The designer can display and alter the
contents
Special Function Registers, and replacement external
memory. Symbolic reference capability allows the

signer to use meaningful symbols provided

rather than absolute values when examing and modifying
the memory, registers, flags, and

system

of

intermil

Emulator

8051

system through an in-cable module

in

real-time while collecting up to

8051

registers, internal data RAM,

resides in

8051

pin-compatible

8051

device

Static RAM memory

I/O

ports

in

the

Intellec

in

the sys-

he

by

ASM51

his system.

255
can

de-

Universal PROM Programmer Personality
Card (UPP-851)

The UPP-851

Universal PROM Programmer. The Universal PROM

Programmer
programming and verifying the
verification

. development system console and are controlled

Universal

is

a personality card for the UPP-\03

is

an Intellec system peripheral capable

8751.

Programming and

operations

PROM Mapper (UPM) program.

are

initiated from the Intellec

by

is

of

the

8051 Workshop

The workshop provides the design engineer
designer hands-on experience with the

puters. The course includes explanation

architecture, system timing and input / output design. Lab

will

sessions
ity with the

allow the attendee to gain detailed familiar-

8051

family and support tools.

8051

of

the Intel

or

microcom-

INSITE™ Library

The

INSITE

applications programs.

2.17

8051

VSS

Circuit ground potential.

Library

contains

8051

utilities

FAMILY PIN DESCRIPTION

Vee

+SV

power supply during operation, programming

verification.

Port 0

Port

0 is

an

8-bit open drain bidirectional 110 port.

also the multiplexed low-order address

when using

output during programming and verification. Port 0 can

sinkl source two

~xternal

memory. It

TTL

loads.

is

used for

Port 1

Port 1
for the low-order address byte during programming
verification.

Port 2

Port 2 is
emits the high-order 8 bits
external memory.
the control signals during programming and verification.

Port

Port 3

Port 3

contains the interrupt, timer, serial

pins that are used by various options. The output latch

corresponding to a special function must be programmed
to
sink/ source one

assigned to the pins

-

is

an

8-bit quasi-bidirectional

Port

I can sinkl source one

an

8-bit quasi-bidirectional 110 port.

of

address when aa:essing

It

is

used for the high-order address and

2 can sink/ source one

is

an

8-bit quasi-bidirectional 110 port.

a one

RXD
(asynchronous)

(I)

for that function

TTL

of

/ data (P3.0). Serial port's receiver data input

or

TTL

load.

port

to

load. The special functions are

Port 3, as follows:

data input I output (synchronous).

- TXD/clock (P3.I). Serial port's transmitter data

or

output (asynchronous)

-

INTO

(P3.2). Interrupt 0 input

counter

- INTI (P3.3). Interrupt 1 input
counter

-

TO
TI

-

O.

1.
(P3.4). Input to counter O .
(P3.5). Input to counter

clock output (synchronous).

or

or

1.

35

and

data

input

I/O

port.

TTL

load.

and

RD

operate. Port 3 can

gate control input for

gate control input for

AFN-Ol488A-39

system

data

It

is used

It

It

and

8051

and

and

It

is

bus

and

and

also

also
WR

8051 Architectural Specification and Functional Description

- WR (P3.6). The write control signal latches the data
byte from Port

-RD

RSTNpD

(P3.7). The read control signal enables External

Data Memory to

0 into the External Data Memory.

Port

O.

.

A

low

to high transition on this pin (at approximately
resets the
proximately
will provide standby power to the RAM. When VPD
low, the RAM's current
internal resistor permits power-on reset using only a
capacitator connected to VCC.

ALE/PROG .

Provides Address Latch Enable output used for latching
the address into external memory during normal opera­tion. Receives the program pulse input during
programming.

80S

+SV),

1.

If

VPD

is

held within its spec (ap-

while VCC drops below spec, VPD

is

drawn from VCC. A small

3V)

is

EPROM

PSEN

The Program Store Enable output
enables the external Program Memory to the bus during

normal fetch operations.

EAlVDD

When held
instructions from the internal
PC

is

80S

I fetches all instructions from external Program

M~mory.

programming supply voltage.

XTAL 1

Input to the oscillator's high gain amplifier. A crystal or
external source can

XTAL 2

Output from the oscillator's amplifier. Required when a
crystal

at

a TTL high level, the

less

than 4096. When held

The pin also receives the

be

used.

is

used.

is

a control signal that

80S

ROM/EPROM

at

a TTL low level, the

21

V EPROM

I executes

when the

36

AFN·01488A·40

8051

Architectural Specification and Functional Description

TABLE 2-1

Notes

on

instruction set

·~Register

Rn

data

-S-bit
nal

@Ri

IIdata
IIdata

addrl6

addrll

rei

bit

*

Data

MOV

"MOV

MOV A.@Ri
MOV A.lldata Move immediate
MOV Rn.A

"MOV

MOV Rn.lldata Move immediate

"MOV
"MOV
"MOV

"MOV

"MOV

MOV@Ri.A

"MOV

MOV @Ri,lIdata Move immediate

"MOV

"MOV
"MOV
"MOVC

"MOVC

MOVX A.@Ri Move External Data

"MOVX

MOVX @Ri.A Move A

·MOVX

·PUSH

'POP

XCH

"XCH

XCH A.@Ri Exchange indirect

XCHD

tTOI

-g-bit

ectly

-8-bit

16

-16-bit

-16-bit
branch can

ory address space.

-II-bit
branch
memory as the first byte

·--Signed (two's complement) 8-bit offset byte. Used by

and all
to first byte

-Direct

tion Register.

- New operation

Tra

nafer

Mnemonic

A.Rn
A.data

Rn.data

data.A
dala.Rn
data.data

data.@Ri

data.lldata

@Ri.data

DPTR.

IIdata

16
C,bit Move direct bit
bit.C

A.@A+ Move

DPTR

A.@A+PC

A.@DPTR

@DPTR.A

data

data

A.Rn
A.data

A.@Ri Exchange indirect RA

and

addressing modes:

R7-RO

of

internal

Data

RAM

register. status register. etc. (128-255)].

Internal
through
constant included in instruction.

constant

destination address. Used by

destination address. Used by

will be within the same 2K-byte page

conditionaljumps.

Addressed bit in Internal

the currently selected Register

data

location's address. This could be an Inter-

location (0-127)

Data

RAM

register R I

included in instruction.

be anywhere within the 64K-byte Program Mem-

of

the

not

Move· register
Move direct byte
Move indirect

Move A
Move direct byte

register
Move A
Move register
Move direct byte

byte

Move indirect

direct byte

Move

direct byte

Move A
Move direct byte

indirect RAM

indirect

Move l6-bit
Data

Move carry

byte addressed
A+DPTR

Move

byte

addre"ed

A+PC

(8-bit address)

Move External

(l6-bit

(8-bit address)
Move A
(l6-bit

Move direct byte

and,inc.

Move direct byte from

staci<

Exchange register with A
Exchange direct byte

with A

with A

least sig nibble with A's LSN

location (0-255) addressed indir-

or

of

Range is-128 to +

following instruction.

pTOvided

Description

to

RAM

to

register

to

direct byte

10

RAM

immediate

to

indirect

RAM

constant

Pointer

to

direct bit

Program

by

to

A

Program

by

to

A

to

address) to A

to

External Data

to

External

address)

SP

and

dec. S P

8051

or a SFR

RD.

the following instruction.

Data

by

A

to

data

to

data

direct byte

to

data

to

data

to

carry

Memory

Memory

A

Data

to

RAM

[i.e.

LCALL & LJMP.

ACALL & AJMP.

127

RAM

or

8048 i 8049.

Bytes

io

to

I

2

A

I

A

2

I
2
2

2

A

to

register

2

direct

RAM

Data

staci<

to

to

to

to

M',

3

2

3

I
2

2

2
2

2

2

(:0

port. con-.

of

bytes relative

Special Func-

Oscillator

Periods

INSTRUCTION

Bani<.

A

The

program

SJMP

12
12
12
12
12

24

12

12
24
24

24

24

12
24

12

24

12
24

24

24

24

24

24

24

24

24

12
12

12

12

·SETB

"CPL

All

mnemonics

37

SET

SUMMARY

Interrupt Response Time: To finish execution
respond to the
instruction
periods

INSTRUCTIONS

INSTRUCTION

ADD
ADDC
SUBB

'MUL

DIV 0 X
DA X
RRC
RLC
SETB

'Note
(i.e.

the

Logic

ANL

"ANL

ANL

ANL
"ANL
"ANL

"ANL
'ANL

ORL
"ORL

ORL

ORL
"ORL
'ORL

"ORL
"ORL

XRL
"XRL

XRL

XRL

'XRL

"XRL

"SETB

CLR
CLR

·CLR

CPL
CPL

RL A

RLC

RR A

RRC

SWAP

interrupt

of

the

(3

to

71's @ 12

C

that operations

PSW

or

Mnemonic

A.Rn
A.data
A.@Ri
A.lldata
data.A
data.lldata

C,bit
C,bit

A.Rn
A.data
A.@Ri

A.lldata
data.A
data.lldata

C,bit
C, bit

A.Rn

A.data

A.@Ri Exclusive-OR indirect

A.lldata

data.A

data.lldata Exclusive-OR immediate

C Set carry 1
bit Set direct bit 2

A Clear A

c.:

bit Clear direct bit

A
C
bit Complement direct bit

A Rotate A Left through

A Rotate A Right

A Rotate A left four

request. push the PC and

interrupt service progr.am requires

MHz).

THAT

AFFECT

FLAG

OV AC

C

X X X

X X

X
X X X

0 X

X

X

on

SFR

bits in the PSW) will also affect nag settings.

AND
AND
AND
AND

AND
AND
direct byte
AND

...

ND
direct bit
OR
OR
OR
OR
OR
OR
direct byte
OR
OR
bit to carry

Exclusive-OR register to A
Exclusive-OR direct byte

to A

RAM
Exclusive-OR
data
Exclusive-OR A
byte

data

Clear carry

Complement A
Complement carry

Rotate A Left

carry

Rotate A Right

carry

(exchange nibbles within

A)

copyrighted©

FLAG

SETTINGS'

INSTRVCTION

CLR

C 0

CPL

C X

ANL

C,bit X

ANL

C:

ORL

C, bit X

ORL

C, bit

MOV C, 'bit

CJNE

byte address

Description

register
direct byte
indirect
immediate

A to direct byte 2
immediate

direct bit
complement

to
register
direct byte to A
indirect RAM
immediate
A to direct byte
immediate

direct bit
complement

to

A

to A

to direct byte

20X

to

A I

to

A 2

RAM

data

data

to

carry

of
carry
to

A I

to

data

to

data

to

to

carry

of

direct

immediate

to

direct

through

Intel

of

current instruction.

to

vector

38

to

C

bit X

X
X
X

or

bit addresses 209-215

Bytes

to A I

to

A 2

to

3

2
2

2

A

I

A

2
2

3

2

2

Corporation

to

the first

81

oscillator

FLAG

OV AC

Oscillator

Periods

12
12
12

12
12
24

24
24

12
12
12
12
12

24

24
24

12
12

12

12

12

24

12
12
12
12
12
12

12
12
12
12

12
12

12

1980.

AFN-01488A-41

8051 Architectural Specification and Functional Description

Arithmetic

Mnemonic

ADD A.Rn

"ADD

A.data

ADDA.@Ri

ADDA./Idata

ADDC A.Rn

*ADDC A.data

Description Bytes Periods

Add register to A
Add direct byte to A
Add indirect RAM to A I
Add immediate data to A
Add register and carry
Add direct byte

flag to A I

aild carry flag

toA

ADDC A.@Ri Add indirect RAM and carry

flag to A

ADDC A./Idata Add immediate data and carry 2

flag to A

"SUBD A.Rn

Subtract register and carry

flag

from A

"SUBD A.data

Subtract direct byte and carry
flag from A

"SUBD A.@Ri

Subtract indirect

RA

M and

carry flag from A

"SUBD A./Idata

INCA

Subtract immediate data aild

flag from A

carry

Increment A

INC Rn Increment register

"INC data Increment direct byte 2

INC@Ri
DECA

Rn

DEC

"DEC

data Decrement direct byte
"DEC@Ri
"INC

DPTR

'MUL

AB

'DIV

AD

DAA

Increment indirect RAM
Decrement A I
Decrement register

Decrement indirect RAM
Increment Data Pointer
Multiply A times D
Divide A

by

D

Decimal add Adjust of A

I

2

2

2

2

2

I
2

Oscillator

12
12
12
12
12
12

12

12

12

12

12

12

12

12
12
12
12
12
12
12
24

48
48

12

Trans'er (Branch)

ContrOl

Mnemonic

AJMP

addrll

"LJMP

addrl6

"SJMP

rei

"JMP

@A+DPTR Jump indirect relative to

Description Byt

Absolute

Jump

Long Jump 3

Short

Jump

the DPTR
Jump

JZ

rei

JNZ

rei

JC

rei

JNC

rei

"JD bit.

rei

"JNB bit. rei

" J

DC

bit.rel

"CJNE

A.data.rel

if A

Jump

if A

Jump

if carry
Jump if carry
Jump relative if direct bit

is

set

Jump relative if direct bit

is

not set

Jump relative if direct bit

is

ser. then clear bit

Compare direct byte to A

& Jump if not Eq.

See Note a.

'CJNE

A.lldata.rel Compare immed. to A &

if not Eq. See Note a.

'CJNE

rei

'CNJE

IIdata.rel

Rn.lldata.

@Ri.

Compare immed. to reg & 3
Jump if not Eq. See Note a.
Compare immed. to indirect
RAM &

Jump

See Note a.

DJNZ

Rn.rel

Decrement register

if not zero

'DJNZ

data. rei

Decrement direct byte & 3

Jump if not zero

Note a) Set C if the first operand

else clear

is

zero

is

not zero 2

is

set

is

not set

Jump

if not Eq.

& Jump 3

is

less

than the second operand;

..

2

2

2

2
2

3

3

3

3

3

3

Oscillator

Periods

24
24
24
24

24
24
24
24
24

24

24

24

24

24

24

24

24

Other

D

..

Mnemonic

crlptlon

NOP No Operation I

Byt

Oscillator

..

Periods

12

Control Trans'er (Subroutine)

Mnemonic

ACALL

LCALL
RET
RETI

addrll

addrl6

Description

Absolute Subroutine Call
Long Subroutine Call
Return from Subroutine Call
Return from Interrupt Call

Oscillator

Bytes Periods

2 24

3

24
24
24

All mnemonics copyrighted@ Intel Corporation 1980.

AFN-01488A-42

38

INTEL CORPORATION, 3065 Bowers Avenue, Santa Clara,

CA

95057 [phone]

Printed in U.S.A./TP-46/0580/2K SC WL