Intel 8051 User Manual

Architectural Specification

May 1980

©

INTEL

CORPORATION, 1980.

AFN-01488A-01

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may appear in

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and shall remain the property
disclosure is subject to restrictions stated in Intel's software license,
Corporation assumes no responsibility for the use

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any circuitry other than circuitry embodied in

product. No other circuit patent licenses are implied.
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part

of

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consent

of

Intel Corporation.

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i

Intel Corporation and may only be used to identify Intel products:

or

reproduced in any form

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Intelevision
and the combinations
Additional copies of this

of

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or

other Intel literature may be obtained from:

or

RMX and a numerical suffix.

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Intel Corporation

3065 Bowers Avenue

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no

responsibility for any enors which

of

Intel Corporation. Use, duplication

or

as

defined in ASPR 7-104.9

or

by any means without the prior wr:itten

J,lScope

.

(a)

(9).

an

or
Intel
Intel

f·INTEL CORPORATION.

1980

8051

Architectural Specification and Functional Description

8031/8051/8751

SINGLE-COMPONENT 8-BIT MICROCOMPUTER

•

803t

- Control Oriented CPU With RAM and

•

8051

- An

8031

With Factory Mask- Programmable ROM

•

8751 -An

8031

With User Programmable/Erasable EPROM

I/O

• 4K x 8 ROM/EPROM

• 128 x 8 RAM

• Four 8-Bit Ports, 32 I/O Lines

• Two 16-Bit Timer/Event Counters

• High-Performance Full-Duplex Serial
Channel

• Boolean Processor

•

Compatible

with

MCS-80™/MCS-85TM

Peripherals

The Intel® 8031/8051/8751
+5

Volt, depletion-load, N-Channel, silicon-gate HMOS technology and packaged in a 40-pin DIP. It provides the

is

a stand-alone, high-performance single-chip computer fabricated with Intel's highly-reliable

• External

• MCS-48™ Architecture Enhanced with:

• Non-Paged Jumps

• Direct Addressing

• Four 8-Register Banks

• Stack Depth

• Multiply, Divide, Subtract, Compare

• Most Instructions Execute

•

411s

Memory

Multiply

hardware features, architectural enhancements and new instructions that are necessary to make

of

effective controller for applications requiring up to 64K bytes
The

8051/8751 contains a non-volatile 4K x 8 read only program memory; a volatile

32

I/O

lines; two 16-bit timer/counters; a five-source, two-priority-Ievel, nested interrupt structure; a serial

I/O

either multi-processor communications,
The

8031

is

identical, except that

be

expanded using standard TTL compatible memories and the byte oriented MCS-80 and MCS-85 peripherals.

The

8051

microcomputer, like its 8048 predecessor,

8051

has extensive facilities for binary and BCD arithmetic and excels in bit-handling capabilities. Efficient

memory results from

12

MHz crystal, 58%

a

an

instruction set consisting

of

the instructions execute in Ills, 40% in

it

lacks the program memory.

the many instructions added to the standard

expansion,

is

efficient both as a controller and as an arithmetic processor. The

of

44% one-byte,

8048 instruction set are multiply, divide, subtract and compare.

program memory and /

or

full duplex UART; and on-chip oscillator and clock circuits.

For

systems that require extra capability, the

41%

two-byte, and

2f1s

and mUltiply and divide require only

Expandable

Up

to 128-Bytes

and Divide

or

up to 64K bytes

128

x 8 read/write data memory;

15%

three-byte instructions. With

to

128K

in

111S

it

a powerful and cost

of

data

I/O

use

of

411S.

storage.

port for

8051

can

program

Among

P1.0

P1,1

P1.2
P1.3

P1.4

P1.5
P1.6
P1.7

RST/VPO
RXD P3.0

TXO P3.1

INTO P3.2

uin

P3.3

TO

P3.4

T1

P3.5 P2.5

\VA

P3.6

RD

P3.7

XTAL2

XTAL1

VSS

Figure

1.

Pin

Configuration

Intel

Corporation

© INTEL CORPORATION.

Assumes

vee

PO.o
PO.1
PO.2
PO.3
PO.4
PO.S
PO.S

PO.7

EAtVDO

ALEIPROG

PSEN

P2.7

P2.S

P2."

P2.3

P2.2

P2.1

P2.D

No

Responsibility

1980.

PSEN

ALE/PROG

TXO

.....

.m_

{{

INTO

......

INT'......

TO-'

n........

WA~

AD"-

:

g

Q.

Figure 2.

for

the

Use

Logic

of

Any

AST/VPD

Circuitry

FREQUENCY
REFERENCE

r

Than

BUS

Circuitry

I

I

I

I

I

I
I
I

I

L-

INTERRUPTS

Embodied

INTERRUPTS

in

•

an Intel

64K-SYTE

EXPANSION

CONTROL

CONTROL

Figure

Product.

8US

PARALLEL
ADDRESS/DATA
AND

3.

Block Diagram

No

Other

Circuit

DATA

110

ADDRESS

AND

}-.

OATA

}-,

ADDRESS

BUS

}~"'.

Symbol

Other

128

BYTES
MEMORY

PORTS.

PINS

Patent

BUS,

licenses

COUNTERS

,...----'---'---,

TWO

16-BIT

TIMER/EVENT

COUNTERS

PROGRAMMABLE

SERIAL

PORT

•

FULL

DUPLEX

UART

•

SYNCHRONOUS

SHIFTER

SERIAL SERIAL

IN

OUT

Are

Implied.

AFN-01488A-02

-1

I
I

I

I
I
I
I

I

I

8051 Single-Chip

Contents

Microcomputer

Architectural Specification

and

Functional Description

©Intel Corporation 1980. All rights reserved.

CHAPTER 1 INTRODUCTION

1.0

1.1

1.2

CHAPTER 2 ARCHITECTURAL OVERVIEW AND

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Abstract. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Intel's Complete Line
Microcomputers
Enhancing the 8048 Architecture for
the

80's

................................

FUNCTIONAL DESCRIPTION
The

8051

Family

Macro-view

2.1: 1 8051

2.1.2

On-Chip Peripheral Functions. . . . .

2.1.2.1

2.1.2.2

2.1.2.3 Timer/Event Counters

2.1.2.4 Serial Communications. . . .

CPU Hardware.

2.2.1

Instruction

2.2.2' Program

2.2.3 Internal Data Memory

2.2.3.1

2.2.3.2 Register Banks

2.2.3.3 Special Function Registers

2.2.3.4 A Register. . . . . . . . . . . . . . . .

2.2.3.5 B Register. . . . . . . . . . . . . . . .

2.2.3.6

2.2.3.7 Stack Pointer . . . . . . . . . . . . .

2.2.3.8 Data Pointer

2.2.4 Arithmetic Section

2.2.5

Program Control Section

2.2.6

Oscillator and Timing Circuitry

2.2.7 Boolean Processor
Memory Organization
Operand Addressing
Data Manipulation

2.5.1

Data Transfer Operations

2.5.2

logic

2.5.3

Arithmetic Operations
Control Transfer
I nstruction Set

2.7.1

What the Instruction Set Is

2.7.2 Organization

2.7.3 Operand Addressing Modes and

Associated Operations
Interrupt System

2.8.1

External Interrupts

2.8.1.1

2.8.1.2 level-Activated Interrupts

Ports and I/O Pins

of

CPU Architecture . . . . . . . . . . .

2.1.2.2.1

2.1.2.2.2 Quasi-Bidirectional

2.1.2.2.3 Microprocessor Bus

Operations

..... .-..

........................

........................

the

8051

Interrupt System

I/O Facilities. . . . . . . . . . . . . .

Open Drain I/O
I/O Pins

.. . .. . ..

Decoder.

Counter

Internal Data RAM

PSW

Register.

...............

........................

...........................

of

........................

Transition-Activated
Interrupts

.......................

.. .. .. .. .. ..

of

Single-Chip

...........

Architecture

..

. . . . . . . .

Pins. . ..

...............

..

.. . ..

.. .. . ..

. . . . . . . . . . . . .

.........

................

.................

.................

...................

....................

..................

the Instruction Set

..................

..................

. . . . . . . .

..............

...........

.•...........

.. ..

.. .. ..

...........

"

...........

..............

...........

.............

......

..

.......

....

......

......

....

.... 1

..

..

..
..
..
..

..
..

...

..
..

...

..
..

..

11
11
11
11
11
11
12
14
14
15
16
17
18
18

".

18

21
22
24

24
24
24

1
1
1

2
2
2
2
3
3
4
4

4
5
6
7
9
9
9
9
9
9
9
9
9
9
9

AFN-Q1488A·03

CHAPTER 2 ARCHITECTURAL OVERVIEW AND

FUNCTIONAL

DESCRIPTION (Continued)

2.10 Accessing External

2.10.1 Operation

2.10.2 Bus Cycle Timing

2.11

TimerlCounter

2.11.1 TIC Mode Selection

2.11.2 Configuring the

2.11.3 TIC Operation

2.11.4 Reading and

2.12

Serial Channel

2.12.1

Serial Port Control Register and
Serial Data Registers

2.12.2 Operating Modes

2.12.2.1 Operating Mode O

2.12.2.2 Operating Modes 1

2.12.3 The

2.12.4 Transmission Rate Generation

2.12.5 UART Message Error Conditions

2.13

External Interface

2.13.1

Processor Reset and

Initialization

2.13.2

Power Down Operation

Internal RAM

Table

2.14

2.15

2.16

2.17

2.1

EPROM Programming
The

8051

Development System and Software
Support
8051

................................

Pin Description

Instruction Set Summary

Memory

of

Ports

..........................

TIC Input

....................

Reloading the TIC

..........................

through 3

Serial Frame

.......................

......................

.....................

....................

as

an

Evolution of the 8048

....................

..............

................

.................

...............

.........

.......... ' ....

.................

•....•••.

................

.................

of

.................

....

.....

......

...

25
26
26
28
28
28
29
29
29

31
31
31

32
32
32
33

33
33
33

34
34

34
35

37

AFN-01488A-04

8051

Architectural Specification and Functional Description

1.0 ABSTRACT

The 8031, 8051,

of

line

single-chip microcomputers. The CPU architec­ture and on-chip peripheral functions
described in this document. A user familiar with the

MCS-48 family should be able to evaluate and design-in

the

8051

A detailed description
expand the
memory,
processor configurations

User's Manual.

1.1

INTEL'S COMPLETE LINE OF

and

8751

are the latest additions to Inters

of

the

using the information included herein.

of

the

hardware required to

8051

with more program memory,

I/O,

specialized peripherals and into multi-

is

described in the

8051

8051

data

Family

are

SINGLE-CHIP MICROCOMPUTERS

In

1976

Intel introduced the 8748 microcomputer. This
marked the first time in history that technology permitted
a complete 8-bit computer
silicon die. This single chip can control a limitless variety
of

products ranging from appliances to automobiles to

computer terminals.

Since

1976

Intel has offered products for the full range
single-chip microcomputer applications by pushing the
8048's architecture in several directions. The 8049 ran
nearly twice as fast
amount

of

on-chip program memory and

as

Applications requiring solely external program memory
were satisfied with the
less

I/O

intensive applications incorporated the
which executed a subset
slower speed. Finally, the
converter onto the

8021

directly to a world in which most signals are analog.

I.

Figure

I positions these products on a performance

versus die-size curve.

10

9

8

7

iu

il 6

c

~

5

o

...

ffi

4

...

3

2

0~------*X----~~1~.5~X------~2~X------.~2.5X

-Based on execution speed, memory size and peripheral functions.

Figure 1.1. Performance Versus Cost

to

be fabricated on a single

of

the 8748/8048 while doubling the

data

memory.

8035 and 8039. Cost sensitive and

8021

of

the 8048's instruction set

8022 integrated an 8-bit

at

A/D

die to allow the chip to interface

•

8051

8022.

8048

8021.

DIE SIZE

•

a

Now, thanks to the density
once again permitted the

to

performance
achieves a
8048

by packing 60,000 transistors onto a die 230 mils

leap into new product areas. The

lOX

function/speed improvement over the

of

HMOS, technology has

birth

of

a microcomputer with

square.

The

8051

family addresses the high-end

computer market.

It

is

the highest performance micfo-

computer family in the world

and

of

the single-chip

out-performs all micro-

processors and microcomputers in control oriented

It

applications.

for

8048 users with ten times the power

shown in Table

offers an upward compatible growth path

of

1.1.

•

4X

Program Memory (4k Bytes)

•

2X

Data Memory (128 Bytes)

•

2X

Register Banks (4

•

2X

Timers (Two 16-bit Timers)

• New Full-Duplex Serial

• More

I/O

Pins (32

vs.

vs.

27)

2)
I/O

Port

the

• Enhanced MCS-48 Architecture

•

Table

21/2 X To

1.4X Die Size

•

1.1:

10X

Execution Speed

8051

Functions/Speed/Cost Relative

to

8048

1.2 ENHANCING THE 8048 ARCHITEC­TURE FOR THE 80's

The goal
industry standard
the
CPU

of

on-chip CPU peripherals.

The
applications demanding a low-cost microcomputer because
of

its hardware simplicity and resulting silicon efficiency.

A

simpleALU
metic, logic,
data
internal data path. The
of

Register-, Register-Indirect- and Immediate-Address-

ing minimize hardware. The conditional branch logic

simply concatenates
bits
results in page boundaries. The simplicity
look-up circuitry also results in page boundaries. The
user flags and test pins provided for monitoring program
and external status in an efficient manner are limited to
two of each. This architecture, and the choice
tion encodings that it permits, results

programs

1

of

the

8051

is

to extend the architecture

8048 single-chip microcomputer into

80's. This meant increasing the power

of

the 8048's

as well as increasing the power, variety and quantity

8048's CPU architecture

is

used in virtually all operations: arith-

data

moves, bit testing and I/O. Since all

is

moved through the ALU this also simplifies the

is

ideal for control-oriented

8048's simple addressing methods

an

immediate value to the upper

of

the program counter to economize on silicon, but

of

the table-

of

In

1,024 byte

of

unsurpassed byte efficiency.

AFN-01488A-05

8051

8048

of

the

instruc-

as

8051

Architectural Specification and Functional Description

The silicon economic architecture of the
some inconvenience to the programmer but the relatively
short programs (one or two kilobytes) keep frustration
levels in check. The
ware and feature compatibility with the
providing a more powerful microcomputer that
to program and
using the
tecting
knowledge he gained by designing with the

Some of the achievements
maximum program memory address space to 64K-bytes,
extending on-chip peripheral functions (counters, serial
ports and parallel ports) to satisfy emerging single-chip
applications, and enhancing a paged architecture to
make
generated
were reassigned to add new high-power operations and to
permit
operations more orthogonal. During this process special
care
maximum execution speed. The
more code efficient than the 8049 for programs longer
than
from an instruction set consisting of 44% one-byte,
two-byte and

M

Hz

in

2;,Is

2.0 THE

The
computer intended for use
applications such as instrumentation, industrial control
and intelligent computer peripherals. It provides the
hardware features, architectural enhancements and new
instructions that make it a powerful and cost effective
controller for applications requiring up to 64K-bytes of
program memory
A Block Diagram

The

program memory.
Program Memory in addition to 64K-bytes

Data Memory.
each member of the
standard memories

MCS-85 peripherals. The
4K-bytes

programmable

light-erasable/ electrically-programmable ROM.

8048

his

investment in algorithm development and the

it

suitable for the relocatable and re-entrant code

by

modern programming techniques. Op codes

new

was

taken to provide optimum byte efficiency and

2048

bytes. Efficient use of program memory results

crystal,

and multiply and divide require 'only 4tis.

8051

8051

is

a stand-alone high-performance single-chip

8031

is

of

Program Memory filled with on-chip mask

8051

challenge

use.

This allows a designer currently

to easily upgrade to the

of

addressing modes which make the old

15%

three-byte instructions. With a

58%

of the instructions execute

the

was

8051

8051

FAMILY

in

sophisticated real-time

and/

or

up to 64K-bytes

is

shown in Figure

a control-oriented

It

can address 64K-bytes

For

systems requiring extra capability,

8051

family can

and

the byte oriented MCS-80 and

8051

ROM while the

CPU

is

an

8031

8751

has 4K-bytes

8048

causes

to maintain soft-

8048

while

is

easier

8051

while pro-

8048.

were to extend the

is

typically 20%

41

%
12

in

ltis, 40%

of

data storage.

3.

without on-chip

of

external

of

External

be

expanded using

with the lower

ofUV-

ment, prototyping, low-volume production
tions requiring field updates; the
high-volume production and the
desiring the flexibility
which can be easily modified

2.1

MACRO-VIEW OF THE

of

external Program Memory

8051

8031

and

updated in the field.

and

applica-

for low-cost,

for applications

8051

ARCHI-

TECTURE

On a single die the
non-volatile 4K x 8 read-only program memory; volatile

128

x 8 read/write data memory;
timer / event counters; a five-source, two-priority-Ievel,
nested interrupt structure; serial
processor communications,
UART; and on-chip oscillator and clock circuits. This
section will provide an overview
a high-level description
architecture and the on-chip functions peripheral to the

CPU. The generic term "8051"
tively to the

2.1.1

The

8051

spaces. These are the 64K-byte Program Memory, 64K-

byte External
Memory and 16-bit Program Counter spaces. The Inter­nal

Data
256-byte Internal
Function Register

2.1. Four Register Banks (each with eight registers),
addressable bits, and the stack reside in the Internal
RAM. The stack depth
Internal Data
8-bit
Counter and the four 8-Register Banks reside in the
Special Function Register address space. These memory
mapped registers include arithmetic registers, pointers,
I/O

ports, and registers for the interrupt system, timers
and serial channel.
space are addressable as bits. The

of Internal Data RAM and

The
address space to accommodate relocatable code.
ditional branches are performed relative to the Program
Counter. The register-indirect
relative to a 16-bit base register with
an 8-bit index register. Sixteen-bit jumps and calls permit
branching to any location in the contiguous 64K

Memory address space.

8031,

8051

CPU

Memory address space

Stack Pointer.

8051

provides a non-paged Program Memory

8051

microcomputer combines CPU;

32

I/O

lines; two 16-bit

I/O

port for either multi-

I/O

8051,

expansion,

of

the

of

its major elements: the

is

also used to refer collec-

and

8751.

or

8051

by providing

full duplex

CPU Architecture

manipulates

Data

Memory, 384-byte Internal

Data

(SFR) address spaces shown in Figure

RAM

and its location

All

128

operands

is

RAM

is

limited only by the available

registers except the Program

bit locations in the

20

SFRs.

jump

in

four

further divided into the
and 128-byte Special

is

determined by the

SFR

8051

contains

permits branching

an

offset provided by

CPU

memory

Data

128

Data

address

128

bytes

Con-

Program

The three pin-compatible versions
reduce development problems to a minimum and provide
maximum flexibility. The

8751

of

this component

is

well

suited for develop-

The

8051

has

five

methods for addressing source oper-

ands: Register, Direct, Register-Indirect, Immediate, and

Base-Register- plus Index-Register- Indirect Addressing.

AFN-01488A-06

2

8051

Architectural Speciffcation ancrFunctionaJ Descrlpfion

64K

t

EXTERNAl-

------

4095

I

INTERNAl-

,

I I

,

-

PROGRAM
COUNTER

The first three methods can
destination operands. Most instructions have a
nation,source" field that specifies the data type, address­ing methods
other than moves, the destination operand
operand.

Registers

through Register, Direct,
dressing; the
Direct or Register-Indirect Addressing; and the

Function Registers through Direct Addressing. External

Data Memory

Addressing. Look-Up-Tables resident in Program

Memory can

Index-Register- Indirect Addressing.

The

80S

internal

Arithmeticl

bits wide. The

byte and double-byte data types.

and

operands

in the four 8-Register Banks can

128

bytes of Internal Data RAM through

is

accessed through Register-Indirect

be

accessed through Base-Register- plus

1

is

classified as an 8-bit machine since the

ROM, RAM, Special Function Registers,

Logic Unit and external data bus are each

80S

1 performs operations on bit, nibble,

be

involved.

or

0

,

,

PROGRAM
MEMORY

Figure 2.1.

used for addressing

For

is

also a source

Register-Indirect Ad-

-"Lr-----A

J

8051

Family Memory Organization

"desti-

operations

be

accessed

Special

8-

64K

OYERl-APPED SPACE

255 I I

1~1..

,

INTERNAl­DATA RAM

INTERNAL

single-byte,
When using a
in

IlJs
instructions (multiply and divide) require only
number of bytes
oscillator periods required for execution are listed in the
appended

I

,

-

DATA MEMORY

and

4S

80S

25S

128

,

SPECIAL
FUNCTION
REGISTERS

4S

two-byte and

12

MHz oscillator, 64 instructions execute

instructions execute in

in

I Instruction Set Summary.

'l

,

each instruction and the number

,

EXTERNAL
DATA
MEMORY

17

three-byte instructions.

4ls.

The remaining

2.1.2 On-Chip Peripheral Functions

Thus

far

only

the

CPU

and

memory

have been described. In addition to the CPU and
memories, an interrupt system, extensive
and several peripheral functions are integrated on-chipto
relieve the CPU
critical tasks and to permit stringent real-time control
external system interfaces. The extensive 110 facilities
include the
address/data bus and the serial port for
The CPU peripheral functions integrated on-chip are the
two 16-bit counters and the serial port. All

together to greatly boost system performance.

of

repetitious, complicated

110 pins, parallel 110 ports, bidirectional

spaces

I/O

I/O

of

,

~s.

The

of

the

80S 1

facilities,

or

time-

expansion.

these work

of

of

The

80S1

has extensive facilities for byte transfer, logic,

at

and integer arithmetic operations. It excels
since data transfer, logic and conditional branch
operations· can be performed directly on Boolean
variables.

The

80S

I's instruction set
instruction set familiar to
allow expansion of
optimize byte efficiency and execution speed.
were reassigned to add new high-power operations and to
permit
operations more orthogonal. Efficient use
memory results from an instruction set consisting of

new

addressing modes which make the old

on-chip· CPU peripherals and to

is

an

enhancement

MCS-48 users.

bit handling

It

is

enhanced to

Op codes

of

of

the

program

49

2.1.2.1

External events and the
peripherals require service by the CPU asynchronous to
the execution
asynchronous activities of these functions to normal
program execution, a sophisticated multiple-source,
priority-level, nested interrupt system
terrupt response latency ranges from
using a

The

sources:
INTI pins, one from each

3

INTERRUPT SYSTEM

real~time-driven

of

any particular section

12

MHz crystal.

80S

I acknowledges interrupt requests from
Two

from external sour.res

of

the two internal counters and

of

3IJs

via

code.

is

the

To

provided. In-

to

7IJs

INTO

AFN-Ol488A-D7

on-chip

tie the

two~

when

five
and

8051

Architectural Specification and Functional Description

one from the serial
separate location
program. Each
of two priority levels and can
and disabled. Additionally all enabled sources can
globally disabled
programmable as either level-

is

active-low to allow the "wire or-ing" of several interrupt

sources

.to

the input pin. The interrupt system

I/O

port. Each interrupt vectors to a

in

Program Memory for its service

of

the

five

sources can

or

enabled. Each external interrupt

be

assigned to either

be

independently enabled

or

transition-activated and

is

shown

be

is

diagrammatically in Figure 2.2.

2.1.2.2 1/0 FACILITIES

The

8051

has instructions that treat its

32

I/O

lines as

32
individually addressable bits and as four parallel 8-bit
ports addressable as

can also assume other functions.

multiplexed low-order address and data bus

expanding the

peripherals.

Port 2 provides the high-order address bus

when expanding the

or

more than

pins of

Port 3 can

256

Ports 0,

1,2

and

3.

Ports

Port 0 provides the

8051

with standard memories and

8051

with external Program Memory

bytes

of

External Data Memory. The

be

configured individually to provide

0,2

used,

and 3

for

external interrupt request inputs, counter inputs, the
serial port's receiver input and transmitter output, and to

generate the control signals used for reading and writing

External Data Memory. The generation
alternate function

on

a Port 3 pin

is

done automatically by

or

use

of

an

the

8051

as

long as the pin is configured as an input. The

configuration

Logic

Symbol

2.1.2.2.1 Open Drain 1/0 Pins

Each pin
output
microcomputer programs each pin as
a one (I) to the pin.
becomes configured as

of

the ports is shown

of

Figure

of

Port 0 can be configured as

or

as a high impedance input. Resetting the

Ifa

2.

zero

(0)

an

output and will continuously

on

the

8051

an

open drain

an

input

by

is later written to the pin it

Family

writing

sink current. Re-writing the pin to a one (I) will place its
output driver in a high-impedance state and configure the
pin

as

an

input. Each

I/O

pin

of

Port 0 can sink two TTL

loads.

2.1.2.2.2 Quasi-Bidirectional

Ports

1,2

and 3 are quasi-bidirectional buffers. Resetting

the microcomputer programs each pin as

(l)

writing a one

to the pin. If a zero (0)

the pin it becomes configured as an output and

1/0

Pins

an

is

later written to

input by

will
continuously sink current. Any pin that is configured as
an

output will

is

written to the pin. Simultaneous to this reconfiguration
the output driver
source current for two oscillator periods. Since current
sourced only when a bit previously written to a zero

be

reconfigured as

of

the quasi-bidirectional port

an

input when a one (I)

will

(0)

is
is

INPUT LEVEL AND
INTERRUPT

FLAG

INTO

......

tNT1

......

REQUEST INTERRUPT ENABLE

REGISTERS:

eXTERNAL

INTRQST0

INTERNAL

TIMER 0

EXTERNAL

INT

RQST 1

INTERNAL

TIMER 1

INTERNAL~

SERIAL

PORT R

• FIVE INTERRUPT SOURCES

•

EACH INTERRUPT CAN BE INDIVIDUALLY ENABLED/DISABLED
ENABLED INTERRUPTS CAN BE GLOBALLY ENABLED/DISABLED

•

•

EACH INTERRUPT CAN BE ASSIGNED TO EITHER OF TWO PRIORITY LEVELS

• EACH INTERRUPT VECTORS TO A SEPARATE LOCATION IN PROGRAM MEMORY
INTERRUPT NESTING TO TWO LEVELS

•
EXTERNAL INTERRUPT REQUESTS CAN BE PROGRAMMED

•
TRANSITION-ACTIVATED

REGISTER:

SOURCE
ENABLE

.....

-

,..

GLOBAL
ENABLE

..AI'"

...AI"'"

I"'"

I'"

r:.

TO

INTERRUPT
PRIORITY
REGISTER:

BE LEVEL-

-

OR

POLLING
HARDWARE

V

1-----

SOURCE

I.D.

V

-----

SOURCE

I.D.

HIGH PRIORITY
INTERRUPT
REQUEST

------

VECTOR

=>

LOW PRIORITY
INTERRUPT

r--

REQUEST

VECTOR

~

Figure 2.2. 8051

Interrupt

4

System

AFN-01488A-08

8051

Architectural Specification and Functional Description

updated to a one (1), a pin programmed as
not

source current into the

pin is

later written with

bidirectional

output
oscillator periods,
proximately 20K- to 4OK-ohms

external

and

2.1.2.2.3

driver's loading

3 can sink/ source one TTL load.

Microprocessor

TTL

gate

that

another

one (1). Since

driver sources current for only two

an

internal pullup resistor

is

provided to hold the

at a TTL

high level. Ports

Bus

A microprocessor bus is provided to permit the
solve a wide range
growth
data

of

user products. This multiplexed address

bus provides
memories,
memories
and

that

timing functions. These are summarized in the

of

problems

an

interface compatible with standard

MCS-80 peripherals

and

to allow the upward

and

include on-chip programmable

Microcomputer Expansion Components

an

input will

is driving

the

it

quasi-

of

80S

the MCS-8S

I/O

chart

of

Figure

if

the

ap-

1,

1

to

and

ports

80S

2.3.
When accessing external memory the high-order address

is

emitted

on

I/O

Expander

Port 2 and

Category

the low-order address

1.0.

8 Line

on

Port

O.

Description

I/O

Expander (Shift Register)

The ALE signal is provided
an

external latch.
signal is provided for enabling
to

Port

0 during a read from the Program Memory
address space. When the
Port

3 automatically generates the read

2

enabling

an

External
generates the write
memory device with the
emits the address
through a push/ pull driver
loads. At the end
automatically reprogrammed
and

Port

2 is returned

cycle. The

80S

1 generates the address,

signals needed by memory

1

that

minimize the requirements placed

program and

data

Memory cycle time is
from stable address
and

lSOns

respectively. The External

for

strobing the address into

The

program store enable (PSEN)

an

external memory device

MOVX instruction is executed

Data

Memory device

(WR)

signal for strobing the external

data

emitted by

and

data

to

the external memory

that

can sink/ source two

of

the read/write bus cycle

to

its high impedance state

to

the state it had

and

I/O

memories.

SOOns

and

Low Cost

and

PSEN

Comments

I/O

At

12

the access times required

are

Expander

(RD)

signal

for

to

Port 0 or

Port

O.

Port

0

TTL

Port

0 is

prior

to

the bus

data

and

control

devices in a manner

on

external

MHz, the Program

approximately 320ns

Data

Memory cycle

Standard

Standard

Multiplexed Address/
Da.ta

'"

C

c

'"

0

Q,

e

0

U

on

QO

Q

QO

•

ell

U

~

'"

;§

;

Q,

e

0

U

RAMs

Standard

Standard

Universal Peripheral

Interfaces 8741A

EPROMs

RAMs 2114A

I/O

Peripherals 8205

2758 I K x 8 450 ns Light Erasable
2716-1 2K x 8 350 ns Light Erasable
2732
2732A

2148
2142-2

8185A

8212
8282
8283
8255A Programmable Peripheral Interface Three 8-bit porgrammable
8251

8286
8287
8253A

8279

8291

8292
8041

4K x 8 450 ns Light Erasable
4K

x 8 250 ns Light Erasable

IK

x 4

100

ns

lK

x 4 70 ns

I K x 4

200 ns

I K x 8

300

ns

A

A

8-Bit Ii 0

8-Bit
8-Bit

Programmable Communications

Interface

I

of
Bi-directional Bus Driver are compatible with the
Bi-directional Bus Driver (Inverting) easy addition

Programmable Interval Timer
Programmable Keyboard/ Display compatible.

GPIB
GPIB Controller

ROM
EPROM

Port

I/O

Port

I/O

Port

8 Binary Decoder MCS-80 and MCS-85 peripheral devices

Interface (128 Keys)

Talker/Listener

Program

Program

User programmable

RAM

RAM

RAM
RAM

.

Memory User programmable to perform custom

Memory

Data

memory can be easily expanded

using standard

Serves as Address Latch

Serial Communcations Receiver/

Transmitter .

Future

I/O

MCS-80/85 devices will also be

and control functions.

and

erasable.

NMOS

of

RAMs.

or

I/O

I/O

ports.

8051·

allowing

specialized interfaces.

port.

Memories with

on-chip

Peripheral 8755-2
Functions.

I/O

and

8155-2
8355-2 2K x 8 300 ns ROM

Figure 2.3.

256 x 8 330 ns

2K x 8

300 ns

8051

Microcomputer Expansion Components

RAM

EPROM

5

AFN-Q1488A-09

8051

Architectural Specification and Functional Description

time

is

IllS

and the access times required from stable
address and from read (RD) or write (WR) command are
approximately 600ns and 250ns respectively.

CRYSTAL
OSCILLATOR

2.1.2.3 TIMER/EVENT COUNTERS

The

8051

contains two 16-bit counters for measuring time
intervals, measuring pulse widths, counting events and
generating precise, periodic interrupt requests. Each can

be programmed independently to operate similar to an

8048

8-bit timer with divide

counter with divide by

32

time-interval or event counter (Mode I), or

by

32

prescaler or 8-bit

prescaler (Mode 0), as a 16-bit

as

an 8-bit

time-interval or event counter with automatic reload

upon overflow (Mode

2).

Additionally, counter 0 can be programmed to a mode

or

or

generate

I's

event

3).

over-

that divides it into one 8-bit time-interval
counter and one 8-bit time-interval counter (Mode

When counter 0
programmed to any

is

in Mode

of

the three aforementioned modes,

3,

counter I can be

although it cannot set an interrupt request flag

is

useful

an interrupt. This mode
flow

can be

used

to pulse the serial port's transmission-rate

because counter

generator. Along with their multiple operating modes and

16-bit precision, the counters can also handle very high

input frequencies. These range from

1.2

(for

MHz to
an input that
and from
(for

0 Hz to an upper limit

1.2

MHz to
external inputs.

12

MHz

crystal) when programmed for

is

a division by

12

of the oscillator frequency

of

12

MHz crystal) when programmed for

Both· internal and external inputs can be

MHzto

50

KHz to 0.5 MHz

1.0

MHz

0.1

gated to the counter by a second external source for
directly measuring pulse widths.

EXTERNAL-.

SOURCE
8048 TIMER/COUNTER

•

• 16-BIT TIMER/COUNTER

• 8-BIT AUTO-RELOAD

EXTSOEURRNCALE

8048 TIMER/COUNTER

•

• 16-BIT TIMER/COUNTER

• 8-BIT AUTO-RELOAD TIMER/COUNTER

$

TIMER/COUNTER

CRYSTAL

°ii~O,.R

-.

__

~~~~~

Figure 2.4.A. Timer/Event Counter

Modes

CRYSTAL
OSCilLATOR

EXTERNAL

SOURCE

• 8-BIT TIMER/COUNTER

$

___

CRYSTAL
OSCilLATOR

CRYSTAL

OSCILLATOR

L--

• 8-BIT

~_--I~

__

~

1---4t----I~

0,

1,

and 2

____

--I~ (INTERRUPT

TIMER

OVERFLOW
(INTERRUPT

REQUEST)
FLAG 0

OVERFLOW
(INTERRUPT

REQUEST)
FLAG 1

PULSE TO
SERIAL PORT

OVERFLOW
(INTERRUPT
REQUEST)
FLAG

1

OVERFLOW
REQUEST)

FLAG 0

The counters are started and stopped under software
control. Each counter sets its interrupt request flag when

aU

it overflows from all ones to

zeros (or auto-reload
value). The operating modes and input sources are
summarized

in Figures 2.4A and 2.4B. The effects

of

the

configuration flags and the status flags are shown in

Figures 2.5A and 2.5B.

GATE

INTO

--~=-~l:'~>-"t"--r-\--J====j~:J

TO------~

XTAl1

COUNTER/TIMER RUN

Figure

2.S.A.

Timer/Counter 0 Control and Status Flag Circuitry

$

EX;5~:~~'"

• 8048 TIMER/COUNTER

• 16-BIT TIMER/COUNTER

• 8-BIT AUTO-RELOAD TIMER/COUNTER

Figure 2.4.8. Timer/Event Counter Mode 3

COUNTER 0

MODE

0:

8-BIT TIMER WITH PRESCALER/8-BIT COUNTER

>----f

6

WITH PRESCAlER

MODE

1:

16-BIT TIMER/COUNTER

2:

8-BIT AUTO-RELOAD TIMER/COUNTER

MODE

3:

8-BIT TIMER/COUNTER (TlO)

MODE

INTERRUPT
REQUEST

PULSE TO

SERIAL PORT

AFN-01488A-l0

8051

Architectural Specification and Functional Description

TIMERI
COUNTER
OIN
MODE 3

INT1

T1

XTAL1

GATE

--

1"'"

~r~

COUNTERI

TIMER

RUN

~

G

Hn

COUNTER 1

MODE

0:

8-BIT TIMER WITH PRESCALERI
8-BIT COUNTER WITH PRESCALER-

MODE

1: 16-BIT TIMER/COUNTER

MODE 2: 8-BIT AUTO-RELOAD TIC
MODE

3:

PREVENTS INCREMENTING
OF TIC 1

J

>-

~

-

1

"'

+12

Figure 2.5.8. Timer/Counter 1 Control and Status Flag Circuitry

-

~

r-r-

-r-

~

~

:=fJ-

-

PULSE

TO
SERIAL
PORT

COUNTER 0

-

J

8-8ITTIMER

(THO)

INTERRUPT
REQUEST

•

)-

• 100r11

Bit

Frame r - - -

• Baud

Rate

from Oscillator

Timer 1 I

• Address Frame

Recognition I

Generetlon I INTERRUPT

or

I

--

- -

SCON

(SERIAL CONTROL)

--

I

I

CONTROL"

TIMING CIRCUITRY

I

g:~~~~t.,.OR

TIMER 1
OVERFLOW

2.1.2.4 SERIAL COMMUNICATIONS

The

8051

has a serial
linking peripheral devices as
through standard asynchronous protocols with full­duplex operatiori. The serial port also has a synchronous
mode for expansion of
shift registers. This hardware serial communications
interface saves

transmission rate than could be achieved through

software. In response

CPU has only to read/write the serial port's buffer to

-

....

1 .....

-:-16

L

______________

Figure 2.6. Serial

I/O

port that

I/O

lines using CMOS and TTL

ROM code and permits a much higher

to

a serial port interrupt request the

is

useful for serially

well

as

multiple805ls

Port~UART

-

--

7

-

---:;:R:;:;S;.-TT-;;-----l

I-

___

~-~-----~

RECEIVER

~~

Modes 1, 2, and 3

service the serial link. A block diagram
shown in Figure 2.6. Methods for linking U
sal asynchronous receiver / transmitter) devices are shown

2.7

in Figure
Figure 2.8.

The full-duplex serial

o modes to facilitate communications with standard U

devices, such as printers and
munications with other

and a method for

___

I/O

I/O

port provides asynchronous

CRT

8051s in multi-processor systems.

-:-

__

_

of

the serial port

ART

expansion

terminals, or com-

~~~~SMIT

RECEIVE
DATA

(univer-

is

shown in

ART

AFN-01488A-11

is

8051 Architectural Specification and Functional Description

I

I

TXD RXD

8051 8051

A. MULTI-80S1

The receiver

is

that would occur if the

TXD RXD TXD

INTERCONNECT

double buffered to eliminate the overrun

CPU
receiver's interrupt before the beginning
frame. Double buffering

8051

since the

can generally maintain the serial link

of

.~

RXD

8051 8051

-HALF

DUPLEX B. MULTI-80S1

Figure 2.7.

RXD TXD

UART

failed to respond to the

of

the next

the transmitter is not needed

at

its
maximum rate without it. A minor degradation in
transmission rate can occur in rare events such as when

of

the servicing

the transmitter has to wait for a lengthy

interrupt service program to complete. In asynchronous

is

modes, false start-bit rejection

For

frames.

noise rejection a best two-out-of-three vote

taken on three samples near the center

provided on received

is

of

each received

bit.

When interfacing with standard UART devices the serial

1)

channel can be programmed to a mode (Mode

or

transmits/ receives a ten-bit frame

or

3)

mode (Mode 2
frame as shown in Figure 2

or

bit, eight

3,

the transmission-rate timing circuitry receives a pulse

nine data bits and a stop bit. In Modes 1 and

from counter
input to counter 1 can

12

of the oscillator frequency. The auto-reload mode

by
of

the counter provides communication rates

that transmits/receives an eleven-bit

..

9.

The frame consists

I each time the counter overflows. The

be

an

external source

programmed

or

that
to

of

a start

a division

of

122

to
31,250 bits per second (including start and stop bits) for a
12

MHz crystal. In Mode 2 the communication rate

of

division by 64

transmission rate of
start and stop bits) for a

the oscillator frequency yielding a

187,500 bits per second (including

12

MHz crystal.

is

~

TXD

RXD TXD RXD

8051

INTERCONNECT

-FULL

Interfacing Schemes

A.1I0INPUT
EXPANSION

B.

a

EXPANSION

Figure 2.8. I/O Expansion Technique

TTY

TYPICAL

a

CRT

RXD

r-----

TXD
CTS

~.

8251

OS
EN

MODE

8051

DUPLEX

8051

DATA

CLOCK

PORT

8051

DATA

CLOCK

PORT

110

OUTPUT

PIN

PIN

TXD
RXD

PORT PIN

8051

C.

8051-8251 INTERFACE

~~~--------~--~--~---'I~

START

START

START 8-BIT

7-BIT

7·BIT

DATA

PARITY'

DATA MARK STOP

DATA

2

PARITY

,

STOP

STOP

Distributed processing offers a faster, more powerful

be

system than can

provided by a single
This results from a hierarchy
processors, each with its own memories and

8051

multiprocessing, a host

of

8051

multiplicity
lyon

separate portions

portion

of

the overall process. The interconnected

s configured to operate simultaneous-

microcomputer controls a

of

the program, each controlling a

reduce the load on the host processor and result in a
cost system

of

data transmission. This form

CPU

processor.

of

interconnected

of

distributed

1/

O.

8051

low-

In

2&3

MULTI­PROCESSOR
COMMUNICA­TIONS

1/0

s

EXPANSION

START

START

....

------------'

a-BIT DATA

a·BITS

9-BIT DATA

j..DATA

__

~~~:I

STOP

STOP

ClK

2&3

o

Figure 2.9. Typical Frame Formats

AFN-01488A-12

8

8051

Architectural Specification and Functional Description

processing
in a complex process are required

is

especially effective in systems where controls

at

physically separated

locations.

and

In Modes 2

3 the automatic wake-up of slave
processors through interrupt driven address-frame
recognition

is

provided

to

facilitate interprocessor com­munications. The protocol for interprocessor com­munications

1.

Slaves

2.

Master-Transmit

3.

Slaves - Serial port interrupts

4.

Master-Transmit

Figure 2.10. Protocol for Multi-Processor

In synchronous mode (Mode
provides
lines using standard

is

shown in Figure 2.10.

-Configure
received ninth

data
data

frame
compares received address to its address.
The slave which has been addressed recon­figures its serial

all subsequent transmissions.

(these will

addressed slave.)

an

efficient, low-cost method

serial

port

to

data

frame containing address in first 8

bits

and

bit designates address frame).

is

Communications

set ninth

received. Interrupt service program

port

control frames and

be

accepted only by the previously

TTL

and CMOS shift registers. The

interrupt

bit

is

a one (I).

data

bit (i.e., ninth

CPU

when address

to interrupt the

0)

the high-speed serial port

of

expanding

CPU

data

if the

CPU

frames

on

I/O

serial channel provides a clock output for synchronizing

. the shifting

rate

is

I M bits

of

bits

a.division

p(:r

second

to/from

by

an

external register. The

12

of the oscillator frequency

at

12

MHz.

data

and

2.2 CPU HARDWARE

This section describes the hardware architecture of the
8051's

CPU

in

detaiL The interrupt system and on-chip
functions peripheral to the
subsequent sections. A detailed
Diagram

2.2.1

is

displayed in Figure

Instruction Decoder

Each program instruction
decoder. This unit generates the internal signals that

control the functions of each unit within the
tion. These signals control the sources and destination
of data, as

well

as the function of the Arithmetic/Logic

Unit (ALU).

CPU are described

8051

Functional Block

2.

II.

is

decoded by the instruction

CPU sec-

in

is

2.2.3 Internal Data Memory

The

8051

contains a I 28-byte Internal

includes registers

R7-RO

twenty memory-mapped

2.2.3.1 INTERNAL

The Internal

Data

RAM provides a convenient 128-byte

in e'ach of four Banks), and

Special Functional Registers.

DATA

RAM

scratch pad memory.

2.2.3.2 REGISTER BANKS

There are four 8-Register Banks within the Internal Data

RAM, each containing registers

2.2.3.3 SPECIAL

FUNCTION

The Special Function Registers include arithmetic registers
(A ,

B,

PSW), pointers (SP,

that provide

an

interface between the CPU and the

DPH,

on-chip peripheral functions.

2.2.3.4 A REGISTER

The A register
location

2.2.3.5 B REGISTER

of

The B register

is

the accumulator register. ACC

the accumulator in the Internal Data Memory.

is

dedicated during multiply and divide and
serves as both a source and a destination. During all other
operations the B register

is

simply another location of

the Internal Data Memory.

2.2.3.6 PSW REGISTER

The carry (CY), auxialiary carry (AC), user flag 0 (FO),
register bank select I (RS I), register bank select 0 (RSO),
overflow (OV) and parity (P) flags reside in the Program
Status Word (PSW) Register. These flags are bit­memory-mapped within the byte-memory-mapped
The PSW flags record processor status information and
control the operation of the processor.

The CY, AC, and

OV

flags generally reflect the status of
the latest arithmetic operation. The P flag
the parity of the A register. The carry flag
Boolean accumulator for bit operations.
are provided in the

"Flag Register Settings" section

2.7.2.
FO

is

a general purpose flag which

stack as

part

of

a PSW save.

The two Register Bank select bits
mine which of the four 8-Register Banks

Data

RAM

R7-RO.

REGISTERS

DPL) and registers

always reflects

Specific details

is

pushed onto the

(RS I 'and

is

selected.

is

RSO)

(which

is

the

PSW.

also a

of

deter-

2.2.2 Program Counter

The I6-bit Program Counter (PC) controls the sequence in
which the instructions stored in program memory are
executed.
instructions listed in section 2.7.2.

It

is

manipulated with the Control Transfer

2.2.3.7 STACK POINTER

The 8-bit Stack Pointer (SP) contains the address at
which the last byte
also the address of the next byte that
is

updatable under software control.

was

pushed onto the stack. This

will

be

popped.

AFN·01488A-13

9

is

SP