Intel 80386EX (386EX) User Manual

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Intel386™ EX Embedded Microprocessor User’s Manual

Intel386™ EX

Embedded

Microprocessor

User’s Manual

February 1995

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Co nditi on s of Sale for such products.

Intel Corporation makes no warr anty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation. Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark

or products. *Other brands and names are the property of their respective owners. Additional copies of this document or other Intel literature may be obtained from:

Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

CHAPTER 1

GUIDE TO THIS MANUAL

1.1 MANUAL CONTENTS................................................................................................... 1-1

1.2 NOTATIONAL CONVENTIONS..................................................................................... 1-2

1.3 SPECIAL TERMINOLOGY............................................................................................ 1-4

1.4 RELATED DOCUMENTS.............................................................................................. 1-5

1.5 CUSTOMER SERVICE.................................................................................................. 1-6

1.5.1 How to Use Intel's FaxBack Service .........................................................................1-6

1.5.2 How to Use Intel's Application BBS . ............ ..................................... ........................1-7

1.5.3 How to Find the Latest

Data Sheets on the BBS............................................................................................1-8

CHAPTER 2

ARCHITECTURAL OVERVIEW

2.1 CORE ............................................................................................................................ 2-1

2.2 INTEGRATED PERIPHERALS...................................................................................... 2-3

2.3 PC COMPATIBILITY...................................................................................... ................ 2-5

2.3.1 I/O Considerations ....................................................................................................2-5

2.3.2 PC/AT Compatibility ..................................... ..... ..... .......... .. ..... .......... .. ..... ..... ............2-5

2.3.3 Enhanced DMA Controller ........................................................................................2-5

2.3.4 SIO Channels ............................................................................................................2-6

CHAPTER 3

CORE OVERVIEW

3.1 SYSTEM MANAGEMENT MODE OVERVIEW ............................................................. 3-2

3.1.1 SMM Hardware Interface ..........................................................................................3-2

3.1.1.1 SMI# (System Management Interrupt Input) ........................ ....... ..... ..... ..........3-2

3.1.1.2 SMIACT# (SMM Active Output ) ............... ........................................................3-3

3.1.2 SMI# Interrupt .................................. ................. ............... ............ ................. ............3-3

3.1.3 SMRAM .....................................................................................................................3-5

3.1.4 Chip-select Unit Support for SMRAM .. ....... ....... ........................................................3-6

3.1.5 I/O Restart .................................................................................................................3-7

3.1.6 HALT Restart ............................................................................................................3-7

3.1.7 SMRAM State Dump Area ........................................................................................3-8

3.1.8 Resume Instruction (RSM) ...................................................................................... 3-10

3.1.9 SMM Priority ....... ............ ................. ............ ............... ................. ............ ............ ...3-10

3.2 SYSTEM MANAGEMENT INTERRUPT...................................................................... 3-10

3.2.1 System Management Interrupt During HALT Cycle ................................................3-12

3.2.2 System Management Interrupt During I/O Instru ction ........ ............... ............ ..........3-13

3.2.3 Interrupt During SMM Handler ................................................................................3-14

3.2.4 SMM Handler Terminated by RESET .....................................................................3-15

3.2.5 HALT During SMM Handler .................................................................................... 3-16

BUILDER Files and Hypertext Manuals and

iii

3.2.6 SMI# During SMM Operation ..................................................................................3-17

3.3 THE Intel386 EX™ PROCESSOR IDENTIFIER REGISTERS ....................................3-17

CHAPTER 4

SYSTEM REGISTER ORGANIZATION

4.1 OVERVIEW ................................................................................................................... 4-2

4.1.1 Intel386™ Processor Core Architecture Registers ...................................................4-2

4.1.2 Intel386™ EX Processor Peripheral Registers .........................................................4-3

4.2 I/O ADDRESS SPACE FOR PC/AT SYSTEMS............................................................ 4-3

4.3 EXPANDED I/O ADDRESS SPACE. ............................................................................. 4-5

4.4 ORGANIZATION OF PERIPHERAL REGISTERS........................................................ 4-7

4.5 I/O ADDRESS DECODING TECHNIQUES................................................................... 4-8

4.5.1 Address Configuration Register ......................................................................... .. .....4-8

4.5.2 Enabling and Disabling the Expanded I/O Space ..................................................... 4-9

4.5.2.1 Programming REMAPCFG Example ...............................................................4-9

4.6 ADDRESSING MODES . .............................................................................................. 4-10

4.6.1 DOS-compatible Mode ............................................................................................4-10

4.6.2 Nonintrusive DOS Mode .........................................................................................4-12

4.6.3 Enhanced DOS Mode .............................................................................................4-12

4.6.4 NonDOS Mode ........................................................................................................4-12

4.7 PERIPHERAL REGISTER ADDRESSES.................................................................... 4-16

CHAPTER 5

DEVICE CONFIGURATION

5.1 INTRODUCTION ........................................................................................................... 5-1

5.2 PERIPHERAL CONFIGURATION................................................................................. 5-2

5.2.1 DMA Controller, Bus Arbiter, and Refresh Unit Configuration ..................................5-3

5.2.1.1 Using The DMA Unit with External Devices ....................................................5-3

5.2.1.2 DMA Service to an SIO or SSIO Peripheral ....................................................5-4

5.2.1.3 Using The Timer To Initiate DMA Transfers ....................... ....... .......... ....... ..... 5-4

5.2.1.4 Limitations Due To Pin Signal Multiplexing ....... ..... .........................................5-4

5.2.2 Interrupt Control Unit Configurati o n .................. ............. ......... .......... ....... .......... .......5-7

5.2.3 Timer/Counter Unit Configuration ...........................................................................5-10

5.2.4 Asynchronous Serial I/O Configuration ...................................................................5-12

5.2.5 Serial Synchronous I/O Configuration ................................................. ....................5-17

5.2.6 Core Configuration .................................................................. ................................5-18

5.3 PIN CONFIGURATION ................................................................................................ 5-20

5.4 DEVICE CONFIGURATION PROCEDURE ................................................................ 5-25

5.5 CONFIGURATION EXAMPLE. .................................................................................... 5-25

5.5.1 Example Design Requirements ............................................................................... 5-26

5.5.2 Example Design Solution ........................................................................................5-26

CHAPTER 6

CLOCK AND POWER MANAGEMENT UNIT

6.1 OVERVIEW ................................................................................................................... 6-1

6.1.1 Clock Generation Logic .............................................................................................6-1

6.1.2 Power Management Logic ........................................................................................6-3

6.1.2.1 SMM Interaction with Power Management Modes ..........................................6-4

6.1.2.2 Bus Interface Unit Operation During Idle Mode ............. ...................... ............6-5

6.1.2.3 Watchdog Timer Unit Operation During Idle Mode .......................................... 6-5

6.1.3 Clock and Power Management Register s and Signals .............................................6-5

6.2 CONTROLLING THE PSCLK FREQUENCY ................................................................ 6-6

6.3 CONTROLLING POWER MANAGEMENT MODES..................................................... 6-8

6.3.1 Idle Mode ........................................................................................................... ....... 6-9

6.3.2 Powerdown Mode ................................................................................................... 6-10

6.4 DESIGN CONSIDERATIONS...................................................................................... 6-11

6.4.1 Reset Considerations ..............................................................................................6-11

6.4.2 Powerdown Considerations .................................................................................... 6-13

CHAPTER 7

BUS INTERFACE UNIT

7.1 OVERVIEW ................................................................................................................... 7-1

7.1.1 Bus Signal Descriptions ............................................................................................7-2

7.2 BUS OPERATION ......................................................................................................... 7-4

7.2.1 Bus States .................................................................................................................7-7

7.2.2 Pipelining ..................................................................................................................7-8

7.2.3 Data Bus Transfers and Operand Alignment ............................................................7-8

7.2.4 Ready Logic ............................................................................................................7-10

7.3 BUS CYCLES.............................................................................................................. 7-12

7.3.1 Read Cycle .............................................................................................................7-12

7.3.2 Write Cycle ...................... ............................. ................................ ........................ ...7-14

7.3.3 Pipelined Cycle .......................................................................................................7-16

7.3.4 Interrupt Acknowledge Cycle ..................................................................................7-19

7.3.5 Halt/Shutdown Cycle ...............................................................................................7-22

7.3.6 Refresh Cycle .........................................................................................................7-24

7.3.7 BS8 Cycle ...............................................................................................................7-27

7.4 BUS LOCK................................................................................................................... 7-29

7.4.1 Locked Cycle Activators .......................................................................................... 7-29

7.4.2 Locked Cycle Timing ...............................................................................................7-29

7.4.3 LOCK# Signal Duration ...........................................................................................7-30

7.5 HOLD/HLDA (HOLD ACKNOWLEDGE)...................................................................... 7-30

7.5.1 HOLD/HLDA Timing ................................................................................................7-31

7.5.2 HOLD Signal Latency .............................................................................................7-33

CHAPTER 8

INTERRUPT CONTROL UNIT

8.1 OVERVIEW ................................................................................................................... 8-1

8.2 ICU OPERATION.............................................................. ............................................. 8-4

8.2.1 Interrupt Sources ......................................... ............... ................. ............ ............ ..... 8-4

8.2.2 Interrupt Priority ........................ ....... .......... ....... .......... .......... ............ ....... .......... .......8-5

8.2.2.1 Assigning an Interrupt Level ............................................................................8-5

8.2.2.2 Determining Priority .........................................................................................8-6

8.2.3 Interrupt Vectors .................. ........................ ..................................... ........................8-7

8.2.4 Interrupt Process .......................................................................................................8-8

8.2.5 Poll Mode ................................................................................................................8-12

8.3 PROGRAMMING......................................................................................................... 8-13

8.3.1 Port 3 Configuration Register (P3CFG) ..................................................................8-15

8.3.2 Interrupt Configuration Register (INTCFG) .............................................................8-16

8.3.3 Initializatio n Command Word 1 (ICW1) ...................................................................8-17

8.3.4 Initializatio n Command Word 2 (ICW2) ...................................................................8-18

8.3.5 Initializatio n Command Word 3 (ICW3) ...................................................................8-19

8.3.6 Initializatio n Command Word 4 (ICW4) ...................................................................8-21

8.3.7 Operation Command Word 1 (OCW1) .. ..................................................................8-22

8.3.8 Operation Command Word 2 (OCW2) .. ..................................................................8-23

8.3.9 Operation Command Word 3 (OCW3) .. ..................................................................8-24

8.3.10 Poll Status Byte (POLL) ..........................................................................................8-25

8.3.11 Programming Considerations ..................................................................................8-25

8.4 DESIGN CONSIDERATIONS...................................................................................... 8-26

8.4.1 Interrupt Acknowledge Cycle ..................................................................................8-26

8.4.2 Interrupt Detection ..... .................................. ........................... ............................. ...8-27

8.4.3 Spurious Interrupts .................................................................................................. 8-28

8.4.4 Interrupt Timing ................................................................................... .................... 8-28

CHAPTER 9

TIMER/COUNTER UNIT

9.1 OVERVIEW ................................................................................................................... 9-1

9.1.1 TCU Signals and Registers .......................................................................................9-2

9.2 TCU OPERATION ......................................................................................................... 9-4

9.2.1 Mode 0 – Interrupt on Terminal Count ......................................................................9-6

9.2.2 Mode 1 – Hardware Retriggerable One-shot ............................................................9-8

9.2.3 Mode 2 – Rate Generator .......................................................................................9-10

9.2.4 Mode 3 – Square Wave ..........................................................................................9-12

9.2.5 Mode 4 – Software- triggered Strobe .......................................................................9-16

9.2.6 Mode 5 – Hardware-triggered Strobe ......................................................................9-18

9.3 PROGRAMMING......................................................................................................... 9-20

9.3.1 Configuring the Input and Output Signals ...............................................................9-20

9.3.2 Initializing the Counters ................................ ................................ ........................ ...9-25

9.3.3 Writing the Counters ............................................................................................... 9-27

9.3.4 Reading the Counter .. ........................................................................................ .....9-28

9.3.4.1 Simple Read . .................................................................................................9-28

9.3.4.2 Counter-latch Command ............................................................................... 9-29

9.3.4.3 Read-back Command ...................................................................................9-31

9.3.5 Programming Considerations ..................................................................................9-34

CHAPTER 10

WATCHDOG TIMER UNIT

10.1 OVERVIEW ................................................................................................................. 10-1

10.1.1 WDT Operation .......................................................................................................10-2

10.1.2 WDT Registers and Signals .................................................................................... 10-3

10.2 PROGRAMMING THE WDT........................................................................................ 10-5

10.2.1 General-purpose Timer Mode . .... ............................................................................10-7

10.2.2 Software Watchdog Mode .......................................................................................10-8

10.2.3 Bus Monitor Mode ...................................................................................................10-8

10.3 DISABLING THE WDT ................................................................................................ 10-9

10.4 DESIGN CONSIDERATIONS ...................................................................................... 10-9

CHAPTER 11

ASYNCHRONOUS SERIAL I/O UNIT

11.1 OVERVIEW ................................................................................................................. 11-1

11.1.1 SIO Signals .............................................................................................................11-3

11.2 SIO OPERATION ........................................................................................................ 11-3

11.2.1 Baud-rate Ge nerator ............................. .......... ............ ....... .......... ....... .......... ..........11-4

11.2.2 Transmitter ..............................................................................................................11-5

11.2.3 Receiver ..................................................................................................................11-8

11.2.4 Modem Control .....................................................................................................11-10

11.2.5 Diagnostic Mode ...................................................................................................11-10

11.2.6 SIO Interrupt Sources ...........................................................................................11-11

11.3 PROGRAMMING.................... ................................................................................... 11-12

11.3.1 Pin and Port Configuration Register s (PINCFG and P

11.3.2 SIO and SSIO Configuration Register (SIOCFG) .................................................11-18

11.3.3 Divisor Latch Registers (DLL

11.3.4 Transmit Buffer Register (TBR

11.3.5 Receive Buffer Register (RBR

11.3.6 Serial Line Control Register (LCR

11.3.7 Serial Line Status Register (LSR

11.3.8 Interrupt Enable Register (IER

11.3.9 Interrupt ID Register (IIR

11.3.10 Modem Control Register (MCR

11.3.11 Modem Status Register (MSR

and DLHn) ............................................................11-19

) ............... .. ................................................... .......11-20

) ...........................................................................11-21

) ............... .. ................................................... ..11-22

) .......................................................................11-23

) ...........................................................................11-24

) ....................................................................................11-25

) ..........................................................................11-26

) ...........................................................................11-28

CFG [n = 1–3]) ................11-14

vii

11.3.12 Scratch Pad Register (SCRn) ...............................................................................11-29

11.4 PROGRAMMING CONSIDERATIONS...................................................................... 11-29

CHAPTER 12

SYNCHRONOUS SERIAL I/O UNIT

12.1 OVERVIEW ................................................................................................................. 12-1

12.1.1 SSIO Signals ...........................................................................................................1 2-4

12.2 SSIO OPERATION.................................................................................................... .. 12-4

12.2.1 Baud-rate Ge nerator ............................. .......... ............ ....... .......... ....... .......... ..........12-4

12.2.2 Transmitter ..............................................................................................................12-6

12.2.3 Receiver ..................................................................................................................12-9

12.3 PROGRAMMING.................... ................................................................................... 12-11

12.3.1 Pin Configuration Register (PINCFG) ................................................. ..................12-13

12.3.2 SIO and SSIO Configuration Register (SIOCFG) .................................................12-14

12.3.3 Prescale Clock Register (CLKPRS) ......................................................................12-15

12.3.4 SSIO Baud-rate Control Register (SSIOBAUD) ................................................... .12-16

12.3.5 SSIO Baud-rate Count Down Register (SSIOCTR) ..............................................12-17

12.3.6 SSIO Control 1 Register (SSIOCON1) ................... ............ ............... ................. ...12-18

12.3.7 SSIO Control 2 Register (SSIOCON2) ................... ............ ............... ................. ...12-20

12.3.8 SSIO Transmit Holding Buffer (SSIOTBUF) .........................................................12-21

12.3.9 SSIO Receive Holding Buffer (SSIORBUF) . .........................................................12-22

12.4 DESIGN CONSIDERATIONS.................................................................................... 12-22

CHAPTER 13

INPUT/OUTPUT PORTS

13.1 OVERVIEW ................................................................................................................. 13-1

13.2 PROGRAMMING......................................................................................................... 1 3-4

13.2.1 Pin Configuration ....................................................................................................13-4

13.2.2 Initializati o n Se quence ............................................................................................13-7

13.3 DESIGN CONSIDERATIONS ...................................................................................... 13-7

13.3.1 Pin Status During and After Reset .................... ............... ............ ............ ............... 1 3-8

CHAPTER 14

CHIP-SELECT UNIT

14.1 OVERVIEW ................................................................................................................. 14-1

14.2 CSU OPERATION....................................................................................................... 14-1

14.2.1 Defining a Channel’s Address Block ....................................................................... 14-1

14.2.2 System Management Mode Support ...................................................................... 14-7

14.2.3 Bus Cycle Length Control ................................. ................. ............... ............ .......... 1 4-7

14.2.4 Bus Size Control .....................................................................................................14-7

14.2.5 Overlapping Regions ..............................................................................................14-8

14.3 PROGRAMMING......................................................................................................... 1 4-9

14.3.1 Pin Configuration Register (PINCFG) ................................................. ..................14-11

viii

14.3.2 Port 2 Configuration Register (P2CFG) ....... .........................................................14-12

14.3.3 Chip-select Address Registers ..............................................................................14-13

14.3.4 Chip-select Mask Registers ..................................................................................14-15

14.3.5 Programming Considerations ................................................................................14-16

CHAPTER 15

REFRESH CONTROL UNIT

15.1 DYNAMIC MEMORY CONTROL................................................................................. 15-1

15.2 RCU OVERVIEW......................................................................................................... 15-1

15.2.1 RCU Signals ...........................................................................................................15-3

15.2.2 Refresh Intervals .....................................................................................................15-3

15.2.3 Refresh Addresses .................................................................................................15-4

15.2.4 Refresh Methods .....................................................................................................15-4

15.2.5 Bus Arbitration ................ ..... ..... ..... ..... ..... .... ..... ..... ..... ..... ..... ..... ..... .... ..... ..... ..... .. ... 1 5-4

15.3 RCU OPERATION....................................................................................................... 15-5

15.4 PROGRAMMING......................................................................................................... 1 5-6

15.4.1 Refresh Clock Interval Register (RFSCIR) ..............................................................15-7

15.4.2 Refresh Control Register (RFSCON) ......................................................................15-8

15.4.3 Refresh Base Address Register (RFSBAD) ............................................................15-9

15.4.4 Refresh Address Register (RFSADD) ...................................................................15-10

15.5 DESIGN CONSIDERATIONS.................................................................................... 15-10

CHAPTER 16

DMA CONTROLLER

16.1 OVERVIEW ................................................................................................................. 16-1

16.1.1 DMA Signals ...........................................................................................................16-3

16.2 DMA OPERATION ....................................................................................................... 16-3

16.2.1 DMA Transfers ........................................................................................................16-3

16.2.2 Bus Cycle Options for Data Transfers .....................................................................16-4

16.2.3 Starting DMA Transfers ............................. .............................................................16-5

16.2.4 Bu s Control Arbitration ................... ..... .. ..... .. ..... ..... ... ..... .. ..... .. ..... ..... .. ..... ..... ... .... ...16-6

16.2.5 Ending DMA Transfers ............................................................................................1 6-6

16.2.6 Buffer-transfer Modes .............................................................................................16-7

16.2.7 Data-transfer Modes ................. ................. ............ ............ ................. ............... ..... 1 6-8

16.2.7.1 Single Data-transfer Mode ................................................. ...........................16-9

16.2.7.2 Block Data-transfer Mode ............................................................................16-13

16.2.7.3 Demand Data-transfer Mode .......................................................................16-16

16.2.8 Cascade Mode ......................................................................................................16-20

16.2.9 DMA Interrupts ......................................................................................................16-21

16.2.10 8237A Compatibility ..............................................................................................16-22

16.3 PROGRAMMING.................... ................................................................................... 16-23

16.3.1 Pin Configuration Register (PINCFG) ................................................. ..................16-26

16.3.2 DMA Configuration Register (DMACFG) ..............................................................16-27

16.3.3 Channel Registers ................................................................................................ 16-28

16.3.4 Overflow Enable Register (DMAOVFE) ............................................................. ...16-29

16.3.5 Command 1 Register (DMACMD1) .......................................................................16-30

16.3.6 Status Register (DMASTS) ...................................................................................16-31

16.3.7 Command 2 Register (DMACMD2) .......................................................................16-32

16.3.8 Mode 1 Register (DMAMOD1) ..............................................................................16-33

16.3.9 Mode 2 Register (DMAMOD2) ..............................................................................16-34

16.3.10 Software Request Register (DMASRR) ................................................................ 16-36

16.3.11 Channel Mask and Group Mask Registers (DMAMSK and DMAGRPMSK) .........16-38

16.3.12 Bus Size Register (DMABSR) ...............................................................................16-39

16.3.13 Chaining Register (DMACHR) ..............................................................................16-40

16.3.14 Interrupt Enable Register (DMAIEN) .....................................................................16-41

16.3.15 Interrupt Status Register (DMAIS) ........................................................................16-42

16.3.16 Software Commands ............................................................................................16-43

16.3.17 Programming Considerations ................................................................................16-44

CHAPTER 17

JTAG TEST-LOGIC UNIT

17.1 OVERVIEW ................................................................................................................. 17-1

17.2 TEST-LOGIC UNIT OPERATION................................................................................ 17-3

17.2.1 Test Access Port (TAP) ..........................................................................................17-3

17.2.2 Test Access Port (TAP) Controller ..........................................................................17-4

17.2.3 Instructi on Register (IR) ............................. .. .......... ..... ....... ..... .......... .. .......... ..... .....17-7

17.2.4 Data Registers ........................................................................................................17-8

17.3 TESTING................................ ................... .. ................................... ................... .. ...... 17-10

17.3.1 Identifying the Device .................................................................................... ........17-11

17.3.2 Bypassing Devices on a Board .............................................................................17-11

17.3.3 Sampling Device Operation and Preloading Data .................................................17-11

17.3.4 Testing the Device ................................................................................................17-12

17.3.5 Testing the Interconnections .................................................................................17-12

17.3.6 Disabling the Output Drivers .................................................................................17-12

17.4 TIMING INFORMATION ............................................................................................ 17-13

17.5 DESIGN CONSIDERATIONS.................................................................................... 17-15

APPENDIX A

SIGNAL DESCRIPTIONS

APPENDIX B

COMPATIBILITY WITH PC/AT* ARCHITECTURE

B.1 DEPARTURES FROM PC/AT* SYSTEM ARCHITECTURE........................................ B-1

B.1.1 DMA Unit .................................................... ................................ ........................ .... B-1

B.1.2 Bus Signals ............................................................................................................. B-2

B.1.3 Interrupt Control Unit .............................................................................................. B-4

B.1.4 SIO Units .................. ..............................................................................................B-4

B.1.5 Word Read/Write Access of 8-bit Registers .................... ....... .......... ....... .......... ...... B-4

B.1.6 CPU- o nly Reset ........ .............................................................................................. B-4

B.1.7 HOLD, HLDA Pins ..................................................................................................B-5

GLOSSARY

INDEX

CONTENTS

FIGURES

Figure Page

2-1 Intel386™ EX Processor Block Diagram......................................................................2-2

3-1 Standard SMI# ...........................................................................................................3-11

3-2 SMIACT# Latency......................................................................................................3-12

3-3 SMI# During HALT.....................................................................................................3-13

3-4 SMI# During I/O Instruction................. ................................ ............................. .......... 3-13

3-5 SMI# Timing. ..............................................................................................................3-14

3-6 Interrupted SMI# Service............................................................................................3-15

3-7 SMI# Service Terminated by RESET.........................................................................3-16

3-8 HALT During SMM Handler........................................................................................3-17

4-1 PC/AT I/O Address Space............................................................................................4-4

4-2 Expanded I/O Address Space......................................................................................4-6

4-3 Address Configuration Register (REMAPCFG)............................................................ 4-9

4-4 Programming the ESE Bit ..........................................................................................4-10

4-5 DOS-Compatible Mode ..............................................................................................4-11

4-6 Example of Nonintrusive DOS-Compatible Mode ......................................................4-13

4-7 Enhanced DOS Mode ................................................................................................ 4-14

4-8 NonDOS Mode...........................................................................................................4-15

5-1 Peripheral and Pin Connections...................................................................................5-2

5-2 Configuration of DMA, Bus Arbiter, and Refresh Unit ................................. ............ ..... 5-5

5-3 DMA Configuration Register.........................................................................................5-6

5-4 Interrupt Control Unit C onfigurati o n........................... ..... ....... ........ ....... ....... ..... ....... ..... 5- 8

5-5 Interrupt Configurati on Register ... ....... .......... ....... ............. ......... .......... ....... .......... .......5-9

5-6 Timer/Counter Unit Configuration...............................................................................5-11

5-7 Timer Configuration Register......................................................................................5-12

5-8 Serial I/O Unit 0 Configuration....................................................................................5-14

5-9 Serial I/O Unit 1 Configuration....................................................................................5-15

5-10 SIO and SSIO Configuration Register.................................................. ......................5-16

5-11 SSIO Unit Configuratio n .............................................................................................5-17

5-12 Core Confi guration.....................................................................................................5-18

5-13 Port 92 Configuration Register ...................................................................................5-19

5-14 Pin Confi gur ation Register .........................................................................................5-21

5-15 Port 1 Configuration Register.....................................................................................5-22

5-16 Port 2 Configuration Register.....................................................................................5-23

5-17 Port 3 Configuration Register.....................................................................................5-24

5-18 Ab bre viated Pin Conf iguration Register Tables..........................................................5-27

5-19 Ab bre viated Peripheral Configuration Register Tables..............................................5-28

5-20 Peripheral and Pin Connections for the Example Design...........................................5-29

5-21 Pin Confi guration Worksheet......................................................................................5-30

5-22 Peripheral Co nfiguration Worksheet...........................................................................5-31

6-1 Clock and Power Management Unit Connections........................................................6-2

6-2 Clock Synchronization..................................................................................................6-3

6-3 SMM Interaction with Idle and Powerdown Modes.......................................................6-4

6-4 Clock Prescale Register (CLKPRS).............................................................................6-7

6-5 PSCLK Divider Circuitry ...............................................................................................6-8

xii

CONTENTS

FIGURES

Figure Page

6-6 Power Control Register (PWRCON).............................................................................6-9

6-7 Timing Diagram, Entering and Leaving Idle Mode.....................................................6-10

6-8 Timing Diagram, Entering and Leaving Powerdown Mode ........................................ 6-11

6-9 Reset Synchronization Circuit....................................................................................6-12

6-10 Phase Clock Generator ..............................................................................................6-13

7-1 Basic External Bus Cycles............................................................................................ 7-6

7-2 Bus State Diagram (Does Not Include Address Pipelining)..........................................7-8

7-3 Ready Logic ...............................................................................................................7-10

7-4 Basic Internal and External Bus Cycles......................................................................7-11

7-5 Nonpipelined Address Read Cycle .............................................................................7-13

7-6 Nonpipelined Address Write Cycles...........................................................................7-15

7-7 Pipelined Address Cycles...........................................................................................7-17

7-8 Interrupt Acknowledge Cycles. ...................................................................................7-21

7-9 Halt Cycle...................................................................................................................7-23

7-10 Basic Refresh Cycle...................................................................................................7-25

7-11 Refresh Cycle Dur ing HOLD/HLDA............................................................................7-26

7-12 BS8 Cycle...................................................................................................................7-28

7-13 LOCK# Signal Dur ing Address Pipelining ..................................................................7-30

7-14 Complete Bus States (Including Pipelined Address)..................................................7-32

8-1 Interrupt Unit Connections................................................................................ ............8-3

8-2 Methods for Changing the Default Interrupt Structure..................................................8-6

8-3 Interrupt Process – Master Request from Non-slave Source.......................................8-9

8-4 Interrupt Process – Slave Request.............................................................................8-10

8-5 Interrupt Process – Master Request from Slave Source............................................8-11

8-6 Port 3 Configuration Register (P3CFG)......................................................................8-15

8-7 Interrupt Configuration Register (INTCFG).. ........................ ........................ ............... 8-16

8-8 Initializatio n Command Word 1 Register (ICW1)........................................................8-17

8-9 Initialization Command Word 2 Register (ICW2)........................................................8-18

8-10 Init ialization Command Word 3 Register (ICW3 – Master).........................................8-19

8-11 Init ialization Command Word 3 Register (ICW3 – Slave) ...........................................8-20

8-12 Init ialization Command Word 4 Register (ICW4)........................................................8-21

8-13 Operati on Command Word 1 (OCW1) .......................................................................8-22

8-14 Operati on Command Word 2 (OCW2) .......................................................................8-23

8-15 Operati on Command Word 3 (OCW3) .......................................................................8-24

8-16 Poll Status Byte (POLL) .............................................................................................8-25

8-17 Inter rupt Acknowledge Cycle......................................................................................8-26

8-18 Spurious Interrupts.....................................................................................................8-28

9-1 Timer/Counter Unit Block Diagram...............................................................................9-2

9-2 Mode 0 – Basic Operation............................................................................................9-6

9-3 Mode 0 – Disabling the Count......................................................................................9-7

9-4 Mode 0 – Writing a New Count.....................................................................................9-7

9-5 Mode 1 – Basic Operation............................................................................................9-8

9-6 Mode 1 – Retriggeri ng the One-shot............................................................................ 9-9

9-7 Mode 1 – Writing a New Count.....................................................................................9-9

xiii

CONTENTS

FIGURES

Figure Page

9-8 Mode 2 – Basic Operation..........................................................................................9-10

9-9 Mode 2 – Disabling the Count....................................................................................9-11

9-10 Mode 2 – Writing a New Count...................................................................................9-11

9-11 Mode 3 – Basic Operation (Even Count)....................................................................9-12

9-12 Mode 3 – Basic Operation ( O dd Count).....................................................................9-13

9-13 Mode 3 – Disabling the Count....................................................................................9-14

9-14 Mode 3 – Writing a New Co unt (With a Trigger).........................................................9-14

9-15 Mode 3 – Writing a New C ount (Without a Trigger)....................................................9-15

9-16 Mode 4 – Basic Operation..........................................................................................9-16

9-17 Mode 4 – Disabling the Count....................................................................................9-17

9-18 Mode 4 – Writing a New Count...................................................................................9-17

9-19 Mode 5 – Basic Operation..........................................................................................9-18

9-20 Mode 5 – Retriggering the Strobe ................... .................... ............ ............ ............ ...9-19

9-21 Mode 5 – Writing a New Count...................................................................................9-19

9-22 Timer Co nfiguration Register (TMRCFG)...................................................................9-21

9-23 Timer/Counter Unit Signal Connections.....................................................................9-22

9-24 Port 3 Configuration Register (P3CFG)................................................ ....... ...............9-23

9-25 Pin Confi gur ation Register (PINCFG).........................................................................9-24

9-26 Timer Co ntrol Register (Control Word Format) .... .................................. .................... 9-26

9-27 Timer

9-28 Timer Co ntrol Register (Counter-latch Format).. ................... .................................. ... 9-29

9-29 Timer

9-30 Timer Co ntrol Register (Read-back Format)... ...........................................................9-31

9-31 Timer

10-1 Watchdog Timer Unit Connections............................................................................. 10-2

10-2 WDT Counter Value Registers (WDTCNTH and WDTCNTL)....................................10-5

10-3 WDT Status Register (WDTSTATUS)........................................................................10-6

10-4 WDT Reload Value Registers (WDTRLDH and WDTRLDL). .....................................10-7

11-1 SIO0 and SI O1 Connections. .....................................................................................11-2

11-2 SIO 11-3 SIO 11-4 SIO 11-5 SIO 11-6 SIO

11-7 Pin Configuration Register (PINCFG).......................................................................11-14

11-8 Port 1 Configuration Register (P1CFG)....................................................................11-15

11-9 Port 2 Configuration Register (P2CFG)....................................................................11-16

11-10 Port 3 Configuration Register (P3CFG)....................................................................11-17

11-11 SIO and SSIO Configuration Register (SIOCFG). ....................................................11-18

11-12 Divisor Lat ch Registers (DLL 11-13 Transmit Buffer Register (TBR 11-14 Receive Buffer Register (RBR 11-15 Serial Line Control Register (LCR 11-16 Serial Line Status Register (LSR

Baud-rate Generator Clock Sources.. .. .. ...........................................................11-4

Transmitter ........................................................................................................11-6

Data Transmission Process Flow......................................................................11-7

Receiver............................................................................................................11-8

Data Reception Process Flow...........................................................................11-9

and DLHn) ...............................................................11-19

)..............................................................................11-20

)...............................................................................11-21

).........................................................................11-22

)...........................................................................11-23

xiv

CONTENTS

FIGURES

Figure Page

11-17 Interrupt Enable Register (IER 11-18 Interrupt ID Register (IIR

11-19 Modem Control Signals – Diagnostic Mode Connections ........................................11-26

11-20 Modem Control Signals – Internal Connections.......................................................11-26

11-21 Modem Control Register (MCR 11-22 Modem Status Register (MSR 11-23 Scratch Pad Register (SCR

12-1 Transmitter and Receiver in Master Mode.................................................................12-2

12-2 Transmitter in Master Mode, Receiver in Slave Mode................................................12-2

12-3 Transmitter in Slave Mode, R eceiver in Master Mode................................................12-3

12-4 Transmitter and Receiver in Slave Mode ...................................................................12-3

12-5 Clock Sources for the Baud-rate Generator...............................................................12-5

12-6 Process Flow for Transmitting Data ...........................................................................12-7

12-7 Transmitter Master Mode, Single Word Transfer (Enabled when Clock is High).......12-8

12-8 Transmitter Master Mode, Single Word Transfer (Enabled when Clock is Low)........12-8

12-9 Process Flow for Receiving Data.............................................................................12-10

12-10 Re ceiver Master Mode, Single Word Transfer .........................................................12-11

12-11 Pin Configuration Register (PINCFG).......................................................................12-13

12-12 SIO and SSIO Configuration Register (SIOCFG). ....................................................12-14

12-13 Clock Prescale Register (CLKPRS) .........................................................................12-15

12-14 SSIO Baud-rate Control Register (SSIOBAUD) ................................... ............ ........12-16

12-15 SSIO B aud-rate Count Down Register (SSIOCTR)..................................................12-17

12-16 SSIO Control 1 Register (SSIOCON1)................................ ............ ................. ........12-19

12-17 SSIO Control 2 Register (SSIOCON2)................................ ............ ................. ........12-20

12-18 SSIO Transmit Holding Buffer (SSIOTBUF).............................................................12-21

12-19 SSIO R eceive Holding Buffer (SSIORBUF) .............................................................12-22

13-1 I/O Port Block Diagram...............................................................................................13-2

13-2 Port Mode Configuration Register (P 13-3 Port Direction Register (P 13-4 Port Data Latch Register (P 13-5 Port Pin State Register (P

14-1 Ch annel Address Comparison Logic..........................................................................14-2

14-2 Determi ning a Channel’s Address Block Size............................................................14-2

14-3 B us Cycle Length Adjustments for Overlapping Regions...........................................14-8

14-4 Pin Configuration Register (PINCFG).......................................................................14-11

14-5 Port 2 Configuration Register (P2CFG)....................................................................14-12

14-6 Chip-select High Address Register (CS 14-7 Chip-select Low Address Register (CS 14-8 Chip-select Hig h Mask Registers (CS 14-9 Chip-select Low Mask Registers (CS

15-1 Refresh Control Unit Connections.. ............................................................................15-2

15-2 Refresh Clock Interval Register (RFSCIR).................................................................15-7

15-3 Refresh Control Register (RFSCON) .........................................................................15-8

15-4 Refresh Base Address Register (RFSBAD) ...............................................................15-9

)..............................................................................11-24

).......................................................................................11-25

).............................................................................11-27

)...............................................................................11-28

)...................................................................................11-29

CFG) ...............................................................13-5

DIR) . ......... ................. ................. ................. ................. ...13-5

LTC),.............................................................................13-6

PIN) .................... ................. ................. ................. ..........13-6

ADH, UCSADH) ....................................... 14-13

ADL, UCSADL) .........................................14-14

MSKH, UCSMSKH).....................................14-15

MSKL, UCSMSKL).......................................14-16

CONTENTS

FIGURES

Figure Page

15-5 Refresh Address Register (RFSADD)......................................................................15-10

16-1 DMA Unit Block Diagram............................................................................................16-2

16-2 DMA Transfer Started by DRQ

16-3 Ch anging the Priority of the DMA Channel and External Bus Requests....................16-6

16-4 Buffer Transfer Ended by an Expired Byte Count ...................................................... 16-7

16-5 Buffer Transfer Ended by the EOP# Input...................... ..... .......................................16-7

16-6 Single Data-transfer Mode with Single Buffer-transfer Mode ...................................16-10

16-7 Single Data-transfer Mode with Autoinitialize Buffer-transfer Mode.........................16-11

16-8 Single Data-transfer Mode with Chaining Buffer-transfer Mode...............................16-12

16-9 Block Data-transfer Mo de with Single Buffer-transfer Mode ....................................16-14

16-10 Block Data-transfer Mo de with Autoinitialize Buffer-tr ansfer Mode. .........................16-15

16-11 Buffer Transfer Suspended by the Deactivation of DRQn........................................16-16

16-12 Demand Data-transfer Mode with Single Buffer-transfer Mode................................16-17

16-13 Demand Data-transfer Mode with Autoinitialize Buffer-transfer Mode. ....................16-18

16-14 Demand Data-transfer Mode with Chaining Buffer-transfer Mode........................... 16-19

16-15 Cascade Mode.........................................................................................................16-21

16-16 Pin Configuration Register (PINCFG).......................................................................16-26

16-17 DMA Configuration Register (DMACFG)..................................................................16-27

16-18 DMA Channel Address and Byte Count Registers...................................................16-28

16-19 DMA Overflow Enable Register (DMAOVFE)...........................................................16-29

16-20 DMA Command 1 Register (DMACMD1).................................................................16-30

16-21 DMA Status Register (DMASTS)..............................................................................16-31

16-22 DMA Command 2 Register (DMACMD2).................................................................16-32

16-23 DMA Mode 1 Register (DMAMOD1) ........................................................................16-33

16-24 DMA Mode 2 Register (DMAMOD2) ........................................................................16-35

16-25 DMA Software R equest Register (DMASRR – write format) . ........................... ........16-36

16-26 DMA Software R equest Register (DMASRR – read format)....................................16-37

16-27 DMA Channel Mask Register (DMAMSK)................................................................16-38

16-28 DMA Group Channel Mask Register (DMAGRPMSK).............................................16-38

16-29 DMA Bus Si ze Register (DMABSR) .........................................................................16-39

16-30 DMA Chaining Register (DMACHR).........................................................................16-40

16-31 DMA Interrupt Enable Register (DMAIEN)...............................................................16-41

16-32 DMA Interrupt Status Register (DMAIS)...................................................................16-42

17-1 Test Logic Unit Connections . .....................................................................................17-2

17-2 TAP Controller (Finit e-State Machine)........................................................................17-6

17-3 Instruction Register (IR)........... ............ .......... ....... ............... ....... .......... ....... ............ ... 1 7-7

17-4 Identification Code Register (IDCODE)......... .. ..... ..... ..... ............................................17-9

17-5 Inter nal and External Timing for Loading the Instruction Register............................17-13

17-6 Inter nal and External Timing for Loading a Data Register........................................ 17-14

B-1 Derivati on of AEN Signal in a Typical PC/AT System............................................. .... B-3

B-2 Derivation of AEN Signal for Intel386™ EX Processor-based Systems...................... B-3

n.................................................................................16-5

xvi

CONTENTS

TABLES

Table Page

2-1 PC-compatible Peripherals...........................................................................................2-3

2-2 Embedded Application-specific Peripherals.................................................................2-4

3-1 Relative Priority of Exceptions and Interrupts .............................................................3-10

4-1 Peripheral Register I/O Address Map in Slot 15 . .......................................................... 4-7

4-2 Peripheral Register Addresses ................................................................................... 4-16

5-1 Signal Pairs on Pins without Multiplexers...................................................................5-20

6-1 Clock and Power Management Register s ....................................................................6-5

6-2 Clock and Power Management Signals........................................................................6-5

7-1 Bus Interface Unit Signals...................................................................... ......................7-2

7-2 Bus Status Definitions ............. ....... ............... ....... .......... ............ .......... ....... ............ .....7-4

7-3 Sequence of Misaligned Bus Transfers........................................................................7-9

8-1 82C59A Master and Slave Interrupt Sources...............................................................8-4

8-2 ICU Registers............................................................................................................. 8-13

9-1 TCU Signals.................................................................................................................9-2

9-2 TCU Registers..............................................................................................................9-3

9-3 Operations Caused by GATE

9-4 Minimum and Maximum Initial Counts........................................................................9-27

9-5 Results of Multiple Read-back Commands Without Reads........................................9-34

10-1 WDT Registers...........................................................................................................10-3

10-2 WDT Signals ......................................................................... ..... ..... ..... ......................10-4

11-1 SIO Signals ................................................................................................................11-3

11-2 Maximum and Minimum Output Baud Rates..............................................................11-5

11-3 Divisor V alues for Common Baud Rates ....................................................................11-5

11-4 Status Signal Priorities and Sources........................................................................11-11

11-5 SIO Re gisters...........................................................................................................11-12

11-6 Access to Multiplexed Registers...............................................................................11-13

12-1 SSIO Signals ..............................................................................................................12-4

12-2 Maximum and Minimum B aud-rate Output Frequencies............................................12-6

12-3 SSIO R egisters .........................................................................................................12-11

13-1 Pin Multiplexing..........................................................................................................13-3

13-2 I/O Port Registers.......................................................................................................13-4

13-3 Control Register Values for I/O Port Pin Configurati ons. ....... ........ ....... ....... ..... ....... ... 1 3-4

13-4 Pin Reset Status.........................................................................................................13-8

14-1 CSU Signals ...............................................................................................................14-9

14-2 CSU Registers................................................................ ............................................14-9

15-1 Refresh Control Unit Signals.................................................................. ....................15-3

15-2 Refresh Control Unit Registers......................................................................... ..... .....15-6

16-1 DMA Signals...............................................................................................................16-3

16-2 DMA Registers.........................................................................................................16-23

16-3 DMA Software Commands.......................................................................................16-43

17-1 T est Access Port Dedicated Pins...............................................................................17-3

17-2 TAP Controller State Descriptions..............................................................................17-4

17-3 Example TAP Controller State Selections ..................................................................1 7-5

17-4 Test-logic Unit Instructions.........................................................................................17-7

n.....................................................................................9-5

xvii

CONTENTS

TABLES

Table Page

17-5 Boundary-scan Register Bit Assignments ................................................................17-10

A-1 Signal Description Abbreviations................................................................................. A-1

A-2 Signal Descriptions...................................................................................................... A-2

A-3 Pin St ate Abbreviations...............................................................................................A-7

A-4 Pin States After Reset and During Idle, Powerdown, and Hold...................................A-8

xviii

CHAPT ER 1

GUIDE TO THIS MANUAL

This manual descri bes the embedded Intel386™ EX micr oprocessor. It is intended for use by hardware designers fam iliar wi t h the principles of microprocessors and wi th t he Int el3 86 arc hitecture.

1.1 MANUAL CONTENTS

This manual contains 17 chapters and 2 appendixes, a glossary, and an index. This chapter, Chap-

ter 1, pr ovides an overview of the manual. This section summarizes the contents of the remaining

chapters and appendixes. The remainder of this chapter describes notational conventions and special terminology used throughout the manual and provides references to related documentation.

Chapter 2 — Architectural Over view — desc ribes the de vice fea ture s and some p otential ap plicatio ns .

Chapter 3 — Core Overview — describes the differences between this device and the Intel386 SX processor core and discusses Intel’s System M anagement Mode (SMM ).

Chapter 4 — System Register Organization — describes the organization of the system registers, the I/O address space, address decoding, an d addressing modes.

Chapter 5 — Device Configuration — explains how to configure the device for various applications.

Chapter 6 — Clock and Power Management Unit — describes the clock generation circuitry, power manageme nt modes, and system rese t logic.

Chapter 7 — Bus Interface Unit — describes the bus interface logic, bus states, bus cycles, and instruction pipelining.

Chapter 8 — Interrupt Control Unit — describes the interrupt sources and priority options and explains how to program the interrupt control unit .

Chapter 9 — Timer/Counter Unit — describes the timer/counters and their available count formats and operating modes.

Chapter 10 — Watchdog Timer Unit — explains how to use the watchdog timer unit as a software watchdog, bus monitor, or general-purpose timer.

1-1

GUIDE TO THIS MANUAL

Chapter 11 — Asynchronous Serial I/O (SIO) Unit — explains how to use the universal asynchronous receiver/transmitters (UA RTs) to transmit and receive serial data.

Chapter 12 — Synchronous Se rial I/O (SSIO ) Unit — explains how to transmit and receive data synchronously.

Chapter 13 — Input/Output Ports — describes the general-pur pose I/O ports and explains how to configure each pin to serve either as an I/O pin or as a pin controlled by an internal peripheral.

Chapter 14 — Chip-select Unit — explains how to use the chip-select channels to access various external memory and I/O devices.

Chapter 15 — Refresh Contr ol Unit — describes how the refre sh c ontr ol uni t genera te s peri odic refresh requests and refresh addresses to simplify the interface to dynamic memory devices.

Chapter 16 — DMA Controller — describes how the enhanced direct memory access controller allows internal and external devices to t ransfer data directly to and from the system and explains how bus control is arbitrat ed.

Chapter 17 — JTAG Test-logic Unit — describe s the indepen dent test -logic unit and explain s how to test the device logic and board-level connections.

Appendix A — Signal Descriptions — describes the device pins and signals and lists pin states after a system reset and during powerdown, idle, and hold.

Appendix B — Compatibi lity with PC/ AT * Arc hite ctur e — describes t he ways in which the device is compatible with the standard PC/AT architecture and the ways in which it departs from the standard.

Glossary — define s terms with spec ial me aning used th roughout this manual.

Index — lists key topics with page number references.

1.2 N O TAT IONAL CONV E NTI ONS

The following notations are used throughout this manual. # The pound symbol (#) appended to a signal name indicates that the

signal is active low.

italics Italics identify variables and introduce new terminology. The context

in which italics are used distinguishes between the two possible meanings. Variables must be replaced with correct values.

1-2

GUIDE TO THIS MANUAL

Instructions Instruction mnem onics are shown in uppe r case to av oid confusion.

You may use ei ther upper case or lower case.

Numbers Hexadecimal numbers are represented by a string of hexadecimal

digits followed by the character H. A zero prefix is added to numbers that begin with A through F. (For example, FF is shown as 0FFH .) Decimal and binary numbers are represented by their customary notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is added for clarity.)

Units of Measur e The following abbreviations are used to represent units of measure:

A amps, ampere s Kbyte kilobytes KΩ kilo-ohms mA milliamps, milliamperes Mbyte megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds pF picofarads W watts V volts

µA microamps, microam peres µF microfara ds µs microseconds µW microwat t s

significant bit a nd 7 (or 15) is the most-significa nt bit.

lowercase, it alic chara cter, it re presents more than one register. For example, PnCFG represents three registers: P1CFG, P2CFG, and P3CFG.

Signal Names Signal names are shown in upper case. When several signals share a

common name, an individual signal is represented by the signal name followed by a number, while the group is represented by the signal name followed by a variable (n). For example, the lower c hip-select signals are named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#. A pound symbol (#) appended to a signal name identifies an active-l ow signal. Port pins are represe nted by the port abbreviation, a period, and the pin number (e.g., P1.0, P1.1).

1-3

GUIDE TO THIS MANUAL

1.3 SPECIAL TERMINOLOGY

The following terms have special meanings in this manual. Assert and De assert The terms assert and deassert refer to the act of making a signal

active (enabled) and inactive (disabled), respectively. The active polarity (high/low) is defined by the signal name . Active-l ow signal s are designated by a pound symbol (#) suffix; active-high signals have no suffix. To assert RD# is to drive it low; to assert ALE is to drive it high; to deassert RD# is to drive it high; to deassert ALE is to drive it low.

DOS Address Integrated peripherals that are compati ble with PC/AT system archi-

tecture can be mapped into DOS (or PC/AT) address es 0H–03FFH. In this manual, the terms DOS address and PC/AT address are synonymous.

Expanded Address All peripheral registers reside at addresses 0F000H–0F8FFH.

PC/AT-compatible integrated peripherals can also be mapped into DOS (or PC/AT) address space (0H–03FFH).

PC/AT Addr ess Integrated peripherals tha t are compatible with PC /AT system arc hi-

tecture can be mapped into PC/ AT (or DOS) addresses 0H –03FFH. In this manual, the terms DOS address and PC/AT address are synonymous.

Reserved Bits Certain re gist er bit s a re desc ribed as reserved bits. These bits are not

used in this device, but they may be use d in future implement ations. Follow these guidelines to ensure compa tibil ity with f uture devic es:

• Avoid any software dependence on the state of undefined

• Use a rea d-m o dify-write sequence to load registers.

• M ask u ndefined bit s when testing the val ues of defined bits.

• Do not depend on the state of undefined bits when storing

undefined bits to memory or to another register.

• Do not depend on the ability to retain information written to

undefined bits.

Set and Clear The terms set and clear refer to the value of a bit or the act of giving

it a value. If a bit is set, its value is “1”; setting a bit gives it a “1” value . If a bit is clear, its val ue is “0”; clearin g a bit gives it a “0” value.

1-4

GUIDE TO THIS MANUAL

Set and Reset The terms set and reset refe r to the act of applying a s ignal to a pi n.

Setting a pin gives it a logic high value; resetting a pin gives it a logic

low value.

1.4 RELATED DOCUMENTS

The following documents conta in addit ional informa tio n that is useful in designin g systems that incorporate the Intel386 EX micropr ocessor. To order d ocuments, please c all Intel L iterature Fulfillment (1-800-548-4725 in the U.S. and Canada; +44(0) 793-431155 in Europe).

Intel386™ EX Embedded Microprocessor data sheet Order Number 272420

Intel386™ SX Microprocessor data sheet Order Number 240187

Intel386™ SX Microprocessor Programmer’s Ref erence Manual Order Number 240331

Intel386™ SX Microprocessor Hardware Reference Manual Order Number 240332

Development Tools Order Number 272326

Buyer’s Guide for the Intel386™ Embedded Proce ssor Fami ly Order Number 272520

Packaging Order Number 240800

1-5

GUIDE TO THIS MANUAL

1.5 CUSTOMER SERVICE

This section provides telephone numbers and describes various cust omer servi ces.

• Customer Support (U.S. and Canada) 800-628-8686

• Customer Training (U.S. and Canada) 800-234-8806

• Literature Fulfillment

— 800-468-8118 (U.S. and Canada) — +44(0)793-431155 (Europe)

• FaxBack* Service

— 800-628-2283 (U.S. and Canada) — +44(0)793-496646 (Europe) — 916-356-3105 (worldwide)

• Applicatio n Bull etin Bo a rd Syste m

— 916-356-3600 (worldwide, up to 14.4-Kbaud line) — 916-356-7209 (worldwide, dedicated 2400-baud line) — +44(0)793-496340 (Europe)

Intel provides 24-hour automat ed technical support through the use of our FaxBack service and our centralized Intel Application Bulletin Board System (BBS). The FaxBack service is a simpleto-use information system that lets you order technical documents by phone for immediate delivery to your fax machine. The BBS is a centralized computer bulletin board system that provides updated application-specific information about Intel products.

Intel also provides the Embedded Applications Journal, a quarterly technical publication with ar- ticles on microcontroller appli cati ons, errata , support tools, and other useful information. To order the journal, call the FaxBack service and order information packet #1 (the Embedded Applications Journal subscripti on form).

1.5.1 How to Use Intel's FaxBack Service

Think of the FaxB ac k servi ce as a lib rary of te chni cal doc um ent s that y ou can acce ss wi th your phone. Just dial the telephone number (see page 1-6) and respond to the system prompts. After you select a document, the system sends a copy to your fax machine.

Each document is assigned an order number and is listed in a subject catalog. First -time users should order the appropriate subject catalogs to get a complete listing of document order numbers.

1-6

GUIDE TO THIS MANUAL

The following catal ogs and information packets are available:

1. Microcontroller, Flash, and iPLD catalog

2. Developme nt tool cata log

3. System ca talo g

4. DVI and multime dia catalog

5. BBS catalog

6. Micr oproc essor and peripheral catalo g

7. Quality and reliability catalog

8. Technic al questionnaire

1.5.2 How to Use Intel's Application BBS

The Application B ullet in Board Syste m (BBS) provides c ent ralized a cces s to i nformation, s oftware drivers, firmware upgrades, and revised software. Any user with a modem and computer can access the BBS. Use the following modem settings.

• 14400, N, 8, 1

If your modem does not support 14.4K baud, the system provides aut o configuration support for 1200- through 14.4K-baud modems.

To access the BB S, just dial the telephone number (see page 1-6) and resp ond t o the syst em prompts. During yo ur first session, t he syste m asks you to register with the system operator b y entering your name and location. The system operator will then set up your ac cess account within 24 hours. At that time, you can access the files on the BBS. For a l isting of files, call the FaxBack service and order catalog #6 (the BBS catalog).

If you encounter any diffi culty accessi ng our high-speed m odem, try our dedicated 2400-baud modem (see pag e 1- 6 ). Use the following modem settings.

• 2400 baud, N, 8, 1

1-7

GUIDE TO THIS MANUAL

1.5.3 How to Find the Latest ApBUILDER Files and Hypertext Manuals and Data Sheets on the BBS

The latest ApBUILDER files and hypertext manuals and data sheets are availabl e first from the BBS. To access the files:

1. Select [F] from the BBS Main menu.

2. Select [L] from the Intel Apps Files menu.

3. The BBS displa ys the list of all area levels and prom pt s for the area num be r.

4. Select [25] to choose the ApBUILDER / Hypertext area.

5. Area l evel 25 has four sublevels: (1) General, (2) 196 Files, (3) 186 Files, and (4) 8051 Files.

6. Select [ 1] to find the latest ApBUILDER files or the number of the appropriate productfamily sublevel to find the hype rte xt manual s and data sheet s.

7. Enter the file number to tag the files you wish to download. The BBS displays the approximate download time for tagged files.

1-8

CHAPT ER 2

ARCHITECTURAL OVERV IEW

The Intel386™ EX embedded microprocessor (Figure 2-1) is based on the static Intel386 SX pro-

cessor. This highly integrated device retains those personal computer functions that are useful in embedded applications and integrates peripherals that are typically needed in embedded systems. The Intel386 EX p rocessor pr ovides a PC -compatible deve lopment platform i n a device that is optimized for embedded applicat ions. Its integra ted periphera ls an d power management opti on s make the Intel386 EX processor ide al for portable system s.

The integrated peripherals of the Intel386 EX are compatible with the standard desktop PC. This allows existing PC software, including most of the industry’s leading desktop and embedded operating systems, to be easi ly imple mented on a n Intel386 EX-bas ed platf orm. The Intel386 E X

processor includes a royalty-free license for the real-time Intel iRMX Using PC-compatible periphe rals also allows for the de velopment a n d debugging of applicatio n software on a standard PC platform.

Typical applications usi ng the Intel386 EX processor inc lude automated m anufacturing equip-

ment, cellular telephones, telecommunications equipment, fax machines, hand-held data loggers,

high-precision industrial flow controllers, i nteractive television, medi cal equipment, modems,

and smart copiers.

2.1 CORE

EMB Operating System.

The Intel386 EX proces sor contains a modular, full y static Intel386 SX CPU and inc orporates

System Management Mode (SMM) for enhanced power management. The Intel386 EX processor

has a 16-bit da ta bus and a 26-bit address bus, supporting up to 64 Mbytes of memory address

space and 64 Kbytes of I/O address space. The CPU performance of the Intel386 EX processor

closely reflects the Intel386 SX CPU performance at the same speeds.

Chapter 3, “Core Overview,” describes differences between this device and the Intel386 SX CPU.

Please refer to the Intel386™ SX Microprocessor Programmer’s Reference Manual (order num-

ber 240331) for applications and system programming information; descriptions of protected, re-

al, and virtual-8086 modes; and details on the instruction set.

2-1

ARCHITECTURAL OVERVIEW

DMA

Controller

and

Bus Arbiter

Unit



Memory Address

CPU

Data

Bus Interface

Memory Data

Address

Data

Unit

Peripheral Address

Address

Peripheral Data

Chip-select

Unit

JTAG-compliant

Test-logic Unit



Clock and Power

Management

Unit

DRAM Refresh

Control Unit

2-2

Watchdog Timer

Unit

Asynchronous Serial I/O

and Synchronous

Serial I/O Units

Interrupt

Control

Unit

Timer/Counter

Unit

Figure 2-1. Intel386™ EX Processor Block Diagram

A2757-02

ARCHITECTURAL OVERVIEW

2.2 INTEGRATED PERIPHERALS

The Intel386 EX processor integrates both PC-compatible peripherals (Table 2-1) and peripherals

that are specific to embe d ded applic ati ons (Table 2-2).

Table 2-1. PC-compatibl e Peri p hera ls

Name Description

Interrupt Control Uni t (ICU)

Timer Counter Uni t (TCU)

Asynchronous Serial I/O (SIO) Unit

Direct Memory Access (DMA) Controller

Consists of two 8259A programmable interr upt contro llers (PIC s) configure d as master and slave. You may cascade up to four external 8259A PICs to expand the external interrupt lines to 36. Refer to Chapter 8, “Interrupt Control Unit.”

Provides three independent 16-bit down counters. The programmable TCU is functionally equivalent to an 82C54 counter/timer with enhancements to allow remapping of peripheral addresses and interrupt assignments. Refer to Chapter 9,

“Timer/Counter Unit.”

Features two independent universal asynchr onous recei ver and transmit ter s (UARTs) which are functio nall y equi vale nt to Natio nal Sem icon ductor’s NS16450. Each channel contains a baud-rate generator, transmitter, receiver, and modem control unit. All four of the serial channel interrupts may be connected to the ICU or two of the interrupts may be connected to the DMA controller. Refer to Chapter 11, “Asynchronous Serial I/O

Unit.”

Transfers internal or external data between any combination of memory and I/O devices for the entire 26-b it addre s s bus. The two ind e pend en t chann el s opera te in 16- or 8-b it bus mode. Buffer chaining allows data to be transferred into noncontiguous memory buffers. DMAs can be tied to any o f the serial devices to support high data rates, minimizing processor interruptions. Provides a special two-cycle mode that uses only one channel for memory-to -m emo r y transfe r s. Bus arbitra ti on logic resolve s prior ity conflicts betwee n the DMA chan nels, the refresh contro l unit, and an exte rna l bus master. SIO and SSIO interr upt s can be connect ed to DMA for high- spee d tran sfer s. Backward compatible with 8237A. Refer to Chapter 16, “DMA Controller.”

2-3

ARCHITECTURAL OVERVIEW

Table 2-2. Embedded Application-specific Peripherals

Name Description

Clock and Power Management Unit

Watchdog Timer (WDT)

Synchronous Serial I/O (SSIO) unit

Parallel I/O Ports

Chip Select Unit (CSU)

Refresh Control Uni t (RCU)

JTAG Testlogi c Un i t

An external clock source provides the input frequency. The clock and power managem e nt un it ge ne rat es sep arate internal clock signals for core an d peripherals (half the input frequency), divides the internal clock by two for baud clock inputs to the SIO and SSIO, and divides the internal clock by a programmable divisor to provide a prescaled clock signal (various frequencies) for the TCU and SSIO. Power management provides idle and powerdown modes (idle stops the CPU clock but leaves the peripheral clocks running; powerdown stops both CPU and peripheral clocks). Refer to Chapter 6,

“Clock and Power Management Unit.”

When enabled, the WDT functions as a general purpose 32-bit timer, a software timer, or a bus monitor. Refer to Chapter 10, “Watchdog Time r Unit.”

Provides simultaneous, bidire ctio nal serial I/O in excess of 5 Mbps. Consists of a transmit chan nel, a receive chann e l, and a baud rate genera to r. Built-in protocols are not included, as these can be emulated using the CPU. The refresh control unit (RCU) is provided for applications that use DRAMs with a simple EPLD-based DRAM controller or PSRAMs that do not need a separate controller. SSIO interrupts can be connected to the DMA unit for high-speed transfers. Refer to Chapter 12, “Synchronous Serial I/O

Unit.”

Three I/O ports facilitate data transfer between the processor and surrounding system circuitry. The Intel386 EX processor is unique in that several functions are multiplexed with each other or with parallel I/O ports. This ensures maximum use of available pins and maintains a small package. Individually programmable for peripheral or I/O function. Refer to Chapter 13, “Input/Output Ports.”

Programmable, eight-chann el CSU allows direct access to up to eight devices. Each channel can operate in 16- or 8-bit bus mode and can generate up to 31 wait states. The CSU can interface with the fastest memory or the slowest peripheral device. The minimum address block for memory address-configured channels is 2 Kbytes. The size of these address blocks can be increased by multiples of 2 Kbytes for memory addresses and by multiples of 2 bytes for I/O addresses. Supports SMM memor y addressing and provides ready generation and programmable wait states. Refer to

Chapter 14, “Chip-sel ect Unit. ”

Provides a means to generate periodic refresh reque sts and refresh addresses. Consists of a programmable interval ti mer unit, a c ontrol unit, and an address ge neration unit. Bus arbitrati on log ic ensure s that refr esh req uest s have the high est prio rit y. Ref er to Chapter 15, “Refresh Control Unit.”

The test-logic unit simplifies board-level testing. Consists of a test access port and a boundary-scan register. Fully compliant with Standard 1149.1–1990,

Test Access Port and Boundary-Scan Architecture

1149.1a–1993. Refer to Chapter 17, “JTAG Test-logic Unit.”

and its supplement, Standar d

IEEE Standard

2-4

ARCHITECTURAL OVERVIEW

2.3 PC COMPATI BIL ITY

Of primary concern to system designers is the ability for the target system to run readily available

software developed for the personal comput er with out modification. The Intel386 EX processor

provides that capability, assuming all the necessary hardware subsystems are available in the tar-

get system. Some applications may require additional functionality from one or more companion

chips and all require a custom BIOS to supply initialization and driver routines for on-chip devic-

es.

2.3.1 I/O Consideration s

The Intel386 EX processor departs from the ISA standard as follows:

• ISA bus signals are not supplied, but t he SX bus is maintained t o allow the ISA bus signals

to be recreated.

• A video controller and keyboard controller a re not provided, but their I/O addresses are

reserved to allow them to be added externally.

• The I/O address space in a PC configuration is limited to 1 Kbyte. The Intel386 EX

processor uses a special address space extension to provide more register space (64 Kbytes) for the added peripherals. Four addressing modes allow you to select the level of PC compatibility you want.

• IRQ10, IRQ11, IRQ12, and IRQ15 are not availa ble for external interrupt connec tio ns.

2.3.2 PC/AT Compatibility

Setting bits in the p ort 92 configurat ion regist er provide s bac kward com pat ibility for 8 086 soft-

ware by forcing address line A20 to zero, which emulates wraparound across the 1 Mbyte address

boundary. FastCPUReset along wi th user-defined soft ware may be use d to reconstruc t some of

the CPU-only reset modes used in 80286-based PC systems.

2.3.3 Enhanced DMA Controller

The enhanced DMA cont roller was selected to mainta in PC compatibility whil e providing in-

creased perform ance. The ISA-standard P C/AT architecture uses two c ascaded 8237A DMA

controllers, provides seven channels, is limited to 16-bit addressing, and requires two DMA chan-

nels for two-cycle memory-to-me mory transfers.

2-5

ARCHITECTURAL OVERVIEW

The enhanced DMA provides tw o channels, uses the same 8-bit registers as the 8237A, and is

programmed through 8-bit registers. It uses 24-bit byt e-count registers to support larger data

blocks, but these re gist ers can be c o nfigu red to look like an 8237A with page registe rs. The en-

hanced DMA supports all of the 8237A’s opera ting modes except one: it d oes not support the

command register bits that control the two-cycle transfers, compressed timing, and

DREQ/DACK signal polarity. Table 2-1 on page 2-3 provides a brief description and Chapter 16,

“DMA Controller” provides details about the enhanced DMA co ntroller.

2.3.4 SIO Chann els

The SIO channels are connected to the equivalent of a local bus, not the ISA bus. In addition, the

SIO channels have fixed addresses, rather than the programmable addresses found in PCs. If an-

other device resides at the SIO c hannel ’s fixed a ddre ss, a cust omi zed BIOS c an det ect it, rema p

the SIO channel into the expanded I/O space, and write the new address into the BIOS data table

that describes the I/O map.

2-6

CHAPT ER 3

CORE OVERV IE W

The Intel386™ EX processor core is based upon the Intel386 SX processor. As such, it functions

exactly like the Intel386 SX processor except for the following enhancements and changes in per-

formance:

• It is fully static. The clocks can be stopped at any time without the loss of data.

• Commonly used DOS and non-DOS peripherals have been added.

• The processor identi fic ation stored in the mi crocode is 2309H.

• Intel’s System Manageme nt Mod e (SMM ) has been impl em ente d. SMM :

— provides an inte r rupt in put pin (SMI # ) and a status outp ut pin (SMIAC T#). — provides an instructio n for exiting SMM (RSM). — requires a special memory partition (SMRAM).

• Two additional address lines have been added for a total of 26 (64 Mbytes of memory

address space; 64 Kbytes of I/O address space).

• An asynchronous FLT# signal has been added (when applied, the out put and directional

pins are floated)

• Four special addressing modes have been provided for various levels of DOS compatibility.

• An interrupt control unit has been added (i .e., the INTR pin o f the Intel386 SX process or is

not directly available.)

• The following instruct ions require one to four additional clock cycles on the Intel386 EX

processor than on the Intel386 SX processor: IN, INS, REP INS, OUT, OUTS, REP OUTS, POPA, HLT, MOV CR0,src.

• Maskable interrupts and NMI have two additional clock cycles of interrupt latency.

For the wide ph ysical address spa ce requirement of 32-bit embedded applications, the Intel386

EX processor is given two additional address pi ns (A24, A 25). The 16 Mbyte physical address

space of the Intel386 SX processor is expanded to 64 Mbytes in the Intel386 EX processor.

The Intel386 EX processor has three low power featu res. First is the SMM (system management

mode) function, which controls syst em power consumpt ion b y using a special inte rr upt (SMI #).

Second is idle mode and third is powerdown mode. (See Chapt er 6, “Cloc k and Power Manage -

ment Unit,” for a description of these two modes.) In addition to these modes, the exter nal clock

(CLK2) can be stopped at any time.

3-1

CORE OVERVIEW

Another enhanced feature is internal support of the A20 Mask function, which forces the A20 sig-

nal to a low level in order to maintain compatibility with old wraparound software for DOS or

Intel 286 microprocessors.

3.1 SYSTEM MANAGEMENT MODE OVERVIEW

The Intel386 EX processor provides a mechanism for system management with a combination of

hardware and CPU microcode enhancements. An externally generated system management inter-

rupt (SMI#) allows the execution of system-wide routines that are independent and transparent to

the operating system. The system management mode (SMM) architectural extensions to the

Intel386 CPU consists of the following elements:

• an interrupt input pin (SMI#) to invoke SMM.

• an output pin (SMIACT#) to identify execution state

• a new instruction (RSM), executa ble from SMM only

For low power systems, the primary function of SMM is to provide a transparent means for power

management . The SMM implem entation is similar to tha t of the Intel386 SL CPU, but the SM-

RAM relocation isn’t supported.

3.1.1 SMM Hardware Interface

The Intel386 EX processor provides two pins for use in SMM systems, SMI# and SMIACT#.

3.1.1.1 SMI# (System Management Interrupt Input)

The SMI# input signal is used to invoke syst e m managem ent mo de. SMI# is a fallin g edge t rig-

gered signal that force s the core into SMM at the completion of the current instruction. SMI# is

similar to NMI in the following ways:

• SMI# is not maskable.

• SMI# is recognized on an instruction boundary and at each iteration for repeat string

instructions.

• SMI# does not break LOCK#ed bus cycles.

• SMI# cannot interrupt currently executi ng SMM code. The processor will latch the falling

edge of a pending SMI# signal while the CPU is executing an existing SMI# (this allows one level of buffering). The nested SMI# is not recognize d until afte r the e xecution of a resume instruction (RSM).

• SMI# will bring the processor out of idle or powerdown mode.

3-2

CORE OVERVIEW

3.1.1.2 SMIACT# (SMM Active Output)

This output i ndic at es tha t t he processor is operatin g i n syst em management mode. It i s ass erte d

when the CPU initiates the SMM sequence and remains active (low) until the processor executes

the RSM instruction to leave SMM. Before SMIACT# is asserted, the CPU waits until the end of

instruction boundary. S MIACT# is used to establish a new memory map for SMM operation. The

processor supports this function b y an extension to the interna l chip-sel ec t unit. In additio n, this

pin can be used by external logic to qualify RESET and SMI#. SMIACT# never transitions during

a pipelined bus cycle.

3.1.2 SMI# Interrup t

When the CPU recognizes SMI# on an instruction boundary, it waits for all write cycles to com-

plete (including those pending external ly) and asserts the SMIACT# pin. The processor then

saves its register state to SM R AM space and begi ns to e xecute the SMM handler. T he R SM in-

struction restores the regist ers, deasserts the SMIAC T# pin, and returns to the user program.

Upon entering SMM , the pr oces sor's PE, MP, EM, TS, HS an d PG bits in CR0 are cleared:

CR0 Bit Mnemonic Description Function

0 PE Protectio n Ena bl e 1 = prot ectio n enab le d

1 MP Math Coprocessor Pre sent 1 = coprocesso r presen t

2 EM Emulate Coprocessor 1 = coprocessor opcodes generate a fault

3 TS Task Switched 1 = coprocessor ESC opcode causes fault

16 HS Halt 1 = HALT is executed

31 PG Paging Enab le 1 = pagi ng enabl ed

0 = protection disabled

0 = coprocessor not present

0 = coprocessor opcodes execute

0 = coprocessor ESC opcode does not cause fault

0 = HALT is not executed

0 = pa ging dis abled

Debug register DR7 is also cleared, except for bits 11– 15.

Internally, a descri ptor register (invisibl e to the programme r) is associated with ea ch program-

mer-visible segment register. Each descriptor register holds a 32-bit segment base address, a 32-

bit segment limit, and other necessary segment attribute s. When a selector val ue is loaded into a

segment regist er, t he assoc iated de scri ptor re gist er i s automa t ical ly u pdated wi th the c o rrect in-

formation. In real mode, only the base address is updated directly (by shifting the selec tor value

3-3

CORE OVERVIEW

four bits to the l eft), si nce the segm ent m axi mum lim it a nd att ribute s are fixed in R ea l mode . I n

Protected mode, the base address, the limit, an d the attrib utes are all updated per t he conte nts of

the segment descriptor indexed by the selector. After saving the CPU state, the SMM State Save

sequence sets the appropriate bits in the segment descriptor, placing the c ore i n an e n viro nment

similar to Real mode, without the 64 Kbyte limit checking.

In SMM, the CPU executes in a real-like mode. In this mode, the CPU can access (read and write)

any location within the 4 Gbyte logical address space. The p hysical address spac e is 64 Mbytes.

The CPU can also perform a jump and a call anywhere within a 1 Mbyte boundary address space.

In SMM, the processor generates addresses as it does in real mode; however, there is no 64 Kbyte

limit. The value loaded into the selector register is shifted to the left four bits and moved into its

corresponding descriptor base, the n added to the e ffective a ddre ss. T he effect ive address can be

generated indirectly, using a 32-bit register. However, only 16 bits of EIP are pushed onto the

stack during calls, exceptions and INTR servi ces. Therefore, w hen returning from calls, excep-

tions or INTRs, the upper 16 bits of the 32-bit EIP will be zero. In an SMI# handler, the EIP

should not be over the 64 Kbyte boundary. The 16-bit CS allows addressing within a 1 Mbyte

boundary.

Instructions that explicitly access the stack (e.g., MOV instructions) can access the entire 4

Gbytes of logical address space by using a 32-bit address size prefix. However, instructions that

implicitly access t he stack (e.g., POP, PUSH, CALL, and RET) sti ll have the 64 Kbytes limi t,

since the B bit of the data segment descript or is cleare d in the SMM .

After SMI# is recognized and the processor state is saved, the processor state is initialized to the

following default values.

General Purpose Register Unpredictable EFLAGS 00000002H EIP 00008000 H CS Selector 3000H DS,ES,FS,GS ,SS Selectors 0000H CS Descriptor Base 00030000H DS,ES,FS,GS,SS Descriptor Base 00000000H CS,DS,ES,FS,GS,SS Descriptor Limit FFFFFH DS,ES,FS,GS ,SS Attri bute s 16-bit CR0 Bits 0, 1, 2, 3, 16, 31 cleared DR6 Unpredictable DR7 Bits 0–10,16–31 cleared

3-4

CORE OVERVIEW

When a valid SMI# is recognized on an inst ruction execution b oundary, the CPU immedi ately

begins execution of the SMM State Sa ve se quence , assert ing SM IAC T# low (unle ss the C PU is

in a shutdown condition). The CPU then starts SMI# handler execution. An SMI# can’t interrupt

a CPU shutdown. The SMI# handler always starts at 38000H. When there are multiple causes of

SMI#s, only one SMI# is generated, thereby ens uring tha t SMI#s are not nested.

3.1.3 SMRAM

The SMM architecture requires that a partition of memory be set aside for the SMM driver. This

is called the SMRAM. Several requirements must be met by the system:

• The address range of this partition must be, as a minimum, from 038000H to 03FFFFH (32

Kbytes).

• The address range from 03FE0 0H to 03FFFFH (512 bytes) is reserved for the CPU and

must be RAM.

• The SMM handler must start executi on at locatio n 038000H. It is not relocatable.

• During normal operation, the SMRAM should only be accessible if the system is in SMM.

• During system initia lizatio n it mus t be possi ble to a cces s the SMR AM in order t o init ialize

it and possibly to install the SMM driver. This must obviously be done outside of the SMM.

• If the SMRAM overlays other memory in the system, then address decoding and chip

enables must allow the SMM driver to access the shadowed memory locations while in SMM.

• The SMRAM should not be access ibl e to alternate bus masters such as DMA.

These requirements are made to ensure that the SMM remains transparent to non-SMM code and

to maintain uniformity across the various Intel processors that support this mode. Note that it is

possible for the designer of an embedded system to place the SMM driver code in read-only stor-

age, as long as the address space between 03FE00H and 03FF FFH is writabl e.

The Intel386 EX processor doe s not support SMRAM relocation. Bit 17 of the SMM Revision

Identifier (se e “SM RAM State Dump Area” on page 3-8) indicates whether the processor sup-

ports the relocation of SMRAM. If this bit is set (1), the processor supports SMRAM relocation.

If this bit is cleared (0), then the processor does not support SMRAM relocation. Since this device

doesn't support S MRA M rel oca ti o n, bit 17 of t he SMM Revision Ide nti fier is clea red. The SM-

RAM address space is fixed from 38000H to 3FFFFH.

3-5

CORE OVERVIEW

3.1.4 Chip-select Uni t Suppo rt for SM RAM

The internal chip-sele ct unit (CSU) has been ext ende d to support the SMRAM by utilizing a re-

served bit (bit 10) in each Low Address and Low Mask register. The CSU ac ts on these bits ex-

actly as if they represented another address line. Instead of being associated with an actual

address line, however, these bits are associated with an internally generated signal, ASMM.

ASMM has the Boolean equation:

ASMM = SMMACT AND NOT(iHLDA)

ASMM is asserted (high true) if the processor is in SMM a nd the core has co ntrol of the system

bus (core hold acknowled ge signal, iHLDA, is not active). ASMM is, in effect , an extra addres s

line into the CSU that is set (1) if the core has control of the system bus and it is in SMM.

To see how this extension of the CSU supports the SMRAM requirements, consider an embedded

system which has 1 Mbyte of 16-bit wide EPROM in the region 03F00000H to 03FFFFFFH and

1 Mbyte of 16-bit wide RAM in the regi on 00000000H to 000FFFFFH. A single 32 Kbyte by 8

RAM in the region 00038000H to 000 3FFFFH is added to su pport SMM. The chip selects for this

system during normal operation would be programmed as follows:

REGION CA25:11 CM25:11 CASMM CMSMM BS16

EPROM 11 1111 0000 0000 0 00 0000 1111 1111 1 0 0 1 RAM 00 0000 0000 0000 0 00 0000 111 1 11 11 1 0 0 1 SMRAM 00 0000 001 1 10 00 0 00 0000 000 0 01 11 1 1 0 0

Each row in the above table repres ents a region of memory and its associat ed chip select logic.

During initialization, these same chip selects could be programmed as follows:

REGION CA25:11 CM25:11 CASMM CMSMM BS16

EPROM 11 1111 0000 0000 0 00 0000 1111 1111 1 0 0 1 RAM 00 0000 0000 0000 0 00 0000 1111 1111 1 0 0 1 SMRAM 00 0001 0011 1000 0 00 0000 0000 0111 1 0 0 0

3-6

CORE OVERVIEW

Only the SMRAM row has been changed; the SMRAM chip select has been redirected to the re-

gion 013F800H to 013FFFFH and the CASMM bit has been cleared. This allows the initialization

software to set up the SMRAM wi thout enteri ng the SMM. Note t hat the external design of the

system will have to guarantee that an SMI# cannot occur while the SMRAM is being initialized.

If the SMM driver ne eds t o acc ess the memory sha dowe d un der the SM RAM , t hen the c hip se -

lects can be reconfigured as follows:

REGION CA25:11 CM25:11 CASMM CMSMM BS16

EPROM 11 1111 0000 0000 0 00 0000 1111 1111 1 0 0 1 RAM 00 0001 0000 0000 0 00 0000 111 1 11 11 1 0 1 1 SMRAM 00 0000 001 1 10 00 0 00 0000 000 0 01 11 1 1 0 0

This leaves the SMRAM in place but moves the normal RAM into the partition 0100000H to

01FFFFFH. The CASMM bit is masked so that the RAM is selected independent of SMM.

3.1.5 I/O Restart

Bit 16 of the SMM Revision Ide ntifie r is set (1) indicating that this device does support the I/O

trap restart extension to the SM M base archi tecture.

The I/O trap rest art slot provides the S MM handler the opt ion of automat ically re-exec utin g an

interrupted I/O instruct ion using the RSM instruction. When the RSM instruct ion is executed

with the I/O trap restart slot set to a value of 0FFH, the CPU will automatically re-execute the I/O

instruction that the SMI# has trap ped. If the slot conta ins 00H when the RSM instruc tio n is exe-

cuted, the CPU will not re-execute the I/O instructio n. This slot is initialized to 00H during an

SMI#. It is the SMM handler's responsibility to load the I/O trap restart slot with 0FFH when re-

start is desire d. The S MM handle r must not set the I/O trap restart slot to 0FFH when the SMI#

is not asserted on an I/O instruction boundary, as this will cause unpredictable result s.

3.1.6 HALT Restart

It is possible fo r SMI # to brea k int o the HALT state a n d the appli ca tion mig ht wa nt to ret u rn to

the HALT state after RSM. The SMM archite cture provides the option of restarting the HALT

instruction after RSM.

3-7

CORE OVERVIEW

CR0 (bit 16) is used as the HALT status bit and is set every time a HALT instruction is executed.

This information is saved by SMM State Save sequence, at the location specified by 3FF02H. The

least-significant bit (bit 0) of this location is a duplicate bit of CR0 (bit 16) during SMI#. A RSM

instruction will restart the HALT instruction if this bit is set. The SMM handler has the option of

clearing this bit at 3FF02H (the HALT restart slot) to force the C PU to p roceed aft er the HALT

instruction. CR0 (bit 16) is still considered a reserved bit and must not be altered by the SMM

handler.

3.1.7 SMRAM State Dump Area

The SMM State Save sequence sets SMIAC T#. This mechanism indicates to internal modules

that the CPU has entered and is currently executing SMM. The resume (RSM) instruction is only

valid when in SMM. SMRAM space is an area located in the memory ad dress range 38000H–

3FFFFH. The SMRAM area cannot be relocated internally. SMRAM space is intended for access

by the CPU only, and should be accessibl e only when SMM is enabl ed. This are a is used by the

SMM State Save seq uence to save the CPU state in a stack-like fashi o n from the top of the SM-

RAM area downward.

The CPU state dump area always starts at 3FFFFH and ends at 3FE00H. The following is a map

of the CPU state dump in the SMRAM.

3-8

CORE OVERVIEW

Hex Address Name Description

03FFFC CR0 Control flags that affect the processor state 03FFF8 CR3 Page directory base register 03FFF4 EFLGS General condition and control flags 03FFF0 EIP I nstruction pointer 03FFEC EDI Destination index 03FFE8 ESI Source index 03FFE4 EBP Base pointer 03FFE0 ESP St a ck pointer 03FFDC EBX General register 03FFC8 EDX General register 03FFD4 ECX General register 03FFD0 EAX General register 03FFCC DR6 Debug register; contains status at exception 03FFC8 DR7 Debug register; controls breakpoints 03FFC4 TR Task register; used to access current task descriptor 03FFC0 LDTR Local descriptor table pointer 03FFBC GS General-purpose segment register 03FFB8 FS General-purpose segment register 03FFB4 DS Data segment register 03FFB0 SS Stack segment reg iste r 03FFAC CS Code segment register 03FFA8 ES General-purpose segment register 03FFA7–03FF04 — Reserved 03FF02 — Halt restart slot 03FF00 — I/O trap restart slot 03FEFC — SMM revision identifier (10000H) 03FEFB–03FE00 — Reserved

The programmer should not modify the contents of this area in S MRAM space directly. SMRAM

space is reserved for CPU access only and is intended to be use d only when the processor is in

SMM.

ERRATA (3/28/95) In the table entry for HEX Address 03FEFC, the description incorrectly showed

it now correctly shows 10000H.

01000H;

3-9

CORE OVERVIEW

3.1.8 Resume Instruction (RSM)

After an SMI# req uest is serviced, the RSM instruction must be executed to allo w the CPU to

return to an application transpare ntl y after se rvicing the SM I #. When the RSM inst r uction is ex-

ecuted, it restores the CPU state from SMRAM and passes contr ol back to the operating system.

The RSM instruction uses the special opcode of 0FAAH. The RSM instruction is reserved for the

SMI# handler and should only be executed by the SMI# handler. Any attempt to execute the RSM

outside of SMM mode will result in an invalid opcode exception. At the end of the RSM instruc-

tion, the processor will drive SMIACT# high, indicating the end of an SMM routine. This allows

the system designer to use SMIACT # as a gate to block RESET to the CPU while in SMM.

3.1. 9 SMM Priorit y

If more than one exc ept ion o r inte rr upt is pending at an i ns truct ion boundary, the processo r ser-

vices them in a predictable order. The priority among classes of exception and inte rrupt sources

is shown in the table below. The processor first services a pending exception or interrupt from the

class that has the highest priority, transferring exe cution to t he first i nstruction of t he handler.

Lower priority exceptions are discarded; lower priority interrupts are held pending. Discarded ex-

ceptions are reissued when the interrupt handler returns execution to the point of interrupti on.

SMI# has the following relative priority, where 1 is highe st and 11 is lowest:

Table 3-1. Relative Pri ority of Exceptions and Interrupts

1 Double Fault 2 Segmentation Violation 3 Page Fault 4 Divide-by-zero 5SMI# 6 Single-step 7 Debug 8 ICE Break

9NMI 10 INTR 11 I/O Lock

3.2 SYSTEM MANAGEMENT INTERRUPT

The Intel386 EX processor extends the standard Intel386 microprocessor architecture by adding a new feature cal led the system m anageme nt interrupt (SM I#). This se ction describes in d etail how SMI# can be utilized by the system designer.

3-10

CORE OVERVIEW

The execution unit will recognize an SMI# (falling edge) on an instruction boundary (see instruction #3 in Figure 3-1 on page 3-11). After all the CPU bus cycles, including pipelined cycles, have completed, the state of the CP U is saved to the SMM St ate Dump Area. Aft er executing a RSM instruction, the C PU will proc eed to the next a pplicati on code instruct ion (see inst ruction # 4 in

Figure 3-1). SMM latency is measured from the falling edge of SMI# to the first ADS# where

SMIACT# is active (see Figure 3-2).

SMI#

Instr

#1 #2

SMI#

SMIACT#

INTR

RESET

InstrInstr

Latency

SMI

RESET must

be blocked

State Save

Interrupts

Blocked

2nd SMI# is blocked

Figure 3-1. Standard SMI#

SMM

Handler

Instr Instr

#4 #5

State

Resume

Interrupts

Blocked

RESET must

be blocked

A2510-01

The SMM handler may optionally enable the NMI interrupt, but NMI is disabled when the SMM handler is entered. (Note that the CPU wi ll not recogni ze NMI whi le executi ng the SM M State Save sequence or SMM State Resume sequence.) NMI will always be enabled following the completion of the first interrupt service routine (ISR) or exception handler.

3-11

CORE OVERVIEW

Once SMI# has been initiated, RESET must be blocked until the CPU state has been completely saved. If RESET occurs during the stat e save process, unpredicta ble re sults will occur. It i s rec ommended that external circuitry use the falling edge of SMI# to block RESET. The SMI# signal needs to be sampled ina ctive, then active, in order to latch a falling edge. The SMI# must n ot be asserted during RESET. Figure 3-2 sh ows the minimum SMM durat ion that is available for switching SMRAM and system memory.

Even if the processor is in SMM, ad dress pipel ine bus cycles c an be performed correc t ly by asserting NA#. Pipeline bus cycles can also be performed immediately before and after SMIACT# assertion. The n umbers in Figure 3-2 also reflec t a pipeline bus cycle.

CLK2

T1 T2

CLK

SMI#

ADS#

READY#

SMIACT#

Normal State

B D

State Save, SMM Handler,

State Restore

Normal State

A2512-01

Figure 3-2. SMIACT# Latency

NOTEEven if bus cycles are pipelined, the minimum clock numbers are guaranteed.

3.2.1 System Management Interrupt During HALT Cycle

Since SMI# is an asynchr onous signal, it may be generated at any time . A condition of inte rest arises when an SMI# occurs while the CPU is in a HALT state. To give the system designer maximum flexibilit y, the processor allows an SM I# to optionally exit the HAL T state. Figure 3-3 shows that the CPU will normally re-execute the HALT instruction after RSM; however, by modifying the HALT restart slot in the SMM State Dump area, the SMM handler can redirect the instruction pointer past the HALT instr uction.

3-12

Instr

A2509-01

State

Save

SMI#

SMM

Handler

Instr

State

Resume

Instr Instr

#1 #2

#4 #5

I/O Instr

Instr

Option

#1 #2

HALT

SMI#

Halted State

CORE OVERVIEW

Instr Instr

#3 #4

Option

State Save

SMM

Handler

State

Resume

A2508-01

Figure 3-3. SMI# During HALT

3.2.2 System Management Interrupt During I/O Instruction

Like the HALT restart feature, the p rocessor allows rest a rti ng I/O cycle s which have been int errupted by an SMI#. This gives the system designer the option of performing a hardware I/O cycle restart withou t having to modify either application, operating system, or BIOS software. (See Fig-

ure 3-4.)

If an SMI# occurs during an I/O cycle, it then becomes the responsibility of the SMM handler to determine the source of the SMI# . If, for example, the source is the powered down I/O device, the SMM handler would power up the I/O de vice and reinitial ize it. The SMM handl er would then write 0FFH to the I/O restart slot in the SMM State Dump area and the RSM instruct ion would then restart the I/O instr uction.

Figure 3-4. SMI# During I/O Instruction

3-13

CORE OVERVIEW

The SMI# input signa l can be asynch ronous and as a result, SMI# must be valid at least three clock periods before READY# is asserted. SMI# must be sampled valid for at least two clocks, with the other clock used to internally arbitrate for control. See Figure 3-5 for details. (Note that this diagram is only for I/O cycles an d memory data rea d cycle s.)

Priority Arbitration

CLK2

SMI#

Sampled

SMI#

tsu tsu

RDY#

A2511-01

Figure 3-5. SMI# Timing

3.2.3 Interrupt During SMM Handl er

When the CPU enters SMM, both INTR and NMI are disabled. (See Figure 3-6.) The SMM handler may enable INTR by executing the STI instruction. NMI will be enabled after the completion of the first i nterrupt service routine (softwa re or hardware init iated ISR) or excepti on handler within the SMM handl er. Software int errupt and exception instructions a re not blocked during the SMM handler.

The SMM feature was desi gned to be used without any othe r int errupts. It is recomm ended that INTR and NMI be bloc ked by the syst em du ring SMI#. The pending INTR and NMI, which i s blocked by SMM, is serviced after completion of RSM instruction execution. Only one INTR and one NMI can be pending.

The SMM handler may choose to enable interrupts to take advantage of device drivers. Since interrupts were enabled while under control of the SMM handler, the signal SMIACT# will continue to be asserted. If the system desi gner wants to take advant age of existing devic e drivers that leverage interrupts, the memory controll er must take thi s into accou nt.

3-14

CORE OVERVIEW

SMM

Handler

RSM

RESET must

State

Restore

be blocked

Application

Instr

A2505-01

SMI#

SMIACT#

INTR

NMI

RESET

Application

Instr

Instr Instr

SMI

Latency

RESET must

be blocked

State Save

SMM

Handler

Instr Instr Instr Instr Instr

Instr

SMM Handler

NMI is Blocked

Intr

Service

Figure 3-6. Interrupted SMI# Service

3.2.4 SMM Handler Terminated by RESET

RESET is allowed to occur (alth ough not recommended duri ng normal operation) so that SMM software developers can escape out of an SMM handler without having to power the entire system down. Also, at power up, RESET must not be internally blocked. However, there are “windows” in time where asserting RESET can cause problems.

One such window is while the CPU is in the process of saving its state to the SMM State Dump area. Should a RESET occur during this time period, the CPU will unconditional ly jump to the RESET locatio n wi th n o guarantee of properly sa ving the SM M state a nd no wa y to res tore the system state. (Even if the state was saved, you can't execute RSM after RESET without going back into SMM.) Should this occu r, it is no longer possible to ret urn to the applicati on code.

The second window is when the CPU is in the process of restoring its original executi on state. Should a RESET occur during this time period, it is no longer possible to return to the application code, unless the progr ammer mov ed the c ontents of the SMM State Dump area to a second secure area.

At normal design, RESET should be masked by external circuitry from SMI# assertion to the first instruction of the SMM handler. See Figure 3-7.

3-15

CORE OVERVIEW

SMM Handler

Instr Instr Instr Instr InstrInstr Instr Instr

SMM Handler

CPU Request

Instr Instr

Instr

A2506-01

SMI#

SMIACT#

INTR

NMI

RESET

Application

Instr

SMI

Latency

State Save

RESET must

be blocked

Figure 3-7. SMI# Service Terminated by RESET

3.2.5 HALT During SMM Handler

The system de signer may wi sh to place the system int o a HALT c onditio n while in SMM . The CPU allows this condition to occur; however, unlike a HALT while in normal mode, the CPU internally blocks INTR a nd NMI from being rec ognized until aft er the RSM i nstruction is executed. If a HALT needs to be breakable in SMM, the SMM handler must enable INTR and NMI before a HALT instruction execution. NMI will be enabled after the completion of the first interrupt service routine within the SMM handle r.

After the SMM handler has enabled INTR and NMI, the CPU will exit the HALT state and return to the SMM handler when INTR or NMI occurs. See Figure 3-8 for details.

3-16

CORE OVERVIEW

SMI#

Instr

#1 #2

State Save

SMM

Handler

Enable

INTR & NMI

INTR or NMI

HALT Halted

State

Interrupt

Handler

SMM

Handler

State

Resume

Instr Instr

#3 #4

A2507-01

Figure 3-8. HALT During SMM Handler

3.2.6 SMI# During SMM Op erati on

If the SMI# request is asserted during SMM operati on, the s econd SM I# can't nest the c ur rently executing SM M. The second SM I# request i s latched, and he ld pendin g by the CPU. Onl y one SMI# request can be pending. After RSM execution is completed, the pending SMI# is serviced. At this time, SMIACT# is deasserted once at completion of RSM, then asserted again for the second SMI#.

If the SMM handler polls the various SM I# source s by o ne of the SMI # triggers, a n d two SMI # sources are found in the SMI# generation circuit, the SMM handler will service both SMI# sources and will execute a RSM instruction. In this SMM handler, if the SMI# generation circuit asserts the second SMI# du ring t he fi rst SM I # service ro utine, the sec o n d SMI# will be pen ding. Next, the SMM han dler will find two SM I# sourc es and servic es them. Afte r the CPU completes the RSM execution, the pending SMI# (second SMI#) will be generated, but there will be nothing to service because t he second SMI# has been servi ced in the first SMM. This unnecessa ry SMI# transaction requires a few h undred clocks. There may be some performance degrada tion if thi s example occurs frequently. For good performance, it is the respons ibility of the SMI# generation circuitry to manage multiple SMI# assertions.

3.3 The Intel386 EX™ PRO CESS OR I DENT IFI ER REGI S TERS

The processor has two identifier registers: the Component and Revision ID register and the SMM Revision ID register. The component ID is 23H; the component revision ID is 09H. This register can be read as 2309H. The SMM revision identifier is 10000H.

3-17

CORE OVERVIEW

3-18

CHAPT ER 4

SYSTEM REGISTER ORGANIZATION

This chapter provides an overview of the system registers incorporated in the Intel386™ EX processor, focusing on register o rganization from an a ddress architecture vie wpoint. The chapte rs that cover the individual peripheral s desc ribe the regist ers in detail.

This chapter is organized as follows:

• Overview

• I/O address space for PC/AT* system s

• Expanded I/O space

• Organization of peripheral registers

• I/O address decoding techniq ues

• Addressing modes

• Peripheral register addresses

4-1

SYSTEM REGISTER ORGANIZATION

4.1 OVERVIEW

The Intel386 EX processor has register reso urces in the following categories:

• Intel386 processor core architecture registers

— general purpose registers — segment registers — instruction pointer and flags — control registers — system address regist ers ( protected mode) — debug registers — test registers

• Intel386 EX processor peripheral registers

— configuration spac e control registers — interrupt control unit registers

ERRATA (3/28/95) Sub-bullet for DMA unit registers incorrectly

stated “8257A-compatible” ; now correctly states “8237A-compatible”.

— timer/c o unter uni t register s — DMA u n it registers (8237A-compatible and enhanced function registers) — asynchronous serial I/O (SIO) registers — clock gene ration selector registers — power management control registers — chip-s elec t unit control registers — refresh control unit registers — watchdog timer control registers — synchronous serial I/O control registers — parallel I/O port control registers

4.1.1 Intel386™ Proc essor Core Arch itectu re Regi sters

These registers are a superset of the 8086 and 80286 processor registers. All 16-bit 8086 and 80286 registers are contained within the 32-bit Intel386 processor core registers. A detailed descriptio n of the Intel386 architecture base registers can be found in the Intel386™ SX Micropro- cessor Programmer's Reference Manual.

4-2

SYSTEM REGISTER ORGANIZATION

4.1.2 Intel386™ EX Processo r Periphera l Registers

The Intel386 EX processor contains some periphe ral s tha t are comm o n an d compat ibl e wi th the PC/AT system arc hitec ture and others that are useful for embedde d ap plications. The perip heral registers control access to these peripherals and enable you to configure on-chip system resources such as timer/counters, power management, chip selects, and watchdog timer.

All of the peripheral registers reside physically in what is called the expanded I/O address space (addresses 0F000H–0F8FFH). Peripherals that a re compatible with PC/AT system archit ect ure can also be m app ed into DOS I/O address space (addresses 0H– 03FFH). The following rules apply for accessing peripheral registers after a system rese t:

• registers within the DOS I/O address space are accessible

• registers withi n the expa nded I/O address space are acce ssi ble only after the e xpanded I/O

address space is enabled

4.2 I/O ADDRES S SPACE FOR PC/AT SYSTEM S

The Intel386 EX processor’s I/O address space is 64 Kbytes. On PC/AT platforms, DOS operat- ing system and applications ass um e that only 1 Kbyte of the total 64-Kbyte I/O address space is used. The first 256 bytes (addresses 00000H–00FFH) are reser ved for I/ O platform (motherboard) resources such as the interrupt and DMA controllers, and the remaining 768 bytes (addresses 0100H–03FFH) are available for “general” I/O peripheral card resources. Since only 1 Kbyte of the address space is supported, a dd-on I/O pe ripheral cards typic ally decode only the lower 10 address lines. Because the upper address lines are not decoded, the 256 platform address locations and the 768 bus address locations are repeated 64 times (on 1-Kbyte boundaries), covering the entire 64-Kbyte address space. (See Figure 4-1.)

Generally, add-on I/O peripheral cards do not use the I/O addresses reserved for the platform resources. Software running on the platform can use any of the 64 repetitions of the 25 6 address locations reserved for accessing platform resources.

4-3

SYSTEM REGISTER ORGANIZATION

General Slot I/O

Platform I/O (Reserved)

General Slot I/O

Platform I/O (Reserved)

General Slot I/O

Platform I/O (Reserved)

FFFFH (64K)

FD00H

FC00H (63K)

0C00H (3K)

0900H

0800H (2K)

0500H

0400H (1K)

4-4

General Slot I/O

0100H (256)

Platform I/O (Reserved)

0000H (0)

A2498-01

Figure 4-1. PC/AT I/O Address Space

SYSTEM REGISTER ORGANIZATION

4.3 EXPANDED I/O ADDRESS SPACE

The Intel386 EX processor’s I/O address scheme is similar to that of EISA(32) systems. It assigns 63 of the 64 repetitions o f the first 256 a ddre ss l ocations o f eve r y 1K block to spe cific slot s. (In a PC, a sl ot is a socke t used for add-in boa rds. In embedded proce ssors, a slot c an be view ed a s simply a part of the total I/O address space.) The partitioning is such that 4 groups of 256 address locations are assigned to e ach slot, for a total of 1024 specific address locations per slot. (See Fig-

ure 4-2 .) Since add-in I/O cards decode only the lower 10 address lines, they respond to th e “gen-

eral” 768 bytes (repeated 64 times). Thus, each slot has 1K addresses (in four 256-byte seg ments) that can potentially contain extended peripheral registers.

4-5

SYSTEM REGISTER ORGANIZATION

General Slot I/O

Slot 15

General Slot I/O

Slot 15

General Slot I/O

Slot 15

General Slot I/O

Slot 15

General Slot I/O

Slot 1

General Slot I/O

Slot 1

General Slot I/O

Slot 1

General Slot I/O

Slot 1

General Slot I/O

Slot 0

General Slot I/O

Slot 0

General Slot I/O

Slot 0

General Slot I/O

Slot 0

FFFFH (64K)

FC00H (63K)

F800H (62K)

F400H (61K)

F000H (60K)

1FFFH (8K)

1C00H (7K)

1800H (6K)

1400H (5K)

1000H (4K)

0C00H (3K)

0800H (2K)

0400H (1K)

0000H (0K)

A2499-01

4-6

Figure 4-2. Expanded I/O Address Space

SYSTEM REGISTER ORGANIZATION

Slot 0 refers to the platform. (Agai n, many of the peripheral s found on a standard PC platform (motherboard) are integrated in the Intel386 EX processor). Thus, a total of 1K unique I/O addresses are assigned to the platform (in addition to the 768 bytes that are repeated). The first 256 address locations are the same platform resources as defined across all platforms. The remaining three groups of 256 address loca tions can be used for a specific platform such as EISA.

The Intel386 EX processor uses slot 15 for the registers needed for integrated peripherals. Using this slot avoids conflicts wit h other devices in an EISA syst em, since EISA systems do not typically use slot 15. The Intel386 EX processor does not currently use slot 14, but it is reserved for future expansion.

4.4 O RGANI ZAT IO N OF PERIP HERAL RE GI STE RS

The registers associated with the integrated peripherals are physically located in slot 15 I/O space. There are sixte en 4K address slots in I/O space. Slot 0 refers to 0H–0FFFH; slot 15 refers t o 0F000H–0FFFFH. Table 4-1 shows the address m ap f or the perip heral registers in sl ot 15. Note that the I/O addresses fall in address ranges 0F000H–0F0FFH, 0F400H–0F4FFH, and 0F800H– 0F8FFH; utilizing the unique sets of 256 I/O addresses i n Slot 15.

Table 4-1. Peripheral Register I/O Address Map in Slot 15

DMA Controller 1 F000H – F01FH Master Interrupt Controller F020H – F03FH Programmable Interval Timer F040H – F05FH DMA Page Registers F080H – F09FH Slave Interrupt Controller F0A0H – F0BFH Math Coprocessor F0F0H – F0FFH Chip Select Unit F400H – F47FH Synchronous Serial I/O Unit F480H – F49FH DRAM Refresh Control Unit F4A0H – F4BFH Watchdog Timer Unit F4C0H – F4CFH Asynchronous Serial I/O Channel 0 (COM1) F4F8H – F4FFH Clock Generation and Power Management Unit F800H – F80FH External/Internal Bus Interface Unit F810H – F81FH Chip Configuration Registers F820H – F83FH Parallel I/O Ports F860H – F87FH Asynchronous Serial I/O Channel 1 (COM2) F8F8H – F8FFH

4-7

SYSTEM REGISTER ORGANIZATION

4.5 I/O ADDRESS DECODING TECHNIQUES

One of the key features of the Intel386 EX processor is that it can be configured to be compatible with the standard PC/AT architecture. In a PC/AT system, the platform I/O resources are located in the slot 0 I/O address space. For the Intel386 EX processor, this means that PC/AT-compatible internal peripherals should be reflected in the slot 0 I/O space for DOS operating system an d application software to access and manipulate them properly.

This discussion leads to the concepts of DOS I/O space and expanded I/O space. DOS I/O space refers to the lower 1K of I/O addresses, where only PC/AT-compatible peripherals can be mapped. Expanded I/O space refers to the top 4K of I/O addresses, where all peripheral registers are physically locat ed. T he remai nder of this se cti on explai ns h ow special I/O a d dress decoding schemes mani pulat e registe r addre sses withi n these tw o I/O spaces.

4.5.1 Address Configura tion Register

I/O address locations 22H and 23H in DOS I/O space offer a special case. These address locations are not used to access any peripheral registers in a PC/AT system. The Intel386 SL microprocessor and other integrated PC solutions use them to enable extra address space required for configuration registers specific to these products. On the Intel386 EX processor, these address locations are used to hide the peri p heral regi sters i n the expanded I/O space. The ex panded I/O s pace can be enabled (registers visible) or disabled (registers hidden).

The 16-bit regi ster at I/O loca tion 22H can als o be used to cont rol mapping of various internal peripherals in I/O address space. This register, REM APC FG, is defined in Figure 4-3.

The remap bits of this register control whethe r the internal periphe rals are mapped into the DOS I/O space. Setting a bit makes the periphe ral accessi ble only in expande d I/O space. C learing a bit makes the peripheral accessible in both DOS I/O space and expanded I/O space. To access the REMAPCFG register, you must first enable the expanded I/O address space. At reset, this register is cleared, which maps internal PC/AT-com pat ibl e periphera ls into DOS I/O space.

4-8

SYSTEM REGISTER ORGANIZATION

Address Configuration Register REMAPCFG

15 8

ESE——— ————

7 0

—

Bit

Number

15 ESE Enables expanded I/O space. 14–7 — Reserved. 6 S1R Remaps serial channel 1 (COM2) address. 5 S0R Remaps serial channel 0 (COM1) address. 4 ISR Remaps slave 8259A interrupt controller address. 3 IMR Remaps master 8259A interrupt controller address. 2 DR Remaps DMA address. 1 — Reserved. 0 TR Remaps timer control unit address.

S1R S0R ISR

Bit

Mnemonic

Expanded Addr: PC/AT Address:

Reset State:

IMR DR — TR

Function

0022H 0022H 0000H

Figure 4-3. Address Configuration Register (REMAPCFG)

4.5.2 Enabling and Disabl in g the Expan ded I/O Spa ce

The Intel386 EX p rocesso r’s expanded I/O space is enable d by a specific write sequence to I/O addresses 22H and 23H (Figure 4-4). Once the expanded I/O space is enabled, internal peripherals (timers, DM A, inte rrupt controlle rs and seria l communi cation channe ls) can be mapped out of DOS I/O space (using the REMAPCFG re giste r) and registe rs associated wit h other int ernal peripherals (such as the chip-select unit, power management unit, watchdog timer) can be accessed.

4.5.2.1 Programming REMAPCFG Example

The expanded I/O space enabl e (ESE) bit in the RE MAPC FG register c an be s et only by three sequential write operations to I/O addresses 22H and 23H as described in Figure 4- 4. Once ESE is set, REMAPCFG_LO and all the on-chip registers in the expanded I/O address range F000H– F8FFH can be accessed. The remap bits in REMAPCFG_LO are still in effect even when the ESE bit is cleared by writing 0 to the ESE bit.

4-9

SYSTEM REGISTER ORGANIZATION

ERRATA (3/28/95) Figure 4-4, Programming the ESE Bit, has been substantially rewritten.

;;disable interrupts

CLI ; Enable expanded I/O space of Intel386(tm) EX processor ; for peripheral initialization.

MOV AX, 08000H ; Enable expanded I/O space

OUT 23H, AL ; and unlock the re-map bits

XCHG AL, AH

OUT 22H, AL

OUT 22H, AX ;; at this point PC/AT peripherals can be mapped out or in ;; other peripherals can be accessed and manipulated ;; For example, ;; Map out the on-chip DMA channels from the DOS I/O space (slot 0)

MOV AL, 04H

OUT 22H, AL ; Disables expanded I/O space

MOV AL, 00H

OUT 23H, AL ;; Re-enable Interrupts

STI

ERRATA (6/1/95) Previous errata incorrectly showed OUT 23H, AX Now correctly shows OUT 22H, AX

Figure 4-4. Setting the ESE Bit

The REMAPCFG register is write-protected until the expanded I/O space is enabled. When the enabling writ e sequence is executed, it sets the ESE bit. A program can check this bit to see whether it has access to the expanded I/O spa ce registers . Clearing the ESE bit disables the expanded I/O space. This again locks the REMAPC FG register and makes it read-only.

4.6 ADDRESSING MODES

Combinations of the value of the ESE bit and the individual remap bit s in the REMAPC FG register yield four different peripheral addressing modes as far as I/O address decoding is concerned.

4.6.1 DOS-compatible Mode

DOS-compatible mode is achie ved by clearing ESE and all the periphe ral remap bits. In this mode, all PC/AT-compatible peripherals are mapped into the DOS I/O space. Only address lines A9–A0 are decoded for internal peripherals. Acce sse s to PC/AT-compat ibl e periphera ls are valid, while all other internal peripherals are inacce ssi ble (see Figure 4-5).

This mode is useful for accessing the internal timer, interrupt controller, serial I/O ports, or DMA controller in a DOS-compatible environment.

4-10

SYSTEM REGISTER ORGANIZATION

REMAPCFG

3FFH

23H

22H

On-chip UART-0

On-chip UART-1

F8FFH

On-chip 8259A-2

On-chip Timer

00000 000

F000H

On-chip 8259A-1

Expanded

I/O

Space

Note: Shaded area indicates that

expanded I/O space peripherals are not accessible

On-chip DMA

DOS I/O Space

A2495-01

Figure 4-5. DOS-Compatible Mode

4-11

SYSTEM REGISTER ORGANIZATION

4.6.2 Nonintrusive DOS Mo de

This mode is achieved by clearing ESE and setting the individual peripherals’ remap bits. Peripherals whose remap bits are set will be mapped out of DOS I/O space. Like DOS-compatible mode, only address lines A9–A0 are decoded internally. This mode is useful for connecting an external peripheral instead of using the integrated peripheral. For example, a system might use an external 8237A DMA rather than using the internal DMA unit . For this configuration, clear the ESE bit and set the remap bit associated with the DMA unit. In this case, the external 8237A is accessible in the DOS I/O space, while the internal DMA can be accessed only after the expanded I/O space is enabled. (See Figure 4-6.)

4.6.3 Enhanced DOS Mode

This mode is achieve d by setting the ESE bit an d clearing all PC/AT-compatible peri pherals’ remap bits. Address lines A15–A0 are de coded int ernal ly. The expanded I/O space is enabled and the PC/AT-com patible interna l periphe rals are a ccessi ble in either DOS I/O s pace or e xpan ded I/O space. (See Figure 4-7.) If an application frequentl y requires the addit ional peripheral s, but at the same time wants to ma intain DOS c ompat ibility for ease of devel opme nt, this is the most useful mode.

4.6.4 NonDOS Mode

This mode is achieved by setting the ESE bit and setting all peripherals’ remap bits. Address lines A15–A0 are decoded intern ally. The expanded I/O space is enabled and all peripherals can be accessed only in expanded I/O space. This mode is useful for systems that don’t require DOS compatibility and have other cus tom peri pheral s in slot 0 I/O space.

For all DOS peripherals, the lower 10 bits in the DOS I/O space and in the expanded I/O space are identical (except the UARTs, whose lower 8 bits are identical). This makes correlation of their respective of fsets in DOS and e x panded I/ O space s easi er. Also, the UAR Ts have fixe d I/O a ddresses. This differs from standard PC/AT configurations, in which these address ranges are programmable.

4-12

SYSTEM REGISTER ORGANIZATION

REMAPCFG

3FFH

23H

22H

On-chip UART-0

On-chip UART-1

F8FFH

On-chip 8259A-2

On-chip Timer

00000 010

F000H

On-chip 8259A-1

Expanded

I/O

Space

Note: Shaded area indicates

that the on-chip DMA and expanded I/O space peripherals are not accessible

Internal DMA

DOS I/O Space

Figure 4-6. Example of Nonintrusive DOS-Compatible Mode

A2496-01

4-13

SYSTEM REGISTER ORGANIZATION

REMAPCFG

3FFH

23H

22H

On-chip UART-2

On-chip UART-1

F8FFH

On-chip 8259A-2

On-chip Timer

00000 000

F000H

On-chip 8259A-1

Other Peripherals

UART-0

UART-1

Timer

8259A-2

8259A-1

On-chip DMA

4-14

On-chip DMA

DOS I/O Space

A2501-01

Figure 4-7. Enhanced DOS Mode

3FFH

SYSTEM REGISTER ORGANIZATION

F8FFH

Other Peripherals

UART-0

UART-1

Timer

REMAPCFG

23H

22H

01111 011

DOS I/O Space

Figure 4-8. NonDOS Mode

F000H

8259A-2

8259A-1

On-chip DMA

A2502-01

4-15

SYSTEM REGISTER ORGANIZATION

4.7 PERIPHERAL REGISTER ADDRESSES

Table 4-2 lists the address es and na mes of a ll the user-ac cessi ble periphera l regist e rs. Although

the Intel386 core has byte, word, and doubleword access to I/O addresses, some registers can only be accessed as bytes. The registers with the High Byte column shaded are byte-addressable only. The default (reset) value of each register is shown in the Reset Value column. An X in this column signifies that the register bits are undefined. Some address values do not access registers, but are decoded to provide a logic control signal. These addresses are listed as Not a register in the Reset column.

Table 4-2. Peripheral Register Addresses (Sheet 1 of 6)

Expanded

Address

F000H 0000H F001H 0001H F002H 0002H F003H 0003H F004H 0004H Reserved F005H 0005H Reserved F006H 0006H Reserved F007H 0007H Reserved F008H 0008H DMACMD1/DMASTS 00H F009H 0009H F00AH 000AH F00BH 000BH F00CH 000CH F00DH 000DH F00EH 00 0EH F00FH 000FH F010H F011H F012H F013H F014H Reserved F015H Reserved F016H Reserved NOTE: Registe rs wi th the “High Byte” column sh aded (darke r shade ) are byte-a ddre ss-

able only. LIghter shade indicates reserved areas.

PC/AT

Address

High Byte Low Byte Reset Value

DMA Controller and Bus Arbiter

DMA0TAR0/1 XX DMA0BYC0/1 XX DMA1TAR0/1 XX DMA1BYC0/1 XX

DMASRR 00H DMAMSK 04H DMAMOD1 00H DMACLRBP Not a register DMACLR Not a register DMACLRMSK Not a register DMAGRPMS K 03H DMA0REQ0/1 00H DMA0REQ2/3 00H DMA1REQ0/1 00H DMA1REQ2/3 00H

4-16

SYSTEM REGISTER ORGANIZATION

Table 4-2. Peripheral Register Addresses (Sheet 2 of 6)

Expanded

Address

F017H Reserved F018H DMABSR F0H F019H F01AH F01BH F01CH F01DH F01EH

F020H 0020H

F021H 0021H

0022H 00 22H REMAPCFG_HI REMAPCFG_LO 0000H

F040H 0040H F041H 0041H F042H 0042H F043H 0043H

F080H Reserved F081H 0081H Reserved F082H 0082H Reserved F083H 0083H DMA1TAR2 XX F084H Reserved F085H DMA1TAR3 XX F086H F087H 0087H F088H Reserved F089H 0089H Reserved F08AH 008AH Reserved F08BH 008BH Reserved NOTE: Registe rs wi th the “High Byte” column sh aded (darke r shade ) are byte-a ddre ss-

able only. LIghter shade indicates reserved areas.

PC/AT

Address

High Byte Low Byte Reset Value

DMACHR/DMAIS 00H DMACMD2 08H DMAMOD2 00 H DMAIEN 00H DMAOVFE 0AH DMACLRTC Not a register

Master Interrupt Controller

ICW1m/IRRm/ISRm/ OCW2m/OCW3m

ICW2m/ICW3m/ OCW1m/POLLm

Address Confi gura tio n Regis ter

Timer Control Unit

TMR0 XX TMR1 XX TMR2 XX TMRCON 00H

DMA Page Registers

DMA0TAR3 XX DMA0TAR2 XX

4-17

SYSTEM REGISTER ORGANIZATION

ERRATA (3/28/95) In the table entry for address F092H , the reset value incorrectly showed 00H; it now correctly s h ows 0 EH.

Table 4-2. Peripheral Register Addresses (Sheet 3 of 6)

Expanded

Address

F08CH Reserved F08DH Reserved F08EH Reserved F08FH Reserved F098H DMA0BYC2 00H F099H F09AH Reserved F09BH Reserved

F092H 0092H

F0A0H 00A0H

F0A1H 00A1H

F400H CS0SADL_HI CS0ADL_LO 0000H F402H CS0SADH_HI CS0ADH_LO 0000H F404H CS0MSKL_HI CS0MSKL_LO 0000H F406H CS0MSKH_HI CS0MSKH_LO 0000H F408H CS1SADL_HI CS1ADL_LO 0000H F40AH CS1SADH_HI CS1ADH_LO 0000H F40CH CS1MSKL_HI CS1MSKL_LO 0000H F40EH CS1MSKH_HI CS1MSKH_LO 0000H F410H CS2ADL_HI CS2ADL_LO 0 000H F412H CS2ADH_HI CS2ADH_LO 0000H F414H CS2MSKL_HI CS2MSKL_LO 0000H F416H CS2MSKH_HI CS2MSKH_LO 0000H F418H CS3ADL_HI CS3ADL_LO 0 000H F41AH CS3ADH_HI CS3ADH_LO 0000H F41CH CS3MSKL_HI CS3MSKL_LO 0000H F41EH CS3MSKH_HI CS3MSKH_LO 0000H F420H CS4ADL_HI CS4ADL_LO 0 000H NOTE: Registe rs wi th the “High Byte” column sh aded (darke r shade ) are byte-a ddre ss-

able only. LIghter shade indicates reserved areas.

PC/AT

Address

High Byte Low Byte Reset Value

DMA1BYC2 00H

A20GATE and Fast CPU Reset

PORT92 0EH

Slave Interrupt Controller

ICW1s/IRRs/ISRs/ OCW2s/OCW3s

ICW2s/ICW3s/ OCW1s/POLLs

Chip-select Unit

4-18

SYSTEM REGISTER ORGANIZATION

Table 4-2. Peripheral Register Addresses (Sheet 4 of 6)

Expanded

Address

F422H CS4A DH_HI CS4ADH_LO 0000H F424H C S4M SKL_HI CS4MSKL_LO 0000 H F426H C S4M S KH_HI CS4MSKH_LO 0000H F428H CS5A DL_ HI CS5ADL_LO 0000 H F42AH CS5ADH_HI CS5ADH_LO 0000H F42CH CS5MSKL_ HI CS5MSKL_LO 0000H F42EH CS5MS KH_HI CS5MSKH_LO 0000H F430H CS6A DL_ HI CS6ADL_LO 0000 H F432H CS6A DH_HI CS6ADH_LO 0000H F434H C S6M SKL_HI CS6MSKL_LO 0000 H F436H C S6M S KH_HI CS6MSKH_LO 0000H F438H UCSADL _HI UCSADL_LO FF6FH F43AH UCSADH_HI UCSADH_ LO FFFFH F43CH UCSMSKL_HI UCSMSKL_LO FFFFH F43EH UCSMSKH_ HI UCSMSKH_ LO FFFFH

F480H SSIOTBUF_ HI SSIOTBUF_ LO 0000H F482H SSIORBUF_HI SSIORBUF_LO 0000H F484H F486H F488H F48AH

F4A0H RFSBAD_HI RFSBAD_LO 0000H F4A2H RFSCIR_HI RFSCIR_LO 0000H F4A4H RFSCON_HI RFSCON_LO 0000H F4A6H RFSADD_HI RFSADD_LO 00FFH

F4C0H WDTRLDH_HI WDTRLDH_LO 0000H F4C2H WDTRLDL_HI WDTRLDL_LO FFFFH F4C4H WDTCNTH_HI WDTCNTH_LO 0000H F4C6H WDTCNTL_HI WDTCNTL_LO FFFFH NOTE: Registe rs wi th the “High Byte” column sh aded (darke r shade ) are byte-a ddre ss-

able only. LIghter shade indicates reserved areas.

PC/AT

Address

High Byte Low Byte Reset Value

Synchro nou s Serial I/O Unit

SSIOBAUD 00H SSIOCON1 C0H SSIOCON2 00H SSIOCTR 00 H

Refresh Control Unit

Watchdog Timer Unit

4-19

SYSTEM REGISTER ORGANIZATION

Table 4-2. Peripheral Register Addresses (Sheet 5 of 6)

Expanded

Address

F4C8H WDTCLR_HI WDTCLR_LO Not a register F4CAH

F4F8H 03F8H F4F9H 03F9H F4FAH 03FAH F4FBH 03FBH F4FCH 03FCH F4FDH 03FDH F4FEH 03FEH F4FFH 03FFH

F800H F804H CLKPRS_HI CLKPRS_LO 0000H

F820H F822H F824H F826H F830H F832H F834H F836H

F860H F862H F864H F868H F86AH F86CH F870H F872H NOTE: Registe rs wi th the “High Byte” column sh aded (darke r shade ) are byte-a ddre ss-

able only. LIghter shade indicates reserved areas.

PC/AT

Address

Asynchrono us Seri al I/O Channe l 0 (COM1)

Clock Generation and Power Management

High Byte Low Byte Reset Value

WDTSTATUS 00 H

RBR0/TBR0/DL L0 FFH IER0/DLH0 FFH IIR0 01H LCR0 00H MCR0 00H LSR0 60H MSR0 X0H SCR0 XX

PWRCON 00H

Device Configuration Registers

P1CFG 00H P2CFG 00H P3CFG 00H PINCFG 00H DMACFG 00H INTCFG 00H TMRCFG 00H SIOCFG 00H

Parallel I/O Ports

P1PIN XX P1LTC FFH P1DIR FFH P2PIN XX P2LTC FFH P2DIR FFH P3PIN XX P3LTC FFH

4-20

SYSTEM REGISTER ORGANIZATION

Table 4-2. Peripheral Register Addresses (Sheet 6 of 6)

Expanded

Address

F874H P3DIR FFH

F8F8H 02F8H F8F9H 02F9H F8FAH 02FAH F8FBH 02FBH F8FCH 02FCH F8FDH 02FDH F8FEH 02FEH F8FFH 02FFH NOTE: Registe rs wi th the “High Byte” column sh aded (darke r shade ) are byte-a ddre ss-

able only. LIghter shade indicates reserved areas.

PC/AT

Address

Asynchrono us Seri al I/O Channe l 1 (COM2)

High Byte Low Byte Reset Value

RBR1/TBR1/DL L1 FFH IER1/DLH1 FFH IIR1 01H LCR1 00H MCR1 00H LSR1 60H MSR1 X0H SCR1 XX

4-21

SYSTEM REGISTER ORGANIZATION

4-22

CHAPT ER 5

DEVICE CONFIGURATION

Device configuration is the process of setting up the microprocessor’s on-chip peripherals1 for a particular system design. Specifically, device configuration consists of programming registers to connect peripheral signal s t o t he pa ckage pins and interconnect t he peri p heral s. The peripherals include the following:

• DMA controller (DMA)

• interrupt control unit (ICU)

• timer/counter unit (TCU)

• asynchronous serial I/O units (SIO0, SIO1)

• synchronous serial I/O unit (SSIO)

• refresh control unit (RCU)

• chip-select unit (CSU)

In addition, the pin c o n figuration registers control connectio ns f rom t he c oprocessor to the core and pin connections to the bus arbiter.

A variety of configuration options provide flex ib il ity in conf iguring the Intel386 EX microprocessor. This chapter describes the available configurations and the configuration registers that are programmed to define a configuration. It prese nts a method of configuring the chip for a set of specifications, and shows an example of configuring the device for a PC/AT* -compatible design. It also provides workshee ts to facilitate the configuration for your design.

5.1 INTRO DUCTI ON

Figure 5-1 shows Peripheral A and its connectio ns to other periphe ral s an d the package pins.

The “Internal Connectio n Logic” provides three kin ds of connect ions:

• connections between peripherals

• connections to package pins via multiplexers

• direct connections to package pins without multiplexers

The internal connection logic is controlled by the Peripheral A configuration regist er.

In this chapter, the terms “peripheral” and “on-chip peripheral” are used interchangeably. An “off-chip peripheral” is external to the Intel386 EX microprocessor.

5-1

DEVICE CONFIGURATION

Each of the pin multiplexers (“Pin Muxes” ) conne cts one of two inter nal signals to a pin. One is a Peripheral A signal. The second signal can be an I/O port signal or a signal from/to another peripheral. The pin multiplexers are controlled by the pin configuration registers. Some input-only pins without multiplexers (“Sha red Pins w/o M uxes”) are routed to two different peripherals. Your design should use only one of the inputs.

Together, the pe ripheral co nfigurat ion regist ers and the pin c o nfiguration regi sters allow you to select the perip herals to be used, t o intercon nect them as your de sign requires, a nd to bring selected signals to the packa ge pins.

Peripherals B, C, D, ...

Pins

Microprocessor

Peripheral A

Peripheral A

Configuration

Internal

Connection

Logic

Control

Pin

Muxes

Control

with

Muxes

Shared Pins

w/o Muxes

Pin Configuration Registers

A2535-01

Figure 5-1. Peripheral and Pin Connections

5.2 PERIPHERAL CONFIGURATION

This section describe s the configuration of eac h on-chip peripheral. The pe ripheral block diagrams in this section a re s im plified to focus o n the signa ls rel evant t o devi ce configurat i on. Fo r more detailed information on the peripheral itself, see the chapter de sc ribing that periphera l.

5-2

DEVICE CONFIGURATION

The symbology used for signal s that share a device pin is shown in Figure 5-2 on page 5-5. Of the two signal names by a pin, the upper signal is associated with the peripheral in the figure. The lower signal in parent heses is the alternate signal, which connects to a different peripheral or the core. If a pin has a multiplexer, it is shown as a switch, and the register bit that controls it is noted above the switch.

Figure 5-21 on page 5-30 summarizes the bit selections in the pin configuration registers, and Fig- ure 5- 2 2 on page 5- 31 summarizes the bit selections in the peripheral configuration registers. The

use of these tables is discus sed in “Configuration Exa mple” on page 5-25.

5.2.1 DMA Controller, Bus Arbiter, and Refresh Unit Configuration

Figure 5-2 shows the DMA controller, bus arbiter, and refresh unit together with information for

their configuration. Request s for a DMA data transfer are s hown as inputs to the multiplexer:

• a serial I/O transmitter (TXD0, TXD1) or receiver (RXD0, RXD1)

• a synchronous serial I/O transmitter (SSIOTX) or receiver (SSIORX)

• a timer (OUT1, OUT2)

• an external source (DRQ0, DRQ1).

The inputs are selected by the DMA configuration register (see Figure 5-3).

5.2.1.1 Using The DMA Unit with External Devices

For each DMA chan nel, three bits in the DM A configurat ion regist er (Figure 5-3) select th e external request input or one of four request inputs from the peripherals. Another bit enables or disables that channel’s DMA acknowledge signal (DACKn#) at the device pin. Enable the DACKn# signal only if you are using the external request signal (DRQn). The acknowledge signals are not routed to the on-chip peripherals, and therefore, these peripherals cannot initiate single-cycle (flyby) DMA transfers.

An external bus master cannot ta lk direc tly to int ernal peri pheral modules be cause the ext ernal address lines are outputs only. However, an external device could use a DMA channel to transfer data to or from an internal peripheral because the DMA generates the addresses. This transaction would be a two-cycle DMA bus transaction.

5-3

DEVICE CONFIGURATION

5.2.1.2 DMA Service to an SIO or SSIO Peripheral

A DMA unit is useful for ser vicing an SIO or SSIO peri pheral operatin g at a high baud rate . At high baud rates, the interrupt response time of the core may be too long to allow the seri al channels to use an interrupt to service the receive-bu ffer -full condition. By the time the interrupt service routine is ready to transfer the receive-buffer data to mem ory, new data would have been loaded into the buffer. By using an appropriately configured DMA channel , data transfers to and from the seri al c han nels c an oc cur wi thin a few bus c ycles of the t im e that a se rial unit i s re a dy to move data. SIO and SSIO inputs to the DM A are se lected by the DM A configurat ion regi ster (Figure 5-3).

5.2.1.3 Using The Timer To Initiate DMA Transfers

A timer output (OUT1, OUT2) can be used to initiate periodic data transfers by the DMA. A DMA channel is programmed for the transfer, and then a timer output pulse triggers the transfer. The most useful DM A and timer combinatio ns for this type of transfer are the peri odic timer modes (mode 2 and mo de 3) with the DMA block-transfer m ode programmed. See Cha pter 9,

“Timer/Counter Unit,” and Chapter 16, “DMA Controller,” for programming the peripherals.

5.2.1.4 Limitations Due To Pin Signal Multiplexing

Pin signal multiplexing can preclude the simultaneous use of a DMA channel and another peripheral or specific peripheral signa l (see Figure 5-2). For example , using DMA channel 1 with an external requestor device precludes using SIO channel 1 due to the multiplexed signal pairs DRQ/RXD1 and DACK1#/T XD1.

5-4

DMA

DREQ0

DMACFG.2:0

DMACFG.3

RXD0 TXD1

SSTBE (SSIO) OUT1 (TCU)

DEVICE CONFIGURATION

DRQ0

To SIO1

(DCD1#)*

DMAACK0#

DMACFG.6:4

DREQ1

DMACFG.7

DMAACK1#

DMAINT

End of Process

HOLD

Bus Arbiter

HLDA

Refresh Unit

REFRESH#

*Alternate pin signals are in parentheses.

RXD1 TXD0

SSRBF (SSIO) OUT2 (TCU)

To/From I/O Port 1

From CSU

From SIO1

From CSU

PINCFG.4

To SIO1

PINCFG.2

PINCFG.3

P1CFG.6

P1CFG.7

PINCFG.6

DACK0# (CS5#)

DRQ1 (RXD1)

DACK1# (TXD1)

EOP# (CTS1#)

HOLD (P1.6)

HLDA (P1.7)

REFRESH# (CS6#)

A2516-01

Figure 5-2. Configuration of DMA, Bus Arbiter, and Refresh Unit

5-5

DEVICE CONFIGURATION

DMA Configuration DMACFG

(read/write)

7 0

D1MSK D1REQ2 D1REQ1 D1REQ0 D0MSK D0REQ2 D0REQ1 D0REQ0

Bit

Number

7 D1MSK DMA Acknowledge 1 Mask:

6–4 D1REQ2 :0 DM A Cha nnel 1 Request Conn ecti on:

3 D0MSK DMA Acknowledge 0 Mask:

2–0 D0REQ2 :0 DM A Cha nnel 0 Request Conn ecti on:

Bit

Mnemonic

Setting this bit masks DMA channel 1’s ac knowled ge (DACK1#) signal. Useful when channel 1’s request (DRQ1) input is connected to an internal peripheral.

Connects one of the five possible hardware sources to channel 1’s request input (DREQ1).

000 = DRQ1 pin (external peripheral) 001 = SIO channel 1’s receive buffer full signal (RBF) 010 = SIO channel 0’s transmit buffer empty signal (TBE) 011 = SSIO receive holding buffer full signal (RHBF) 100 = TCU counter 2’s output signal (OUT2) 101 = reserved 110 = reserved 111 = reserved

Setting this bit masks DMA channel 0’s ac knowled ge (DACK0#) signal. Useful when channel 0’s request (DRQ0) input is connected to an internal peripheral.

Connects one of the five possible hardware sources to channel 0’s request input (DREQ0).

000 = DRQ0 pin (external peripheral) 001 = SIO channel 0’s receive buffer full signal (RBF) 010 = SIO channel 1’s transmit buffer empty signal (TBE) 011 = SSIO transmit holding buffer empty signal (THBE) 100 = TCU counter 1’s output signal (OUT1) 101 = reserved 110 = reserved 111 = reserved

Expanded Addr: PC/AT Addr:

Reset State:

Function

F830H — 00H

5-6

Figure 5-3. DMA Configuration Register

DEVICE CONFIGURATION

5.2.2 Interrupt Control Unit Con figurati on

The interrupt control unit (ICU) comprises two 8259A interrupt controllers connected in cascade, as shown in Figure 5-4. (See Chapter 8, “Inter rupt Control Unit,” for a description of the ICU.)

Figure 5-5 describes the interrupt configuration register (INTCFG).

The ICU receives requests from seven internal sources:

• three outputs from the timer/counter unit (OUT2:0)

• an output from each of the serial I/O units (SIOINT1:0)

• an output from the synchronous serial I/O unit (SSIOINT)

• an output from the DMA unit (DMAINT)

In addition, the ICU controls the interrupt sources on eight external pins:

• INT3:0 (multiplexe d with I/O port signals P3.5:2) are enabl ed or disabled by the P3C FG

• INT7:4 share their package pins with four TCU inputs: TMRGATE1, TMRCLK1,

TMRGATE0, and TMRCLK0. These signal pairs are not multiplexed; however, the pin inputs are enable d or disabled by the INTCFG register.

The three cascade output s (CAS2:0) should be e nabl ed when an exte rnal 8259A module is connected to one of the INT3:0 signals. The cascade outputs are then ORed with address lines A18:16 (see “Interrupt Acknowledge Cycle” on page 7-19 for details).

5-7

DEVICE CONFIGURATION

8259A

Master

IR0

IR1 IR2

IR3 IR4

OUT0 (TCU)

P3CFG.2

0 1

SIOINT1 SIOINT0

P3CFG.3

IR5

0 1

P3CFG.4

IR6

0 1

P3CFG.5

CAS2:0

IR7

0 1

INTCFG.0

0 1

INTCFG.1

SSIOINT

0 1

OUT1(TCU) OUT2(TCU) DMAINT

INT

8259A

Slave

IR0

IR1

IR2 IR3 IR4

INTCFG.2

IR5

CAS2:0

IR6

IR7

0 1

INTCFG.3

0 1

WDTOUT#

*Alternate pin signals are in parentheses.

INTCFG.7

A18:16

To/From I/O Port 3

To TCU

P3CFG.2

P3CFG.3

P3CFG.4

P3CFG.5

INT0 (P3.2)*

INT1 (P3.3)

INT2 (P3.4)

INT3 (P3.5)

INT4 (TMRCLK0)

INT5 (TMRGATE0)

INT6 (TMRCLK1)

INT7 (TMRGATE1)

CAS2:0 (A18:16)

A2522-01

5-8

Figure 5-4. Interrupt Control Unit Configuration

DEVICE CONFIGURATION

Interrupt Configuration INTCFG

(read/write)

Expanded Addr: PC/AT Addr:

Reset State:

F832H — 00H

7 0

CE — — — IR6 IR5 IR1 IR0

Bit

Number

Bit

Mnemonic

Function

7 CE Cascade Enable:

Setting this bit enables the cascade signals, providing access to external slave 82C59A devices. The cascade signals are used to address specific slaves. If enabled, slave IDs appear on the A18:16 address lines during interrupt acknowledge cycles.

6–4 — Reserved. These bits are u ndefined; for compatibility with future devices,

do not modify these bits.

3 IR6 Internal Slave IR6 Connection:

Setting this bit connects the INT7 pin to the slave IR6 signal. Clearing this bit connects V

to the slave IR6 signal.

2 IR5 Internal Slave IR5 Connection:

Setting this bit connects the INT6 pin to the slave IR5 signal. Clearing this bit connects V

to the slave IR5 signal.

1 IR1 Internal Slave IR1 Connection:

Setting this bit connects the INT5 pin to the slave IR1 signal. Clearing this bit connects the SSIO interrupt signal (SSIOINT) to the slave IR1 signal.

0 IR0 Internal Slave IR0 Connection:

Setting this bit connects the INT4 pin to the slave IR0 signal. Clearing this bit connects V

to the slave IR0 signal.

Figure 5-5. Interrupt Configuration Register

5-9

DEVICE CONFIGURATION

5.2.3 Timer/Cou nter Uni t Confi gu rati on

The three-channel timer/counter unit (TCU) and its configuration register (TMRCFG) are shown in Figure 5-6 and Figure 5-7. The clock in puts can be exte r nal signals (TMRCLK2:0) or the onchip programmable clock (PSCLK). All of the clock inputs can be held low, and the gate inputs can be held high by program ming bit s in the TM RCF G regi ster. Several of the time r si g nals g o to the interrupt control unit (see Figure 5-4 on page 5-8).

The channel-0 and channel-1 signal s are se lect ed indivi d ually. In contrast , the channel-2 signal s (TMRC LK2, TMRGAT E2, TMR OUT2) are sel ected as a group. Note that using the channel-2 signals precludes use of the coprocesso r signal s (PEREQ, BUSY#, and ERROR#). Also, y ou must choose individually bet ween interrupt inputs and timer clock signals (TMRC LK0/INT4, TMRCLK1/INT6) and between interrupt inputs and timer gate signals (TMRGATE0/INT5, TMRGATE1/INT7).

5-10

Timer/Counter

Unit

CLKIN0

GATE0

OUT0

CLKIN1

GATE1

OUT1

CLKIN2

GATE2

OUT2

*Alternate pin signals are in parentheses.

TMRCFG.7

TMRCFG.0

TMRCFG.1

To ICU

To/From I/O Port 3

TMRCFG.2

TMRCFG.3

To ICU, DMA

To/From I/O Port 3

TMRCFG.4

TMRCFG.5

To ICU, DMA

PSCLK

To Core

To ICU

DEVICE CONFIGURATION

TMRCLK0 (INT4)*

TMRGATE0 (INT5)

P3CFG.0

TMROUT0 (P3.0)

TMRCLK1 (INT6)

TMRGATE1 (INT7)

P3CFG.1

TMROUT1 (P3.1)

PINCFG.5

TMRCLK2 (PEREQ)

TMRGATE2 (BUSY#)

TMROUT2 (ERROR#)

A2517-01

Figure 5-6. Timer/Counter Unit Configurati on

5-11

DEVICE CONFIGURATION

Timer Configuration TMRCFG

(read/write)

7 0

TMRDIS — GT2CON CK2CON GT1CON CK1CON GT0CON CK0CON

Expanded Addr: PC/AT Addr:

Reset State:

F834H – 00H

Bit

Number

Bit

Mnemonic

Function

7 TMRDIS Timer Disable:

Setting this bit disables the CLK

signals.

CLK

sign als. Clearing this bi t enables t he

6— Reserved. This bit is undefined; for compatibility with future devices, do

not modify this bit.

5 GT2CON Gate 2 Connection:

Setting this bit connects GATE2 to the TMRGATE2 pin. Clearing this bit connects GATE2 to V

CC.

4 CK2CON Clock 2 Connection:

Clearing this bit connects CLK2 to the internal PSCLK signal. Setting this bit connects CLK2 to the TMRCLK2 pin.

3 GT1CON Gate 1 Connection:

Setting this bit connects GATE1 to the TMRGATE1 pin. Clearing this bit connects GATE1 to V

2 CK1CON Clock 1 Connection:

Clearing this bit connects CLK1 to the internal PSCLK signal. Setting this bit connects CLK1 to the TMRCLK1 pin.

1 GT0CON Gate 0 Connection:

Setting this bit connects GATE0 to the TMRGATE0 pin. Clearing this bit connects GATE0 to V

0 CK0CON Clock 0 Connection:

Clearing this bit connects CLK0 to the internal PSCLK signal. Setting this bit connects CLK0 to the TMRCLK0 pin.

5-12

Figure 5-7. Timer Confi guration Register

DEVICE CONFIGURATION

5.2.4 Asynchrono us Seri al I/O Co nfigur atio n

Figure 5-8 and Figure 5-9 show the configuratio n of the asynchronous serial I/O unit, consisting

of channels SIO0 and SIO1. Each channel has an output (SIOINT1, SIOINT2) to the inter rupt control unit (see Figure 5-4 on page 5-8). ( These signals do not go to package pins.) The value of SIOINTn is the value of one of the status signals (receiver line status, receiver buffer full, transmit buffer empty, modem status), where the selection is made by a priority circuit.

All of the SIO0 pins are multiplexed with I/O port signals. Note that using SIO1 precludes using DMA channel 1 for externa l DMA requests due to the multipl exing of the transm it and receive signals with DMA signals (RXD1/DRQ1, TXD1/DAC K1#). Also, using SIO1 modem signals RTS1#, DSR1 #, DTR1#, and RI1# precludes use of the SSIO signals.

5-13

DEVICE CONFIGURATION

SIO0

BCLKIN

Receive Data

Transmit Data

Clear to Send

Request to Send

Data Set Ready

SIOCFG.0

0 1

SIOINT0 to ICU

SIOCFG.6

0 1

SERCLK

To/From I/O Port 3

To/From I/O Port 2

To/From I/O Port 1

P3CFG.7

COMCLK (P3.7)*

P2CFG.5

RXD0 (P2.5)

P2CFG.6

TXD0 (P2.6)

P2CFG.7

CTS0# (P2.7)

P1CFG.1

RTS0# (P1.1)

P1CFG.3

DSR0# (P1.3)

Data Carrier

Detect

Data Terminal

Ready

Ring Indicator

*Alternate pin signals are in parentheses.

Figure 5-8. Serial I/O Unit 0 Configuration

5-14

P1CFG.0

0 1

To/From I/O Port 1

DCD0# (P1.0)

P1CFG.2

DTR0#

To/From I/O Port 1

(P1.2)

P1CFG.4

0 1

To/From I/O Port 1

RI0# (P1.4)

A2521-01

DEVICE CONFIGURATION

SIO1

BCLKIN

Receive Data

Transmit Data

Clear to Send

Request to Send

Data Set Ready

SIOCFG.1

0 1

SIOINT1 to ICU

SIOCFG.7

0 1

SERCLK

To/From I/O Port 3

To DMA

From DMA

To/From DMA

From SSIO

To/From SSIO

P3CFG.7

COMCLK (P3.7)*

RXD1 (DRQ1)

PINCFG.2

TXD1 (DACK1#)

PINCFG.3

CTS1# (EOP#)

PINCFG.0

RTS1# (SSIOTX)

DSR1# (STXCLK)

Data Carrier

Detect

0 1

Data Terminal

Ready

Ring Indicator

0 1

*Alternate pin signals are in parentheses.

Figure 5-9. Serial I/ O Unit 1 Configuratio n

To DMA

DCD1# (DRQ0)

PINCFG.1

DTR1#

To/From SSIO

To SSIO

(SRXCLK)

RI1# (SSIORX)

A2519-01

5-15

DEVICE CONFIGURATION

SIO and SSIO Configuration SIOCFG

(read/write)

7 0

S1M S0M — — — SSBSRC S1BSRC S0BSRC

Bit

Number

7 S1M SIO1 Modem Signal Connectio ns:

6 S0M SIO0 Modem Signal Connectio ns:

5–3 — Reserved. These bits are u ndefined; for compatibility with future devices,

2 SSBSRC SSIO Baud-rate Generator Clock Source:

1 S1BSRC SIO1 Baud-rate Generator Clock Source:

0 S0BSRC SIO0 Baud-rate Generator Clock Source:

Bit

Mnemonic

Setting this bit connects the SIO1 modem input signals internally. Clearing this bit connects the SIO1 modem input signals to the package pins.

Setting this bit connects the SIO0 modem input signals internally. Clearing this bit connects the SIO0 modem input signals to the package pins.

do not modify these bits.

Setting this bit connects the internal SERCLK signal to the SSIO baudrate generator. Clearing this bit connects the internal PSCLK signal to the SSIO baud-rate generator.

Setting this bit connects the internal SERCLK signal to the SIO1 baudrate generator. Clearing this bit connects the COMCLK pin to the SIO1 baud-rate generator.

Setting this bit connects the internal SERCLK signal to the SIO0 baudrate generator. Clearing this bit connects the COMCLK pin to the SIO0 baud-rate generator.

Expanded Addr: PC/AT Addr:

Reset State:

Function

F836H — 00H

5-16

Figure 5-10. SIO and SSIO Configuration Register

DEVICE CONFIGURATION

5.2.5 Serial Synch ron ou s I/O Con figu rati on

The synchronous serial I/O unit (SSIO) is shown in Figure 5-11. Its single configuration register bit is in the SIOCFG register (Table 5-10). The transmit buffer empty and receive buffer full signals (SSTBE and SSR BF) g o to t he DMA unit (Fi gure 5-2 on page 5- 5), an d an interrupt si gnal (SSIOINT) goes to the ICU (Figure 5-4 on page 5-8). As programmed in the SSIOCON1 register (see Chapt er 12), SSIOINT is asserted for one of two conditions: the receive buffer is full or the transmit buffer is empty. Note tha t usin g the SSIO signals prec ludes the use of four of the SIO1 modem signals.

SSIO

BCLKIN

Receive Data

Transmit Data

Transmit Clock

Receive Clock

*Alternate pin signals are in parentheses.

SIOCFG.2

0 1

Figure 5-11. SSIO Unit Configuration

PSCLK SERCLK

SSTBE (To DMA) SSRBF (To DMA) SSIOINT (To ICU)

From SIO1

From SSIO1

To SIO1

PINCFG.0

To SIO1

PINCFG.1

SSIORX (RI1#)*

SSIOTX (RTS1#)

STXCLK (DSR1#)

SRXCLK (DTR1#)

A2518-01

5-17

DEVICE CONFIGURATION

5.2.6 Core Configuration

Three coprocessor signals (ERROR #, PEREQ, and BU SY in Figure 5-12) can be routed to the core, as determined by bit 5 of the PINCFG register (see Figure 5-14 on page 5- 21). Due to signal multiplexing at the pins, the coprocess or and Timer 2 cannot be used in the same configuration.

Core

Error#

PEREQ

BUSY#

RESET

PINCFG.5

From TCU

To TCU

RESET Timing

Generation

From Internal Chip RESET

PORT92.1

PINCFG.5

ERROR# (TMROUT2#)*

PEREQ (TMRCLK2)

BUSY# (TMRGATE2)

PORT92.0

A20

*Alternate pin signals are in parentheses.

To Chip Select and A20 Pin

A2520-01

Figure 5-12. Core Configuration

Setting bit 0 in the PORT92 register (see Figure 5-13) resets the core without resetting the peripherals. Unlike t he RESET pin, whi ch is asynchronous and c an be used to synchroniz e internal clocks to CLK2, this core-only reset is synchronized with the on-chip clocks and does not affect the on-chip clock synchronization.

5-18

DEVICE CONFIGURATION

Clearing bit 1 in the PORT92 register forces addres s line 20 to 0. This bit affects only addresse s generated by the c ore. A ddresses gene rated by the DM A and t he refresh c ontrol u nit are not affected by this bit.

Port 92 Configuration PORT92

(read/write)

7 0

— — — — — — A20G CPURST

Bit

Number

7–2 — Reserved. These bits are u ndefined; for compatibility with future devices,

1 A20G A20 Grounded:

0 CPURST CPU Reset:

Bit

Mnemonic

do not modify these bits.

Setting this bit leaves core-generated addresses unmodified. Clearing this bit forces address line A20 to 0. This bit affects ad dresses generated only by the core. Addresses generated by the DMA and the Refresh Unit are not affected by this bit.

Setting this bit resets the core without resetting the peripherals. Clearing this bit has no effect.

Expanded Addr: PC/AT Addr:

Reset State:

Function

F092H 0092H 0EH

Figure 5-13. Port 92 Configuration Register

ERRATA (3/28/95) Figure 5-13 incorrectly showed Reset State as 00H; now correctly shows 0EH. Register bit 1 incorrectly shown as A20, now correctly shows A20G.

5-19

DEVICE CONFIGURATION

5.3 PI N CONFIGURATION

Most of the microprocessor’s pac kage pins support tw o signals. Some of these pins support two input signals with out a multiplexer. The se input-signal pairs are l isted in Table 5-1. The pin is connected to b oth peripheral inputs.

The remaining pins supporting two signals have multiplexe rs. For each suc h pin, a bit in a pin configuration register enables one of the signals. Figure 5-18 on page 5-27 lists t he bit s in eac h of the four pin configuration registers. These abbreviated regist er tables are dis cussed in “Con-

figuration Example” on page 5-25.

Table 5-1. Signal Pairs on Pins without Multiplexers

Names Signal Descripti ons

DRQ0/ DCD1#

DRQ1/ RXD1

DSR1#/ STXCLK

RI1#/ SSIORX

TMRCLK0/ INT4

TMRGATE0/ INT5

TMRCLK1/ INT6

TMRGATE1/ INT7

DMA External Request 0 indicates that an off-chip peripheral requires DMA service. Data Carrier Detect SIO1 indicates that the modem or data set has detected the

asynchronous serial channel’s data carrier.

DMA External Request1 indicates that an off-chip peripheral requires DMA service. Receive Data SIO1 accepts serial data from the modem or data set to the

asynchronous serial channel SIO1. Data Set Ready SIO1 indicates that the modem or data set is ready to establish a

communication link with asynchronous serial channel SIO1.

SSIO Transmit Clock synchronizes data being sent by the synchronous serial port. Ring Indicator SIO1 ind icate s that the modem or data set has received a telephone

ringing signal. SSIO Receive Serial Data accepts serial data (most-significant bit first) being sent to

the synchronous serial port. Timer/Coun ter Cloc k0 Input can serve as an external clock input for timer/counter0.

(The timer/counters can also be clocked internally.)

Interrupt 4 is an undedicated external interrupt. Timer/Counter0 Gate Input can control timer/counter0’s counting (enable, disable, or

trigger, depending on the programmed mode).

Interrupt 5 is an undedicated external interrupt. Timer/Coun ter Cloc k1 Input can serve as an external clock input for timer/counter1.

(The timer/counters can also be clocked internally.)

Interrupt 6 is an undedicated external interrupt. Timer/Counter0 Gate Input can control timer/counter1’s counting (enable, disable, or

trigger, depending on the programmed mode). Interrupt 7 is an undedicated external interrupt.

5-20

DEVICE CONFIGURATION

Pin Configuration PINCFG

(read/write)

7 0

— PM6 PM5 PM4 PM3 PM2 PM1 PM0

Bit

Number

7— Reserved. This bit is undefined; for compatibility with future devices, do

6 PM6 Pin Mod e:

5 PM5 Pin Mod e:

4 PM4 Pin Mod e:

3 PM3 Pin Mod e:

2 PM2 Pin Mod e:

1 PM1 Pin Mod e:

0 PM0 Pin Mod e:

Bit

Mnemonic

not modify this bit.

Setting this bit connects REFRESH# to the package pin. Clearing this bit connects CS6# to the package pin.

Setting this bit connects the timer control unit signal s, TMROUT2 , TMRCLK2, and TMRGATE2, to the package pins. Clearing this bit connects the coprocessor signals, PEREQ, BUSY# , and ERROR# , to the package pins.

Setting this bit connects CS5# to the package pin. Clearing this bit connects DACK0# to the package pin.

Setting this bit connects CTS1# to the packa ge pin. Cleari ng this bit connects EOP# to the package pin.

Setting this bit connects TXD1 to the package pin. Clearing this bit connects DACK1# to the package pin.

Setting this bit connects DTR1# to the package pin. Clearing this bit connects SRXCLK to the package pin.

Setting this bit connects RTS1# to the packa ge pin. Cleari ng this bit connects SSIOTX to the package pin.

Expanded Addr: PC/AT Addr:

Reset State:

Function

F826H — 00H

Figure 5-14. Pin Configuration Register

5-21

DEVICE CONFIGURATION

Port 1 Configuration P1CFG

(read/write)

7 0

PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

Bit

Number

7 PM7 Pin Mod e:

6 PM6 Pin Mod e:

5 PM5 Pin Mod e:

4 PM4 Pin Mod e:

3 PM3 Pin Mod e:

2 PM2 Pin Mod e:

1 PM1 Pin Mod e:

0 PM0 Pin Mod e:

Bit

Mnemonic

Setting this bit connects HLDA to the package pin. Clearing this bit connects P1.7 to the package pin.

Setting this bit connects HOLD to the package pin. C learing this bit connects P1.6 to the package pin.

Setting this bit connects LOCK# to the package pin. Clearing this bit connects P1.5 to the package pin.

Setting this bit connects RI0# to t he package pin. Clearing this bit connects P1.4 to the package pin.

Setting this bit connects DSR0# to the package pin. Clearing this bit connects P1.3 to the package pin.

Setting this bit connects DTR0# to the package pin. Clearing this bit connects P1.2 to the package pin.

Setting this bit connects RTS0# to the packa ge pin. Cleari ng this bit connects P1.1 to the package pin.

Setting this bit connects DCD0# to the package pin. Clearing this bit connects P1.0 to the package pin.

Expanded Addr: PC/AT Addr:

Reset State:

Function

F820H — 00H

5-22

Figure 5-15. Port 1 Configuration Register

DEVICE CONFIGURATION

Port 2 Configuration P2CFG

(read/write)

7 0

PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

Bit

Number

7 PM7 Pin Mod e:

6 PM6 Pin Mod e:

5 PM5 Pin Mod e:

4 PM4 Pin Mod e:

3 PM3 Pin Mod e:

2 PM2 Pin Mod e:

1 PM1 Pin Mod e:

0 PM0 Pin Mod e:

Bit

Mnemonic

Setting this bit connects CTS0# to the packa ge pin. Cleari ng this bit connects P2.7 to the package pin.

Setting this bit connects TXD0 to the package pin. Clearing this bit connects P2.6 to the package pin.

Setting this bit connects RXD0 to the package pin. Clearing this bit connects P2.5 to the package pin.

Setting this bit connects CS4# to the package pin. Clearing this bit connects P2.4 to the package pin.

Setting this bit connects CS3# to the package pin. Clearing this bit connects P2.3 to the package pin.

Setting this bit connects CS2# to the package pin. Clearing this bit connects P2.2 to the package pin.

Setting this bit connects CS1# to the package pin. Clearing this bit connects P2.1 to the package pin.

Setting this bit connects CS0# to the package pin. Clearing this bit connects P2.0 to the package pin.

Expanded Addr: PC/AT Addr:

Reset State:

Function

F822H — 00H

Figure 5-16. Port 2 Configuration Register

5-23

DEVICE CONFIGURATION

Port 3 Configuration P3CFG

(read/write)

7 0

PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

Bit

Number

7 PM7 Pin Mod e:

6 PM6 Pin Mod e:

5 PM5 Pin Mod e:

4 PM4 Pin Mod e:

3 PM3 Pin Mod e:

2 PM2 Pin Mod e:

1 PM1 Pin Mod e:

0 PM0 Pin Mod e:

Bit

Mnemonic

Setting this bit connects COMCLK to the package pin. Clear ing this bit connects P3.7 to the package pin.

Setting this bit connects PWRDOWN to the package pin. Clearing this bit connects P3.6 to the package pin.

Setting this bit connects INT3 to the package pin. Clearing this bit connects P3.5 to the package pin.

Setting this bit connects INT2 to the package pin. Clearing this bit connects P3.4 to the package pin.

Setting this bit connects INT1 to the package pin. Clearing this bit connects P3.3 to the package pin.

Setting this bit connects INT0 to the package pin. Clearing this bit connects P3.2 to the package pin.

Setting this bit connects TMROUT1 to the package pin. Cleari ng this bit connects P3.1 to the package pin.

Setting this bit connects TMROUT0 to the package pin. Cleari ng this bit connects P3.0 to the package pin.

Expanded Addr: PC/AT Addr:

Reset State:

Function

F824H — 00H

5-24

Figure 5-17. Port 3 Configuration Register

DEVICE CONFIGURATION

5.4 DEVICE CONFIGURATION PROCEDURE

Before configuring the microprocessor, you should make the following selections:

• the set of peripherals to be used

• the signals to be available at the package pins

• the desired peripheral-periphera l and peripheral-core connections

Although final decisions regarding these selections may be influenced by the possible configurations, we recommend that you initially make the selections without regard to limitations on the configurations.

We suggest the following procedure for configuring the device for your design. (“Configuration

Example” on page 5-25 introduces an aide for recording the steps in the procedure and shows an

example configuration.)

1. Pin Configuration. For each desired pin signal, consult the peripheral configuration

diagram to find the bit value in the pin configuration re gister that connec ts the signal to a device pin. If the signal shares a pin that has no multiplexer, make a note of its companion signal.

2. Peripheral Configuration. For each peripheral in your design, consult the peripheral

configuration diagram a nd the peripheral co nfiguration register to find the bit va lues for your desired internal connec tions.

3. Configura tion Revie w. Review the result s of steps 1 and 2 to see if the con fig uration

registers have conflicting bit values. If conflic ts exist, follow steps 3.1 and 3.2.

3.1. Attempt to resolve the pin configuration confl icts first. In some case s you may find that using a different peripheral channel resolve s the conflict (e.g., using SIO1 instead of SIO0, or DMA channel 0 instead of channel 1.

3.2. Attempt to resolve peripheral configuration conflicts.

If conflicts remain, consider peri pheral subst itutio ns (e.g. , SIO1 instead of SIO0, DM A c hannel 1 instead of channel 0) that may re solve them and return to step 1.

5.5 CONFIGURATION EXAMPLE

This section presents a n example of configuri ng the device for a PC/AT-c ompatibl e configuration. It also introduces an aide to execut ing the steps in the con figu ration process.

5-25

DEVICE CONFIGURATION

5.5.1 Example Design Req uirem en ts

The example is a PC/AT-compat i ble design with the f ollow ing requireme nts :

• Interrupt Control Unit:

— External interrupt inputs available at package pins: INT7:0. — Cascade outputs (CAS2:0) co nnected to package pins.

• Timer Control Unit:

— Counters 0, 1: Clock input is on-chip programmable clock (PSCLK); TMROUT0,

TMROUT1 connec ted to pac kage pins.

— Counter 2: Clock input is on-chip programmable clock (PSCLK); no signals connected

to package pins.

• DMA Unit:

— Request and acknowled ge signals fo r DMA channe l 0 (DRQ0, DACK0 #) connected to

package pins.

— End-of-process signal (EOP#) connected to a package pin.

• Asynchronous Serial I/O channel 0 (SIO0):

— Clock input is the seria l communic ations bau d clock (COMCL K ). — RXD0, TXD0, RTS0#, DSR0#, DCD0#, DTR0# and RI0# connected to package pins.

• Asynchronous Serial I/O channel 1(SIO1):

— Clock input is the seria l communic ations bau d clock (COMCL K ). — Mo dem signals internal l y connected.

• Synchronous Serial I/O (SSIO):

— Clock input is SERC LK . — SSIORX, SSIOTX, SRXCLK , and STXCLK connected to package pins.

• Chip Select:

— Chip select signals CS6#, CS4:0# connected to package pins.

• Core and Bus Arbiter:

— Coprocessor signals connected to package pins. — HOLD and HLDA# connected to package pins . — LOCK# and PWRDOWN c onnected to package pins.

5.5.2 Example Desi gn Soluti on

The example solution is given in three figures. In Figure 5-18 and Figure 5-19, the configuration register bit values are re corded in the abbreviated regist er tables. The resulting connections are shown in Figure 5-20. Figure 5-21 and Figure 5-22 are blank worksheets for your use.

5-26

DEVICE CONFIGURATION

P1CFG P2CFG P3CFG

0 = P1.7

1 = HLDA 1 = CTS0# 1 = COMCLK 0 = P1.6

1 = HOLD 1 = TXD0 1 = PWRDOWN 0 = P1.5

1 = LOCK# 1 = RXD0 1 = INT3 0 = P1.4

1 = RIO# 1 = CS4# 1 = INT2 0 = P1.3

1 = DSR0# 1 = CS3# 1 = INT1 0 = P1.2

1 = DTR0# 1 = CS2# 1 = INT0 0 = P1.1

1 = RTS0# 1 = CS1# 1 = TMROUT1 0 = P1.0

1 = DCD0# 1 = CS0# 1 = TMROUT0

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

0 = P2.7

0 = P2.6

0 = P2.5

0 = P2.4

0 = P2.3

0 = P2.2

0 = P2.1

0 = P2.0

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

0 = P3.7

0 = P3.6

0 = P3.5

0 = P3.4

0 = P3.3

0 = P3.2

0 = P3.1

0 = P3.0

PINCFG Pins w/o Muxes X Pins w/o Mux es X

7 Reserve d R

0 = CS6#

1 = REFRESH# RXD1 X INT5 X 0 = Coprocessor Sigs.

1 = TMR2 Signals 0 = DACK0#

1 = CS5# SSIORX X INT7 X 0 = EOP#

1 = CTS1# 0 = DACK1#

1 = TXD1 0 = SRXCLK

1 = DTR1# 0 = SSIOTX

1 = RTS1#

DRQ0 X TMRCL K0 DCD1# INT 4 X DRQ1 TMRGATE0

DSR1# TMRCLK1 STXCLK X INT6 X RI1# TMRGATE1

PEREQ, BUSY#, ERROR#

TMROUT2, TMRCLK2, TMRGATE2

Figure 5-18. Abbreviated Pin Configuration Register Tables

5-27

Intel 80386EX (386EX) User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual