Intel 80386 DX Datasheet

Intel386TMDX MICROPROCESSOR

32-BIT CHMOS MICROPROCESSOR

WITH INTEGRATED MEMORY MANAGEMENT

Flexible 32-Bit Microprocessor Ð 8, 16, 32-Bit Data Types Ð 8 General Purpose 32-Bit Registers

Very Large Address Space Ð 4 Gigabyte Physical Ð 64 Terabyte Virtual Ð 4 Gigabyte Maximum Segment Size

Integrated Memory Management Unit Ð Virtual Memory Support Ð Optional On-Chip Paging Ð 4 Levels of Protection Ð Fully Compatible with 80286

Object Code Compatible with All 8086 Family Microprocessors

Virtual 8086 Mode Allows Running of 8086 Software in a Protected and Paged System

Hardware Debugging Support

The Intel386 DX Microprocessor is an entry-level 32-bit microprocessor designed for single-user applications and operating systems such as MS-DOS and Windows. The 32-bit registers and data paths support 32-bit addresses and data types. The processor addresses up to four gigabytes of physical memory and 64 terabytes (2**46) of virtual memory. The integrated memory management and protection architecture includes address translation registers, multitasking hardware and a protection mechanism to support operating systems. Instruction pipelining, on-chip address translation, ensure short average instruction execution times and maximum system throughput.

The Intel386 DX CPU offers new testability and debugging features. Testability features include a self-test and direct access to the page translation cache. Four new breakpoint registers provide breakpoint traps on code execution or data accesses, for powerful debugging of even ROM-based systems.

Object-code compatibility with all 8086 family members (8086, 8088, 80186, 80188, 80286) means the Intel386 DX offers immediate access to the world’s largest microprocessor software base.

Optimized for System Performance Ð Pipelined Instruction Execution Ð On-Chip Address Translation Caches Ð 20, 25 and 33 MHz Clock Ð 40, 50 and 66 Megabytes/Sec Bus

Bandwidth

Numerics Support via Intel387TMDX Math Coprocessor

Complete System Development Support Ð Software: C, PL/M, Assembler

System Generation Tools

Ð Debuggers: PSCOPE, ICE

High Speed CHMOS IV Technology

132 Pin Grid Array Package

132 Pin Plastic Quad Flat Package

(See Packaging Specification, OrderÝ231369)

-386

Intel386TMDX Pipelined 32-Bit Microarchitecture

Intel386TMDX and Intel387TMDX are Trademarks of Intel Corporation. MS-DOS and Windows are Trademarks of MICROSOFT Corporation.

*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

231630– 49

Intel386TMDX MICROPROCESSOR

32-BIT CHMOS MICROPROCESSOR

WITH INTEGRATED MEMORY MANAGEMENT

CONTENTS PAGE

1. PIN ASSIGNMENT

1.1 Pin Description Table АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 6

2. BASE ARCHITECTURE ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 8

2.1 Introduction АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 8

2.2 Register Overview ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 8

2.3 Register Descriptions АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 9

2.4 Instruction Set АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 15

2.5 Addressing Modes АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 18

2.6 Data Types ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 20

2.7 Memory Organization ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 22

2.8 I/O Space АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 23

2.9 Interrupts ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 24

2.10 Reset and Initialization ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 27

2.11 Testability ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 28

2.12 Debugging Support АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 28

3. REAL MODE ARCHITECTURE ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 32

3.1 Real Mode Introduction ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 32

3.2 Memory Addressing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 33

3.3 Reserved Locations ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 34

3.4 Interrupts ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 34

3.5 Shutdown and Halt АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 34

4. PROTECTED MODE ARCHITECTURE ААААААААААААААААААААААААААААААААААААААААААААААААААА 34

4.1 Introduction ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 34

4.2 Addressing Mechanism ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 35

4.3 Segmentation ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 36

4.4 Protection АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 46

4.5 Paging АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 52

4.6 Virtual 8086 Environment ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 56

5. FUNCTIONAL DATA ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 61

5.1 Introduction ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 61

5.2 Signal Description АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 61

5.2.1 Introduction ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 61

5.2.2 Clock (CLK2) АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 62

5.2.3 Data Bus (D0 through D31) АААААААААААААААААААААААААААААААААААААААААААААААААААААА 62

5.2.4 Address Bus (BEOÝthrough BE3Ý, A2 through A31) АААААААААААААААААААААААААААА 62

5.2.5 Bus Cycle Definition Signals (W/RÝ, D/CÝ, M/IO, LOCKÝ) ААААААААААААААААААААА 63

5.2.6 Bus Control Signals (ADSÝ, READYÝ,NAÝ, BS16Ý) ААААААААААААААААААААААААААА 64

5.2.7 Bus Arbitration Signals (HOLD, HLDA) ААААААААААААААААААААААААААААААААААААААААААА 65

5.2.8 Coprocessor Interface Signals (PEREQ, BUSYÝ, ERRORÝ) ААААААААААААААААААААА 65

5.2.9 Interrupt Signals (INTR, NMI, RESET) АААААААААААААААААААААААААААААААААААААААААААА 66

5.2.10 Signal Summary АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 67

ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 5

CONTENTS PAGE

5. FUNCTIONAL DATA (Continued)

5.3. Bus Transfer Mechanism

5.3.1 Introduction ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 67

5.3.2 Memory and I/O Spaces ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 68

5.3.3 Memory and I/O Organization ААААААААААААААААААААААААААААААААААААААААААААААААААА 69

5.3.4 Dynamic Data Bus Sizing АААААААААААААААААААААААААААААААААААААААААААААААААААААААА 69

5.3.5 Interfacing with 32- and 16-bit Memories ААААААААААААААААААААААААААААААААААААААААА 70

5.3.6 Operand Alignment АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 71

5.4 Bus Functional Description АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 71

5.4.1 Introduction ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 71

5.4.2 Address Pipelining ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 74

5.4.3 Read and Write Cycles АААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 76

5.4.4 Interrupt Acknowledge (INTA) Cycles АААААААААААААААААААААААААААААААААААААААААААА 87

5.4.5 Halt Indication Cycle ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 88

5.4.6 Shutdown Indication Cycle ААААААААААААААААААААААААААААААААААААААААААААААААААААААА 89

5.5 Other Functional Descriptions ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 90

5.5.1 Entering and Exiting Hold Acknowledge АААААААААААААААААААААААААААААААААААААААААА 90

5.5.2 Reset during Hold Acknowledge ААААААААААААААААААААААААААААААААААААААААААААААААА 90

5.5.3 Bus Activity During and Following Reset ААААААААААААААААААААААААААААААААААААААААА 90

5.6 Self-test Signature АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 92

5.7 Component and Revision Identifiers ААААААААААААААААААААААААААААААААААААААААААААААААААА 92

5.8 Coprocessor Interface АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 94

5.8.1 Software Testing for Coprocessor Presence ААААААААААААААААААААААААААААААААААААА 94

6. INSTRUCTION SET АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 95

6.1 Instruction Encoding and Clock Count Summary ААААААААААААААААААААААААААААААААААААААА 95

6.2 Instruction Encoding Details ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 110

7. DESIGNING FOR ICETM-386 DX EMULATOR USE АААААААААААААААААААААААААААААААААААААА 117

8. MECHANICAL DATA АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 119

8.1 Introduction АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 119

8.2 Package Dimensions and Mounting АААААААААААААААААААААААААААААААААААААААААААААААААА 119

8.3 Package Thermal Specification АААААААААААААААААААААААААААААААААААААААААААААААААААААА 122

9. ELECTRICAL DATA АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 123

9.1 Introduction АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 123

9.2 Power and Grounding АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 123

9.3 Maximum Ratings АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 124

9.4 D.C. Specifications ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 124

9.5 A.C. Specifications ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 125

10. REVISION HISTORY ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 137

NOTE:

This is revision 011; This supercedes all previous revisions.

ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 67

1. PIN ASSIGNMENT

The Intel386 DX pinout as viewed from the top side of the component is shown by Figure 1-1. Its pinout as viewed from the Pin side of the component is Figure 1-2.

Intel386TMDX MICROPROCESSOR

and GND connections must be made to multi-

ple V must be connected to the appropriate voltage level. The circuit board should include V planes for power distribution and all V pins must be connected to the appropriate plane.

Pins identified as ‘‘N.C.’’ should remain completely unconnected.

and VSS(GND) pins. Each VCCand V

NOTE:

and GND

and V

231630– 33

Figure 1-1. Intel386TMDX PGA

PinoutÐView from Top Side

Table 1-1. Intel386

Signal/Pin Signal/Pin Signal/Pin Signal/Pin Signal/Pin Signal/Pin

A2 C4 A24 L2 D6 L14 D28 M6 V A3 A3 A25 K3 D7 K12 D29 P4 D12 F3 A4 B3 A26 M1 D8 L13 D30 P3 G2 F14 A5 B2 A27 N1 D9 N14 D31 M5 G3 J2 A6 C3 A28 L3 D10 M12 D/C A7 C2 A29 M2 D11 N13 ERROR A8 C1 A30 P1 D12 N12 HLDA M14 L12 J13 A9 D3 A31 N2 D13 P13 HOLD D14 M3 M4 A10 D2 ADS A11 D1 BE0 A12 E3 BE1 A13 E2 BE2 A14 E1 BE3 A15 F1 BS16 A16 G1 BUSY A17 H1 CLK2 F12 D21 N9 RESET C9 A6 B4 A18 H2 D0 H12 D22 P9 V A19 H3 D1 H13 D23 N8 A5 B1 B12 A20 J1 D2 H14 D24 P7 A7 B5 C6 A21 K1 D3 J14 D25 N6 A10 B11 C7 A22 K2 D4 K14 D26 P5 A14 B14 E13 A23 L1 D5 K13 D27 N5 C5 C11 F13

E14 D14 P12 INTR B7 M7 M8

E12 D15 M11 LOCK

C13 D16 N11 M/IO

B13 D17 N10 NA

A13 D18 P11 NMI B8 P2 P14

C14 D19 P10 PEREQ C8 P8 W/R

B9 D20 M9 READY

DX PGA PinoutÐFunctional Grouping

Figure 1-2. Intel386TMDX PGA

PinoutÐView from Pin Side

C12 V

A11 G12 J3

A8 G14 J12

C10 M13 M10 A12 N4 N3 D13 N7 P6

G13 V

A1 A9 B6

A2 N.C. A4

231630– 34

B10

Intel386TMDX MICROPROCESSOR

1.1 PIN DESCRIPTION TABLE

The following table lists a brief description of each pin on the Intel386 DX. The following definitions are used in these descriptions:

The named signal is active LOW. I Input signal. O Output signal. I/O Input and Output signal. Ð No electrical connection.

For a more complete description refer to Section 5.2 Signal Description.

Symbol Type Name and Function

CLK2 I CLK2 provides the fundamental timing for the Intel386 DX.

D31–D

A31–A

BE0Ý–BE3

W/R

D/C

M/IO

LOCK

ADS

READY

BS16

HOLD I BUS HOLD REQUEST input allows another bus master to request

I/O DATA BUS inputs data during memory, I/O and interrupt acknowledge

read cycles and outputs data during memory and I/O write cycles.

O ADDRESS BUS outputs physical memory or port I/O addresses.

O BYTE ENABLES indicate which data bytes of the data bus take part in

a bus cycle.

O WRITE/READ is a bus cycle definition pin that distinguishes write

cycles from read cycles.

O DATA/CONTROL is a bus cycle definition pin that distinguishes data

cycles, either memory or I/O, from control cycles which are: interrupt acknowledge, halt, and instruction fetching.

O MEMORY I/O is a bus cycle definition pin that distinguishes memory

cycles from input/output cycles.

O BUS LOCK is a bus cycle definition pin that indicates that other

system bus masters are denied access to the system bus while it is active.

O ADDRESS STATUS indicates that a valid bus cycle definition and

address (W/R A

31–A2

, D/CÝ, M/IOÝ, BE0Ý, BE1Ý, BE2Ý, BE3Ýand

) are being driven at the Intel386 DX pins.

I NEXT ADDRESS is used to request address pipelining.

I BUS READY terminates the bus cycle.

I BUS SIZE 16 input allows direct connection of 32-bit and 16-bit data

buses.

control of the local bus.

Intel386TMDX MICROPROCESSOR

1.1 PIN DESCRIPTION TABLE (Continued)

Symbol Type Name and Function

HLDA O BUS HOLD ACKNOWLEDGE output indicates that the Intel386 DX

BUSY

ERROR

I BUSY signals a busy condition from a processor extension.

I ERROR signals an error condition from a processor extension.

PEREQ I PROCESSOR EXTENSION REQUEST indicates that the processor

INTR I INTERRUPT REQUEST is a maskable input that signals the Intel386

NMI I NON-MASKABLE INTERRUPT REQUEST is a non-maskable input

RESET I RESET suspends any operation in progress and places the Intel386

N/C Ð NO CONNECT should always remain unconnected. Connection of a

I SYSTEM POWER provides thea5V nominal D.C. supply input.

I SYSTEM GROUND provides 0V connection from which all inputs and

has surrendered control of its local bus to another bus master.

extension has data to be transferred by the Intel386 DX.

DX to suspend execution of the current program and execute an interrupt acknowledge function.

that signals the Intel386 DX to suspend execution of the current program and execute an interrupt acknowledge function.

DX in a known reset state. See Interrupt Signals for additional information.

N/C pin may cause the processor to malfunction or be incompatible with future steppings of the Intel386 DX.

outputs are measured.

Intel386TMDX MICROPROCESSOR

2. BASE ARCHITECTURE

2.1 INTRODUCTION

The Intel386 DX consists of a central processing unit, a memory management unit and a bus interface.

The central processing unit consists of the execution unit and instruction unit. The execution unit contains the eight 32-bit general purpose registers which are used for both address calculation, data operations and a 64-bit barrel shifter used to speed shift, rotate, multiply, and divide operations. The multiply and divide logic uses a 1-bit per cycle algorithm. The multiply algorithm stops the iteration when the most significant bits of the multiplier are all zero. This allows typical 32-bit multiplies to be executed in under one microsecond. The instruction unit decodes the instruction opcodes and stores them in the decoded instruction queue for immediate use by the execution unit.

The memory management unit (MMU) consists of a segmentation unit and a paging unit. Segmentation allows the managing of the logical address space by providing an extra addressing component, one that allows easy code and data relocatability, and efficient sharing. The paging mechanism operates beneath and is transparent to the segmentation process, to allow management of the physical address space. Each segment is divided into one or more 4K byte pages. To implement a virtual memory system, the Intel386 DX supports full restartability for all page and segment faults.

Memory is organized into one or more variable length segments, each up to four gigabytes in size. A given region of the linear address space, a segment, can have attributes associated with it. These attributes include its location, size, type (i.e. stack, code or data), and protection characteristics. Each task on an Intel386 DX can have a maximum of 16,381 segments of up to four gigabytes each, thus providing 64 terabytes (trillion bytes) of virtual memory to each task.

The segmentation unit provides four-levels of protection for isolating and protecting applications and the operating system from each other. The hardware enforced protection allows the design of systems with a high degree of integrity.

The Intel386 DX has two modes of operation: Real Address Mode (Real Mode), and Protected Virtual Address Mode (Protected Mode). In Real Mode the Intel386 DX operates as a very fast 8086, but with

32-bit extensions if desired. Real Mode is required primarily to setup the processor for Protected Mode operation. Protected Mode provides access to the sophisticated memory management, paging and privilege capabilities of the processor.

Within Protected Mode, software can perform a task switch to enter into tasks designated as Virtual 8086 Mode tasks. Each such task behaves with 8086 semantics, thus allowing 8086 software (an application program, or an entire operating system) to execute. The Virtual 8086 tasks can be isolated and protected from one another and the host Intel386 DX operating system, by the use of paging, and the I/O Permission Bitmap.

Finally, to facilitate high performance system hardware designs, the Intel386 DX bus interface offers address pipelining, dynamic data bus sizing, and direct Byte Enable signals for each byte of the data bus. These hardware features are described fully beginning in Section 5.

2.2 REGISTER OVERVIEW

The Intel386 DX has 32 register resources in the following categories:

General Purpose Registers

Segment Registers

Instruction Pointer and Flags

Control Registers

System Address Registers

Debug Registers

Test Registers.

The registers are a superset of the 8086, 80186 and 80286 registers, so all 16-bit 8086, 80186 and 80286 registers are contained within the 32-bit Intel386 DX.

Figure 2-1 shows all of Intel386 DX base architecture registers, which include the general address and data registers, the instruction pointer, and the flags register. The contents of these registers are task-specific, so these registers are automatically loaded with a new context upon a task switch operation.

The base architecture also includes six directly accessible segments, each up to 4 Gbytes in size. The segments are indicated by the selector values placed in Intel386 DX segment registers of Figure 2-1. Various selector values can be loaded as a program executes, if desired.

Intel386TMDX MICROPROCESSOR

GENERAL DATA AND ADDRESS REGISTERS 31 16 15 0

AX EAX

BX EBX

CX ECX

DX EDX

SI ESI

DI EDI

BP EBP

SP ESP

SEGMENT SELECTOR REGISTERS

INSTRUCTION POINTER AND FLAGS REGISTER 31 16 15 0

The selectors are also task-specific, so the segment registers are automatically loaded with new context upon a task switch operation.

The other types of registers, Control, System Address, Debug, and Test, are primarily used by system software.

15 0

CS CODE

SS STACK

IP EIP

FLAGS EFLAGS

Figure 2-1. Intel386TMDX Base

Architecture Registers

DATA

2.3 REGISTER DESCRIPTIONS

2.3.1 General Purpose Registers

General Purpose Registers: The eight general pur-

pose registers of 32 bits hold data or address quantities. The general registers, Figure 2-2, support data operands of 1, 8, 16, 32 and 64 bits, and bit fields of 1 to 32 bits. They support address operands of 16 and 32 bits. The 32-bit registers are named EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP.

The least significant 16 bits of the registers can be accessed separately. This is done by using the 16bit names of the registers AX, BX, CX, DX, SI, DI,

BP, and SP. When accessed as a 16-bit operand, the upper 16 bits of the register are neither used nor changed.

Finally 8-bit operations can individually access the lowest byte (bits 0–7) and the higher byte (bits 8–

15) of general purpose registers AX, BX, CX and DX. The lowest bytes are named AL, BL, CL and DL, respectively. The higher bytes are named AH, BH, CH and DH, respectively. The individual byte accessibility offers additional flexibility for data operations, but is not used for effective address calculation.

31 16 15 8 7 0

AH A X AL EAX

BH B X BL EBX

CH C X CL ECX

DH D X DL EDX

SI ESI

DI EDI

BP EBP

SP ESP

31 16 15 0

EIP

X ä Y

Figure 2-2. General Registers

and Instruction Pointer

2.3.2 Instruction Pointer

The instruction pointer, Figure 2-2, is a 32-bit register named EIP. EIP holds the offset of the next instruction to be executed. The offset is always relative to the base of the code segment (CS). The lower 16 bits (bits 0–15) of EIP contain the 16-bit instruction pointer named IP, which is used by 16-bit addressing.

2.3.3 Flags Register

The Flags Register is a 32-bit register named EFLAGS. The defined bits and bit fields within EFLAGS, shown in Figure 2-3, control certain operations and indicate status of the Intel386 DX. The lower 16 bits (bit 0 – 15) of EFLAGS contain the 16-bit flag register named FLAGS, which is most useful when executing 8086 and 80286 code.

Intel386TMDX MICROPROCESSOR

NOTE:

0 indicates Intel reserved: do not define; see section 2.3.10.

Figure 2-3. Flags Register

231630– 50

VM (Virtual 8086 Mode, bit 17)

The VM bit provides Virtual 8086 Mode within Protected Mode. If set while the Intel386 DX is in Protected Mode, the Intel386 DX will switch to Virtual 8086 operation, handling segment loads as the 8086 does, but generating exception 13 faults on privileged opcodes. The VM bit can be set only in Protected Mode, by the IRET instruction (if current privilege level

0) and by task switches at any privilege level. The VM bit is unaffected by POPF. PUSHF always pushesa0inthis bit, even if executing in virtual 8086 Mode. The EFLAGS image pushed during interrupt processing or saved during task switches will containa1inthis bit if the interrupted code was executing as a Virtual 8086 Task.

RF (Resume Flag, bit 16)

The RF flag is used in conjunction with the debug register breakpoints. It is checked at instruction boundaries before breakpoint processing. When RF is set, it causes any debug fault to be ignored on the next instruction. RF is then automatically reset at the successful completion of every instruction (no faults are signalled) except the IRET instruction, the POPF instruction, (and JMP, CALL, and INT instructions causing a task switch). These instructions set RF to the value specified by the memory image. For example, at the end of the breakpoint service routine, the IRET

instruction can pop an EFLAG image having the RF bit set and resume the program’s execution at the breakpoint address without generating another breakpoint fault on the same location.

NT (Nested Task, bit 14)

This flag applies to Protected Mode. NT is set to indicate that the execution of this task is nested within another task. If set, it indicates that the current nested task’s Task State Segment (TSS) has a valid back link to the previous task’s TSS. This bit is set or reset by control transfers to other tasks. The value of NT in EFLAGS is tested by the IRET instruction to determine whether to do an inter-task return or an intra-task return. A POPF or an IRET instruction will affect the setting of this bit according to the image popped, at any privilege level.

IOPL (Input/Output Privilege Level, bits 12-13)

This two-bit field applies to Protected Mode. IOPL indicates the numerically maximum CPL (current privilege level) value permitted to execute I/O instructions without generating an exception 13 fault or consulting the I/O Permission Bitmap. It also indicates the maximum CPL value allowing alteration of the IF (INTR Enable Flag) bit when new values are popped into the EFLAG register. POPF and IRET instruction can alter the IOPL field when executed at CPL

0. Task switches can always alter the IOPL field, when the new flag image is loaded from the incoming task’s TSS.

Intel386TMDX MICROPROCESSOR

OF (Overflow Flag, bit 11)

OF is set if the operation resulted in a signed overflow. Signed overflow occurs when the operation resulted in carry/borrow into the sign bit (high-order bit) of the result but did not result in a carry/borrow out of the highorder bit, or vice-versa. For 8/16/32 bit operations, OF is set according to overflow at bit 7/15/31, respectively.

DF (Direction Flag, bit 10)

DF defines whether ESI and/or EDI registers postdecrement or postincrement during the string instructions. Postincrement occurs if DF is reset. Postdecrement occurs if DF is set.

IF (INTR Enable Flag, bit 9)

The IF flag, when set, allows recognition of external interrupts signalled on the INTR pin. When IF is reset, external interrupts signalled on the INTR are not recognized. IOPL indicates the maximum CPL value allowing alteration of the IF bit when new values are popped into EFLAGS or FLAGS.

TF (Trap Enable Flag, bit 8)

TF controls the generation of exception 1 trap when single-stepping through code. When TF is set, the Intel386 DX generates an exception 1 trap after the next instruction is executed. When TF is reset, exception 1 traps occur only as a function of the breakpoint addresses loaded into debug registers DR0–DR3.

SF (Sign Flag, bit 7)

SF is set if the high-order bit of the result is set, it is reset otherwise. For 8-, 16-, 32-bit operations, SF reflects the state of bit 7, 15, 31 respectively.

ZF (Zero Flag, bit 6)

ZF is set if all bits of the result are 0. Otherwise it is reset.

AF (Auxiliary Carry Flag, bit 4)

The Auxiliary Flag is used to simplify the addition and subtraction of packed BCD quantities. AF is set if the operation resulted in a carry out of bit 3 (addition) or a borrow into bit 3 (subtraction). Otherwise AF is reset. AF is affected by carry out of, or borrow into bit 3 only, regardless of overall operand length: 8, 16 or 32 bits.

PF (Parity Flags, bit 2)

PF is set if the low-order eight bits of the operation contains an even number of ‘‘1’s’’ (even parity). PF is reset if the low-order eight bits have odd parity. PF is a function of only the low-order eight bits, regardless of operand size.

CF (Carry Flag, bit 0)

CF is set if the operation resulted in a carry out of (addition), or a borrow into (subtraction) the high-order bit. Otherwise CF is reset. For 8-, 16- or 32-bit operations, CF is set according to carry/borrow at bit 7, 15 or 31, respectively.

Note in these descriptions, ‘‘set’’ means ‘‘set to 1,’’ and ‘‘reset’’ means ‘‘reset to 0.’’

2.3.4 Segment Registers

Six 16-bit segment registers hold segment selector values identifying the currently addressable memory segments. Segment registers are shown in Figure 2-

4. In Protected Mode, each segment may range in size from one byte up to the entire linear and physi-

SEGMENT

REGISTERS DESCRIPTOR REGISTERS (LOADED AUTOMATICALLY)

V â WV â W

15 0 Physical Base Address Segment Limit Attributes from Descriptor

Selector CS– Ð

Selector SS– Ð Ð

Selector DS – Ð Ð Ð

Selector ES– Ð Ð Ð

Selector FS – Ð Ð Ð

Selector GS – Ð Ð Ð

Figure 2-4. Intel386TMDX Segment Registers, and Associated Descriptor Registers

Other

Segment

Intel386TMDX MICROPROCESSOR

cal space of the machine, 4 Gbytes (232bytes). If a maximum sized segment is used (limit FFFFFFFFH) it should be Dword aligned (i.e., the least two significant bits of the segment base should be zero). This will avoid a segment limit violation (exception 13) caused by the wrap around. In Real Address Mode, the maximum segment size is fixed at 64 Kbytes (2

The six segments addressable at any given moment are defined by the segment registers CS, SS, DS, ES, FS and GS. The selector in CS indicates the current code segment; the selector in SS indicates the current stack segment; the selectors in DS, ES, FS and GS indicate the current data segments.

bytes).

2.3.5 Segment Descriptor Registers

The segment descriptor registers are not programmer visible, yet it is very useful to understand their content. Inside the Intel386 DX, a descriptor register (programmer invisible) is associated with each programmer-visible segment register, as shown by Figure 2-4. Each descriptor register holds a 32-bit segment base address, a 32-bit segment limit, and the other necessary segment attributes.

When a selector value is loaded into a segment register, the associated descriptor register is automatically updated with the correct information. In Real Address Mode, only the base address is updated directly (by shifting the selector value four bits to the left), since the segment maximum limit and attributes are fixed in Real Mode. In Protected Mode, the base address, the limit, and the attributes are all updated per the contents of the segment descriptor indexed by the selector.

Whenever a memory reference occurs, the segment descriptor register associated with the segment being used is automatically involved with the memory reference. The 32-bit segment base address becomes a component of the linear address calcula-

tion, the 32-bit limit is used for the limit-check opera-

tion, and the attributes are checked against the type of memory reference requested.

2.3.6 Control Registers

The Intel386 DX has three control registers of 32 bits, CR0, CR2 and CR3, to hold machine state of a global nature (not specific to an individual task). These registers, along with System Address Registers described in the next section, hold machine state that affects all tasks in the system. To access the Control Registers, load and store instructions are defined.

CR0: Machine Control Register (includes 80286 Machine Status Word)

CR0, shown in Figure 2-5, contains 6 defined bits for control and status purposes. The low-order 16 bits of CR0 are also known as the Machine Status Word, MSW, for compatibility with 80286 Protected Mode. LMSW and SMSW instructions are taken as special aliases of the load and store CR0 operations, where only the low-order 16 bits of CR0 are involved. For compatibility with 80286 operating systems the Intel386 DX LMSW instructions work in an identical fashion to the LMSW instruction on the 80286. (i.e. It only operates on the low-order 16-bits of CR0 and it ignores the new bits in CR0.) New Intel386 DX operating systems should use the MOV CR0, Reg instruction.

The defined CR0 bits are described below.

PG (Paging Enable, bit 31)

the PG bit is set to enable the on-chip paging unit. It is reset to disable the on-chip paging unit.

R (reserved, bit 4)

This bit is reserved by Intel. When loading CR0 care should be taken to not alter the value of this bit.

31 24 23 16 15 8 7 0

00000000000000000000000000R

G SMPE

TEMP

X ä Y

MSW

NOTE: 0 indicates Intel reserved: Do not define; SEE SECTION 2.3.10

Figure 2-5. Control Register 0

CR0

Intel386TMDX MICROPROCESSOR

TS (Task Switched, bit 3)

TS is automatically set whenever a task switch operation is performed. If TS is set, a coprocessor ESCape opcode will cause a Coprocessor Not Available trap (exception 7). The trap handler typically saves the Intel387 DX coprocessor context belonging to a previous task, loads the Intel387 DX coprocessor state belonging to the current task, and clears the TS bit before returning to the faulting coprocessor opcode.

EM (Emulate Coprocessor, bit 2)

The EMulate coprocessor bit is set to cause all coprocessor opcodes to generate a Coprocessor Not Available fault (exception 7). It is reset to allow coprocessor opcodes to be executed on an actual Intel387 DX coprocessor (this is the default case after reset). Note that the WAIT opcode is not affected by the EM bit setting.

MP (Monitor Coprocessor, bit 1)

The MP bit is used in conjunction with the TS bit to determine if the WAIT opcode will generate a Coprocessor Not Available fault (exception 7) when TS

1, the WAIT opcode generates a trap.

TS Otherwise, the WAIT opcode does not generate a trap. Note that TS is automatically set whenever a task switch operation is performed.

PE (Protection Enable, bit 0)

The PE bit is set to enable the Protected Mode. If PE is reset, the processor operates again in Real Mode. PE may be set by loading MSW or CR0. PE can be reset only by a load into CR0. Resetting the PE bit is typically part of a longer instruction sequence needed for proper transition from Protected Mode to Real Mode. Note that for strict 80286 compatibility, PE cannot be reset by the LMSW instruction.

CR1: reserved

CR1 is reserved for use in future Intel processors.

CR2: Page Fault Linear Address

CR2, shown in Figure 2-6, holds the 32-bit linear address that caused the last page fault detected. The

1. When both MPe1 and

error code pushed onto the page fault handler’s stack when it is invoked provides additional status information on this page fault.

CR3: Page Directory Base Address

CR3, shown in Figure 2-6, contains the physical base address of the page directory table. The Intel386 DX page directory table is always pagealigned (4 Kbyte-aligned). Therefore the lowest twelve bits of CR3 are ignored when written and they store as undefined.

A task switch through a TSS which changes the value in CR3, or an explicit load into CR3 with any value, will invalidate all cached page table entries in the paging unit cache. Note that if the value in CR3 does not change during the task switch, the cached page table entries are not flushed.

2.3.7 System Address Registers

Four special registers are defined to reference the tables or segments supported by the 80286 CPU and Intel386 DX protection model. These tables or segments are:

GDT (Global Descriptor Table),

IDT (Interrupt Descriptor Table),

LDT (Local Descriptor Table),

TSS (Task State Segment).

The addresses of these tables and segments are stored in special registers, the System Address and System Segment Registers illustrated in Figure 2-7. These registers are named GDTR, IDTR, LDTR and TR, respectively. Section 4 Protected Mode Archi-

tecture describes the use of these registers.

GDTR and IDTR

These registers hold the 32-bit linear base address and 16-bit limit of the GDT and IDT, respectively.

The GDT and IDT segments, since they are global to all tasks in the system, are defined by 32-bit linear addresses (subject to page translation if paging is enabled) and 16-bit limit values.

31 24 23 16 15 8 7 0

PAGE FAULT LINEAR ADDRESS REGISTER CR2

PAGE DIRECTORY BASE REGISTER 0 0 0 0 0 0 0 0 0 0 0 0 CR3

NOTE: 0 indicates Intel reserved: Do not define; SEE SECTION 2.3.10

Figure 2-6. Control Registers 2 and 3

Intel386TMDX MICROPROCESSOR

47 32-BIT LINEAR BASE ADDRESS 16 15 LIMIT 0

SYSTEM ADDRESS REGISTERS

GDTR

IDTR

SYSTEM SEGMENT

REGISTERS DESCRIPTOR REGISTERS (AUTOMATICALLY LOADED)

V â WV â W

15 0 32-BIT LINEAR BASE ADDRESS 32-BIT SEGMENT LIMIT ATTRIBUTES

TR SELECTOR

LDTR SELECTOR

Figure 2-7. System Address and System Segment Registers

LDTR and TR

These registers hold the 16-bit selector for the LDT descriptor and the TSS descriptor, respectively.

The LDT and TSS segments, since they are taskspecific segments, are defined by selector values stored in the system segment registers. Note that a segment descriptor register (programmer-invisible) is associated with each system segment register.

2.3.8 Debug and Test Registers

Debug Registers: The six programmer accessible

debug registers provide on-chip support for debugging. Debug Registers DR0 – 3 specify the four linear breakpoints. The Debug Control Register DR7 is used to set the breakpoints and the Debug Status Register DR6, displays the current state of the breakpoints. The use of the debug registers is described in section 2.12 Debugging support.

DEBUG REGISTERS 31 0

LINEAR BREAKPOINT ADDRESS 0 DR0

LINEAR BREAKPOINT ADDRESS 1 DR1

LINEAR BREAKPOINT ADDRESS 2 DR2

LINEAR BREAKPOINT ADDRESS 3 DR3

Intel reserved. Do not define. DR4

Intel reserved. Do not define. DR5

BREAKPOINT STATUS DR6

BREAKPOINT CONTROL DR7

TEST REGISTERS (FOR PAGE CACHE) 31 0

TEST CONTROL TR6

TEST STATUS TR7

Test Registers: Two registers are used to control the testing of the RAM/CAM (Content Addressable Memories) in the Translation Lookaside Buffer portion of the Intel386 DX. TR6 is the command test register, and TR7 is the data register which contains the data of the Translation Lookaside buffer test. Their use is discussed in section 2.11 Testability.

Figure 2-8 shows the Debug and Test registers.

2.3.9 Register Accessibility

There are a few differences regarding the accessibility of the registers in Real and Protected Mode. Table 2-1 summarizes these differences. See Section 4 Protected Mode Architecture for further details.

2.3.10 Compatibility

VERY IMPORTANT NOTE:

COMPATIBILITY WITH FUTURE PROCESSORS

In the preceding register descriptions, note certain Intel386 DX register bits are Intel reserved. When reserved bits are called out, treat them as fully undefined. This is essential for your software compatibility with future processors! Follow the guidelines below:

1) Do not depend on the states of any undefined bits when testing the values of defined register bits. Mask them out when testing.

2) Do not depend on the states of any undefined bits when storing them to memory or another register.

3) Do not depend on the ability to retain information written into any undefined bits.

4) When loading registers always load the undefined bits as zeros.

Figure 2-8. Debug and Test Registers

Intel386TMDX MICROPROCESSOR

Table 2-1. Register Usage

Use in Use in Use in

General Registers Yes Yes Yes Yes Yes Yes

Segment Registers Yes Yes Yes Yes Yes Yes

Flag Register Yes Yes Yes Yes IOPL* IOPL*

Control Registers Yes Yes PLe0PL

GDTR Yes Yes PLe0 Yes No Yes

IDTR Yes Yes PLe0 Yes No Yes

LDTR No No PLe0 Yes No No

TR No No PLe0 Yes No No

Debug Control Yes Yes PLe0PL

Test Registers Yes Yes PLe0PL

NOTES:

0: The registers can be accessed only when the current privilege level is zero.

PL *IOPL: The PUSHF and POPF instructions are made I/O Privilege Level sensitive in Virtual 8086 Mode.

Real Mode Protected Mode Virtual 8086 Mode

Load Store Load Store Load Store

0 No Yes

0No No

5) However, registers which have been previously stored may be reloaded without masking.

Depending upon the values of undefined register bits will make your software dependent upon the unspecified Intel386 DX handling of these bits. Depending on undefined values risks making your software incompatible with future processors that define usages for the Intel386 DXundefined bits. AVOID ANY SOFTWARE DEPENDENCE UPON THE STATE OF UNDEFINED Intel386 DX REGISTER BITS.

2.4 INSTRUCTION SET

2.4.1 Instruction Set Overview

The instruction set is divided into nine categories of operations:

Data Transfer

Arithmetic

Shift/Rotate

String Manipulation

Bit Manipulation

Control Transfer

High Level Language Support

Operating System Support

Processor Control

These Intel386 DX instructions are listed in Table 2-2.

All Intel386 DX instructions operate on either 0, 1, 2, or 3 operands; where an operand resides in a register, in the instruction itself, or in memory. Most zero operand instructions (e.g. CLI, STI) take only one byte. One operand instructions generally are two bytes long. The average instruction is 3.2 bytes long. Since the Intel386 DX has a 16-byte instruction queue, an average of 5 instructions will be prefetched. The use of two operands permits the following types of common instructions:

Memory to Register

Immediate to Register

Immediate to Memory.

The operands can be either 8, 16, or 32 bits long. As a general rule, when executing code written for the Intel386 DX (32-bit code), operands are 8 or 32 bits; when executing existing 80286 or 8086 code (16-bit code), operands are 8 or 16 bits. Prefixes can be added to all instructions which override the default length of the operands, (i.e. use 32-bit operands for 16-bit code, or 16-bit operands for 32-bit code).

For a more elaborate description of the instruction set, refer to the

Intel386 DX Programmer’s Refer-

ence Manual.

Intel386TMDX MICROPROCESSOR

2.4.2 Intel386TMDX Instructions

Table 2-2a. Data Transfer

GENERAL PURPOSE

MOV Move operand

PUSH Push operand onto stack

POP Pop operand off stack

PUSHA Push all registers on stack

POPA Pop all registers off stack

XCHG Exchange Operand, Register

XLAT Translate

CONVERSION

MOVZX Move byte or Word, Dword, with zero

extension

MOVSX Move byte or Word, Dword, sign

extended

CBW Convert byte to Word, or Word to Dword

CWD Convert Word to DWORD

CWDE Convert Word to DWORD extended

CDQ Convert DWORD to QWORD

INPUT/OUTPUT

IN Input operand from I/O space

OUT Output operand to I/O space

ADDRESS OBJECT

LEA Load effective address

LDS Load pointer into D segment register

LES Load pointer into E segment register

LFS Load pointer into F segment register

LGS Load pointer into G segment register

LSS Load pointer into S (Stack) segment

FLAG MANIPULATION

LAHF Load A register from Flags

SAHF Store A register in Flags

PUSHF Push flags onto stack

POPF Pop flags off stack

PUSHFD Push EFlags onto stack

POPFD Pop EFlags off stack

CLC Clear Carry Flag

CLD Clear Direction Flag

CMC Complement Carry Flag

STC Set Carry Flag

STD Set Direction Flag

Table 2-2b. Arithmetic Instructions

ADDITION

ADD Add operands

ADC Add with carry

INC Increment operand by 1

AAA ASCII adjust for addition

DAA Decimal adjust for addition

SUBTRACTION

SUB Subtract operands

SBB Subtract with borrow

DEC Decrement operand by 1

NEG Negate operand

CMP Compare operands

DAS Decimal adjust for subtraction

AAS ASCII Adjust for subtraction

MULTIPLICATION

MUL Multiply Double/Single Precision

IMUL Integer multiply

AAM ASCII adjust after multiply

DIVISION

DIV Divide unsigned

IDIV Integer Divide

AAD ASCII adjust before division

Table 2-2c. String Instructions

MOVS Move byte or Word, Dword string

INS Input string from I/O space

OUTS Output string to I/O space

CMPS Compare byte or Word, Dword string

SCAS Scan Byte or Word, Dword string

LODS Load byte or Word, Dword string

STOS Store byte or Word, Dword string

REP Repeat

REPE/ REPZ Repeat while equal/zero

RENE/ REPNZ Repeat while not equal/not zero

Table 2-2d. Logical Instructions

LOGICALS

NOT ‘‘NOT’’ operands

AND ‘‘AND’’ operands

OR ‘‘Inclusive OR’’ operands

XOR ‘‘Exclusive OR’’ operands

TEST ‘‘Test’’ operands

Intel386TMDX MICROPROCESSOR

Table 2-2d. Logical Instructions (Continued)

SHIFTS

SHL/SHR Shift logical left or right

SAL/SAR Shift arithmetic left or right

SHLD/ SHRD Double shift left or right

ROTATES

ROL/ROR Rotate left/right

RCL/RCR Rotate through carry left/right

Table 2-2e. Bit Manipulation Instructions

SINGLE BIT INSTRUCTIONS

BT Bit Test

BTS Bit Test and Set

BTR Bit Test and Reset

BTC Bit Test and Complement

BSF Bit Scan Forward

BSR Bit Scan Reverse

Table 2-2f. Program Control Instructions

CONDITIONAL TRANSFERS

SETCC Set byte equal to condition code

JA/JNBE Jump if above/not below nor equal

JAE/JNB Jump if above or equal/not below

JB/JNAE Jump if below/not above nor equal

JBE/JNA Jump if below or equal/not above

JC Jump if carry

JE/JZ Jump if equal/zero

JG/JNLE Jump if greater/not less nor equal

JGE/JNL Jump if greater or equal/not less

JL/JNGE Jump if less/not greater nor equal

JLE/JNG Jump if less or equal/not greater

JNC Jump if not carry

JNE/JNZ Jump if not equal/not zero

JNO Jump if not overflow

JNP/JPO Jump if not parity/parity odd

JNS Jump if not sign

JO Jump if overflow

JP/JPE Jump if parity/parity even

JS Jump if Sign

Table 2-2f. Program Control Instructions

(Continued)

UNCONDITIONAL TRANSFERS

CALL Call procedure/task

RET Return from procedure

JMP Jump

ITERATION CONTROLS

LOOP Loop

LOOPE/ LOOPZ Loop if equal/zero

LOOPNE/ LOOPNZ Loop if not equal/not zero

JCXZ JUMP if register CXe0

INTERRUPTS

INT Interrupt

INTO Interrupt if overflow

IRET Return from Interrupt/Task

CLI Clear interrupt Enable

STI Set Interrupt Enable

Table 2-2g. High Level Language Instructions

BOUND Check Array Bounds

ENTER Setup Parameter Block for Entering

Procedure

LEAVE Leave Procedure

Table 2-2h. Protection Model

SGDT Store Global Descriptor Table

SIDT Store Interrupt Descriptor Table

STR Store Task Register

SLDT Store Local Descriptor Table

LGDT Load Global Descriptor Table

LIDT Load Interrupt Descriptor Table

LTR Load Task Register

LLDT Load Local Descriptor Table

ARPL Adjust Requested Privilege Level

LAR Load Access Rights

LSL Load Segment Limit

VERR/ VERW Verify Segment for Reading or Writing

LMSW Load Machine Status Word (lower

16 bits of CR0)

SMSW Store Machine Status Word

Table 2-2i. Processor Control Instructions

HLT Halt

WAIT Wait until BUSYÝnegated

ESC Escape

LOCK Lock Bus

Intel386TMDX MICROPROCESSOR

2.5 ADDRESSING MODES

2.5.1 Addressing Modes Overview

The Intel386 DX provides a total of 11 addressing modes for instructions to specify operands. The addressing modes are optimized to allow the efficient execution of high level languages such as C and FORTRAN, and they cover the vast majority of data references needed by high-level languages.

2.5.2 Register and Immediate Modes

Two of the addressing modes provide for instructions that operate on register or immediate operands:

Immediate Operand Mode: The operand is included in the instruction as part of the opcode.

2.5.3 32-Bit Memory Addressing

Modes

The remaining 9 modes provide a mechanism for specifying the effective address of an operand. The linear address consists of two components: the segment base address and an effective address. The effective address is calculated by using combinations of the following four address elements:

DISPLACEMENT: An 8-, or 32-bit immediate value, following the instruction.

BASE: The contents of any general purpose register. The base registers are generally used by compilers to point to the start of the local variable area.

The one exception is the simultaneous use of Base and Index components which requires one additional clock.

As shown in Figure 2-9, the effective address (EA) of an operand is calculated according to the following formula.

EAeBase Rega(Index Reg * Scaling)aDisplacement

Direct Mode: The operand’s offset is contained as part of the instruction as an 8-, 16- or 32-bit displacement.

EXAMPLE: INC Word PTR[500

EXAMPLE: MOV[ECX], EDX

Based Mode: A BASE register’s contents is added to a DISPLACEMENT to form the operands offset.

EXAMPLE: MOV ECX,[EAX

Index Mode: An INDEX register’s contents is added to a DISPLACEMENT to form the operands offset.

EXAMPLE: ADD EAX, TABLE[ESI

Scaled Index Mode: An INDEX register’s contents is multiplied by a scaling factor which is added to a DISPLACEMENT to form the operands offset.

EXAMPLE: IMUL EBX, TABLE[ESI*4],7

Based Index Mode: The contents of a BASE register is added to the contents of an INDEX register to form the effective address of an operand.

EXAMPLE: MOV EAX,[ESI

Based Scaled Index Mode: The contents of an INDEX register is multiplied by a SCALING factor and the result is added to the contents of a BASE register to obtain the operands offset.

EXAMPLE: MOV ECX,[EDX*8][EAX

][

EBX

]

INDEX: The contents of any general purpose register except for ESP. The index registers are used to access the elements of an array, or a string of characters.

SCALE: The index register’s value can be multiplied by a scale factor, either 1, 2, 4 or 8. Scaled index mode is especially useful for accessing arrays or structures.

Combinations of these 4 components make up the 9 additional addressing modes. There is no performance penalty for using any of these addressing combinations, since the effective address calculation is pipelined with the execution of other instructions.

Based Index Mode with Displacement: The contents of an INDEX Register and a BASE register’s contents and a DISPLACEMENT are all summed together to form the operand offset.

EXAMPLE: ADD EDX,[ESI][EBP

Based Scaled Index Mode with Displacement: The contents of an INDEX register are multiplied by a SCALING factor, the result is added to the contents of a BASE register and a DISPLACEMENT to form the operand’s offset.

EXAMPLE: MOV EAX, LOCALTABLE[EDI*4

[

EBP

]

00FFFFF0H

]

Intel386TMDX MICROPROCESSOR

Figure 2-9. Addressing Mode Calculations

2.5.4 Differences Between 16 and 32

Bit Addresses

In order to provide software compatibility with the 80286 and the 8086, the Intel386 DX can execute 16-bit instructions in Real and Protected Modes. The processor determines the size of the instructions it is executing by examining the D bit in the CS segment Descriptor. If the D bit is 0 then all operand lengths and effective addresses are assumed to be 16 bits long. If the D bit is 1 then the default length for operands and addresses is 32 bits. In Real Mode the default size for operands and addresses is 16-bits.

Regardless of the default precision of the operands or addresses, the Intel386 DX is able to execute either 16 or 32-bit instructions. This is specified via the use of override prefixes. Two prefixes, the Operand Size Prefix and the Address Length Prefix, override the value of the D bit on an individual instruction basis. These prefixes are automatically added by Intel assemblers.

231630– 51

Example: The processor is executing in Real Mode and the programmer needs to access the EAX registers. The assembler code for this might be MOV EAX, 32-bit MEMORYOP, ASM386 Macro Assembler automatically determines that an Operand Size Prefix is needed and generates it.

Example: The D bit is 0, and the programmer wishes to use Scaled Index addressing mode to access an array. The Address Length Prefix allows the use of MOV DX, TABLE[ESI*2]. The assembler uses an Address Length Prefix since, with D addressing mode is 16-bits.

Example: The D bit is 1, and the program wants to store a 16-bit quantity. The Operand Length Prefix is used to specify only a 16-bit value; MOV MEM16, DX.

0, the default

Intel386TMDX MICROPROCESSOR

Table 2-3. BASE and INDEX Registers for 16- and 32-Bit Addresses

BASE REGISTER BX,BP Any 32-bit GP Register INDEX REGISTER SI,DI Any 32-bit GP Register

SCALE FACTOR none 1, 2, 4, 8 DISPLACEMENT 0, 8, 16 bits 0, 8, 32 bits

16-Bit Addressing 32-Bit Addressing

Except ESP

The OPERAND LENGTH and Address Length Prefixes can be applied separately or in combination to any instruction. The Address Length Prefix does not allow addresses over 64K bytes to be accessed in Real Mode. A memory address which exceeds FFFFH will result in a General Protection Fault. An Address Length Prefix only allows the use of the additional Intel386 DX addressing modes.

When executing 32-bit code, the Intel386 DX uses either 8-, or 32-bit displacements, and any register can be used as base or index registers. When executing 16-bit code, the displacements are either 8, or 16 bits, and the base and index register conform to the 80286 model. Table 2-3 illustrates the differences.

2.6 DATA TYPES

The Intel386 DX supports all of the data types commonly used in high level languages:

Bit: A single bit quantity.

Bit Field: A group of up to 32 contiguous bits, which spans a maximum of four bytes.

Bit String: A set of contiguous bits, on the Intel386 DX bit strings can be up to 4 gigabits long.

Byte: A signed 8-bit quantity.

Unsigned Byte: An unsigned 8-bit quantity.

Integer (Word): A signed 16-bit quantity.

Long Integer (Double Word): A signed 32-bit quantity. All operations assume a 2’s complement representation.

Unsigned Integer (Word): An unsigned 16-bit quantity.

Unsigned Long Integer (Double Word): An unsigned 32-bit quantity.

Signed Quad Word: A signed 64-bit quantity.

Unsigned Quad Word: An unsigned 64-bit quantity.

Offset: A 16- or 32-bit offset only quantity which indirectly references another memory location.

Pointer: A full pointer which consists of a 16-bit segment selector and either a 16- or 32-bit offset.

Char: A byte representation of an ASCII Alphanumeric or control character.

String: A contiguous sequence of bytes, words or dwords. A string may contain between 1 byte and 4 Gbytes.

BCD: A byte (unpacked) representation of decimal digits 0–9.

Packed BCD: A byte (packed) representation of two decimal digits 0–9 storing one digit in each nibble.

When the Intel386 DX is coupled with an Intel387 DX Numerics Coprocessor then the following common Floating Point types are supported.

Floating Point: A signed 32-, 64-, or 80-bit real number representation. Floating point numbers are supported by the Intel387 DX numerics coprocessor.

Figure 2-10 illustrates the data types supported by the Intel386 DX and the Intel387 DX numerics coprocessor.

Intel386TMDX MICROPROCESSOR

Figure 2-10. Intel386TMDX Supported Data Types

231630– 52

Intel386TMDX MICROPROCESSOR

2.7 MEMORY ORGANIZATION

2.7.1 Introduction

Memory on the Intel386 DX is divided up into 8-bit quantities (bytes), 16-bit quantities (words), and 32-bit quantities (dwords). Words are stored in two consecutive bytes in memory with the low-order byte at the lowest address, the high order byte at the high address. Dwords are stored in four consecutive bytes in memory with the low-order byte at the lowest address, the high-order byte at the highest address. The address of a word or dword is the byte address of the low-order byte.

In addition to these basic data types, the Intel386 DX supports two larger units of memory: pages and segments. Memory can be divided up into one or more variable length segments, which can be swapped to disk or shared between programs. Memory can also be organized into one or more 4K byte pages. Finally, both segmentation and paging can be combined, gaining the advantages of both systems. The Intel386 DX supports both pages and segments in order to provide maximum flexibility to the system designer. Segmentation and paging are complementary. Segmentation is useful for organizing memory in logical modules, and as such is a tool for the application programmer, while pages are useful for the system programmer for managing the physical memory of a system.

(also known as a virtual address) consists of a selector and an offset. A selector is the contents of a segment register. An offset is formed by summing all of the addressing components (BASE, INDEX, DISPLACEMENT) discussed in section 2.5.3 Memory Addressing Modes into an effective address. Since each task on Intel386 DX has a maximum of 16K

1) selectors, and offsets can be 4 gigabytes,

bits) this gives a total of 246bits or 64 terabytes of logical address space per task. The programmer sees this virtual address space.

The segmentation unit translates the logical address space into a 32-bit linear address space. If the paging unit is not enabled then the 32-bit linear address corresponds to the physical address. The paging unit translates the linear address space into the physical address space. The physical address is what appears on the address pins.

The primary difference between Real Mode and Protected Mode is how the segmentation unit performs the translation of the logical address into the linear address. In Real Mode, the segmentation unit shifts the selector left four bits and adds the result to the offset to form the linear address. While in Protected Mode every selector has a linear base address associated with it. The linear base address is stored in one of two operating system tables (i.e. the Local Descriptor Table or Global Descriptor Table). The selector’s linear base address is added to the offset to form the final linear address.

2.7.2 Address Spaces

The Intel386 DX has three distinct address spaces:

logical, linear, and physical.Alogical address

Figure 2-11. Address Translation

Figure 2-11 shows the relationship between the various address spaces.

231630– 53

Intel386TMDX MICROPROCESSOR

2.7.3 Segment Register Usage

The main data structure used to organize memory is the segment. On the Intel386 DX, segments are variable sized blocks of linear addresses which have certain attributes associated with them. There are two main types of segments: code and data, the segments are of variable size and can be as small as 1 byte or as large as 4 gigabytes (2

In order to provide compact instruction encoding, and increase processor performance, instructions do not need to explicitly specify which segment register is used. A default segment register is automatically chosen according to the rules of Table 2-4 (Segment Register Selection Rules). In general, data references use the selector contained in the DS register; Stack references use the SS register and Instruction fetches use the CS register. The contents of the Instruction Pointer provides the offset. Special segment override prefixes allow the explicit use of a given segment register, and override the implicit rules listed in Table 2-4. The override prefixes also allow the use of the ES, FS and GS segment registers.

Type of Implied (Default) Segment Override

Memory Reference Segment Use Prefixes Possible

Code Fetch CS None

Destination of PUSH, PUSHF, INT, SS None CALL, PUSHA Instructions

Source of POP, POPA, POPF, SS None IRET, RET instructions

Destination of STOS, MOVS, REP ES None STOS, REP MOVS Instructions (DI is Base Register)

Other Data References, with Effective Address Using Base Register of:

[

EAX

[

EBX

[

ECX

[

EDX

[

ESI

[

EDI

[

EBP

[

ESP

bytes).

Table 2-4. Segment Register Selection Rules

] ] ]

]

There are no restrictions regarding the overlapping of the base addresses of any segments. Thus, all 6 segments could have the base address set to zero and create a system with a four gigabyte linear address space. This creates a system where the virtual address space is the same as the linear address space. Further details of segmentation are discussed in section 4.1.

2.8 I/O SPACE

The Intel386 DX has two distinct physical address spaces: Memory and I/O. Generally, peripherals are placed in I/O space although the Intel386 DX also supports memory-mapped peripherals. The I/O space consists of 64K bytes, it can be divided into 64K 8-bit ports, 32K 16-bit ports, or 16K 32-bit ports, or any combination of ports which add up to less than 64K bytes. The 64K I/O address space refers to physical memory rather than linear address since I/O instructions do not go through the segmentation or paging hardware. The M/IO tional address line thus allowing the system designer to easily determine which address space the processor is accessing.

DS DS,CS,SS,ES,FS,GS DS DS,CS,SS,ES,FS,GS DS DS,CS,SS,ES,FS,GS DS DS,CS,SS,ES,FS,GS DS DS,CS,SS,ES,FS,GS DS DS,CS,SS,ES,FS,GS SS DS,CS,SS,ES,FS,GS SS DS,CS,SS,ES,FS,GS

pin acts as an addi-

Intel386TMDX MICROPROCESSOR

The I/O ports are accessed via the IN and OUT I/O instructions, with the port address supplied as an immediate 8-bit constant in the instruction or in the DX register. All 8- and 16-bit port addresses are zero extended on the upper address lines. The I/O instructions cause the M/IO

I/O port addresses 00F8H through 00FFH are reserved for use by Intel.

pin to be driven low.

2.9 INTERRUPTS

2.9.1 Interrupts and Exceptions

Interrupts and exceptions alter the normal program flow, in order to handle external events, to report errors or exceptional conditions. The difference between interrupts and exceptions is that interrupts are used to handle asynchronous external events while exceptions handle instruction faults. Although a program can generate a software interrupt via an INT N instruction, the processor treats software interrupts as exceptions.

Hardware interrupts occur as the result of an external event and are classified into two types: maskable or non-maskable. Interrupts are serviced after the execution of the current instruction. After the interrupt handler is finished servicing the interrupt, execution proceeds with the instruction immediately af- ter the interrupted instruction. Sections 2.9.3 and

2.9.4 discuss the differences between Maskable and Non-Maskable interrupts.

Exceptions are classified as faults, traps, or aborts depending on the way they are reported, and whether or not restart of the instruction causing the exception is supported. Faults are exceptions that are detected and serviced before the execution of the faulting instruction. A fault would occur in a virtual memory system, when the processor referenced a page or a segment which was not present. The operating system would fetch the page or segment from disk, and then the Intel386 DX would restart the instruction. Traps are exceptions that are reported immediately after the execution of the instruction which caused the problem. User defined interrupts are examples of traps. Aborts are exceptions which do not permit the precise location of the instruction causing the exception to be determined. Aborts are used to report severe errors, such as a hardware error, or illegal values in system tables.

Thus, when an interrupt service routine has been completed, execution proceeds from the instruction

immediately following the interrupted instruction. On the other hand, the return address from an exception fault routine will always point at the instruction causing the exception and include any leading instruction prefixes. Table 2-5 summarizes the possible interrupts for the Intel386 DX and shows where the return address points.

The Intel386 DX has the ability to handle up to 256 different interrupts/exceptions. In order to service the interrupts, a table with up to 256 interrupt vectors must be defined. The interrupt vectors are simply pointers to the appropriate interrupt service routine. In Real Mode (see section 3.1), the vectors are 4 byte quantities, a Code Segment plus a 16-bit offset; in Protected Mode, the interrupt vectors are 8 byte quantities, which are put in an Interrupt Descriptor Table (see section 4.1). Of the 256 possible interrupts, 32 are reserved for use by Intel, the remaining 224 are free to be used by the system designer.

2.9.2 Interrupt Processing

When an interrupt occurs the following actions happen. First, the current program address and the Flags are saved on the stack to allow resumption of the interrupted program. Next, an 8-bit vector is supplied to the Intel386 DX which identifies the appropriate entry in the interrupt table. The table contains the starting address of the interrupt service routine. Then, the user supplied interrupt service routine is executed. Finally, when an IRET instruction is executed the old processor state is restored and program execution resumes at the appropriate instruction.

The 8-bit interrupt vector is supplied to the Intel386 DX in several different ways: exceptions supply the interrupt vector internally; software INT instructions contain or imply the vector; maskable hardware interrupts supply the 8-bit vector via the interrupt acknowledge bus sequence. Non-Maskable hardware interrupts are assigned to interrupt vector 2.

2.9.3 Maskable Interrupt

Maskable interrupts are the most common way used by the Intel386 DX to respond to asynchronous external hardware events. A hardware interrupt occurs when the INTR is pulled high and the Interrupt Flag bit (IF) is enabled. The processor only responds to interrupts between instructions, (REPeat String instructions, have an ‘‘interrupt window’’, between memory moves, which allows interrupts during long

Intel386TMDX MICROPROCESSOR

Table 2-5. Interrupt Vector Assignments

Function

Divide Error 0 DIV, IDIV YES FAULT

Debug Exception 1 any instruction YES TRAP*

NMI Interrupt 2 INT 2 or NMI NO NMI

One Byte Interrupt 3 INT NO TRAP

Interrupt on Overflow 4 INTO NO TRAP

Array Bounds Check 5 BOUND YES FAULT

Invalid OP-Code 6 Any Illegal Instruction YES FAULT

Device Not Available 7 ESC, WAIT YES FAULT

Double Fault 8 Any Instruction That Can ABORT

Coprocessor Segment Overrun 9 ESC NO ABORT

Invalid TSS 10 JMP, CALL, IRET, INT YES FAULT

Segment Not Present 11 Segment Register Instructions YES FAULT

Stack Fault 12 Stack References YES FAULT

General Protection Fault 13 Any Memory Reference YES FAULT

Intel Reserved 15

Page Fault 14 Any Memory Access or Code Fetch YES FAULT

Coprocessor Error 16 ESC, WAIT YES FAULT

Intel Reserved 17–31

Two Byte Interrupt 0– 255 INT n NO TRAP

* Some debug exceptions may report both traps on the previous instruction, and faults on the next instruction.

Interrupt

Number

Instruction Which

Can Cause

Exception

Generate an Exception

Return Address

Points to

Faulting

Instruction

Type

string moves). When an interrupt occurs the processor reads an 8-bit vector supplied by the hardware which identifies the source of the interrupt, (one of 224 user defined interrupts). The exact nature of the interrupt sequence is discussed in section 5.

The IF bit in the EFLAG registers is reset when an interrupt is being serviced. This effectively disables servicing additional interrupts during an interrupt service routine. However, the IF may be set explicitly by the interrupt handler, to allow the nesting of interrupts. When an IRET instruction is executed the original state of the IF is restored.

2.9.4 Non-Maskable Interrupt

Non-maskable interrupts provide a method of servicing very high priority interrupts. A common example of the use of a non-maskable interrupt (NMI) would be to activate a power failure routine. When the NMI

input is pulled high it causes an interrupt with an internally supplied vector value of 2. Unlike a normal hardware interrupt, no interrupt acknowledgment sequence is performed for an NMI.

While executing the NMI servicing procedure, the Intel386 DX will not service further NMI requests, until an interrupt return (IRET) instruction is executed or the processor is reset. If NMI occurs while currently servicing an NMI, its presence will be saved for servicing after executing the first IRET instruction. The IF bit is cleared at the beginning of an NMI interrupt to inhibit further INTR interrupts.

2.9.5 Software Interrupts

A third type of interrupt/exception for the Intel386 DX is the software interrupt. An INT n instruction causes the processor to execute the interrupt service routine pointed to by the nth vector in the interrupt table.

Intel386TMDX MICROPROCESSOR

A special case of the two byte software interrupt INT n is the one byte INT 3, or breakpoint interrupt. By inserting this one byte instruction in a program, the user can set breakpoints in his program as a debugging tool.

A final type of software interrupt, is the single step interrupt. It is discussed in section 2.12.

2.9.6 Interrupt and Exception Priorities

Interrupts are externally-generated events. Maskable Interrupts (on the INTR input) and Non-Maskable Interrupts (on the NMI input) are recognized at instruction boundaries. When NMI and maskable INTR are both recognized at the same instruction boundary, the Intel386 DX invokes the NMI service routine first. If, after the NMI service routine has been invoked, maskable interrupts are still enabled, then the Intel386 DX will invoke the appropriate interrupt service routine.

Table 2-6a. Intel386 Invoking Service Routines in Case of

Simultaneous External Interrupts

Exceptions are internally-generated events. Exceptions are detected by the Intel386 DX if, in the course of executing an instruction, the Intel386 DX detects a problematic condition. The Intel386 DX then immediately invokes the appropriate exception service routine. The state of the Intel386 DX is such that the instruction causing the exception can be restarted. If the exception service routine has taken care of the problematic condition, the instruction will execute without causing the same exception.

It is possible for a single instruction to generate several exceptions (for example, transferring a single operand could generate two page faults if the operand location spans two ‘‘not present’’ pages). However, only one exception is generated upon each attempt to execute the instruction. Each exception service routine should correct its corresponding exception, and restart the instruction. In this manner, exceptions are serviced until the instruction executes successfully.

As the Intel386 DX executes instructions, it follows a consistent cycle in checking for exceptions, as shown in Table 2-6b. This cycle is repeated

1. NMI

2. INTR

DX Priority for

as each instruction is executed, and occurs in parallel with instruction decoding and execution.

Table 2-6b. Sequence of Exception Checking

Consider the case of the Intel386 DX having just completed an instruction. It then performs the following checks before reaching the point where the next instruction is completed:

1. Check for Exception 1 Traps from the instruction just completed (single-step via Trap Flag, or Data Breakpoints set in the Debug Registers).

2. Check for Exception 1 Faults in the next instruction (Instruction Execution Breakpoint set in the Debug Registers for the next instruction).

3. Check for external NMI and INTR.

4. Check for Segmentation Faults that prevented fetching the entire next instruction (exceptions 11 or 13).

5. Check for Page Faults that prevented fetching the entire next instruction (exception 14).

6. Check for Faults decoding the next instruction (exception 6 if illegal opcode; exception 6 if in Real Mode or in Virtual 8086 Mode and attempting to execute an instruction for Protected Mode only (see 4.6.4); or exception 13 if instruction is longer than 15 bytes, or privilege violation in Protected Mode (i.e. not at IOPL or

at CPL

0).

7. If WAIT opcode, check if TSe1 and MPe1 (exception 7 if both are 1).

8. If ESCAPE opcode for numeric coprocessor, check if EM

1orTSe1 (exception 7 if either

are 1).

9. If WAIT opcode or ESCAPE opcode for numeric coprocessor, check ERROR nal (exception 16 if ERROR

input sig-

input is assert-

ed).

10. Check in the following order for each memo-

ry reference required by the instruction:

a. Check for Segmentation Faults that pre-

vent transferring the entire memory quantity (exceptions 11, 12, 13).

b. Check for Page Faults that prevent trans-

ferring the entire memory quantity (exception 14).

Note that the order stated supports the concept of the paging mechanism being ‘‘underneath’’ the segmentation mechanism. Therefore, for any given code or data reference in memory, segmentation exceptions are generated before paging exceptions are generated.

Intel386TMDX MICROPROCESSOR

2.9.7 Instruction Restart

The Intel386 DX fully supports restarting all instructions after faults. If an exception is detected in the instruction to be executed (exception categories 4 through 10 in Table 2-6b), the Intel386 DX invokes the appropriate exception service routine. The Intel386 DX is in a state that permits restart of the instruction, for all cases but those in Table 2-6c. Note that all such cases are easily avoided by proper design of the operating system.

Table 2-6c. Conditions Preventing

Instruction Restart

A. An instruction causes a task switch to a task

whose Task State Segment is partially ‘‘not present’’. (An entirely ‘‘not present’’ TSS is restartable.) Partially present TSS’s can be avoided either by keeping the TSS’s of such tasks present in memory, or by aligning TSS segments to reside entirely within a single 4K page (for TSS segments of 4K bytes or less).

B. A coprocessor operand wraps around the top

of a 64K-byte segment or a 4G-byte segment, and spans three pages, and the page holding the middle portion of the operand is ‘‘not present.’’ This condition can be avoided by starting at a page boundary any segments containing coprocessor operands if the segments are approximately 64K-200 bytes or larger (i.e. large enough for wraparound of the coprocessor operand to possibly occur).

Note that these conditions are avoided by using the operating system designs mentioned in this table.

2.9.8 Double Fault

A Double Fault (exception 8) results when the processor attempts to invoke an exception service routine for the segment exceptions (10, 11, 12 or 13), but in the process of doing so, detects an exception other than a Page Fault (exception 14).

A Double Fault (exception 8) will also be generated when the processor attempts to invoke the Page Fault (exception 14) service routine, and detects an exception other than a second Page Fault. In any functional system, the entire Page Fault service routine must remain ‘‘present’’ in memory.

Double page faults however do not raise the double fault exception. If a second page fault occurs while the processor is attempting to enter the service routine for the first time, then the processor will invoke

the page fault (exception 14) handler a second time, rather than the double fault (exception 8) handler. A subsequent fault, though, will lead to shutdown.

When a Double Fault occurs, the Intel386 DX invokes the exception service routine for exception 8.

2.10 RESET AND INITIALIZATION

When the processor is initialized or Reset the registers have the values shown in Table 2-7. The Intel386 DX will then start executing instructions near the top of physical memory, at location FFFFFFF0H. When the first InterSegment Jump or Call is executed, address lines A20-31 will drop low for CS-relative memory cycles, and the Intel386 DX will only execute instructions in the lower one megabyte of physical memory. This allows the system designer to use a ROM at the top of physical memory to initialize the system and take care of Resets.

RESET forces the Intel386 DX to terminate all execution and local bus activity. No instruction execution or bus activity will occur as long as Reset is active. Between 350 and 450 CLK2 periods after Reset becomes inactive the Intel386 DX will start executing instructions at the top of physical memory.

Table 2-7. Register Values after Reset

Flag Word UUUU0002H Note 1 Machine Status Word (CR0) UUUUUUU0H Note 2 Instruction Pointer 0000FFF0H Code Segment F000H Note 3 Data Segment 0000H Stack Segment 0000H Extra Segment (ES) 0000H Extra Segment (FS) 0000H Extra Segment (GS) 0000H DX register component and

All other registers undefined Note 4

NOTES:

1. EFLAG Register. The upper 14 bits of the EFLAGS register are undefined, VM (Bit 17) and RF (BIT) 16 are 0 as are all other defined flag bits.

2. CR0: (Machine Status Word). All of the defined fields in the CR0 are 0 (PG Bit 31, TS Bit 3, EM Bit 2, MP Bit 1, and PE Bit 0).

3. The Code Segment Register (CS) will have its Base Address set to FFFF0000H and Limit set to 0FFFFH.

4. All undefined bits are Intel Reserved and should not be used.

5. DX register always holds component and stepping identifier (see 5.7). EAX register holds self-test signature if selftest was requested (see 5.6).

stepping ID Note 5

Intel386TMDX MICROPROCESSOR

2.11 TESTABILITY

2.11.1 Self-Test

The Intel386 DX has the capability to perform a selftest. The self-test checks the function of all of the Control ROM and most of the non-random logic of the part. Approximately one-half of the Intel386 DX can be tested during self-test.

Self-Test is initiated on the Intel386 DX when the RESET pin transitions from HIGH to LOW, and the

BUSY

pin is low. The self-test takes about 2**19 clocks, or approximately 26 milliseconds with a 20 MHz Intel386 DX. At the completion of self-test the processor performs reset and begins normal operation. The part has successfully passed self-test if the contents of the EAX register are zero (0). If the results of EAX are not zero then the self-test has detected a flaw in the part.

2.11.2 TLB Testing

The Intel386 DX provides a mechanism for testing the Translation Lookaside Buffer (TLB) if desired. This particular mechanism is unique to the Intel386 DX and may not be continued in the same way in future processors. When testing the TLB paging must be turned off (PG TLB testing hardware and avoid interference with the test data being written to the TLB.

There are two TLB testing operations: 1) write entries into the TLB, and, 2) perform TLB lookups. Two Test Registers, shown in Figure 2-12, are provided for the purpose of testing. TR6 is the ‘‘test command register’’, and TR7 is the ‘‘test data register’’. The fields within these registers are defined below.

C: This is the command bit. For a write into TR6 to cause an immediate write into the TLB entry, write a 0 to this bit. For a write into TR6 to cause an immediate TLB lookup, write a 1 to this bit.

Linear Address: This is the tag field of the TLB. On a TLB write, a TLB entry is allocated to this linear address and the rest of that TLB entry is set per the value of TR7 and the value just written into TR6. On a TLB lookup, the TLB is interrogated per this value and if one and only one TLB entry matches, the rest of the fields of TR6 and TR7 are set from the matching TLB entry.

Physical Address: This is the data field of the TLB. On a write to the TLB, the TLB entry allocated to the linear address in TR6 is set to this value. On a TLB lookup, the data field (physical address) from the TLB is read out to here.

0 in CR0) to enable the

PL: On a TLB write, PL TR7 to select which of four associative blocks of the TLB is to be written, but PL

1 causes the REP field of

0 allows the internal pointer in the paging unit to select which TLB block is written. On a TLB lookup, the PL bit indicates whether the lookup was a hit (PL gets set to 1) or a miss (PL gets reset to 0).

V: The valid bit for this TLB entry. All valid bits can also be cleared by writing to CR3.

D, D

: The dirty bit for/from the TLB entry.

U, U

: The user bit for/from the TLB entry.

W, W

: The writable bit for/from the TLB entry.

For D, U and W, both the attribute and its complement are provided as tag bits, to permit the option of a ‘‘don’t care’’ on TLB lookups. The meaning of these pairs of bits is given in the following table:

TLB Lookup X after TLB Write

Effect During Value of Bit

0 0 Miss All Bit X Becomes Undefined 0 1 Match if X 1 0 Match if X

0 Bit X Becomes 0

1 Bit X Becomes 1

1 1 Match all Bit X Becomes Undefined

For writing a TLB entry:

1. Write TR7 for the desired physical address, PL

and REP values.

2. Write TR6 with the appropriate linear address,

etc. (be sure to write C

0 for ‘‘write’’ com-

mand).

For looking up (reading) a TLB entry:

1. Write TR6 with the appropriate linear address (be

sure to write C

1 for ‘‘lookup’’ command).

2. Read TR7 and TR6. If the PL bit in TR7 indicates

a hit, then the other values reveal the TLB contents. If PL indicates a miss, then the other values in TR7 and TR6 are indeterminate.

2.12 DEBUGGING SUPPORT

The Intel386 DX provides several features which simplify the debugging process. The three categories of on-chip debugging aids are:

1) the code execution breakpoint opcode (0CCH),

2) the single-step capability provided by the TF bit in

the flag register, and

3) the code and data breakpoint capability provided

by the Debug Registers DR0-3, DR6, and DR7.

Intel386TMDX MICROPROCESSOR

31 12 11 0

LINEAR ADDRESS

PHYSICAL ADDRESS 0 0 0 0 0 0 0

NOTE: 0 indicates Intel reserved: Do not define; SEE SECTION 2.3.10

Figure 2-12. Test Registers

VDDUUWW

ÝÝÝ

0000CTR6

REP 0 0 TR7

2.12.1 Breakpoint Instruction

A single-byte-opcode breakpoint instruction is available for use by software debuggers. The breakpoint opcode is 0CCh, and generates an exception 3 trap when executed. In typical use, a debugger program can ‘‘plant’’ the breakpoint instruction at all desired code execution breakpoints. The single-byte breakpoint opcode is an alias for the two-byte general software interrupt instruction, INT n, where n The only difference between INT 3 (0CCh) and INT n is that INT 3 is never IOPL-sensitive but INT n is IOPL-sensitive in Protected Mode and Virtual 8086 Mode.

2.12.2 Single-Step Trap

If the single-step flag (TF, bit 8) in the EFLAG register is found to be set at the end of an instruction, a single-step exception occurs. The single-step exception is auto vectored to exception number 1. Precisely, exception 1 occurs as a trap after the instruction following the instruction which set TF. In typical practice, a debugger sets the TF bit of a flag register image on the debugger’s stack. It then typically transfers control to the user program and loads the flag image with a signal instruction, the IRET instruction. The single-step trap occurs after executing one instruction of the user program.

Since the exception 1 occurs as a trap (that is, it occurs after the instruction has already executed), the CS:EIP pushed onto the debugger’s stack points to the next unexecuted instruction of the program being debugged. An exception 1 handler, merely by ending with an IRET instruction, can therefore efficiently support single-stepping through a user program.

placed in ROM code or in code shared by several tasks, neither of which can be supported by the INT3 breakpoint opcode.

The Intel386 DX contains six Debug Registers, providing the ability to specify up to four distinct breakpoints addresses, breakpoint control options, and read breakpoint status. Initially after reset, breakpoints are in the disabled state. Therefore, no breakpoints will occur unless the debug registers are pro-

3. grammed. Breakpoints set up in the Debug Registers are autovectored to exception number 1.

2.12.3.1 LINEAR ADDRESS BREAKPOINT

Up to four breakpoint addresses can be specified by writing into Debug Registers DR0 –DR3, shown in Figure 2-13. The breakpoint addresses specified are 32-bit linear addresses. Intel386 DX hardware continuously compares the linear breakpoint addresses in DR0 – DR3 with the linear addresses generated by executing software (a linear address is the result of computing the effective address and adding the 32-bit segment base address). Note that if paging is not enabled the linear address equals the physical address. If paging is enabled, the linear address is translated to a physical 32-bit address by the onchip paging unit. Regardless of whether paging is enabled or not, however, the breakpoint registers hold linear addresses.

2.12.3.2 DEBUG CONTROL REGISTER (DR7)

A Debug Control Register, DR7 shown in Figure 2-13, allows several debug control functions such as enabling the breakpoints and setting up other control options for the breakpoints. The fields within the Debug Control Register, DR7, are as follows:

REGISTERS (DR0 – DR3)

2.12.3 Debug Registers

The Debug Registers are an advanced debugging feature of the Intel386 DX. They allow data access breakpoints as well as code execution breakpoints. Since the breakpoints are indicated by on-chip registers, an instruction execution breakpoint can be

LENi (breakpoint length specification bits)

A 2-bit LEN field exists for each of the four breakpoints. LEN specifies the length of the associated breakpoint field. The choices for data breakpoints are: 1 byte, 2 bytes, and 4 bytes. Instruction execu-

Intel386TMDX MICROPROCESSOR

31 16 15 0

BREAKPOINT 0 LINEAR ADDRESS DR0

BREAKPOINT 1 LINEAR ADDRESS DR1

BREAKPOINT 2 LINEAR ADDRESS DR2

BREAKPOINT 3 LINEAR ADDRESS DR3

Intel reserved. Do not define. DR4

Intel reserved. Do not define. DR5

LEN R W LEN R W LEN R W LEN R W

3 3 3 2 2 2 1 1 1 0 0 0 D EE3322110 0

31 16 15 0

NOTE: 0 indicates Intel reserved: Do not define; SEE SECTION 2.3.10

Figure 2-13. Debug Registers

tion breakpoints must have a length of 1 (LENi

00). Encoding of the LENi field is as follows:

LENi Breakpoint Significant Bits in

Encoding Field Width Breakpoint Address

00 1 byte All 32-bits used to

01 2 bytes A1–A31 used to

10 UndefinedÐ

do not use

this encoding

11 4 bytes A2–A31 used to

Usage of Least

specify a single-byte breakpoint field.

specify a two-byte, word-aligned breakpoint field. A0 in Breakpoint Address Register is not used.

specify a four-byte, dword-aligned breakpoint field. A0 and A1 in Breakpoint Address Register are not used.

e0b

BBB TSD 3210

00G000

The following is an example of various size breakpoint fields. Assume the breakpoint linear address in DR2 is 00000005H. In that situation, the following illustration indicates the region of the breakpoint field for lengths of 1, 2, or 4 bytes.

0000 0 0 0 0 0

GLGLGLGLGL

DR2e00000005H; LEN2e00B

31 0

bkpt fld2 00000004H

DR2e00000005H; LEN2e01B

31 0

DR2e00000005H; LEN2e11B

31 0

BBBB

bkpt fld2x00000004H

DR6

DR7

00000008H

00000000H

00000008H

00000000H

The LENi field controls the size of breakpoint field i by controlling whether all low-order linear address bits in the breakpoint address register are used to detect the breakpoint event. Therefore, all breakpoint fields are aligned; 2-byte breakpoint fields begin on Word boundaries, and 4-byte breakpoint fields begin on Dword boundaries.

bkpt fld2

00000008H

00000004H

00000000H

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