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impedance from 60 ohms to 57 ohms.
Changed topology information in Figure 24 and Table 16.
Table 17 Added alternate PCI-X 100MHz Slot and Embedded
Topology Figure 25 and Table 16.
Table 18 Changed Add-in card impedance from 60 ohms +/-
15% to 57 ohms +/- 15%.
In Chapter 7:
DDR 333 Source Synchronous recommendations removed the
requirement for length matching for DQS groups based on
simulations
Removed row in Table 48 “Length Matching Requirements:
between clock groups”. This is required only for unbuffered
clocks and was already mentioned in the previous row.
Table 51: removed row in “Trace Length: 80331 signal Ball to
Series Term ination” because the series termination is no
longer needed.
Table 52: Removed Rout ing Guideline 4 because unbuffered
and registered DIMM’s have the same topology.
Deleted Figure 57 because simulations showed that series
resistors is no longer needed for DDR 333 DIMM control
signals
Table 53: Removed Lengt h Matching within DQS group
recommendation now because length matching will happen
when matching to M_CK.
Changed Embedded DDR 333 DQ/DQS Topology Figure 44
resistor listed as 50 ohms +/- 5% to 51 ohms +/- 5% because
this is a standard value resistor.
In Chapter 9
Removed VCC25/VCC18 from the power up sequence order
and added a note stating that there is no sequence order
requirements for the VCC25 or VCC18 rail.
Other:
Moved the decoupling guidelines from Chapter 3 to Chapter 4.
Removed reference to the Hot Plug controller. This feature is
not part of the 80331 product.
10
Intel® 80331 I/O Process orDesign Guide
Introduction
Introduction1
1.1About This Document
This document provides layout information and guidelines for designing platform or add-in bo ard
applications with the Intel
It is recommended that this document be used as a guideline. Intel recommends employing
best-known design practices with board level simulation, signal integrity testing and validation for
a robust design.
Designers please note that this g uide focu ses upo n sp ecific design cons iderations fo r the 8 0331 and
is not intended to be an all-inclusive list of all good design practices. Use this guide as a starting
point and use empirical data to optimize your particular design.
Intel Corporation assumes no responsibility for any errors which may appear in this document nor
does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice. In
particular, d escri p t ions of f eatu res, t i mings , pack aging , and pin-outs does not imply a commitment
to implement them. In fact, this specification does not imply a commitment by Intel to design,
manufacture, or sell the product described herein.
®
80331 I/O processor (80331), which is ARM* architecture compliant.
11
Intel® 80331 I/O Process orDesign Guide
Introduction
1.1.1Terminology and Definitions
Table 1. Terminology and Definitions (Sheet 1 of 2)
TermDefinition
80331Intel
Stripline
®
80331 I/O processor
Stripline in a PCB is composed of the
conductor inserted in a dielectric with GND
planes to the top and bottom.
NOTE: An easy way to distinguish stripline
from microstrip is that you need to
strip away layers of the board to view
the trace on stripline.
Microstrip
Prepreg
Core
PCB
DDR
DDR II
DIMMDual Inline Memory Module
Source
Synchronous
DDR
SSTL_2Series Stub Terminated Logic for 2.5 V
JEDECProvides standards for the semiconductor industry.
DLL
Material used for the lamination process of manufacturing PCBs. It consists of a layer of
epoxy material that is placed between two cores. This layer melts into epoxy when heated and
forms around adjacent traces.
Material used for the lamination process of manufacturing PCBs. This material is two sided
laminate with copper on each side. The core is an internal layer that is etched.
Layer 1: copper
Prepreg
Layer 2: GND
Core
Layer 3: V
Prepreg
Layer 4: copper
Example of a Four-Layer Stack
Double Data Rate Synchronous DRAM. Data is clocked on both rising and falling edges of the
clock.
DDR II is backward compatible with DDR I. However, it has an increased DDR data rate to
3.2 GBytes/sec with a clock rate of 200 MHz for multiple DIMM configurations. It allows data
rate of 6.4 Gbytes/sec with a clock rate of 400 MHz for a single DIMM point to point
configuration.
• For reads data leaves the DDR or memory controller with a data strobe. The memory
controller delays the data strobe internally to line it up with the data valid window.
• For writes the memory controller places the data strobe in the middle of the data valid
window to ensure that the correct data gets clocked into the DRAM.
Delay Lock Loop - refers to the DDR feature used to provide appropriate strobe delay to clock
in data.
CC
Microstrip in a PCB is composed of the
conductor on the top layer above the dielectric
with a ground plane below
Printed circuit board.
Example manufacturing process consists of
the following steps:
• Consists of alternating layers of core and
prepreg stacked
• The finished PCB is heated and cured.
• The via holes are drilled
• Plating covers holes and outer surfaces
• Etching removes unwanted copper
• Board is tinned, coated with solder mask
and silk screened
12
Table 1. Terminology and Definitions (Sheet 2 of 2)
TermDefinition
A network that transmits a coupled signal to another network is aggressor network.
Intel® 80331 I/O Process orDesign Guide
Introduction
Aggressor
VictimA network that receives a coupled cross-talk signal from anot her net wor k is a victi m network.
NetworkThe trace of a PCB that completes an electrical connection between two or more components.
StubBranch from a trunk terminating at the pad of an agent.
Intersymbol Interference (ISI). This occurs when a transition that has not been completely
dissipated, interferes with a signal being transmitted down a transmission line. ISI can impact
both the timing and signal integrity. It is dependent on frequency, time delay of the line and the
ISI
CRBCustomer Reference Board
PC1600
PC2100
PC2700
PC3200
DownstreamAt or toward the Primary PCI interface from the Secondary PCI interface
Local memory
DWORD32-bit data word.
Local bus
OutboundAt or toward the PCI interface of the 80331 AT U from the Internal Bus.
InboundAt or toward the Internal Bus of the 80331 from the PCI interface of the ATU.
Local processor Intel XScale
Core processor Intel XScale® core within the 80331.
Flip Chip
Mode
Conversion
ROMBRaid on motherboard
ODT
refection coefficient at the driver and receiver. Examples of ISI patterns that could be used in
testing at the maximum allowable frequencies are the sequences shown below:
JEDEC Names for DDR based on peak data rates.
PC1600= clock of 100 MHz * 2 data words/clock * 8 bytes = 1600 MB/sec
JEDEC Names for DDR based on peak data rates.
PC2100= clock of 133 MHz * 2 data words/clock * 8 bytes = 2128 MB/sec
JEDEC Names for DDR II based on peak data rates.
PC2700= clock of 167 MHz * 2 data words/clock * 8 bytes = 2672 MB/sec
JEDEC Names for DDR II based on peak data rates.
PC3200= clock of 200 MHz * 2 data words/clock * 8 bytes = 3200 MB/sec
Memory subsystem on the Intel XScale
busses.
80331 Internal Bus.
FC-BGA (flip chip-ball grid array) chip packages are designed with core flipped up on the back of
the chip, facing away from the PCB. This allows more efficient cooling of the package.
Mode Conversions are due to imperfections on the interconnect which transform differential
mode voltage to common mode voltage and common mode voltage to differential voltage.
On Die Termination - eliminates the need for termination resistors by placing the termination at
the chip.
4. Intel XScale® 80200 Processor based on Intel® Microarchitecture Developer’s Manual
(273411), Intel Corp orati on
5. PCI Local Bus Specification, Revision 2.3 - PCI Special Interest Group
6. PCI-X Specification, Revision 1.0b - PCI Special Interest Group
7. PCI Bus Power Management Interface Specification, Revis ion 1.1 - PCI Special Interest
Group
8. IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE JTAG-1149.1-1990)
14
Intel® 80331 I/O Process orDesign Guide
1.2About the Intel® 80331 I/O Processor
The 80331 is a multi-function device that integrates the Intel XScale® core (ARM* architecture
compliant) with intelligent peripherals and PCI-to-PCI Bridge. The 80331 consolidates the
following into a single system:
• Intel XScale
• PCI-to-PCI Bridge supporting PCI-X interfaces on the Primary and Secondary bus.
• Address Translation Unit (PCI-to-Internal Bus Application Bridge) interfaced to the
Secondary Bus
• High-Performance Memory Controller
• Interrupt Controller with up to 13 external interrupt inputs
• Two Direct Memory Access (DMA) Controllers
• Application Accelerator
• Messaging Unit
• Peripheral Bus Interface Unit
• Performance Monitor
• Tw o I
®
core
2
C Bus Interface Units
Introduction
• Two 16550 compatible UARTs with flow control (four pins)
• Eight General Purpose Input Output (GPIO) ports
It is an integrated processor that addresses the needs of intelligent I/O applications and helps
reduce intelligent I/O system costs.
The 80331 is of fered in a Flip Chip Ball Grid Array (FCBGA) package. This is a fu ll-array package
with 829 ball connections. The mechanical dimensions for this package are provided in the figure
below and
(FCBGA), mapped by pin function. This diagram is helpfu l in placing components around the
80331 for the layout of a PCB. To simplify routing and minimize the number of cross traces, keep
this layout in mind when placi ng compo nents on y our board. Th e signals, by des ign, are located o n
the FCBGA package to simplify signal routing and system implementation.
Table 2. FC-style, H-PBGA Package Dimensions
Table 2. Figure 3 and Figure 4 show the 829 pins of the Flip Chip Ball Grid Array
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
B1210-01
20
Intel® 80331 I/O Process orDesign Guide
1
2.1Power Plane Layout
Figure 5 provides an example of how the 80331 DDR, CPU core and 1.5 V core power planes are
partitioned on the Intel® IQ80331 Evaluation Platform Board (IQ80331).
Note: The voltage for the secondary PCIX bus and primary PCIX bus can be on the same plane.
Figure 5. Intel® 80331 I/O Processor Power Plane Layout
VCC_DDR
Package Information
(Use Top Layer for VTT Plane)
DDR DIMM Connector
VCC_XSCALE
VCC 1.5 V
DDR VDD Regulator
To Regulators
B2529-0
21
Intel® 80331 I/O Process orDesign Guide
Package Information
2.2Intel® 80331 I/O Processor Applications
This section provides a block diagram of a 80331 Serial ATA adapter card application. This entire
SATA RAID card adapter can be implemented with just a few chips using the 80331 integrated
PCI-X bridge and IO processing capability.
This chapter provides the recommended pull-up and pull-down terminations for a 80331 layout.
Table 3 li sts these 80331 termination values. On a motherboard, the PCI Local Bus Specification,
Revision 2.3 requires that the PCI signals provide the termination resistors. Pull-ups on the PCI
signals are not required with PCIODT_EN = 1 (enabled), because they are implemented on the die.
Refer to the
Table 3. Terminations: Pull-up/Pull-down (Sheet 1 of 4)
Signal
PWRDELAY
Table 3 for more information.
Pull-up or Pull-down
Resistor Value (in Ohms)
If battery backup is
implemented:
• 1.5 K pull-up to 3.3 V is
required on
PWRDELAY.
Battery Backup not
implemented:
• This pin can be
permanently pulled low
with a 1.5K pull-down
Comments
NOTES:
• Alternatively tied to P_RST# refer to Section 11.4.2, “ARM
TRST#1.5K pull-down*
TMS
TDI
TCK
GPIO[0]/U0_RXD8.2 K pull-upNote : GPIO[7:0] initializes as inputs on assertion of P_RST#.
GPIO[1]/U0_TXD8.2 K pull-upNote: GPIO[7:0] initializes as inputs on assertion of P_RST#.
GPIO[2]/U0_CTS#8.2 K pull-upNote : GPIO[7:0] initializes as inputs on assertion of P_RST#.
GPIO[3]/U0_RTS#8.2 K pull-upN ote: GPIO[7:0] initializes as inputs on assertion of P_RST#.
GPIO[4]/U1_RXD8.2 K pull-upNote : GPIO[7:0] initializes as inputs on assertion of P_RST#.
GPIO[5]/U1_TXD8.2 K pull-upNote: GPIO[7:0] initializes as inputs on assertion of P_RST#.
GPIO[6]/U1_CTS#8.2 K pull-upNote : GPIO[7:0] initializes as inputs on assertion of P_RST#.
GPIO[7]/U1_RTS8.2 K pull-upNote: GPIO[7:0] initializes as inputs on assertion of P_RST#.
ARB_EN(see comments)
NC when not being used
(has internal pull-up)
NC when not being used
(has internal pull-up)
1.5K pull-down when not
used
Multi-ICE” on page 142 for more information about using with a
ICE.
• When not used this signal is be tied to GND.
• This pin has an internal pull-up.
This signal has been defeatured. Please refer to the Intel® 80331
Specification Update for more information.
23
Intel® 80331 I/O Process orDesign Guide
Terminations
Table 3. Terminations: Pull-up/Pull-down (Sheet 2 of 4)
Signal
PCIODT_EN
P_32BITPCI#
S_INT[D:A]# .Refer to comments
S_LOCK#Refer to comments
S_SERR#Refer to comments
S_TRDY#Refer to comments
S_PERR#Refer to comments
S_DEVSEL#Refer to comments
S_FRAME#Refer to comments
S_STOP#Refer to comments
S_IRDY#Refer to comments
S_AD[63:32]Refer to comments
S_C/BE[7:4 ]Re fe r to c omments
S_PAR64Refer to comments
S_REQ64#Re fer to comments
S_ACK64#Refer to comments
S_M66ENRefer to comments
Pull-up or Pull-down
Resistor Value (in Ohms)
1.5 K pull-down when
needed (see comments)
1.5 K pull-down when
needed (see comments)
PCI Bus ODT Enable: is latched on the rising (deasserting) edge of
P_RST#, and determines when the PCI-X interface has On Die
Termination enabled valid on the secondary PCI bus only.
• 0 = ODT disabled on the secondary PCI bus. (Requires pull-down
resistor).
• 1 = ODT enabled on the secondary PCI bus. (Default mode).
This signal controls termination for the following signals:
S_AD[63:32], S_C/BE[7:4]#, S_PAR64, S_REQ64#, S_REQ[3:0]#,
NOTE: This signal is muxed onto signal A[20].
Primary PCI-X Bus Width: By default, identifies 80331 subsystem as
64-bit unless user attaches appropriate pull-down resistor.
0 = 32 bit wide bus. (Requires pull-down resistor).
1 = 64 bit wide bus. (Default mode).
NOTE: Muxed onto signal A[2]
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required when PCI
bus is to operate at 66 MHz. This signal is grounded for 33 MHz
operation.
Comments
24
Intel® 80331 I/O Process orDesign Guide
Table 3. Terminations: Pull-up/Pull-down (Sheet 3 of 4)
Signal
S_RCOMP100 ohm +/- 1% to GND
SCLKIN
S_REQ[3:0]#Refer to comments
S_PCIXCAPRefer to comments
PRIVMEM
PRIVDEV1.5 K pull-down when
P_RCOMP100 ohm +/- 1% to GND
P_REQ#Refer to comments
P_LOCK#Refer to comments
P_SERR#Refer to comments
P_TRDY#Refer to comments
P_PERR#Refer to comments
P_DEVSEL#Refer to comments
P_FRAME#Refer to comments
P_STOP#Refer to comments
P_IRDY#Refer to comments
P_AD[63:32]Refer to comments
P_C/BE[7:4]Refer to comments
P_PAR64Refer to comments
P_REQ64#Refer to comments
P_ACK64#Refer to comments
Pull-up or Pull-down
Resistor Value (in Ohms)
Through 33.2ohm resistor
to S_CLKOUT
1.5 K pull-down when
needed (refer to comments)
needed (refer to comments)
• When PCIODT_EN = 1 no external pull-up needed
• When PCIODT_EN = 0, then 8.2 K pull-up is required.
66 MHz PCI: connect pin to GND.
66 MHz PCI-X: use 0.01 µF to GND || 10 K resistor to GND.
100 MHz PCI-X: use 0.01 µF to GND.
133 MHz PCI-X: use 0.01 µF to GND.
Private Memory Enable:PRIVMEM latched at rising (deasserting)
edge of P_RST# and determines when the 80331 operates with
Private Memory Space on the secondary PCI bus of the PCI-to-PCI
Bridge.
0 = Normal addressing mode. Requires pull-down resistor.
1 = Private Addressing enable in PCI-to-PCI Bridge. (Default mode)
Muxed onto signal A[1],Private Device Enable:PRIVDEV latched at rising (deasserting)
edge of P_RST# and determines when the 80331 operates with
Private Device enabled on the secondary PCI bus of the PCI-to-PCI
Bridge.
0 = All Secondary PCI devices are accessible to Primary PCI
1 = Private Devices enabled in PCI-to-PCI Bridge. (Default mode)
Muxed onto signal A[0]
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
Terminations
Comments
1
25
Intel® 80331 I/O Process orDesign Guide
Terminations
Table 3. Terminations: Pull-up/Pull-down (Sheet 4 of 4)
Signal
P_M66ENRefer to comments
P_REQ#Refer to comments
M_CK[2:0], M_CK[2:0]#Refer to commentsFor M_CKs and M_CK#s not used leave these pins unconnected.
DQS[8:0]#Refer to CommentsWhen not in DDRII mode these signals are NC’s
DDRRES[2:1]
HPI#8.2 K pull-up
P_BOOT16#
MEM_TYPE
RETRY
CORE_RST#
BRG_EN
DDRSLWCRESRefer to Figure 9
DDRIMPCRESRefer to Figure 9
ODT[1:0]
Pull-up or Pull-down
Resistor Value (in Ohms)
•Refer to Figure 8 for the
recommended
termination for DDRII
mode.
• When not in DDRII
mode these signals
have a 1.0 K pull-down.
1.5 K pull-down when
needed (refer to comments)
1.5 K pull-down when
needed (refer to comments)
1.5 K pull-down when
needed (refer to comments)
1.5 K pull-down when
needed (refer to comments)
1.5 K pull-down when
needed (refer to comments)
Connect to ODT on DIMM
terminated with 49.9 ohm
resistor to VTT
Comments
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
Bus Width is latched on the rising (asserting) edge of P_RST#, it sets
the default bus width for the PBI Memory Boot window:
• 0 = 16 bits wide (Requires a pull-down resistor.)
• 1 = 8 bits wide (Default mode)
Muxed onto signal AD[4].
Memory Type:MEM_TYPE is latched on the rising (asserting) edge
of P_RST# and it defines the speed of the DDR SDRAM interface.
0 = DDR-II SDRAM at 400 MHz (Required pull-down resistor.)
1 = DDR SDRAM at 333 MHz (Default mode)
Muxed onto signal AD[2]
Configuration Retry Mode: RETRY is lat ched on t he rising (asserting)
edge of P_RST# and determines when PCI interface of the ATU
disables PCI configuration cycles by signaling a retry until the
configuration cycle retry bit is cleared in the PCI configuration and
status register.
0 = Configuration Cycles enabled (Requires pull down resistor.)
1 = Configuration Retry enabled in the ATU and the Configuration.
(Default mode)
Muxed onto signal AD[6]
Core Reset Mode is latched on the rising (asserting) edge of P_RST#
and determines when the Intel
processor reset bit is cleared in PCI configuration and status register.
0 = Hold in reset. (Requires pull-down resistor.)
1 = Do not hold in reset. (Default mode)
Muxed onto signal AD[5]
Bridge Enable: BRG_EN latched at rising (deasserting) edge of
P_RST# and determines when the 80331 operates wi th PCI- to-PCI
The following section describes filters needed for biasing PLL circuitry.
Intel® 80331 I/O Process orDesign Guide
Terminations
3.1.1V
T o reduce clock skew, the V
package. The lowpass filter, as shown in
timing relationships in system designs. The node con necti ng V
short as possible. The
- V
The following notes list the layout guidelines for this filter.
Figure 7. V
CCPLL
Pin Requirements
balls for the Phase Lock Loop (PLL) circuit are isolated on the
CCPLL
Figure 7 reduces noise induced clock jitter and its effects on
and the capacitor must be as
CCPLL
Figure 7 filter circuit is recommended for each of the Four PLL pairs: V
SSA1, VCCPLL2
- V
SSA2, VCCPLL4
- V
SSA4
and V
CCPLL5
- V
SSA5
pairs.
• 4.7 µH (Inductor)
— L must be magnetically shielded
—ESR: max < 0.4Ω
— rated at 45mA
— An example of this inductor is TDK part number MLZ2012E4R7P.
• 22 µF (Capacitor)
—ESR: max < 0.4Ω
— ESL < 3.0nH
— Place 22 µF capacitor as close as possible to package pin.
• 0.5 ohm 1% (Resistor)
— 1/16W 6.3V
• 0.5 ohm 1% resistor must be placed between V
• Route V
• V
CCPLL
[1-5] and V
CCPLL
[1-5] and V
[1-5] as differential traces.
SSA
[1-5] traces must be ground referenced (No VCC references).
SSA
and L. The resistor rating is 1/16W.
CC
• Maximum total board trace length = 1.2”.
• Minimum trace space to other nets = 30 mils.
• The 1.5 V supply regulator used for the PLL filter must have less than +/- 3% tolerance.
• Note: V
Configuration
CCPLL
SSA1
, V
SSA2, VSSA4 and VSSA5
pins must not be connected to ground.
CCPLL1
1.5 V
0.5 ohms , 1%
Note: Do Not conn ect V SSA pins to g round
Board Trace:
Trace w idth > 25 mils
Trace Spac ing < 10 mils
Trace Length < 600 mils
4.7 uH <25%
22 uF <20%
Board Route
Traces
Breakout Traces
Beneath BGA
Breakout Trace:
Trace w idth > 6 mils
Tra c e S pa c in g < 6 mils
Trace Length < 600 mils
VCCPLL
Intel®
I/O Processor
VSSA
27
Intel® 80331 I/O Process orDesign Guide
Terminations
3.2DDR Resistor Compensation
The Figure 8 provides the 80331 DDR II DDRES circuitry. The DDRRES1 resistor has a tight
toleranc e of 40.2 ohm 0.5%. DDRRES2 is used as compensation for DDR-II OCD. Due to the fact that
OCD is not supported this pin should be pulled to GND with a 1K resistor.
s
Note: when not in DDR II mode these pins must have a 1.0 K pull-down to GND.
External reference resistors are used to control slew rate and driver impedance. The
DDRIMPCRES (or DDRDRVCRES) resistor directly controls the on-die termination (ODT). The
recommendations are as follows:
With these values the ODT is 150/75 ohms for DDRII and 200/100 ohms for DDR.
Figure 9. DDR Driver Compensation Circuitry
DDRIMPCRES
DDRCRES0
Intel® 80331 I/O Process orDesign Guide
Terminations
.
385 ohms DDR
285 ohms DDRII
DDRSLWCRES
845 ohms DDR
825 ohms DDRII
29
Intel® 80331 I/O Process orDesign Guide
Terminations
This Page Intentionally Left Blank
30
Intel® 80331 I/O Process orDesign Guide
Routing Guidelines
Routing Guidelines4
This chapter provides some basic ro uting guidel ines for layout and design of a printed circuit board
80331. The high-speed clocking required when designing with the 80331 requires special
using
attention to signal integrity. In fact, it is highly recommended that the board design be simulated to
determine optimum layout for signal integrity. The information in this chapter provides guidelines
to aid the designer with board layout. Several factors influence the signal integrity of a
design. These factors include:
• Power distribution
• Minimizing crosstalk
• Decoupling
• Layout considerations when routing the DDR memory, DDR II memory, and PCI-X bus
interfaces
80331
4.1General Routing Guidelines
This section details general routing guidelines for designing with 80331. The order in which
signals are routed varies from designer to designer. Some designers prefer to route all clock signals
first, while others pre fer to route al l high -speed b us sig nals fi rst. Ei ther ord er can be u sed, pr ovide d
the guidelines listed here are followed.
31
Intel® 80331 I/O Process orDesign Guide
Routing Guidelines
4.2Crosstalk
Crosstalk is caused by capacitive and inductive cou pling between si gnals. Crosstal k is composed of
both backward and forward crosstalk components. Backward crosstalk creates an induced signal on
victim network that propagates in the opposite direction of the aggressor signal. Forward crosstalk
creates a signal that propagates in the same direction as the aggressor signal.
Circuit board analysis software is used to analyze your board layout for crosstalk probl ems. Examples
of 2D analysis tools include Parasitic Parameters from ANSOFT
Crosstalk problems occur when circuit etch lines run in parallel. When board analysis software is not
available, the layout needs to be designed to mai ntain at least the minimum recommended spacing for
bus interfaces.
• A general guideline to use is, that space distance between adjacent signals be a least 3.3 times
the distance from signal trace to the nearest return plane. The coupled noise between adjacent
traces decreases by the square of the distance between the adjacent traces.
• It is also recommended to specify the height of the above reference plane when laying out
traces and provide this parameter to the PCB manufacturer. By moving traces closer to the
nearest reference plane, the coupled noise decreases by the square of the distance to the
reference plane.
Figure 10. Crosstalk Effects on Trace Distance and Height
P
H
aggressorvictim
Reference Plane
• Avoid slots in the ground plane. Slots increases mutual inductance thus increasing crosstalk.
• Throughout the design guide unbroken GND reference planes are recommended. If it is not
possible to route over an unbroken ground plane then an unbroken power plane is acceptable.
If it is necessary to use power plane referencing, it is better to reference the power plane used
by the I/O connector (if applicable). It is also recommended to add decoup ling to the connector
near the pins.
*
and XFS from Quad Design*.
Reduce Crosstalk:
- Maximize P
- Minimize H
A9259-01
• Make sure that ground plane surrounding connector pin fields are not completely cleared out.
When this area is completely cleared out, around the connector pins, all the return current must
flow together around the pin field increasing crosstalk. The preferred method of laying out a
connector in the GND layer is shown in
32
Figure 11B.
Figure 11. PCB Ground Layout Around Connectors
Connector
Connector Pins
GND PCB Layer
A. Incorrect methodB. Correct method
Intel® 80331 I/O Process orDesign Guide
Routing Guidelines
A9260-01
33
Intel® 80331 I/O Process orDesign Guide
Routing Guidelines
4.3EMI Considerations
It is highl y recommended that good EMI design practices be followed when designing wit h the
80331.
• To minimize EMI on your PCB a useful technique is to not extend the power planes to the
edge of the board.
• Another technique is to surround the perimeter of your PCB layers with a GND trace. This
helps to shield the PCB with grounds minimizing radiation.
The below link can provide some useful general EMI guidelines considerations:
Have ample decoupling to ground, for the power planes, to minimize the effects of the switching
currents. Three types of decoupling are: the bulk, the high-frequency ceramic, and the inter-plane
capacitors.
• Bulk capacitance consist of electrolytic or tantalum capacitors. These capacitors supply large
reservoirs of charge, but they are useful only at lower frequencies due to lead inductance
effects. The bulk capacitors can be located anywhere on the board.
• For fast switching currents, high-frequency low-inductance capacitors are most effective.
Place these capacitors as close to the device being decoupled as possible. This minimizes the
parasitic resistance and inductance associated with board traces and vias.
• Use an inter-plane capacitor between power and ground planes to reduce the effective plane
impedance at high frequencies. The general guideline for placing capacitors is to place
high-frequency ceramic capacitors as close as possible to the module.
4.4.1D ecoupling
Inadequate high-frequency decoupling results in intermittent and unreliable behavior.
A general guideline recommends that you use the largest easily available capacitor in the lowest
inductance package. The high speed decoupling capacitor should be placed as close to the pin as
possible with short, wide trace.
Table 4 provides the details on the recommended decoupling capacitors for each of the voltage
1. Polymerized organic capacitors recommended for bulk decoupling.
2. X5R, X7R or COG dielectric recommended for ceramic capacitors.
Number of
Caps
35
Intel® 80331 I/O Process orDesign Guide
Routing Guidelines
4.5Trace Impedance
All signal layers require controlled impedance of 50 Ω +/- 15%, microstrip or stripline where
appropriate for motherboard applicati ons and 60
applications. Selecting the appropriate board stack-up to minimize impedance variations is very
important. When calculating flight times, it is important to consider the minimum and maximum
trace impedance based on the switching neighboring traces. Use wider spaces between traces , since
this can minimize trace-to-trace coupling, and reduce cross talk.
When a different stack up is used the trace widths must be adjusted appropriately. When wider
traces are used, the trace spacing must be adjusted accordingly (linearly).
It is highly recommended that a 2D Field Solver be used to design the high-speed traces. The
following Impedance Calculator URL provide approximations for the trace impedance of various
topologies. They may be used t o generate the starting point for a full 2D Field solver.
http://emclab.umr.edu/pcbtlc/
The following website link provides a useful basic guideline for calculating trace parameters:
http://www.ultracad.com/calc.htm
Ω +/- 15%, microstrip or stripline, for add- in card
Note: Using stripline transmission lines may give better results than m icrost rip. This is due to th e
difficulty of precisely controlling the dielectric constant of the solder mask, and the difficulty in
limiting the plated thickness of microstrip conductors, which can substantially increase cross-talk.
36
Intel® 80331 I/O Process orDesign Guide
Board Layout Guidelines
Board Layout Guidelines5
This section provides details on the motherboard and adapter card stackup suggestions. It is highly
recommended that signal integrity simulations be run to verify each 80331 PCB layout especially
when it deviates from the recommendations listed in these design guidelines. The information in
this chapter is an example of a stackup for a motherboard and an adapter card which can be used as
a reference.
5.1Motherboard Stack Up Information
When 80331 is used in server and workstation Raid On Mother Board (ROMB) appli cations the
motherboard is implemented on eight layers. The specified impedance range for all board
implementations are 50 ohms +/-15%. Adjustments are made for interfaces specified at other
impedances.
The motherboard is supporting other components in addit io n to 8033 1, so i t is ass umed that
server/workstation motherboard requirements dominates to assu re the proc essor and memory
subsystem can be implemented with typical 50-ohm guidelines. Dimensions and tolerances for t he
motherboard are per
Table 5 defines the typical layer geometries for six or eight layer boards.
Table 5. Refer to Figure 12 for location of variables in Table 5.
T a ble 5. Motherboard Stack Up, Stripline and Microstrip (Sheet 1 of 2)
VariableType
Solder Mask
Thickness (mil)
Core Thickness (mil)N/A9.89.610
Core E
Plane Thickness
Trace Height
Trace Thickness
Trace Width (mil)Microstrip5.03.56.5
(mil)
(mil)
Preg E
(mil)
N/A0.80.61.0
N/A 3.653.653.65
r
N/A4.303.754.852113 material.
r
Power2.72.52.9
Ground1.351.151.55
13.53.33.7
23.53.33.7
310.59.911.1
Microstrip4.303.754.852113 material.
Stripline14.303.754.852113 material.
r
Stripline24.664.195.13
Microstrip1.751.22.3
Stripline1.41.21.6
Nominal
(mils)
Minimum
(mils)
Maximum
(mils)
The trace height is determined to achieve a nominal
50 ohms.Solder Mask E
7628 material. Trace height 3 is composed of one
piece of 2113 and one piece of 7628. It is assumed
that the 7628 material covers the bottom and sides
of the layer 3 traces as well as the top and sides of
the layer 4 traces. The 2113 material covers the top
of the layer three traces and the bottom of the layer
4 traces.
Notes
37
Intel® 80331 I/O Process orDesign Guide
Board Layout Guidelines
Table 5. Motherboard Stack Up, Stripline and Microstrip (Sheet 2 of 2)
VariableType
Nominal
(mils)
Minimum
(mils)
Maximum
(mils)
Stripline4.02.55.5
Microstrip15.0--Each interface sets the trace spacing based on its
Trace Spaci ng (mil)
Stripline12.0--
Total Thickness (mil)FR462.056.068.0
Trace V el ocity (ps/in)
Trace Impedance
(ohms)
Microstrip-135141
Stripline167178
Microstrip5042.557.5
Stripline504555
NOTE: Each interface sets the trace spacing based on its signal integrity of differential impedance
requirements. For the purposes of the building the transmission line models, it is assumed the artwork is
very accurate and therefore a constant. Thus, all the variability in the trace spacing is the result of the
tolerances of the trace width.
Figure 12. Motherboard Stackup Recommendations
Notes
signal integrity of differential impedance
requirements. For the purposes of the building the
transmission line models, it is assumed the artwork
is very accurate and therefore a constant. Thus, all
the variability in the trace spacing is the result of the
tolerances of the trace width.
Velocity varies based on variation in Er . It cannot be
controlled during the fab process.
Microstrip
Trace Spacing
L1
L2 (GND)
L3
L4 (VCC)
L5 (VCC)
Total Thickenss
L6
L7 (GN D )
Trace Spacing
Trace Width
L8
S tr ip lin e
Microstrip
L1
L3
Stripline
Trace Width
Microstrip Trace Thickness
Solder M ask Thickness
Trace Height 1
Trace Height 2
Stripline Trace Thickness
Trace Height 3
Core Thickness
Plane Thickness
L6
B3555-01
38
Intel® 80331 I/O Process orDesign Guide
5.2Adapter Card Stackup
The 80331 can be implemented on PCI-X adapter cards with six or eight layer stackups. The
specified impedance range for all adapter card implementations are 60ohms +/-15%. Adjustments
are made for interfaces specified at other impedances.
for six or eight layer boards.
Note: Values are the same as the motherboard stack up with the exception of the impedance.
T a ble 6. Adapter Card Stack Up, Microstrip and Stripline
Table 6 defines the typical layer geometries
Board Layout Guidelines
VariableType
Solder Mask Thickness (mil)N/A0.80.61.0
Solder Mask E
Core Thickness (mil)N/A2.83.03.2
Core E
Plane Thickness (mil)
Trace Height
Trace Thickness (mil)
Trace Width (mil)Microstrip4.02.55.5
Total Thickne ss (mil)FR462.056.068.0
(mil)
Preg E
N/A3.653.653.65
r
N/A4.33.754.852113 material
r
Power2.72.52.9
Ground1.351.151.55
13.53.33.7
23.53.33.7
310.59.911.1
Microstrip4.303.754.852113 material
Stripline14.303.754.852113 material
r
Stripline24.33.754.85
Microstrip1.751.22.3
Stripline1.41.21.6
Stripline4.02.55.5
Nominal
(mils)
Minimum
(mils)
Maximum
(mils)
Notes
The trace height is determined to achieve a
nominal 60 ohms.
7628 material. Trace height 3 is composed
of one piece of 2113 and one piece of
7628.
Trace Spacing (using
microstrip E2E/C2C)
Trace Spacing (using
stripline E2E/C2C)[12]/[16]
Trace Impedance
NOTE: Each interface sets the trace spacing based on its signal integrity of differential impedance
requirements. For the purposes of the building the transmission line models, it is assumed the artwork is
very accurate and therefore a constant. Thus, all the variability in the trace spacing is the result of the
tolerances of the trace width.
[12]/[16]
Microstrip605169
Stripline605169
39
Intel® 80331 I/O Process orDesign Guide
Board Layout Guidelines
Figure 13. Adapter Card Stackup
Microstrip
Trace Spacing
L1
L3
Total Thickenss
L6
Microstrip
Trace Width
L2 (GND)
L4 (VCC)
L5 (VCC)
L7 (GND)
L8
Stripline
Trace Spacing
L1
L3
L6
Stripline
Trace Width
Microstrip Trace Thickness
Solder Mask Thickness
Trace Height 1
Trace Height 2
Stripline Trace Thickness
Trace Height 3
Core Thickness
Plane Thickness
B3555-01
40
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
PCI-X Layout Guidelines6
This chapter describes several factors to be co nsidered with a PCI/PCI-X design. These in clude the
PCI IDSEL, PCI RCOMP, PCI Interrupts, and PCI arbitration.
6.1Interrupt Routing and IDSEL Lines
Figure 14 shows the 80331 connected to three PCI connectors. Notice that the interrupts are rotated
for each connector. The practice of Rotating INTs can also be used when connecting to individual
multifunction PCI devices as well. The IDSEL lines acts as chip selects during the configuration
cycles. Configuration cycles allow read and write access to one of the device configuration space
registers. The IDSEL lines can be mapped to upper address lines which are unused during the
configuration cycles. The ATU is hardwired to AD30 for IDSEL. Note that AD16 typically is
reserved for a PCI/PCI-X bridge. Each IDSEL line needs a 200
in the figure below.
ohm series resistor on it as shown
Figure 14. Interrupt and IDSEL Mapping
S_INT[D:A]#
S_AD[31:0]
®
Intel
80331 I/O
Processor
Note: PCI Bus Interrupt Signals “Rotate” on Subsequent PCI Connectors.
PCI Connector 1
INTA#
INTB#
INTC#
INTD#
200
AD20
Ω
INTA#
INTB#
INTC#
INTD#
IDSEL
PCI Connector 2PCI Connector 3
INTB#
INTC#
INTD#
INTA#
AD17
200
Ω
INTA#
INTB#
INTC#
INTD#
IDSEL
INTC#
INTD#
INTA#
INTB#
AD18
200
INTA#
INTB#
INTC#
INTD#
IDSEL
Ω
41
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
6.1.1PCI Arbitration
80331 contains two PCI Arbiters to facilitate arbitration on the primary and secondary PCI buses.
Refer to the PCI Local Bus Specification, Revision 2.3, for more information on arbiter
algorithms. The specification essentially states that the algorithm needs to be fair to prevent any
one device from consuming to much of the PCI bandwidth.
A typical implementation of the arbitration logic is a two-level rotating round robin configuration.
A high priority status is assigned to a master request in level one and a low-level priority statu s is
assigned to a master request in level two. The arbiter checks each of the REQ# lines in the first
level. When none are asserted it traverses to checking level two. Once the GNT# has been asserted
to a master, this master has the lowest priority in its level.
The arbiter also conducts bus parking by driving A/D, C/BE# and PAR lines to a known value while
the bus is idle. The arbiter typically leaves the GNT# asserted to the master that used the bus last.
6.1.2PCI Resistor Compensation
Figure 15 provides the recommended resistor compensation pin termination for the PCI primary
and secondary buses. The voltage at the RCOMP pins is 0.75 V and a 1/16 W resistor rating is
acceptable.
Figure 15. PCI RCOMP
S_RCOMP
100 Ω
P_RCOMP
100 Ω
42
Intel® 80331 I/O Process orDesign Guide
6.2PCI General Layout Guidelines
For acceptable signal integrity with bus speeds up to 133 MHz it is important to PCB design layout
to have controlled impedance.
• Signal trace velocity needs to be roughly 150 – 190 ps/inch
• The following signals have no length restrictions: P_INT[D:A], S_INT[D :A] and TCK, TDI,
TDO, TMS and TRST#
6.3PCI-X Topology Layout Guidelines
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, recommends the
following guidelines for the number of loads for your PCI-X designs. Any deviation from these
maximum values requires close attention to layout with regard to loading and trace lengths.
The following sections describe layout recommendations based on the signal integrity simulation
analysis. This analysis was conducted using the following parameters:
• Receiver Model: generic models for PCI-X and PCI
• Driver Package Model: 80331 model
• Connector Model: Multiline coupled model
• Generic Spec Models: PCI-X and PCI
• Cross talk impact on timing was modeled
• Process corners for PCB stack and trace geometries were modeled
• PVT corner cases for buffers and package models were modeled
• Signal quality analysis covered rise time at the receiver, fall time at the receiver, rising flight
time, falling flight time, low to high ring-back (noise margin high), high to low ringback (noise
margin low) and low and high overshoot.
Note: The overshoot and undershoot exceeded the specifications. The r equirement calls for 0 .5 V and the
observed overshoot in simulation was 1.2 V. This fact needs to be taken into consideration when
accessing the reliability of your application.
The following notes should be considered when designing to this section’s design guide
recommendations:
1. The lengths recommended for AD lines are given as a range of length (for example 2.0” to
5.0”). This means that each AD bit can be routed any where between this range. There is no
length matching required among AD bits. For example, AD1 can be 2.0” and AD2 can be
5.0”. Routing anywhere in this range assures that the bit will meet the Set up and Hold time
requirement. This is because each bit is sampled with respect to a common clock, independent
of its relation with other bits.
2. There is no length matching requirement between Clock and AD bits. This means, that the
clock can be routed to 6” and any AD bit can be 2”. However the length matching requirement
among clocks to each devices (and feedback clock) remains.
3. If your board aligns to the topology in these recommendations with the exception of one or
more devices, these requirements listed are still valid. Each of the recommendations is made
with an assumption that any device can be a “no mount”. In this case adding the length before
and after the “no mount” device, as a single segment is acceptable.
44
6.4.1PCI Clock Layout Guidelines
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, allows a maximum of
ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz and 133 MHz. A
0.5
typical PCI-X application may require separate clock point-to-point connections distributed to each
PCI device. 80331 provides four buffered clocks on the secondary PCI bus, S_CLKO[3:0]to
connect to multiple PCI-X devices. The
outputs and length matching requirements. The recommended clock buffer layout are specified as
follows:
• Match each of the 80331 output clock lengths to within 25 mils to help minimize the skew.
• Keep distance between clock lines and other signals “d” at least 25 mils from each other.
• Keep distance between clock line and itself “a” at a minimum of 25 mils apart (for serpentine
clock layout).
• S_CLKIN gets connected to S_CLKOUT through a 22 ohm res istor
• The 22 ohm resistor is placed within 1” maximum distance of S_CLKOUT.
• A series termination resistor with the value of 22 ohm resistor is placed within 1” maximum
distance of each of the clock outputs SCLKO[3:0].
Figure 16 shows the use of four secondary PCI clock
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
Note: Using the value of 33.2 ohm for the series termination resistor is also acceptable.
Figure 16. PCI Clock Distribution and Matching Requirements
9
22
S_CLKIN
®
Intel
80331
I/O
Processor
Notes:
– PCI Clock lengths X0, X1, X2, X3 and X4 should be matched within 25 mils of each other.
– Minimum separation between two different CLKs, "d"
– Minimum separation between two segments of the same CLK line, "a"
– 22 Ohm resistor must be placed less than 1” of the S_CLKOUT output.
– 22 Ohm resistors must be placed less than 1” of the S_CLKO[0:3] outputs.
Signal GroupPCI Clock S_CLKO[3:0].
Reference PlaneRoute over unbroken ground plane.
Preferred TopologyStripline
Breakout
Motherboard Impedance (for both
microstrip and stripline).
Add-in card Impedance (for both
microstrip and stripline).
Stripline Trac e Spacing: Separation
between two different clock lines, “d”
clock lines.
Stripline Trac e Spacing: Separation
between two segments of the same
clock line (on serpentine layout), “a”
dimension.
Stripline Trac e Spacing: Separation
between clocks and other lines.
Length Matching Requirements for
Topologies having NO Slot
Length Matching Requirements for
Topologies having only Slot
Length Matching Requirements for
Topologies having both Slots and
Embedded Devices
Total Length of 80331 PCI CLKs on a
motherboard (or embedded design).
Total Length of Clock Line in an
Add-in Card.
Series Termination.22 ohms 1%
Trace Length from driver to series
termination.
S_CLKIN Series Termination.
Maximum ske w for PCIX.0.3 ns.
5 mils on 5 mils spacing. Maximum le ngth of breakou t regio n is
500mils.
50 ohms +/- 15%.
57 ohms +/- 15%.
25 mils edge to edge from any other signal.
25 mils edge to edge from any other signal.
50 mils edge to edge from any other signal.
• Each of the Clock out (Clk0 - Clk3) should be length matched
to the Feedback Clk (Feedback Clock is that running from
CLKOUT to CLKIN). The length matching should be within 25
mills.
• Each of the Clock out (Clk0 - Clk3) to the Slots should be
length matched to within 25mils.
• The Feedback Clk (Feedback Clock is that running from
CLKOUT to CLKIN) should be routed 3.5” longer than the
Clocks running to the Slots. This should be done to a tolerance
of within 25 mills.
• Each of the Clock out (Clk0 - Clk3) to the Slots (if more than 1
slot) should be length matched to within 25mills.
• The Clock out to the Embedded Device(s) should be routed
3.5” longer than the Clocks running to the Slots. This should be
done to a tolerance of within 25 mills.
• The Feedback Clk (Feedback Clock is that running from
CLKOUT to CLKIN) should be routed 3.5” longer than the
Clocks running to the Slots. This should be done to a tolerance
of within 25 mills.
Less than 14.0” maximum.
2.4” minimum to 2.6” maximum.
1” maximum.
Connect S_CLKIN to one end of a 22 ohm resistor and the other
end connected to S_CLKOUT.
46
Intel® 80331 I/O Process orDesign Guide
Table 8. PCI-X Clock Layout Requirement s Summary (Sheet 2 of 2)
ParameterRouting Guidelines
Maximum skew for PCI.1.0 ns.
Routing Guideline 1.
Routing Guideline 2.
Point-to-point signal routing needs to be used to keep reflections
low.
Same number of vias and routing layers as all the other clock lines
from the driver to the receiver.
PCI-X Layout Guidelines
47
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
6.4.2Single-Slot at 133 MHz
Figure 17 shows one of the chipset PCI AD lines connected through TL_AD1 line segments to a
P
Figure 17. Single-Slot Point-to-Point Topology
single-slot connector CONN1 through TL1 line segment to the 80331.
AD1
TL_AD1
CONN1
TL1
Table 9. PCI-X 133 MHz Single Slot Routing Recommendations
ParameterRouting Guideline for Lower AD Bus Routing Guideline for Upper AD Bus
Reference Plane
Preferred Layer
Breakout5 mils on 5 mils spacing. Maximum length of breakout region is 500 mils.
Motherboard Impedance (for
both microstrip and stripline)
Add-in card Impedance (for
both microstrip and stripline)
Stripline Trace Spacing12 mils from edge to edge
Microstrip Trace Spacing18 mils from edge to edge
Group SpacingSpacing from other groups: 25 mils minimum edge to edge
Trace Length 1 (TL1): From
80331 signal Ball to first
junction
Trace Length 2 (TL_AD1)from connector to receiver
Length Matching
Requirements:
Number of viasTwo vias maximum
Route over an unbroken ground plane
Stripline
50 ohms +/- 15%
57 ohms +/- 15%
2.25” minimum - 7.5” maximum1.25” minimum - 6.75” maximum
0.75” minimum - 1.5” maximum1.75” minimum - 2.75” maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines Table 8.
48
6.4.3Embedded PCI-X 133 MHz
This section lists the routing recommendations for PCI-X 133 MHz without a slot. Figure 18 shows
the block di agram of thi s topology and Table 10 describes the routing recommendations.
Reference Plane
Preferred Layer
Break out5 mils on 5 mils spacing. Maximum length of breakout region is 500 mils
Motherboard impedance (both
Microstrip and stripline)
Add-in card impedance (both
Microstrip and stripline)
Stripline Trace Spacing12 mils, edge to edge
Microstrip Trace Spacing18 mils, edge to edge
Group SpacingSpacing from other groups: 25 mils minimum edge-to-edge
Trace Length 1 (TL1): From 80331
signal Ball to first junction
Trace Length 2 junction of TL_EM1
and TL_EM2 to embedded device
Length Matching Requirements:
Number of viasThree vias for each path
Route over an unbroken ground plane
Stripline
50 ohms +/- 15%
60 ohms +/- 15%
1.75” minimum - 4.0” maximum
1.25” minimum - 3.25” maximum
No length matching is required among datalines. For length matching for
clocks, refer clock guidelines Table 8.
TL_EM2
EM 2
49
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
6.4.4Embedded PCI-X 133 MHz Alternate Topology
This section lists another embedded topology with routing recommendations for PCI-X 133 MHz.
Figure 19 shows the block diagram of this topology and Table 11 describes the routing
Reference Plane
Preferred Layer
Break out5 mils on 5 mils spacing. Maximum length of breakout region is 500 mils
Motherboard impedance
(both Microstrip and stripline)
Add-in card impedance (both
Microstrip and stripline)
Stripline Trace Spacing12 mils edge to edge
Microstrip Trace Spacing18 mils, edge to edge
Group SpacingSpacing from other groups: 25 mils minimum edge to edge
Trace Length 1 (TL1): From
80331 signal Ball to first
device
Trace Length 3 TL2: First
device to second device.
Length Matching
Requirements:
Number of viasThree vias for each path
Route over an unbroken ground plane
Stripline
50 ohms +/- 15%
60 ohms +/- 15%
1.5” minimum - 3.5” maximum
1.5” minimum - 3.5” maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines Table 8.
50
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
6.4.5Combination of PCI-X 133 MHz Slot and Embedded Topology
Figure 20and Table 12 combine the two topologies using both a slot and an embedded device.
Figure 20. Embedded PCI-X 133 MHz Topology
AD1
EM1
TL_AD1
TL_EM1
CONN1
TL1
Table 12. Embedded and Slot PCI-X 133 MHz Routing Recommendations
ParameterRouting Guid eline for Lower AD Bus Routing Guideline for Uppe r AD Bus
Reference Plane
Preferred Layer
Break out5 mils on 5 mils spacing. Maximum length of breakout region is 500 mils
Motherboard impedance
(both Microstrip and stripline)
Add-in card impedance (both
Microstrip and stripline)
Stripline Trace Spacing12 mils edge to edge
Microstrip Trace Spacing18 mils, edge to edge
Group SpacingSpacing from other groups: 25 mils min, center to center
Trace Length 1 (TL1): From
80331 signal ball to first
junction
Trace Length 3 TL_EM1
from the first junction to the
embedded device
Trace Length TL_AD1 - from
connector to the receiver
Length Matching
Requirements:
Number of viasThree vias max
Route over an unbroken ground plane
Stripline
50 ohms +/- 15%
57 ohms +/- 15%
1.25” minimum - 3.0” maximum1.25” minimum - 3.0” maximum
1.25” minimum - 3.75” maximum1.25” minimum - 3.75” maximum
0.75” - 1.5” maximum1.75” - 2.75” maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines Table 8.
51
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
6.4.6Combination PCI-X 133 MHz Slot and Embedded Topology 2
Figure 21and Table 13 combine the two topologies using both a slot and an embedded device.
Figure 21. Embedded PCI-X 133 MHz Topology
AD1
TL_AD1
EM1
CONN1
TL1
TL2
Table 13. Embedded and Slot PCI-X 133 MHz Routing Recommendations
ParameterRouting Guideline for Lower AD Bus Routing Guideline for Upper AD Bus
Reference Plane
Preferred Layer
Break out5 mils on 5 mils spacing. Maximum length of breakout region is 500 mils
Motherboard impedance
(both Microstrip and stripline)
Add-in card impedance (both
Microstrip and stripline)
Stripline Trace Spacing12 mils edge to edge
Microstrip Trace Spacing18 mils, edge to edge
Group SpacingSpacing from other groups: 25 mils min, center to center
Trace Length TL1: From
80331 signal ball to
embedded device.
Trace Length TL2: - from
Embedded Device to PCIX
connector CONN1
Trace Length TL_AD1 - from
connector to the receiver
Length Matching
Requirements:
Number of viasThree vias max
Route over an unbroken ground plane
Stripline
50 ohms +/- 15%
57 ohms +/- 15%
1.25” minimum - 2.0” maximum1.25” minimum - 2.0” maximum
1.25” minimum - 3.5” maximum1.25” minimum - 3.0” maximum
0.75” - 1.5” maximum1.75” - 2.75” maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines Table 8.
52
6.4.7PCI-X 100 MHz Slot Topology
Figure 22and Table 14 provide details on the PCI-X 100 MHz slot topology.
ParameterRouting Guid eline for Lower AD Bus Routing Guideline for Uppe r AD Bus
Reference Plane
Preferred Layer
Breakout5 mils on 5 mils spacing. Maximum length of the breakout is 500 mils.
Motherboard Trace
Impedance (microstrip and
stripline)
Add-in card Impedance
(microstrip and stripline)
Stripline Trace Spacing12 mils, from edge to edge
Microstrip Trace Spacing18 mils, from edge to edge
Group SpacingSpacing from other groups: 25 mils min, center to center
Trace Length 1 TL1: From
80331 signal Ball to first
junction
Trace Length TL2 - between
junction and connector
Trace Length TL_AD1,
TL_AD2- from connector to
receiver
Length Matching
Requirements:
Number of viasThree vias max
Route over an unbroken ground plane
Stripline
50 Ohms +/- 15%
57 Ohms +/- 15%
1.0” minimum - 9.5” maximum1.0” - 7.0” maximum
0.8” - 1.1” maximum0.8” - 1.1” maximum
0.75” minimum - 1.5” maximum1.75” minimum - 2.75” maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines Table 8.
AD2
TL_AD2
CONN2
TL3
53
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
6.4.8PCI-X 100 MHz Embedded Topology
Figure 23and Table 15 combine both a slot and an embedded device.
Breakout5 mils on 5 mils spacing. Maximum length of the breakout is 500 mils.
Motherboard Trace
Impedance (microstrip and
stripline)
Add-in card Impedance
(microstrip and stripline)
Stripline Trace Spacing12 mils, from edge to edge
Microstrip Trace Spacing18 mils, from edge to edge
Group SpacingSpacing from other groups: 25 mils minimum edge to edger
Trace Length 1 TL1: From
80331 signal Ball to first
junction
Trace Length TL_EM1 between junction and
embedded device
Trace Length TL_EM2,
TL_EM3- from second
junction to embedded
devices
Length Matching
Requirements:
Number of viasFour vias maximum for each path
Route over an unbroken ground plane
Stripline
50 Ohms +/- 15%
60 Ohms +/- 15%
0.5” minimum - 3.0” maximum
2.5” - 3.5” maximum
1.5” minimum to 3.5 maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines Table 8.
TL_EM3
TL_EM2
EM3
EM2
54
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
6.4.9PCI-X 100 MHz Slot and Embedded Topolo gy
Figure 24and Table 16 combine both slots and an embedded device.
Figure 24. Combination of Slot and Embedded PCI-X 100 MHz Routing Topology
EM1
TL_EM1
TL1
AD1
TL_AD1
CONN1
TL2
AD2
TL_AD2
CONN2
Table 16. Combination of Slot and Embedded PCI-X 100 MHz Routing Recommendations
ParameterRouting Guid eline for Lower AD Bus Routing Guideline for Uppe r AD Bus
Reference Plane
Preferred Layer
Breakout5 mils on 5 mils spacing. Maximum length of the breakout is 500 mils.
Motherboard Trace
Impedance (microstrip and
stripline)
Add-in card Impedance
(microstrip and stripline)
Stripline Trace Spacing12 mils, from edge to edge
Microstrip Trace Spacing18 mils, from edge to edge
Group SpacingSpacing from other groups: 25 mils minimum edge to edge
Trace Length 1 TL1: From
80331 signal Ball to first
connector CONN1
Trace Length TL2 - first PCI
connector CONN1 to second
PCI connector CONN2
Trace Length TL_AD1,
TL_AD2 - from PCI
connector to receiver
Trace Length TL_EM1 - from
second connector CONN2 to
embedded device
Length Matching
Requirements:
Number of viasThree vias maximum
Route over an unbroken ground plane
Stripline
50 Ohms +/- 15%
57 Ohms +/- 15%
2.0” minimum - 3.75” maximum2.0”minimum - 3.0” maximum
0.8” minimum - 1.2” maximum
2.25” minimum - 3.75” maximum2.25” minimu m - 3.5” maximum
0.75” minimum - 1.5” maximum1.75” minimum - 2.75” maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines Table 8.
55
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
6.4.10PCI-X 100 MHz Slot and Embedded Topology 2
Figure 24and Table 16 combine both a slots and an embedded device.
Figure 25. Combination of Slots and Embedded PCI-X 100 MHz Routing Topology
TL1
EM1
TL_EM1
TL2
AD1
CONN1
TL_AD1
AD2
TL_AD2
CONN2
TL3
Table 17. Combination of Slot and Embedded PCI-X 100 MHz Routing 2 Recommendations
(Sheet 1 of 2)
ParameterRouting Guideline for Lower AD Bus Routing Guideline for Upper AD Bus
Reference Plane
Preferred Layer
Breakout5 mils on 5 mils spacing. Maximum length of the breakout is 500 mils.
Motherboard Trace
Impedance (microstrip and
stripline)
Add-in card Impedance
(microstrip and stripline)
Stripline Trace Spacing12 mils, from edge to edge
Microstrip Trace Spacing18 mils, from edge to edge
Group SpacingSpacing from other groups: 25 mils minimum edge to edge
Trace Length 1 TL1: From
80331signal Ball to first
junction
Trace Length TL2 - first
junction to First PCI
Connector
Trace Length TL3 - First PCI
Connector to Second PCI
Connector
Trace Length TL_EM1 - from
first junction to the
Embedded Device.
Route over an unbroken ground plane
Stripline
50 Ohms +/- 15%
57 Ohms +/- 15%
1.5” minimum - 4.25” maximum1.5”minimum - 3.75” maximum
0.0” minimum to 1.0” maximum
0.8” minimum - 1.2” maximum
1.0” minimum - 3.25” maximum1.0” minimum - 3.25” maximum
56
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
Table 17. Combination of Slot and Embedded PCI-X 100 MHz Routing 2 Recommendations
(Sheet 2 of 2)
Trace Length TL_AD1,
TL_AD2 - from connector to
0.75” minimum - 1.5” maximum1.75” minimum - 2.75” maximum
receiver
Length Matching
Requirements:
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines Table 8.
Number of viasThree vias maximum
6.4.11PCI-X 66 MHz Slot Topology
Figure 26 and Table 18 provides routing details for a topology with for an embedded PCI-X
Reference PlaneRoute over an unbroken ground plane
Breakout5 mils on 5 mils spacing. Maximum length of the breakout is 500 mils.
Motherboard Trace
Impedance (microstrip and
stripline)
Add-in card Impedance
(microstrip and stripline)
Stripline Trace Spacing12 mils, from edge to edge
Microstrip Trace Spacing18 mils, from edge to edge
Group SpacingSpacing from other groups: 25 mils minimum center to center
Trace Length 1 (TL1): From
80331 signal Ball to first
junction
Trace Length TL2 to TL4
between junctions
50 Ohms +/- 15%
57 Ohms +/- 15%
1.0” minimum - 6.0” maximum1.0” minimum - 4.75” maximum
ParameterRouting Guideline for AD BusRouting Guideline for Upper AD Bus
Reference PlaneRoute over an unbroken ground plane
Breakout5 mils on 5 mils spacing. Maximum length of the breakout is 500 mils.
Motherboard Trace
Impedance (microstrip and
stripline)
Add-in card Impedance
(microstrip and stripline)
Stripline Trace Spacing12 mils, from edge to edge
Microstrip Trace Spacing18 mils, from edge to edge
Group SpacingSpacing from other groups: 25 mils minimum center to center
Trace Length 1 TL1: From
80331 signal Ball to first slot
50 Ohms +/- 15%
57 Ohms +/- 15%
1.0” minimum - 5.0” maximum1.0” minimum - 4.5” maximum
ParameterRouting Guideline Lower A D BusRouting Guideline Upper AD Bus
Reference PlaneRoute over an unbroken ground plane
Breakout5 mils on 5 mils spacing. Maximum length of the breakout is 500 mils.
Motherboard Trace Impedance (microstrip and
stripline)
50 Ohms +/- 15%
62
Intel® 80331 I/O Process orDesign Guide
PCI-X Layout Guidelines
T able 23. PCI 66 MHz Mixed Mode Table (Sheet 2 of 2)
ParameterRouting Guideline Lower AD BusRouting Guideline Upper AD Bus
Add-in card Impedance (microstrip and stripline)57 Ohms +/- 15%
Stripline Trace Spacing10 mils, from edge to edge
Microstrip Trace Spacing15 mils, from edge to edge
Group SpacingSpacing from other groups: 25 mils minimum edge-to-edge
Trace Length 1 TL1: From 80331 signal Ball to f irst
connector
Trace Length TL_EM1, TL_EM2: From 1st PCI
connector to embedded device
Trace Length TL_AD1 from PCI connector to
receiver
Length Matching Requirements
1.0” minimum to 5.0” maximum1.0” minimum - 4.5” maximum
1.5” minimum - 4.0” maximum
0.75” minimum - 1.5” maximum1.75” minimum - 2.75” maximum
No length matching is required among datalines. For length matching for
clocks, refer clock guidelines Table 8.
Number of ViasFour vias maximum
6.4.17PCI 33 MHz Slot Topology
Figure 32 and Table 24 provides routing details for a topology with for a PCI 33 MHz design with
Reference PlaneRoute over an unbroken ground plane
Breakout5 mils on 5 mils spacing. Maximum length of the breakout is 500 mils.
Motherboard Trace
Impedance (microstrip and
stripline)
Add-in card Impedance
(microstrip and stripline)
Stripline Trace Spacing10 mils, from edge to edge
Microstrip Trace Spacing15 mils, from edge to edge
Group SpacingSpacing from other groups: 25 mils minimum edge-to-edge
Trace Length 1 TL1: From
80331 signal Ball to first
connector
50 Ohms +/- 15%
57 Ohms +/- 15%
1” minimum - 7.0” maximum1” minimum - 6.5” maximum
Reference PlaneRoute over an unbroken ground plane
Breakout
Motherboard Trace Impedance (microstrip and
stripline)
Add-in card Impedance (microstrip and
stripline)
5 mils on 5 mils spacing. Maximum length of the breakout is
500 mils.
50 Ohms +/- 15%
57 Ohms +/- 15%
Stripline Tr ace Spacing10 mils, from edge to edge
Microstrip Trace Spacing15 mils, from edge to edge
Group SpacingSpacing from other groups: 25 mils minimum edge-to-edge
Trace Length 1 TL1: 80331 signal Ball to 1st
junction
Trace Length TL2 from 1st junction to 1st PCI
connector
Trace Length TL3 to TL5 between connectors 0.75” minimum - 1.5” maximum
Length Matching Requirements
Number of viasFour vias maximum
Routing Guideline for lowe r AD
Bus
1.0” minimum - 5.5” maximum
1.5 - 4.0” maximum
No length matching is required among datalines. For length
matching for clocks, refer clock guidelines Table 8.
Routing Guideline for
upper AD Bus
1.0” minimum - 5.5”
maximum
1.75” minimum - 2.75”
maximum
66
Intel® 80331 I/O Process orDesign Guide
Memory Controller
Memory Controller7
The Memory Controller allows direct control of a DDR SDRAM memory subsystem. It features
programmable chip selects and support for error correction codes (ECC). The memory controller can
be configured for DDR SDRAM at 333 MHz and DDR-II at 400MHz. The memory controller
supports pipelined access and arbitration control to maximize performance. The memory controll er
interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete DDR
SDRAM devices.
External memory can be configured as host addressable memory or private 80331memory utilizing
the Address Translation Unit and Bridge.
7.1DDR Bias Voltages
The 80331 supports 2.5 V DDR memory and 1.8V for DDRII. Table 27 lists the
minimum/maximum values for the DDR memory bias voltages and Table 28 lists the
minimum/maximum values for the DDR II memory bias voltages.
T a ble 27. DDR Bias Voltages
SymbolParameterMinimumMaximumUnits
V
V
V
CC25
DDQ
REF
V
2.5 V Power balls to be connected to a 2.5 V power board plane.2.32.7V
80331 with the DDR-SDRAM memory sub-system needs continuous ground referencing for all
DDR signals. The DDR channel requires the referencing stack-up to allow ground referencing on
all of the DDR signals from the 80331 to the parallel termination at the end of the channel.
Note: Leave unused M_CKs and M_CK#s unconnected.
The 80331 signal integrity specifications are for a single DIMM only for both DDR333 and DDR
II 400. The DIMM topology supported for the recommendations listed in this section are for x8
single / double banks and x16 single/double banks.
DDR333 = single DIMM and supports both Buffered / Unbuffered DIMM
DDRII 400 = single DIMM and supports Buffered DIMM
Table 29 details the 80331 Core Speed and DDR/DDRII memory configuration.
Table 29. Core Speed and Memory Configuration
Core/DDRDDR333DDR-II 400
Low500MHz500MHz
Medium667MHzN/A
HighN/A800MHz
The DDR interface is divided up into three groups that each have s pecial routing guidelines:
• Source synchronous signal group: DQ/DQS/DQM/CB signals
• Clocked: M_CK signals
• Control signals: Address/RAS/CAS/CS/WE/CKE signals
• Clock Target Differential Impedance 100 oh ms and 50 ohms single-ended impedance.
• Memory Model Micron T17A_DQ and Intel generic models.
• PLL Clock - Pericom* CDCBV857, PI6DCV16859.
• DIMM models and topologies used the JEDEC model as a reference.
• For unbuffered emb edded and po st PLL/r egi ster t he st andard r ecommendation s were us ed as a
reference.
• Spacing recommendations are for trace edge to edge except for differential pairs in which
center to center was specified.
• Signal Quality analysis covered for Rising flight time, Falling flight time, Low to high
ring-back (noise margi n high) , High t o Low ring- back ( noise mar gi n Low), and Low and H igh
Overshoot.
• Crosstalk Analysis was performed for all the major interfaces with actual package models.
• Frequency: 167MHz (DDR 333 MT/s).
• Connector –E SPICE of DIMM Connector (Derived from SPICE Circuit)
• Package - Actual extracted Package Model used.
The topologies simulated are listed in Table 30.
T a ble 30. Simulated DDR 333 Top ologies
DIMMEmbedded
1. DQ/DQS
• Read- RAW A, RAWB
• Write -RAW A, RAW B
2. Clock
•Buffered
• Unbuffered
3. Address/CMD
• Registered
• Unbuffered - RAWA, RAWB
1. DQ/DQS
• Read- Single Bank
• Write - Single Bank
2. Clock
•Buffered
• Unbuffered
•Post-PLL
• PLL to SDRAM
• PLL to Register
• PLL to Feedback
3. Address/CMD
• Registered
• Unbuffered - Single bank ECC and non ECC
• Post Register - single bank ECC and non ECC
69
Intel® 80331 I/O Process orDesign Guide
Memory Controller
7.3.1DDR 333 Stackup Example
Table 31 below provides an example of a table of recommended topologies for motherboard and
add-in card eight layer PCB designs. Figure 35 provides an example of a cross section used to
implement 100 ohm differential trace impedance.Throughout this section the important
recommendation to meet is the trace impedance. The example in
reference.
Table 31 is provided as a
70
Table 31. Example Topologies for DDR Trace
Intel® 80331 I/O Process orDesign Guide
Memory Controller
Topology
Microstrip
(layers 1 or 8)
Stripline
(layers 3 or 6)
1. Microstrip Differential Lines: Motherboard/Add-in 100 ohm: Constructed by two microstrips of 5 mils traces
separated by center to center distance of 13 mils as shown in Figure 35.
2. Strip Differential Lines: Motherboard Stripline 100 ohms: Constructed by two striplines of 4 mils traces
separated by center to center distance of 12 mils as shown in Figure 35.
3. Strip Differential Lines: Add-in stripline 100 ohms: Constructed by two striplines of 4 mils traces separated by
center to center distance of 13 mils as shown in Figure 35.
The following sections provide layout information for 80331 DDR333 configuration.
7.4.1Source Synchronous Signal Group
The guidelines below are for the source synchronous signal group which includes Data bits DQ,
check bits CB, data mask DM, and DQS associated strobe.
The 80331 source synchronous signals are divided into groups consisting of data bits DQ and
check bits CB. There is an associated strobe DQS for each DQ, DM and CB group. When data
masking is not used system me mory DM pi ns on the D DR needs to be tied to ground. The groupi ng
is as follows for the different memory configurations:
TL3Microstrip0.25”0.5”Same as TL2Fan out for series termination
TL4VttMicrostrip0.150.5”5 milsSplit termination
Microstrip/
Stripline
Minimum
Length
Maximum
Length
0.5”5 mils
Trace
Impedance
45 ohms +/- 15%
or
50 ohms +/- 15%
SpacingNo tes
12 mils
Lead-in traces are preferred as
striplines.
Figure 39. DIMM DQ/DQS Split Termination Topology
2.5V
100 ohms
+/- 5%
TL1TL2TL3
22 ohms +/- 5%
TL4
DIMM
GND
100 ohms
+/- 5%
80
7.4.2Clock Signal Groups
The 80331 drives the command clock signals required by the DDR interface. The source-clocked
signals are “clocked” into the DIMM using the command clock signals. The 80331 drives the
command clock signals and the source-clocked signals together, these signals can be source
clocked. The 80331 drives the command clock in the center of the valid window, and the
source-clocked signals propagate with the command clock signal. An important timing
specification is the difference between the command clock flight time and the source clocked
signal flight time. The absolute flight time is not as critical.
The common clock signal group con tains M_CK[2:0] and M_CK[2:0]#. The fo llowing tables an d
figure show the routing requirements for the clock signal group.
T a ble 39. DIMM Clocked Signal Group Termination
DDR SDRAMRs SeriesRp Parallel
22.1 +/- 5% ohms (non-buffered DDR only)none
Intel® 80331 I/O Process orDesign Guide
Memory Controller
81
Intel® 80331 I/O Process orDesign Guide
Memory Controller
Table 40. Clock Signal Group Registered/Unbuffered DIMM Routing Requirements
ParameterRouting Guideline
Reference Plane
Preferred Topology
Preferred Topology
Breakout trace width and spacing5 mils x 5 mils routed as differential pair
Route over unbroken ground plane
Differential Microstrip (preferred) or differential
stripline
Stripline routing is recommended for the clock signals.
Micro-strip is also acceptable with strict adherence to
all routing recommendations.
Differential: Trace impedance of 100 ohms
Refer to Figure 41
5 mils for breakout
5 mils from one clock M_CK of the differential pair
M_CK#.
>20 mils between the other signals or vias including
other clock pairs.
See Table 37 for the net length details.
<= .5”
2.0” to 10” (correlated within +/- 1.0” of DQ/DQS and
command trace lengths)
Termination:
- Buffered Termination
- Un-Buffered Termi nat ion
Length matching Requi r e m e nts:
• Within differential clock pairs• +/- 0.025” max. within Pairs [Intra-pair]
• With respect to the DQ/DQS group (from die to
DIMM connector)
• With respect to Address/Command group (from
die to DIMM connector)
• Among Unbuffered Clock Pairs
Series Resistor Rs
Parallel Resistor Rp• no parallel resistor required
Routing Guideline 1Clock signals’ polarity needs to be alternated.
Routing Guideline 2Maximum of 2 pair of vias from controller to DIMM
Routing Guideline 3
None required
22.1 ohms +/- 5% series termination on each
differential segment after the breakout.
The package lengths from Die to Ball provided in
Table 37 must be accounted for when length matching
• +/- 1.5” max. when M_CK is routed Stripline
• +/- 1.0” max. when M_CK is routed Micro-strip
• For total capacitive loads greater than 36pF,
M_CK trace lengths must be 2.0” to 3.0” longer
than all ADD/CMD/CTRL trace lengths
• For capacitive loads less than or equal to 36pF,
M_CK trace lengths must be 1.0” to 3.0” longer
than all ADD/CMD/CTRL trace lengths
• +/- 0.1” max. between the 3 pairs of Unbuffered
Clocks
• 22.1 +/- 5% ohms unbuffered
• no series resistor required for registered DIMM’s
Route clock as differential impedance of 100 ohms
with single ended impedance of 50 ohms
82
Table 41. Registered DIMM Clock Topology Lengths
Intel® 80331 I/O Process orDesign Guide
Memory Controller
TracesDescriptionLayer
TL1BreakoutMicrostrip0.5”5 mils
TL2Lead-inMicrostrip2 “10”
Minimum
Length
Maximum
Length
Trace
Impedance
Differential
Impedance 100
ohms +/- 15%
SpacingNo tes
20 mils
from
others
Figure 40. DDR 333 Registered DIMM Clock Topology
TL1TL2
5 mils trace width OK for
breakout.
Route as differential pairs
DIMM
B2526-01
83
Intel® 80331 I/O Process orDesign Guide
Memory Controller
Table 42. DDR 333 Unbuffered DIMM Clock T opology Lengths
TracesDescriptionLayer
Minimum
Length
Maximum
Length
Impedance
TL1
(all 3
clock
BreakoutMicrostrip0.5”5 mils
pairs)
TL2
(all 3 x
clock
pairs)
Lead-in
Microstrip/
Stripline
2 “10”
Differential
Impedance 100
ohms +/- 15%
NOTE: Length matching should be done from die to DIMM connector
1. Between intra pairs +/- 25 mils
2. Between clock pairs M_CK0, M_CK1, M_CK2 +/- 100mils on unbuffered clocks
3. DQS lengths are within +/- 1.5 “ max. of MCK for stripline
4. DQS lengths are within +/- 1.0 “ max. of MCK for stripline
5. Address/Command/Control lengths are with-in 2” to 3” less than MCK
6. Any address/command/control lengths greater than M_CK from die to DIMM is not guaranteed for x2 bank
unbuffered configurations.
Figure 41. DDR 333 Unbuffered DIMM Clock Topology
TL1_CK0
22 ohms +/- 5%
22 ohms +/- 5%
Cloc k Pair CK0
Trace
TL2_CK0
SpacingNo tes
5 mils trace width OK for
breakout.
20 mils
from
others
• Route as differential pairs.
• Series termination of 22
ohms +/- 5%.
184 pin DIMM Connector
Pins 137 & 138
TL1_CK1
TL1_CK2
22 ohms +/- 5%
22 ohms +/- 5%
Cloc k Pair CK1
22 ohms +/- 5%
22 ohms +/- 5%
Cloc k Pair CK2
TL2_CK1
184 pin DIMM Connector
Pins 16 & 17
TL2_CK2
184 pin DIMM Connector
Pins 76 & 75
84
Intel® 80331 I/O Process orDesign Guide
7.4.2.1Control Signals Termination
The control signal group includes RAS#, CAS#, WE#, BA[1:0], MA[12:0], CS[1:0]#, and
CKE[1:0]. The series and parallel termination is shown in Table 43.
Table 43. Source Clocked Signal Routing
DDR SDRAM
7.4.2.1.1Control Signal Routing Guidelines
Figure 42 and Table 44 provide the routing guidelines for the source clocked group of signals.
Figure 42. Trace Length Requirements for Source Clocked Routing
Routing Guideline 1Route these signals on the same layer as the M_CKs.
Routing Guideline 2Minimize layer changes (two vias or less)
Route over unbroken ground plane is preferred.
(Refer to Table for alternatives if this is not feasible).
Micro-strip only for Un-buffered memory
configurations
Either Micro-strip or Stripline for Buffered DIMMs and
lightly loaded Un-buffered DIMMs (i.e. single bank or
dual bank w/ less than or equal to 36pF input
capacitance).
5 mils x 5 mils acceptable through pin field and
terminations
• 45 ohms Motherboard/Add-in card impedance
• 50 ohms Motherboard/Add-in Card Impedance
• Spacing within group 12 mils minimum
• 5 mils acceptable through pin field and
terminations
• > 20 mils from the Clock/DQ/DQS groups
51.1 +/- 5% ohms
OR
Split termination of 100 ohms +/- 5% terminated to
2.5V and 100 ohms +/- 5% terminated to ground
Place Vtt terminations in a Vtt island after the DIMM
See Table 37 for package net length report and
Table 45 for more details.
≤ 0.5”
2.0” to 9.0”
0.15” to 0.5”
The package lengths from Die to Ball provided in
Table 37 must be accounted for when length matching
For total capacitive loads greater than 36pF, all
ADD/CMD/CTRL trace lengths must be 2.0” to 3.0”
shorter than M_CK’s trace length
For total capacitive loads less than or equal to 36pF,
all ADD/CMD/CTRL trace lengths must be 1.0” to 3.0”
shorter than M_CK’s trace length
• Any of the other
groups
(DQ/DQS/Clock) > 20
mils
Single VTT termination in
VTT island is preferred.
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Intel® 80331 I/O Process orDesign Guide
Memory Controller
7.4.3Em bedded Configurati on
The following tables provide layout guidelines for applications in which the DDR 333 memory
SDRAM components are placed directly on the board without a DIMM.
This section lists the recommendations for the DDR 333 embedded source synchronous routing.
These signals include all the DQ/DQS signals. Refer to
matching requirements and Figure 44 for the topology diagram. The topologies simulated are listed
in Table 30.
T able 46. DDR 333 Embedded Source Synchronous Routing Recommendations (Sheet 1 of 2)
ParameterRouting Guideline
Reference Plane
Preferred T opology
Breakout Termination, Fan-in and Fanout width and
spacing
Trace Impedance
Trace Spacing (trace edge to edge)
Package Trace Length:
• Breakout Trace Length (TL1)
• Lead-in to Series Term. Trace Length (TL2)1.0” to 4.0”
• Fan-in/ Fan-out from Series Termination Trace
Length (TL3 & TL4)
• Parallel Termination Trace Length (TL5)
• Lead-in to SDRAM (TL6)1.0” to 4.0”
Length Matching:
• With respect to the clock signal
• Length Matching within DQS group• +/- .05” within DQS group
Series T ermi nation22 ohms +/- 5%
Table 46 and Table 47 for the lengths and
Stripline routing: Route over unbroken ground plane
Micro-strip routing: Route over unbroken ground or
power plane
Stripline. Simulations show that stripline routing of the
DQ and DQS signals provides the best solution space.
Micro-strip routing is also acceptable.
5 mils x 5 mils. Microstrip is recommended for pin
escapes and terminations.
• 45 ohm +/- 15% or
• 50 ohms +/- 15%
• 5 mils is acceptable for pin escapes and
fan-in/fan-out from terminations.
• >12 mils between any DQ/DQS signals
• >20 mils bust be maintained from any other
groups
The package lengths from Die to Ball provided in
Table 37 must be accounted for when length
matching. Refe r to Table 47 for more details on
segment lengths.
≤ 0.5”
≤ 0.1”
0.15” to 0.5” (placed directly after series termination
fan-in)
• The package lengths from Die to Ball provided in
Table 37 must be accounted for when length
matching.
• When M_CK is routed on a stripline layer, DQS
should be routed to within +/- 1.5” of its
corresponding M_CK
• When M_CK is routed on a micro-strip layer, DQS
should be routed to within +/- 1.0” of its
corresponding M_CK
89
Intel® 80331 I/O Process orDesign Guide
Memory Controller
T able 46. DDR 333 Embedded Source Synchronou s Routing Recommendations (Sheet 2 of 2)
ParameterRouting Guideline
51 ohms +/- 5%
• Place the VTT terminations in VTT island after the
Parallel Termination
Routing Guideline 1
Routing Guideline 2: Vias
DIMM (trace length of 0.15” to 0.5”).
or
• Split termination of 100 ohms +/- 5% to 2.5 V and
100 ohms +/- 5% to ground
Route all data signals and their associated strobes on
the same layer.
2 Minimize layer changes especially DQS signals.
<
(two vias or less). Equal number of vias between DQ
and its respective DQS signal.
This section lists the recommendations for the DDR 333 clock signals. Refer to Figure 45 for
buffered clock topology, Figure 46 for unbuf fered clock topolo gy. Refer to Table 48 for a summary
of DDR 333 embedded clock routin g guideli nes. Refer to Table 49 for a description of the segment
lengths and matching requ irements for buf fered clock topology. R efer t o Table 50 for a description
of unbuffered clock topology information.
Breakout Termination, Fan-in and Fanout width and
spacing
Trace Impedance
Trace Spacing (trace edge to edge)
Registered TerminationNone required
Un-buffered Termination
Length matching Requirements:
• Within Differential Clock pairs• +/- 0.025” max. within Pairs [Intra-pair]
• Registered Clock from IOP Die to PLL Input with
Respect to DQS
• Registered Clock from IOP Die to PLL Input with
Respect to Add/CMD/Control
• Un-buffered Clock from IOP Die to SDRAM input
with respect to DQ S
• Un-buffered Clock from IOP Die to SDRAM input
with respect to Add/CMD/Control
• Unbuffered Clock Pairs
Number of vias
Routing Guideline
• Route over unbroken ground plane
• Stripline routing is recommended for the clock
signals. Micro-strip will work with strict adherence
to all routing recommendations. Careful
simulation and timing analysis of ADD/CMD
signals is recommended.
5 mils x 5 mils. Microstrip is recommended for pin
escapes and terminations.
Differential Target impedance of 100 Ohms +/-15%
(Applies to both Buffered and Unbuffered Topologies)
5 mils. for breakout region
>20 mils. between any other signals or vias including
other clock pairs.
• 22 ohms +/-5% series termination on each
differential leg after breakout route
• Post PLL and Unbuffered SDRAM Clock areas to
be Routed as T Point differential as per JEDEC
Unbuffered and Registered Post PLL Clock
Topology
• The package lengths from Die to Ball provided in
Table 37 must be accounted for when length
matching.
• See respective registered Table 49 and
unbuffered Table 50 tables Topology/ Trace
Length tables for additional information.
• With-in +/- 1.0” of all strobes (DQS0-8) (strobe
length measured from IOP die to SDRAM)
• 1.0” to 2.0” longer than Add/CMD/Control
(Add/CMD/Control length measured from IOP die
to Register input)
• With-in +/- 1.0” of associated strobe (DQS) (strobe
length measured from IOP die to SDRAM)
• 1.0” to 2.0” longer than Add/CMD/Control from
(Add/CMD/Control length measured from IOP die
to SDRAM input)
• +/- 0.1” max. between the 3 pairs of Unbuffered
Clocks (clock length measured from IOP die to
SDRAM)
• For Registered: maximum of 3 pairs from IOP to
PLL
• For Unbuffered: maximum of 4 pairs.
All un-buffered clocks utilized in memory
implementations must be load balanced. Use
capacitors equal to the SDRAM’s clock input
capacitance to balance loading across all the clocks
used. Topology shown is based on a Raw B
implementation. Refer to JEDEC Un-buffered DIMM
specs. for Raw Card C implementation specifics.
TL10.47”0.49”Same as TL020 milsRoute per DDR1 JEDEC
TL20.72 “0.73”Same as TL020 milsRoute per DDR1 JEDEC
TL30.360.37”Same as TL020 milsRoute per DDR1 JEDEC
TL4BreakoutAny0.5”5 milsRoute as differential
Microstrip/
Stripline
Minimum
Length
2”10”
Maximum
Length
Trace
Impedance
Differential 100
ohms +/- 15%
SpacingNo tes
• Match within +/- 1” of
strobes (DQS) from
20 mils
from any
other
signals
controller to SDRAM and
within +/- 1” of
Address/CMD control from
controller to SDRAM input.
• Route as T Differential
pairs as per DDR1 DIMM
JEDEC.
Trace Length
Series Resistor22 +/- 5% ohms unbuffered configurations only
Parallel Resistor
Package Trace Length:
Main Route Trace Lengths:
CAS#, WE#, BA[1:0], MA[12:0], CS[1:0]#, and CKE[1:0]). Refer to
ParameterRouting Guideline
• Micro-strip only for Un-buffered memory
configurations
• Either Micro-strip or Stripline for Registered
memory implementations and lightly loaded
Un-buffered memory implementations (i.e. single
bank w/ less than or equal to 36pF input
capacitance).
5 mils x 5 mils. Microstrip is recommended for pin
escapes and terminations.
• 45 ohm +/- 15% or
• 50 ohms +/- 15%
• 5 mils is acceptable for pin escapes and
terminations.
• >12 mils within group
• >20 mils must be maintained from any other
groups (Clock/DQ/DQS)
Refer to following Embedded Addr/CMD Topology
Table 52 for unbuffered and Table 53 for registered.
51 +/- 5% ohms
• Place the VTT terminations in VTT island after the
DIMM (trace length of 0.15” to 0.5”0.
• Split termination of 100 ohms +/- 5% to 2.5 V and
100 ohms +/- 5% to ground
See Package Details for net length report Table 37.
Refer to respective following Un-buffered or
Registered Topology/ Trace Length tables for more
details.
TL2Microstrip1. 2 “1.35”S ame as TL112 mils
TL3Microstrip0. 5”0.6”Same as TL112 mils
Fan out for series termination
(only for unbuffered)
TL40.3”0.35”Same as TL112 mils
TL50.14”0.18”Same as TL112 mils
TL60.32”0.35”Same as TL112 mils
TL70.25”0.5”Same as TL112 mils
TL8BreakoutAny0”0.5”5 mils
Spacing: within the same
group 12 mils
With other groups 20 mils
TL9Lead-in
Microstrip/
Stripline
1”8”
45 ohms+/-15%
or 50 ohms
+/-15%
12 mils
TL10VTTMicrostrip0.25”0.5”5 milsPlace in VTT Island
NOTE: All traces except breakout TL8 traces are of the same impedance and spacing requirements.
TL31.39”2.57”Same as TL212 mils
TL40.4”0.56”Same as TL212 mils
TL50.14”0.15”Same as TL212 mils
TL60.48”0.63”Same as TL212 mils
TL70.20”0.32”Same as TL212 mils
TL80.490.72”Same as TL212 mils
TL9Lead-inMicrostrip1”9”
TL10Microstrip
TL11VttMicrostrip0.25’0.5”5 mils
NOTES:
1. Post Register recommendations are referenced from JEDEC DDR1 Registered DIMM.