Intel 80219 User Manual

Intel® 80219 General Purpose PCI Processor

Specification Update

July 2004

Notice: The In tel® 80219 General Purpose PCI Process or (80219) may con tain desig n defect s or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.

Document Number: 274020-002

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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to the m. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to the m.

The Intel published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

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The ARM* and ARM Powered logo marks (the ARM marks) are trademarks of ARM, Ltd., and Intel uses these marks under license from ARM, Ltd. *Other names and brands may be claimed as the property of others.

80219 General Purpose PCI Processor may contain design defects or errors known as errata which may cause the product to deviate from

2 Specification Update

Revision History......................................................................................... 5

Preface....................................................................................................... 6

Summary Table of Changes....................................................................... 7

Identification Information...........................................................................11

Core Errata .............................................................................................. 13

Non-Core Errata....................................................................................... 20

Specification Changes ............................................................................. 24

Specification Clarifications....................................................................... 26

80219 General Purpose PCI Processor

Intel

Documentation Changes ......................................................................... 29

Specification Update 3

80219 General Purpose PCI Processor

Intel

This Page Left Intentionally Blank

4 Specification Update

Revision History

Date Version Description

July 2004 002 Added Specification Clarification 7.

November 2003 001 Initial Release.

80219 General Purpose PCI Processor

Intel

Revision History

Specification Update 5

80219 General Purpose PCI Processor

Intel

Preface

This document is an update to the specifications contained in the Affected Documents/Related Documents table below. specification clarifications and changes. software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents/Related Documents

This document is a compilation of device and documentation errata,

It is intended for hardware system manufacturers and

Intel® 80219 General Purpose PCI Processor Developer’s Manual 274017

Intel

80219 General Purpose PCI Processor Advance Information Datasheet 274018

Intel

80219 General Purpose PCI Processor Design Guide 274019

Nomenclature

Errata are design defects or errors. These may cause the Intel® 80219 General Purpose PCI

Processor

be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product life cycle, or until a particular

stepping is no longer commercially available. Under these circumstances, err ata removed fro m the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the approp riate product specification or user documentation (datasheets, manuals, etc.).

Title Order

behavior to deviate from published specifications. Hardware and software designed to

These clarifications will be incorporated in

1. ARM* architec ture compliant.

6 Specification Update

80219 General Purpose PCI Processor

Intel

Summary Table of Changes

The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. following notations:

Codes Used in Summary Table

Stepping

X: Errata exists in the stepping indicated. Specification Change or

Clarification that applies to this stepping. (No mark) or (Blank box): This erratum is fixed in liste d stepping or specification change does not

apply to listed steppin g.

Page

(Page): Page location of item in this document.

80219 General Purpos e PCI Processor product.

This table uses the

Status

Doc: Document change or update will be implemented. PlanFix: This erratum may be fixed in a future stepping of the product. Fixed: This erratum has been previously fixed. NoFix: There are no plans to fix this erratum.

Row

Change bar to left of table row indicates this erratum is either new or

modified from the previous version of the document.

Specification Update 7

80219 General Purpose PCI Processor

Intel

Summary Table of Changes

Core Errata

Steppings

No.

A-0

1 X 13 NoFix Boundary Scan Is Not Fully Compliant to the IEEE 1149.1 Specification 2 X 13 NoFix Drain Is Not Flushed Correctly when Stalled in the Pipeline 3 X 14 NoFix Undefined Data Processing-‘like’ Instructions are Interpreted as an MSR Instruction 4 X 14 NoFix Debug Unit Synchronization with the TXRXCTRL Register 5 X 14 NoFix Extra Circuitry Is Not JTAG Boundary Scan Compliant

6 X 15 NoFix 7 X 15 NoFix Load Immediately Following a DMM Flush Entry is Also Flushed

8 X 15 NoFix Trace Buffer Does Not Operate Below 1.3 V 9 X 15 NoFix Data Cache Unit Can St all for a Single Cycle

10 X 16 NoFix Aborted Store that Hits the Data Cache May Mark Writeback Data As Dirty 11 X 17 NoFix

12 X 17 NoFix 13 X 18 NoFix Accesses to the CP15 ID register with opcode2 > 0b001 returns unpredictable values 14 X 18 NoFix 15 X 19 NoFix Updating the JTAG parallel register requires an extra TCK rising edge

Page Status Errata

Incorrect Decode of Unindexed Mode, Using Addressing Mode 5, Can Corrupt Protected Registers

Performance Monitor Unit Event 0x1 Can Be Incremented Erroneously by Unrelated Events

In Special Debug State, Back-to-B ack Mem ory O peration s Where the First Instruction Aborts May Cause a Hang

Disabling and re-enabling the MMU can hang the core or cause it to execute the wrong code

8 Specification Update

80219 General Purpose PCI Processor

Intel

Summary Table of Changes

Non-Core Errata

Steppings

No.

A-0

1 X 20 NoFix 2 X 20 NoFix PBI Issue When Using 16-bit PBI Trans actions in PCI Mode

3 X 21 NoFix MCU Pointers are Incorrect following a Restoration from a Power Fail 4 X 21 NoFix 5 X 21 NoFix Lost Data During Bursts of Large Number of Partials with 32-bit ECC Memory 6 X 22 NoFix 7 X 22 NoFix The MCU supports a page size of 2 Kbytes for 64-bit mode

8 X 23 NoFix Vih Minimum Input High Voltage (Vih) level for the PCI pins

Page Status Errata

The ATU Returns Invalid Data for the DWORD that Target Aborted from the MCU when Using 32-Bit Memory, ECC Enabled and in PCI Mode

PMU Does Not Account for when the Arbiter Deasserts GNT# One Cycle before FRAME#

The MTTR1 (Core Multi-Transaction Timer) is not operating due to improper behavior of the core internal bus request signal (REQ#)

Specification Update 9

+ 21 hidden pages

Intel 80219 User Manual

Contents

Revision History

Preface

Summary Table of Changes