ICST ICS1892Y, ICS1892Y-10, ICS1892Y-14 Datasheet

Integrated Circuit Systems, Inc.

ICS1892

Document Type: Data Sheet

Document Stage: Released

10Base-T/100Base-TX Integrated PHYceiver

General

The ICS1892, an enhanced version of the ICS 1890, is a fully integrated, physical-layer device (PHY) that is compliant with both the 10Base-T and 100Base-TX CSMA/CD Ethernet Standard, ISO/IEC 8802-3.

The ICS1892 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cable with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1892 can virtually eliminate errors from killer packets.

The ICS1892 supports a broad range of applications: data terminal equipment (network interface cards and motherboards), switches, repeaters, bridges, and routers. Its Media Independent Interface (MII) supports direct chip-to-chip and motherboard-to-daughterboard connections as well as connections to an MII connector and cable. The ICS1892 also provides a Serial Management Interface for exchanging command and status information with a Station Management (STA) entity.

The ICS1892 Media Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be done manually (with input pins or control register settings) or automatically (using the Auto-Negotiation features). When the ICS1892 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common.

ICS1892 Block Diagram

Features

•

Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz across a temperature range from -5° to +85° C

•

DSP-based baseline wander correction to virtually eliminate killer packets across temperature range of from

-5° to +85° C

•

Low-power, 0.5-micron CMOS

•

Single 5.0-V power supply.

•

Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sublayers of IEEE standard

•

10Base-T and 100Base-TX IEEE 802.3 compliant

•

Fully integrated, DSP-based PMD includes:

– Adaptive equalization and baseline wander correction – Transmit wave shaping and stream cipher scrambler – MLT-3 encoder and NRZ/NRZI encoder

•

Highly configurable design supports:

– Node, repeater, and switch applications – Managed and unmanaged applications – 10M or 100M half- and full-duplex modes – Parallel detection – Auto-negotiation, with Next Page capabilities

•

MAC/Repeater Interface can be configured as:

– 10M or 100M Media Independent Interface – 100M Symbol Interface (bypasses the PCS) – 10M 7-wire Serial Interface

•

Provides Loopback Modes for Diagnostic Functions

•

Small Footprint 64-pin Low-Profile LQFP and MQFP packages available



10/100 MII or

Alternate

MAC/Repeater

Interface

MII Serial

Management

Interface

1892 Rev. D, 2/26/01

Interface

MUX

MII

Extended

Set

100Base-T

PCS

•Frame

• CRS/COL Detection

• Parallel to Serial

•4B/5B

Low-Jitter

Clock

Synthesizer

Clock Power LEDs and PHY

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

PMA

• Clock Recovery

• Link Monitor

• Signal Detection

• Error Detection

10Base-T

TP_PMD

•MLT-3

• Stream C ipher

• Adaptive Equalizer

• Baseline Wander Correction

Configuration

and Status

Address

Integrated

Switch

Auto-

Negotiation

Twi ste d-

Pair

Interface to

Magnetics

Modules and

RJ45

Connector

Table of ContentsICS1892 Data Sheet

Table of Contents

Section Title Page

Chapter 1 Abbreviations and Acronyms................................................................9

Chapter 2 Conventions and Nomenclature..........................................................11

Chapter 3 ICS 1892 Enhanced Features.............................................................. 13

Chapter 4 Overview of the ICS 1892 .................................................................... 15

4.1 100Base-TX Operation .............................................................................. 16

4.2 10Base-T Operation .................................................................................. 16

Chapter 5 Operating Modes Overview ................................................................ 17

5.1 Reset Operations ....................................................................................... 18

5.1.1 General Reset Operations ......................................................................... 18

5.1.2 Specific Reset Operations ......................................................................... 19

5.2 Power-Down Operations ........................................................................... 20

5.3 Automatic Power-Saving Operations ......................................................... 21

5.4 Auto-Negotiation Operations ..................................................................... 21

5.5 100Base-TX Operations ............................................................................ 22

5.6 10Base-T Operations ................................................................................ 22

5.7 Half-Duplex and Full-Duplex Operations ................................................... 22

Chapter 6 Interface Overviews ............................................................................. 23

6.1 MII Data Interface ...................................................................................... 24

6.2 100M Symbol Interface .............................................................................. 25

6.3 10M Serial Interface .................................................................................. 27

6.4 Link Pulse Interface ................................................................................... 29

6.5 Serial Management Interface .................................................................... 30

6.6 Twisted-Pair Interface ................................................................................ 30

6.7 Clock Reference Interface ......................................................................... 30

6.7.1 Clock Source: Oscillator or CMOS Driver .................................................. 30

6.7.2 Clock Source: Crystal ................................................................................ 31

6.8 Configuration Interface .............................................................................. 32

6.9 Status Interface ......................................................................................... 32

Chapter 7 Functional Blocks ................................................................................ 33

7.1 Functional Block: Media Independent Interface ........................................ 34

7.2 Functional Block: Auto-Negotiation ........................................................... 35

7.2.1 Auto-Negotiation General Process ............................................................ 36

7.2.2 Auto-Negotiation: Parallel Detection .......................................................... 37

7.2.3 Auto-Negotiation: Remote Fault Signaling ................................................ 37

7.2.4 Auto-Negotiation: Reset and Restart ......................................................... 38

7.2.5 Auto-Negotiation: Progress Monitor .......................................................... 39

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ICS1892

Table of Contents

Section Title Page

7.3 Functional Block: 100Base-X PCS and PMA Sublayers ........................... 41

7.3.1 PCS Sublayer ............................................................................................ 41

7.3.2 PMA Sublayer ............................................................................................ 41

7.3.3 PCS/PMA Transmit Modules ..................................................................... 42

7.3.4 PCS/PMA Receive Modules ...................................................................... 43

7.3.5 PCS Control Signal Generation ................................................................. 44

7.3.6 4B/5B Encoding/Decoding ......................................................................... 45

7.4 Functional Block: 100Base-TX TP-PMD Operations ................................. 46

7.4.1 100Base-TX Operation: Stream Cipher Scrambler/Descrambler .............. 46

7.4.2 100Base-TX Operation: MLT-3 Encoder/Decoder .................................... 46

7.4.3 100Base-TX Operation: DC Restoration ................................................... 46

7.4.4 100Base-TX Operation: Adaptive Equalizer .............................................. 47

7.4.5 100Base-TX Operation: Twisted-Pair Transmitter ..................................... 47

7.4.6 100Base-TX Operation: Twisted-Pair Receiver ......................................... 47

7.4.7 100Base-TX Operation: Auto Polarity Correction ...................................... 48

7.4.8 100Base-TX Operation: Isolation Transformer .......................................... 48

7.5 Functional Block: 10Base-T Operations .................................................... 49

7.5.1 10Base-T Operation: Manchester Encoder/Decoder ................................ 49

7.5.2 10Base-T Operation: Clock Synthesis ....................................................... 49

7.5.3 10Base-T Operation: Clock Recovery ....................................................... 49

7.5.4 10Base-T Operation: Idle .......................................................................... 50

7.5.5 10Base-T Operation: Link Monitor ............................................................. 50

7.5.6 10Base-T Operation: Smart Squelch ......................................................... 51

7.5.7 10Base-T Operation: Carrier Detection ..................................................... 51

7.5.8 10Base-T Operation: Collision Detection .................................................. 51

7.5.9 10Base-T Operation: Jabber ..................................................................... 52

7.5.10 10Base-T Operation: SQE Test ................................................................. 52

7.5.11 10Base-T Operation: Twisted-Pair Transmitter ......................................... 53

7.5.12 10Base-T Operation: Twisted-Pair Receiver ............................................. 53

7.5.13 10Base-T Operation: Auto Polarity Correction .......................................... 54

7.5.14 10Base-T Operation: Isolation Transformer .............................................. 54

7.6 Functional Block: Management Interface .................................................. 55

7.6.1 Management Register Set Summary ........................................................ 55

7.6.2 Management Frame Structure ................................................................... 55

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Table of ContentsICS1892 Data Sheet

Table of Contents

Section Title Page

Chapter 8 Management Register Set................................................................... 58

8.1 Introduction to Management Register Set ................................................. 59

8.1.1 Management Register Set Outline ............................................................ 59

8.1.2 Management Register Bit Access ............................................................. 60

8.1.3 Management Register Bit Default Values .................................................. 60

8.1.4 Management Register Bit Special Functions ............................................. 61

8.2 Register 0: Control Register ...................................................................... 62

8.2.1 Reset (bit 0.15) .......................................................................................... 62

8.2.2 Loopback Enable (bit 0.14) ........................................................................ 63

8.2.3 Data Rate Select (bit 0.13) ........................................................................ 63

8.2.4 Auto-Negotiation Enable (bit 0.12) ............................................................ 63

8.2.5 Low Power Mode (bit 0.11) ........................................................................ 64

8.2.6 Isolate (bit 0.10) ......................................................................................... 64

8.2.7 Restart Auto-Negotiation (bit 0.9) .............................................................. 64

8.2.8 Duplex Mode (bit 0.8) ................................................................................ 65

8.2.9 Collision Test (bit 0.7) ................................................................................ 65

8.2.10 IEEE Reserved Bits (bits 0.6:0) ................................................................. 65

8.3 Register 1: Status Register ........................................................................ 66

8.3.1 100Base-T4 (bit 1.15) ................................................................................ 66

8.3.2 100Base-TX Full Duplex (bit 1.14) ............................................................ 67

8.3.3 100Base-TX Half Duplex (bit 1.13) ............................................................ 67

8.3.4 10Base-T Full Duplex (bit 1.12) ................................................................. 67

8.3.5 10Base-T Half Duplex (bit 1.11) ................................................................ 67

8.3.6 IEEE Reserved Bits (bits 1.10:7) ............................................................... 68

8.3.7 MF Preamble Suppression (bit 1.6) ........................................................... 68

8.3.8 Auto-Negotiation Complete (bit 1.5) .......................................................... 68

8.3.9 Remote Fault (bit 1.4) ................................................................................ 69

8.3.10 Auto-Negotiation Ability (bit 1.3) ................................................................ 69

8.3.11 Link Status (bit 1.2) .................................................................................... 69

8.3.12 Jabber Detect (bit 1.1) ............................................................................... 70

8.3.13 Extended Capability (bit 1.0) ..................................................................... 70

8.4 Register 2: PHY Identifier Register ............................................................ 71

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ICS1892

Table of Contents

Section Title Page

8.5 Register 3: PHY Identifier Register ............................................................ 73

8.5.1 OUI bits 19-24 (bits 3.15:10) ..................................................................... 73

8.5.2 Manufacturer's Model Number (bits 3.9:4) ................................................ 73

8.5.3 Revision Number (bits 3.3:0) ..................................................................... 74

8.6 Register 4: Auto-Negotiation Register ....................................................... 75

8.6.1 Next Page (bit 4.15) ................................................................................... 75

8.6.2 IEEE Reserved Bit (bit 4.14) ...................................................................... 76

8.6.3 Remote Fault (bit 4.13) .............................................................................. 76

8.6.4 Technology Ability Field (bits 4.12:5) ......................................................... 76

8.6.5 Selector Field (Bits 4.4:0) .......................................................................... 77

8.7 Register 5: Auto-Negotiation Link Partner Ability Register ........................ 78

8.7.1 Next Page (bit 5.15) ................................................................................... 78

8.7.2 Acknowledge (bit 5.14) .............................................................................. 79

8.7.3 Remote Fault (bit 5.13) .............................................................................. 79

8.7.4 Technology Ability Field (bits 5.12:5) ......................................................... 79

8.7.5 Selector Field (bits 5.4:0) ........................................................................... 79

8.8 Register 6: Auto-Negotiation Expansion Register ..................................... 80

8.8.1 IEEE Reserved Bits (bits 6.15:5) ............................................................... 80

8.8.2 Parallel Detection Fault (bit 6.4) ................................................................ 81

8.8.3 Link Partner Next Page Able (bit 6.3) ........................................................ 81

8.8.4 Next Page Able (bit 6.2) ............................................................................ 81

8.8.5 Page Received (bit 6.1) ............................................................................. 81

8.8.6 Link Partner Auto-Negotiation Able (bit 6.0) .............................................. 81

8.9 Register 7: Auto-Negotiation Next Page Transmit Register ...................... 82

8.9.1 Next Page (bit 7.15) ................................................................................... 83

8.9.2 IEEE Reserved Bit (bit 7.14) ...................................................................... 83

8.9.3 Message Page (bit 7.13) ........................................................................... 83

8.9.4 Acknowledge 2 (bit 7.12) ........................................................................... 83

8.9.5 Toggle (bit 7.11) ........................................................................................ 83

8.9.6 Message Code Field / Unformatted Code Field (bits 7.10:0) .................... 83

8.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register ...... 84

8.10.1 Next Page (bit 8.15) ................................................................................... 85

8.10.2 IEEE Reserved Bit (bit 8.14) ...................................................................... 85

8.10.3 Message Page (bit 8.13) ........................................................................... 85

8.10.4 Acknowledge 2 (bit 8.12) ........................................................................... 85

8.10.5 Message Code Field / Unformatted Code Field (bits 8.10:0) .................... 85

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Table of ContentsICS1892 Data Sheet

Table of Contents

Section Title Page

8.11 Register 16: Extended Control Register .................................................... 86

8.11.1 Command Override Write Enable (bit 16.15) ............................................ 87

8.11.2 ICS Reserved (bits 16.14:11) .................................................................... 87

8.11.3 PHY Address (bits 16.10:6) ....................................................................... 87

8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) ......................................... 87

8.11.5 ICS Reserved (bit 16.4) ............................................................................. 87

8.11.6 NRZ/NRZI Encoding (bit 16.3) ................................................................... 87

8.11.7 Invalid Error Code Test (bit 16.2) .............................................................. 88

8.11.8 ICS Reserved (bit 16.1) ............................................................................. 88

8.11.9 Stream Cipher Disable (bit 16.0) ............................................................... 88

8.12 Register 17: Quick Poll Detailed Status Register ...................................... 89

8.12.1 Data Rate (bit 17.15) ................................................................................. 90

8.12.2 Duplex (bit 17.14) ...................................................................................... 90

8.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11) ................................... 91

8.12.4 100Base Receive Signal Lost (bit 17.10) .................................................. 91

8.12.5 PLL Lock Error (bit 17.9) ........................................................................... 92

8.12.6 False Carrier (bit 17.8) ............................................................................... 92

8.12.7 Invalid Symbol (bit 17.7) ............................................................................ 92

8.12.8 Halt Symbol (bit 17.6) ................................................................................ 93

8.12.9 Premature End (bit 17.5) ........................................................................... 93

8.12.10 Auto-Negotiation Complete (bit 17.4) ........................................................ 93

8.12.11 100Base-TX Signal Detect (bit 17.3) ......................................................... 93

8.12.12 Jabber Detect (bit 17.2) ............................................................................. 93

8.12.13 Remote Fault (bit 17.1) .............................................................................. 94

8.12.14 Link Status (bit 17.0) .................................................................................. 94

8.13 Register 18: 10Base-T Operations Register .............................................. 95

8.13.1 ICS Reserved (bit 18.15) ........................................................................... 95

8.13.2 Polarity Reversed (bit 18.14) ..................................................................... 96

8.13.3 ICS Reserved (bits 18.13:6) ...................................................................... 96

8.13.4 Jabber Inhibit (bit 18.5) .............................................................................. 96

8.13.5 ICS Reserved (bit 18.4) ............................................................................. 96

8.13.6 Auto Polarity Inhibit (bit 18.3) .................................................................... 96

8.13.7 SQE Test Inhibit (bit 18.2) ......................................................................... 96

8.13.8 Link Loss Inhibit (bit 18.1) .......................................................................... 97

8.13.9 Squelch Inhibit (bit 18.0) ............................................................................ 97

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ICS1892

Table of Contents

Section Title Page

8.14 Register 19: Extended Control Register 2 ................................................. 98

8.14.1 Node/Repeater Configuration (bit 19.15) ................................................... 99

8.14.2 Hardware/Software Priority Status (bit 19.14) ........................................... 99

8.14.3 Remote Fault (bit 19.13) ............................................................................ 99

8.14.4 ICS Reserved (bits 19.12:2) ...................................................................... 99

8.14.5 Automatic 10Base-T Power-Down (bit 19.1) ........................................... 100

8.14.6 Automatic 100Base-TX Power-Down (bit 19.0) ....................................... 100

Chapter 9 ICS 1892 Pin Listing and Pin Descriptions ..................................... 101

9.1 ICS 1892 Pin Listings .............................................................................. 101

9.1.1 Pin Listing by Pin Number ....................................................................... 102

9.1.2 Pin Listings by Alphabetical Pin Name .................................................... 103

9.2 ICS 1892 Pin Descriptions ....................................................................... 104

9.2.1 Transformer Interface Pins ...................................................................... 104

9.2.2 Multifunction (Multiplexed) Pins: PHY Address and LED Pins ................ 105

9.2.3 Configuration Pins ................................................................................... 106

9.2.4 MAC/Repeater Interface Pins .................................................................. 109

9.2.5 Reserved Pins ......................................................................................... 118

9.2.6 Ground and Power Pins .......................................................................... 118

Chapter 10 DC and AC Operating Conditions .................................................. 120

10.1 Absolute Maximum Ratings ..................................................................... 120

10.2 Recommended Operating Conditions ..................................................... 120

10.3 Recommended Component Values ......................................................... 121

10.4 DC Operating Characteristics .................................................................. 122

10.4.1 DC Operating Characteristics for Supply Current .................................... 122

10.4.2 DC Operating Characteristics for TTL Inputs and Outputs ...................... 122

10.4.3 DC Operating Characteristics for REF_IN ............................................... 122

10.4.4 DC Operating Characteristics for Media Independent Interface .............. 123

10.5 Timing Diagrams ..................................................................................... 124

10.5.1 Timing for Clock Reference In (REF_IN) Pin ........................................... 124

10.5.2 Timing for Transmit Clock (TXCLK) Pin .................................................. 125

10.5.3 Timing for Receive Clock (RXCLK) Pin ................................................... 126

10.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing ........ 127

10.5.5 10M MII: Synchronous Transmit Timing .................................................. 128

10.5.6 MII / 100M Stream Interface: Synchronous Receive Timing ................... 129

10.5.7 MII Management Interface Timing ........................................................... 130

10.5.8 10M Serial Interface: Receive Latency .................................................... 131

10.5.9 10M Media Independent Interface: Receive Latency .............................. 132

10.5.10 10M Serial Interface: Transmit Latency ................................................... 133

10.5.11 10M Media Independent Interface: Transmit Latency ............................. 134

10.5.12 MII / 100M Stream Interface: Transmit Latency ...................................... 135

10.5.13 MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) ............ 136

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Section Title Page

10.5.14 100M MII / 100M Stream Interface: Receive Latency ............................. 137

10.5.15 Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion ..... 138

10.5.16 Reset: Power-On Reset ........................................................................... 139

10.5.17 Reset: Hardware Reset and Power-Down ............................................... 140

10.5.18 10Base-T: Heartbeat Timing (SQE) ........................................................ 141

10.5.19 10Base-T: Jabber Timing ........................................................................ 142

10.5.20 10Base-T: Normal Link Pulse Timing ...................................................... 143

10.5.21 Auto-Negotiation Fast Link Pulse Timing ................................................ 144

Chapter 11 Physical Dimensions of ICS 1892 Package................................... 145

Chapter 12 Ordering Information ....................................................................... 147

ICS1892, Rev. D, 2/26/01 February 26, 2001

ICS1892

Chapter 1 Abbreviations and Acronyms

Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet.

Table 1-1.

Abbreviation /

Acronym

4B/5B 4-Bit / 5-Bit Encoding/Decoding

ANSI American National Standards Institute

CMOS complimentary metal-oxide semiconductor

CSMA/CD Carrier Sense Multiple Access with Collision Detection

CW Command Override Write

DSP digital signal processing

ESD End-of-Stream Delimiter

FDDI Fiber Distributed Data Interface

FLP Fast Link Pulse

IDL A ‘dead’ time on the link following a 10Base-T packet, not to be confused with idle

IEC International Electrotechnical Commission

IEEE Institute of Electrical and Electronic Engineers

ISO International Standards Organization

LH Latching High

LL Latching Low

LMX Latching Maximum

Abbreviations and Acronyms

Interpretation

MAC Media Access Control

Max. maximum

Mbps Megabits per second

MDI Media Dependent Interface

MF Management Frame

MII Media Independent Interface

Min. minimum

MLT-3 Multi-Level Transition Encoding (3 Levels)

N/A Not Applicable

NLP Normal Link Pulse

No. Number

NRZ Not Return to Zero

NRZI Not Return to Zero, Invert on one

OSI Open Systems Interconnection

ICS1892, Rev. D, 2/26/01 February 26, 2001

Chapter 1 Abbreviations and AcronymsICS1892 Data Sheet

Table 1-1.

Abbreviations and Acronyms (

Continued

Abbreviation /

Acronym

OUI Organizationally Unique Identifier

PCS Physical Coding sublayer

PHY physical-layer device

The ICS1892 is a physical-layer device, also referred to as a ‘PHY’ or ‘PHYceiver’. (The ICS 1890 is also a physical-layer device.)

PLL phase-locked loop

PMA Physical Medium Attachment

PMD Physical Medium Dependent

ppm parts per million

QFP quad flat pack

RO read only

R/W read/write

R/W0 read/write zero

SC self-clearing

SF Special Functions

SFD Start-of-Frame Delimiter

)

Interpretation

SI Stream Interface

Serial Interface Symbol Interface

With reference to the MII/SI pin, the acronym ‘SI’ has multiple meanings.

•

Generically, SI means 'Stream Interface', and is documented as such in the ICS 1890 data sheet.

•

However, when the MAC/Repeater Interface is configured for: – 10M operations, SI is an acronym for 'Serial Interface'.

– 100M operations, SI is an acronym for 'Symbol Interface'.

SQE Signal Quality Error

SSD Start-of-Stream Delimiter

STA Station Management Entity

STP shielded twisted pair

TAF Technology Ability Field

TP-PMD Twisted-Pair Physical Layer Medium Dependent

Typ. typ ical

UTP unshielded twisted pair

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ICS1892

Chapter 2 Conventions and Nomenclature

Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet.

Table 2-1.

Asterisk (*) Within this table, see the item ‘Pin (or signal) names’

Bits

Code groups Within this table, see the item ‘Symbols’

Colon (:) Within this table, see these items:

Numbers

Pin (or signal) names

Conventions and Nomenclature

Item Convention / Nomenclature

•

A bit in a register is identified using the format ‘register.bit’. For example, bit

0.15 is bit 15 of register 0.

•

When a colon is used with bits, it indicates the range of bits. For example, bits 1.15:11 are bits 15, 14, 13, 12, and 11 of register 1.

•

For a range of bits, the order is always from the most-significant bit to the least-significant bit.

•

‘Bits’

•

‘Pin (or signal) names’

•

As a default, all numbers use the decimal system (that is, base 10) unless followed by a lowercase letter. A string of numbers followed by a lowercase letter: – A ‘b’ represents a binary (base 2) number

– An ‘h’ represents a hexadecimal (base 16) number – An ‘o’ represents an octal (base 8) number

•

All numerical references to registers use decimal notation (and not hexadecimal).

•

All pin or signal names are provided in capital letters.

•

A pin name that includes a forward slash ‘/’ is a multi-function, configuration pin. These pins provide the ability to select between two ICS1892 functions. The name provided: – Before the ‘/’ indicates the pin name and function when the signal level

on the pin is logic zero.

– After the ‘/’ indicates the pin name and function when the signal level on

the pin is logic one. For example, the HW/SW pin selects between Hardware (HW) mode and Software (SW) mode.

– When the signal level on the HW/SW pin is logic zero, the ICS1892

Hardware mode is selected.

– When the signal level on the HW/SW pin is logic one, the ICS1892

Software mode is selected.

•

An asterisk appended to the end of a pin name or signal name (such as RESET*) indicates an active-low operation.

•

When a colon is used with pin or signal names, it indicates a range. For example, TXD[3:0] represents pins/signals TXD3, TXD2, TXD1, and TXD0.

•

When pin name abbreviations are spelled out, words in parentheses indicate additional description that is not part of the pin name abbreviation.

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Chapter 2 Conventions and NomenclatureICS1892 Data Sheet

Table 2-1.

Registers

Signal references

Symbols

Ter ms : ‘set’, ‘active’, ‘asserted’,

Ter ms : ‘cleared’, ‘de-asserted’, ‘inactive’

Conventions and Nomenclature (

Item Convention / Nomenclature

Continued

•

A bit in a register is identified using the format ‘register.bit’. For example, bit

0.15 is bit 15 of register 0.

•

All numerical references to registers use decimal notation (and not hexadecimal).

•

When register name abbreviations are spelled out, words in parentheses indicate additional description that is not part of the register name abbreviation.

•

When referring to signals, the terms: – ‘FALSE’, ‘low’, or ‘zero’ represent signals that are logic zero.

– ‘TRUE’, ‘high’, or ‘one’ represent signals that are logic one.

•

Chapter 10, “DC and AC Operating Conditions” defines the electrical

specifications for ‘logic zero’ and ‘logic one’ signals.

•

In this data sheet, code group names are referred to as ‘symbols’ and they are shown between '/' (slashes). For example, the symbol /J/ represents the first half of the Start-of-Stream Delimiter (SSD1).

•

Symbol sequences are shown in succession. For example, /I/J/K/ represents an IDLE followed by the SSD.

The terms ‘set’, ‘active’, and ‘asserted’ are synonymous. They do not necessarily infer logic one. (For example, an active-low signal can be set to logic zero.)

The terms ‘cleared’, ‘inactive’, and ‘de-asserted’ are synonymous. They do not necessarily infer logic zero.

)

Ter ms : ‘twisted-pair receiver’

Ter ms : ‘twisted-pair transmitter’

In reference to the ICS1892, the term ‘Twisted-Pair Receiver’ refers to the set of Twisted-Pair Receive output pins (TP_RXP and TP_RXN).

In reference to the ICS1892, the term ‘Twisted-Pair Transmitter’ refers to the set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN).

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ICS1892

Chapter 3 ICS1892 Enhanced Features

The ICS1892 is an enhanced version of the ICS 1890. In contrast to the ICS 1890, the ICS1892 offers significant improvements in both performance and features while maintaining backward compatibility. The specific differences between these devices are listed below.

1. The ICS1892 employs an advanced digital signal processing (DSP) architecture that improves the 100Base-TX Receiver performance beyond that of any other PHY in the market. Specifically:

a. The ICS1892 DSP-based, adaptive equalization process allows the ICS1892 to accommodate a

maximum cable attenuation/insertion loss of 29 dB, which is nearly equivalent to the attenuation loss of a 150-meter Category 5 cable.

b. The ICS1892 DSP-based, baseline-wander correction process virtually eliminates killer packets.

2. The analog 10Base-T Receive Phase-Locked Loop (PLL) of the ICS 1890 is replaced with a digital PLL in the ICS1892, thereby resulting in lower jitter and improved stability.

3. The ICS 1890 Frequency-Locked Loop (FLL) that is part of the 100Base-TX Clock and Data Recovery circuitry is replaced with a digital FLL in the ICS1892, also resulting in lower jitter and improved stability.

4. The ICS1892 transmit circuits are improved in contrast to the ICS 1890, resulting in a decrease in the magnitude of the 10Base-T harmonic content generated during transmission. (See ISO/IEC 8802-3: 1993 clause 8.3.1.3.)

5. The ICS1892 supports the Auto-Negotiation Next Page functions described in IEEE Std 802.3u-1995 clause 28.2.3.4.

6. The ICS1892 supports Management Frame (MF) Preamble Suppression.

7. The ICS1892 provides the Remote Jabber capability.

8. The ICS1892 has an improved version of the ICS 1890 10Base-T Squelch operation.

9. The ICS1892 “seeds” (that is, initializes) the Transmit Stream Cipher Shift register by using the ICS1892 PHY address from Table 8-16, which minimizes crosstalk and noise in repeater applications.

10. The ICS1892 offers an automatic 10Base-T power-down mode.

11. The enhanced features of the ICS1892 required some modifications to the ICS 1890 Management Registers. However, the ICS1892 Management Registers are backward-compatible with the ICS 1890 Management Registers. Table 3-1 summarizes the differences between the ICS 1890 and the ICS1892 Management Registers.

Chapter 3 ICS1892 Enhanced Features

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Chapter 3 ICS1892 Enhanced FeaturesICS1892 Data Sheet

Table 3-1.

Bit(s)

Summary of Differences between ICS 1890 and ICS1892 Registers

ICS 1890 ICS1892

Function Default Function Default

1.6 Reserved 0b (always) Management Frame Preamble Suppression

3.9:4 Model Number 000010b Model Number 000011b

3:0 Revision Number 0011b Revision Number 0000b

6.2 Next Page Able 0b (always) Next Page Able 1b

7.15:0 Not applicable (N/A) N/A Auto-Negotiate Next Page Transmit Register

8.15:0 N/A N/A Auto-Negotiate Next Page Link Partner Ability

9.15:0

through

15.15:0

IEEE reserved. 0000h IEEE reserved.

Note:

Although the default value is changed, this response more accurately reflects an MDIO access to registers 9–15.

18.15 Reserved 0b Remote Jabber 0b

19.1 Reserved 0b Automatic 10Base-T Power Down 1b

20.15:0

through

31.15:0

N/A N/A ICS test registers.

(There is no claim of backward compatibility for these registers.)

2001h

0000h

FFFFh

See specific registers and bits.

Note:

1. There are new registers and bits. For example: a. Registers 7 and 8 are new (that is, the ICS 1890 does not have these registers). b. Registers 20 through 31 are new ICS test registers.

2. For some bits (such as the model number and revision number bits), the default values are changed.

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Chapter 4 Overview of the ICS1892

The ICS1892 is a stream processor. During data transmission, it accepts sequential nibbles from its MAC (Media Access Control)/Repeater Interface, converts them into a serial bit stream, encodes them, and transmits them over the medium through an external isolation transformer. When receiving data, the ICS1892 converts and decodes a serial bit stream (acquired from an isolation transformer that interfaces with the medium) into sequential nibbles. It subsequently presents these nibbles to its MAC/Repeater Interface.

The ICS1892 implements the OSI model’s physical layer, consisting of the following, as defined by the ISO/IEC 8802-3 standard:

•

Physical Coding sublayer (PCS)

•

Physical Medium Attachment sublayer (PMA)

•

Physical Medium Dependent sublayer (PMD)

•

Auto-Negotiation sublayer

The ICS1892 is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1892 can interface directly to a MAC and offers multiple, configurable modes of operation. Alternately, this configurable interface can be connected to a repeater, which extends the physical layer of the OSI model.

Chapter 4 Overview of the ICS1892

The ICS1892 transmits framed packets acquired from its MAC/Repeater Interface and receives encapsulated packets from another PHY, which it translates and presents to its MAC/Repeater Interface.

Note:

As per the ISO/IEC standard, the ICS1892 does not affect, nor is it affected by, the underlying structure of the MAC/repeater frame it is conveying.

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4.1 100Base-TX Operation

During 100Base-TX data transmission, the ICS1892 accepts packets from a MAC/repeater and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1892 encapsulates each MAC/repeater frame, including the preamble, with an SSD and an ESD. As per the ISO/IEC Standard, the ICS1892 replaces the first octet of each MAC preamble with an SSD and appends an ESD to the end of each MAC/repeater frame.

When receiving data from the medium, the ICS1892 removes each SSD and replaces it with the pre-defined preamble pattern before presenting the nibbles to its MAC/Repeater Interface. When the ICS1892 encounters an ESD in the data stream, signifying the end of the frame, it ends the presentation of nibbles to its MAC/Repeater Interface. Therefore, the local MAC/repeater receives an unaltered copy of the transmitted frame sent by the remote MAC/repeater.

During periods when MAC frames are being neither transmitted nor received, the ICS1892 signals and detects the IDLE condition on the Link Segment. In the 100Base-TX mode, the ICS1892 transmit channel sends a continuous stream of scrambled ones to signify the IDLE condition. Similarly, the ICS1892 receive channel continually monitors its data stream and looks for a pattern of scrambled ones. The results of this signaling and monitoring provide the ICS1892 with the means to establish the integrity of the Link Segment between itself and its remote link partner and informing its Station Management Entity (STA) of the link status.

For 100M data transmission, the ICS1892 MAC/Repeater Interface can be configured to provide either a 100M Media Independent Interface (MII) or a 100M Symbol Interface. With the Symbol Interface configuration, the data stream bypasses the ICS1892 Physical Coding sublayer (PCS) and the following results:

1. The ICS1892 shifts the responsibility of performing the 4B/5B translation to the MAC/repeater. As a result, the requirement is for a 5-bit data path between the MAC/repeater and the ICS1892.

2. The latency through the ICS1892 reduces. (The ICS1892 provides this 100M Symbol Interface primarily for repeater applications for which latency is a critical performance parameter.)

Chapter 4 Overview of the ICS1892ICS1892 Data Sheet

4.2 10Base-T Operation

During 10Base-T data transmission, the ICS1892 inserts only the IDL delimiter into the data stream. The ICS1892 appends the IDL delimiter to the end of each MAC frame. It is not required to insert an SSD-like delimiter because the 10Base-T preamble already has a Start-of-Frame delimiter (SFD).

When receiving data from the medium (such as a twisted-pair cable), the ICS1892 uses the preamble to synchronize its receive clock. When the ICS1892 receive clock establishes lock, it presents the preamble nibbles to its MAC/Repeater Interface. The 10M MAC/Repeater Interface can be configured as either a 10M MII, a 10M Serial Interface, or a Link Pulse Interface.

In 10M operations, during periods when MAC frames are being neither transmitted nor received, the ICS1892 signals and detects Normal Link Pulses. This action allows the integrity of the Link Segment with the remote link partner to be established and then reported to the ICS1892’s STA.

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Chapter 5 Operating Modes Overview

The ICS1892 operating modes and interfaces are configurable with one of two methods. The first configuration method is by using hardware pins. With this method, the HW/SW (hardware/software) pin determines whether it is the hardware pins or the register bits that have priority for configuring the ICS1892.

The second – and more typical – configuration method is by using register bits, typically controlled from software. The register bits are accessible through a standard MII (Media Independent Interface) Serial Management Port. Even when the MAC/Repeater Interface is not supporting the standard MII Data Interface, access to the Serial Management Port is provided (that is, operation of the Serial Management Port is independent of the MAC/Repeater Interface configuration).

The ICS1892 provides a number of configuration functions to support a variety of operations. For example, the MAC/Repeater Interface can be configured to operate as a 10M MII, a 100M MII, a 100M Symbol Interface, a 10M Serial Interface, or a Link Pulse Interface. The protocol on the Medium Dependent Interface (MDI) can be configured to support either 10M or 100M operations in either half-duplex or full-duplex modes.

The ICS1892 is fully compliant with the ISO/IEC 8802-3 standard, as it pertains to both 10Base-T and 100Base-TX operations. The feature-rich ICS1892 allows easy migration from 10-Mbps to 100-Mbps operations as well as from systems that require support of both 10M and 100M links.

This chapter is an overview of the following ICS1892 modes of operation:

Chapter 5 Operating Modes Overview

•

Section 5.1, “Reset Operations”

•

Section 5.2, “Power-Down Operations”

•

Section 5.3, “Automatic Power-Saving Operations”

•

Section 5.4, “Auto-Negotiation Operations”

•

Section 5.5, “100Base-TX Operations”

•

Section 5.6, “10Base-T Operations”

•

Section 5.7, “Half-Duplex and Full-Duplex Operations”

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5.1 Reset Operations

This section first discusses reset operations in general and then specific ways in which the ICS1892 can be configured for various reset options.

5.1.1 General Reset Operations

The following reset operations apply to all the specific ways in which the ICS1892 can be reset, which are discussed in Section 5.1.2, “Specific Reset Operations”.

5.1.1.1 Entering Reset

When the ICS1892 enters a reset condition (either through hardware, power-on reset, or software), it does the following:

1. Isolates the MAC/Repeater Interface input pins

2. Drives all MAC/Repeater Interface output pins low

3. Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN)

4. Initializes all its internal modules and state machines to their default states

5. Enters the power-down state

6. Initializes all internal latching low (LL), latching high (LH), and latching maximum (LMX) Management Register bits to their default values

Chapter 5 Operating Modes OverviewICS1892 Data Sheet

5.1.1.2 Exiting Reset

When the ICS1892 exits a reset condition, it does the following:

1. Exits the power-down state

2. Latches the Serial Management Port Address of the ICS1892 into the Extended Control Register, bits

16.10:6. [See Section 8.11.3, “PHY Address (bits 16.10:6)”.]

3. Enables all its internal modules and state machines

4. Sets all Management Register bits to either (1) their default values or (2) the values specified by their associated ICS1892 input pins, as determined by the HW/SW pin

5. Enables the Twisted-Pair Transmit pins (TP_TXP and TP_TXN)

6. Resynchronizes both its Transmit and Receive Phase-Locked Loops, which provide its transmit clock (TXCLK) and receive clock (RXCLK)

7. Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition is removed

5.1.1.3 Hot Insertion

As with the ICS 1890, the ICS1892 reset design supports ‘hot insertion’ of its MII. (That is, the ICS1892 can connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the MAC/repeater.)

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5.1.2 Specific Reset Operations

This section discusses the following specific ways that the ICS1892 can be reset:

•

Hardware reset (using the RESET* pin)

•

Power-on reset (applying power to the ICS1892)

•

Software reset (using Control Register bit 0.15)

Chapter 5 Operating Modes Overview

Note:

At the completion of a reset (either hardware, power-on, or software), the ICS1892 sets all registers to their default values.

5.1.2.1 Hardware Reset

Entering Hardware Reset

Holding the active-low RESET* pin low for a minimum of five REF_IN clock cycles initiates a hardware reset (that is, the ICS1892 enters the reset state). During reset, the ICS1892 executes the steps listed in

Section 5.1.1.1, “Entering Reset”.

Exiting Hardware Reset

After the signal on the RESET* pin transitions from a low to a high state, the ICS1892 completes in 640 ns (that is, in 16 REF_IN clocks) steps 1 through 5, listed in Section 5.1.1.2, “Exiting Reset”. After the first five steps are completed, the Serial Management Port is ready for normal operations, but this action does not signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and receive clock (RXCLK) are available, which is typically 53 ms after the RESET* pin goes high. [For details on this transition, see Section 10.5.17, “Reset: Hardware Reset and Power-Down”.]

Note:

1. The MAC/Repeater Interface is not available for use until the TXCLK and RXCLK are valid.

2. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit that is used to initiate a software reset.

5.1.2.2 Power-On Reset

Entering Power-On Reset

When power is applied to the ICS1892, it waits until the potential between VDD and VSS achieves a minimum voltage of 4.5 VDC before entering reset and executing the steps listed in Section 5.1.1.1,

“Entering Reset”. After entering reset from a power-on condition, the ICS1892 remains in reset for

approximately 20 µs. (For details on this transition, see Section 10.5.16, “Reset: Power-On Reset”.)

Exiting Power-On Reset

The ICS1892 automatically exits reset and performs the same steps as for a hardware reset. (See Section

5.1.1.2, “Exiting Reset”.)

Note:

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The only difference between a hardware reset and a power-on reset is that during a power-on reset, the ICS1892 isolates the RESET* input pin. All other functionality is the same. As with a hardware reset, the Control Register bit 0.15 does not represent the status of a power-on reset.

5.1.2.3 Software Reset

Entering Software Reset

Initiation of a software reset occurs when a management entity writes a logic one to Control Register bit

0.15. When this write occurs, the ICS1892 enters the reset state for two REF_IN clock cycles.

Chapter 5 Operating Modes OverviewICS1892 Data Sheet

Note:

Entering a software reset is nearly identical to entering a hardware reset or a power-on reset, except that during a software-initiated reset, the ICS1892 does not enter the power-down state.

Exiting Software Reset

At the completion of a reset (either hardware, power-on, or software), the ICS1892 sets all registers to their default values. This action automatically clears (that is, sets equal to logic zero) Control Register bit 0.15, the software reset bit. Therefore, for a software reset (only), bit 0.15 is a self-clearing bit that indicates the completion of the reset process.

Note:

1. The RESET* pin is active low but Control Register bit 0.15 is active high.

2. Exiting a software reset is nearly identical to exiting a hardware reset or a power-on reset, except that upon exiting a software-initiated reset, the ICS1892 does not re-latch its Serial Management Port Address into the Extended Control Register. [For information on the Serial Management Port Address, see Section 8.11.3, “PHY Address (bits 16.10:6)”.]

3. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit that is used to initiate a software reset. During a hardware or power-on reset, Control Register bit 0.15 does not get set to logic one. As a result, this bit 0.15 cannot be used to indicate the completion of the reset process for hardware or power-on resets.

5.2 Power-Down Operations

The ICS1892 enters the power-down state whenever either (1) the RESET* pin is low or (2) Control Register bit 0.11 (the Power-Down bit) is logic one. In the power-down state, the ICS1892 disables all internal functions and drives all MAC/Repeater Interface output pins to logic zero except for those that support the MII Serial Management Port. In addition, the ICS1892 tri-states its Twisted-Pair Transmit pins (TP_TXP and TP_TXN) to achieve an additional reduction in power.

There is one significant difference between entering the power-down state by setting Control Register bit

0.11 as opposed to entering the power-down state during a reset. When the ICS1892 enters the

power-down state:

•

By setting Control Register bit 0.11, the ICS1892 maintains the value of all Management Register bits except for the latching low (LL), latching high (LH), and latching maximum (LMX) status bits. Instead, these LL, LH, and LMX Management Register bits are re-initialized to their default values.

•

During a reset, the ICS1892 sets all of its Management Register bits to their default values. It does not maintain the state of any Management Register bit.

For more information on power-down operations, see the following:

•

Section 8.14, “Register 19: Extended Control Register 2”

•

Section 10.4, “DC Operating Characteristics”, which has tables that specify the ICS1892 power

consumption while in the power-down state

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5.3 Automatic Power-Saving Operations

The ICS1892 has power-saving features that automatically minimize its total power consumption while it is operating. Table 5-1 lists the ICS1892 automatic power-saving features for the various modes.

Chapter 5 Operating Modes Overview

Table 5-1.

PowerSaving

Feature

Disable Internal Modules

STA Control of Automatic PowerSaving Features

Automatic Power-Saving Features, 10Base-T and 100Base-TX Modes

10Base-T Mode 100Base-TX Mode

In 10Base-T mode, the ICS1892 disables all its internal 100Base-TX modules.

When an STA sets the state of the ICS1892 Extended Control Register 2, bit 19.0 to logic:

•

Zero, the 100Base-TX modules always remain enabled, even during 10Base-T operations.

•

One, the ICS1892 automatically disables 100Base-TX modules while the ICS1892 is operating in 10Base-T mode.

5.4 Auto-Negotiation Operations

The ICS1892 has an Auto-Negotiation sublayer. It provides both an input pin, ANSEL (Auto-Negotiation Select) and a Control Register bit (bit 0.12) to determine whether its Auto-Negotiation sublayer is enabled or disabled. The ICS1892 HW/SW input pin exclusively selects whether the ANSEL pin (which is used for the hardware mode) or Control Register bit 0.12 (which is used for the software mode) controls its Auto-Negotiation sublayer.

When enabled, the ICS1892 Auto-Negotiation sublayer exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode it has in common with its remote link partner. For example, if the ICS1892 supports 100Base-TX and 10Base-T modes – but its link partner supports 100Base-TX and 100Base-T4 modes – the two devices automatically select 100Base-TX as the highest-performance common operating mode. For details regarding initialization and control of the auto-negotiation process, see Section 7.2, “Functional Block: Auto-Negotiation”.

Mode for ICS1892

In 100Base-TX mode, the ICS1892 disables all its internal 10Base-T modules.

When an STA sets the state of the ICS1892 Extended Control Register 2, bit 19.1 to logic:

•

Zero, the 10Base-T modules always remain enabled, even during 100Base-TX operations.

•

One, the ICS1892 automatically disables 10Base-T modules while the ICS1892 is operating in 100Base-TX mode.

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5.5 100Base-TX Operations

The ICS1892 100Base-TX mode is a primary operating mode that provides 100Base-TX physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 100Base-TX mode, the ICS1892 is a 100M translator between a MAC/repeater and the physical transmission medium. As such, the ICS1892 has two interfaces, both of which are fully configurable: one to the MAC/repeater and one to the Link Segment. In 100Base-TX mode, the ICS1892 provides the following functions:

•

Data conversion from both parallel-to-serial and serial-to-parallel formats

•

Data encoding/decoding (4B/5B, NRZ/NRZI, and MLT-3)

•

Data scrambling/descrambling

•

Data transmission/reception over a twisted-pair medium

To accurately transmit and receive data, the ICS1892 employs DSP-based wave shaping, adaptive equalization, and baseline wander correction. In addition, in 100Base-TX mode, the ICS1892 provides a variety of control and status means to assist with Link Segment management. For more information on 100Base-TX, see Section 7.4, “Functional Block: 100Base-TX TP-PMD Operations”.

5.6 10Base-T Operations

The ICS1892 10Base-T mode is another primary operating mode that provides 10Base-T physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 10Base-T mode, the ICS1892 is a 10M translator between a MAC/repeater and the physical transmission medium. As such, the ICS1892 has two interfaces, both of which are fully configurable: one to the MAC/repeater and one to the Link Segment. In 10Base-T mode, the ICS1892 provides the following functions:

•

Data conversion from both parallel-to-serial and serial-to-parallel formats

•

Manchester data encoding/decoding

•

Data transmission/reception over a twisted-pair medium

In addition, in 10Base-T mode, the ICS1892 provides a variety of control and status means to assist with Link Segment management. For more information on 10Base-T, see Section 7.5, “Functional Block:

10Base-T Operations”.

Chapter 5 Operating Modes OverviewICS1892 Data Sheet

5.7 Half-Duplex and Full-Duplex Operations

The ICS1892 supports half-duplex and full-duplex operations for both 10Base-T and 100Base-TX applications. Full-duplex operation allows simultaneous transmission and reception of data, which effectively doubles the Link Segment throughput to either 20 Mbps (for 10Base-T operations) or 200 Mbps (for 100Base-TX operations).

As per the ISO/IEC standard, full-duplex operations differ slightly from half-duplex operations. These differences are necessary, as during full-duplex operations a PHY actively uses both its transmit and receive data paths simultaneously.

•

In 10Base-T full-duplex operations, the ICS1892 disables its loopback function (that is, it does not automatically loop back data from its transmitter to its receiver and disable its SQE Test function).

•

In both 10Base-T and 100Base-TX full-duplex operations, the ICS1892 asserts its CRS signal only in response to receive activity while its COL signal always remains inactive.

For more information on half-duplex and full-duplex operations, see the following sections:

•

Section 8.2, “Register 0: Control Register”

•

Section 8.2.8, “Duplex Mode (bit 0.8)”

•

Section 8.3, “Register 1: Status Register”

•

Section 8.6, “Register 4: Auto-Negotiation Register”

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Chapter 6 Interface Overviews

The ICS1892 MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications.

This chapter includes overviews of the following MAC/repeater-to-PHY interfaces:

•

Section 6.1, “MII Data Interface”

•

Section 6.2, “100M Symbol Interface”

•

Section 6.3, “10M Serial Interface”

•

Section 6.4, “Link Pulse Interface”

•

Section 6.5, “Serial Management Interface”

•

Section 6.6, “Twisted-Pair Interface”

•

Section 6.7, “Clock Reference Interface”

•

Section 6.8, “Configuration Interface”

•

Section 6.9, “Status Interface”

Chapter 6 Interface Overviews

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6.1 MII Data Interface

The most common configuration for the ICS1892 MAC/Repeater Interface is to configure the MAC/Repeater Interface as a Medium Independent Interface (MII) operating at either 10 Mbps or 100 Mbps (depending on the configuration). When the MAC/Repeater Interface is configured for the MII Data Interface mode, the MAC/Repeater Interface is used to transfer between the ICS1892 and the MAC/repeater framed, 4-bit parallel nibbles, along with control and status signals.

The ICS1892 implements an MII that is fully compliant with the IEEE Std 802.3u when connecting to MACs or repeaters. The ICS1892 MII supports a variety of interfaces to MACs and repeaters, which can occur as follows:

•

On the same board (that is chip to chip)

•

On a motherboard to a daughterboard

•

Through an MII connector and cable (in a manner similar to AUI connections)

Clause 22 of the ISO/IEC standard defines the MII between an Ethernet PHY and the MAC/Reconciliation sublayer for 10-Mbps and 100-Mbps operations. The specification supports a variety of physical media, including 100Base-TX, 100Base-T4, and 100Base-FX. The specification is such that use of a specific medium for the Link Segment is transparent to the MAC. The ICS1892 supports this definition for both 100Base-TX and 10Base-T operations.

The ISO/IEC-specified MII has both a transmit and a receive data path. Each data path can synchronously exchange 4 bits of data (that is, nibbles).

Chapter 6 Interface OverviewsICS1892 Data Sheet

•

The transmit data path includes the following:

– A data nibble, TXD[3:0] – A transmit data clock to synchronize transfers, TXCLK – A transmit enable signal, TXEN – A transmit error signal, TXER

•

The receive data path includes the following:

– A separate data nibble, RXD[3:0] – A receive data clock to synchronize transfers, RXCLK – A receive data valid signal, RXDV – A receive error signal, RXER

Both the transmit clock and the receive clock are provided to the MAC/Reconciliation sublayer by the ICS1892 (that is, the ICS1892 sources the TXCLK and RXCLK signals).

Clause 22 also defines as part of the MII a Carrier Sense signal (CRS) and a Collision Detect signal (COL). The ICS1892 is fully compliant with these definitions and sources both of these signals to the MAC/repeater. When operating in:

•

Half-duplex mode, the ICS1892 asserts the Carrier Sense signal when data is being either transmitted or received. While operating in half-duplex mode, the ICS1892 also asserts the Collision Detect signal to indicate that data is being received while a transmission is in progress.

•

Full-duplex mode, the ICS1892 asserts the Carrier Sense signal only when receiving data and forces the Collision Detect signal to remain inactive.

As mentioned in Section 5.1.1.3, “Hot Insertion”, the ICS1892 design allows hot insertion of its MII. That is, it is possible to connect its MII to a MAC when power is already applied to the MAC. To support this functionality, the ICS1892 isolates its MII signals and tri-states the signals on the Twisted-Pair Transmit pins (TP_TXP and TP_TXN) during a power-on reset. Upon completion of the reset process, the ICS1892 enables its MII and enables its Twisted-Pair Transmit signals.

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6.2 100M Symbol Interface

The 100M Symbol Interface has a primary objective of supporting 100Base-TX repeater applications for which the repeater requires only recovered parallel data and for which the repeater provides all the necessary framing and control functions.

When the Mac/Repeater Interface is configured for 100M Symbol operations, the ICS1892 and the MAC/repeater exchange unframed 5-bit, parallel symbols at a 25-MHz clock rate.

The ICS1892 configuration functions determine the operation of the MAC/Repeater Interface. The configuration functions are controlled by either input pins (in which case, the HW/SW pin is logic zero to select the hardware mode) or Management Register bits (in which case, the HW/SW pin is logic one to select the software mode).

•

In hardware mode, the ICS1892 enables the 100M Symbol Interface when both of the following are true:

– The MII/SI input pin is logic one (that is, the selection is for the Symbol Interface). – The 10/100SEL input pin is logic one (that is, the selection is for 100M operations).

•

In software mode, the ICS1892 enables the 100M Symbol Interface when both the following are true:

– The MII/SI input pin is logic one (that is, the selection is for the Symbol Interface). – The Control Register Data Rate bit (bit 0.13) is set to logic one (that is, the selection is for selecting

100M operations)

Chapter 6 Interface Overviews

Note:

The 100M Symbol Interface bypasses the ICS1892 PCS and provides a direct unscrambled, unframed, 5-bit interface between the MAC/repeater and the PMA sublayer. A benefit of bypassing the PCS is a reduction in the latency through the ICS1892. That is, when the ICS1892 MAC/Repeater Interface is configured as a 100M Symbol Interface, the bit delays through the ICS1892 are smaller than the standard MII Data Interface can allow. The ICS1892 provides this 100M Symbol Interface primarily for Repeater applications, for which latency is a critical performance parameter.

In addition to the exchange of symbol data, the ICS1892 provides ISO/IEC-compliant control signals (such as CRS) to the MAC/repeater. The ICS1892 CRS signal provides a fast look-ahead, which can benefit a repeater application.

In the 100M Symbol Interface mode, the ICS1892 continues to assert the CRS signal using its PCS logic. This action does not affect the bit delay or latency because the PCS CRS logic examines the bits received from the PMA sublayer serially. In fact, because the PCS CRS does not wait for a nibble or symbol to be constructed, the PCS CRS is available in advance of the symbol generation. Therefore, by employing the PCS CRS generation logic, the ICS1892 can provide an ‘early’ indication of a Carrier Detect to the MAC/repeater.

The 100M Symbol Interface consists of the following fourteen signals: STCLK, STD[4:0], SRCLK, SRD[4:0], SCRS, and SD. (When the ICS1892 MAC/Repeater Interface is configured for 100M Symbol operations, its default MII pin names and their associated functions are redefined. For more information, see Section 9.2.4.2, “MAC/Repeater Interface Pins for 100M Symbol Interface”.)

In software mode, the 10/100SEL pin becomes an output that indicates the state of bit 0.13.

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Chapter 6 Interface OverviewsICS1892 Data Sheet

Table 6-1 lists the pin mappings for the ICS1892 100M Symbol Interface mode.

Table 6-1.

Default

10M / 100M

Pin Mappings for 100M Symbol Interface Mode

MAC/Repeater Interface Pin Mappings, Configured for

100M Symbol Interface Mode

MII Pin Names

COL No connect. [Because the MAC/repeater sources both active and ‘idle’ data, a PHY

cannot distinguish between an active and idle transmission channel (that is, to a PHY the transmit channel always appears active). Therefore, a PHY cannot accurately detect a collision.]

CRS SCRS

LSTA SD

MDC MDC

MDIO MDIO

RXCLK SRCLK

RXD0 SRD0

RXD1 SRD1

RXD2 SRD2

RXD3 SRD3

RXDV No connect. (Data exchanged between the MAC/repeater and a PHY is not framed in

the 100M Symbol Interface mode. Therefore, RXDV has no meaning.)

RXER SRD4

TXCLK STCLK

TXD0 STD0

TXD1 STD1

TXD2 STD2

TXD3 STD3

TXEN No connect. (100Base-TX operations require continuous transmission of data.

Therefore, the MAC/repeater is responsible for sourcing IDLE symbols when it is not transmitting data.)

TXER STD4

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6.3 10M Serial Interface

When the Mac/Repeater Interface is configured as a 10M Serial Interface, the ICS1892 and the MAC/repeater exchange a framed, serial bit stream along with associated control signals. The 10M Serial Interface configuration is ideally suited to applications that already incorporate a serial 10Base-T MAC with a standard ‘7-wire’ interface. The ICS1892 MAC/Repeater Interface can be configured for 10M Serial Interface operations, as determined by ICS1892 configuration functions. When the HW/SW pin is set for:

•

Hardware mode, the 10M Serial Interface is selected when the following are true:

– The MII/SI input pin is logic one (that is, the selection is for a Serial Interface). – The 10/100SEL input pin is logic zero (that is, the selection is for 10M operations). – The 10/LP input pin is logic zero

•

Software mode, the 10M Serial Interface is selected when the following are true:

– The MII/SI input pin is logic one (that is, the selection is for a Serial Interface). – The Control Register Data Rate bit (bit 0.13) is logic zero (that is, the selection is for 10M operations). – The 10/LP input pin is logic zero

Chapter 6 Interface Overviews

Note:

The 10M Serial Interface has two data paths: one for data transmission and one for data reception. Each data path exchanges a serial bit stream with the MAC/repeater at a 10-MHz clock rate. A benefit of using the 10M Serial Interface – in contrast to the 10M MII Interface – is a reduction in the bit latency through the ICS1892. This reduction is attributed to the elimination of both parallel-to-serial and serial-to-parallel data conversions.

The 10M Serial Interface consists of the following nine signals: 10TCLK, 10TXEN, 10TD, 10RCLK, 10RXDV, 10RD, 10CRS, 10COL, and LSTA. (When the ICS1892 MAC/Repeater Interface is configured for 10M Serial operations, both its default MII pin names and their associated functions are redefined. For more information, see Section 9.2.4.3, “MAC/Repeater Interface Pins for 10M Serial Interface”.)

In software mode, the 10/100SEL pin becomes an output that indicates the state of bit 0.13.

ICS1892, Rev. D, 2/26/01 February 26, 2001

Table 6-2 lists the pin mappings for the ICS1892 10M Serial Interface mode.

Chapter 6 Interface OverviewsICS1892 Data Sheet

Table 6-2.

10M / 100M

Pin Mappings for 10M Serial Interface Mode

Default

MAC/Repeater Interface Pin Mappings, Configured for

10M Serial Interface Mode

MII Pin Names

COL 10COL

CRS 10CRS

LSTA LSTA

MDC MDC

MDIO MDIO

RXCLK 10RCLK

RXD0 10RD

RXD1, RXD2, RXD3 No connect. [Data reception is serial, so only the 10RD (RXD0) pin is needed.]

RXDV 10RXDV

RXER No connect. (10Base-T mode does not support error generation or detection.)

TXCLK 10TCLK

TXD0 10TD

TXD1, TXD2, TXD3 No connect. [Data transmission is serial, so only the 10TD (TXD0) pin is needed.]

TXEN 10TXEN

TXER No connect. (0Base-T mode does not support error generation or detection.)

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6.4 Link Pulse Interface

The Link Pulse Interface allows an application to control each step in the auto-negotiation process except for the actual generation and reception of 10Base-T link pulses (that is, Normal Link Pulses). The ICS1892 MAC/Repeater Interface can be configured as a Link Pulse Interface as determined by ICS1892 configuration functions.

The Link Pulse Interface is selected as follows:

•

The HW/SW pin must be set for the hardware setting (logic low).

•

The MII/SI input pin must be set for the Symbol/Serial Interface (logic high).

•

The 10/LP input pin must be set for Link Pulse mode (logic high).

•

The 10/100SEL input pin must be set for 100M operations (logic high).

Although the 10/100SEL pin must be set for 100M operations, a Normal Link Pulse has the same ISO/IEC definition regardless of whether the 10/100SEL pin is set for 10M (10 MHz) or 100M (100 MHz.)

The Link Pulse Interface allows the MAC/repeater to control the transmission of Normal Link Pulses to the remote link partner, thereby allowing the MAC/repeater to control the auto-negotiation processes.

The Link Pulse Interface consists of the following five signals: LTCLK, LPTX, LRCLK, LPRX, and SD. (When the ICS1892 MAC/Repeater Interface is configured for Link Pulse operations, its default MII pins are redefined. For more information, see Section 9.2.4.4, “MAC/Repeater Interface Pins for Link Pulse

Interface”.)

Table 6-3 lists the ICS1892 pin mappings for the ICS1892 Link Pulse Interface mode.

Chapter 6 Interface Overviews

Table 6-3.

COL No connect

CRS No connect

LSTA SD

MDC MDC

MDIO MDIO

RXCLK LRCLK

RXD0, RXD1, RXD2, RXD3 No connect

RXDV No connect

RXER LPRX

TXCLK LTCLK

TXD0, TXD1, TXD2, TXD3 No connect

TXEN No connect

TXER LPTX

Pin Mappings for Link Pulse Interface Mode

Default

10M / 100M

MII Pin Names

MAC/Repeater Interface Pin Mappings, Configured for

Link Pulse Interface Mode

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6.5 Serial Management Interface

The ISO/IEC 8802-3 standard specifies a two-wire Serial Management Interface and protocol as part of the MII. This interface is used to exchange configuration, control, and status information between a Station Management entity (an STA) and a physical layer device (a PHY). The ISO/IEC standard specifies a frame structure and protocol for this interface as well as a set of Management Registers that it can access. The ICS1892 implementation of this interface complies fully with the ISO/IEC standard. It provides a bi-directional data pin (MDIO) along with an input pin for the clock (MDC). The clock is used to synchronize all data transfers between a PHY and the STA.

In addition to the ISO/IEC defined registers, the ICS1892 provides several extended status and control registers to provide more refined control of the MII and MDI interfaces. For example, the QuickPoll Detailed Status Register provides the ability to acquire the most-important status functions with a single MDIO read.

In the ICS1892, the MDIO and MDC pins remain active for all the MAC/Repeater Interface modes, that is, 10M/100M MII, 100M Symbol, 10M Serial, and Link Pulse. Therefore, to the ICS1892 the signals from these pins represent the Serial Management Interface, not just the MII Management Interface.

6.6 Twisted-Pair Interface

The ICS1892 twisted-pair interface consists of the following:

•

Twisted-Pair Transmitter: The differential Twisted-Pair Transmit pins TP_TXP and TP_TXN

•

Twisted-Pair Receiver: The differential Twisted-Pair Receive pins TP_RXP and TP_RXN

•

Transmit current-select pins: 10TCSR and 100TCSR

The ICS1892 uses the same pins for both 10Base-T and 100Base-TX operating modes. The differential Twisted-Pair Transmit and Twisted-Pair Receive pins directly interface with a universal magnetic module, which in turn interfaces with a single RJ-45 connector. The universal magnetic module has two isolation transformers: one for the transmit channel and one for the receive channel. The isolation transformers provide the interface between the ICS1892 and the twisted-pair medium.

Chapter 6 Interface OverviewsICS1892 Data Sheet

6.7 Clock Reference Interface

The REF_IN and REF_OUT pins provide the ICS1892 Clock Reference Interface. The ICS1892 requires a single clock reference with a frequency of 25 MHz ±50 parts per million. This accuracy is necessary to meet the interface requirements of the ISO/IEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4.

The ICS1892 supports three clock source configurations. The clock source can be from (1) an oscillator, (2) a CMOS driver, or (3) a crystal. The following paragraphs offer specific design recommendations for these clock sources.

6.7.1 Clock Source: Oscillator or CMOS Driver

When using either an oscillator or a CMOS driver, the design must provide a connection from the clock source to the ICS1892 REF_IN pin while leaving the ICS1892 REF_OUT pin unconnected. ICS also recommends that the design provide a dedicated driver for the REF_IN pin.

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