ICST ICS1567M Datasheet

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ICS1567

Integrated

Circuit

Systems, Inc.

Differential Output Video Dot Clock Generator

General Description

The ICS1567 is a very high performance monolithic PLL frequency synthesizer. Utilizing ICS’s advanced CMOS mixed-mode technology, the ICS1567 provides a low cost solution for high-end video clock generation, and for telecom system clock generation.

The ICS1567 has differential video clock outputs (CLK and CLK) that are compatible with industry standard video DACs & RAMDACs. An additional clock output, LD, is provided, whose frequency is divided down from the main clock by a programmable divider.

Operating frequencies are selectable from a pre-programmed (customer-defined) table. An on-chip crystal oscillator for generating the reference frequency is provided on the ICS1567.

Programming of the ICS1567 is accomplished via frequency select pins on the package. The ICS1567 has five lines plus a STROBE pin which permits selection of 32 frequencies. Reset of the pipeline delay on Brooktree RAMDACs is automatically performed on a rising edge of the STROBE line.

Features

High frequency operation for extended video modes - up to 180 MHz

Compatible with Brooktree high performance RAMDACs

a)Differential output clocks with ECL logic levels

b)Programmable divider modulus for load clock

c)Circuitry included for automatic reset of Brooktree RAMDAC pipeline delay

Low cost - eliminates need for multiple ECL crystal clock oscillators in video display systems

Strobed/Transparent frequency select options

32-user selected mask-programmable frequencies

Fast acquisition of selected frequencies, strobed or nonstrobed

Advanced PLL for low phase-jitter

Dynamic control of VCO sensitivity providing optimized loop gain over entire frequency range

Small footprint - 16-pin wide body (300 mil) SOIC

Applications

Workstations

High-resolution PC and MAC displays

8514A - TMS340X0 systems

EGA - VGA - Super VGA video

Telecom reference clock generation - suitable for Sonet, ATM and other data rates up to 155.52Mb.

Pin Configuration

FS0

1

 

 

XTAL1

2

 

XTAL2

3

ICS1567

VSS

6

STROBE

4

 

VSS

5

 

 

 

 

 

 

 

LD

7

 

FS4

8

 

16 FS1

15 FS2

14 FS3

13 VDD

12 VDDO

11 VDDO

10 CLK

9 CLK

16-Pin SOIC

ICS1567RevB090894

ICST ICS1567M Datasheet

ICS1567

Block Diagram

 

 

 

 

 

LOOP

 

X1

 

 

 

 

FILTER

 

CRYSTAL

 

/ R

 

CHARGE

 

X2

 

PHASE

VCO

OSCILL.

 

 

 

 

 

COMP.

 

 

 

 

 

 

 

 

 

 

 

 

 

PRESCALER

 

 

 

 

/ M

/ A

 

 

 

 

 

 

DIFF.

CLK+

FS0

 

 

 

 

CLK−

ROM

/ 2

 

MUX

OUTPUT

FS1

 

 

 

 

 

 

 

 

 

 

 

 

FS2

 

/ 4

 

/ N1

 

 

FS3

 

 

 

 

 

 

 

 

 

MUX

 

FS4

 

 

 

 

LOAD

 

 

 

 

DRIVER

STROBE

 

 

 

 

 

 

 

 

 

 

 

Figure 1

System Schematic

FS0

 

1

 

16

 

 

FS1

 

2

 

15

 

 

 

 

 

 

 

FS2

 

XTAL

3

 

14

 

 

 

 

 

 

FS3

 

 

 

 

 

 

 

4

ICS1567

13

 

 

STROBE

 

 

 

 

VDD

 

5

12

 

10

 

 

 

 

 

VDDO

 

VSS

6

 

11

 

 

 

 

 

7

 

10

 

 

 

 

LOAD

 

 

 

 

CLK

 

 

 

 

 

 

FS4

 

8

 

9

 

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

C3

C2

C1+

 

 

 

 

 

 

.1

.1

22

 

 

Figure 2

2

ICS1567

Typical Output Configuration

Notes:

CLK & CLK outputs are pseudo-ECL. Logic low level is set by the ratio of the resistors stacked across the power supply VLO = (V supply • 160)/(110 +160) in the example shown above.

The above values are a good starting point for RAMDAC or clock generator interface.

 

 

 

 

 

 

Figure 3

Pin Description

 

 

 

 

 

 

 

 

 

 

 

PIN NUMBER

 

PIN SYMBOL

TYPE

 

DESCRIPTION

 

 

 

 

 

 

 

 

1

• FS0

IN

 

Frequency Select LSB.

2

XTAL1

IN

 

Crystal Interface/External Oscillator Input.

3

XTAL2

OUT

 

Crystal Interface.

4

• STROBE

IN

 

Control For Frequency Select Latch, also performs automatic

 

 

 

 

 

 

 

RAMDAC reset.

5

VSS

--

 

Device Ground (Both pins must be connected.)

6

VSS

--

 

Device Ground (Both pins must be connected.)

7

 

 

 

 

OUT

 

Load Output. This output is at CLK frequency divided by N1.

LD

 

8

• FS4

IN

 

Frequency Select MSB.

9

 

 

 

OUT

 

Clock Output Inverted.

CLK

 

10

CLK

OUT

 

Clock Output Non-Inverted.

11

 

VDDO

--

 

Output Stage Power (Both pins must be connected).

 

 

 

 

 

 

 

 

12

VDDO

--

 

Output Stage Power (Both pins must be connected).

13

VDD

--

 

PLL System Power.

14

• FS3

IN

 

Frequency Select.

15

• FS2

IN

 

Frequency Select.

16

• FS1

IN

 

Frequency Select.

 

 

 

 

 

 

 

 

• = inputs with internal pull-up resistor

3

ICS1567

Circuit Description

Overview

The ICS1567 is designed to provide the graphics system clock signals required by industry standard RAMDACs. One of 32 pre-programmed (user-definable) frequencies may be selected under digital control. Fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just simple multiples of the reference frequency. The ICS1567 uses the latest generation of frequency synthesis techniques developed by ICS and is completely suitable for the most demanding video applications.

Digital Inputs

The FS0-FS4 pins and the STROBE pin are used to select the desired operating frequency from the 32 pre-programmed frequencies in the ROM table of the ICS1567. The STROBE pin also controls activation of the pipeline delay RESET function included in the ICS1567 (see PIPELINE DELAY RESET section for details). The FS0-FS4 and STROBE pins are each equipped with a pull-up and will be at a logic HIGH level when not connected.

Transparent Mode - When the STROBE pin is held HIGH, the FS0 through FS4 inputs are transparent; that is, they directly access the ROM table. The synthesizer will output the frequency programmed into the location addressed by the FS0-FS4 pins.

Latched Mode - When the STROBE pin is held LOW, the FS0-FS4 pins are ignored. The synthesizer will output the frequency corresponding to the state of the FS0-FS4 pins when the STROBE pin was last HIGH. In the event that the ICS1567 is powered-up with the STROBE pin held LOW, the synthesizer will output the frequency programmed into address 0 (i.e., the one selected with FS0 through FS4 at a logic LOW level).

Frequency Synthesizer Description

Refer to Figure 1 for a block diagram of the ICS1567. The reference frequency is generated by an on-chip crystal oscillator, or the reference frequency may be applied to the ICS1567 from an external frequency source.

The ICS1567 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency provided to the PLL. The phase-frequency detector shown in the block diagram drives the VCO to a frequency that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. This occurs when:

F(vco) =

F(XTAL1) Feedback Divider

Reference Divider

This expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency provided to the part (assuming correctly-programmed dividers). The divider programming is one of the functions performed by the ROM look-up table in the ICS1567. The VCO gain is also ROM programmable which permits the ICS1567 to be optimized for best performance at each frequency in the table.

The feedback divider makes use of a dual-modulus prescaler technique that allows construction of a programmable counter to operate at high speeds while still allowing the feedback divider to be programmed in steps of 1. This is an improvement over conventional fixed prescaler architectures that typically impose a factor-of-four penalty (or larger) in this respect.

A post-divider may be inserted between the VCO and the CLK and CLK outputs of the ICS1567. This is useful in generation of lower frequencies, as the VCO has been optimized for high-frequency operation. Different post-divider settings may be used for each frequency in the table.

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