ICST GSP90C65V, GSP90C65N, GSP90C65M, AV90C65V, AV90C65N, AV90C65M, ICS90C65M, ICS90C65N, ICS90C65V Datasheet

Loading...
ICST GSP90C65V, GSP90C65N, GSP90C65M, AV90C65V, AV90C65N, AV90C65M, ICS90C65M, ICS90C65N, ICS90C65V Datasheet

Integrated

ICS90C65

Circuit

 

Systems, Inc.

 

Dual Voltage Video/Memory Clock Generator

Introduction

The Integrated Circuit Systems ICS90C65 is a dual clock generator for VGA applications. It simultaneously generates two clocks. One clock is for the video memory, and the other is the video dot clock.

The ICS90C65 has been specifically designed to serve the portable PC market with operation at either 3.3V or 5V with a comprehensive power-saving shut-down mode.

This data sheet supplies sales order information, a functional overview, signal pin details, a block diagram, AC/DC characteristics, timing diagrams, and package mechanical information.

Description

The Integrated Circuit Systems Video Graphics Array Clock Generator (ICS90C65) is capable of producing different output frequencies under firmware control. The video output frequency is derived from a 14.318 MHz system clock available in IBM PC/XT/AT and Personal System/2 computers. It is designed to work with Western Digital Imaging Video Graphics Array and 8514/A devices to optimize video subsystem performance.

The video dot clock output may be one of 15 internallygenerated frequencies or one external input. The selection of the video dot clock frequency is done through four inputs.

VSEL0

VSEL1

VSEL2

VSEL3

Features

Specified for dual voltage operation (VDD=3.3V or 5V), but operates continuously from 3.0V to 5.25V

Designed to be powered-down for extended battery life

Backward compatibility to the ICS90C64 and ICS90C63

Dual Clock generator for the IBM-compatible Western Digital Imaging Video Graphics Array (VGA) LSI devices, and 8514/A chip sets

Integral loop filter components, reduce cost and phase jitter

Generates fifteen video clock frequencies (including 25.175 and 28.322 MHz) derived from a 14.318 MHz system clock reference frequency

On-chip generation of eight memory clock frequencies

Video clock is selectable among the 15 internally generated clocks and one external clock

CMOS technology

Available in 20-pin PLCC, SOIC and DIP packages

VSEL0 and VSEL1 are latched by the SELEN signal. VSEL2 and VSEL3 are used as direct inputs to the VCLK selection. Table 1-1 is the truth table for VCLK selection.

The input and truth table have been designed to allow a direct connection to one of the many Western Digital Imaging VGA controllers or 8514/A chip sets.

The MCLK output is one of eight internally-generated frequencies as shown in Table 1-2. The various VCLK and MCLK frequencies are derived from the 14.318 MHz input frequency.

The VCLKE and MCLKE input can tristate the VCLK and

MCLK outputs to facilitate board level testing.

Note:ICS90C65N (DIP) pin-out is identical to ICS90C65M (SOIC) pin-out.

90C65ARevA111095

ICS90C65

ICS90C65 VGA Interface

The ICS90C65 has two system interfaces: System Bus and VGA Controller, as well as other programmable inputs. Figure 1 shows how the Integrated Circuit Systems’s VGA Clock ICS90C65 is connected to a VGA controller. Western Digital Imaging VGA controllers normally have a status bit that indicates to the VGA controller that it is working with a clock chip. When working with a clock chip the VGA controller changes t wo of i ts cl ock inputs to outputs . They are theVCLK1/VCSLD/VCSEL and VCLK2/VCSEL/VCSELH outputs and they are used to select the required video frequency.

When the power-down capabilities are used, the control signal for PWRDN is normally held in one of a group of latches. If the power-down function is not to be used, PWRDN must be tied to VDD, otherwise the internal pull-down will place the chip in the power-down mode.

WD90C26

pull-up at reset

 

AMD(3)

 

and PR15(5)=0

 

LATCH

 

 

VCKIN

VCS

 

 

 

 

 

MCLK

VCSEL

 

 

 

ICS90C65

SD2

 

VSEL0

PWRDN

SD3

 

VSEL1

VCLK

 

 

 

 

 

VSEL2

MC

 

 

 

 

SELEN

14.318

 

CLK1

 

MHz

 

 

 

 

 

Figure 1

2

ICS90C65

System Bus Inputs

The system bus inputs are:

CLKI

VSEL0

VSEL1

The ICS90C65 uses the system bus 14.318 MHz clock as a reference to generate all its frequencies for both video and memory clocks. Data lines D2 and D3 are commonly used as inputs to VSEL0 and VSEL1 for video frequency selection.

Inputs from VGA Controller

The VGA controller input to the ICS90C65 is:

SELEN

The ICS90C65 is programmed to generate different video clock frequencies using the inputs of VSEL0, VSEL1, VSEL2, and VSEL3. The signals VSEL2 and VSEL3 may be supplied by the VGA controller as is the case in Western Digital Imaging VGA controllers. The inputs VSEL0-1 are latched with the signal SELEN. The SELEN input should be an active low pulse. This active low pulse is generated in Western Digital Imaging VGA controllers during I/O writes to internal register 3C2h.

Note: Only VSEL0 and VSEL1 are latched with signal SELEN.

Outputs to VGA Controller

The outputs from the ICS90C65 to the VGA controller are:

MCLK

VCLK

MCLK and VCLK are the two clock outputs to the VGA controller.

Analog Filters

The analog filters are integral to the ICS90C65 device. No external components are required. This feature reduces PC board space requirements and component costs. Phase-jitter is reduced as externally-generated noise cannot easily influence the phase-locked loop filter.

User-Definable Inputs

The user definable inputs are:

EXTCLK

VLCKE, MCLKE

MSELO-2

VSEL2, VSEL3

PWRDN

EXTCLK is an additional input that may be internally routed to the VCLK output. This additional input is useful for supporting modes that require frequencies not provided by the ICS90C65 or for use during board test.

VCLKE and MCLKE are the output enable signals for VCLK and MCLK. When low the respective output is tristated.

MSEL0-2 are the memory clock (MCLK) select lines. Table 1-2 shows how MCLK frequencies are selected. All signals in this group have internal pull-up resistors.

VSEL2 and VSEL3 are video clock (VCLK) select lines that can select additional VCLK frequencies. See Table 1-1.

VSEL2 and VSEL3 have internal pull-ups.

PWRDN can place the ICS90C65 in a power-down mode which drops its supply current requirement below 1 microamp. When placed in this mode, the digital inputs may be either high or low or floating without causing an increase in the ICS90C65 supply current.

The PWRDN pin must be low (It has an internal pull-down.) in order to place the device in its low power state. The output pins (VCLK and MCLK) are driven high by the ICS90C65 when it is in its low power state.

If CLKI is being driven by an external source, it may be driven low or high without a power penalty. If CLKI is at an intermediate voltage (VSS+0.5 < VIN <VDD-0.5), there will be a small increase in supply current. If CLKI is driven at 14.318 MHz while the chip is in power-down, the ICS90C65 supply current will increase to approximately 1.2 mA.

The SELEN (pin 6) may be used to guard against inadvertent frequency changes during power-down/powerup sequences. By holding the SELEN low during power-down and power-up sequences, the ICS90C65 will retain the most recent video frequency selection.

3

+ 7 hidden pages