ICST ICS1887M Datasheet

Integrated	ICS1887
Circuit
Systems, Inc.
FDDI / Fast Ethernet PHYceiverTM

General Description

The ICS1887 is designed to provide high performance clock recovery and generation for 125 MHz serial data streams. The ICS1887 is ideally suited for LAN transceiver applications in either FDDI or Fast Ethernet environments. The ICS1887 converts NRZ to/from NRZI data in addition to providing a 5-bit parallel digital data transmit and receive interface.

Clock and data recovery is performed on an input serial data stream or the buffered transmit data depending upon the state of the loopback input. A continuous clock source will continue to be present even in the absence of input data. All internal timing is derived from either a low cost crystal, differential or single-ended source.

The ICS1887 utilizes advanced CMOS phase-locked loop technology which combines high performance and low power at a greatly reduced cost.

Features

•Single IC solution to existing designs requiring multiple devices

•Data and clock recovery for 125 MBaud FDDI or Fast Ethernet applications

•Clock multiplication from either a crystal, differential or single-ended timing source

•Continuous clock in the absence of data

•No external PLL components

•Lock/Loss status indicator output

•Loopback mode for system diagnostics

•Selectable loop timing mode

•PECL driver with settable sink current

•Parallel digital transmit and receive data interface

•NRZ to/from NRZI data conversion

•Consult ICS for optional configurations and data rates

Block Diagram

Pin Configuration

28-Pin SOIC

PHYceiver is a trademark of Integrated Circuit Systems, Inc.

ICS1887RevF112596

ICS1887

Pin Descriptions

	PIN	PIN NAME	TYPE	DESCRIPTION
	NUMBER
	1	VSS		Negative Supply Voltage
	2	TXOFF~2	TTL-Compatible	Transmitter Off*
	3	CD~	TTL-Compatible1	Carrier Detect input*
	4	TX+	PECL	Positive Transmit serial data output
	5	TX–	PECL	Negative Transmit serial data output
	6	VSS		Negative supply voltage
	7	IPRG1		PECL Output stage current set (TX)
	8	RX–	PECL	Negative Receive serial data input
	9	RX+	PECL	Positive Receive serial data input
	10	LB~	TTL-Compatible	Loop Back mode select*
	11	LOCK	TTL-Compatible	Lock detect output
	12	RD4	TTL-Compatible	Recovered data output 4
	13	RD3	TTL-Compatible	Recovered data output 3
	14	VSS		Negative supply voltage
	15	RD2	TTL-Compatible	Recovered data output 2
	16	RD1	TTL-Compatible	Recovered data output 1
	17	RD0	TTL-Compatible	Recovered data output 0
	18	RCLK	TTL-Compatible	Recovered Receive clock output
	19	VDD		Positive supply voltage
	20	REF_IN		Positive reference clock/crystal input
	21	REF_OUT		Negative reference clock/crystal output
	22	VDD		Positive supply voltage
	23	TCLK	TTL-Compatible	Transmit clock output
	24	TD0	TTL-Compatible	Transmit data input 0
	25	TD1	TTL-Compatible	Transmit data input 1
	26	TD2	TTL-Compatible	Transmit data input 2
	27	TD3	TTL-Compatible	Transmit data input 3
	28	TD4	TTL-Compatible	Transmit data input 4

* Active Low Input.

Note:

1.A running production change will be made to this input in the June 1996 time frame to convert this input from the TTL-compatible to PECL to more closely match applications requirements. See Substituting the ICS1887 for the AMD PDR & PDT applications note for more information.

2.This pin was formerly used for Loop-Timed operation. If your design did not use loop timing, this change does not affect you. If your application requires loop timing, please contact ICS.

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ICS1887

Input Pin Descriptions

Parallel Transmit Data (TD0 .. TD4)

Five bit TTL compatible digital input, which is received by the ICS1887 on the positive edge of TCLK. High impedance input drivers routed to the serial NRZ to NRZI converter. In loopback testing mode, this NRZI data is multiplexed to the input of the device clock recovery section.

Differential ECL Receive Data Input (RX+ & RX-)

The clock recovery and data regenerator from the receive buffer are driven from this PECL input. During loopback testing mode this input is ignored.

Carrier Detect (CD~)

Active low input which forces the VCO to free run. Upon receipt of a loss of input signal (such as from an optical-to- electrical transducer), the internal phase-lock loop will free-run at the selected operating frequency. Also, when asserted, CD will set the lock output low.

Transmitter Off (TXOFF~)

Active low input which, when low, forces TX+ low and TX-high. When high, data passes through TX+ and TXunaffected. This input has an internal pull-up resistor.

Loopback Mode (LB~)

Active low input which causes the clock recovery PLL to operate using the transmit input data reference and ignore the receive RX± data. Utilized for system loopback testing.

External Crystal or Reference Clock (REF_IN and REF_OUT)

This oscillator input can be driven from either a fundamental mode crystal or a stable reference. For either method, the reference frequency is 25.00 MHz.

Output Pin Descriptions

Differential ECL Transmit Data (TX+ and TX-)

This differential output is converted TD[0..4] serial data. This output remains active during loopback mode.

Transmit Clock (TCLK)

TTL compatible 25 MHz clock used by the parallel processor transmitter for clocking out transmit data. This clock can be derived from either an independent clock source or from the recovered data clock (system loop time mode).

Parallel Receive Data (RD0 .. RD4)

The regenerated five bit parallel data derived from the serial data input. In loopback mode this data is regenerated from the transmit data. This data is phase-aligned with the negative edge of RCLK clock output.

Receive Clock (RCLK)

A 25 MHz digital clock recovered with the internal clock recovery PLL. In loopback mode this clock is recovered from the transmit data.

Lock/Loss Detect (LOCK)

Set high when the clock recovery PLL has locked onto the incoming data. Set low when there is no incoming data, which in turn causes the PLL to free-run. This signal can be used to indicate or ‘alarm’ the next receive stage that the incoming serial data has stopped.

Output Description

The differential driver for the TX± is current mode and is designed to drive resistive terminations in a complementary fashion. The output is current-sinking only, with the amount of sink current programmable via the IPRG1 pin. The sink current is equal to four times the IPRG1 current. For most applications, an 910Ω resistor from VDD to IPRG1 will set the current to the necessary precision.

The TX± pins are incapable of sourcing current, so VOH must be set by the ratios of the Thevenin termination resistors for each of these lines. R1 is a pull-up resistor connected from the PECL output to VDD. R2 is a pull-down resistor connected from the PECL output to VSS. R1 and R2 are electrically in parallel from an AC standpoint. If we pick a target impedance of 50Ω for our transmission line impedance, a value of 62Ω for R1 and a value of 300Ω for R2 would yield a Thevinin equivalent characteristic impedance of 50Ω and a VOH value of VDD -.88 volts, compatible with PECL circuits.

To set a value for VOL, we must determine a value for Iprg that will cause the output FET’s to sink an appropriate current. We desire VOL to be VDD -1.81 or greater. Setting up a sink current of 19 milliamperes would guarantee this through our output terminating resistors. As this is controlled by a 4/1 current mirror, 4.75 mA into Iprg should set this current properly. An 910Ω resistor from VDD to Iprg should work fine.

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ICS1887

ICS1887 System Diagram

(PECL Termination for 50Ω Transmission Lines)

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ICS1887

Substituting the ICS1887 for the AMD PDR & PDT

This note describes the issues involved in replacing the AMD PDR & PDT with the

ICS1887.

There are a number of implementation differences between AMD’s PDR & PDT and the ICS1887. This note describes the differences and how they affect an application.

Signal Detect

Many twisted pair and fiber optic transceivers provide a signal detect indication that becomes active when the amount of energy being received reaches a threshold that makes it appear to be data and not ambient noise.

The AMD PDR device has a single ended PECL input (SDI) and provides a TTL level output (SDO) that tracks the input. The input controls the source that the PLL locks to. When signal detect is asserted, the PLL locks to the incoming receive data. When signal detect is deasserted, the PLL locks to the LSCLK input to prevent locking to an off center frequency.

CD PECL Input: Board Layout Options

Option 1

Differential PECL to CMOS Conversion Circuit

The current ICS1887 device provides a single	Option 2
TTL-compatible input, carrier detect (CD~).	Single-Ended PECL to CMOS Conversion Circuit
When carrier detect is asserted, the ICS1887
locks to the incoming receive data. When car-
rier detect is deasserted, or if carrier detect is
asserted and no data is present on the receive
inputs, the PLL will free run and continue to
provide RXCLK at the nominal 25 MHz
frequency. This allows the carrier detect input
to always be tied to an asserted level (ground).
If a true signal detect is required by a chip that
connects to the ICS1887, a simple, low cost
PECL to CMOS converter can be used. The
following circuit implements this function:
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