ICST ICS1523M Datasheet

Integrated

Circuit ICS1523

Systems, Inc.

High-Performance Programmable Line-Locked Clock Generator

General Description

The ICS1523 is a low-cost but very high-performance frequency generator for line-locked and genlocked highresolution video applications. Using ICS’s advanced low-voltage CMOS mixed-mode technology, the ICS1523 is an effective clock solution for video projectors and displays at resolutions from VGA to beyond UXGA.

The ICS1523 offers pixel clock outputs in both differential (to 250 MHz) and single-ended (to 150 MHz) formats. Dynamic Phase Adjust™ circuitry allows user control of the pixel clock phase relative to the recovered sync signal. A second differential output at half the pixel clock rate enables deMUXing of multiplexed analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC.

The advanced PLL uses either its internal programmable feedback divider or an external divider. The device is programmed by a standard I2C-bus™ serial interface and is available in a 24-pin wide small-outline integrated circuit (SOIC) package.

Features

•Pixel clock frequencies up to 250 MHz

•Very low jitter

•Dynamic Phase Adjust (DPA) for clock outputs

•Balanced PECL differential outputs

•Single-ended SSTL_3 clock outputs

•Double-buffered PLL/DPA control registers

•Independent software reset for PLL/DPA

•External or internal loop filter selection

•Uses 3.3Vdc. Inputs are 5V-tolerant.

•I2C-bus™ serial interface can run at either low speed (100 kHz) or high speed (400 kHz).

•Lock detection

•24-pin 300-mil SOIC package

Applications

•LCD monitors and video projectors

•Genlocking multiple video subsystems

•Frequency synthesis

Block Diagram

Pin Configuration

24-Pin SOIC

I2C-bus is a trademark of Philips Corporation.

Dynamic Phase Adjust is a trademark of Integrated Circuit Systems, Inc.

ICS1523 Rev S 5/21/99

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.

ICS1523

Document Revision History

Rev P (First Release)

Pin Descriptions changed to add type column. (pg 3) Added SDA and AC Input Characteristics. (pg 18)

Changed VCO Output, Intrinsic Jitter graph to show slow and fast cases (pg 19)

Timing diagram changes to reference t0 to REF and notes on test conditions added (pg 22) Lock Renamed Lock/Ref (Throughout).

General cleanup for readability.

RevQ

Added typical external loop filter values. (pg 17)

Added section on power supply considerations and SSTL_3 outputs. (pg 18)

Correct labels and scale on VCO Output, Intrinsic Jitter graph. (pg 20)

Correct depiction of timing diagram and added typical transition timing. (pg 23)

Added Document Revision History. (pg 25)

RevR

Change to descriptions for pins 20 to 23. (pg 3)

Change to description for Reg 0h bits 0 and 1, added table. (pg 6) Within table for Reg 0h bits 6 and 7, changed Osc_En to IN_SEL . (pg 6) Moved Reg 0 bits 4 through 7 from pg 6 to new pg 7.

Change to Software Programming Flow diagram. (pg 13).

Added under Absolute Maximum Ratings ESD ratings and warning. (pg 19)

Under Recommend Operating Conditions, PECL Outputs, Output Low Voltage, added a note and added a new page. (pg 19) Under Recommend Operating Conditions, SSTL-3 Outputs, Output Low Voltage, changed direction of symbols. (pg 19) Change to VCO Output Frequency and Intrinsic Jitter graph to reflect correct VCO frequency (pg 20)

Rev S

Moved Revision History from last page of data sheet to second page. (pg 2)

In Layout Guideline 2, changed shunt capacitor value from 150 pF to 33 pF. (pg 19)

Changed various cross-references within Layout Guidelines. (pg 19)

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ICS1523

Overview

The ICS1523 addresses stringent graphics system line-locked and genlocked applications and provides the clock signals required by high-performance video analog-to-digital converters. Included are a phase-locked loop (PLL) with a 500-MHz voltage controlled oscillator (VCO), a Dynamic Phase Adjust to provide a user-programmed pixel clock delay, the means for deMUXing multiplexed ADCs, and both balanced-program- mable (PECL) and single-ended (SSTL_3) high-speed clock outputs.

Phase-Locked Loop

The phase-locked loop is optimized for line-locked applications, for which the inputs are horizontal sync signals. A high-performance Schmitt trigger preconditions the HSYNC input, whose pulses can be degraded if they are from a remote source. This preconditioned HSYNC signal is provided as a clean reference signal with a short transition time. (In contrast, the signal that a typical PC graphics card provides has a transition time of tens of nanoseconds.)

A second high-frequency input such as a crystal oscillator and a 7-bit programmable divider can be selected. This selection allows the loop to operate from a local source and is also useful for evaluating intrinsic jitter.

A 12-bit programmable feedback divider completes the loop. Designers can substitute an external divider.

Either the conditioned HSYNC input or the loop output (recovered HSYNC) is available at the FUNC pin, aligned to the edge of the pixel clock.

Automatic Power-On Reset Detection

The ICS1523 has automatic power-on reset detection circuitry and it resets itself if the supply voltage drops below threshold values. No external connection to a reset signal is required.

Dynamic Phase Adjust™

The Dynamic Phase Adjust™ allows addition of a programmable delay to the pixel clock output, relative to the recovered HSYNC signal. The ability to add delays is particularly useful when multiple video sources must be synchronized. A delay of up to one pixel clock period is selectable in the following increments:

•1/64 period for pixel clock rates to 40 MHz

•1/32 period for pixel clock rates to 80 MHz

•1/16 period for pixel clock rates to 160 MHz

Output Drivers and Logic Inputs

The ICS1523 utilizes low-voltage TTL (LVTTL) inputs as well as SSTL_3 (EIA/JESD8-8) and low-voltage PECL (pseudoECL) outputs, operating at 3.3-V supply voltage. The LVTTL inputs are 5 V-tolerant. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated unterminated.

I2C-bus™ Serial Interface

The ICS1523 utilizes the industry-standard I2C-bus™ serial interface. The interface uses 12 registers: one write-only, eight read/write, and three read-only. Two ICS1523 devices can be addressed, according to the state of the I2CADR pin. When the pin is low, the read address is 4Dh, and the write address is 4Ch. When the pin is high, the read address is 4Fh, and the write address is 4Eh. The I2C-bus serial interface can run at either low speed (100 kHz) or high speed (400 kHz) and provides 5V-tolerant input.

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ICS1523

Pin Descriptions

	PIN NO.	PIN NAME	TYPE	DESCRIPTION	COMMENTS
	1	VDDD	PWR	Digital supply	3.3V to digital sections
	2	VSSD	PWR	Digital ground
	3	SDA	IN/OUT	Serial data	I2 C-bus1
	4	SCL	IN	Serial clock	I2 C-bus1
	5	PDEN	IN	PFD enable	Suspends charge pump1
	6	EXTFB	IN	External feedback in	External divider input to PFD1
	7	HSYNC	IN	Horizontal sync	Clock input to PLL1
	8	EXTFIL	IN	External filter	External PLL loop filter
	9	XFILRET	IN	External filter return	External PLL loop filter return
	10	VDDA	PWR	Analog supply	3.3V for analog circuitry
	11	VSSA	PWR	Analog ground	Ground for analog circuitry
	12	OSC	IN	Oscillator	Input from crystal oscillator package1 , 2
					Chip I2 C address select
	13	I2 CADR	IN	I2 C address	Low = 4Dh read, 4Ch write
					High = 4Fh read, 4Eh write
	14	LOCK/REF	OUT	Lock indicator/reference	Displays PLL or DPA lock or REF input
		(SSTL)
	15	FUNC (SSTL)	OUT	Function output	SSTL_3 selectable HSYNC output
	16	CLK/2 (SSTL)	OUT	Pixel clock/2 out	SSTL_3 driver to ADC deMUX input
	17	CLK (SSTL)	OUT	Pixel clock out	SSTL_3 driver to ADC
	18	VDDQ	PWR	Output driver supply	3.3V to output drivers
	19	VSSQ	PWR	Output driver ground	Ground for output drivers
	20	CLK– (PECL)	OUT	Pixel clock out	Inverted PECL driver to ADC. Open drain.
	21	CLK+ (PECL)	OUT	Pixel clock out	PECL driver to ADC. Open drain.
	22	CLK/2– (PECL)	OUT	Pixel clock/2 out	Inverted PECL driver to ADC deMUX input.
					Open drain.
	23	CLK/2+ (PECL)	OUT	Pixel clock/2 out	PECL driver to ADC deMUX input. Open drain.
	24	IREF	IN	Reference current	Reference current for PECL outputs

Notes:

1.These LVTTL inputs are 5V-tolerant.

2.Connect to ground if unused.

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ICS1523

Block Diagram

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ICS1523

I2C Register Map Summary

	Register	Name	Access	Bit Name	Bit #	Reset	Description
	Index					Value
	0h	Input Control	R / W	PDen	0	1	Phase Detector Enable (0=External Enable, 1=Always Enabled)
				PD_Pol	1	0	Phase Detector Enable Polarity (0=Not Inverted, 1=Inverted)
				Ref_Pol	2	0	External Reference Polarity (0=Positive Edge, 1=Negative Edge)
				Fbk_Pol	3	0	External Feedback Polarity (0=Positive Edge, 1=Negative Edge)
				Fbk_Sel	4	0	External Feedback Select (0=Internal Feedback, 1=External)
				Func_Sel	5	0	Function Out Select (0=Recovered HSYNC, 1=Input HSYNC)
				EnPLS	6	1	Enable PLL Lock/Ref Status Output (0=Disable 1=Enable)
				EnDLS	7	0	Enable DPA Lock/Ref Status Output (0=Disable 1=Enable)
	1h	Loop Control	R / W *	PFD0-2	0-2	0	Phase Detector Gain
				Reserved	3	0	Reserved
				PSD0-1	4-5	0	Post-Scaler Divider (0 = ÷2, 1 = ÷4, 2 = ÷8, 3 = ÷16)
				Reserved	6-7	0	Reserved
	2h	FdBk Div 0	R / W *	FBD0-7	0-7	FF	PLL FeedBack Divider LSBs (bits 0-7) *
	3h	FdBk Div 1	R / W *	FBD8-11	0-3	F	PLL Feedback Divider MSBs (bits 8-11) *
				Reserved	4-7	0	Reserved
	4h	DPA Offset	R / W	DPA_OS0-5	0-5	0	Dynamic Phase Aligner Offset
				Reserved	6	0	Reserved
				Fil_Sel	7	0	Loop Filter Select (0=External, 1=Internal)
	5h	DPA Control	R / W **	DPA_Res0-1	0-1	3	DPA Resolution (0=16 delay elements, 1=32, 2=Reserved, 3=64)
				Metal_Rev	2-7	0	Metal Mask Revision Number
	6h	Output Enables	R / W	OE_Pck	0	0	Output Enable for PECL PCLK Outputs ( 0=High Z, 1=Enabled)
				OE_Tck	1	0	Output Enable for STTL_3 CLK Output ( 0=High Z, 1=Enabled)
				OE_P2	2	0	Output Enable for PECL CLK/2 Outputs ( 0=High Z, 1=Enabled)
				OE_T2	3	0	Output Enable for STTL_3 CLK/2 Output ( 0=High Z, 1=Enabled)
				OE_F	4	0	Output Enable for STTL_3 FUNC Output ( 0=High Z, 1=Enabled)
				Ck2_Inv	5	0	CLK/2 Invert (0=Not Inverted, 1= Inverted)
				Out_Scl	6-7	0	SSTL Clock Scaler (0 = ÷1, 1 = ÷2, 2 = ÷4, 3 = ÷8)
	7h	Osc_Div	R / W	Osc_Div 0-6	0-6	0	Osc Divider modulus
				In-Sel	7	1	Input Select (0=HSYNC Input, 1=Osc Divider)
	8h	Reset	Write	DPA	0-3	x	Writing xAh resets DPA and loads working register 5
				PLL	4-7	x	Writing 5xh resets PLL and loads working registers 1-3
	10h	Chip Ver	Read	Chip Ver	0-7	17	Chip Version 23 Dec (17 Hex) as in 1523
	11h	Chip Rev	Read	Chip Rev	0-7	01	Initial value 01h. Value Increments with each all-layer change.
	12h	Rd_Reg	Read	DPA_Lock	0	N/A	DPA Lock Status (0=Unlocked, 1=Locked)
				PLL_Lock	1	N/A	PLL Lock Status (0=Unlocked, 1=Locked)
				Reserved	2-7	0	Reserved

*Identifies double-buffered registers. Working registers are loaded during software PLL reset.

**Identifies double-buffered register. Working registers are loaded during software DPA reset.

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ICS1523

Detailed Register Description

Name:		Input Control
Register:		0h
Index:		Read /Write
Bit Name		Bit #	Reset Value	Description
PDen		0	1	Phase/Frequency Detector Enable
PD_Pol		1	0	Phase/Frequency Detector Enable Polarity
Ref_Pol		2	0	Phase/Frequency Detector External Reference Polarity
Fbk_Pol		3	0	External Reference Feedback Polarity
Fbk_Sel		4	0	External Feedback Select
Func_Sel		5	0	Function Output Select
EnPLS		6	1	Enable PLL Lock Status Output on LOCK/REF pin
EnDLS		7	0	Enable DPA Lock Status Output on LOCK/REF pin
Bit	Name		Description
0	PDen		Phase/Frequency
						PDen	PD_Pol		Phase/Frequency Detector
			Detector Enable						Is Enabled When:
						0	0		PDEN= 1
1	PD_Pol		Phase/Frequency Detector			X	1		Always (Default)
						1	0		PDEN = 0
			Enable Polarity
2	Ref_Pol		Phase/Frequency Detector External Reference Polarity —
			Edge of input signal on which Phase Detector triggers.
			0 = Rising Edge (default)
			1 = Falling Edge
3	Fbk_Pol		External Reference Feedback Polarity — Edge of EXTFB (pin 6) signal on which
			Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1).

0 = Positive Edge (default)

1 = Negative Edge

Table continues on next ppage

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ICS1523

Name: Input Control

Register: 0h

Bit	Name	Description
4	Fbk_Sel	External Feedback Select
		0 = Internal Feedback (default)
		1 = External Feedback
5	Func_Sel	Function Output Select — Selects re-clocked output to FUNC (pin 15).
		0 = Recovered HSYNC (default). Re-generated HSYNC output.
		1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7).
6	EnPLS	Enable PLL Lock Status Output	EnPLS	EnDLS	IN_SEL	LOCK/REF(14)
		on LOCK/REF pin	0	0	N/A	0
			0	1	N/A	1 if DPA locked, 0 otherwise
7	EnDLS	Enable DPA Lock Status Output	1	0	N/A	1 if PLL locked, 0 otherwise
		on LOCK/REF pin	1	1	0	Post Schmitt trigger
						HSYNC(7) XOR Ref_Pol
		Bits 6,7 enable multiple functions	1	1	1	Fosc ¸ Osc_Div

at LOCK/REF, (pin 14)

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ICS1523

Name:	Loop Control Register
Register:	1h
Index:	Read /Write*

Bit Name	Bit #	Reset Value	Description
PFD0-2	0 - 2	0	Phase Frequency Detector Gain
Reserved	3	0	Reserved
PSD0-1	4 - 5	0	Post-Scaler Divider
Reserved	6-7	0	Reserved

Bit	Name	Description
0-2	PFD0-2	Phase/Frequency Detector Gain
			Bit 2	Bit 1	Bit 0	PFD Gain (µ A/2π rad)
			0	0	0	1
			0	0	1	2
			0	1	0	4
			0	1	1	8
			1	0	0	16
			1	0	1	32
			1	1	0	64
			1	1	1	128

3Reserved

4-5	PSD 0-1	Post-Scaler Divider — Divides the output of the VCO to the DPA and Feedback Divider.
			Bit 5	Bit 4	PSD Divider
			0	0	2 (default)
			0	1	4
			1	0	8
			1	1	16
6-7	Reserved

*Double-buffered register. Actual working registers are loaded during software PLL reset. See register 8h for details.

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