ICST ICS1522M Datasheet

ICST ICS1522M Datasheet





Systems, Inc.

User-ProgrammableVideo Clock Generator/ Line-Locked

Clock Regenerator

General Description

The ICS1522 is a very high performance monolithic phaselocked loop (PLL) frequency synthesizer. Utilizing ICS’s advanced CMOS mixed-mode technology, the ICS1522 provides a low-cost solution for high-end video clock generation where synchronization to an external video source is required.

The ICS1522 has differential video clock outputs (CLK+ and CLK-) that are compatible with industry standard video DAC.

Operating frequencies are fully programmable with direct control provided for reference divider, feedback divider and postscaler.


Serial programming: Feedback and reference divisors, VCO gain, phase comparator gain, relative phase and test modes.

Supports high-resolution graphics - Differential CLK out-puts to 230 MHz

Eliminates need for multiple ECL output voltage control-

led crystal oscillators and external components

Fully-programmable synthesizer capability - not just a clock multiplier

Line-locked clock generation capability; 15 - 100 kHz

External feedback loop capability allows graphics system to be used as the feedback divisor with

synchronous switchover to internal feedback

Small footprint 24-pin SOIC

Coarse and fine phase adjustment permits precise clocking in video recovery application


Block Diagram

LCD Projector Systems

Multimedia video line locking

Genlock applications



ICS reserves the right to make changes in the device data identified in this publication





without further notice. ICS advises its customers to obtain the latest version of all




device data to verify that any information being relied upon by the customer is current



and accurate.






The ICS1522 is ideally suited to provide the graphics system clock signals required by high-performance video DACs. Fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just simple multiples of the reference frequency. The ICS1522 uses the latest generation of frequency synthesis techniques developed by ICS and is completely suitable for the most demanding video applications.

PLL Synthesizer Description -

Ratiometric Mode

The ICS1522 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency pro-vided to the PLL (see Block Diagram). The reference frequency is generated by an on-chip crystal oscillator or the reference frequency may be applied to the ICS1522 from an external frequency source, typically horizontal sync from another dis-play system.

The phase-frequency detector shown in the Block Diagram drives the voltage-controlled oscillator, or VCO, to a frequency that will cause the two inputs to the phasefrequency detector to be matched in frequency and phase. This occurs when:

F(VCO): = F(XTAL1) . Feedback Divider

Reference Divider

This expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers).

The VCO gain is programmable, which permits the ICS1522 to be optimized for best performance at all operating frequencies.

The feedback divider may be programmed for any modulus from 64 to 2048 in steps of one followed by a divide by 1, 2, 4 or 8 feedback post-scaler.

The reference divider may be programmed for any modulus from 1 to 1024 in steps of one.

Output Post-scaler

A programmable post-scaler may be inserted between the VCO and the CLK+ and CLKoutputs of the ICS1522. This is useful in generating of lower frequencies, as the VCO has been optimized for high-frequency operation.

The post-scaler allows the selection of dividing the VCO frequency by either 1, 2, 4 or 8.

Load Clock Divider

The ICS1522 has an additional programmable divider (referred to in the Block Diagram as the load counter) that is used to generate the LOAD clock frequency for the video DAC. The modulus of this divider may be set to 3, 4, 5, 6, 8, or 10 under register control. The design of this divider permits the output duty factor to be 50/50, even when odd modulus is selected. The input frequency to this divider is the output of the output post-scaler described above.

Digital Inputs - ICS1522

The programming of the ICS1522 is performed serially by using the SDATA, SCLK, and SELn pins to load the 7, 11 bit internal memory locations.

Single bit changes are accomplished by addressing the appro-priate memory location and writing only 11 bits of data, not by writing all 77 data bits.

For proper programming of the ICS1522, it is important that all transitions of the SELn input occur during the same state of the SCLK input.

SDATA is shifted into a 15 bit serial register on the rising edge of SCLK while SELn is low. The first bit loaded is R/ Wn followed by a 3 bit address and 11 bit data (both address & data are LSB first). When a rising edge of SCLK occurs while SELn is high (SDATA ignored), the contents of the serial register are loaded into the addressed 11 bit memory location if R/Wn is low. If R/Wn is high upon the above condition, the data from the addressed memory location is loaded into the serial shift register and SDATA is set as an output. The 3 bit address and 11 bit data will be serially shifted out of the ICS1522 on the SDATA pin on the rising edge of SCLK while SELn is low (see Timing Diagram).

An additional control pin on the ICS1522, PDEN can be used to disable the phase-frequency detector in line-locked applica-tions. When disabled, the phase detector will ignore any inputs and allow the VCO to coast. This feature is useful in systems using composite sync.


24-Pin SOIC


Output Description

The differential output drivers, CLK+ and CLK-, are current-mode and are designed to drive resistive terminations in a complementary fashion. The outputs are currentsinking only, with the amount of sink current programmable via the IPRG pin. The sink current, which is steered to either CLK+ or CLK-, is four times the current supplied to the IPRG pin. For most applications, a resistor from VDDO to IPRG will set the current to the necessary precision.

Reference Oscillator and

Crystal Selection

The ICS1522 has circuitry on-board to implement a Pierce oscillator with the addition of a quartz crystal and two external loading capacitors (EXTREF bit must be set to logic 0). Pierce oscillators operate the crystal in anti- (also called parallel-) resonant mode.

Series-resonant crystals may also be used with the ICS1522. Be aware that the oscillation frequency will be slightly higher than the frequency that is stamped on the can (typically 0.025-0.05%).

As the entire operation of the phase-locked loop depends on having a stable reference frequency, we recommend that the crystal be mounted as closely as possible to the package. Avoid routing digital signals or the ICS1522 outputs underneath or near these traces. It is also desirable to ground the crystal can to the ground plane, if possible. If an external reference frequency source is to be used with the ICS1522, it is important that it be jitter-free. The rising and falling edges of that signal should be fast and free of noise for best results. The loop phase is locked to the rising edge of the XTAL1/EXTREF input signal, if REF_POL is set to logic 0. Additionally, the EXTREF bit should be set to logic 1 to switch in a TTL-compatible buffer at this input.

Line-Locked Operation

Some video applications require a clock to be generated that is a multiple of horizontal sync. The ICS1522 supports this mode of operation. The reference divider should be set to divide by one and the desired polarity (rising or falling) of lock edge should be selected. By using the phase detector hardware disable mode (PDEN), the PLL can be made to free-run at the beginning of the vertical interval of the external video, and can be reactivated at its completion.

External Feedback Operation

The ICS1522 option also supports the inclusion of an external counter as the feedback divider of the PLL. This mode is useful in graphic systems that must be “genlocked” to external video sources.

When the FBK_SEL bit is set to logic 0, the phasefrequency detector will use the EXTFBK pin as its feedback input. The loop phase will be locked to the rising edges of the signal applied to the EXTFBK input if FBK_POL is set to logic 0 Synchronous switchover to the internal feedback can be ac-complished by setting the FBK-SEL bit to logic 1 while an active feedback source exists on the EXTFBK pin.

Fine Phase Adjustment

The ICS1522 has the capability of adjusting the pixel clock phase relative to the input reference phase. Entire pixels can be added or removed under register control with sub-pixel adjust-ment accomplished by a control voltage on the FINE input pin. By utilizing the fine phase adjust, after first synchronously switching from external feedback to internal feedback, the graphics system phase can be precisely controlled relative to the input horizontal sync.



Power-On Initialization

The ICS1522 has an internal power-on reset circuit that sets the frequency of the CLK+and CLKoutputs to be half the crystal or reference frequency assuming that they are between 10 MHz and 25 MHz (refer to default settings in Register Definition). Because the power-on reset circuit is on the VDD supply, and because that supply is filtered, care must be taken to allow the reset to de-assert before programming. A safe guideline is to allow 20 microseconds after the VDD supply reaches four volts.

Board Test Support

It is often desirable to statically control the levels of the output pins for circuit board test. The ICS1522 supports this through a register programmable mode, AUXEN. When this mode is set, AUXCLK will directly control the logic levels of the CLK+ and CLKpins while OMUX1, OMUX2, OMUX3, and OMUX4 will control OUT1, OUT2, OUT3 and OUT4, respectively.

Power Supplies and Decoupling

The ICS1522 has three VSS pins to reduce the effects of package inductance. Both pins are connected to the same potential on the die (the ground bus). These pins should connect to the ground plane of the video board as close to the package as is possible.

The ICS1522 has a VDDO pin which is the supply of +5 volt power to all output drivers. This pin should be connected to the power plane (or bus) using standard high-frequency decoupling practice. That is, capacitors should have low series inductance and be mounted close to the ICS1522. The VDD pin is the power supply pin for the PLL synthesizer circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for this pin (as shown in the recommended application circuitry). This will allow the PLL to “track” through power supply fluctuations without visible effects.

Pin Discriptions



















Charge Pump output (External loop filter applications)













Serial Data Input/Output













Serial Clock Input













Serial Port enable (active Low)







Analog +5 Volt Supply







External Reference Input / Xtal Oscillator Input







Xtal Oscillator Output













Fine Phase Adjust Input

































Output 4













Output 3







Output Driver +5 Volt Supply







Output 2







Output 1


























Output Driver Current Programming Input







Differential CLK - Output













Differential CLK + Output













Digital +5 Volt Supply













Phase Detector Enable (Active High)













External Feedback Input






External VCO input













VCO Control Voltage Input (External loop filter applications)























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