ICST GSP82C404N, GSP82C404M, AV82C404N, AV82C404M, ICS82C404N, ICS82C404M Datasheet

Integrated

Circuit

Systems, Inc.

ICS82C404

Advance Information

Dual Programmable Graphics Frequency Generator

General Description

The ICS82C404 is a fully programmable graphics clock generator. It can generate user specified clock frequencies using an externally generated input reference or by a single crystal. The output frequency is programmed by entering a 24-bit digital word through the serial port.

Two fully user-programmable phase-locked loops are offered in a single package. One PLL is designed to drive the memory clock, while the second drives the video clock. The outputs may be changed on-the-fly to any desired frequency between 390 kHz and 120 MHz. The ICS82C404 is ideally suited for any design where multiple or varying frequencies are required.

This part is ideal for graphics applications. It generates low jitter, high speed pixel clocks. It can be used to replace multiple, expensive high speed crystal oscillators. The flexibility of the device allows it to generate non-standard graphics clocks.

The leader in the area of multiple clock output clocks on a single chip, ICS has been shipping graphics frequency generators since October, 1990, and is constantly improving the phase-locked loop. The ICS82C404 incorporates a patented fourth generation PLL that offers the best jitter performance available.

Features

∙Pin-for-pin and function compatible with ICD’s version of the 82C404

∙Dual programmable graphics clock generator

∙Memory and video clocks are individually programmable “on-the-fly”

∙Ideal for designs where multiple or varying frequencies are required

∙Increased frequency resolution from optional pre-divide- by-2 on the M counter

∙Output enable feature available for tristating outputs

∙Independent clock outputs range from 390 kHz to 120 MHz

∙Operation up to 140 MHz available

∙Power-down capabilities

∙Low-power, high speed 0.8μ CMOS technology

∙Glitch-free transitions

∙Available in 16-pin PDIP or SOIC package

Block Diagram

ICS82C404RevA111095

ICS82C404

Pin Configuration

	SEL0/CLK	1		16	PD
	SEL1/DATA	2	ICS82C404	15	EXTSEL
	VDD	3		14	INIT1
	OE	4		13	VDD
	GND	5		12	INIT0
	X1	6		11	EXTCLK
	X2	7		10
					FPMODE
	MCLK	8		9	VCLK

16-Pin PDIP or SOIC

Pin Descriptions

PIN NUMBER			PIN NAME		DESCRIPTION
1		SEL0-CLK			Clock input in serial programming mode.
					Clock select pin in operating mode.
2		SEL1-DATA			Data input in serial programming mode.
					Clock select pin in operating mode.
3		AVDD			Power.
4		OE			Tristates outputs when low.
5		GND			Ground.
6		X1			Crystal input.
7		X2			Crystal output.
8		MCLK			Memory clock output.
9		VCLK			Video clock output.
10					Clock select input used to force REG2 programmed frequency.
		FPMODE
11		EXTCLK			External clock input.
12		INIT0			Selects initial power-up conditions, LSB.
13		VDD			Power.
14		INIT1			Selects initial power-up conditions, MSB.
15		EXTSEL			Selects external clock input (EXTCLK) as VCLK output.
16					Power-down pin, active low.
		PD

2

ICS82C404

Register Definitions

The register file consists of the following six registers:

Register Addressing

Address	Register	Definition
000	REG0	Video Clock Register 1
001	REG1	Video Clock Register 2
010	REG2	Video Clock Register 3
011	MREG	Memory Register
100	PWRDWN	Divisor for Power-down mode
110	CNTL REG	Control Register

The ICS82C404 places the three video clock registers and the memory clock register in a known state upon power-up. The registers are initialized based on the state of the INIT1 and INIT0 pins at application of power to the device. The INIT pins must ramp up with VDD if a logical 1 on either pin is required. These input pins are internally pulled down and will default to a logical 0 if left unconnected.

The registers are initialized as follows:

Register Initialization

INIT1	INIT0	MREG	REG0	REG1	REG2
0	0	32.500	25.175	28.322	28.322
0	1	40.000	25.175	28.322	28.322
1	0	50.350	40.000	28.322	28.322
1	1	56.644	40.000	50.350	50.350

Register Selection

When the ICS82C404 is operating, the video clock output is controlled with a combination of the SEL0, SEL1, PD, and OE pins. The video clock is also multiplexed to an external clock (EXTCLK) which can be selected with the EXTSEL pin. The VCLK Selection Table shows how VCLK is selected.

VCLK Selection

OE	PD			EXTSEL	FPMODE	SEL1	SEL0	VCLK
0		x		x	x	x	x	Tristate
1	0			x	x	x	x	Forced High
1	1			x	1	0	0	REG0
1	1			x	1	0	1	REG1
1	1			0	1	1	0	EXTCLK
1	1			1	1	1	x	REG2
1	1			x	1	1	1	REG2
1	1			x	0	x	x	REG2

As seen in the table above, OE acts to tristate the output. The PD pin forces the VCLK signal high while powering down the part. The EXTCLK pin will only be multiplexed in when EXTSEL and SEL0 are logic 0 and SEL1 is a logic 1.

The memory clock outputs are controlled by PD and OE as follows:

MCLK Selection

OE	PD			MCLK
0		x		Tristate
1	1			MREG
1	0			PWRDWN

The Clock Select pins SEL0 and SEL1 have two purposes. In serial programming mode, these pins act as the clock and data pins. New data bits come in on SEL1 and these bits are clocked in by a signal on SEL0. While these pins are acquiring new information, the VCLK signal remains unchanged. When SEL0 and SEL1 are acting as register selects, a time-out interval is required to determine whether the user is selecting a new register or wants to program the part. During this initial time-out, the VCLK signal remains at its previous frequency. At the end of this time-out interval, a new register is selected. A second time-out interval is required to allow the VCO to settle to its new value. During this period of time, typically 5 ms, the input reference signal is multiplexed to the VCLK signal.

When MCLK or the active VCLK register is being reprogrammed, then the reference signal is multiplexed glitch-free to the output during the first time-out interval. A second timeout interval is also required to allow the VCO to settle. During this period, the reference signal is multiplexed to the appropriate output signal.

3

ICS82C404

Control Register Definition

The control register allows the user to adjust various internal options. The register is defined as follows:

	Bit	Bit Name	Default Value	Description
	9	C5	0	This bit determines which power-down mode the		pin will
					PD
				implement. Power-down mode 1, C5=0, forces the MCLK signal to
				be a function of the power-down register. Power-down mode 2,
				C5=1, turns off the crystal and disables all outputs.
	8	C4	0	This bit determines which clock is multiplexed to VCLK during
				frequency changes. C4=0 multiplexes the reference frequency to the
				VCLK output. C4=1 multiplexes MCLK to the VCLK output for
				applications where the graphics controller cannot run as slow as
	7	C3	0	fREF.
				This bit determines the length of the time-out interval. The time-out
				interval is derived from the MCLK VCO. If this VCO is
				programmed to certain extremes, the time-out interval maybe too
	6	C2	0	short. C3=0, normal time-out. C3=1, doubled time-out interval.
				Reserved, must be set to 0.
	5	C1	1
				This bit adjusts the duty cycle. C1=0 causes a 1ns decrease in
				output high time. C1=1 causes no adjustment. If the load
				capacitance is high, the adjustment can bring the duty cycle closer
	4	C0	0	to 50%.
	3	NS2	0	Reserved, must be set to 0.
				Acts on register 2. NS2=0 prescales the N counter by 2.
	2	NS1	0	NS2=1 prescales the P counter value to 4.
				Acts on register 1. NS1=0 prescales the N counter by 2.
	1	NS0	0	NS1=1 prescales the P counter value to 4.
				Acts on register 0. NS0=0 prescales the P counter by 2.
				NS0=1 prescales the P counter value to 4.

4