ICST GSP2694M, AV2694N, AV2694M, ICS2694M, ICS2694N Datasheet

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ICS2694

Integrated

Circuit

Systems, Inc.

Motherboard Clock Generator

Description

The ICS2694 Motherboard Clock Generator is an integrated circuit using PLL and VCO technology to generate virtually all the clock signals required in a PC. The use of the device can be generalized to satisfy the timing needs of most digital systems by reprogramming the VCO or reconfiguring the counter stages which derive the output frequencies from the VCO’s.

The primary VCO is customarily used to generate the CPU clock and is so labeled on the ICS2694. Pre-programmed frequency sets are listed on page 6. These choices were made to match the major microprocessor families. CPUSEL (0-3) allow the user to select the appropriate frequency for the application.

Due to the filter in the phase-locked loop, the CPUCLK will move in a linear fashion from one frequency to a newlyselected frequency without glitches. If a fixed CPUCLK value is desired, CPUSEL (0-3) may be hard wired to the desired address with STROBE tied high. (It has a pull-up.) For board test and debug, pulling OUTPUTE to Ground will tristate all the outputs.

Features

Low cost - eliminates multiple oscillators and Count Down Logic

Primary VCO has 16 Mask Programmable frequencies (normally CPU clock)

Secondary VCO has 1 Mask Programmable frequency (usually 96 MHz)

Pre-programmed versions for typical PC applications

10 Outputs in addition to the primary CPU clock

Capability to reconfigure counter stages to change the frequencies of the outputs via mask options

Advanced PLL design

On-chip PLL filters

Very Flexible Architecture

Applications

Pin Configuration

CPU clock and Co-processor clock

Hard Disk and Floppy Disk clock

Keyboard clock

OUT2

1

 

 

Serial Port clock

 

OUT1

2

 

Bus clock

 

OUT0

3

 

System counting or timing functions

OUT9

4

 

 

 

CPUCLK

5

ICS2694

 

 

VSS

6

 

 

 

 

 

DVDD

7

 

 

 

STROBE

8

 

 

 

CPUSEL0

9

 

 

 

CPUSEL1

10

 

 

 

CPUSEL2

11

 

 

 

CPUSEL3

12

 

24

OUT3

23

OUT4

22

OUT5

21

OUT6

20

OUT7 (CPUCLK/2)

19

OUT8

18

AVDD

17

XTAL2

16

XTAL1

15

AVSS

14

OUTPUTE

13

CLKIN

24-Pin DIP or SOIC

ICS2694RevA1094

ICS2694

Pin Description

PIN NUMBER

NAME

DESCRIPTION

1

OUT2

4mA Output.

2

OUT1

4mA Output.

3

OUT0

4mA Output

4

OUT9

4mA Output.

5

CPUCLK

4mA Output driven by Voltage Controlled Oscillator 1 (VC01). VC01 is controlled

 

 

by a 16 word ROM.

6

VSS

Ground for digital portion of chip.

7

DVDD

Plus supply for digital portion of chip.

8

STROBE

Input control for transparent latches associated with CPU (0-3) which select one of

 

 

16 values for CPUCLK. Holding STROBE high causes the latches to be transparent.

9

CPUSEL0

LSB CPUCLK address bit.

10

CPUSEL1

CPUCLK address bit.

11

CPUSEL2

CPUCLK address bit.

12

CPUSEL3

MSB CPUCLK address bit.

13

CLKIN

An alternative input for the reference clock. The crystal oscillator output and CLKIN

 

 

are gated together to generate the reference clock for the VCO’s. If CLKIN is used,

 

 

XTAL1 should be held high and XTAL2 left open. If the internal oscillator is used,

 

 

hold CLKIN high.

14

OUTPUTE

Pulling this line low tristates all outputs.

15

AVSS

Ground for analog portion of chip.

16

XTAL1

Input of internal crystal oscillator stage.

17

XTAL2

Output of internal crystal oscillator stage. This pin should have nothing connected

 

 

to it but one of the quartz crystal terminals.

18

AVDD

Positive supply for analog portion of chip.

19

OUT8

4mA Output.

20

OUT7

4mA Output. (Usually assigned as CPUCLK/2 for co-processor use.)

21

OUT6

4mA Output.

22

OUT5

4mA Output.

23

OUT4

4mA Output.

24

OUT3

4mA Output.

 

 

 

2

ICST GSP2694M, AV2694N, AV2694M, ICS2694M, ICS2694N Datasheet

ICS2694

Frequency Reference

The internal reference oscillator contains all of the passive components required. An appropriate series-resonant crystal should be connected between XTAL1 (1) and XTAL2 (2). In IBM-compatible applications, this will typically be a 14.31818 MHz crystal, but fundamental mode crystals between 10 MHz and 25 MHz have been tested. Maintain short lead lengths between the crystal and the ICS2694. In order to optimize the quality of the quartz crystal oscillator, the input switching threshold of XTAL1 is VDD/2 rather than the conventional 1.4V of TTL. Therefore, XTAL1 may not respond properly to a legal TTL signal since TTL is not required to exceed VDD/2. Therefore, another clock input CLKIN (pin 13) has been added to the chip which is sized to have an input switching point of 1.4V. Inside the chip, these two inputs are ANDED. Therefore, when using the XTAL1 and XTAL2, CLKIN should be held high. (It has a pull-up.) When using CLKIN, XTAL1 should be held high. (It does not have a pull-up because a pull-up would interfere with the oscillator bias.)

It is anticipated that some applications will use both clock inputs, properly gated, for either board test or unique system functions. By generating all the system clocks from one reference input, the phase and delay relationships between the various outputs will remain relatively fixed, thereby eliminating problems arising from totally unsynchronized clocks interacting in a system.

Power Supply Conditioning

The ICS2694 is a member of the second generation of dot clock products. By incorporating the loop filter on chip and upgrading the VCO, the ease of application has been substantially improved over earlier products. If a stable and noise-free power supply is available, no external components are required. However, in some applications it may be judicious to decouple the power supply as shown in Figures 1 or 2. Figure 1 is the normal configuration for 5 volt only applications. Which of the two provides superior performance depends on the noise content of the power supplies. In general, the configuration of Figure 1 is satisfactory. Figure 2 is the more conventional if a 12 volt analog supply is available, although the improved performance comes at a cost of an extra component; however, the cost of the discretes used in Figure 1’s are less than the cost of Figure 1’s discrete components.

Since the ICS2694 outputs a large number of high-frequency clocks, conservative design practices are recommended. Care should be exercised in the board layout of supply and ground traces, and adequate power supply decoupling capacitors consistent with the application should be used.

+5

 

 

C1

 

+50

 

 

C1

 

 

 

 

DVDD

 

 

 

DVDD

 

 

 

.µ1F

 

 

 

.µ1F

 

 

 

 

 

 

 

 

+5

33

 

 

AVDD

+120

470

 

 

AVDD

R1

C2

C3

R1

D1

C2

 

 

 

 

 

 

22µV

.µ1F

VSS, AVSS

 

 

4.7V

.µ1F

VSS, AVSS

 

 

 

 

 

 

Figure 1

Figure 2

3

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