ICST ICS1572M-101, ICS1572M-301 Datasheet

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ICST ICS1572M-101, ICS1572M-301 Datasheet

ICS1572

Integrated

Circuit

Systems, Inc.

User Programmable Differential Output Graphics Clock Generator

Description

The ICS1572 is a high performance monolithic phase-locked loop (PLL) frequency synthesizer. Utilizing ICS’s advanced CMOS mixed-mode technology, the ICS1572 provides a low cost solution for high-end video clock generation in workstations and high-end PC applications.

The ICS1572 has differential video clock outputs (CLK+ and CLK-) that are compatible with industry standard video DACs. Another clock output, LOAD, is provided whose frequency is derived from the main clock by a programmable divider. An additional clock output is available, LD/N2, which is derived from the LOAD frequency and whose modulus may also be programmed.

Operating frequencies are fully programmable with direct control provided for reference divider, pre-scaler, feedback divider and post-scaler.

Reset of the pipeline delay on Brooktree RAMDACs may be performed under register control. Outputs may also be set to desired states to facilitate circuit board testing.

Features

Supports high-resolution graphics - CLK output to 180 MHz

Eliminates need for multiple ECL output crystal oscillators

Fully programmable synthesizer capability - not just a clock multiplier

Available in 20-pin 300-mil wide body SOIC package

Available in both parallel (101) and serial (301) programming versions

Circuit included for reset of Brooktree RAMDAC pipeline delay

Applications

Workstations

AutoCad Accelerators

High-end PC graphics systems

 

 

 

 

 

 

 

 

ICS1572-101 Pinout

 

 

 

 

 

 

 

 

 

N.C.

1

20

N.C.

 

 

 

 

 

LOOP

 

 

AD0

2

19

AD1

 

 

 

 

 

FILTER

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL1

 

 

 

 

 

 

 

XTAL1

3

18

AD2

XTAL2

CRYSTAL

/ R

PHASE-

CHARGE

 

VCO

 

XTAL2

4

17

VDD

OSCILLATOR

 

FREQUENCY

PUMP

 

 

 

 

 

 

 

 

 

 

 

STROBE

5

16

VDD

 

 

 

DETECTOR

 

 

 

 

EXTFBK

 

 

 

 

 

 

 

VSS

6

15

VDDO

 

 

 

 

PRESCALER

 

VSS

7

14

IPRG

BLANK

(-301 only)

 

 

 

 

 

 

 

 

 

 

 

 

 

MUX

/ M

/ A

 

 

LOAD

8

13

CLK+

 

 

 

 

LD/N2

9

12

CLK-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PROGRAMMING

 

 

 

FEEDBACK DIVIDER

 

N.C.

10

11

N.C.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTERFACE

 

 

 

 

 

 

 

 

 

 

 

 

 

MUX

 

 

 

 

 

ICS1572-301 Pinout

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

/ 2

 

 

DIFF.

CLK+

N.C.

1

20

N.C.

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

CLK

AD0

2

19

AD1

 

 

 

/ 4

 

 

 

 

 

 

 

 

 

 

XTAL1

3

18

AD2

 

 

 

 

 

 

 

 

 

 

 

 

/ N1

 

 

 

XTAL2

4

17

VDD

 

 

 

 

 

MUX

DRIVER

LOAD

STROBE

5

16

VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

6

15

VDDO

 

 

 

 

 

 

 

 

VSS

7

14

IPRG

 

 

 

 

 

/ N2

DRIVER

LD/N2

LOAD

8

13

CLK+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LD/N2

9

12

CLK-

 

 

 

 

 

 

 

 

N.C.

10

11

N.C.

Figure 1

ICS1572RevC093094

RAMDAC is a trademark of Brooktree Corporation.

 

ICS1572

Overview

The ICS1572 is ideally suited to provide the graphics system clock signals required by high-performance video DACs. Fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just simple multiples of the reference frequency. The ICS1572 uses the latest generation of frequency synthesis techniques developed by ICS and is completely suitable for the most demanding video applications.

PLL Synthesizer Description -

Ratiometric Mode

The ICS1572 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency provided to the PLL (see Figure 1). The reference frequency is generated by an on-chip crystal oscillator or the reference frequency may be applied to the ICS1572 from an external frequency source.

The phase-frequency detector shown in the block diagram drives the voltage-controlled oscillator, or VCO, to a frequency that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. This occurs when:

F(VCO): = F(XTAL1) . Feedback Divider

Reference Divider

This expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers).

The VCO gain is programmable, which permits the ICS1572 to be optimized for best performance at all operating frequencies.

The reference divider may be programmed for any modulus from 1 to 128 in steps of one.

The feedback divider may be programmed for any modulus from 37 through 391 in steps of one. Any even modulus from 392 through 782 can also be achieved by setting the “double” bit which doubles the feedback divider modulus. The feedback divider makes use of a dual-modulus prescaler technique that allows the programmable counters to operate at low speed without sacrificing resolution. This is an improvement over conventional fixed prescaler architectures that typically impose a factor-of-four penalty (or larger) in this respect.

Table 1 permits the derivation of “A” & “M” counter programming directly from desired modulus.

PLL Post-Scaler

A programmable post-scaler may be inserted between the VCO and the CLK+ and CLKoutputs of the ICS1572. This is useful in generating of lower frequencies, as the VCO has been optimized for high-frequency operation.

The post-scaler allows the selection of:

VCO frequency

VCO frequency divided by 2

VCO frequency divided by 4

Internal register bit (AUXCLK) value

Load Clock Divider

The ICS1572 has an additional programmable divider (referred to in Figure 1 as the N1 divider) that is used to generate the LOAD clock frequency for the video DAC. The modulus of this divider may be set to 3, 4, 5, 6, 8, or 10 under register control. The design of this divider permits the output duty factor to be 50/50, even when an odd modulus is selected. The input frequency to this divider is the output of the PLL post-scaler described above.

Digital Inputs - ICS1572-101 Option

The AD0-AD3 pins and the STROBE pin are used to load all control registers of the ICS1572 (-101 option). The AD0-AD3 and STROBE pins are each equipped with a pull-up and will be at a logic HIGH level when not connected. They may be driven with standard TTL or CMOS logic families.

The address of the register to be loaded is latched from the AD0-AD3 pins by a negative edge on the STROBE pin. The data for that register is latched from the AD0-AD3 pins by a positive edge on the STROBE pin. See Figure 2 for a timing diagram. After power-up, the ICS1572-101 requires 32 register writes for new programming to become effective. Since only 13 registers are used at present, the programming system can perform 19 “dummy” writes to address 13 or 14 to complete the sequence.

2

ICS1572

This allows the synthesizer to be completely programmed for the desired frequency before it is made active. Once the part has been “unlocked” by the 32 writes, programming becomes effective immediately.

ALL registers identified in the data sheet (0-9, 11, 12 & 15) MUST be written upon initial programming. The programming registers are not initialized upon power-up, but the latched outputs of those registers are. The latch is made transparent after 32 register writes. If any register has not been written, the state upon power-up (random) will become effective. Registers 13 & 14 physically do not exist. Register 10 does exist, but is reserved for future expansion. To insure compatibility with possible future modifications to the database, ICS recommends that all three unused locations be written with zero.

ICS1572-101 Register Loading

STROBE

 

 

5

 

 

 

 

 

 

1

2

3

4

AD0-AD3

ADDRESS VALID

DATA VALID

 

Figure 2

Digital Inputs - ICS1572-301 Option

The programming of the ICS1572-301 is performed serially by using the DATCLK, DATA, and HOLD~pins to load an internal shift register.

DATA is shifted into the register on the rising edge of DATCLK. The logic value on the HOLD~ pin is latched at the same time. When HOLD~ is low, the shift register may be loaded without disturbing the operation of the ICS1572. When high, the shift register outputs are transferred to the control registers, and the new programming information becomes active. Ordinarily, a high level should be placed on the HOLD~ pin when the last data bit is presented. See Figure 3 for the programming sequence.

ICS1572-301 Register Loading

8

DATCLK

6 7

DATA

DATA_1

DATA_2

DATA_56

HOLD

Figure 3

An additional control pin on the ICS1572-301, BLANK can perform either of two functions. It may be used to disable the phase-frequency detector in line-locked applications. Alternatively, the BLANK pin may be used as a synchronous enable for VRAM shift clock generation. See sections on Line-Locked Operations and VRAM shift clock generation for details.

Output Description

The differential output drivers, CLK+ and CLK, are currentmode and are designed to drive resistive terminations in a complementary fashion. The outputs are current-sinking only, with the amount of sink current programmable via the IPRG pin. The sink current, which is steered to either CLK+ or CLK-, is approximately four times the current supplied to the IPRG pin. For most applications, a resistor from VDDO to IPRG will set the current to the necessary precision. See Figure 6 for output characteristics.

The LOAD output is a high-current CMOS type drive whose frequency is controlled by a programmable divider that may be selected for a modulus of 3, 4, 5, 6, 8, or 10. It may also be suppressed under register control.

The LD/N2 output is high-current CMOS type drive whose frequency is derived from the LOAD output. The programmable modulus may range from 1 to 512 in steps of one.

Pipeline Delay Reset Function

The ICS1572 implements the clocking sequence required to reset the pipeline delay on Brooktree RAMDACs. This sequence can be generated by setting the appropriate register bit (DACRST) to a logic 1 and then resetting to logic 0.

When changing frequencies, it is advisable to allow 500 microseconds after the new frequency is selected to activate the reset function. The output frequency of the synthesizer should be stable enough at that point for the video DAC to correctly execute its reset sequence. See Figure 4 for a diagram of the pipeline delay reset sequence.

Pipeline Delay Reset Timing

STROBE

 

 

or

10

11

DATCLK

 

9

 

CLK+

 

 

 

TCLK

12

LOAD

 

 

Figure 4

3

ICS1572

Reference Oscillator and Crystal

Selection

The ICS1572 has circuitry on-board to implement a Pierce oscillator with the addition of only one external component, a quartz crystal. Pierce oscillators operate the crystal in anti- (also called parallel-) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when ordering crystals.

Series-resonant crystals may also be used with the ICS1572. Be aware that the oscillation frequency will be slightly higher than the frequency that is stamped on the can (typically 0.025- 0.05%).

As the entire operation of the phase-locked loop depends on having a stable reference frequency, we recommend that the crystal be mounted as closely as possible to the package. Avoid routing digital signals or the ICS1572 outputs underneath or near these traces. It is also desirable to ground the crystal can to the ground plane, if possible.

If an external reference frequency source is to be used with the ICS1572, it is important that it be jitter-free. The rising and falling edges of that signal should be fast and free of noise for best results.

The loop phase is locked to the falling edges of the XTAL1 input signals.

Line-Locked Operation

The ICS1572 supports line-locked clock applications by allowing the LOAD (N1) and N2 divider chains to act as the feedback divider for the PLL.

The N1 and N2 divider chains allow a much larger modulus to be achieved than the PLL’s own feedback divider. Additionally, the output of the N2 counter is accessible off-chip for performing horizontal reset of the graphics system, where necessary. This mode is set under register control (ALTLOOP bit). The reference divider (R counter) is set to divide by 1 in this mode, and the HSYNC signal of the external video will be supplied to the XTAL1 input. The output frequency of the synthesizer will then be:

F(CLK) : = F (XTAL1) . N1 . N2.

By using the phase-detector hardware disable mode, the PLL can be made to free-run at the beginning of the vertical interval of the external video, and can be reactivated at its completion.

ICS1572-101 The ICS1572-101 supports phase detector disable via a special control mode. When the PDRSTEN (phase detector reset enable) bit is set, a high level on AD3 will disable PLL locking.

ICS1572-301 The ICS1572-301 supports phase detector disable via the BLANK pin. When the PDRSTEN bit is set, a high level on the BLANK input will disable PLL locking.

External Feedback Operation

The ICS1572-301 option also supports the inclusion of an external counter as the feedback divider of the PLL. This mode is useful in graphic systems that must be “genlocked” to external video sources.

When the EXTFBEN bit is set to logic 1, the phase-frequency detector will use the EXTFBK pin as its feedback input. The loop phase will be locked to the rising edges of the signal applied to the EXTFBK input.

VRAM Shift Clock Generation

The ICS1572-301 option supports VRAM shift clock generation and interruption. By programming the N2 counter to divide by 1, the LD/N2 output becomes a duplicate of the LOAD output. When the SCEN bit is set, the LD/N2 output may be synchronously started and stopped via the blank pin. When BLANK is high, the LD/N2 will be free-running and in phase with LOAD. When BLANK is taken low, the LD/N2 output is stopped at a low level. See Figure 5 for a diagram of the sequence. Note that this use of the BLANK pin precludes its use for phase comparator disable (see Line-Locked Operation).

VRAM Shift Clock Control

BLANK

LOAD

LD/N2

Figure 5

4

ICS1572

Power-On Initialization

The ICS1572 has an internal power-on reset circuit that performs the following functions:

1)Sets the multiplexer to pass the reference frequency to the CLK+ and CLKoutputs.

2)Selects the modulus of the N1 divider (for the LOAD clock) to be four.

These functions should allow initialization of most graphics systems that cannot immediately provide for register programming upon system power-up.

Because the power-on reset circuit is on the VDD supply, and because that supply is filtered, care must be taken to allow the reset to de-assert before programming. A safe guideline is to allow 20 microseconds after the VDD supply reaches 4 volts.

Phase Detector Gain: For most graphics applications and divider ranges, set P[1,0] = 10 and set P[2] = 1. Under some circumstances, setting the P[2] bit “on” can reduce jitter. During 1572 operation at exact multiples of the crystal frequency, P[2] bit = 0 may provide the best jitter performance.

Board Test Support

It is often desirable to statically control the levels of the output pins for circuit board test. The ICS1572 supports this through a register programmable mode, AUXEN. When this mode is set, two register bits directly control the logic levels of the CLK+/CLKpins and the LOAD pin. This mode is activated when the S[0] and S[1] bits are both set to logic 1. See Register Mapping for details.

Programming Notes

VCO Frequency Range: Use the post-divider to keep the VCO frequency as high as possible within its operating range.

Divider Range: For best results in normal situations (i.e., pixel clock generation for hi-res displays), keep the reference divider modulus as short as possible (for a frequency at the output of the reference divider in the few hundred kHz to several MHz range). If you need to go to a lower phase comparator reference frequency (usually required for increased frequency accuracy), that is acceptable, but jitter performance will suffer somewhat.

VCO Gain Programming: Use the minimum gain which can reliably achieve the VCO frequency desired, as shown here:

VCO GAIN

MAX FREQUENCY

4

120 MHz

5

200 MHz

6

230 MHz

 

 

7

*

 

 

 

 

* SPECIAL APPLICATION. Contact factory for custom product above 230 MHz.

Power Supplies and Decoupling

The ICS1572 has two VSS pins to reduce the effects of package inductance. Both pins are connected to the same potential on the die (the ground bus). BOTH of these pins should connect to the ground plane of the video board as close to the package as is possible.

The ICS1572 has a VDDO pin which is the supply of +5 volt power to all output drivers. This pin should be connected to the power plane (or bus) using standard high-frequency decoupling practice. That is, capacitors should have low series inductance and be mounted close to the ICS1572.

The VDD pin is the power supply pin for the PLL synthesizer circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for this pin (as shown in the recommended application circuitry). This will allow the PLL to “track” through power supply fluctuations without visible effects. See Figure 7 for typical external circuitry.

Figure 6

5

ICS1572

ICS1572 Typical Interface

DATA BUS

SELECT

1

N.C.

N.C

20

 

+5V

2

AD0

AD1

19

 

 

 

3

XTAL1

AD2

18

+

 

4

XTAL2

AD3

17

 

 

 

5

STROBE

VDD

16

 

 

6

VSS

VDDO

15

120

120

7

VSS

IPRG

14

 

 

8

LOAD

CLK+

13

 

 

9

LD/N2

CLK-

12

 

 

10

N.C.

N.C.

11

 

 

 

 

 

 

 

TO

 

 

 

 

 

RAMDAC

 

 

 

 

390

390

Figure 3

6

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