ICST ICS1531Y-100, ICS1531Y-140, ICS1531Y-165 Datasheet

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Integrated Circuit Systems, Inc.

Document Type: Data Sheet

ICS1531

Document Stage: Preliminary Product Preview

Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

General Description

The ICS1531 is a high-performance, cost-effective, 3-channel, 8-bit analog-to-digital converter with an integrated line-locked clock generator. It is part of a family of chips intended for high-resolution video applications that use analog inputs, such as LCD monitors, LCD projectors, plasma displays, and projection TVs. Using ICS's low-voltage CMOS mixed-signal technology, the ICS1531 is an effective data-capture solution for resolutions from VGA to UXGA.

The ICS1531 offers analog-to-digital data conversion and synchronized pixel clock generation at speeds of 100, 140, or 165 MHz (or mega samples per second, MSPS). The Dynamic Phase Adjust (DPA) circuitry allows end-user control over the pixel clock phase, relative to the recovered sync signal and analog pixel data. Either the internal pixel clock can be used as a capture clock input to the analog-to-digital converters or an external clock input can be used. The ICS1531 provides either one or two 24-bit pixels per clock. An ADCSYNC output pin provides recovered HSYNC from the pixel clock phase-locked-loop (PLL) divider chain output, which can be used to synchronize display enable output.

A clamp signal can be generated internally or provided through the CLAMP pin. A high-bandwidth video amplifier with adjustable gain allows fine tuning of the analog signal. The advanced PLL uses an internal programmable feedback divider. Two additional, independent programmable PLLs, each with spread-spectrum functionality, support memory and panel clock requirements.

Features

3-channel 8-bit analog-to-digital conversion up to 165 MHz

Direct connection to analog input data (no external pre-amplifier circuit needed)

Video amplifier: 500-MHz analog bandwidth, software-adjustable gain

Dynamic Phase Adjust (DPA) for software-adjustable analog sample points

Software selectable: One pixel per clock (for 24-bit pixels) or two pixels per clock (for a total of 48 bits)

Internal clamp circuit. Very low jitter.

Low-voltage TTL clock outputs, synchronized with digital pixel data outputs

Independent software reset for PLLs and DPA

Double-buffered PLL and DPA control registers

Two additional PLLs with spread spectrum for memory and panel clock

External/internal loop-filter selection with software

Automatic Power-On Reset (POR) detection

Uses 3.3 VDC. Digital inputs are 5-V tolerant.

Industry-standard 2-wire serial bus interface speeds: low (100 kHz), high (400 kHz), or ultra (800 kHz)

Lock detection available in hardware and software

144-pin low-profile quad flat pack (LQFP) package

Applications

LCD displays, LCD projectors, plasma displays, and projection TVs

ICS1531

Functional

Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RA0-RA7

Red

 

 

 

 

CLAMP

 

 

 

 

 

 

 

 

 

ADC

 

 

 

 

 

RB0-RB7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GA0-GA7

G reen

 

 

 

 

CLAMP

 

 

 

 

 

 

 

ADC

 

 

 

 

 

GB0-GB7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BA0-BA7

Blue

 

 

 

 

CLAMP

 

 

 

 

 

 

 

ADC

 

 

 

 

 

BB0-BB7

VSYNC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADCR CLK

HSY NC

 

 

 

 

PLL

 

 

 

DPA

 

 

 

 

 

 

 

ADCSYNC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCL

 

 

 

Serial IF

 

POR

 

 

 

 

PLL

 

Spread Spectrum

 

 

 

 

MCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL In

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Crystal

 

 

 

 

 

 

PLL

 

Spread Spectrum

 

 

 

 

PNLCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL O ut

 

 

 

Oscillator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICS1531 Rev N 12/1/99

PRODUCT PREVIEW documents contain information on new products in

December, 1999

 

the sampling or preproduction phase of development. Characteristic data

 

 

and other specifications are subject to change without notice.

 

 

 

 

 

 

ICS1531 Data Sheet - Preliminary

Table of Contents

 

 

 

 

Table of Contents

Section

Title

Page

Chapter 1

Abbreviations and Acronyms...............................................................................................................

3

Chapter 2

Summary ...........................................................................................................................................

4

Chapter 3 Pin Diagram and Listings .....................................................................................................................

9

Chapter 4

Functional Blocks................................................................................................................................

19

Chapter 5

Application Overview ..........................................................................................................................

22

Chapter 6

Register Set .........................................................................................................................................

23

Chapter 7

Programming .......................................................................................................................................

54

Chapter 8 Layout and Power Considerations ....................................................................................................

58

Chapter 9

AC/DC Operating Conditions .............................................................................................................

61

Chapter 10

Timing Diagrams................................................................................................................................

63

Chapter 11 VCO Transfer Characteristic.............................................................................................................

70

Chapter 12

Package Dimensions.........................................................................................................................

71

Chapter 13

Ordering Information.........................................................................................................................

73

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

2

 

 

ICS1531 Data Sheet - Preliminary

Chapter 1 Abbreviations and Acronyms

 

 

 

 

Chapter 1 Abbreviations and Acronyms

Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet.

Table 1-1. Abbreviations and Acronyms

Abbreviation /

Interpretation

Acronym

 

 

 

ADC

analog-to-digital converter

 

 

ASIC

application-specific integrated circuit

 

 

BNC

Type of connector, named for (“Bayonet”) Paul Neill and Carl Concelman

 

 

CMOS

complimentary metal-oxide semiconductor

 

 

DAC

digital-to-analog converter

 

 

DPA

Dynamic Phase Adjust

 

 

EMI

electro-magnetic interference

 

 

FCC

(United States) Federal Communications Commission

 

 

IF

interface

 

 

LCD

liquid crystal display

 

 

LQFP

low-profile quad flat pack

 

 

LSB

least-significant bit

 

 

LVTTL

low-voltage digital transistor-transistor logic

 

 

Max.

maximum

 

 

Min.

minimum

 

 

MSB

most-significant bit

 

 

MSPS

mega samples per second

 

 

MUX

multiplexer

 

 

N/A

Not Applicable

 

 

PC

personal computer

 

 

PFD

phase/frequency detector

 

 

PLL

phase-locked loop

 

 

POR

power-on reset

 

 

Reg

register

 

 

RGB

red, green, blue

 

 

R/W

read/write

 

 

SXGA

super XGA

 

 

TTL

transistor-transistor logic

 

 

Typ.

typical

 

 

UXGA

ultra XGA

 

 

VCO

voltage-controlled oscillator

 

 

VESA

Video Electronics Standards Association

 

 

VGA

video graphics array

 

 

XGA

eXtended graphics array

 

 

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

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ICS1531 Data Sheet - Preliminary

Chapter 2 Summary

 

 

 

 

Chapter 2 Summary

2.1Overview

The ICS1531 addresses stringent display system line-locked applications by providing clock signals and digitized pixel data through internal high-performance analog-to-digital converters (ADCs). The ICS1531 is a complete solution for capturing analog red, green, and blue (RGB) signals from personal computers and workstations. It supports data capture for resolutions from VGA (640 × 480) to UXGA (1600 × 1200). The ICS1531 features are described in the following sections.

2.2Clamp, Video Amplifier, and Analog-to-Digital Circuits (Condition RGB Inputs)

For the following circuits, see Figure 4-3.

2.2.1Clamp Circuits (Adjust RGB Inputs to ADC Range)

To properly digitize incoming RGB analog signals, the ICS1531 must adjust the signals to the range of the ADC. This adjustment is done by clamping the signal, which both (1) establishes a bottom voltage limit and

(2) offsets the signal to align the black level of the incoming signal with the bottom voltage limit. Then the signal is amplified to adjust the top limit to the upper range of the ADC.

The ICS1531 incorporates an internal clamping circuit to generate a clamping signal. Optionally, the CLAMP pin can be used to input an externally generated clamp signal (Reg 30:2). In either case, the polarity of the signal to a clamp can be programmed (Reg 30:3). Typically, the clamp signal is generated by ADCSYNC (the recovered HSYNC timing pulse). The clamp signal is generated during a non-display region of time, when most PC display controllers output a black signal.

2.2.2Video Amplifier Circuits (Amplify RGB Inputs)

The ICS1531’s video amplifier circuit can directly accept analog RGB input signals from a PC display controller (that is, no external pre-amplifier is required). The video amplifier circuit has three independent 500-MHz video amplifiers for the RGB inputs. To adjust the top level of the signal, this video amplifier circuit can be programmed for a gain of 1.0, 1.2, 1.4, or 1.6 (Regs 31:1-0, 32:1-0, and 33:1-0). As a result, the video amplifier circuit can improve low-amplitude signals and adjust analog input signals for the optimum sampling range of the ADC circuit.

2.2.3Analog-to-Digital Circuits (Digitize RGB Inputs)

The ICS1531 has high-performance analog-to-digital converters (ADCs) to capture and digitize analog RGB data (Reg 30:7). Low-power CMOS technology is used to create 8-bit ADCs, which are calibrated to align the capture event between (1) the 3 analog input channels and (2) either 3 or 6 digital output channels. The ADC can provide (through Reg 30:6) one of the following:

Two 24-bit pixels aligned to a half-rate pixel clock (two-pixels-per-clock mode), which can be used for 48-bit interface panels and image-scaling chips

One 24-bit pixel aligned to a full-rate pixel clock (one-pixel-per-clock mode), which can be used for 24-bit-per-pixel applications

In addition, programmable digital-to-analog converters for the R, G, and B inputs fine-tune VRTR, VRTG, and VRTB, the individual R, G, and B maximum reference ‘top’ voltages (Regs 34-36).

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

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ICS1531 Data Sheet - Preliminary

Chapter 2 Summary

 

 

 

 

2.3Phase-Locked Loop (Generates Pixel Clock from Input HSYNC)

The ICS1531 uses a phase-locked loop (PLL) to generate its pixel clock output frequency. A PLL is a closed-loop feedback system that locks an output signal’s phase and frequency to that of a reference input signal’s phase and frequency. In the case of the ICS1531, when its PLL is locked it locks a pixel clock output to that of an HSYNC signal from input video.For a block diagram of the ICS1531 PLL, see Figure 4-1 and Figure 4-2.

2.3.1Phase/Frequency Detector (Compares Two Input Signals)

The first section of the PLL is the Phase/Frequency Detector (PFD). To use the PLL, first the PFD must be enabled either through hardware control (with a signal from the PDEN pin) or software control (Reg 00:1-0). Once the PFD is enabled, the PFD compares both the phase and frequency of the following two input signals.

PFD Input Signal 1: External HSYNC Signal or Internal Oscillator Signal

The first input to the PFD can be selected from either the external HSYNC signal or the ICS1531 internal crystal oscillator signal (Reg 00:5).

External HSYNC signal

Typically, one of the input signals to the PFD comes from the HSYNC of a PC display controller. This input HSYNC signal can have a transition time of tens of nanoseconds. Furthermore, if the input HSYNC signal is from a remote source, its pulses can degrade.

A high-performance Schmitt trigger (Reg 00:7-6) conditions the HSYNC pulse before it is input to the PFD. The polarity of this input pulse can be programmed (Reg 00:2). The result of this conditioning is REF, a clean reference clock signal that in comparison to the input HSYNC signal has a short transition time. [For more information on adjusting the HSYNC signal, see Section 2.6, “Dynamic Phase Adjust (Positions Pixel Clock on Sub-Pixel Basis)”.]

Internal crystal oscillator

Alternatively, one of the input signals to the PFD can be from the ICS1531 internal crystal oscillator (Regs 07:7-0 and 2C:6-4).

PFD Input Signal 2: Signal from Feedback Loop

The second input to the PFD comes from the output of the PLL feedback loop, which results from the processing that takes place with the charge pump, filter, voltage-controlled oscillator, post-scaler divider, and feedback divider. That is, the PLL output (the signal from the feedback loop) also appears as one of the two inputs to the PFD.

As a result of the comparison of the two input signals, the PFD processes the inputs so there is the proper ratio between them. Then the PFD uses the output to drive a charge pump.

2.3.2Charge Pump (Boosts Voltage Gain of Signal from PFD)

The charge pump, which is a current-source and current-sink pair, boosts the voltage gain of the signal from the PFD. This PFD signal gain is programmable over a 7-bit range up to 128 A (Reg 01:2-0).

2.3.3Loop Filter (Filters Output from Charge Pump)

The loop filter, which is a capacitance and resistance in series, acts as a low-bandpass filter for the frequency output from the charge pump. The ICS1531 can select between either an external loop filter, or more typically, an internal loop filter (Reg 08:0). The advantage of the internal filter is that it can be used for all Video Electronics Standards Association (VESA) timing modes, for ease in manufacturing.

Note: VESA establishes standard timing specifications for the personal-computer industry. Although many computer manufacturers require that display controllers adhere to the VESA timing specifications, there is no enforcement. As a result, not all display controllers conform precisely to the VESA timing specifications.

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

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ICS1531 Data Sheet - Preliminary

Chapter 2 Summary

 

 

 

 

2.3.4Voltage-Controlled Oscillator (Matches Input Signals to PFD)

The voltage level resulting from the output signals from the combined processing by the PFD, charge pump, and loop filter drives the voltage-controlled oscillator (VCO). The VCO uses the level of this input voltage to proportionally adjust its frequency output. This signal is compared to the input to the PFD so that both inputs to the PFD match in both phase and frequency. The VCO can operate up to nearly 600 MHz with a fixed gain. Consequently, the ICS1531 can be optimized for the best performance at all operating frequencies. (For more information on the VCO, see Chapter 11, “VCO Transfer Characteristics”.)

2.3.5Post-Scaler Divider (Sets Ratio of VCO and Pixel Clock Frequencies)

Using the frequency output from the VCO, the programmable Post-Scaler Divider (PSD) can set the ratio of VCO frequency-to-pixel clock frequency at 2:1, 4:1, 8:1, or 16:1 (Reg 01:5-4). The maximum pixel clock output frequency is therefore 300 MHz. However, for practical applications, the analog-to-digital converter limits this output frequency to either 100, 140, or 165 MHz.

2.3.6Feedback Divider (Controls Number of Pixel Clocks per HSYNC)

The ICS1531’s internal 12-bit pixel Feedback Divider (Regs 02 and 03) controls the total number of pixel clocks per line (that is, between successive HSYNCs). The total number of pixels per line includes both displayed and non-displayed pixels.

Reg 06:2 can delay the recovered HYSNC signal (that is, ADCSYNC) by one input clock period. This delay has the effect of moving channel ‘A’ data to the ‘B’ channel output pins and the channel ‘B’ data to the ‘A’ channel output pins.

Note:

1.As a starting point to capture analog RGB input from VESA-compliant sources, ICS recommends certain register settings for the software “*.ics files” that come with the ICS1531 Register Tool. However, the Register Tool register settings are only a guide. (For more information on the ICS1531 Register Tool and its *.ics.files, see the ICS1531 Demo Board Guide.)

2.The display manufacturer must provide a way to optimize the display for the particular display controller in use.

3.If the ICS1531 internal pixel PLL Feedback Divider is not set correctly, it can create visible errors on the display.

4.To adjust the ICS1531 on a sub-pixel basis, see Section 2.6, “Dynamic Phase Adjust (Positions Pixel Clock on Sub-Pixel Basis)”.

2.4Analog-to-Digital Converter (Synchronizes Data Capture)

By using the internal 3-channel analog-to-digital converter (ADC), the ICS1531 internally provides the pixel clock needed to synchronize data capture. The pixel clock can be further processed by the Dynamic Phase Adjust. [For more information on the ADC, see Section 2.2.3, “Analog-to-Digital Circuits (Digitize RGB Inputs)” and Figure 4-3.] For the pixel clock to appear on the CLK pin, the pixel clock output must be enabled (Reg 06:6).

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

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ICS1531 Data Sheet - Preliminary

Chapter 2 Summary

 

 

 

 

2.5Additional PLLs, with Spread Spectrum (Drive Memory and Panel Data Clocks)

Besides the pixel clock PLL, the ICS1531 has two other independent PLLs for use as needed. Typically, one of the PLLs is used to drive memory clocks (Regs 26–2B and 2D) and the other PLL is used to drive panel data clocks (Regs 20–25 and 2D). Both of these additional PLLs are tailored for the required frequency ranges. Each supports software-controlled spread-spectrum clock dithering to reduce measured electro-magnetic interference (EMI).

2.6Dynamic Phase Adjust (Positions Pixel Clock on Sub-Pixel Basis)

Most display controllers provide an HSYNC signal that can be used as a reference signal for the pixel clock. However, when this HSYNC signal is used as an input, frequently it has significant jitter that impacts data capture. Furthermore, the analog data stream from the display controller to the ICS1531 has no pixel-rate reference clock.

So that analog pixel data inputs can be properly sampled and digitized, the ICS1531’s pixel PLL tracks the input HSYNC signal and the line-to-line jitter. To provide a properly aligned sampling clock (ADCSYNC) to the ADC blocks, the ICS1531’s Dynamic Phase Adjust (DPA) circuitry can add delays to the pixel clock position. The delay, which occurs in relation to the edge of ADCSYNC (the recovered HSYNC signal), is added in sub-pixel time increments.

Regs 04:5-0, 05:1-0 and 06 are used to program the ICS1531 DPA for a value representing incremental sub-pixel delay units. By choosing the proper value, pixel data to the ICS1531 can be sampled at the optimum time for proper digitization and the best-looking display. Typically, a system’s microcontroller presets this value, based on either a table or proprietary algorithms. The end user can change the value through the system’s on-screen display controls.

Table 2-1 lists the number of possible delay element units that can be used to program to add a delay of up to one pixel clock period, in increments of either 16, 32, or 64 (Reg 04:5-0 and Reg 5:1-0).

Table 2-1. Increments for Delay Element Units

Number of

 

Pixel Clock Range, MHz

Delay Element Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

55

 

 

260

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

27

 

 

 

130

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64

14

 

64

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: To adjust the ICS1531 on a pixel-by-pixel basis, see Section 2.3.6, “Feedback Divider (Controls Number of Pixel Clocks per HSYNC)”.

2.7Automatic Power-On Reset Detection (Automatically Resets ICS1531)

The ICS1531 automatically detects power-on resets. As a result, the ICS1531 resets itself if the supply voltage drops below threshold values. No external connection to a reset signal is required.

2.8Logic Inputs and Outputs

Inputs. The ICS1531 uses both of the following inputs:

Analog inputs

Digital inputs. The digital inputs are low-voltage TTL (LVTTL) inputs that operate at 3.3 V. These LVTTL inputs are also 5-V tolerant. (For inputs that are 5-V tolerant, see Section 3.2.3.10, “List of 5-V Tolerant Pins”.)

Outputs. The ICS1531 has high-speed LVTTL clock outputs.

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

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ICS1531 Data Sheet - Preliminary

Chapter 2 Summary

 

 

 

 

2.9Industry-Standard 2-Wire Serial Interface

To access all its registers, the ICS1531 uses an industry-standard 2-wire serial interface that operates at one of the following speeds:

A low speed of 100 kHz

A high speed of 400 kHz

An ultra speed of 800 kHz

For use with the 2-wire serial interface, the ICS1531 has 5 V-tolerant inputs. The ICS1531 can use either of two unique, alternative sets of addresses. Table 2-2 lists the addresses that can be used, depending on the state of the SBADR pin.

Table 2-2. ICS1531 Address Sets

Addresses in

Address Set 1.

Address Set 2.

Address Set

(SBADR Pin Is Low)

(SBADR Pin Is High)

 

 

 

7-bit device address

24h

25h

 

 

 

8-bit read address

49h

4Bh

 

 

 

8-bit write address

48h

4Ah

 

 

 

2.10 Programmable Outputs

For general-purpose outputs, the ICS1531 provides three programmable pins, PSEL3, PSEL2, PSEL1 (Reg 37:2-0).

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

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ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

 

 

 

 

Chapter 3 Pin Diagram and Listings

3.1Pin Diagram for ICS1531

Figure 3-1 shows the pin diagram for the ICS1531, which is packaged in a 144-pin low-profile quad flat pack (LQFP).

Figure 3-1. Pin Diagram

1VSS

2TRESE T

3VSS

4N C

5VSS

6H SYNC

7VSSSU B

8PSEL1

9PSEL2

10PS EL3

11N C

12VS S(TEST)

13VS SSUB

14R eserved

15AR ED

16VRTR

17VR B

18N C

19AG R N

20VRTG

21R eserved

22AB LUE

23VRTB

24VD DA ADC

25VS SAADC

26VS SAADC

27VD DA ADC

28C LAM P

29VD DQ AD C

30BB 7

31BB 6

32BB 5

33BB 4

34BB 3

35BB 2

36VS SQ ADC

0111111111111111111111212121212121212 12 12 13 13 13 13 13 13 1313131314141414141 901234567890123456789012345678901234

DVSVTSERS OL Ce RSVC NC NC NC NC NC NC NC NC NC NC NC NC NC NCNCNCNDVSVCNCSDSSVDVDPBSFXXE DSAFCKsSDSLASDEAIT QQTeSADNDLF UOrADRI SUvUREL TeBT d

ICS1531

27 C DA QSSV 17 2A G 07 3A G 96 4A G 86 5A G 76 6A G 66 7A G 56 CDA Q DD V 46 C DA QSSV 36 0B G 26 1B G 16 2B G 06 3B G 95 4B G 85 5B G 75 CDA Q DDV 65 C DA QSSV 55 C NYSC DA 45 KL CR CD A 35 CDA DD DV 25 C DADSSV 15 6B G 05 7B G 94 0AB 84 1AB 74 2AB 64 3AB 54 CDA Q DDV 44 CD A QSSV 34 4AB 24 5AB 14 6 AB 04 7AB 93 0BB 83 1BB 73 CDA Q DDV

VD DXTL

108

XO U T

107

XIN

106

VSSXTL

 

 

105

PN LCLK

 

104

VD DPC LK

 

103

VSSPC LK

 

102

MC LK

 

101

VD DMC LK

 

100

VSSM CLK

 

99

N C

 

98

N C

 

97

VSSAAD C

 

96

R A0

 

95

R A1

 

94

R A2

 

93

R A3

92

R A4

 

91

R A5

 

90

VD DQ AD C

 

89

VSSQ AD C

88

R A6

 

87

R A7

 

86

R B0

 

85

R B1

 

84

R B2

 

83

R B3

 

82

VD DQ AD C

 

81

VSSQ AD C

80

R B4

 

79

R B5

 

78

R B6

 

77

R B7

76

G A0

75

G A1

74

VD DQ AD C

73

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

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ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

 

 

 

 

3.2Pin Listings

Note:

1.The TRESET pin (pin 2) was formerly a Reserved pin.

2.The following pins, formerly ‘Reserved’, are now NC (No Connect): 4, 11, 18, 97–98, 117–133, 136

3.The (active-low) STATUS pin (pin 111) was formerly called ‘LOCK’

3.2.1Pin Listing by Pin Number

Table 3-1. ICS1531 Pins, by Pin Number

Pin No.

Pin Name

 

Pin No.

Pin Name

 

Pin No.

Pin Name

 

Pin No.

Pin Name

 

 

 

 

 

 

 

 

 

 

 

1

VSS

 

37

VDDQADC

 

73

VDDQADC

 

109

VDDQ

 

 

 

 

 

 

 

 

 

 

 

2

TRESET

 

38

BB1

 

74

GA1

 

110

VSSQ

 

 

 

 

 

 

 

 

 

 

 

3

VSS

 

39

BB0

 

75

GA0

 

111

STATUS

 

 

 

 

 

 

 

 

 

 

 

4

NC

 

40

BA7

 

76

RB7

 

112

REF

 

 

 

 

 

 

 

 

 

 

 

5

VSS

 

41

BA6

 

77

RB6

 

113

OSCOUT

 

 

 

 

 

 

 

 

 

 

 

6

HSYNC

 

42

BA5

 

78

RB5

 

114

CLK

 

 

 

 

 

 

 

 

 

 

 

7

VSSSUB

 

43

BA4

 

79

RB4

 

115

Reserved

 

 

 

 

 

 

 

 

 

 

 

8

PSEL1

 

44

VSSQADC

 

80

VSSQADC

 

116

VSSSUB

 

 

 

 

 

 

 

 

 

 

 

9

PSEL2

 

45

VDDQADC

 

81

VDDQADC

 

117

NC

 

 

 

 

 

 

 

 

 

 

 

10

PSEL3

 

46

BA3

 

82

RB3

 

118

NC

 

 

 

 

 

 

 

 

 

 

 

11

NC

 

47

BA2

 

83

RB2

 

119

NC

 

 

 

 

 

 

 

 

 

 

 

12

VSS(TEST)

 

48

BA1

 

84

RB1

 

120

NC

 

 

 

 

 

 

 

 

 

 

 

13

VSSSUB

 

49

BA0

 

85

RB0

 

121

NC

 

 

 

 

 

 

 

 

 

 

 

14

Reserved

 

50

GB7

 

86

RA7

 

122

NC

 

 

 

 

 

 

 

 

 

 

 

15

ARED

 

51

GB6

 

87

RA6

 

123

NC

 

 

 

 

 

 

 

 

 

 

 

16

VRTR

 

52

VSSDADC

 

88

VSSQADC

 

124

NC

 

 

 

 

 

 

 

 

 

 

 

17

VRB

 

53

VDDDADC

 

89

VDDQADC

 

125

NC

 

 

 

 

 

 

 

 

 

 

 

18

NC

 

54

ADCRCLK

 

90

RA5

 

126

NC

 

 

 

 

 

 

 

 

 

 

 

19

AGRN

 

55

ADCSYNC

 

91

RA4

 

127

NC

 

 

 

 

 

 

 

 

 

 

 

20

VRTG

 

56

VSSQADC

 

92

RA3

 

128

NC

 

 

 

 

 

 

 

 

 

 

 

21

Reserved

 

57

VDDQADC

 

93

RA2

 

129

NC

 

 

 

 

 

 

 

 

 

 

 

22

ABLUE

 

58

GB5

 

94

RA1

 

130

NC

 

 

 

 

 

 

 

 

 

 

 

23

VRTB

 

59

GB4

 

95

RA0

 

131

NC

 

 

 

 

 

 

 

 

 

 

 

24

VDDAADC

 

60

GB3

 

96

VSSAADC

 

132

NC

 

 

 

 

 

 

 

 

 

 

 

25

VSSAADC

 

61

GB2

 

97

NC

 

133

NC

 

 

 

 

 

 

 

 

 

 

 

26

VSSAADC

 

62

GB1

 

98

NC

 

134

VDDA

 

 

 

 

 

 

 

 

 

 

 

27

VDDAADC

 

63

GB0

 

99

VSSMCLK

 

135

VSSA

 

 

 

 

 

 

 

 

 

 

 

28

CLAMP

 

64

VSSQADC

 

100

VDDMCLK

 

136

NC

 

 

 

 

 

 

 

 

 

 

 

29

VDDQADC

 

65

VDDQADC

 

101

MCLK

 

137

SCL

 

 

 

 

 

 

 

 

 

 

 

30

BB7

 

66

GA7

 

102

VSSPCLK

 

138

SDA

 

 

 

 

 

 

 

 

 

 

 

31

BB6

 

67

GA6

 

103

VDDPCLK

 

139

VSSD

 

 

 

 

 

 

 

 

 

 

 

32

BB5

 

68

GA5

 

104

PNLCLK

 

140

VDDD

 

 

 

 

 

 

 

 

 

 

 

33

BB4

 

69

GA4

 

105

VSSXTL

 

141

PDEN

 

 

 

 

 

 

 

 

 

 

 

34

BB3

 

70

GA3

 

106

XIN

 

142

SBADR

 

 

 

 

 

 

 

 

 

 

 

35

BB2

 

71

GA2

 

107

XOUT

 

143

XFILRET

 

 

 

 

 

 

 

 

 

 

 

36

VSSQADC

 

72

VSSQADC

 

108

VDDXTL

 

144

EXTFIL

 

 

 

 

 

 

 

 

 

 

 

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Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

10

 

 

ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

 

 

 

 

3.2.2Pin Listing by Alphabetical Pin Name

Note:

1.The TRESET pin was formerly a Reserved pin.

2.The following pins, formerly ‘Reserved’, are now NC (No Connect): 4, 11, 18, 97–98, 117–133, 136

3.The (active-low) STATUS pin was formerly called ‘LOCK’.

Table 3-2. ICS1531 Pins, by Alphabetical Pin Name

 

Pin Name

 

Pin No.

 

 

Pin Name

Pin No.

 

Pin Name

Pin No.

 

 

 

 

 

 

 

 

 

 

 

 

ABLUE

 

22

 

 

GB3

60

 

SDA

138

 

 

 

 

 

 

 

 

 

 

 

 

ADCRCLK

 

54

 

 

GB4

59

 

STATUS

111

 

 

 

 

 

 

 

 

 

 

 

 

ADCSYNC

 

55

 

 

GB5

58

 

TRESET

2

 

 

 

 

 

 

 

 

 

 

 

 

AGRN

 

19

 

 

GB6

51

 

VDDA

134

 

 

 

 

 

 

 

 

 

 

 

 

ARED

 

15

 

 

GB7

50

 

VDDAADC

24, 27

 

 

 

 

 

 

 

 

 

 

 

 

BA0

 

49

 

 

HSYNC

6

 

VDDD

140

 

 

 

 

 

 

 

 

 

 

 

 

BA1

 

48

 

 

MCLK

101

 

VDDDADC

53

 

 

 

 

 

 

 

 

 

 

 

 

BA2

 

47

 

 

NC

4, 11, 18, 97–98,

 

VDDMCLK

100

 

 

 

 

 

 

 

117–133, 136

 

 

 

 

 

BA3

 

46

 

 

 

 

VDDPCLK

103

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BA4

 

43

 

 

OSCOUT

113

 

VDDQ

109

 

 

 

 

 

 

 

 

 

 

 

 

BA5

 

42

 

 

PDEN

141

 

VDDQADC

29, 37, 45, 57,

 

 

 

 

 

 

 

 

 

 

 

65, 73, 81, 89

 

BA6

 

41

 

 

PNLCLK

104

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BA7

 

40

 

 

PSEL1

8

 

VDDXTL

108

 

 

 

 

 

 

 

 

 

 

 

 

BB0

 

39

 

 

PSEL2

9

 

VRB

17

 

 

 

 

 

 

 

 

 

 

 

 

BB1

 

38

 

 

PSEL3

10

 

VRTB

23

 

 

 

 

 

 

 

 

 

 

 

 

BB2

 

35

 

 

RA0

95

 

VRTG

20

 

 

 

 

 

 

 

 

 

 

 

 

BB3

 

34

 

 

RA1

94

 

VRTR

16

 

 

 

 

 

 

 

 

 

 

 

 

BB4

 

33

 

 

RA2

93

 

VSS

1, 3, 5

 

 

 

 

 

 

 

 

 

 

 

 

BB5

 

32

 

 

RA3

92

 

VSSA

135

 

 

 

 

 

 

 

 

 

 

 

 

BB6

 

31

 

 

RA4

91

 

VSSAADC

25, 26, 96

 

 

 

 

 

 

 

 

 

 

 

 

BB7

 

30

 

 

RA5

90

 

VSSD

139

 

 

 

 

 

 

 

 

 

 

 

 

CLAMP

 

28

 

 

RA6

87

 

VSSDADC

52

 

 

 

 

 

 

 

 

 

 

 

 

CLK

 

114

 

 

RA7

86

 

VSSMCLK

99

 

 

 

 

 

 

 

 

 

 

 

 

EXTFIL

 

144

 

 

RB0

85

 

VSSPCLK

102

 

 

 

 

 

 

 

 

 

 

 

 

GA0

 

75

 

 

RB1

84

 

VSSQ

110

 

 

 

 

 

 

 

 

 

 

 

 

GA1

 

74

 

 

RB2

83

 

VSSQADC

36, 44, 56, 64,

 

 

 

 

 

 

 

 

 

 

 

72, 80, 88

 

GA2

 

71

 

 

RB3

82

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GA3

 

70

 

 

RB4

79

 

VSSSUB

7, 13, 116

 

 

 

 

 

 

 

 

 

 

 

 

GA4

 

69

 

 

RB5

78

 

VSS(TEST)

12

 

 

 

 

 

 

 

 

 

 

 

 

GA5

 

68

 

 

RB6

77

 

VSSXTL

105

 

 

 

 

 

 

 

 

 

 

 

 

GA6

 

67

 

 

RB7

76

 

XFILRET

143

 

 

 

 

 

 

 

 

 

 

 

 

GA7

 

66

 

 

REF

112

 

XIN

106

 

 

 

 

 

 

 

 

 

 

 

 

GB0

 

63

 

 

Reserved

14, 21, 115

 

XOUT

107

 

 

 

 

 

 

 

 

 

 

 

 

 

GB1

 

62

 

 

SBADR

142

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GB2

 

61

 

 

SCL

137

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICS1531 Rev N 12/1/99

 

 

 

 

 

 

 

 

December, 1999

 

 

Copyright © 1999, Integrated Circuit Systems, Inc.

 

 

 

 

 

 

 

 

All rights reserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

 

 

 

 

3.2.3Pin Listing by Functional Grouping

3.2.3.1Clock Pins

For more information on the clock pins, see Figure 4-2 and Figure 4-3.)

Table 3-3. Clock Pins

Pin

Pin

 

Pin Description

Name

Type

 

 

 

 

 

ADCRCLK

Input or

Analog-to-Digital Converter Reference Clock.

 

Output

This pin outputs a half-rate pixel clock for latching digital output pixel data.

 

 

Typically, this pin connects to an LCD panel controller/scaler.

 

 

In this table, see also CLK.

ADCSYNC

Input or

Analog-to-Digital Converter Sync.

 

Output

This pin provides a recovered HSYNC signal (that is, an HSYNC signal conditioned by a

 

 

Schmitt trigger) that aligns to ADCRCLK.

 

 

For some previous ICS chips, the ADCSYNC pin is called FUNC.

 

 

 

CLK

Output

Clock.

 

 

This pin outputs the full-rate pixel clock for latching digital output pixel data.

 

 

In this table, see also ADCRCLK.

HSYNC

Input

Horizontal Sync. (See Table 3-6.)

 

 

 

MCLK

Output

Memory Clock.

 

 

This pin provides an independent user-programmable clock source.

 

 

Typically, this pin is used by LCD panel controller/scaler chips or microcontrollers.

OSCOUT

Output

Oscillator Output.

 

 

This output from this pin is from a crystal oscillator.

 

 

The output frequency is one of the following:

 

 

 

– The same frequency as the input frequency to the crystal oscillator

 

 

 

– The frequency that results when the input frequency is divided by a programmable

 

 

 

value

 

 

 

PNLCLK

Output

Panel Clock.

 

 

This pin provides an independent user-programmable clock source.

 

 

Typically, this pin is used by LCD panel controller/scaler chips or microcontrollers.

REF

Output

Reference.

 

 

This pin provides various reference line clock sync signals.

 

 

 

SCL

Input

Serial Clock. (See Table 3-7.)

 

 

 

XIN

Input

Crystal Input.

 

 

This pin accepts input from one of the following:

 

 

A 14.31818-MHz crystal

 

 

An external clock source

XOUT

Output

Crystal Output.

 

 

Do one of the following with this pin:

 

 

Connect it to a 14.31818-MHz crystal.

 

 

Leave it open for an external clock source.

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

12

 

 

ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

 

 

 

 

3.2.3.2Control Pins

Table 3-4. Control Pins

Pin

Pin

 

 

 

 

 

Pin Description

 

Name

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLAMP

Input

Clamp.

 

 

 

 

 

 

 

This pin accepts an external signal that is provided as an alternative to the ICS1531’s

 

 

internally generated clamp signal.

 

 

 

 

 

 

 

 

 

 

 

 

PSEL1,

Output

Programmable Select 1, 2, 3.

 

 

 

 

 

PSEL2,

 

These pins are used as general-purpose programmable output pins.

PSEL3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRESET

Input

Test Reset.

 

 

 

 

 

 

 

When the ICS1531:

 

 

 

 

 

 

 

 

Is not in Test mode, this pin has no effect.

 

 

 

 

Is placed into Test mode:

 

 

 

 

 

 

 

 

 

This pin acts as a reset that sets the ICS1531 to an initial known state.

 

 

 

 

For information about the Test mode, in this table see VSS(TEST).

 

 

 

 

 

 

 

 

 

 

VSS(TEST)

Input

Ground (Normal Mode) or Test Mode.

 

 

 

 

Normal Mode.

 

 

 

 

 

 

 

 

For the VSS(TEST) pin’s Normal-mode function, see Table 3-4.

 

 

 

Test Mode.

 

 

 

 

 

 

 

 

 

– When this pin is connected to either VDDA or VDDAADC, the ICS1531 is in Test

 

 

 

 

 

mode. As a result, the ICS1531 is set to an initial known state.

 

 

 

 

The Test mode overrides whatever the bit setting of Reg 37:3 is, so that the

 

 

 

 

 

Calibration Regs 38h to 3Ch are automatically enabled.

 

 

 

 

– The Test mode bits are intended for use only by ICS.

 

 

 

 

 

 

 

 

 

 

 

In Test mode, Test-mode bits are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICS1531

 

VDDA or VDDAADC

 

 

 

 

 

 

enabled and Calibration Regs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS(TEST)

 

 

 

 

 

38h to 3Ch are automatically

 

 

 

 

 

 

Test Mode

enabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

13

 

 

ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

 

 

 

 

3.2.3.3Pixel Data Pins

Table 3-5. Pixel Data Pins

Pin

Pin

 

Pin Description

Name

Type

 

 

 

 

 

ABLUE,

Input

Analog Blue, Analog Green, Analog Red.

AGRN,

 

These pins accept analog data for the ADC blue, green, and red channels.

ARED

 

Typically, the data for these pins comes from a PC display controller.

BA7 – BA0,

Output

Blue (‘A channel’) A7 – A0, Green (‘A channel’) A7 – A0, Red (‘A channel’) A7 – A0.

GA7 – GA0,

 

These pins output first blue, green, and red pixel data, respectively.

RA7 – RA0

 

A7 pins reflect most-significant data bits. A0 pins reflect least-significant data bits.

BB7 – BB0,

Output

Blue (‘B channel’) B7 – B0, Green (‘B channel’) B7 – B0, Red (‘B channel’) B7 – B0.

GB7 – GB0,

 

These pins output second blue, green, and red pixel data, respectively.

RB7 – RB0

 

B7 pins reflect most-significant data bits. B0 pins reflect least-significant data bits.

Figure 3-2 shows the following:

The relationship of:

Outputs from the ICS1531 ADC

To inputs of a 1024 × 768 LCD panel that samples 2 pixels of data with either a 36or 48-bit data signal.

DA indicates ‘A channel’ pixels, and DB indicates ‘B channel’ pixels.)

For timing information, see Chapter 10, “Timing Diagrams”.

Figure 3-2. Relationship of Outputs from an ICS1531’s ADC to Inputs of 1024 × 768 LCD Panel

DA (1,1) DB (1,1)

RA7-0 GA7-0 BA7-0 RB7-0 GB7-0 BB7-0

DA (1,1)

DB (1,1)

DA (2,1)

DB (512,1)

DA (1,2)

DB (1,2)

 

 

DA (1,3)

 

 

 

DA (1,768)

 

DB (512,768)

 

 

 

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

14

 

 

ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

 

 

 

 

3.2.3.4Phase-Locked Loop Pins

Table 3-6 lists the pins for the phase-locked loop circuitry. For a block diagram that shows the function of these pins, see Figure 4-1.

Table 3-6. Phase-Locked Loop Pins

Pin

Pin

 

Pin Description

Name

Type

 

 

 

 

 

EXTFIL

Input

External Filter.

 

 

This pin works with XFILRET (in this table, see XFILRET) and other components as part of an

 

 

optional external filter for the pixel phase-locked loop.

 

 

 

HSYNC

Input

Horizontal Sync.

 

 

This 5-V tolerant pin is the clock input for the pixel PLL.

 

 

Typically this pin is connected to the HSYNC from a PC display controller.

 

 

In this data sheet, this HSYNC signal is also called ‘input HSYNC’.

LOCK

Output

In this table, see the ‘STATUS’ pin name.

 

 

 

PDEN

Input

Phase-Detector Enable.

 

 

This pin is the input for the Phase/Frequency Detector enable that can suspend the charge

 

 

pump activity. It is 5-V tolerant. (For more information, see Reg 00:1-0 in Section 6.5.1,

 

 

“Register 00h: Input Control Register”.)

 

 

 

STATUS

Output

Status (Formerly called ‘Lock’).

 

 

This active-low pin works with Reg 2C:1-0 and Reg 12:3-2. The signal on this pin is:

 

 

Low when a lock condition occurs for one of the PLLs selected by Reg 2C:1-0 or 12:3-2.

 

 

High when no lock condition occurs for one of the PLLs selected by Reg 2C:1-0 or 12:3-2.

XFILRET

Input

External Filter Return.

 

 

This pin works with EXTFIL (in this table, see EXTFIL) and other components as part of an

 

 

optional external filter for the pixel phase-locked loop.

 

 

 

 

3.2.3.5Industry-Standard 2-Wire Serial Bus Pins

Table 3-7. Industry-Standard 2-Wire Serial Bus Pins

Pin

Pin

 

 

Pin Description

Name

Type

 

 

 

 

 

 

SBADR

Input

Serial Bus Address.

 

 

This pin determines the address for the ICS1531 industry-standard 2-wire serial bus.

 

 

When the signal on this pin is:

 

 

 

Low, the pixel bit address is 49h for read operations and 48h for write operations.

 

 

High, the pixel bit address is 4Bh for read operations and 4Ah for write operations.

 

 

For more information on this pin, see Section 2.9, “Industry-Standard 2-Wire Serial

 

 

 

Interface”.

 

 

 

SCL

Input

Serial Clock.

 

 

This 5-V tolerant pin is the clock for the interface to an industry-standard 2-wire serial bus.

 

 

 

SDA

Input/

Serial Data.

 

Output

This 5-V tolerant pin connects to the data pin for an industry-standard 2-wire serial bus.

 

 

 

 

 

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

15

 

 

ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

 

 

 

 

3.2.3.6Ground Pins

Table 3-8. Ground Pins

Pin Name

Pin Description

VSS

Ground for (Analog Inputs for Digital Pixel PLL Circuitry).

These pins are used to ground digital portions of the pixel PLL circuitry that receive analog inputs.

The VSSD pin must also be connected to these pins.

VSSA

Ground for Analog (Pixel PLL Circuitry).

 

This pin is used to ground the analog portions of the pixel PLL circuitry.

 

 

VSSAADC

Ground for Analog ADC (Circuitry).

 

These pins are used to ground the analog portions of the ADC.

 

 

VSSD

Ground for Digital (Pixel PLL and Circuitry for Industry-Standard 2-Wire Serial Interface).

 

This pin is used to ground the digital portions of the pixel PLL circuitry and the circuitry for an

 

industry-standard 2-wire serial interface.

 

 

VSSDADC

Ground for Digital ADC (Circuitry).

 

This pin is used to ground the digital portions of the ADC.

 

 

VSSMCLK

Ground for Memory Clock (Circuitry).

 

This pin is used to ground the circuitry for the memory clock PPL (that is, MCLK).

 

 

VSSPCLK

Ground for Panel Clock (Circuitry).

 

This pin is used to ground the circuitry for the panel clock PLL (that is, PNLCLK).

 

 

VSSQ

Ground for Output Drivers.

 

This pin is used to ground output drivers for the pixel PLL circuitry.

 

 

VSSQADC

Ground for Output Drivers for ADC.

 

These pins are used to ground the pixel data output drivers for the analog-to-digital converter.

 

 

VSSSUB

Ground for Substrate.

 

These pins are used to provide ground for the chip substrate.

VSS(TEST) Ground (Normal Mode) or Test Mode.

Normal Mode.

Typically, this pin must be connected to ground (the Normal mode).

When the ICS1531 is in Normal mode, the Calibration registers 38h to 3Ch can be enabled by using Reg 37:3. (See Section 6.5.39, “Register 37h: PSEL”.)

ICS1531

 

 

 

 

 

 

 

 

VSS(TEST)

Normal Mode

 

 

 

In Normal mode, use Reg 37:3 to

 

 

 

 

 

 

 

enable Calibration Regs 38h to 3Ch.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test Mode.

For the VSS(TEST) pin’s Test-mode function, see Table 3-4.

VSSXTL Ground for Crystal Oscillator.

This pin is used to ground the internal crystal oscillator circuitry.

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

16

 

 

ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

 

 

 

 

3.2.3.7Power Pins

Table 3-9. Power Pins

Pin Name

 

 

Pin Description

 

 

 

VDDA

(3.3

V) Supply for Analog (Pixel PLL Circuitry).

 

This pin supplies 3.3 V to the analog portions of the pixel PLL circuitry.

 

 

 

VDDAADC

(3.3

V) Supply for Analog ADC (Circuitry).

 

These pins supply 3.3 V to the analog portions of the ADC.

 

 

 

VDDD

(3.3

V) Supply for Digital (Pixel PLL and Industry-Standard 2-Wire Serial Bus) Circuitry.

 

This pin supplies 3.3 V to the digital pixel PLL and circuitry for an industry-standard 2-wire serial bus

 

interface.

 

 

 

VDDDADC

(3.3

V) Supply for Digital ADC (Circuitry).

 

This pin supplies 3.3 V to digital portions of the ADC.

 

 

 

VDDMCLK

(3.3

V) Supply for Memory Clock.

 

This pin supplies 3.3 V to the memory clock PLL circuitry.

 

 

 

VDDPCLK

(3.3

V) Supply for Panel Clock.

 

This pin supplies 3.3 V to the panel clock PLL circuitry.

 

 

 

VDDQ

(3.3

V) Supply for Output Drivers.

 

This pin supplies 3.3 V to the output driver circuitry for the pixel PLL.

 

 

 

VDDQADC

(3.3

V) Supply for Output Drivers for Analog-to-Digital Converter.

 

These pins supply 3.3 V to the pixel data output drivers of the ADC.

 

 

VDDXTL

(3.3V) Supply for Crystal Oscillator.

 

This pin supplies 3.3 V to the internal crystal oscillator circuitry.

 

 

VRB

Voltage Reference Bottom.

 

The ADC uses this pin as a bottom reference voltage. Typically, this pin is grounded.

 

 

VRTB,

Voltage Reference Top Blue, Green, Red

VRTG,

The ADC uses these pins as an alternative to the blue, green, and red top reference voltages

VRTR

from the internal DACs.

 

Each of these pins must connect to its own separate bypass capacitor.

 

 

 

 

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

17

 

 

ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

 

 

 

 

3.2.3.8No-Connect Pins

Table 3-10. No-Connect Pins

Pin

Pin Description

Name

 

 

 

NC

No Connect.

 

Do not connect these pins.

 

Caution: Do not connect or use No-Connect pins. Connecting them can affect the performance

 

and operation of the ICS1531 and future members of the ICS153X family.

 

 

3.2.3.9Reserved Pins

Table 3-11. Reserved Pins

Pin

Pin

Pin Description

Name

Type

 

 

 

 

Reserved

Reserved.

 

 

These pins are always reserved for use by ICS.

 

 

Caution: Do not connect or use Reserved pins. Connecting them can affect the performance

 

 

and operation of the ICS1531 and future members of the ICS153X family.

 

 

 

3.2.3.10List of 5-V Tolerant Pins

The following pins are 5-V tolerant:

HSYNC (Table 3-6)

PDEN (Table 3-6)

SCL (Table 3-7)

SDA (Table 3-7)

TRESET (Table 3-4)

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

18

 

 

ICS1531 Data Sheet - Preliminary

Chapter 4 Functional Blocks

 

 

 

 

Chapter 4 Functional Blocks

4.1Pixel PLL Functional Block

Figure 4-1. Pixel PLL Block Diagram

OSCOUT

(113)

 

OE OSC Reg2C:6

REF (112)

STATUS

(111)

 

 

 

 

 

 

 

 

1:5-4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SD eg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P R

 

 

 

 

 

 

 

 

 

 

 

 

XFILRET

(143)

:12CgeR-0

CLNPLK Lock 12geR:2

KLCMLock 1egR2:3

 

VCO

 

PostScaler Divider

 

 

 

 

 

:2

 

 

 

 

 

EXTFIL

LESKCL

 

earghC Filter

pmuP Select

Fil Sel Reg8:0

CapSelReg8:3-1 IntFilterResSelReg8:6-4

RSS8:7egelnthu

 

 

 

 

 

 

 

 

 

 

 

 

(144)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg2C

 

1DCFUNC

MUX

FER

 

 

 

 

Lock Logic

 

seahP reqF eDctoter

ixPelPLL Lock 0P-2FDReg12:1 0-:21geR

 

PAD Lock Reg12:0

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

n :0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DE eg0

 

 

 

 

 

 

 

 

 

OSC SEL Reg2C:5-4 0

 

 

 

 

 

 

 

 

 

 

 

P R

 

 

 

 

 

 

 

 

 

1

MUX

2

3

 

 

PDEN

(141)

 

 

 

PD Pol Reg0:1

In Sel Reg0:5

1

MUX

0

 

Fdbk Pol Reg0:3

 

 

 

 

 

 

 

 

 

 

 

 

OSC DIV

 

OSC Div Reg7:7-0

Ref Pol Reg0:2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

el -6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIV2

 

 

 

HSYNCS

0:7

 

 

 

2-Wire

 

Interface

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg

 

 

 

Serial

 

 

 

 

 

 

 

 

 

 

OSC

 

 

 

 

 

 

HSYNC

(6)

SDA (138)

 

SCL

(137)

ADC CLK

 

 

 

 

CLK

(114)

OE Tck Reg6:6

 

Delay g6:2

 

 

 

 

 

 

 

ADC FUNC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC Re

1

M

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

amic

ase just

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dyn

Ph Ad

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

egR03-:3 07KBDF- 02geR-:7

 

 

 

 

 

 

 

-1seRPAD0

 

0-5:1geR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

kcabdeeF ivDreid

 

 

8-11KBDF

 

daoivL

:40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

05-

0-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DPA OS Reg4:5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BkD

Reg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fd

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6:3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

MU

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Static Regs

 

 

 

 

ChipMajor/ MinorRev Reg11:7-0

 

 

 

 

Ver

10:7-0

 

 

 

 

 

 

Chip

 

 

 

 

 

 

 

Reg

PixelPLLReset RegA:7-4

 

 

 

 

 

 

 

 

 

 

 

POR

 

 

 

 

 

 

 

 

DPAReset

RegA:3-0

SBADR (142)

 

 

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

19

12/1/99 N Rev ICS1531

20

Circuit Integrated 1999, © Copyright .reserved rights All

 

.Inc Systems,

 

 

1999 December,

ADC _CLK

XIN (106)

14.318 MHz Crystal

O sc

XOUT (107)

Divide

By 16

 

 

 

 

 

 

 

PNLCLK-M

 

 

 

 

 

PN LC LK_PFD

 

 

 

PN LC LK_Lock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg 20:7-0

 

 

 

 

 

Reg 24:4-2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R eg 12:2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M U X

 

 

R eference

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P hase

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D ivider

 

 

 

 

 

 

Freq

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

De tector

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg 25:2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Feedback

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PNLCLK-N

 

 

D ivider

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg 21:7-0

 

 

 

 

Spread

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Spectrum

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PNLCLK-S S0

P NLC LK-SS1

PNLCLK_SS

 

PNLCLK_SSENB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg 22:7-0

R eg 23:3-0

Reg 24:7-6

 

 

 

 

R eg 25:1

 

 

 

 

 

 

 

MC LK-M

 

 

 

 

 

M CLK_PFD

 

 

 

 

 

MCLK_Lock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg 26:7-0

 

 

 

 

 

Reg 2A:4-2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg 12:3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reference

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Phase

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Divider

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Freq

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Detector

 

 

 

 

 

Feedback

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCLK-N

 

 

 

 

 

Divider

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg 27:7-0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Divide

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Spread

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

By 144

 

 

 

 

 

 

 

 

 

 

 

 

 

Spectrum

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M CLK-SS0

MCLK-SS1

MCLK_SS

 

M CLK_SSENB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R eg 28:7-0

Reg 29:3-0

Reg 2A:7-6

 

 

 

 

Reg 2B:1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VC O

Divide By 2

 

 

 

PNLCLK_O SD

 

 

 

Reg 24:1-0

Output

 

 

 

 

 

 

 

 

 

 

PNLCLK

Scaler

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Divider

 

 

 

(104)

 

 

 

 

 

 

 

 

PNLCLK_O E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg 25:0

VCO

Divide By 2

 

 

 

M CLK_O SD

 

 

 

Reg 2A:1-0

Output

 

 

 

 

 

 

 

 

Scaler

 

 

 

 

 

 

 

 

MCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Divider

 

 

(101)

 

 

 

 

 

 

 

 

MCLK_OE

 

 

 

 

 

 

 

Reg 2B:0

OSC

 

2.4

 

Diagram Block CLK .2-4 Figure

Block Functional CLK

 

Preliminary - Sheet Data ICS1531

Blocks Functional 4 Chapter

ICST ICS1531Y-100, ICS1531Y-140, ICS1531Y-165 Datasheet

12/1/99 N Rev ICS1531

21

Circuit Integrated 1999, © Copyright .reserved rights All

 

.Inc Systems,

 

 

1999 December,

Reference

 

 

 

 

 

 

RA0 - RA7

Voltage

 

 

 

 

 

 

 

VRTR (16)

 

 

0

 

(95, 94, 93, 92,

 

 

 

8

 

 

 

 

1

 

91, 90, 87, 86)

 

 

 

 

 

 

 

 

 

 

ADC_Inv

ADC_OE

 

 

 

 

Clamp

RED

M U X

 

 

ARED (15)

 

Reg 30:5

Reg 30:7

 

 

and Amp

 

 

 

 

 

 

ADC BLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RB0 - RB7

 

 

 

 

8

 

 

(85, 84,

83, 82,

 

 

 

 

 

 

79, 78, 77, 76)

 

 

 

 

 

 

 

 

 

 

 

 

 

ADC_Inv

ADC_OE

 

 

 

 

 

 

 

Reg 30:5

Reg 30:7

 

Reference

 

 

 

 

 

 

GA0 - GA7

Voltage

 

 

 

 

 

 

 

VRTG (20)

 

 

0

 

(75, 74, 71, 70,

 

 

 

8

 

 

 

 

1

 

69, 68, 67, 66)

 

AGRN (19)

Clamp

GREEN

M U X

ADC_Inv

ADC_OE

 

 

 

Reg 30:5

Reg 30:7

 

 

 

 

 

 

 

 

 

 

 

 

and Amp

ADC BLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GB0 - GB7

 

 

 

 

8

 

 

(63, 62, 61, 60,

 

 

 

 

 

 

59, 58, 51, 50)

 

 

 

 

 

 

 

 

 

 

 

 

 

ADC_Inv

ADC_OE

 

Reference

 

 

 

 

 

Reg 30:5

Reg 30:7

 

 

 

 

 

 

 

BA0 - BA7

Voltage

 

 

 

 

 

 

 

 

VRTB (23)

 

8

0

 

(49, 48, 47, 46,

 

 

 

1

 

43, 42, 41, 40)

 

 

 

 

 

 

 

VRB (17)

Clamp

BLUE

M U X

ADC_Inv

ADC_OE

 

CLAM P_Sel

ABLUE (22)

 

Reg 30:5

Reg 30:7

 

and Amp

ADC BLOCK

 

 

 

 

Reg 30:2

 

 

 

 

 

 

 

 

 

 

 

 

 

CLAMP

1

 

 

 

 

BB0 - BB7

 

(28)

 

 

 

 

 

0

 

8

 

 

(39, 38, 35, 34,

 

 

 

 

 

 

 

M U X

 

 

 

33, 32, 31, 30)

 

 

 

 

 

 

 

 

 

 

Half-rate clock (even in 1X mode)

SET_ADC

ADC_Inv

ADC_OE

 

 

 

 

 

Reg 30:5

Reg 30:7

 

 

 

 

 

 

 

 

 

CLA MP _Pol

 

 

Reg 30:4

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg 30:3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A DCRC LK_Del

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output-rate clock (1X or 1/2X)

 

 

 

Reg 37:6-5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

Q

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADCRC LK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADC_Sel

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(54)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADC_CLK

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

R eg 30:6

 

 

 

 

O E_AD CRC LK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q

 

 

 

 

 

 

M U X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADCRCLK_Inv

 

 

 

 

 

Reg 6:5

 

 

 

 

 

 

 

 

 

 

M U X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reg 37:7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O E _ADC RCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R eg 6:5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Full-rate clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADCSYNC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADC_FUNC

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(55)

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE _AD CSYNC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M U X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R eg 6:4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O E _ADCSYN C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R eg 6:4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Func

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.4

 

Diagram Block ADC .3-4 Figure

Block Functional ADC

 

Preliminary - Sheet Data ICS1531

Blocks Functional 4 Chapter

 

 

ICS1531 Data Sheet - Preliminary

Chapter 5 Application Overview

 

 

 

 

Chapter 5 Application Overview

Figure 5-1 shows a basic application for the ICS1531.

Figure 5-1. ICS1531 Application

15-Pin VGA

Connector VSYNC

(Monitor End)

HSYNC

 

Recovered HSYNC

 

Pixel Data Clock

LCD

Pixel Data

ASIC

 

 

 

Red

 

 

 

 

 

Green

 

 

ICS1531

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Blue

 

 

 

 

 

 

 

 

 

 

 

 

 

Panel Clock

Memory Clock

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

22

 

 

ICS1531 Data Sheet - Preliminary

Chapter 6 Register Set

 

 

 

 

Chapter 6 Register Set

The tables in this chapter detail the functionality of the bits in the ICS1531 Register Set. The tables include the register locations, the bit positions, names, and definitions, along with their read/write access, reset values, and any special functions or capabilities.

6.1Reserved Bits

The ICS1531 has a number of reserved bits throughout the Register Set. These bits provide enhanced test functions (intended for use only by ICS manufacturing) and calibration functions (intended for use in production environments).

Important: The customer must not change the value of reserved bits. If the customer changes the default values of these reserved bits, normal operation of the ICS1531 can be affected.

6.2Register Set Conventions

Register Set conventions include the following:

Bits are listed in the order of most-significant bit (MSB) to least-significant bit (LSB).

Unless otherwise indicated, bit settings are listed in terms of digital (and not hexadecimal) values.

When a bit definition includes word(s) in parentheses, the word in parenthesis is not part of the bit name, but is given to explain the origin of the bit’s name.

6.3Register Set Abbreviations and Acronyms

Table 6-1 lists and defines abbreviations and acronyms used specifically in this chapter. (Table 1-1 lists other abbreviations and acronyms used throughout this data sheet.)

Table 6-1. Register Set Abbreviations and Acronyms

Abbreviation

Definition

or Acronym

 

 

 

D-DPA

Double-Buffered / Dynamic Phase Adjust. Indicates double-buffered registers for which

 

working registers load during a software Dynamic Phase Adjust reset.

 

 

D-MK

Double-Buffered / Memory Clock. Indicates double-buffered registers for which working

 

registers load during a software MCLK reset.

 

 

D-PK

Double-Buffered / Panel Clock. Indicates double-buffered registers for which working registers

 

load during a software PNLCLK reset.

 

 

D-PLL

Double-Buffered / Phase-Locked Loop. Indicates double-buffered registers for which working

 

registers load during a software pixel PLL reset.

 

 

IN-A

Increment All. Indicates a value that increments with each all-layer revision of the ICS1531.

 

 

Reg

Register

 

 

R/W

Read/Write

 

 

Spec. Func.

Special Function. Indicates a special function, such as the following (listed in this table):

 

D-DPA, D-MK, D-PK, D-PLL

 

 

ICS1531 Rev N 12/1/99

Copyright © 1999, Integrated Circuit Systems, Inc.

December, 1999

 

All rights reserved.

 

 

 

 

23

+ 53 hidden pages