ICST GSP1574BM, AV1574BM, AV1574BEB, GSP1574BEB, ICS1574BEB, ICS1574BM Datasheet

									Integrated	ICS1574B
									Circuit
									Systems, Inc.

User Programmable Laser Engine Pixel Clock Generator

Description

The ICS1574B is a very high performance monolithic phaselocked loop (PLL) frequency synthesizer designed for laser engine applications. Utilizing ICS’s advanced CMOS mixedmode technology, the ICS1574B provides a low cost solution for high-end pixel clock generation for a variety of laser engine product applications.

The pixel clock output (PCLK) frequency is derived from the main clock by a programmable resettable divider.

Operating frequencies are fully programmable with direct control provided for reference divider, feedback divider and post-scaler.

Block Diagram

Features

•Supports high resolution laser graphics. PLL/VCO frequency re-programmable through serial interface port to 400 MHz; allows less than ±1.5ns pixel clock resolution.

•Laser pixel clock output is synchronized with conditioned beam detect input

•Ideal for laser printer, copier and FAX pixel clock applications

•On-chip PLL with internal loop filter

•On-chip XTAL oscillator frequency reference

•Resettable, programmable counter gives glitch-free clock alignment

•Single 5 volt power supply

•Low power CMOS technology

•Compact – 16-pin 0.150" skinny SOIC package

•User re-programmable clock frequency supports zoom and gray scale functions

Figure 1

1574B 8/31/00

ICS1574B

Pin Configuration

PCLKEN 1

XTAL1 2

XTAL2 3

DATCLK 4

VSS 5

VSS 6

PCLK 7

(Do Not Connect) Reserved 8

ICS1574B

16 DATA

15 HOLD

14 TEST (Connect to VSS))

13 VDD

12 VDDO

11 Reserved (Do Not Connect)

10 Reserved (Do Not Connect)

9 Reserved (Do Not Connect)

				16-Pin Skinny SOIC
Pin Descriptions
PIN NUMBER		PIN NAME				DESCRIPTION
7	PCLK				Pixel clock output.
1	PCLKEN				PCLK Enable (Input).
2	XTAL1				Quartz crystal connection 1 / external reference frequency input.
3	XTAL2				Quartz crystal connection 2.
4	DATCLK				Data Clock (Input).
16	DATA				Serial Register Data (Input).
15						(Input).
		HOLD			HOLD
14	Test				Test. (Must be connected to VSS.)
8, 9, 10, 11	Reserved				Reserved. (Do Not Connect.)
13	VDD				PLL system power (+5V. See application diagram).
12	VDDO				Output stage power (+5V).
5, 6	VSS				Device ground. (Both pins must be connected.)

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ICS1574B

PCLK Programmable Divider

The ICS1574B has a programmable divider (referred to in Figure 1 as the PCLK divider) that is used to generate the PCLK clock frequency for the pixel clock output. The modulus of this divider may be set to 3, 4, 5, 6, 8, 10, 12, 16 or 20 under register control. The design of this divider permits the output duty factor to be 50/50, even when an odd modulus is selected. The input frequency to this divider is the output of the PLL post-scaler described below:

The phase of the PCLK output is aligned with the internal high frequency PLL clock (FVCO) immediately after the assertion of the PCLKEN input pulse (active low if PCLKEN_POL bit is 0 or active high if PCLKEN_POL bit is 1).

When PCLKEN is deasserted, the PCLK output will complete its current cycle and remain at VDD until the next PCLKEN pulse. The minimum time PCLKEN must be disabled (TPULSE) is 1/FPCLK.

See Figure 2a for an example of PCLKEN enable (negative polarity) vs. PCLK timing sequences.

Figure 2a

TK = K •TVCO

Td = LOGIC PROP.DELAY TIME

(typically 9ns with a 10pF load on PCLK)

TVCO = 1/FVCO

Figure 2b

The resolution of Ton is one VCO cycle.

The time required for a PCLK cycle start following a PCLKEN enable is described by Figure 2b and the following table:

K Values

PCLK Divider	K
3	2
4a	3.5
4b	3
5	4.5
6	3.5
8a	5.5
8b	5
10	7
12	6.5
16a	9.5
16b	9
20	12

Typical values for Tr and Tf with a 10pF load on PCLK are 1ns.

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ICS1574B

PLL Post-Scaler

A programmable post-scaler may be inserted between the VCO and the PCLK divider of the ICS1574B. This is useful in generating lower frequencies, as the VCO has been optimized for high-frequency operation. The post-scaler is not affected by the PCLKEN input.

The post-scaler allows the selection of:

•VCO frequency

•VCO frequency divided by 2

•VCO frequency divided by 4

•AUX-EN Test Mode

PLL Synthesizer Description —

Ratiometric Mode

The ICS1574B generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency provided to the PLL (see Figure 1). The reference frequency is generated by an on-chip crystal oscillator or the reference frequency may be applied to the ICS1574B from an external frequency source.

The phase-frequency detector shown in the block diagram drives the voltage-controlled oscillator, or VCO, to a frequency that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. This occurs when:

	F(VCO):	=	F(XTAL1) • Feedback Divider
			Reference Divider

This expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers).

The VCO gain is programmable, permitting the ICS1574B to be optimized for best performance at all operating frequencies.

The reference divider may be programmed for any modulus from 1 to 128 in steps of one.

The feedback divider may be programmed for any modulus from 37 through 392 in steps of one. Any even modulus from 392 through 784 can also be achieved by setting the “double” bit which doubles the feedback divider modulus. The feed-

back divider makes use of a dual-modulus prescaler technique that allows the programmable counters to operate at low speed without sacrificing resolution. This is an improvement over conventional fixed prescaler architectures that typically impose a factor-of-four (or larger) penalty in this respect.

Table 1 permits the derivation of “A” & “M” converter programming directly from desired modulus.

Digital Inputs

The programming of the ICS1574B is performed serially by using the DATCLK, DATA, and HOLD pins to load an internal shift register.

DATA is shifted into the register on the rising edge of

DATCLK. The logic value on the HOLD pin is latched at the same time. When HOLD is low, the shift register may be loaded without disturbing the operation of the ICS1574B. When high, the shift register outputs are transferred to the control registers, and the new programming information becomes active. Ordinarily, a high level should be placed on the HOLD pin when the last data bit is presented. See Figure 3 for the programming sequence.

The PCLKEN input polarity may be programmed under register control via Bit 39.

Figure 3

Output Description

The PCLK output is a high-current CMOS type drive whose frequency is controlled by a programmable divider that may be selected for a modulus of 3, 4, 5, 6, 8, 10, 12, 16 or 20. It may also be suppressed under register control via Bit 46.

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