ICST ICS1567M Datasheet

Integrated Circuit Systems , In c.

ICS1567

Differential Output Video Dot Clock Generator

General Description

The ICS1567 is a very high performance monolithic PLL frequency synthesizer. Utilizing ICS’s advanced CMOS mixed-mode technology, the ICS1567 provides a low cost solution for high-end video clock generation, and for telecom system clock generation.

The ICS1567 has di ffer enti al vi deo cloc k ou tpu ts (C LK and CLK) that are compatible with industry standar d video DACs & RAMDACs. An additional clock output,

LD, is provided, whose frequency is divided down from the main clock by a prog rammable divider.

Operating frequencies are selectable from a pre-programmed (customer -defined) table. An on-c hip crystal oscillator for generati ng th e re fe rence fre que ncy is provi de d on the ICS1567.

Programming of the ICS1567 is acc om pl is he d vi a f re quen cy select pins on the package. The ICS1567 has five lines plus a STROBE pin which permits selection of 32 fr equencie s. Reset of the pipel ine delay on Brooktree RAMDACs is auto matically performed on a rising edge of the STROBE line.

Features

•• High frequency operation for extended video modes - up

to 180 MHz

•• Compatible wit h Brooktr ee high perform anc e RAMDAC s

a) Differenti al output clocks wi th ECL logic leve ls b) Programmable divider modulus fo r loa d clock c) Circuitry included for automatic reset of Brooktree

RAMDAC pipeline delay

•• Low cost - el imina tes ne ed fo r mul tiple ECL c ryst al cloc k

oscillators in video disp lay syste ms

•• Strobe d/ Tr ansparent frequency selec t op ti on s

•• 32-user selected mask-programmable frequencies

•• Fast acquisition of selected frequencies, strobed or non-

strobed

•• Advanced PL L for low ph ase -j itte r

•• Dynamic c ont rol of VC O se nsi ti vit y p rovi di ng o ptimized

loop gai n ove r entire freque ncy range

•• Small footprin t - 16-pin wide body (300 mil) SOIC

FS0 1 16 FS1 XT AL1 2 15 FS2 XT AL2 3 14 FS3

STROBE 4 13 VDD

VSS 5 12 VDDO VSS 6 11 VDDO

LD 7 10 CLK

FS4 8 9

CLK

ICS1567

Pin Configuration

ICS1567RevB090894

Applications

•• Workstations

•• High-resol ution PC a nd MAC di spla y s

•• 8514A - TMS340X0 system s

•• EGA - VGA - Super VGA video

•• Telecom reference clock generation - suitable for Sonet,

ATM and other data rate s up to 155.52Mb.

16-Pin SOIC

CLK+ CLK−

X1 X2

CRYSTAL OSCILL.

/ R

/ M

/ A

PHASE COMP.

CHARGE

LOOP FILTER

VCO

PRESCALER

DIFF. OUTPUT

DRIVER

/ 2

/ 4

MUX

/ N1

FS0 FS1 FS2 FS3 FS4

STROBE

MUX

ROM

LOAD

Figure 1

System Schematic

116 215 314 413 512 611 710 89

FS0

XT AL

STROBE

LOAD FS4

FS1 FS2 FS3

CLK CLK

DDO

C3.1C2.1C1+

ICS1567

Figure 2

Block Diagram

ICS1567

Typical Output Configuration

Pin Description

PIN NUMBER PIN SYMBOL TYPE DESCRIPTION

• FS0

Frequency Select LSB.

XTAL1

Crystal Inte rfa ce /E xter na l Oscill a tor Input .

XTAL2

OUT

Crystal Inte rfa ce .

• STROBE

Control Fo r Frequency Sel e ct Lat ch , also performs automati c RAMDAC reset.

VSS

Device Ground (Both pins mu st be conne cte d.)

VSS

Device Ground (Both pins mu st be conne cte d.)

OUT

Load Output. This output is at CL K fre quency divi de d by N 1 .

• FS4

Frequency Select MSB.

CLK

OUT

Clock Out put Inve rt ed .

CLK

OUT

Clock Output Non-In ve rted.

11 VDDO

Output Stage Powe r (Bot h pins must be conn ect ed ).

VDDO

Output Stage Powe r (Bot h pins must be conn ect ed ).

VDD

PLL System Power.

• FS3

Frequency Select.

• FS2

Frequency Select.

• FS1

Frequency Select.

• = inputs with internal pull- up re sisto r

Notes: CLK &

CLK outputs are pseudo-ECL. Logic low level is set by the ratio of the resistor s stacked acr o s s the power suppl y

= (V suppl y • 160)/(110 +160) in the example shown above.

The above val ue s are a good sta rt in g poi nt fo r RAMDAC or clo ck gen er at or i nte rf ac e .

Figure 3

ICS1567

Circuit Description

Overview

The ICS1567 is design ed to provide the gra phics system clock signals require d by industry standa rd RAMDACs. One of 32 pre-progr amm ed (user -de fina ble) freque nci es ma y be sel ecte d under digital control. Fully programmable feedback and reference divider capability allow virtually any frequency to be genera ted, n ot just simpl e m ultip les of the re fere nce freque ncy. The ICS1567 uses the latest ge neration of fre quency synthesis technique s deve loped b y ICS and is comp letel y suitabl e for the most dem an din g vid eo app li ca tions.

Digital Inputs

The FS0-FS4 pins and the STROB E pin are used to select the desired ope ra ting fr eq ue nc y fro m the 32 pr e- prog ra mme d f requencies in the ROM tabl e of the ICS1567. The STR OBE pi n also controls activation of the pipeline delay RESET function included in the ICS1567 (see PIPELINE DELAY RESET section for details). The FS0 -FS4 and STROBE pins are each equipped wit h a pull-up and will be at a logic HIGH level whe n not connected.

Transpa rent Mode - When the STROBE pin is held HIGH, the FS0 through FS4 inputs are transparent; that is, they directly access the ROM table. The synthesizer will output the frequency programmed into the location addressed by the FS0-FS4 pins.

Latched Mode - When the STROBE pin is held LOW, the FS0-FS4 pins are ignored. The synthesizer will output the frequency correspon ding t o the st ate of t he FS0-FS4 pins when the STROB E pin was last H IGH. In the event tha t the ICS1567 is powered-up with the STROBE pin held LOW, the synthesizer wi ll output t he frequ ency pro grammed into add ress 0 (i .e., the one selected wit h FS0 throug h FS4 at a log ic LOW level).

Frequency Synthesizer Description

Refer to Figure 1 for a block diagram of the ICS1567. The refere nce freque nc y i s gen erated by an o n-chip crysta l osci ll ator , or the re ferenc e fr eq uency may be appli e d to the ICS156 7 from an external frequency source.

The ICS1567 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be rati ometrical ly related to th e reference frequency pr ovided to the PLL. The phase -fre qu en cy detector sh own in th e bloc k diagram drive s the VCO to a frequency that wi ll cause the two inpu ts t o t he phas e-freq uen cy de tec tor t o b e ma tched in frequency a nd phase. This oc curs when:

F(XTAL1) • Feedback Divider

F(vco) =

Reference Divider

This expression is exact; that is, the accuracy of the output frequen cy depends sol e ly on the re fe rence frequency provided to the part (assuming correctly-programmed dividers). The divider progr amm in g is one of the fu ncti ons pe rfor med by the ROM look-up table in the ICS1567. The VCO gain is also ROM programmable which permits the ICS1567 to be optimized for be st performa nc e a t ea ch fre que ncy in the tabl e.

The feedback divider makes use of a dual-modulus prescaler technique that allows construction of a program ma ble count e r to operate at high speeds while still allowing the feedback divider to be progr ammed in steps of 1. This is an improvement over conventional fixed prescaler architectures that typically impose a factor -of -fou r pena lt y (or lar g er) in this respect.

A p ost-divide r may b e insert ed betwe en the VCO and t he CLK and

CLK outputs of the ICS1567. This is useful in generation

of lower frequencies, as the VCO has been optimized for high-frequency ope ration. Different post-divide r settings m a y be used for each frequenc y in the table.

ICS1567

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