ICST ICS1531Y-100, ICS1531Y-140, ICS1531Y-165 Datasheet

ICS1531 Rev N 12/1/99 December, 1999

December 8, 2000 2:31pm

PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

Integrated Circuit Systems, Inc.

Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 1531

Document Type: Data Sheet

Document Stage: Preliminary Product Preview

Features

•

3-channel 8-bit analog-to-digital conversion up to 165 MHz

•

Direct connection to analog input data (no external pre-amplifier circuit needed)

•

Video amplifier: 500-MHz analog bandwidth, software-adjustable gain

•

Dynamic Phase Adjust (DPA) for software-adjustable analog sample points

•

Software selectable: One pixel per clock (for 24-bit pixels) or two pixels per clock (for a total of 48 bits)

•

Internal clamp circuit. Very low jitter.

•

Low-voltage TTL clock outputs, synchronized with digital pixel data outputs

•

Independent software reset for PLLs and DPA

•

Double-buffered PLL and DPA control registers

•

Two additional PLLs with spread spectrum for memory and panel clock

•

External/internal loop-filter selection with software

•

Automatic Power-On Reset (POR) detection

•

Uses 3.3 VDC. Digital inputs are 5-V tolerant.

•

Industry-standard 2-wire serial bus interface speeds: low (100 kHz), high (400 kHz), or ultra (800 kHz)

•

Lock detection available in hardware and software

•

144-pin low-profile quad flat pack (LQFP) package

Applications

•

LCD displays, LCD projectors, plasma displays, and projection TVs

General Description

The ICS1531 is a high-performance, cost-effective, 3-channel, 8-bit analog-to-digital converter with an integrated line-locked clock generator. It is part of a family of chips intended for high-resolution video applications that use analog inputs, such as LCD monitors, LCD projectors, plasma displays, and projection TVs. Using ICS's low-voltage CMOS mixed-signal technology, the ICS1531 is an effective data-capture solution for resolutions from VGA to UXGA.

The ICS1531 offers analog-to-digital data conversion and synchronized pixel clock generation at speeds of 100, 140, or 165 MHz (or mega samples per second, MSPS). The Dynamic Phase Adjust (DPA) circuitry allows end-user control over the pixel clock phase, relative to the recovered sync signal and analog pixel data. Either the internal pixel clock can be used as a capture clock input to the analog-to-digital converters or an external clock input can be used. The ICS1531 provides either one or two 24-bit pixels per clock. An ADCSYNC output pin provides recovered HSYNC from the pixel clock phase-locked-loop (PLL) divider chain output, which can be used to synchronize display enable output.

A clamp signal can be generated internally or provided through the CLAMP pin. A high-bandwidth video amplifier with adjustable gain allows fine tuning of the analog signal. The advanced PLL uses an internal programmable feedback divider. Two additional, independent programmable PLLs, each with spread-spectrum functionality, support memory and panel clock requirements.

ICS1531 Functional Block Diagram

PLL DPA

PLL

Spread Spectrum

POR

Serial IF

PLL

ADC

Crystal

Oscillator

Red

Green

Blue

HSYNC

SDA

SCL

XTAL In

XTAL Out

RA0-RA7 RB0-RB7

GA0-GA7 GB0-GB7

BA0-BA7 BB0-BB7

MCLK

PNLCLK

REF

ADCRCLK

ADC

VSYNC

Spread Spectrum

CLAMP

ADCSYNC

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Table of ContentsICS1531 Data Sheet - Preliminary

Table of Contents

Section Title Page

Chapter 1 Abbreviations and Acronyms...............................................................................................................3

Chapter 2 Summary ...........................................................................................................................................4

Chapter 3 Pin Diagram and Listings .....................................................................................................................9

Chapter 4 Functional Blocks................................................................................................................................19

Chapter 5 Application Overview ..........................................................................................................................22

Chapter 6 Register Set .........................................................................................................................................23

Chapter 7 Programming .......................................................................................................................................54

Chapter 8 Layout and Power Considerations ....................................................................................................58

Chapter 9 AC/DC Operating Conditions .............................................................................................................61

Chapter 10 Timing Diagrams................................................................................................................................63

Chapter 11 VCO Transfer Characteristic.............................................................................................................70

Chapter 12 Package Dimensions.........................................................................................................................71

Chapter 13 Ordering Information.........................................................................................................................73

Chapter 1 Abbreviations and Acronyms

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Chapter 1 Abbreviations and Acronyms

Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet.

Table 1-1.

Abbreviations and Acronyms

Abbreviation /

Acronym

Interpretation

ADC analog-to-digital converter

ASIC application-specific integrated circuit

BNC Type of connector, named for (“

B

ayonet”) Paul Neill and Carl Concelman

CMOS complimentary metal-oxide semiconductor

DAC digital-to-analog converter

DPA Dynamic Phase Adjust

EMI electro-magnetic interference

FCC (United States) Federal Communications Commission

IF interface

LCD liquid crystal display

LQFP low-profile quad flat pack

LSB least-significant bit

LVTTL low-voltage digital transistor-transistor logic

Max. maximum

Min. minimum

MSB most-significant bit

MSPS mega samples per second

MUX multiplexer

N/A Not Applicable

PC personal computer

PFD phase/frequency detector

PLL phase-locked loop

POR power-on reset

Reg register

RGB red, green, blue

R/W read/write

SXGA super XGA

TTL transistor-transistor logic

Typ. typical

UXGA ultra XGA

VCO voltage-controlled oscillator

VESA Video Electronics Standards Association

VGA video graphics array

XGA eXtended graphics array

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Chapter 2 SummaryICS1531 Data Sheet - Preliminary

Chapter 2 Summary

2.1 Overview

The ICS1531 addresses stringent display system line-locked applications by providing clock signals and digitized pixel data through internal high-performance analog-to-digital converters (ADCs). The ICS1531 is a complete solution for capturing analog red, green, and blue (RGB) signals from personal computers and workstations. It supports data capture for resolutions from VGA (640 × 480) to UXGA (1600 × 1200). The ICS1531 features are described in the following sections.

2.2 Clamp, Video Amplifier, and Analog-to-Digital Circuits (Condition RGB Inputs)

For the following circuits, see Figure 4-3.

2.2.1 Clamp Circuits (Adjust RGB Inputs to ADC Range)

To properly digitize incoming RGB analog signals, the ICS1531 must adjust the signals to the range of the ADC. This adjustment is done by clamping the signal, which both (1) establishes a bottom voltage limit and (2) offsets the signal to align the black level of the incoming signal with the bottom voltage limit. Then the signal is amplified to adjust the top limit to the upper range of the ADC.

The ICS1531 incorporates an internal clamping circuit to generate a clamping signal. Optionally, the CLAMP pin can be used to input an externally generated clamp signal (Reg 30:2). In either case, the polarity of the signal to a clamp can be programmed (Reg 30:3). Typically, the clamp signal is generated by ADCSYNC (the recovered HSYNC timing pulse). The clamp signal is generated during a non-display region of time, when most PC display controllers output a black signal.

2.2.2 Video Amplifier Circuits (Amplify RGB Inputs)

The ICS1531’s video amplifier circuit can directly accept analog RGB input signals from a PC display controller (that is, no external pre-amplifier is required). The video amplifier circuit has three independent 500-MHz video amplifiers for the RGB inputs. To adjust the top level of the signal, this video amplifier circuit can be programmed for a gain of 1.0, 1.2, 1.4, or 1.6 (Regs 31:1-0, 32:1-0, and 33:1-0). As a result, the video amplifier circuit can improve low-amplitude signals and adjust analog input signals for the optimum sampling range of the ADC circuit.

2.2.3 Analog-to-Digital Circuits (Digitize RGB Inputs)

The ICS1531 has high-performance analog-to-digital converters (ADCs) to capture and digitize analog RGB data (Reg 30:7). Low-power CMOS technology is used to create 8-bit ADCs, which are calibrated to align the capture event between (1) the 3 analog input channels and (2) either 3 or 6 digital output channels. The ADC can provide (through Reg 30:6) one of the following:

•

Two 24-bit pixels aligned to a half-rate pixel clock (two-pixels-per-clock mode), which can be used for 48-bit interface panels and image-scaling chips

•

One 24-bit pixel aligned to a full-rate pixel clock (one-pixel-per-clock mode), which can be used for 24-bit-per-pixel applications

In addition, programmable digital-to-analog converters for the R, G, and B inputs fine-tune VRTR, VRTG, and VRTB, the individual R, G, and B maximum reference ‘top’ voltages (Regs 34-36).

Chapter 2 Summary

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ICS1531 Data Sheet - Preliminary

2.3 Phase-Locked Loop (Generates Pixel Clock from Input HSYNC)

The ICS1531 uses a phase-locked loop (PLL) to generate its pixel clock output frequency. A PLL is a closed-loop feedback system that locks an output signal’s phase and frequency to that of a reference input signal’s phase and frequency. In the case of the ICS1531, when its PLL is locked it locks a pixel clock output to that of an HSYNC signal from input video.For a block diagram of the ICS1531 PLL, see Figure 4-1 and Figure 4-2.

2.3.1 Phase/Frequency Detector (Compares Two Input Signals)

The first section of the PLL is the Phase/Frequency Detector (PFD). To use the PLL, first the PFD must be enabled either through hardware control (with a signal from the PDEN pin) or software control (Reg 00:1-0). Once the PFD is enabled, the PFD compares both the phase and frequency of the following two input signals.

•

PFD Input Signal 1:

External HSYNC Signal or Internal Oscillator Signal

The first input to the PFD can be selected from either the external HSYNC signal or the ICS1531 internal crystal oscillator signal (Reg 00:5).

– External HSYNC signal

Typically, one of the input signals to the PFD comes from the HSYNC of a PC display controller. This input HSYNC signal can have a transition time of tens of nanoseconds. Furthermore, if the input HSYNC signal is from a remote source, its pulses can degrade.

A high-performance Schmitt trigger (Reg 00:7-6) conditions the HSYNC pulse before it is input to the PFD. The polarity of this input pulse can be programmed (Reg 00:2). The result of this conditioning is REF, a clean reference clock signal that in comparison to the input HSYNC signal has a short transition time. [For more information on adjusting the HSYNC signal, see Section 2.6, “Dynamic

Phase Adjust (Positions Pixel Clock on Sub-Pixel Basis)”.]

– Internal crystal oscillator

Alternatively, one of the input signals to the PFD can be from the ICS1531 internal crystal oscillator (Regs 07:7-0 and 2C:6-4).

•

PFD Input Signal 2:

Signal from Feedback Loop

The second input to the PFD comes from the output of the PLL feedback loop, which results from the processing that takes place with the charge pump, filter, voltage-controlled oscillator, post-scaler divider, and feedback divider. That is, the PLL output (the signal from the feedback loop) also appears as one of the two inputs to the PFD.

As a result of the comparison of the two input signals, the PFD processes the inputs so there is the proper ratio between them. Then the PFD uses the output to drive a charge pump.

2.3.2 Charge Pump (Boosts Voltage Gain of Signal from PFD)

The charge pump, which is a current-source and current-sink pair, boosts the voltage gain of the signal from the PFD. This PFD signal gain is programmable over a 7-bit range up to 128 µA (Reg 01:2-0).

2.3.3 Loop Filter (Filters Output from Charge Pump)

The loop filter, which is a capacitance and resistance in series, acts as a low-bandpass filter for the frequency output from the charge pump. The ICS1531 can select between either an external loop filter, or more typically, an internal loop filter (Reg 08:0). The advantage of the internal filter is that it can be used for all Video Electronics Standards Association (VESA) timing modes, for ease in manufacturing.

Note:

VESA establishes standard timing specifications for the personal-computer industry. Although many computer manufacturers require that display controllers adhere to the VESA timing specifications, there is no enforcement. As a result, not all display controllers conform precisely to the VESA timing specifications.

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Chapter 2 SummaryICS1531 Data Sheet - Preliminary

2.3.4 Voltage-Controlled Oscillator (Matches Input Signals to PFD)

The voltage level resulting from the output signals from the combined processing by the PFD, charge pump, and loop filter drives the voltage-controlled oscillator (VCO). The VCO uses the level of this input voltage to proportionally adjust its frequency output. This signal is compared to the input to the PFD so that both inputs to the PFD match in both phase and frequency. The VCO can operate up to nearly 600 MHz with a fixed gain. Consequently, the ICS1531 can be optimized for the best performance at all operating frequencies. (For more information on the VCO, see Chapter 11, “VCO Transfer Characteristics”.)

2.3.5 Post-Scaler Divider (Sets Ratio of VCO and Pixel Clock Frequencies)

Using the frequency output from the VCO, the programmable Post-Scaler Divider (PSD) can set the ratio of VCO frequency-to-pixel clock frequency at 2:1, 4:1, 8:1, or 16:1 (Reg 01:5-4). The maximum pixel clock output frequency is therefore 300 MHz. However, for practical applications, the analog-to-digital converter limits this output frequency to either 100, 140, or 165 MHz.

2.3.6 Feedback Divider (Controls Number of Pixel Clocks per HSYNC)

The ICS1531’s internal 12-bit pixel Feedback Divider (Regs 02 and 03) controls the total number of pixel clocks per line (that is, between successive HSYNCs). The total number of pixels per line includes both displayed and non-displayed pixels.

Reg 06:2 can delay the recovered HYSNC signal (that is, ADCSYNC) by one input clock period. This delay has the effect of moving channel ‘A’ data to the ‘B’ channel output pins and the channel ‘B’ data to the ‘A’ channel output pins.

Note:

1. As a starting point to capture analog RGB input from VESA-compliant sources, ICS recommends certain register settings for the software “

*.ics files

” that come with the ICS1531 Register Tool. However, the Register Tool register settings are only a guide. (For more information on the ICS1531 Register Tool and its

*.ics.files

, see the ICS1531 Demo Board Guide.)

2. The display manufacturer must provide a way to optimize the display for the particular display controller in use.

3. If the ICS1531 internal pixel PLL Feedback Divider is not set correctly, it can create visible errors on the display.

4. To adjust the ICS1531 on a sub-pixel basis, see Section 2.6, “Dynamic Phase Adjust (Positions

Pixel Clock on Sub-Pixel Basis)”.

2.4 Analog-to-Digital Converter (Synchronizes Data Capture)

By using the internal 3-channel analog-to-digital converter (ADC), the ICS1531 internally provides the pixel clock needed to synchronize data capture. The pixel clock can be further processed by the Dynamic Phase Adjust. [For more information on the ADC, see Section 2.2.3, “Analog-to-Digital Circuits (Digitize RGB

Inputs)” and Figure 4-3.] For the pixel clock to appear on the CLK pin, the pixel clock output must be

enabled (Reg 06:6).

Chapter 2 Summary

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ICS1531 Data Sheet - Preliminary

2.5 Additional PLLs, with Spread Spectrum (Drive Memory and Panel Data Clocks)

Besides the pixel clock PLL, the ICS1531 has two other independent PLLs for use as needed. Typically, one of the PLLs is used to drive memory clocks (Regs 26–2B and 2D) and the other PLL is used to drive panel data clocks (Regs 20–25 and 2D). Both of these additional PLLs are tailored for the required frequency ranges. Each supports software-controlled spread-spectrum clock dithering to reduce measured electro-magnetic interference (EMI).

2.6 Dynamic Phase Adjust (Positions Pixel Clock on Sub-Pixel Basis)

Most display controllers provide an HSYNC signal that can be used as a reference signal for the pixel clock. However, when this HSYNC signal is used as an input, frequently it has significant jitter that impacts data capture. Furthermore, the analog data stream from the display controller to the ICS1531 has no pixel-rate reference clock.

So that analog pixel data inputs can be properly sampled and digitized, the ICS1531’s pixel PLL tracks the input HSYNC signal and the line-to-line jitter. To provide a properly aligned sampling clock (ADCSYNC) to the ADC blocks, the ICS1531’s Dynamic Phase Adjust (DPA) circuitry can add delays to the pixel clock position. The delay, which occurs in relation to the edge of ADCSYNC (the recovered HSYNC signal), is added in sub-pixel time increments.

Regs 04:5-0, 05:1-0 and 06 are used to program the ICS1531 DPA for a value representing incremental sub-pixel delay units. By choosing the proper value, pixel data to the ICS1531 can be sampled at the optimum time for proper digitization and the best-looking display. Typically, a system’s microcontroller presets this value, based on either a table or proprietary algorithms. The end user can change the value through the system’s on-screen display controls.

Table 2-1 lists the number of possible delay element units that can be used to program to add a delay of up

to one pixel clock period, in increments of either 16, 32, or 64 (Reg 04:5-0 and Reg 5:1-0)

.

Note:

To adjust the ICS1531 on a pixel-by-pixel basis, see Section 2.3.6, “Feedback Divider (Controls

Number of Pixel Clocks per HSYNC)”.

2.7 Automatic Power-On Reset Detection (Automatically Resets ICS1531)

The ICS1531 automatically detects power-on resets. As a result, the ICS1531 resets itself if the supply voltage drops below threshold values. No external connection to a reset signal is required.

2.8 Logic Inputs and Outputs

•

Inputs.

The ICS1531 uses both of the following inputs:

– Analog inputs – Digital inputs. The digital inputs are low-voltage TTL (LVTTL) inputs that operate at 3.3 V. These

LVTTL inputs are also 5-V tolerant. (For inputs that are 5-V tolerant, see Section 3.2.3.10, “List of 5-V

To l e r a n t P i n s ”.)

•

Outputs.

The ICS1531 has high-speed LVTTL clock outputs.

Table 2-1.

Increments for Delay Element Units

Number of

Delay Element Units

Pixel Clock Range, MHz

16 55 260 32 27 130 64 14 64

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Chapter 2 SummaryICS1531 Data Sheet - Preliminary

2.9 Industry-Standard 2-Wire Serial Interface

To access all its registers, the ICS1531 uses an industry-standard 2-wire serial interface that operates at one of the following speeds:

•

A low speed of 100 kHz

•

A high speed of 400 kHz

•

An ultra speed of 800 kHz

For use with the 2-wire serial interface, the ICS1531 has 5 V-tolerant inputs. The ICS1531 can use either of two unique, alternative sets of addresses. Table 2-2 lists the addresses that can be used, depending on the state of the SBADR pin.

2.10 Programmable Outputs

For general-purpose outputs, the ICS1531 provides three programmable pins, PSEL3, PSEL2, PSEL1 (Reg 37:2-0).

Table 2-2.

ICS1531 Address Sets

Addresses in

Address Set

Address Set 1.

(SBADR Pin Is Low)

Address Set 2.

(SBADR Pin Is High)

7-bit device address 24h 25h

8-bit read address 49h 4Bh

8-bit write address 48h 4Ah

Chapter 3 Pin Diagram and Listings

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ICS1531 Data Sheet - Preliminary

Chapter 3 Pin Diagram and Listings

3.1 Pin Diagram for ICS1531

Figure 3-1 shows the pin diagram for the ICS1531, which is packaged in a 144-pin low-profile quad flat

pack (LQFP).

Figure 3-1. Pin Diagram

V S S Q A D C

7 2

G A 2

7 1

G A 3

7 0

G A 4

6 9

G A 5

6 8

G A 6

6 7

G A 7

6 6

V D D Q A D C

6 5

V S S Q A D C

6 4

G B 0

6 3

G B 1

6 2

G B 2

6 1

G B 3

6 0

G B 4

5 9

G B 5

5 8

V D D Q A D C

5 7

V S S Q A D C

5 6

A D C S Y N C

5 5

A

D C R C L K

5 4

V D D D A D C

5 3

V S S D A D C

5 2

G B 6

5 1

G B 7

5 0

B A 0

4 9

B A 1

4 8

B A 2

4 7

B A 3

4 6

V D D Q A D C

4 5

V S S Q A D C

4 4

B A 4

4 3

B A 5

4 2

B A 6

4 1

B A 7

4 0

B B 0

3 9

B B 1

3 8

V D D Q A D C

3 7

VDDXTL 108

XOUT 107

XIN 106

VSSXTL 105

PNLC LK 104

VDD PCLK 103

VSSPCLK 102

MC LK 101

VDDMCLK 100

VSSMCLK 99

NC 98 NC 97

VSSAADC 96

RA0 95 RA1 94 RA2 93 RA3 92 RA4 91 RA5 90

VDDQADC 89

VSSQADC 88

RA6 87 RA7 86 RB0 85 RB1 84 RB2 83 RB3 82

VDDQADC 81

VSSQADC 80

RB4 79 RB5 78 RB6 77 RB7 76 GA0 75 GA1 74

VDDQADC 73

1 0 9

V D D Q

1 1 0

V S S Q

1 1 1

S T A T U S

1 1 2

R E F

1 1 3

O S C O U T

1 1 4

C L

K

1 1 5

R e

s e r

v e d

1 1 6

V S S S U B

1 1 7

N C

1 1 8

N C

1 1 9

N C

1 2 0

N C

1 2 1

N C

1 2 2

N C

1 2 3

N C

1 2 4

N C

1 2 5

N C

1 2 6

N C

1 2 7

N C

1 2 8

N C

1 2 9

N C

1 3 0

N C

1 3 1

N C

1 3 2

N C

1 3 3

N C

1 3 4

V D D A

1 3 5

V S S A

1 3 6

N C

1 3 7

S C L

1 3 8

S D A

1 3 9

V S S D

1 4 0

V D D D

1 4 1

P D E N

1 4 2

S B A D R

1 4 3

X F I

L R

E T

1 4 4

E X T F I

L

1 VSS 2 TRESET 3 VSS 4NC 5 VSS 6 HSYNC 7 VSSSUB 8 PSEL1

9 PSEL2 10 PS EL3 11 N C 12 VS S(TEST) 13 VS SSUB 14 Reserved 15 AR ED 16 VRT R 17 VR B 18 NC 19 AG RN 20 VRT G 21 Reserved 22 AB LUE 23 VRT B 24 VD DAADC 25 VS SAADC 26 VS SAADC 27 VD DAADC 28 CLA MP 29 VD DQADC 30 BB 7 31 BB 6 32 BB 5 33 BB 4 34 BB 3 35 BB 2 36 VS SQADC

IC S 1 5 3 1

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Chapter 3 Pin Diagram and ListingsICS1531 Data Sheet - Preliminary

3.2 Pin Listings

Note:

1. The TRESET pin (pin 2) was formerly a Reserved pin.

2. The following pins, formerly ‘Reserved’, are now NC (No Connect): 4, 11, 18, 97–98, 117–133, 136

3. The (active-low) STATUS pin (pin 111) was formerly called ‘LOCK’

3.2.1 Pin Listing by Pin Number

Table 3-1.

ICS1531 Pins, by Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 VSS 37 VDDQADC 73 VDDQADC 109 VDDQ

2 TRESET 38 BB1 74 GA1 110 VSSQ

3 VSS 39 BB0 75 GA0 111 STATUS

4 NC 40 BA7 76 RB7 112 REF

5 VSS 41 BA6 77 RB6 113 OSCOUT

6 HSYNC 42 BA5 78 RB5 114 CLK

7 VSSSUB 43 BA4 79 RB4 115 Reserved

8 PSEL1 44 VSSQADC 80 VSSQADC 116 VSSSUB

9 PSEL2 45 VDDQADC 81 VDDQADC 117 NC

10 PSEL3 46 BA3 82 RB3 118 NC

11 NC 47 BA2 83 RB2 119 NC

12 VSS(TEST) 48 BA1 84 RB1 120 NC

13 VSSSUB 49 BA0 85 RB0 121 NC

14 Reserved 50 GB7 86 RA7 122 NC

15 ARED 51 GB6 87 RA6 123 NC

16 VRTR 52 VSSDADC 88 VSSQADC 124 NC

17 VRB 53 VDDDADC 89 VDDQADC 125 NC

18 NC 54 ADCRCLK 90 RA5 126 NC

19 AGRN 55 ADCSYNC 91 RA4 127 NC

20 VRTG 56 VSSQADC 92 RA3 128 NC

21 Reserved 57 VDDQADC 93 RA2 129 NC

22 ABLUE 58 GB5 94 RA1 130 NC

23 VRTB 59 GB4 95 RA0 131 NC

24 VDDAADC 60 GB3 96 VSSAADC 132 NC

25 VSSAADC 61 GB2 97 NC 133 NC

26 VSSAADC 62 GB1 98 NC 134 VDDA

27 VDDAADC 63 GB0 99 VSSMCLK 135 VSSA

28 CLAMP 64 VSSQADC 100 VDDMCLK 136 NC

29 VDDQADC 65 VDDQADC 101 MCLK 137 SCL

30 BB7 66 GA7 102 VSSPCLK 138 SDA

31 BB6 67 GA6 103 VDDPCLK 139 VSSD

32 BB5 68 GA5 104 PNLCLK 140 VDDD

33 BB4 69 GA4 105 VSSXTL 141 PDEN

34 BB3 70 GA3 106 XIN 142 SBADR

35 BB2 71 GA2 107 XOUT 143 XFILRET

36 VSSQADC 72 VSSQADC 108 VDDXTL 144 EXTFIL

Chapter 3 Pin Diagram and Listings

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ICS1531 Data Sheet - Preliminary

3.2.2 Pin Listing by Alphabetical Pin Name

Note:

1. The TRESET pin was formerly a Reserved pin.

2. The following pins, formerly ‘Reserved’, are now NC (No Connect): 4, 11, 18, 97–98, 117–133, 136

3. The (active-low) STATUS pin was formerly called ‘LOCK’.

Table 3-2.

ICS1531 Pins, by Alphabetical Pin Name

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

ABLUE 22 GB3 60 SDA 138

ADCRCLK 54 GB4 59 STATUS 111

ADCSYNC 55 GB5 58 TRESET 2

AGRN 19 GB6 51 VDDA 134

ARED 15 GB7 50 VDDAADC 24, 27

BA0 49 HSYNC 6 VDDD 140

BA1 48 MCLK 101 VDDDADC 53

BA2 47 NC 4, 11, 18, 97–98,

117–133, 136

VDDMCLK 100

BA3 46 VDDPCLK 103

BA4 43 OSCOUT 113 VDDQ 109

BA5 42 PDEN 141 VDDQADC 29, 37, 45, 57,

65, 73, 81, 89

BA6 41 PNLCLK 104

BA7 40 PSEL1 8 VDDXTL 108

BB0 39 PSEL2 9 VRB 17

BB1 38 PSEL3 10 VRTB 23

BB2 35 RA0 95 VRTG 20

BB3 34 RA1 94 VRTR 16

BB4 33 RA2 93 VSS 1, 3, 5

BB5 32 RA3 92 VSSA 135

BB6 31 RA4 91 VSSAADC 25, 26, 96

BB7 30 RA5 90 VSSD 139

CLAMP 28 RA6 87 VSSDADC 52

CLK 114 RA7 86 VSSMCLK 99

EXTFIL 144 RB0 85 VSSPCLK 102

GA0 75 RB1 84 VSSQ 110

GA1 74 RB2 83 VSSQADC 36, 44, 56, 64,

72, 80, 88

GA2 71 RB3 82

GA3 70 RB4 79 VSSSUB 7, 13, 116

GA4 69 RB5 78 VSS(TEST) 12

GA5 68 RB6 77 VSSXTL 105

GA6 67 RB7 76 XFILRET 143

GA7 66 REF 112 XIN 106

GB0 63 Reserved 14, 21, 115 XOUT 107

GB1 62 SBADR 142

GB2 61 SCL 137

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Chapter 3 Pin Diagram and ListingsICS1531 Data Sheet - Preliminary

3.2.3 Pin Listing by Functional Grouping

3.2.3.1 Clock Pins

For more information on the clock pins, see Figure 4-2 and Figure 4-3.)

Table 3-3.

Clock Pins

Name

Typ e

Pin Description

ADCRCLK Input or

Output

Analog-to-Digital Converter Reference Clock.

•

This pin outputs a half-rate pixel clock for latching digital output pixel data.

•

Typically, this pin connects to an LCD panel controller/scaler.

•

In this table, see also CLK.

ADCSYNC Input or

Output

Analog-to-Digital Converter Sync.

•

This pin provides a recovered HSYNC signal (that is, an HSYNC signal conditioned by a Schmitt trigger) that aligns to ADCRCLK.

•

For some previous ICS chips, the ADCSYNC pin is called FUNC.

CLK Output

Clock.

•

This pin outputs the full-rate pixel clock for latching digital output pixel data.

•

In this table, see also ADCRCLK.

HSYNC Input

Horizontal Sync.

(See Table 3-6.)

MCLK Output

Memory Clock.

•

This pin provides an independent user-programmable clock source.

•

Typically, this pin is used by LCD panel controller/scaler chips or microcontrollers.

OSCOUT Output

Oscillator Output.

•

This output from this pin is from a crystal oscillator.

•

The output frequency is one of the following: – The same frequency as the input frequency to the crystal oscillator – The frequency that results when the input frequency is divided by a programmable

value

PNLCLK Output

Panel Clock.

•

This pin provides an independent user-programmable clock source.

•

Typically, this pin is used by LCD panel controller/scaler chips or microcontrollers.

REF Output

Reference.

This pin provides various reference line clock sync signals.

SCL Input

Serial Clock.

(See Table 3-7.)

XIN Input

Crystal Input.

This pin accepts input from one of the following:

•

A 14.31818-MHz crystal

•

An external clock source

XOUT Output

Crystal Output.

Do one of the following with this pin:

•

Connect it to a 14.31818-MHz crystal.

•

Leave it open for an external clock source.

Chapter 3 Pin Diagram and Listings

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ICS1531 Data Sheet - Preliminary

3.2.3.2 Control Pins

Table 3-4.

Control Pins

Name

Typ e

Pin Description

CLAMP Input

Clamp.

This pin accepts an external signal that is provided as an alternative to the ICS1531’s internally generated clamp signal.

PSEL1, PSEL2, PSEL3

Output

Programmable Select 1, 2, 3.

These pins are used as general-purpose programmable output pins.

TRESET Input

Test Reset.

When the ICS1531:

•

Is not in Test mode, this pin has no effect.

•

Is placed into Test mode: – This pin acts as a reset that sets the ICS1531 to an initial known state. – For information about the Test mode, in this table see VSS(TEST).

VSS(TEST) Input

Ground (Normal Mode) or Test Mode.

•

Normal Mode.

For the VSS(TEST) pin’s Normal-mode function, see Table 3-4.

•

Tes t Mo de . – When this pin is connected to either VDDA or VDDAADC, the ICS1531 is in Test

mode. As a result, the ICS1531 is set to an initial known state.

– The Test mode overrides whatever the bit setting of Reg 37:3 is, so that the

Calibration Regs 38h to 3Ch are automatically enabled.

– The Test mode bits are intended for use only by ICS.

VSS(TEST)

ICS1531

In Test mode, Test-mode bits are enabled and Calibration Regs 38h to 3Ch are automatically enabled.

VDDA or VDDAADC

Test Mode

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Chapter 3 Pin Diagram and ListingsICS1531 Data Sheet - Preliminary

3.2.3.3 Pixel Data Pins

Figure 3-2 shows the following:

•

The relationship of:

– Outputs from the ICS1531 ADC – To inputs of a 1024 × 768 LCD panel that samples 2 pixels of data with either a 36- or 48-bit data

signal.

•

DA indicates ‘A channel’ pixels, and DB indicates ‘B channel’ pixels.)

For timing information, see Chapter 10, “Timing Diagrams”.

Figure 3-2. Relationship of Outputs from an ICS1531’s ADC to Inputs of 1024 × 768 LCD Panel

Table 3-5.

Pixel Data Pins

Name

Type

Pin Description

ABLUE, AGRN, ARED

Input

Analog Blue, Analog Green, Analog Red.

•

These pins accept analog data for the ADC blue, green, and red channels.

•

Typically, the data for these pins comes from a PC display controller.

BA7 – BA0, GA7 – GA0, RA7 – RA0

Output

Blue (‘A channel’) A7 – A0, Green (‘A channel’) A7 – A0, Red (‘A channel’) A7 – A0.

•

These pins output first blue, green, and red pixel data, respectively.

•

A7 pins reflect most-significant data bits. A0 pins reflect least-significant data bits.

BB7 – BB0, GB7 – GB0, RB7 – RB0

Output

Blue (‘B channel’) B7 – B0, Green (‘B channel’) B7 – B0, Red (‘B channel’) B7 – B0.

•

These pins output second blue, green, and red pixel data, respectively.

•

B7 pins reflect most-significant data bits. B0 pins reflect least-significant data bits.

DB (512,768)

DA (1,1)

DB (1,1) DA (2,1)

DB (1,2)

DA (1,2)

DA (1,3)

DA (1,768)

DB (512,1)

RA7-0 GA7-0 BA7-0

DA (1,1)

RB7-0 GB7-0 BB7-0

DB (1,1)

Chapter 3 Pin Diagram and Listings

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ICS1531 Data Sheet - Preliminary

3.2.3.4 Phase-Locked Loop Pins

Table 3-6 lists the pins for the phase-locked loop circuitry. For a block diagram that shows the function of

these pins, see Figure 4-1.

3.2.3.5 Industry-Standard 2-Wire Serial Bus Pins

Table 3-6.

Phase-Locked Loop Pins

Name

Typ e

Pin Description

EXTFIL Input

External Filter.

This pin works with XFILRET (in this table, see XFILRET) and other components as part of an optional external filter for the pixel phase-locked loop.

HSYNC Input

Horizontal Sync.

•

This 5-V tolerant pin is the clock input for the pixel PLL.

•

Typically this pin is connected to the HSYNC from a PC display controller.

•

In this data sheet, this HSYNC signal is also called ‘input HSYNC’.

LOCK Output In this table, see the ‘STATUS’ pin name.

PDEN Input

Phase-Detector Enable.

This pin is the input for the Phase/Frequency Detector enable that can suspend the charge pump activity. It is 5-V tolerant. (For more information, see Reg 00:1-0 in Section 6.5.1,

“Register 00h: Input Control Register”.)

STATUS Output

Status (Formerly called ‘Lock’).

This active-low pin works with Reg 2C:1-0 and Reg 12:3-2. The signal on this pin is:

•

Low when a lock condition occurs for one of the PLLs selected by Reg 2C:1-0 or 12:3-2.

•

High when no lock condition occurs for one of the PLLs selected by Reg 2C:1-0 or 12:3-2.

XFILRET Input

External Filter Return.

This pin works with EXTFIL (in this table, see EXTFIL) and other components as part of an optional external filter for the pixel phase-locked loop.

Table 3-7.

Industry-Standard 2-Wire Serial Bus Pins

Name

Typ e

Pin Description

SBADR Input

Serial Bus Address.

This pin determines the address for the ICS1531 industry-standard 2-wire serial bus.

•

When the signal on this pin is: – Low, the pixel bit address is 49h for read operations and 48h for write operations. – High, the pixel bit address is 4Bh for read operations and 4Ah for write operations.

•

For more information on this pin, see Section 2.9, “Industry-Standard 2-Wire Serial

Interface”.

SCL Input

Serial Clock.

This 5-V tolerant pin is the clock for the interface to an industry-standard 2-wire serial bus.

SDA Input/

Output

Serial Data.

This 5-V tolerant pin connects to the data pin for an industry-standard 2-wire serial bus.

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Chapter 3 Pin Diagram and ListingsICS1531 Data Sheet - Preliminary

3.2.3.6 Ground Pins

Table 3-8.

Ground Pins

Pin Name Pin Description

VSS

Ground for (Analog Inputs for Digital Pixel PLL Circuitry).

•

These pins are used to ground digital portions of the pixel PLL circuitry that receive analog inputs.

•

The VSSD pin must also be connected to these pins.

VSSA

Ground for Analog (Pixel PLL Circuitry).

This pin is used to ground the analog portions of the pixel PLL circuitry.

VSSAADC

Ground for Analog ADC (Circuitry).

These pins are used to ground the analog portions of the ADC.

VSSD

Ground for Digital (Pixel PLL and Circuitry for Industry-Standard 2-Wire Serial Interface).

This pin is used to ground the digital portions of the pixel PLL circuitry and the circuitry for an industry-standard 2-wire serial interface.

VSSDADC

Ground for Digital ADC (Circuitry).

This pin is used to ground the digital portions of the ADC.

VSSMCLK

Ground for Memory Clock (Circuitry).

This pin is used to ground the circuitry for the memory clock PPL (that is, MCLK).

VSSPCLK

Ground for Panel Clock (Circuitry).

This pin is used to ground the circuitry for the panel clock PLL (that is, PNLCLK).

VSSQ

Ground for Output Drivers.

This pin is used to ground output drivers for the pixel PLL circuitry.

VSSQADC

Ground for Output Drivers for ADC.

These pins are used to ground the pixel data output drivers for the analog-to-digital converter.

VSSSUB

Ground for Substrate.

These pins are used to provide ground for the chip substrate.

VSS(TEST)

Ground (Normal Mode) or Test Mode.

•

Normal Mode. – Typically, this pin must be connected to ground (the Normal mode). – When the ICS1531 is in Normal mode, the Calibration registers 38h to 3Ch can be enabled by

using Reg 37:3. (See Section 6.5.39, “Register 37h: PSEL”.)

•

Test Mode. For the VSS(TEST) pin’s Test-mode function, see Table 3-4.

VSSXTL

Ground for Crystal Oscillator.

This pin is used to ground the internal crystal oscillator circuitry.

VSS(TEST)

ICS1531

In Normal mode, use Reg 37:3 to enable Calibration Regs 38h to 3Ch.

Normal Mode

Chapter 3 Pin Diagram and Listings

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ICS1531 Data Sheet - Preliminary

3.2.3.7 Power Pins

Table 3-9.

Power Pins

Pin Name Pin Description

VDDA

(3.3 V) Supply for Analog (Pixel PLL Circuitry).

This pin supplies 3.3 V to the analog portions of the pixel PLL circuitry.

VDDAADC

(3.3 V) Supply for Analog ADC (Circuitry).

These pins supply 3.3 V to the analog portions of the ADC.

VDDD

(3.3 V) Supply for Digital (Pixel PLL and Industry-Standard 2-Wire Serial Bus) Circuitry.

This pin supplies 3.3 V to the digital pixel PLL and circuitry for an industry-standard 2-wire serial bus interface.

VDDDADC

(3.3 V) Supply for Digital ADC (Circuitry).

This pin supplies 3.3 V to digital portions of the ADC.

VDDMCLK

(3.3 V) Supply for Memory Clock.

This pin supplies 3.3 V to the memory clock PLL circuitry.

VDDPCLK

(3.3 V) Supply for Panel Clock.

This pin supplies 3.3 V to the panel clock PLL circuitry.

VDDQ

(3.3 V) Supply for Output Drivers.

This pin supplies 3.3 V to the output driver circuitry for the pixel PLL.

VDDQADC

(3.3 V) Supply for Output Drivers for Analog-to-Digital Converter.

These pins supply 3.3 V to the pixel data output drivers of the ADC.

VDDXTL

(3.3V) Supply for Crystal Oscillator.

This pin supplies 3.3 V to the internal crystal oscillator circuitry.

VRB

Voltage Reference Bottom.

The ADC uses this pin as a bottom reference voltage. Typically, this pin is grounded.

VRTB, VRTG, VRTR

Voltage Reference Top Blue, Green, Red

•

The ADC uses these pins as an alternative to the blue, green, and red top reference voltages from the internal DACs.

•

Each of these pins must connect to its own separate bypass capacitor.

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Chapter 3 Pin Diagram and ListingsICS1531 Data Sheet - Preliminary

3.2.3.8 No-Connect Pins

3.2.3.9 Reserved Pins

3.2.3.10 List of 5-V Tolerant Pins

The following pins are 5-V tolerant:

•

HSYNC (Table 3-6)

•

PDEN (Table 3-6)

•

SCL (Table 3-7)

•

SDA (Table 3-7)

•

TRESET (Table 3-4)

Table 3-10.

No-Connect Pins

Name

Pin Description

NC

No Connect.

Do not connect these pins.

Caution:

Do not connect or use No-Connect pins. Connecting them can affect the performance and operation of the ICS1531 and future members of the ICS153X family.

Tabl e 3- 11 .

Reserved Pins

Name

Typ e

Pin Description

Reserved –

Reserved.

These pins are always reserved for use by ICS.

Caution:

Do not connect or use Reserved pins. Connecting them can affect the performance and operation of the ICS1531 and future members of the ICS153X family.

Chapter 4 Functional Blocks

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ICS1531 Data Sheet - Preliminary

Chapter 4 Functional Blocks

4.1 Pixel PLL Functional Block

Figure 4-1. Pixel PLL Block Diagram

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ICS1531 Rev N 12/1/99 December, 1999

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Chapter 4 Functional BlocksICS1531 Data Sheet - Preliminary

4.2 CLK Functional Block

Figure 4-2. CLK Block Diagram

Phase

Freq

Detector

MUX

Feedback

Divider

Reference

Divider

PNLCL K_PFD

Reg 24:4-2

PNLCLK-M

Reg 20:7-0

PNLCLK -N

Reg 21:7-0

Divide By 2

PN LCLK _Lo ck

Reg 12:2

PNLCLK

(104)

PNLCLK_OSD

Reg 24:1-0

PNLCL K_OE

Reg 25:0

Phase

Freq

Detector

VCO

Output

Scaler

Divider

Feedback

Divider

MCLK

(101)

MCLK_PFD

Reg 2A:4-2

MCLK-M

Reg 26:7-0

MCLK_OSD

Reg 2A:1-0

MCLK-N

Reg 27:7-0

MCLK_OE

Reg 2B:0

Divide By 2

MCLK _Lock

Reg 12:3

Reference

Divider

Crystal

Osc

14.318 MHz

XIN (106)

1

0

CLK_SEL

Reg 25:2

Divide

By 16

ADC_CLK

OSC

VCO

Sprea d

Spectrum

Output

Scaler

Divider

PNLCL K_SS

Reg 24:7-6

PNLCLK_SSENB

Reg 25:1

PNLCLK-SS1

Reg 23:3-0

PNLCLK-SS0

Reg 22:7-0

XOUT (107)

MCLK_SS

Reg 2A:7-6

MCLK-SS1

Reg 29:3-0

MCLK-SS0

Reg 28:7-0

MCLK_SSENB

Reg 2B:1

Divide

By 144

Spread

Spectrum

Chapter 4 Functional Blocks

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ICS1531 Data Sheet - Preliminary

4.3 ADC Functional Block

Figure 4-3. ADC Block Diagram

BB0 - BB7

(39, 38, 35, 34,

33, 32, 31, 30)

ADC_OE

Reg 30:7

ADC_Inv

Reg 30:5

BA0 - BA7

(49, 48, 47, 46,

43, 42, 41, 40)

ADC_OE

Reg 30:7

ADC_Inv

Reg 30:5

GB0 - GB7

(63, 62, 61, 60,

59, 58, 51, 50)

ADC_OE

Reg 30:7

ADC_Inv

Reg 30:5

GA0 - GA7

(75, 74, 71, 70,

69, 68, 67, 66)

ADC_OE

Reg 30:7

ADC_Inv

Reg 30:5

RB0 - RB7

(85, 84, 83, 82,

79, 78, 77, 76)

ADC_OE

Reg 30:7

ADC_Inv

Reg 30:5

RA0 - RA7

(95, 94, 93, 92,

91, 90, 87, 86)

ADC_OE

Reg 30:7

ADC_Inv

Reg 30:5

SET_ADC

Reg 30:4

8

1

0

1

0

1

0

MUX

Half-rate clock (even in 1X mode)

BLUE

ADC BLOCK

GREEN

ADC BLOCK

RED

ADC BLOCK

DQ

Q

1

0

MUX

OE_ADCRCLK

Reg 6:5

1

OE_ADCSYNC

Reg 6:4

0

MUX

1

0

MUX

OE_ADCSYNC

Reg 6:4

ADCRCLK

(54)

Input Func

Input Full-rate clock

ADCSYNC

(55)

ADC_Sel

Reg 30:6

Output-rate clock (1X or 1/2X)

VRTR (16)

ABLUE (22)

AGRN (19)

ARED (15)

VRB (17)

1

0

MUX

CLAMP_Sel

Reg 30:2

Clamp

and Amp

Reference

Voltage

VRTG (20)

VRTB (23)

Clamp

and Amp

Clamp

and Amp

CLAMP

(28)

CLAMP_Pol

Reg 30:3

Reference

Voltage

Reference

Voltage

ADC_CLK

ADC_FUNC

OE_ADCRCLK

Reg 6:5

ADCRCLK_Del

Reg 37:6-5

ADCRCLK_Inv

Reg 37:7

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Chapter 5 Application OverviewICS1531 Data Sheet - Preliminary

Chapter 5 Application Overview

Figure 5-1 shows a basic application for the ICS1531.

Figure 5-1. ICS1531 Application

VSYNC

HSYNC

Red

Green

Blue

ICS1531

15-Pin VGA Connector (Monitor End)

LCD ASIC

•

Recovered HSYNC

•

Pixel Data Clock

•

Pixel Data

•

Panel Clock

•

Memory Clock

Chapter 6 Register Set

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ICS1531 Data Sheet - Preliminary

Chapter 6 Register Set

The tables in this chapter detail the functionality of the bits in the ICS1531 Register Set. The tables include the register locations, the bit positions, names, and definitions, along with their read/write access, reset values, and any special functions or capabilities.

6.1 Reserved Bits

The ICS1531 has a number of reserved bits throughout the Register Set. These bits provide enhanced test functions (intended for use only by ICS manufacturing) and calibration functions (intended for use in production environments).

Important:

The customer must not change the value of reserved bits. If the customer changes the default values of these reserved bits, normal operation of the ICS1531 can be affected.

6.2 Register Set Conventions

Register Set conventions include the following:

•

Bits are listed in the order of most-significant bit (MSB) to least-significant bit (LSB).

•

Unless otherwise indicated, bit settings are listed in terms of digital (and not hexadecimal) values.

•

When a bit definition includes word(s) in parentheses, the word in parenthesis is not part of the bit name,

but is given to explain the origin of the bit’s name.

6.3 Register Set Abbreviations and Acronyms

Table 6-1 lists and defines abbreviations and acronyms used specifically in this chapter. (Table 1-1 lists

other abbreviations and acronyms used throughout this data sheet.)

Table 6-1.

Register Set Abbreviations and Acronyms

Abbreviation

or Acronym

Definition

D-DPA

Double-Buffered / Dynamic Phase Adjust.

Indicates double-buffered registers for which

working registers load during a software Dynamic Phase Adjust reset.

D-MK

Double-Buffered / Memory Clock.

Indicates double-buffered registers for which working

registers load during a software MCLK reset.

D-PK

Double-Buffered / Panel Clock.

Indicates double-buffered registers for which working registers

load during a software PNLCLK reset.

D-PLL

Double-Buffered / Phase-Locked Loop.

Indicates double-buffered registers for which working

registers load during a software pixel PLL reset.

IN-A

Increment All.

Indicates a value that increments with each all-layer revision of the ICS1531.

Reg

Register

R/W

Read/Write

Spec. Func.

Special Function.

Indicates a special function, such as the following (listed in this table):

D-DPA, D-MK, D-PK, D-PLL

ICST ICS1531Y-100, ICS1531Y-140, ICS1531Y-165 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual