ICST GSP9177-01CF52, AV9177-01CF52, ICS9177-01CF52 Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9177

Block Diagram

ICS9177RevB060297P

High Frequency System Clock Generator

The ICS9177 is a multiple output clock generator ideal for
high speed processor system applications. A single high­speed internal VCO is utilized to derive up to four simultaneous
clock output frequencies. This enables output clock skew
matching and the minimization of clock jitter. The internal
VCO operates up to 350 MHz providing edge skew matched
output clocks.

One differential PECL (Positive ECL) output pair provides a
high speed processor clock. 12 TTL clock outputs are also
provided for other system functions, such as bus clocks. Input
selection pins are used to select the TTL output clock
frequencies.

For information about ICS9177 customization optics, please
contact ICS.

• Provides output frequencies up to 175 Mhz

• Internal VCO is divided into four skew-matched output
frequencies (Out A, B, C, D)

• External clock feedback provides input to output skew
matching

• Differential PECL clock output pair provided for high
speed output (Out A)

• 12 TTL clock outputs (for Out B, C, D)

• Single 5 volt power supply voltage

• Internal loop filters

• 52-pin QFP package

Pin Configuration

52-Pin QFP

ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.

2

ICS9177

Pin Description

*Internal pull-up resistor

PIN

NUM-

BER

PIN

NAME

TYPE DESCRIPTION

1 GND
2 REFCLK INPUT from external oscillator

3 FBCLK INPUT

external PLL Feedback path
from one of the OutC
outputs

4 DSEL1# INPUT

PLL divider mode control
(Contains i nter nal pul l-up
resistors)

5 DSEL0# INPUT
6 TESTEN INPUT Test mode ENABLE pin

7 TSTCLK INPUT Ext er na l Test Cl k
8NC

9VCC
10 GND
11 PCOUT1 OUTPUT

TTL - Group 2
Programmable clock output s

12 PCOUT0 OUTPUT
13 GND
14 VCC
15 PBOUT1 OUTPUT

TTL - Group 1
Programmable clock output s

16 PBOUT0 OUTPUT
17 VCC
18 GND
19 PAOUT1 OUT PUT

TTL - Group 0
Programmable clock output s

20 PAOUT0 OUT PUT
21 VCC
22 GND
23 RESETL INPUT Low true divider rese t pin
24 BOUT1 OUTP UT

TTL - 50 MHz out put cl ock

25 BOUT0 OUTP UT
26 VCC
27 GND

PIN

NUM-

BER

PIN

NAME

TYPE DESCRIPTION

28 COUT2 OUTPUT

TTL - 25 MHz output clock

29 COUT1 OUTPUT
30 VCC
31 GND
32 COUT0 TTL - 25 MHz output clock

33 DOUT0

TTL - 12.5 MHz output

clock
34 GND
35 NC

36 AOUT1 OUTPUT

ECL - 100 MHz, 75 MHz or

50 MHz based on DSEL(1:0)

pins

37 AOUT0 OUTPUT
38 NC

39 GND

40

ECL+5V
(same as

VCC)
41 NC
42 NC

43

ANALO-

G +5V
44

ANALO-

G +5V
45 AGND

46 PCSEL1 INPUT

Programmable clock Group
C select

47 PCSEL0 INPUT
48 PBSEL1 INPUT

Programmable clock Group
B select

49 PBSEL0 INPUT
50 PASEL1 INPUT

Programmable clock Group

A select
51 PASEL0 INPUT
52 VC

3

ICS9177

Function Tables

Example of System Block Diagram - Clocking

Table 1: Primary Function Table Typical System Usage

Table 2: CLOCK SELECT Blocks Function Table

Note: x=A, B, or C. (See Figure 1.)

T ypical System Usag e

REF IN

(MHx)

DSEL1# DSEL0# RSTL TEST

f

1

OUT

A

OUT

B

OUT

C

OUT

D

DESCRIPTION

25 0 0 1 0 200 MHz

f/4 f/4 f/8 f/16 Mode 0 - 1/1

25 0 1 1 0 300 M hz

f/4 f/6 f/12 f/24 Mode 1 - 3/2

331010

200/264

MHz

f/2 f/4 f/8 f/16 Mode 2 - 2/1

251110 X 1111Mode 3 - A ll 1

-XX0X X 0000Reset Mode

- 0 0 1 1 TCLK

f/2 f/2 f/4 f/8 Test Mode 0

- 0 1 1 1 TCLK

f/2 f/3 f/6 f/12 Test Mode 1

- 1 0 1 1 TCLK f/1 f/2 f/4 f/8 Test Mode 2

- 1 1 1 1 TCLK f/2 f/2 f/2 f/2 Test Mode 3

PxSEL

1

PxSEL

0

Function of CLOCK SELECT Blocks

0 0 Both outputs at the same frequency as Out B

.

0 1 Both outputs at the same frequency as Out C .
1 0 Both outputs at the same frequency as Out D .
1 1 Both outputs disabled in the high state.