ICST GSP9107C-17CS08, GSP9107C-17CN08, AV9107C-17CN08, AV9107C-17CS08, ICS9107C-17CN08 Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

AV9107C-17

Block Diagram

CPU Frequency Generator

Applications

Computer: The AV9107C-17 is the ideal solution for
replacing high speed oscillators and for reducing clock
speeds to save power in computers. The device provides
smooth, glitch-free frequency transitions so that the CPU
can continue to operate during slow down or speed up. The
rate of frequency change makes the AV9107C-17
compatible with all 386DX, 386SX, 486DX, 486DX2, and
486SX devices.

AV 9107-17 RevC052197P

T he AV9107C-17 offers a tiny footprint solution for
generating two simultaneous clocks. One clock, the
REFCLK, is a fixed output frequency which is the same as
the input reference crystal (or clock). The other clock,
CLK1, can vary between 25.06 and 33.29 MHz.

The device has advanced features which include on-chip
loop filters, tristate outputs, and power-down capability. A
mini-mum of external components - two decoupling
capacitors and an optional ferrite bead - are all that are
required for jitter-free operation.

Patented on-chip Phase-Locked Loop with VCO
for clock generation
Provides reference clock and synthesized clock
Generates frequencies of 25 and 33 MHz
8-pin DIP or SOIC package

14.318 MHz input reference frequency
On-chip loop filter
Low power CMOS technology
Single +3.3 or +5 volt power supply

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AV9107C-17

Pin Descriptions

Pin Configuration

8-Pin DIP, SOIC

Functionality

(at 14.318) MHz reference frequency input)

Frequency Transitions

A key AV9107C-17 f eature is the ability to provide glitch-
free frequency transitions between its output frequencies.

Output Enable

The Output Enable feature tristates the specified output
clock pins. This places the selected output pin in a high
impedance state to allow for system level diagnostic testing.

Absolute Maximum Ratings

AVDD, VDD referenced to GND . . . . . . . . . . . . . . . 7V

Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V

Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect product reliability.

FS CLK1

0
1

25.06 MHz

33.29 MHz

PIN

NUMBER

PIN NAME TYPE DESCRIPTION

1 FS0 Input Frequency Select 0 for CLK1.
2 GND - Digital Ground.
3 X1/ICLK Input Crystal Output or Input Clock frequency. Typically 14.318 MHz system clock.
4 X2 Output Crystal Output (No Connect when clock used.).
5 OE Input Output Enable. Tristates CLK1 and REFCLK when low. Has internal pull-up.
6 CLK1 Output Clock 1 Output (see decoding tables).
7 VDD - Digital power supply (+5V DC).

8 REFCLK Output

Reference Clock output. Produces a buffered version of the input clock or crystal frequency
(typically 14.318 MHz).