ICST GSP1574BM, AV1574BM, AV1574BEB, GSP1574BEB, ICS1574BEB Datasheet

...
Integrated Circuit Systems, Inc.
Description Features
ICS1574B
Block Diagram
User Programmable Laser Engine Pixel Clock Generator
1574B 8/31/00
Supports high resolution laser graphics. PLL/VCO frequency re-programmable through serial interface port to 400 MHz; allows less than ±1.5ns pixel clock resolution.
Laser pixel clock output is synchronized with conditioned beam detect input
Ideal for laser printer, copier and FAX pixel clock applications
On-chip PLL with internal loop filter
On-chip XTAL oscillator frequency reference
Resettable, programmable counter gives glitch-free clock alignment
Single 5 volt power supply
Low power CMOS technology
Compact – 16-pin 0.150" skinny SOIC package
User re-programmable clock frequency supports zoom and gray scale functions
The ICS1574B is a very high performance monolithic phase­locked loop (PLL) frequency synthesizer designed for laser engine applications. Utilizing ICS’s advanced CMOS mixed­mode technology, the ICS1574B provides a low cost solution for high-end pixel clock generation for a variety of laser en­gine product applications.
The pixel clock output (PCLK) frequency is derived from the main clock by a programmable resettable divider.
Operating frequencies are fully programmable with direct control provided for reference divider, feedback divider and post-scaler.
Figure 1
ICS1574B
2
Pin Configuration
16-Pin Skinny SOIC
Pin Descriptions
REBMUNNIPEMANNIPNOITPIRCSED
7KLCP.tuptuokcolclexiP
1NEKLCP.)tupnI(elbanEKLCP
21LATX .tupniycneuqerfecnereferlanretxe/1noitcennoclatsyrcztrauQ
32LATX.2noitcennoclatsyrcztrauQ
4KLCTAD.)tupnI(kcolCataD
61ATAD.)tupnI(ataDretsigeRlaireS
51DLOH.)tupnI(DLOH
41tseT).SSVotdetcennocebtsuM(.tseT
11,01,9,8devreseR).tcennoCtoNoD(.devreseR
31DDV.)margaidnoitacilppaeeS.V5+(rewopmetsysLLP
21ODDV.)V5+(rewopegatstuptuO
6,5SSV).detcennocebtsumsniphtoB(.dnuorgeciveD
PCLKEN
XTAL1
XTAL2
DATCLK
VSS
VSS
PCLK
Reserved
(Do Not Connect)
DATA
HOLD
TEST
VDD
VDDO
Reserved
(Connect to VSS))
(Do Not Connect)
(Do Not Connect)
(Do Not Connect)
Reserved
Reserved
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ICS1574B
3
ICS1574B
PCLK Programmable Divider
The ICS1574B has a programmable divider (referred to in Fig- ure 1 as the PCLK divider) that is used to generate the PCLK clock frequency for the pixel clock output. The modulus of this divider may be set to 3, 4, 5, 6, 8, 10, 12, 16 or 20 under register control. The design of this divider permits the output duty factor to be 50/50, even when an odd modulus is se­lected. The input frequency to this divider is the output of the PLL post-scaler described below:
The phase of the PCLK output is aligned with the internal high frequency PLL clock (F
VCO
) immediately after the asser­tion of the PCLKEN input pulse (active low if PCLKEN_POL bit is 0 or active high if PCLKEN_POL bit is 1).
When PCLKEN is deasserted, the PCLK output will complete its current cycle and remain at VDD until the next PCLKEN pulse. The minimum time PCLKEN must be disabled (T
PULSE
) is 1/F
PCLK
.
See Figure 2a for an example of PCLKEN enable (negative polarity) vs. PCLK timing sequences.
Figure 2a
Figure 2b
seulaVK
rediviDKLCPK
32
a45.3
b43
55.4
65.3
a85.5
b85
017
215.6
a615.9
b619
0221
TK = K •T
VCO
Td = LOGIC PROP.DELAY TIME (typically 9ns with a 10pF load on PCLK)
T
VCO
= 1/F
VCO
The resolution of Ton is one VCO cycle.
The time required for a PCLK cycle start following a PCLKEN enable is described by Figure 2b and the following table:
Typical values for Tr and Tf with a 10pF load on PCLK are 1ns.
ICS1574B
4
PLL Post-Scaler
A programmable post-scaler may be inserted between the VCO and the PCLK divider of the ICS1574B. This is useful in generating lower frequencies, as the VCO has been optimized for high-frequency operation. The post-scaler is not affected by the PCLKEN input.
The post-scaler allows the selection of:
VCO frequency
VCO frequency divided by 2
VCO frequency divided by 4
AUX-EN Test Mode
PLL Synthesizer Description — Ratiometric Mode
The ICS1574B generates its output frequencies using phase­locked loop techniques. The phase-locked loop (or PLL) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency pro­vided to the PLL (see Figure 1). The reference frequency is generated by an on-chip crystal oscillator or the reference fre­quency may be applied to the ICS1574B from an external frequency source.
The phase-frequency detector shown in the block diagram drives the voltage-controlled oscillator, or VCO, to a fre­quency that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. This occurs when:
back divider makes use of a dual-modulus prescaler tech­nique that allows the programmable counters to operate at low speed without sacrificing resolution. This is an improve­ment over conventional fixed prescaler architectures that typically impose a factor-of-four (or larger) penalty in this re­spect.
Table 1 permits the derivation of “A & M converter pro- gramming directly from desired modulus.
Digital Inputs
The programming of the ICS1574B is performed serially by using the DATCLK, DATA, and HOLD pins to load an internal shift register.
DATA is shifted into the register on the rising edge of DATCLK. The logic value on the HOLD pin is latched at the same time. When HOLD is low, the shift register may be loaded without disturbing the operation of the ICS1574B. When high, the shift register outputs are trans­ferred to the control registers, and the new programming information becomes active. Ordinarily, a high level should be placed on the HOLD pin when the last data bit is presented. See Figure 3 for the programming sequence.
The PCLKEN input polarity may be programmed under register control via Bit 39.
F
(VCO)
: =
F(XTAL1)
Feedback Divider
Reference Divider
Figure 3
This expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency pro­vided to the part (assuming correctly programmed dividers).
The VCO gain is programmable, permitting the ICS1574B to be optimized for best performance at all operating frequen­cies.
The reference divider may be programmed for any modulus from 1 to 128 in steps of one.
The feedback divider may be programmed for any modulus from 37 through 392 in steps of one. Any even modulus from 392 through 784 can also be achieved by setting the double bit which doubles the feedback divider modulus. The feed-
Output Description
The PCLK output is a high-current CMOS type drive whose frequency is controlled by a programmable divider that may be selected for a modulus of 3, 4, 5, 6, 8, 10, 12, 16 or 20. It may also be suppressed under register control via Bit 46.
Loading...
+ 8 hidden pages