HIT 2SK3133-S, 2SK3133-L Datasheet
2SK3133(L),2SK3133(S)
Silicon N Channel MOS FET
High Speed Power Switching
ADE-208-720 (Z)
Target Specification
1st. Edition
February 1999
Features
• Low on-resistance
R
DS(on)
= 7 mΩ typ.
• Low drive current
• 4 V gate drive device can be driven from 5 V source
Outline
1. Gate
2. Drain
3. Source
4. Drain
1
2
3
4
1
2
3
4
LDPAK
G
D
S
2SK3133(L),2SK3133(S)
2
Absolute Maximum Ratings (Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage V
DSS
30 V
Gate to source voltage V
GSS
±20 V
Drain current I
D
50 A
Drain peak current I
D(pulse)
Note 1
200 A
Body-drain diode reverse drain current I
DR
50 A
Channel dissipation Pch
Note 2
50 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Note: 1. PW ≤ 10 µs, duty cycle ≤ 1%
2. Value at Tc = 25°C
Electrical Characteristics (Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V
(BR)DSS
30——V I
D
= 10 mA, VGS = 0
Gate to source leak current I
GSS
——±0.1 µAVGS = ±20 V, VDS = 0
Zero gate voltege drain current I
DSS
——10µAVDS = 30 V, VGS = 0
Gate to source cutoff voltage V
GS(off)
1.0 — 2.5 V ID = 1 mA, VDS = 10 V
Note 1
Static drain to source on state R
DS(on)
— 7 10 mΩ ID = 25 A, VGS = 10 V
Note 1
resistance — 12 18 mΩ ID = 25 A, VGS = 4 V
Note 1
Forward transfer admittance |yfs| TBD TBD — S ID = 25 A, VDS = 10 V
Note 1
Input capacitance Ciss — TBD — pF VDS = 10V
Output capacitance Coss — TBD — pF VGS = 0
Reverse transfer capacitance Crss — TBD — pF f = 1 MHz
Total gate charge Qg — TBD — nc VDD = 10 V
Gate to source charge Qgs — TBD — nc VGS = 10 V
Gate to drain charge Qgd — TBD — nc ID = 50 A
Turn-on delay time t
d(on)
— TBD — ns VGS = 10 V, ID = 25 A
Rise time t
r
— TBD — ns RL = 0.4 Ω
Turn-off delay time t
d(off)
— TBD — ns
Fall time t
f
— TBD — ns
Body–drain diode forward voltage V
DF
— TBD — V IF = 50 A, VGS = 0
Body–drain diode reverse
recovery time
t
rr
— TBD — ns IF = 50 A, VGS = 0
diF/ dt = 50 A/ µs
Note: 1. Pulse test
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