HIT 2SK3133-S, 2SK3133-L Datasheet

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HIT 2SK3133-S, 2SK3133-L Datasheet

2SK3133(L),2SK3133(S)

Silicon N Channel MOS FET

High Speed Power Switching

ADE-208-720 (Z)

Target Specification

1st. Edition

February 1999

Features

Low on-resistance RDS(on) = 7 mΩ typ.

Low drive current

4 V gate drive device can be driven from 5 V source

Outline

LDPAK

4

4

 

D

 

 

 

 

1

2

3

 

G

1 2

 

1.

Gate

 

3

 

 

 

 

2.

Drain

 

 

 

3.

Source

 

 

 

4.

Drain

 

S

 

 

 

2SK3133(L),2SK3133(S)

Absolute Maximum Ratings (Ta = 25°C)

Item

Symbol

Ratings

Unit

Drain to source voltage

VDSS

30

V

Gate to source voltage

VGSS

±20

V

Drain current

ID

50

A

 

 

 

 

Drain peak current

Note 1

200

A

ID(pulse)

Body-drain diode reverse drain current

IDR

50

A

Channel dissipation

Pch Note 2

50

W

Channel temperature

Tch

150

°C

 

 

 

 

Storage temperature

Tstg

–55 to +150

°C

Note: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tc = 25°C

Electrical Characteristics (Ta = 25°C)

Item

Symbol

Min

Typ

Max

Unit

 

 

Test Conditions

Drain to source breakdown voltage

V(BR)DSS

30

V

I

D = 10 mA, VGS = 0

Gate to source leak current

IGSS

±0.1

µA

 

 

VGS = ±20 V, VDS = 0

Zero gate voltege drain current

IDSS

10

µA

 

 

VDS = 30 V, VGS = 0

Gate to source cutoff voltage

V

1.0

2.5

V

I

D

= 1 mA, V

DS

= 10 V Note 1

 

GS(off)

 

 

 

 

 

 

 

 

Static drain to source on state

RDS(on)

7

10

m Ω

 

 

ID = 25 A, VGS = 10 V Note 1

resistance

 

12

18

m Ω

 

 

ID = 25 A, VGS = 4 V Note 1

 

 

 

 

 

 

 

 

Forward transfer admittance

|yfs|

TBD

TBD

S

I D = 25 A, VDS = 10 V Note 1

 

 

 

 

 

 

 

 

 

 

 

Input capacitance

Ciss

TBD

pF

V

DS = 10V

 

 

 

 

 

 

 

 

 

 

 

 

 

Output capacitance

Coss

TBD

pF

V

 

GS = 0

 

 

Reverse transfer capacitance

Crss

TBD

pF

f = 1 MHz

 

 

 

 

 

 

 

 

 

 

 

 

Total gate charge

Qg

TBD

nc

V

DD = 10 V

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate to source charge

Qgs

TBD

nc

V

GS = 10 V

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate to drain charge

Qgd

TBD

nc

I

D = 50 A

 

 

 

 

 

 

 

 

 

 

Turn-on delay time

td(on)

TBD

ns

V

 

GS = 10 V, ID = 25 A

Rise time

tr

TBD

ns

R

L = 0.4 Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Turn-off delay time

td(off)

TBD

ns

 

 

 

 

 

 

Fall time

tf

TBD

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Body–drain diode forward voltage

VDF

TBD

V

I

F = 50 A, VGS = 0

Body–drain diode reverse

trr

TBD

ns

I

F = 50 A, VGS = 0

recovery time

 

 

 

 

 

 

 

diF/ dt = 50 A/ µs

Note: 1. Pulse test

2

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