Fairchild Semiconductor 100329APC, 100329ADC Datasheet

© 2000 Fairchild Semiconductor Corporation DS500047 www.fairchildsemi.com

August 1989
Revised August 2000

100329A Low Power Octal ECL/TTL Bidirectional Translator with Register

100329A
Low Power Octal ECL/TTL Bidirectional Translator with

Register

General Description

The 100329A is an o ctal register ed bidirectio nal translator
designed to convert TTL logic levels to 100K ECL logic lev­els and vice versa. The dire ction of the translation is dete r­mined by the DIR input. A LOW on the outp ut enable input
(OE) holds the ECL ou tputs in a cut- off state and the TTL
outputs at a high impedance level. The outputs change
synchronously with the r ising edge of the clock i nput (CP)
even though only one output is enabled at the time.

The cut-off state is designe d to be more negative than a
normal ECL LOW l evel. This allows the output emi tter-fol­lowers to turn off when the termination supply is

−2.0V, pre-

senting a high impedance to the data bus. This high
impedance reduces the termination power and prevents
loss of low state noise margin when several loads share
the bus.

The 100329A is designe d with FAST

 TTL output buffers,

featuring optimal DC drive an d capabl e of quickly cha rging
and discharging highly capacitive loads. All inputs have
50 k

Ω pull-down resistors.

Features

■ Bidirectional translation

■ ECL high impedance outputs

■ Registered outputs

■ FAST TTL outputs

■ 3-STATE outputs

■ Voltage compensated operating range

= −4.2V to −5.7V

■ High drive IOS

Ordering Code:

Logic Symbol

Pin Descriptions

All pins function at 100K ECL levels except for T0–T7.

Connection Diagram

FAST is a registered trademark of Fairc hild Semiconductor Corporation.

Order Number Package Number Package Description

100329APC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Pin Names Description

E

0–E7

ECL Data I/O

T

0–T7

TTL Data I/O
OE Output Enable Input
CP Clock Pulse Input

(Active Rising Edge)
DIR Direction Control Input

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100329A

Truth Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
[N] = LOW-to-HIGH Clock Transit ion
NC = No Change

Functional Diagram

Note: DIR and OE use ECL lo gic lev els

Detail

Note 1: ECL input to TTL out put mode.
Note 2: TTL input to ECL output mode.
Note 3: Retains data present before CP.

OE DIR CP

ECL TTL

Notes

Port Port

L L X Input Z 1, 3
L H X LOW Input 2, 3

(Cut-Off)
HL[N]LL1
HL[N]HH1
HLLXNC1, 3
HH[N]LL 2
HH[N]HH2
HHLNCX2, 3

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100329A

Absolute Maximum Ratings(Note 4) Recommended Operating

Conditions

Note 4: The “Absolute Maximum Ratings” are those value s beyond which

the safety of the dev ice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.

Note 5: ESD testing conforms to MIL-STD-883, Method 3015.
Note 6: Either voltage lim it or c urrent limit is sufficient to pro te c t in puts.

TTL-to-ECL DC Electrical Characteristics (Note 7)

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND, TC = 0°C to +85°C, V

TTL

= +4.5V to +5.5V

Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operation under “worst case” conditions.

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

j

) +150°C

V

EE

Pin Potential to Ground Pin −7.0V to +0.5V

V

TTL

Pin Potential to Ground Pin −0.5V to +6.0V

ECL Input Voltage (DC) V

EE

to +0.5V

ECL Output Current

(DC Output HIGH)

−50 mA

TTL Input Voltage (Note 6)

−0.5V to +6.0V

TTL Input Current (Note 6)

−30 mA to +5.0 mA

Voltage Applied to Output

in HIGH State
3-STAT E Output

−0.5V to +5.5V

Current Applied to TTL Output

in LOW State (Max) twice therated I

OL

(mA)

ESD (Note 5)

≥2000V

Case Temperature (T

C

)0°C to +85°C

ECL Supply Voltage (V

EE

) −5.7V to −4.2V

TTL Supply Voltage (V

TTL

) +4.5V to +5.5V

Symbol Parameter Min Typ Max Units Conditions

V

OH

Output HIGH Voltage −1025 −955 −870 mV VIN = VIH (Max) or VIL (Min)

V

OL

Output LOW Voltage −1830 −1705 −1620 mV Loading with 50Ω to −2V
Cutoff Voltage OE or DIR LOW,

−2000 −1950 mV VIN = VIH (Max) or VIL (Min)
Loading with 50Ω to −2V

V

OHC

Output HIGH Voltage

−1035

mV VIN = VIH (Min) or VIL (Max)

Corner Point HIGH Loading with 50Ω to −2V

V

OLC

Output LOW Voltage

−1610 mV

Corner Point LOW

V

IH

Input HIGH Voltage 2.0 5.0 V Over V

TTL

, VEE, TC Range

V

IL

Input LOW Voltage 0 0.8 V Over V

TTL

, VEE, TC Range

I

IH

Input HIGH Current 70 µAVIN = +2.7V
Breakdown Test 1.0 mA VIN = +5.5V

I

IL

Input LOW Current −700 µAVIN = +0.5V

V

FCD

Input Clamp

−1.2 V I

IN

= −18 mA

Diode Voltage

I

EE

VEE Supply Current LE LOW, OE and DIR HIGH

Inputs OPEN

−189 −94 mA V

EE

= −4.2V to −4.8V

−199 −94 VEE = −4.2V to −5.7V