1. Chapter 2.8 M Relay: Add M1037, M1119, M1182,
M1308, M1346, and M1356, and update the
description of the functions of M1055~M1057and
M1183.
2. Chapter 2.13 Special Data Register: Add D1037,
D1312, D1354, and D1900~D1931, and modify the
attributes of the latched functions of D1062,
D1114, D1115, and D1118.
3. Chapter 2.16 Applications of Special M Relays and
D Registers: Update the description of the
functions of RTCs; add M1037, D1037( Enable SPD
function), M1119( Enable 2-speed ou tput function
of DDRVI instruction) , M1308, D1312( Output
specified pulses or seek Z phase signal when zero
point is achieved) , and M1346( Output clear
signals when ZRN is completed); Easy PLC Link is
changed to PLC Link, and the description is added.
4. Chapter 3.1 Basic Instructions (without API
numbers) and Chapter 3.2 Explanations to Basic
Instructions: Add NP and PN instructions, and add
Chapter 3.7 Numerical List of Instructions (in
alphabetic order)
5. Chapter 3.6 Numerical List of Instructions and
Chapter 3.8 Detailed Instruction Explanation:
Increase explanations of DSPA instruction, and
add floating-point contact type comparison
instructions FLD=, FLD>, FLD<, FLD<>, FLD<=,
FLD>=, FAND=, FAND>, FAND<, FAND<>,
FAND<=, FAND>=, FOR=, FOR>, FOR<, FOR<>,
FOR<=, FOR>=; add the supplementary
description of PLSR instruction and the description
of K11~K19 in DTM instruction mode; update the
description of API166 instruction.
2011/09/15
Issue Description of Changes Date
1. SE is added in the title of the manual.
2. Chapter 2.16: The default value in D1062 is K10.
3. API 15 in Chapter 3: The contents about S<D are
deleted in program example 3.
Third
Edition
4. API 148 and API 149 are added in chapter 3.
5. The information related to DVP-SE is added.
6. The information related to DVP32ES-C is added.
7. The descriptions of the models are added in the
A.1 Installing the USB Driver…………………………………………… …………….................A-2
iii
The DVP-ES2 series PLCs, the DVP-ES2-C series PLCs, the DVP-EX2 series
PLCs, the DVP-SS2 series PLCs, the DVP-SA2 series PLCs, the DVP-SX2
series PLCs, and the DVP-SE series PLCs are listed below.
This chapter introduces basic and advanced concepts of ladder logic, which is the mostly
adopted programming language of PLC. Users familiar with the PLC concepts can move to
the next chapter for further programming concepts. However, for users not familiar with the
operating principles of PLC, please refer to this chapter to get a full understanding of PLC
concepts.
PLC utilizes a standard scan method when evaluating user program.
Scanning process:
Scan input status
Evaluate user program
Refresh the outputs
Input sig nal
Program
Output
Input X
Input terminal
Store to memory
Input signal memory
Read X0 status from memory
X0
Y0
Read Y0 state from memory
Y0
M0
Output latched memory
Read the physical input status and store the data in internal
memory.
Evaluate the user program with data stored in internal memory.
Program scanning starts from up to down and left to right until
reaching the end of the program.
Write the evaluated data to the physical outputs
Input signal:
PLC reads the ON/OFF status of each input and
stores the status into memory before evaluating
the user program.
Once the external input status is stored into
internal memory, any change at the external
inputs will not be updated until next scan cycle
Writ e Y0 stat e into
Device Memory
starts.
Program:
PLC executes instructions in user program from
top to down and left to right then stores the
Write M0 state into
Output
evaluated data into internal memory. Some of this
memory is latched.
Output:
When END command is reached the program
Output terminal
evaluation is complete. The output memory is
transferred to the external physical outputs.
Output Y
Scan time
The duration of the full scan cycle (read, evaluate, write) is called “scan time.” With more I/O or
longer program, scan time becomes longer.
PLC measures its own scan time and stores the value (0.1ms) in register
Read
scan time
Measure
scan time
D1010, minimum scan time in register D1011, and maximum scan time in
register D1012.
Scan time can also be measured by toggling an output every scan and then
measuring the pulse width on the output being toggled.
Scan time can be calculated by adding the known time required for each
Calculate
scan time
instruction in the user program. For scan time information of individual
instruction please refer to Ch3 in this manual.
1-2
1. PLC Concepts
Scan time exception
PLC can process certain items faster than the scan time. Some of these items interrupts and halt
the scan time to process the interrupt subroutine program. A direct I/O refresh instruction REF
allows the PLC to access I/O immediately during user program evaluation instead of waiting until
the next scan cycle.
1.2 Current Flow
Ladder logic follows a left to right principle. In the example below, the current flows through paths
started from either X0 or X3.
X0
X1X2
Y0
Y0
X3
Reverse Current
When a current flows from right to left, which makes a reverse current logic, an error will be
detected when compiling the program. The example below shows the reverse current flow.
Introduction to the basic internal devices in a PLC
Bit memory represents the physical input points and receives external input
X
(Input Relay)
Y
(Output Relay)
M
(Internal Relay)
S
(Step Relay)
signals.
Device indication: Indicated as X and numbered in octal, e.g. X0~X7,
X10~X17…X377
Bit memory represents the physical output points and saves the status to be
refreshed to physical output devices.
Device indication: Indicated as Y and numbered in octal, e.g. Y0~Y7,
Y10~Y17. ..Y377
Bit memory indicates PLC status.
Device indication: Indicated as M and numbered in decimal, e.g. M0, M1,
M2…M4095
Bit memory indicates PLC status in Step Function Control (SFC) mode. If no
STL instruction is applied in program, step point S can be used as an internal
relay M as well as an annunciator.
Device indication: Indicated as S and numbered in decimal, e.g. S0, S1,
S2…S1023
T
(Relay)
(Word)
(Dword)
C
(Counter)
(Relay)
(Word)
(Dword)
D
(Data register)
(Word)
E, F
(Index register)
(Word)
Bit, word or double word memory used for timing
register in it. When its coil is ON and the set time is reached, the associated
contact will be energized. Every timer has its resolution (unit:
1ms/10ms/100ms).
and has coil, contact and
Device indication: Indicated as T and numbered in decimal, e.g. T0, T1,
T2…T255
Bit, word or double word memory used for counting and has coil, contact and
register in it. The counter count once (1 pulse) when the coil goes from OFF to
ON. When the predefined counter value is reached, the associated contact will
be energized. There are 16-bit and 32-bit high-speed counters available for
users.
Device indication: Indicated as C and numbered in decimal, e.g. C0, C1,
C2…C255
Word memory stores values and parameters for data operations. Every
register is able to store a word (16-bit binary value). A double word will occupy
2 consecutive data registers.
Device indication: Indicated as D and numbered in decimal, e.g. D0, D1,
D2…D4999
Word memory used as a modifier to indicate a specified device (word and
double word) by defining an offset. Index registers not used as a m odifier can
be used as general purpose register.
Device indication: indicated as E0 ~ E7 and F0 ~ F7.
1-4
1. PLC Concepts
1.5 Ladder Logic Symbols
The following table displays list of WPLSoft symbols their descripti on, command, and memory
registers that are able to use the symbol.
Basic instructions and API
instructions. Please refer to
chapter 3 Instruction Set
1.5.1 Creating a PLC Ladder Program
The editing of the program should start from the left side bus line to the right side bus line, and from
up to down. However, the right side bus line is omitted when editing in WPLSoft. A single row can
have maximum 11 contacts on it. If more than 11 contacts are connected, a continuous symbol “0”
will be generated automatically and the 12th contact will be placed at the start of next row. The
same input points can be used repeatedly. See the figure below:
X1X2
X0
X12X13
X11
0
X4X5X6X7
X3
X10
C0
C1
0
Y1
When evaluating the user program, PLC scan starts from left to right and proceeds to next row
down until the PLC reaches END instruction. Output coils and basic / application instructions
belong to the output process and are placed at the right of ladder diagram. The sample program
below explains the execution order of a ladder diagram. The numbers in the black circles indicate
the execution order.
1-6
X0X1Y1X4
Y1
M0
X3
M1
T0
M3
TMRT0K10
Execution order of the sample program:
1 LD X0
2 OR M0
3 AND X1
4 LD X3
AND M1
ORB
5 LD Y1
AND X4
6 LD T0
AND M3
ORB
7 ANB
8 OUT Y1
TMR T0 K10
1.5.6 OR / ORI (Connect NO contact in parallel / Connect NC contact in parallel)
OR (ORI) instruction connects a NO (NC) in parallel with another device or block.
OR instruction OR instructionOR instruction
1.5.7 ORP / ORF (Connect Rising edge in parallel/ Connect Falling edge in parallel)
Similar to OR instruction, ORP (ORF) instruction connects rising (falling) edge triggers in parallel
with another device or block
1.5.8 ANB (Connect block in series)
ANB instruction connects a block in series with another block
ANB command
1.5.9 ORB (Connect block in parallel)
ORB instruction connects a block in parallel with another block
ORB instruction
1.5.10 MPS / MRD / MPP (Branch instructions)
These instructions provide a method to create multiplexed output branches based on current result
stored by MPS instruction.
1-8
1. PLC Concepts
Branch
instruction
Branch
Symbol
Description
Start of branches. Stores current result of
MPS
┬
program evaluation. Max. 8 MPS-MPP pairs can
be applied
MRD
MPP
├
└
Reads the stored current result from previous
MPS
End of branches. Pops (reads then resets) the
stored result in previous MPS
Note: When compiling ladder diagram with WPLSoft, MPS, MRD and MPP could be automatically
added to the compiled results in instruction format. However, sometimes the branch instructions
are ignored by WPLSoft if not necessary. Users programming in instruction format can enter branch
instructions as required.
Connection points of MPS, MRD and MPP:
MPS
MPS
MRD
MPP
MPP
Note: Ladder diagram editor in ISPSoft does not support MPS, MRD and MPP instructions. To
achieve the same results as branch instructions, users have to connect all branches to the left
hand bus bar.
WPLSoft
ISPSoft
1.5.11 STL (Step Ladder Programming)
STL programming uses step points, e.g. S0 S21, S22, which allow users to program in a clearer
and understandable way as drawing a flow chart. The program will proceed to next step only if the
previous step is completed, therefore it forms a sequential control process similar to SFC
(Sequential Function Chart) mode. The STL sequence can be converted into a PLC ladder diagram
which is called “step ladder diagram” as below.
Generally, the ladder diagram programming is conducted according to the “up to down and left to
right” principle. However, some programming methods not following this principle still perform the
same control results. Here are some examples explaining this kind of “fuzzy syntax.”
Example 1:
X0X2X4
X5X3X1
Better method OK method
LD X0 LD X0
OR X1 OR X1
LD X2 LD X2
OR X3 OR X3
ANB LD X4
LD X4 OR X5
OR X5 ANB
ANB ANB
The two instruction programs can be converted into the same ladder diagram. The difference
between Better and OK method is the ANB operation conducted by MPU. ANB instruction cannot
be used continuously for more than 8 times. If more than 8 ANB instructions are used continuously,
program error will occur. Therefore, apply ANB instruction after a block is made is the better
method to prevent the possible errors. In addition, it’s also the more logical and clearer
programming method for general users.
Example 2:
X0
Good method Bad method
X1
LD X0 LD X0
OR X1 LD X1
X2
X3
OR X2 LD X2
OR X3 LD X3
ORB
ORB
ORB
The difference between Good and Bad method is very clear. With longer program code, the
required MPU operation memory increases in the Bad method. To sum up, following the general
principle and applying good / better method when editing programs prevents possible errors and
improves program execution speed as well.
Common Programming Errors
PLC processes the diagram program from up to down and left to right. When editing ladder
diagram users should adopt this principle as well otherwise an error would be detected by WPLSoft
when compiling user program. Common program errors are listed below:
1-12
Reverse cur rent
1. PLC Concepts
OR operation upward is not allowed.
“Reverse current” exists.
Output should be connected on top of the
circuit..
Block combination should be made on top of the
circuit..
Parallel connection with empty device is not
allowed..
Parallel connection with empty device is not
allowed.
No device in the middle block.
Devices and blocks in series should be
horizontally aligned
Label P0 should be at the first row of the
complete network.
Correct the circuit of reverse current. The pointed reverse current loops are modified on the right.
X0X1X2
X0
X3
X6
reverse current
X4
X1
X7
X2
X5
X10
LOOP1
Ö
X3X4X5
X6X7X5
X10
X10
LOOP1
Example 6:
Correct the circuit of reverse current. The pointed reverse current loops are modified on the ri ght.
X0
X3
X6
X1
X4
X7
reverse current
X2
X5
X10
LOOP1
X0X1X2
X3X4X5
X6
X3X7X10
Ö
Reverse current
X0
X3
X6
X1
X4
X7
X2
X5
X10
LOOP2
X6
X0X1X7 X10
X4
LOOP1
LOOP
2
1.9 Basic Program Design Examples
Example 1 - Stop First latched circuit
When X1 (START) = ON and X2 (STOP) = OFF, Y1 will be ON.
If X2 is turned on, Y1 will be OFF. This is a Stop First circuit
because STOP button has the control pri ority than START
1-16
Y1
X1
X2
Y1
Example 2 - Start First latched circuit
When X1 (START) = ON and X2 (STOP) = OFF, Y1 will be ON
and latched. If X2 is turned ON, Y1 remains ON. This is a Start
First circuit because START button has the control priority than
STOP
Example 3 - Latched circuit of SET and RST
The diagram opposite are latched circuits consist of RST and
SET instructions.
In PLC processing principle, the instruction close to the end of
the program determines the final output status of Y1. Therefore,
if both X1 and X2 are ON, RST which is lower than SET forms a
Stop First circuit while SET which is lower than RST forms a
Start First circuit.
Example 4 - Power down latched circuit
The auxiliary relay M512 is a latched relay. Once X1 is ON, Y1
retains its status before power down and resumes after power
up.
X1
Y1
Stop first
X1
X2
Start first
X2
X1
X1
X2
M512
1. PLC Concepts
X2
Y1
SET
RST
Y1
Y1
RST
SET
Y1
Y1
M512
SET
RST M 5 12
Y1
Example 5 - Conditional Control
X1
Y1
X2
Y2
X3
X4
Y1
Y1
Y2
X1
X3
X2
X4
Y1
Y2
Because NO contact Y1 is connected to the circuit of Y2 output, Y1 becomes one of the conditions
for enabling Y2, i.e. for turning on Y2, Y1 has to be ON
NC contact Y1 is connected to Y2 output circuit and NC contact Y2 is connected Y1 output circuit.
If Y1 is ON, Y2 will definitely be OFF and vice versa. This forms an Interlock circuit which prevents
both outputs to be ON at the same time. Even if both X1 and X2 are ON, in this case only Y1 will
be enabled.
Example 7 - Sequential Control
X1
Y1
X3
Y2
Y1
Connect NC contact Y2 to Y1 output circuit and
NO contact Y1 to Y2 output circuit. Y1 becomes
one of the conditions to turn on Y2. In addition, Y1
X2
Y2
X4
Y1
Y2
will be OFF when Y2 is ON, which forms an
sequential control process.
Example 8 - Oscillating Circuit
An oscillating circuit with cycle ΔT+ΔT
Y1
Y1
Y1
TT
In the first scan, Y1 turns on. In the second scan, Y1 turns off due to the reversed state of contact
Y1. Y1 output status changes in every scan and forms an oscillating circuit with output cycleΔ
T(ON)+ΔT(OFF)
1-18
Example 9 – Oscillating Circuit with Timer
An oscillating circuit with cycle nT+ΔT
1. PLC Concepts
X0
Y1
TMR
T0
Kn
X0
T0
Y1
Y1
TTn
When X0 = ON, T0 starts timing (nT). Once the set time is reached, contact T0 = ON to enable
Y1(ΔT). In next scan, Timer T0 is reset due to the reversed status of contact Y1. Therefore contact
T0 is reset and Y1 = OFF. In next scan, T0 starts timing again. The process forms an oscillating
circuit with output cycle nT+ΔT.
Example 10 - Flashing Circuit
The ladder diagram uses two timers to form an oscillating circuit which enables a flashing indicator
or a buzzing alarm. n1 and n2 refer to the set values in T1 and T2 and T refers to timer resolution.
X0
T1
X0T1
T2
TMR
Y1
T1
Kn1
T2TMRKn2
X0
Tn2
Y1
T
n1
Example 11 - Trigger Circuit
In this diagram, rising-edge contact X0 generates trigger pulses to control two actions executing
interchangeably.
X0
X0
T
M0
Y1
M0
M0
M0
Y1
Y1
Y1
Example 12 - Delay OFF Circuit
If X0 = ON, timer T10 is not energized but coil Y1 is ON. When X0 is OFF, T10 is activated. After
100 seconds (K1000 × 0.1 sec = 100 sec), NC contact T10 is ON to turn off Y1. Turn-off action is
delayed for 100 seconds by this delay OFF circuit.
The output delay circuit is composed of two timers executing delay actions. No matter input X0 is
ON or OFF, output Y4 will be delayed.
X0
T5
K50
5 secs
T5
T5
Y4
TMR
T6
Y4
Y4
X0
TMR
T6
K30
Example 14 -
Timing extension circuit
X0
TMR
T11
T12
T11
T12TMRKn2
Y1
.
Kn1
The total delay time: (n1+n2)* T. T refers to the
timer resolution.
Timer = T11, T12
Timer resolution: T
Example 15 – Counting Range Extension Circuit
X13
The counting range of a 16-bit counter is 0 ~
32,767. The opposite circuit uses two counters to
increase the counting range as n1*n2. When
value in counter C6 reaches n2, The pulses
counted from X13 will be n1*n2.
C5
X14
C6
CNT
RST
Y1
C5
Kn1
C6CNTKn 2
C5RST
C6
T6
X0
T11
T12
Y1
n1*
T
(n1+n2)*
n2*
T
3 secs
T
T
1-20
Example 16 - Traffic light control (Step Ladder Logic)
Traffic light control