Dell Latitude 7350 Schematics

Vinafix.com

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B

C

D

E

MODEL NAME :

PCB NO :

LA-B331P ( DAA0008K010 )

ZAU70

BOM P/N :

1 1

Dell/Compal Confidential

2 2

ZZZ
MB_PCB

Schematic Document

Crested Butte (Broadwell Y)

3 3

2014-08-13

Rev: 1.0

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P01-Cover Page

P01-Cover Page

P01-Cover Page

LA-9262P

LA-9262P

LA-9262P

E

1 51Wednesda y, August 13, 2014

1 51Wednesda y, August 13, 2014

1 51Wednesda y, August 13, 2014

1.0

1.0

1.0

Vinafix.com

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eDP Panel

1 1

Conn x 2.

Touch Screnn

P.21

P.29

NFGG Slot A-Key A

WLAN
BT
WiGig

NFGG Slot B-Key B

WWAN

2 2

P.24

SATA3.0 / PCIE

P.25

uSIM Conn

NFGG Slot B-Key B

SSD

P.26

eDP 1.3

DP1.2

PCIE *2

USB2.0

USB2.0

SATA3.0

I2C

Intel

Broadwell ULT

BGA 1234 Balls

4.5W TDP

Memory Bus (DDR3L-RS)

Dual Channel

1.35V DDR3L-RS 1600 MHz

USB2.0

USB2.0

USB2.0

I2S

Digital MIC

Channel A
DDR3L-RS 4Gb or 8Gb (x16) * 4

P.14, 15

Channel B
DDR3L-RS 4Gb or 8Gb (x16) * 4

P.16, 17

USH Module :
Smart Card
Finger Print
NFC

Front Camera

Rear Camera

P.29

P.23

P.23

Audio Codec
ALC3263

Headphone Jack

( iPhone & Nokia compatible)

Int. Speaker

Line Out

e-Compass +

Accelerometer

DE303DLHCTR

I2C

Sensor HUB
STM32L151RB

I2C

I2C

I2C Buffer
PCA9511ADP

Analog Switch
TS5A22364

3 3

TX3GD20TR

ALS

CM32181

SPI ROM
8M x2

P.08

SPI

Proximity Sensor

Gyro Sensor

STM8T143

TPM
AT97SC3205

P.27

Page 5 ~ 18

DP1.2

USB3.0

USB2.0

40 Pin
Base
Docking Conn

LPC Bus

SMSC MEC1641

4 4

RTC conn.

DC/DC Interface CKT.

Power Circuit DC/DC

A

P.34

P.30, 31

P.36 ~ 48

B

C

I2C

P.33

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2011/02/23 2013/10/28

2011/02/23 2013/10/28

2011/02/23 2013/10/28

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P02-Block Diagram

P02-Block Diagram

P02-Block Diagram

LA-9262P

LA-9262P

LA-9262P

E

2 51Wednesda y, August 13, 2014

2 51Wednesda y, August 13, 2014

2 51Wednesda y, August 13, 2014

0.1

0.1

0.1

Vinafix.com

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Compal Confidential

Project Code : ZAU70
File Name : LA-B331P

1 1

LS-B331P
Audio Codec and Jack

LS-B332P
Sensor HUB
Volume Up/Down, PWR, Home Key Button

FPC 50 pin

FFC 24 pin

LA-B331P M/B

Camera Cable

Coaxial and Wire

eDP Cable

Coaxial and Wire

Front & Rear Camera

LCD Panel

FFC 8 pin

LS-B333P

FPC 70 pin

DOCK, SIM CARD,DCIN CONN

2 2

3 3

Wire 6 pin

CABLE

9 pin

Battery Pack

FPC

20 pin

USH Module

Touch Panel Control Baor d

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P03-DaughterB block diagram

P03-DaughterB block diagram

P03-DaughterB block diagram

LA-9 262 P

LA-9 262 P

LA-9 262 P

E

3 51Wednesda y, August 13, 2014

3 51Wednesda y, August 13, 2014

3 51Wednesda y, August 13, 2014

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0.1

Vinafix.com

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Board ID Table for AD channel

Ra 100K +/- 5%

3.3V +/- 5%Vcc

0
1
2
3
4
5
6
7

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

NC

VRbBoard ID

min

0 V 0 V

0.168 V

0.375 V

0.634 V

0.958 V

1.372 V

1.851 V

2.433 V

AD_BID typVAD_BID

0.250 V

0.503 V

0.819 V

1.185 V

1.650 V

2.200 V

3.300 V

0.155 V

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

maxAD_BIDV

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

0.3

0.4

0.5

1.0

PCH
USB
Port

SMBUS Control Table

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

MEM_SMBCLK
MEM_SMBDATA

EC_SMB00_CLK
EC_SMB00_DAT

EC_SMB01_CLK
EC_SMB01_DAT

EC_SMB03_CLK
EC_SMB03_DAT

EC_SMB04_CLK
EC_SMB04_DAT

EC_SMB05_CLK
EC_SMB05_DAT

SOURCE

PCH

PCH

MEC1641

MEC1641

MEC1641

MEC1641

MEC1641

Base BATT

V

V

Charger

V

USH

V

XDP

V

Link

Mapping

PCH
DDI

1 1

Port
Mapping

USB PORT#

0

1

2

DESTINATION

Base

Debug Port

Front Camera

3

4

5

6

7

Rear Camera

NGFF (WWAN)

NGFF (WLAN)

USH

DDI PORT# DESTINATION

B

C

Base (mini-DP)

NGFF (WiGig)

DESTINATIONUSB 3.0 PORT#

1

Base

2

3

4

FLEX CLOCKS DESTINATION

CLKOUT_LPC_0

CLKOUT_LPC_1

EC LPC

Debug

SATA PCI EXPRESS

SATA0

SATA1

SATA2

SATA3

DESTINATION

NGFF SSD

NGFF (WWAN)

CLK

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

DESTINATIONDIFFERENTIAL

Lane 1

Lane 2

NGFF (WLAN)

Lane 3

Lane 4

NGFF (WLAN)

NGFF (WWAN)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

A

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Lane 5

Lane 6

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

DESTINATION

NGFF (WLAN)

NGFF (WLAN)

NGFF (WWAN)

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P04-Notes List

P04-Notes List

P04-Notes List

LA-9262P

LA-9262P

LA-9262P

4 51Wednesda y, August 13, 2014

4 51Wednesda y, August 13, 2014

4 51Wednesda y, August 13, 2014

0.1

0.1

0.1

Vinafix.com

5

4

3

2

1

UCPU1A

PCH_DDI1_N028
PCH_DDI1_P028
PCH_DDI1_N128
PCH_DDI1_P128
PCH_DDI1_N228

1 2

RH1 100K_040 2_5%@

1 2

D D

C C

B B

RH2 100K_040 2_5%@

1 2

RH3 1M_0402_ 5%

RH4 1M_0402_ 5%

1 2

1 2

RC4 100K_040 2_5%

+3VS

1 2

RC51 10K_0402 _5%

RP19

1 8
2 7
3 6
4 5

2.2K_080 4_8P4R_5%

RP1

1 8
2 7
3 6
4 5

10K_8P4R_5 %

vPRO@

1 2

RH177 10 0K_0402_5%

nvPRO@

1 2

RH178 10 0K_0402_5%

1 2

RC10 10K_0402 _5%

Avoid stub in the PWRGD path
while placing resistors RC44 & RC53

PCH_DDI1_DAT
PCH_DDI1_CLK
PCH_DDI2_CLK
PCH_DDI2_DAT

GNSS_IRQ_R
WLAN_RST#
TP_INT#
TPM_IRQ#_R

H_CPUPWRGD_R

PCH_GPIO79

VPRO

ENBKL

PCH_ENVDD

PCH_DDI1_HPD

PCH_DDI2_HPD

eDP_HPD

SM_PG_CTRL43

H_PROCHOT#28,33,38 ,39,44

WLAN_RST#24
TPM_IRQ#27

TP_INT#28,33

AUDIO_IRQ22

MEM_CONFIG29

GNSS_IRQ25

+1.05VS_VCCST

RC6
62_0402 _5%

1 2

Width 15 mils, Spacing 25 mils, Length < 500 mil

DDR3 Compensation Signals

+3VS +1.35V_DDR

12

RC17
220K_040 2_5%

12

@

RC18
2M_0402_ 5%

CC1 0.1U_0402_10V7 K@

Base

WiGig

PCH_INV_PWM21
ENBKL21
PCH_ENVDD21,29

1 2

RC50 0_0402_ 5%@

TP_INT#

1 2

RC49 0_0402_ 5%@

H_PECI33

RC8 56_0402_5%

12
12
12

1 2

UC1

5

NC

VCC

4

Y

GND

74AUP1G07GW_ TSSOP5

PCH_MUTE#22

T2@

1 2

RC12200_040 2_1%
RC13121_040 2_1%
RC14100_040 2_1%

1

2

A

3

@

T1

PCH_DDI1_P228
PCH_DDI1_N328
PCH_DDI1_P328

PCH_DDI2_N024
PCH_DDI2_P024
PCH_DDI2_N124
PCH_DDI2_P124
PCH_DDI2_N224
PCH_DDI2_P224
PCH_DDI2_N324
PCH_DDI2_P324

ENBKL
PCH_ENVDD

WLAN_RST#
TPM_IRQ#_R
PCH_GPIO79
VPRO

GNSS_IRQ_R

H_CATERR#

H_PROCHOT#_RH_PROCHOT#

H_CPUPWRGD_R

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
H_DRAMRST#

DDR_PG_CNTL

DDR_PG_CNTL

AD25
AC25
AD26
AC26
AG25
AE25
AG26
AE26

AD22
AC22
AG22
AE22
AD21
AC21
AG21
AE21

UCPU1I

BM41

EDP_BKLCTL

BR42

EDP_BKLEN

BN40

EDP_VDDEN

K35

PIRQA_N_GPIO 77

F31

PIRQB_N_GPIO 78

J34

PIRQC_N_GPI O79

D38

PIRQD_N_GPI O80

B25

PME

M29

GPIO55

L30

GPIO52

F35

GPIO54

H33

GPIO51

C39

GPIO53

BDW_Y_DDR3L_ BGA1234

@

UCPU1B

CF41

PROC_DETECT

CH39

CATERR

CK42

PECI

CH41

PROCHOT

CG42

PROCPWRGD

CV7

SM_RCOMP0

CP7

SM_RCOMP1

CT7

SM_RCOMP2

AB2

SM_DRAMRST

BL14

SM_PG_CNTL1

BDW_Y_DDR3L_ BGA1234

@

DDI1_TXN_0

DDI eDP

DDI1_TXP_0
DDI1_TXN_1
DDI1_TXP_1
DDI1_TXN_2
DDI1_TXP_2
DDI1_TXN_3
DDI1_TXP_3

DDI2_TXN_0
DDI2_TXP_0
DDI2_TXN_1
DDI2_TXP_1
DDI2_TXN_2
DDI2_TXP_2
DDI2_TXN_3
DDI2_TXP_3

BDW_Y_DDR3L_ BGA1234

@

1 OF 20REV = 1

eDP Sideband

PCI

9 OF 20REV = 1

MISC

THERMAL

PWR

DDR3

2 OF 20REV = 1

EDP_DISP_UTIL

JTAG

EDP_TXN0

EDP_TXP0

EDP_TXN1

EDP_TXP1

EDP_TXN2

EDP_TXP2

EDP_TXN3

EDP_TXP3

EDP_AUXN
EDP_AUXP

EDP_RCOMP

Display

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

DDPB_HPD
DDPC_HPD

EDP_HPD

PROC_TCK

PROC_TMS_CN40

PROC_TRST

PROC_TDI

PROC_TDO

AD17
AC17
AG18
AE18
AD18
AC18
AA17
W17

AG16
AE17

AP41
Y21

RC1 Width 20 mils, Spacing 25 mils,
Length < 100 mil

BP43
BN42
BP41
BR40

Y26
Y25
W26
W25

Y30
Y29
W29

PRDY
PREQ

BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7

eDP_TXN_P0 21
eDP_TXP_P0 21
eDP_TXN_P1 21
eDP_TXP_P1 21

eDP_AUXN 21
eDP_AUXP 21

+EDP_COM

RC1 24.9_04 02_1%

EDP_DISP

RC2 0_0402_ 5%@

PCH_DDI1_CLK
PCH_DDI1_DAT
PCH_DDI2_CLK
PCH_DDI2_DAT

PCH_DDI1_HPD
PCH_DDI2_HPD
eDP_HPD

CU40

XDP_PRDY#

CR41

XDP_PREQ#

CM41

CPU_XDP_TCK

CN40

CPU_XDP_TMS

CR39

JTAG_TRST#

CU36

CPU_XDP_TDI

CU38

CPU_XDP_TDO CPU_XDP_TDO

CM39
CN38
CK36
CM37
CN36
CR35
CN34
CR34

closed MCP 1000 mils

XDP_PRDY#
XDP_PREQ#

CPU_XDP_TCK
CPU_XDP_TMS
JTAG_TRST#
CPU_XDP_TDI
CPU_XDP_TDO

1 2

12

PCH_DDI1_CLK 28
PCH_DDI1_DAT 28

PCH_DDI1_AUXN 28
PCH_DDI2_AUXN 24
PCH_DDI1_AUXP 28
PCH_DDI2_AUXP 24

PCH_DDI1_HPD 28
PCH_DDI2_HPD 24

eDP_HPD 21

XDP_PRDY# 19
XDP_PREQ# 19

CPU_XDP_TCK 19
CPU_XDP_TMS 19
JTAG_TRST# 7,19
CPU_XDP_TDI 19
CPU_XDP_TDO 19

XDP_BPM0# 19
XDP_BPM1# 19

T3@
T4@
T5@
T6@
T7@
T8@

+VCCIOA_OUT

PU/PD for JTAG signals

1 2

RC11 51_0402 _5%

Stuffed : Dual TCK

unstuffed : Singel TCK

Stuffed : Single & Dual TCK

CPU_XDP_TCK

JTAG_TRST#

T9@
T10@

T11@
T12@
T13@
T14@
T15@

1 2

RC15 51_0402 _5%

1 2

RC16 51_0402 _5%@

+1.05VS_VCCST

R1d

R2
R9

+1.35V_DDR

A A

H_DRAMRST#

5

1 2

RC20 0_0402_ 5%@

12

RC19
470_040 2_5%

DDR3_DRAMRST# 14,15,16,17

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P05-MCP(1/7) D DI,ED P,PM,XDP

P05-MCP(1/7) D DI,ED P,PM,XDP

P05-MCP(1/7) D DI,ED P,PM,XDP

LA-9262P

LA-9262P

LA-9262P

1

5 51Wednesda y, August 13, 2014

5 51Wednesda y, August 13, 2014

5 51Wednesda y, August 13, 2014

0.1

0.1

0.1

Vinafix.com

5

D D

4

3

2

1

DDR_A_D[0..6 3]14,15

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

UCPU1C

CT17

SA_DQ0

CV17

SA_DQ1

CN14

SA_DQ2

CP15

SA_DQ3

CN16

SA_DQ4

CR16

SA_DQ5

CM13

SA_DQ6

CV15

SA_DQ7

CT13

SA_DQ8

CP13

SA_DQ9

CP10

SA_DQ10

CM10

SA_DQ11

CN12

SA_DQ12

CV13

SA_DQ13

CV10

SA_DQ14

CT10

SA_DQ15

CT25

SA_DQ16

CP25

SA_DQ17

CN22

SA_DQ18

CP23

SA_DQ19

CN24

SA_DQ20

CV25

SA_DQ21

CV23

SA_DQ22

CT23

SA_DQ23

CN20

SA_DQ24

CN18

SA_DQ25

CT21

SA_DQ26

CT19

SA_DQ27

CP19

SA_DQ28

CP21

SA_DQ29

CV19

SA_DQ30

CV21

SA_DQ31

BU2

SA_DQ32

BW2

SA_DQ33

BW6

SA_DQ34

BU4

SA_DQ35

BW4

SA_DQ36

BT3

SA_DQ37

BU6

SA_DQ38

BT5

SA_DQ39

BN2

SA_DQ40

BR2

SA_DQ41

BN6

SA_DQ42

BN4

SA_DQ43

BR6

SA_DQ44

BR4

SA_DQ45

BM5

SA_DQ46

BM3

SA_DQ47

BT11

SA_DQ48

BU10

SA_DQ49

BW12

SA_DQ50

BW10

SA_DQ51

BW8

SA_DQ52

BU8

SA_DQ53

BU12

SA_DQ54

BT9

SA_DQ55

BN8

SA_DQ56

BR8

SA_DQ57

BN12

SA_DQ58

BN10

SA_DQ59

BR12

SA_DQ60

BR10

SA_DQ61

BM11

SA_DQ62

BM9

SA_DQ63

BDW_Y_DDR3L_ BGA1234

@

DDR Channel A

3 OF 20REV = 1

SA_CK#0

SA_CK0

SA_CKE0
SA_CKE1

SA_CS#0
SA_CS#1

SA_ODT0

SA_RAS#

SA_WE#

SA_CAS#

SA_BS0
SA_BS1
SA_BS2

SA_MA0

SA_MA1

SA_MA2

SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7

SA_MA8

SA_MA9

SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
SM_VCCDDQG

NC
NC

NC
NC

CG4
CG2
CC4
CC6

CH11
CH9
CA12
CA10

CA4
CA2
CA6

CE2
CE4
CC8

CB5
CC2
CF11

CE8
CE12
CF5
CE10
CG8
CG6
CH3
CE6
CB9
CC12
CF3
CG12
CH5
CB3
CF9
CG10

CU16
CR12
CR24
CR20
BV3
BP3
BV9
BP9

CT15
CU12
CU24
CU20
BV5
BP5
BV11
BP11

AP13
AU14
AT13
CC14

10 mil trace width

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

M_CLK_A_DDR#0 14,15,18
M_CLK_A_DDR0 14,15,18

DDR_A_CKE0 14,15,18
DDR_A_CKE1 14,15,18

DDR_A_CS0# 14,15,1 8
DDR_A_CS1# 14,15,1 8

DDR_A_RAS# 14,15,18
DDR_A_WE# 1 4,15,18
DDR_A_CAS# 14,15,18

DDR_A_BS0 14 ,15,18
DDR_A_BS1 14 ,15,18
DDR_A_BS2 14 ,15,18

DDR_A_MA[0..15 ] 14,15,18

DDR_A_DQS#[0 ..7] 14,1 5

DDR_A_DQS[0. .7] 14,15

V_DDR_REF_C A 1 8
V_DDR_REFA_R 18
V_DDR_REFB_R 18

DDR_B_D[0..6 3]16,17

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UCPU1D

BK3

SB_DQ0

BK5

SB_DQ1

BG6

SB_DQ2

BJ2

SB_DQ3

BJ4

SB_DQ4

BJ6

SB_DQ5

BG2

SB_DQ6

BG4

SB_DQ7

BF3

SB_DQ8

BF5

SB_DQ9

BC6

SB_DQ10

BE2

SB_DQ11

BE4

SB_DQ12

BE6

SB_DQ13

BC2

SB_DQ14

BC4

SB_DQ15

BE10

SB_DQ16

BC10

SB_DQ17

BE8

SB_DQ18

BC8

SB_DQ19

BF11

SB_DQ20

BC12

SB_DQ21

BE12

SB_DQ22

BF9

SB_DQ23

BJ12

SB_DQ24

BG12

SB_DQ25

BJ8

SB_DQ26

BJ10

SB_DQ27

BG8

SB_DQ28

BG10

SB_DQ29

BK9

SB_DQ30

BK11

SB_DQ31

AM1

SB_DQ32

AH2

SB_DQ33

AJ3

SB_DQ34

AM5

SB_DQ35

AM3

SB_DQ36

AJ1

SB_DQ37

AJ5

SB_DQ38

AH4

SB_DQ39

AG3

SB_DQ40

AG1

SB_DQ41

AD2

SB_DQ42

AE3

SB_DQ43

AE1

SB_DQ44

AG5

SB_DQ45

AD4

SB_DQ46

AE5

SB_DQ47

AM9

SB_DQ48

AM7

SB_DQ49

AH8

SB_DQ50

AJ9

SB_DQ51

AM11

SB_DQ52

AJ7

SB_DQ53

AJ11

SB_DQ54

AH10

SB_DQ55

AE11

SB_DQ56

AG7

SB_DQ57

AE7

SB_DQ58

AE9

SB_DQ59

AG11

SB_DQ60

AG9

SB_DQ61

AD8

SB_DQ62

AD10

SB_DQ63

BDW_Y_DDR3L_ BGA1234

@

DDR Channel B

4 OF 20REV = 1

SB_CK#0

SB_CK0

SB_CKE0
SB_CKE1

SB_CS#0
SB_CS#1

SB_ODT0

SB_RAS#

SB_WE#

SB_CAS#

SB_BS0
SB_BS1
SB_BS2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AW6
AW4
AP11

NC

AP9

NC

BA2
BA4
AR8

NC

AP5

NC

AR10
AT11

AU10

BA10
AW12
AW10

AY11
BA12
AU2

AT9

DDR_B_MA0

AR4

DDR_B_MA1

AU8

DDR_B_MA2

AR6

DDR_B_MA3

AT5

DDR_B_MA4

AT3

DDR_B_MA5

BA8

DDR_B_MA6

AY3

DDR_B_MA7

AW2

DDR_B_MA8

AY5

DDR_B_MA9

AY9

DDR_B_MA10

AU4

DDR_B_MA11

AU6

DDR_B_MA12

AW8

DDR_B_MA13

BA6

DDR_B_MA14

AR2

DDR_B_MA15

BH5

DDR_B_DQS#0

BD5

DDR_B_DQS#1

BD11

DDR_B_DQS#2

BH11

DDR_B_DQS#3

AK2

DDR_B_DQS#4

AF2

DDR_B_DQS#5

AK8

DDR_B_DQS#6

AF8

DDR_B_DQS#7

BH3

DDR_B_DQS0

BD3

DDR_B_DQS1

BD9

DDR_B_DQS2

BH9

DDR_B_DQS3

AK4

DDR_B_DQS4

AF4

DDR_B_DQS5

AK10

DDR_B_DQS6

AF10

DDR_B_DQS7

M_CLK_B_DDR#0 16,17 ,18
M_CLK_B_DDR0 16,17, 18

DDR_B_CKE0 16,17,18
DDR_B_CKE1 16,17,18

DDR_B_CS0# 16,17,18
DDR_B_CS1# 16,17,18

DDR_B_RAS# 16,17,18
DDR_B_WE# 1 6,17,18
DDR_B_CAS# 16,17,18

DDR_B_BS0 16,17 ,18
DDR_B_BS1 16,17 ,18
DDR_B_BS2 16,17 ,18

DDR_B_MA[0..15 ] 16,17,18

DDR_B_DQS#[0 ..7] 16,1 7

DDR_B_DQS[0. .7] 16,17

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P06-MCP(2/7) D DRIII

P06-MCP(2/7) D DRIII

P06-MCP(2/7) D DRIII

LA-9262P

LA-9262P

LA-9262P

1

6 51Wednesda y, August 13, 2014

6 51Wednesda y, August 13, 2014

6 51Wednesda y, August 13, 2014

0.1

0.1

0.1

Vinafix.com

5

4

3

2

1

12

CH1 12P_0402_50 V8J

32.768KHZ_12. 5PF_9H032000 42

CH2

D D

+RTCVCC

1U_0402_6. 3V6K

1 2

RH18 20K_0402 _5%

1 2

RH19 20K_0402 _5%

1U_0402_6. 3V6K

+RTCVCC

RH23 330K_0402_ 5%

RH24 330K_0402_ 5%@

C C

PCH JTAG

+1.05VA

Stuffed : Single & Dual TCK

R4

R3d

R5
R8

R6

YH1

12

12P_0402 _50V8J

far away hot spot

1

CH3

2

1

CLP1 & CLP2 place near DIMM

CH4

2

1 2

1 2

INTVRMEN

H：Integrated VRM enable

*

L：Integrated VRM disable

1 2

RH28 51_0402 _5%

1 2

RH32 51_0402 _5%

1 2

RH33 51_0402 _5%

RH36 1K_0402_ 5%@

1 2

1 2

RH39 51_0402 _5%@

12

CMOS

12

@

CLRP1
SHORT PADS

12

PCH_RTCRST#

PCH_SRTCRST#

PCH_INTVRMEN

PCH_RTCX1

RH14
10M_0402 _5%

PCH_RTCX2

XDP_TDI

PCH_JTAG_TDO

XDP_TMS

PCH_JTAG_JTAGX

PCH_JTAG_TCK

I2S_SCLK22
I2S_MCLK22
I2S_SFRM22
I2S_SDOUT22

+RTCVCC

RP2

1 8

HDA_BIT_CLK

2 7

HDA_RST#

3 6

HDA_SYNC

4 5

HDA_SDOUT

33_8P4R_ 5%

PCH_JTAG_JTAGX

T16@

PCH_JTAG_TDO

T17@

XDP_TMS

T18@
T19@

PCH_JTAG_TCK
XDP_TDI

T20@

closed MCP 1000 mils

1 2

RH15 1M_0402_ 5%

PCH_RTCRST#19

I2S_SDIN022

JTAG_TRST#5,19
PCH_JTAG_TCK19
XDP_TDI19
PCH_JTAG_TDO19
XDP_TMS19

PCH_JTAG_JTAGX1 9

PCH_RTCX1
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#

HDA_BIT_CLK
HDA_SYNC
HDA_RST#

HDA_SDOUT

PCH_JTAG_TCK
XDP_TDI
PCH_JTAG_TDO
XDP_TMS

PCH_JTAG_JTAGX

UCPU1E

C9

RTCX1

C7

RTCX2

J5

INTRUDER

H6

INTVRMEN

D6

SRTCRST

A8

RTCRST

L6

HDA_BCLK_I2S0 _SCLK

L4

HDA_SYNC_I2S0_ SFRM

J9

HDA_RST_N_I2S_ MCLK

L10

HDA_SDI0_I2 S0_RXD

L8

HDA_SDI1_I2 S1_RXD

N3

HDA_SDO_I2S0 _TXD

N5

HDA_DOCK_EN_N _I2S1_TXD

N7

HDA_DOCK_RST_N_ _I2S1_SFRM

N9

I2S1_SCLK

CM7

PCH_TRST

CK17

PCH_TCK

CL20

PCH_TDI

CL18

PCH_TDO

CK15

PCH_TMS

P17

RSVD_P17

G26

PMTEST_RST

CL16

JTAGX

C5

RSVD_C5

BDW_Y_DDR3L_ BGA1234

@

RTC

SATA

Audio

SATA1GP_SATAPHY_PC_GPIO3 5

JTAG

5 OF 20REV = 1

SATA_RN0_PERN6_L 3
SATA_RP0_PERP6_L3

SATA_TN0_PETN6_L3
SATA_TP0_PETP6_L3

SATA_RN1_PERN6_L 2
SATA_RP1_PERP6_L2

SATA_TN1_PETN6_L2
SATA_TP1_PETP6_L2

SATA_RN2_PERN6_L 1
SATA_RP2_PERP6_L1

SATA_TN2_PETN6_L1
SATA_TP2_PETP6_L1

SATA_RN3_PERN6_L 0
SATA_RP3_PERP6_L0

SATA_TN3_PETN6_L0
SATA_TP3_PETP6_L0

SATA0GP_GPIO34

SATA2GP_GPIO36
SATA3GP_GPIO37

SATA_IREF
RSVD_R34
RSVD_R32

SATA_RCOMP

SATALED

V36
V38
W43
AA43

T37
T39
T43
V42

Y38
W39
T41
W41

W37
Y36
AB42
AA41

F29
H29
D33
L26

L42
R34
R32
L44
C30

SATA_RN1 26
SATA_RP1 26
SATA_TN1 26
SATA_TP1 26

PCIE_PRX_DTX_N6 2 5
PCIE_PRX_DTX_P6 2 5
PCIE_PTX_DRX_N6 2 5
PCIE_PTX_DRX_P6 2 5

PCH_GPIO34 SATAMPHY_PWREN
SATAMPHY_PWREN
SIO_EXT_SMI#
NGFF1_SATA_ SEL

SATA_RCOMP
PCH_SATALED#

Width = 15 mil, Spacing = 12 mil
Close PCH within 500 mil

closed MCP 2000 mils

PCH_GPIO34
SATAMPHY_PWREN
SIO_EXT_SMI#
NGFF1_SATA_ SEL

SATAMPHY_PWREN 31

SIO_EXT_SMI# 33

NGFF1_SATA_ SEL 33

1 2

RH20 3K_0402_ 1%

RH21 10K_0402 _5%

12

T21@
T22@
T23@
T24@

ME_FWP#3 3

DMN66D0LDW-7_SO T363-6

NGFF SSD

NGFF (WWAN)

+V1.05S_ASATA3 PLL

+3VS

From EC, for
enable
ME code
programing

PCH_GPIO34

SIO_EXT_SMI#

NGFF1_SATA_ SEL

PCH_GPIO34

3

Q1B

5

+3VS_AUDIO

4

12

MC1 10P_0402 _50V8J@

Reserve for RF please close to UH1

RH168 10K_0402 _5%

RH16 10K_0402 _5%

RH17 100K_040 2_5%

RH169 100K_040 2_5%@

D21

@

SDMK0340L-7 -F_SOD323- 2

1M_0402_ 5%

6 1

DMN66D0LDW-7_SO T363-6

12

HDA_SDO

+5VALW

ME debug mode , this signal
has a weak internal PD

R1

L=>security measures defined
in the Flash Descriptor will be

1 2

in effect (default)
H=>Flash Descriptor Security
will be overridden

2

Q1A

HDA_SDOUT

1 2

1 2

1 2

1 2

RH25

1 2

1K_0402_ 5%

Low = Disabled

*

High = Enabled

+3VS

BASE_DET# 28,33,36

HDA_SDOUT

B B

1 2

RH26 10K_0402_5 %

+3VS

RH29 10K_0402_5 %

+3VS

CLK_PCIE2#24

WLAN

WLAN

WWAN

A A

5

CLK_PCIE224

+3VS

CLK_REQ2#24

+3VS

CLK_PCIE4#24
CLK_PCIE424

+3VS

CLK_REQ4#24
CLK_PCIE5#25
CLK_PCIE525

+3VS

CLK_REQ5#25

1 2

1 2

RH34 10K_0402_5 %
RH40 0_0402_5%@

1 2

1 2

RH37 10K_0402_5 %

1 2

RH42 10K_0402_5 %

1 2

RH43 0_0402_5%@

1 2

RH44 10K_0402_5 %

1 2

RH45 0_0402_5%@

4

PCH_GPIO18

PCH_GPIO19

CLK_REQ2#_ R

CLK_REQ3#_ R

CLK_REQ4#_ R

CLK_REQ5#_ R

UCPU1F

AD29

CLKOUT_PCIE_N0

AC29

CLKOUT_PCIE_P0

B33

PCIECLKRQ0_N_ GPIO18

AD30

CLKOUT_PCIE_N1

AC30

CLKOUT_PCIE_P1

H25

PCIECLKRQ1_N_ GPIO19

AE30

CLKOUT_PCIE_N2

AG30

CLKOUT_PCIE_P2

P25

PCIECLKRQ2_N_ GPIO20

AC34

CLKOUT_PCIE_N3

AD34

CLKOUT_PCIEP3

P27

PCIECLKRQ3_N_ GPIO21

AE29

CLKOUT_PCIE_N4

AG29

CLKOUT_PCIE_P4

D35

PCIECLKRQ4_N_ GPIO22

AG33

CLKOUT_PCIE_N5

AE33

CLKOUT_PCIE_P5

G30

PCIECLKRQ5_N_ GPIO23

BDW_Y_DDR3L_ BGA1234

@

Clock Signal

DIFFCLK_BIASREF

TESTLOW_AC33
TESTLOW_AD33

CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP

6 OF 20REV = 1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

XTAL24_IN

XTAL24_OUT

RSVD_BK41
RSVD_BK43

TESTLOW_N14
TESTLOW_M15

AR44

XTAL24_IN

AP45

XTAL24_OUT

BK41

XCLK_BIA SREF <1 00 MILS

BK43
A38

XCLK_BIASREF

AC33

TESTLOW1

AD33

TESTLOW2

N14

TESTLOW3

M15

TESTLOW4

K15

CLKOUT_LPC0

L14

CLKOUT_LPC1

AE34
AG34

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

1 2

RH31 3K_0402_ 1%

1 2

RH38 22_0402 _5%

1 2

RH41 22_0402 _5%

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

+V1.05S_AXCK_LCPLL

CLK_PCI_MEC 33
CLK_LPC_DEBUG 19

XTAL24_IN

XTAL24_OUT

RH170 10K_0402 _5%

TESTLOW1
TESTLOW2
TESTLOW3
TESTLOW4

1 2
1 2

RH171 10K_0402 _5%

1 2

RH172 10K_0402 _5%

1 2

RH173 10K_0402 _5%

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 2

RH27 1M_0402_ 5%

YH2

24MHZ_12PF_7V24 000020

123

1

CH5
15P_0402 _50V8J

2

P07-MCP(3/7) S ATA,HDA,CLK,SPI

P07-MCP(3/7) S ATA,HDA,CLK,SPI

P07-MCP(3/7) S ATA,HDA,CLK,SPI

LA-9262P

LA-9262P

LA-9262P

4

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Compal Electron ics, Inc.

1

1

CH6
15P_0402 _50V8J

2

7 51Wednesda y, August 13, 2014

7 51Wednesda y, August 13, 2014

7 51Wednesda y, August 13, 2014

0.1

0.1

0.1

Vinafix.com

A

1 1

2 2

B

UCPU1G

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_IO3

P13

LAD0

M13

LAD1

R14

LAD2

K13

LAD3

P15

LFRAME

C26

SPI_CLK

H27

SPI_CS0

M27

SPI_CS1

K27

SPI_CS2

D31

SPI_MOSI

B23

SPI_MISO

F27

SPI_IO2

J26

SPI_IO3

BDW_Y_DDR3L_ BGA1234

@

LPC SMBUS

SPI

LPC_AD019,33
LPC_AD119,33
LPC_AD219,33
LPC_AD319,33
LPC_FRAME#19,33

PCH_SPI_CLK27

PCH_SPI_CS2#27

PCH_SPI_SI27

PCH_SPI_SO27

C

SML0ALERT_N_GPIO 60

SML1ALERT_N_PCHHO T_N_GPIO73

C-Link

7 OF 20REV = 1

SMBALERT_N_GPIO11

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK_GPIO7 5

SML1DATA_GPIO74

CL_CLK

CL_DATA

CL_RST

D

SMBCLK
SMBDATA
SML1CLK

K21

SMBALERT#

P21

SMBCLK

B21

SMBDATA

F21

SML0ALERT#

P19

SML0CLK

B19

SML0DATA

H8

SML1ALERT#

C14

SML1CLK

A14

SML1DATA

D23
H23
K23

CL_CLK 24
CL_DATA 24
CL_RST# 24

SML1DATA

SML0ALERT#
SML0CLK
SML0DATA

SMBALERT#
SML1ALERT#
PCH_SMBCLK
PCH_SMBDATA

1K_0804_ 8P4R_1%

1K_0804_ 8P4R_1%

RP5

1 8
2 7
3 6
4 5

RP23

1 8
2 7
3 6
4 5

RP7

1 8
2 7
3 6
4 5

10K_8P4R_5 %

E

+3V_PCH

+3VS

SML1CLK

SML1DATA

Closed to ROM

1 2

RH46 33_0402 _5%

RP4

SPI_SO_ROM1
SPI_IO2_ROM1
SPI_SI_ROM1

3 3

SPI ROM FOR ME ( 8MByte )
ROM is Quad SPI

SPI_PCH_CS0#
SPI_SO_ROM1

+3.3V_SPI

RH47 1K_0402_5%
RH48 1K_0402_5%

SPI_SO_ROM2
SPI_IO2_ROM2
SPI_SI_ROM2

4 4

SPI ROM FOR ME ( 8MByte )
ROM is Quad SPI

SPI_PCH_CS1#
SPI_SO_ROM2

1 8
2 7
3 6
4 5

33_0804 _8P4R_5%

U1

@

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64F VSSIQ_SO8

1 2
1 2

RH52 33_0402 _5%

U2

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64F VSSIQ_SO8

VCC

/HOLD(IO 3)

CLK

DI(IO0)

Closed to ROM

1 2

RP6

1 8
2 7
3 6
4 5

33_0804 _8P4R_5%

@

VCC

/HOLD(IO 3)

CLK

DI(IO0)

A

SPI_PCH_CLKSPI_CLK_ROM1

SPI_PCH_SO
SPI_PCH_IO2
SPI_PCH_SI
SPI_PCH_IO3SPI_IO3_ROM1

+3.3V_SPI

8
7

SPI_IO3_ROM1

6

SPI_CLK_ROM1SPI_IO2_ROM1

5

SPI_SI_ROM1

SPI_PCH_IO2
SPI_PCH_IO3

SPI_PCH_CLKSPI_CLK_ROM2

SPI_PCH_SO
SPI_PCH_IO2
SPI_PCH_SI
SPI_PCH_IO3SPI_IO3_ROM2

+3.3V_SPI

8
7

SPI_IO3_ROM2

6

SPI_CLK_ROM2SPI_IO2_ROM2

5

SPI_SI_ROM2

1

CH7
.1U_0402_1 6V7K

2

1

CH8
.1U_0402_1 6V7K

2

U1

X76SPI

X76

X76_SPIROM@

WINBOND@

SA000039A3 0

W25Q64FVSSIQ_SO8

U1

EON@

SA00006MK00

EN25QH64-104HIP_SO8

from CPU to SPI R OM

PCH_SPI_CS1#

PCH_SPI_SO

PCH_SPI_SI

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_IO2

PCH_SPI_IO3

+3.3V_SPI

RC40 0_0402_ 5%@

RC41 0_0402_ 5%@

RC42 0_0402_ 5%@

RC43 0_0402_ 5%@

RC44 0_0402_ 5%@

RC45 0_0402_ 5%@

RC46 0_0402_ 5%@

RC47 0_0402_ 5%@

B

+3.3V_M

12

SPI_PCH_CS1#

12

SPI_PCH_SO

12

SPI_PCH_SI

12

SPI_PCH_CLK

12

SPI_PCH_CS0#

12

SPI_PCH_IO2

12

SPI_PCH_IO3

12

U2

WINBOND@

SA000039A3 0

W25Q64FVSSIQ_SO8

U2

EON@

SA00006MK00

EN25QH64-104HIP_SO8

ACES_50696- 0200M-001

1 2

RH55 0_0402_ 5%@

RH56 0_0402_ 5%@

1 2

JSPI1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

GND

22

GND

CONN@

C

SML1_SMBCLK 33

SML1_SMBDATA 33

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

Connect EC

SMBCLK

SMBDATA

Compal Secre t Data

Compal Secre t Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

D

QH1A

DMN66D0LDW-7_SO T363-6

1 2

RH54 0_0402_ 5%@

6 1

DMN66D0LDW-7_SO T363-6

+3VS

2

RH57 0_04 02_5%@

QH1B

3

1 2

PCH_SMBCLK

5

4

PCH_SMBDATA

Title

Title

Title

P23-USB 3.0 IO CONN

P23-USB 3.0 IO CONN

P23-USB 3.0 IO CONN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-9262P

LA-9262P

LA-9262P

Date: Sheet of

Date: Sheet of

Date: Sheet of

Connect XDP

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Compal Electron ics, Inc.

E

PCH_SMBCLK 1 9

PCH_SMBDATA 1 9

0.1

0.1

8 51Wednesda y, August 13, 2014

8 51Wednesda y, August 13, 2014

8 51Wednesda y, August 13, 2014

0.1

Vinafix.com

5

+3V_PCH

D D

C C

B B

A A

1 2

R2 3K_04 02_5%@

+3V_PCH_DSW

Deep S3 support, connect to DSW power rail

RP8

1 8

+3VS

+3V_PCH

100K_080 4_8P4R_5%

PCH_GPIO15

TLS Confidentiality

+3V_PCH

+3V_PCH_DSW

+3V_PCH

+3VS

+3V_PCH

2 7
3 6
4 5

10K_8P4R_5 %

1 2

RH80 1M_0402_ 5%

RP24

1 8
2 7

PCH_APWROK

3 6

PCH_RSMRST#

4 5

RESET_OUT#

Low - Intel ME Crypto Transport Layer Security (TLS)

*

cipher suite with no confidentiality
High - Intel ME Crypto Transport Layer Security (TLS)
cipher suite with confidentiality

vPRO@

RH100 1K_0402_ 5%

RH107 10K_0402 _5%

RH109 10K_0402 _5%

RH110 10K_0402 _5%

RH175 10K_0402 _5%

RH12 10K_0402 _5%

RH111 10K_0402 _5%

RH114 100K_040 2_5%

RH119 100K_040 2_5%

+3VS

12

12

1 2

1 2

1 2

1 2

1 2

12

RH126 1K_04 02_5%@

1 2

LOW=Default

*

HIGH=No Reboot

TPM@

1 2

RH129 10K_0402 _5%

RH132 100K_040 2_5%

NTPM@

PBTN_OUT#_R

Deep S3 support, connect to EC

SYS_RESET#
SUS_PWR_DN
CS_PWR_BTN#
EC_WAKE#_R

12

12

NON-Deep S3 Support

AC_PRESENT

PCH_GPIO15

USH_ON

SENSOR_INT#

SIO_EXT_WAKE#

PCH_WWAN_WAKE#

SIO_EXT_SCI#

PCH_GPIO13

LCD_CAB_DET#

TS_INT#

HDA_SPKR

TPM_DET

TPM_DET

SUSACK#33
PM_SYS_RESET#19
SYS_PWROK19,33
RESET_OUT#32,33
PCH_APWROK33

PCH_RSMRST#33

ME_SUS_PWR_ACK33

SIO_PWRBTN#19,33
AC_PRESENT33

CS_PWR_BTN#33

SIO_SLP_S0#19,33, 42

SIO_SLP_WLAN#33

Deep S3 support,
PCH_GPIO27 connect from EC PCH_WAKE#

SUS_PWR_DN

PCH_APWROK

PCH_RSMRST# PCH_RSMRST#_R

PLT_RST#19,23 ,24,25,27,2 9,33

USB3MPHY_PWREN31

WLAN_ON24
USH_ON30

WLAN_PWR30

SIO_EXT_WAKE#33

WWAN_OFF#25

GNSS_OFF#25

Sensor_RST #23

SENSOR_HUB_I2C_WAKE23

TS_INT#29

MPHY_PWREN3 1

SENSOR_INT#23

EN_CAM30

PCH_WWAN_WAKE#25

SENSOR_EN30

SIO_EXT_SCI#33

DEVSLP025

AUDIO_PWREN30

DEVSLP126

WWAN_PWR_OFF#25

HDA_SPKR22

TPM BOM Optional

TPM_DET

1 = W/TP M

TPM

0 = W/O TPM

5

4

Non Deep S3 (Pop RH61)

Deep S3 (Pop RH62)

1 2

RH61 0_0402_5%@
RH62 0_0402_5%@

1 2
1 2

RH63 0_0402_5%@

1 2

RH65 0_0402_5%

vPRO@

1 2

RH67 0_0402_5%@

1 2

RH68 0_0402_5%@

1 2

RH69 0_0402_5%@
RH70 0_0402_5%@

1 2

1 2

RH71 0_0402_5%@

1 2

RH179 0_0402_ 5%

nvPRO@

RH78 0_0402_ 5%@

+3VS

5

IN1

4

O

USH_ON
PCH_GPIO15
MEM_CONFIG0
MEM_CONFIG1

EC_WAKE#_R
TPM_DET

SIO_EXT_WAKE#

TS_INT#

PCH_GPIO13
SENSOR_INT#

PCH_WWAN_WAKE#

SIO_EXT_SCI#

HDA_SPKR

4

IN2

3

12

RH89
100K_040 2_5%

SUSACK#_R
SYS_RESET#

RESET_OUT#
APWROK
PCH_PLTRST#

SUS_PWR_DN
PBTN_OUT#_R
AC_PRESENT_RAC_PRESENT
CS_PWR_BTN#
SLP_S0#
SIO_SLP_WLAN#

APWROKRESET_OUT#

1 2

1

P

2

G

UH1
SN74AHC1G08DCKR_SC70 -5

UCPU1J

J30

BMBUSY_N_USB3PHY_PC_G PIO76

C18

GPIO8

J14

LAN_PHY_PWR_CTRL _GPIO12

K25

GPIO15

N26

GPIO16

H31

GPIO17

C22

GPIO24

K17

GPIO27

M25

GPIO28

B15

GPIO26

F25

GPIO56

F23

GPIO57

F15

GPIO58

D15

GPIO59

L18

GPIO44

B29

GPIO47

K29

GPIO48

B31

GPIO49

F33

GPIO50

D29

HSIOPC_PCIEPHY_PC_ GPIO71

E14

GPIO13

M19

GPIO14

F17

GPIO25

P23

GPIO45

L22

GPIO46

D17

GPIO9

B17

GPIO10

E30

DEVSLP0_GPIO3 3

R36

SDIO_POWER_EN_ GPIO70

K31

DEVSLP1_GPIO3 8

J41

DEVSLP2_GPIO3 9

A34

SPKR_GPIO81

BDW_Y_DDR3L_ BGA1234

@

UCPU1H

D19

SUSACK

E26

SYS_RESET

A22

SYS_PWROK

F9

PCH_PWROK

J22

APWROK

M23

PLTRST

F7

RSMRST

D8

SUSWARN_N_SUSPWRDNACK_ GPIO30

M21

PWRBTN

M17

ACPRESENT_GPIO31

H17

BATLOW_N_GPIO 72

G22

SLP_S0

J18

SLP_WLAN_N_ GPIO29

BDW_Y_DDR3L_ BGA1234

@

PCH_PLTRST#

@

RH92
10K_0402 _5%

1 2

CPU/MISC

GPIO

LPIO

10 OF 2 0REV = 1

3

SystemPower Management

8 OF 20REV = 1

PCH Stra p PIN

DSWODVREN

DSWODVREN

DSWODVREN - On Die DSW VR Enable

H：Enable

*

L：Disable

THERMTRIP

RCIN_N_GPIO 82

SERIRQ

PCH_OPI_RCO MP

RSVD_AJ14
RSVD_AL18

GSPI0_CS_N_ _GPIO83

GSPI0_CLK_G PIO84
GSPI0_MISO_G PIO85
GSPI0_MOSI_G PIO86

GSPI1_CS_N_ GPIO87

GSPI1_CLK_G PIO88
GSPI1_MISO_G PIO89

GSPI_MOSI_GPIO 90
UART0_RXD_GPIO 91

UART0_TXD_GPIO9 2
UART0_RTS_N_GPIO 93
UART0_CTS_N_GPIO 94

UART1_RXD_GPIO 0

UART1_TXD_GPIO1
UART1_RST_N_GPIO 2
UART1_CTS_N_GPIO 3

I2C0_SDA_G PIO4

I2C0_SCL_ GPIO5

I2C1_SDA_G PIO6

I2C1_SCL_ GPIO7

SDIO_CLK_G PIO64

SDIO_CMD_GPIO 65

SDIO_D0_G PIO66
SDIO_D1_G PIO67
SDIO_D2_G PIO68
SDIO_D3_G PIO69

3

2

G14

DPWROK

WAKE

SLP_S4
SLP_S3

SLP_A
SLP_SUS
SLP_LAN

DSWODVREN

J7

DPWROK

F19

WAKE#

B35

CLKRUN#

D25
B27
A18

SIO_SLP_S5#

H19

SIO_SLP_S4#

N22

SIO_SLP_S3#

G18

SIO_SLP_M#

D27

RH73 0_0402_ 5%@

K19

Deep S3 Support

Non Deep S3 (De-pop RH313)

12

12

1 2

RC23 0_04 02_5%@

IRQ_SERIRQ 33

1 2

RH83 0_0402_ 5%@

CLKRUN# 33

SUSCLK 24,25,26
SIO_SLP_S5# 19

SIO_SLP_S4# 19,33
SIO_SLP_S3# 19,33

SUSCLK

SIO_SLP_M# 19,33
SIO_SLP_SUS# 33

MC2 10P_0402_5 0V8J@

1 2

+RTCVCC

Reserve for RF please close to UH1

SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_M#
SIO_SLP_WLAN#

H_THERMTRIP# 33

SIO_RCIN# 3 3

NGFF_WWAN_PWREN 30
USH_DET# 29
SSD_PWREN 30

BT_ON/OFF # 24
GPIO88_SLP_S0# 3 3

TS_EN 30

TS_RST# 29

DEBUG_UART_TX 3 3

I2C0_SDA 22,2 3,25

I2C0_SCK 22,2 3,25

I2C1_SDA 28,2 9

I2C1_SCK 28,2 9

CONTACTLESS_DET # 29

WWAN_RST# 2 5

GPIO Pin

PCH_GPIO16

PCH_GPIO17

PCH_GPIO51

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

PCH_PCIE_WAKE# 33

12

T46 @
T47 @
T48 @
T49 @
T50 @

DDR Memory Configuratino Type Strap pin

+3VS

Micron 4G
SA00005TH0L

RH120 10K_0402 _5%@

RH122 10K_0402 _5%@

RH124 10K_0402 _5%@

MEM_CONFIG25

Micron 8G
SA00006FB0L

0 1

0

0

0

0 0

2

PCH DPWROK Option for Deep S3

12

12

12

Hynix 4G
SA00006JF0L

1

DSWVRMEN

GPIO32_CL KRUN

SUS_STAT_N_GPIO61

SUSCLK_GPIO62

SLP_S5_N_G PIO63

RH79 330K_040 2_5%

RH81 330K_040 2_5%@

CG40

H_THERMTRIP#_R H_T HERMTRIP#

C34

SIO_RCIN#

E34

IRQ_SERIRQ

AB4

PCH_OPIRCOMP

AJ14
AL18

Width = 15 mil, Spacing = 12 mil
Close PCH within 500 mil

D40

PCH_GPIO83

G34
L36

USH_DET#

K33

SSD_PWREN

L34
M31
F37
H35
M35

DDR_CHA_EN

F39

DDR_CHB_EN

N43
N41
P29
H38
N39
N30
N36

I2C0_SDA

R42

I2C0_SCK

J37

I2C1_SDA

M33

I2C1_SCK

N34

PCH_GPIO64

H40

CONTACTLESS_DET #

R40

SDIO_D0

R38
J39

LCD_CAB_DET#

P31

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

1

RH59 8.2K_040 2_5%

CLKRUN#

WAKE#

DPWROK

EC_WAKE#_R

H_THERMTRIP#

PCH_GPIO83
PCH_GPIO64
CONTACTLESS_DET #
USH_DET#
IRQ_SERIRQ
SIO_RCIN#

I2C0_SCK
I2C0_SDA
I2C1_SDA
I2C1_SCK

DDR_CHA_EN
DDR_CHB_EN

DDR_CHA_EN
DDR_CHB_EN

PCH_OPIRCOMP
SSD_PWREN

GPIO86 h ave int ernal pu ll down

Boot BIOS Strap

*

SDIO_D0

1 2

1 2

RH58 1K_0402_ 5%

1 2

RH64 100K_040 2_5%@

RH72

@

0_0402_ 5%

1 2

@

1 2

0_0402_ 5%

RH93 0_0402_ 5%@

PCH_DPWROK 33

RH74

PCH_RSMRST#DPWROK

1 2

1 2

RC21 1K_0402_ 5%

1 2

RH176 10K_0402 _5%
RH11 10K_0402 _5%@
RH174 100K_040 2_5%

1 2
1 2

RH94 100K_040 2_5%

1 2

RH95 8.2K_040 2_5%

1 2

RH96 10K_0402 _5%

RP22

1 8
2 7
3 6
4 5

1K_0804_ 8P4R_1%

1 2

RH99 100K_040 2_5%

1 2

RH101 100K_040 2_5%

1 2

RH102 SHORT PADS@

1 2

RH103 SHORT PADS@

RC22 49.9_04 02_1%

1 2
1 2

RH105 1K_0402_ 5%@

Boot BIOS LocationPCH_GPIO86

SPI

0

RH112 1K_0402_ 5%@

RH113 1K_0402_ 5%@

1 2

12

+3VS

+3V_PCH_DSW

Deep S3 Support

Non Deep S3

EC_WAKE# 33

+1.05VS_VCCST

+3VS

12

+VS_LPSS_SDIO

GPIO66 h ave int ernal pu ll down

Top-Bloc k Swap Override mode

0 = Enab le

*

1 = Disa ble

MEM_CONFIG2

MEM_CONFIG0

MEM_CONFIG1

Hynix 8G
SA00006Q90L

10

1

0

Title

Title

Title

P01-Cover Page

P01-Cover Page

P01-Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-9262P

LA-9262P

LA-9262P

Date: Sheet of

Date: Sheet of

Date: Sheet of

RH121 10K_0402 _5%@

RH123 10K_0402 _5%@

RH125 10K_0402 _5%@

Samsung 4G
SA00006J32L

0

0

1 1

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Samsung 8G
SA00006J82L

1

0

1

12

12

12

Elpida 4G
SA00005HT0L

9 51Wednesda y, August 13, 2014

9 51Wednesda y, August 13, 2014

9 51Wednesda y, August 13, 2014

Elpida 8G
SA00006O90L

10

11

11

0.1

0.1

0.1

Vinafix.com

5

PCIE_PRX_DTX_N524

D D

NGFF (WLAN)

NGFF (WLAN)

C C

PCIE_PRX_DTX_P524

PCIE_PTX_DRX_N524
PCIE_PTX_DRX_P524

PCIE_PRX_DTX_N324
PCIE_PRX_DTX_P324

PCIE_PTX_DRX_N324
PCIE_PTX_DRX_P324

1 2

CH9 0.1U_04 02_10V7K

1 2

CH11 0.1U_0 402_10V7K

1 2

CH15 0.1U_0 402_10V7K

1 2

CH16 0.1U_0 402_10V7K

+V1.05S_AUSB3PLL

RH134 3K_0402_ 1%

4

PCIE_PTX_DRX_N5_C
PCIE_PTX_DRX_P5_C

PCIE_PTX_DRX_N3_C
PCIE_PTX_DRX_P3_C

1 2

Width = 15 mil, Spacing = 15 mil
Close PCH within 500 mil

PCIE_RCOMP

UCPU1K

AF40

PERN5_L0

AG41

PERP5_L0

AU40

PETN5_L0

AU42

PETP5_L0

AD40

PERN5_L1

AE41

PERP5_L1

AW40

PETN5_L1

AW42

PETP5_L1

AE43

PERN5_L2

AD42

PERP5_L2

BA42

PETN5_L2

BA40

PETP5_L2

AF42

PERN5_L3

AG43

PERP5_L3

BB41

PETN5_L3

BB43

PETP5_L3

AD38

PERN3

AC39

PERP3

AY41

PETN3

AY43

PETP3

AH38

PERN4

AH40

PERP4

AV41

PETN4

AV43

PETP4

AF38

PERN1_USB3RN3

AE39

PERP1_USB3RP3

BD41

PETN1_USB3TN3

BD43

PETP1_USB3TP3

AH42

PERN2_USB3RN4

AJ43

PERP2_USB3RP4

BC40

PETN2_USB3TN4

BC42

PETP2_USB3TP4

AT41

RSVD_AT41

AT43

RSVD_AT43

F41

PCIE_RCOMP

C41

PCIE_IREF

BDW_Y_DDR3L_ BGA1234

@

PCIE USB

11 OF 2 0REV = 1

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

RSVD_V4
RSVD_T3

RSVD_Y4

RSVD_W3

USB3RN1
USB3RP1

USB3TN1

USB3TP1

USB3RN2
USB3RP2

USB3TN2

USB3TP2

USBRBIAS
USBRBIAS

RSVD_H13

RSVD_F13

OC0_N_GPI O40
OC1_N_GPI O41
OC2_N_GPI O42
OC3_N_GPI O43

W12
V12

T9
V10

Y10
Y8

AB10
AA9

W9
W7

V8
T7

V6
T5

Y6
W5

V4
T3

Y4
W3

AJ41
AM41

BG42
BG40

AM43
AK42

BF41
BF43

B13
D13
H13
F13

E18
E22
H21
D21

3

USB20_N0 28
USB20_P0 28

USB20_N1 19
USB20_P1 19

USB20_N2 23
USB20_P2 23

USB20_N4 23
USB20_P4 23

USB20_N5 25
USB20_P5 25

USB20_N6 24
USB20_P6 24

USB20_N7 29
USB20_P7 29

USB3RN1 28
USB3RP1 28

USB3TN1 2 8

USB3TP1 28

1 2

USBRBIAS

RH133

22.6_04 02_1%

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

closed MCP 2000 mils

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

Base

Debug Port

Front Camera

Rear Camera

NGFF (WWAN)

NGFF (WLAN)

USH

Base

Net USB_BIAS route impedacnes should be 50-ohm
and length less than 4 50-mil spacing is 15-mil.

Within 450 mils

USB_OC0#
USB_OC2#
USB_OC3#
USB_OC1#

T35@
T36@
T37@
T38@

2

RP9

1 8
2 7
3 6
4 5

10K_8P4R_5 %

1

+3V_PCH

UCPU1R

CB11

RSVD_CB11

H15

RSVD_H15

TP_F3_H2

B B

A A

5

TP_F45_ F43
TP_F3_H2
TP_H44

T44@

4

F3

DAISY_CHAIN_NCTF_F3

F43

DAISY_CHAIN_NCTF_F43

H2

DAISY_CHAIN_NCTF_H2

H44

DAISY_CHAIN_NCTF_H4 4

BDW_Y_DDR3L_ BGA1234

@

DAISY_CHAIN_NCTF_A44
DAISY_CHAIN_NCTF_C4 3
DAISY_CHAIN_NCTF_C4 5
DAISY_CHAIN_NCTF_F45

DAISY_CHAIN_NCTF_D2

DAISY_CHAIN_NCTF_D4 4

DAISY_CHAIN_NCTF_F1

18 OF 2 0REV = 1

A44

TP_A44

C43

TP_D44_C 43

C45

TP_C45

F45

TP_F45_ F43

D2

TP_D2

D44

TP_D44_C 43

F1

TP_F1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

T41@

T42@

T43@

T45@

Compal Secre t Data

Compal Secre t Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P09-MCP(5/7) PCIE,USB

P09-MCP(5/7) PCIE,USB

P09-MCP(5/7) PCIE,USB

LA-9262P

LA-9262P

LA-9262P

1

10 51Wedne sday, August 13, 2014

10 51Wedne sday, August 13, 2014

10 51Wedne sday, August 13, 2014

0.1

0.1

0.1

Vinafix.com

5

+1.35V_DDR +1.35V_DDR

D D

1

+

2

@

C216
470U_X_2VY_R9M

1

+

2

@

C217
470U_X_2VY_R9M

4

3

2

1

VCC_BK45
VCC_CB41
VCC_CA40
VCC_BY41
VCC_BW40
VCC_CY17
VCC_AY45
VCC_BB45
VCC_BD45

VCC_BF45

VCC_BH45

VCC_BT45
VCC_BV45
VCC_BY45
VCC_CB45
VCC_CD45
VCC_CF45
VCC_CM45
VCC_CN44
VCC_CR43
VCC_CR45
VCC_CU44
VCC_CV43
VCC_CV45
VCC_CY19
VCC_CY21
VCC_CY23
VCC_CY25
VCC_CY27
VCC_CY29
VCC_CY31
VCC_CY33
VCC_CY36
VCC_CY38
VCC_CY42
VCC_CY44
VCC_BM45
VCC_BP45
VCC_CA44
VCC_BV41
VCC_BV43
VCC_BW44
VCC_CY40
VCC_CY13
VCC_CY15
VCC_BW42
VCC_BY43
VCC_CA42
VCC_CB43

BK45
CB41
CA40
BY41
BW40
CY17
AY45
BB45
BD45
BF45
BH45
BT45
BV45
BY45
CB45
CD45
CF45
CM45
CN44
CR43
CR45
CU44
CV43
CV45
CY19
CY21
CY23
CY25
CY27
CY29
CY31
CY33
CY36
CY38
CY42
CY44
BM45
BP45
CA44
BV41
BV43
BW44
CY40
CY13
CY15
BW42
BY43
CA42
CB43

+VCC_CORE+1.35V_DDR

+VCC_CORE

1

2

C225
100P_040 2_50V8J

UCPU1L

+1.35V_DDR

10U_060 3_6.3V6M

10U_060 3_6.3V6M

1

1

CC2

2

2

2.2U_040 2_6.3V6M

2.2U_040 2_6.3V6M

CC8

1

1

C C

VIDSOUT:
Requires a pull-up to VCCIO through a pull-up res istor of 110 ±5% clos e to the processo r, and a pull-up
to VCCIO through a pull-up resis tor of 110 ±5% close to Intel MVP 7.
VIDSCLK:
Required pul l-up to VCCIO through 55 ±5% close to Intel IMVP 7.

B B

2

+1.05VS_VCCST

RC32 75_0402 _5%

RC33 130_040 2_1%

2

close to CPU

1 2

10U_060 3_6.3V6M

10U_060 3_6.3V6M

1

1

CC3

CC4

2

2

2.2U_040 2_6.3V6M

2.2U_040 2_6.3V6M

CC10

CC9

1

1

2

2

12

10U_060 3_6.3V6M

1

CC5

2

CC11

VR_SVID_ALRT#

H_CPU_SVIDDAT

10U_060 3_6.3V6M

1

CC7

CC6

2

VGATE44

+VCCIO_OUT

+1.05VS

RH135

@

1 2

0_0603_ 5%

1

CH20
22U_0603_6 .3V6M

2

1

CH19

0.1U_0402_ 10V7K

2

+1.05VS_VCCST

+1.05VS_VCCST

1

CH21
1U_0402_6. 3V6K

2

12

@

R6
1K_0402_ 5%

VGATE

+1.05VS_VCCST

VR12.6_VR_O N

12

R8

1 2

150_040 2_5%

R7

1.5K_040 2_5%

FIVE_EN

RC24 & R C25 clo se to PC H

+VCC_CORE

VCCSENSE44

VR_SVID_ALRT#44

VR_SVID_CLK44
VR_SVID_DAT44

1.05VS_VCCST _PG19,32
VR12.6_VR_O N44

VR_SVID_ALRT#

VGATE

+1.35V_DDR

1

C224
100P_040 2_50V8J

2

1 2

RC24 100_040 2_1%

1 2

RC25 0_0402_ 5%@

+VCCIO_OUT
+VCCIOA_OUT

1 2

RC26 43_0402 _5%
RC27 0_0402_ 5%@

1 2
1 2

RC28 0_0402_ 5%@

1 2

RC29 0_0402_ 5%@

1 2

RC30 0_0402_ 5%@

1 2

RC31 0_0402_ 5%@

FIVE_EN19

+VCC_CORE

VCCSENSE_R

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
VCCSTPG_MCP
VR_ON_MCPVR12.6_VR_O N
VRPG_MCP

FIVE_EN

+1.05VS_VCCST

CJ32

RSVD_CJ32

CM33

RSVD_CM33

CT3

VDDQ_CT3

CY3

VDDQ_CY3

CB1

VDDQ_CB1

BV1

VDDQ_BV1

CF1

VDDQ_CF1

BA14

VDDQ_BA14

CL1

VDDQ_CL1

CM3

VDDQ_CM3

CW1

VDDQ_CW1

AP1

VDDQ_AP1

AV1

VDDQ_AV1

BB1

VDDQ_BB1

BC14

VDDQ_BC14

BE14

VDDQ_BE14

BF1

VDDQ_BF1

BK1

VDDQ_BK1

BP1

VDDQ_BP1

CR1

VDDQ_CR1

AV45

VCC_AV45

CJ28

RSVD_CJ28

CH45

VCC_SENSE

AL16

RSVD_AL16

BM43

VCCIO_OUT

AR40

VCOMP_OUT

AL22

RSVD_AL22

AK33

RSVD_AK33

CL14

RSVD_CL14

CD43

VIDALERT

CD41

VIDSCLK

CE40

VIDSOUT

BU14

VCCST_PWRGD

CE42

VR_EN

CF43

VR_READY

CK40

PWR_DEBUG

CJ22

RSVD_TP_CJ22

CK23

RSVD_TP

CK27

IVR_ERROR

CL26

IST_TRIGGER

CK21

RSVD_CK21

CL22

RSVD_CL22

CK25

RSVD

CM27

RSVD_CM27

CK19

RSVD_CK19

CJ16

RSVD_CJ16

CK31

RSVD_CK31

AJ20

VCCST_AJ20

BDW_Y_DDR3L_ BGA1234

@

12 OF 2 0REV = 1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P10-MCP(6/7) PWR,VCC

P10-MCP(6/7) PWR,VCC

P10-MCP(6/7) PWR,VCC

LA-9262P

LA-9262P

LA-9262P

1

11 51Wedne sday, August 13, 2014

11 51Wedne sday, August 13, 2014

11 51Wedne sday, August 13, 2014

0.1

0.1

0.1

Vinafix.com

5

4

3

2

1

+1.05VDX_MODPHY

+1.05V_SATAMOD PHY

D D

+1.05V_USB3MODPHY

+1.05V_SATAMOD PHY

C C

+1.05VA

+1.05VA

B B

Deep S3 Support

+3VALW

+3V_PCH

Non Deep S3

+3VS

1

2

R9

1 2

0_1206_ 5%

CH25

1U_0402_6. 3V6K

R10

@

1 2

0_1206_ 5%

CH30

1U_0402_6. 3V6K

R11

@

1 2

0_1206_ 5%

CH38

1U_0402_6. 3V6K

LH1

1 2

2.2UH_LQM21PN2R2MC0D_2 0%

22U_0603_6 .3V6M

LH2

1 2

2.2UH_LQM21PN2R2MC0D_2 0%

22U_0603_6 .3V6M

RH139

@

1 2

0_0402_ 5%

@

1 2

0_0402_ 5%

RH141

@

1 2

0_0603_ 5%

@

1 2

0_0603_ 5%

1U_0402_6. 3V6K

CH60

10U_0603_6 .3V6M

+V1.05A_DCPSUS2

1U_0402_6. 3V6K

RH145

RH146

CH78

closed t o VCC3_ 3

CH80

0.1U_0402_ 10V7K

1

0.1U_0402_ 10V7K

2

+V1.05S_MPHY_SATA

1

2

+V1.05S_MPHY_USB3

1

0.1U_0402_ 10V7K

2

CH46

CH55

1

2

CH63

1

2

1

CH81

0.1U_0402_ 10V7K

2

CH26

CH31

0.1U_0402_ 10V7K

CH39

1

22U_0603_6 .3V6M

2

1

22U_0603_6 .3V6M

2

+V1.05A_DCPSUS3

1U_0402_6. 3V6K

1

2

+3V_PCH_DSW

1

2

+V1.05S_MPHY_PCIE

1

0.1U_0402_ 10V7K

2

1

2

1

2

CH47

CH56

1

CH61

2

CH82

0.1U_0402_ 10V7K

1

CH27

2

+V1.05S_ASATA3 PLL

1

CH48

1U_0402_6. 3V6K

2

+V1.05S_AUSB3PLL+1.05V_USB3MODPHY

1

CH57

1U_0402_6. 3V6K

2

+3VS_AUDIO

1

2

+1.05VS

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS

2.2UH_LQM2MPN2R2NG0L_30%

1

@

2

1

@

2

+3VS_AUDIO

CH62

0.1U_0402_ 10V7K

L1

1 2

47U_0805_6 .3V6M

L3

1 2

47U_0805_6 .3V6M

CH66

CH75

1U_0402_6. 3V6K

CH50

22U_0603_6 .3V6M

1

47U_0805_6 .3V6M

2

1

47U_0805_6 .3V6M

2

+3V_PCH

CH67

CH76

+1.05VS +1.05VS +1.05VA

1

@

+

C221
330U_B2_2.5 VM_R9M

2

AB38

AA45

AC45
AD36
AE45

AA13

AG14

AB14

+3VS

AL37
AK35
AL30

+1.05VS

AK31

+1.05VS

+1.05VS

AL39

+1.05VS
+1.05VS

AK23

+1.05VS

AL14

DCPSUS c an be N C, if IN TVRMEN pull up
to enabl e Integ rated VR M

1

2

1

2

+1.05VS

CH45

1

2

+V1.05S_MPHY_PCIE

+V1.05S_MPHY_SATA

+V1.05S_MPHY_USB3

1

+V1.05S_AUSB3PLL

2

+V1.05A_DCPSUS3

+3VS_AUDIO

+V1.05A_DCPSUS2

+3V_PCH_DSW

+V1.05S_AXCK_DCB

+V1.05S_AXCK_LCPLL

+V1.05S_AXCK_DCB

1

CH68

1U_0402_6. 3V6K

2

+V1.05S_AXCK_LCPLL

1

CH77

1U_0402_6. 3V6K

2

1

@

+

C222
330U_B2_2.5 VM_R9M

2

UCPU1M

VCCPCIEPHY_AB38

W45

VCCPCIEPHY_W45
VCCPCIEPHY

N45

VCCSATAPHY

T45

VCCSATAPHY_T45
VCCUSB3PHY_AC45
VCCUSB3PHY_AD36
VCCUSB3PHY

T31

VCC1_05_PH Y

T33

VCCSATA3PLL

T35

VCCUSB3PLL

U30

DCPSUS3

W1

VCCHDA_W1
VCCHDA
DCPSUS2

U18

VCCSUS3_3

AA1

VCCDSW3_3_AA1
VCCDSW3_3_AB1 4

A30

VCC3_3_A30

A28

VCC3_3_A28

A26

VCC3_3_A26

T27

VCC3_3

VCCCLK4
VCCACLKPLL
VCCCLK6

VCCCLK2

AJ26

VCCCLK7
VCCCLK5

AJ28

VCCCLK3
VCCCLK1
VCCSUS3_3_AL1 4

BDW_Y_DDR3L_ BGA1234

@

1

+

2

MPHY

ICC

13 OF 2 0REV = 1

+V1.05S_APLLO PI

1

CH65

1U_0402_6. 3V6K

2

+V1.05S_APLL

1

CH69

1U_0402_6. 3V6K

2

+V1.05S_AUSB

1

CH79

1U_0402_6. 3V6K

2

@

C223
330U_B2_2.5 VM_R9M

VCCSUS3_3_RTC_ AC15

VCCRTC
DCPRTC

RTC

SPI

VCCSPI_T25

VCCASW

VCC1_05_Y2 2
VCC1_05_W 22

VCC1_05_AJ 16

VCC1_05_AH 36

VCC1_05_AG 45

VCC1_05

VCC1_05_T1 7

DCPSUSBYP
VCCASW_N1
VCCASW_T1

VCCASW_W14

DCPSUS1

VCCTS1_5

VCCTS3_3_AB36

VCCSDIO

DCPSUS4

VCCUSB2PLL

VCCOPIPLL

VCCHDAPLL

VCC1_05_U SB

RH143

@

1 2

0_0402_ 5%

RH144

@

1 2

0_0402_ 5%

RH147

@

1 2

0_0402_ 5%

VCCSPI

AC15
AA15
V15

A24
T25

AE15

Y22
W22
AJ16
AH36
AG45
AJ45
T17

AG13
N1
T1
W14

U16

AJ32
AB36

A32

T21

AK17
AK19
AK29

AE13

+PCH_VCCDSW

+1.05V_M+V1.05S_ASATA3 PLL

+1.05VS

+1.5VS

1

CH59
1U_0402_6. 3V6K

2

+RTCVCC

RH137

@

1 2

0_0402_ 5%

+1.05VS

1

@

CH71
47U_0805_6 .3V6M

2

1

2

+RTC_VCCSUS

1 2

CH35 0.1U_0 402_10V7K

+PCH_VCCDSW

+1.05V_M

+V1.05A_DCPSUS1

+VS_LPSS_SDIO

+V1.05A_AOSCSUS

+V1.05S_AUSB
+V1.05S_APLLO PI
+V1.05S_APLL

1

@

CH70
47U_0805_6 .3V6M

2

1 2

C205 0.47U_0402_ 6.3V6K

+3.3V_M

1

CH40

0.1U_0402_ 10V7K

2

CH49

1 2

1U_0402_6. 3V6K

+3VS

CH54

0.1U_0402_ 10V7K

+1.05VS

LH3

@

1 2

0_0805_ 5%

+3V_PCH_DSW

+V1.05A_AOSCSUS

1

CH72

1U_0402_6. 3V6K

2

+RTC_VCCSUS

1

2

1

2

1

2

+VS_LPSS_SDIO

+VS_LPSS_SDIO

1

CH73
47U_0805_6 .3V6M

2

1

CH28
1U_0402_6. 3V6K

2

closed t o VCCRT C

CH32

1U_0402_6. 3V6K

1

0.1U_0402_ 10V7K

2

closed t o VCC1_ 05

CH41

0.1U_0402_ 10V7K

1

2

closed t o VCCAS W

CH58

1U_0402_6. 3V6K

1

0.1U_0402_ 10V7K

2

1

2

1

CH74
47U_0805_6 .3V6M

2

CH51

0.1U_0402_ 10V7K

+V1.05A_DCPSUS1

1

2

+3V_PCH

RH136

@

1 2

0_0402_ 5%

+RTCVCC

RH138

RH140

@

1 2

0_0402_ 5%

RH142

@

1 2

0_0402_ 5%

@

1 2

+1.05VA

L2

1

2

+1.05VS

1

2

+1.05V_M

1

2

CH34

0.1U_0402_ 10V7K

CH44

10U_0603_6 .3V6M

CH53

22U_0603_6 .3V6M

+1.8VS

+3VS

CH33

CH42

1U_0402_6. 3V6K

CH52

@

1 2

0_0402_ 5%

CH64

0.1U_0402_ 10V7K

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VA

A A

closed t o VCCCL K6 closed t o VCCCL K2 closed to VCCCLK7 cl osed to VCCCLK5 cl osed to VCCCLK3 cl osed to VCCCLK1

+1.05VS

1

2

CH83

1U_0402_6. 3V6K

+1.05VS +1.05VS +1.05VS +1.05VS +1.05VS

1

CH84

1U_0402_6. 3V6K

2

5

1

CH85

1U_0402_6. 3V6K

2

1

CH86

1U_0402_6. 3V6K

2

4

1

CH87

1U_0402_6. 3V6K

2

1

CH88

1U_0402_6. 3V6K

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P10-MCP(6/7) PWR,VCC

P10-MCP(6/7) PWR,VCC

P10-MCP(6/7) PWR,VCC

LA-9262P

LA-9262P

LA-9262P

1

12 51Wedne sday, August 13, 2014

12 51Wedne sday, August 13, 2014

12 51Wedne sday, August 13, 2014

0.1

0.1

0.1

Vinafix.com

5

4

3

2

1

closed MCP 1000 mils

D D

12

CFG4 CFG4

RC341K_0402_ 5%

eDP Strap

1 : Disa bled; N o Physic al Disp lay Port
attached to Emb edded Di splay P ort

CFG4

0 : Enab led; An externa l Displ ay

*

Port dev ice is connecte d to th e
Embedded Displa y Port

RC3549.9_040 2_1%

12

CFG_RCOMP

12

PROC_OPI_COMP

RC3649.9_040 2_1%

12

TD_IREF

RC378.2K_04 02_1%

Width = 15 mil, Spacing = 15 mil
Close PCH within 500 mil

C C

UCPU1N

AH29

VSS

AM19

VSS

AH6

VSS

AH31

VSS

AH30

VSS

AH33

VSS

AH32

VSS

AH34

VSS

AH44

VSS

AJ39

VSS

AJ30

VSS

AJ37

VSS

AK6

VSS

AJ18

VSS

AM17

VSS

AN6

VSS

AR42

VSS

AK12

VSS

AK21

VSS

AK27

VSS

5

BE44

VSS

AM13

VSS

BL8

VSS

CJ18

VSS

CJ24

VSS

AM21

VSS

AM23

VSS

AM25

VSS

AM27

VSS

AM29

VSS

AM31

VSS

AM35

VSS

CJ30

VSS

AM45

VSS

CL5

VSS

AN2

VSS

AN4

VSS

CL24

VSS

AN8

VSS

AN10

VSS

AN12

VSS

AN14

VSS

AN40

VSS

AN42

VSS

AN44

VSS

AP7

VSS

AP15

VSS

AP43

VSS

CN1

VSS

AT1

VSS

AT7

VSS

AT15

VSS

AT39

VSS

AT45

VSS

AU44

VSS

AV13

VSS

AV15

VSS

AV39

VSS

AW44

VSS

CU1

VSS

AY1

VSS

AY7

VSS

CV3

VSS

BDW_Y_DDR3L_ BGA1234

@

B B

A A

AY13

VSS

AY15

VSS

AY39

VSS

BA44

VSS

BB3

VSS

BB5

VSS

BB7

VSS

BB9

VSS

BB11

VSS

BB13

VSS

BB15

VSS

BB39

VSS

BC44

VSS

BD1

VSS

BD7

VSS

BD13

VSS

BD15

VSS

BD39

VSS

BE40

VSS

BE42

VSS

BF7

VSS

BF13

VSS

BF15

VSS

BF39

VSS

BG14

VSS

BG44

VSS

BH1

VSS

BH7

VSS

BH13

VSS

BH15

VSS

BH39

VSS

BH41

VSS

BH43

VSS

BJ44

VSS

BK7

VSS

BK13

VSS

BK15

VSS

BK39

VSS

BL2

VSS

BL4

VSS

BL6

VSS

BL10

VSS

BL12

VSS

BL40

VSS

BL42

VSS

BL44

VSS

BM1

VSS

BM7

VSS

BM13

VSS

BM39

VSS

BN44

VSS

BP13

VSS

CH1

VSS

CH15

VSS

CV39

VSS

CV41

VSS

CW12

VSS

CW14

VSS

CW16

VSS

CW18

VSS

AJ24

VSS

AP39

VSS

14 OF 2 0REV = 1

CFG3

T39@

UCPU1S

CFG3

CFG_RCOMP

TD_IREF

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CW20
AM39
L32
CN42
CP3
CP17
CP29
CR8
CR14
CR18
CR22
CR26
CR37
CT31
CU8
CU14
CU18
CU22
CU26
CU42
CV35
CV37
CW5
CW8
CW22
CW24
CW26
CW28
CW32
CW34
CY7
CY10
D10
G28
J24
J28
CD9
CD5
CD3
CC10
CA8
AW14
AR14
AG39
BU40
BU42
L2
L20
L28
CD11
G32
CW30
J20
J32

CV27
CT27
CP27
CU28
CV29
CT29
CM29
CU30
CN30
CV31
CP31
CN32
CV33
CU34
CT33
CP33
CR28
CN28
CR32
CU32
CR30

BT41
BT43

BJ40
BJ42

L40

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10

PROC_OPI_RC OMP

CFG_11
CFG_12
CFG_13
CFG_14
CFG_15

RESERVED

CFG_16
CFG_17
CFG_18
CFG_19
CFG_RCOMP

RSVD_BT41
RSVD_BT43
RSVD_BJ40
RSVD_BJ42
TD_IREF

19 OF 2 0REV = 1

BDW_Y_DDR3L_ BGA1234

@

CFG019

4

CFG119
CFG219
CFG319
CFG419
CFG519
CFG619
CFG719
CFG819
CFG919
CFG1019
CFG1119
CFG1219
CFG1319
CFG1419
CFG1519
CFG1619
CFG1719
CFG1819
CFG1919

UCPU1O

L24

VSS

L16

VSS

H10

VSS

H36

VSS

CN26

VSS

BP7

VSS

BP39

VSS

BR44

VSS

BT1

VSS

BT7

VSS

BT13

VSS

J16

VSS

BT39

VSS

BU44

VSS

BV7

VSS

BV13

VSS

BV15

VSS

BV39

VSS

BY1

VSS

BY3

VSS

BY5

VSS

BY7

VSS

BY9

VSS

BY11

VSS

BY13

VSS

BY15

VSS

BY39

VSS

C16

VSS

C20

VSS

C24

VSS

C28

VSS

C32

VSS

C36

VSS

CB7

VSS

CB13

VSS

CB15

VSS

CB39

VSS

CC40

VSS

CC42

VSS

CC44

VSS

CD1

VSS

CD7

VSS

CD13

VSS

CD15

VSS

CD39

VSS

CE44

VSS

CF7

VSS

CF13

VSS

CF15

VSS

CG44

VSS

CH13

VSS

CJ26

VSS

CK3

VSS

CK10

VSS

CK38

VSS

CK44

VSS

CL12

VSS

CM15

VSS

CM17

VSS

CM19

VSS

CM21

VSS

CM23

VSS

CM25

VSS

CM31

VSS

CM35

VSS

CM43

VSS

CN8

VSS

BDW_Y_DDR3L_ BGA1234

@

15 OF 2 0REV = 1

1 2

R310 1K_ 0402_5%

BJ14

RSVD_TP_BJ14

BT15

RSVD_TP_BT15

AL32

RSVD_TP_AL32

AL34

RSVD_TP_AL34

AA18

RSVD_TP_AA18

Y18

RSVD_TP_Y18

CK13

RSVD_TP_CK13

CL34

RSVD_CL34

CL28

RSVD_CL28

AJ22

RSVD_AJ22

AL20

RSVD_AL20

AB6

PROC_OPI_COMP

CK6

RSVD_CK6

CL8

RSVD_CL8

AK25

RSVD_AK25

AL24

RSVD_AL24

N18

RSVD_N18

P33

RSVD_P33

AP3

RSVD_AP3

W21

RSVD_W21

AJ34

RSVD_AJ34

Y34

RSVD_Y34

Y33

RSVD_Y33

W33

RSVD_W33

UCPU1P

CH7

VSS

V2

VSS

E16

VSS

U24

VSS

R30

VSS

U22

VSS

G20

VSS

E20

VSS

N24

VSS

N28

VSS

N32

VSS

P35

VSS

R2

VSS

R4

VSS

R6

VSS

R8

VSS

R10

VSS

E24

VSS

R16

VSS

R22

VSS

E28

VSS

R24

VSS

R26

VSS

R28

VSS

AV7

VSS

E32

VSS

E36

VSS

R20

VSS

VSS_SENSE_CH43

16 OF 2 0REV = 1

BDW_Y_DDR3L_ BGA1234

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

N20

VSS

AK15

VSS

AM33

VSS

AK44

VSS

CA14

VSS

U28

VSS

U32

VSS

V17

VSS

V40

VSS

R44

VSS

T15

VSS

F5

VSS

G16

VSS

R18

VSS

U26

VSS

U34

VSS

G24

VSS

N16

VSS

AJ13

VSS

AC32

VSS

AL28

VSS

AL26

VSS

CJ20

VSS

CF39

VSS

CH43

VSSSENSE_R

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

RC38 & R C39 clo se to PC H

RC38 0_0402_ 5%@

RC39 100_040 2_1%

1 2
1 2

UCPU1T

T23

VSS

AR12

VSS

AU12

VSS

AV3

VSS

AV5

VSS

AV9

VSS

AC1

VSS

AC24

VSS

AC19

VSS

AH15

VSS

AB16

VSS

AB15

VSS

AB12

VSS

AB8

VSS

AA37

VSS

AA35

VSS

AC13

VSS

AA34

VSS

AA33

VSS

AA32

VSS

AA30

VSS

AA29

VSS

AA28

VSS

AB40

VSS

AA26

VSS

AA25

VSS

AA24

VSS

AA22

VSS

AA21

VSS

AA19

VSS

AA7

VSS

AA5

VSS

AA39

VSS

AA3

VSS

A40

VSS

A36

VSS

A20

VSS

A10

VSS

BM15

VSS

BP15

VSS

CN5

VSS

CR5

VSS

CU5

VSS

W28

VSS

W24

VSS

W19

VSS

AH22

VSS

AH21

VSS

AH20

VSS

AH19

VSS

AH17

VSS

BDW_Y_DDR3L_ BGA1234

@

UCPU1Q

J43

VSS

J1

VSS

D42

VSS

A42

VSS

Y44

VSS

W32

VSS

W35

VSS

Y2

VSS

Y12

VSS

Y14

VSS

Y16

VSS

W34

VSS

W30

VSS

T13

VSS

L38

VSS

Y42

VSS

A6

VSS

D4

VSS

H42

VSS

BDW_Y_DDR3L_ BGA1234

@

AD32

VSS

AH14

VSS

AH12

VSS

AG37

VSS

AG35

VSS

AG32

VSS

AG28

VSS

AG24

VSS

AG19

VSS

AF44

VSS

AF16

VSS

AF14

VSS

AF12

VSS

AF6

VSS

AE37

VSS

AE35

VSS

AE32

VSS

AE28

VSS

AE24

VSS

AE19

VSS

AE16

VSS

AD44

VSS

AD28

VSS

AD24

VSS

AD19

VSS

AD16

VSS

AD12

VSS

AD6

VSS

AC43

VSS

AC41

VSS

AC37

VSS

AC35

VSS

AC9

VSS

AC7

VSS

AC3

VSS

AB44

VSS

AC28

VSS

AD14

VSS

AC11

VSS

AC5

VSS

W18

VSS

W16

VSS

V44

VSS

U20

VSS

U14

VSS

T19

VSS

AH28

VSS

AH27

VSS

AH26

VSS

AH25

VSS

AH23

VSS

AV11

VSS

AH16

VSS

H4

VSS

A16

VSS

T29

VSS

20 OF 2 0REV = 1

CL32

VSS

CL30

VSS

CK33

VSS

CK29

VSS

CJ34

VSS

CG14

VSS

CE14

VSS

BW14

VSS

BR14

VSS

BN14

VSS

AF36

VSS

AA11

VSS

Y19

VSS

Y24

VSS

Y28

VSS

Y32

VSS

Y40

VSS

J3

VSS

J45

VSS

17 OF 2 0REV = 1

VSSSENSE 4 4

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P11-MCP(7/7) PWR,VSS,CFG

P11-MCP(7/7) PWR,VSS,CFG

P11-MCP(7/7) PWR,VSS,CFG

LA-9262P

LA-9262P

LA-9262P

1

13 51Wedne sday, August 13, 2014

13 51Wedne sday, August 13, 2014

13 51Wedne sday, August 13, 2014

0.1

0.1

0.1

Vinafix.com

5

4

3

2

1

follow INTEL PDG

12

CD1 .047U_0402_16 V7K

CD2 .047U_0402_16 V7K

12

1 2

CD3 .047U_0402_16 V7K

CD4 .047U_0402_16 V7K

D D

DDR_A_DQS#[0 ..7]6,15

DDR_A_DQS[0. .7]6,15

DDR_A_D[0..6 3]6,15

DDR_A_MA[0..15 ]6,15,1 8

All VREF traces should
have 10 mil trace width

C C

B B

1 2

PLACE TH ESE CAP S
NEAR TO RESPECT IVE DIMM PINS

+VREFCA

+VREFDQ_A

DDR3_DRAMRST#5 ,15,16,17

@

CAD NOTE :
PLACE TH E CAP N EAR TO
SDRAM RE SET PIN

1

CD5

2

0.1U_0402_ 25V6

+VREFCA
+VREFDQ_A

DDR_A_BS06 ,15,18
DDR_A_BS16 ,15,18
DDR_A_BS26 ,15,18

M_CLK_A_DDR06,15,1 8
M_CLK_A_DDR#06, 15,18

DDR_A_CKE06,15,18
DDR_A_CKE16,15,18
M_ODT015,18

DDR_A_CS0#6,15 ,18
DDR_A_CS1#6,15 ,18

DDR_A_RAS#6,15,18
DDR_A_CAS#6,15,18
DDR_A_WE#6,15 ,18

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M_CLK_A_DDR0
M_CLK_A_DDR#0

DDR_A_CKE0
DDR_A_CKE1
M_ODT0

DDR_A_CS0#
DDR_A_CS1#

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DQS0
DDR_A_DQS1

DDR_A_DQS#0
DDR_A_DQS#1

DDR3_DRAMRST#

12

RD1 240_0402_ 1%

RD3 240_0402_ 1%

12

UD1

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7

K9

J9
K1

J1

L2

L1

J3
K3

L3

F3
C7

G3
B7

E7
D3

T2

L8

L9

MT41K256M16 HA-125M:E_FBGA96

@

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC

BA0
BA1
BA2

CK
CK#

CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC

RAS#
CAS#
WE#

DQSL
DQSU

DQSL#
DQSU#

DML
DMU

RESET#

ZQ0

ZQ1/NC

96-BALL
SDRAM DDR3L

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

UD2

E3

DDR_A_D7

F7

DDR_A_D0

F2

DDR_A_D3

F8

DDR_A_D5

H3

DDR_A_D6

H8

DDR_A_D4

G2

DDR_A_D2

H7

DDR_A_D1

D7

DDR_A_D13

C3

DDR_A_D14

C8

DDR_A_D12

C2

DDR_A_D11

A7

DDR_A_D8

A2

DDR_A_D10

B8

DDR_A_D9

A3

DDR_A_D15

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.35V_DDR +1.35V_DDR

+VREFCA
+VREFDQ_A

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M_CLK_A_DDR0
M_CLK_A_DDR#0

DDR_A_CKE0
DDR_A_CKE1
M_ODT0

DDR_A_CS0#
DDR_A_CS1#

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DQS2
DDR_A_DQS3

DDR_A_DQS#2
DDR_A_DQS#3

DDR3_DRAMRST#

RD2 240_0402_1%

RD4 240_0402_1%

12

12

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

96-BALL

SDRAM DDR3L

MT41K256M16 HA-125M:E_FBGA96

@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

DDR_A_D23
DDR_A_D21
DDR_A_D19
DDR_A_D17
DDR_A_D18
DDR_A_D16
DDR_A_D22
DDR_A_D20

DDR_A_D31
DDR_A_D27
DDR_A_D29
DDR_A_D25
DDR_A_D26
DDR_A_D28
DDR_A_D24
DDR_A_D30

+1.35V_DDR

1U_0402 _6.3V6K

1U_0402 _6.3V6K

1U_0402 _6.3V6K

CD6

1

1

A A

5

2

2

4

1U_0402 _6.3V6K

CD8

CD7

1

1

2

2

1U_0402 _6.3V6K

1U_0402 _6.3V6K

CD9

CD10

1

1

2

2

10U_060 3_6.3V6M

10U_060 3_6.3V6M

CD11

1

2

1U_0402 _6.3V6K

CD13

CD12

1

1

2

2

10U_060 3_6.3V6M

1U_0402 _6.3V6K

CD14

1

2

3

10U_060 3_6.3V6M

CD16

1

2

Issued Date

Issued Date

Issued Date

1

2

CD17

1

@

+

CD18
330U_B2_2VM_R1 5M

2

Compal Secre t Data

Compal Secre t Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

CD15

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P12-DD RIII Chan nel_A Lower

P12-DD RIII Chan nel_A Lower

P12-DD RIII Chan nel_A Lower

LA-9262P

LA-9262P

LA-9262P

1

14 51Wedne sday, August 13, 2014

14 51Wedne sday, August 13, 2014

14 51Wedne sday, August 13, 2014

0.1

0.1

0.1

Vinafix.com

5

4

3

2

1

follow INTEL PDG

CD19 .047U_04 02_16V7K

12

12

CD20 .047U_04 02_16V7K

CD21 .047U_04 02_16V7K

D D

DDR_A_DQS#[0 ..7]6,14

DDR_A_DQS[0. .7]6,14

DDR_A_D[0..6 3]6,14

DDR_A_MA[0..15 ]6,14,1 8

All VREF traces should
have 10 mil trace width

C C

B B

1 2

1 2

CD22 .047U_04 02_16V7K

PLACE TH ESE CAP S
NEAR TO RESPECT IVE DIMM PINS

+VREFCA

+VREFDQ_A

DDR3_DRAMRST#5 ,14,16,17

CAD NOTE :
PLACE TH E CAP N EAR TO
SDRAM RE SET PIN

UD3

+VREFCA +VREFCA

1

@

CD23

0.1U_0402_ 25V6

2

+VREFDQ_A

DDR_A_BS06 ,14,18
DDR_A_BS16 ,14,18
DDR_A_BS26 ,14,18

M_CLK_A_DDR06,14,1 8
M_CLK_A_DDR#06, 14,18

DDR_A_CKE06,14,18
DDR_A_CKE16,14,18
M_ODT014,18

DDR_A_CS0#6,14 ,18
DDR_A_CS1#6,14 ,18

DDR_A_RAS#6,14,18
DDR_A_CAS#6,14,18
DDR_A_WE#6,14 ,18

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15 DDR_A_MA15

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M_CLK_A_DDR0
M_CLK_A_DDR#0

DDR_A_CKE0
DDR_A_CKE1
M_ODT0

DDR_A_CS0#
DDR_A_CS1#

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DQS7
DDR_A_DQS5

DDR_A_DQS#7
DDR_A_DQS#5

DDR3_DRAMRST#

RD5 240_0402_ 1%

12

12

RD7 240_0402_ 1%

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

96-BALL
SDRAM DDR3L

MT41K256M16 HA-125M:E_FBGA96

@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

DDR_A_D62
DDR_A_D59
DDR_A_D63
DDR_A_D58
DDR_A_D57
DDR_A_D61
DDR_A_D56
DDR_A_D60

DDR_A_D43
DDR_A_D44
DDR_A_D40
DDR_A_D46
DDR_A_D45
DDR_A_D42
DDR_A_D41
DDR_A_D47

+1.35V_DDR +1.35V_DDR

+VREFDQ_A

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

M_CLK_A_DDR0
M_CLK_A_DDR#0

DDR_A_CKE0
DDR_A_CKE1
M_ODT0

DDR_A_CS0#
DDR_A_CS1#

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DQS6
DDR_A_DQS4

DDR_A_DQS#6
DDR_A_DQS#4

DDR3_DRAMRST#

RD6 240_0402_ 1%

RD8 240_0402_ 1%

12

12

UD4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC

BA0
BA1
BA2

CK
CK#

CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC

RAS#
CAS#
WE#

DQSL
DQSU

DQSL#
DQSU#

DML
DMU

RESET#

ZQ0

ZQ1/NC

96-BALL
SDRAM DDR3L

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

T8
R3
L7
R7
N7
T3
T7

M7

M2

N8

M3

J7
K7

K9
J9
K1
J1
L2
L1

J3
K3
L3

F3
C7

G3

B7

E7
D3

T2

L8

L9

MT41K256M16 HA-125M:E_FBGA96

@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3

DDR_A_D54

F7

DDR_A_D50

F2

DDR_A_D48

F8

DDR_A_D49

H3

DDR_A_D53

H8

DDR_A_D51

G2

DDR_A_D55

H7

DDR_A_D52

D7

DDR_A_D38

C3

DDR_A_D32

C8

DDR_A_D36

C2

DDR_A_D39

A7

DDR_A_D33

A2

DDR_A_D37

B8

DDR_A_D34

A3

DDR_A_D35

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.35V_DDR

1U_0402 _6.3V6K

1

2

A A

5

4

1U_0402 _6.3V6K

1U_0402 _6.3V6K

CD24

1

2

1U_0402 _6.3V6K

CD26

CD25

1

1

2

2

1U_0402 _6.3V6K

1U_0402 _6.3V6K

CD27

CD28

1

1

2

2

10U_060 3_6.3V6M

10U_060 3_6.3V6M

CD29

1

2

1U_0402 _6.3V6K

CD31

CD30

1

1

2

2

3

10U_060 3_6.3V6M

CD33

Issued Date

Issued Date

Issued Date

10U_060 3_6.3V6M

CD34

CD35

1

1

2

2

Compal Secre t Data

Compal Secre t Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1U_0402 _6.3V6K

CD32

1

2

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P13-DD RIII Chan nel_A Upper

P13-DD RIII Chan nel_A Upper

P13-DD RIII Chan nel_A Upper

LA-9262P

LA-9262P

LA-9262P

1

15 51Wedne sday, August 13, 2014

15 51Wedne sday, August 13, 2014

15 51Wedne sday, August 13, 2014

0.1

0.1

0.1

Vinafix.com

5

4

3

2

1

follow INTEL PDG

CD36 .047U_04 02_16V7K

12

12

CD37 .047U_04 02_16V7K

CD38 .047U_04 02_16V7K

D D

DDR_B_DQS#[0 ..7]6,17

DDR_B_DQS[0. .7]6,17

DDR_B_D[0..6 3]6,17

DDR_B_MA[0..15 ]6,17,18

All VREF traces should
have 10 mil trace width

C C

B B

1 2

1 2

CD39 .047U_04 02_16V7K

PLACE TH ESE CAP S
NEAR TO RESPECT IVE DIMM PINS

+VREFCA

+VREFDQ_B

DDR3_DRAMRST#5,14,15,17

CAD NOTE :
PLACE TH E CAP N EAR TO
SDRAM RE SET PIN

@

1

CD40

2

0.1U_0402_ 25V6

+VREFCA
+VREFDQ_B

DDR_B_BS06,17 ,18
DDR_B_BS16,17 ,18
DDR_B_BS26,17 ,18

M_CLK_B_DDR06,17,18
M_CLK_B_DDR#06,17, 18

DDR_B_CKE06,1 7,18
DDR_B_CKE16,1 7,18
M_ODT21 7,18

DDR_B_CS0#6,17,18
DDR_B_CS1#6,17,18

DDR_B_RAS#6,1 7,18
DDR_B_CAS#6,1 7,18
DDR_B_WE#6,17,18

UD5

M8

VREFCA

H1

VREFDQ

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15 DDR_B_MA15

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

M_CLK_B_DDR0
M_CLK_B_DDR#0

DDR_B_CKE0
DDR_B_CKE1
M_ODT2

DDR_B_CS0#
DDR_B_CS1#

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DQS3

DDR_B_DQS#3
DDR_B_DQS#0

RD9 240_0402_ 1%

RD11 240_040 2_1%

12

12

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

T7

A14

M7

A15/NC

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE0

J9

CKE1/NC

K1

ODT0

J1

ODT1/NC

L2

CS0#

L1

CS1#/NC

J3

RAS#

K3

CAS#

L3

WE#

F3

DQSL

C7

DQSU

G3

DQSL#

B7

DQSU#

E7

DML

D3

DMU

T2

RESET#

L8

ZQ0

L9

ZQ1/NC

96-BALL
SDRAM DDR3L

MT41K256M16 HA-125M:E_FBGA96

@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E3

DDR_B_D28

F7

DDR_B_D24

F2

DDR_B_D29

F8

DDR_B_D26

H3

DDR_B_D25

H8

DDR_B_D30

G2

DDR_B_D27

H7

DDR_B_D31

D7

DDR_B_D3

C3

DDR_B_D1

C8

DDR_B_D4

C2

DDR_B_D0

A7

DDR_B_D6

A2

DDR_B_D2

B8

DDR_B_D7

A3

DDR_B_D5

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.35V_DDR +1.35V_DDR

+VREFCA
+VREFDQ_B

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

M_CLK_B_DDR0
M_CLK_B_DDR#0

DDR_B_CKE0
DDR_B_CKE1
M_ODT2

DDR_B_CS0#
DDR_B_CS1#

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DQS2
DDR_B_DQS1DDR_B_DQS0

DDR_B_DQS#2
DDR_B_DQS#1

DDR3_DRAMRST#DDR3_DRAMRST#

12

RD10 240_040 2_1%

12

RD12 240_040 2_1%

UD6

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15/NC

BA0
BA1
BA2

CK
CK#

CKE0
CKE1/NC
ODT0
ODT1/NC
CS0#
CS1#/NC

RAS#
CAS#
WE#

DQSL
DQSU

DQSL#
DQSU#

DML
DMU

RESET#

ZQ0

ZQ1/NC

96-BALL
SDRAM DDR3L

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

T8
R3
L7
R7
N7
T3
T7

M7

M2

N8

M3

J7
K7

K9
J9
K1
J1
L2
L1

J3
K3
L3

F3
C7

G3

B7

E7
D3

T2

L8

L9

MT41K256M16 HA-125M:E_FBGA96

@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E3

DDR_B_D22

F7

DDR_B_D21

F2

DDR_B_D16

F8

DDR_B_D18

H3

DDR_B_D17

H8

DDR_B_D20

G2

DDR_B_D19

H7

DDR_B_D23

D7

DDR_B_D9

C3

DDR_B_D14

C8

DDR_B_D8

C2

DDR_B_D15

A7

DDR_B_D12

A2

DDR_B_D10

B8

DDR_B_D11

A3

DDR_B_D13

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.35V_DDR

1U_0402 _6.3V6K

1U_0402 _6.3V6K

CD41

1

A A

5

1

2

2

4

1U_0402 _6.3V6K

1U_0402 _6.3V6K

CD42

CD43

1

1

2

2

1U_0402 _6.3V6K

1U_0402 _6.3V6K

CD44

CD45

1

1

2

2

10U_060 3_6.3V6M

10U_060 3_6.3V6M

CD46

1

2

1U_0402 _6.3V6K

CD48

CD47

1

1

2

2

10U_060 3_6.3V6M

1U_0402 _6.3V6K

CD49

1

2

3

10U_060 3_6.3V6M

1

2

1

CD52

+

CD53
330U_B2_2VM_R1 5M

2

Compal Secre t Data

Compal Secre t Data

2011/06/02 2013/10/28

2011/06/02 2013/10/28

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

CD51

CD50

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

Compal Electron ics, Inc.

Compal Electron ics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electron ics, Inc.

P14-DD RIII Chan nel_B Lower

P14-DD RIII Chan nel_B Lower

P14-DD RIII Chan nel_B Lower

LA-9262P

LA-9262P

LA-9262P

1

16 51Wedne sday, August 13, 2014

16 51Wedne sday, August 13, 2014

16 51Wedne sday, August 13, 2014

0.1

0.1

0.1