Dell latitude 7300,latitude 7400 Schematics

5

4

3

2

1

COMPAL CONFIDENTIAL

MODEL NAME :EDC40

D D

PCB NO : LA-G871P
BOM P/N : 431ADY31L0x

Merion 14 AR

Whiskey lake-U U42

2019-03-05

REV : 1.0 (A00)

@ : Nopop Component

EMI@ : EMI Component

@EMI@ : EMI Nopop Component

ESD@ : ESDComponent

@ESD@ : ESD Nopop Component

C C

RF@ : RF Component

@RF@ : RF Nopop Component

CONN@ : Connector Component

CXDP@ : XDP Component

DS3@ : Deep sleep support
NDS3@ : non Deep sleep support

750@ : NUVOTON NPCT750 TPM Component

B B

ST33@ : ST ST33HTPH TPM Component

RTD3@ : RTD3 support

@RTD3@ : RTD3 Nopop Component

NRTD3@ : non RTD3 support

MB PCB

Part Number

DAA000HW010

Description

PCB 2EE LA-G871P REV1 MB AR 1

VPRO@ : vPro Component
NVPRO@ : Non-vPro Component

Layout Dell logo

JUMP@ : Jump solder and short

A A

Power CKT : Merion 14_WHL_PWR_X02_1228a

COPYRIGHT 2018

ALL RIGHT RESERVED
REV:A00
PWB: 7YM2P

5

GPIO map : 20181221a Rev1.5

@JUMP@ : Jump no solder

i7@ : Only i7 config support 4*4 antenna

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

4

3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-G871P

LA-G871P

LA-G871P

1 109Tuesday, March 05, 2 019

1 109Tuesday, March 05, 2 019

1 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

5

4

3

2

1

Merion14 AR Block Diagram

Memory BUS (DDR4)

DDR4 2400MHz for WHL-U

D D

2-Lane eDP1.3

P38

PCIE[5][6][7][8]

HDMI 1.4
CONN

EDP CONN

HDMI

P40

AR-SP

P42-4 3

SMBus

SATA[1]/PC IE[12]

M.2,2230 Key E

P52

WLAN+BT/CNVi

USB2.0[7] USB2.0[10]

PCIE[10]

P52

Left side TypeC

USB2.0

USB2.0[1] from PCH

C C

SMBus

P45

PD Solut i on
TPS65982DD

TBT

P44,50

PCIE[9]

Card reader
RTS524 2

SD4.0

Micro SIM

P70

P70

P52

M.2,3042 Key B

WWAN/LTE/HCA

PCIex2 for 2nd SSD and
Optane

CNVi

EDP

DDI[1]

DDI[2]

INTEL

WHL-U 42 MCP

PAGE 6~19

USB/PCIE MUX

PCIE[11]

HD3SS3212

P54

USB3.0[4]

SPI

SATA[2]/PCIE[16][15] [14][13]

Pop option

GD25B256 DYIG

B B

vPro use

256Mb 4K sector WSON8

P8

GD25B64CYIGR

P8

P8

P63

P63

Smart Card

USH board

TDA8034HN

RFID/NFC

Fingerprint
CONN

Fingerprint
MOCV

Non-vPro use

64Mb 4K sector WSO N8

GD25B127D SIGR

USB2.0[8]

SPI

USH TPM1.2
BCM58202

SPI

FP-USB2.0

P66

ESPI

SMSC KBC
MEC510 5

P58-5 9

Non-vPro use

128Mb 4K sector SOP8

TPM2.0
ST-ST33HTPH 2032AHC 1

BC link

KB/TP CONN

PWM

FAN CONN

Up to 2x16GB Modules

USB

I2C

P66

USB2.0[2]

SLGC55544BVTR
USB POWER SHARE

HD Audio I/F

Reverse Type

DDR4-SO-DIMM X2

BANK 0, 1, 2, 3

P23~24

I2C[0]

USB2.0[6]

USB2.0[2]_PS

P71

USB3.0[2]

USB2.0[3]

USB3.0[3]

I2C[3]

HDA Codec
ALC3254

M.2 2280

SSD Conn

P56

P68

LCD Touch

USB3.0 Conn
PS(Ext Port 1)

USB3.0 Conn
(Ext Port 2)

Active Steering Antenna
(MB

)

INT.Speaker

Universal Jack

Dig. MIC

Camera

P38

P38

P71

P72

P56

P56

P38

Trough eDP Cable

Trough eDP Cable

Right side

Left side

P9

LED/B

Bettery LED

Breath LED

LID SWITCH

USH CONN

CPU&PCH XDP Port

AUTOMATIC POWER
SWITCH(APS)

DC/DC Interface

POWER ON/OFF SW

P64

P64

P66

P79

P79

P78

P77

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

Document Num ber Re v

Document Num ber Re v

Document Num ber Re v

LA-G871P

LA-G871P

LA-G871P

1

2 109Tuesday, March 05, 2019

2 109Tuesday, March 05, 2019

2 109Tuesday, March 05, 2019

1.0

1.0

1.0

5

JUSB2-->Lef t

4

POWER STATES

Signal

State

S0 (Full ON) / M0

D D

S3 (Suspend to RAM) / M3 LOW

S4 (Suspend to DISK) / M3

S5 (SOFT OFF) / M3

S3 (Suspend to RAM) / M-OFF

SLP
S3#

HIGH

LOW

LOW

SLP

SLP

S5#

S4#

HIGH HIGH

HIGH HIGH

HIGH HIGH

LOW

LOW

LOW

HIGH HIGH

SLP
A#

HIGH

HIGH

HIGH

LOW

ALW AYS
PLANE

ON

ON ON ON

ON ON

ON ON

ON ON

M
PLANE

ON

OFF OFF OFF

SUS
PLANE

RUN
PLAN E

ON ON ON

OFF

OFF

OFF

OFF

OFFLOW

CLOCKS

OFF

OFF

OFF

3

USB3.0

USB3.0-1

USB3.0-2

USB3.0-3

USB3.0-4

USB3.0-5

USB3.0-6

SSIC

PCIE

PCIE-1

PCIE-2

PCIE-3

PCIE-4

PCIE-5

PCIE-6

PCIE-7

PCIE-8

SATA

PCIE-9

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

C C

LOW LOW LOW

LOW LOW LOW LOW

HIGH

ON

ON

OFF OFF OFF OFF

OFF OFF OFF OFF

PCIE-10 M.2 2230(BT)

PCIE-11

PCIE-12

SATA-0

SATA-1

PCIE-13

PCIE-14

PCIE-15

PCIE-16

SATA-1*

SATA-2

2

N/A

JUSB1-->Right

M.2 3042(LTE)

Alpine Ridge - SP

Card Reader

M.2 2230(WLAN)

M.2 3042(LTE)

M.2 2280 SSD
(PCIex4 or SATA)

USB PORT#DESTINATION

1

2

3

4

5

6

7

8

9

10

1

DESTINATION

Type C

JUSB1-->Right

JUSB2-->Left

N/A

N/A

Camera

M2 3042(WWAN)

USH

Reserve for FPR in PB

PM TABLE

+5V_ALW

+3.3V_ALW

B B

State

S0

S5 S4/AC

S5 S4/AC doesn't exist OFFOFF OFF

A A

power
plane

5

+3.3V_ALW_DSW

+3.3V_ALW_PCH

+RTC_CELL

+1.8V_PRIM

+5V_ALW2

+3.3V_ALW2

+3.3V_RTC_LDO

+1.0V_PRIM

ON

ON

+1.2V_MEM

+2.5V_MEM

+1.0V_VCCSTG

ON ON

OFF OFF

+5V_RUN

+3.3V_RUN

+0.6V_DDR_VTT

+1.8V_RUN

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-G871P

LA-G871P

LA-G871P

3 109Tuesday, March 05, 2 019

3 109Tuesday, March 05, 2 019

3 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

5

Barrel
ADAPT ER

D D

Type-C
ADAPTER

CHARGER
ISL9538
(PU700)

+13.5VB

4

SY8210A
(PU200)

SY8286R
(PU301)

SYV828C

(PU102)

SIO_SLP_S4#

0.6V_DDR_ VTT_ON

PCH_P RIM_EN

ALWO N

+1.2V_MEM

+0.6V_DDR_VTT

+1.0V_PRIM

+5V_ALW

+5V_ALW2

3

TPS22961

(UZ27)

VCCSTG_ EN

SY8057BQ

(PU401)

SY8057CQ

(PU402)

EM5209

(UZ47)

+VCCPLL_OC

RUN_ ON

PCH_P RIM_EN

RUN_ ON

+1.0VS_VCCIO

+1.0V_PRIM_CORE

BATTERY

SY8288B

C C

(PU100)

ALWO N

+3.3V_RTC_LDO

+3.3V_ALW2

SLGC55544C

(UI3)

SY6288

(UI1)

USB_PW R_SHR_ VBUS_EN

USB_PW R_EN1#

2

TPS22961

(UZ19)

TPS22961

(UZ21)

+5V_RUN

+5V_USB_CHG_PWR

+USB_EX2_PWR

VCCSTG_ EN

RUN_ ON

+1.0V_VCCSTG

+1.0V_VCCST

Merion 14 Touch PWR is +5V

PJV1701

(QV8)

EM5209

(@UZ5)

3.3V_TS_EN

AUD_PW R_EN

1

CPU PWR

PCH PWR

Peripheral Device PWR

TYPE-C Power

+TS_PWR

+5V_RUN_AUDIO

+3.3V_ALW

RT8097A

FDMF3035

ISL95808

(PU614)

B B

IMVP_V R_ON

FDMF3035

(PU612)

IMVP_V R_ON

+VCC_GT+VCC_SA

+5V_ALW

(PU610)
FDMF303 5
(PU613)

IMVP_V R_ON

+VCC_CORE

TPS65982DD

(UT5)

AO6405

(QV1)

EN_IN VPWR

+BL_PWR_SRC

+20V_TBTA_VBUS_1(5V~20V)

TYPE-C

+20V_TBTA_VBUS_1(5V~20V)

A A

AP2204

(UT8)

+5V_ALW

+5V_TBT_VBUS

AP2112 K

(UT7)

+3.3V_VDD_PIC

Reserved

5

4

3

(PU501)

EM5209

(UZ47)

EM5209

(UZ3)

EM5209

(UZ4)

G527ATP1U

(UV24)

AP7361C

(PU503)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

PCH_P RIM_EN

WLAN_ PWR_EN

PCH_P RIM_EN

RUN_ ON

3.3V_W WAN_EN

EN_LC DPWR

SIO_SLP_S4#

+1.8V_PRIM

+3.3V_W LAN

+3.3V_ALW_PCH

+3.3V_RUN

+3.3V_W WAN

+LCDV DD

+2.5V_MEM

for D DR4

2

AOZ1336

(UZ8)

EM5209

(@UZ5)

PJV1701

(QZ1)

DELL CONFIDENTIAL/PROPRIETARY

RUN_ ON

AUD_PW R_EN

3.3V_CAM_ EN#

Title

Title

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

+1.8V_RUN

+3.3V_RUN_AUDIO

+3.3V_CAM

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Power rails

Power rails

Power rails

LA-G871P

LA-G871P

LA-G871P

1

4 109Tuesday, March 05, 2019

4 109Tuesday, March 05, 2019

4 109Tuesday, March 05, 2019

1.0

1.0

1.0

1

PCH

PWRBTN#

RSMRST#

SLP_SUS #

SLP_S5 #

SLP_S4 #

SLP_S3 #

SLP_LAN#

SLP_WLAN#/GPD 9

PCH_PWRO K

VCCST_PWRGD

PROCPWRGD

SLP_A#

2

SIO_PWRBTN#

PCH_RSMRST #

SIO_SLP_SU S#

SIO_SLP_S5 #

SIO_SLP_S4 #

SIO_SLP_S3 #

SIO_SLP_A#

SIO_SLP_LAN#

SIO_SLP_WLAN#

RESET_OUT#

PCH_PWRO K

VCCST_PWRGD

H_CPUPWR GD

16

15

10

11

14

12

8

7

5

9

3

+3.3V_ALW

+3.3V_SPI

3

+1.0V_MPHYGT

5

6

+1.0V_PRIM_C ORE

6

17

4

+3.3V_ALW

G524B1T11

+3.3V_ALW

EM5209VF+3.3V_LAN

+5V_RU N

LP2301ALT1G

+3.3V_RUN

LP2301ALT1G+3.3V_CAM

+1.0V_PRIM

+3.3V_ALW_DSW

+3.3V_ALW_PCH

+1.8V_PRIM

+RTC_CEL L

PCH_PLTRS T#

PCH_DPWR OK

ENVDD_PCH

SIO_SLP_LAN#

@PCH_3.3V_TS _EN

3.3V_TS_EN (EC)

3.3V_CAM_EN#

VCCPRIM_1P0
VCCPRIM_CORE
DCPDSW _1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
VCCCLK1~ 6
VCCMPHYGT_1P0
VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB

VCCDSW_3P 3

VCCHDA
VCCSPI
VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM

VCCPGPPG
VCCATS

VCCRTC

VCCPRIM_CORE

PLTRST#

DSW_PWROK

EDP_VDDEN

SLP_LAN#

GPP_B21

GPD7

5

4

Timing Diagram for S5 to S0 mode

D D

6

C C

VCCST_PWRGD

12

H_CPUPWR GD

15

PCH_PLTRS T#

17

0.6V_DDR_VTT_ON

12

+1.0V_PRIM_C ORE

+1.8V_PRIM

6

6

+1.0V_PRIM SY8286

CPU

VCCST_PWRGD

PROCPWRGD

PLTRST#

DDR_VTT_CNT L

+PWR_SR C

TPS62134

+3.3V_ALW

+VCC_CO RE

VCC

+1.0VS_VCCIO

VCCIO SYS_PWROK

+VCC_GT

VCCGT

+1.2V_MEM

VDDQ
VDDQC
VCCPLL_OC

VCCST
VCCSTG
VCCPL L

VCCSA

+1.0V_VCC ST

+VCC_S A

11

+1.0V_PRIM

TPS22961

SIO_SLP_S4 #

+LCDVD D

SIO_SLP_SU S#

11

RT8097

+PWR_SR C

+5V_TSP

Power Button

SIO_SLP_WLAN#

11

11

RUN_ON

+5V_ALW

EM5209VF

+5V_RU N

ADAPTER

+3.3V_ALW

EC 5105

10

+PWR_SR C

ISL95857

PCH_PWRO K

14

BATTERY

7

4

16

5

9

11

PCH_RSMRST #

PCH_DPWR OK

RESET_OUT#

SIO_SLP_SU S#

SIO_SLP_S4 #

SIO_SLP_S5 #

SIO_SLP_LAN#

SIO_SLP_S3 #

SIO_SLP_A#

12

IMVP_VR_ON

EM5209VF

11

3.3V_WWAN_EN

+1.8V_PRIM

EM5209VF +1.8V_RUN

+PWR_SR C

TLV62130

+3.3V_ALW

EM5209VF

SLP_WLAN#_GATE

OR
Gate

SIO_SLP_WLAN#

NMOS

AUX_EN_WOWL

B B

+3.3V_ALW

+3.3V_WLAN

11

A A

EM5209VF

+3.3V_RUN

+1.0VS_VCCIO

+3.3V_WWAN

13

+3.3V_HDD_M2

+VCC_S A

+VCC_CO RE

+VCC_GT

2AC1BAT

ALWON

PCH_PRIM_EN

EN_INVPWR

0.6V_DDR_VTT_ON

5

10

SIO_SLP_S4 #

+PWR_SR C

SYV828EC 5105

+PWR_SR C

SY8288

+3.3V_ALW

EM5209VF

+PWR_SR C

AO6405

+5V_ALW2
+5V_ALW

+3.3V_ALW2
+3.3V_ALW

+PWR_SR C

SY8210

+3.3V_RTC _LDO

+3.3V_ALW_PCH

+BL_PWR_S RC

+1.2V_MEM

+0.6V_DDR _VTT

12

1BAT

2AC

5

18

VDDQ

VTT

DDR

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET O F ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFO RMATION OF DELL INC. ("DELL ") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLO SED TO ANY THIRD
PARTY WITHOUT D ELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Power Sequence

Power Sequence

Power Sequence

LA-G871P

LA-G871P

LA-G871P

1

5 109Tuesday, March 05 , 2019

5 109Tuesday, March 05 , 2019

5 109Tuesday, March 05 , 2019

1.0

1.0

1.0

5

4

3

2

1

For 2LANE EDP

+3.3V_RUN

D D

C C

CPU_DP1_CTRL_CLK

2

1

RC503 2.2K_0402_5%

CPU_DP1_CTRL_DATA

2

1

RC178 2.2K_0402_5%

CPU_DP2_CTRL_CLK

12

RC176 2.2K_0402_5%

CPU_DP2_CTRL_DATA

12

RC502 2.2K_0402_5%

All VREF traces should
have 10 mil trace width

AR

+1.0VS_VCCIO

COMPENSATION PU FOR eDP
CAD Note:
Trace width=5 mils
Isolation Spacing=25mil,
Max length=100 mils.

CPU_DP1_N0<42>

CPU_DP1_P0<42>

CPU_DP1_N1<42>

CPU_DP1_P1<42>

CPU_DP1_N2<42>

CPU_DP1_P2<42>

CPU_DP1_N3<42>

CPU_DP1_P3<42>

CPU_DP2_N0<42>

CPU_DP2_P0<42>

CPU_DP2_N1<42>

CPU_DP2_P1<42>

CPU_DP2_N2<42>

CPU_DP2_P2<42>

CPU_DP2_N3<42>

CPU_DP2_P3<42>

1

RC8 24.9_0402_1%

CPU_DP1_CTRL_CLK<42>

CPU_DP1_CTRL_DATA<42>

+3.3V_ALW_PCH

1 2

@

RC101

2

GPP_H17

20K_0402_5%

EDP_COMP

CPU_DP1_CTRL_CLK

CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

GPP_H17

CPU@

UC1A

AL5

DDI1_TXN_0

AL6

DDI1_TXP_0

AJ5

DDI1_TXN_1

AJ6

DDI1_TXP_1

AF6

DDI1_TXN_2

AF5

DDI1_TXP_2

AE5

DDI1_TXN_3

AE6

DDI1_TXP_3

AC4

DDI2_TXN_0

AC3

DDI2_TXP_0

AC1

DDI2_TXN_1

AC2

DDI2_TXP_1

AE4

DDI2_TXN_2

AE3

DDI2_TXP_2

AE1

DDI2_TXN_3

AE2

DDI2_TXP_3

AM6

DISP_RCOMP

CC8

GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#

CC9

GPP_E19/DPPB_CTRLDATA

CH4

GPP_E20/DPPC_CTRLCLK

CH3

GPP_E21/DPPC_CTRLDATA

CP4

GPP_E22/DPPD_CTRLCLK

CN4

GPP_E23/DPPD_CTRLDATA

CR26

GPP_H16/DDPF_CTRLCLK

CP26

GPP_H17/DDPF_CTRLDATA

WHL-U42_BGA1528

DDI

DISPLAY SIDEBANDS

AG4

EDP_TXN_0

AG3

EDP_TXP_0

AG2

EDP_TXN_1

AG1

EDP_TXP_1

AJ4

EDP

GPP_E13/DDPB_HPD0/DISP_MISC0
GPP_E14/DDPC_HPD1/DISP_MISC1

GPP_E15/DPPD_HPD2/DISP_MISC2
GPP_E16/DPPE_HPD3/DISP_MISC3

GPP_E17/EDP_HPD/DISP_MISC4

1 of 20

EDP_TXN_2
EDP_TXP_2

EDP_TXN_3
EDP_TXP_3

EDP_AUX_N
EDP_AUX_P

DISP_UTILS

DDI1_AUX_N

DDI1_AUX_P
DDI2_AUX_N

DDI2_AUX_P
DDI3_AUX_N

DDI3_AUX_P

EDP_BKLTEN

EDP_VDDEN

EDP_BKLTCTL

AJ3

AJ2
AJ1

AH4
AH3

AM7

AC7

AC6
AD4

AD3
AG7

AG6

CN6
CM6

CP7
CP6

CM7

CK11

CG11
CH11

CPU_DP1_AUXN

CPU_DP1_AUXP

CPU_DP2_AUXN
CPU_DP2_AUXP

CPU_DP3_AUXN
CPU_DP3_AUXP

CPU_DP1_HPD
CPU_DP2_HPD

EDP_HPD

EDP_TXN0 <38>

EDP_TXP0 <38>

EDP_TXN1 <38>

EDP_TXP1 <38>

EDP_AUXN <38>

EDP_AUXP <38>

CPU_DP1_AUXN <42>
CPU_DP1_AUXP <42>

CPU_DP2_AUXN <42>
CPU_DP2_AUXP <42>

1

@

PAD~D

1

@

PAD~D

CPU_DP1_HPD <42>

CPU_DP2_HPD <42>

EDP_HPD <38>

PANEL_BKLEN <38>

ENVDD_PCH <38>

EDP_BIA_PWM <38>

EDP_HPD

T1

T2

2

1

RC2100K_0402_5%

+3.3V_ALW_PCH

RC753

This strap should sample HIGH.
There should NOT be any on-board device

CPU@

UC1I

CR30

CNV_WR_D0N

CP30

CNV_WR_D0P

CM30

CNV_WR_D1N

CN30

CNV_WR_D1P

CN32

CNV_WT_D0N

CM32

CNV_WT_D0P

CP33

CNV_WT_D1N

CN33

CNV_WT_D1P

CN31

CNV_WR_CLKN

CP31

CNV_WR_CLKP

CP34

CNV_WT_CLKN

CN34

CNV_WT_CLKP

CP32

CNV_WT_RCOMP_0

CR32

CNV_WT_RCOMP_1

CP20

GPP_F0/CNV_PA_BLANKING

CK19

GPP_F1

CG17

GPP_F2

CR14

GPP_C8/UART0_RXD

CP14

GPP_C9/UART0_TXD

CN14

GPP_C10/UART0_RTS#

CM14

GPP_C11/UART0_CTS#

CJ17

GPP_F8/CNV_MFUART2_RXD

CH17

GPP_F9/CNV_MFUART2_TXD

CF17

GPP_F23/A4WP_PRESENT

WHL-U42_BGA1528

CNVio

9 of 20

3

GPP_H18/CPU_C10_GATE#

GPP_H19/TIMESYNC_0

GPP_H21/XTAL_FREQ_SELECT

GPP_D4/IMGCLKOUT0/BK4/SBK4

GPP_H20/IMGCLKOUT_1

GPP_F12/EMMC_DATA0
GPP_F13/EMMC_DATA1

GPP_F14/EMMC_DATA2

EMMC

GPP_F15/EMMC_DATA3

GPP_F16/EMMC_DATA4
GPP_F17/EMMC_DATA5

GPP_F18/EMMC_DATA6
GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F11/EMMC_CMD

GPP_F22/EMMC_RESET#

EMMC_RCOMP

GPP_H22
GPP_H23

GPP_F10

GPD7

GPP_F3

1

CNV_COEX3<52>

SBIOS_TX<79>

CNV_COEX2<52>
CNV_COEX1<52>

CNV_PRX_DTX_N0
CNV_PRX_DTX_P0

CNV_PRX_DTX_N1
CNV_PRX_DTX_P1

CNV_PTX_DRX_N0

CNV_PTX_DRX_P0

CNV_PTX_DRX_N1

CNV_PTX_DRX_P1

CLK_CNV_PRX_DTX_N
CLK_CNV_PRX_DTX_P

CLK_CNV_PTX_DRX_N

CLK_CNV_PTX_DRX_P

CNV_WT_RCOMP

2

RC448150_0402_1%

CNV_COEX3

PCH_TBT_PERST#

SBIOS_TX
TYPEC_CON_SEL1

TYPEC_CON_SEL2

CNV_COEX2
CNV_COEX1

CNV_PRX_DTX_N0<52>

CNV_PRX_DTX_P0<52>

CNV_PRX_DTX_N1<52>

CNV_PRX_DTX_P1<52>

CNV_PTX_DRX_N0<52>

CNV_PTX_DRX_P0<52>

CNV_PTX_DRX_N1<52>

B B

+3.3V_ALW_PCH

1

1

PCH_TBT_PERST#

PCH_TBT_PERST#

2

RC557 10K_0402_5%RTD3@

2

RC754 10K_0402_5%@

CNV_PTX_DRX_P1<52>

CLK_CNV_PRX_DTX_N<52>

CLK_CNV_PRX_DTX_P<52>

CLK_CNV_PTX_DRX_N<52>

CLK_CNV_PTX_DRX_P<52>

PCH_TBT_PERST#<42>

Reserve

+3.3V_ALW_PCH+3.3V_ALW_PCH

RC744

@

10K_0402_5%

1 2

TYPEC_CON_SEL2TYPEC_CON_SEL1

12

RC745

@

10K_0402_5%

A A

Vendor TBDTBDFOXCONJAE

TYPEC_CON_SEL 1

TYPEC_CON_SEL 2

5

LOW

LOW

LOW

HIGH

@

10K_0402_5%

1 2

12

@

10K_0402_5%

LOW

RC743

RC63

HIGHHIGH

HIGH

4

driving it to opposite direction during strap sampling.

CPU_C10_GATE#

CN27

CM27

GPP_H21

CF25

RTD3_CIO_PWR_EN

CN26

GPP_H23

CM26

CK17

TBT_RTD3_WAKE#

BV35

CN20

TBT_FORCE_PWR

CG25

CH25

MEM_CONFIG0

CR20

MEM_CONFIG1

CM20

MEM_CONFIG2

CN19

MEM_CONFIG3

CM19

MEM_CONFIG4

CN18
CR18

CP18
CM18

CM16
CP16

CR16
CN16

EMMC_RCOMP

CK15

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXP RESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

CPU_C10_GATE# <17,87>

RTD3_CIO_PWR_EN <42>

TBT_RTD3_WAKE# <42>

TBT_FORCE_PWR < 42>

1

@

T408

PAD~D

1

@

T409

PAD~D

1

@

T410

PAD~D

1

@

T411

PAD~D

1

@

T412

PAD~D

Jony_01/16 : CK15 - Keep 200 ohm
575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pdf

1 2

RC10 200_0402_1%

2

RTD3_CIO_PWR_EN

@

10K_0402_5%

1 2

4.7K_0402_5%

20K_0402_5%

4.7K_0402_5%

20K_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

CPU(1/14)DDI,EDP,CSI2,EMMC

CPU(1/14)DDI,EDP,CSI2,EMMC

CPU(1/14)DDI,EDP,CSI2,EMMC

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

+3.3V_ALW_PCH

RC95

100K_0402_5%

TBT_RTD3_WAKE#

RC443

RC444

@

@

RC537

RC446

@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1 2

RC454

@

20K_0402_5%

1 2

+3.3V_ALW_PCH

1 2

GPP_H21

LOW: 38.4/19.2MHZ (DEFAULT)
HIGH: 24MHZ

1 2

+3.3V_ALW_PCH

0 = Master Attached Flash Sharing
(MAFS) enabled. (Default)
1 = Slave Attached Flash Sharing
(SAFS) enabled.

1 2

GPP_H23

1 2

LA-G871P

LA-G871P

LA-G871P

1

6 109Tuesday, March 05, 2019

6 109Tuesday, March 05, 2019

6 109Tuesday, March 05, 2019

1.0

1.0

1.0

5

DDR4, Ballout for side by side(Non-Interleave)

4

3

2

1

D D

CPU@

UC1B

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D4

DDR_A_D5

DDR_A_D6
DDR_A_D7

DDR_A_D8
DDR_A_D9

DDR_A_D10
DDR_A_D11

DDR_A_D12
DDR_A_D13

DDR_A_D14
DDR_A_D15

DDR_A_D32
DDR_A_D33

DDR_A_D34
DDR_A_D35

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D40
DDR_A_D41

C C

B B

DDR_A_D42
DDR_A_D43

DDR_A_D44
DDR_A_D45

DDR_A_D46
DDR_A_D47

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3

DDR_B_D4

DDR_B_D5
DDR_B_D6

DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10

DDR_B_D11
DDR_B_D12

DDR_B_D13
DDR_B_D14

DDR_B_D15
DDR_B_D32

DDR_B_D33
DDR_B_D34

DDR_B_D35
DDR_B_D36

DDR_B_D37
DDR_B_D38

DDR_B_D39
DDR_B_D40

DDR_B_D41
DDR_B_D42

DDR_B_D43
DDR_B_D44

DDR_B_D45
DDR_B_D46

DDR_B_D47

Interleave / Non-Interleaved

A26

DDR0_DQ_0/DDR0_DQ_0

D26

DDR0_DQ_1/DDR0_DQ_1

D28

DDR0_DQ_2/DDR0_DQ_2

C28

DDR0_DQ_3/DDR0_DQ_3

B26

DDR0_DQ_4/DDR0_DQ_4

C26

DDR0_DQ_5/DDR0_DQ_5

B28

DDR0_DQ_6/DDR0_DQ_6

A28

DDR0_DQ_7/DDR0_DQ_7

B30

DDR0_DQ_8/DDR0_DQ_8

D30

DDR0_DQ_9/DDR0_DQ_9

B33

DDR0_DQ_10/DDR0_DQ_10

D32

DDR0_DQ_11/DDR0_DQ_11

A30

DDR0_DQ_12/DDR0_DQ_12

C30

DDR0_DQ_13/DDR0_DQ_13

B32

DDR0_DQ_14/DDR0_DQ_14

C32

DDR0_DQ_15/DDR0_DQ_15

H37

DDR0_DQ_16/DDR0_DQ_32

H34

DDR0_DQ_17/DDR0_DQ_33

K34

DDR0_DQ_18/DDR0_DQ_34

K35

DDR0_DQ_19/DDR0_DQ_35

H36

DDR0_DQ_20/DDR0_DQ_36

H35

DDR0_DQ_21/DDR0_DQ_37

K36

DDR0_DQ_22/DDR0_DQ_38

K37

DDR0_DQ_23/DDR0_DQ_39

N36

DDR0_DQ_24/DDR0_DQ_40

N34

DDR0_DQ_25/DDR0_DQ_41

R37

DDR0_DQ_26/DDR0_DQ_42

R34

DDR0_DQ_27/DDR0_DQ_43

N37

DDR0_DQ_28/DDR0_DQ_44

N35

DDR0_DQ_29/DDR0_DQ_45

R36

DDR0_DQ_30/DDR0_DQ_46

R35

DDR0_DQ_31/DDR0_DQ_47

AN35

DDR0_DQ_32/DDR1_DQ_0

AN34

DDR0_DQ_33/DDR1_DQ_1

AR35

DDR0_DQ_34/DDR1_DQ_2

AR34

DDR0_DQ_35/DDR1_DQ_3

AN37

DDR0_DQ_36/DDR1_DQ_4

AN36

DDR0_DQ_37/DDR1_DQ_5

AR36

DDR0_DQ_38/DDR1_DQ_6

AR37

DDR0_DQ_39/DDR1_DQ_7

AU35

DDR0_DQ_40/DDR1_DQ_8

AU34

DDR0_DQ_41/DDR1_DQ_9

AW35

DDR0_DQ_42/DDR1_DQ_10

AW34

DDR0_DQ_43/DDR1_DQ_11

AU37

DDR0_DQ_44/DDR1_DQ_12

AU36

DDR0_DQ_45/DDR1_DQ_13

AW36

DDR0_DQ_46/DDR1_DQ_14

AW37

DDR0_DQ_47/DDR1_DQ_15

BA35

DDR0_DQ_48/DDR1_DQ_32

BA34

DDR0_DQ_49/DDR1_DQ_33

BC35

DDR0_DQ_50/DDR1_DQ_34

BC34

DDR0_DQ_51/DDR1_DQ_35

BA37

DDR0_DQ_52/DDR1_DQ_36

BA36

DDR0_DQ_53/DDR1_DQ_37

BC36

DDR0_DQ_54/DDR1_DQ_38

BC37

DDR0_DQ_55/DDR1_DQ_39

BE35

DDR0_DQ_56/DDR1_DQ_40

BE34

DDR0_DQ_57/DDR1_DQ_41

BG35

DDR0_DQ_58/DDR1_DQ_42

BG34

DDR0_DQ_59/DDR1_DQ_43

BE37

DDR0_DQ_60/DDR1_DQ_44

BE36

DDR0_DQ_61/DDR1_DQ_45

BG36

DDR0_DQ_62/DDR1_DQ_46

BG37

DDR0_DQ_63/DDR1_DQ_47

WHL-U42 _BGA1528

DDR_A_DQS#[0..7]<23>

DDR_A_D[0..63]<23>

DDR_A_DQS[0..7]<23>

DDR_A_MA[0..16]<23>

2 of 20

LPDDR3 / DDR4

DDR0_CKN_0/DDR0_CKN_0

DDR0_CKP_0/DDR0_CKP_0

DDR0_CKN_1/DDR0_CKN_1

DDR0_CKP_1/DDR0_CKP_1

DDR0_CKE_0/DDR0_CKE_0

DDR0_CKE_1/DDR0_CKE_1

DDR0_CKE_2/NC

DDR0_CKE_3/NC

DDR0_CS#_0/DDR0_CS#_0

DDR0_CS#_1/DDR0_CS#_1

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1

DDR0_CAB_9/DDR0_MA_0

DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3
NC/DDR0_MA_4

DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6

DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8

DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10

DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12

DDR0_CAB_0/DDR0_MA_13

DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_3/DDR0_MA_16

DDR0_CAB_4/DDR0_BA_0

DDR0_CAB_6/DDR0_BA_1
DDR0_CAA_5/DDR0_BG_0

DDR0_CAA_8/DDR0_ACT#

DDR0_CAA_9/DDR0_BG_1

Interleave / Non-Interleaved

DDR0_DQSN_0/DDR0_DQSN_0

DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSN_1/DDR0_DQSN_1

DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSN_2/DDR0_DQSN_4

DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSN_3/DDR0_DQSN_5

DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSN_4/DDR1_DQSN_0

DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSN_5/DDR1_DQSN_1

DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSN_6/DDR1_DQSN_4

DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_7/DDR1_DQSP_5

LPDDR3 / DDR4

NC/DDR0_ALERT#

NC/DDR0_PAR

DDR_VREF_CA

DDR0_VREF_DQ_0

DDR0_VREF_DQ_1

DDR1_VREF_DQ

DDR_VTT_CTL

V32

V31
T32

T31

U36

U37
U34

U35

AE32

AF32
AE31

AF31

AC37

AC36
AC34

AC35
AA35

AB35
AA37

AA36
AB34

W36
Y31

W34
AA34

AC32

AC31
AB32

Y32

W32

AB31
V34

V35

W35

C27

D27
D31

C31
J35

J34
P34

P35
AP35

AP34
AV34

AV35
BB35

BB34
BF34

BF35

W37

W31

F36
D35

D37
E36

C35

DDR_A_CLK#0

DDR_A_CLK0
DDR_A_CLK#1

DDR_A_CLK1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CKE2
DDR_A_CKE3

DDR_A_CS#0
DDR_A_CS#1

DDR_A_ODT0

DDR_A_ODT1

DDR_A_CLK#0 <23>
DDR_A_CLK0 <23>

DDR_A_CLK#1 <23>
DDR_A_CLK1 <23>

DDR_A_CKE0 <23>
DDR_A_CKE1 <23>

1

@

T351

PAD~D

1

@

T350

PAD~D

DDR_A_CS#0 <23>
DDR_A_CS#1 <23>

DDR_A_ODT0 <23>

DDR_A_ODT1 <23>

DDR_A_MA0 <23>

DDR_A_MA1 <23>

DDR_A_MA2 <23>

DDR_A_MA3 <23>

DDR_A_MA4 <23>

DDR_A_MA5 <23>

DDR_A_MA6 <23>

DDR_A_MA7 <23>

DDR_A_MA8 <23>

DDR_A_MA9 <23>

DDR_A_MA10 <23>

DDR_A_MA11 <23>
DDR_A_MA12 <23>

DDR_A_MA13 <23>

DDR_A_MA14 <23>

DDR_A_MA15 <23>

DDR_A_MA16 <23>

DDR_A_BA0 <23>

DDR_A_BA1 <23>

DDR_A_BG0 <23>

DDR_A_ACT# <23>
DDR_A_BG1 <23>

DDR_A_DQS#0 <23>

DDR_A_DQS0 <23>
DDR_A_DQS#1 <23>

DDR_A_DQS1 <23>
DDR_A_DQS#4 <23>

DDR_A_DQS4 <23>
DDR_A_DQS#5 <23>

DDR_A_DQS5 <23>
DDR_B_DQS#0 <24>

DDR_B_DQS0 <24>
DDR_B_DQS#1 <24>

DDR_B_DQS1 <24>
DDR_B_DQS#4 <24>

DDR_B_DQS4 <24>
DDR_B_DQS#5 <24>

DDR_B_DQS5 <24>

DDR_A_ALERT# <23>

DDR_A_PARITY <23>

DDR_VTT_CTRL <23>

DDR0_PAR,DDR0_ALERT#
for DDR4

+DDR_VREF_CA

+DDR_VREF_B_DQ

DDR_A_D16
DDR_A_D17

DDR_A_D18
DDR_A_D19

DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_A_D28
DDR_A_D29

DDR_A_D30
DDR_A_D31

DDR_A_D48
DDR_A_D49

DDR_A_D50

DDR_A_D51
DDR_A_D52

DDR_A_D53
DDR_A_D54

DDR_A_D55

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

DDR_A_D60
DDR_A_D61

DDR_A_D62
DDR_A_D63

DDR_B_D16
DDR_B_D17

DDR_B_D18
DDR_B_D19

DDR_B_D20
DDR_B_D21

DDR_B_D22

DDR_B_D23
DDR_B_D24

DDR_B_D25
DDR_B_D26

DDR_B_D27

DDR_B_D28
DDR_B_D29

DDR_B_D30
DDR_B_D31

DDR_B_D48
DDR_B_D49

DDR_B_D50
DDR_B_D51

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

DDR_B_D60
DDR_B_D61

DDR_B_D62
DDR_B_D63

DDR_B_DQS#[0..7]<24>

DDR_B_D[0..63]<24>

DDR_B_DQS[0..7]<24>

DDR_B_MA[0..16]<24>

CPU@

UC1C

lnterleave /
Non-lnterle ave d

J22

DDR1_DQ_0/DDR0_DQ_16

H25

DDR1_DQ_1/DDR0_DQ_17

G22

DDR1_DQ_2/DDR0_DQ_18

H22

DDR1_DQ_3/DDR0_DQ_19

F25

DDR1_DQ_4/DDR0_DQ_20

J25

DDR1_DQ_5/DDR0_DQ_21

G25

DDR1_DQ_6/DDR0_DQ_22

F22

DDR1_DQ_7/DDR0_DQ_23

D22

DDR1_DQ_8/DDR0_DQ_24

C22

DDR1_DQ_9/DDR0_DQ_25

C24

DDR1_DQ_10/DDR0_DQ_26

D24

DDR1_DQ_11/DDR0_DQ_27

A22

DDR1_DQ_12/DDR0_DQ_28

B22

DDR1_DQ_13/DDR0_DQ_29

A24

DDR1_DQ_14/DDR0_DQ_30

B24

DDR1_DQ_15/DDR0_DQ_31

G31

DDR1_DQ_16/DDR0_DQ_48

G32

DDR1_DQ_17/DDR0_DQ_49

H29

DDR1_DQ_18/DDR0_DQ_50

H28

DDR1_DQ_19/DDR0_DQ_51

G28

DDR1_DQ_20/DDR0_DQ_52

G29

DDR1_DQ_21/DDR0_DQ_53

H31

DDR1_DQ_22/DDR0_DQ_54

H32

DDR1_DQ_23/DDR0_DQ_55

L31

DDR1_DQ_24/DDR0_DQ_56

L32

DDR1_DQ_25/DDR0_DQ_57

N29

DDR1_DQ_26/DDR0_DQ_58

N28

DDR1_DQ_27/DDR0_DQ_59

L28

DDR1_DQ_28/DDR0_DQ_60

L29

DDR1_DQ_29/DDR0_DQ_61

N31

DDR1_DQ_30/DDR0_DQ_62

N32

DDR1_DQ_31/DDR0_DQ_63

AJ29

DDR1_DQ_32/DDR1_DQ_16

AJ30

DDR1_DQ_33/DDR1_DQ_17

AM32

DDR1_DQ_34/DDR1_DQ_18

AM31

DDR1_DQ_35/DDR1_DQ_19

AM30

DDR1_DQ_36/DDR1_DQ_20

AM29

DDR1_DQ_37/DDR1_DQ_21

AJ31

DDR1_DQ_38/DDR1_DQ_22

AJ32

DDR1_DQ_39/DDR1_DQ_23

AR31

DDR1_DQ_40/DDR1_DQ_24

AR32

DDR1_DQ_41/DDR1_DQ_25

AV30

DDR1_DQ_42/DDR1_DQ_26

AV29

DDR1_DQ_43/DDR1_DQ_27

AR30

DDR1_DQ_44/DDR1_DQ_28

AR29

DDR1_DQ_45/DDR1_DQ_29

AV32

DDR1_DQ_46/DDR1_DQ_30

AV31

DDR1_DQ_47/DDR1_DQ_31

BA32

DDR1_DQ_48/DDR1_DQ_48

BA31

DDR1_DQ_49/DDR1_DQ_49

BD31

DDR1_DQ_50/DDR1_DQ_50

BD32

DDR1_DQ_51/DDR1_DQ_51

BA30

DDR1_DQ_52/DDR1_DQ_52

BA29

DDR1_DQ_53/DDR1_DQ_53

BD29

DDR1_DQ_54/DDR1_DQ_54

BD30

DDR1_DQ_55/DDR1_DQ_55

BG31

DDR1_DQ_56/DDR1_DQ_56

BG32

DDR1_DQ_57/DDR1_DQ_57

BK32

DDR1_DQ_58/DDR1_DQ_58

BK31

DDR1_DQ_59/DDR1_DQ_59

BG29

DDR1_DQ_60/DDR1_DQ_60

BG30

DDR1_DQ_61/DDR1_DQ_61

BK30

DDR1_DQ_62/DDR1_DQ_62

BK29

DDR1_DQ_63/DDR1_DQ_63

WHL-U42 _BGA1528

DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_0/DDR1_CKP_0

DDR1_CKN_1/DDR1_CKN_1
DDR1_CKP_1/DDR1_CKP_1

DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1

DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1

DDR1_CAB_5/DDR1_MA_2

DDR1_CAA_0/DDR1_MA_5

DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8
DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11

DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13

DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_3/DDR1_MA_16

DDR1_CAB_4/DDR1_BA_0

DDR1_CAB_6/DDR1_BA_1
DDR1_CAA_5/DDR1_BG_0

DDR1_CAA_9/DDR1_BG_1
DDR1_CAA_8/DDR1_ACT#

DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQSP_0/DDR0_DQSP_2

DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSP_1/DDR0_DQSP_3

DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSP_2/DDR0_DQSP_6

DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSP_3/DDR0_DQSP_7

DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQSP_4/DDR1_DQSP_2

DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQSP_5/DDR1_DQSP_3

DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSP_6/DDR1_DQSP_6

DDR1_DQSN_7/DDR1_DQSN_7
DDR1_DQSP_7/DDR1_DQSP_7

3 of 20

LPDDR3 / DDR4

DDR1_CKE_2/NC
DDR1_CKE_3/NC

NC/DDR1_ODT_1

NC/DDR1_MA_3

NC/DDR1_MA_4

lnterleave / Non-lnterleaved

NC/DDR1_ALERT#

NC/DDR1_PAR

DRAM_RESET#

DDR_RCOMP_0

DDR_RCOMP_1
DDR_RCOMP_2

AF28
AF29

AE28
AE29

T28
T29

V28
V29

AL37
AL35

AL36
AL34

AG36
AG35

AF34
AG37

AE35
AF35

AE37
AC29

AE36
AB29

AG34
AC28

AB28
AK35

AJ35
AK34

AJ34

AJ37

AJ36
W29

Y28
W28

H24
G24

C23
D23

G30
H30

L30
N30

AL31
AL30

AU31
AU30

BC31
BC30

BH31
BH30

Y29
AE34

BU31

BN28

BN27
BN29

DDR_B_CLK#0

DDR_B_CLK0

DDR_B_CLK#1

DDR_B_CLK1

DDR_B_CKE0

DDR_B_CKE1

DDR_B_CS#0

DDR_B_CS#1

DDR_B_ODT0

DDR_B_ODT1

DDR_B_ALE RT#
DDR_B_PAR ITY

DDR_DRAMRS T#

SM_RCOMP0
SM_RCOMP1

SM_RCOMP2

DDR_B_CLK#0 <24>

DDR_B_CLK0 <24>
DDR_B_CLK#1 <24>

DDR_B_CLK1 <24>

DDR_B_CKE0 <24>
DDR_B_CKE1 <24>

1

@

T353

PAD~D

1

@

T354

PAD~D

DDR_B_CS#0 <24>
DDR_B_CS#1 <24>

DDR_B_ODT0 <24>

DDR_B_ODT1 <24>

DDR_B_MA0 <24>
DDR_B_MA1 <24>

DDR_B_MA2 <24>

DDR_B_MA3 <24>

DDR_B_MA4 <24>

DDR_B_MA5 <24>

DDR_B_MA6 <24>

DDR_B_MA7 <24>

DDR_B_MA8 <24>

DDR_B_MA9 <24>

DDR_B_MA10 <24>

DDR_B_MA11 <24>

DDR_B_MA12 <24>

DDR_B_MA13 <24>

DDR_B_MA14 <24>

DDR_B_MA15 <24>
DDR_B_MA16 <24>

DDR_B_BA0 <24>

DDR_B_BA1 <24>

DDR_B_BG0 <24>

DDR_B_BG1 <24>

DDR_B_ACT# <24>

DDR_A_DQS#2 <23>

DDR_A_DQS2 <23>

DDR_A_DQS#3 <23>

DDR_A_DQS3 <23>
DDR_A_DQS#6 <23>

DDR_A_DQS6 <23>
DDR_A_DQS#7 <23>

DDR_A_DQS7 <23>
DDR_B_DQS#2 <24>

DDR_B_DQS2 <24>
DDR_B_DQS#3 <24>

DDR_B_DQS3 <24>
DDR_B_DQS#6 <24>

DDR_B_DQS6 <24>
DDR_B_DQS#7 <24>

DDR_B_DQS7 <24>

DDR_B_ALERT# <24>
DDR_B_PARITY <24>

DDR_DRAMRST# <23>

DDR1_PAR,DDR1_ALERT#
for DDR4

Hank3/5:575962_WHL_DDR4_RVP_RN_TDK_Rev0p7.pdf page12,keep setting

DDR4 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

A A

CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

1 2

RC5 121_040 2_1%

1 2

RC504 80.6_0402_ 1%

1 2

RC7 100_040 2_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

CPU(2/14)DDR4

CPU(2/14)DDR4

CPU(2/14)DDR4

Document Num ber Re v

Document Num ber Re v

Document Num ber Re v

LA-G871P

LA-G871P

LA-G871P

1

7 109Tuesd ay, March 05, 2 019

7 109Tuesd ay, March 05, 2 019

7 109Tuesd ay, March 05, 2 019

1.0

1.0

1.0

5

SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236

PCH_SPI_CLK

PCH_SPI_D1

PCH_CL_DATA1<52>

PCH_CL_CLK1<52>

PCH_CL_RST1#<52>

ESPI_ALERT#<58>

1031 change

PCH_SPI_D0
PCH_SPI_D2

PCH_SPI_D3

PCH_SPI_CS#0
PCH_SPI_CS#1

PCH_SPI_CS#2

RTC_DET#

1 2

PCH_SPI_DO_XDP<79>

PCH_SPI_DO2_XDP<79>

D D

+1.8V_PRIM

1 2

RC244 10K_040 2_1%

C C

RC833 100K_0402_ 5%@

RC96 10 0K_0402_5%

RC505 1K _0402_1%CXDP@

1 2

RC11 1K_0402_1%CXDP@

PCH_SPI_CS#2<66>

RTC_DET#<83>

MEDIACARD_IRQ#<70>

ESPI_ALERT#

ESPI_RESE T#

12

PCH_SPI_CLK

12

ESPI_ALERT#

CH37
CF37

CF36
CF34

CG34
CG36

CG35
CH34

CF20
CG22

CF22
CG23

CH23
CG20

BV29

BV28

CH7
CH8

CH9

For signal deglitch, refer to 575412_WHL_U_PDG rev0p8

4

CPU@

UC1E

SPI0_CLK
SPI0_MISO

SPI0_MOSI
SPI0_IO2

SPI - FLASH

SPI0_IO3
SPI0_CS0#

SPI0_CS1#
SPI0_CS2#

GPP_D1/SPI1_CLK/BK1/SBK1
GPP_D2/SPI1_MISO_IO1/BK2/SBK2

GPP_D3/SPI1_MOSI_IO0/BK3/SBK3
GPP_D21/SPI1_IO2

GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS0#/BK0/SBK0

CL_CLK
CL_DATA

CL_RST#

GPP_A0/RCIN#/TIME_SYNC1

GPP_A6/SERIRQ

WHL-U42 _BGA1528

SPI - TOUCH

C LINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

SMBUS , SMLINK

LPC , ESPI

5 of 20

WEAK INTERNAL PU WEAK INTERNAL PU

BOOT HALT

HIGH
LOW

+3.3V_ALW _PCH

WEAK INTERNAL PU

A0 PERSONALITY STRAP

HIGH
LOW

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1

GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

+3.3V_ALW _PCH

12

RC94

100K_0402_ 5%

PCH_SPI_D0

12

RC518

@

4.7K_0402_ 5%

Disa bled
Enabled

12

RC62

100K_0402_ 5%

PCH_SPI_D3

12

RC515

@

4.7K_0402_ 5%

PLACE RC62 AND RC515 CLOS
TO THE SPI SIGNAL TO AVOID STUB

Disa bled
Enabled

3

MEM_SMBCLK

CK14

MEM_SMBDATA

CH15

GPP_C2

CJ15

SML0_SMBCLK

CH14

SML0_SMBDATA

CF15

GPP_C5

CG15

SML1_SMBCLK

CN15

SML1_SMBDATA

CM15

GPP_B23

CC34

ESPI_IO0_R

CA29

ESPI_IO1_R

BY29

ESPI_IO2_R

BY27

ESPI_IO3_R

BV27

CA28
CA27

ESPI_CLK

BV32

BV30

GPP_A8

BY30

566439_CNL_PCH_UY_EDS_Vol_1_Rev_1. 1.pdf
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V. This strap should sample HIGH.
There should NOT be any on-board device driving it to opposite direction
during strap sampling.

Merion no RJ45 LAN p ort

SML1_SMBCLK <58>
SML1_SMBDATA <58>

1 2

RC366 15_0402_5%

1 2

RC367 15_0402_5%

1 2

RC368 15_0402_5%

1 2

RC369 15_0402_5%

ESPI_CS# <58,79>
ESPI_RESET# <58,79>

1 2

RC19 33 _0402_5% EMI@

+3.3V_ALW _PCH

12

RC61

100K_0402_ 5%

PCH_SPI_D2

12

RC519

@

4.7K_0402_ 5%

PLACE RC61 AND RC519 CLOS

CONSENT STRAP

HIGH
LOW

TO THE SPI SIGNAL TO AVOID STUB

Disa bled
Enabled

ESPI_IO0 <58,79>
ESPI_IO1 <58,79>

ESPI_IO2 <58,79>
ESPI_IO3 <58,79>

RVP 15 ohm
575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pd f

ESPI_CLK_5105 <58,79>

2

ESPI_CLK_51 05

SML0_SMB CLK

SML1_SMB CLK

MEM_SMB CLK

RF Request

1 2

CC316@RF@ 33P_0402_50V8J

1 2

CC318@RF@ 33P_0402_50V8J

1 2

CC319@RF@ 33P_0402_50V8J

1 2

CC320@RF@ 33P_0402_50V8J

Place close CPU side

Merion Limit height
QC2 change to SB000014O00 H=0.6mm(MAX)

+3.3V_RUN

1

QC2

S1

2

G1

MEM_SMBCLK

6

D1

4

S2

5

G2

MEM_SMBDATA

D2

PJX138K_ SOT563-6

3

1219 Change

1

DDR_XDP_WAN_SMBCLK <23,24,79>

DDR_XDP_WAN_SMBDAT <23,24,79>

DDR_XDP_WAN_SMBDAT

DDR_XDP_WAN_SMBCLK

MEM_SMBCLK

MEM_SMBDATA

SML1_SMBCLK

SML1_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

RTC_DET#

RC318 2.2K_0402_5%

RC319 2.2K_0402_5%

GPP_A8

1 2

1 2

1 2

RC849 8.2K_04 02_5%@

1 2

RC12 1 K_0402_5%

1 2

RC14 1 K_0402_5%

1 2

RC15 1 K_0402_5%

1 2

RC507 1K_040 2_5%

1 2

RC347 499_040 2_1%@

1 2

RC348 499_040 2_1%@

1 2

RC866 10K_02 01_5%

1031 change

+3.3V_RUN

+3.3V_ALW_PCH

Follow RVP pull up change to 4.7K

B B

PCH_SPI_D1_ R1<66>

PCH_SPI_D0_ R1<66>

PCH_SPI_CLK _R1<6 6>

Pop optio n at P.102

For vPro
256Mb WSON8 Flash ROM
For Non-vPro

PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R

33_0402_5%

@EMI@

12

RC289

A A

33P_0402_50V8J

12

CC1452

5

33_0402_5%

@EMI@

12

RC299

33P_0402_50V8J

@EMI@

@EMI@

12

CC1453

PCH_SPI_CS#0_R1

PCH_SPI_D2_R1

PCH_SPI_CS#1_R1 PCH_SPI_CS#1_R2

PCH_SPI_D2_R1

1 2

RC32 0_0201_5%@

1 2

RC33 49.9_0201_1%

VPRO@

NVPRO@

1 2

RC302 0_0201_5%

1 2

RC35 33 _0201_1%

NVPRO@

4

PCH_SPI_CS#0_R2

PCH_SPI_D1_0_R
PCH_SPI_D2_0_R

PCH_SPI_D1_1_R
PCH_SPI_D2_1_R

64Mb WSON8 Flash ROM

UC5VPRO@

1

CS#

2

SO(IO1)

3

IO2

4

VSS

ThemalPad

GD25B256DYIG_W SON8_8X6

For Non-vPro
128Mb SOP8 Flash ROM

UC6NVPRO@

1

CS#

2

DO(IO1)

3

IO2

4

GND

DI(IO0)

GD25B127DS IGR_SO8

SOFTWARE TAA

VPRO PDG P.296 R1 50 ohm

PCH_SPI_D1_R1

RC734 49.9_0201_ 1%VPRO@

PCH_SPI_D0_R1

RC570 49.9_0201_ 1%VPRO@

PCH_SPI_CLK_R1

RC571 49.9_0201_ 1%VPRO@

PCH_SPI_D3_R1

RC572 49.9_0201_ 1%VPRO@

NVPRO follow PDG P.298 R1 33 ohm

PCH_SPI_D1_R1

RC573 33_0201_1%NVPRO@

PCH_SPI_D0_R1

RC574 33_0201_1%NVPRO@

PCH_SPI_CLK_R1

RC575 33_0201_1%NVPRO@

PCH_SPI_D3_R1

RC576 33_0201_1%NVPRO@

PDG SPI0 2 resistor 50ohm, SPI0 3 resistor 33ohm
CLOSEED TO ROM
Please place close for future replace to RP

+3.3V_SPI

8

VCC

PCH_SPI_D3_0_R

7

IO3

PCH_SPI_CLK_0_R

6

SCLK

PCH_SPI_D0_0_R

5

SI(IO0)

9

+3.3V_SPI

8

PCH_SPI_D3_1_R

VCC

7

IO

PCH_SPI_CLK_1_R

6

CLK

PCH_SPI_D0_1_R

5

3

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

CC9

1 2

0.1U_0201_1 0V6K

NVPRO@

CC10

1 2

0.1U_0201_1 0V6K

PCH_SPI_D1_0_R

PCH_SPI_D0_0_R

PCH_SPI_CLK_0_R

PCH_SPI_D3_0_R

PCH_SPI_D1_1_R

PCH_SPI_D0_1_R

PCH_SPI_CLK_1_R

PCH_SPI_D3_1_R

Pop optio n at P.102

Pop optio n at P.102

VPRO PDG P.296 R2 5 ohm
NVPRO PDG P.298 R2 10 ohm

1 2

RC24 0_ 0201_5%NVPRO@

1 2

RC25 4. 99_0201_1%

VPRO@

1 2

RC26 4. 99_0201_1%

VPRO@

1 2

RC27 4. 99_0201_1%

VPRO@

1 2

RC28 0_ 0201_5%@

1 2

RC29 4. 99_0201_1%

VPRO@

1 2

RC30 4. 99_0201_1%

VPRO@

+3.3V_SPI

+3.3V_ALW _PCH

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

PROM_BIOS_R<63 >

1 2

RC31 0_ 0201_5%@

DC4

RB521CM-30T2R _SOD923-2

PCH_SPI_CS# 1_R1

PCH_SPI_D0_ R1

PCH_SPI_D1_ R1

PCH_SPI_CLK _R1

PCH_SPI_CS# 0_R1

PCH_SPI_D2_ R1

PCH_SPI_D3_ R1

21

PCH_SPI_CS# 1

PCH_SPI_D0

PCH_SPI_D1

PCH_SPI_CLK

PCH_SPI_CS# 0

PCH_SPI_D2

PCH_SPI_D3

JSPI1

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

GND1

22

GND2

ACES_5050 6-02041-P01

2

DELL CONFIDENTIAL/PROPRIETARY

GPP_C2

RC266 4.7K _0402_5%

TLS CONFIDENTIALITY

HIGH
LOW(DEFAULT)

GPP_C5

RC277 4.7K _0402_5%

GPP_C5

@

RC397 20K _0402_5%

EC interface

HIGH
LOW (DEFAULT)

GPP_B23

RC317 150K_0402_5%

for DCI-OOB

EXI BOOT STALL BYPASS

HIGH
LOW(DEFAULT)

WEAK INTERNAL PD

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

CPU(3/14)SPI,ESPI,SMB,LPC

CPU(3/14)SPI,ESPI,SMB,LPC

CPU(3/14)SPI,ESPI,SMB,LPC

Document Num ber Re v

Document Num ber Re v

Document Num ber Re v

LA-G871P

LA-G871P

LA-G871P

1

1 2

ENABLE
DISABLE

1 2

1 2

ESPI

LPC

1 2

ENABLED
DIABLED

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_ALW_PCH

8 109Tuesd ay, March 05, 2 019

8 109Tuesd ay, March 05, 2 019

8 109Tuesd ay, March 05, 2 019

1.0

1.0

1.0

BOOT BIOS Dest i nat i on(Bi t 6)

+3.3V_ALW_PCH

1 2

Place close CPU side

1 2

1 2

1 2

1 2

1 2

1 2

12

12

1

@

RC400
10K_0402_5 %

10K_0402_5 %
RC401

+3.3V_ALW_PCH

+3.3V_RUN

+3.3V_RUN

TBT_DET#

HIG H NON AR

LOW AR

5

@

T12

PAD~D

TPM_PIRQ#< 66>

PCH_3.3V_TS_EN<38>

RC710,RC711 change to 33oh m from 75ohm,

D D

PU OPTION TO AVOID RSP SIGNALS

+1.8V_PRIM

C C

+3.3V_RUN

B B

FROM FLOATING IN CASE INTERNAL PUS NOT ENABLED IN A0

I2C3_A NT for ACTIVE S TEERING ANT for MERIO N

+3.3V_ALW_PC H

1 2

RC831 4.7K_0402_5 %

12

12

12

12

12

12

NRB_BIT

RC72420K _0402_5% @

RC73320K _0402_5% @

RC747100K_0402_ 5% @

RC84110K_0402_5 % @

RC5122.2K_ 0201_5%

RC5132.2K_ 0201_5%

CNV_BRI_PRX_DTX<52>

CNV_RGI_PTX_DRX_R<52>

CNV_BRI_PTX_DRX_R<52>

CNV_RGI_PRX_DTX<52>

CNV_BRI_PRX_DTX

CNV_RGI_PRX_DTX

PCH_3.3V_TS_ EN

GPP_A7

I2C3_ANT_SDA

I2C3_ANT_SCL

M.2 CNVI MODES

0 = Integrated CNVi enable.
1 = Integrated CNVi disable. (Disable CNVi for bring up)
WEAK INTERNAL PU

follow Intel MOW WW32

1 2

RC710 33_0402_5 %

1 2

RC711 33_0402_5 %

RC710,RC711 place d closer to PCH.

3MM_CAM_DET #<38>

P_SENSOR_PWR_SAVE#<38>

SMART_SPK_DET1#<56>

TS_INT#<38>

TS

TP

Follow RVP,PDG pull up change to 20K

+1.8V_PRIM

TS_I2C_SDA<38 >

TS_I2C_SCL<38>

I2C1_SDA_TP<63>

I2C1_SCK_TP<63>

@

T388

PAD~D

@

T389

PAD~D

566439_CNL_PCH_LP__EDS_Rev1p2
P.119 Primary Well Group H (Per-pad 1.8 V or 3.3 V)
Please setting 3.3V

add I2C3 TP for for sensor IC(Reserved)
add I2C3_ANT TP for ACTIVE STEERING ANT for MERION

20K_0402_5%

RC842

1 2

CNV_RGI_PTX_DRX_R

12

4.7K_0402_5%

@

RC832

NO REBOOT STRAP

HIGH
LOW(DEFAULT)

Weak IPD

No REBOOT

REBOOT ENABLE

4

PRIM_CORE_OPT_ DIS

GPP_A7

ONE_DIMM#

NRB_BIT

1

PME#

TPM_PIRQ#

PCH_3.3V_TS_ EN

GPP_B22

CNV_BRI_PRX_DTX

CNV_RGI_PTX_DRX

CNV_BRI_PTX_DRX

CNV_RGI_PRX_DTX

3MM_CAM_DET #

P_SENSOR_PW R_SAVE#

SMART_SPK_DET 1#

TS_INT#

I2C2_SDA_ALS

1

I2C2_SCL_ALS

1

I2C3_ANT_SDA
I2C3_ANT_SCL

CPU@

UC1F

CC27

GPP_B15/GSPI0_CS0#

CC32

GPP_A7/PIRQA#/GSPI0_CS1#

CE28

GPP_B16/GSPI0_CLK

CE27

GPP_B17/GSPI0_MISO

CE29

GPP_B18/GSPI0_MOSI

CA31

GPP_B19/GSPI1_CS0#

CA32

GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#

CC29

GPP_B20/GSPI1_CLK

CC30

GPP_B21/GSPI1_MISO

CA30

GPP_B22/GSPI1_MOSI

CK20

GPP_F5/CNV_BRI_RSP

CG19

GPP_F6/CNV_RGI_DT

CJ20

GPP_F4/CNV_BRI_DT

CH19

GPP_F7/CNV_RGI_RSP

CR12

GPP_C20/UART2_RXD

CP12

GPP_C21/UART2_TXD

CN12

GPP_C22/UART2_RTS#

CM12

GPP_C23/UART2_CTS#

CM11

GPP_C16/I2C0_SDA

CN11

GPP_C17/I2C0_SCL

CK12

GPP_C18/I2C1_SDA

CJ12

GPP_C19/I2C1_SCL

CF27

GPP_H4/I2C2_SDA

CF29

GPP_H5/I2C2_SCL

CH27

GPP_H6/I2C3_SDA

CH28

GPP_H7/I2C3_SCL

CJ30

GPP_H8/I2C4_SDA

CJ31

GPP_H9/I2C4_SCL

WHL-U42 _BGA1528

I2C , UART

1031 change,RC435 reserve for FUSE location

+3.3V_RUN

I2C3_ANT_SCL

I2C3_ANT_SDA

RF Request

+3.3V_RUN_R

100P_0201_50V8J

@RF@

1

CC1466

2

place as close as JASA1

Reserved for wake on voice

SIO_SLP_S0#<11,17,66,79,87>

1218 add RC867 reserve for BITS3921 23

Active Steering Antenna circuit

1 2

RC435 0_0603_5%

1 2

RC549 0_0201_5%@

1 2

RC548 0_0201_5%@

PRIM_CORE_OPT_ DIS

SIO_SLP_S0#

3

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

ISH

6 of 20

GPP_D11/ISH_SPI_MISO/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI

GPP_H10/I2C5_SDA/ISH_I2C2_SDA

GPP_H11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#

+3.3V_RUN_R

I2C3_ANT_SCL_R

I2C3_ANT_SDA_R

+3.3V_ALW_PCH

5

UC9

@

1

MC74VHC1G32D FT2G_SC70-5~D

P

INB

4

O

2

INA

G

3

1 2

RC867 0_0201_5%@

1 2

RC660 0_0201_5%@

IR_CAM_DET#

CN22

DGPU_HOLD_R ST#

CR22

TBT_DET#

CM22

GPP_D12

CP22

ISH_I2C0_ACC_SDA

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_D13/ISH_UART0_RXD

GPP_D14/ISH_UART0_TXD

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1

GPP_A20/ISH_GP2
GPP_A21/ISH_GP3

GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

CK22

CH20

CH22

CJ22

CJ27

CJ29

CM24

CN23
CM23

CR24

CG12

CH12
CF12

CG14

BW35
BW34

CA37
CA36

CA35
CA34

BW37

CONN@

JASA1

4

4

G2

3

G1

3

2

2

1

1

CVILU_CI1804M1HR G-NH

ISH_I2C0_ACC_SCL

ISH_I2C1_ALS_SDA

ISH_I2C1_ALS_SCL

ISH_I2C2_SDA
ISH_I2C2_SCL

SML0B_SMBDATA
SML0B_SMBCLK

WWAN_FULL_PWR _EN

SIO_EXT_WAKE#

LCD_CBL_D ET#

PCH_HDD_E N

ISH_ACC1
ISH_ACC2

ISH_TABLE_MODE#

ISH_ALS_INT#
ISH_NB_MODE

ISH_LID_CL#_NB
ISH_LID_CL#_TAB

NB_MODE for NB13/Bandon
LID_CL#_NB for NB13/Bandon
LID_CL#_TAB for NB13/Bandon
ISH_ALS_INT# for Merion

6

5

Link CI1804M1HRG-NH done 0212

VR_LPM_R# <87>

2

IR_CAM_DET# <38>

1

@

T420

PAD~D

1

@

T415

PAD~D

1

@

T416

PAD~D

ISH_I2C1_ALS_SDA <38>

ISH_I2C1_ALS_SCL <38>

ISH_I2C2_SDA <52>

ISH_I2C2_SCL <52>

Reserve

WWAN_FULL_PWR _EN <52>

SIO_EXT_WAKE# <5 8>

LCD_CBL_DET# < 38>

1

@

T421

PAD~D

1

@

T395

PAD~D

1

@

T396

PAD~D

1

@

T397

PAD~D

ISH_ALS_INT# <38>

1

@

T375

PAD~D

1

@

T376

PAD~D

1

@

T377

PAD~D

TBT_DET#

RF Request

SML0B_SMBCL K

PRIM_CORE_OPT_ DIS

SIO_EXT_WAKE#

SML0B_SMBCLK

SML0B_SMBDATA

GPP_D12

LCD_CBL_D ET#

IR_CAM_DET#

ISH_I2C2_SDA

ISH_I2C2_SCL

CC1476@RF@ 33P _0402_50V8J

RC854 10K_04 02_5%@

RC748 10K_04 02_5%

RC829 1K_040 2_5%@

RC830 1K_040 2_5%@

RC847 100K_0 402_5%

1 2

RC749 100K_0 402_5%

RC345 100K_0 402_5%

1 2

RC363 1K_040 2_5%

1 2

RC362 1K_040 2_5%

+3.3V_ALW_PC H

A A

12

2.2K_0402_5 %
RC46

@

GPP_B22

HIGH
LOW(DEFAULT)

LPC
SPI

5

10K_0402_5%

12

DIMM Detect

HIGH
LOW

RC53

ONE_DIMM#

1 DIMM
2 DIMM

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

CPU(4/14)GSPI,I2C,UART,ISH

CPU(4/14)GSPI,I2C,UART,ISH

CPU(4/14)GSPI,I2C,UART,ISH

LA-G871P

LA-G871P

LA-G871P

1

9 109Tuesday, March 05, 201 9

9 109Tuesday, March 05, 201 9

9 109Tuesday, March 05, 201 9

1.0

1.0

1.0

5

4

3

2

1

For Merion AR (follow WHL 180416a port map)

CPU@

UC1H

D D

AR(PCIE5~8) --->

Card Reader RTS5242----->

M.2 2230(WLAN) --->

C C

M.2 3042(LTE/SATA Cache)--->

M2 2280 SSD (4 Lane) --->

B B

A A

PCIE_PRX_DTX_N5<42>
PCIE_PRX_DTX_P5<42>

PCIE_PTX_DRX_N5<42>
PCIE_PTX_DRX_P5<42>

PCIE_PRX_DTX_N6<42>
PCIE_PRX_DTX_P6<42>

PCIE_PTX_DRX_N6<42>
PCIE_PTX_DRX_P6<42>

PCIE_PRX_DTX_N7<42>
PCIE_PRX_DTX_P7<42>

PCIE_PTX_DRX_N7<42>
PCIE_PTX_DRX_P7<42>

PCIE_PRX_DTX_N8<42>
PCIE_PRX_DTX_P8<42>

PCIE_PTX_DRX_N8<42>
PCIE_PTX_DRX_P8<42>

PCIE_PRX_DTX_N9<70>
PCIE_PRX_DTX_P9<70>

PCIE_PTX_DRX_N9<70>
PCIE_PTX_DRX_P9<70>

PCIE_PRX_DTX_N10<52>
PCIE_PRX_DTX_P10<52>

PCIE_PTX_DRX_N10<52>
PCIE_PTX_DRX_P10<52>

PCIE_PRX_DTX_N11<54>
PCIE_PRX_DTX_P11<54>

PCIE_PTX_DRX_N11<54>
PCIE_PTX_DRX_P11<54>

PCIE_PRX_DTX_N12<52>

PCIE_PRX_DTX_P12<52>
PCIE_PTX_DRX_N12<52>

PCIE_PTX_DRX_P12<52>

PCIE_PRX_DTX_N13<68>
PCIE_PRX_DTX_P13<68>

PCIE_PTX_DRX_N13<68>
PCIE_PTX_DRX_P13<68>

PCIE_PRX_DTX_N14<68>
PCIE_PRX_DTX_P14<68>

PCIE_PTX_DRX_N14<68>
PCIE_PTX_DRX_P14<68>

PCIE_PRX_DTX_N15<68>
PCIE_PRX_DTX_P15<68>

PCIE_PTX_DRX_N15<68>
PCIE_PTX_DRX_P15<68>

PCIE_PRX_DTX_N16<68>
PCIE_PRX_DTX_P16<68>

PCIE_PTX_DRX_N16<68>
PCIE_PTX_DRX_P16<68>

2

1

RC50 100_0402_1%

Jony _12/21: Refer RVP keep it setting
570990_CF L_U_DD R4_RV P_CRB_ Sch_Re v0p8. pdf

PCIE_RCOMPN

PCIE_RCOMPP

BW9

PCIE5_RXN/USB31_5_RXN

BW8

PCIE5_RXP/USB31_5_RXP

BW4

PCIE5_TXN/USB31_5_TXN

BW3

PCIE5_TXP/USB31_5_TXP

BU6

PCIE6_RXN/USB31_6_RXN

BU5

PCIE6_RXP/USB31_6_RXP

BU4

PCIE6_TXN/USB31_6_TXN

BU3

PCIE6_TXP/USB31_6_TXP

BT7

PCIE7_RXN

BT6

PCIE7_RXP

BU2

PCIE7_TXN

BU1

PCIE7_TXP

BU9

PCIE8_RXN

BU8

PCIE8_RXP

BT4

PCIE8_TXN

BT3

PCIE8_TXP

BP5

PCIE9_RXN

BP6

PCIE9_RXP

BR2

PCIE9_TXN

BR1

PCIE9_TXP

BN6

PCIE10_RXN

BN5

PCIE10_RXP

BR4

PCIE10_TXN

BR3

PCIE10_TXP

BN10

PCIE11_RXN/SATA0_RXN

BN8

PCIE11_RXP/SATA0_RXP

BN4

PCIE11_TXN/SATA0_TXN

BN3

PCIE11_TXP/SATA0_TXP

BL6

PCIE12_RXN/SATA1A_RXN

BL5

PCIE12_RXP/SATA1A_RXP

BN2

PCIE12_TXN/SATA1A_TXN

BN1

PCIE12_TXP/SATA1A_TXP

BK6

PCIE13_RXN

BK5

PCIE13_RXP

BM4

PCIE13_TXN

BM3

PCIE13_TXP

BJ6

PCIE14_RXN

BJ5

PCIE14_RXP

BL2

PCIE14_TXN

BL1

PCIE14_TXP

BG5

PCIE15_RXN/SATA1B_RXN

BG6

PCIE15_RXP/SATA1B_RXP

BL4

PCIE15_TXN/SATA1B_TXN

BL3

PCIE15_TXP/SATA1B_TXP

BE5

PCIE16_RXN/SATA2_RXN

BE6

PCIE16_RXP/SATA2_RXP

BJ4

PCIE16_TXN/SATA2_TXN

BJ3

PCIE16_TXP/SATA2_TXP

CE6

PCIE_RCOMP_N

CE5

PCIE_RCOMP_P

CR28

GPP_H12/M2_SKT2_CFG_0

CP28

GPP_H13/M2_SKT2_CFG_1

CN28

GPP_H14/M2_SKT2_CFG_2

CM28

GPP_H15/M2_SKT2_CFG_3

WHL-U42_BGA1528

USB_OC3#

USB_OC0#

USB_OC1#

USB_OC2#

PCIE / USB3.1 / SATA

8 of 20

RC757 20K_0402_5%@

RC758 20K_0402_5%@

RC759 20K_0402_5%@

RC760 20K_0402_5%@

PCIE1_RXN/USB31_1_RXN

PCIE1_RXP/USB31_1_RXP

PCIE1_TXN/USB31_1_TXN

PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN/SSIC_1_R XN
PCIE2_RXP/USB31_2_RXP/SSIC_1_RX P

PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN

PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP

PCIE3_RXN/USB31_3_RXN

PCIE3_RXP/USB31_3_RXP

PCIE3_TXN/USB31_3_TXN

PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN

PCIE4_RXP/USB31_4_RXP

PCIE4_TXN/USB31_4_TXN

PCIE4_TXP/USB31_4_TXP

USB2.0

USB2_COMP

GPP_E9/USB2_OC0#/GP_BSSB_CLK

GPP_E10/USB2_OC1#/GP_BSSB_DI

1

1 2

1 2

1

USB2_VBUSSENSE

GPP_E11/USB2_OC2#

GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0

GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1

GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#/SPI1_CS1#

2

2

USB2_1N
USB2_1P

USB2_2N
USB2_2P

USB2_3N
USB2_3P

USB2_4N
USB2_4P

USB2_5N
USB2_5P

USB2_6N
USB2_6P

USB2_7N
USB2_7P

USB2_8N
USB2_8P

USB2_9N
USB2_9P

USB2_10N
USB2_10P

USB2_ID

RSVD_69

CB5
CB6

CA4
CA3

BY8
BY9

CA2
CA1

BY7
BY6

BY4
BY3

BW6
BW5

BW2
BW1

CE3
CE4

CE1
CE2

CG3
CG4

CD3
CD4

CG5
CG6

CC1
CC2

CG8
CG9

CB8
CB9

CH5
CH6

CC3
CC4

CC5
CE8

CC6

CK6

CK5
CK8

CK9

CP8

CR8
CM8

CN8
CM10

CP10

CN7

AR3

HDD_DET#

M3042_PCIE#_SATA

M2280_PCIE_SATA#

USBCOMP

USB2_ID

VBUSSENSE

USB_OC2#

Rese rve

USB_OC3#

Rese rve

HDD_DEVSLP

HDD_DET#

M3042_PCIE#_SATA
M2280_PCIE_SATA#

USB3_PRX_DTX_N2 <71>
USB3_PRX_DTX_P2 <71>

USB3_PTX_DRX_N2 <71>

USB3_PTX_DRX_P2 <71>

USB3_PRX_DTX_N3 <72>
USB3_PRX_DTX_P3 <72>

USB3_PTX_DRX_N3 <72>

USB3_PTX_DRX_P3 <72>

USB3_PRX_DTX_N4 <54>
USB3_PRX_DTX_P4 <54>

USB3_PTX_DRX_N4 <54>

USB3_PTX_DRX_P4 <54>

USB20_N1 <44>
USB20_P1 <44>

USB20_N2 <71>
USB20_P2 <71>

USB20_N3 <72>
USB20_P3 <72>

USB20_N6 <38>

USB20_P6 <38>

USB20_N7 <52>
USB20_P7 <52>

USB20_N8 <66>
USB20_P8 <66>

USB20_N9 <66>
USB20_P9 <66>

USB20_N10 <52>
USB20_P10 <52>

2

1

RC47 113_0402_1%

1 2

RC337 0_0201_5%@

RC49 1K_0402_5%

1

RC520 1K_0402_5%@

RC521 1K_0402_5%@

RC730 1K_0402_5%@

2

1

USB_OC0# <71>

USB_OC1# <72>

T417

@

PAD~D

M3042_DEVSLP <52>

M2280_DEVSLP <68>

M3042_PCIE#_SATA <58>

M2280_PCIE_SATA# <68>

1 2

2

1

2

1

-----> Ext USB3 Port 1 charge

-----> Ext USB3 Port 2

-----> M.2 3042(LTE)

-----> Type C (PD)

-----> Ext USB2 Port 1

-----> Ext USB2 Port 2

-----> UF CAM

-----> M2 3042(WWAN)

-----> USH

-----> Option to FPR in PB

-----> M.2 2230(BT)

M2280_PCIE_SATA#

HDD_DET#

M3042_PCIE#_SATA

USB_OC3#
USB_OC0#

USB_OC1#
USB_OC2#

RC764 10K_0402_5%

RC765 10K_0402_5%

RC766 10K_0402_5%

RC836

RC837 10K_0402_5%

RC839 10K_0402_5%

RC838 10K_0402_5%

+3.3V_RUN

12

12

2

1

+3.3V_ALW_PCH

10K_0402_5%

2

1

12

12

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet

Compal Electronics, Inc.

CPU(5/14)PCIE,USB,SATA

CPU(5/14)PCIE,USB,SATA

CPU(5/14)PCIE,USB,SATA

LA-G871P

LA-G871P

LA-G871P

10 109Tuesday, March 05, 2019

10 109Tuesday, March 05, 2019

10 109Tuesday, March 05, 2019

1

1.0

1.0

1.0

of

1

CC21

1 2

15P_0402_5 0V8J

4

3

YC1
24MHZ_12PF_ 8Y24000034

2

1

CC22

1 2

15P_0402_5 0V8J

CC23

1 2

15P_0402_5 0V8J

RC66
10M_0402_5 %

1 2

RC751 10K_0402_5%

1 2

RC48 1 K_0402_5%@

1 2

RC834 100K_0402_5%

RC72 10K _0402_5%

RC555 10K_0402 _5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

CPU(6/14)CLK,PM,RTC

CPU(6/14)CLK,PM,RTC

CPU(6/14)CLK,PM,RTC

Document Num ber Re v

Document Num ber Re v

Document Num ber Re v

12

YC2

32.768KHZ_1 2.5PF_9H03200 042

ESR MAX=50k ohm

PCH_RTCX2_R

15P_0402_5 0V8J

12

PCH_PRIM_EN <78,87>

1 2

1 2

+RTC_CELL_PCH

1 2

RC69 1M_0402_5%

RC73 10K _0402_5%

RC344 10K_0402 _5%@

RC68 10K _0402_5%@

1 2

1 2

1 2

LA-G871P

LA-G871P

LA-G871P

1

+3.3V_ALW_PCH

CC26

1 2

+3.3V_ALW_PCH

+3.3V_ALW_DSW

+3.3V_ALW

11 109Tuesday, Marc h 05, 2019

11 109Tuesday, Marc h 05, 2019

11 109Tuesday, Marc h 05, 2019

1.0

1.0

1.0

RC445 0_0201_5%@

REFCLK_CNV

4.7P_0402_50V8C

ESD@

1

CC1477

2

1 2

20K_0402_5 %

4.7K_0402_ 5%

2

XTAL24_IN_CPU

XTAL24_OUT_CPU

PCH_RTCX1

PCH_RTCX2

RC451

@

RC452

2

+3.3V_ALW_PCH

1 2

RC728 0_0402_5%E MI@

1 2

RC729 0_0402_5%E MI@

DC1

NDS3@

2 1

RB751S-40_ SOD523-2

DC2

NDS3@

21

RB751S-40_ SOD523-2

For deglitch,
refer to 575412_WHL_U_PDG rev0p8

0 = 3.3V supply is 3.3V +/- 5% (3.3V for bring up)
1 = 3.3V supply is 3.0V +/- 5%

1 2

INPUT3VSEL

1 2

Jony_1221: Refer RVP is 200 K ohm
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.p df

XTAL24_IN

XTAL24_OUT

REFCLK_CNV

SUSCLK

SIO_SLP_SUS #

VCCDSW _EN_Q

1 2

RC441 0_0201_5%DS3@

@NDS3@

1 2

RC442

8/21 can change to 10 K for merge to RP

DELL CONFIDENTIAL/PROPRIETARY

200K_0402_1%

RC59

1 2

1 2

RC532 0_0402_5%@

0_0201_5%

3.3V_CAM_ EN#

PCH_BATLOW #

AC_PRESE NT

INTRUDER#

VRALERT#

SIO_SLP_LAN #

Title

Title

Title

Size

Size

Size

Date : Sheet of

Date : Sheet of

Date : Sheet of

3

CLK_ITPXDP_N
CLK_ITPXDP_P

@

RC530

RC298

SUSCLK

XTAL24_IN_CPU

XTAL24_OUT_CPU

XCLK_BIASR EF

REFCLK_CNV

PCH_RTCX1
PCH_RTCX2

SRTCRST#

PCH_RTCRST#

@

RC60

RC738 0_0201_5%@

RC402 60.4_0402_ 1%

LC5 BL M15BD121SN1 D_2P~DESD@

LC5 place near CPU side

PCH_RTCRST# <58,79>

CMOS1 DVT1.0 footprint change to SHORTPADS-NPM

CMOS1 must take care short & touch risk on layout placement

1 2

0_0201_5%

1 2

RC439

RC440RE5 36RC21 5RC441RC 442

V V V

X

V V V

X X

0_0201_5%

1 2

0_0201_5%@

1 2

12

CC93 0.1 U 16V K X5R 0 201@

1 2

1 2

ESD Request
0419 ESD YuHeng: follow Intel recommendation

1 2

RC56 20K_0402_5 %

1 2

CC24 1U _0201_6.3V6M

1 2

RC57 20K_0402_5 %

1 2

CC25 1U _0201_6.3V6M

1

2

2

PLTRST_TPM# <66>

1

CMOS1 SHORT PADS~D@

X

X

CLK_ITPXDP_N_R <79>

CLK_ITPXDP_P_R <79>

SUSCLK <52,68>

X

REFCLK_CNV_L <52>

+RTC_CELL_PCH

VCCDSW_EN_GPIO<18>

VCCDSW_EN<58>

ALW_PW RGD_3V_5V<6 3,85>

PCH_PLTRST#_AND

12

RC65

@

100K_0402_ 5%

4

CPU@

UC1J

AW2

CLKOUT_PCIE_N_0

AY3

CLKOUT_PCIE_P_0

CF32

GPP_B5/SRCCLKREQ0#

BC1

CLKOUT_PCIE_N_1

BC2

CLKOUT_PCIE_P_1

CE32

GPP_B6/SRCCLKREQ1#

BD3

CLKOUT_PCIE_N_2

BC3

CLKOUT_PCIE_P_2

CF30

GPP_B7/SRCCLKREQ2#

BH3

CLKOUT_PCIE_N_3

BH4

CLKOUT_PCIE_P_3

CE31

GPP_B8/SRCCLKREQ3#

BA1

CLKOUT_PCIE_N_4

BA2

CLKOUT_PCIE_P_4

CE30

GPP_B9/SRCCLKREQ4#

BE1

CLKOUT_PCIE_N_5

BE2

CLKOUT_PCIE_P_5

CF31

GPP_B10/SRCCLKREQ5#

WHL-U42 _BGA1528

PCH_PLTRST#_AND <38 ,42,52,68,70>

CLOCK SINGNALS

10 of 20

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL_IN

XTAL_OUT

XCLK_BIASREF

CLKIN_XTAL

RTCX1
RTCX2

SRTCRST#

RTCRST#

AU1

AU2

BT32

CK3
CK2

CJ1
CM3

BN31
BN32

BR37
BR34

PCH_PLTRST#

PCH_PLTRST#_A ND

Support DS3

5

CLK_PCIE_N0<52>

LAN_W AKE#

12

PCH_PCIE_W AKE#

12

VCCST_PW RGD

12

PCH_PW ROK

12

CLK_PCIE_P0<52>

CLKREQ_PCIE#0<52>

+3.3V_RUN

CLK_PCIE_N1<52>

CLK_PCIE_P1<52>

CLKREQ_PCIE#1<52>

+3.3V_RUN

CLK_PCIE_N2<68>
CLK_PCIE_P2<68>

CLKREQ_PCIE#2<68>

+3.3V_RUN

+3.3V_RUN

CLK_PCIE_N4<70>
CLK_PCIE_P4<70>

CLKREQ_PCIE#4<70>

+3.3V_RUN

CLK_PCIE_N5<42>
CLK_PCIE_P5<42>

CLKREQ_PCIE#5<42>

+3.3V_RUN

M.2 3042 WWAN--->

D D

M.2 2230 WLAN--->

M.2 2280 SSD--->

Card Reader --->

AR--->

+3.3V_ALW_DSW

RC323 10K_0402_5%

C C

RC67 1K _0402_5%

+1.0V_VCCST

RC71 1K _0402_5%

RC536 10K_0 402_5%@

1 2

RC297 0_0 201_5%@RF@

12

RC189 10K _0402_5%

1 2

RC526 0_0 201_5%@RF@

12

RC522 10K _0402_5%

1 2

RC727 0_0 201_5%@RF@

12

RC525 10K _0402_5%

12

RC523 10K _0402_5%

1 2

RC528 0_0 201_5%@RF@

12

RC51 10K_0402_5 %

1 2

RC529 0_0 201_5%@RF@

12

RC190 10K _0402_5%

PCH_PLTRST#

MC74VHC1G0 8DFT2G_SC70-5

UC7

CLKREQ_PCIE #0_R

CLKREQ_PCIE #1_R

CLKREQ_PCIE #2_R

CLKREQ_PCIE #3_R

CLKREQ_PCIE #4_R

CLKREQ_PCIE #5_R

+3.3V_ALW_PCH

5

1

P

B

2

A

G

3

4

O

No Support DS3

'V' mean POP, 'X' mean DE-POP

PCH GLITCH ISSUE MIT IGATION(PDG p.130)

B B

+3.3V_ALW_PCH

A A

H_CPUPW RGD

100P_0402_50V8J

12

CC300ESD@

ESD Request:place near CPU side

SIO_SLP_SUS #

12

RC229100K_0402_ 5%

12

CC14650.33U_040 2_10V6K @

SIO_SLP_S4#

12

RC232100K_0402_ 5%

12

CC14670.33U_040 2_10V6K @

SIO_SLP_S3#

12

RC231100K_0402_ 5%

12

CC14680.33U_040 2_10V6K @

SIO_SLP_A#

12

RC233100K_0402_ 5%

12

CC14690.33U_040 2_10V6K @

SIO_SLP_W LAN#

12

RC234100K_0402_ 5%

12

CC14700.33U_040 2_10V6K @

SIO_SLP_LAN #

12

RC761100K_0402_ 5%

12

CC14710.33U_040 2_10V6K @

SIO_SLP_S5#

12

RC230100K_0402_ 5% @

PCH_PLTRST#

12

RC237100K_0402_ 5% @

1211 change
Follow NB14 UU AR, Intel CNVi recommendation RC237 pop,
But measure cold reset and Global reset sequence timing fail, So depop RC237

SIO_SLP_S0#

12

RC763100K_0402_ 5%

VCCST_PW RGD

100P_0402_50V8J

12

CC301ESD@

5

S4 power side PD need @,need check

RC215

POP

NO Support Deep sleep

DE-POP

Support Deep sleep

PCH_DPW ROK

1 2

@NDS3@

RC215

100K_0402_1%

0.01UF_0402_25V7K

12

1

@

CC266

2

0_0201_5%

RC220

@

T355

PCH_RSMRS T#_AND

10K_0402_5%

12

PAD~D

RC75

VCCST_PWRGD<59,79>

PCH_RSMRST#_AND<63,79>

1

RC77 1K _0402_5%@

RC78 62 _0402_5%

ME_SUS_PWR_ACK is for LPC use only

SUSACK# is for LPC use only

PCH_PLTRST#_A ND

.047U_0402_16V7K

12

CC196ESD@

For E SD solution

4

SYS_RESET#<79>

1 2

1 2

Follow PDG P.251

PCH_PCIE_WAKE#<42,58,59>

LAN_WAKE#<58>

@

T422

PCH_DPWROK<58>

PAD~D

CPU@

PCH_PLTRST#

SYS_RESET#

PCH_RSMRS T#_AND

H_CPUPW RGDH_ CPUPWRG D_R

VCCST_PW RGD_CPU

SYS_PW ROK<58,79>

PCH_PWROK<88>

T380

T381

@

PAD~D

@

PAD~D

1

1

LAN_W AKE#
PM_LANPH Y_ENABLE

1

XDP_DBRESET#<79>

GPP_A13
GPP_A15

UC1K

BJ35

GPP_B13/PLTRST#

CN10

SYS_RESET#

BR36

RSMRST#

AR2

PROCPWRGD

BJ2

VCCST_PWRGOOD

CR10

SYS_PWROK

BP31

PCH_PWROK

BP30

DSW_PWROK

BV34

GPP_A13/SUSWARN#/SUSPWRDACK

BY32

GPP_A15/SUSACK#

BU30

WAKE#

BU32

GPD2/LAN_WAKE#

BU34

GPD11/LANPHYPC

WHL-U42 _BGA1528

+3.3V_ALW_PCH

RC248

@

2.2K_0402_ 5%

1 2

1

CC78

0.1U_0402_2 5V6

2

Follow ICL_2/23 CKT

RC243 0_0201_5%@

1 2

SYSTEM POWER MANAGE MENT

11 of 20

SYS_RESET#

3

GPP_B12/SLP_S0#

GPD4/SLP_S3#

GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SPL_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

INPUT3VSEL

ESD Request:place near CPU side ESD Request:place near CPU side

SIO_SLP_S0#

BJ37
BU36

BU27

SIO_SLP_S5#

BT29

BU29

SIO_SLP_LAN #

BT31

BT30

SIO_SLP_A#

BU37

BU28

BU35

PCH_BATLOW #

BV36

BR35

INTRUDER#

3.3V_CAM_ EN#

CC37
CC36

VRALERT#

BT27

INPUT3VSEL

SYS_RESET#

0.1U_0402_25V6

@ESD@

12

CC302

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

SIO_SLP_S0# <9,17,66,79,87>
SIO_SLP_S3# <17,42,59,79>

SIO_SLP_S4# <17,79,86,87>

SIO_SLP_S5# <79>

SIO_SLP_SUS# <58>

SIO_SLP_WLAN# <78>

SIO_SLP_A# <79>

SIO_PWRBTN# <58,79>

AC_PRESENT <58>

3.3V_CAM_EN# <38>

ESD Request
0419 ESD YuHeng: follow Intel recommendation

2

MACO_EN

TBT_CIO_PLUG_EVENT#

CPU_GC6_FB_EN

CONTACTLESS_DET#

HOST_SD_WP#
AUD_PWR_EN

SMART_SPK_DET0#

ISH_P_SENSOR_INT#

2.7MM_CAM_DET#

SD_RCOMP

RC116 200_0402_1%

CAM_MIC_CBL_DET# <38>

1

@

T452

PAD~D

TBT_CIO_PLUG_EVENT# <42>

1

1 2

T383

@

PAD~D

CONTACTLESS_DET# <66>

HOST_SD_WP# <70>

AUD_PWR_EN <56>

SMART_SPK_DET0# <56>

ISH_P_SENSOR_INT# <3 8>

2.7MM_CAM_DET# <38>

AUDIO

3

CH36
CL35

CL36
CM35

CN35
CH35

CK36
CK34

BW36
BY31

CK33
CM34

7 of 20

SDIO / SDXC

GPP_A17/SD_VDD1_PWR _EN#/ISH_GP7

GPP_G0/SD_CMD

GPP_G1/SD_DATA0

GPP_G2/SD_DATA1
GPP_G3/SD_DATA2

GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_1P8_RCOMP
SD_3P3_RCOMP

HDA_SYNC

HDA_BIT_CLK

HDA_SDOUT

HDA_SDIN0<56>

HDA_RST#

CNV_RF_RESET#

CLKREQ_CNV#

DMIC_CLK0_CPU

DMIC_DATA0_CPU

KB_DET#
DGPU_PWROK

SPKR

4

CNVI_EN#

CPU@

UC1G

BN34

HDA_SYNC/I2S0_SFRM

BN37

HDA_BCLK/I2S0_SCLK

BN36

HDA_SDO/I2S0_TXD

BN35

HDA_SDI0/I2S0_RXD

BL36

HDA_SDI1/I2S1_RXD/SNDW 1_DATA

BL35

HDA_RST#/I2S1_SCLK/SNDW 1_CLK

CK23

GPP_D23/I2S_MCLK

BL37

I2S1_SFRM/SNDW2_CLK

BL34

I2S1_TXD/SNDW2_DATA

CJ32

GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CN V_RF_RESET#

CH32

GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

CH29

GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_C LKREQ

CH30

GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP24

GPP_D19/DMIC_CLK0/SNDW 4_CLK

CN24

GPP_D20/DMIC_DATA0/SNDW 4_DATA

CK25

GPP_D17/DMIC_CLK1/SNDW 3_CLK

CJ25

GPP_D18/DMIC_DATA1/SNDW 3_DATA

CF35

GPP_B14/SPKR

WHL-U42_BGA1528

5

1 2

D D

C C

HDA_SYNC_R<56>

HDA_BIT_CLK_R<56>

HDA_SDOUT_R<56>

ME_FWP_PCH<79>

HDA_RST#_R<56>

CC27

RF@

47P_0402_50V8J

Close to RC93

+3.3V_ALW_PCH

RC725 10K_0402_5%

HDA_BIT_CLK_R

1

2

2

RC92 33_0402_5%

1

RC93 33_0402_5%EMI@

1

RC561 33_0402_5%

1 2

RC562 1K_0402_5%

1

RC560 33_0402_5%

CAM_MIC_CBL_DET#

1

2

2

2

1218
Follow NB14 UU AR
Add 'CNVI_EN#' net connection to GPP_H3

CNV_RF_RESET#<52>

CLKREQ_CNV#<52>

CNVI_EN#<52>

T404 PAD~D@

T405 PAD~D@

T419 PAD~D@

1

1

KB_DET#<63>

1

SPKR<56>

1

+3.3V_ALW_PCH

2

1

ENABLE
DISAB LE

HDA_SDOUT

1

DISABLE

ENABLE

SPKR

+3.3V_RUN

CONTACTLESS_DET#

2

1 2

1

1

12

AUD_PWR_EN

12

HOST_SD_WP#

12

1

CLKREQ_CNV#

CNV_RF_RESET#

2

CNVI_EN#

2

KB_DET#

B B

A A

RC278 10K_0402_5%

RC279 10K_0402_5%

RC292 10K_0402_5%

+3.3V_ALW_PCH

RC288 10K_0402_5%

1206 change

Follow NB14 UU AR
'CNV_RF_RESET#' change to 75K PD from 71.5K
'CLKREQ_CNV#' change to 71.5K PD from 75K

RC752 71.5K_04 02_1%

RC640 75K_0402_5%

RC868 75K_0402_5%

1218
Follow NB14 UU AR
Add 75K PD for 'CNVI_EN#'

RC183 2.2K_0402_5%@

TOP SWAP STRAP

HIGH
LOW(DEFAULT)

Internal 20k PD

+3.3V_ALW_PCH

2

RC187 4.7K_0402_5%@

Flash Descriptor Security override

HIGH
LOW(DEFAULT)

RF Request. Place near CPU side (Intel MOW)

1

2

HDA_RST#

CC331

2.2P_0402_50V8C

@RF@

HDA_SDIN0

1

2

CC332

@RF@

2.2P_0402_50V8C

1

2

HDA_SDOUT

CC333

2.2P_0402_50V8C

@RF@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU(7/14)MISC,JTAG,HDA,SDIO

CPU(7/14)MISC,JTAG,HDA,SDIO

CPU(7/14)MISC,JTAG,HDA,SDIO

LA-G871P

LA-G871P

LA-G871P

12 109Tuesday, March 05, 2019

12 109Tuesday, March 05, 2019

12 109Tuesday, March 05, 2019

1

1.0

1.0

1.0

5

2

1

RC120 1K_0201_1%@

CFG0

1

RC411 1K_0201_1%@

4

2

CFG7

3

2

1

EAR-STALL/NOT STALL RESET
SEQUENCE AFTER PCU PLL IS LOCKED

CFG0

D D

RC405 1K_0201_1%@

PCH/ PCH LESS MODE SELECTION

CFG1

RC406 1K_0201_1%@

PCI EXPRESS STATIC LANE REVERSAL
FOR ALL PEG PORTS

CFG2

C C

RC407 1K_0201_1%@

PCH/ PCH LESS MODE SELECTION

CFG3

RC723 1K_0201_1%

0: AN EXTERNAL DISPLAY PORT DEVICE PORT IS CONNECTED TO THE EMBEDDED PORT
1: NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

DISPLAY PORT PRESENCE STRAP

CFG4

B B

RC409 1K_0201_1%@

RC410 1K_0201_1%@

PCIE PORT BIFURCATION STRAPS

11: DEVICE1 FUNTION 1, DEVICE 1 FUNCTION2 DISABLED
10: DEVICE1 FUNTION 1, ENABLED DEVICE 1 FUNCTION2 DISABLED

1:(DEFAULT)NORMAL OPERATION; NO STALL
0:STALL

2

1

1

1 2

1 2

1

1

CFG1

1: (DEFAULT) NORMAL OPERATION
0: PCH-LESS MODE

2

CFG2

1: (DEFAULT)NORMAL OPERATION

0: LANE REVERSAL

CFG3

1:(DEFAULT) NORMAL OPERATION
0: PCH-LESS MODE

CFG4

0: ENABLED
1: DISABLED;

2

CFG5

2

CFG6

PEG DEFER TRAINING

CFG7

RC412 1K_0201_1%@

ALLOW THE USE OF CFG ON LOCKED UNITS

CFG8

RC413 1K_0201_1%@

NO SVID PROTOCOL CAPABLE VR CONNECTED

CFG9

RC414 1K_0201_1%@

SAFE MODE BOOT

CFG10

RC415 1K_0201_1%@

DMI AC COUPLING - JUST A PLA CE HOLDER.
NOT APPLICABLE FOR ULX-ULT

CFG11

RC416 1K_0201_1%@

PM SYNC LEGACY

CFG12

RC417 1K_0201_1%@

1: (DEFAULT) PEG TRAIN IMMEDIATELY

FOLLOWING XXRESETB DE ASSERTION
0: PEG WAIT FOR BIOS FOR TRAINING

2

1

1: DISABLED(DEFAULT); IN THIS CASE, CFG WILL BE
DISABLED IN LOCKED UNITS AND ENABLED IN UN-LOCKED UNITS AND

0: EENABLED; CFG WILL BE
AVAILABLE REGARDLESS OF THE LOCKING OF THE UNIT

1 2

1

1 2

1:(DEFULT)
DMI WILL BE CONFIGURED AS HALF S WING DC COUPLED
0:DMI WILL BE CONFIGURED AS FULL SWING A C COUPLED

1 2

1

CFG8

CFG9

1:VRS SUPPORTING SVID PROTOCOL ARE PRESENT
0: NO VR SUPPORTING SVID

2

CFG10

1: POWER FEATURES ACTIVATED DURING RESET
0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED

CFG11

CFG12

1: (DEFAULT) PMSYNC 2.0

0 : LEGACY

2

CFG13

Refer RVP CFG_RCOMP Keep 49.9 ohm to GND
570990_CF L_U_DD R4_RV P_CRB_ Sch_Re v0p8. pdf

+1.0V_PRIM_XDP

Refer RVP CFG_RCOMP Keep 1.5K to 1.0 VA
570990_CF L_U_DD R4_RV P_CRB_ Sch_Re v0p8. pdf

CFG[0..19]<79>

RC624 49.9_0201_1%

RC125 1.5K_0201_5%

ITP_PMODE<79>

need check

12

12

CFG0

CFG1

CFG2

CFG3
CFG4

CFG5
CFG6

CFG7
CFG8

CFG9
CFG10

CFG11
CFG12

CFG13
CFG14

CFG15

CFG16
CFG18

CFG17

CFG19

CFG_RCOMP

ITP_PMODE

CPU@

UC1Q

T4

CFG_0

R4

CFG_1

T3

CFG_2

R3

CFG_3

J4

CFG_4

M4

CFG_5

J3

CFG_6

M3

CFG_7

R2

CFG_8

N2

CFG_9

R1

CFG_10

N1

CFG_11

J2

CFG_12

L2

CFG_13

J1

CFG_14

L1

CFG_15

L3

CFG_16

N3

CFG_18

L4

CFG_17

N4

CFG_19

AB5

CFG_RCOMP

W4

ITP_PMODE

CG2

RSVD25

CG1

RSVD24

H4

RSVD34

H3

RSVD33

BV24

RSVD22

BV25

RSVD23

G3

RSVD66

G4

RSVD67

BK36

RSVD17

BK35

RSVD16

W3

RSVD35

AM4

RSVD7

AM3

RSVD6

A35

RSVD1

D34

RSVD30

G2

RSVD32

G1

RSVD31

WHL-U42_BGA1528

RESERVED SIGNALS

20 of 20

RSVD_TP5
RSVD_TP4

IST_TRIG

RSVD_TP3

RSVD15
RSVD14

TP_1
TP_2

RSVD21
RSVD20

RSVD18
RSVD19

RSVD29

RSVD26

RSVD27

VSS_434

RSVD12
RSVD13

RSVD8
RSVD9

RSVD11
RSVD10

RSVD72
RSVD73

RSVD74
RSVD75

TP_4
TP_3

RSVD68

RSVD_TP1

RSVD_TP2

RSVD28

RSVD36
RSVD37

SKTOCC#

F37
F34

CP36
CN36

BJ36
BJ34

BK34
BR18

BT9
BT8

BP8
BP9

CR4

CP3

CR3

BP36

AT3
AU3

AN1
AN2

AN4
AN3

AL2
AL1

AL4
AL3

BP34
BP35

C34

A34

B35

CR35

AH26
AJ27

E1

RC848 0_0201_5%@

RC420

@

RC563 0_0201_5%

@

RC564 0_0201_5%

@

SKTOCC#

RC565 0_0201_5%

@

1206 change

Follow NB14 UU AR
Add T423 for CNVi Intel request

1

1

1

1

1

1

1

1

1

2

1

1

1

PAD~D

PAD~D

PAD~D

PAD~D

PAD~D

PAD~D

PAD~D

12

PAD~D

PAD~D

PAD~D

PAD~D

PAD~D

1 2

1 2

1 2

@

T16

@

T17

@

T18

@

T19

@

T20

@

T21

@

T360

@

T361

@

T363

0_0201_5%

1

@

T364

@

T365

@

T423

+1.0V_VCCSTG

1

2

RC436

@

100_0201_1%

CFG5,6

PCH/ PCH LESS MODE SELECTION

01: DEVICE1 FUNTION 1, DISABLED, DEVICE 1 FUNCTION2 ENABLED
00: DEVICE 1 FUNCTION 1 ENABLED, DEVICE 1 FUNCTION 2 ENABLED

PMSYNC AYNC MODE- PM SYNC

1: (DEFAULT)SYNCHCRONOUS (1 24 MHZ CYCLE PER BIT)

CFG13

0: ASYNC - 4-24MHZ CYCLES PER BIT

2

1

A A

RC418 1K_0201_1%@

CFG14

RC419 1K_0201_1%@

1 2

CFG15

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

CFG14 CFG15

5

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

CPU(8/14)CFG,RSVD

CPU(8/14)CFG,RSVD

CPU(8/14)CFG,RSVD

LA-G871P

LA-G871P

LA-G871P

13 109Tuesday, March 05, 2019

13 109Tuesday, March 05, 2019

13 109Tuesday, March 05, 2019

1

1.0

1.0

1.0

of

2

2

+1.0V_VCC STG

TOUCH_SCREE N_PD#

Merion Limit height
QC4 change to SB000014O00 H=0.6mm(MAX)

TOUCH_SCREEN_PD# don't move to RPC,

TOUCH_SCREE N_PD#

TOUCH_SCREE N_PD

1219 Change

QC4

@

2

5

1 2

RC566 0 _0201_5%@

1

S1

G1

D1

S2

G2

D2

PJX138K _SOT563-6

3

TOUCH_SCREE N_PD

6

4

Reserve for Panel side TS PH voltage problem

MEM_INTERLE AVED

PROCHOT#

TOUCH_SCREEN_DET#<38>

TOUCHPAD_INTR#<58,63>

4

2

1

RC84 499 _0402_1%

2

1

RC559 0_0201_5%@

XDP_OBS0_R<79 >
XDP_OBS1_R<79 >

@

T366

PAD~D

@

T367

PAD~D

1

1

RC106

2

2

49.9_0201_1%

H_CATERR#

PROCHOT#_R

H_THERMTRIP#_ R

XDP_OBS 2_R

1

XDP_OBS 3_R

1

MEM_INTERLE AVED

TOUCH_SCREE N_PD#

TOUCHPAD_INTR#

CPU_POPI RCOMP

PCH_POPI RCOMP

EDRAM_OP IO_RCOMP

EOPIO_RC OMP

12

1

RC107

RC109

RC108

49.9_0201_1%

@

@

2

49.9_0201_1%

49.9_0201_1%

need check

RC108,RC109

This is applicable only for CFL U43e. These pins are
RSVD in WHL and hence can be left unconnected

CB34
CC35

BP27

BW25

AA4
AR1

Y4

BJ1

U1
U2

U3
U4

CE9

CN3

L5
N5

CPU@

UC1D

CATERR#
PECI

PROCHOT#
THRMTRIP#

BPM#_0
BPM#_1

BPM#_2
BPM#_3

GPP_E3/ CPU_GP0
GPP_E7/ CPU_GP1

GPP_B3/ CPU_GP2
GPP_B4/ CPU_GP3

PROC_POP IRCOMP
PCH_OPIRC OMP

RSVD70
RSVD71

WHL-U42 _BGA1528

5

+1.0V_VCC ST

2

H_THERMTRIP#_ R

H_CATERR#

PROCHOT#

TOUCH_SCREE N_PD#

TOUCHPAD_INTR#

PECI_EC<58>

PROCHOT#<58, 84,88>

H_THERMTRIP#<23,24 ,59>

RC218 1K_0201 _1%

1 2

2

1

RC219 49.9_020 1_1%@

+1.0V_VCC STG

RC558 1K_0201 _1%

1

D D

+3.3V_RUN

2

1

RC82 10K _0201_5%@

2

1

RC567 10K_020 1_5%

C C

CPU MISC

3

PROC_TCK

JTAG

PROC_TDO
PROC_TMS

PROC_TRST#

PCH_TRST#

PCH_JTAGX

PROC_PRE Q#

PROC_PRDY#

4 of 20

PCH_JTAG_TDO PCH_JTAG_TDI

@ESD@

0.1U_0201_25V6K

1

CC303

2

T6
U6

PROC_TDI

Y5
T5

AB6

W6

PCH_TCK

U5

PCH_TDI

W5

PCH_TDO

P5

PCH_TMS

Y6

P6

W2

W1

ESD request,Place near CPU side.

CPU_XDP_TRST#

XDP_JTAGX

@ESD@

0.1U_0201_25V6K

1

CC304

2

CPU_XDP_TCLK <79>
CPU_XDP_TDI <79>

CPU_XDP_TDO <79>
CPU_XDP_TMS <79>

RC86 51_0201_5%@

PCH_JTAG_TCK <79>
PCH_JTAG_TDI <79>

PCH_JTAG_TDO <79>
PCH_JTAG_TMS <79>

CPU_XDP_TRST# <79 >
XDP_JTAGX <79>

1

RC87 1K_ 0201_5%@

CPU_XDP_PREQ# <79>
CPU_XDP_PRDY# <79>

XDP_JTAGX

@ESD@

0.1U_0201_25V6K

1

CC305

2

1

2

1

TOUCH_SCREEN_PD#_R

+3.3V_RUN

12

RC104

@

10K_020 1_5%

TOUCH_SCREEN_PD#_R <38>

+3.3V_ALW_PCH

@

RC843
10K_020 1_5%

1 2

12

RC844

10K_020 1_5%

DIMM TYPE

HIGH Interlea ve

Non-In terleave

LOW

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DIS CLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU(9/14)XDP

CPU(9/14)XDP

CPU(9/14)XDP

Document Number Re v

Document Number Re v

Document Number Re v

LA-G871P

LA-G871P

LA-G871P

1

14 109Tuesday, March 05, 2019

14 109Tuesday, March 05, 2019

14 109Tuesday, March 05, 2019

1.0

1.0

1.0

+VCC_CORE

2

2

1

1

2

1

2

1

Close C PU

RC150

100_0402_1%

RC151

100_0402_1%

1V@0 .0 5A

VCC_SENSE_IA <88>
VSS_SENSE_IA <88>

+1.0V_VCCSTG

2

VCCCORE35

VCCCORE36
VCCCORE37

VCCCORE38
VCCCORE44

VCCCORE45
VCCCORE48

VCCCORE49
VCCCORE50

VCCCORE46
VCCCORE47

VCCCORE51
VCCCORE52

VCCCORE56
VCCCORE57

VCCCORE58
VCCCORE59

VCCCORE53
VCCCORE54

VCCCORE55
VCCCORE63

VCCCORE64
VCCCORE60

VCCCORE61
VCCCORE62

VCCCORE69
VCCCORE65

VCCCORE66
VCCCORE67

VCCCORE68
VCCCORE70

VCCCORE73
VCCCORE71

VCCCORE72
VCCCORE74

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

RSVD5

VCCSTG1

AW24

AW25
AW26

AW27
AY24

AY26
BA5

BA7
BA8

BA25
BA27

BB2
BB26

BC5
BC6

BC7
BC9

BC10
BC26

BC27
BD5

BD8
BD10

BD25
BD27

BE9
BE24

BE25
BE26

BE27
BF2

BF9
BF24

BF26
BG27

AN6
AN5

AA3

AA1

AA2

Y3

BG3

+VCC_CORE

VCCSENSE_R
VSSSENSE_R

H_CPU_SVIDALRT#

VIDSCLK_R

VIDSOUT_R

+1.0V_VCCSTG_R

RC430

@

0_0201_5%

1

1

0_0201_5%

RC429

@

2

RC153 0_0603_5%@

+VCC_CORE_G0
+VCC_CORE_G1

+VCC_CORE_G2
+VCC_CORE_G3

3

+VCC_CORE

CPU@

UC1L

AN9

VCCCORE5

AN10

VCCCORE1

AN24

VCCCORE2

AN26

VCCCORE3

AN27

VCCCORE4

AP2

VCCCORE6

AP9

VCCCORE9

AP24

VCCCORE7

AP26

VCCCORE8

AR5

VCCCORE13

AR6

VCCCORE14

AR7

VCCCORE15

AR8

VCCCORE16

AR10

VCCCORE10

AR25

VCCCORE11

AR27

VCCCORE12

AT9

VCCCORE19

AT24

VCCCORE17

AT26

VCCCORE18

AU5

VCCCORE24

AU6

VCCCORE25

AU7

VCCCORE26

AU8

VCCCORE27

AU9

VCCCORE28

AU24

VCCCORE20

AU25

VCCCORE21

AU26

VCCCORE22

AU27

VCCCORE23

AV2

VCCCORE30

AV5

VCCCORE32

AV7

VCCCORE33

AV10

VCCCORE29

AV27

VCCCORE31

AW5

VCCCORE39

AW6

VCCCORE40

AW7

VCCCORE41

AW8

VCCCORE42

AW9

VCCCORE43

AW10

VCCCORE34

BB9

RSVD3

BC24

RSVD4

AY9

RSVD1

BB24

RSVD2

WHL-U42_BGA1528

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e

(w/ on package cache)

CPU POWER 1 OF 4

12 of 20

5

PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

4

+VCC_CORE: 0.55~1.5V, 29A

D D

+VCC_EDRAM: 1V, 2.5A

+V1.8S_EDRAM: 1.8V, 50mA - REMOVE
+VCC_EOPIO: 0.8~1V, 2A - REMOVE

CPU@

UC1O

K12
K14

K15
K17

K18
K20

L25

M24

M26
P24

P26
R24

R25
R26

W25

V24

C C

Y25
Y24

RESERVED SIGNALS

RSVD48
RSVD49

RSVD50
RSVD51

RSVD52
RSVD53

RSVD54
RSVD55

RSVD56
RSVD57

RSVD58
RSVD59

RSVD60
RSVD61

RSVD62
RSVD63

RSVD64
RSVD65

WHL-U42_BGA1528

15 of 20

RSVD38
RSVD39

RSVD40
RSVD41

RSVD42
RSVD43

RSVD44
RSVD45

RSVD46
RSVD47

AA24
AA26

AB25
AC24

AC25
AC26

AD24
AD26

V25
T25

VCCEOPIO_SENSE
VSSEOPIO_SENSE

1

@

T368

PAD~D

1

@

T369

PAD~D

PAD~D

PAD~D

PAD~D

PAD~D

1

1

1

1

T371

T372

T373

T374

@

@

@

@

SVID ALERT

B B

VIDALERT_N<88>

SVID DATA

VIDSOUT<88>

SVID CLK

A A

VIDSCLK<88>

+1.0V_VCCST

12

+1.0V_VCCST

12

+1.0V_VCCST

12

56_0402_1%

RC154

100_0402_1%

RC156

43_0402_5%

@

RC158

CAD Note: Place the PU resistors close to CPU
RC154 close to CPU 1000 - 1500mils

2

H_CPU_SVIDALRT#

1

RC155220_0402_5%

CAD Note: Place the PU resistors close to CPU
RC156close to CPU 1000 - 1500mils

VIDSOUT_R

12

RC1570_0201_5% @

CAD Note: Place the PU resistors close to CPU
RC158close to CPU 1000 - 1500mils

12

VIDSCLK_R

RC1590_0201_5% @

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU(10/14)PWR-VCC CORE

CPU(10/14)PWR-VCC CORE

CPU(10/14)PWR-VCC CORE

LA-G871P

LA-G871P

LA-G871P

15 109Tuesday, March 05, 2019

15 109Tuesday, March 05, 2019

15 109Tuesday, March 05, 2019

1

1.0

1.0

1.0

5

4

3

2

1

THE BALLOUT ONLY FOR WHL ES2 CPU

D D

+VCCGT: 0.55~1.5V, 54A
+VCCGTX : 0.55~1.5V, 7A

+VCC_GT+VCC_CORE

CPU@

UC1M

A5
A6

A8

A11

A12
A14

A15
A17

A18
A20

AA9
AB2

AB8
AB9

AB10

AC8

AD9
AE8

C C

B B

AE10

AF10

AJ10

AL10

AM8

AE9

AF2
AF8

AG8

AG9
AH9

AJ8

AK2
AK9

AL8
AL9

Y10

B11

B14
B17

B20

C11
C12

C14
C15

C17
C18

C20

D11

D12
D14

V2

Y8

B3

B4
B6

B8

C2

C3
C6

C7
C8

D4

D7

CPU POWER 2 OF 4

VCCGT8
VCCGT9

VCCGT10
VCCGT1

VCCGT2
VCCGT3

VCCGT4
VCCGT5

VCCGT6
VCCGT7

ES1/ES2

VCCGT11/VCCCORE75
VCCGT13/VCCCORE76

VCCGT14/VCCCORE77
VCCGT15/VCCCORE78

VCCGT12/VCCCORE79
VCCGT16/VCCCORE80

VCCGT17/VCCCORE81
VCCGT19/VCCCORE82

VCCGT20/VCCCORE83
VCCGT18/VCCCORE84

VCCGT22/VCCCORE85
VCCGT23/VCCCORE86

VCCGT21/VCCCORE87
VCCGT24/VCCCORE88

VCCGT25/VCCCORE89
VCCGT26/VCCCORE90

VCCGT28/VCCCORE91
VCCGT27/VCCCORE92

VCCGT29//VCCCORE93
VCCGT30/VCCCORE94

VCCGT32/VCCCORE95
VCCGT33/VCCCORE96

VCCGT31/VCCCORE97
VCCGT34/VCCCORE98

VCCGT115/VCCCORE99
VCCGT119/VCCCORE100

VCCGT120/VCCCORE101

VCCGT39

VCCGT40
VCCGT41

VCCGT42
VCCGT35

VCCGT36
VCCGT37

VCCGT38
VCCGT49

VCCGT51
VCCGT52

VCCGT53
VCCGT54

VCCGT43
VCCGT44

VCCGT45
VCCGT46

VCCGT47
VCCGT48

VCCGT50
VCCGT62

VCCGT63
VCCGT55

VCCGT56
VCCGT57

WHL-U42_BGA1528

13 of 20

1.5V@54A

VCCGT58
VCCGT59

VCCGT60
VCCGT61

VCCGT64
VCCGT69

VCCGT70
VCCGT71

VCCGT72
VCCGT65

VCCGT66
VCCGT67

VCCGT68
VCCGT73

VCCGT74
VCCGT75

VCCGT76
VCCGT77

VCCGT78
VCCGT79

VCCGT87
VCCGT88

VCCGT89
VCCGT90

VCCGT80
VCCGT81

VCCGT82
VCCGT83

VCCGT84
VCCGT85

VCCGT86
VCCGT95

VCCGT96
VCCGT91

VCCGT92
VCCGT93

VCCGT94
VCCGT98

VCCGT97

VCCGT100

VCCGT101

VCCGT99

VCCGT102
VCCGT104

VCCGT105
VCCGT106

VCCGT103
VCCGT107

VCCGT108
VCCGT109

VCCGT111
VCCGT112

VCCGT110
VCCGT114

VCCGT113

VCCGT116

VCCGT117
VCCGT118

VCCGT_SENSE
VSSGT_SENSE

D15
D17

D18
D20

E4
F5

F6
F7

F8
F11

F14
F17

F20
G11

G12
G14

G15
G17

G18
G20

H5
H6

H7
H8

H11
H12

H14
H15

H17
H18

H20
J7

J8
J11

J14
J17

J20
K2

K11
L7

L8
L10

M9
N7

N8
N9

N10
P2

P8
R9

T8
T9

T10
U8

U10

V9

W8
W9

E3
D2

+VCC_GT

VCCGT_SENSE_R
VSSGT_SENSE_R

+VCC_GT

1

Close C PU

RC160

100_0402_1%

2

1

RC632 0_0201_5%@

1 2

RC631 0_0201_5%@

2

VCC_SENSE_GT <88 >
VSS_SENSE_GT <88>

12

RC161

100_0402_1%

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU(11/14)PWR-VCCGT

CPU(11/14)PWR-VCCGT

CPU(11/14)PWR-VCCGT

LA-G871P

LA-G871P

LA-G871P

16 109Tuesday, March 05, 2019

16 109Tuesday, March 05, 2019

16 109Tuesday, March 05, 2019

1

1.0

1.0

1.0

5

4

3

2

1

+1.2V_DDR: 1.2V, 3.5A
+1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA
+1.0V_VCCSTG: 1V, 40mA
+VCCPLL_OC: 1.2V, 260mA
+1.0VS_VCCIO: 0.85~0.95V, 3.1A

D D

C C

+VCC_SA: 1.15V, 5.1A

+VCCPLL_OC source

CZ102 1U_ 0201_6.3V6M

1 2

RZ120 0_020 1_5%@

SIO_SLP_S3#<11,17,42,59,79>

SIO_SLP_S0#<9,11,66,79,8 7>

RZ1418 0_0201_5%@

RZ1419 0_0201_5%@

1 2

1 2

+1.2V_MEM +VCCPLL_OC

1 2

RZ119 0_0402_ 5%@

UZ27

1

VIN1

12

+5V_ALW

2

VIN2

7

VIN thermal

3

VBIAS

VCCPLL_ENVCCSTG_EN

4

ON

EM5201V_D FN8_3X3

VOUT

6

5

GND

2

CZ303

0.1U_0201_1 0V6K

1

Follow 575962 RVP V0P7,VCCSFR_OC enable gated by VCCSTG_EN

+1.0V_VCCSTG source

+1.0V_PRIM

+3.3V_RUN

RZ1422

1 2

1 2

RZ1420

CPU_C10_GATE#<6,87>

B B

@

0_0201_5%

RUN_ON<17,58,59,78,87>

MC74VHC1G0 8DFT2G_SC70-5

1 2

RZ320 0_020 1_5%@

CZ105 1U_ 0201_6.3V6M

100K_0402_5%

+3.3V_ALW

1

B

2

A

UZ35

+5V_ALW

5

P

G

3

12

O

4

VCCSTG_EN

UZ19

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

EM5201V_D FN8_3X3

4.4moh m/6A
TR=12.5us@Vin=1.05V

+1.0V_VCCSTG +1.0V_V CCST

12

JUMP@

PJP2
PAD-OPEN1x1m

+1.0V_VCC STG_C

6

VOUT

5

GND

Follow 575962 RVP V0P7,VCCSTG RAIL design

+1.0V_VCCST source

+1.0V_PRIM

UZ21

VCCST_EN

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

EM5201V_D FN8_3X3

4.4moh m/6A
TR=12.5us@Vin=1.05V

VOUT

+1.0V_VCC ST_C

6

5

GND

12

CZ100 1U_ 0201_6.3V6M

SIO_SLP_S3#<11,17,42,59,79>

SIO_SLP_S4#<11,79,86,87>

A A

RUN_ON<17,58,59,78,87>

Follow 575962 V0p7 PDG page519,Premium design Vccst gated by RUN_ON

RZ1416 0_0201_5%@

RZ1417 0_0201_5%@

RZ1423 0_0201_5%@

+5V_ALW

1 2

1 2

1 2

RC864

@

0_0603_5%

12

JUMP@

PJP1

12

PAD-OPEN1x1m

1 2

CZ101 0.1 U_0201_10V6K

1 2

RZ151 0_ 0603_5%@

pop option with UZ19

1 2

CZ106

0.1U_0201_1 0V6K

RC864 Co-lay
with PJP1

+1.0V_VCCST

RF Request

+1.2V_MEM

place as close as CPU

RF@

RF@

680P_0402_50V7K

1200P_0402_50V7K

1

1

CC1479

CC1478

2

2

+1.0V_VCCST

PSC

PDG0.8 P.479 0402

close to package

1

2

+1.0V_VCCSTG

+1.0V_VCCSTG

0801 Confirmed with
Intel can change to 0201

CC28

1U_0201_6.3V6M

1V@0 .12 A

1V@0 .04 A

1

0801 Confirmed with

PDG0.8 P.479 0402

+1.2V_MEM

Primary Side

Secondary Side

Intel can change to 0201

CC29

2

1U_0201_6.3V6M

+VCCPLL_OC

PSC

1.2V @0.2 6A

close to package

Follow RVP rev1.0

1

PDG0.8 P.479 0402

0801 Confirmed with
Intel can change to 0201

WHL_U PDG rev0. 8 P.479
VDDQ:
Primary Side cap

1x 22uF 0603 + 6x 10uF 0402

Secondary Side cap
4x 1uF 0402/0201 + 3x 10uF 0402

PDG P.479 22U 0603,10U 0402

1

1

CC32

2

2

22U_0603_6.3V6M

PDG P.479 1U 0402/0201,10U 0402

1

1

CC1454

2

2

10U_0402_6.3V6M

1

CC430

2

2

1U_0201_6.3V6M

1

1

1

CC35

CC34

CC33

2

10U_0402_6.3V6M

1

CC45

2

10U_0402_6.3V6M

CC36

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC46

CC195

CC1455

2

2

1U_0201_6.3V6M

10U_0402_6.3V6M

+1.2V_MEM

1.2V @3.5 A

1V@0 .12 A

PDG0.8 P.479
0805 Reserve
MOW WW30

1

1x22U/47U 0805

CC1480

0.1U_0201_10V6K

1

CC37

2

10U_0402_6.3V6M

1

CC1456

2

1U_0201_6.3V6M

CC96

2

22U_0603_6.3V6M

PDG0.8 P.479 0402

0801 Confirmed with
Intel can change to 0201

CC96 follow Intel MOW WW30 change to pop
but 22U_0805 shortage,so use 22U_060 3.

1

CC38

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC1457

2

1U_0201_6.3V6M

1U_0201_6.3V6M

CPU@

UC1N

AD36

VDDQ1

AH32

VDDQ2

AH36

VDDQ3

AM36

VDDQ4

AN32

VDDQ5

AW32

VDDQ6

AY36

VDDQ7

BE32

VDDQ8

BH36

VDDQ9

R32

VDDQ10

Y36

VDDQ11

BC28

RSVD1

BP11

VCCST1

BP2

VCCST2

BG1

VCCSTG1

BG2

VCCSTG2

BL27

VCCPLL_OC1

BM26

VCCPLL_OC2

BR11

VCCPLL1

BT11

VCCPLL2

WHL-U42 _BGA1528

PSC

close to package

1

CC31

2

1U_0201_6.3V6M

1

PDG0.8 P.479 0201

CC1462

2

0.1U_0201_10V6K

CPU POWER 3 OF 4

14 of 20

+1.0V_VCCST

VCCIO1
VCCIO2

VCCIO3
VCCIO4

VCCIO5
VCCIO6

VCCIO7
VCCIO8

VCCIO9

VCCIO10

VCCIO11
VCCIO12

VCCIO13
VCCIO14

VCCIO15
VCCIO16

VCCSA2
VCCSA1

VCCSA3
VCCSA5

VCCSA6
VCCSA4

VCCSA9
VCCSA7

VCCSA8

VCCSA13

VCCSA14
VCCSA10

VCCSA11
VCCSA12

VCCSA15
VCCSA16

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

+VCC_SA

+1.0VS_VCCIO

+1.0VS_VCCIO

AK24

0.95 V@3. 1A

AK26

AL24
AL25

AL26
AL27

AM25
AM27

BH24
BH25

BH26
BH27

BJ24
BJ26

BP16
BP18

BG8
BG10

BH9
BJ8

BJ9
BJ10

BK8
BK25

BK27
BL8

BL9
BL10

BL24
BL26

BM24
BN25

BP28
BP29

BE7
BG7

RC166 100_0402_1%

Primary Side

1 2

RC425 0_0201_5%@

1 2

RC426 0_0201_5%@

1 2

1

CC1458

2

1.15 V@5. 1A

VCCIO_SENSE
VSSIO_SENSE

PDG P.479 0201

1

CC1459

2

1U_0201_6.3V6M

Primary or Secondary Side

1

1

CC235

CC234

2

2

10U_0402_6.3V6M

PDG P.479 0402

Placeholder

1

1

CC40

CC39

2

2

@

@

10U_0402_6.3V6M

+VCC_SA

+1.0VS_VCCIO

Close CPU

12

RC163
100_0402_1 %

VCCIO_SENSE <87>

VSSIO_SENSE <87>

12

12

RC165

@

0_0201_5%

RC164

100_0402_1%

VSS_SENSE_SA <88>
VCC_SENSE_SA <88>

WHL_U PDG rev0. 8 P.479
VCCIO:
Primary Side cap
4x 1uF 0201

Primary or Secondary Side
6x 10uF 0402

Placeholder Only
4x 10uF 0402

1

1

CC1460

CC1461

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

PDG P.479 0402

1

1

1

CC236

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC41

2

@

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC51

CC52

CC237

2

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC42

2

@

10U_0402_6.3V6M

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

CPU(12/14)PWR-VCCIO,MEM

CPU(12/14)PWR-VCCIO,MEM

CPU(12/14)PWR-VCCIO,MEM

Document Num ber Re v

Document Num ber Re v

Document Num ber Re v

LA-G871P

LA-G871P

LA-G871P

1

17 109Tuesday, Marc h 05, 2019

17 109Tuesday, Marc h 05, 2019

17 109Tuesday, Marc h 05, 2019

1.0

1.0

1.0

5

4

3

2

1

close UC1 <100mil

1 2

LC1 LQM18PN2R2NC0L_2P~D

RC422

@

0.01_0603_1%

1 2

D D

0809 BSOD
Pop LC2 INDUCTOR,CC100 22U_0603

+1.0V_PRIM +1.0V_CLK

depop RC175
Add CC103 22U_0603

1 2

LC2 LQM18PN2R2NC0L_2P~D

RC175

@

0.01_0603_1%

1 2

CC100/CC103 one is close to the
CPU and the other is far fr om the CPU.

C C

JUMP@

PJP3

1 2

PAD-OPEN1x3m

1

2

+1.0V_MPHYGT source

close UC1 <120mil

0809 BSOD
Pop LC3 INDUCTOR,CC102 22U_0603
depop RC173
Add CC104 22U_0603

1 2

LC3 LQM18PN2R2NC0L_2P~D

RC173

@

0.01_0603_1%

1 2

CC102/CC104 one is close to the

B B

CPU and the other is far fr om the CPU.

1

2

1

CC85

2

@

22U_0603_6.3V6M

1

2

CC103

CC100

22U_0603_6.3V6M

22U_0603_6.3V6M

CC83/CC70 close to CP5

PDG0.8 P.505 0402

0801 Confirmed with
Intel can change to 0201*2

+1.0V_MPHYGT+1.0V_PRIM

1

2

CC104

CC102

22U_0603_6.3V6M

22U_0603_6.3V6M

CC80/CC69 close to BV2

PDG0.8 P.505 0402

0801 Confirmed with
Intel can change to 0201*2

+1.0V_APLL+1.0V_PRIM

1

CC86

2

@

22U_0603_6.3V6M

1

1

CC70

CC83

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

PDG rev0.8 P.509
Place an 22uF edge cap not more t han
12 mm away measuring from package edge.

+1.0V_AMPHYPLL+1.0V_MPHYGT

1

1

CC69

CC80

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

PDG0.8 P.505 0402

0801 Confirmed with
Intel can change to 0201

+3.3V_ALW_PCH

PDG P.505 no decoup. PDG P.505 no decoup.

12

1

2

CC98 close to CP17

PCH Internal VRM
close to BT24

+1.0V_MPHYGT

LC4

BLM18EG221TN1D_2P~D

1 2

RC845

@RF@

0_0201_5%

CC77

RF@

2.2P_0201_25V

+1.8V_PRIM

1.8V @0. 696 A

1

CC98

2

+VCCPDSW_1P05

PDG0.8 P.505 0402

1.05 V@3 .10 8A

1

2

2

RF@

2.2P_0201_25V

1

1U_0201_6.3V6M

PDG0.8 P.504 0402 reserve

0801 Confirmed with
Intel can change to 0201

1.05 V@0 .02 4A

1

CC65

2

1U_0201_6.3V6M

PDG P.504 0603

CC71

22U_0603_6.3V6M

CC95

+1.0V_MPHYGT

+1.0V_PRIM

CC67/CC68 close t o BP20

1

CC68

2

PDG0.8 P.504 0402

0801 Confirmed with
Intel can change to 0201*2

+3.3V_ALW_PCH

+1.0V_PRIM_CORE

0801 Confirmed with
Intel can change to 0201

VCCHDA

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0V_PRIM

+3.3V_ALW_DSW

1031 change

+3.3V_ALW_PCH

+1.0V_PRIM

+1.0V_PRIM

+1.0V_APLL

1.05 V@1 .62 5A

1

CC67

2

1U_0201_6.3V6M

1U_0201_6.3V6M

3.3V @0. 199 A

1.05 V@4 .26 A

CC66 close to BV18

1

CC66

2

@

1U_0201_6.3V6M

1.05 V@0 .10 2A

1.05 V@0 .15 2A

1.05 V@0 .10 2A

1.05 V@0 .12 9A

3.3V @0. 001 A

3.3V @0. 006 A

3.3V @0. 002 A

CPU@

UC1P

BP20

VCCPRIM_1P05_1

BW16

VCCPRIM_1P05_9

BW18

VCCPRIM_1P05_10

BW19

VCCPRIM_1P05_11

BY16

VCCPRIM_1P05_12

CA14

VCCPRIM_1P05_14

CC15

VCCPRIM_1P8_1

CD15

VCCPRIM_1P8_4

CD16

VCCPRIM_1P8_5

CP17

VCCPRIM_1P8_8

CB22

VCCPRIM_3P3_4

CB23

VCCPRIM_3P3_5

CC22

VCCPRIM_3P3_6

CC23

VCCPRIM_3P3_7

CD22

VCCPRIM_3P3_8

CD23

VCCPRIM_3P3_9

CP29

VCCPRIM_3P3_10

BU15

VCCPRIM_CORE1

BU22

VCCPRIM_CORE2

BV15

VCCPRIM_CORE3

BV16

VCCPRIM_CORE4

BV18

VCCPRIM_CORE5

BV19

VCCPRIM_CORE6

BV20

VCCPRIM_CORE7

BV22

VCCPRIM_CORE8

BW20

VCCPRIM_CORE9

BW22

VCCPRIM_CORE10

CA12

VCCPRIM_CORE11

CA16

VCCPRIM_CORE12

CA18

VCCPRIM_CORE13

CA19

VCCPRIM_CORE14

CA20

VCCPRIM_CORE15

CB12

VCCPRIM_CORE16

CB14

VCCPRIM_CORE17

CB15

VCCPRIM_CORE18

BT24

VCCDSW_1P05

BU14

VCCAPLL_1P05_4

BV12

VCCPRIM_MPHY_1P05_1

BW12

VCCPRIM_MPHY_1P05_3

BW14

VCCPRIM_MPHY_1P05_4

BY12

VCCPRIM_MPHY_1P05_5

BY14

VCCPRIM_MPHY_1P05_6

BV2

VCCAMPHYPLL_1P05

BR15

VCCAPLL_1P05_2

CC12

VCCDUSB_1P05

BR24

VCCDSW_3P3_1

BT20

VCCHDA

BV23

VCCSPI

BT18

VCCPRIM_1P05_4

BT19

VCCPRIM_1P05_5

BU18

VCCPRIM_1P05_7

BU19

VCCPRIM_1P05_8

BT22

VCCPRIM_1P05_6

BP22

VCCPRIM_1P05_2

BV14

VCCPRIM_MPHY_1P05_2

WHL-U42_BGA1528

CPU POWER 4 OF 4

16 of 20

VCCPRIM_3P3_3

VCCRTC

VCCPRIM_1P05_13

DCPRTC

VCCPRIM_1P05_3

VCCAPLL_1P05_3

VCCA_BCLK_1P05

VCCAPLL_1P05_1

VCCA_SRC_1P05

VCCA_XTAL_1P05

VCCDPHY_1P24_2

VCCDPHY_1P24_4

VCCDPHY_1P24_1

VCCDPHY_1P24_3
VCCDPHY_1P24_5

VCCDSW_3P3_2

VCCA_19P2_1P05

VCCPRIM_1P8_2
VCCPRIM_1P8_3

VCCPRIM_1P8_6
VCCPRIM_1P8_7

VCCPRIM_1P8_9

VCCPRIM_3P3_2

VCCPRIM_3P3_1

GPP_B0/CORE_VID0

GPP_B1/CORE_VID1

CB16

BR23

BY20

BP24

BR20

BT12

BP14

BR14

BU12

CP5

BY24

CA24

BY23

CA23
CP25

BT23

BR12

CC18
CC19

CD18
CD19

CP23

BW23

BP23

CB36

CB35

3.3V @0. 199 A

PDG0.8 P.505
0402 reserve

1.05 V@0 .00 9A

1.05 V@0 .10 2A

1.05 V@0 .03 4A

1.05 V@0 .03 4A

1.24 V@0 .61 A

PCH Internal VRM

1.05 V@0 .02 7A

3.3V @0. 199 A

3.3V @0. 199 A

+3.3V_ALW_PCH

1

CC75

2

@

1U_0201_6.3V6M

+1.0V_PRIM

PDG P.505 0201 reserve

+1.0V_PRIM

+1.0V_APLL

+1.0V_PRIM

+1.0V_APLL

+1.0V_PRIM

+1.0V_CLK

+VCCLDOSRAM_1P24

+1.0V_PRIM

+3.3V_ALW_PCH

+3.3V_ALW_PCH

CORE_VID0 <87>
CORE_VID1 <87>

CC75 close to CP29

0801 Confirmed with
Intel can change to 0201,
Follow MOW Delete CC74

DCPRTC

1

2

PCH Internal VRM
close to BP24

CAD NOTE: CAPs

1.8V @0. 696 A

3.0V @0. 002 A

CC76

@

1U_0201_6.3V6M

+VCCDPHY_1P24

+1.8V_PRIM

+RTC_CELL_PCH

1

1

CC72

CC73

2

2

1U_0201_6.3V6M

0.1U_0201_6.3V6K

PDG0.8 P.505 0402

0801 Confirmed with
Intel can change to 0201

PCH Internal VRM

1

close to CP25

PDG P.505 0402

CC84

2

4.7U_0402_6.3V6M

+3.3V_ALW_DSW

3.3V @0. 199 A

1

CC1464 close to CP23

PDG0.8 P.505 0402 reserve

CC1464

2

0801 Confirmed with
Intel can change to 0201

@

1U_0201_6.3V6M

CC72/CC73 close to BR23

1

CC1463 close to BR24

CC1463

2

PDG0.8 P.505 0402 reserve

0801 Confirmed with

@

Intel can change to 0201

1U_0201_6.3V6M

+3.3V_ALW_DSW +3.3V_ALW_PCH

1 2

RC440 0_0402_5%@NDS3@

1 2

RC214 0_0201_5%@

+3.3V_ALW_DSW_R

1 2

RC439 0_0402_5%DS3@

22U_0402_6.3V6M

22U_0402_6.3V6M

@

@

1

1

CC280

CC279

2

2

RC439

RC440RE53 6RC215R C441RC44 2

A A

Support DS3

No Support DS3

V V V

X

V V V

X X

X

X

'V' mean POP, 'X' mean DE-POP

5

QC7 c hange to SB00000SS00
For Merion layout l imit height

QC7

DS3@

NTK3139PT1G_SOT723-3

1 3

D

2

0.1U_0402_25V6K

12

12

@

CC340

X

L2N7002WT1G_SC-70-3

13

D

DS3@

S

QC6

+3.3V_ALW

S

499K_0402_1%

DS3@

12

G

RC432

49.9K_0402_1%

DS3@

RC433

2

G

100K_0402_5%

RC431

1 2

VCCDSW_EN_GPIO <11>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF E NGINEERING DRAWING A ND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT M AY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU(13/14)PCH PWR

CPU(13/14)PCH PWR

CPU(13/14)PCH PWR

Document Number Re v

Document Number Re v

Document Number Re v

LA-G871P

LA-G871P

LA-G871P

1

18 109Tuesday, March 05, 2019

18 109Tuesday, March 05, 2019

18 109Tuesday, March 05, 2019

1.0

1.0

1.0

5

4

3

2

1

CPU@

D D

C C

B B

CR34

VSS_1

BT5

VSS_2

BY5

VSS_3

CP35

VSS_4

CM37

VSS_5

CK37

VSS_6

AW1

VSS_7

CM1

VSS_8

BD6

VSS_9

AY4

VSS_10

B34

VSS_11

E35

VSS_12

A4

VSS_13

AE24

VSS_14

AE26

VSS_15

AF25

VSS_16

AG24

VSS_17

AG26

VSS_18

AH24

VSS_19

AH25

VSS_20

B2

VSS_21

B36

VSS_22

C36

VSS_23

C37

VSS_24

CN1

VSS_25

CN2

VSS_26

CN37

VSS_27

CP2

VSS_28

D1

VSS_29

A32

VSS_30

F33

VSS_31

A3

VSS_32

BJ7

VSS_33

CJ36

VSS_34

A36

VSS_35

BK10

VSS_36

CJ4

VSS_37

AB27

VSS_38

BK2

VSS_39

CK1

VSS_40

AB3

VSS_41

BK28

VSS_42

AB30

VSS_43

BK3

VSS_44

CK4

VSS_45

AB33

VSS_46

BK33

VSS_47

CK7

VSS_48

AB36

VSS_49

BK4

VSS_50

CL2

VSS_51

AB4

VSS_52

BK7

VSS_53

CM13

VSS_54

AB7

VSS_55

BL25

VSS_56

CM17

VSS_57

AC10

VSS_58

BL28

VSS_59

CM21

VSS_60

AC27

VSS_61

BL29

VSS_62

CM25

VSS_63

AC30

VSS_64

BL30

VSS_65

CM29

VSS_66

BL31

VSS_67

CM31

VSS_68

AD33

VSS_69

BL32

VSS_70

CM33

VSS_71

AD35

VSS_72

WHL -U42_BGA1528

UC1R

GND 1 OF 3

17 of 20

VSS_73
VSS_74

VSS_75
VSS_76

VSS_77
VSS_78

VSS_79
VSS_80

VSS_81
VSS_82

VSS_83
VSS_84

VSS_85
VSS_86

VSS_87
VSS_88

VSS_89
VSS_90

VSS_91
VSS_92

VSS_93
VSS_94

VSS_95
VSS_96

VSS_97
VSS_98

VSS_99

VSS_100

VSS_101
VSS_102

VSS_103
VSS_104

VSS_105
VSS_106

VSS_107
VSS_108

VSS_109
VSS_110

VSS_111
VSS_112

VSS_113
VSS_114

VSS_115
VSS_116

VSS_117
VSS_118

VSS_119
VSS_120

VSS_121
VSS_122

VSS_123
VSS_124

VSS_125
VSS_126

VSS_127
VSS_128

VSS_129
VSS_130

VSS_131
VSS_132

VSS_133
VSS_134

VSS_135
VSS_136

VSS_137
VSS_138

VSS_139
VSS_140

VSS_141
VSS_142

VSS_143
VSS_144

BL7
AE25

BM33
CM5

AE27
BM35

CM9
AE30

BM36
CN13

AE7
BM9

CN17
AF27

BN30
CN21

AF3
BN7

CN25
AF30

CN29
AF33

BP15
AF36

AF4
CN5

AF7
BP25

CN9
AG10

BP3
CP1

BP32
CP11

AH27
BP33

CP13
AH28

BP4
CP15

AH29
BP7

CP19
AH30

CP21
AH31

BR19
CP27

AH33
BR25

AH35
CP37

AJ25
BT15

AJ28
BT16

CP9
AJ7

CR2
AK3

CR36
AK33

D21
AK36

BT25
D25

AK4
BT28

AL28
BT33

D5
AL29

BT35

D6

AL32

BT36

D8

AL7

D9

AM10
BU11

E23

AM28

E27

AM33

BU23

E29

AM35
BU24

E31

BU25

E33

AN25

BU7

E9

AN28
BV11

F12

AN29

F15

AN30

F18

AN31

BV3

F2

AN7

BV31

F21

AN8

BV33

F24

BV4

F3

AP3

BW11

F4

AP33

BW15

G21

AP36

G27

AP4
G33

AR28

G35

G36

AT33

BW24

G9

AT35

H21

AT36

BW7

H27
AT4

BY11
AU10

BY15

H9

AU28
BY22

J12

AU29

J15

WHL -U42_BGA1528

CPU@

UC1S

VSS_145

VSS_146
VSS_147

VSS_148
VSS_149

VSS_150
VSS_151

VSS_152
VSS_153

VSS_154
VSS_155

VSS_156
VSS_157

VSS_158
VSS_159

VSS_160
VSS_161

VSS_162
VSS_163

VSS_164
VSS_165

VSS_166
VSS_167

VSS_168
VSS_169

VSS_170
VSS_171

VSS_172
VSS_173

VSS_174
VSS_175

VSS_176
VSS_177

VSS_178
VSS_179

VSS_180
VSS_181

VSS_182
VSS_183

VSS_184
VSS_185

VSS_186
VSS_187

VSS_188
VSS_189

VSS_190
VSS_191

VSS_192
VSS_193

VSS_194
VSS_195

VSS_196
VSS_197

VSS_198
VSS_199

VSS_200
VSS_201

VSS_202
VSS_203

VSS_204
VSS_205

VSS_206
VSS_207

VSS_208
VSS_209

VSS_210
VSS_211

VSS_212
VSS_213

VSS_214
VSS_215

VSS_216

GND 2 OF 3

18 of 20

VSS_217

VSS_218
VSS_219

VSS_220
VSS_221

VSS_222
VSS_223

VSS_224
VSS_225

VSS_226
VSS_227

VSS_228
VSS_229

VSS_230
VSS_231

VSS_232
VSS_233

VSS_234
VSS_235

VSS_236
VSS_237

VSS_238
VSS_239

VSS_240
VSS_241

VSS_242
VSS_243

VSS_244
VSS_245

VSS_246
VSS_247

VSS_248
VSS_249

VSS_250
VSS_251

VSS_252
VSS_253

VSS_254
VSS_255

VSS_256
VSS_257

VSS_258
VSS_259

VSS_260
VSS_261

VSS_262
VSS_263

VSS_264
VSS_265

VSS_266
VSS_267

VSS_268
VSS_269

VSS_270
VSS_271

VSS_272
VSS_273

VSS_274
VSS_275

VSS_276
VSS_277

VSS_278
VSS_279

VSS_280
VSS_281

VSS_282
VSS_283

VSS_284
VSS_285

VSS_286
VSS_287

VSS_288
VSS_289

BY25

J18
AU32

BY28
J21

AV25
BY33

J24
AV28

BY35
J33

AV3
BY36

J36
AV33

J6
AV36

C1
K21

AV4
C21

K22
AV6

C25
K24

AV8
C29

K25
AW28

C33
K27

AW29
C4

K28
AW3

C9
K29

AW30
CA11

K3
AW31

CA15
K30

AY33
CA22

K31
AY35

K32
B12

K4
B15

CA25
K9

B18
CB11

L27
B21

L33
B23

L35
B25

CB18
L36

B27
CB19

L6
B29

CB2
N25

B31
CB20

N27
CB25

CPU@

UC1T

N6

VSS_290

B37

VSS_291

CB3

VSS_292

P10

VSS_293

B5

VSS_294

CB33

VSS_295

P3

VSS_296

B7

VSS_297

CB4

VSS_298

P33

VSS_299

B9

VSS_300

CB7

VSS_301

P36

VSS_302

BA10

VSS_303

CC11

VSS_304

P4

VSS_305

BA28

VSS_306

P7

VSS_307

BA3

VSS_308

CC20

VSS_309

R27

VSS_310

BB3

VSS_311

CC25

VSS_312

R28

VSS_313

BB33

VSS_314

CC28

VSS_315

R29

VSS_316

BB36

VSS_317

CC31

VSS_318

R30

VSS_319

BB4

VSS_320

CC7

VSS_321

R31

VSS_322

BC25

VSS_323

CD11

VSS_324

T27

VSS_325

CD12

VSS_326

T30

VSS_327

BC29

VSS_328

CD14

VSS_329

T33

VSS_330

T35

VSS_331

BC32

VSS_332

CD24

VSS_333

T36

VSS_334

CD25

VSS_335

T7

VSS_336

BC8

VSS_337

CE33

VSS_338

U26

VSS_339

BD28

VSS_340

CE35

VSS_341

U7

VSS_342

BD33

VSS_343

CE36

VSS_344

V26

VSS_345

BD35

VSS_346

CE7

VSS_347

V27

VSS_348

BD36

VSS_349

CF11

VSS_350

V3

VSS_351

BE10

VSS_352

CF14

VSS_353

V30

VSS_354

BE28

VSS_355

CF19

VSS_356

V33

VSS_357

BE29

VSS_358

CF2

VSS_359

V36

VSS_360

BE3

VSS_361

WHL -U42_BGA1528

GND 3 OF 3

19 of 20

VSS_362
VSS_363

VSS_364
VSS_365

VSS_366
VSS_367

VSS_368
VSS_369

VSS_370
VSS_371

VSS_372
VSS_373

VSS_374
VSS_375

VSS_376
VSS_377

VSS_378
VSS_379

VSS_380
VSS_381

VSS_382
VSS_383

VSS_384
VSS_385

VSS_386
VSS_387

VSS_388
VSS_389

VSS_390
VSS_391

VSS_392
VSS_393

VSS_394
VSS_395

VSS_396
VSS_397

VSS_398
VSS_399

VSS_400
VSS_401

VSS_402
VSS_403

VSS_404
VSS_405

VSS_406
VSS_407

VSS_408
VSS_409

VSS_410
VSS_411

VSS_412
VSS_413

VSS_414
VSS_415

VSS_416
VSS_417

VSS_418
VSS_419

VSS_420
VSS_421

VSS_422
VSS_423

VSS_424
VSS_425

VSS_426
VSS_427

VSS_428
VSS_429

VSS_430
VSS_431

VSS_432
VSS_433

CF23
V4

BE30
CF28

W10
BE31

CF3
W27

CF4
W30

BF3
CG33

W7
BF33

CG7
BF36

Y26
BF4

CH31
Y27

BG25
Y30

BG28
CJ11

Y33
CJ14

Y35
BH28

CJ19
Y7

BH29
CJ23

BH32
CJ28

BH33
CJ33

BH35
CJ35

BP19
BR16

BY18
BY19

CC16
BU16

CC14
BR22

BU20
CD20

BT14
BP12

CB24
CC24

J5
U24

BD7
AR4

AU4
AW4

BA6
BC4

BE4
BE8

BA4
BD4

BG4
CJ2

CJ3
AM5

CM4
AC5

AG5
CR6

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

MCP(14/14)VSS

MCP(14/14)VSS

MCP(14/14)VSS

LA-G871P

LA-G871P

LA-G871P

19 109Tuesday, March 05, 2 019

19 109Tuesday, March 05, 2 019

19 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

5

D D

C C

4

3

2

1

Reserve

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

SOC or PCH / FCH

SOC or PCH / FCH

SOC or PCH / FCH

LA-G871P

LA-G871P

LA-G871P

20 109Tuesday, March 05, 2 019

20 109Tuesday, March 05, 2 019

20 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

5

D D

C C

4

3

2

1

Reserve

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

SOC or PCH / FCH

SOC or PCH / FCH

SOC or PCH / FCH

LA-G871P

LA-G871P

LA-G871P

21 109Tuesday, March 05, 2 019

21 109Tuesday, March 05, 2 019

21 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

5

D D

C C

4

3

2

1

Reserve

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

SOC or PCH / FCH

SOC or PCH / FCH

SOC or PCH / FCH

LA-G871P

LA-G871P

LA-G871P

22 109Tuesday, March 05, 2 019

22 109Tuesday, March 05, 2 019

22 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

1

+0.6V_DDR_ VTT

+2.5V_MEM

H_THERMTRIP# <14,24,59>

+DDR_VREF_CA

0.022U_0402_16V7K

CD31

For DDR4

1 2

2

+3.3V_RUN_ DIMM1

+DDR_VREF _A_CA

0.6V_DDR_VTT_ON <8 6>

+1.2V_MEM

+3.3V_RUN

CONN@

JDIMM1B

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS1

2

VSS2

5

VSS3

6

VSS4

9

VSS5

10

VSS6

14

VSS7

15

VSS8

18

VSS9

19

VSS10

22

VSS11

23

VSS12

26

VSS13

27

VSS14

30

VSS15

31

VSS16

35

VSS17

36

VSS18

39

VSS19

40

VSS20

43

VSS21

44

VSS22

47

VSS23

48

VSS24

51

VSS25

52

VSS26

56

VSS27

57

VSS28

60

VSS29

61

VSS30

64

VSS31

65

VSS32

68

VSS33

69

VSS34

72

VSS35

73

VSS36

77

VSS37

78

VSS38

81

VSS39

82

VSS40

85

VSS41

86

VSS42

89

VSS43

90

VSS44

93

VSS45

94

VSS46

98

VSS47

262

GND1

264

NPTH2

LOTES_ADDR02 06-P001A

JDIMM1_EVE NT#

+DDR_VREF_A_CA

REVERSE

RD14 1K _0402_5%@

VDD11
VDD12

VDD13
VDD14

VDD15
VDD16

VDD17
VDD18

VDD19

VPP1
VPP2

VSS48
VSS49

VSS50
VSS51

VSS52
VSS53

VSS54
VSS55

VSS56
VSS57

VSS58
VSS59

VSS60
VSS61

VSS62
VSS63

VSS64
VSS65

VSS66
VSS67

VSS68
VSS69

VSS70
VSS71

VSS72
VSS73

VSS74
VSS75

VSS76
VSS77

VSS78
VSS79

VSS80
VSS81

VSS82
VSS83

VSS84
VSS85

VSS86
VSS87

VSS88
VSS89

VSS90
VSS91

VSS92
VSS93

VSS94

GND2

NPTH1

1 2

+1.2V_MEM

1K_0402_1%

12

1K_0402_1%

12

+1.2V_MEM

141
142

147
148

153
154

159
160

163

258

VTT

257
259

99
102

103
106

107
167

168
171

172
175

176
180

181
184

185
188

189
192

193
196

197
201

202
205

206
209

210
213

214
217

218
222

223
226

227
230

231
234

235
238

239
243

244
247

248
251

252

261

263

RD15

1 2

RD17 2_ 0402_1%

RD16

12

24.9_0402_1%

12

RD18

5

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..16]<7>

Layout Note:
Place near JDIMM1

D D

C C

+1.2V_MEM

12

+1.2V_MEM

1

2

10U_0603_10V6M

CD1

12

1U_0201_6.3V6M

1

CD9

2

10U_0603_10V6M

10U_0603_10V6M

CD3

CD2

12

12

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD11

CD10

2

2

0801 Confirmed with
Intel 1U can change to 0201

Layout Note:
Place near
JDIMM1.258

Refence WHL R VP rev0 .7

10U_0603_10V6M

10U_0603_10V6M

CD4

CD5

12

12

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD13

CD12

2

2

10U_0603_10V6M

1U_0201_6.3V6M

Refence WHL R VP rev0 .7

+0.6V_DDR_VTT

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0603_10V6M

@

12

12

CD63

B B

DIMM Select

SA01SA1

0

DIMM1

*

DIMM2

1

0

DIMM3

1

DIMM4

A A

1U_0201_6.3V6M

10U_0603_10V6M

1

1

CD23

CD24

CD22

2

2

0801 Confirmed with
Intel 1U can change to 0201

SA2

0

0

0

0

0

0

1

1

CD69

2

+3.3V_RUN

12

12

Merion Limit height
CD17 change to SGA0000AM00 H=1.0mm(MAX)

WHL_U PDG rev0.8 P.92
VDDQ:

4 near each side of the DIMM

10U_0603_10V6M

10U_0603_10V6M

220U_D7_2VM_R4.5M

connector close to VDD pins
16x 10uF 0603

@

1

16x 1uF 0402

CD8

CD7

CD6

12

CD14

1

2

RD4

@

0_0201_5%

RD5

@

0_0201_5%

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

CD70

CD17

12

+

Placehold er
1x 330uF 7343

2

VPP :
DIMM pin side, 1 p er DIMM
2x 10uF 0603
2x 1uF 0402

+2.5V_MEM

1U_0201_6.3V6M

1

CD15

CD16

2

WHL_U PDG rev0.8 P.92
VTT:

Place on VTT plane close to SODIMM
2x 10uF 0603(1 cap stuffed, 1 placeholder)
4x 1uF 0402
VDD SP D:
Place close to DIMM
2x 0.1uF 0402
2x 2.2uF 0402

+3.3V_RUN+3.3V_ RUN

12

RD6

@

0_0201_5%

12

RD7

@

0_0201_5%

1U_0201_6.3V6M

1

2

0801 Confirmed with
Intel 1U can change to 0201

+3.3V_RUN

12

RD10

@

0_0603_5%

+3.3V_RUN_ DIMM1

2.2U_0402_6.3V6M

1

1

CD27

2

2

12

RD8

@

0_0201_5%

DIMM1_SA0

DIMM1_SA1

DIMM1_SA2

12

RD9

@

0_0201_5%

CD18

0.1U_0201_10V6K

CD28

1U_0201_6.3V6M

1

CD19

2

+DDR_VREF _A_CA

1

2

4

DDR_A_CLK 0<7>
DDR_A_CLK #0<7>

DDR_A_CLK 1<7>

DDR_A_CLK #1<7>

DDR_A_CKE 0<7>

DDR_A_CKE 1<7>

DDR_A_CS# 0<7>

DDR_A_CS# 1<7>

DDR_A_ODT0<7>
DDR_A_ODT1<7>

DDR_A_BG0<7>

10U_0603_10V6M

10U_0603_10V6M

1

CD21

CD20

2

1

CD29

@

1

2

0.1U_0201_6.3V6K

CD25

0.1U_0402_2 5V6

1

2

2

2.2U_0402_6.3V6M

CD26

1 2

RD12 0_ 0201_5%@

DDR_A_BG1<7>

DDR_A_ACT#< 7>

DDR_A_PAR ITY<7>

DDR_A_ALE RT#<7>

DDR_XDP_W AN_SMB DAT<8 ,24,79>

DDR_XDP_W AN_SMB CLK<8 ,24,79>

+1.2V_MEM

DDR_A_CLK 0

DDR_A_CLK #0

DDR_A_CLK 1

DDR_A_CLK #1

DDR_A_CKE 0

DDR_A_CKE1

DDR_A_CS# 0
DDR_A_CS# 1

1

T50PA D~D @

1

T51PA D~D @

DDR_A_ODT0
DDR_A_ODT1

DDR_A_BG0
DDR_A_BG1

DDR_A_BA0

DDR_A_BA0<7>

DDR_A_BA1

DDR_A_BA1<7>

DDR_A_MA0
DDR_A_MA1

DDR_A_MA2
DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA1 0

DDR_A_MA1 1

DDR_A_MA1 2
DDR_A_MA1 3

DDR_A_MA1 4

DDR_A_MA1 5
DDR_A_MA1 6

DDR_A_ACT#

DDR_A_PAR ITY
DDR_A_ALE RT#

JDIMM1_EVE NT#
DDR_DRAMRS T#_R

DIMM1_SA2

DIMM1_SA1

DIMM1_SA0

+1.2V_MEM

470_0402_1%

12

RD11

DDR_DRAMRS T#

DDR_DRAMRST# <7>DDR_DRAMRST#_R<24>

3

Link LOTES_ADDR0206-P001A02 done 0410

CONN@

JDIMM1A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR02 06-P001A

REVERSE

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

DDR_VTT_CTRL<7>

DQ10

DQ11
DQ12

DQ13
DQ14

DQ15

DQ16

DQ17
DQ18

DQ19

DQ20
DQ21

DQ22
DQ23

DQ24
DQ25

DQ26
DQ27

DQ28
DQ29

DQ30

DQ31

DQ32

DQ33
DQ34

DQ35
DQ36

DQ37
DQ38

DQ39

DQ40
DQ41

DQ42
DQ43

DQ44
DQ45

DQ46
DQ47

DQ48
DQ49

DQ50

DQ51
DQ52

DQ53
DQ54

DQ55

DQ56

DQ57
DQ58

DQ59

DQ60
DQ61

DQ62
DQ63

8

DQ0

7

DQ1

20

DQ2

21

DQ3

4

DQ4

3

DQ5

16

DQ6

17

DQ7

13

11

28

DQ8

29

DQ9

41

42
24

25
38

37

34

32

50

49
62

63

46
45

58
59

55

53

70
71

83
84

66
67

79

80

76

74

174

173
187

186
170

169
183

182

179

177

195
194

207
208

191
190

203
204

200

198

216
215

228

229
211

212
224

225

221

219

237

236
249

250

232
233

245
246

242

240

DDR_A_D2

DDR_A_D5
DDR_A_D1

DDR_A_D7
DDR_A_D0

DDR_A_D4
DDR_A_D6

DDR_A_D3
DDR_A_DQS0

DDR_A_DQS# 0

DDR_A_D8

DDR_A_D13

DDR_A_D15

DDR_A_D11

DDR_A_D12

DDR_A_D10

DDR_A_D9

DDR_A_D14

DDR_A_DQS1

DDR_A_DQS# 1

DDR_A_D32

DDR_A_D36

DDR_A_D34

DDR_A_D35

DDR_A_D37

DDR_A_D33

DDR_A_D39

DDR_A_D38

DDR_A_DQS4

DDR_A_DQS# 4

DDR_A_D41

DDR_A_D45

DDR_A_D46

DDR_A_D43

DDR_A_D40

DDR_A_D44

DDR_A_D42

DDR_A_D47
DDR_A_DQS5

DDR_A_DQS# 5

DDR_A_D29

DDR_A_D25

DDR_A_D30
DDR_A_D26

DDR_A_D28

DDR_A_D24

DDR_A_D27

DDR_A_D31

DDR_A_DQS3

DDR_A_DQS# 3

DDR_A_D23

DDR_A_D16

DDR_A_D22

DDR_A_D20

DDR_A_D18

DDR_A_D19

DDR_A_D17

DDR_A_D21

DDR_A_DQS2
DDR_A_DQS# 2

DDR_A_D52

DDR_A_D49

DDR_A_D55

DDR_A_D51

DDR_A_D48

DDR_A_D53

DDR_A_D54

DDR_A_D50

DDR_A_DQS6
DDR_A_DQS# 6

DDR_A_D57

DDR_A_D60

DDR_A_D62

DDR_A_D59

DDR_A_D61

DDR_A_D56

DDR_A_D63

DDR_A_D58
DDR_A_DQS7

DDR_A_DQS# 7

1

NC

2

A

3

GND

74AUP1G07S E-7_TSSOP5

+DDR_VREF _A_CA

+1.2V_MEM

UD1

5

4

Y

1 2

CD32@ 0.1U_0201_10V6K

RD19 100K_0402_5%

VCC

6/8 Change to SA00007WE00 DII

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

DDR4 DIMMA

DDR4 DIMMA

DDR4 DIMMA

Document Num ber Re v

Document Num ber Re v

Document Num ber Re v

LA-G871P

LA-G871P

LA-G871P

1

23 109Tuesday, Marc h 05, 2019

23 109Tuesday, Marc h 05, 2019

23 109Tuesday, Marc h 05, 2019

1.0

1.0

1.0

5

DDR_B_DQS#[0..7]<7>

DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

DDR_B_MA[0..16]<7>

4

3

2

1

For DDR4

Link LOTES_ADDR0206-P001A02 done 0410

CONN@

JDIMM2A

REVERSE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

1

1

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR02 06-P001A

8

DQ0

7

DQ1

20

DQ2

21

DQ3

4

DQ4

3

DQ5

16

DQ6

17

DQ7

13

DQS0(T)

11

DQS0#(C)

28

DQ8

29

DQ9

41

DQ10

42

DQ11

24

DQ12

25

DQ13

38

DQ14

37

DQ15

34

DQS1(T)

32

DQS1#(C)

50

DQ16

49

DQ17

62

DQ18

63

DQ19

46

DQ20

45

DQ21

58

DQ22

59

DQ23

55

DQS2(T)

53

DQS2#(C)

70

DQ24

71

DQ25

83

DQ26

84

DQ27

66

DQ28

67

DQ29

79

DQ30

80

DQ31

76

DQS3(T)

74

DQS3#(C)

174

DQ32

173

DQ33

187

DQ34

186

DQ35

170

DQ36

169

DQ37

183

DQ38

182

DQ39

179

DQS4(T)

177

DQS4#(C)

195

DQ40

194

DQ41

207

DQ42

208

DQ43

191

DQ44

190

DQ45

203

DQ46

204

DQ47

200

DQS5(T)

198

DQS5#(C)

216

DQ48

215

DQ49

228

DQ50

229

DQ51

211

DQ52

212

DQ53

224

DQ54

225

DQ55

221

DQS6(T)

219

DQS6#(C)

237

DQ56

236

DQ57

249

DQ58

250

DQ59

232

DQ60

233

DQ61

245

DQ62

246

DQ63

242

DQS7(T)

240

DQS7#(C)

H_THERMTRIP# <14,23,5 9>

DDR_B_D1
DDR_B_D4

DDR_B_D6
DDR_B_D7

DDR_B_D0
DDR_B_D5

DDR_B_D3
DDR_B_D2

DDR_B_DQS0
DDR_B_DQS# 0

DDR_B_D13
DDR_B_D11

DDR_B_D14
DDR_B_D10

DDR_B_D9
DDR_B_D8

DDR_B_D12
DDR_B_D15

DDR_B_DQS1
DDR_B_DQS# 1

DDR_B_D32
DDR_B_D37

DDR_B_D38
DDR_B_D35

DDR_B_D36
DDR_B_D33

DDR_B_D34
DDR_B_D39

DDR_B_DQS4
DDR_B_DQS# 4

DDR_B_D41
DDR_B_D47

DDR_B_D43
DDR_B_D42

DDR_B_D45
DDR_B_D46

DDR_B_D40
DDR_B_D44

DDR_B_DQS5
DDR_B_DQS# 5

DDR_B_D17

DDR_B_D20

DDR_B_D22
DDR_B_D19

DDR_B_D16

DDR_B_D21

DDR_B_D23
DDR_B_D18

DDR_B_DQS2

DDR_B_DQS# 2

DDR_B_D25

DDR_B_D29

DDR_B_D27
DDR_B_D30

DDR_B_D24

DDR_B_D28

DDR_B_D26
DDR_B_D31

DDR_B_DQS3
DDR_B_DQS# 3

DDR_B_D48
DDR_B_D49

DDR_B_D51

DDR_B_D54

DDR_B_D52
DDR_B_D53

DDR_B_D50
DDR_B_D55

DDR_B_DQS6
DDR_B_DQS# 6

DDR_B_D57
DDR_B_D60

DDR_B_D59

DDR_B_D63

DDR_B_D61
DDR_B_D56

DDR_B_D58
DDR_B_D62

DDR_B_DQS7
DDR_B_DQS# 7

+DDR_VREF _B_CA

+3.3V_RUN_ DIMM2

+DDR_VREF _B_CA

+1.2V_MEM

+DDR_VREF_B_CA

CONN@

JDIMM2B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS1

2

VSS2

5

VSS3

6

VSS4

9

VSS5

10

VSS6

14

VSS7

15

VSS8

18

VSS9

19

VSS10

22

VSS11

23

VSS12

26

VSS13

27

VSS14

30

VSS15

31

VSS16

35

VSS17

36

VSS18

39

VSS19

40

VSS20

43

VSS21

44

VSS22

47

VSS23

48

VSS24

51

VSS25

52

VSS26

56

VSS27

57

VSS28

60

VSS29

61

VSS30

64

VSS31

65

VSS32

68

VSS33

69

VSS34

72

VSS35

73

VSS36

77

VSS37

78

VSS38

81

VSS39

82

VSS40

85

VSS41

86

VSS42

89

VSS43

90

VSS44

93

VSS45

94

VSS46

98

VSS47

262

GND1

264

NPTH2

LOTES_ADDR02 06-P001A

+1.2V_MEM

1K_0402_1%

12

RD28

RD30 2_ 0402_1%

1K_0402_1%

12

RD29

VDD11
VDD12

VDD13
VDD14

VDD15
VDD16

VDD17
VDD18

VDD19

VTT

VPP1
VPP2

VSS48
VSS49

VSS50
VSS51

VSS52
VSS53

VSS54
VSS55

VSS56
VSS57

VSS58
VSS59

VSS60
VSS61

VSS62
VSS63

VSS64
VSS65

VSS66
VSS67

VSS68
VSS69

VSS70
VSS71

VSS72
VSS73

VSS74
VSS75

VSS76
VSS77

VSS78
VSS79

VSS80
VSS81

VSS82
VSS83

VSS84
VSS85

VSS86
VSS87

VSS88
VSS89

VSS90
VSS91

VSS92
VSS93

VSS94

GND2

NPTH1

1 2

+1.2V_MEM

141
142

147
148

153
154

159
160

163

258

257
259

99
102

103
106

107
167

168
171

172
175

176
180

181
184

185
188

189
192

193
196

197
201

202
205

206
209

210
213

214
217

218
222

223
226

227
230

231
234

235
238

239
243

244
247

248
251

252

261

263

12

24.9_0402_1%

12

RD31

+DDR_VREF_B_DQ

0.022U_0402_16V7K

CD62

+0.6V_DDR_ VTT

+2.5V_MEM

DDR_DRAMRS T#_R

+1.2V_MEM

JDIMM2_EVE NT#

DDR_B_CLK 0
DDR_B_CLK #0

DDR_B_CLK 1
DDR_B_CLK #1

DDR_B_CKE 0
DDR_B_CKE 1

DDR_B_CS# 0
DDR_B_CS# 1

T54PA D~D @

T55PA D~D @

DDR_B_ODT0
DDR_B_ODT1

DDR_B_BG0
DDR_B_BG1

DDR_B_BA0
DDR_B_BA1

DDR_B_MA0
DDR_B_MA1

DDR_B_MA2

DDR_B_MA3

DDR_B_MA4
DDR_B_MA5

DDR_B_MA6

DDR_B_MA7

DDR_B_MA8
DDR_B_MA9

DDR_B_MA1 0

DDR_B_MA1 1

DDR_B_MA1 2

DDR_B_MA1 3

DDR_B_MA1 4

DDR_B_MA1 5
DDR_B_MA1 6

DDR_B_ACT#

DDR_B_PAR ITY
DDR_B_ALE RT#

JDIMM2_EVE NT#

DIMM2_SA2
DIMM2_SA1

DIMM2_SA0

1 2

RD27 1K _0402_5%@

Layout Note:

D D

+1.2V_MEM

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

CD35

CD33

CD34

CD36

12

12

12

12

+1.2V_MEM

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD41

2

2

C C

+0.6V_DDR_VTT

10U_0603_10V6M

@

12

CD66

B B

1U_0201_6.3V6M

1

1

CD43

CD42

CD44

2

2

0801 Confirmed with
Intel 1U can change to 0201

Layout Note:
Place near
JDIMM2.258

Refence WHL R VP rev0 .7

1U_0201_6.3V6M

10U_0603_10V6M

1

1

12

CD55

CD54

2

2

0801 Confirmed with
Intel 1U can change to 0201

DIMM Select

SA2

SA01SA1

DIMM1

DIMM2

DIMM3

*

DIMM4

0

0

0

0

0

1

0

0

0

1

1

Place near JDIMM2

Refence WHL R VP rev0 .7

10U_0603_10V6M

10U_0603_10V6M

CD37

CD38

12

12

12

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

1

CD46

CD45

2

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD71

CD56

2

2

+3.3V_RUN

12

RD20

@

0_0201_5%

12

RD21

@

0_0201_5%

Merion Limit height
CD49 change to SGA0000AM00 H=1.0mm(MAX)

WHL_U PDG rev0.8 P.92
VDDQ:

4 near each side of the DIMM

10U_0603_10V6M

220U_D7_2VM_R4.5M

10U_0603_10V6M

CD39

12

1U_0201_6.3V6M

CD47

WHL_U PDG rev0.8 P.92
VTT:

Place on VTT plane close to SODIMM
2x 10uF 0603(1 cap stuffed, 1 placeholder)
4x 1uF 0402
VDD SP D:
Place close to DIMM
2x 0.1uF 0402
2x 2.2uF 0402

CD72

12

RD22

@

0_0201_5%

12

RD23

@

0_0201_5%

connector close to VDD pins
16x 10uF 0603(2 DIMMS TOTAL)

@

1

CD40

CD49

16x 1uF 0402(2 DIMMS TOTAL)

+

Placehold er
1x 330uF 7343

2

VPP :
DIMM pin side, 1 p er DIMM
2x 10uF 0603
2x 1uF 0402

+2.5V_MEM

1U_0201_6.3V6M

1

CD48

2

0801 Confirmed with
Intel 1U can change to 0201

+3.3V_RUN+3.3V_ RUN

12

RD24

@

0_0201_5%

DIMM2_SA0
DIMM2_SA1

DIMM2_SA2

12

RD25

@

0_0201_5%

1U_0201_6.3V6M

1

2

+3.3V_RUN

CD50

1U_0201_6.3V6M

1

CD51

2

12

RD26

@

0_0603_5%

+3.3V_RUN_DIMM2

2.2U_0402_6.3V6M

1

12

CD59

2

+DDR_VREF _B_CA

10U_0603_10V6M

10U_0603_10V6M

1

1

CD53

CD52

2

2

DDR_DRAMRS T#_R<23>

0.1U_0402_2 5V6

0.1U_0201_10V6K

CD60

2.2U_0402_6.3V6M

0.1U_0201_6.3V6K

1

1

CD58

CD57

2

2

CD61

@

DDR_DRAMRS T#_R

3

2

CEST523NC5VB_SOT-523-3

ESD@

DD1

1

1206 change

DD1 close to CD61

0821 ESD team request to add DD1.

1

2

DDR_B_CLK 0<7>
DDR_B_CLK #0<7>

DDR_B_CLK 1<7>

DDR_B_CLK #1<7>

DDR_B_CKE 0<7>
DDR_B_CKE 1<7>

DDR_B_CS# 0<7>

DDR_B_CS# 1<7>

DDR_B_ODT0<7>
DDR_B_ODT1<7>

DDR_B_BG0<7>
DDR_B_BG1<7>

DDR_B_BA0<7>
DDR_B_BA1<7>

DDR_B_ACT#< 7>

DDR_B_PAR ITY<7>

DDR_B_ALE RT#<7>

DDR_XDP_W AN_SMB DAT<8,23 ,79>

DDR_XDP_W AN_SMB CLK<8 ,23,79>

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

DDR4 DIMMB

DDR4 DIMMB

DDR4 DIMMB

Document Num ber Re v

Document Num ber Re v

Document Num ber Re v

LA-G871P

LA-G871P

LA-G871P

1

24 109Tuesday, Marc h 05, 2019

24 109Tuesday, Marc h 05, 2019

24 109Tuesday, Marc h 05, 2019

1.0

1.0

1.0

5

D D

C C

4

3

2

1

Reserve

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

DDR_2

DDR_2

DDR_2

LA-G871P

LA-G871P

LA-G871P

25 109Tuesday, March 05, 2 019

25 109Tuesday, March 05, 2 019

25 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

5

D D

C C

4

3

2

1

Reserve

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

DDR_3

DDR_3

DDR_3

LA-G871P

LA-G871P

LA-G871P

26 109Tuesday, March 05, 2 019

26 109Tuesday, March 05, 2 019

26 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

5

D D

C C

4

3

2

1

Reserve

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

DGPU

DGPU

DGPU

LA-G871P

LA-G871P

LA-G871P

27 109Tuesday, March 05, 2 019

27 109Tuesday, March 05, 2 019

27 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

5

D D

C C

4

3

2

1

Reserve

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

DGPU

DGPU

DGPU

LA-G871P

LA-G871P

LA-G871P

28 109Tuesday, March 05, 2 019

28 109Tuesday, March 05, 2 019

28 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

5

D D

C C

4

3

2

1

Reserve

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

DGPU

DGPU

DGPU

LA-G871P

LA-G871P

LA-G871P

29 109Tuesday, March 05, 2 019

29 109Tuesday, March 05, 2 019

29 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0

5

D D

C C

4

3

2

1

Reserve

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

DGPU

DGPU

DGPU

LA-G871P

LA-G871P

LA-G871P

30 109Tuesday, March 05, 2 019

30 109Tuesday, March 05, 2 019

30 109Tuesday, March 05, 2 019

1

1.0

1.0

1.0