Dell Latitude 5490 Schematics
A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
MODEL NAME :DDM70
PCB NO : LA-F401P
BOM P/N : 431A8F31LXX
BR MLK14 KBL-U UMA
Kabylake U42
2 2
@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
CXDP@ : XDP Component
CONN@ : Connector Component
3 3
U42@ : KBL-R U42 Component
2018-08-17
REV :3.0 (A02)
U22@ : KBL-R U22 Component
DS3@ : Support DS3 Component
MB PCB
Part Number
DAA000EE000
4 4
COPYRIGHT 2015
ALL RIGHT RESERVED
REV:X00
PWB: TXD2X
Description
PCB 25A LA-F401P REV0 MB 1
Layout Dell logo
A
NDS3@ : No Support DS3 Component
650@ : Pop NPCT650VB2YX Component
750@ : Pop NPCT750JAAYX Component
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATIO N OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AU THORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-F401P
LA-F401P
LA-F401P
1 69Friday, August 17, 2018
1 69Friday, August 17, 2018
1 69Friday, August 17, 2018
E
0.2
0.2
0.2
A
B
C
D
E
BreckenridgeMLK 14 UMA Block Diagram
Memory BUS (DDR4)
USB
USH TPM1.2
BCM58102
SPI
DDR4 2133MHz for KBL-U
DDR4 2400MHz for KBL-H
Up to 2x8GB Modules
USB2.0[9]
USB3.0[6]
SLGC55544BVTR
USB POWER SHARE
USB3 Repeater
PS8713B
HD Audio I/F
SATA REPEATER
PI3EQX6741STZDEX
SATA/PCIE REPEATER
PS8558 x2
USB2.0[10]
USH board
P39
P29
P23
SW2_DP1
To Type C
P24
P32
P33
USB2.0[4]
2-Lane eDP1.3
HDMI
SW2_DP3
To VGA
M.2,3030 Key A
WLAN+BT
DP DeMUX
PS8338B
PCIE[3]
P33
USB2.0[7]
DDI[1]
INTEL
Kaby Lake Refresh U MCP
DDI[2]
P22
PAGE 6~19
SATA[0]
ESPI
SMSC KBC
MEC5105
SPI
P35-36
SATA[2]/PCIE[12][11]
W25Q128JVSIQ
128M 4K sector
P8
W25Q128JVSIQ
128M 4K sector
P8
reserve
TPM1.2/2.0 Nuvoton
NPCT750JAAYX
KB/TP CONN
FAN CONN
P45
P36
P39
1 1
EDP CONN
HDMI 1.4
CONN
VGA
CONN
P24
2 2
PCIE[1]
Card reader
RTS5242
P31
SD4.0
P31
3 3
PCIE[4]
Intel Jacksonville
WGI219LM
Transformer
RJ45
P30
P30
P30
DP TO VGA
RTD2166
SATA[1]/PCIE[8]
SATA/PCIE REPEATER
PS8558 x1
SATA[1]/PCIE[8]
M.2,3042 Key B
WWAN/LTE/HCA
USB3.0[2]
Non-AR Type C
DP1.2 4 lanes
TX/RX
USB 3.0 + AM
Type C CONN.
4 4
USB2.0
CC
Vbus
HS Redriver Switch
TUSB546@
PS8743@
P25
GPIO
PD Solution
TPS65982DC
P26-27P28
SW2_DP1
USB3.0[1]
SMBUS
USB2.0[1]
Smart Card
TDA8034HN
RFID/NFC
Fingerprint
CONN
SPI
Reverse Type
DDR4-SO-DIMM X2
BANK 0, 1, 2, 3
P20~21
USB2.0[8]
USB2.0[5]
USB2.0[9]_PS
P43
USB3.0[6]
P42
USB2.0[2]
USB3.0[3]
USB2.0[3]
USB3.0[4]
HDA Codec
ALC3246
P39
P34
P41
LCD Touch
Camera
P29
P29
USB3.0 Conn
PS(Ext Port 1)
P43
USB3.0 Conn
(Ext Port 2)
P44
USB3.0 Conn
(Ext Port 3)
INT.Speaker
Universal Jack
Dig. MIC
P44
P34
P34
P29
Trough eDP Cable
SATA HDD
Conn
P41
M.2 2280
SSD Conn
P40
Trough eDP Cable
LID SWITCH
USH CONN
CPU&PCH XDP Port
AUTOMATIC POWER
SWITCH(APS)
Free Fall sensor
DC/DC Interface
POWER ON/OFF
SW & LED
LED board
P46
P38
P14
P11
P41
P47
P46
5V VR
Charger
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
C
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block diagram
Block diagram
Block diagram
LA-F401P
LA-F401P
LA-F401P
E
2 69Friday, August 17, 2018
2 69Friday, August 17, 2018
2 69Friday, August 17, 2018
0.2
0.2
0.2
5
POWER STATES
Signal
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
PM TABLE
+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW
C C
State
S0
S3
S5 S4/AC
S5 S4/AC doesn't exist
power
plane
+3.3V_ALW_PCH +1.2V_MEM
+RTC_CELL
+1.8V_PRIM
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT
ON
ON
+3.3V_CV2
+2.5V_MEM
+1.0V_VCCST
+5V_RUN
+3.3V_RUN
+0.6V_DDR_VTT
+1.8V_RUN
+VCC_CORE
+VCC_GT
+VCC_SA
+1.0VS_VCCIO
ON ON
ON
OFF
OFFOFF
OFFON
OFF
OFF
M
PLANE
ON
4
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-5
USB3.0-6
SSIC
SSIC
3
2
1
For Breckenridge12/14/15 UMA
PCIE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
PCIE-7
PCIE-8
PCIE-9
PCIE-10
PCIE-11
PCIE-12
SATA
SATA-0
SATA-1
M.2 3042(SATA Cache or HCA)
SATA-1*
SATA-2
M.2 2280 SSD
(PCIex2 or SATA)
12" not support JUSB3
Type-C Port Type-C Port
M.2 3042(LTE)
JUSB2-->Left
JUSB3-->Rear Left
Card Reader
JUSB1-->Right
M.2 3030(WLAN)
LOM
NA
NA
SATA HDD
NA
NA
USB PORT#DESTINATION
DESTINATION
1
2
3
4
5
6
7
8
9
10
JUSB2-->Left
JUSB3-->Rear Left
M2 3042(WWAN)
Camera
NA
M.2 3030(BT)
Touch Screen
JUSB1-->Right
USH
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERI NG DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THI S DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-F401P
LA-F401P
LA-F401P
1
3 69Friday, August 17, 2018
3 69Friday, August 17, 2018
3 69Friday, August 17, 2018
0.2
0.2
0.2
5
Barrel
ADAPTER
D D
CHARGER
ISL9538
(PU901)
Type-C
ADAPTER
+PWR_SRC
SY8286RAC
(PU301)
BATTERY
C C
SY8210A
(PU200)
SY8288C
(PU102)
SY8288B
(PU100)
4
SIO_SLP_S4#
0.6V_DDR_VTT_ON
PCH_PRIM_EN
(SIO_SLP_SUS#)
ALWON
ALWON
+1.2V_MEM
+0.6V_DDR_VTT
+1.0V_PRIM
+5V_ALW
+5V_ALW2
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
TPS22961
(UZ26)
3
PCH_PRIM_EN
(SIO_SLP_SUS#)
SIO_SLP_S4#
+VCC_SFR_OC
TPS62134C
(PU401)
TPS62134D
(PU402)
EM5209
(UZ4)
SLGC55544C
(UI3)
SY6288
(UI1)
SY6288
(UI2)
RUN_ON
PCH_PRIM_EN
(SIO_SLP_SUS#)
RUN_ON
USB_POWERSHARE_VBUS_EN
USB_PWR_EN1#
USB_PWR_EN2#
+1.0VS_VCCIO
+1.0V_PRIM_CORE
+USB_EX2_PWR
+USB_EX3_PWR
TPS22961
(UZ19)
TPS22961
(UZ21)
+5V_RUN
+5V_USB_CHG_PW R
2
CPU PWR
PCH PWR
GT3 PWR
RUN_ON
SIO_SLP_S0#
SIO_SLP_S4#
LP2301
(QV8)
EM5209
(@UZ5)
+1.0V_VCCSTG
+1.0V_VCCST
3.3V_TS_EN
@PCH_3.3V_TS_EN
AUD_PWR_EN
Peripheral Device PWR
TYPE-C Power
GPU PWR
+5V_TSP
+5V_RUN_AUDIO
1
RT8097A
FDMF3035
ISL95857
(PU602)
IMVP_VR_ON
B B
+VCC_SA
FDMF3035
(PU612)
IMVP_VR_ON
+VCC_GT
(PU610)
FDMF3035
(PU613)
U42@
IMVP_VR_ON
+VCC_CORE
AO6405
(QV1)
EN_INVPWR
+BL_PWR_SRC
(PU501)
EM5209
(UZ2)
EM5209
(UZ3)
EM5209
(UZ4)
G524B1T11U
(UV24)
PCH_PRIM_EN
(SIO_SLP_SUS#)
SIO_SLP_LAN#
3.3V_WWAN_EN
@PCH_ALW_ON
PCH_PRIM_EN
(SIO_SLP_SUS#)
RUN_ON
@SIO_SLP_WLAN#
AUX_EN_WOWL
LCD_VCC_TEST_EN
ENVDD_PCH
+1.8V_PRIM
+3.3V_LAN
+3.3V_WW AN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_WLAN
+LCDVDD
AOZ1336
(UZ8)
LP2301A
(QZ1)
EM5209
(@UZ5)
RUN_ON
3.3V_CAM_EN#
AUD_PWR_EN
+1.8V_RUN
+3.3V_CAM
+3.3V_RUN_AUDIO
TYPE-C
+TBTA_VBUS(5V~20V)
A A
AP2204
(UT8)
5
+5V_ALW
+5V_TBT_VBUS
AP2112K
(UT7)
+3.3V_TBT_SX
4
TPS22967
(UZ18)
AP7361C
(PU503)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERI NG DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THI S DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CV2_ON
SIO_SLP_S4#
+3.3V_CV2
+2.5V_MEM
for DDR4
USH/B
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-F401P
LA-F401P
LA-F401P
1
4 69Friday, August 17, 2018
4 69Friday, August 17, 2018
4 69Friday, August 17, 2018
0.2
0.2
0.2
5
4
3
2
1
PD &
FW reflash
2.2K
2.2K
+3.3V_RUN
202
200
202
200
53
51
1
4
DIMM1
DIMM2
XDP
LNG2DMTR
1K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_TP
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
0ohm short pad
0ohm short pad
DMN66D0LDW-7
DMN66D0LDW-7
28
31
LOM
UPD1_SMBCLK_Q
UPD1_SMBDAT_Q
DDR_XDP_WAN_SMBCLK
DDR_XDP_WAN_SMBDAT
2.2K
2.2K
@2.2K
@2.2K
9
TP
8
+3.3V_CV2
M9
USH
L9
USH/B
+3.3V_TBTA_FLASH
B5
A5
R7
R8
D D
SKL-U
R9
W3
SML1_SMBDATA
SML1_SMBCLK
03
W2
02
02
01
01
00 D7
00
04
04
V3
E11 D8
03
C C
KBC
MEC 5105
MEM_SMBCLK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
1K
1K
DAT_TP_SIO_I2C_CLK
C12
CLK_TP_SIO_I2C_DAT
E10
B3
USH_EXPANDER_SMBCLK
E5
USH_EXPANDER_SMBDAT
UPD2_SMBCLK
E7
UPD2_SMBDAT
C3
UPD1_SMBCLK
UPD1_SMBDAT
B4
+3.3V_ALW_PCH
1K
499
499
F7
05
B6
B B
A A
05
A12
06
N10
06
07
M4
M7
07
C508
C8
08
F6
09
E9
09
10
N2
PBAT_CHARGER_SMBCLK
M3
10
PBAT_CHARGER_SMBDAT
2.2K
2.2K
+3.3V_ALW
100 ohm
100 ohm
4
5
Charger
BATTERY
CONN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERI NG DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THI S DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-F401P
LA-F401P
LA-F401P
1
5 69Friday, August 17, 2018
5 69Friday, August 17, 2018
5 69Friday, August 17, 2018
0.2
0.2
0.2
5
4
3
2
1
For 2LANE EDP,BRMLK12
+3.3V_RUN
12
RC175 2.2K_0402_5%
RC178 2.2K_0402_5%
D D
RC176 2.2K_0402_5%
RC177 2.2K_0402_5%
C C
CPU_DP1_CTRL_CLK
12
CPU_DP1_CTRL_DATA
12
CPU_DP2_CTRL_CLK
12
CPU_DP2_CTRL_DATA
HDMI
PS8338(AR)/
PS8348(NON AR)
+1.0VS_VCCIO
CPU_DP1_N0<23>
CPU_DP1_P0<23>
CPU_DP1_N1<23>
CPU_DP1_P1<23>
CPU_DP1_N2<23>
CPU_DP1_P2<23>
CPU_DP1_N3<23>
CPU_DP1_P3<23>
CPU_DP2_N0<22>
CPU_DP2_P0<22>
CPU_DP2_N1<22>
CPU_DP2_P1<22>
CPU_DP2_N2<22>
CPU_DP2_P2<22>
CPU_DP2_N3<22>
CPU_DP2_P3<22>
12
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
GPP_E23
EDP_COMP
CPU_DP1_CTRL_CLK<23>
CPU_DP1_CTRL_DATA<23>
CPU_DP2_CTRL_CLK<22>
CPU_DP2_CTRL_DATA<22>
@
T120
PAD~D
RC2 24.9_0402_1%
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
CPU@
UC1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22
N12
GPP_E23
E52
EDP_RCOMP
KBL-RU42_BGA1356
KBL-RU42_BGA1356.olb
DDI
DISPLAY SIDEBANDS
KBL-R U4+2
EDP
Rev_0.1
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
RSVD
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
RSVD
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
1 OF 20
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
CPU_DP1_AUXN
F50
CPU_DP1_AUXP
E48
F48
G46
CPU_DP3_AUXN
F46
CPU_DP3_AUXP
L9
L7
L6
N9
L10
R12
R11
U13
EDP_TXN0 <29>
EDP_TXP0 <29>
EDP_TXN1 <29>
EDP_TXP1 <29>
EDP_AUXN <29>
EDP_AUXP <29>
@
T281
PAD~D
@
T282
PAD~D
CPU_DP2_AUXN <22>
CPU_DP2_AUXP <22>
@
T1
PAD~D
@
T2
PAD~D
CPU_DP1_HPD <23>
CPU_DP2_HPD <22>
EDP_HPD <29>
PANEL_BKLEN <29>
EDP_BIA_PWM <29>
ENVDD_PCH <29>
EDP_HPD
1 2
RC1 100K_0402_5%
CPU@
UC1I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
B B
A A
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
KBL-RU42_BGA1356
KBL-R U4+2
Rev_0.1
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
9 OF 20
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
CSI2_COMP
TBT_FORCE_PWR
EMMC_RCOMP
RC4 200_0402_1%
1 2
RC3 100_0402_1%
1 2
PAD~D
@
T19
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/14)
CPU (1/14)
CPU (1/14)
LA-F401P
LA-F401P
LA-F401P
6 69Friday, August 17, 2018
6 69Friday, August 17, 2018
6 69Friday, August 17, 2018
1
0.2
0.2
0.2
5
4
3
2
1
For DDR4
DDR_A_DQS#[0..7]<20>
DDR4, Ballout for side by side(Non-Interleave)
D D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
C C
B B
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
AW65
AW63
AW61
AW59
AW39
AW37
AW35
AW33
AW31
AW29
AW27
AW25
UC1B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
Interleave / Non-Interleaved
BB65
DDR0_DQ[16]/DDR0_DQ[32]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
KBL-RU42_BGA1356
CPU@
KBL-R U4+2
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR CH - A
2 OF 20
DDR3L / LPDDR3 / DDR4
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
Interleave / Non-Interleaved
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_ALERT#
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
Rev_0.1
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_PAR
DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>
DDR_A_MA[0..16]<20>
AU53
DDR_A_CLK#0
AT53
DDR_A_CLK0
AU55
DDR_A_CLK#1
AT55
DDR_A_CLK1
BA56
DDR_A_CKE0
BB56
DDR_A_CKE1
AW56
DDR_A_CKE2
AY56
DDR_A_CKE3
AU45
DDR_A_CS#0
AU43
DDR_A_CS#1
AT45
DDR_A_ODT0
AT43
DDR_A_ODT1 DDR_B_ODT0
BA51
DDR_A_MA5
BB54
DDR_A_MA9
BA52
DDR_A_MA6
AY52
DDR_A_MA8
AW52
DDR_A_MA7
AY55
DDR_A_BG0
AW54
DDR_A_MA12
BA54
DDR_A_MA11
BA55
DDR_A_ACT#
AY54
DDR_A_BG1
AU46
DDR_A_MA13
AU48
DDR_A_MA15
AT46
DDR_A_MA14 DDR_B_MA15
AU50
DDR_A_MA16
AU52
DDR_A_BA0
AY51
DDR_A_MA2
AT48
DDR_A_BA1
AT50
DDR_A_MA10
BB50
DDR_A_MA1
AY50
DDR_A_MA0
BA50
DDR_A_MA3
BB52
DDR_A_MA4
AM70
DDR_A_DQS#0
AM69
DDR_A_DQS0
AT69
DDR_A_DQS#1
AT70
DDR_A_DQS1
BA64
DDR_A_DQS#4
AY64
DDR_A_DQS4
AY60
DDR_A_DQS#5
BA60
DDR_A_DQS5
BA38
DDR_B_DQS#0
AY38
DDR_B_DQS0
AY34
DDR_B_DQS#1
BA34
DDR_B_DQS1
BA30
DDR_B_DQS#4
AY30
DDR_B_DQS4
AY26
DDR_B_DQS#5
BA26
DDR_B_DQS5
AW50
DDR_A_ALERT#
AT52
DDR_A_PARITY
AY67
AY68
+DDR_VREF_A_DQ
BA67
AW67
DDR_A_CLK#0 <20>
DDR_A_CLK0 <2 0>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <2 0>
DDR_A_CKE0 <2 0>
DDR_A_CKE1 <2 0>
@
T3
PAD~D
@
T4
PAD~D
DDR_A_CS#0 <2 0>
DDR_A_CS#1 <2 0>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>
DDR_A_BG0 <20>
DDR_A_ACT# <20>
DDR_A_BG1 <20>
DDR_A_BA0 <20>
DDR_A_BA1 <20>
DDR0_PAR,DDR0_ALERT# for DDR4
DDR_A_ALERT# <2 0>
+DDR_VREF_CA
@
T132
PAD~D
+DDR_VREF_B_DQ
DDR_VTT_CTRL <20>
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
UC1C
Interleave / Non-Interleaved
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
KBL-RU42_BGA1356
CPU@
KBL-R U4+2
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR CH - B
3 OF 20
DDR3L / LPDDR3 / DDR4
Interleave / Non-Interleaved
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
Rev_0.1
DDR1_MA[3]
DDR1_MA[4]
DDR1_PAR
DDR_B_DQS#[0..7]<21>
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
DDR_B_D[0..63]<21>
DDR_B_DQS[0..7]<21>
DDR_B_MA[0..16]<21>
DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3
DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT1
DDR_B_MA5
DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
DDR_B_ACT#
DDR_B_BG1
DDR_B_MA13
DDR_B_MA14
DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR_B_CLK#0 <21>
DDR_B_CLK#1 <21>
DDR_B_CLK0 <21>
DDR_B_CLK1 <21>
DDR_B_CKE0 <2 1>
DDR_B_CKE1 <2 1>
DDR_B_CS#0 <21>
DDR_B_CS#1 <21>
DDR_B_ODT0 <21>
DDR_B_ODT1 <21>
DDR_B_BG0 <21>
DDR_B_ACT# <21>
DDR_B_BG1 <21>
DDR_B_BA0 <21>
DDR_B_BA1 <21>
DDR1_PAR,DDR1_ALERT# for DDR4
DDR_B_ALERT# <2 1>DDR_A_PARITY <20>
DDR_B_PARITY <21>
DDR_DRAMRST# <20>
PAD~D
PAD~D
@
T5
@
T6
DDR4 COMPENSATION SIGNALS
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
A A
Max trace length= 500 mil
1 2
RC6 80.6_0402_1%
1 2
RC7 100_0402_1%
1 2
RC5 121_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/14)
CPU (2/14)
CPU (2/14)
LA-F401P
LA-F401P
LA-F401P
7 69Friday, August 17, 2018
7 69Friday, August 17, 2018
7 69Friday, August 17, 2018
1
0.2
0.2
0.2
5
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
PCH_SPI_CLK
RC10 1K_0402_1%CXDP@
PCH_SPI_DO_XDP<14>
D D
PCH_SPI_DO2_XDP<14>
1 2
1 2
RC11 1K_0402_1%CXDP@
+3.3V_1.8V_ESPI
PCH_SPI_CS#2<37>
PCH_CL_CLK1<33>
PCH_CL_DATA1<33>
PCH_CL_RST1#<33>
ESPI_ALERT#<35>
RC21 8.2K_0402_1%
PCH_SPI_D1
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2
12
4
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
AW13
AY11
KBL-RU42_BGA1356
CPU@
UC1E
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
KBL-R U4+2
LPC
3
SMBUS, SMLINK
GPP_C2/SMBALERT#
GPP_C5/SML0ALERT#
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
Rev_0.1
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A8/CLKRUN#
5 OF 20
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
SML0_SMBCLK
SML0_SMBDATA
GPP_C5
SML1_SMBCLK
SML1_SMBDATA
GPP_B23
ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R
ESPI_CLK
PCI_CLK_LPC1
CLKRUN#
2
SML0_SMBCLK <30>
SML0_SMBDATA <30>
SML1_SMBCLK <35>
SML1_SMBDATA <35>
RC366 15_0402_5%
1 2
1 2
RC367 15_0402_5%
RC368 15_0402_5%
1 2
1 2
RC369 15_0402_5%
ESPI_CS# <35,36>
ESPI_RESET# <35,36>
1 2
RC16EMI@ 15_0402_5%
RC22
@
1 2
MEM_SMBCLK
MEM_SMBDATA
ESPI_IO0 <35,36>
ESPI_IO1 <35,36>
ESPI_IO2 <35,36>
ESPI_IO3 <35,36>
22_0402_5%
+3.3V_RUN
6
5
DMN65D8LDW-7_SO T363-6
3 4
QC2B
DMN65D8LDW-7_SO T363-6
ESPI_CLK_5105 <35,36>
For BR/SB
2
1
DDR_XDP_WAN_SMBCLK <14,20,2 1,41>
QC2A
DDR_XDP_WAN_SMBDAT <14,20,21,41>
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
1
+3.3V_RUN
1 2
RC318 2.2K_0402_5%
1 2
RC319 2.2K_0402_5%
+3.3V_ALW_PCH
1 2
RC12 1K_0402_5%
1 2
RC14 1K_0402_5%
1 2
RC15 1K_0402_5%
1 2
RC17 1K_0402_5%
1 2
RC347 499_0402_1%
1 2
RC348 499_0402_1%
ENABLE
DISABLE
ESPI
LPC
ENABLED
DIABLED
+3.3V_LAN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
C C
SOFTWARE TAA
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R
33_0402_5%
@EMI@
12
RC28
33P_0402_50V8J
@EMI@
12
CC7
B B
A A
33_0402_5%
@EMI@
12
RC29
33P_0402_50V8J
@EMI@
12
CC8
+3.3V_SPI
RC30 1K_ 0402_5%@
RC31 1K_ 0402_5%@
RC316 1K_0402_5%@
03/02:follow Intel MOW_2015W W06
12
PCH_SPI_D2_R1
12
PCH_SPI_D3_R1
12
PCH_SPI_D3_R1
PCH_SPI_D1_R1<37>
PCH_SPI_D0_R1<37>
PCH_SPI_CLK_R1<37>
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1
128Mb Flash ROM
@
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R
1 2
RC37 0_0402_5%
1 2
RC39 33_0402_5%
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R
1
2
3
4
W25Q128JVSIQ_SO8
/CS
IO1
IO2
GND
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
RC407 33_0402_5%
@
RC408 33_0402_5%
@
RC409 33_0402_5%
@
RC410 33_0402_5%
@
UC5
VCC
IO3
CLK
IO0
128Mb Flash ROM
UC6
PCH_SPI_CS#1_R1
PCH_SPI_D2_R1
RC42 0_0402_5%
@
1 2
1 2
RC43 33_0402_5%
@
PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R
@
1
/CS
2
IO1
3
IO2
4
GND
W25Q128JVSIQ_SO8
VCC
IO3
CLK
IO0
1 2
1 2
1 2
1 2
+3.3V_SPI
8
7
PCH_SPI_D3_0_R
6
5
PCH_SPI_D0_0_R
+3.3V_SPI
8
7
PCH_SPI_D3_1_R
6
PCH_SPI_CLK_1_R
5
PCH_SPI_D0_1_R
RPC1
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
1 2
0.1U_0201_10V6K
@
1 2
0.1U_0201_10V6K
PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R
CC9
CC10
PCH_SPI_D3_1_RPCH_SPI_D3_R1
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R
+3.3V_SPI
ESPI_CLK_5105
SML0_SMBCLK
SML1_SMBCLK
MEM_SMBCLK
RC32 0_0402_5%
@
+3.3V_ALW_PCH
12
12
12
12
12
12
12
@
RC330_0402_5%
@
RC340_0402_5%
@
RC350_0402_5%
@
RC360_0402_5%
@
RC380_0402_5%
@
RC400_0402_5%
12
RC410_0402_5%
PCH_SPI_CS#1_R1
PCH_SPI_CS#1
PCH_SPI_D0_R1
PCH_SPI_D0
PCH_SPI_D1_R1
PCH_SPI_D1
PCH_SPI_CLK_R1
PCH_SPI_CLK
PCH_SPI_CS#0_R1
PCH_SPI_CS#0
PCH_SPI_D2_R1
PCH_SPI_D2
PCH_SPI_D3_R1
PCH_SPI_D3
@
RF Request
1 2
CC316@RF@ 33P_0402_50V8J
1 2
CC318@RF@ 33P_0402_50V8J
1 2
CC319@RF@ 33P_0402_50V8J
1 2
CC320@RF@ 33P_0402_50V8J
Place close CPU side
@CONN@
ACES_50506-02041-P01
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND1
22
GND2
JSPI1
SML0_SMBCLK
SML0_SMBDATA
CLKRUN#
PCH_SMB_ALERT#
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
WEAK INTERNAL 20K PD
GPP_C5
ESPI@
EC interface
HIGH
LOW(DEFAULT)
WEAK INTERNAL 20k PD
GPP_B23
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
WEAK INTERNAL PD
1 2
RC19 499_0402_1%@
1 2
RC20 499_0402_1%@
1 2
RC27 8.2K_0402_5%LPC@
1 2
RC23 2.2K_0402_5%
1 2
RC25 4.7K_0402_5%
1 2
RC317 150K_ 0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/14)
CPU (3/14)
CPU (3/14)
LA-F401P
LA-F401P
LA-F401P
8 69Friday, August 17, 2018
8 69Friday, August 17, 2018
8 69Friday, August 17, 2018
1
0.2
0.2
0.2
5
+3.3V_RUN
12
RC370 10K_0 402_5%
RC282 100K_0402_5%@
RC237 10K_0402_5%
RC402 49.9K_040 2_1%@
D D
RC403 49.9K_040 2_1%@
+3.3V_ALW_PCH
RC283 10K_0402_5%
RC330 49.9 K_0402_1%@
RC331 49.9 K_0402_1%@
C C
12
12
12
12
TPM_PIRQ#<37>
HDD_FALL_INT
PCH_3.3V_TS_EN
SIO_EXT_SCI#
LPSS_UART2_RXD
LPSS_UART2_TXD
12
SIO_EXT_WAKE#
12
LPSS_UART2_RXD
12
LPSS_UART2_TXD
12
RC560 0_0402_5%
12
RC561 0_0402_5%
@
Reserve
MEDIACARD_IRQ#<31>
HDD_FALL_INT<41>
PCH_3.3V_TS_EN<29>
RC405
@
SBIOS_TX<36>
I2C1_SDA_TP<45>
I2C1_SCK_TP<45>
ONE_DIMM#
TPM_PIRQ#_R
NRB_BIT
HDD_FALL_INT
SIO_EXT_SCI#
BBS_BIT6
12
GPP_C8
100K_0402_5%
TYPEC_CON_SEL1
TYPEC_CON_SEL2
LPSS_UART2_RXD
LPSS_UART2_TXD
4
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
KBL-RU42_BGA1356
CPU@
UC1F
LPSS ISH
KBL-R U4+2
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6
3
Rev_0.1
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
6 OF 20
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
2
MEM_INTERLEAVED
AR_DET#
ISH_I2C2_SDA
ISH_I2C2_SCL
RTD3_CIO_PWR_EN
HDD_EN
CLKDET#
TPM_TYPE
LID_CL#_PCH
ISH_I2C2_SDA <33>
ISH_I2C2_SCL <33>
9/24: Reserve for embedded location ,refer Intel PDG 0.9
ISH_UART0_RXD <33>
ISH_UART0_TXD <33>
ISH_UART0_RTS# <33>
ISH_UART0_CTS# <33>
SIO_EXT_WAKE# <35>
@
T18
PAD~D
LCD_CBL_DET# <29>
HDD_EN <41>
@
T258
PAD~D
@
PAD~D
GPP_A GROUP is +1.8V
T268
WWAN
WLAN
1
For BR/SB UMA
ISH_I2C2_SDA
ISH_I2C2_SCL
LCD_CBL_DET#
1 2
RC363 1K_04 02_5%
1 2
RC362 1K_04 02_5%
1 2
RC287 100K_ 0402_5%
+1.8V_RUN
+3.3V_RUN
+3.3V_RUN
12
RC186 4.7K_ 0402_5%@
NRB_BIT
+3.3V_RUN
10K_0402_5%
RC267@
TPM_TYPE
TPM_TYPE no function,Reserve GPIO for future use,
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
Internal 20k PD
B B
+3.3V_ALW_PCH
RC184 8.2K_ 0402_5%@
No REBOOT
REBOOT ENABLE
12
BBS_BIT6
BOOT BIOS Destination(Bit 6)
HIGH
LOW(DEFAULT)
Internal 20k PD
A A
LPC
SPI
5
1 2
10K_0402_5%
12
DIMM Detect
HIGH
LOW
ONE_DIMM#
RC268
1 DIMM
2 DIMM
1 2
12
Vendor TBDTBDFOXCONJAE
TYPEC_CON_SEL1 LOW
TYPEC_CON_SEL2
RC555
@
10K_0402_5%
RC556
@
10K_0402_5%
+3.3V_ALW_PCH
+3.3V_ALW_PCH+3.3V_ALW_PCH
RC553
@
10K_0402_5%
1 2
TYPEC_CON_SEL2TYPEC_CON_SEL1
LOW
4
12
@
10K_0402_5%
LOW
HIGH LOW
RC554
HIGHHIGH
HIGH
MEM_INTERLEAVED
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RC371
@
10K_0402_5%
1 2
12
10K_0402_5%
RC372
3
DIMM TYPE
HIGH
LOW
Interleave
Non-Interleave
AR_DET#
2
+3.3V_ALW_PCH
RC400
10K_0402_5%
1 2
12
10K_0402_5%
RC401
@
AR_DET#
HIGH NON AR
LOW AR
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (4/14)
CPU (4/14)
CPU (4/14)
LA-F401P
LA-F401P
LA-F401P
RC349 100_ 0402_1%@
1
1 2
RC349
POP
DEPOP TPM
9 69Friday, August 17, 2018
9 69Friday, August 17, 2018
9 69Friday, August 17, 2018
China TPM
0.2
0.2
0.2
5
4
3
2
1
For NON AR, Breckenridge 12/14/15 UMA
CPU@
UC1H
PCIE / USB3 / SATA
D D
Card Reader RTS5242----->
Ext USB3 Port 1 Charge----->
M.2 3030(WLAN) --->
10/100/1G LAN --->
C C
Spindle HDD--->
M.2 3042(SATA Cache
or/HCA)--->
M2 2280 SSD --->
B B
PCIE_PRX_DTX_N1<3 1>
PCIE_PRX_DTX_P1<31>
PCIE_PTX_DRX_N1<3 1>
PCIE_PTX_DRX_P1<31>
USB3_PRX_DTX_N6<42>
USB3_PRX_DTX_P6<42>
USB3_PTX_DRX_N6<42>
USB3_PTX_DRX_P6<42>
PCIE_PRX_DTX_N3<3 3>
PCIE_PRX_DTX_P3<33>
PCIE_PTX_DRX_N3<3 3>
PCIE_PTX_DRX_P3<33>
PCIE_PRX_DTX_N4<3 0>
PCIE_PRX_DTX_P4<30>
PCIE_PTX_DRX_N4<3 0>
PCIE_PTX_DRX_P4<30>
SATA_PRX_DTX_N0<41>
SATA_PRX_DTX_P0<41>
SATA_PTX_DRX_N0<41>
SATA_PTX_DRX_P0<41>
PCIE_PRX_DTX_N8<3 2>
PCIE_PRX_DTX_P8<32>
PCIE_PTX_DRX_N8<3 2>
PCIE_PTX_DRX_P8<32>
1 2
RC45 100_ 0402_1%
CPU_XDP_PRDY#<14>
CPU_XDP_PREQ#<14>
PCIE_PRX_DTX_N11<39>
PCIE_PRX_DTX_P11<39>
PCIE_PTX_DRX_N11<39>
PCIE_PTX_DRX_P11<39>
PCIE_PRX_DTX_N12<39>
PCIE_PRX_DTX_P12<39>
PCIE_PTX_DRX_N12<39>
PCIE_PTX_DRX_P12<39>
PCIE_RCOMPN
PCIE_RCOMPP
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
KBL-RU42_BGA1356
KBL-R U4+2
USB2
SSIC / USB3
USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
Rev_0.1
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E8/SATALED#
8 OF 20
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USBCOMP
USB2_ID
USB2_VBUSSENSE
Reserve
USB_OC3#
M3042_PCIE#_SATA
M2280_PCIE_SATA#
SATALED#
USB3_PRX_DTX_N1 <25>
USB3_PRX_DTX_P1 <2 5>
USB3_PTX_DRX_N1 <25>
USB3_PTX_DRX_P1 <2 5>
USB3_PRX_DTX_N2 <33>
USB3_PRX_DTX_P2 <3 3>
USB3_PTX_DRX_N2 <33>
USB3_PTX_DRX_P2 <3 3>
USB3_PRX_DTX_N3 <44>
USB3_PRX_DTX_P3 <4 4>
USB3_PTX_DRX_N3 <44>
USB3_PTX_DRX_P3 <4 4>
USB3_PRX_DTX_N4 <44>
USB3_PRX_DTX_P4 <4 4>
USB3_PTX_DRX_N4 <44>
USB3_PTX_DRX_P4 <4 4>
USB20_N1 <26>
USB20_P1 <2 6>
USB20_N2 <44>
USB20_P2 <4 4>
USB20_N3 <44>
USB20_P3 <4 4>
USB20_N4 <33>
USB20_P4 <3 3>
USB20_N5 <29>
USB20_P5 <2 9>
USB20_N7 <33>
USB20_P7 <3 3>
USB20_N8 <29>
USB20_P8 <2 9>
USB20_N9 <43>
USB20_P9 <4 3>
USB20_N10 <38>
USB20_P10 <38>
1 2
RC44 113_0402_1%
USB2_ID <26>
1 2
RC338 1K_0402_5%
USB_OC0# <43>
USB_OC1# <44>
USB_OC2# <44>
HDD_DEVSLP <41>
M3042_DEVSLP <33>
M2280_DEVSLP <40>
HDD_DET# <39,41>
M3042_PCIE#_SATA <32,35>
M2280_PCIE_SATA# <39,40>
SATALED# <33,40,4 6>
----->Type-C Port
-----> M.2 3042(LTE)
-----> Ext USB3 Port 2
-----> Ext USB3 Port 3
-----> Typce-C(Non AR)
-----> Ext USB Port 2(LEFT)
-----> Ext USB Port 3(REAR LEFT)
-----> M2 3042(WWAN)
-----> Camera
-----> M.2 3030(BT)
-----> LCD Touch
-----> Ext USB Port 1 Charge(RIGHT)
-----> USH
USB2_ID
USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#
1 2
RC337 10K_0402_5%
10K_8P4R_5%
1
2
3
4 5
RPC3
8
7
6
+3.3V_ALW_PCH
M2280_PCIE_SATA#
HDD_DET#
SATALED#
M3042_PCIE#_SATA
A A
4 5
3
2
1
10K_8P4R_5%
6
7
8
+3.3V_RUN
RPC4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (5/14)
CPU (5/14)
CPU (5/14)
LA-F401P
LA-F401P
LA-F401P
10 69Friday, August 17, 2018
10 69Friday, August 17, 2018
10 69Friday, August 17, 2018
1
0.2
0.2
0.2
5
4
3
2
1
For BR UMA
CPU@
UC1J
D D
WWAN--->
WLAN--->
M.2 SDD--->
LAN--->
Card Reader --->
+3.3V_LAN
C C
+3.3V_ALW_DSW
+1.0V_VCCST
+3.3V_ALW_PCH
10/6 depop, prevent singal step.
B B
H_CPUPWRGD VCCST_PWRGD
100P_0402_50V8J
12
CC300ESD@
A A
ESD Request:place near C PU side
CLK_PCIE_N0<33>
CLK_PCIE_P0<33>
CLKREQ_PCIE#0<33>
+3.3V_RUN
CLK_PCIE_N1<33>
CLK_PCIE_P1<33>
CLKREQ_PCIE#1<33>
+3.3V_RUN
+3.3V_RUN
CLK_PCIE_N3<40>
CLK_PCIE_P3<40>
CLKREQ_PCIE#3<40>
+3.3V_RUN
CLK_PCIE_N4<30>
CLK_PCIE_P4<30>
CLKREQ_PCIE#4<30>
+3.3V_RUN
CLK_PCIE_N5<31>
CLK_PCIE_P5<31>
CLKREQ_PCIE#5<31>
+3.3V_RUN
12
RL70 10K_0402_5%@
RC323 10K_0402_5%
RC67 1K_0402_5%
RC411 10K_0402_5%@
LAN_WAKE#
12
12
PCH_PCIE_WAKE#
12
VCCST_PWRGD
RC71 1K_0402_5%
12
ME_SUS_PWR_ACK
RC74 10K_0402_5%@
12
PCH_PWROK
+3.3V_1.8V_PGPPA
@
RC551 1K_0402_5%
100P_0402_50V8J
12
CC301ESD@
@RF@
12
RC3730_0402_5%
RC189 10K_0402_5%
RC47 10K_0402_5%
RC50 10K_0402_5%
RC59 10K_0402_5%
RC51 10K_0402_5%
RC190 10K_0402_5%
@
T9
PAD~D
12
SUSACK#_R
RC215
POP
DE-POP
PCH_DPWROK PCH_RSMRST#_AND
RC215 0_0402_5%
NDS3@
0.01UF_0402_25V7K
100K_0402_1%
12
1
@
CC266
2
12
12
RC3740_0402_5%
12
12
12
RC3760_0402_5%
12
12
RC3770_0402_5%
12
12
RC3780_0402_5%
12
PCH_PLTRST#
RC220
@
@
TC7SH08FU_SSOP5~D
VCCST_PWRGD<14,35,36>
ME_SUS_PWR_ACK<35>
SUSACK#<35>
NO Support Deep sleep
Support Deep sleep
1 2
@RF@
@RF@
@RF@
@RF@
1 2
RC62 0_0402_5%
1 2
RC244 0_0402_5%
+3.3V_ALW_PCH
1
B
2
A
UC7
RC77 1K_0402_5%@
RC78 60.4_0402_1%
@
RC444 0_0402_5%
RC443 0_0402_5%@
12
RC75
10K_0402_5%
CLKREQ_PCIE#0_R
CLKREQ_PCIE#1_R
CLKREQ_PCIE#2_R
CLKREQ_PCIE#3_R
CLKREQ_PCIE#4_R
CLKREQ_PCIE#5_R
5
P
4
O
G
3
PCH_RSMRST#_AND<14, 45>
1 2
1 2
1 2
1 2
PCH_PLTRST#_AND
12
PCH_PCIE_WAKE#<35,36>
PM_LANPHY_ENABLE<30>
XDP_DBRESET#<14>
+3.3V_RUN
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
KBL-RU42_BGA1356
PLTRST_LAN# <30> PLTRST_TPM# <37>
PCH_PLTRST#_EC <36>
PCH_PLTRST#_AND <31,33,38,40>
RC65
@
100K_0402_5%
PCH_PLTRST#
SYS_RESET#
PCH_RSMRST#_AND
H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPU
SYS_PWROK<14,35>
PCH_PWROK<56>
PCH_DPWROK<35>
ME_SUS_PWR_ACK_R
SUSACK#_R
LAN_WAKE#<30,35>
3.3V_CAM_EN#<29>
12
RC311 10K_0402_5%
XDP_DBRESET#
12
RC225@ 8.2K_0402_5%
12
RC227@ 8.2K_0402_5%
if pop UC12, RC291 also need pop (74AHC1G09GW is OD output)
KBL-R U4+2
CLOCK SIGNALS
PCH_PLTRST#
RC60 0_0402_5%@
PCH_PLTRST#_AND
@
RC325 0_0402_5%
CPU@
UC1K
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
KBL-RU42_BGA1356
1 2
@
RC290 0_0402_5%
+3.3V_RUN
1
B
2
ME_RESET#
A
RSVD_E3/XTAL24_IN
RSVD_C7/XTAL24_OUT
1 2
1 2
5
P
4
O
G
UC12@
74AHC1G09GW_TSSOP5
3
Rev_0.1
KBL-U / KBL-R U4+2
XTAL24_IN/NC_2
XTAL24_OUT/NC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
10 OF 20
KBL-R U4+2
SYS_RESET#_R
Close to CPU
E3
XTAL24_IN_U42_CPU XTAL24_IN_U42
C7
XTAL24_OUT_U42_CPU
E37
XTAL24_IN_U22_CPU
E35
XTAL24_OUT_U22_CPU
F43
CLK_ITPXDP_N
E43
CLK_ITPXDP_P
BA17
SUSCLK
E42
XCLK_BIASREF
AM18
PCH_RTCX1
AM20
PCH_RTCX2
AN18
SRTCRST#
AM16
PCH_RTCRST# <35>
PCH_RTCRST#
1 2
RC417 33_0402_5%U42@
1 2
RC418 33_0402_5%U42@
1 2
RC419 33_0402_5%U22@
1 2
RC420 33_0402_5%U22@
1 2
RC297 0_0402_5%@
1 2
RC298 0_0402_5%@
SUSCLK <33,40>
1 2
RC52 2.7K_0402_1%
1 2
RC324 59_0402_1%@
546765_546765_2014WW 48_Skylake_MOW_Rev_1_0
1 2
RC56 20K_0402_5%
1 2
CC78 1U_0201_6.3V6M
1 2
CC79 1U_0201_6.3V6M@
1 2
RC57 20K_0402_5%
1 2
CC80 1U_0201_6.3V6M
1 2
CC81 1U_0201_6.3V6M@
1
SHORT PADS~D
@
1
CMOS1
2
2
CMOS1 must take care short & touch risk on layout placement
Rev_0.1
AT11
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
11 OF 20
+3.3V_RUN
1 2
RC224 1K_0402_5%
SIO_SLP_S0#
AP15
BA16
AY16
AN15
SIO_SLP_SUS#
AW15
BB17
AN16
BA15
AY15
AU13
PCH_BATLOW#
AU11
PME#
AP16
INTRUDER#
AM10
MPHYP_PWR_EN
AM11
VRALERT#
connect to VCCMPHYGTAON_1P0 enable pin
@
RC291
10K_0402_5%
1 2
SYS_RESET#
SIO_SLP_S0# <17,37,54>
SIO_SLP_S3# <35,36>
SIO_SLP_S4# <17,35,52,55>
SIO_SLP_S5# <35>
SIO_SLP_SUS# <35>
SIO_SLP_LAN# <35,47>
SIO_SLP_WLAN# <35,47>
SIO_SLP_A# <35>
SIO_PWRBTN# <14,35>
AC_PRESENT <35>
PAD~D
XTAL24_OUT_U42
XTAL24_IN_U22
XTAL24_OUT_U22
CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>
+1.0V_CLK5
For Skylake, pop RC 52,depop RC324
For Cannonlake, pop RC324, depop RC52
+RTC_CELL_PCH
MLCC downsize 4/18
MLCC downsize 4/18
VCCDSW_EN_GPIO<18>
VCCDSW_EN<35>
ALW_PWRGD_3V_5V<45, 51>
No Support DS3
@
T115
SYS_RESET#
0.1U_0402_25V6
@ESD@
12
CC302
ESD Request:place near C PU side
XTAL24_IN_U22
XTAL24_OUT_U22
For KBL-R U42
XTAL24_IN_U42
XTAL24_OUT_U42
PCH_RTCX1
PCH_RTCX2
1 2
@
RC445 0_0402_5%
RC439
Support DS3
'V' mean POP, 'X' mean DE-POP
V V V
X X
For KBL-R U22
1 2
@
RC294 0_0402_5%
1M_0402_1%
1 2
@
RC295 0_0402_5%
@
1M_0402_1%
1 2
@
NDS3@
2 1
RB751S40_SOD523-2
NDS3@
RB751S40_SOD523-2
XTAL24_IN_U22_R
U22@
RC46
1 2
XTAL24_OUT_U22_R
For Skylake,YC1 24 M Hz (50 Ohm ESR)
For Cannonlake,YC1 38.4 M Hz (30 Ohm ESR)
546765_546765_2014WW 48_Skylake_MOW_Rev_1_0
1 2
RC550 0_0402_5%
U42@
RC421
RC422 0_0402_5%
@
DC1
XTAL24_IN_U42_R
1 2
XTAL24_OUT_U42_R
For Skylake,YC3 24 M Hz (50 Ohm ESR)
RC54
10M_0402_5%
1 2
1 2
PCH_RTCX2_R
RC296 0_0402_5%
SIO_SLP_SUS#
VCCDSW_EN_Q
DC2
21
RC440RE536 RC215RC441 RC442
X
X
V V V
X
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_ALW
POWER_SW#_M B<36,46>
X
U22@
CC21
1 2
12P_0402_50V8J
3
4
YC1
U22@
24MHZ_12PF_X3G024000DC1H
1
2
U22@
CC22
1 2
12P_0402_50V8J
U42@
CC334
1 2
12P_0402_50V8J
3
4
U42@
YC3
24MHZ_12PF_X3G024000DC1H
1
2
U42@
CC335
1 2
12P_0402_50V8J
CC23
1 2
12P_0402_50V8J
12
YC2
32.768KHZ_12.5PF_9H03200042
ESR MAX=50k ohm
CC26
1 2
12P_0402_50V8J
@DS3@
RC441
1 2
0_0402_5%
RC442
NDS3@
1 2
0_0402_5%
8/21 can change to 10K for merge t o RP
PCH_BATLOW#
AC_PRESENT
INTRUDER#
MPHYP_PWR_EN
VRALERT#
SIO_SLP_LAN#
SUSCLK
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
PCH_PRIM_EN <17,47, 53,54,55>
1 2
RC72 8.2K_0402_5%
1 2
RC243 10K_0402_5%
1 2
RC69 1M_0402_5%
1 2
RC387 10K_0402_5%@
1 2
RC73 10K_0402_5%@
1 2
RC344 10K_0402_5%@
1 2
RC68 10K_0402_5%@
1 2
RC48 1K_0402_5%@
JAPS1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND
20
GND
@CONN@
ACES_50506-01841-P01
+3.3V_ALW_DSW
+RTC_CELL_PCH
+3.3V_ALW_PCH
+3.3V_ALW
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (6/14)
CPU (6/14)
CPU (6/14)
LA-F401P
LA-F401P
LA-F401P
1
11 69Friday, August 17, 2018
11 69Friday, August 17, 2018
11 69Friday, August 17, 2018
0.2
0.2
0.2
5
4
3
2
+1.0V_VCCSTG
1
PCH_JTAG_TDI
PCH_JTAG_TDO
CPU@
UC1D
49.9_0402_1%
D63
A54
C65
C63
A65
C55
D55
B54
C56
BA5
AY5
AT16
AU16
H66
H65
UC1G
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
KBL-RU42_BGA1356
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
KBL-RU42_BGA1356
ESD Request. Place near CPU side
PROCHOT#_R
100P_0402_50V8J
12
CPU@
AUDIO
D D
+1.0V_VCCST
RC79 49.9_040 2_1%@
RC80 1K_0402_5%
+1.0V_VCCSTG
RC83 1K_0402_5%
+3.3V_RUN
RC414 10K_0402_5%
RC413 10K_0402_5%
C C
B B
RC278 10K_0402_5%
RC272 10K_0402_5%@
RC279 10K_0402_5%
RC345 100K_0402_5%
RC292 10K_0402_5%
RC404 10K_0402_5%
+3.3V_ALW_PCH
RC346 10K_0402_5%
RC288 10K_0402_5%
12
H_CATERR#
12
H_THERMTRIP#
12
PROCHOT#
12
TOUCHPAD_INTR#
12
CAM_MIC_CBL_DET#
12
CONTACTLESS_DET#
12
TOUCH_SCREEN_PD#
12
AUD_PWR_EN
12
IR_CAM_DET#
12
HOST_SD_WP#
12
FFS_INT2
12
SIO_EXT_SMI#
12
KB_DET#
HDA_SYNC_R<34>
HDA_BIT_CLK_R<34>
HDA_SDOUT_R<34>
HDA_RST#_R<3 4>
ME_FWP_PCH
CC27
RF@
47P_0402_50V8J
Close to RC93
TOUCH_SCREEN_PD# don't move to RPC,
HDA_BIT_CLK_R
1
2
PECI_EC<35>
PROCHOT#<35,56,59>
H_THERMTRIP#<20,21,36>
RC84 499_0402_1%
T10
T11
TOUCH_SCREEN_PD#<29>
TOUCHPAD_INTR#<35,45>
TOUCH_SCREEN_DET#<29>
12
1 2
RC92 33_0402_5%
1 2
RC93 33_0402_5%EMI@
RC94 33_0402_5%
1 2
RC223 1K_0402_5%
1 2
RC95 33_0402_5%
1 2
FFS_INT2<41>
IR_CAM_DET#<29>
1 2
XDP_OBS0_R<14>
XDP_OBS1_R<14>
@
PAD~D
@
PAD~D
12
RC88
49.9_0402_1%
KB_DET#<45>
SPKR<34>
RC89
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0<34>
HDA_RST#
PROCHOT#_R
H_THERMTRIP#
XDP_OBS2_R
XDP_OBS3_R
SIO_EXT_SMI#
TOUCHPAD_INTR#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
12
12
RC90
49.9_0402_1%
49.9_0402_1%
FFS_INT2
IR_CAM_DET#
KB_DET#
H_CATERR#
EOPIO_RCOMP
RC91
RF Request. Place near CPU side (Intel MOW)
1
2
HDA_RST#
CC331
2.2P_0402_50V8C
@RF@
+3.3V_ALW_PCH +3.3V_ALW_PCH
12
RC183 8.2K_0402_5%@
TOP SWAP STRAP
A A
HIGH
LOW(DEFAULT)
Internal 20k PD
SPKR HDA_SDOUT
ENABLE
DISABLE
5
RC187 4.7K_04 02_5%@
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
12
DISABLE
ENABLE
4
KBL-R U4+2
CPU MISC
CC336ESD@
KBL-R U4+2
Rev_0.1
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
4 OF 20
GPP_A17/SD_PWR_EN#/ISH_GP7
CPU_XDP_TCLK XDP_JTAGX
B61
CPU_XDP_TCLK
D60
CPU_XDP_TDI
A61
CPU_XDP_TDO
C60
CPU_XDP_TMS
B59
CPU_XDP_TRST#
B56
PCH_JTAG_TCK
D59
PCH_JTAG_TDI
A56
PCH_JTAG_TDO
C59
PCH_JTAG_TMS
C61
CPU_XDP_TRST#
A59
XDP_JTAGX
RC87 1K_04 02_5%@
Rev_0.1
SDIO / SDXC
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
7 OF 20
1 2
@
RC328 0_04 02_5%
CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>
PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>
1 2
AB11
AB13
AB12
W12
W11
CONTACTLESS_DET#
W10
W8
AUD_PWR_EN
W7
BA9
BB9
AB7
SD_RCOMP
AF13
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX
+1.0V_VCCSTG
1 2
RC96 200_0402_1%
0.1U_0402_25V6
@ESD@
12
HDA_SDIN0
1
2
CC332
2.2P_0402_50V8C
@RF@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
2
HDA_SDOUT
CC333
2.2P_0402_50V8C
@RF@
CC303
ESD request,Place near CPU side.
PCH_JTAG_TMS
1 2
RC86 51_0402_5%@
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
+3.3V_ALW_PCH
ME_FWP PCH has internal 20K PD.
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
CAM_MIC_CBL_DET# <29>
CONTACTLESS_DET# <38>
HOST_SD_WP# <31>
AUD_PWR_EN <34>
0.1U_0402_25V6
@ESD@
12
CC304
2
1 2
RC81 51_0402_5%
1 2
RC82 100_0402 _5%
1 2
RC130 51_0402_5%
1 2
ME_FWP
@
PT,ST pop RC222 and SW1; MP pop RC221
RC222
@
1K_0402_5%
1 2
ME_FWP<35>
0.1U_0402_25V6
@ESD@
12
CC305
RC221 0_04 02_5%
ME_FWP_PCH
SW1
@
1
2
ME_FWP_PCH
3
4
5
SS3-CMFTQR9_3P
H_THERMTRIP# PROCHOT#
0.1U_0402_25V6
@ESD@
12
CC312
A
B
C
G1
G2
0.1U_0402_25V6
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (7/14)
CPU (7/14)
CPU (7/14)
LA-F401P
LA-F401P
LA-F401P
1
@ESD@
CC310
0.2
0.2
12 69Friday, August 17, 2018
12 69Friday, August 17, 2018
12 69Friday, August 17, 2018
0.2
5
D D
4
CFG[0..19]<14>
3
2
1
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin
12
RC113 10K_0402_1%@
CFG0
RC112 10K_0402_1%@
RC110 10K_0402_1%@
12
12
Stall reset sequence
HIGH(DEFAULT)
LOW
C C
RC109 1K_04 02_5%
eDP enable
HIGH(DEFAULT)
LOW
B B
No stall(Normal Operation)
stall
12
CFG4
Disabled
Enabled
+1.0V_PRIM_XDP
RC114 49.9 _0402_1%
RC115 1.5K_ 0402_5%
ITP_PMODE<14>
@
T16
PAD~D
@
T17
PAD~D
1 2
U42@
RC436 0_04 02_5%
12
CFG_RCOMP
12
ITP_PMODE
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
UC1S
E68
CFG[0]
B67
CFG[1]
D65
CFG[2]
D67
CFG[3]
E70
CFG[4]
C68
CFG[5]
D68
CFG[6]
C67
CFG[7]
F71
CFG[8]
G69
CFG[9]
F70
CFG[10]
G68
CFG[11]
H70
CFG[12]
G71
CFG[13]
H69
CFG[14]
G70
CFG[15]
E63
CFG[16]
F63
CFG[17]
E66
CFG[18]
F66
CFG[19]
E60
CFG_RCOMP
E8
ITP_PMODE
AY2
RSVD_AY2
AY1
RSVD_AY1
D1
RSVD_D1
D3
RSVD_D3
K46
RSVD_K46
K45
RSVD_K45
AL25
RSVD_AL25
AL27
RSVD_AL27
C71
RSVD_C71
B70
RSVD_B70
F60
RSVD_F60
A52
RSVD_A52
BA70
RSVD_TP_BA70
BA68
RSVD_TP_BA68
J71
RSVD_J71
J68
RSVD_J68
F65
VSS_F65
G65
VSS_G65
F61
RSVD_F61
E61
RSVD_E61
KBL-RU42_BGA1356
CPU@
KBL-R U4+2
RESERVED SIGNALS-1
Rev_0.1
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
RSVD_TP
RSVD_TP
MSM#
PROC_SELECT#
19 OF 20
UC1T
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
AR56
AW71
AW70
AP56
C64
PROC_SELECT#:This pin is for compatibility
with future platforms. It should be unconnected
for KBL
@
T12
PAD~D
@
T13
PAD~D
@
T14
PAD~D
@
T15
PAD~D
@
T128
PAD~D
@
T129
PAD~D
@
T130
PAD~D
@
T126
PAD~D
@
T127
PAD~D
@
PAD~D
@
PAD~D
1 2
RC120 100K_0402_5%@
For Skylake , RC120 depop
For Cannonlake, RC120 pop
546765_546765_2014W W48_Skylake_MOW_Rev_1_0
1/5 2014WW 52 MOW reserve to support
Cannonlake-U PCH compatibility
close UC1.U11/U12 and <400mil
1 2
RC313 0_04 02_5%@
ZVM# for SKYLAKE-U 2+3e
T113
T114
+VCC_1P8+1.8V_PRIM
1
2
MSM# for SKYLAKE-U 2+3e
+1.0V_VCCST
1
CC113
CC112
@
@
2
1U_0201_6.3V6M
MLCC downsize 4/18
1U_0201_6.3V6M
AW69
AW68
AU56
AW48
U12
U11
H11
KBL-RU42_BGA1356
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_U12
RSVD_U11
RSVD_H11
SPARE
Rev_0.1
RSVD_F6
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20
F6
C11
B11
A11
D12
C12
F52
KBL-R U4+2
CPU@
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (8/14)
CPU (8/14)
CPU (8/14)
LA-F401P
LA-F401P
LA-F401P
13 69Friday, August 17, 2018
13 69Friday, August 17, 2018
13 69Friday, August 17, 2018
1
0.2
0.2
0.2
+1.0V_PRIM
1 2
RC216 0_0603_1%@
+1.0V_PRIM_XDP
0.1U_0201_10V6K
0.1U_0201_10V6K
@
CC28
1
1
2
2
D D
Place near
JXDP1
VCCST_PWRGD<11,35,36>
PCH_RSMRST#_AND<11,4 5>
C C
+1.0V_VCCST
+3.3V_RUN
+1.0V_PRIM_XDP
5
+1.0V_PRIM_XDP
@
CC29
XDP_OBS0_R<12>
XDP_OBS1_R<12>
RC123 1K_0402_5%@
RC124CXDP@
PCH_SPI_DO_XDP<8>
SYS_PWROK<11,35>
RC132 150_0402_5%
RC218 150_0402_5%@
RC219 10K_0402_5%@
RC137 3K_04 02_5%
RC138 51_0402_5%@
RC239 0_0402_5%CXDP@
RC240 0_0402_5%CXDP@
RC5 need to close to JCPU1
1 2
1 2
1K_0402_5%
RC217 0_0402_5%@
FIVR_EN
CFG0
RC126 1K_0402_5%@
RC128 0_0402_5%CXDP@
RC129 0_0402_5%@
DDR_XDP_WAN_SMBDAT<8,20,21,41>
DDR_XDP_WAN_SMBCLK<8,20,21,41>
12
FIVR_EN_R
12
FIVR_EN
12
FIVR_EN
12
XDP_DBRESET#
12
CPU_XDP_PREQ#
CPU_XDP_PREQ#<10>
CPU_XDP_PRDY#<10>
1 2
1 2
1 2
1 2
1 2
1 2
PCH_JTAG_TCK<12>
CPU_XDP_TCLK<12>
CPU XDP
H_VCCST_PWRGD_XDP
SIO_PWRBTN#<11,35>
CPU_XDP_PREQ#
CPU_XDP_PRDY#
RESET_OUT#_R
CPU_XDP_TCLK
+1.0V_PRIM_XDP
CFG0
CFG1
CFG2
CFG3
XDP_OBS0
XDP_OBS1
CFG4
CFG5
CFG6
CFG7
FIVR_EN_R
+3.3V_ALW_PCH+1.0VS_VCCIO
1 2
0.1U_0402_25V6
12
CC33@
Place near JXDP1.47
4
CXDP@
XDP_PRSNT_PIN1 CF G3
RC133
1.5K_0402_5%
CXDP@
PCH_SPI_DO_XDP
RESET_OUT#_R
1 2
RC121 0_0402 _5%
1 2
RC122 0_04 02_5%@
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
@CONN@SAMTE_BSH-030-01-L-D-A
Place near JXDP1.48
XDP_DBRESET#
+1.0V_PRIM_XDP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
12
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
ITP_PMODE
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS
0.1U_0402_25V6
CXDP@
CC32
Place near JXDP1.41
3
CFG[0..19]<13>
CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>
ITP_PMODE <13>
XDP_DBRESET# <11>
PCH_SPI_DO2_XDP <8>
SIO_PWRBTN#
+3.3V_ALW_DSW
1.5K_0402_5%
1 2
0.1U_0402_25V6
12
@
RC241
CC269
2
+3.3V_RUN
CC30
12
0.1U_0201_10V6K
TDO_XDP
TDI_XDP
XDP_TMS
TRST#_XDP
RUNPWROK<35>
@
UC8
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
CPU_XDP_TMS
RC131 51_0402_5%
CPU_XDP_TDI
RC134 51_0402_5%
CPU_XDP_TDO
RC135 100_0402_5%
CPU_XDP_TRST#
RC136@ 51_0402_5%
CPU_XDP_TCLK
RC139 51_0402_5%
1 2
XDP_TMS
@
RC228 0_04 02_5%
1 2
TDI_XDP
@
RC229 0_04 02_5%
1 2
TDO_XDP
@
RC230 0_04 02_5%
GND PAD
1 2
1 2
1 2
1 2
1 2
1B
2B
3B
4B
GND
1
3
6
8
11
7
15
+1.0V_VCCSTG
PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>
CPU_XDP_TDO <12>
CPU_XDP_TDI <12>
CPU_XDP_TMS <12>
CPU_XDP_TRST# <12>
B B
A A
TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#
0.1U_0402_25V6
@ESD@
12
CC306
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.
0.1U_0402_25V6
@ESD@
12
CC307
0.1U_0402_25V6
@ESD@
12
CC308
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (9/14)
CPU (9/14)
CPU (9/14)
LA-F401P
LA-F401P
LA-F401P
14 69Friday, August 17, 2018
14 69Friday, August 17, 2018
14 69Friday, August 17, 2018
1
0.2
0.2
0.2
5
+VCC_CORE: 0.3~1.35V
D D
@
T122
PAD~D
@
T123
PAD~D
C C
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache)
+VCC_CORE +VCC_CORE
+VCC_CORE_G0
+VCC_CORE_G1
UC1L
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD
AK32
RSVD
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
KBL-RU42_BGA1356
CPU@
CPU POWER 1 OF 4
KBL-R U4+2
4
Rev_0.1
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
12 OF 20
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
VCCSENSE
VSSSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
+1.0V_VCCSTG_R
VIDSCLK <56>
RC143 0_0603_5%@
+VCC_CORE
1 2
12
1 2
RC140
RC141
100_0402_1%
100_0402_1%
3
VCCSENSE <56>
VSSSENSE <56>
+1.0V_VCCSTG
VIDSCLK
RF Request
1 2
CC321@RF@ 33P_0402_50V8J
Place close CPU side
2
PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side , underneath the package
Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
1
B B
SVID ALERT
VIDALERT_N<56>
SVID DATA
A A
VIDSOUT<56>
+1.0V_VCCST
1 2
+1.0V_VCCST
1 2
56_0402_1%
RC152
100_0402_1%
RC157
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils
12
H_CPU_SVIDALRT#
RC153220_0402_5%
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils
VIDSOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (10/14)
CPU (10/14)
CPU (10/14)
LA-F401P
LA-F401P
LA-F401P
15 69Friday, August 17, 2018
15 69Friday, August 17, 2018
15 69Friday, August 17, 2018
1
0.2
0.2
0.2
5
4
3
2
1
+VCCGT: 0.3~1.35V
KBL-R 4+2 and KBL-U 2+2&2+3e option (place on power page)
D D
+VCC_GT
+VCC_GT
C C
VCC_GT_SENSE<56>
VSS_GT_SENSE<56>
B B
@
+VCC_GT_+VCC_CORE +VCC_GT
1 2
RC161
1 2
VCC_GT_SENSE
VSS_GT_SENSE
12
RC163
+VCC_GT_K52
100_0402_1%
100_0402_1%
RC437 0_04 02_5%
+VCC_GT
UC1M
KBL-U / KBL-R U4+2
A48
VCCGT/VCCCORE_5
A53
VCCGT/VCCCORE_6
J43
VCCGT/VCCCORE_44
J45
VCCGT/VCCCORE_45
J46
VCCGT/VCCCORE_46
J48
VCCGT/VCCCORE_47
J50
VCCGT/VCCCORE_48
J52
VCCGT/VCCCORE_49
K48
VCCGT/VCCCORE_57
K50
VCCGT/VCCCORE_58
K52
VCCGT/RSVD_6
A58
VCCGT
A62
VCCGT
A66
VCCGT
AA63
VCCGT
AA64
VCCGT
AA66
VCCGT
AA67
VCCGT
AA69
VCCGT
AA70
VCCGT
AA71
VCCGT
AC64
VCCGT
AC65
VCCGT
AC66
VCCGT
AC67
VCCGT
AC68
VCCGT
AC69
VCCGT
AC70
VCCGT
AC71
VCCGT
J53
VCCGT
J55
VCCGT
J56
VCCGT
J58
VCCGT
J60
VCCGT
K53
VCCGT
K55
VCCGT
K56
VCCGT
K58
VCCGT
K60
VCCGT
L62
VCCGT
L63
VCCGT
L64
VCCGT
L65
VCCGT
L66
VCCGT
L67
VCCGT
L68
VCCGT
L69
VCCGT
L70
VCCGT
L71
VCCGT
M62
VCCGT
N63
VCCGT
N64
VCCGT
N66
VCCGT
N67
VCCGT
N69
VCCGT
J70
VCCGT_SENSE
J69
VSSGT_SENSE
KBL-RU42_BGA1356
KBL-R U4+2
CPU@
CPU POWER 2 OF 4
KBL-U / KBL-R U4+2
VCCGTX_AK42/VCCCORE_12
VCCGTX_AK43/VCCCORE_13
VCCGTX_AK45/VCCCORE_14
VCCGTX_AK46/VCCCORE_15
VCCGTX_AK48/VCCCORE_16
VCCGTX_AK50/VCCCORE_17
VCCGTX_AL43/VCCCORE_21
VCCGTX_AL46/VCCCORE_22
VCCGTX_AL50/VCCCORE_23
VCCGTX_AM48/VCCCORE_29
VCCGTX_AM50/VCCCORE_30
VCCGTX_AM52/VCCCORE_31
VCCGTX_AK52/RSVD_5
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
Rev_0.1
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
13 OF 20
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AL43
AL46
AL50
AM48
AM50
AM52
AK52
+VCC_GT_AK52
@
AK53
AK55
AK56
AK58
AK60
AK70
AL53
AL56
AL60
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
RC438 0_04 02_5%
Avoid adding via to adjust DDR trace
So, floating pin of AK70,BB57,BB66,AU58,AU63
Follow KBL-R_U42_Processor_Line_BGA1356_Ballout_Rev1p0
KBL-R 4+2 and KBL-U 2+2&2+3e option (place on power page)
+VCC_GT_+VCC_CORE
1 2
+VCC_GT
+VCC_GTX
VCCGTX for KBL-U 2+3e only
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (11/14)
CPU (11/14)
CPU (11/14)
LA-F401P
LA-F401P
LA-F401P
16 69Friday, August 17, 2018
16 69Friday, August 17, 2018
16 69Friday, August 17, 2018
1
0.2
0.2
0.2
5
4
3
2
1
+5V_ALW
CZ104
@
1 2
4
O
@
CC252
1U_0402_6.3V6K
UZ34
1
2
+1.2V_MEM
1
CC122
2
1U_0201_6.3V6M
@
RZ119 0_0402_5%
UZ26
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
MLCC downsize 4/18
1
CC123
2
CC250
1U_0402_6.3V6K
1U_0201_6.3V6M
SIO_SLP_S0#
SIO_SLP_S3#
AND
1 2
1
2
+VCCPLL_OC source
+1.2V_MEM+1.2V_MEM_CPUCLK
@
RC231 0_0402_5%
1 2
D D
PSC
1
CC176
10U_0402_6.3V6M
1
CC177
2
2
10U_0402_6.3V6M
1
2
PSC
22U_0603_6.3V6M
CC294
1
2
+1.0V_VCCST
C C
PSC
1
2
CC195
1U_0402_6.3V6K
MLCC downsize 4/18
CC178
10U_0402_6.3V6M
22U_0603_6.3V6M
CC295
1
2
+1.0V_VCCSTG
1
2
VDDQ: 8.45A
1
CC179
2
10U_0402_6.3V6M
22U_0603_6.3V6M
CC296
1
2
PSC
1
CC297
2
10U_0402_6.3V6M
+1.2V_MEM_CPUCLK
BSC
+VCC_SFR_OC
1
CC84
CC85
@
@
2
1
1U_0201_6.3V6M
1U_0201_6.3V6M
2
CC288
1U_0402_6.3V6K
1
2
+1.2V_MEM
CC322
RF@
2.2P_0402_50V8C
UC1N
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
KBL-RU42_BGA1356
+1.0V_VCCST
CPU@
1
2
CPU POWER 3 OF 4
PSC
CC202
1U_0402_6.3V6K
KBL-R U4+2
Rev_0.1
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 OF 20
+VCC_SA
+1.0VS_VCCIO
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
VCCIO_SENSE
AM22
VSSIO_SENSE
H21
H20
1 2
RC168 100_0402_1%
+VCC_SA
+1.0VS_VCCIO
12
RC166
100_0402_1%
VSA_SEN- <56>
VSA_SEN+ <5 6>
RC165
1 2
12
RC167
100_0402_1%
VCCIO_SENSE <54>
VSSIO_SENSE <54>
100_0402_1%
RF Request
B B
+1.0V_VCCST source
MLCC downsize 4/18
12
1U_0201_6.3V6M
CZ1003
12
CZ1002
1U_0201_6.3V6M
VCCSTG_EN
PCH_PRIM_EN<11,47,53,54,55>
SIO_SLP_S4#<11,17,3 5,52,55>
1 2
@
RZ120 0_0402_5%
+3.3V_ALW
5
0.1U_0402_10V7K
1
P
B
2
A
G
3
TC7SH08FU_SSOP5~D
+1.0VS_VCCIO
PSC
1
2
+1.0V_VCCSTG source
+VCC_SFR_OC
6
VOUT
5
GND
1
CC118
CC119
2
1U_0201_6.3V6M
1U_0201_6.3V6M
S0 S0Ix S3
HIGH
LOW
HIGH
HIGH
HIGH LOW LOW
LOW
LOW
1 2
CZ103 0.1U_0201_10V6K
+1.0V_VCCST+1.0V_VCCSTG
1 2
RZ151 0_0603_5%@
MLCC downsize 4/18
MLCC downsize 4/18
A A
CZ1000
CZ1001
5
12
1U_0201_6.3V6M
12
1U_0201_6.3V6M
SIO_SLP_S4#<11,17,3 5,52,55>
+5V_ALW
+1.0V_PRIM
UZ21
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm/6A
TR=12.5us@Vin=1.05V
VOUT
GND
6
5
4
+1.0V_VCCST_C
PJP1
12
PAD-OPEN1x1m
1 2
CZ101 0.1U_0201_10V6K
+1.0V_VCCST
SIO_SLP_S0#<11,37,54>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CZ1004
CZ1005
RUN_ON<35,36,47,54>
TC7SH08FU_SSOP5~D
12
1U_0201_6.3V6M
12
1U_0201_6.3V6M
UZ35
RZ320 0_0402_5%@
+5V_ALW
+3.3V_ALW
5
1
B
2
A
3
1 2
P
G
O
+1.0V_PRIM
4
VCCSTG_EN
UZ19
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm/6A
TR=12.5us@Vin=1.05V
2
VOUT
GND
12
PJP2
PAD-OPEN1x1m
6
+1.0V_VCCSTG_C
5
DELL CONFIDENTIAL/PROPRIETARY
pop option with UZ19
1 2
CZ106 0.1U_0201_10V6K
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (12/14)
CPU (12/14)
CPU (12/14)
LA-F401P
LA-F401P
LA-F401P
17 69Friday, August 17, 2018
17 69Friday, August 17, 2018
17 69Friday, August 17, 2018
1
0.2
0.2
0.2
5
+1.0V_PRIM
D D
+1.8V_PRIM
C C
+3.3V_ALW_PCH
+1.8V_PRIM
B B
1 2
@
RC299 0_06 03_5%
1 2
@
RC300 0_04 02_5%
1 2
@
RC301 0_04 02_5%
1 2
@
RC302 0_04 02_5%
1 2
@
RC303 0_04 02_5%
1 2
@
RC304 0_04 02_5%
1 2
RC234 0_0402_5%@
1 2
@
RC235 0_04 02_5%
1 2
RC211 0_0402_5%LPC@
1 2
@ESPI@
RC212 0_04 02_5%
1 2
@
RC305 0_04 02_5%
1 2
@
RC306 0_04 02_5%
1 2
@
RC307 0_04 02_5%
1 2
@
RC308 0_04 02_5%
+3.3V_ALW_PCH
1 2
LC1 BLM15GA750SN1D_2P
1
1
CC105
@
2
2
1U_0201_6.3V6M
+1.0V_MPHYAON
+1.0V_CLK6
+1.0V_DTS
+1.0V_CLK1
+1.0V_CLK3
+1.8V_PGPPF
+3.3V_1.8V_PGPPG
+3.3V_1.8V_PGPPA
+3.3V_PGPPB+3.3V_ALW_PCH
+3.3V_PGPPC
+3.3V_PGPPD
+3.3V_PGPPE
8/28 schematic review
CC104
@
1U_0201_6.3V6M
close UC1.AJ19 and <400mil
close UC1.AF20 and <400mil
+3.3V_1.8V_ESPI
PJP4
1 2
PAD-OPEN1x1m
Must be +1.8V for eSPI I/F
LC1,LC2 need link SM01000S100(S SUPPRE_ FBMA-1H-100505-601T 0402 )
+3.3V_VCCHDA
1
CC313
2
0.1U_0201_10V6K
+1.0V_MPHYAON
1
1
CC861U_0201_6.3V6M
CC871U_0201_6.3V6M
2
2
+1.0V_MPHYGT
close UC1.N15 and CC210 <400mil, CC211 <120mil
1
2
MLCC downsize 4/18
+1.0V_SRAM
1
CC109
@
2
1
MLCC downsize 4/18
CC341
2
RF@
18P_0402_50V8J
close UC1.K15, UC1.L15 and <100mil
@
1 2
RC169 0_0603_5%
1
2
CC281
@
0.1U_0201_10V6K
+1.0V_PRIM
1 2
LC2 BLM15GA7 50SN1D_2P
1
RF@
2
CC225
12P_0402_50V8J
close UC1.V15 and <100mil
MLCC downsize 4/18
A A
close UC1.N20 and <100mil
1 2
@
RC173 0_04 02_5%
5
+1.0V_CLK4+1.0V_PRIM
22U_0603_6.3V6M
CC226
1
2
1 2
@
RC170 0_04 02_5%
close UC1.K19 and <100mil
4
close UC1.AL1 and <120mil
1
1
CC881U_0201_6.3V6M
CC891U_0201_6.3V6M
2
2
MLCC downsize 4/18
1
1
CC98
2
1
CC108
@
2
CC99
2
1U_0201_6.3V6M
+1.0V_APLLEBB
1U_0201_6.3V6M
1
2
+1.0V_AMPHYPLL+1.0V_MPHYGT
22U_0603_6.3V6M
1
2
+1.0V_CLK2+1.0V_PRIM
22U_0603_6.3V6M
1
2
4
CC210
@
1U_0201_6.3V6M
47U_0805_6.3V6M
+1.0V_PRIM_CORE+1.0VO_DSW
CC901U_0201_6.3V6M
CC911U_0201_6.3V6M
@
@
1
1
2
2
close UC1.AF18 and <400mil
+1.0V_AMPHYPLL
+1.0V_APLL
1U_0201_6.3V6M
+1.0V_PRIM
+3.3V_ALW_DSW
+3.3V_VCCHDA
+3.3V_ALW_PCH
+1.0V_PRIM
close UC1.N18 and <120mil
1
CC110
CC111
2
1U_0201_6.3V6M
1U_0201_6.3V6M
close UC1.K15 and <120mil
CC219
1
1
CC129
CC128
@
@
2
2
1U_0201_6.3V6M
MLCC downsize 4/18
+1.0V_APLL
1
CC314
2
0.1U_0201_10V6K
CC220
close UC1.AB19 and <400milclose UC1.K17 and <120mil
@
1
2
+3.3V_SPI
1U_0201_6.3V6M
+1.0V_PRIM
CC931U_0201_6. 3V6M
1
2
@
3
PCH PWR
CC921U_0201_6. 3V6M
UC1O
CPU@
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB_1P0
KBL-RU42_BGA1356
+3.3V_ALW_DSW +3.3V_ALW_PCH
@DS3@
22U_0603_6.3V6M
@
CC279
1
1
2
2
RC439
RC440RE536RC215RC441RC442
Support DS3
No Support DS3
'V' mean POP, 'X' mean DE-POP
V V V
X X
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
KBL-R U4+2
CPU POWER 4 OF 4
1 2
RC440 0_04 02_5%NDS3@
1 2
RC214 0_04 02_5%@
1 2
RC439 0_04 02_5%
22U_0603_6.3V6M
@
CC280
X
V V V
Rev_0.1
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
15 OF 20
+3.3V_ALW_DSW _R
X
X
close UC1.AG15 and <120mil
Must be +1.8V
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+3.3V_1.8V_PGPPA
+3.3V_PGPPD
+1.8V_PGPPF
+3.3V_1.8V_PGPPG
+1.0V_DTS
+3.3V_ALW_PCH
close UC1.AK19 and <120mil
+DCPRTC
close UC1.BB10 and <120mil
+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5
Take care!!! Note1 on Page 19
QC7
LP2301ALT1G_SOT23-3
123
D
S
G
0.1U_0402_25V6K
12
@
CC340
49.9K_0402_1%
RC433
12
L2N7002WT1G_SC-70-3
X
13
D
QC6
2
G
S
2
+3.3V_PGPPB
@
CC1241U_0201_6.3V6M
1
2
close UC1.AA1 and <400mil
CORE_VID0 <54>
CORE_VID1 <54>
+3.3V_ALW
499K_0402_1%
12
RC432
1 2
2
close UC1.Y16 and <400mil
+3.3V_PGPPC
@
CC1251U_0201_6.3V6M
1
CC951U_0201_6.3V6M
@
@
1
2
1
2
2
MLCC downsize 4/18
+RTC_CELL_PCH
1
1
1
2
+1.0V_CLK6
CC214
0.1U_0201_10V6K
2
2
CC270
0.1U_0201_10V6K
close UC1.A10 and <120mil
1
1
CC106
@
@
2
2
1U_0201_6.3V6M
MLCC downsize 4/18
close UC1.L19 and <100mil
100K_0402_5%
RC431
VCCDSW_EN_GPIO <1 1>
DELL CONFIDENTIAL/PROPRIETARY
1
+1.0V_MPHYGT
1 2
@
+3.3V_ALW_PCH
1
2
CC101
1U_0201_6.3V6M
RC309 0_06 03_5%
1 2
@
RC310 0_06 03_5%
+3.3V_1.8V_PGPPG
close UC1.AD15 and <400mil
1
CC126
2
1U_0201_6.3V6M
close UC1.V19 and <120mil
MLCC downsize 4/18
12P_0402_50V8J
RF@
CC337
+1.0V_APLLEBB
1
CC127
2
+3.3V_PGPPE
close UC1.T16 and <400mil
CC941U_0201_6.3V6M
CC961U_0201_6. 3V6M
@
1
2
1
CC102
CC103
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1
2
+1.8V_PRIM
1
CC100
2
CC971U_0201_6. 3V6M
@
1
2
1U_0201_6.3V6M
MLCC downsize 4/18
RF Request
+1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB
1
CC107
1U_0201_6.3V6M
1 2
RC171 0_ 0603_5%
1
2
2
22U_0603_6.3V6M
CC221
1
2
CC323
RF@
2.2P_0402_50V8C
+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM
CC324
RF@
1
CC223
2
1 2
PAD-OPEN1x3m
2.2P_0402_50V8C
close UC1.AK17 and <120mil
1
2
CC224
1U_0402_6.3V6K
0.1U_0201_10V6K
PJP3
+1.0V_MPHYGT source
561280_561280_KBL_UY_PDG_Rev0p9:
MPHY has defeature
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (13/14)
CPU (13/14)
CPU (13/14)
LA-F401P
LA-F401P
LA-F401P
18 69Thursday, September 13, 2018
18 69Thursday, September 13, 2018
18 69Thursday, September 13, 2018
1
+1.0V_SRAM
1U_0201_6.3V6M
1
2
+1.0V_MPHYGT+1.0V_PRIM
CC325
RF@
2.2P_0402_50V8C
0.2
0.2
0.2
5
4
3
2
1
CPU@
KBL-R U4+2
UC1P
A5
VSS
A67
VSS
A70
VSS
AA2
VSS
AA4
D D
C C
B B
VSS
AA65
VSS
AA68
VSS
AB15
VSS
AB16
VSS
AB18
VSS
AB21
VSS
AB8
VSS
AD13
VSS
AD16
VSS
AD19
VSS
AD20
VSS
AD21
VSS
AD62
VSS
AD8
VSS
AE64
VSS
AE65
VSS
AE66
VSS
AE67
VSS
AE68
VSS
AE69
VSS
AF1
VSS
AF10
VSS
AF15
VSS
AF17
VSS
AF2
VSS
AF4
VSS
AF63
VSS
AG16
VSS
AG17
VSS
AG18
VSS
AG19
VSS
AG20
VSS
AG21
VSS
AG71
VSS
AH13
VSS
AH6
VSS
AH63
VSS
AH64
VSS
AH67
VSS
AJ15
VSS
AJ18
VSS
AJ20
VSS
AJ4
VSS
AK11
VSS
AK16
VSS
AK18
VSS
AK21
VSS
AK22
VSS
AK27
VSS
AK63
VSS
AK68
VSS
AK69
VSS
AK8
VSS
AL2
VSS
AL28
VSS
AL32
VSS
AL35
VSS
AL38
VSS
AL4
VSS
AL45
VSS
AL48
VSS
AL52
VSS
AL55
VSS
AL58
VSS
AL64
VSS
KBL-RU42_BGA1356
GND 1 OF 3
Rev_0.1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16 OF 20
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
CPU@
UC1Q
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
KBL-RU42_BGA1356
KBL-R U4+2
Rev_0.1
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
17 OF 20
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
CPU@
UC1R
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
KBL-RU42_BGA1356
KBL-R U4+2
GND 3 OF 3
Rev_0.1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
18 OF 20
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
Note1: VCCPRIM_CORE Implementation with PCH CORE_VID Recommendation
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (14/14)
CPU (14/14)
CPU (14/14)
LA-F401P
LA-F401P
LA-F401P
19 69Friday, August 17, 2018
19 69Friday, August 17, 2018
19 69Friday, August 17, 2018
1
0.2
0.2
0.2
5
4
3
2
1
For DDR4
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7 >
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..16]<7>
Layout Note:
D D
Place near JDIMM1
+1.2V_MEM
10U_0603_10V6M
CD1
12
12
+2.5V_MEM
10U_0603_10V6M
CD2
12
10U_0603_10V6M
10U_0603_10V6M
CD6
CD4
CD5
CD3
12
12
12
12
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
10U_0603_10V6M
10U_0603_10V6M
12
@
CD17
CD7
CD8
12
+
1U_0201_6.3V6M
1U_0201_6.3V6M
1
CD76
2
1U_0201_6.3V6M
1
1
1
CD77
CD78
2
2
2
10U_0603_10V6M
1U_0201_6.3V6M
10U_0603_10V6M
1
1
CD21
CD20
CD79
2
2
MLCC downsize 4/18
+1.2V_MEM
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
CD108
CD109
2
2
C C
+0.6V_DDR_VTT
10U_0603_10V6M
CD22
12
B B
1
1
CD110
2
2
MLCC downsize 4/18
1U_0201_6.3V6M
1
CD80
2
1U_0201_6.3V6M
CD111
Layout Note:
Place near
JDIMM1.258
1
2
DIMM Select
SA01SA1
0
DIMM1
DIMM2
1
0
DIMM3
1
DIMM4
A A
1U_0201_6.3V6M
1
CD64
2
1U_0201_6.3V6M
1
CD81
2
SA2
0
0
1
1U_0201_6.3V6M
1
1
CD65
CD66
2
2
MLCC downsize 4/18
1U_0201_6.3V6M
1U_0201_6.3V6M
1
CD82
CD83
2
12
@
0_0402_5%
12
0
0
0
0
1U_0201_6.3V6M
1
2
RD4
@
RD5
0_0402_5%
CD67
12
12
1
2
@
0_0402_5%
1U_0201_6.3V6M
CD68
+DDR_VREF_A_CA
+3.3V_RUN+3.3V_RUN+3.3V_RUN
RD6
@
RD7
0_0402_5%
1
2
12
12
1U_0201_6.3V6M
CD69
0.1U_0402_10V6K
1
2
RD8
@
0_0402_5%
DIMM1_SA0
DIMM1_SA1
DIMM1_SA2
@
RD9
0_0402_5%
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1
CD71
+3.3V_RUN
12
1
2
CD72
2
@
RD10
0_0603_5%
2.2U_0402_6.3V6M
CD27
1
CD73
2
+3.3V_RUN_DIMM1
0.1U_0201_10V6K
CD28
1
2
1
1
CD70
2
2
2.2U_0402_6.3V6M
@
1
CD26
CD25
2
1U_0201_6.3V6M
1
1
CD74
CD75
2
2
DDR_A_CKE0<7>
DDR_A_BG1<7>
DDR_A_BG0<7>
DDR_A_CLK0<7>
DDR_A_CLK#0<7>
DDR_A_PARITY<7>
DDR_A_BA1<7>
DDR_A_CS#0<7>
DDR_A_MA14<7>
DDR_A_ODT0<7>
DDR_A_CS#1<7>
DDR_A_ODT1<7>
DDR_XDP_WAN_SMBCLK<8,14,21,41>
+2.5V_MEM
DDR_A_D1
DDR_A_D0
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D2
DDR_A_D13
DDR_A_D12
DDR_A_D15
DDR_A_D14
DDR_A_D35
DDR_A_D37
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D38
DDR_A_D34
DDR_A_D44
DDR_A_D45
DDR_A_D42
DDR_A_D46
DDR_A_CKE0
DDR_A_BG1
DDR_A_BG0
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA6
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_PARITY
DDR_A_BA1
DDR_A_CS#0
DDR_A_MA14
DDR_A_ODT0
DDR_A_CS#1
DDR_A_ODT1
T51PAD~D @
DDR_A_D30
DDR_A_D26
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D27
DDR_A_D29
DDR_A_D21
DDR_A_D17
DDR_A_D19
DDR_A_D22
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D63
DDR_A_D62
+3.3V_RUN_DIMM1
+1.2V_MEM
JDIMM1
1
VSS1
3
DQ5
5
VSS3
7
DQ1
9
VSS5
DQS0_c11DM0_n/DBI0_n
13
DQS0_t
15
VSS8
17
DQ7
19
VSS10
21
DQ3
23
VSS12
25
DQ13
27
VSS14
29
DQ9
31
VSS16
33
DM1_n/DBI_n
35
VSS17
37
DQ15
39
VSS19
41
DQ10
43
VSS21
45
DQ21
47
VSS23
49
DQ17
51
VSS25
DQS2_c53DM2_n/DBI2_n
55
DQS2_t
57
VSS28
59
DQ23
61
VSS30
63
DQ19
65
VSS32
67
DQ29
69
VSS34
71
DQ25
73
VSS36
DM3_n/DBI3_n75DQS3_t
77
VSS37
79
DQ30
81
VSS39
83
DQ26
85
VSS41
87
CB5/NC
89
VSS43
91
CB1/NC
93
VSS45
DQS8_c95DM8_n/DBI_n/NC
97
DQS8_t
99
VSS48
101
CB2/NC
103
VSS50
105
CB3/NC
107
VSS52
109
CKE0
111
VDD1
113
BG1
115
BG0
117
VDD3
119
A12
121
A9
123
VDD5
125
A8
127
A6
129
VDD7
131
A3
133
A1
135
VDD9
137
CK0_t
139
CK0_c
141
VDD11
143
PARITY
145
BA1
147
VDD13
149
CS0_n
151
WE_n/A14
153
VDD15
155
ODT0
157
CS1_n
159
VDD17
161
ODT1
163
VDD19
165
C1, CS3_n,NC
167
VSS53
169
DQ37
171
VSS55
173
DQ33
175
VSS57
177
DQS4_c
179
DQS4_t
181
VSS60
183
DQ38
185
VSS62
187
DQ34
189
VSS64
191
DQ44
193
VSS66
195
DQ40
197
VSS68
199
DM5_n/DBI5_n
201
VSS69
203
DQ46
205
VSS71
207
DQ42
209
VSS73
211
DQ52
213
VSS75
215
DQ49
217
VSS77
219
DQS6_c
221
DQS6_t
223
VSS80
225
DQ55
227
VSS82
229
DQ51
231
VSS84
233
DQ61
235
VSS86
237
DQ56
239
VSS88
241
DM7_n/DBI7_n
243
VSS89
245
DQ62
247
VSS91
249
DQ58
251
VSS93
253
SCL
255
VDDSPD
257
VPP1
259
VPP2
261
GND1
LCN_DAN05-Q0406-0103
CONN@
LINK DAN05-Q0406-0103 DONE
VSS11
VSS13
VSS15
DQS1_c
DQS1_t
VSS18
VSS20
VSS22
VSS24
VSS26
VSS27
VSS29
VSS31
VSS33
VSS35
DQS3_c
VSS38
VSS40
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
RESET_n
CKE1
VDD2
ACT_n
ALERT_n
VDD4
VDD6
VDD8
EVENT_n/NF
VDD10
CK1_t/NF
CK1_c/NF
VDD12
A10/AP
VDD14
RAS_n/A16
VDD16
CAS_n/A15
VDD18
C0/CS2_n/NC
VREFCA
VSS54
VSS56
VSS58
DM4_n/DBI4_n
VSS59
VSS61
VSS63
VSS65
VSS67
DQS5_c
DQS5_t
VSS70
VSS72
VSS74
VSS76
VSS78
DM6_n/DBI6_n
VSS79
VSS81
VSS83
VSS85
VSS87
DQS7_c
DQS7_t
VSS90
VSS92
VSS94
GND2
VSS2
DQ4
VSS4
DQ0
VSS6
VSS7
DQ6
VSS9
DQ2
DQ12
DQ8
DQ14
DQ11
DQ20
DQ16
DQ22
DQ18
DQ28
DQ24
DQ31
DQ27
A11
BA0
A13
SA2
DQ36
DQ32
DQ39
DQ35
DQ45
DQ41
DQ47
DQ43
DQ53
DQ48
DQ54
DQ50
DQ60
DQ57
DQ63
DQ59
SDA
SA0
VTT
SA1
+1.2V_MEM
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
A7
124
126
A5
128
A4
130
132
A2
134
136
138
140
142
144
A0
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
DDR_A_D4
DDR_A_D5
DDR_A_D3
DDR_A_D7
DDR_A_D9
DDR_A_D8
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D32
DDR_A_D36
DDR_A_D39
DDR_A_D33
DDR_A_D40
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D43
DDR_DRAMRST#_R
DDR_A_CKE1
DDR_A_ACT#
DDR_A_ALERT#
DDR_A_MA11
DDR_A_MA7
DDR_A_MA5
DDR_A_MA4
DDR_A_MA2
JDIMM1_EVENT#
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_MA0
DDR_A_MA10
DDR_A_BA0
DDR_A_MA16
DDR_A_MA15
DDR_A_MA13
DIMM1_SA2
DDR_A_D31
DDR_A_D25
DDR_A_D28
DDR_A_D24
DDR_A_D20
DDR_A_D16
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D23
DDR_A_D53
DDR_A_D52
DDR_A_D54
DDR_A_D55
DDR_A_D61
DDR_A_D60
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D58
DDR_A_D59
DIMM1_SA0
DIMM1_SA1
DDR_A_CKE1 <7>
DDR_A_ACT# <7>
DDR_A_ALERT# <7>
DDR_A_CLK1 <7>
DDR_A_CLK#1 <7>
DDR_A_BA0 <7>
+DDR_VREF_A_CA
T50 PAD~D@
+DDR_VREF_A_CA
DDR_XDP_WAN_SMBDAT <8,14,21,41>
+0.6V_DDR_VTT
1 2
@
RD12 0_0402_5%
1
CD29
@
0.1U_0402_25V6
2
JDIMM1_EVENT#
DDR_VTT_CTRL<7>
1 2
RD14 1K_0402_5%@
UD1
1
NC
VCC
2
A
3
GND
74AUP1G07GW_TSSOP5
Y
6/8 Change to SA00007WE00 DII
+1.2V_MEM
+1.2V_MEM
1K_0402_1%
12
RD15
RD17 2_0402_1%
1K_0402_1%
12
RD16
+1.2V_MEM
5
1 2
CD32@ 0.1U_0201_10V6K
4
RD19 100K_0402_5%
470_0402_1%
12
1 2
RD11
DDR_DRAMRST#
1 2
DDR_DRAMRST# <7>DDR_DRAMRST#_R<21>
+DDR_VREF_CA+DDR_VREF_A_CA
0.022U_0402_16V7K
CD31
12
24.9_0402_1%
12
RD18
H_THERMTRIP# <12,21,36>
0.6V_DDR_VTT_ON <52>
+3.3V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Compal Ele ctronics, Inc.
Compal Ele ctronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Ele ctronics, Inc.
DDR4
DDR4
DDR4
LA-F401P
LA-F401P
LA-F401P
1
20 69Friday, August 17, 2018
20 69Friday, August 17, 2018
20 69Friday, August 17, 2018
0.2
0.2
0.2
5
4
3
2
1
DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7 >
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..16]<7>
Layout Note:
10U_0603_10V6M
CD34
12
1U_0201_6.3V6M
1
CD85
2
+0.6V_DDR_VTT
SA01SA1
0
1
0
1
Place near JDIMM2
10U_0603_10V6M
10U_0603_10V6M
CD35
CD36
12
12
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
CD86
CD87
2
2
10U_0603_10V6M
CD54
1
12
2
SA2
0
0
0
0
0
0
1
10U_0603_10V6M
10U_0603_10V6M
CD37
12
12
1U_0201_6.3V6M
1U_0201_6.3V6M
1
CD88
CD89
2
Layout Note:
Place near
JDIMM2.258
MLCC downsize 4/18
1U_0201_6.3V6M
1U_0201_6.3V6M
1
CD104
CD105
2
12
RD20
@
0_0402_5%
12
@
RD21
0_0402_5%
10U_0603_10V6M
10U_0603_10V6M
CD40
CD38
CD39
12
12
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
CD90
CD91
2
2
MLCC downsize 4/18
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
CD106
CD107
2
2
12
@
RD22
0_0402_5%
12
RD23
@
0_0402_5%
+2.5V_MEM
330U_D3_2.5VY_R6M
12
@
CD49
+
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
1
CD100
CD101
2
2
2
CD102
10U_0603_10V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
1
1
1
CD52
CD53
CD103
2
2
2
MLCC downsize 4/18
1U_0201_6.3V6M
1U_0201_6.3V6M
1
2
RD24
@
0_0402_5%
DIMM2_SA0
DIMM2_SA1
DIMM2_SA2
@
RD25
0_0402_5%
CD93
1U_0201_6.3V6M
1
CD94
2
+DDR_VREF_B_CA
1U_0201_6.3V6M
1
CD92
2
+3.3V_RUN+3.3V_RUN+3 .3V_RUN
12
12
1U_0201_6.3V6M
1
CD95
2
0.1U_0402_10V6K
1
2
+3.3V_RUN
CD57
12
12
1U_0201_6.3V6M
1
CD96
2
2.2U_0402_6.3V6M
@
CD58
1
2
@
RD26
0_0603_5%
+3.3V_RUN_DIMM2
2.2U_0402_6.3V6M
1
CD59
2
1U_0201_6.3V6M
1
CD97
2
0.1U_0201_10V6K
CD60
1U_0201_6.3V6M
1
1
CD98
CD99
2
2
DDR_B_CKE0<7>
DDR_B_BG1<7>
DDR_B_BG0<7>
DDR_B_CLK0<7 >
DDR_B_CLK#0<7>
DDR_B_PARITY<7>
DDR_B_BA1<7>
DDR_B_CS#0<7 >
DDR_B_MA14<7>
DDR_B_ODT0<7>
DDR_B_CS#1<7>
DDR_B_ODT1<7>
DDR_XDP_WAN_SMBCLK<8,14,20,41>
+2.5V_MEM
D D
+1.2V_MEM
10U_0603_10V6M
CD33
12
+1.2V_MEM
1U_0201_6.3V6M
1
1
CD84
2
2
C C
B B
DIMM Select
DIMM1
DIMM2
DIMM3
*
DIMM4
A A
DDR_B_D1
DDR_B_D4
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D7
DDR_B_D6
DDR_B_D13
DDR_B_D12
DDR_B_D14
DDR_B_D15
DDR_B_D33
DDR_B_D36
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D39
DDR_B_D38
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_CKE0
DDR_B_BG1
DDR_B_BG0
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA6
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_PARITY
DDR_B_BA1
DDR_B_CS#0
DDR_B_MA14
DDR_B_ODT0
DDR_B_CS#1
DDR_B_ODT1
T55PAD~D @
DDR_B_D21
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D23
DDR_B_D22
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D52
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D55
DDR_B_D54
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
+3.3V_RUN_DIMM2
+1.2V_MEM
JDIMM2
1
VSS1
3
DQ5
5
VSS3
7
DQ1
9
VSS5
DQS0_c11DM0_n/DBI0_n
13
DQS0_t
15
VSS8
17
DQ7
19
VSS10
21
DQ3
23
VSS12
25
DQ13
27
VSS14
29
DQ9
31
VSS16
33
DM1_n/DBI_n
35
VSS17
37
DQ15
39
VSS19
41
DQ10
43
VSS21
45
DQ21
47
VSS23
49
DQ17
51
VSS25
DQS2_c53DM2_n/DBI2_n
55
DQS2_t
57
VSS28
59
DQ23
61
VSS30
63
DQ19
65
VSS32
67
DQ29
69
VSS34
71
DQ25
73
VSS36
DM3_n/DBI3_n75DQS3_t
77
VSS37
79
DQ30
81
VSS39
83
DQ26
85
VSS41
87
CB5/NC
89
VSS43
91
CB1/NC
93
VSS45
DQS8_c95DM8_n/DBI_n/NC
97
DQS8_t
99
VSS48
101
CB2/NC
103
VSS50
105
CB3/NC
107
VSS52
109
CKE0
111
VDD1
113
BG1
115
BG0
117
VDD3
119
A12
121
A9
123
VDD5
125
A8
127
A6
129
VDD7
131
A3
133
A1
135
VDD9
137
CK0_t
139
CK0_c
141
VDD11
143
PARITY
145
BA1
147
VDD13
149
CS0_n
151
WE_n/A14
153
VDD15
155
ODT0
157
CS1_n
159
VDD17
161
ODT1
163
VDD19
165
C1, CS3_n,NC
167
VSS53
169
DQ37
171
VSS55
173
DQ33
175
VSS57
177
DQS4_c
179
DQS4_t
181
VSS60
183
DQ38
185
VSS62
187
DQ34
189
VSS64
191
DQ44
193
VSS66
195
DQ40
197
VSS68
199
DM5_n/DBI5_n
201
VSS69
203
DQ46
205
VSS71
207
DQ42
209
VSS73
211
DQ52
213
VSS75
215
DQ49
217
VSS77
219
DQS6_c
221
DQS6_t
223
VSS80
225
DQ55
227
VSS82
229
DQ51
231
VSS84
233
DQ61
235
VSS86
237
DQ56
239
VSS88
241
DM7_n/DBI7_n
243
VSS89
245
DQ62
247
VSS91
249
DQ58
251
VSS93
253
SCL
255
VDDSPD
257
VPP1
259
VPP2
261
GND1
LCN_DAN05-Q0406-0103
CONN@
VSS2
VSS4
VSS6
VSS7
VSS9
VSS11
DQ12
VSS13
VSS15
DQS1_c
DQS1_t
VSS18
DQ14
VSS20
DQ11
VSS22
DQ20
VSS24
DQ16
VSS26
VSS27
DQ22
VSS29
DQ18
VSS31
DQ28
VSS33
DQ24
VSS35
DQS3_c
VSS38
DQ31
VSS40
DQ27
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
RESET_n
CKE1
VDD2
ACT_n
ALERT_n
VDD4
VDD6
VDD8
EVENT_n/NF
VDD10
CK1_t/NF
CK1_c/NF
VDD12
A10/AP
VDD14
RAS_n/A16
VDD16
CAS_n/A15
VDD18
C0/CS2_n/NC
VREFCA
VSS54
DQ36
VSS56
DQ32
VSS58
DM4_n/DBI4_n
VSS59
DQ39
VSS61
DQ35
VSS63
DQ45
VSS65
DQ41
VSS67
DQS5_c
DQS5_t
VSS70
DQ47
VSS72
DQ43
VSS74
DQ53
VSS76
DQ48
VSS78
DM6_n/DBI6_n
VSS79
DQ54
VSS81
DQ50
VSS83
DQ60
VSS85
DQ57
VSS87
DQS7_c
DQS7_t
VSS90
DQ63
VSS92
DQ59
VSS94
GND2
+1.2V_MEM
2
4
DQ4
6
8
DQ0
10
12
14
16
DQ6
18
20
DQ2
22
24
26
28
DQ8
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
A11
122
A7
124
126
A5
128
A4
130
132
A2
134
136
138
140
142
144
A0
146
148
150
BA0
152
154
156
158
A13
160
162
164
166
SA2
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
SDA
256
SA0
258
VTT
260
SA1
262
DDR_B_D5
DDR_B_D0
DDR_B_D2
DDR_B_D3
DDR_B_D9
DDR_B_D8
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D11
DDR_B_D10
DDR_B_D37
DDR_B_D32
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_DRAMRST#_R
DDR_B_CKE1
DDR_B_ACT#
DDR_B_ALERT#
DDR_B_MA11
DDR_B_MA7
DDR_B_MA5
DDR_B_MA4
DDR_B_MA2
JDIMM2_EVENT#
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_MA0
DDR_B_MA10
DDR_B_BA0
DDR_B_MA16
DDR_B_MA15
DDR_B_MA13
DIMM2_SA2
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D31
DDR_B_D30
DDR_B_D53
DDR_B_D48
DDR_B_D50
DDR_B_D51
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
DIMM2_SA0
DIMM2_SA1
DDR_B_CKE1 <7>
DDR_B_ACT# <7>
DDR_B_ALERT# <7>
DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>
DDR_B_BA0 <7>
+DDR_VREF_B_CA
T54 PAD~D@
+DDR_VREF_B_CA
DDR_XDP_WAN_SMBDAT <8 ,14,20,41>
+0.6V_DDR_VTT
JDIMM2_EVENT#
RD27 1K_0402_5%@
1
@
0.1U_0402_25V6
2
1 2
CD61
+DDR_VREF_B_CA
DDR_DRAMRST#_R <20>
+1.2V_MEM
1K_0402_1%
12
RD28
1 2
RD30 2_0402_1%
1K_0402_1%
12
RD29
H_THERMTRIP# <12,20,36>
0.022U_0402_16V7K
CD62
12
24.9_0402_1%
12
RD31
For DDR4
+DDR_VREF_B_DQ
LINK DAN05-Q0406-0103 DONE
DELL CONFIDENTIAL/PROPRIETARY
Compal Ele ctronics, Inc.
Compal Ele ctronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Ele ctronics, Inc.
DDR4
DDR4
DDR4
LA-F401P
LA-F401P
LA-F401P
1
21 69Friday, August 17, 2018
21 69Friday, August 17, 2018
21 69Friday, August 17, 2018
0.2
0.2
0.2
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