Dell Latitude 5480,Latitude 5488 Schematics

A

COMPAL CONFIDENTIAL

B

C

D

E

1 1

MODEL NAME :CDM70
PCB NO : LA-E082P
BOM P/N :

BR14 KBL-U DSC

Kabylake U

2 2

@ : Nopop Component

EMC@ : EMI, ESD and RF Component

CXDP@ : XDP Component

CONN@ : Connector Component

3 3

2016-11-07

REV : 1.0 (A00)

MB PCB

Part Number

DAA000CR000

Description

PCB 1SD LA-E082P REV0 MB DSC 1

Layout Dell logo

4 4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

COPYRIGHT 2015

ALL RIGHT RESERVED
REV:X00
PWB: DKJP1

T

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

A

B

PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

C

D

itle

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-E082P

LA-E082P

LA-E082P

1 75Monday, December 12, 2016

1 75Monday, December 12, 2016

1 75Monday, December 12, 2016

E

1.0

1.0

1.0

A

B

C

D

E

Breckenridge 14 DSC Block Diagram

Memory BUS (DDR4)

USB

2133 MHz
Up

to 2x8GB Modules

USB2.0[1]

USB POWER SHARE

HD Audio I/F

SATA/PCIE REPEATER

PS8558x2

SATA/PCIE MUX

SS3415

HD3

SLGC55544BVTR

USB3 Repeater

713B

PS8

dGPU
23X

23

E

DP CONN

HDMI 1.4
CON

N

DP TO VGA
RTD2166

M.2,3042 Key B

WWAN/LTE

USB3.0[2]

E 48~52

P29

P23

P24

P32

USB2.0[4]

P34

P34

2GB
DDR3L

PAGE 53~54 PAG

VGA
CONN

P24

PCIE[9]

Intel Jacksonville

WGI219LM

Transformer

RJ45

P33

P33

P33

1 1

2 2

PCIE[1]

Card reader
RTS5242

SD4.0

3 3

PCIE[5][6][7][ 8]

2-Lane eDP1.3

SW2_DP1

To Type C

SW2_DP2

To M2 WiGig card

SW2_DP3

To VGA

PCIE[4]

M.2,3030 Key A

WLAN+BT/WIGIG

SW2_DP2

Expander IO
IT8

DP DeMUX

PS8348B

PCIE[3]

P32

USB2.0[7]

010F N

P35

DDI[1]

DDI[2]

P22

INTEL

KABYLAKE_U MCP

PAGE 6~19

SPI

SATA[2] /PCIE[12][1 1]

W25Q128FVSI Q

P8

P8

reserve

P37

P45

35

P

ESPI

SMSC KBC
MEC5105

P34-3 5

128M 4K sector

W25Q128FVSI Q

128M 4K sector

TPM

2.0

ATTPM20P-G1MA1-ABF

KB/TP CONN

FAN CONN

Reverse Type

DDR4-SO-DIMM X2

BAN

P20~21

P43

P42

HDA Codec
ALC3246

P38

P39

K 0, 1, 2, 3

USB2.0[8]

USB2.0[5]

USB2.0[1]_PS

USB3.0USB3.0[1]

USB2.0[2]

USB3.0[3]

USB2.0[3]

USB3.0[4]

P33

LCD

Touch

P29

Camera

P29

USB3.0 Conn
PS(

Ext Port 1)

P43

USB3.0 Conn
(Ext Port 2)

USB3.0 Conn
(Ext Port 3)

INT.Speaker

Universal Jack

Dig.

MIC

P44

P44

P33

P33

P29

Trough eDP Cable

Trough eDP Cable

LID SWITCH

USH CONN

P47

P38

Non-AR Type C

P41

USB2.0[10]

M.2 2280

SSD Conn

P39

P40

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

DP1.2 4 lanes

TX/RX

USB 3.0 + AM
Type C CONN.

4 4

USB

CC

Vbus

2.0

HS Redriver Switch
TUSB546

P25

GPIO

PD Solut i on
TPS65982D

P26-2 7P28

SW2_DP1

USB3.0[6]

SMBUS

USB2.0[9]

Smart Card

TDA8034HN

RFID/NFC

Fingerprint
CONN

SPI

SPI

5V VR

Charger

A

B

C

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

E SECRET AND OTHER PR OPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

TRAD
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

SATA HDD

Conn

USH TPM1.2

M58102

BC

USH

board

CPU&PCH XDP Port

AUTOMATIC POWER
SWITCH(APS)

Free Fall sensor

Interface

DC/DC

POWER ON/OFF

SW & LED

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Block diagram

Block diagram

Block diagram

LA-E082P

LA-E082P

LA-E082P

E

2 75Monday, December 1 2, 2016

2 75Monday, December 1 2, 2016

2 75Monday, December 1 2, 2016

P14

P11

P41

P47

P46

1.0

1.0

1.0

5

POWER STATES

Signal

State

S0 (Full ON) / M0

S3 (Suspend to RAM) / M3 LOW

D D

S4 (Suspend to DISK) / M3

S5 (SOFT OFF) / M3

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

SLP
S3#

HIGH

LOW

LOW

LOW LOW LOW

OW LOW LOW LOW

L

SLP

SLP

S5#

S4#

HIGH HIGH

HIGH HIGH

HIGH HIGH

LOW

LOW

LOW

HIGH HIGH

HIGH

ALWAYS

SLP

PLANE

A#

HIGH

ON

HIGH

ON ON ON

ON ON

HIGH

ON ON

ON ON

LOW

ON

ON

PM TABLE

+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW

power

C C

State

S0

S3

S5 S4/AC

S5 S4/AC doesn't exist

plane

+3.3V_ALW_PCH +1.2V_MEM

+RTC_CELL

1.8V_PRIM

+
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT

ON ON ON

ON

ON

+3.3V_CV2

+2.5V_MEM
+1.0V_VCCST

ON

OFF

OFFOFF

+5V_RUN

+3.3V_RUN

+0.6V_DDR_VTT

1.8V_RUN

+
+VCC_CORE

+VCC_GT

+VCC_SA
+1.0VS_VCCIO

4

M
PLANE

ON

OFF OFF OFF

OFF OFF OFF OFF

OFF OFF OFF OFF

OFF

OFF

OFF

RUN

SUS

PLANE

PLANE

ON ON ON

OFF

OFF

OFF

OFF

OFFLOW

CLOCKS

OFF

OF

F

OFF

USB3.0

USB3.0-1

USB3.0-2

USB3.0-3

USB3.0-4

U

SB3.0-5

USB3.0-6

SSIC

SSIC

3

PCIE

PCIE-1

PCIE-2

PCIE-3

PCIE-4

PCIE-5

PCIE-6

PCIE-7

PCIE-8

PCIE-9

PCIE-10

PCIE-11

PCIE-12

SATA

SATA-0

TA-1

SA

SATA-1*

SATA-2

ESTINATION

J

USB1-->Right

M.2 3042(LTE)

JUSB2-->Lef t

JUSB3-->Rear Lef t

Card Reader

Type-C Port

M.2 3030(WLAN)

M.2 3030(WIGIG)

Discrete Graphics x4

LOM

NA

NA

SATA HDD

M.2 2280 SSD

PCIex2 or SATA)

(

2

USB PORT#D

For Breckenridge14/15 DSC

DESTINATION

1

2

3

4

5

6

7

8

9

10

JUSB1-->Right

JU

SB2-->Lef t

JUSB3-->Rear Lef t

M

2 3042(WWAN)

Camera

NA

M.2 3030(BT)

Touch Screen

Type-C Port

USH

1

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

T

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S E XPRESS WRITTEN CONSENT.

5

4

3

2

Title

ize Document Number Re v

Size Document Number Re v

Size Document Number Re v

S

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-E082P

LA-E082P

LA-E082P

1

3 75Monday, December 12, 2016

3 75Monday, December 12, 2016

3 75Monday, December 12, 2016

1.0

1.0

1.0

5

Barrel
ADAPTER

D D

CHARGER
ISL88

738

(PU801)

Type-C
ADAPTER

+PWR_SRC

BATTERY

C C

SY82

10A

(PU200)

SYX198D

(PU301)

SY82

88C

(PU102)

SYX196D

(PU800)

RT8813A

(PU701)

88B

SY82

(PU100)

4

IO_SLP_S4#

S

0.6V_DDR_VTT_ON

SIO_

SLP_SUS#

ALWO

DGPU_PWROK
GPU_GC6_FB_EN

3V3_MAIN_EN

ALWON

N

+1.2V_MEM

+0.6V_DDR_VTT

+1.0V_PRIM

+5V_ALW

+5V_ALW2

+1.35V_MEM_GFX

+GPU_CORE

+3.3V_RTC_LDO

+3.3V_ALW2

+3.3V_ALW

TPS22961

(UZ26)

3

SIO_SLP_SUS#
SIO_SLP_S4#

TPS62134C

(PU401)

TPS62134D

(PU402)

EM5209

(UZ4)

55544C

SLGC

(UI3)

SY62

88

(UI1)

SY6288

(UI2)

+VCC_SFR_OC

RUN_ ON

SIO_SLP_SUS#

RUN_ ON

USB_PW R_SHR_ EN#

USB_PWR_EN1#

USB_PWR_EN2#

2

TPS22961

(UZ19)

TPS22961

(UZ21)

EM5

(UV15)

+1.0VS_VCCIO

+1.0V_PRIM_CORE

+5V_RUN

+5V_USB_CHG_PWR

+USB_EX2_PWR

+USB_EX3_PWR

209VF

RUN_ ON

SLP_S0#

SIO_

SIO_SLP_S4#

3V3_MAIN_EN

LP2301

(QV8)

EM5209

(@UZ5)

+1.0V_VCCSTG

+1.0V

_VCCST

+1.0V_PEX_VDD

3.3V_TS_EN

AUD_PW R_EN

1

CPU PWR

PCH PWR

GT3 PWR

Peripheral Device PWR

TYPE-C Power

GPU PWR

+5V_TSP

+5V_RUN_AUDIO

SIO_SLP_SUS#

02KTTR

AP34

(PU501)

857

ISL95857

(PU602)

IMVP_VR_ON

B B

ISL95

(PU604)

IMVP_VR_ON

+VCC_GT+VCC_SA

ISL95857

(PU603)

IMVP_VR_ON

+VCC_CORE

AO6405

(QV1)

EN_IN VPWR

+BL_PWR_SRC

EM5209

(UZ2)

EM5209

(UZ3)

EM5209

(UZ4)

G524B1T11U
(UV24)

SIO_SLP_L AN#

AUX_EN_WOW L

@SIO_SLP_WLAN#

SIO_SLP_SUS#

@PCH_ALW _ON

RUN_ ON

3.3V_W WAN_EN

ENVCC_PCH

+3.3V_LAN

+3.3V_WLAN

+3.3V_ALW_PCH

+3.3V_RUN

+3.3V_WWAN

LCDVDD

+

TYPE-C

+TBTA_VBUS(5V~20V)

TPS22967

(UZ18)

AP7175SP

A A

AP2204

(UT8)

5

ALW

+5V_

+5V_TBT_VBUS

AP2112K

(UT7)

+3.3V_TBT_SX

4

(PU503)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S E XPRESS WRITTEN CONSENT.

3

CV2_ON

SIO_SLP_S4#

+3.3V_CV2

+2.5V_MEM

for DDR4

USH/

2

AOZ13

36

(UZ8)

LP2301A

(QZ1)

EM5209

(@UZ5)

LP2301A

(QV1)

EM5209VF

(UV15)

B

ON

RUN_

3.3V_CAM_EN#

AUD_PW R_EN

DGPU_PWR_EN

3V3_MAIN_EN

+3.3V_CAM

+3.3V_RUN_AUDIO

+3.3V_GFX_AON

_RUN_GFX

+3.3V

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Power rails

Power rails

Power rails

LA-E082P

LA-E082P

LA-E082P

1

4 75Monday, December 12, 2016

4 75Monday, December 12, 2016

4 75Monday, December 12, 2016

1.0

1.0

1.0

5

4

3

2

1

PD &
FW reflash

2.2K

2.2K

+3.3V_RUN

202
200

202

200

DIMMA

DIMMB

53
51

1
4

XDP

LNG2DMTR

1

K

+3.3V_ALW_PCH

2.2K

2.2K

@2.2K

@2.2K

2.2K

2.2K

+3.3V_ALW_PCH

DMN66D0LDW-7
DMN66D0LDW-7

+3.3V_TP

+3.3V_ALW

+3.3V_ALW

DMN66D0LDW-7
DMN66D0LDW-7

28
31

LOM

UPD1_SMBC LK_Q
UPD1_SMBDAT_Q

DDR_XDP_WAN_SMBCLK
D

DR_XDP_ WAN_SMBDAT

2.2K

2.2K

2.2K

2.2K

9

TP

8

+3.3V_CV2

M9

USH

L9

USH/B

+3.3V_TBT_FLASH

B5
A5

R
R8

D D

SKL-U

R9

W3

SML1_SMBDATA

SML1_SMBCLK

03

W2

02
02

01
01

00 D7
00

V3

E11 D8

0

3

C C

KBC

04
04

MEM_SMBCLK

7

MEM_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

1K

+3.3V_ALW_PCH

DAT_TP_SIO_I2C_CLK
CLK_TP_SIO_I2C_DAT

USH_SMBCLK

USH_SMBDAT

UPD1_SMBCLK
UPD1_SMBDAT

C12
E

B3
E5

E7

C3
B4

1

K

10

1K

499

499

MEC 5105

F7

05

B6

05

A

12

B B

A A

5

06

N10

06

07

7

0

08

09

09

10
10

EXPANDER_GPU_SMCLK

M4

EXPANDER_GPU_SMDATA

M7

C508
C8

F6

E9

PBAT_CHARGER_SMBCLK

N2

3

M

PBAT_CHARGER_SMBDAT

2.2K

2.2K

2.2K
.2K

2

+3.3V_ALW

+3.3V_ALW

100 ohm

100 ohm

MN66D0LDW-7

D
DMN66D0LDW-7

1.8K

1.8K

+3.3V_RUN_GFX

GPU

EXPANDER

Charger

7

BATTERY

6

CONN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S E XPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-E082P

LA-E082P

LA-E082P

1

5 75Monday, December 12, 2016

5 75Monday, December 12, 2016

5 75Monday, December 12, 2016

1.0

1.0

1.0

5

4

3

2

1

For 2LANE EDP,BR/SB12

+3.3V_RUN

CPU_DP1_CTRL_CLK

RC175 2.2K_0402_5%
RC178 2.2K_0402_5%

D D

RC176 2.2K_0402_5%
RC177 2.2K_0402_5%

C C

B B

12

CPU_DP1_CTRL_DATA

12

CPU_DP2_CTRL_CLK

12

CPU_DP2_CTRL_DATA

12

HDMI

PS8

338(AR)/

PS8348(NON AR)

+1.0VS_VCCIO

CPU_DP1_N0<23>
CPU_DP1_P0<23>
CPU_DP1_N1<23>
CPU_DP1_P1<23>
CPU_DP1_N2<23>
CPU_DP1_P2<23>
CPU_DP1_N3<23>
CPU_DP1_P3<23>

CPU_DP2_N0<22>
CPU_DP2_P0<22>
CPU_DP2_N1<22>
CPU_DP2_P1<22>
CPU_DP2_N2<22>
CPU_DP2_P2<22>
CPU_DP2_N3<22>
CPU_DP2_P3<22>

12

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

GPP_E23

EDP_COMP

CPU_DP1_CTRL_CLK<23>

CPU_DP1_CTRL_DATA<23>

CPU_DP2_CTRL_CLK<22>

CPU_DP2_CTRL_DATA<22>

@

T120

PAD~D

RC2 24.9_0402_1%

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils , Spacing=25mil,
Ma

x length=100 mils.

UC1A

CPU@

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL

-U_BGA1356

SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0

UC1I

CPU@

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL

-U_BGA1356

SKL-U

DDI

DISPLAY SIDEBANDS

SKL_U LT

EDP

1 OF 20

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

EDP_DISP_UTIL

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

DDI1_AUXN

DDI1_AUXP

DDI2_AUXN

DDI2_AUXP

DDI3_AUXN

DDI3_AUXP

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

CPU_DP1_AUXN

G50

CPU_DP1_AUXP

F50
E48
F48

CPU_DP3_AUXN

G46

CPU_DP3_AUXP

F46
L9

L7
L6
N9
L10

R12
R11
U13

CSI2_COMP
TBT_FORCE_PWR

EMMC_RCOMP

RC4 200_0402_1%

EDP_TXN0 <29>
EDP_TXP0 <29>
EDP_TXN1 <29>
EDP_TXP1 <29>

EDP_AUXN <29>
EDP_AUXP <29>

PAD~D
PAD~D

CPU_DP2_AUXN <22>

CPU_DP2_AUXP <22>

PAD~D
PAD~D

CPU_DP1_HPD <23>
CPU_DP2_HPD <22>

EDP_HPD <29>

PANEL_BKLEN <29>
EDP_BIA_PWM <29>
ENVDD_PCH <29,34>

1 2

RC3 100_0402_1%

1 2

PAD~D

@

T19

@

T281

@

T282

@

T1

@

T2

EDP_HPD

1 2

RC1 100K_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (1/14)

CPU (1/14)

CPU (1/14)

LA-E082P

LA-E082P

LA-E082P

6 75Monday, December 12, 2016

6 75Monday, December 12, 2016

6 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For DDR4

DDR_A_DQS#[0..7]<20>

2 OF 20

DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>

DDR_A_MA[0..16]<20>

DDR_A_CLK#0

AU53

DDR_A_CLK0

AT53

DDR_A_CLK#1

AU55

DDR_A_CLK1

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56

DDR_A_CKE2

AW56

DDR_A_CKE3

AY56

DDR_A_CS#0

AU45

DDR_A_CS#1

AU43

DDR_A_ODT0

AT45

DDR_A_ODT1 DDR_B_ODT0

AT43

DDR_A_MA5

BA51

DDR_A_MA9

BB54

DDR_A_MA6

BA52

DDR_A_MA8

AY52

DDR_A_MA7

AW52

DDR_A_BG0

AY55

DDR_A_MA12

AW54

DDR_A_MA11

BA54

DDR_A_ACT#

BA55

DDR_A_BG1

AY54

DDR_A_MA13

AU46

DDR_A_MA15

AU48

DDR_A_MA14 DDR_B_MA15

AT46

DDR_A_MA16

AU50

DDR_A_BA0

AU52

DDR_A_MA2

AY51

DDR_A_BA1

AT48

DDR_A_MA10

AT50

DDR_A_MA1

BB50

DDR_A_MA0

AY50

DDR_A_MA3

BA50

DDR_A_MA4

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#4

BA64

DDR_A_DQS#5

AY60

DDR_A_DQS5

BA60

DDR_B_DQS#0

BA38

DDR_B_DQS0

AY38

DDR_B_DQS#1

AY34

DDR_B_DQS1

BA34

DDR_B_DQS#4

BA30

DDR_B_DQS4

AY30

DDR_B_DQS#5

AY26

DDR_B_DQS5

BA26

DDR_A_ALERT#

AW50

DDR_A_PARITY

AT52
AY67

+DDR_VREF_A_DQ

AY68
BA67

AW67

DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>

DDR_A_CKE0 <20>
DDR_A_CKE1 <20>

@

T3

PAD~D

@

T4

PAD~D

DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>

DDR_A_BG0 <20>

DDR_A_ACT# <20>
DDR_A_BG1 <20>

DDR_A_BA0 <20>
DDR_A_BA1 <20>

DDR0_PAR,DDR0_ALERT# for DDR4

DDR_A_ALERT# <20>

+DDR_VREF_CA

@

T132

PAD~D

+DDR_VREF_B_DQ

DDR_VTT_CTRL <20>

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26

DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]
DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SK

L-U_BGA1356

CPU@

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DRAM_RESET#
DDR_RCOMP[0]

DDR CH - B

DDR_RCOMP[1]
DDR_RCOMP[2]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR4, Ballout for side by side(Non-Interleave)

D D

UC1B

CPU@

DDR_A_D0

AL71

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42

C C

B B

DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SK

L-U_BGA1356

SKL-U

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

DDR0_ODT[1]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

DDR0_ALERT#

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_ALERT#

DDR1_PAR

3 OF 20

DDR_B_DQS#[0..7]<21>

DDR_B_D[0..63]<21>
DDR_B_DQS[0..7]<21>

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70

AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

DDR_B_MA[0..16]<21>

DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1

DDR_B_ODT1
DDR_B_MA5

DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
DDR_B_ACT#
DDR_B_BG1

DDR_B_MA13
DDR_B_MA14

DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3

DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7

DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDR_B_CLK#0 <21>
DDR_B_CLK#1 <21>
DDR_B_CLK0 <21>
DDR_B_CLK1 <21>

DDR_B_CKE0 <21>
DDR_B_CKE1 <21>

@

T5

PAD~D

@

T6

PAD~D

DDR_B_CS#0 <21>
DDR_B_CS#1 <21>
DDR_B_ODT0 <21>
DDR_B_ODT1 <21>

DDR_B_BG0 <21>

DDR_B_ACT# <21>
DDR_B_BG1 <21>

DDR_B_BA0 <21>
DDR_B_BA1 <21>

D

DR1_PAR,DDR1_ALERT# for DDR4

DDR_B_ALERT# <21>DDR_A_PARITY <20>
DDR_B_PARITY <21>
DDR_DRAMRST# <20>

DDR4 COMPENSATION SIGNALS

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

A A

1 2

RC5 121_0402_1%

1 2

RC6 80.6_0402_1%

1 2

RC7 100_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (2/14)

CPU (2/14)

CPU (2/14)

LA-E082P

LA-E082P

LA-E082P

7 75Monday, December 12, 2016

7 75Monday, December 12, 2016

7 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

SPI_MOSI= SPI_IO0
SP

I_MISO= SPI_IO1

PCH EDS R0.7 p.235~236

PCH_SPI_CLK
PCH_SPI_D1

1 2

PCH_SPI_DO_XDP<14>

D D

PCH_SPI_DO2_XDP<14>

RC10 1K_0402_1%CXDP@

1 2

RC11 1K_0402_1%CXDP@

+3.3V_RUN

+3.3V_1.8V_ESPI

PCH_SPI_CS#2<36>

PCH_CL_CLK1<32>
PCH_CL_DATA1<32>
PCH_CL_RST1#<32>

RC13 10K_0402_5%LPC@

SIO_RCIN#<34>

ESPI_ALERT#<34>

RC21 8.2K_0402_1%

PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2

12

12

AW3
AW2

AU4
AU3
AU2
AU1

AW13

AY11

AV2
AV3

M2
M3

J4
V1
V2

M1

G3
G2
G1

4

UC1E

CPU@

SPI - FLASH

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#
GPP_A6/SERIRQ

SKL

-U_BGA1356

SKL-U

SMBUS, SMLINK

LPC

GPP_A14/SUS_STAT#/ESPI_RESET#

3

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

5 OF 20

R7
R8
R10

R9
W2
W1

W3
V3
AM7

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#

SML0_SMBCLK
SML0_SMBDATA
GPP_C5

SML1_SMBCLK
SML1_SMBDATA
GPP_B23

ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R

ESPI_CLK
PCI_CLK_LPC1

SML0_SMBCLK <30>
SML0_SMBDATA <30>

SML1_SMBCLK <34>
SML1_SMBDATA <34>

1 2

RC366 15_0402_5%

1 2

RC367 15_0402_5%

1 2

RC368 15_0402_5%

1 2

RC369 15_0402_5%

ESPI_CS# <34,35>
ESPI_RESET# <34>

1 2

RC16EMI@ 15_0402_5%

1 2

CLKRUN# <34>

RC22@ 22_0402_5%

2

MEM_SMBCLK

MEM_SMBDATA

ESPI_IO0 <34,35>
ESPI_IO1 <34,35>
ESPI_IO2 <34,35>
ESPI_IO3 <34,35>

+3.3V_RUN

6

5

DMN65D8LDW-7_SOT363-6

3 4

QC2B

DMN65D8LDW-7_SOT363-6

ESPI_CLK_5105 <34,35>

Fo

2

1

DDR_XDP_WAN_SMBCLK <14,20,21,41>

QC2A

DDR_XDP_WAN_SMBDAT <14,20,21,41>

DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK

MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA

1

r BR/SB

1 2

RC318 2.2K_0402_5%

1 2

RC319 2.2K_0402_5%

1 2

RC12 1K_0402_5%

1 2

RC14 1K_0402_5%

1 2

RC15 1K_0402_5%

1 2

RC17 1K_0402_5%

1 2

RC347 499_0402_1%

1 2

RC348 499_0402_1%

+3.3V_RUN

+3.3V_ALW_PCH

C C

SOFTWARE TAA

PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R

33_0402_5%

@EMI@

12

RC28

33P_0402_50V8J

@EMI@

12

CC7

B B

A A

33_0402_5%

@EMI@

12

RC29

33P_0402_50V8J

@EMI@

12

CC8

+3.3V_SPI

RC31 1K_0402_5%@

RC316 1K_0402_5%@

03/02:follow Intel MOW_2015WW06

PCH_SPI_D2_R1

12

PCH_SPI_D3_R1

12

PCH_SPI_D1_R1<36>

PCH_SPI_D0_R1<36>

PCH_SPI_CLK_R1<36>

12

PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R

@

1 2

RC37 0_0402_5%

1 2

RC39 33_0402_5%

PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R

1

/CS

2

IO1

3

IO2

4

GND

W25Q128FVSIQ_SO8

PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1

PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1

8Mb Flash ROM

UC5

VCC
CLK

IO3
IO0

8
7
6
5

128Mb Flash ROM

UC6

PCH_SPI_CS#1_R1
PCH_SPI_D2_R1

RC42 0_0402_5%@
RC43 33_0402_5%@

1 2
1 2

PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R

@

1

/CS

2

IO1

3

IO2

4

GND

W25Q128FVSIQ_SO8

VCC
CLK

8
7

IO3

6
5

IO0

1 8
2 7
3 6
4 5

1 2

RC407 33_0402_5%@

1 2

RC408 33_0402_5%@

1 2

RC409 33_0402_5%@

1 2

RC410 33_0402_5%@

+3.3V_SPI

PCH_SPI_D3_0_R
PCH_SPI_D0_0_R

+3.3V_SPI

PCH_SPI_D3_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R

RPC1

CC9

1 2

0.1U_0201_10V6K

CC10

@

1 2

0.1U_0201_10V6K

PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R

PCH_SPI_D3_1_RPCH_SPI_D3_R1
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R

+3.3V_SPI

ESPI_CLK_5105

SML0_SMBCLK

SML1_SMBCLK

RC32 0_0402_5%

@

+3.3V_ALW_PCH

12
12
12
12
12
12
12

@

RC330_0402_5%

@

RC340_0402_5%

@

RC350_0402_5%

@

RC360_0402_5%

@

RC380_0402_5%

@

RC400_0402_5%

12

RC410_0402_5%

PCH_SPI_CS#1_R1

PCH_SPI_CS#1

PCH_SPI_D0_R1

PCH_SPI_D0

PCH_SPI_D1_R1

PCH_SPI_D1

PCH_SPI_CLK_R1

PCH_SPI_CLK

PCH_SPI_CS#0_R1

PCH_SPI_CS#0

PCH_SPI_D2_R1

PCH_SPI_D2

PCH_SPI_D3_R1

PCH_SPI_D3

@

RF Request

1 2

CC316@RF@ 33P_0402_50V8J

1 2

CC318@RF@ 33P_0402_50V8J

1 2

CC319@RF@

CC320@RF@ 33P_0402_50V8J

Place close CPU side

JSPI1

22

GND2

21

GND1

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

E-T_6705K-Y20N-00L

CONN@

SML0_SMBCLK
SML0_SMBDATA

CLKRUN#

PCH_SMB_ALERT#

TLS C ONFIDENTIALITY

HIGH
LOW(DEFAULT)

WEAK INTERNAL 20K PD

GPP_C5

EC interface

HIGH

W(DEFAULT)

LO

WEAK INTERNAL 20k PD

GPP_B23

RC317 150K_0402_5%

EXI BOOT STALL BYPASS

HIGH
LOW(DEFAULT)

WEAK INTERNAL PD

1 2

RC19 499_0402_1%@

1 2

RC20 499_0402_1%@

1 2

RC27 8.2K_0402_5%LPC@

1 2

RC23 2.2K_0402_5%

ENABLE
DISAB LE

1 2

RC25 4.7K_0402_5%ESPI@

ESPI

LPC

1 2

ENABLED
DI

+3.3V_LAN

+3.3V_RUN

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_ALW_PCH

ABLE D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (3/14)

CPU (3/14)

CPU (3/14)

LA-E082P

LA-E082P

LA-E082P

8 75Monday, December 12, 2016

8 75Monday, December 12, 2016

8 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For BR DSC

UC1F

+3.3V_RUN

AN8
AP7
AP8
AR7

AM5
AN7
AP5
AN5

AB1
AB2

AB3
AD1

AD2
AD3
AD4

AH9

AH10
AH11

AH12
AF11

AF12

W4

U7
U6

U8
U9

Reserve

MEDIACARD_IRQ#<31>

HDD_FALL_INT<41>

SIO_EXT_SCI#<34>

I2C1_SDA_TP<45>
I2C1_SCK_TP<45>

+3.3V_RUN

10K_0402_5%

TPM_PIRQ#<36>

3.3V_TS_EN<29>

RC405 100K_0402_5%@

SBIOS_TX<35>

RC267@

HDD_FALL_INT

D D

C C

RC370 10K_0402_5%
RC282 100K_0402_5%

RC237 10K_0402_5%
RC402 49.9K_0402_1%@
RC403 49.9K_0402_1%@

+3.3V_ALW_PCH

RC283 10K_0402_5%
RC330 49.9K_0402_1%
RC331 49.9K_0402_1%

+3.3V_RUN

RC186 4.7K_0402_5%@

12
12

12
12
12

12
12
12

12

3.3V_TS_EN

SIO_EXT_SCI#

NRB_BIT

LPSS_UART2_RXD
LPSS_UART2_TXD

SIO_EXT_WAKE#
LPSS_UART2_RXD
LPSS_UART2_TXD

ONE_DIMM#
NRB_BIT
HDD_FALL_INT

BBS_BIT6
GPP_C8

12

LPSS_UART2_RXD
LPSS_UART2_TXD

CPU@

LPSS ISH

GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

SK

L-U_BGA1356

NO REBOOT STRAP

H

IGH

LOW(DEFAULT)

Internal 20k PD

B B

+3.3V_ALW_PCH

RC184 8.2K_0402_5%@

No REBOOT

REBOOT ENABLE

BBS_BIT6

12

1 2

10K_0402_5%

12

DIMM Detect

HIGH

OW

L

ONE_DIMM#

RC268

1 DIMM
2 DIMM

LPSS_UART2_TXD
LPSS_UART2_RXD

BOOT BIOS Dest i nat i on (Bi t 6)

HIGH
LOW(DEFAULT)

Internal 20k PD

LPC
S

PI

SKL-U

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

CONN@

JUART1

1

1

2

2

3

3

4

4

5

GND

6

GND

CVILU_CI1804M1VRA-NH

CI1804M1VRA-NH LINK DON

+3.3V_ALW_PCH

MEM_INTERLEAVED

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A12/BM_BUSY#/ISH_GP6

RC371

@

10K_0402_5%

1 2

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

6 OF 20

E

MEM_INTERLEAVED

P2
P3

AR_DET#

P4
P1

M4
N3

N1
N2

ISH_I2C2_SDA

AD11

ISH_I2C2_SCL

AD12

U1
U2
U3
U4

AC1

RTD3_CIO_PWR_EN

AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

DGPU_HOLD_RST# <48>
DGPU_PWR_EN <52>

ISH_I2C2_SDA <32>
ISH_I2C2_SCL <32>

9/24: Reserve for embedded locat i on ,r ef er I nt el PDG

ISH_UART0_RXD <32>

ISH_UART0_TXD <32>
ISH_UART0_RTS# <32>

ISH_UART0_CTS# <32>

SIO_EXT_WAKE# <34>

@

PAD~D

HDD_EN

CLKDET#

TPM_TYPE
LID_CL#_PCH

LCD_CBL_DET# <29>

HDD_EN <41>

@

T258

PAD~D

PAD~D

WWAN

T18

@

T268

GPP_A GROUP is +1.8V

+3.3V_ALW_PCH

RC400
10K_0402_5%

1 2

AR_DET#

WLAN

0. 9

Reserved

ISH_I2C2_SDA
ISH_I2C2_SCL

LCD_CBL_DET#
DGPU_PWR_EN

DGPU_PWR_EN

TPM_TYPE

1 2

RC363 1K_0402_5%

1 2

RC362 1K_0402_5%

1 2

RC287 100K_0402_5%

1 2

RC386 10K_0402_5%

1 2

RC385 10K_0402_5%@

1 2

RC349 100_0402_1%@

+1.8V_RUN

+3.3V_RUN

12

10K_0402_5%
RC372

A A

DIMM TYPE

HIGH

LOW

Interleave

Non-Interleave

12

10K_0402_5%
RC401

@

AR_DET#

H

IGH NON AR

LOW A

R

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (4/14)

CPU (4/14)

CPU (4/14)

LA-E082P

LA-E082P

LA-E082P

9 75Monday, December 12, 2016

9 75Monday, December 12, 2016

9 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For Non AR,Breckenridge 14/15 DSC

UC1H

CPU@

PCIE/US B3/SATA

D D

Card Reader RTS5242----->

Type-C Port ----->

M.2 3030(WLAN) --->

M.2 3030(WiGig) --->

PEG_CTX_C_GRX_N1
PEG_CTX_C_GRX_P1

Discrete Graphics--->

C C

/100/1G LAN --->

10

PEG_CTX_C_GRX_N2
PEG_CTX_C_GRX_P2

PEG_CTX_C_GRX_N3
PEG_CTX_C_GRX_P3

M2 2280 SSD --->

B B

PEG_CRX_GTX_P[0..3]<48>
PEG_CRX_GTX_N[0..3]<48>

PEG_CTX_C_GRX_P[0..3]<48>
PEG_CTX_C_GRX_N[0..3]<48>

PCIE_PRX_DTX_N1<31>
PCIE_PRX_DTX_P1<31>
PCIE_PTX_DRX_N1<31>
PCIE_PTX_DRX_P1<31>

USB3_PRX_DTX_N6<25>
USB3_PRX_DTX_P6<25>
USB3_PTX_DRX_N6<25>
USB3_PTX_DRX_P6<25>

PCIE_PRX_DTX_N3<32>
PCIE_PRX_DTX_P3<32>
PCIE_PTX_DRX_N3<32>
PCIE_PTX_DRX_P3<32>

PCIE_PRX_DTX_N4<32>
PCIE_PRX_DTX_P4<32>
PCIE_PTX_DRX_N4<32>
PCIE_PTX_DRX_P4<32>

1 2

CC34 0.22U_0402_16V7K

1 2

CC35 0.22U_0402_16V7K

1 2

CC36 0.22U_0402_16V7K

1 2

CC37 0.22U_0402_16V7K

1 2

CC38 0.22U_0402_16V7K

1 2

CC39 0.22U_0402_16V7K

1 2

CC40 0.22U_0402_16V7K

1 2

CC41 0.22U_0402_16V7K

PCIE_PRX_DTX_N9<30>
PCIE_PRX_DTX_P9<30>

1 2

RC45 100_0402_1%

CPU_XDP_PRDY#<14>

CPU_XDP_PREQ#<14>

PCIE_PRX_DTX_N11<38>
PCIE_PRX_DTX_P11<38>
PCIE_PTX_DRX_N11<38>
PCIE_PTX_DRX_P11<38>
PCIE_PRX_DTX_N12<38>
PCIE_PRX_DTX_P12<38>
PCIE_PTX_DRX_N12<38>
PCIE_PTX_DRX_P12<38>

PEG_CRX_GTX_P[0..3]

PEG_CRX_GTX_N[0..3]

PEG_CTX_C_GRX_P[0..3]
PEG_CTX_C_GRX_N[0..3]

PEG_CRX_GTX_N0
PEG_CRX_GTX_P0
PEG_CTX_GRX_N0PEG_CTX_C_GRX_N0
PEG_CTX_GRX_P0PEG_CTX_C_GRX_P0

PEG_CRX_GTX_N1
PEG_CRX_GTX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1

PEG_CRX_GTX_N2
PEG_CRX_GTX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2

PEG_CRX_GTX_N3
PEG_CRX_GTX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3

PCIE_RCOMPN
PCIE_RCOMPP

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN
PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL

-U_BGA1356

SKL-U

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN
USB3_1_RXP

USB3_1_TXN
USB3_1_TXP

USB3_4_RXN
USB3_4_RXP

USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1

AH7
AH8

AG3

USB2_VBUSSENSE

AG4
A9

C9
D9

USB_OC3#

B9
J1

J2
J3

H2

SATAGP0

H3

SATAGP1
M2280_PCIE_SATA#

G4
H1

SATALED#

USB2_ID

USB3_PRX_DTX_N1 <42>
USB3_PRX_DTX_P1 <42>
USB3_PTX_DRX_N1 <42>

USB3_PTX_DRX_P1 <42>

USB3_PRX_DTX_N2 <32>
USB3_PRX_DTX_P2 <32>
USB3_PTX_DRX_N2 <32>

USB3_PTX_DRX_P2 <32>

USB3_PRX_DTX_N3 <44>
USB3_PRX_DTX_P3 <44>
USB3_PTX_DRX_N3 <44>

USB3_PTX_DRX_P3 <44>

USB3_PRX_DTX_N4 <44>
USB3_PRX_DTX_P4 <44>
USB3_PTX_DRX_N4 <44>

USB3_PTX_DRX_P4 <44>

USB20_N1 <43>
USB20_P1 <43>

USB20_N2 <44>
USB20_P2 <44>

USB20_N3 <44>
USB20_P3 <44>

USB20_N4 <32>
USB20_P4 <32>

USB20_N5 <29>
USB20_P5 <29>

USB20_N7 <32>
USB20_P7 <32>

USB20_N8 <29>
USB20_P8 <29>

USB20_N9 <26>
USB20_P9 <26>

USB20_N10 <37>
USB20_P10 <37>

USB2_ID <26>

1 2

RC338 1K_0402_5%

USB_OC0# <43>
USB_OC1# <44>
USB_OC2# <44>

Reserve

M2280_DEVSLP <40,41>

M2280_PCIE_SATA# <38,39>

SATALED# <32,40,46>

-----> Ext USB3 Port 1 Charge

-----> M.2 3042(LTE)

-----> Ext USB3 Port 2

-----> Ext USB3 Port 3

--

---> Ext USB Port 1 Charge(RIGHT)

-----> Ext USB Port 2(LEFT)

-----> Ext USB Port 3(REAR LEFT)

-----> M2 3042(WWAN)

-----> Camera

-----> M.2 3030(BT)

-----> LCD Touch

-----> Typce-C(Non AR)

USB2_ID

@

-----> USH

SATAGP1

RC337 0_0402_5%

RC416 1K_0402_5%

USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#

M2280_PCIE_SATA#
SATAGP0

SATALED#
SATAGP1

1 2

1 2

10K_8P4R_5%

1
2
3
4 5

4 5
3
2
1

10K_8P4R_5%

2

RPC3

RPC4

1K_0402_5%

+3.3V_ALW_PCH

8
7
6

6
7
8

+3.3V_RUN

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (5/14)

CPU (5/14)

CPU (5/14)

LA-E082P

LA-E082P

LA-E082P

10 75Monday, December 12, 2016

10 75Monday, December 12, 2016

10 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For BR DSC

1 2

RC417 3 3_0402_5%
1M_0402_1%

UC1J

CPU@

CLK_PCIE_N0<48>

D D

GPU--->

WLAN--->

WIGIG--->

M.2 SDD--->

N--->

LA

Card Reader --->

C C

B B

CLK_PCIE_P0<48>

CLKREQ_PCIE#0<48>

+3.3V_RUN

CLK_PCIE_N1<32>
CLK_PCIE_P1<32>

CLKREQ_PCIE#1<32>

+3.3V_RUN

CLK_PCIE_N2<32>
CLK_PCIE_P2<32>

CLKREQ_PCIE#2<32>

+3.3V_RUN

CLK_PCIE_N3<40>
CLK_PCIE_P3<40>

CLKREQ_PCIE#3<40>

+3.3V_RUN

CLK_PCIE_N4<30>
CLK_PCIE_P4<30>

CLKREQ_PCIE#4<30>

+3.3V_RUN

CLK_PCIE_N5<31>
CLK_PCIE_P5<31>

CLKREQ_PCIE#5<31>

+3.3V_RUN

+3.3V_LAN

+3.3V_ALW_DSW

+1.0V_VCCST

+3.3V_ALW_PCH

10/6 depop, prevent singal step.

H_CPUPW RGD VCCST_PWRGD

100P_0402_50V8J

12

CC300ESD@

RC215

POP
DE-POP

PCH_DPW ROK PCH_RS MRST#_AND

0.01UF_0402_25V7K

12

1

@

CC266

2

RC189 10K_0402_5%

RC47 10K _0402_5%

RC50 10K _0402_5%

RC59 10K _0402_5%

RC51 10K _0402_5%

RC190 10K_0402_5%

RL70 10K_0402_5%@

RC323 10 K_0402_5%

RC67 1K_0402_5%

RC71 1K_0402_5%

RC74 10K_0402_5%@

2

RC411 10K_040 2_5%@

@

T9

PAD~D

100P_0402_50V8J

12

CC301ESD@

ESD Request:place near CPU side

NO Support Deep sleep
Support Deep sleep

1 2

RC215 0_0402_5%@

100K_0402_1%

RC220

LAN_WAKE#

12

12

PCH_PCIE_ WAKE#

12

VCCST_PW RGD

12

ME_SUS_PWR_ACK

12

VCCST_PWRGD<14,34,35>

12

12

RC3730_0402_5%

12

12

RC3740_0402_5%

12

12

RC3750_0402_5%

12

12

RC3760_0402_5%

12

12

RC3770_0402_5%

12

12

RC3780_0402_5%

12

PCH_RSMRST#_AND<14,45>

RC75
10K_040 2_5%

CLKREQ_P CIE#0_R

@RF@

CLKREQ_P CIE#1_R

@RF@

CLKREQ_P CIE#2_R

@RF@

CLKREQ_P CIE#3_R

@RF@

CLKREQ_P CIE#4_R

@RF@

CLKREQ_P CIE#5_R

@RF@

PCH_PLTRST#

TC7SH08FU_S SOP5~D

1 2

RC77 1K_0402_5%@

1 2

RC78 60.4 _0402_1%

SYS_PWROK<14,34>
PCH_PWROK<63>

PCH_DPWROK<35>

ME_SUS_PWR_ACK<34>

SUSACK#<34>

PCH_PCIE_WAKE#<34,35>

LAN_WAKE#<30,34>

PM_LANPHY_ENABLE<30>

3.3V_CAM_EN#<29>

RC311 10K_0 402_5%

XDP_DBRESET#<14>

+3.3V_RUN

RC225@ 8.2K_0402_5%
RC227@ 8.2K_0402_5%

PCH_RSMRST#_AND

D42

CLKOUT_PCIE _N0

C42

CLKOUT_PCIE _P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE _N1

A42

CLKOUT_PCIE _P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE _N2

C41

CLKOUT_PCIE _P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE _N3

C40

CLKOUT_PCIE _P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE _N4

A40

CLKOUT_PCIE _P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE _N5

E38

CLKOUT_PCIE _P5

AU7

GPP_B10 /SRCCLKREQ5#

SKL

@

1 2

RC62 0_0 402_5%

@

1 2

RC244 0_0402_5%

@

1 2

RC406 0_0402_5%

+3.3V_ALW_PCH

5

1

P

B

4

O

2

A

G

UC7

3

PCH_PLTRST#

AN10

SYS_RESET#

H_CPUPW RGDH_CPUPW RGD_R
VCCST_PW RGD_CPU

12

XDP_DBRESET#

GPP_B13 /PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PW RGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PW ROK

AR13

GPP_A13 /SUSWARN#/SUSPWRDNACK

AP11

GPP_A15 /SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LA NPHYPC

AT15

GPD7/RSVD

SKL

12
12

-U_BGA1356

PCH_PLTRST#_AND

12

RC65

@

100K_04 02_5%

UC1K

CPU@

-U_BGA1356

@

RC290 0_0402_5%

ME_RESET#

SKL_ ULT

CLOCK SIGNALS

PLTRST_LAN# <30>
PCH_PLTRST#_EC <35>
PLTRST_GPU# <48>

PCH_PLTRST#_AND <31,32,37,40>

SYSTEM POWER MANAGEMENT

1 2

+3.3V_RUN

5

1

P

B

4

O

2

A

G

UC12@

74AHC1G0 9GW_TSSOP 5

3

SKL-U

SYS_RESET#_R

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIA SREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

10 OF 20

PCH_PLTRST#

PCH_PLTRST#_ AND

GPP_B12 /SLP_S0#

GPD4/SLP _S3#
GPD5/SLP _S4#

GPD10/SL P_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP _WLAN#

GPD6/SLP _A#

GPD3/PW RBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11 /PME#

INTRUDER#

GPP_B11 /EXT_PWR_G ATE#

GPP_B2/VRALERT#

11 OF 20

1 2

RC224 1K_0402_5%

CLK_ITPXDP _N

F43

CLK_ITPXDP _P

E43
BA17

SUSCLK
XTAL24_IN

E37

XTAL24_OUT

E35

XCLK_BIA SREF

E42

PCH_RTCX1

AM18

PCH_RTCX2

AM20
AN18

SRTCRST#

AM16

PCH_RTCRST# <34>

PCH_RTCRST#

CMOS1 must take care short & touch risk on layout placement

RC60 0_0 402_5%@

@

RC325 0_0402_5%

SIO_SLP_S0#

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15

PCH_BATLOW#

AU13

AU11

PME#

AP16

INTRUDER#
MPHYP_PW R_EN

AM10
AM11

VRALERT#

+3.3V_RUN

@

RC291

10K_0402_5%

1 2

SYS_RESET#

1 2

RC297 0_0402_5%@

1 2

RC298 0_0402_5%@

SUSCLK <32,40>

1 2

RC52 2.7K_0402_ 1%

1 2

RC324 59 _0402_1%@

546765_546765_2014WW48_Skylake_MOW_Rev_ 1_0

1 2

RC56 20K _0402_5%

1 2

CC24 1U_0402_6 .3V6K

1 2

RC57 20K _0402_5%

1 2

CC25 1U_0402_6 .3V6K

1

1

2

SHORT PADS~D

@

CMOS1

1 2

1 2

SIO_SLP_S0# <17,36,61>
SIO_SLP_S3# <34,35>
SIO_SLP_S4# <17,34,59,62>
SIO_SLP_S5# <34>

SIO_SLP_SUS# <17,34,47,60,61,62>
SIO_SLP_LAN# <34,47>

SIO_SLP_WLAN# <34,47>
SIO_SLP_A# <34>

SIO_PWRBTN# <14,34>

AC_PRESENT <34>

@

T115

PAD~D

connect to VCCMPHYGTAON_1P0 enable pin

CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>

+1.0V_CLK5

For

Skylake, pop RC52,depop RC324

For Cannonlake, pop RC324,depop RC52

2

PLTRST_TPM# <36>

+RTC_CELL

XTAL24_IN
XTAL24_OUT

PCH_RTCX1
PCH_RTCX2

SYS_RESET#

0.1U_0402_25V6

12

ESD Request:place near CPU side

RC46

1 2

1 2

RC295 33 _0402_5%

546765_546765_2014WW48_Skylake_MOW_Rev_ 1_0

1 2

@

RC296 0_0402_5%

8/21 can change to 10K for merge to RP

PCH_BATLOW#
AC_PRESE NT

INTRUDER#

MPHYP_PW R_EN

VRALERT#

SIO_SLP_LAN#

SUSCLK

+3.3V_ALW_PCH

+3.3V_ALW

+3.3V_ALW

@ESD@

CC302

For Skylake,YC1 24 MHz (50 Ohm ESR)
For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)

RC54
10M_0402_5%

1 2

POWER_SW#_MB<35,46>

XTAL24_IN_R

3

4

1

2

XTAL24_OUT_R

12

PCH_RTCX2_R

1 2

RC72 8.2K _0402_5%

1 2

RC243 10K_0402_5 %

1 2

RC69 1M_0 402_5%

1 2

RC387 10K_0402_5 %@

1 2

RC73 10K_0402_5%@

1 2

RC344 10K_0402_5 %@

1 2

RC68 10K_0402_5%@

1 2

RC48 1K_0402_5%@

SIO_SLP_S3#
SIO_SLP_S5#

SIO_SLP_S4#
SIO_SLP_A#

PCH_RTCRST#

SYS_RESET#
SIO_SLP_S0#

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

CC21

1 2

15P_040 2_50V8J

YC1
24MHZ_12PF_X3G0240 00DC1H

CC22

1 2

15P_040 2_50V8J

CC23

1 2

12P_040 2_50V8J

YC2

32.768K HZ_12.5PF_9H03200042

ESR MAX=50k ohm

CC26

1 2

12P_040 2_50V8J

+3.3V_ALW_DSW

+RTC_CELL

+3.3V_ALW_PCH

+3.3V_ALW

JAPS1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

GND

20

GND

CONN@

ACES_50506-01841-P01

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (6/14)

CPU (6/14)

CPU (6/14)

Document Number Re v

Document Number Re v

Document Number Re v

LA-E082P

LA-E082P

LA-E082P

1

11 75Monday, December 12, 2016

11 75Monday, December 12, 2016

11 75Monday, December 12, 2016

1.0

1.0

1.0

5

4

3

2

+1.0V_VCCSTG

1

PCH_JTAG_TDI
PCH_JTAG_TDO

D D

+1.0V_VCCST

RC79 49.9_0402_1%@

RC80 1K_0402_5%

+1.0V_VCCSTG

RC83 1K_0402_5%

+3.3V_RUN

RC414 10K_0402_5%
RC413 10K_0402_5%

C C

B B

RC278 10K_0402_5%
RC272 10K_0402_5%@
RC279 10K_0402_5%
RC345 100K_0402_5%
RC292 10K_0402_5%
RC404 10K_0402_5%

+3.3V_ALW_PCH

RC346 10K_0402_5%

RC288

H_CATERR#

12

H_THERMTRIP#

12

H_PROCHOT#

12

TOUCHPAD_INTR#

12

CAM_MIC_CBL_DET#

12

CONTACTLESS_DET#

12

TOUCH_SCREEN_PD#

12

AUD_PWR_EN

12

IR_CAM_DET#

12

HOST_SD_WP#

12

FFS_INT2

12

SIO_EXT_SMI#

12

12

HDA_SYNC_R<33>

HDA_BIT_CLK_R<33>

HDA_SDOUT_R<33>

HDA_RST#_R<33>

RF@

47P_0402_50V8J

Close to RC93

CH_SCREEN_PD# don't move to RPC,

TOU

ME_FWP

HDA_BIT_CLK_R

1

CC27

2

PECI_EC<34>

H_PROCHOT#<34,63,66>

H_THERMTRIP#<20,21,35>

1 2

RC93 33_0402_5%EMI@

1 2

RC94 33_0402_5%

1 2

RC223 1K_0402_5%

1 2

RC95 33_0402_5%

RC84 499_0402_1%

XDP_OBS0_R<14>

XDP_OBS1_R<14>

T10
T11

TOUCH_SCREEN_PD#<29>
TOUCHPAD_INTR#<34,45>

TOUCH_SCREEN_DET#<29>

12

FFS_INT2<41>

IR_CAM_DET#<29>

HDD_DET#<39,41>

DGPU_PWROK<35,52,68>

1 2

@

PAD~D

@

PAD~D

SIO_EXT_SMI#<34>

12

RC88

49.9_0402_1%

KB_DET#<45>

SPKR<33>

RC89

HDA_BIT_CLK
HDA_SDOUT

HDA_SDIN0<33>

HDA_RST#

H_PROCHOT#_R
H_THERMTRIP#

XDP_OBS2_R
XDP_OBS3_R

TOUCHPAD_INTR#

CPU_POPIRCOMP
PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

EOPIO_RCOMP

12

12

RC90

49.9_0402_1%

49.9_0402_1%

FFS_INT2

IR_CAM_DET#

KB_DET#

H_CATERR#

RC91

49.9_0402_1%

AY22
BB22
BA21
AY21

AW22

AY20

AW20

AK10

AW5

D63
A54
C65
C63
A65

C55
D55
B54
C56

A6

A7
BA5
AY5

AT16

AU16

H66
H65

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1
GPP_B14/SPKR

U_BGA1356

UC1D

CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

SKL-

U_BGA1356

RF Request. Place near CPU side (Intel MOW)

1

2

HDA_RST#

CC331

2.2P_0402_50V8C

@RF@

+3.3V_ALW_PCH +3.3V_ALW_PCH

HDA_SDOUT

12

ENABLE
DISAB LE

SPKR

5

RC183 8.2K_0402_5%@

TOP SWAP STRAP

A A

HIGH
LOW(DEFAULT)

Inte

rnal 20k PD

RC187 4.7K_0402_5%@

Flash Descriptor Security override

HIGH
LOW(DEFAULT)

12

DISABLE

ENABLE

4

CPU@

CPU MISC

SKL-U

JTAG

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

HDA_SDIN0

1

2

CC332

2.2P_0402_50V8C

@RF@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

B61

PROC_TCK

D60

PROC_TDI

A61

PROC_TDO

C60

PROC_TMS

B59
B56

D59
A56
C59
C61

PCH_TRST#

A59

JTAGX

4 OF 20

SDIO/SDXC

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

HDA_SDOUT

1

2

CC333

2.2P_0402_50V8C

@RF@

3

CPU_XDP_TCLK XDP_JTAGX

CPU_XDP_TCLK
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TMS
CPU_XDP_TRST#

PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
CPU_XDP_TRST#
XDP_JTAGX

RC87 1K_0402_5%@

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_RCOMP

1 2

GPP_F23

7 OF 20SKL-

CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>

PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>

AB11

GC6_EVENT#

AB13
AB12

GPU_GC6_FB_EN

W12

CONTACTLESS_DET#

W11
W10

AUD_PWR_EN

W8
W7

BA9
BB9

SD_RCOMP

AB7

AF13

12

RC3280_0402_5%

+1.0V_VCCSTG

1 2

RC96 200_0402_1%

PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX

0.1U_0402_25V6

@ESD@

12

CC303

@

1 2

RC86 51_0402_5%@

CAM_MIC_CBL_DET# <29>

GC6_EVENT# <48>
GPU_GC6_FB_EN <48,52>

CONTACTLESS_DET# <37>

HOST_SD_WP# <31>

AUD_PWR_EN <33>

ESD request,Place near CPU side.

PCH_JTAG_TMS

Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the ent ir e r egi on of t he SPI f la sh to be updat ed usi ng FPT.

+3.3V_ALW_PCH

ME_FWP PCH has internal 20K PD.
(su

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short

David_xie

0.1U_0402_25V6

@ESD@

12

CC304

2

1 2

RC81 51_0402_5%

1 2

RC82 100_0402_5%

1 2

RC130 51_0402_5%

ME_FW_EC

@

RC221 0_0402_5%

PT,ST pop RC222 and SW1; MP pop RC221

RC222

@

1K_0402_5%

1 2

ME_FW_EC<34>

1 2

ME_FWP

ME_FWP

@

SW1

1

A

2

B

3

C

4

G1

5

G2

SS3-CMFTQR9_3P

spend power rail)

H_THERMTRIP# H_PROCHOT#

0.1U_0402_25V6

0.1U_0402_25V6

@ESD@

12

CC305

@ESD@

12

CC312

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (7/14)

CPU (7/14)

CPU (7/14)

LA-E082P

LA-E082P

LA-E082P

0.1U_0402_25V6

@ESD@

12

CC310

1.0

1.0

12 75Monday, December 12, 2016

12 75Monday, December 12, 2016

12 75Monday, December 12, 2016

1

1.0

5

D D

4

CFG[0..19]<14>

3

2

1

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

12

RC113 10K_0402_1%@

CFG0

RC112 10K_0402_1%@
RC110 10K_0402_1%@

12
12

Stall reset sequence

HIGH(DEFAULT )
LOW

C C

RC109 1K_0402_5%

eDP enable

HIGH(DEFAULT )
LOW

B B

No stall(Normal Operat i on)

al l

st

12

CFG4

Disa bled
Enabled

+1.0V_PRIM_XDP

RC114 49.9_0402_1%
RC115 1.5K_0402_5%

ITP_PMODE<14>

@

T16

PAD~D

@

T17

PAD~D

CFG_RCOMP

12

ITP_PMODE

12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

CFG18
CFG19

AL25
AL27

BA70
BA68

E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70

E63
F63

E66
F66

E60

E8

AY2
AY1

D1
D3

K46
K45

C71
B70

F60
A52

J71
J68

F65
G65

F61
E61

UC1S

CPU@

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP
ITP_PMODE
RSVD_AY2

RSVD_AY1
RSVD_D1

RSVD_D3
RSVD_K46

RSVD_K45
RSVD_AL25

RSVD_AL27
RSVD_C71

RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70

RSVD_TP_BA68
RSVD_J71

RSVD_J68
VSS_F65

VSS_G65
RSVD_F61

RSVD_E61

SK

L-U_BGA1356

RESERVED SIGNALS-1

SKL-U

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

TP5
TP6

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

TP4

RSVD_A69
RSVD_B69

RSVD_AY3
RSVD_D71

RSVD_C70
RSVD_C54

RSVD_D54

TP1
TP2

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

19 OF 20

BB68
BB69

AK13
AK12

BB2
BA3

AU5
AT5

D5
D4
B2
C2

B3
A3

AW1
E1

E2
BA4

BB4
A4

C4
BB5
A69

B69

D71
C70

C54
D54

AY4
BB3

AY71
AR56

AW71
AW70

AP56
C64

PROC_SELECT#:This pin is for compatibility
wi
for KBL

@

T12

PAD~D

@

T13

PAD~D

@

T14

PAD~D

@

T15

PAD~D

@

T128

PAD~D

@

T129

PAD~D

@

T130

PAD~D

@

T126

PAD~D

@

T127

PAD~D

@

T113

PAD~D

@

T114

PAD~D

1 2

RC120 100K_0402_5%@

For Skylake , RC120 depop

or Cannonlake, RC120 pop

F

546765_546765_2014WW48_Skylake_MOW_Rev_1_0

th future platforms. It should be unconnected

1/5 2014WW52 MOW reserve to support
C

annonlake-U PCH compatibility

close UC1.U11/U12 and <400mil

1 2

RC313 0_0402_5%@

Z

VM# for SKYLAKE-U 2+3e

+1.0V_VCCST

+VCC_1P8+1.8V_PRIM

MSM# for SKYLAKE-U 2+3e

CPU@

SPARE

SKL-U

RSVD_F6

RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

20 OF 20

F6
E3
C11
B11
A11
D12
C12
F52

UC1T

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

1

2

CC222

@

RSVD_H11

SK

L-U_BGA1356

1U_0402_6.3V6K

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (8/14)

CPU (8/14)

CPU (8/14)

LA-E082P

LA-E082P

LA-E082P

13 75Monday, December 12, 2016

13 75Monday, December 12, 2016

13 75Monday, December 12, 2016

1

1.0

1.0

1.0

@

CC29

5

+1.0V_PRIM_XDP

XDP_OBS0_R<12>
XDP_OBS1_R<12>

RC123 1K_0402_5%@

RC124CXDP@

PCH_SPI_DO_XDP<8>

SYS_PWROK<11,34>

RC239 0_0402_5%CXDP@
RC240 0_0402_5%CXDP@

RC5 need to close to JCPU1

1 2
1 2

1K_0402_5%

FIVR_EN
CFG0

RC217 0_0402_5%@
RC126 1K_0402_5%@
RC128 0_0402_5%CXDP@
RC129 0_0402_5%@

DDR_XDP_WAN_SMBDAT<8,20,21,41>

DDR_XDP_WAN_SMBCLK<8,20,21,41>

1 2
1 2
1 2
1 2

CPU_XDP_PREQ#<10>

CPU_XDP_PRDY#<10>

1 2
1 2

PCH_JTAG_TCK<12>

CPU_XDP_TCLK<12>

CPU XDP

H_VCCST_PWRGD_XDP

SIO_PWRBTN#<11,34>

CPU_XDP_PREQ#
CPU_XDP_PRDY#

RESET_OUT#_R

CPU_XDP_TCLK

+1.0V_PRIM

1 2

RC216 0_0603_1%@

+1.0V_PRIM_XDP

0.1U_0201_10V6K

0.1U_0201_10V6K

@

CC28

1

1

2

2

D D

Place near
JX

DP1

VCCST_PWRGD<11,34,35>

PCH_RSMRST#_AND<11,45>

+1.0V_PRIM_XDP

CFG0
CFG1

CFG2
CFG3

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6
CFG7

FIVR_EN_R

4

XDP_PRSNT_PIN1

1 2

RC121 0_0402_5%

1 2

RC122 0_0402_5%@

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12
PWRGOOD/HOOK039ITPCLK/HOOK4

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

CXDP@

CFG3

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

CONN@SAMTE_BSH-030-01-L-D-A

TD0

TDI

+1.0V_PRIM_XDP

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

CFG17
CFG16

CFG8
CFG9

CFG10
CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

ITP_PMODE
XDP_DBRESET#

TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS

3

CFG[0..19]<13>

CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>

ITP_PMODE <13>
XDP_DBRESET# <11>

PCH_SPI_DO2_XDP <8>

2

+3.3V_RUN

CC30

12

0.1U_0201_10V6K

TDO_XDP

TDI_XDP

XDP_TMS

TRST#_XDP

RUNPWROK<34>

UC8

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126BQ_DHVQFN14_2P5X3

GND

GND PAD

1

3

1B

6

2B

8

3B

11

4B

7
15

CPU_XDP_TDO <12>

CPU_XDP_TDI <12>

CPU_XDP_TMS <12>

CPU_XDP_TRST# <12>

FIVR_EN_R

C C

B B

RC132 150_0402_5%

+1.0V_VCCST

RC218 150_0402_5%@

RC219 10K_0402_5%@

+3.3V_RUN

+1.0V_PRIM_XDP

RC137 3K_0402_5%

RC138 51_0402_5%@

12

FIVR_EN

12

FIVR_EN

12

XDP_DBRESET#

12

CPU_XDP_PREQ#

12

+3.3V_ALW_PCH+1.0VS_VCCIO

RC133

1.5K_0402_5%

1 2

CXDP@

PCH_SPI_DO_XDP
RESET_OUT#_R

0.1U_0402_25V6

12

CC33@

Place near JXDP1.47

Place near JXDP1.48

XDP_DBRESET#

0.1U_0402_25V6

CXDP@

12

CC32

SIO_PWRBTN#

Place near JXDP1.41

+3.3V_ALW_DSW

1.5K_0402_5%

1 2

0.1U_0402_25V6

12

@

RC241

CC269

@

TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

0.1U_0402_25V6

@ESD@

12

CC306

ESD request,Place near JXDP1 side. ES

12

CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_TDO

CPU_XDP_TRST#
CPU_XDP_TCLK

XDP_TMS
TDI_XDP

@

TDO_XDP

@

0.1U_0402_25V6

@ESD@

CC307

1 2

RC131 51_0402_5%

1 2

RC134 51_0402_5%

1 2

RC135 100_0402_5%

1 2

RC136@ 51_0402_5%

1 2

RC139 51_0402_5%

1 2
1 2

RC229 0_0402_5%

1 2

RC230 0_0402_5%

0.1U_0402_25V6

@ESD@

12

CC308

D request,Place near UC8 side.

+1.0V_VCCSTG

PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (9/14)

CPU (9/14)

CPU (9/14)

LA-E082P

LA-E082P

LA-E082P

14 75Monday, December 12, 2016

14 75Monday, December 12, 2016

14 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

+VCC_CORE: 0.3~1.35V

D D

@

T122

PAD~D

@

T123

PAD~D

C C

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e

(w/ on package cach e)

+VCC_CORE +VCC_CORE

+VCC_CORE_G0
+VCC_CORE_G1

AK33
AK35
AK37
AK38
AK40

AL33
AL37

AL40
AM32
AM33
AM35
AM37
AM38

AK32
AB62

AC63
AE63

AE62
AG62

AL63

AJ62

A30
A34
A39
A44

G30
K32

P62
V62

H63
G61

SKL

UC1L

CPU@

VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30

RSVD_K32
RSVD_AK32
VCCOPC_AB62

VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE

VSSOPC_SENSE
VCCEOPIO

VCCEOPIO
VCCEOPIO_SENSE

VSSEOPIO_SENSE

-U_BGA1356

SKL-U

CPU POWER 1 OF 4

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37

VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

12 OF 20

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

VCCSENSE
VSSSENSE

H_CPU_SVIDALRT#
VIDSCLK

VIDSOUT

+1.0V_VCCSTG_R

VIDSCLK <63>

RC143 0_0603_5%@

+VCC_CORE

1 2

12

1 2

RC140

RC141

100_0402_1%

100_0402_1%

VCCSENSE <63>
VSSSENSE <63>

+1.0V_VCCSTG

VIDSCLK

RF Request

1 2

CC321@RF@ 33P_0402_50V8J

Place close CPU side

PSC(Primary side cap) : Place as close to the package as
BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

possible

B B

SVID ALERT

VIDALERT_N<63>

SVID DATA

A A

VIDSOUT<63>

+1.0V_VCCST

1 2

+1.0V_VCCST

1 2

56_0402_1%

RC152

100_0402_1%

RC157

CAD Note: Place the PU resistors close to CPU

RC204 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

12

RC153220_0402_5%

CAD Note: Place the PU resistors close to CPU

RC208close to CPU 300 - 1500mils

VIDSOUT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (10/14)

CPU (10/14)

CPU (10/14)

LA-E082P

LA-E082P

LA-E082P

15 75Monday, December 12, 2016

15 75Monday, December 12, 2016

15 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

+VCCGT: 0.3~1.35V
+V

CCGTX : 0.3~1.35V

+VCC_GT +VCC_GT

D D

C C

RC161

100_0402_1%

1 2

VCC_GT_SENSE<63>
VSS_GT_SENSE<63>

B B

VCC_GT_SENSE
VSS_GT_SENSE

12

RC163

100_0402_1%

AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

M62
N63
N64
N66
N67
N69

A48
A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68

L70
L71

J70
J69

UC1M

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

SKL

-U_BGA1356

CPU@

CPU POWER 2 OF 4

SKL-U

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58

VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

13 OF 20

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50

VCCGTX for SKYLAKE-U 2+3e

AL53
AL56
AL60
AM48

AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

Reserve for soldering

+VCC_GTUS

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (11/14)

CPU (11/14)

CPU (11/14)

LA-E082P

LA-E082P

LA-E082P

16 75Monday, December 12, 2016

16 75Monday, December 12, 2016

16 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

+5V_ALW

@

CZ104

1 2

4

O

@

1

2

CC253

1U_0402_6.3V6K

UZ34

1

2

+1.2V_MEM

1

2

CC250

1U_0402_6.3V6K

@

RZ119 0_0402_5%

UZ26

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

CC251

1U_0402_6.3V6K

SIO_SLP_S0#

SIO_SLP_S3#

AND

1 2

+VCCPLL_OC source

+1.2V_MEM+1.2V_MEM_CPUCLK

@

1 2

RC231 0_0402_5%

P

D D

SC

1

1

2

1

CC177

CC176

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

PSC

22U_0603_6.3V6M

CC294

1

1

2

2

+1.0V_VCCST

C C

B B

PSC

1

2

CC195

1U_0402_6.3V6K

VDDQ: 8.45A

1

CC179

CC178

2

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

CC296

CC295

1

2

+1.0V_VCCSTG

BSC

1

PS

C

1

CC297

2

10U_0402_6.3V6M

CC199

1U_0402_6.3V6K

+1.2V_MEM_CPUCLK

+VCC_SFR_OC

2

CC288

1U_0402_6.3V6K

2

CC322

RF@

RF Request

+1.0V_VCCST source

+1.2V_MEM

2.2P_0402_50V8C

AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51

AM40

AL23

A18
A22

K20
K21

UC1N

CPU POWER 3 OF 4

VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20

VCCPLL_K21

SK

L-U_BGA1356

+1.0V_VCCST

CPU@

1

2

CC202

1U_0402_6.3V6K

SKL-U

+VCC_SA

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

14 OF 20

1 2

RC168 100_0402_1%

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

+1.0VS_VCCIO

VCCIO_SENSE
VSSIO_SENSE

+VCC_SA

+1.0VS_VCCIO

12

RC166

100_0402_1%

VSA_SEN- <63>
VSA_SEN+ <63>

RC165

1 2

12

RC167

100_0402_1%

VCCIO_SENSE <61>
VSSIO_SENSE <61>

100_0402_1%

12

CZ102 1U_0402_6.3V6K

VCCSTG_EN

SIO_SLP_SUS#<11,34,47,60,61,62>
SIO_SLP_S4#<11,17,34,59,62>

1 2

@

RZ120 0_0402_5%

+3.3V_ALW

5

1

P

B

2

A

G

3

+1.0VS_VCCIO

0.1U_0402_10V7K

TC7SH08FU_SSOP5~D

PSC

1

2

CC252

1U_0402_6.3V6K

+1.0V_VCCSTG source

+VCC_SFR_OC

6

VOUT

5

GND

S0

HIGH

HIGH

HIGH LOW LOW

S0Ix

LOW

HIGH

S3

LOW

LOW

1 2

CZ103 0.1U_0201_10V6K

+1.0V_VCCST+1.0V_VCCSTG

1 2

RZ151 0_0603_5%@

+1.0V_PRIM

12

CZ100 1U_0402_6.3V6K

SIO_SLP_S4#<11,17,34,59,62>

A A

5

+1.0V_PRIM

+5V_ALW

UZ21

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
TR=12.5us@Vin=1.05V

VOUT

GND

+1.0V_VCCST_C

6

5

4

PJP1

12

PAD-OPEN1x1m

1 2

CZ101 0.1U_0201_10V6K

+1.0V_VCCST

SIO_SLP_S0#<11,36,61>

RUN_ON<34,35,47,61>

TC7SH08FU_SSOP5~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

12

CZ105 1U_0402_6.3V6K

UZ35

RZ320 0_0402_5%@

+5V_ALW

+3.3V_ALW

5

1

B

2

A

3

1 2

P

O

G

4

VCCSTG_EN

UZ19

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
R=12.5us@Vin=1.05V

T

2

VOUT

GND

12

PJP2
PAD-OPEN1x1m

+1.0V_VCCSTG_C

6

5

DELL CONFIDENTIAL/PROPRIETARY

pop option with UZ19

1 2

CZ106 0.1U_0201_10V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number Re v

Size Document Number Re v

Size Document Number Re v

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (12/14)

CPU (12/14)

CPU (12/14)

LA-E082P

LA-E082P

LA-E082P

17 75Monday, December 12, 2016

17 75Monday, December 12, 2016

17 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

+1.0V_PRIM

+1.0V_MPHYAON

ose UC1.K17 and <120mil

1

D D

+1.8V_PRIM

C C

+3.3V_ALW_PCH

+1.8V_PRIM

@ESPI@

B B

1 2

@

RC299 0_0603_5%

1 2

@

RC300 0_0402_5%

1 2

@

RC301 0_0402_5%

1 2

@

RC302 0_0402_5%

1 2

@

RC303 0_0402_5%

1 2

@

RC304 0_0402_5%

1 2

RC234 0_0402_5%@

1 2

@

RC235 0_0402_5%

1 2

RC211 0_0402_5%LPC@

1 2

RC212 0_0402_5%

1 2

@

RC305 0_0402_5%

1 2

@

RC306 0_0402_5%

1 2

@

RC307 0_0402_5%

1 2

@

RC308 0_0402_5%

+3.3V_ALW_PCH

1 2

LC1 BLM15GA750SN1D_2P

1

CC215

2

RF@

47P_0402_50V8J

+1.0V_MPHYAON

+1.0V_CLK6

+1.0V_DTS

+1.0V_CLK1

+1.0V_CLK3

+1.8V_PGPPF

+3.3V_1.8V_PGPPG

close UC1.AF20 and <400mil

+3.3V_1.8V_PGPPA

+3.3V_1.8V_ESPI

PJP4

+3.3V_PGPPB+3.3V_ALW_PCH

PAD-OPEN1x1m

Must be +1.8V for eSPI I/F

+3.3V_PGPPC

+3.3V_PGPPD

+3.3V_PGPPE

8/28 schematic review

LC1,LC2 need link SM01000S100(S SUPPRE_ FBMA-1H-100505-601T 0402)

+3.3V_VCCHDA

1

CC313

2

0.1U_0201_10V6K

close UC1.AJ19 and <400mil

2

CC203

1U_0402_6.3V6K

+1.0V_MPHYGT

close UC1.N15 and CC210 <400mil, CC211 <120mil

1

2

+1.0V_SRAM

1

2

close UC1.K15, UC1.L15 and <100mil

@

1 2

RC169 0_0603_5%

1

2

CC281

@

0.1U_0201_10V6K

+1.0V_PRIM

1 2

LC2 BLM15GA750SN1D_2P

1

CC225

2

@

47U_0805_6.3V6M

close UC1.V15 and <100mil

4

close UC1.AL1 and <120mil

1

2

CC204

1U_0402_6.3V6K

1

CC210

2

@

CC211

1U_0402_6.3V6K

47U_0805_6.3V6M

CC217

+1.0V_APLLEBB

@

1U_0402_6.3V6K

2

CC218

+1.0V_AMPHYPLL+1.0V_MPHYGT

1

CC219

2

@

47U_0805_6.3V6M

+1.0V_PRIM_CORE+1.0VO_DSW

1

2

close UC1.AB19 and <400milcl

1

CC205

2

@

1U_0402_6.3V6K

close UC1.AF18 and <400mil

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0V_PRIM

+3.3V_ALW_DSW

+3.3V_VCCHDA

+3.3V_SPI

+3.3V_ALW_PCH

+1.0V_PRIM

1U_0402_6.3V6K

close UC1.K15 and <120mil

1

2

CC264

@

1U_0402_6.3V6K

+1.0V_APLL

1

CC314

2

0.1U_0201_10V6K

+1.0V_PRIM

CC206

@

1U_0402_6.3V6K

UC1O CPU@

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

1 2

@

RC170 0_0402_5%

close UC1.K19 and <100mil

1 2

@

RC173 0_0402_5%

close UC1.N20 and <100mil

3

PCH PWR

CPU POWER 4 OF 4

+1.0V_CLK2+1.0V_PRIM

1

CC220

2

@

47U_0805_6.3V6M

+1.0V_CLK4+1.0V_PRIM

1

CC226

2

@

SKL-U

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

close UC1.L19 and <100mil

close UC1.Y16 a nd <400mil

close UC1.AG15 and <120mil

Must be +1.8V

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19
T1
AA1
AK17
AK19

BB14
BB10
A14
K19
L21
N20
L19
A10
AN11

AN13

+3.3V_1.8V_PGPPA

+3.3V_PGPPD
+1.8V_PGPPF

+3.3V_1.8V_PGPPG

+1.0V_DTS

+3.3V_ALW_PCH

close UC1.BB10 and <120mil

+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5

+3.3V_PGPPB

close UC1.AA1 and <400mil

close UC1.AK19 and <120mil

+DCPRTC

CORE_VID0 <61>
CORE_VID1 <61>

Take care!!! Note1 on Page 19

1 2

@

RC171 0_0402_5%

1

CC221

2

@

47U_0805_6.3V6M

+1.0V_MPHYGT source

2

1

CC265

2

@

1

2

+1.0V_CLK6

+3.3V_PGPPC

1

CC207

2

@

1U_0402_6.3V6K

1U_0402_6.3V6K

+RTC_CELL

1

2

CC270

CC214

0.1U_0201_10V6K

close UC1.A10 and <120mil

1

CC216

2

@

1U_0402_6.3V6K

+3.3V_PGPPE

close UC1.T16 a nd <400mil

1

2

1

2

CC213

1U_0402_6.3V6K

0.1U_0201_10V6K

+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM

CC208

@

1U_0402_6.3V6K

+1.8V_PRIM

1

2

close UC1.AK17 and <120mil

1

1

CC223

2

2

0.1U_0201_10V6K

+1.0V_MPHYGT

@

RC309 0_0603_5%

@

RC310 0_0603_5%

+3.3V_ALW_PCH

1

CC209

2

@

CC212

1U_0402_6.3V6K

+1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB

CC224

1U_0402_6.3V6K

1

1 2

1 2

+1.0V_SRAM

+1.0V_APLLEBB

+3.3V_1.8V_PGPPG

close UC1.AD15 and <400mil

1

CC326

2

1U_0402_6.3V6K

close UC1.V19 and <120mil

1U_0402_6.3V6K

RF Request

1

1

2

2

CC324

CC323

RF@

RF@

2.2P_0402_50V8C

2.2P_0402_50V8C

PJP3

1 2

PAD-OPEN1x3m

1

2

CC325

RF@

2.2P_0402_50V8C

+1.0V_MPHYGT+1.0V_PRIM

561280_561280_KBL_UY_PDG_Rev0p9 :MPHY has defeature

47U_0805_6.3V6M

+3.3V_ALW +3.3V_ALW_DSW

A A

1 2

@

RC214 0_0402_5%

22U_0603_6.3V6M

@

22U_0603_6.3V6M

@

CC279

CC280

1

1

2

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

e Document Number Rev

Size Document Number Re v

Size Document Number Re v

Siz

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (13/14)

CPU (13/14)

CPU (13/14)

LA-E082P

LA-E082P

LA-E082P

18 75Monday, December 12, 2016

18 75Monday, December 12, 2016

18 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Rec o mmendat i on

CPU@

SKL-U

UC1P

GND 1 OF 3

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

D D

C C

B B

AA65
AA68
AB15
AB16
AB18
AB21

AB8
AD13
AD16
AD19
AD20
AD21
AD62

AD8
AE64
AE65
AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH6
AH63
AH64
AH67

AJ15
AJ18
AJ20

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AK8
AL28

AL32
AL35
AL38

AL45
AL48
AL52
AL55
AL58
AL64

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF1

VSS
VSS
VSS
VSS

AF2

VSS

AF4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AL2

VSS
VSS
VSS
VSS
VSS

AL4

VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL

-U_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

16 OF 20

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48

AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

AT63
AT68

AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6

AW60
AW62
AW64
AW66

AW8

AY66

BA10
BA14
BA18

BA23
BA28
BA32
BA36

BA45

CPU@

SKL-U

UC1Q

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B10

VSS

B14

VSS

B18

VSS

B22

VSS

B30

VSS

B34

VSS

B39

VSS

B44

VSS

B48

VSS

B53

VSS
VSS

B62

VSS

B66

VSS

B71

VSS

BA1

VSS
VSS
VSS
VSS

BA2

VSS
VSS
VSS
VSS
VSS

F68

VSS
VSS

SKL

-U_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

17 OF 20

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71

F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

CPU@

SKL-U

UC1R

GND 3 OF 3

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

SKL

-U_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

18 OF 20

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

R1

: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITI ON,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (14/14)

CPU (14/14)

CPU (14/14)

LA-E082P

LA-E082P

LA-E082P

19 75Monday, December 12, 2016

19 75Monday, December 12, 2016

19 75Monday, December 12, 2016

1

1.0

1.0

1.0

5

4

3

2

1

For DDR4

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>

DDR_A_MA[0..16]<7>

Layout Note:

D D

C C

B B

A A

Place near JDIMM1

+1.2V_MEM

10U_0603_10V6M

10U_0603_10V6M

CD2

CD1

12

12

+1.2V_MEM

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

CD9

CD10

+0.6V_DDR_VTT

12

DIMM Select

SA01SA1

DIMM1

DIMM2

DIMM3

DIMM4

10U_0603_10V6M

CD3

12

1U_0402_6.3V6K

12

CD11

Layout Note:
Place near
JDIMM1.258

10U_0603_10V6M

CD22

0

0

0

1

0

1

1

10U_0603_10V6M

10U_0603_10V6M

CD5

CD4

12

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

12

CD13

CD12

1U_0402_6.3V6K

1U_0402_6.3V6K

CD23

CD24

1

1

2

2

SA2

0

0

0

0

10U_0603_10V6M

1U_0402_6.3V6K

12

12

CD6

12

12

CD14

RD4

@

0_0402_5%

@

RD5
0_0402_5%

10U_0603_10V6M

330U_D3_2.5VY_R6M

10U_0603_10V6M

12

@

CD8

CD17

CD7

12

+

+2.5V_MEM

1U_0402_6.3V6K

CD19

12

1

2

10U_0603_10V6M

1

CD20

2

@

RD10
0_0603_5%

2.2U_0402_6.3V6M
CD27

10U_0603_10V6M

1

CD21

2

+3.3V_RUN_DIMM1

0.1U_0201_10V6K
CD28

1

2

DDR_XDP_WAN_SMBCLK<8,14,21,41>

DDR_A_CKE0<7>

DDR_A_BG1<7>
DDR_A_BG0<7>

DDR_A_CLK0<7>
DDR_A_CLK#0<7>

DDR_A_CS#1<7>

DDR_A_ODT1<7>

+2.5V_MEM

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD15

CD16

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

RD6

@

0_0402_5%

12

@

RD7
0_0402_5%

12

@

0_0402_5%

12

0.1U_0402_10V6K

1

CD25

2

RD8

DIMM1_SA0
DIMM1_SA1
DIMM1_SA2

@

RD9
0_0402_5%

1U_0402_6.3V6K

1

1

CD18

2

2

2.2U_0402_6.3V6M

@

1

CD26

2

+3.3V_RUN

DDR_A_D1
DDR_A_D0
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D6
DDR_A_D2
DDR_A_D13
DDR_A_D12

DDR_A_D15
DDR_A_D14
DDR_A_D35
DDR_A_D37
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D38
DDR_A_D34
DDR_A_D44
DDR_A_D45

DDR_A_D42
DDR_A_D46

DDR_A_CKE0
DDR_A_BG1

DDR_A_BG0
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA6
DDR_A_MA3

DDR_A_MA1
DDR_A_CLK0

DDR_A_CLK#0
DDR_A_PARITY

DDR_A_ODT1

T51PAD~D @

DDR_A_D30
DDR_A_D26
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D27
DDR_A_D29
DDR_A_D21
DDR_A_D17

DDR_A_D19
DDR_A_D22
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57

DDR_A_D63
DDR_A_D62

+3.3V_RUN_DIMM1

+1.2V_MEM

JDIMM1

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5
DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16
DM1_n/DBI_n33DQS1_t

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25
DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36
DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45
DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1
VDD13 VDD14
CS0_n BA0
WE_n/A14 RAS_n/A16
VDD15 VDD16
ODT0 CAS_n/A15
CS1_n A13
VDD17 VDD18

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LCN_DAN05-Q0406-0103
CONN@

LINK DAN05-Q0406-0103 DONE

VSS11

DQ12

VSS13
VSS15

DQS1_c

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26
VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46
VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1
VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67
DQS5_c
DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87
DQS7_c
DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

VSS2
VSS4
VSS6
VSS7
VSS9

+1.2V_MEM

2
4

DQ4

6
8

DQ0

10
12
14
16

DQ6

18
20

DQ2

22
24
26
28

DQ8

30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

A11

122

A7

124
126

A5

128

A4

130
132

A2

134
136
138
140
142
144

A0

146

162
164
166

SA2

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254

SDA

256

SA0

258

VTT

260

SA1

262

DDR_A_D4
DDR_A_D5

DDR_A_D3
DDR_A_D7
DDR_A_D9
DDR_A_D8
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D32
DDR_A_D36

DDR_A_D39
DDR_A_D33
DDR_A_D40
DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D47
DDR_A_D43

DDR_DRAMRST#_R
DDR_A_CKE1

DDR_A_ACT#
DDR_A_ALERT#

DDR_A_MA11
DDR_A_MA7

DDR_A_MA5
DDR_A_MA4

DDR_A_MA2
JDIMM1_EVENT#

DDR_A_CLK1
DDR_A_CLK#1

DDR_A_BA0

DDR_A_MA15

DIMM1_SA2
DDR_A_D31
DDR_A_D25

DDR_A_D28
DDR_A_D24
DDR_A_D20
DDR_A_D16
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18
DDR_A_D23
DDR_A_D53
DDR_A_D52

DDR_A_D54
DDR_A_D55
DDR_A_D61

DDR_A_D60

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D58

DDR_A_D59

DIMM1_SA0
DIMM1_SA1

DDR_A_CKE1 <7>
DDR_A_ACT# <7 >

DDR_A_ALERT# <7>

DDR_A_BA0 <7>

+DDR_VREF_A_CA

T50 PAD~D@

+DDR_VREF_A_CA

DDR_XDP_WAN_SMBDAT <8,14,2 1,41>

+0.6V_DDR_VTT

+1.2V_MEM

470_0402_1%

12

RD11

1 2

@

RD12 0_0402_5%

+1.2V_MEM

12

12

1

CD29

@

0.1U_0402_25V6

2

JDIMM1_EVENT#

DDR_VTT_CTRL<7>

1 2

RD14 1K_0402_5%@

UD1

1

NC

VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

+1.2V_MEM

5

4

Y

DDR_DRAMRST#

1K_0402_1%

RD15

1 2

RD17 2_0402_1%

1K_0402_1%

RD16

1 2

CD32@ 0.1U_0201_10V6K

1 2

RD19 100K_0402_5%

DDR_DRAMRST# <7>DDR_DRAMRST#_R<21>

+DDR_VREF_CA+DDR_VREF_A_CA

0.022U_0402_16V7K

CD31

12

24.9_0402_1%

12

RD18

H_THERMTRIP# <12,21,35>

0.6V_DDR_VTT_ON <59>

+3.3V_RUN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

ADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

TR

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTE N CONSENT.

2

Title

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

DDR4

DDR4

DDR4

LA-E082P

LA-E082P

LA-E082P

1

20 75Monday, December 12, 2016

20 75Monday, December 12, 2016

20 75Monday, December 12, 2016

1.0

1.0

1.0

5

DDR_B_DQS#[0..7]<7>

DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>

DDR_B_MA[0..16]<7>

Layout Note:

10U_0603_10V6M

CD33

12

1U_0402_6.3V6K

12

CD41

SA01SA1

0

1

0

1

Place near JDIMM2

10U_0603_10V6M

CD35

CD34

12

12

1U_0402_6.3V6K

12

12

CD43

CD42

+0.6V_DDR_VTT

10U_0603_10V6M

CD54

12

SA2

0

0

0

0

0

0

1

10U_0603_10V6M

10U_0603_10V6M

CD36

12

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD44

Layout Note:
Place near
JDIMM2.258

1U_0402_6.3V6K

CD55

1

2

CD37

CD45

12

12

12

12

1U_0402_6.3V6K

1

2

@

0_0402_5%

RD21
0_0402_5%

10U_0603_10V6M

330U_D3_2.5VY_R6M

10U_0603_10V6M

10U_0603_10V6M

12

@

CD39

CD49

CD40

CD38

12

12

+

+2.5V_MEM

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

CD48

CD47

CD46

CD56

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

12

@

RD20

@

12

RD22
0_0402_5%

RD23

@

0_0402_5%

12

@

0_0402_5%

DIMM2_SA0
DIMM2_SA1
DIMM2_SA2

RD24

@

RD25
0_0402_5%

1U_0402_6.3V6K

1

CD50

2

+DDR_VREF_B_CA

1

2

+3.3V_RUN

1U_0402_6.3V6K

1

CD51

2

0.1U_0402_10V6K
CD57

1

2

12

@

RD26
0_0603_5%

2.2U_0402_6.3V6M

12

CD59

D D

+1.2V_MEM

10U_0603_10V6M

12

+1.2V_MEM

1U_0402_6.3V6K

12

C C

B B

DIMM Select

DIMM1

DIMM2

DIMM3

*

DIMM4

A A

10U_0603_10V6M

1

1

CD52

2

2

2.2U_0402_6.3V6M

@

CD58

+3.3V_RUN_DIMM2

0.1U_0201_10V6K

1

CD60

2

4

3

2

1

For DDR4

+1.2V_MEM

DDR_B_D1
DDR_B_D4
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D7
DDR_B_D6
DDR_B_D13
DDR_B_D12

DDR_B_D14
DDR_B_D15
DDR_B_D33
DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D39
DDR_B_D38
DDR_B_D42
DDR_B_D43

10U_0603_10V6M

CD53

DDR_B_CKE0<7>

DDR_B_BG1<7>
DDR_B_BG0<7>

DDR_B_CLK0<7>
DDR_B_CLK#0<7>

DDR_B_PARITY<7>

DDR_B_ODT1<7>

DDR_XDP_WAN_SMBCLK<8,14,20,41>

DDR_B_BA1<7>

+2.5V_MEM

DDR_B_D44
DDR_B_D45

DDR_B_CKE0
DDR_B_BG1

DDR_B_BG0
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA6
DDR_B_MA3

DDR_B_MA1
DDR_B_CLK0

DDR_B_CLK#0
DDR_B_PARITY

DDR_B_BA1

T55PAD~D @

DDR_B_D21
DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D23
DDR_B_D22
DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27
DDR_B_D52
DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D55
DDR_B_D54
DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

+3.3V_RUN_DIMM2

JDIMM2

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5
DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16
DM1_n/DBI_n33DQS1_t

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25
DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36
DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45
DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13
CS0_n BA0
WE_n/A14 RAS_n/A16
VDD15 VDD16
ODT0 CAS_n/A15
CS1_n A13
VDD17 VDD18
ODT1 C0/CS2_n/NC
VDD19 VREFCA

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LCN_DAN05-Q0406-0103
CONN@

VSS11

DQ12

VSS13
VSS15

DQS1_c

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26
VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46
VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1
VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12
A10/AP

VDD14

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

VSS2
VSS4
VSS6
VSS7
VSS9

+1.2V_MEM

2
4

DQ4

6
8

DQ0

10
12
14
16

DQ6

18
20

DQ2

22
24
26
28

DQ8

30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

A11

122

A7

124
126

A5

128

A4

130
132

A2

134
136
138
140
142
144

A0

146
148

166

SA2

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254

SDA

256

SA0

258

VTT

260

SA1

262

DDR_B_D5
DDR_B_D0

DDR_B_D2
DDR_B_D3
DDR_B_D9
DDR_B_D8
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D11
DDR_B_D10
DDR_B_D37
DDR_B_D32

DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_DRAMRST#_R
DDR_B_CKE1

DDR_B_ACT#
DDR_B_ALERT#

DDR_B_MA11
DDR_B_MA7

DDR_B_MA5
DDR_B_MA4

DDR_B_MA2
JDIMM2_EVENT#

DDR_B_CLK1
DDR_B_CLK#1

DDR_B_MA0
DDR_B_MA10

DIMM2_SA2
DDR_B_D16
DDR_B_D17

DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D31
DDR_B_D30
DDR_B_D53
DDR_B_D48

DDR_B_D50
DDR_B_D51
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62
DDR_B_D63

DIMM2_SA0
DIMM2_SA1

DDR_B_CKE1 <7>
DDR_B_ACT# <7>

DDR_B_ALERT# <7>

DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>

DDR_XDP_WAN_SMBDAT <8,14,20,41>

+0.6V_DDR_VTT

JDIMM2_EVENT#

RD27 1K_0402_5%@

1

CD61

@

0.1U_0402_25V6

2

+DDR_VREF_B_CA

1 2

DDR_DRAMRST#_R <20>

+1.2V_MEM

1K_0402_1%

12

RD28

1 2

RD30 2_0402_1%

1K_0402_1%

12

RD29

H_THERMTRIP# <12,20,35>

0.022U_0402_16V7K

CD62

12

24.9_0402_1%

12

RD31

+DDR_VREF_B_DQ

LINK DAN05-Q0406-0103 DONE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

T

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTE N CONSENT.

2

Title

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

DDR4

DDR4

DDR4

LA-E082P

LA-E082P

LA-E082P

1

21 75Monday, December 12, 2016

21 75Monday, December 12, 2016

21 75Monday, December 12, 2016

1.0

1.0

1.0

A

B

C

D

E

+3.3V_RUN

SW2_DP1_AUXN

RV70 100K_0402_5%
RV71 100K_0402_5%
RV72 100K_0402_5%

1 1

RV73 1M_0402_5%

RV74 1M_0402_5%
RV75 1M_0402_5%

RV76 100K_0402_5%
RV77 100K_0402_5%
RV78 100K_0402_5%

@

@

RV81

RV79

1 2

2 2

3 3

Internally t i ed t o V DD33/2, 3. 3 V I / O;
PCx =

(defaul t)

L:Portx output with f i xed 400 mV a nd 0dB
x=1, 2, 3

4.7K_0402_5%

12

RV82

RV80

@

@

4.7K_0402_5%

M:Portx output conf i gur at i on is set by l i nk t raini ng

H:Portx output with f i xed 800 mV a nd 0dB

12

SW2_DP2_AUXN

12

SW2_DP3_AUXN

12

0.01UF_0402_25V7K

SW2_DP1_CADET

12

SW2_DP2_CADET

12

SW2_DP3_CADET

12

SW2_DP1_AUXP

12

SW2_DP2_AUXP

12

SW2_DP3_AUXP

12

+3.3V_RUN

@

@

RV85

RV83

1 2

1 2

4.7K_0402_5%

12

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

12

RV86

RV84

@

@

4.7K_0402_5%

4.7K_0402_5%

@

RV89

RV87

1 2

1 2

4.7K_0402_5%

4.7K_0402_5%

12

12

RV88

RV90

@

4.7K_0402_5%

4.7K_0402_5%

@

@

RV93

RV91

1 2

1 2

4.7K_0402_5%

12

12

RV92

@

4.7K_0402_5%

RV95

1 2

1 2

4.7K_0402_5%

4.7K_0402_5%

12

12

RV94

RV96

@

@

4.7K_0402_5%

4.7K_0402_5%

PS8348B_PI0
PS8348B_PI1
PS8348B_SW1
PS8348B_SW0
PS8348B_PEQ
PS8348B_CFG
PS8348B_PC1

PS8348B_PC3

PI0:Automat i c E Q di s abl e, I nt er nal pull do wn ~150K oh m, 3. 3 V I / O
PI0 = L: Automat i c E Q enabl e( def ault)

H: Automat i c E Q di sabl e

CPU_DP2_P0<6>
CPU_DP2_N0<6>

CPU_DP2_P1<6>
CPU_DP2_N1<6>

CPU_DP2_P2<6>
CPU_DP2_N2<6>

CPU_DP2_P3<6>
CPU_DP2_N3<6>

CPU_DP2_AUXP<6>
CPU_DP2_AUXN<6>

CPU_DP2_CTRL_CLK<6>

CPU_DP2_CTRL_DATA<6>

0.01UF_0402_25V7K
CV81

CV80

12

12

CV86 0.1U_0201_10V6K
CV87 0.1U_0201_10V6K

CV88 0.1U_0201_10V6K
CV89 0.1U_0201_10V6K

CV90 0.1U_0201_10V6K
CV91 0.1U_0201_10V6K

CV92 0.1U_0201_10V6K
CV93 0.1U_0201_10V6K

CV94 0.1U_0201_10V6K
CV95 0.1U_0201_10V6K

CPU_DP2_HPD<6> SW2_DP2_P3 <32>

0.01UF_0402_25V7K

12

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

0.1U_0201_10V6K
CV83

CV82

1

1

2

2

PS8348B_PI0
PS8348B_PI1

PS8348B_SW1
PS8348B_SW0

PS8348B_CFG
PS8348B_PC1
PS8348B_PC2
PS8348B_PC3

PS8348B_PEQ

0.1U_0201_10V6K
CV84

1

2

CPU_DP2_P0_C
CPU_DP2_N0_C

CPU_DP2_P1_C
CPU_DP2_N1_C

CPU_DP2_P2_C
CPU_DP2_N2_C

CPU_DP2_P3_C
CPU_DP2_N3_C

CPU_DP2_AUXP_C
CPU_DP2_AUXN_C

T204@ PAD~D

T223@ PAD~D

T224@ PAD~D

0.1U_0201_10V6K
CV85

+3.3V_RUN

12

RV97

4.99K_0402_1%

UV7

1

VDD33

10

VDD33

34

VDD33

11

IN_D0p

12

IN_D0n

14

IN_D1p

15

IN_D1n

16

IN_D2p

17

IN_D2n

19

IN_D3p

20

IN_D3n

64

IN_AUXp

63

IN_AUXn

66

IN_DDC_SCL

65

IN_DDC_SDA

8

IN_CA_DET

7

IN_HPD

2

PI0 / SDA_CTL

3

PI1 / SCL_CTL

4

SW1

5

SW0

21

CFG

22
23

PC2

45

PC3

18

PEQ

13

PD

9

REXT

67

PAD(GND)

For Breckenridge 12/14/15

Priority: Type-C -> WiGig -> VGA

OUT1_D0p
OUT1_D0n

OUT1_D1p
OUT1_D1n

OUT1_D2p
OUT1_D2n

OUT1_D3p
OUT1_D3n

OUT2_D0p
OUT2_D0n

OUT2_D1p
OUT2_D1n

OUT2_D2p
OUT2_D2n

OUT2_D3p
OUT2_D3n

OUT3_D0p
OUT3_D0n

OUT3_D1p
OUT3_D1n

OUT3_D2p
OUT3_D2n

OUT3_D3p
OUT3_D3n

OUT1_AUXp_SCL
OUT1_AUXn_SDA

OUT2_AUXp_SCL
OUT2_AUXn_SDA

OUT3_AUXp_SCL
OUT3_AUXn_SDA

OUT1_CA_DET

OUT1_HPD

OUT2_CA_DET

OUT2_HPD

OUT3_CA_DET

OUT3_HPD

PS8348BQFN66GTR-A0_QFN66_5X10

CEXT

55
54

52
51

50
49

47
46

44
43

41
40

39
38

36
35

33
32

30
29

28
27

25
24

62

60
59

58
57

SW2_DP1_CADET

48
53

SW2_DP2_CADET

37
42

SW2_DP3_CADET

26
31

56

2.2U_0402_6.3V6M
CV96

1

2

SW2_DP1_P0 <25>
SW2_DP1_N0 <25>

SW2_DP1_P1 <25>
SW2_DP1_N1 <25>

SW2_DP1_P2 <25>
SW2_DP1_N2 <25>

SW2_DP1_P3 <25>
SW2_DP1_N3 <25>

SW2_DP2_P0 <32>
SW2_DP2_N0 <32>

SW2_DP2_P1 <32>
SW2_DP2_N1 <32>

SW2_DP2_P2 <32>
SW2_DP2_N2 <32>

SW2_DP2_N3 <32>

SW2_DP3_P0 <24>
SW2_DP3_N0 <24>

SW2_DP3_P1 <24>
SW2_DP3_N1 <24>

SW2_DP1_AUXP <25,26>
SW2_DP1_AUXN <25,26>
SW2_DP2_AUXP <32>

SW2_DP2_AUXN <32>
SW2_DP3_AUXP <24>

SW2_DP3_AUXN <24>

SW2_DP1_HPD <25,26>

SW2_DP2_HPD <32>

SW2_DP3_HPD <24>

-----> WIGIG

-----> TYPE C

---

--> VGA

Internally pull down ~150K.3.3V I/O
For Control Switching Mode (CFG = L):
[SW1,SW0 ]= [L,L], Port1 is selected (default)
[SW1,SW0 ]= [L,H], Port2 is selected
[SW1,SW0 ]= [H,L], Port3 is selected
[SW1,SW0 ]= [H,H], Port3 is selected

4 4

For Automat i c S witc hi ng Mode ( CF G0= H):
[SW1,SW0 ]= [L,L], Port1 >Port2 >Port3 (default)
[SW1,SW0 ]= [L,H], Port1 >Port3 >Port2
[SW1,SW0 ]= [H,L], Port3 >Port2 >Port1
[SW1,SW0 ]= [H,H], Port3 >Port1 >Port2
[SW1,SW0 ]= [L,M], Port2 >Port1 >Port3
[SW1,SW0 ]= [M,M], Port2 >Port3 >Port1

A

Internally t i ed t o V DD33/2, 3. 3 V I / O

Q =

PE

M:default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H:HEQ , compensate channel loss up to 14.5dB @ HBR2
L:LLEQ, compensate channel loss up to 8.5dB @ HBR2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

B

PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

C

D

Date: Sheet of

Compal Electronics, Inc.

DP SW2 PS8348B

DP SW2 PS8348B

DP SW2 PS8348B

LA-E082P

LA-E082P

LA-E082P

22 75Monday, December 12, 2016

22 75Monday, December 12, 2016

22 75Monday, December 12, 2016

E

1.0

1.0

1.0

544332211

0.1U_0201_10V6K

CV39

1

@

2

+3.3V_RUN

+3.3V_RUN

+5V_RUN

1

AP2330W-7_SC59-3

IN

UV2

GND2OUT

3

12

RV19@10K_0402_5%

1 2

RV10 470_0402_1%

1 2

RV11 470_0402_1%

1 2

RV12 470_0402_1%

1 2

RV13 470_0402_1%

1 2

RV14 470_0402_1%

1 2

RV15 470_0402_1%

1 2

RV16 470_0402_1%

1 2

RV17 470_0402_1%

1 2

RV18 10K_0402_5%

+VHDMI_VCC

0.1U_0201_10V6K

1

@

2

HDMI_HPD

HDMI_CTRL_DATA
HDMI_CTRL_CLK

HDMI_CEC
HDMI_L_CLKN

HDMI_L_CLKP
HDMI_L_TX_N0

HDMI_L_TX_P0
HDMI_L_TX_N1

HDMI_L_TX_P1
HDMI_L_TX_N2

HDMI_L_TX_P2

HDMI_OB

2

G

For 1.65G HDMI from CPU

10U_0603_10V6M

CV41

12

CV40

HDMI connector

JHDMI1

CONN@

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

CONCR_099BKAC19YBLCNF

LINK 099BKAC19YBLCNF DONE

1

D

QV4
L2N7002W T1G_SC-70-3

3

GND
GND
GND
GND

20
21
22
23

5

1 2

RV24 5.6_0402_5%EMI@

LV3

EMI@

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

RV25 5.6_0402_5%EMI@

1 2

RV27

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

RV28

1 2

RV30 5.6_0402_5%EMI@

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

RV31

1 2

RV33

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

RV34 5.6_0402_5%EMI@

LV6

LV9

LV12

4

3

5.6_0402_5%EMI@

4

3

5.6_0402_5%EMI@

4

3

5.6_0402_5%EMI@

5.6_0402_5%

4

3

D D

C C

CPU_DP1_P0<6>

CPU_DP1_N0<6>

CPU_DP1_P1<6>

CPU_DP1_N1<6>

CPU_DP1_P2<6>

CPU_DP1_N2<6>

CPU_DP1_P3<6>

CPU_DP1_N3<6>

1 2

CV31 0.1U_0402_25V6

1 2

CV32 0.1U_0402_25V6

1 2

CV33 0.1U_0402_25V6

1 2

CV34 0.1U_0402_25V6

1 2

CV35 0.1U_0402_25V6

1 2

CV36 0.1U_0402_25V6

12

0.1U_0402_25V6

CV37

12

0.1U_0402_25V6

CV38

HDMI_TX_P2

HDMI_TX_N2

HDMI_TX_P1

HDMI_TX_N1

HDMI_TX_P0

HDMI_TX_N0

HDMI_CLKP

HDMI_CLKN

HDMI_L_TX_P2

4

EMI@

RV26
200_0402_5%

3

1 2

HDMI_L_TX_N2

RV29
200_0402_5%

1 2

RV32
200_0402_5%

1 2

RV35
200_0402_5%

1 2

EMI@

EMI@

EMI@

HDMI_L_TX_P1

HDMI_L_TX_N1

HDMI_L_TX_P0

HDMI_L_TX_N0

HDMI_L_CLKP

HDMI_L_CLKN

HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN

4

3

4

3

4

3

1M_0402_5%

RV20

CPU_DP1_HPD<6>

1 2

G

123

D

S

QV5

L2N7002W T1G_SC-70-3

HDMI_HPD

1 2

RV21 20K_0402_5%

B B

+3.3V_RUN

QV3A

2

DMN65D8LDW-7_SOT363-6

CPU_DP1_CTRL_CLK<6>

CPU_DP1_CTRL_DATA<6>

1

5

QV3B

DMN65D8LDW-7_SOT363-6

HDMI_CTRL_CLK

6

HDMI_CTRL_DATA

34

1 2

RV22 2.2K_0402_5%

1 2

RV23 2.2K_0402_5%

+VHDMI_VCC

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S E XPRESS WRITTEN CONSENT.

Title

Title

Title

ze Document Number Rev

Size Document Number Re v

Size Document Number Re v

Si

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

HDMI CONN

HDMI CONN

HDMI CONN

LA-E082P

LA-E082P

LA-E082P

23 75Monday, December 12, 2016

23 75Monday, December 12, 2016

23 75Monday, December 12, 2016

1.0

1.0

1.0