Dell LATITUDE 5290 boardview

A

B

C

D

E

MODEL NAME : LA-F371P non-AR

PCB NO : DAA000EC010

BOM P/N : 431A8C31L01

1 1

Dell/Compal Confidential

2 2

Schematic Document

Pebble Creek MLK (Kabylake R/U)

3 3

2017-11-03

Rev: 1.0

ZZZ

MB_PCB

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P01-Cover Page

P01-Cover Page

P01-Cover Page

Document Number Re v

Document Number Re v

Document Number Re v

LA-F371P

LA-F371P

LA-F371P

E

1 65Tuesday, November 07, 2017

1 65Tuesday, November 07, 2017

1 65Tuesday, November 07, 2017

1.0

1.0

1.0

A

12.3" 3:2
Samsung W UXGA+

ALS
AMS-TAOS TSL2591

Touch Cntrl

1 1

Wacom G12T-W9015

Gyro + Accelerometer
ST LSM6DS3TR

E-Compass
ST LIS2MDLTR

p.22

p.31

p.22

p.31

p.31

on WF camera module

SPI ROM 16M (Main)

SPI ROM 4M(2nd)

NPCT750JB AYX

p.23

p.25

uSIM

p.26

p.24

CHRG_IN

From EC

5V_ALW

CHRG_IN

From EC

5V_ALW

0
8
2
2

2
4
0
3

0
3
2
2

GPIO
(BIOS C ontrolled)

p.38

to EC

to EC

to PCH

to PCH

SPI

USB3.0

RealTek
RTS5242 PCIe to SD

5V@1.5A

Parade
MUX
PS8743A

Parade
MUX
PS8743A

USH Control Vault
Broadcom 58102

Module : DWRFID1603

RDIF/NFC
Antenn a

BC1.2
TI TPS254 4

p.37

p.37

SAR Proximity Sensor
Smtech SX9310

Hall Sensor (On USH board )
TCS40DPR

Kickstand Open /Close detection
(mechanical switch)

Finger Print Reader
NB 2023-S

Smart Card Reader
NXP TDA803 4HN

on IO board

SSD M.2 2280
Slot 3-Key-M

WWAN 4G LTE
M.2 3042 Slot 2-Key-B

Hardware Crypto Accelerator

Module : EM7455

LTE Coex

2 2

RFFEM

uSD Connector

WLAN / BT 4.1
M.2 2230 Slot 1-Key-A
3x3(UI)

WiGig (UI)

Module :
8265NGW/QCNFA 344A

18265NGW

SD4.0/SDXC

SD_WP

p.27

USB3.0 TypeA
BC1.2
with Power Share
TI TPS254 4

USB3.0 / DP x 2lanes or DP x 4 lanes

VBUS

Port-A

CC 2

USB Type-C
ALT mode
with PD

3 3

USB (Top)

USB (Bottom)

p.39

MOSFET

VBUS PP_5V0
CC

TI-ACE 65 982-DC

I2C

p.35

USB3.0 / DP x 2lanes or DP x 4 lanes

Port-B
USB Type-C
ALT mode
with PD

VBUS

CC 2

USB (Top)

USB (Bottom)

p.39

MOSFET

VBUS PP_5V0
CC

TI-ACE 65 982-DC

I2C to EC

p.36

eDP x2 lanes

p.7

p.31

USB 2.0

IOB conn p.43

PCIe x 2lanes

GNSS I2C

PCIe x 2lanes

USB 3.0 / SSIC

USB 2.0

PCIe x 1lane

PCIe x 1lane

USB2.0

eLBS

CLINK

PCIe x 1lane

p.27

USB2.0

USB2.0

p.38

USB3.0

DP1.2 x 4lanes

USB3.0

USB3.0

DP1.2 x 4lanes

p.31

p.31

p.42 p.30

B

eDP

I2C

ISH

Channel A

I2C

I2C

SPI SPI#2

I2C

SPI

I2C (iSH)

SPI#1

Channel B

CSI-2#2

I2C

I2C

CSI-02#0

USB#7

USB2.0 #5

KabyLake U

EC

MEC5105

ESPI

HDA

GPIO

USB2#2

I2C_CLK

I2C_DAT

I2C_INT

I2C 3

PCIe#7,8

I2C (iSH)

PCIe#11/PCIe #12

USB3 # 2 / SSIC

USB2 # 4

PCIe#5

PCIe#6

USB2#7

UART

CLINK

PCIe#9

USB2#9
UART

USB3#3

DDI#2

USB3.0 #1

USB3.0 #4

DDI#1

TABLET

Memory Bus

Memory Bus

MIPI CSI-2 x 2lanes

I2C

I2C

MIPI CSI-2 x 2lanes

D+/D-

4x DMIC

3DMIC on M/B
1DMIC on WFCAM

Dock_Dete ct

Channel A - 4GB
LPDDR3 1866/2133
32Gb x 32 QDP

Channel B - 4GB
LPDDR3 1866/2133
32Gb x 32 QDP

5MP FFC
5BF501 T2/OV5 670

8MP RFC
5BA802T2/OV8 858

Face IR Module
LiteOn 5SF106N2B

HDA

1.5V

p.28

EC JTAG

SPI Programmer

USB PD Debug

DCI Debug

Channel A - 4GB

Channel B - 4GB

Audio Codec
ALC325 3-VA3-C G

p.19

p.20

p.33

SKYCAM PMIC
TPS68470YFFR_DBSG A56

I2C

p.33

p.43

Universal
Headset Jack

p.28 p.29

2x
Speaker

p.29

XDP DEbug

ESPI Debug

APS Debug

Coin Cell

I2C_INT

CHRG_IN

5V/2A

C

3.3V LDO

VSW_3V3

p.34

SPI ROM 2MB

GND

GND

DET_L

DET_L

I2C1

I2C1

CLK

CLK

I2C1

I2C1

DAT

DAT

I2C1

I2C1

INT

INT

5V

5V

D+

D-

12V

DET_R

GND

D+

D-

12V

DET_R

GND

USB 2.0 D+
USB 2.0 D-

D

Boost
TPS61 200

A/D

A/D

SPI

SPI

I2C_CLK

I2C_DAT

I2C_INT

HEAD_DET # GPIO

VR_OUT

VCC_EC
VSW_3V3

VCC

CSR1021

TX/RX

I2C_CLK

I2C_DAT

I2C_INT

GPIO
GPIO

KSO/KSI

GPIO

Pi-Matching i-pex conn

PTP_MODE #
PTP_SL P#

Keyboard Matrix

BT ON/OFF ButtonGPIO

I2C_CLK

I2C_DAT

I2C_INT

PTP_MODE #
EN

CLK

DAT

INT

I/O Expander
TI TCA6416

I2C_CLK

I2C_DAT

I2C_INT

E

USB_D-

Charge/Low _BAT#

KB_LED_PW M

KB_BL_D ET#
MASK_LE D#
MUTE_LE D#

BT_LED#

Accelermeter
ST LNG2DMTR

USB 2.0 D+USB_D+
USB 2.0 D-

5V 5V

WCFW_EN

+VCC_EC

WC_OUT

POGO_DET _R#

WC_DISC

CHG_DICS(NC)

I2C#1_INT

I2C#1_D AT

I2C#1_C LK

WC PRU Board

GND

Keyboard

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Compal Secret Data

Compal Secret Data

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

P02-Block Diagram

P02-Block Diagram

P02-Block Diagram

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

LA-F371P

LA-F371P

LA-F371P

Date: Sheet of

Date: Sheet o f

Date: Sheet o f

E

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

2 65Tuesday, November 07, 2 017

2 65Tuesday, November 07, 2 017

2 65Tuesday, November 07, 2 017

1.0

1.0

1.0

A

B

C

D

E

Rear Camera + 4th DMIC

BTB FPC 34 pin

1 1

Front Camera + ALS sensor+ LED

BTB FPC 30 pin

JUFC 1

p.33

PWR_BUTTON Board

JWFC1

p.33

LS-F371P

IOB

M/B

2 2

LA-F371P

JIOB2 eDP+iTou ch

p.43

JIOB1

p.43

BTB FPC 30pin

p.47

BATT_CON N

LS-F371P

IOB Cable

BTB FPC 40pin

3 3

p.22

Dock Board LS-F372P
(K/B + Bluetooth + Wireless Charge)

eDP+itouch Y-Cable
Coaxial cable 50P

iTouch

14pin

LCD Panel

Base Board
LS-D893P

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

40pin

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

P03-DaughterB block diagram

P03-DaughterB block diagram

P03-DaughterB block diagram

Document Number Re v

Document Number Re v

Document Number Re v

LA-F371P

LA-F371P

LA-F371P

LA-F371P

LA-F371P

LA-F371P

LA-F371PLA-F371P

LA-F371PLA-F371P

LA-F371PLA-F371P

E

3 65Tuesday, November 07, 2017

3 65Tuesday, November 07, 2017

3 65Tuesday, November 07, 2017

1.0

1.0

1.0

A

Board ID Table

3.3V +/- 5%Vcc

0
1
2
3
4
5
6
7

RBoard ID

240K +/- 5% 4700p
130K +/- 5%
62K +/- 5%
33K +/- 5%

8.2K +/- 5%

4.3K +/- 5%
2K +/- 5%

NC

4700p
4700p
4700p
4700p
4700p
4700p

C

REV

Pre-EVT1
EVT1
DVT1
DVT2
PVT

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

0.3

0.4

1.0

SMBUS Control Table

SOURCE

No use

1 1

PCH_SML0CLK

PCH_SML0DATA

PCH_SML1CLK

PCH_SML1DATA

SMBCLK

SMBDATA

EC_SMB00_CLK

EC_SMB00_DAT

EC_SMB01_CLK

EC_SMB01_DAT

EC_SMB02_CLK

EC_SMB02_DAT

EC_SMB03_CLK

EC_SMB03_DAT

EC_SMB04_CLK

EC_SMB04_DAT

EC_SMB05_CLK

EC_SMB05_DAT

EC_SMB10_CLK

EC_SMB10_DAT

PCH

PCH

PCH

MEC5105

MEC5105

MEC5105

MEC5105

MEC5105

MEC5105

MEC5105

Base

V

BATT

V

Charger

V

XDP

V

USH

V

PD
Control ler

Trinit y
Dock

P-Sensor

MUX

V V

V V

V

V

IMVP

IO
EXpendor

Link

V

V

USB 3.0Board ID Table

Flexible I/O

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Interface DESTINATION

USB 3.0 #1

USB 3.0 #2/SSIC

USB 3.0 #3

USB 3.0 #4

PCI-E#1 / USB 3.0#5

PCI-E#2 / USB 3.0#6

PCI-E #3

PCI-E #4

PCI-E #5

USB Type-C Port-A

NGFF (WWAN)

USB 3.0 Type-A

USB Type-C Port-B

Reserved for AR

Reserved for AR

Reserved for AR

Reserved for AR

NGFF (WLAN)

PCI-E #6

PCI-E #7

PCI-E #8 /SATA #1

PCI-E #9

NGFF (SSD)

NGFF (SSD) #7/#8 2lane PCI-E

Card Reader

PCI-E #10

PCI-E #11

NGFF (WWAN/2nd SSD)

PCI-E #12 NGFF (WWAN/2nd SSD)

Port Mapping USB 2.0

DESTINATIONUSB 2.0 PORT#

1

2

3

4

5

7

Type-C Port-A

Dock

Type-C Port-B NGFF (WWAN)

WWAN

IR CAM

WLAN

USB Type-A9

USH10

CLK

CLK

DESTINATIONDIFFERENTIAL

CLKOUT_PCIE0

CLKOUT_PCIE1

NGFF (WLAN)

CLKOUT_PCIE2

CLKOUT_PCIE3

SSD

CLKOUT_PCIE5 Card Reader

FLEX CLOCKS DESTINATION

CLKOUT_LPC_0

CLKOUT_LPC_1

ESPI

ESPI

Displayport

DDI PORT# DESTINATION

DDI

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

1

2

Deciphered Date

Deciphered Date

Deciphered Date

USB Type-C Port-B

USB Type-C Port-A

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Symbol Note :

: means de-pop

@

: means Digital Ground

: means Analog Ground

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P04-Notes List

P04-Notes List

P04-Notes List

Document Number Re v

Document Number Re v

Document Number Re v

LA-F371P

LA-F371P

LA-F371P

4 65Tuesday, November 07, 2017

4 65Tuesday, November 07, 2017

4 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

Functional Strap Definitions
GPP_E19 (Internal Pull Down): DDPB_CTRLDATA
0 = Port B is not detected.
1 = Port B is detected.
GPP_E21 (Internal Pull Down): DDPC_CTRLDATA
0 = Port C is not detected.
1 = Port C is detected.

D D

Type-C PortB

Type-C PortA

+3VS

CPU_DP2_CTRL_CLK

RC43 2.2K_0402_5%

RC45 2.2K_0402_5%

RC178 2.2K_0402_5%

RC179 2.2K_0402_5%

+3V_PRIM

RC199

C C

UFCAM_CSI2_DN033
UFCAM_CSI2_DP033
UFCAM_CSI2_DN133
UFCAM_CSI2_DP133

WFCAM_CSI2_DN433
WFCAM_CSI2_DP433
WFCAM_CSI2_DN533
WFCAM_CSI2_DP533
WFCAM_CSI2_DN633
WFCAM_CSI2_DP633
WFCAM_CSI2_DN733
WFCAM_CSI2_DP733

B B

DDR Memory Conf i gura t i no Type Str ap pin

+1.8VA

GPIO Pin

A A

GPP_ F1 3

GPP_ F1 4

GPP_ F1 5

GPP_ F1 6 MEM_C ONF IG 3

Pin Name

MEM_C ON FI G0

MEM_C ON FI G1

MEM_C ON FI G2

12

CPU_DP2_CTRL_DATA

12

CPU_DP1_CTRL_CLK

12

CPU_DP1_CTRL_DATA

12

1 2

@

@

@

MEDIACARD_IRQ#

10K_0402_5%

UCPU1I

@

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL-U_BGA1356

RH17

RH15 10K_0402_5%

RH12 10K_0402_5%

RH9 10K_0 402_5%

12

12

12

12

Micron
8G

10K_0402_5%@

0

1866 Mb ps

000

0 0 0 0 0 0 0

5

SKL_U LT

Micron

Mircon

16G

32G

0 1

1

0 1

0

+1.0VS_VCCIO

PVT-010
Add R3 CPN CPU

UCPU1

SR3L9@

R3 R3

SA0000AWS2L

i5 vpro R

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

MEM_CONFIG3

Hynix

Hynix

Hynix

32G

16G

8G

01

0

1

0

0 11

CAD Note:Trace width=20 mils, Isolat i on Spaci ng=25 mil,
Max length=100 mils.

PVT-010
Add R3 CPN CPU

UCPU1

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

EMMC_RCOMP

9 OF 20

RH18

RH16 10K_0402_5%

@

RH13 10K_0402_5%

@

RH10 10K_0402_5%

@

Samsun g

Samsun g

16G

8G

1

0

1

1

1

1

0

4

DDI1_P2_TXN037
DDI1_P2_TXP037
DDI1_P2_TXN137
DDI1_P2_TXP137
DDI1_P2_TXN237
DDI1_P2_TXP237
DDI1_P2_TXN337
DDI1_P2_TXP337

PCH_DDI2_N03 7
PCH_DDI2_P037
PCH_DDI2_N13 7
PCH_DDI2_P137
PCH_DDI2_N23 7
PCH_DDI2_P237
PCH_DDI2_N33 7
PCH_DDI2_P337

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

1 2

RC108 24.9_0402_1%

COMPENSATION PU FOR eDP

4+2 CPU Option

UCPU1

SR3LB@

SA0000AWB3L

i5 Nvpro R

C37
D37
C32
D32
C29
D29
B26
A26

E13

@

B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

Samsun g
32G

0

0

2133 Mb ps

0

1

CSI2_COMP

RC197

MEM_CONFIG0
MEM_CONFIG1
MEM_CONFIG2
MEM_CONFIG3

GNSS_OFF#

USH_DET#
GNSS_IRQ
WWAN_PWR_OFF#

EMMC_RCOMP

12

10K_0402_5%@

12

12

12

4

QNEG@

SA0000AWB1L

i5 Nvpro R

UFCAM_CSI2_CLKN0 33
UFCAM_CSI2_CLKP0 33
WFCAM_CSI2_CLKN1 33
WFCAM_CSI2_CLKP133

RC114

1 2

1 2

0_0402_5%

1 2

RC66 200_0402_1%

Samsun g

Mircon

Hynix

32G

32G

32G

1

0

0

111

0

0

1

1 1

E55
F55
E58
F58
F53

G53

F56

G56

C50
D50
C52
D52
A50
B50
D51
C51

L13
L12

N7
N8

N11

EDP_COMP

GNSS_OFF# 25

USH_DET# 41,43
GNSS_IRQ 25
WWAN_PWR_OFF# 25

N12

E52

UCPU1

QNBE@

SA0000AWR0L

i7 vpro R

100_0402_1%

MEDIACARD_IRQ# 27

Mircon

Hynix

16G

16G

1 0

0

0 0

0

1 1

1 1 1

3

UCPU1A

@

DDI1_TXN[0]
DDI1_TXP[0]
DDI1_TXN[1]
DDI1_TXP[1]
DDI1_TXN[2]
DDI1_TXP[2]
DDI1_TXN[3]
DDI1_TXP[3]

DDI2_TXN[0]
DDI2_TXP[0]
DDI2_TXN[1]
DDI2_TXP[1]
DDI2_TXN[2]
DDI2_TXP[2]
DDI2_TXN[3]
DDI2_TXP[3]

GPP_E18/DDPB_CTRLCLK
GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK
GPP_E21/DDPC_CTRLDATA

GPP_E22/DDPD_CTRLCLK
GPP_E23/DDPD_CTRLDATA

EDP_RCOMP

SKL-U_BGA1356

SKL-U

DDI

DISPLAY SIDEBANDS

EDP

1 OF 20

SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0

PVT-010
Add R3 CPN CPU

R3

SR3JY@

UCPU1
i3 NVPro

SA0000B2Y1L

DRAM Option (R1) , R3 check P08

Micron 8G/1866

MICRON_8G@

UD1

MT52L256M32D1PF-107WT

SA00009XU0L

Micron 16G/1866

MICRON_16G@

UD1

MT52L512M32D2PF-107WT

SA00009U70L

Micron 32G/1866

MICRON_32G@

UD1

MT52L1G32D4PG-107WT

SA00009XV0L

Hynix 8G/1866

HYNIX_8G@

UD1

H9CCNNN8GTMLAR-NUD FBGA

SA00008G64L

Hynix 16G/1866

HYNIX_16G@

UD1

H9CCNNNBJTMLAR-NU D FBGA

SA00008FJ4L

Hynix 32G/1866

HYNIX_32G@

UD1

H9CCNNNCLTMLAR-NU D FBGA

SA0000AEN0L

Samsung 8G/1866

SAMSUNG_8G@

UD1

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

Samsung 16G/1866

SAMSUNG_16G@

UD1

K4E6E304EB-EGCF FBGA17

SA00008QV2L

Samsung 32G/1866

SAMSUNG_32G@

UD1

4EBE304EB-EGCF FBGA178

SA00008X10L

Issued Date

Issued Date

Issued Date

3

Samsun g
16G

1

1

UCPU1

QNEE@

SA0000AWS0L

i5 vpro R

X76

X7669231L05

X7669231L07

X7669231L09

X7669231L06

X7669231L08

X7669231L10

X76_8G@

X768G
X76

X7669231L01

X7669231L01

X76_16G@

X7616G
X76

X7669231L02

X7669231L02

X76_32G@

X7632G
X76

X7669231L03

X7669231L03

Security Cl assification

Security Cl assification

Security Cl assification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

C47

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2

GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

G50
F50
E48
F48
G46
F46

L9
L7
L6
N9
L10

R12
R11
U13

CPU_DP1_HPD
CPU_DP2_HPD
I2C0_IRQ_TS
WLAN_RST#
EDP_HPD

eDP_TXN_P0 22
eDP_TXP_P0 22
eDP_TXN_P1 22
eDP_TXP_P1 22

eDP_AUXN 22
eDP_AUXP 22

PCH_DDI1_AUXN 36,37
PCH_DDI1_AUXP 36,37
PCH_DDI2_AUXN 35,37
PCH_DDI2_AUXP 35,37

@

PAD~D

@

PAD~D

CPU_DP1_HPD 30,36,37
CPU_DP2_HPD 30,35,37

I2C0_IRQ_TS 22
WLAN_RST# 24

EDP_HPD 22

PANEL_BKLEN 22
EDP_BIA_PWM 22
PCH_ENVDD 22

2+2 CPU Option

QNB1@

UCPU1
i3 NVPro

SA0000B2Y0L

MICRON_8G@

UD2

MT52L256M32D1PF-107W T

SA00009XU0L

MICRON_16G@

UD2

MT52L512M32D2PF-107W T

SA00009U70L

MICRON_32G@

UD2

MT52L1G32D4PG-107WT

SA00009XV0L

HYNIX_8G@

UD2

H9CCNNN8GTMLAR-NUD FBGA

SA00008G64L

HYNIX_16G@

UD2

H9CCNNNBJTMLAR-NU D FBGA

SA00008FJ4L

HYNIX_32G@

UD2

H9CCNNNCLTMLAR-NU D FBGA

SA0000AEN0L

SAMSUNG_8G@

UD2

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

SAMSUNG_16G@

UD2

K4E6E304EB-EGCF FBGA17

SA00008QV2L

SAMSUNG_32G@

UD2

4EBE304EB-EGCF FBGA178

SA00008X10L

Compal Secret Data

Compal Secret Data

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

SR343@

UCPU1
i3 NVPro

SA0000A387L

MICRON_8G@

UD3

MT52L256M32D1PF-107WT

SA00009XU0L

MICRON_16G@

UD3

MT52L512M32D2PF-107WT

SA00009U70L

MICRON_32G@

UD3

MT52L1G32D4PG-107WT

SA00009XV0L

HYNIX_8G@

UD3

H9CCNNN8GTMLAR-NUD FBGA

SA00008G64L

HYNIX_16G@

UD3

H9CCNNNBJTMLAR-NU D FBGA

SA00008FJ4L

HYNIX_32G@

UD3

H9CCNNNCLTMLAR-NU D FBGA

SA0000AEN0L

SAMSUNG_8G@

UD3

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

SAMSUNG_16G@

UD3

K4E6E304EB-EGCF FBGA17

SA00008QV2L

SAMSUNG_32G@

UD3

4EBE304EB-EGCF FBGA178

SA00008X10L

2

2Lane eDP

T6
T5

SR342@

UCPU1
i5 NVPro

SA0000A377L

MICRON_8G@

UD4

MT52L256M32D1PF-107WT

SA00009XU0L

MICRON_16G@

UD4

MT52L512M32D2PF-107WT

SA00009U70L

MICRON_32G@

UD4

MT52L1G32D4PG-107WT

SA00009XV0L

HYNIX_8G@

UD4

H9CCNNN8GTMLAR-NUD FBGA

SA00008G64L

HYNIX_16G@

UD4

H9CCNNNBJTMLAR-NU D FBGA

SA00008FJ4L

HYNIX_32G@

UD4

H9CCNNNCLTMLAR-NU D FBGA

SA0000AEN0L

SAMSUNG_8G@

UD4

K4E8E324EB-EGCF FBGA178P

SA00009XY0L

SAMSUNG_16G@

UD4

K4E6E304EB-EGCF FBGA17

SA00008QV2L

SAMSUNG_32G@

UD4

4EBE304EB-EGCF FBGA178

SA00008X10L

1

+3VS

I2C0_IRQ_TS

WLAN_RST#

GNSS_IRQ
USH_DET#

GNSS_OFF#

EDP_HPD

CPU_DP1_HPD

CPU_DP2_HPD

SR340@

UCPU1
i5 Vpro

SA0000ADO2L

DRAM Config Option

(Resistor pop location)

MEM_CONFIG0

X76_M8G@

RH18

10K_0402_5%

SD028100280

X76_M16G@

RH17

10K_0402_5%

SD028100280

X76_M32G@

RH18

10K_0402_5%

SD028100280

X76_H8G@

RH17

10K_0402_5%

SD028100280

X76_H16G@

RH18

10K_0402_5%

SD028100280

X76_H32G@

RH17

10K_0402_5%

SD028100280

X76_S8G@

RH18

10K_0402_5%

SD028100280

X76_S16G@

RH17

10K_0402_5%

SD028100280

X76_S32G@

RH18

10K_0402_5%

SD028100280

RC194 100K_0201_5%

RH505

RH8 10K_0201_5%

@

RH7 100K_0201_5%
RH5

RC126 100K_0402_5%

RC124 100K_0402_5%

RC46 100K_0402_5%

@SR33Z@

UCPU1
i7 VPro

SA0000ADP2L

MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3

X76_M8G@

RH16

10K_0402_5%

SD028100280

X76_M16G@

RH16

10K_0402_5%

SD028100280

X76_M32G@

RH15

10K_0402_5%

SD028100280

X76_H8G@

RH15

10K_0402_5%

SD028100280

X76_H16G@

RH16

10K_0402_5%

SD028100280

X76_H32G@

RH16

10K_0402_5%

SD028100280

X76_S8G@

RH15

10K_0402_5%

SD028100280

X76_S16G@

RH15

10K_0402_5%

SD028100280

X76_S32G@

RH16

10K_0402_5%

SD028100280

1 2

1 2
1 2
1 2

X76_M8G@

RH13

10K_0402_5%

SD028100280

X76_M16G@

RH13

10K_0402_5%

SD028100280

X76_M32G@

RH13

10K_0402_5%

SD028100280

X76_H8G@

RH13

10K_0402_5%

SD028100280

X76_H16G@

RH12

10K_0402_5%

SD028100280

X76_H32G@

RH12

10K_0402_5%

SD028100280

X76_S8G@

RH12

10K_0402_5%

SD028100280

X76_S16G@

RH12

10K_0402_5%

SD028100280

X76_S32G@

RH13

10K_0402_5%

SD028100280

12

10K_0201_5%

10K_0201_5%

12

12

12

+1.8VA

+3VS

X76_M8G@

RH10

10K_0402_5%

SD028100280

X76_M16G@

RH10

10K_0402_5%

SD028100280

X76_M32G@

RH10

10K_0402_5%

SD028100280

X76_H8G@

RH10

10K_0402_5%

SD028100280

X76_H16G@

RH10

10K_0402_5%

SD028100280

X76_H32G@

RH10

10K_0402_5%

SD028100280

X76_S8G@

RH10

10K_0402_5%

SD028100280

X76_S16G@

RH10

10K_0402_5%

SD028100280

X76_S32G@

RH9

10K_0402_5%

SD028100280

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P05-MCP(1/14)DDI,EDP,CSI2,EMMC

P05-MCP(1/14)DDI,EDP,CSI2,EMMC

P05-MCP(1/14)DDI,EDP,CSI2,EMMC

LA-F371P

LA-F371P

LA-F371P

1

5 65Tuesday, November 07, 2017

5 65Tuesday, November 07, 2017

5 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

4

3

2

1

LPDDR3, Ballout for side by side(Non-Interleave)

DDR_A_DQS#[0..7]19

DDR_A_DQS[0..7]19

DDR_A_D[0..63]19

DDR_A_CA1_[0..9]19,21

DDR_A_CA2_[0..9]19,21

D D

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42

C C

B B

DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

UCPU1B

@

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356

DDR_B_DQS#[0..7]20

DDR_B_DQS[0..7]20

DDR_B_D[0..63]20

DDR_B_CA1_[0..9]20,21

DDR_B_CA2_[0..9]20,21

SKL-U

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]

DDR0_ODT[0]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

DDR0_ODT[1]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_ALERT#

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

2 OF 20

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26

AW50
AT52

AY67
AY68
BA67

AW67

DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1

DDR_A_CKE0
DDR_A_CKE1
DDR_A_CKE2
DDR_A_CKE3

DDR_A_CS#0
DDR_A_CS#1

DDR_A_ODT0

DDR_VTT_CNTL

DDR_A_CLK#0 19,21
DDR_A_CLK0 19,21
DDR_A_CLK#1 19,21
DDR_A_CLK1 19,21

DDR_A_CKE0 19,21
DDR_A_CKE1 19,21
DDR_A_CKE2 19,21
DDR_A_CKE3 19,21

DDR_A_CS#0 19,21
DDR_A_CS#1 19,21
DDR_A_ODT0 19,21

DDR_A_CA1_0 19,21
DDR_A_CA1_1 19,21
DDR_A_CA1_2 19,21
DDR_A_CA1_3 19,21
DDR_A_CA1_4 19,21
DDR_A_CA1_5 19,21
DDR_A_CA1_6 19,21
DDR_A_CA1_7 19,21
DDR_A_CA1_8 19,21
DDR_A_CA1_9 19,21

DDR_A_CA2_0 19,21
DDR_A_CA2_1 19,21
DDR_A_CA2_2 19,21
DDR_A_CA2_3 19,21
DDR_A_CA2_4 19,21
DDR_A_CA2_5 19,21
DDR_A_CA2_6 19,21
DDR_A_CA2_7 19,21
DDR_A_CA2_8 19,21
DDR_A_CA2_9 19,21

DDR_A_DQS#0 19
DDR_A_DQS0 19
DDR_A_DQS#1 19
DDR_A_DQS1 19
DDR_A_DQS#4 19
DDR_A_DQS4 19
DDR_A_DQS#5 19
DDR_A_DQS5 19
DDR_B_DQS#0 20
DDR_B_DQS0 20
DDR_B_DQS#1 20
DDR_B_DQS1 20
DDR_B_DQS#4 20
DDR_B_DQS4 20
DDR_B_DQS#5 20
DDR_B_DQS5 20

+V_DDR_REF_CA 21
+V_DDR_REFA_R 21
+V_DDR_REFB_R 21

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UCPU1C

@

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

3 OF 20

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1

DDR_B_ODT0

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDR_B_CLK#0 20,21
DDR_B_CLK#1 20,21
DDR_B_CLK0 20,21
DDR_B_CLK1 20,21

DDR_B_CKE0 20,21
DDR_B_CKE1 20,21
DDR_B_CKE2 20,21
DDR_B_CKE3 20,21

DDR_B_CS#0 20,21
DDR_B_CS#1 20,21
DDR_B_ODT0 20,21

DDR_B_CA1_0 20,21
DDR_B_CA1_1 20,21
DDR_B_CA1_2 20,21
DDR_B_CA1_3 20,21
DDR_B_CA1_4 20,21
DDR_B_CA1_5 20,21
DDR_B_CA1_6 20,21
DDR_B_CA1_7 20,21
DDR_B_CA1_8 20,21
DDR_B_CA1_9 20,21

DDR_B_CA2_0 20,21
DDR_B_CA2_1 20,21
DDR_B_CA2_2 20,21
DDR_B_CA2_3 20,21
DDR_B_CA2_4 20,21
DDR_B_CA2_5 20,21
DDR_B_CA2_6 20,21
DDR_B_CA2_7 20,21
DDR_B_CA2_8 20,21
DDR_B_CA2_9 20,21

DDR_A_DQS#2 19
DDR_A_DQS2 19
DDR_A_DQS#3 19
DDR_A_DQS3 19
DDR_A_DQS#6 19
DDR_A_DQS6 19
DDR_A_DQS#7 19
DDR_A_DQS7 19
DDR_B_DQS#2 20
DDR_B_DQS2 20
DDR_B_DQS#3 20
DDR_B_DQS3 20
DDR_B_DQS#6 20
DDR_B_DQS6 20
DDR_B_DQS#7 20
DDR_B_DQS7 20

@

T36

PAD~D

+1.2V_DDR

NC

A

GND

VCC

UC1

5

4

Y

1

CC15

0.1U_0402_10V7K

2

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

12

R32
100K_0402_5%

SM_PG_CTRL 53

Compal Secret Data

Compal Secret Data

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

LPDDR3 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

1 2

RC164 200_0402_1%

RC166 80.6_0402_1%

1 2

RC165 162_0402_1%

1 2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P06-MCP(2/14)LPDDR3

P06-MCP(2/14)LPDDR3

P06-MCP(2/14)LPDDR3

LA-F371P

LA-F371P

LA-F371P

1

6 65Tuesday, November 07, 2017

6 65Tuesday, November 07, 2017

6 65Tuesday, November 07, 2017

1.0

1.0

1.0

DDR_VTT_CNTL

1

2

3

74AUP1G07GW_TSSOP5

Use SA00005U600

A A

5

4

PCH_SPI_DO_XDP13
PCH_SPI_DO2_XDP13

+1.8V_ESPI

TPM_PIRQ#8,31

5

ESPI_ALERT#

SIO_RCIN#

PVT-048

De-pop debug XDP related compoments

RC67 1K_0402_5%@XDP@ 1 2
RC69 1K_0402_5%@XDP@

1 2

RC198

@

1 2

PCH_SPI_CS2#31

TC1

0_0201_5%

ESPI_ALERT#30

CL_CLK24
CL_DATA24
CL_RST#24

SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236

PCH_SPI_CLK
PCH_SPI_SO
PCH_SPI_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#
PCH_SPI_CS1#

SIO_RCIN#

ESPI_ALERT#

PVT-023

Change 0 ohm to short pad

+1.8VA

R513

1 2

@

0_0201_5%

D D

+1.8V_ESPI

1 2

RC83 10K_0402_5%

+1.8V_PGPP

@

1 2

RC73 10K_0402_5%

+3.3V_SPI

CC90

C C

PCH_SPI_CS0#

SPI_SO_VROM1

SPI_IO2_VROM1

128Mb Flash ROM

UH1

1

CS#

2

HOLD#_RESET#

DO

3

WP#

4

GND

ThemalPad

W25Q128JVEIQ_WSON8_8X6

VCC

8
7
6

CLK

5

DI

9

1 2

0.1U_0402_25V6

SPI_IO3_VROM1

SPI_CLK_VROM1

SPI_SI_VROM1

AW3

AW2
AU4
AU3
AU2
AU1

AW13

AY11

AV2

AV3

M2
M3

J4
V1
V2

M1

G3
G2
G1

4

UCPU1E

@

SPI - FLASH

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-U_BGA1356

SKL-U

SMBUS, SMLINK

LPC

GPP_A14/SUS_STAT#/ESPI_RESET#

3

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

5 OF 20

SPI_SI_VROM1

PCH_SPI_CLK_TPM31
PCH_SPI_SI_TPM31

PCH_SPI_SO_TPM31

SPI_CLK_VROM1

SPI_SO_VROM1
SPI_IO2_VROM1
SPI_IO3_VROM1

DDR_XDP_SMBCLK

R7

DDR_XDP_SMBDAT

R8

PCH_SMB_ALERT#

R10

R9
W2

GPP_C5

W1

SML1_SMBCLK

W3

SML1_SMBDAT

V3

GPP_B23

AM7

AY13
BA13
BB13
AY12
BA12
BA11

PCI_CLK_LPC0

AW9

PCI_CLK_LPC1

AY9
AW11

CLKRUN#

RP2

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

RP3

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

RFQ-034

change LPC to ESPI mode

ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R

PCH_SPI_SO

PCH_SPI_IO2
PCH_SPI_IO3

DDR_XDP_SMBCLK 13
DDR_XDP_SMBDAT 13

SML1_SMBCLK 30
SML1_SMBDAT 30

RC383 15_0402_5%1 2
RC384 15_0402_5%

1 2

RC385 15_0402_5%

1 2

RC386 15_0402_5%

1 2

ESPI_CS# 30,43

ESPI_RESET# 30

RC71 15_0402_5%

1 2
1 2

RC70 22_0402_5%@

PCH_SPI_SI

PCH_SPI_CLK

2

SPI_CLK_VROM1

33_0402_5%

RC169@

1 2

33P_0402_50V8J

CC91@

1 2

ESPI_IO0 30,43
ESPI_IO1 30,43
ESPI_IO2 30,43
ESPI_IO3 30,43

ESPI_CLK 30,43

ESPI_CLK

Reserve for RF

DDR_XDP_SMBDAT

DDR_XDP_SMBCLK

CLKRUN#

SML1_SMBCLK

SML1_SMBDAT

1

12

EMC@12P_0402_50V8J

CC78

12

RN12.2K_0402_5%

12

RN22.2K_0402_5%

12

@

RC828.2K_0402_5%

+3V_PRIM

1 2

RC55 1K_0402_5%

1 2

RC51 1K_0402_5%

change RC49 to 2.2k

PCH_SMB_ALERT#

RC49 2.2K_0402_5%

TLS C ONFIDENTIALITY

HIGH
LOW(DEFAULT)

+3VS

1 2

ENABLE
DISAB LE

+3V_PRIM

+3V_PRIM

GPP_C5

+3V_PRIM

RH19 1K_0402_ 5%~D

1 2

B B

SPI debug conn

PCH_SPI_CS1#
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_IO2

+3.3V_SPI

+3V_PRIM

A A

PCH_SPI_IO3

JSPI2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_50521-01041-P01

CONN@

PCH SPI

PVT-023

Change 0 ohm to short pad

RC170

@

9/5 MOW
Opt i on 1: I mpl e ment a 1 k Oh m pull - down r esi st or on t he si gnal and de- popul at e

the
required 1 kOhm pull-up resistor(MOW WW5).
In this case, customers must ensure that the SPI
f l ash devi ce on t he pl a t fo r m has HOLD f unct i onal i t y di sabl ed by default.

Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y plat f or ms
with ES and SKL S/H plat f or ms wi t h pre-ES 1/ ES1 s a mpl es( MO W W W9).

+3.3V_SPI+3V_PRIM

12

@

RH20 1K_0402_ 5%~D

1 2

@

RH21 1K_0402_ 5%~D

1 2

@

PCH_SPI_IO2

PCH_SPI_IO3

PCH_SPI_IO3

EC interface

HIGH
LOW(DEFAULT)

GPP_B23

EXI BOOT STALL BYPASS

HIGH
LOW(DEFAULT)

1 2

RC58 4.7K_0201_5%

ESPI

LPC

+3V_PRIM

1 2

RC64 150K_0201_1%@

ENABLE
DISAB LE

0_0402_1%

TPM

Security Cl assification

Security Cl assification

JSPI

5

4

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P07-MCP(3/14)SPI,SMB,LPC

P07-MCP(3/14)SPI,SMB,LPC

P07-MCP(3/14)SPI,SMB,LPC

LA-F371P

LA-F371P

LA-F371P

1

7 65Tuesday, November 07, 2017

7 65Tuesday, November 07, 2017

7 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

+3VS

HOST_SD_WP#

1 2

RC56

10K_0402_5%

UART2_TXD

1 2

D D

C C

RH3 49.9K_0201_1%

RH4 49.9K_0201_1%

RC190 49.9K_0402_1%

RC191 49.9K_0402_1%

+3V_PRIM

RC180

RC181

RC396

@

RC149

+3VS_TS

RC48 4.7K_0402_5%

RC50 4.7K_0402_5%

+3V_PRIM

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

RC63 2.2K_0201_5%@

UART2_RXD

UART2_RTS#

UART2_CTS#

TPM_PIRQ#7,31

10K_0201_5%

10K_0201_5%

100K_0201_5%

10K_0402_5%

I2C1_SDA_TS

I2C1_SCK_TS

NRB_BIT

RC196

1 2

EDP_CAB_DET#

WWAN_RST#

PCH_3.3V_TS_EN

SIO_EXT_SCI#

RC398

RC399

@

1 2

@

1 2

0_0201_5%

0_0201_5%

0_0201_5%

UART2_RTS#

I2C1_SDA_TS
I2C1_SCK_TS
SKYCAM_I2C_DATA
SKYCAM_I2C_CLK
UF_I2C_DATA
UF_I2C_CLK

SKYCAM_I2C_DATA34
SKYCAM_I2C_CLK34

NO REBOOT STRAP

HIGH

B B

LOW(DEFAULT)
Weak IPD

+3V_PRIM

12

RC65

@

2.2K_0201_5%

GPP_B22

No REBOOT

REBOOT ENABLE

ACCEL_INT1#

ACCEL_INT2#

KICKSTD_SW_DET#_PCH

ALS_I2C1_ALERT#_PCH

BOOT BIOS Destination(Bit 6)

HIGH
LOW(DEFAULT)

Internal PD 20K

A A

LPC
SPI

TS_ID0 TS_ID0_M

RB751S40T1G_SOD523-2

PCB footprint
RB520SM-30 T2R_EMD2 -2

5

12

D112

DII-DMN65D8LW-7

4

EDP_CAB_DET#22

PCH_3.3V_TS_EN44

DEBUG_UART0_TX30

HOST_SD_WP#27

UART2_RXD43
UART2_TXD43
UART2_RTS#43
UART2_CTS#43

TS_RST#22

I2C1_SDA_TS22
I2C1_SCK_TS22

UF_I2C_DATA33
UF_I2C_CLK33

33P_0402_50V8J

33P_0402_50V8J

12

12

CC98@EMC@

12

D107

RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

+3VS_TS +3VS_TS

1 3

D

Q351

2

G

12

D108

12

D109

12

D110

RC393

100K_0201_5%

S

4

EDP_CAB_DET#
TPM_PIRQ#_R
NRB_BIT

SIO_EXT_SCI#

GPP_B22

WWAN_RST#

HOST_SD_WP#

UART2_RXD
UART2_TXD
UART2_RTS#
UART2_CTS#

TS_RST#
GPP_C17

I2C1_SDA_TS
I2C1_SCK_TS

SKYCAM_I2C_DATA
SKYCAM_I2C_CLK

UF_I2C_DATA
UF_I2C_CLK

33P_0201_50V8J

@EMC@

1

2

CC13

CC99@EMC@

PCB footprint
RB520SM-30 T2R_EMD2 -2

PCB footprint
RB520SM-30 T2R_EMD2 -2

PCB footprint
RB520SM-30 T2R_EMD2 -2

PCB footprint
RB520SM-30 T2R_EMD2 -2

12

UCPU1F

@

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKL-U_BGA1356

33P_0201_50V8J

@EMC@

1

2

CC7

TS_ID0_D 22

33P_0201_50V8J

1

2

33P_0201_50V8J

@EMC@

1

2

CC11

ACCEL_INT1#_D 31

ACCEL_INT2#_D 31

KICKSTD_SW_DET# 30,42

ALS_I2C1_ALERT# 33

3

LPSS ISH

X76

@EMC@

X7669231L56

CC8

X7669231L52

X7669231L54

X7669231L51

X7669231L53

X7669231L55

X76_8G_R3@

X768G3
X76

X7669231L57

X7669231L57

X76_16G_R3@

X7616G3
X76

X7669231L58

X7669231L58

X76_32G_R3@

X7632G3
X76

X7669231L59

X7669231L59

SKL-U

GPP F group

1.8V only

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SD A

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP F group

1.8V only

DRAM Option (R3)

Micron 8G/1866

MICRON_8G_R3@

UD1

MT52L256M32D1PF-107WT

SA00009XU1L

Micron 16G/1866

MICRON_16G_R3@

UD1

MT52L512M32D2PF-107WT

SA00009U71L

Micron 32G/1866

MICRON_32G_R3@

UD1

MT52L1G32D4PG-107WT

SA00009XV1L

Hynix 8G/1866

HYNIX_8G_R3@

UD1

H9CCNNN8GTMLAR-NUD FBGA

SA00008G65L

Hynix 16G/1866

HYNIX_16G_R3@

UD1

H9CCNNNBJTMLAR-NU D FBGA

SA00008FJ5L

Hynix 32G/1866

HYNIX_32G_R3@

UD1

H9CCNNNCLTMLAR-NU D FBGA

SA0000AEN1L

Samsung 8G/1866

SAMSUNG_8G_R3@

UD1

K4E8E324EB-EGCF FBGA178P

SA00009XY1L

Samsung 16G/1866

SAMSUNG_16G_R3@

UD1

K4E6E304EB-EGCF FBGA17

SA00008QV3L

Samsung 32G/1866

SAMSUNG_32G_R3@

UD1

4EBE304EB-EGCF FBGA178

SA00008X11L

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

MT52L256M32D1PF-107W T

MT52L512M32D2PF-107W T

MT52L1G32D4PG-107WT

H9CCNNN8GTMLAR-NUD FBGA

H9CCNNNBJTMLAR-NU D FBGA

H9CCNNNCLTMLAR-NU D FBGA

K4E8E324EB-EGCF FBGA178P

K4E6E304EB-EGCF FBGA17

4EBE304EB-EGCF FBGA178

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

MICRON_8G_R3@

UD2

SA00009XU1L

MICRON_16G_R3@

UD2

SA00009U71L

MICRON_32G_R3@

UD2

SA00009XV1L

HYNIX_8G_R3@

UD2

SA00008G65L

HYNIX_16G_R3@

UD2

SA00008FJ5L

HYNIX_32G_R3@

UD2

SA0000AEN1L

SAMSUNG_8G_R3@

UD2

SA00009XY1L

SAMSUNG_16G_R3@

UD2

SA00008QV3L

SAMSUNG_32G_R3@

UD2

SA00008X11L

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

6 OF 20

MT52L256M32D1PF-107WT

MT52L512M32D2PF-107WT

MT52L1G32D4PG-107WT

H9CCNNN8GTMLAR-NUD FBGA

H9CCNNNBJTMLAR-NU D FBGA

H9CCNNNCLTMLAR-NU D FBGA

K4E8E324EB-EGCF FBGA178P

K4E6E304EB-EGCF FBGA17

4EBE304EB-EGCF FBGA178

DDR_CHB_EN

P2

DDR_CHA_EN

P3

AR_DET#

P4

CPU_DET#

P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

MICRON_8G_R3@

UD3

SA00009XU1L

MICRON_16G_R3@

UD3

SA00009U71L

MICRON_32G_R3@

UD3

SA00009XV1L

HYNIX_8G_R3@

UD3

SA00008G65L

HYNIX_16G_R3@

UD3

SA00008FJ5L

HYNIX_32G_R3@

UD3

SA0000AEN1L

SAMSUNG_8G_R3@

UD3

SA00009XY1L

SAMSUNG_16G_R3@

UD3

SA00008QV3L

SAMSUNG_32G_R3@

UD3

SA00008X11L

2

ISH_I2C0_SDA 31

ISH_I2C0_SCL 31

ALS_I2C1_SDA 33

ALS_I2C1_SCL 33

ACCEL_INT1#
ACCEL_INT2#
TS_ID0

ALS_I2C1_ALERT#_PCH

PAD~D

3.3V_CAM_EN 34

MICRON_8G_R3@

UD4

MT52L256M32D1PF-107WT

SA00009XU1L

MICRON_16G_R3@

UD4

MT52L512M32D2PF-107WT

SA00009U71L

MICRON_32G_R3@

UD4

MT52L1G32D4PG-107WT

SA00009XV1L

HYNIX_8G_R3@

UD4

H9CCNNN8GTMLAR-NUD FBGA

SA00008G65L

HYNIX_16G_R3@

UD4

H9CCNNNBJTMLAR-NU D FBGA

SA00008FJ5L

HYNIX_32G_R3@

UD4

H9CCNNNCLTMLAR-NU D FBGA

SA0000AEN1L

SAMSUNG_8G_R3@

UD4

K4E8E324EB-EGCF FBGA178P

SA00009XY1L

SAMSUNG_16G_R3@

UD4

K4E6E304EB-EGCF FBGA17

SA00008QV3L

SAMSUNG_32G_R3@

UD4

4EBE304EB-EGCF FBGA178

SA00008X11L

2

KICKSTD_SW_DET#_PCH

ALS_I2C1_ALERT#_PCH

@

T15

KICKSTD_SW_DET#_PCH

1

+3VS

DDR_CHA_EN

DDR_CHB_EN

DDR_CHA_EN

DDR_CHB_EN

ACCEL_INT1#

ACCEL_INT2#

TS_ID0

TS_RST#

GPP_C17

RH30 100K_0402_5%~D

1 2

RH29 100K_0402_5%~D

1 2

RH31 SHORT PADS

1 2

@

RH28 SHORT PADS

1 2

@

RC182

1 2

RC183

1 2

RC192 100K_0201_5%

1 2

RC391 220K_0201_5%

1 2

RC392 100K_0201_5%1 2

RC205

1 2

RC206

1 2

+3V_PRIM

12

R5771

10K_0201_5%

AR_DET#

12

R5772

@

10K_0201_5%

+3V_PRIM

12

@U22@

R5775

10K_0201_5%

CPU_DET#

12

@U42@

R5776

10K_0201_5%

+1.8V_PGPP

10K_0201_5%

10K_0201_5%

+3V_PRIM

10K_0201_5%

10K_0201_5%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P08-MCP(4/14)GSPI,I2C,UART,ISH

P08-MCP(4/14)GSPI,I2C,UART,ISH

P08-MCP(4/14)GSPI,I2C,UART,ISH

LA-F371P

LA-F371P

LA-F371P

1

8 65Tuesday, November 07, 2017

8 65Tuesday, November 07, 2017

8 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

4

3

2

1

UCPU1H

@

PCIE/US B3/SATA

H13

D D

PCIE_PRX_WLANTX_N524

1 2

PCIE_PRX_WLANTX_P524
PCIE_PTX_WLANRX_N524
PCIE_PTX_WLANRX_P524

PCIE_PRX_SSDTX_N723
PCIE_PRX_SSDTX_P723
PCIE_PTX_SSDRX_N723
PCIE_PTX_SSDRX_P723

SATA_PRX_SSDTX_N823
SATA_PRX_SSDTX_P823
SATA_PTX_SSDRX_N823
SATA_PTX_SSDRX_P823

PCIE_PRX_CARDTX_N927
PCIE_PRX_CARDTX_P927
PCIE_PTX_CARDRX_N927
PCIE_PTX_CARDRX_P927

1 2

RC113 100_0402_1%

CPU_XDP_PRDY#13
CPU_XDP_PREQ#13

PCIE_PRX_WWANTX_N1125
PCIE_PRX_WWANTX_P1125
PCIE_PTX_WWANRX_N1125
PCIE_PTX_WWANRX_P1125
PCIE_PRX_WWANTX_N1225
PCIE_PRX_WWANTX_P1225
PCIE_PTX_WWANRX_N1225
PCIE_PTX_WWANRX_P1225

PCIE_RCOMPN
PCIE_RCOMPP

WLAN
PCIe Gen2 x 1

C C

PCIe SSD

SATA SSD

Cardreade r
PCIe Gen2 x 1

+1.8V_PGPP

@

RC72 10K_0402_5%

M.2 2242
WWAN 2nd
SSD SATA/PCIe 2 Lane ony 4/14

B B

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-U_BGA1356

SKL-U

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

SIO_SLP_S0#10,31,45,56,57

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN

USB3_1_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN

USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

8 OF 20

PRIM_CORE_OPT_DIS

SIO_SLP_S0#

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6

USBCOMP
OTG_ID

AG3
AG4

VBUSSENSE

USB_OC0#

A9

USB_OC1#

C9

USB_OC2#

D9

PRIM_CORE_OPT_DIS

B9

J1

SIO_EXT_WAKE#

J2
J3

H2

GPP_E1

H3
G4

H1

USB3RN1 37
USB3RP1 37
USB3TN1 37

USB3TP1 37

USB3RN2 25
USB3RP2 25
USB3TN2 25

USB3TP2 25

USB3RN3 39
USB3RP3 39
USB3TN3 39

USB3TP3 39

USB3RN4 37
USB3RP4 37
USB3TN4 37

USB3TP4 37

USB20_N1 35
USB20_P1 35

USB20_N2 43
USB20_P2 43

USB20_N3 36
USB20_P3 36

USB20_N4 25
USB20_P4 25

USB20_N5 43
USB20_P5 43

USB20_N7 24
USB20_P7 24

USB20_N9 39
USB20_P9 39

USB20_N10 43
USB20_P10 43

RC137 113_0402_1%

1 2

RC62

1 2

RC61 1K_0201_ 5%@

1 2

1 2

RC41

+3V_PRIM

U4252

5

1

2

MC74VHC1G32DFT2G_SC70-5

P

INB

4

O

INA

G

3

VR_LPM_R#

0_0201_5%

Type-C PortA

WWAN

USB3.0 Type-A

Type-C PortB

Type-C PortA

Dock

Type-C PortB

NGFF (WWAN)

IR Camera

NGFF (WLAN)

USB Type-A

USH

0_0201_5%

USB_OC2# 39

SSD_DEVSLP 23
SIO_EXT_WAKE# 30
WWAN_DEVSLP 2 5

m2280_PCIE_SATA# 23

m3042_PCIE#_SATA 30

VR_LPM_R# 56

PD1_OTG_ID 35
PD1_VBUS_SENSE 35

SIO_EXT_WAKE#

USB_OC0#

USB_OC1#

USB_OC2#

PRIM_CORE_OPT_DIS

m2280_PCIE_SATA#

GPP_E1

OTG_ID

VBUSSENSE

Type-C PortA

1 2

1 2

1 2

@

1 2

1 2

1 2
1 2

12

10K_0201_5%

12

10K_0402_5%

0_0201_5%

RC59 10K_0402_5%

RC13 10K_0402_5%

RC11 10K_0402_5%

RC14 10K_0402_5%

RC12 10K_0402_5%

RC195

@

RC204

RH90

@

RH91 1K_0201_5%

+3V_PRIM

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P09-MCP(5/14)PCIE,USB,SATA

P09-MCP(5/14)PCIE,USB,SATA

P09-MCP(5/14)PCIE,USB,SATA

LA-F371P

LA-F371P

LA-F371P

1

9 65Tuesday, November 07, 2017

9 65Tuesday, November 07, 2017

9 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

D D

WLAN--->

WWAN--->

SSD--->

Card Reader --->

CLK1_PCIE_WLAN#24
CLK1_PCIE_WLAN24
CLKREQ_PCIE#124

CLK2_PCIE_WWAN#25
CLK2_PCIE_WWAN25
CLKREQ_PCIE#225

CLK_PCIE_SSD#23
CLK_PCIE_SSD23
CLKREQ_PCIE#323

+3VS

+3VS

+3VS

+3VS

CLK_PCIE_MMI#27
CLK_PCIE_MMI27
CLKREQ_PCIE#527

+3VS

1 2

RC157 10K_0402_5%

1 2

RC153 10K_0402_5%

1 2

RC159 10K_0402_5%

@

1 2

RC168 10K_0402_5%

1 2

RC161 10K_0402_5%

+3.3V_ALW_DSW

C C

1 2

RC90 1K_0402_5%

1 2

RC143 10K_0402_5%

1 2

RC84 8.2K_0402_5%

+3VS

1 2

RC97@ 8.2K_0402_5%

PCH_PCIE_WAKE#

LAN_WAKE#

BATLOW#

ME_RESET#

PLT_RST#22,23,24,25,27,30,31,32,34,43

+1.0V_VCCST

H_VCCST_PWRGD_P

1 2

RC25 1K_0402_5%

+3V_PRIM

ME_SUS_PWR_AC K

1 2

RC162 10K_0402_5%@

H_VCCST_PWRGD_P13,32

PCH_RSMRST#_R

PCH_PWROK

@

T7

PAD~D

H_VCCST_PWRGD_PH_CPUPWRGD

100P_0402_50V8J~D

CA3

1

2

PCH_RSMRST#_R13,30

1 2

RC39 1K_0402_5%@

RC26 60.4_0402_1%

1 2

SYS_PWROK13,30

PCH_PWROK57

PCH_DPWROK_P30

ME_SUS_PWR_AC K30

PCH_PCIE_WAKE#30

LAN_WAKE#30

PCH_DPWROK_P

SUSACK#30

3.3V_IRCAM_EN#43

1 2

RC189 10K_0402_5%

1 2

B B

RC397 10K_0201_1%@

100P_0402_50V8J~D

CA4

1

2

ESD Request:place near CPU side

RC78

POP

NO Support Deep sleep

DE-POP

Support Deep sleep

PCH_DPWROK_P PCH_RSMRST#_R

A A

1

2

1 2

RC78 0_0402_5%@

0.01U_0402_16V7K

100K_0402_5%~D

12

CC16

RC80

5

XDP_DBRESET#13

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

4

UCPU1J

@

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356

RC152

100K_0402_5%

PCH_PLTRST#

SYS_RESET#
PCH_RSMRST#_R

H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPUH_VCCST_PWRGD_P

ME_SUS_PWR_ACK

PCH_PCIE_WAKE#
LAN_WAKE#

XDP_DBRESET#

4

CLOCK SIGNALS

1 2

RC150 0_0402_5%@

4

UCPU1K

O

SYSTEM POWER MANAGEMENT

ME_RESET#

12

12

@

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356

RC96@ 8.2K_0402_5%

SKL_U LT

+3VS

5

1

P

B

2

A

G

UC4

TC7SH08FU_SSOP5

3

SKL-U

1 2

RC34 0_0402_5%

+3VS

5

1

P

B

O

2

A

G

74AHC1G09GW_TSSOP5

3

3

1 2

SUSCLK

RC74 1K_0402_5%@

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

CLK_ITPXDP_N_R

F43

CLK_ITPXDP_P_R

E43

BA17

E37
E35

E42

AM18
AM20

AN18
AM16

SUSCLK

XTAL24_IN
XTAL24_OUT

XCLK_BIASREF

PCH_RTCX1
PCH_RTCX2

SRTCRST#

RTC_RST#

RC33 0_0402_5%

1 2

RC32 0_0402_5%1 2

SUSCLK 23,24,25

1 2

RC31 2.7K_0402_1%

RTC_RST# 30

+1.0V_CLK

CLK_ITPXDP_N 13
CLK_ITPXDP_P 13

CMOS1

RC154
10K_0402_5%

1 2

10 OF 20

PCH_PLTRST#

@

+RTCVCC

RC89 20K_0201_5%

RC85

1U_0402_6.3V6K

1 2

1 2

20K_0201_5%

CC22

1U_0402_6.3V6K

1

CC25

2

1

PDG_An RC delay circuit with a t i me del ay i n t he
range of 18– 25 ms shoul d be pr ovi ded.

2

The circuit should be connected to VCCRTC.

12

@

CLRP1
10K_0201_5%

SRTCRST#

1

1

SHORT PADS~D

@

2

2

CMOS1 must take care
short & touch risk on layout placement

INTRUDER#

+3.3V_ALW_DSW

VRALERT#

SLP_S0# for support connect stand by mode

8/21 CRB1 .0 change to 0603 1/10W

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#
SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B11/EXT_PWR_GATE#

INTRUDER#

GPP_B2/VRALERT#

11 OF 20

AC_PRESENT

SIO_SLP_S0#

AT11

SIO_SLP_S3#

AP15

SIO_SLP_S4#

BA16

SIO_SLP_S5#

AY16

AN15
AW15
BB17
AN16

BA15

AC_PRESENT

AY15
AU13

BATLOW#

AU11

PME#

AP16

INTRUDER#

AM10
AM11

VRALERT#

1 2

RC91 10K_0402_5%

SIO_SLP_S0# 9 ,31,45,56,57
SIO_SLP_S3# 3 0,32
SIO_SLP_S4# 3 0,32
SIO_SLP_S5# 3 0

SIO_SLP_SUS# 30,32,44,54,55,56

@

PAD~D

SIO_SLP_WLAN# 44
SIO_SLP_A# 30

SIO_PWRBTN# 10,13,30

AC_PRESENT 30

@

PAD~D

T26

T38

+3VS

12

RC38

10K_0402_5%

SYS_RESET#_R

4

UC3@

Security Cl assification

Security Cl assification

Security Cl assification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

RC36 1K_0402_5%

Issued Date

Issued Date

Issued Date

3

@

SYS_RESET#

Compal Secret Data

Compal Secret Data

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2

XTAL24_IN

XTAL24_OUT

PCH_RTCX1
PCH_RTCX2

RTC_RST#

RC88

1 2

RC60

1 2

1

RC380

U22@

1 2

U22@

RC86
10M_0402_5%

1 2

1 2

1M_0201_5%

1 2

33_0201_1%

RC381

1 2

33_0201_1%

RC87 0_0402_5%

RC35

U22@

PCH_RTCX2_R

3

4

YC1
24MHZ_12PF_7M24090001

1

2

12

YC2
9PF 20PPM 9H03280012

ESR MAX=50k ohm

U22@

CC2

1 2

15P_0201_50V8J

CC1

1 2

15P_0201_50V8J

CC23

1 2

6.8P_0402_50V8J

CC24

1 2

6.8P_0402_50V8J

+RTCVCC

1M_0402_5%

+3V_PRIM

10K_0201_5%

APS CONN

+3V_PRIM

+3VALW

+3VALW

SIO_PWRBTN#10,13,30

SIO_SLP_S3#

SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#

RTC_RST#

SYS_RESET#

SIO_SLP_S0#

ACES_50506-01841-P01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P10-MCP(6/14)CLK,PM,RTC

P10-MCP(6/14)CLK,PM,RTC

P10-MCP(6/14)CLK,PM,RTC

LA-F371P

LA-F371P

LA-F371P

1

20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

U22@

U22@

JAPS1

GND
GND
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

@CONN@

10 65Tuesday, November 07, 2017

10 65Tuesday, November 07, 2017

10 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

4

3

2

1

+1.0V_VCCST

H_CATERR#

1 2

RC7 49.9_0402_1%@

RC20 1K_0402_5%

+1.0V_VCCSTG

RC28 1K_0402_5%

D D

+3VS

PVT-001

Due to touch control baord with internal PU 35K, so d epop RC9

RC9 10K_0402_5%@

RC163 10K_0402_5%@

+3V_PRIM

RC8 10K_0402_5%

RC68 10K_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

H_THERMTRIP#_R

H_PROCHOT#

TOUCH_SCREEN_PD#

EC_SLP_S0IX#

SIO_EXT_SMI#

NFC_DET#

TDI_XDP

TDO_XDP

TMS_XDP

PCH_JTAG_TCLK

+5VALW

RC2 51_0402_5%

RC19 100_0402_5%

RC18 51_0402_5%

RC17 51_0402_5%

@

CPU MISC

SKL-U

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

4 OF 20

TCLK_XDP

B61

TDI_XDP

D60

TDO_XDP

A61

TMS_XDP

C60

TRST#_XDP

B59

PCH_JTAG_TCLK

B56

TDI_XDP

D59

TDO_XDP

A56

TMS_XDP

C59

TRST#_XDP

C61

TCLK_XDP

A59

TCLK_XDP 13
TDI_XDP 13
TDO_XDP 13
TMS_XDP 13
TRST#_XDP 13

PCH_JTAG_TCLK 13

1 2

RC3 1K_0402_5%@

+1.0V_VCCSTG

UCPU1D

AT16
AU16

D63

A54
C65
C63

A65

C55
D55

B54
C56

A6

A7
BA5
AY5

H66
H65

@

SKL-U_BGA1356

CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

H_PECI30
H_PROCHOT#30,50,53,57
H_THERMTRIP#30

1 2

RC27 499_0402_1%

1 2

RC389 60.4_0402_1%

T9
T10

TOUCH_SCREEN_PD#22

EC_SLP_S0IX#30

12

12

RC160

49.9_0402_1%

XDP_OBS0_R13
XDP_OBS1_R13

@

PAD~D

@

PAD~D

12

RC167

49.9_0402_1%

H_PROCHOT#_RH_PROCHOT#
H_THERMTRIP#_R

XDP_OBS2_R
XDP_OBS3_R

SIO_EXT_SMI#
TOUCH_SCREEN_PD#
NFC_DET#
EC_SLP_S0IX#

CPU_POPIRCOMP
PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

EOPIO_RCOMP

12

RC122

RC123

49.9_0402_1%

49.9_0402_1%

H_CATERR#

Strap pin

RC188

@

1 2

2

6 1

@

Q25A

1 2

RC53 100K_0402_5%~D

1 2

RC202 10K_0402_5%

1 2

RC200 100K_0402_5%~D

1 2

RC193

+DVDDIO

1 2

0_0201_5%

1M_0201_5%

DMN2400UV-7_SOT-563-6

CAM_CBL_DET#

WWAN_OFF#

CONTACTLESS_DET#

EDP_ID0

C C

UCPU1G

@

AUDIO

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL-U_BGA1356

TPM_DET

TPM_DET

SPKR28

HDA_SYNC_R
HDA_BLK_R
HDA_SDOUT_R

SPKR

TPM_DET

1 2

HDA_SYNC28
HDA_BLK28
HDA_SDOUT28

HDA_SDI028

HDA_BLK

1

CC17

B B

@

22P_0402_50V8J

2

RC75 33_0402_5%
RC77 33_0402_5%

HDA_SDOUT

RC76 33_0402_5%

HDA_SDI0

1 2
1 2

NGFF_WWAN_PW REN44

Close to RC77

HDA_SDOUT

RF@

2P_0201_25V8B

12

CC93

HDA_SDI0

RF@

2P_0201_25V8B

12

CC94

BA22
AY22
BB22
BA21
AY21

AW22

AY20

AW20

AK10

AW5

J5

AK7
AK6
AK9

H5
D7

D8
C8

SKL-U

TPM@

1 2

@

SDIO/SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_A17/SD_PWR_EN#/ISH_GP7

+3V_PRIM

RH11100K_0201_5%

12

RH14100K_0201_5%

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

7 OF 20

CAM_CBL_DET#

AB11
AB13
AB12
W12

CONTACTLESS_DET#

W11
W10
W8

EDP_ID0

W7

BA9
BB9

SD_RCOMP

AB7

AF13

From EC, for
ena ble
ME code
program ing

ME_FWP30

3

@

5

4

CAM_CBL_DET# 43

SPK_ID 29

SSD_PWR_EN 44
CONTACTLESS_DET# 4 3
WWAN_OFF# 25
PCH_AUD_PWR_E N 30
EDP_ID0 22

SD_PWR_EN 44

1 2

RC140 200_0402_1%

Q25B
DMN2400UV-7_SOT-563-6

R5774

+1.0V_VCCSTG

12

12

12

12

HDA_SDO

ME debug mode , this signal
has a weak internal PD
L=>security measures def i ned
in the Flash Descriptor will be
in ef f ect ( def ault)
H=>Flash Descriptor Security
will be overridden

RC92

HDA_SDOUT

1 2

1K_0402_5%

Low = Disabled

*

High = Enabled

+3VS

+3V_PRIM

100K_0201_5%

+3V_PRIM +3V_PRIM

A A

1 2

RC158 8.2K_0402_5%

@

TOP SWAP STRAP

HIGH
LOW(DEFAULT)

ENABLE
DISAB LE

SPKR

5

RC81 4.7K_0402_5%

@

Flash Descriptor Security
override

HIGH
LOW(DEFAULT)

1 2

HDA_SDOUT

DISABLE

ENABLE

4

TPM_DET

TPM

1 = W/TPM

0 = W/O TPM

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P11-MCP(7/14)MISC,JTAG,HDA,SDIO

P11-MCP(7/14)MISC,JTAG,HDA,SDIO

P11-MCP(7/14)MISC,JTAG,HDA,SDIO

LA-F371P

LA-F371P

LA-F371P

1

11 65Tuesday, November 07, 2017

11 65Tuesday, November 07, 2017

11 65Tuesday, November 07, 2017

1.0

1.0

1.0

TPM BOM Optional

5

No stall(Normal Operat i on)

D D

4

CFG[0..15]13

3

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

2

1

UCPU1S

@

1 2

RC29 10K_0402_1%

@

Stall reset sequence

HIGH(DEFAULT)
LOW

C C

1 2

RC40 10K_0402_1%

eDP enable

HIGH(DEFAULT)
LOW

B B

CFG0

sta ll

CFG4

Disa bled
Enabled

PVT-024

Change 0 ohm to short pad

+1.0VA

1 2

R5770

E68

CFG0

1 2

RC37 10K_0402_1%

@

1 2

RC30 10K_0402_1%

@

+1.0VA_XDP1

@

0_0201_5%

+1.0VA_XDP1

CFG1613
CFG1713

CFG1813
CFG1913

CFG_RCOMP

RC112 4 9.9_0402_1%

RC10 1.5K_0402_5%

12

ITP_PMODE

12

ITP_PMODE13

@

T31

PAD~D

@

T28

PAD~D

CFG1
CFG2

CFG3
CFG4

CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

AL25
AL27

BA70
BA68

B67
D65
D67
E70
C68
D68
C67
F71

G69

F70

G68

H70

G71

H69

G70

E63
F63

E66
F66

E60

E8

AY2
AY1

D1
D3

K46
K45

C71
B70

F60

A52

J71
J68

F65

G65

F61
E61

SKL-U_BGA1356

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2
RSVD_AY1

RSVD_D1
RSVD_D3

RSVD_K46
RSVD_K45

RSVD_AL25
RSVD_AL27

RSVD_C71
RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70
RSVD_TP_BA68

RSVD_J71
RSVD_J68

VSS_F65
VSS_G65

RSVD_F61
RSVD_E61

RESERVED SIGNALS-1

SKL-U

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54
RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

19 OF 20

BB68
BB69

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

TP4

A69
B69

AY3

D71
C70

C54
D54

AY4

TP1

BB3

TP2

AY71
AR56

AW71
AW70

AP56
C64

RC24 100K_0402_5%

1 2

@

T27

PAD~D

@

T30

PAD~D

@

T33

PAD~D

@

T34

PAD~D

@

T22

PAD~D

@

T37

PAD~D

@

T39

PAD~D

@

T40

PAD~D

@

T41

PAD~D

ZVM# for SKYLAKE-U 2+3e

Pebble Creek use 2+2e

@

T23

PAD~D

@

T29

PAD~D

MSM# for SKYLAKE-U 2+3e

XTAL24_IN_RU

XTAL24_OUT_RU

+1.0V_VCCST

@

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

XTAL24_OUT_RU

C7
U12
U11
H11

SKL-U_BGA1356

RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11

Support for KBL-R U4+2

U42@

RC377 33_0201_1%

U42@

RC378 33_0201_1%

12

12

UCPU1T

SKL-U

SPARE

RSVD_F6

RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

U42@

RC374 1M_0201_1%

1 2

YC3

1

1

CC96

27P_0201_25V8

2

24MHZ_18PF_XRCGB24M000F2P51R0

U42@

1

20 OF 20

U42@

NC

F6

XTAL24_IN_RU

E3
C11
B11
A11
D12
C12
F52

3

3

NC

2

4

CC97

27P_0201_25V8

2

U42@

1

X76

X7669231L60

X7669231L62

X7669231L61

A A

32Gb 2133 DRAM Option (R1) , (R3)

Micron 32G/2133

Micron 32G_R3@

UD1

MT52L1G32D4PG-107WT

SA00009ZN1L

Hynix 32G/2133

HYNIX_32G_@

UD1

H9CCNNNCLGALAR-NVD FBGA

SA00009ZL0L

Samsung 32G/2133

SAMSUNG_32G@

UD1

K4EBE304EB-EGCG FBGA178

SA00008VV0L

5

Micron 32G_R3@

UD2

MT52L1G32D4PG-107WT

SA00009ZN1L

HYNIX_32G_@

UD2

H9CCNNNCLGALAR-NVD FBGA

SA00009ZL0L

SAMSUNG_32G@

UD2

K4EBE304EB-EGCG FBGA178

SA00008VV0L

Micron 32G_R3@

UD3

MT52L1G32D4PG-107WT

SA00009ZN1L

HYNIX_32G_@

UD3

H9CCNNNCLGALAR-NVD FBGA

SA00009ZL0L

SAMSUNG_32G@

UD3

K4EBE304EB-EGCG FBGA178

SA00008VV0L

4

MT52L1G32D4PG-107WT

H9CCNNNCLGALAR-NVD FBGA

K4EBE304EB-EGCG FBGA178

Micron 32G_R3@

UD4

SA00009ZN1L

HYNIX_32G_@

UD4

SA00009ZL0L

SAMSUNG_32G@

UD4

SA00008VV0L

DRAM Config Option

(Resistor pop location)

MEM_CONFIG0

X76_M32G@

RH17

10K_0402_5%

SD028100280

X76_H32G@

RH18

10K_0402_5%

SD028100280

X76_S32G@

RH17

10K_0402_5%

SD028100280

MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3

X76_M32G@

RH16

10K_0402_5%

SD028100280

X76_H32G@

RH15

10K_0402_5%

SD028100280

X76_S32G@

RH15

10K_0402_5%

SD028100280

X76_M32G@

RH13

10K_0402_5%

SD028100280

X76_H32G@

RH13

10K_0402_5%

SD028100280

X76_S32G@

RH13

10K_0402_5%

SD028100280

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

X76_M32G@

RH9

10K_0402_5%

SD028100280

X76_H32G@

RH9

10K_0402_5%

SD028100280

X76_S32G@

RH9

10K_0402_5%

SD028100280

Compal Secret Data

Compal Secret Data

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P12-MCP(8/14)CFG,RSVD

P12-MCP(8/14)CFG,RSVD

P12-MCP(8/14)CFG,RSVD

LA-F371P

LA-F371P

LA-F371P

1

12 65Tuesday, November 07, 2017

12 65Tuesday, November 07, 2017

12 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

PVT-025

Change 0.01 ohm to short pad

D D

RC130

Plac e
near
JXDP1

1 2

+1.0VA

+1.0VA_XDP

@

0_0603_5%

+1.0VA_XDP

0.1U_0402_10V7K

0.1U_0402_10V7K

@

1

2

@

1

CC33

CC37

2

+1.0VS_VCCIO

+1.0V_VCCST

RC119 150_0402_5%@

RC109 150_0402_5%@

RC111 10K_0402_5%@

1 2

1 2

1 2

+1.0VA_XDP

1 2

RC151 51_0 402_5%

CFG[0..15]12

C C

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG3

XDP_OBS0_R11
XDP_OBS1_R11

@XDP@
@XDP@

H_VCCST_PWRGD_P10,32

PCH_RSMRST#_R10,30

FIVR_EN

CFG0

PCH_SPI_DO_XDP7

SYS_PWROK10,30

B B

PCH_SPI_DO_XDP

PCH_SPI_DO2_XDP7

@XDP@

XDP_PRSENT#

@

CC26@ 0.1U_0402_25V6

Place near
JXDP1.47

PVT-048

De-pop debug XDP related compoments

RC141 1K_0402_5%@XDP@

RC142 0_0402_5%@

RC138 0_0402_5%
RC136 0_0402_5%

RC132 1K_0402_5%@

RC131@XDP@

RC121 0_0402_5%

@

RC144

@

RC100 0_0402_5%
RC99 0_0402_5%

@

RC187 33_0201_1%@XDP@

12

12

PVT-048

De-pop debug XDP related compoments

1 2
1 2

1 2

1 2

1K_0402_5%

PVT-048

De-pop debug XDP related compoments

1 2
1 2
1 2
1 2

PVT-048

De-pop debug XDP related compoments

1 2

+3V_PRIM

5

U44

1

@XDP@

P

NC

2

Y

A

G

NL17SZ14DFT2G_SOT353-5

3

12

H_VCCST_PWRGD_XDP

1K_0402_5%

4

4

FIVR_EN_R

FIVR_EN

FIVR_EN

CPU_XDP_PREQ#

RESET_OUT#_R

XDP_PRSNT_PIN1

XDP_OBS0
XDP_OBS1

FIVR_EN_R

RESET_OUT#_R

XDP_PRSENT#

XDP_PRSENT 45

+3V_PRIM

12

RC107

1.5K_0402_5%

PCH_SPI_DO_XDP XDP_DBRESET#

Place near
JXDP1.48

CPU XDP

CPU_XDP_PREQ#9
CPU_XDP_PRDY#9

H_VCCST_PWRGD_XD P

SIO_PWRBTN#10,30

DDR_XDP_SMBDAT7
DDR_XDP_SMBCLK7

PCH_JTAG_TCLK11

TCLK_XDP11

+1.0VA_XDP

XDP_PRSNT_PIN1
CPU_XDP_PREQ#

CFG0

CFG1

CFG2

CFG3

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6
CFG7

SIO_PWRBTN#

FIVR_EN_R

RESET_OUT#_R

TCLK_XDP

3

+3VS

1K_0402_5%

12

PVT-048

De-pop debug XDP related compoments

0.1U_0402_25V6

12

JXDP1

112
334
556
778
9910
111112

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57
595960

61

61

GND62GND

JXT_FP270H-061G1AM

CONN@

2

1

+3.3V_ALW_DSW

1.5K_0402_5%

12

RC120

Place near
JXDP1.41

SIO_PWRBTN#

@XDP@

CC95

RC127

0.1U_0402_25V6

@

CC36

12

TRST#_XDP

51_0402_5%

TCLK_XDP

51_0402_5%

RC106

12

@

RC102

12

+1.0VA_XDP

2
4

CFG17

6

CFG16

8
10

CFG8

12

CFG9

14

14

16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

63

CFG10
CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

XDP_DBRESET#

TDO_XDP
TRST#_XDP
TDI_XDP
TMS_XDP
XDP_PRSENT#

16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58

CFG17 12
CFG16 12

CFG8 12
CFG9 12

CFG10 12
CFG11 12

CFG19 12
CFG18 12

CFG12 12
CFG13 12

CFG14 12
CFG15 12

CLK_ITPXDP_P 10
CLK_ITPXDP_N 10

ITP_PMODE 12

XDP_DBRESET# 10

TDO_XDP 11
TRST#_XDP 11
TDI_XDP 11
TMS_XDP 11

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P13-MCP(9/14)XDP

P13-MCP(9/14)XDP

P13-MCP(9/14)XDP

LA-F371P

LA-F371P

LA-F371P

13 65Tuesday, November 07, 2017

13 65Tuesday, November 07, 2017

1

13 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

4

3

2

1

PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

+VCC_CORE: 0.55~1.5V, 29A

D D

+VCC_EDRAM: 1V, 2.5A
+V1.8S_EDRAM: 1.8V, 50mA
+VCC_EOPIO: 0.8~1V, 2A

@

T8

PAD~D

@

T18

PAD~D

C C

+VCC_CORE +VCC_CORE

+VCC_CORE_G0

+VCC_CORE_G1

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e

(w/ on package cache)

AK33
AK35
AK37
AK38
AK40
AL33
AL37

AL40
AM32
AM33
AM35
AM37
AM38

AK32

AB62

AC63

AE63

AE62
AG62

AL63

AJ62

A30
A34
A39
A44

G30

K32

P62
V62

H63

G61

@

SKL-U_BGA1356

UCPU1L

VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE
VSSOPC_SENSE

VCCEOPIO
VCCEOPIO

VCCEOPIO_SENSE
VSSEOPIO_SENSE

CPU POWER 1 OF 4

1.5V@29A

1V@2.5A

1V@0 .0 5A

1V@2A

SKL-U

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37

VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

SVID ALERT

VIDALERT_N5 7

12 OF 20

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32

VCCSENSE

E33

VSSSENSE

H_CPU_SVIDALRT#

B63

VIDSCLK_R

A63

VIDSOUT_R

D64

G20

+1.0V_VCCSTG_R

+1.0V_VCCST

56_0402_1%

12

PVT-026

Change 0 ohm to short pad

RC1

RC94

+VCC_CORE

12

Close CPU

RC5

100_0402_1%

VCCSENSE 57

RC6

100_0402_1%

0_0402_1%@

H_CPU_SVIDALRT#

12

RC22220_0402_5%

VSSSENSE 57

+1.0V_VCCSTG

12

1 2

CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils

SVID DATA

B B

VIDSOUT57

SVID CLK

VIDSCLK57

+1.0V_VCCST

12

+1.0V_VCCST

12

100_0402_1%

RC93

100_0402_1%

@

RC95

CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils

VIDSOUT_R

12

RC230 _0402_5%~D

CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils

VIDSCLK_R

12

RC210_0402_5%~D

CDI#61280

10.2.7 SVID Topology

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Table 10-9. SVID Bus Routing Guidelines
need double pull high

Compal Secret Data

Compal Secret Data

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P14-MCP(10/14)PWR-VCC CORE

P14-MCP(10/14)PWR-VCC CORE

P14-MCP(10/14)PWR-VCC CORE

LA-F371P

LA-F371P

LA-F371P

1

14 65Tuesday, November 07, 2017

14 65Tuesday, November 07, 2017

14 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

4

3

2

1

+VCCGT: 0.55~1.5V, 54A
+VCCGTX : 0.55~1.5V, 7A

D D

+VCCIA_GT

C C

K52

Close CPU

VCC_GT_SENSE57

VSS_GT_SENSE57

B B

+VCC_GT +VCC_GT

SKL-U

CPU POWER 2 OF 4

1.5V@54A

1.5V@7A

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

+VCC_GT

12

12

RC44

100_0402_1%

VCC_GT_SENSE
VSS_GT_SENSE

RC42

100_0402_1%

AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

A48
A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70

L71
M62
N63
N64
N66
N67
N69

J70

J69

UCPU1M

@

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

SKL-U_BGA1356

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

13 OF 20

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

AK52

+VCCIA_GT

+VCC_GT

R275

U42@

0.0002_0805_5%

1 2

R277

U42@

0.0002_0805_5%

1 2

@

R279 0_0402_5%

1 2

AK52

@

R280 0_0402_5%

1 2

K52

+VCCIA_GT +VCC_GT+VCC_CORE

+VCCIA_GT

+VCC_GT

R276

U22@

0.0002_0805_5%

1 2

R278

U22@

0.0002_0805_5%

1 2

A A

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P15-MCP(11/14)PWR-VCCGT

P15-MCP(11/14)PWR-VCCGT

P15-MCP(11/14)PWR-VCCGT

LA-F371P

LA-F371P

LA-F371P

1

15 65Tuesday, November 07, 2017

15 65Tuesday, November 07, 2017

15 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

4

3

2

1

+1.2V_DDR: 1.2V, 3.5A
+1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA
+1.0V_VCCSTG: 1V, 40mA
+VCCPLL_OC: 1.2V, 260mA
+1.0VS_VCCIO: 0.85~0.95V, 3.1A
+VCC_SA: 1.15V, 5.1A

D D

+1.2V_MEM_CPUCLK+1.2V_DDR

1 2

@

RC156

PVT-027

+1.2V_MEM_CPUCLK

BSC

PSC

1

1

CC83

CC76

2

2

@

1U_0201_6.3V6M

10U_0402_6.3V6M

+1.2V_MEM_CPUCL K (VDDQC) Plac e on CPU
Back Side (undern eath the package) :
1U_0201*1 pcs (@)
Primary Side (close to package ):

C C

10U_0402 * 1 pcs

Change 0 ohm to short pad

0_0402_1%

+1.0V_VCCST

close to package

1

2

PSC

CC35

1U_0402_6.3V6K

+1.0V_VCCSTG

BSC

underneath the package

1

CC4

2

@

1U_0402_6.3V6K

+1.2V_MEM_CPUCLK

+VCCPLL_OC +1.0V_VCCST

PSC

1

CC68

2

1U_0201_6.3V6M

+1.2V_DDR

1V@0 .1 2A

1V@0 .0 4A

1.2V@ 0. 26 A

1V@0 .1 2A

close to packageclose to package

PSC

AU23
AU28
AU35
AU42

BB23
BB32
BB41
BB47
BB51

AM40

AL23

1

2

A18

A22

K20
K21

CC3

UCPU1N

@

CPU POWER 3 OF 4

VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20
VCCPLL_K21

SKL-U_BGA1356

1U_0402_6.3V6K

SKL-U

0.95V @3 .1 A

1.2V @3 .5A

1.15V @5 .1 A

+VCC_SA

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

14 OF 20

RC116 100_0402_1%

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

1 2

+1.0VS_VCCIO

VCCIO_SENSE
VSSIO_SENSE

+VCC_SA

+1.0VS_VCCIO

12

RC115

100_0402_1%

VSA_SEN- 57
VSA_SEN+ 57

12

12

Close CPU

RC147

100_0402_1%

VCCIO_SENSE 56
VSSIO_SENSE 56

RC155

100_0402_1%

+1.2_DDR Decoupling Requirment
Back Side (undern eath the package) :
10U_0402*2 pcs + 1U_0201 *4 pcs (@)
Primary Side (close to package ):
10U_0402*4 pcs + 22U_0603*3 pcs

B B

+1.2V_DDR

PSC

1

1

CC88

2

2

22U_0603_6.3V6M

1

1

CC87

CC86

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CC19

2

10U_0402_6.3V6M

1

CC84

CC82

10U_0402_6.3V6M

CC20

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

BSC

1

1

1

1

CC18

CC85

2

A A

5

2

2

@

@

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC77

2

@

1U_0201_6.3V6M

4

1

CC80

CC75

CC74

2

2

@

@

1U_0201_6.3V6M

@

1U_0201_6.3V6M

1U_0201_6.3V6M

+1.0VS_VCCIO Dec oupling Requir ment
Back Side (undern eath the package) :
10U_0402*2 pcs + 1U_0201 *4 pcs (@)
Primary Side (close to package ):
1U_0402*4 pcs

+1.0VS_VCCIO

PSC

1

2

1

1

CC60

2

1U_0402_6.3V6K

1

CC63

CC69

1U_0402_6.3V6K

CC61

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

BSC

1

1

CC67

2

@

10U_0402_6.3V6M

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CC71

CC62

2

2

@

10U_0402_6.3V6M

1

1

1

1

CC65

CC72

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

CC66

2

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P16-MCP(12/14)PWR-VCCIO,MEM

P16-MCP(12/14)PWR-VCCIO,MEM

P16-MCP(12/14)PWR-VCCIO,MEM

LA-F371P

LA-F371P

LA-F371P

1

16 65Tuesday, November 07, 2017

16 65Tuesday, November 07, 2017

16 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

4

3

2

PVT-028

Change 0 ohm to short pad

1

+3.3V_PGPP+3V_PRIM

1 2

@

RC134

D D

C C

B B

+3.3V_ALW_DSW +1.8VA +1.0VA +1.0V_PRIM_CORE

1

@

CC73

2

47U_0805_6.3V6M

PVT-028

Change 0 ohm to short pad

+1.0VA

RC125

RC47

PVT-028

Change 0 ohm to short pad

+1.0V_MPHYGT

RC133

RC128

PVT-028

Change 0 ohm to short pad

1

CC47

2

1 2

@

1 2

@

1 2

@

1 2

@

47U_0805_6.3V6M

1

CC29

2

+1.0V_MPHYAON

0_0603_5%

+1.0V_DTS

0_0402_1%

+1.0V_SRAM

0_0603_5%

+1.0V_APLLEBB

0_0402_1%

47U_0805_6.3V6M

+1.0V_CLK+1.0VA

1 2

@

PVT-028

Change 0 ohm to short pad

RC103

0_0603_5%

1

CC28

2

@

1

CC52

2

47U_0805_6.3V6M

+1.5VS_AUDIO

12

@

close UC1.A10 and <120mil

1U_0402_6.3V6K

RC185
0_0603_5%

+3V_PRIM

+1.0V_MPHYGT

12

RC186
0_0603_5%

L23

1 2

BLM18EG221SN1D_2P

CC53

2P_0201_25V8B

12

CDI#561280
3/23 follow PDG 5.76GHz
An EMI Filter Implementation to Isolate

5.76 GHz Noise Coming From VccHDA

1

2

1

CC32

2

1U_0402_6.3V6K

1

CC14

CC54

2

@

1U_0402_6.3V6K

1U_0402_6.3V6K

close UC1.AF18 and <400mil

close UC1.K17 and <120mil

close UC1.AL1 and <120mil

close UC1.N15 and CC210 <400mil, CC211 <120mil

1

1

CC43

CC39

2

2

@

1U_0402_6.3V6K

47U_0805_6.3V6M

close UC1.AJ19 and <400mil

CC64

2P_0201_25V8B

12

+1.0V_SRAM

close UC1.AF20 and <400mil

1

CC44

2

@

+1.0V_APLLEBB

1U_0402_6.3V6K

close UC1.N18 and <120mil

1

2

+3.3V_ALW_DSW

+1.0VA+1.0V_PRIM_CORE+1.0V_MPHYAON

close UC1.AB19 and <400mil

1

CC51

2

@

1U_0402_6.3V6K

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0VA

+3.3V_ALW_DSW

+3.3V_SPI

+3V_PRIM

CC38

1U_0402_6.3V6K

+1.0VA

1.0V @0. 696 A

1.0V @2. 57A

1.0V @0. 022 A

1.0V @2. 1A

1.0V @0. 088 A

1.0V @0. 026 A

3.3V @0. 118 A

1.5V @0. 068 A

3.3V @0. 011 A

1.0V @0. 642 A

3.3V @0. 075 A

1.0V @0. 033 A

UCPU1O

@

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKL-U_BGA1356

+3VALW

+1.0V_AMPHYPLL+1.0V_MPHYGT

@

1 2

1 2

@

RC129

close UC1.V15 and <100mil

L30

1 2

BLM18EG221SN1D_2P

CC92

2P_0201_25V8B

12

A A

0_0402_1%

12

12

close UC1.K15 and <120mil

1

CC34

2

@

+1.0V_APLL+1.0VA

R121
0_0201_5%

CC49
2P_0201_25V8B

1U_0402_6.3V6K

+3.3V_ALW_DSW

22U_0603_6.3V6M

@

CC55

1

2

22U_0603_6.3V6M

@

CC59

1

2

place near AD17,AD18,AJ17

RC394 0_0402_5%

+3.3V_ALW_DSW_Q352

1 2

RC395 0_0402_5%

1

C1134

@

0.1U_0201_10V6K

2

DII-DMN65D8LW-7

Q352

DMG2301U-7_SOT23-3

1 3

D

2

12

13

D

Q353

S

S

G

R233

49.9K_0402_1%

2

G

12

R234
499K_0402_1%

R235
100K_0402_5%

1 2

PCH PWR

CPU POWER 4 OF 4

VCCDSW_EN_GPIO 30

SKL-U

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

15 OF 20

1 2

0_0402_5%

1 2

1 2

1

CC27
22U_0603_6.3V6M

2

PVT-028

Change 0 ohm to short pad

+1.8VA

1 2

RC139

+1.8V_PGPP

AK15
AG15
Y16
Y15
T16
AF16

1.8V @0. 161 A

AD15

V19

T1

AA1

1.8V @0. 006 A

AK17

3.3V @0. 001 A

AK19

3.0V @0. 001 A

BB14

BB10

A14

1.0V @0. 135 A

K19

L21

N20

L19

A10

AN11
AN13

RC16

RC117

0_0603_5%

RC104

0_0603_5%

@

0_0603_5%

close UC1.V19 and <120mil

close UC1.BB10 and <120mil

+VCCCLK1

+VCCCLK2

+VCCCLK3

+VCCCLK4

+VCCCLK5

+VCCCLK6

+VCCCLK1

1

CC5

0.1U_0201_10V6K

2

Close to Pin A14 Close to Pin N20

+VCCCLK2

1

CC42

0.1U_0201_10V6K

2

+VCCCLK3

close UC1.AG15 and <120milclose UC1.Y16 and <400milclose UC1.T16 and <400mil

0_0603_5%

+1.8V_PGPP

+3.3V_PGPP

+1.8V_PGPP
+3.3V_PGPP

+1.0V_DTS

1

CC58

2

@

1U_0402_6.3V6K

+3V_PRIM +1.8VA

12

CC46

close UC1.AA1 and <400mil

close UC1.AK19 and <120mil

1

CC70

1

2

CC81

2

4.7P_0402_50V8C

+RTCVCC

1

CC79

2

1U_0402_6.3V6K

0.1U_0402_10V7K

1

CC50

2

@

1U_0402_6.3V6K

1

CC48

2

1U_0402_6.3V6K

close UC1.AK17 and <120mil

0.1U_0402_10V7K

CORE_VID0 56
CORE_VID1 56

+1.0V_CLK+1.0V_CLK

RC118

1 2

1 2

1 2

1

CC30
22U_0603_6.3V6M

2

0_0603_5%

RC105

0_0603_5%

RC15

0_0402_5%

1

2

1

2

1

CC57

2

+VCCCLK4

CC40

0.1U_0201_10V6K

+VCCCLK5

CC41

0.1U_0201_10V6K

Close to Pin L 19Close to Pin K19

+VCCCLK6

0.1U_0402_10V7K

+3V_PRIM

1

2

1

CC45

2

@

1U_0402_6.3V6K

CC56

1U_0402_6.3V6K

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P17-MCP(13/14)PCH PWR

P17-MCP(13/14)PCH PWR

P17-MCP(13/14)PCH PWR

Document Number Re v

Document Number Re v

Document Number Re v

LA-F371P

LA-F371P

LA-F371P

1

17 65Tuesday, November 07, 2017

17 65Tuesday, November 07, 2017

17 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

Note1: VCCPRIM_CORE Implementat i on wit h PCH CORE_VI D Reco mmendat i on

4

3

2

1

Note1: VCCPRIM_CORE Implementat i on wit h PCH CORE_VI D Reco mmendat i on

SKL-U

UCPU1P

@

GND 1 OF 3

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

D D

C C

B B

AA65
AA68
AB15
AB16
AB18
AB21

AD13
AD16
AD19
AD20
AD21
AD62

AE64
AE65
AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH63
AH64
AH67

AJ15
AJ18
AJ20

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AL28
AL32
AL35
AL38

AL45
AL48
AL52
AL55
AL58
AL64

AB8

AD8

AF1

AF2
AF4

AH6

AJ4

AK8
AL2

AL4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-U_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

16 OF 20

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

AT63
AT68

AT71
AU10
AU15
AU20
AU32
AU38

AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6
AW60
AW62
AW64
AW66

AW8
AY66

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71

BA1
BA10
BA14
BA18

BA2
BA23
BA28
BA32
BA36

BA45

F68

UCPU1Q

@

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-U_BGA1356

SKL-U

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

17 OF 20

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

@

F8
G10
G22
G43
G45
G48

G5
G52
G55
G58

G6
G60
G63
G66
H15
H18
H71

J11
J13
J25
J28
J32
J35
J38
J42

J8
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17

SKL-U_BGA1356

UCPU1R

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND 3 OF 3

SKL-U

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

18 OF 20

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P18-MCP(14/14)VSS

P18-MCP(14/14)VSS

P18-MCP(14/14)VSS

LA-F371P

LA-F371P

LA-F371P

18 65Tuesday, November 07, 2017

18 65Tuesday, November 07, 2017

1

18 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

5

+1.8VU +1.8VU

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

CD40

DDR_A_DQS#[0..7]6

DDR_A_DQS[0..7]6

DDR_A_D[0..63]6

DDR_A_CA1_[0..9]6,21

DDR_A_CA2_[0..9]6,21

D D

12

CD83

1

2

+1.8VU

1U_0402_6.3V6K~D

CD36

1

2

+1.2V_DDR

+1.2V_DDR+1.2V_DDR

10U_0603_6.3V6M~D

CD2

12

+1.2V_DDR +1. 2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

CD59

12

C C

Closed to UD19

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD38

1

2

1U_0402_6.3V6K~D

CD9

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

2

1U_0402_6.3V6K~D

CD24

CD23

CD18

1

1

2

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD11

CD37

1

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

CD16

1

1

CD27

2

2

+1.2V_DDR +1.2V_DDR

+1.2V_DDR +1.2V_DDR

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD31

12

B B

1U_0402_6.3V6K~D

CD14

CD10

1

1

2

2

4

UD4

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0
DQS1
DQS2
DQS3

DQS0#
DQS1#
DQS2#
DQS3#

CKE0
CKE1

Vref_DQ

Vref_CA

CS0#
CS1#

3

+1.8VU

+1.8VU

1U_0402_6.3V6K~D

DDR_A_D27

P9

DQ0

DDR_A_D29

N9

DQ1

DDR_A_D25

N10

DQ2

DDR_A_D31

N11

DQ3

DDR_A_D28

M8

DQ4

DDR_A_D24

M9

DQ5

DDR_A_D30

M10

DQ6

DDR_A_D26

M11

DQ7

DDR_A_D20

F11

DQ8

DDR_A_D17

F10

DQ9

DDR_A_D22

F9

DDR_A_D18

F8

DDR_A_D21

E11

DDR_A_D16

E10

DDR_A_D23

E9

DDR_A_D19

D9

DDR_A_D51

T8

DDR_A_D55

T9

DDR_A_D49

T10

DDR_A_D53

T11

DDR_A_D50

R8

DDR_A_D54

R9

DDR_A_D48

R10

DDR_A_D52

R11

DDR_A_D56

C11

DDR_A_D61

C10

DDR_A_D62

C9

DDR_A_D59

C8

DDR_A_D60

B11

DDR_A_D57

B10

DDR_A_D63

B9

DDR_A_D58

B8

DDR_A_CA1_0

R2

CA0

DDR_A_CA1_1

P2

CA1

DDR_A_CA1_2

N2

CA2

DDR_A_CA1_3

N3

CA3

DDR_A_CA1_4

M3

CA4

DDR_A_CA1_5

F3

CA5

DDR_A_CA1_6

E3

CA6

DDR_A_CA1_7

E2

CA7

DDR_A_CA1_8

D2

CA8

DDR_A_CA1_9

C2

CA9

DDR_A_DQS3

L10

DDR_A_DQS2

G10

DDR_A_DQS6

P10

DDR_A_DQS7

D10

DDR_A_DQS#3

L11

DDR_A_DQS#2

G11

DDR_A_DQS#6

P11

DDR_A_DQS#7

D11

L8

DM0

G8

DM1

P8

DM2

D8

DM3

DDR_A0_ZQ0

B3

ZQ0

B4

ZQ1

K3
K4

L3
L4

J3

CK

J2

CK#

J8

ODT

J11
H4

B2

VSS

B5

VSS

C5

VSS

E4

VSS

E5

VSS

F5

VSS

H2

VSS

J12

VSS

K2

VSS

L6

VSS

M5

VSS

N4

VSS

N5

VSS

R4

VSS

R5

VSS

T2

VSS

T3

VSS

T4

VSS

T5

VSS

RD20 240_0402_1%

DDR_A0_ZQ1

DDR_A_CS#0
DDR_A_CS#1

DDR_A_ODT0

1 2

RD19 240_0402_1%

1 2

DDR_A_CKE0 6,21
DDR_A_CKE1 6,21

DDR_A_CS#0 6,21
DDR_A_CS#1 6,21

DDR_A_CLK0 6,21
DDR_A_CLK#0 6,21

DDR_A_ODT0 6,21

+VREFDQ_A
+VREFCA

Closed to DRAM Closed to DRAM

+VREFDQ_A +VREFDQ_A+VREFCA +VREFCA

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

CD21

1

2

CD22

1

2

+1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD80

1

12

2

10U_0603_6.3V6M~D

CD50

12

+1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

12

Closed to UD20

1U_0402_6.3V6K~D

CD79

CD63

1

2

10U_0603_6.3V6M~D

All VREF traces should
have 10 mil trace width

1U_0402_6.3V6K~D

CD12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD39

1

2

CD3

12

1

2

CD65

1

2

+1.2V_DDR+1.2V_DDR

1U_0402_6.3V6K~D

2

+1.8VU

1U_0402_6.3V6K~D

CD54

CD84

1

1

2

2

+1.2V_DDR

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD60

CD61

0.1U_0402_16V7K~D

CD58

1

2

CD77

1

1

2

2

0.1U_0402_16V7K~D

1

1

CD57

CD74

2

2

1U_0402_6.3V6K~D

CD56

1

2

UD2

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0
DQS1
DQS2
DQS3

DQS0#
DQS1#
DQS2#
DQS3#

CKE0
CKE1

CS0#
CS1#

Vref_DQ
Vref_CA

DDR_A_D12

P9

DQ0

DDR_A_D8

N9

DQ1

DDR_A_D10

N10

DQ2

DDR_A_D14

N11

DQ3

DDR_A_D13

M8

DQ4

DDR_A_D9

M9

DQ5

DDR_A_D15

M10

DQ6

DDR_A_D11

M11

DQ7

DDR_A_D7

F11

DQ8

DDR_A_D1

F10

DQ9

DDR_A_D0

F9

DDR_A_D5

F8

DDR_A_D3

E11

DDR_A_D6

E10

DDR_A_D4

E9

DDR_A_D2

D9

DDR_A_D40

T8

DDR_A_D45

T9

DDR_A_D43

T10

DDR_A_D47

T11

DDR_A_D44

R8

DDR_A_D41

R9

DDR_A_D46

R10

DDR_A_D42

R11

DDR_A_D33

C11

DDR_A_D37

C10

DDR_A_D34

C9

DDR_A_D39

C8

DDR_A_D36

B11

DDR_A_D32

B10

DDR_A_D35

B9

DDR_A_D38

B8

DDR_A_CA2_0

R2

CA0

DDR_A_CA2_1

P2

CA1

DDR_A_CA2_2

N2

CA2

DDR_A_CA2_3

N3

CA3

DDR_A_CA2_4

M3

CA4

DDR_A_CA2_5

F3

CA5

DDR_A_CA2_6

E3

CA6

DDR_A_CA2_7

E2

CA7

DDR_A_CA2_8

D2

CA8

DDR_A_CA2_9

C2

CA9

DDR_A_DQS1

L10

DDR_A_DQS0

G10

DDR_A_DQS5

P10

DDR_A_DQS4

D10

DDR_A_DQS#1

L11

DDR_A_DQS#0

G11

DDR_A_DQS#5

P11

DDR_A_DQS#4

D11

L8

DM0

G8

DM1

P8

DM2

D8

DM3

DDR_A1_ZQ0

B3

ZQ0

DDR_A1_ZQ1

B4

ZQ1

K3
K4

DDR_A_CS#0

L3

DDR_A_CS#1

L4

J3

CK

J2

CK#

DDR_A_ODT0

J8

ODT

J11
H4

B2

VSS

B5

VSS

C5

VSS

E4

VSS

E5

VSS

F5

VSS

H2

VSS

J12

VSS

K2

VSS

L6

VSS

M5

VSS

N4

VSS

N5

VSS

R4

VSS

R5

VSS

T2

VSS

T3

VSS

T4

VSS

T5

VSS

1

RD1 240_0402_1%

1 2

RD2 240_0402_1%

1 2

DDR_A_CKE2 6,21
DDR_A_CKE3 6,21

DDR_A_CLK1 6,21
DDR_A_CLK#1 6,21

+VREFDQ_A
+VREFCA

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

CD69

CD71

1

1

2

2

Decoupling per DRAM device
VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF
VDDCA 2x 0402 1uF 1x 0603 10uF
VDD2 3x 0402 1uF 1x 0603 10uF
VDD1 2x 0402 1uF 1x 0603 10uF

intel uesd 0201 for 0.1uF

A A

5

4

+1.2V_DDR

3

+1.8VU

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD32

12

CD41

12

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P19-DDRIII Channel A

P19-DDRIII Channel A

P19-DDRIII Channel A

Document Number Re v

Document Number Re v

Document Number Re v

LA-F371P

LA-F371P

LA-F371P

1

19 65Tuesday, November 07, 2017

19 65Tuesday, November 07, 2017

19 65Tuesday, November 07, 2017

1.0

1.0

1.0

5

DDR_B_DQS#[0..7]6

DDR_B_DQS[0..7]6

DDR_B_D[0..63]6

DDR_B_CA1_[0..9]6,21

DDR_B_CA2_[0..9]6,21

D D

+1.8VU+1.8VU

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

12

CD35

CD49

1

2

+1.8VU +1.8VU

1U_0402_6.3V6K~D

CD7

1

2

+1.2V_DDR

+1.2V_DDR

10U_0603_6.3V6M~D

CD17

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

2

1U_0402_6.3V6K~D

CD76

CD51

CD33

1

1

2

2

+1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR

Closed to UD21

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD1

1

12

2

C C

B B

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD13

CD82

CD30

1

1

2

2

+1.2V_DDR

10U_0603_6.3V6M~D

0.1U_0402_16V7K~D

1U_0402_6.3V6K~D

CD15

1

2

CD73

12

1

2

+1.2V_DDR

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

1

CD28

CD6

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD5

CD29

1

1

2

2

4

UD3

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

DDR_B_D30

P9

DQ0

DDR_B_D28

N9

DQ1

DDR_B_D26

N10

DQ2

DDR_B_D27

N11

DQ3

DDR_B_D29

M8

DQ4

DDR_B_D24

M9

DQ5

DDR_B_D25

M10

DQ6

DDR_B_D31

M11

DQ7

DDR_B_D48

F11

DQ8

DDR_B_D51

F10

DQ9

DDR_B_D50

F9

DQ10

DDR_B_D54

F8

DQ11

DDR_B_D52

E11

DQ12

DDR_B_D49

E10

DQ13

DDR_B_D55

E9

DQ14

DDR_B_D53

D9

DQ15

DDR_B_D62

T8

DQ16

DDR_B_D58

T9

DQ17

DDR_B_D61

T10

DQ18

DDR_B_D56

T11

DQ19

DDR_B_D63

R8

DQ20

DDR_B_D59

R9

DQ21

DDR_B_D57

R10

DQ22

DDR_B_D60

R11

DQ23

DDR_B_D19

C11

DQ24

DDR_B_D18

C10

DQ25

DDR_B_D16

C9

DQ26

DDR_B_D17

C8

DQ27

DDR_B_D23

B11

DQ28

DDR_B_D22

B10

DQ29

DDR_B_D21

B9

DQ30

DDR_B_D20

B8

DQ31

DDR_B_CA1_0

R2

CA0

DDR_B_CA1_1

P2

CA1

DDR_B_CA1_2

N2

CA2

DDR_B_CA1_3

N3

CA3

DDR_B_CA1_4

M3

CA4

DDR_B_CA1_5

F3

CA5

DDR_B_CA1_6

E3

CA6

DDR_B_CA1_7

E2

CA7

DDR_B_CA1_8

D2

CA8

DDR_B_CA1_9

C2

CA9

DDR_B_DQS3

L10

DQS0

DDR_B_DQS6

G10

DQS1

DDR_B_DQS7

P10

DQS2

DDR_B_DQS2

D10

DQS3

DDR_B_DQS#3

L11

DQS0#
DQS1#
DQS2#
DQS3#

Vref_DQ
Vref_CA

DDR_B_DQS#6

G11

DDR_B_DQS#7

P11

DDR_B_DQS#2

D11

L8

DM0

G8

DM1

P8

DM2

D8

DM3

DDR_B0_ZQ0

RD13 240_0402_1%

B3

ZQ0

DDR_B0_ZQ1

B4

ZQ1

K3

CKE0

K4

CKE1

DDR_B_CS#0

L3

CS0#

DDR_B_CS#1 DDR_B_CS#1

L4

CS1#

J3

CK

J2

CK#

DDR_B_ODT0

J8

ODT

J11
H4

B2

VSS

B5

VSS

C5

VSS

E4

VSS

E5

VSS

F5

VSS

H2

VSS

J12

VSS

K2

VSS

L6

VSS

M5

VSS

N4

VSS

N5

VSS

R4

VSS

R5

VSS

T2

VSS

T3

VSS

T4

VSS

T5

VSS

Decoupling per DRAM device
VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF
VDDCA 2x 0402 1uF 1x 0603 10uF
VDD2 3x 0402 1uF 1x 0603 10uF
VDD1 2x 0402 1uF 1x 0603 10uF

1 2

RD14 240_0402_1%

1 2

DDR_B_CKE0 6,21
DDR_B_CKE1 6,21 DDR_B_CKE3 6,21

DDR_B_CS#0 6,21
DDR_B_CS#1 6,21

DDR_B_CLK0 6,21
DDR_B_CLK#0 6, 21

DDR_B_ODT0 6,21

+VREFDQ_B
+VREFCA

Closed to DRAM Closed to DRAM

+VREFDQ_B +VREFDQ_B+VREFCA +VREFCA

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

CD19

1

2

CD47

1

2

3

10U_0603_6.3V6M~D

+1.2V_DDR+1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M~D

CD81

12

+1.2V_DDR +1.2V_DDR +1.2V_DDR

Closed to UD22

10U_0603_6.3V6M~D

CD64

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

2

1U_0402_6.3V6K~D

CD52

CD25

CD85

1

1

2

2

+1.2V_DDR

10U_0603_6.3V6M~D

12

All VREF traces should
have 10 mil trace width

+1.8VU+1.8VU

1U_0402_6.3V6K~D

CD48

12

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD78

1

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

CD75

1

1

2

2

+1.2V_DDR +1.2V_DDR

1U_0402_6.3V6K~D

CD62

2

UD1

1U_0402_6.3V6K~D

CD34

CD55

1

1

2

2

+1.2V_DDR

1U_0402_6.3V6K~D

CD53

CD68

1

1

2

2

+1.2V_DDR

0.1U_0402_16V7K~D

1

CD4

CD26

2

1U_0402_6.3V6K~D

CD66

CD8

1

1

2

2

@

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

H9CCNNN8JTMLAR-NTM_FBGA178~D

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0
DQS1
DQS2
DQS3

DQS0#
DQS1#
DQS2#
DQS3#

CKE0
CKE1

CS0#
CS1#

Vref_DQ
Vref_CA

DDR_B_D9

P9

DQ0

DDR_B_D15

N9

DQ1

DDR_B_D13

N10

DQ2

DDR_B_D12

N11

DQ3

DDR_B_D14

M8

DQ4

DDR_B_D10

M9

DQ5

DDR_B_D8

M10

DQ6

DDR_B_D11

M11

DQ7

DDR_B_D39

F11

DQ8

DDR_B_D38

F10

DQ9

DDR_B_D37

F9

DDR_B_D33

F8

DDR_B_D34

E11

DDR_B_D35

E10

DDR_B_D32

E9

DDR_B_D36

D9

DDR_B_D1

T8

DDR_B_D5

T9

DDR_B_D7

T10

DDR_B_D2

T11

DDR_B_D0

R8

DDR_B_D4

R9

DDR_B_D3

R10

DDR_B_D6

R11

DDR_B_D41

C11

DDR_B_D45

C10

DDR_B_D42

C9

DDR_B_D47

C8

DDR_B_D44

B11

DDR_B_D40

B10

DDR_B_D43

B9

DDR_B_D46

B8

DDR_B_CA2_0

R2

CA0

DDR_B_CA2_1

P2

CA1

DDR_B_CA2_2

N2

CA2

DDR_B_CA2_3

N3

CA3

DDR_B_CA2_4

M3

CA4

DDR_B_CA2_5

F3

CA5

DDR_B_CA2_6

E3

CA6

DDR_B_CA2_7

E2

CA7

DDR_B_CA2_8

D2

CA8

DDR_B_CA2_9

C2

CA9

DDR_B_DQS1

L10

DDR_B_DQS4

G10

DDR_B_DQS0

P10

DDR_B_DQS5

D10

DDR_B_DQS#1

L11

DDR_B_DQS#4

G11

DDR_B_DQS#0

P11

DDR_B_DQS#5

D11

L8

DM0

G8

DM1

P8

DM2

D8

DM3

DDR_B1_ZQ0

B3

ZQ0

DDR_B1_ZQ1

B4

ZQ1

K3
K4

DDR_B_CS#0

L3
L4

J3

CK

J2

CK#

DDR_B_ODT0

J8

ODT

J11
H4

B2

VSS

B5

VSS

C5

VSS

E4

VSS

E5

VSS

F5

VSS

H2

VSS

J12

VSS

K2

VSS

L6

VSS

M5

VSS

N4

VSS

N5

VSS

R4

VSS

R5

VSS

T2

VSS

T3

VSS

T4

VSS

T5

VSS

1

RD8 240_0402_1%

1 2

RD7 240_0402_1%

1 2

DDR_B_CKE2 6,21

DDR_B_CLK1 6,21
DDR_B_CLK#1 6, 21

+VREFDQ_B
+VREFCA

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

CD70

1

2

CD72

1

2

intel uesd 0201 for 0.1uF

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/10/22 2013/10/28

2015/10/22 2013/10/28

2015/10/22 2013/10/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

P20-DDRIII Channel B

P20-DDRIII Channel B

P20-DDRIII Channel B

Document Number Re v

Document Number Re v

Document Number Re v

LA-F371P

LA-F371P

LA-F371P

1

20 65Tuesday, November 07, 2017

20 65Tuesday, November 07, 2017

20 65Tuesday, November 07, 2017

1.0

1.0

1.0