Datasheet SY100S324 Datasheet (MICREL)

LOW POWER HEX

L

TTL-to-ECL
TRANSLATOR

SY100S324

FEATURES

■ Max. propagation delay of 1.4ns

■ IEE min. of –70mA

■ Industry standard 100K ECL levels

■ Extended supply voltage option:

VEE = –4.2V to –5.5V

■ Differential outputs

■ Voltage and temperature compensation for improved

noise immunity

■ Internal 75KΩ input pull-down resistors

■ Twice as fast as Fairchild’s 324

■ Function and pinout compatible with Fairchild F100K

■ Available in 24-pin CERPACK and 28-pin PLCC

packages

BLOCK DIAGRAM

E

Q

D

0

D

1

D

2

D

3

D

4

D

5

0

Q

0

Q

1

Q

1

Q

2

Q

2

Q

3

Q

3

Q

4

Q

4

Q

5

Q

5

DESCRIPTION

The SY100S324 is a hex translator designed to convert
TTL logic levels to 100K ECL levels. The inputs are TTL
compatible with differential outputs that can either be
used as an inverting/non-inverting translator or as
differential line drivers. A common Enable (E), when LOW,
holds all inverting outputs HIGH and holds all non­inverting outputs LOW.

When used in the differential mode, due to its high
common mode rejection, it overcomes voltage gradients
between the TTL and ECL ground systems. The VEE and
VTTL power may be applied in either order.

PIN CONFIGURATIONS

1

0

EES

V

Q

Q1Q

25

24 23 22 21 20 19

26

Q

2

27

Q

2

28

V

CC

1

V

CC
CCA
CCA

Q

2
3
4

3

V
V

Top View

PLCC

J28-1

567891011

4

4

Q

Q3Q

EES

V

Q0D

5

Q

D
D
Q
Q
Q
Q

1

2

D

18

D

0

17

V

TTL

16

E

15

V

EES

14

V

EE

13

D

3

12

D

4

0

5

5

D

Q

1
2
0
0
1
1

TT

D

E

V

24 23 22 21 20 19

1
2
3
4
5
6

Top View

Flatpack

F24-1

7891011

2

2

CC

Q

Q

V

EE

V

CCA

V

3

D

CCA

V

4

D

18

D

5

17

Q

5

16

Q

5

15

Q

4

14

Q

4

13

Q

3

12

3

Q

PIN NAMES

Pin Function

D0–D5 Data Inputs
E Enable Inputs
Q0–Q5 Data Outputs
Q0–Q5 Complementary Data Outputs
VEES VEE Substrate
VTTL TTL VCC Power Supply

CCA VCCO for ECL Outputs

V

Rev.: F Amendment: /0

1

Issue Date: July, 1999

Micrel

SY100S324

DC ELECTRICAL CHARACTERISTICS

VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND, VTTL = +4.5V to +5.5V

Symbol Parameter Min. Sim. Max. Unit Condition

OH Output HIGH Voltage –1025 –986 –880 mV VIN = VIH (Max.) Loading with 50Ω

V
VOL Output LOW Voltage –1810 –1674 –1620 mV VIN = VIL (Min.)

OHC Output HIGH Voltage –1035 ——mV VIN = VIH (Min.) Loading with 50Ω to –2V

V
VOLC Output LOW Voltage ——–1610 mV VIN = VIL (Max.)

VIH Input HIGH Voltage 2.0 — 5.0 V Guaranteed HIGH Signal for All Inputs
VIL Input LOW Voltage 0 — 0.8 V Guaranteed LOW Signal for All Inputs
VCD Input Clamp Diode Voltage ——–1.5 V IIN = –10mA

IH Input HIGH Current

I

Data ——20 µAVIN = +2.4V
Enable ——120 All Other Inputs VIN = GND

IH Input HIGH Current ——1.0 mA VIN = +5.5V, VTTL = Max.,

I

Breakdown Test, All Inputs All Other Inputs VIN = GND

IL Input LOW Current

I

Data –1.2 ——mA VIN = +0.4V

Enable –6.7 —— All Other Inputs VIN = VIH
IEE VEE Power Supply Current –70 –45 –28 mA All Inputs VIN = +4.0V
I

TTL VTTL Power Supply Current — 25 35 mA All Inputs VIN = GND

AC ELECTRICAL CHARACTERISTICS

PLCC /FLATPACK

VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND, VTTL = +4.5V to +5.5V

Symbol Parameter Min. Typ. Max. Unit Condition

PLH Propagation Delay 400 850 1400 ps See Switching Wave Form Figures

t
tPHL Data and Enable to Output

TLH Transition Time 350 — 1700 ps

t
tTHL 20% to 80%, 80% to 20%

2

Micrel

SWITCHING WAVEFORM

SY100S324

80%

INPUT

t

PHL

50%

t

PLH

COMPLEMENT

t

PLH

t

PHL

80%

TRUE

t

TLH

Figure 1. Propagation Delay and Transition Times

NOTE:

VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND, VTTL = +4.5V to +5.5V

TEST CIRCUIT

V

IH

V

TTL

20%

2.5 ± 0.3 ns2.5 ± 0.3 ns
+3.0V

+1.5V

0V

50%

50%

20%

t

THL

SCOPE

CHAN A

PULSE

GENERATOR

NOTES:

VCC, VCCA = +2V, VEE = –2.5V, VTTL = +7.0V, VIH = +6.0V
L1, L2 and L3 = equal length 50Ω impedance lines
RT = 50Ω terminator internal to scope
Decoupling 0.1µF from GND to VCC, VEE and VTTL
All unused outputs are loaded with 50Ω to GND
CL = Fixture and stray capacitance ≤ 3pF

L1

R

T

0.1µF

V

EE

Figure 2. AC Test Circuit

L2

L3

0.1µF

SCOPE

CHAN B

R

T

2.5µF

0.1µF0.1µF

V

CC

PRODUCT ORDERING CODE

Ordering Package Operating

Code Type Range

SY100S324FC F24-1 Commercial
SY100S324JC J28-1 Commercial
SY100S324JCTR J28-1 Commercial

3

Micrel

24 LEAD CERPACK (F24-1)

SY100S324

Rev. 03

4

Micrel

28 LEAD PLCC (J28-1)

SY100S324

Rev. 03

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA

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© 2000 Micrel Incorporated

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