The SP6200 and SP6201 are CMOS Low Dropout (LDO) regulators designed to meet a broad range of applications that
require accuracy, speed and ease of use. These LDOs offer extremely low quiescent current which only increases
slightly under load, thus providing advantages in ground current performance over bipolar LDOs. The LDOs handle an
extremely wide load range and guarantee stability with a 1µF ceramic output capacitor. They have excellent low
frequency Power Supply Rejection Ratio (PSRR), not found in other CMOS LDOs and thus offer exceptional Line
Regulation. High frequency PSRR is better than 40dB up to 400kHz. Load Regulation is excellent and temperature
stability is comparable to bipolar LDOs. An enable feature is provided on all versions.
The SP6200/6201 is available in fixed and adjustable output voltage versions in tiny DFN and small SOT-23-5
packages. A V
good indicator is provided on all fixed output versions.
EN (pin 3) may be connected
directly to IN (pin 1).
3
SP6201
4
470kΩ
RSN
V
OUT
C
= 1µF
OUT
(V
good)
OUT
1
Page 2
ABSOLUTE MAXIMUM RATINGS, NOTE 1
These are stress ratings only and functional operation of
the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect
reliability.
Supply Input Voltage (VIN)............................. -2V to 7V
Output Voltage (V
Enable Input Voltage (VEN)............................ -2V to 7V
Power Dissipation (PD).......... Internally Limited, No t e 3
Lead Temperature (soldering 5s)....................... 260°C
Storage Temperature ........................ -65˚C to +150˚C
) ......................... -0.6 to ( VIN +1V)
OUT
OPERATING RATINGS, NOTE 2
Input Voltage (VIN)..................................+2.5V to +6V
Enable Input Voltage (VEN)..........................0V to +6V
Junction Temperature (TJ)................-40˚C to +125˚C
Note 1. Exceeding the absolute maximum rating may damage the device.
Note 2. The device is not guaranteed to function outside its operating rating.
Note 3. The maximum allowable power dissipation at any TA (ambient temperature) is P
Exceeding the maximum allowable power dissipation will result in excessive die temperature, and the regulator will
D (MAX)
= (TJ
– TA) / θϑA.
(MAX)
go into thermal shutdown. The θJA of the SP6200/6201 (all versions) is 191°C/W for the SOT-23-5 and 59°C/W for
the DFN package on a standard 4 layer board (see “Thermal Considerations” section for further details).
Note 4. Output voltage temperature coefficient is defined as the worst case voltage change divided by the total
temperature range.
Note 5. Load Regulation is measured at constant junction temperature using low duty cycle pulse testing. Parts are
tested for load regulation in the load range; from 0.1mA to 100mA, SP6200; from 0.1mA to 200mA, SP6201. Changes
in output voltage due to heating effects are covered by the thermal regulation specification. Not applicable to output
voltages less than 2.5V.
Note 6. Dropout Voltage is defined as the input to output differential at which the output voltage drops 2% below
its nominal value measured at 1V differential. Not applicable to output voltages less than 2.7V.
Note 7. Ground pin current is the regulator quiescent current. The total current drawn from the supply is the sum
of the load current plus the ground pin current.
Note 8. Thermal regulation is defined as the change in output voltage at a time ”t” after a change in power dissipation
is applied, excluding load or line regulation effects. Specifications are for a 100mA load pulse at VIN = 6V for t = 10ms.
The SP6200 and SP6201 are CMOS LDOs
designed to meet a broad range of applications
that require accuracy, speed and ease of use.
These LDOs offer extremely low quiescent current which only increases slightly under load,
thus providing advantages in ground current
performance over bipolar LDOs. The LDOs
handle an extremely wide load range and guarantee stability with a 1µF ceramic output capacitor. They have excellent low frequency
PSRR, not found in other CMOS LDOs and thus
offer exceptional Line Regulation. High frequency PSRR is better than 40dB up to 400kHz.
Load Regulation is excellent and temperature
stability is comparable to bipolar LDOs. Thus,
overall system accuracy is maintained under all
DC and AC conditions. Enable feature is provided on all versions. A Vout good indicator
(RSN pin) is provided in all the fixed output
voltage devices. An adjustable output version is
also available. Current Limit and Thermal protection is provided internally and is well controlled.
Architecture
The SP6200 and SP6201 are only different in
their current limit threshold. The SP6200 has a
current limit of 140mA, while the SP6201 current limit is 420mA. The SP6201 can provide
pulsed load current of 300mA. The LDOs have
a two stage amplifier which handles an extremely wide load range (10µA to 300mA) and
guarantees stability with a 1µF ceramic load
capacitor. The LDO amplifier has excellent gain
and thus touts PSRR performance not found in
other CMOS LDOs. The amplifier guarantees
no overshoot on power up or while enabled
through the EN pin. The amplifier also contains
an active pull down, so that when the load is
removed quickly the output voltage transient is
minimal; thus output deviation due to load transient is small and fairly well matched when
connecting and disconnecting the load.
An accurate 1.250V bandgap reference is
bootstrapped to the output in fixed output versions of 2.7V and higher. This increases both the
low frequency and high frequency PSRR. The
adjustable version also has the bandgap reference bootstrapped to the output, thus the lowest
externally programmable output voltage is 2.7V.
The 2.5V fixed output version has the bandgap
always connected to the Vin pin. Unlike many
LDOs, the bandgap reference is not brought out
for filtering by the user. This tradeoff was maid
to maintain good PSRR at high frequency (PSRR
can be degraded in a system due to switching
noise coupling into this pin). Also, often leakages of the bypass capacitor or other components cause an error on this high impedance
bandgap node. Thus, this tradeoff has been
made with "ease of use" in mind.
Protection
Current limit behavior is very well controlled,
providing less than 10% variation in the current
limit threshold over the entire temperature range
for both SP6200 and SP6201. The SP6200 has a
current limit of 140mA, while the SP6201 has a
current limit of 420mA. Thermal shutdown activates at 162°C and deactivates at 147°C. Thermal shutdown is very repeatable with only a 2 to
3 degree variation from device to device. Thermal shutdown changes by only 1 to 2 degrees
with Vin change from 4V to 7V.
Enable (Shutdown Not) Input
The LDOs are turned off by pulling the EN pin
low and turned on by pulling it high. If it is not
necessary to shut down the LDO, the EN (pin 3)
should be tied to IN (pin 1) to keep the regulator
output on at all time. The enable threshold is
0.9V and does not change more than 100mV
over the entire temperature and Vin voltage
range. The lot to lot variations in Enable Threshold is also within 100mV. Shutdown current is
guaranteed to be <1uA without requiring the
user to pull enable all the way to 0V. Standard
TTL or CMOS levels will transition the device
from totally on to totally off.
An accurate Vout good indicator is provided on
all the fixed output version devices, pin 4 (RSN),
Figure 1. This is an open drain, logic output that
can be used to hold a microprocessor or microcontroller in a RESET condition when it's power
supplied by Vout is 4% out of nominal regulation. A 1% hysteresis is included in the Reset
Not function, so that false alarms are not issued
as a result of LDO's output noise. The Reset Not
function reacts in 10 to 50µs.
Adjustable Output Version
The adjustable version can be programmed to
any voltage from 2.7V to 6V for the industrial
temperature range; 2.5V to 6V for the commercial temperature range. The output can not be
programmed below 2.5V due a headroom restriction. Since the bandgap is bootstrapped to
the output, the output voltage must be above the
minimum bandgap supply voltage. The bandgap
requires 2.7V or greater at -40°C and requires
2.5V or greater at 0°C.
The regulator's output can be adjusted to a
specific output voltage by using two external
resistors, Figure 2. The resistor's set the output
voltage based on the following equation:
V
= 1.25 (R2/R1 + 1)
OUT
Resistor values are not critical because the ADJ
node has a high input impedance, but for best
results use resistors of 470kΩ or less. A capacitor from ADJ to Vout pin provides improved
noise performance as is shown in the following
plot.
Noise Performance 10Hz to 100kHz
Adj, Vin = 4.3V, Vout = 3.3V (Cin = Cout = 1uF)
400
300
200
Output Noise (uVrms)
100
1.0E+021.0E+031.0E+041.0E+051.0E+061.0E+07
Bypass Cap from Vout to FB (pF)
THEORY OF OPERATION: Continued
Input Capacitor
A small capacitor, 1µF or higher, is required
from V
to GND to create a high frequency
IN
bypass for the LDO amplifier. Any ceramic or
tantalum capacitor may be used at the input.
Capacitor ESR (effective series resistance)
should be smaller than 3Ω.
Output Capacitor
An output capacitor is required between V
OUT
and GND to prevent oscillation. A capacitance
as low as 0.22µF can fulfill stability requirements in most applications. A 1µF capacitor
will ensure unconditional stability from no load
to full load over the entire input voltage, output
voltage and temperature range. Larger capacitor
values improve the regulator's transient response.
The output capacitor value may be increased
without limit. The output capacitor should have
an ESR (effective series resistance) below 5Ω
and a resonant frequency above 1MHz.
No Load Stability
The SP6200/6201 will remain stable and in
regulation with no external load (other than the
internal voltage driver) unlike many other voltage regulators. This is especially important in
CMOS RAM keep-alive applications.
Thermal Considerations
The SP6200 is designed to provide 100mA of
continuous current, while the SP6201 will provide 200mA of continuous current. Maximum
power dissipation can be calculated based on the
output current and the voltage drop across the
part. To determine the maximum power dissipation in the package, use the junction-to-ambient
thermal resistance of the device and the following basic equation:
(T
PD =
T
is the maximum junction temperature of
J(max)
J(max)
θ
- TA)
JA
the die and is 125°C. TA is the ambient operating.
θJA is the junction-to-ambient thermal resistance
for the regulator and is layout dependent.
The actual power dissipation of the regulator
circuit can be determined using one simple
for PD and solving for the
operating conditions that are critical to the application will give the maximum operating conditions for the regulator circuit. For example, if
we are operating the SP6201- 3.0V at room
temperature, with a SOT-23-5 package on a 4
layer standard board we can determine the maximum input voltage for a set output current.
P
D(max)
(125°C -25°C)
=
(191°C/W)
= 0.52W
To prevent the device from entering thermal
shutdown, maximum power dissipation can not
be exceeded. Using the output voltage of 3.0V
and an output current of 200 mA, the maximum
input voltage can be determined. Ground pin
current can be taken from the electrical spec’stable (I
mum input voltage is determined as follows:
=200uA at I
GND
=200mA). The maxi-
OUT
0.52W = (VIN – 3.0V)*200mA + VIN*0.2mA
Solving for VIN, we get:
(0.52W + 0.6W)
VIN =
200.2mA
After calculations, we find that the maximum
input voltage of a 3.0V application at 200mA of
output current in an SOT-23-5 package is 5.59V.
Dual-Supply Operation
When used in dual supply systems where the
regulator load is returned to a negative supply,
the output voltage must be diode clamped to
ground.
SP6200EM5/TREADJ-40˚C to +125˚CADJ5 Pin SOT-23
SP6200EM5-1-5 E15-40˚C to +125˚C1.5V5 Pin SOT-23
SP6200EM5-1-5/TR E15-40˚C to +125˚C1.5V5 Pin SOT-23
SP6200EM5-1-8
E18
-40˚C to +125˚C1.8V5 Pin SOT-23
SP6200EM5-1-8/TRE18-40˚C to +125˚C1.8V5 Pin SOT-23
SP6200EM5-2-5E25-40˚C to +125˚C2.5V5 Pin SOT-23
SP6200EM5-2-5/TRE25-40˚C to +125˚C2.5V5 Pin SOT-23
SP6200EM5-2-7
E27
-40˚C to +125˚C2.7V5 Pin SOT-23
SP6200EM5-2-7/TRE27-40˚C to +125˚C2.5V5 Pin SOT-23
SP6200EM5-2-85E285-40˚C to +125˚C2.85V5 Pin SOT-23
SP6200EM5-2-85/TRE285-40˚C to +125˚C2.85V5 Pin SOT-23
SP6200EM5-3-0
E30
-40˚C to +125˚C3.0V5 Pin SOT-23
SP6200EM5-3-0/TRE30-40˚C to +125˚C3.0V5 Pin SOT-23
SP6200EM5-3-3E33-40˚C to +125˚C3.3V5 Pin SOT-23
SP6200EM5-3-3/TRE33-40˚C to +125˚C3.3V5 Pin SOT-23
SP6200EM5-3-5
E35
-40˚C to +125˚C3.5V5 Pin SOT-23
SP6200EM5-3-5/TRE35-40˚C to +125˚C3.5V5 Pin SOT-23
SP6200EM5-5-0E50-40˚C to +125˚C5.0V5 Pin SOT-23
SP6200EM5-5-0/TRE50-40˚C to +125˚C5.0V5 Pin SOT-23
SP6201EM5
FADJ
-40˚C to +125˚CADJ5 Pin SOT-23
SP6201EM5/TRFADJ-40˚C to +125˚CADJ5 Pin SOT-23
SP6201EM5-1-5 F15-40˚C to +125˚C1.5V5 Pin SOT-23
SP6201EM5-1-5/TR F15-40˚C to +125˚C1.5V5 Pin SOT-23
SP6201EM5-1-8
F18
-40˚C to +125˚C1.8V5 Pin SOT-23
SP6201EM5-1-8/TRF18-40˚C to +125˚C1.8V5 Pin SOT-23
SP6201EM5-2-5F25-40˚C to +125˚C2.5V5 Pin SOT-23
SP6201EM5-2-5/TRF25-40˚C to +125˚C2.5V5 Pin SOT-23
SP6201EM5-2-7
F27
-40˚C to +125˚C2.7V5 Pin SOT-23
SP6201EM5-2-7/TRF27-40˚C to +125˚C2.5V5 Pin SOT-23
SP6201EM5-2-85F285-40˚C to +125˚C2.85V5 Pin SOT-23
SP6201EM5-2-85/TRF285-40˚C to +125˚C2.85V5 Pin SOT-23
SP6201EM5-3-0
F30
-40˚C to +125˚C3.0V5 Pin SOT-23
SP6201EM5-3-0/TRF30-40˚C to +125˚C3.0V5 Pin SOT-23
SP6201EM5-3-3F33-40˚C to +125˚C3.3V5 Pin SOT-23
SP6201EM5-3-3/TRF33-40˚C to +125˚C3.3V5 Pin SOT-23
SP6201EM5-3-5
F35
-40˚C to +125˚C3.5V5 Pin SOT-23
SP6201EM5-3-5/TRF35-40˚C to +125˚C3.5V5 Pin SOT-23
SP6201EM5-5-0F50-40˚C to +125˚C5.0V5 Pin SOT-23
SP6201EM5-5-0/TRF50-40˚C to +125˚C5.0V5 Pin SOT-23
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6200EM5-1-5/TR = standard; SP6200EM5-L-1-5/TR = lead free. Lead
Free SOT-23 packages can be identified by a Bar “|” to the left of the standard Top Marking.
/TR = Tape and Reel. Pack quantity is 2500 for SOT-23.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
Solved By SipexTM
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
SP6200ER/TR620-0ER-40˚C to +125˚CADJ8 Pin DFN
SP6200ER-1-5 620-015-40˚C to +125˚C1.5V8 Pin DFN
SP6200ER-1-5/TR 620-015-40˚C to +125˚C1.5V8 Pin DFN
SP6200ER-1-8
620-018
-40˚C to +125˚C1.8V8 Pin DFN
SP6200ER-1-8/TR620-018-40˚C to +125˚C1.8V8 Pin DFN
SP6200ER-2-5620-025-40˚C to +125˚C2.5V8 Pin DFN
SP6200ER-2-5/TR620-025-40˚C to +125˚C2.5V8 Pin DFN
SP6200ER-2-7
620-027
-40˚C to +125˚C2.7V8 Pin DFN
SP6200ER-2-7/TR620-027-40˚C to +125˚C2.5V8 Pin DFN
SP6200ER-2-85620-0285-40˚C to +125˚C2.85V8 Pin DFN
SP6200ER-2-85/TR620-0285-40˚C to +125˚C2.85V8 Pin DFN
SP6200ER-3-0
620-030
-40˚C to +125˚C3.0V8 Pin DFN
SP6200ER-3-0/TR620-030-40˚C to +125˚C3.0V8 Pin DFN
SP6200ER-3-3620-033-40˚C to +125˚C3.3V8 Pin DFN
SP6200ER-3-3/TR620-033-40˚C to +125˚C3.3V8 Pin DFN
SP6200ER-3-5
620-035
-40˚C to +125˚C3.5V8 Pin DFN
SP6200ER-3-5/TR620-035-40˚C to +125˚C3.5V8 Pin DFN
SP6200ER-5-0620-050-40˚C to +125˚C5.0V8 Pin DFN
SP6200ER-5-0/TR620-050-40˚C to +125˚C5.0V8 Pin DFN
SP6201ER
620-1ER
-40˚C to +125˚CADJ8 Pin DFN
SP6201ER/TR620-1ER-40˚C to +125˚CADJ8 Pin DFN
SP6201ER-1-5 620-115-40˚C to +125˚C1.5V8 Pin DFN
SP6201ER-1-5/TR 620-115-40˚C to +125˚C1.5V8 Pin DFN
SP6201ER-1-8
620-118
-40˚C to +125˚C1.8V8 Pin DFN
SP6201ER-1-8/TR620-118-40˚C to +125˚C1.8V8 Pin DFN
SP6201ER-2-5620-125-40˚C to +125˚C2.5V8 Pin DFN
SP6201ER-2-5/TR620-125-40˚C to +125˚C2.5V8 Pin DFN
SP6201ER-2-7
620-127
-40˚C to +125˚C2.7V8 Pin DFN
SP6201ER-2-7/TR620-127-40˚C to +125˚C2.5V8 Pin DFN
SP6201ER-2-85620-1285-40˚C to +125˚C2.85V8 Pin DFN
SP6201ER-2-85/TR620-1285-40˚C to +125˚C2.85V8 Pin DFN
SP6201ER-3-0
620-130
-40˚C to +125˚C3.0V8 Pin DFN
SP6201ER-3-0/TR620-130-40˚C to +125˚C3.0V8 Pin DFN
SP6201ER-3-3620-133-40˚C to +125˚C3.3V8 Pin DFN
SP6201ER-3-3/TR620-133-40˚C to +125˚C3.3V8 Pin DFN
SP6201ER-3-5
620-135
-40˚C to +125˚C3.5V8 Pin DFN
SP6201ER-3-5/TR620-135-40˚C to +125˚C3.5V8 Pin DFN
SP6201ER-5-0620-150-40˚C to +125˚C5.0V8 Pin DFN
SP6201ER-5-0/TR620-150-40˚C to +125˚C5.0V8 Pin DFN
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6200ER-1-5/TR = standard; SP6200ER-L-1-5/TR = lead free.
Lead Free DFN packages can be identified by a Bar “__” under the standard Top Marking.
/TR = Tape and Reel. Pack quantity is 3,000 for DFN.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
Solved By SipexTM
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.