Datasheet SP600 Datasheet (Intersil)

Semiconductor

E

PART WITHDRAWN

Features

• Maximum Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . 500V

• Ability to Interface and Drive Standard and Current
Sensing N-Channel Power MOSFET/IGBT Devices

• Creation and Management of a Floating Power Supply
for Upper Rail Drive

• Simultaneous Conduction Lockout

PROCESS OBSOLETE

NO NEW DESIGNS

SP600

July 1998 File Number 2428.4

Half Bridge 500VDC Driver

The SP600 is a smart power high voltage integrated circuit
(HVIC) optimized to drive MOS gated power devices in half­bridge topologies. It provides the necessary control and
management for PWM motor drive, power supply, and UPS
applications.

• Overcurrent Protection

• Single Low Current Bias Supply Operation

• Latch Immune CMOS Logic

• Peak Drive in Excess of 0.5A

Pinout

1

FAULT

I

2

TRIPSEL

V

3

BIAS

V

4

DD

V

5

SS

TRIP

6

L

7

CL1
G2L

8

G1L

9

D1L

10

V

11

DF

SP600 (PDIP)

TOP VIEW

22

TOP

21

BOT

20

NC
D1U

19

G1U

18

G2U

17

CL2

16

TRIP

15

PHAS

14

V

13

OUT

V

12

BS

Functional Block Diagram

10Ω R

V

BIAS

3

V

DD

4

V

DF

11

U

TOP

22

BOT

21

FAULT

1

I

TRIPSEL

2

3.5Ω R

750Ω R

ND

BS

Ordering Information

PART TEMPERATURE PACKAGE

SP600 -40oC to +85oC 22 Lead Plastic DIP

V

BS

12

D1U

19

3.5Ω R

G1U

18

G2U

17

TRIP

15

CL2

16

PHASE

14

O

13

D1L

10

G1L

9

G2L

8

TRIP

6

CL1

7

V

SS

5

U

V

OUT

LOWER UPPER

L

I

ONT

I

LEVEL

OFFT

SHIFT

UV

LOCK

OUT

I

TRIPSEL

I

ONB

I

I

TRIPSEL

OFFB

UV

LOCK

OUT

CMOS

TIMING

AND

CONTROL

F

S

Q

R

FILTER

FAULT

V

OUT

SENSE

AND

FILTER

S

Q

R

+

-

S

Q

R

S

Q

R

+

-

S

Q

R

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Copyright © Harris Corporation 1998

SP600

Absolute Maximum Ratings Full Temperature Range, All

Thermal Information

VoltageReferenced to VSSUnless Otherwise Noted. Note 1, Note 2.
Low Voltage Power Supply, V

Floating Low Voltage Boot Strap . . . . . . . . . . . . . . . . . . . . . . 18V

Power Supply to Phase, V

Low Voltage Signal Pins

Fault, I

TRIPSEL

, VDD, TRIPL, CL1, G2L . . .-0.5VDC to VDD +0.5
G1L, D1L, VDF, TOP, BOT

CL2, TRIPU, G1U, G2U, D1U to Phase. . . . -0.5

(Note 1) . . . . . . . . . . . . . . 18V

BIAS

BS

VDC

DC
DC

to VBS +0.5

Thermal Resistance θ

JA

Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W

Maximum Package Power Dissipation at TA = +85oC, P

O

Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW

Operating Ambient Temperature Range, TA . . . . . . .-25oC to +85oC

Storage Temperature Range, TS. . . . . . . . . . . . . . .-40oC to +150oC

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+265oC

High Voltage Pins

Phase, V

(VBS,V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V

PHASE

, TRIPU, CL2, G2U and D1U: 0V-18V Higher Than

OUT

DC

Phase)

Dynamic High Voltage Rating Phase,. . . . . . . . . . . . . 10,000V/µs

DV

PHASE/DT

NOTES:

1. Care must betaken inthe application of V
Prolonged high peakcurrents mayresult if+15V
If it is desirable to switch the 15V

2. Consult factory for additional package offerings.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

source or if a CDD is larger, additional series impedance may be required.

DC

Electrical Specifications (V

asnot toimpose high peak dissipation demands on arelatively smallmetallized noise dropping resistor (RND).

BIAS

BIAS

is applied abruptlyand/or ifthe localbypass capacitorCDDis large. Itis suggestedthat CDDbe ≤ 10MFD.

DC

= 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to
VSSExcept TRIPU, CL2, G1U, D1U, and VBSReferenced to PHASE. DF:VDFto VBS,
CF: VBS to PHASE

PARAMETER SYMBOL TEMP MIN TYP MAX UNITS

DC CHARACTERISTICS
Input Current (5V < V

TOP

, V

BOT

, V

TRIPSEL

< 15V) I

IN

+25oC - 20 30 µA

-40oC to +85oC - 30 33 µA

I

Quiescent Current (All Inputs Low) I

BIAS

BIAS

L

+25oC - 1.7 2.05 mA

-40oC to +85oC - 1.7 2.1 mA

I

Quiescent Current

BIAS

(V

≥ V

OUT

, and All Inputs Low)

BIAS

IBS Quiescent Current Bootstrap Supply I

I

BIAS

BS

H

+25oC - 1.7 2.05 mA

-40oC to +85oC - 1.7 2.1 mA
+25oC - 875 1000 µA

-40oC to +85oC - 900 1060 µA

TOP Threshold Level V

TOP

+25oC 789V

-40oC to +85oC 6.95 8 9.1 V

BOTTOM Threshold Level V

BOT

+25oC 789V

-40oC to +85oC 6.9 8 9.1 V

Current TRIPSELECT Threshold Level V

TRIPSEL

+25oC 789V

-40oC to +85oC 6.95 8 9.1 V

Trip Lower and Upper Comparator Threshold
Level - Normal (I

TRIPSEL

= VSS)

Trip Lower and Upper Comparator Threshold
Level - Boost (I
V

TRIP L/U

N

TRIPSEL

= VDD) % of Measured

Under Voltage Lockout Thresholds (VDD and VBS)V

V

TRIP L/U

V

TRIP L/U

LOCK

N

+25oC 90 105 125 mV

-40oC to +85oC 90 105 127 mV

B

+25oC 110 130 150 %

-40oC to +85oC 109 130 152 %

+25oC 9 10 11.5 V

-40oC to +85oC 9.7 10.5 11.8 V

Phase Out of Status Voltage Threshold (PHASE) V

OSVT

+25oC 579V

-40oC to +85oC 4.7 7 9.6 V

2

SP600

Electrical Specifications (V

= 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to

BIAS

VSSExcept TRIPU, CL2, G1U, D1U, and VBSReferenced to PHASE. DF:VDFto VBS,
CF: VBS to PHASE (Continued)

PARAMETER SYMBOL TEMP MIN TYP MAX UNITS

Faultbar Impedance at I

Upper/LowerSourceImpedances(I

Upper/Lower Sink Impedances (I

= 1mA RF +25oC 500 760 1000 Ω

FBAR

SOURCE

SINK

=10mA) R

= 10mA) R

Bootstrap Supply Current Limiting Impedance R

Noise Dropping Resistor Impedance R

High Voltage Leakage (500V VBS, V

OUT

, PHASE,
TRIPU, CL2, G1U, G2U, and D1U to VSS. All other
Pins at VSS)

Miller Clamp Diodes; D1U and D1L (ID = 10mA) V
Noise Clamping Zeners; CL2 and CL1 (IZ = 10mA) V

CL2/1-LOW

Noise Clamping Zeners; CL2 and CL1 (IZ = 50mA) V

V

Limiting Resistance R

OUT

NOTE: Maximum Steady State ÷ 15VDC Supply Current = I

SO L/U

SI L/U

BS

ND

I

LK

D1U/L

CL2/1-

HIGH

O

BIAS

-40oC to +85oC 450 760 1100 Ω
+25oC 121723Ω

-40oC to +85oC 7 17 29 Ω
+25oC 8 12 16 Ω

-40oC to +85oC 5 12 20 Ω
+25oC 2 3.5 5 Ω

-40oC to +85oC 1.4 3.5 5.6 Ω
+25oC 6 10 14 Ω

-40oC to +85oC 5.4 10 14.6 Ω
+25oC-13µA

+25oC 0.40 0.90 1.40 V
+25oC 6.35 6.61 6.85 V

-40oC to +85oC 6.15 6.61 7.15 V
+25oC 7.0 8.5 8.0 V

+25oC 2 3.5 5 Ω

-40oC to +85oC 1.4 3.5 5.6 Ω

÷I

BS

L

Switching Specifications (All Referenced to V

DF: VDF to VBS, CF: VBS to PHASE)

PARAMETER SYMBOL TEMP MIN TYP MAX UNITS

Refresh One Shot Timer t

Delay Time of Trip I/U Voltage (I

TRIPSEL

G2U/G2L Low (50% Overdrive)

Delay Time of Trip I Voltage (I

TRIPSEL

Faultbar Low

Delay Time of Phase Out of Status to Faultbar
Low (TOP High)

Minimum Logic Input Pulse Width: TOP and
BOTTOM

Minimum G1U/G1L On Time t

Minimum Pulsed Off Time, G2U/G2L t

Turn On Delay Time of G1U (BISTATE MODE) t

low) to

low) to

, Except: TRIPU, Cl2, G1U, G2U, and D1U Referenced to PHASE.

SS

REF

+25oC 200 350 500 µs

-40oC to +85oC 180 350 540 µs

t

OFF

TN

+25oC 234µs

-40oC to +85oC 1.85 3 4.35 µs

t

FN

+25oC 234µs

-40oC to +85oC 1.85 3 4.35 µs

t

OSVF

+25oC 500 700 900 ns

-40oC to +85oC 400 700 1050 ns

t

MINIW

+25oC 300 430 600 ns

-40oC to +85oC 275 430 660 ns

ON

+25oC 1.6 2.3 3.1 µs

-40oC to +85oC 1.5 2.4 3.4 µs

OFF

+25oC 1.3 2.0 3.4 µs

-40oC to +85oC 1.05 2.1 3.9 µs

ON

D

+25oC 2.5 3.2 4.5 µs

-40oC to +85oC 2.1 3.3 5.2 µs

3

SP600

Switching Specifications (All Referenced to V

DF: VDF to VBS, CF: VBS to PHASE) (Continued)

PARAMETER SYMBOL TEMP MIN TYP MAX UNITS

Turn On Delay Time of G1L (BISTATE MODE) t

Turn On Delay Time of G1U
(THREE-STATE MODE)

Turn On Delay Time of G1L
(THREE-STATE MODE)

Turn Off Delay Time of G2U and G2L t

Minimum Dead Time: G1U off to G1L on, or G1L
off to G1U on (BISTATE MODE)

Fault Reset Delay to Clear Faultbar t

Rise Time of Upper and Lower Driver
(Load = 2000pF)

Fall Time of Upper and Lower Driver
(Load = 2000pF)

, Except: TRIPU, Cl2, G1U, G2U, and D1U Referenced to PHASE.

SS

ON

D

+25oC 2.5 3.2 4.5 µs

-40oC to +85oC 2.1 3.3 5.2 µs

t

ON

D

+25oC 0.75 1.0 1.5 µs

-40oC to +85oC 0.60 1.1 1.75 µs

t

ON

D

+25oC 0.75 1.0 1.5 µs

-40oC to +85oC 0.60 1.1 1.75 µs

OFF

D

+25oC 0.75 1.0 1.45 µs

-40oC to +85oC 0.60 1.1 1.75 µs

t

D.T.

+25oC 1.5 2.5 3.5 µs

-40oC to +85oC 1.2 2.6 4 µs

R.T.

+25oC 3.4 4.5 6.6 µs

-40oC to +85oC 3.15 4.8 7.4 µs

t

R U/L

+25oC 25 50 100 ns

-40oC to +85oC 15 50 115 ns

t

F U/L

+25oC 25 50 100 ns

-40oC to +85oC 15 50 115 ns

Recommended Operating Conditions and Functional Pin Description (All Voltages Referenced to V

Otherwise Noted. See Figure 1)

PARAMETER CONDITION

FAULTBAR Open Drain Fault Indicator Output

I

TRIPSELECT

V

BIAS

V

DD

V

SS

TRIP I 100mV Signal to Shut Off LOWER Drive and Trigger a Fault Output

CL1 Lower Noise Clamp Zener

G2L and G1L Low Impedance Driver Designed to Drive Power MOS Transistors (LOWER)

V

DF

V

BS

V

OUT

PHASE Floating Reference Point for High Side Control Circuitry: VBS, TRIPU, CL2, G1U, G2U and D1U

TRIP

U

CL2 Upper Noise Clamp Zener

G2U and G1U Low Impedance Driver Designed to Drive Power MOS Transistors (UPPER)

TOP Digital Input to Command the UPPER On
BOT Digital Input to Command the LOWER On
D1U Miller Clamp UPPER to V
D1L Miller Clamp LOWER to V

Digital Input Command to Increase TRIPL and TRIPU Threshold by 30%

14.5V to 16.5V with 15V nominal, ≅ 1.5mA DC BIAS Current
CDD to V

SS

COMMON

Current Limiting Charging Resistor for Bootstrap Capacitor Power Supply
Bootstrap Supply, Normally a Diode Drop Below VDD Voltage with Respect to the Floating PHASE Reference
Load Connection Node

100mV Signal, Referenced to PHASE, to Shut Off UPPER Drive

BS

DD

, Unless

SS

4

Timing Diagram

SP600

ON

1
0

1
0

1
0

1

B

0
1

0
1

T

0
1

T

0
1

B

0
1

0
1

0

V

DC

COM

REFRESH

ONE SHOT

VALID BOT

I

OFF

I

OFF

UPPER

LOWER

V

TOP

BOT

I

ON

I

ON

OUT

THREE-ST ATE MODE SLOWERTHAN REFRESH ONE SHOTTIMER

NOTE: BOT switching not relevant.

ON

1
0

1
0
1
0

1

B

0
1

0
1

T

0
1

T

0
1

B

0
1

0
1

0

V

DC

COM

REFRESH

ONE SHOT

VALID BOT

I

I

OFF

UPPER

LOWER

V

TOP

BOT

I

ON

OFF

I

ON

OUT

BISTATE MODE SLOWER THAN REFRESH ONE SHOT TIMER

Typical Circuit Configuration

TRUTH TABLE

Applicable to Typical Circuit Configuration (Figure 1)

INPUTS OUTPUTS

TOP BOT TRIP

L

000XX100 1

11001110 1

11011100 0

110X0100 0

XX1XX100 0

010XX101 1

100XX100 1

XXXXX000 0

NOTE: 0 = False, 1 = True, X = Don’t Care

TRIP

U

PHASE V

BIAS

UPPER LOWER FAULT BAR

5

SP600

SYSTEM CONTROL

15V

25VDC≤ V

RCUR

DU

R

PU

19

18 17

G1U G2UD1U TRIPUPHASE

21

BOT

22

TOP

1

FAULT

2

I

TRIPSELECT

V

I

BIAS

15

SP600

HVIC

BIASVDD

34 5

C

DD

14

OUT

V

BS

V

DF

D1L

G1L

G2L

13

C

F

12

D

F

11

10

9

8

6

L

I

BS

R

CL

R

DL

R

PL

V

V

TRIP

SS

COM

LINK

≤ 500V

DC

V

LOAD

OUT

FIGURE 1. TYPICAL CIRCUIT CONFIGURATION

LEGEND

Application Specific R

Application Specific R

Application Specific R

Application Specific R

Application Specific R

Application Specific R

3µF at ≥ 15DC C

0.22µF Ceramic X7R at ≥ 15V

Harris P/N A114M or Equiv PRV ≥ V

DC

LINK

CU

DU

PU

CL

DL

PL

DD

C

D

Upper Gate Charging Resistor

Upper Gate Discharge Resistor

Upper Current Pilot Resistor

Lower Gate Charging Resistor

Lower Gate Discharging Resistor

Lower Current Pilot Resistor

Local LV Filter Capacitor

Flying Capacitor for Bootstrap Supply

F

Flying Diode for Bootstrap Supply

F

NOTE: Refer to ‘Additional Product Offerings’ for information concerning power output devices.

6

Functional Description

SP600

The SP600 provides a flexible, digitally controlled power
function which is intended to be used as PWM drivers of
N-Channel MOSFETs and/or IGBTs for up to 240VAC line
rectified totem-pole applications. The CMOS driveable
inputs are filtered and captured by the control logic to deter­mine the output state. The logic includes fixed timing to pro­hibit simultaneous conduction of the external power switches
and, thru the V

sense detector, verifies the output volt-

OUT

age state is in agreement with the controlled inputs. The
>11V

floating power supply required to drivethe upper rail

DC

external power device is created and managed by the HVIC
through C
supply each time V

and DF. This capacitor is refreshed from the V

F

goes low. If the upper channel is

OUT

DD

commanded on for a long period of time, the bootstrap
capacitor CF is automatically refreshed by bringing V

OUT

low. This is accomplished by turning off the upper rail MOS­FET/IGBT, momentarily turning on the lower rail output
device, followed by returning control back to the upper
switch. Otherwise, C

would gradually deplete its charge

F

allowing the upper switch to come out of saturation. The
upper and lower gate drivers allow for controlled charge and
discharge rates as well as facilitate the use of nearly lossless
current sensing power MOS devices. The over current trip
level can be boosted 30% on a pulse by pulse basis by logic
level ‘1’ applied to I

TRIPSELECT

.AFAULT output signal is

generated when any of the following occurs:

V bias is low
Over current is detected
V phase doesn’t agree with the input signal

Reset of

FAULT is provided by externally removing power or
by holding both TOP and BOT inputs low for the required
reset time (trt

MAX

).

Each application can be individually optimized by the selec­tion of external components tailored to ensure proper overall
system operation including:

Determining the ratings and sizing of MOSFETs and IGBTs,
mixed or matched, as well as flyback diodes (FBD).

The selection of separate gate charge (R
(R

) impedance chosen per the load capacitance, frequency

D

of operation, and D
of the associated FBDs. R

dependent recovery characteristics

I/DT

should also be sized to prevent

D

) and discharge

C

simultaneous bridge conduction by ensuring gate discharge
in the allotted turn off pulse width (t

OFF MIN

The selection of over current detection resistors (R

).

), com-

P

patible with current sense MOSFETs/IGBTs or shunt(s) may
be used.

For the floating bootstrap supply D
mined. D

must support the worse case system bus voltage

F

and handle the charging currents of C
should take into consideration T
operating frequency. Proper selection of C
between the minimum t

time of the lower rail to charge up

ON

and CFmust be deter-

F

. Proper selection

F

and TFRper the desired

RR

is a trade off

F

the capacitor, the amount of charge transfer required by the
load, and cost. Due to automatic refresh the capacitor is
replenished every 350µs TYP (or even sooner if input com­mands the TOP to switch at a faster repetition rate).

The local filter capacitor (C
large enough to transfer the charge to C
significant droop in V

DD

least 10 times larger than C
V

and VSSpins to minimize series resistance and

DD

) should be sized sufficiently

DD

without causing a

F

. As a rule of thumb it should be at

and be located adjacent to the

F

inductance.

Refer to Application Note AN8829 for more details about module operation and selection of external components.

7