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CCD Delay Line Series
MN3880S
NTSC CCD Video Signal Delay Element
Overview
The MN3880S is a CCD signal delay element for video
signal processing applications.
It contains such components as a shift register clock
driver, charge I/O blocks, two CCD delay elements, a
clamp bias circuit, resampling output amplifiers, and
booster circuits.
The MN3880S samples the input using the supplied
clock signal with a frequency of 7.15909 MHz, twice the
NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two
lines.
Features
Single 4.9 V power supply
Single chip combining luminance signal delay
element and delay element for chrominance signal
after passing through a low pass filter
Applications
VCRs
Pin Assignment
VBIASC
VOC
N.C.
V
DD
–V
BB
N.C.
VOY
VBIASY
1
2
3
4
5
6
7
8
SOP016-P-0225
(TOP VIEW)
VINC
16
N.C.
15
N.C.
14
X1
13
V
12
11
10
9
SS
N.C.
N.C.
VINY
1
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MN3880S CCD Delay Line Series
Block Diagram
VINC
XI
SS
V
12
Bias circuit
16
Charge
input block
øS driver ø1 driver ø2 driver øR driver
Timing adjustment
13
Waveform amplitude
adjustment block
Timing adjustment
CCD 454 stages
DD
V
4
Charge
detection block
VBIASC
1
Resampling
output amplifier
øSH driver
øSH driver
2
VOC
øSH driver
øSH driver
Resampling
output amplifier
8
VBIASY
7
VOY
VINY
øS driver ø1 driver ø2 driver øR driver
Clamp circuit
9
Charge
input block
5
BB
–V
CCD 454 stages
Charge
detection block
2
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CCD Delay Line Series MN3880S
Pin Descriptions
Pin No. Symbol Pin Name Remarks
1 VBIASC Output gate connection (C)
2 VOC Signal output (C)
3 N.C. No connection
4VDDPower supply
5–VBBSubstrate connection Negative voltage pin
6 N.C. No connection
7 VOY Signal output (Y)
8 VBIASY Output gate connection (Y)
9 VINY Signal output (Y)
10 N.C. No connection
11 N.C. No connection
12 V
13 XI Clock input
14 N.C. No connection
15 N.C. No connection
16 VINC Signal output (C)
SS
GND
3
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MN3880S CCD Delay Line Series
Application Circuit Example
10µF
–
+
(0.01µF)
0.1µF
Bias circuit
SS
V
12
DD
V
4
VBIASC
1
VINC
(0.01µF)
1000pF
XI
16
Charge input
block
CCD 454 stages
Charge
detection block
øS driver ø1 driver ø2 driver øR driver øSH driver
Timing adjustment
13
Waveform amplitude
adjustment block
Timing adjustment
øS driver ø1 driver ø2 driver øR driver øSH driver
Resampling
output amplifier
øSH driver
øSH driver
2
VOC
Clamp circuit
–
0.47µF
VINY
+
Charge input
block
5
BB
CCD 454 stages
Charge
detection block
Resampling
output amplifier
8
9
–V
(0.01µF)
VBIASY
(0.01µF)
Note: If the external capacitor attached to pin 5 is an electrolytic capacitor, attach the negative pole to pin 5.
4
7
VOY
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CCD Delay Line Series MN3880S
Package Dimensions (Unit:mm)
SOP016-P-0225
10.10
±0.20
16
18
9
1.10
±0.20
±0.20
±0.20
0.05
-
6.50
+0.10
4.30
0.15
0 to 10°
0.40min.
0.20
+0.50
-
±0.20
1.50
1.60
(0.6)
1.27
SEATING PLANE
0.40
±0.10
±0.10
0.10
5
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