The MN35503 is a CMOS digital-to-analog converter
designed especially for PCM digital audio equipment. It
features a built-in digital filter with 16/20-bit input.
It uses pulse edge modulation (PEM) and JVC advanced
noise shaping (VANS) to yield the high resolution and
low distortion ratio equivalent to those of 20-bit systems
covering the range between 0 and 20 kHz.
The chip incorporating an 8-fold oversampling digital
filter that eliminates a low-pass filter after the D/A
converter and greatly reduces the power consumption of
the overall D/A conversion system.
The chip makes a major contribution to reducing the
cost and size of CD players and other digital audio
equipment.
Features
Built-in 8-fold oversampling digital filter using I2S bus
•Bandwidth ripple: within ±0.05 dB for 0 to 0.454 f
•Cutoff band attenuation (0.546 to 7.454) f
(n–0.03125) f
to (n+0.03125) f
s
n=1 to 7 (integer)
(The above characteristics include those for an
external primary low-pass filter with f
Built-in digital de-emphasis
=32.0 kHz 0 to14.5 kHz max. deviation
f
s
+0.072dB/ – 0.047 dB
fs=44.1 kHz 0 to 20 kHz max. deviation
+0.077dB/ – 0.028 dB
f
=48.0 kHz 0 to 21.8 kHz max. deviation
s
+0.052dB/ – 0.053 dB
(The above characteristics include those for an
external primary low-pass filter with f
The digital filter is designed to deliver the above
bandwidth characteristics when used with an external
primary low-pass filter with f
=1.95 fs.
c
Built-in digital attenuation
Up/down over 32 steps
Support for double-speed operation (192 fs clock)
4PEM output configuration (2PEM output per channel)
Support for low-voltage (3.0 volt) operation
: 37dB
s
: min. 60dB
s
=1.95 fs.)
s
=1.95 fs.)
c
Pin Assignment
, 256f
s
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(TOP VIEW)
SOP028-P-0375
, 384f
, 512fs, 576f
s
s
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MA
DIN
LRCK
BCK
MB
DV
DD2
CKO
DV
SS2
M1
OUT1C
N.C.
AV
DD1
OUT1D
AV
SS1
s
Choice of system clocks:
192f
Choice of input data formats: right-packed or I2S bus
(16 or 20 bits, alternating channel input, MSB first)
Built-in phase comparator
Applications
CD players and other digital audio equipment
PDO
MD
MC
M3
DV
DD1
XIN
XOUT
DV
SS1
M2
OUT2C
N.C.
AV
DD2
OUT2D
AV
SS2
s
Page 2
MN35503For Audio Equipment
Block Diagram
XIN
PDO
232822
OSC
Block
XOUT
7
CKO
OUT2C
19
OUT2D
16
2
DIN
I/F Block
3
LRCK
DF Block
• 8fs
Over sampling
Digital Filter
• De-emphasis
Filter
• Attenuater
4
9
M1
BCK
1st.
Order
Noise
shaper
Block
Mode Control Block
20
25
M3
M2
PEM
Block
VANS
Block
D/A Block
PEM
Block
1
5
26
MA
MB
MC
27
MD
10
OUT1C
13
OUT1D
Page 3
For Audio Equipment
MN35503
Pin Descriptions
Pin No.SymbolFunction Description
1MAOperating mode selection pin 4 (See Table 1.)
2DINSerial data input pin (MSB first)
3LRCKLR synchronization signal input pin (fs rate)
4BCKData shift bit clock input pin
5MBOperating mode selection pin 5 (See Table 1.)
6DV
DD2
Power supply pin 2 for digital circuits
7CKOClock output pin
8DV
SS2
Ground pin 2 for digital circuits
9M1Operating mode selection pin 1, with pull-up resistor (See Table 1.)
10OUT1CPEM output pin 1C (Left channel with reversed phase)
11N.C.No connection (Leave this pin open.)
12AV
Note*1: This pin provides tristate output indicating the result of comparing the phases of the internal fs-rate-signal and the
LRCK input signal. It is at "H" level when the LRCK signal leads and is at "L" level when the signal lags. At all other
times, it is in the high-impedance state.
1
Page 4
MN35503For Audio Equipment
Operating Mode Descriptions
Table 1-1. MN35503 Operating Modes
Mode Selection PinsPin States and Operating Modes
M1 Includes pull-up resistorL
M2 Includes pull-up resistorLH
M3LH L H
MALHLHMDATLH
MBLHLHLHLHMCLKLHLH
MCRSBUPMLATRSBUP
MDRSBDNLHRSBDN
MODE000102031011121
Input data form Right-packed
Input word length (bits)16
LRCK level for left channel data H
XIN clock frequency (f
CKO output frequency (f
1
*
)384192576 384/576 256/384256
s
)384192576
s
2
*
DE-EMP. (fs=[kHz])– 44.1 32 48– 44.1 – 32 See Table 3– 44.1 32 48
Output level 0.598 × AV
Table 4 shows how the inputs from the two pins MC (RSBUP) and MD (RSBDN) control digital attenuation
except the serial modes.
Table 4. Attenuation Modes
Pin NamePin States and Operating Modes
MC (RSBUP)L↑↓L↑H
MD (RSBDN)LL↑H↑
ModeResetMuteNormalAttenuation control
Volume Mute (–∞)0dBUPDOWN
Note: The upward arrow indicates the rising edge change of the input signal; the paired arrows, the rising and falling edge
changes.
There are a total of 32 attenuation levels.
According to the attenuation control shown in Table-4, volume goes up or down in one step every input-signal
rising-edge. Still, in the 0 dB state, up-pulse does not change the volume. Similary, in the muting state (–∞), downpulse does not change the volume.
The change of the input signals is detected by inner clock of 16 f
changes in the RSBUP and RSBDN signals. Note, however, that changes in attenuation level require a period corresponding to 2 f
to complete.
s
Do not simultaneously change the RSBUP and RSBDN signals unless setting up for a reset.
period, so always use a frequency of 8 fs or less for