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MacBook Pro A2141
boardview
135 pgs11.96 Mb0

Apple MacBook Pro A2141 boardview

Vinafix.com
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7
6 5 4 3
SCHEM,MLB,X970
2 1
ECNREV DESCRIPTION OF REVISION
CK APPD
DATE
2019-06-192
D
CSAPAGE
1 2 3 4
6 7 8 8 9 10
12 13
2
3
55
6
7
9
10
12
13
CONTENTS
MLB BOM Configuration 1 BOM Configuration 2 PD Parts CPU DMI/PEG/FDI/RSVD CPU Clock/Misc/JTAG/CFG CPU DDR4 Interfaces CPU Power CPU Ground CPU Decoupling 1 CPU Decoupling 211 PCH RTC/CLK/ESPI/PM PCH DMI/JTAG/SPI/HDA
ANDY
ANDY
01/17/2019 08/22/2018 08/22/2018 10/14/20184 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/201911 01/17/2019 01/17/2019
CSAPAGEDATESYNC
511 52 53
55 56
59 60 61 01/17/2019 62 63
52 53 54 5554 56 57 01/17/2019
59 60 62 01/17/2019 63 64 65
CONTENTS
ZIFENG
I2C Connections 2 02/14/2019 Power Sensors High Side Power Sensors Load Side Power Sensors Extended 1 Power Sensors Extended 2 Thermal Sensors Power Sensor Extended 3 Fans/SMC/AMUX Support 01/17/2019 Audio Placeholder Audio Jack Codec Audio Left Amplifiers Audio Right Amplifiers
ZIFENG
RAYMOND RAYMOND RAYMOND RAYMOND
ARMIN
ADRIEN ADRIEN ADRIEN
DATESYNC
02/14/2019I2C Connections 1
01/17/2019 02/12/2019 02/12/2019
02/12/20195857 01/17/201958
01/17/2019 01/17/2019
101 102 103
105 106 107 108
110 111 112 113
CSAPAGE
104 105 106 107 108 GPU Memory Rails 109 110 111 112 113
115 116
CONTENTS
GPU Navi14 GDDR6 CHs A, B GPU Navi14 GDDR6 CHs C, D GPU Core Rails Controller GPU Core GFX/SOC Phases104
GPU 1.8V / 0.75V USB-C HIGH SPEED 1 USB-C HIGH SPEED 2 USB-C T Support109 USB-C PORT CONTROLLER TA USB-C PORT CONTROLLER TB114 USB-C T CONNECTOR USBC T Connector Support
SEAN YANIR ANDY YANIR YANIR YANIR YANIR ANDY
DATESYNC
D
08/22/2018 08/22/2018 08/22/2018 08/22/2018 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 03/26/2019
C
14 01/17/2019 15 16 16 17 18 19 19
21 22 DDR4 SDRAM Channel A 1
24 25 26 27
14
15
17
18
20
23 01/17/2019
2423
25
26
27
28
PCH PCI-E/USB PCH GPIO/MISC/NCTF PCH Power PCH Decoupling CPU/PCH Merged XDP Chipset Support 1 Chipset Support 220 DDR4 VREF Margining
DDR4 SDRAM Channel A 2 DDR4 SDRAM Channel B 1 DDR4 SDRAM Channel B 2 DDR4 Termination USB-C HIGH SPEED 1
ARMIN ANDY
YANIR
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 02/19/2019 01/17/201922
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019
64 66
73 74 75
77
68 Trackpad Support
69
70
71
72
73
76
77
78
79
Audio Flex Connectors Keyboard Support
VR 3.3V G3H & Battery Conn PBUS Supply & Battery Charger IMVP IC IMVP VCC Block IMVP SA Block IMVP GT Block Power 5V 3.3V Supply VR 2.5V & 1.2V/VTT PMIC BUCKS AND SWs PMIC LDOs PMIC GPIOs & Control80
ADRIEN 01/17/2019 SHAN
RAYMOND
ARMIN
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/201976 01/17/2019
114 115 116 117 118 119 120 121 DFU TEST POINTS
123 124
126 127 06/05/2019
117 01/17/2019 118
120 121
123 124 125122 126 127 128125 10/14/2018 129 130
USB-C T 5V VR GPU 3.3V / Discharge GPU Sequencing & Straps119 Power Alias 1 Power Alias 2 Signal Alias122 High speed No Testpoints
FCT TESTPOINTS 2 ICT, MAC-1, & EE Testpoints Desense Caps 1 Desense Caps 2 Desense Caps 3 Desense Caps 4
TUZMAN J780 ZIFENG
ANDY ANDY ANDY ANDY ZIFENG ZIFENG
ZIFENG ZIFENG
09/05/2018 08/22/2018 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 03/26/2019 08/22/2018
08/22/2018
C
B
28 29 30
32 33 34 35 36 37 38 39 40 41 SoC PCIe
29 30 31 3231 33 34 35 36 37 38 39 40 41 42
USB-C HIGH SPEED 2 USB-C X Support USB-C PORT CONTROLLER XA USB-C PORT CONTROLLER XB USB-C X Connector USBC X Connector Support TBT 5V REGULATOR WIFI/BT: Support WIFI/BT: MODULE 1 AP & BT Conn SoC GPIO/SEP/USB/DDR/Test SoC AOP/AON/SMC SoC ISP/I2C/UART/SPI/I2S
ANDY
YANIR YANIR YANIR YANIR YANIR
METE
ANDY ANDY ANDY ANDY
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 02/19/2019 01/17/2019 01/17/2019
78 79 01/17/2019
81 84 82 83 84 85
87 90 88
90 91
81
82
85
86
87
88
91
92
93
94
VR VCCIO Power FETs SOC/PMIC Aliases LCD Backlight Driver eDP Display Connector SSD1 S4E 0 SSD1 S4E 1 SSD1 S4E 2 SSD1 S4E 3 SSD1 PMIC & VR SSD0 S4E 0 SSD0 S4E 1 SSD0 S4E 2 SSD0 S4E 3
ARMIN ARMIN
01/17/2019
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/201989 01/17/2019 01/17/2019
128 129 130 131 132 133 134 135 200
131 140 141 143
147 148
Memory Bite/Byte Swizzle Debug BOM 639 XTA BOM 639 XLA BOM 639 MISC144 BOM Alt Table
Dev Support 10/14/2018
LAST_MODIFICATION=Tue Jun 18 17:59:51 2019
ANDY
SEAN
01/17/2019 10/14/2018 10/14/2018 10/14/2018 10/14/2018 01/17/2019 01/17/2019More BOM Alt Table
B
A
42 43 44 45 46 47 48 49 50
43 44 45 46 47 48 49 50 51
SoC Power 1 SoC Power 2 SoC Power 3 SoC Ground SoC Shared Support SoC Project Support MESA SECURE ELEMENT DFR Support
LAST_MODIFICATION=Tue Jun 18 17:59:51 2019
ARMIN
ANDY ARMIN ANDY
ARMIN
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 02/19/2019 01/17/2019 02/19/2019 01/17/2019
92 93 94
97 98 99 100
95
96
97
98
99
100
101
102
103
SSD0 PMIC & VR GPU VRAM CHs A, B GPU VRAM CHs C, D EDP Mux GPU PCC / Sensors96 GPU Navi14 PCIe / DP A / Misc GPU Navi14 DP / GPIO / Debug GPU Navi14 Power GPU Navi14 VSS & Decoupling
LAST_MODIFICATION=Tue Jun 18 17:59:51 2019
J187_ALAN J187_ALAN
J780 SEAN
SEAN
01/17/2019 09/18/2018 09/18/2018 08/22/201895 08/22/2018 08/22/2018 08/22/2018 08/22/2018 08/22/2018
CANDIDATE
DRAWING TITLE
SCHEM,MLB-NAVI,X970
SYNC_DATE=08/22/2018SYNC_MASTER=ZIFENG
A
DRAWING
TITLE=MLB ABBREV=ABBREV
LAST_MODIFIED=Tue Jun 18 17:59:51 2019
Schematic / PCB #'s
8
SIZEDRAWING NUMBER
Apple Inc.
051-04492
REVISION
D
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL1 SCH SCHSCHEM,MLB-NAVI,X970051-04492 CRITICAL1 PCBPCBPCBF,MLB-NAVI,X970820-01700
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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X970 BOM Groups
BOM GROUP BOM OPTIONS
SSD_LANDS:6 ALTERNATE,S4E_L6 SSD_LANDS:7 ALTERNATE,S4E_L6,S4E_L7 SSD_LANDS:8 ALTERNATE,S4E_L6,S4E_L7,S4E_L8
SCH,PCB,COMMON,ALTERNATE,COMMON1,COMMON2,COMMON3,PROGPARTSX970_COMMON CPUPEG:X8X4X4,EDP:YES,BOARD_ID:0X3A,SE:DEV_2019,EN_VP0R_LPS:YESCOMMON1 PCC:YES,RF_TUNING,BOARD_REV:010,BAT_I2C:3V3COMMON2 SKIP_5V3V3:AUDIBLE,XDP:YES,VCCSPI:3V3,SVID_PU:CORECOMMON3 LOADISNS,LOADRC:YES,SENSOR:DEVSNS ALTERNATE,SNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,WIFI_DBG,BOOTCFG0,ESPI_DBGDEVEL:ENG ALTERNATE,LOADRC:NODEVEL:PVT
BOM Variants
BOM NUMBER BOM NAME BOM OPTIONS
COMMON PARTS,MLB-NAVI,X970 X970_COMMON685-00271
SSD_LANDS:6685-00308 ITLC 6L Parts,MLB-NAVI,X970 SSD_LANDS:7685-00309 ITLC 7L Parts,MLB-NAVI,X970
685-00310 SSD_LANDS:8ITLC 8L Parts,MLB-NAVI,X970
DEVEL:ENG985-00889 DEV PARTS,MLB-NAVI,X970 685-00296 VRAM:MC-4GBVRAM PARTS,MICRON,4GB,MLB-NAVI,X970 685-00297 VRAM:SS-4GBVRAM PARTS,SAMSUNG,4GB,MLB-NAVI,X970 685-00298 VRAM:HY-8GBVRAM PARTS,HYNIX,8GB,MLB-NAVI,X970
VRAM:MC-8GBVRAM PARTS,MICRON,8GB,MLB-NAVI,X970685-00299 VRAM:SS-8GB685-00300 VRAM PARTS,SAMSUNG,8GB,MLB-NAVI,X970
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
685-00271 CRITICAL BOM_BASEBASE1 COMMON PARTS,MLB-NAVI,X970
CRITICAL1685-00309 7L SSD_BOM:7LITLC 7L Parts,MLB-NAVI,X970
685-00310 CRITICAL1 SSD_BOM:8L8LITLC 8L Parts,MLB-NAVI,X970
985-00889 1 DEVEL BOM_DEVCRITICALDEV PARTS,MLB-NAVI,X970
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
SSD_BOM:6LCRITICAL6L685-00308 1 ITLC 6L Parts,MLB-NAVI,X970
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Memory Options
BOM GROUP BOM OPTIONS
MEM:HY-16GB DRAM:HY-16GB,RAMCFG0:L MEM:MC-16GB DRAM:MC-16GB,RAMCFG1:L MEM:HY-32GB DRAM:HY-32GB,RAMCFG3:L,RAMCFG0:L MEM:MC-32GB DRAM:MC-32GB,RAMCFG3:L,RAMCFG1:L MEM:MC-64GB DRAM:MC-64GB,RAMCFG2:L,RAMCFG1:L
VRAM Options
BOM GROUP BOM OPTIONS
VRAM_SIZE:4GB,VRAM_IC:MC-4GBVRAM:MC-4GB VRAM_SIZE:4GB,VRAM_IC:SS-4GBVRAM:SS-4GB VRAM_SIZE:8GB,VRAM_IC:HY-8GBVRAM:HY-8GB VRAM_SIZE:8GB,VRAM_IC:MC-8GBVRAM:MC-8GB
VRAM:SS-8GB VRAM_SIZE:8GB,VRAM_IC:SS-8GB
SSD Options
BOM GROUP BOM OPTIONS
SSD:TS-256 SSD_NAND:TS-256,SOC:1GB,JTAG:L5 SSD:WD-256 SSD_NAND:WD-256,SOC:1GB,JTAG:L5
SSD_NAND:TS-512,SOC:1GB,JTAG:L5SSD:TS-512 SSD:SS-512 SSD_NAND:SS-512,SOC:1GB,JTAG:L5 SSD:WD-512 SSD_NAND:WD-512,SOC:1GB,JTAG:L5 SSD:TS-1TB SSD_NAND:TS-1TB,SOC:2GB,JTAG:L6,SSD_BOM:6L
SSD_NAND:WD-1TB,SOC:2GB,JTAG:L6,SSD_BOM:6LSSD:WD-1TB SSD:TS-2TB SSD_NAND:TS-2TB,SOC:2GB,JTAG:L7,SSD_BOM:7L SSD:WD-2TB SSD_NAND:WD-2TB,SOC:2GB,JTAG:L7,SSD_BOM:7L SSD:HY-4TB SSD_NAND:HY-4TB,SOC:2GB,SSD_BOM:8L SSD:WD-4TB SSD_NAND:WD-4TB,SOC:2GB,SSD_BOM:8L SSD:WD-8TB SSD_NAND:WD-8TB,SOC:2GB,SSD_BOM:8L
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
D
C
B
B
A
Board ID[7:0] = 8b'00111010 = 8h'3A
BOM GROUP BOM OPTIONS
BOARDID5,BOARDID4,BOARDID3,BOARDID1BOARD_ID:0X3A
8
SYNC_MASTER= SYNC_DATE=08/22/2018
PAGE TITLE
A
BOM Configuration 1
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
67
35 4
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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CPU
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
1 U0500 CRITICAL CPU:6C-2.6G337S00722
CPU,CFLH,SRF6U,PRQ,2.6,1.15,6C,BGA1440
CPU,CFLH,SRFD1,PRQ,2.3,1.2,8C,BGA1440
1337S00731 U0500
337S00724 CRITICAL CPU:8C-2.4G1
998-12472 1 CPU:INTERPOSER
DRAM
333S00200
333S00163
998-18918 8
CPU,CFLH,SRFD0,PRQ,2.4,1.25,8C,BGA1440
INTERPOSER,CFL-H,BGA1440
Note: Two rows per part for legibility
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,DDR4-2666,8GBIT,19NM,H,BGA78
8
IC,DDR4-2666,8GBIT,19NM,H,BGA78
8
IC,DDR4-2666,8GBIT,Z11B,18NM,M,BGA78
IC,DDR4-2666,8GBIT,Z11B,18NM,M,BGA78
8 CRITICAL
IC,DDR4-2666,16GBIT,19NM,H,BGA78
8333S00201
IC,DDR4-2666,16GBIT,19NM,H,BGA78
8333S00201
IC,DDR4-3200,16GBIT,16NM,ES,M,BGA78
IC,DDR4-3200,16GBIT,16NM,ES,M,BGA78
IC,DDR4-3200,32GBIT,16NM,ES,M,BGA78
IC,DDR4-3200,32GBIT,16NM,ES,M,BGA78
U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430
U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630
U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430
U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630
U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430
U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630
U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430
U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630
U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430
U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630
U0500
U0500 CRITICAL
CRITICAL333S00200 8 DRAM:HY-16GB
CRITICAL333S00163
CRITICAL DRAM:HY-32GB
CRITICAL998-18918 8
BOM OPTIONCRITICAL
CPU:8C-2.3GCRITICAL
BOM OPTIONCRITICAL
DRAM:HY-16GBCRITICAL
DRAM:MC-16GB
DRAM:MC-16GB
DRAM:HY-32GBCRITICAL
DRAM:MC-32GBCRITICAL998-18917 8
DRAM:MC-32GBCRITICAL8998-18917
DRAM:MC-64GB
DRAM:MC-64GBCRITICAL
GPU
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
CRITICAL GPU:ULA337S00719 1 UA000GPU,AMD,NAVI14,ULA,A0,ES,BGA1125
CRITICAL337S00720 1 UA000 GPU:PRAGPU,AMD,NAVI14,PROA,A0,ES,BGA1125
UA0001 CRITICAL998-19125 GPU,AMD,NAVI14,ULA,A0,ES,FF,PSL,BGA1125 GPU:UFS
1 CRITICALUA000998-19126 GPU,AMD,NAVI14,ULA,A0,ES,SS,PSL,BGA1125 GPU:USS
1 UA000998-19109 GPU,AMD,NAVI14,ULA,A0,ES,FF,MTAG,BGA1125 GPU:UFUCRITICAL
CRITICAL1 UA000998-19110 GPU,AMD,NAVI14,ULA,A0,ES,SS,MTAG,BGA1125 GPU:USU
CRITICAL GPU:ADPTR_VDDCR1 UA000998-19111 NAVI14 ADPTR,VDDGFX,VDDSOC,D406
BOM OPTIONCRITICAL
GPU:TDPCRITICALUA0001 GPU,AMD,NAVI14,ULA,A0,ES,TDP,BGA1125998-19127
GPU:ADPTR_VMEMCRITICALUA0001998-19112 NAVI14 ADPTR,VDDCI,MVDD,D407
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
Programmable Parts
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
UB090 CRITICAL1341S01436 TBT-T,R1 (VXXXX) PROTO-3,X970
341S01434 ROM,BT SFLASH (V37) PROTO-3,X970 CRITICAL1 U3750
U3710 CRITICALWIFI ROM (V01) WW1,X6651341S00725
341S01403 CRITICAL1
ROM,VBIOS,NAVI-14,PROA (VXXX) P-0-A,X970
ROM,VBIOS,NAVI-14,ULA (VXXX) P-0-A,X970
UA130 GPU:PRA
UA1301341S01404 GPU:ULA
H9M & Alternates
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
339S00373 1 SOC:2GBCRITICALU3900
339S00371 U3900
POP,GIBRALTAR+2GB 21NM,H,B0,SCK,CSP1406
POP,GIBRALTAR+1GB 21NM,H,B0,ATK,CSP1406
PART NUMBER
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
339S00372 339S00373 H9M 2GBANY ALL
339S00377 339S00373 H9M 2GBALLANY
339S00373 H9M 2GBANY ALL339S00378
339S00371339S00376 ANY ALL H9M 1GB
339S00371 ANY ALL339S00370 H9M 1GB
339S00375 ANY ALL H9M 1GB339S00371
SSD NAND
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
NAND,3DV4,64GBT,S4E,256G,T,SUB Y,SLGA110
NAND,3DV4,64GBT,S4E,256G,SD,SUBY,SLGA110
NAND,3DV4,128GBT,S4E,256G,T,SUBY,SLGA110
NAND,3DV5,128GBT,S4E,256G,SS,SLGA110
NAND,3DV4,128GBT,S4E,256G,SD,SBY,SLGA110
5 CRITICAL SSD_NAND:WD-512998-16970 U8600,U9100,U9200,U9300,U9400
NAND,3DV4,192GBT,XXX,S4E,256G,T,SLGA110
6 SSD_NAND:TS-1TB335S00395
NAND,3DV4,192GBT,XXX,S4E,256G,H,SLGA110 U8600,U8700,U9100,U9200,U9300,U9400
6 CRITICAL SSD_NAND:WD-1TB335S00407
U8600,U9100,U9200,U9300,U9400 SSD_NAND:TS-512998-16397
U8600,U8700,U9100,U9200,U9300,U9400
BOM OPTIONCRITICAL
CRITICALU28901 TBT-X,R0 (VXXXX) PROTO-3,X970341S01435
CRITICAL
BOM OPTIONCRITICAL
CRITICAL1 SOC:1GB
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BOM OPTIONCRITICAL
SSD_NAND:TS-256CRITICALU8600,U9100,U9200,U9300,U94005998-16395
CRITICAL5998-16969 U8600,U9100,U9200,U9300,U9400
SSD_NAND:WD-256
CRITICAL5
CRITICAL5 U8600,U9100,U9200,U9300,U9400
SSD_NAND:SS-512335S00424
CRITICAL
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
SSD NAND Substrate Alts
Sub1
TABLE_5_HEAD
TABLE_5_ITEM
998-16394 998-16395 ALLANY SSD NAND: TB_256
TABLE_5_ITEM
998-16944 998-16969 ANY ALL SSD NAND: WD_256
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
Sub2
PART NUMBER
998-16970 ALLANY998-16945 SSD NAND: WD_512
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
ALL998-16396 998-16397 ANY SSD NAND: TB_512
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
D
C
B
VRAM
333S00209
PCH CNL-H
IC,GDDR6,8GBIT,14GBPS,1.35V,18NM,M,BG180
4
IC,GDDR6,8GBIT,14GBPS,1.35V,18NM,S,BG180
IC,GDDR6,16GBIT,14GBPS,1.35V,19NM,H,B180
IC,GDDR6,16GBIT,14GBPS,1.35V,16NM,M,B180
IC,GDDR6,16GBIT,14GBPS,1.35V,18NM,S,B180
TABLE_5_ITEM
NAND,3DV4,192GBT,XXX,S4E,256G,T,SLGA110
1335S00395 CRITICAL
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
BOM OPTIONCRITICAL
TABLE_5_ITEM
U9600,U9610,U9700,U9710 CRITICAL VRAM_IC:MC-4GB4
TABLE_5_ITEM
CRITICAL VRAM_IC:SS-4GBU9600,U9610,U9700,U9710333S00210
TABLE_5_ITEM
CRITICALU9600,U9610,U9700,U9710 VRAM_IC:HY-8GB333S00211 4
TABLE_5_ITEM
CRITICAL VRAM_IC:MC-8GBU9600,U9610,U9700,U9710333S00212 4
TABLE_5_ITEM
335S00408 6 SSD_NAND:WD-2TB
335S00380 8 CRITICAL
335S00391
VRAM_IC:SS-8GBCRITICALU9600,U9610,U9700,U9710333S00213 4
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
BOM OPTIONCRITICAL
TABLE_5_ITEM
NAND,3DV4,320GBT,XXX,S4E,256G,T,SLGA110
1335S00407 SSD_NAND:WD-2TBCRITICAL
NAND,3DV4,192GBT,XXX,S4E,256G,H,SLGA110
NAND,3DV4,320GBT,XXX,S4E,256G,SD,SLGA110
NAND,3DV4,512GBT,S4E,256G,H,SLGA110
8 CRITICAL
NAND,3DV4,512GBT,XXX,S4E,256G,SD,SLGA110
NAND,3DV4,1TBT,XXX,S4E,512G,SD,SLGA110
8335S00433 CRITICAL
U8600,U8700,U9100,U9200,U9300,U9400
U8600,U8700,U9100,U9200,U9300,U9400
U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400
U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400
U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400
U8800
U8800
CRITICAL
CRITICAL
SSD_NAND:TS-2TB
SSD_NAND:TS-2TB335S00397 6
SSD_NAND:HY-4TB
SSD_NAND:WD-4TB
SSD_NAND:WD-8TB
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
Plasma Cleaned
POR
PART NUMBER
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
TABLE_ALT_ITEM
ANY ALL998-18459 335S00391 SSD NAND: WD-4TB Plasma
B
CRITICALU12001337S00552 IC,CNL PCH-H,USFF,SR40F,PRQ,BGA499
A
ACE & Ridges
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,TBT,TITAN RIDGE DP,SLMHS,PRQ,C1,CSP337
IC,CD3217,ACE2,B2,USB PWR SW W/HV,BGA123
U2800,UB000 CRITICAL2338S00441
U3100,U3200,UB300,UB400 CRITICAL353S01960 4
Power Controllers
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,ISL9240HIB0Z,PMU,SOUNA,WCSP40,2.1X3.3MM
1353S01525
IC,ISL95828A,IMVP8 CPU REG,QFN48,6X6MM
338S00267 1
353S02108
IC,PMU,CALPE,D2249A0,OTP-AI,CSP324,0.4P
IC,RAA225101A2,SVI2,CONTROLLER,QFN40,5X5
IC,SUPPLY,INTERSIL,ISL6277B,SVI2.0,QFN48
WIFI/BT Module & Alternate
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,MODULE,WIFI/BT,MURATA,HARPOON,M,ES7.7,LGA385
PART NUMBER
ALLANY WIFI/BT Module339S00609339S00610
U7100 CRITICAL353S00928 1
UA600 CRITICAL1
UA8001353S01660
U3730 CRITICAL339S00609 1
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
CRITICALU7000
CRITICALU7800
CRITICAL
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
SYNC_MASTER= SYNC_DATE=08/22/2018
PAGE TITLE
A
BOM Configuration 2
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
3 OF 200
SHEET
3 OF 135
8
67
35 4
2
1
Vinafix.com
D
C
B
A
1X 870-08567
PG0410
POGO-2.3OD-4.78H-X968
SM
1
3.4OD1.75ID-1.12H-SM
3.4OD1.75ID-1.12H-SM
3.4OD1.75ID-1.12H-SM
9X 870-08821
PG0411
POGO-2.3OD-4.63H-SM
SM-1
1
PG0421
POGO-2.3OD-4.63H-SM
SM-1
1
PG0440
POGO-2.3OD-4.63H-SM
SM-1
1
PG0441
POGO-2.3OD-4.63H-SM
SM-1
1
PG0430
POGO-2.3OD-4.63H-SM
SM-1
1
PG0471
POGO-2.3OD-4.63H-SM
SM-1
1
PG0470
POGO-2.3OD-4.63H-SM
SM-1
1
PG0401
POGO-2.3OD-4.63H-SM
SM-1
1
PG0400
POGO-2.3OD-4.63H-SM
SM-1
1
2.7X1.8R-1.4ID-0.91H-SM
2.7X1.8R-1.4ID-0.91H-SM
TOUCH-COWLING-HOOK-X378
3.4OD1.75ID-1.12H-SM
3.4OD1.75ID-1.45H-SM
3.4OD1.75ID-1.45H-SM
3.4OD1.75ID-1.9H-SM
3.4OD1.75ID-1.9H-SM
3.4OD1.75ID-1.9H-SM
3.4OD1.75ID-1.9H-SM
3.4OD1.75ID-2.12H-SM
Shield Can Through-Holes
APN 998-2691
DRAM
TH0400
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0401
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0402
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0403
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0404
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0405
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0406
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0407
TH-NSP
1
SL-1.2X0.4-1.5X0.7
H9MVRAM
TH0408
1
SL-1.2X0.4-1.5X0.7
TH0409
1
SL-1.2X0.4-1.5X0.7
TBT Left
TH0410
1
SL-1.2X0.4-1.5X0.7
TH0411
1
SL-1.2X0.4-1.5X0.7
TH-NSP
TH-NSP
TH-NSP
TH-NSP
APN 860-00392
BS0400
BS0410
BS0401
BS0411
APN 806-06520
BS0420
BS0421
APN 806-06521
BS0430
BS0450
BS0431
BS0441
APN 860-00469
BS0470
BS0471
APN 806-06600
BS0480
APN 806-20398
DFR Touch - TOP side
1
1
1
1
1
USB-C Left BOT side - North
USB-C Right BOT side - North
USB-C Left BOT side - South
USB-C Right BOT side - Left
DFR Touch BOT side
1
Angle Sensor BOT side
1
1
1
DFR Display BOT side - Left
Trackpad BOT side - Left
DFR Display BOT side - Right
1
Keyboard BOT side - Right
1
eDP TOP side - Left
1
eDP TOP side - Right
1
Audio Jack + Mesa BOT side - Southwest
OMIT_TABLE
BS0472
1
SM
GPU VR
TH0412
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0413
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TBT Right
TH0420
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0421
TH-NSP
1
SL-1.2X0.4-1.5X0.7
678
4X 860-00986 11X 860-01209
BM0488
2.8OD1.2ID-3.59H-SM
1
2
BM0485
2.8OD1.2ID-3.59H-SM
1 2
BM0487
2.8OD1.2ID-3.59H-SM
1
2
BM0489
2.8OD1.2ID-3.59H-SM
1 2
2X 860-01447
BM0407
2.8OD1.2ID-1.55H-SM
1
2
BM0413
2.8OD1.2ID-1.55H-SM
1
2
1X 860-01394
BM0482
3.14OD1.2ID-3.69H-SM
1
2
BM0403
2.8OD1.2ID-1.65H-SM
1 2
BM0410
2.8OD1.2ID-1.65H-SM
1 2
BM0408
2.8OD1.2ID-1.65H-SM
1 2
BM0406
2.8OD1.2ID-1.65H-SM
1 2
BM0402
2.8OD1.2ID-1.65H-SM
1 2
BM0483
2.8OD1.2ID-1.65H-SM
1 2
BM0409
2.8OD1.2ID-1.65H-SM
1 2
BM0405
2.8OD1.2ID-1.65H-SM
1 2
BM0412
2.8OD1.2ID-1.65H-SM
1 2
3X 860-01208
BM0400
2.8OD1.2ID-4.4H-SM
1 2
BM0484
2.8OD1.2ID-4.4H-SM
1
2
BM0486
2.8OD1.2ID-4.4H-SM
1
2
1X 860-01452
BM0411
3.21OD1.2ID-4.163H-SM
1
2
3 245
OMIT_TABLE
1
SH0400
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0416
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0415
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0405
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0407
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0410
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0411
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
Dummy Parts
Bumpers & Bridges
NOSTUFF
C0404
1UF
1 2
10%
402
CKPLUS_WAIVE=TERMSHORTED
CERM6.3V
C0406
1UF
1 2
10%
6.3V CERM
CKPLUS_WAIVE=TERMSHORTED
402
C0420
1.0UF
1 2
20%4V0201
CKPLUS_WAIVE=TERMSHORTED
X6S
NOSTUFF
C0421
1.0UF
1 2
20%
0201
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0422
1.0UF
1 2
20%
0201
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0423
1.0UF
1 2
20%
0201
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0424
1.0UF
1 2
20%
0201
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0425
1.0UF
1 2
20%
0201 X6S
4V
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0426
1.0UF
1 2
020120%
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0427
1
D
C
1.0UF
1 2
20%
OMIT_TABLE
1
SH0412
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0414
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
CKPLUS_WAIVE=TERMSHORTED
CKPLUS_WAIVE=TERMSHORTED
CKPLUS_WAIVE=TERMSHORTED
0201 X6S
4V
NOSTUFF
C0428
1.0UF
1 2
0201
20%
4V X6S
NOSTUFF
C0429
1.0UF
1 2
20%
0201
4V X6S
NOSTUFF
C0430
B
1.0UF
OMIT_TABLE
1
SH0413
SM
1 2
0201
20%
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0431
1.0UF
Shield Cans & Cowlings
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
SH0400 CRITICAL806-20400 1 SHIELD,FENCE,DIPLEX,X968
1806-17829 SH0407 CRITICALSHIELD,FENCE,TR,RT,X1181
1 CRITICAL806-20399 SHIELD,FENCE,TR,LT,X968 SH0410
SH0411,SH0412806-21174 2 CRITICALSHIELD,FENCE,DRAM,X1181
2 CRITICAL806-15804 SH0413,SH0415SHIELD,SLED,GPU,X1183
2 CRITICAL806-13997 SH0414,SH0416SHIELD,SLED,CPU,X1181
1 CRITICAL806-20878 SH0420SHIELD,FENCE,VRAM,X968
1 CRITICAL806-20877 SH0421SHIELD,FENCE,VRAM,BTM,X968
SHIELD-DIPLEX-BLACK-X378A-X1099
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
CRITICALSH0405806-17111 1 SHIELD,FENCE,H9M,X1181
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL1806-20876 SHIELD,FENCE,GPU VR,X968 SH0422
TABLE_5_ITEM
CRITICAL1806-20398 TOP MODULE TOUCH,COWLING,SMT HOOK,X968 BS0472
SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0420
SM
OMIT_TABLE
1
SH0421
SM
OMIT_TABLE
1
SH0422
SM
SYNC_MASTER=
PAGE TITLE
PD Parts
Apple Inc.
1 2
0201
20%
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0432
1.0UF
1 2
20%
0201
4V X6S
CKPLUS_WAIVE=TERMSHORTED
DRAWING NUMBER
051-04492
REVISION
SYNC_DATE=10/14/2018
SIZE
D
A
2.15.0
SHIELD-DIPLEX-BLACK-X378A-X1099
BOM_COST_GROUP=MECHANICALS
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
BRANCH
PAGE
4 OF 200
SHEET
4 OF 135
8
67
35 4
2
1
Vinafix.com
D
C
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
IN IN IN IN
IN IN IN IN
OUT OUT OUT OUT
OUT OUT OUT OUT
DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>
DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>
DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>
DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>
E8 F6 E5
J9
D8 E6 D5
J8
A8 B6 A5 B4
B8 C6 B5 D4
CFL-H-DDR4-IL-8+2
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
U0500
BGA
CFLH
SYM 1 OF 13
CRITICAL
OMIT_TABLE
DMI
678
PEG_RCOMP
PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8
PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15
PEG_RXP0
PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8 PEG_RXP9
PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15
G2
D25 F24 D23 F22 D21 F20 D19 F18 E17 E16 E15 E14 E13 E12 E11 E10
E25 E24 E23 E22 E21 E20 E19 E18 D17 F16 D15 F14 D13 F12 D11 F10
CPU_PEG_RCOMP
PEG_GPU_D2R_N<0> PEG_GPU_D2R_N<1> PEG_GPU_D2R_N<2> PEG_GPU_D2R_N<3> PEG_GPU_D2R_N<4> PEG_GPU_D2R_N<5> PEG_GPU_D2R_N<6> PEG_GPU_D2R_N<7> PCIE_TBT_X_D2R_N<0> PCIE_TBT_X_D2R_N<1> PCIE_TBT_X_D2R_N<2> PCIE_TBT_X_D2R_N<3> PCIE_TBT_T_D2R_N<0> PCIE_TBT_T_D2R_N<1> PCIE_TBT_T_D2R_N<2> PCIE_TBT_T_D2R_N<3>
PEG_GPU_D2R_P<0> PEG_GPU_D2R_P<1> PEG_GPU_D2R_P<2> PEG_GPU_D2R_P<3> PEG_GPU_D2R_P<4> PEG_GPU_D2R_P<5> PEG_GPU_D2R_P<6> PEG_GPU_D2R_P<7> PCIE_TBT_X_D2R_P<0> PCIE_TBT_X_D2R_P<1> PCIE_TBT_X_D2R_P<2> PCIE_TBT_X_D2R_P<3> PCIE_TBT_T_D2R_P<0> PCIE_TBT_T_D2R_P<1> PCIE_TBT_T_D2R_P<2> PCIE_TBT_T_D2R_P<3>
From Intel EDS PEG RCOMP Range = 24.76,25.25
Voltage = VCCIO (Page 121, Note 3)
PPVCCIO_S0_CPU
1
R0510
24.9
1% 1/16W MF-LF 402
2
PLACE_NEAR=U0500.G2:5mm
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
5 8 10 117 124
119
NC_DDI1_ML_C_N<0>
NC_DDI1_ML_C_P<0>
119
119
NC_DDI1_ML_C_N<1> NC_DDI1_ML_C_P<1>
119
119
NC_DDI1_ML_C_N<2> NC_DDI1_ML_C_P<2>
119
119
NC_DDI1_ML_C_N<3> NC_DDI1_ML_C_P<3>
119
NC_DDI2_ML_C_N<0>
119
NC_DDI2_ML_C_P<0>
119
119
NC_DDI2_ML_C_N<1>
119
NC_DDI2_ML_C_P<1> NC_DDI2_ML_C_N<2>
119
NC_DDI2_ML_C_P<2>
119
119
NC_DDI2_ML_C_N<3>
119
NC_DDI2_ML_C_P<3>
NC_DDI3_ML_N<2>
119
NC_DDI3_ML_P<2>
119
119
NC_DDI3_ML_N<3> NC_DDI3_ML_P<3>
119
NC_DDI3_ML_N<0>
119
119
NC_DDI3_ML_P<0>
119
NC_DDI3_ML_N<1> NC_DDI3_ML_P<1>
119
Port D pins out of order to match Intel symbol.
K37 K36
J34
J35 H36 H37
J38
J37
H33 H34 G38
F37 F35 F34 E36 E37
E33 F33 B33
C33 D34
C34
B34 B36
3 245
CFL-H-DDR4-IL-8+2
DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3
DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3
DDI3_TXN2 DDI3_TXP2 DDI3_TXN3 DDI3_TXP3
DDI3_TXN0 DDI3_TXP0 DDI3_TXN1 DDI3_TXP1
U0500
BGA
CFLH
SYM 11 OF 13
CRITICAL
OMIT_TABLE
EDP
DIGITAL DISPLAY INTERFACES
EDP_AUXN EDP_AUXP
EDP_TXN0 EDP_TXN1 EDP_TXN2 EDP_TXN3
EDP_TXP0 EDP_TXP1 EDP_TXP2 EDP_TXP3
DISP_RCOMP
EDP_DISP_UTIL
DDI1_AUXN DDI1_AUXP
DDI2_AUXN DDI2_AUXP
DDI3_AUXN DDI3_AUXP
B26 C26
E29 E28 B29 B28
D29 F28 A29 C28
D37 A33
E27 D27
E26 F26
B27 A27
NC
DP_INT_IG_AUX_N DP_INT_IG_AUX_P
DP_INT_IG_ML_N<0> DP_INT_IG_ML_N<1> DP_INT_IG_ML_N<2> DP_INT_IG_ML_N<3>
DP_INT_IG_ML_P<0> DP_INT_IG_ML_P<1> DP_INT_IG_ML_P<2> DP_INT_IG_ML_P<3>
CPU_EDP_RCOMP
NC_DDI1_AUXCH_C_N NC_DDI1_AUXCH_C_P
NC_DDI2_AUXCH_C_N NC_DDI2_AUXCH_C_P
NC_DDI3_AUXCH_N NC_DDI3_AUXCH_P
119
119
119
119
119
119
1
120 95
120 95
120 95
120 95
120 95
120 95
120 95
120 95
120 95
120 95
PPVCCIO_S0_CPU
1
R0530
24.9
1% 1/16W MF-LF 402
2
PLACE_NEAR=U0500.D37:5mm
D
124
5 8 10
117
C
B
PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5
PCI EXPRESS BASED INTERFACE SIGNALS
PEG_TXN6 PEG_TXN7 PEG_TXN8
PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
A25 C24 A23 C22 A21 C20 A19 C18 B17 B16 B15 B14 B13 B12 B11 B10
B25 B24 B23 B22 B21 B20 B19 B18 A17 C16 A15 C14 A13 C12 A11 C10
PEG_GPU_R2D_C_N<0> PEG_GPU_R2D_C_N<1> PEG_GPU_R2D_C_N<2> PEG_GPU_R2D_C_N<3> PEG_GPU_R2D_C_N<4> PEG_GPU_R2D_C_N<5> PEG_GPU_R2D_C_N<6> PEG_GPU_R2D_C_N<7> PCIE_TBT_X_R2D_C_N<0> PCIE_TBT_X_R2D_C_N<1> PCIE_TBT_X_R2D_C_N<2> PCIE_TBT_X_R2D_C_N<3> PCIE_TBT_T_R2D_C_N<0> PCIE_TBT_T_R2D_C_N<1> PCIE_TBT_T_R2D_C_N<2> PCIE_TBT_T_R2D_C_N<3>
PEG_GPU_R2D_C_P<0> PEG_GPU_R2D_C_P<1> PEG_GPU_R2D_C_P<2> PEG_GPU_R2D_C_P<3> PEG_GPU_R2D_C_P<4> PEG_GPU_R2D_C_P<5> PEG_GPU_R2D_C_P<6> PEG_GPU_R2D_C_P<7> PCIE_TBT_X_R2D_C_P<0> PCIE_TBT_X_R2D_C_P<1> PCIE_TBT_X_R2D_C_P<2> PCIE_TBT_X_R2D_C_P<3> PCIE_TBT_T_R2D_C_P<0> PCIE_TBT_T_R2D_C_P<1> PCIE_TBT_T_R2D_C_P<2> PCIE_TBT_T_R2D_C_P<3>
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
TP-P5 TP-P5
TP-P5 TP-P5 TP-P5
TP0501 TP0502
TP0503 TP0504 TP0505
TP TP
TP TP TP
U0500
CFL-H-DDR4-IL-8+2
BGA
1 1
1 1 1
CPU_DC_B2_C1 CPU_IST_TRIG CPU_DC_B38_C38
NC
CPU_DC_BR2_BR1 CPU_DC_C1_B2 CPU_DC_C38_B38
NC
NC
BR33
AT13
AW13
NC
RSVD IST_TRIG
B2
RSVD
B38
RSVD
BP1
RSVD
BR2
RSVD
C1
RSVD
C38
SKTOCC* ZVM*
MSM*
CFLH
SYM 13 OF 13
PROC_TRIGIN
PROC_TRIGOUT
PROC_AUDIO_CLK
PROC_AUDIO_SDI
PROC_AUDIO_SDO
DDR_VTT_CNTL
PM_DOWN
Impedance Spectrum Tool
E3
H23 J23
G27 G25 G29
BT13 BP31
PCH_CPU_TRIGGER CPU_PCH_TRIGGER_R
PCH_DISPA_BCLK PCH_DISPA_SDO CPU_PROC_AUD_SDO_R
PM_MEMVTT_EN CPU_PCH_PM_DOWN_R
Each corner of CPU has two testpoints.
5
5
IN
IN IN
5
OUT
13
20
20
1
TP-P6
1
TP-P6
PLACE_NEAR=TP0506.1:5mm
121 74
A
TP0506
A
TP0507
B
Other corner test signals connected in daisy-chain fashion. Continuity should exist between both TP's on each corner.
R0524
5
CPU_PCH_TRIGGER_R
30
1 2
5%
1/20W
MF
201
CPU_PCH_TRIGGER
OUT
13
A
5
5
BOM_COST_GROUP=CPU & CHIPSET
CPU_PCH_PM_DOWN_R
CPU_PROC_AUD_SDO_R
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
R0525
20
1 2
5%
1/20W
MF
201
R0526
20
1 2
5%
1/20W
MF
201
CPU_PCH_PM_DOWN
PCH_DISPA_SDI
Apple Inc.
13
OUT
20
OUT
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
5 OF 200
SHEET
5 OF 135
A
SIZE
D
8
67
35 4
2
1
Vinafix.com
678
3 245
1
D
C
8 11 117
8 11 46 117
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
PP1V05_S0SW PP1V05_S3
46
CPU_PROCHOT_L
IN
121 46
These can be placed close to
J1800 and only for debug access
NOSTUFF
R0649
1K
5%
1/20W
MF
201
CPU_CFG<16> CPU_CFG<9> CPU_CFG<3> CPU_CFG<1> CPU_CFG<0>
NOSTUFF
1K
5%
1/20W
MF
201
1
2
1
2
R0648
NOSTUFF
1
R0643
1K
5% 1/20W MF 201
2
NOSTUFF
R0641
1K
5%
1/20W
MF
201
1
2
NOSTUFF
1
R0640
1K
5% 1/20W MF 201
2
18 6
18 6
18 6
18 6
18 6
PP0600 PP0601
PP0602 PP0603
18 6
18 6
18 6
18 6
18 6
NOSTUFF
R0647
1K
5%
1/20W
MF
201
CPU_CFG<7> CPU_CFG<6> CPU_CFG<5> CPU_CFG<4>
CPUCFG6_PD
1
2
R0646
1K
5%
1/20W
MF
201
1
2
CPUCFG5_PD
1
R0645
1K
5% 1/20W MF 201
2
EDP:YES
R0644
1K
5%
1/20W
MF
201
CPU_CFG<2>
NOSTUFF
1
2
1
R0642
1K
5% 1/20W MF 201
2
P2MM
SM
1
PP
P2MM
SM
1
PP
P2MM
SM
1
PP
P2MM
SM
1
PP
OUT
CPU_RSVD_R14
CPU_RSVD_N29
CPU_RSVD_AE29
CPU_RSVD_AA14
TP0619
1
R0605
1K
1% 1/16W MF-LF 402
2
A
TP-P6
NOSTUFF
1
R0604
1K
1% 1/16W MF-LF 402
2
TP_CPU_RSVD_TP_D1
1
PPVCC_S0_CPU
8 58 117
6
6
6
6
1
R0601
1K
1% 1/16W MF-LF 402
2
6
6
6
6
CPU_RSVD_R14 CPU_RSVD_N29 CPU_RSVD_AE29 CPU_RSVD_AA14
77
OUT
PLACE_NEAR=U0500.BR30:5mm
R0603
499
1 2
1%
201
1/20W
MF
46 13
13
13
121 13
120 12
120 12
120 12
120 12
120 12
120 12
BI
IN IN IN
IN IN
IN IN
IN IN
D1
V30 V12 V29 Y35
R14
N29 AE29 AA14
CPU_CATERR_L
CPU_PECI
CPU_PROCHOT_R_L
PM_THRMTRIP_L
PM_SYNC CPU_RESET_L CPU_PWRGD
CPU_CLK24M_NSSC_CLK_N CPU_CLK24M_NSSC_CLK_P
CPU_CLK100M_PCIBCLK_N CPU_CLK100M_PCIBCLK_P
CPU_CLK100M_BCLK_N CPU_CLK100M_BCLK_P
CRITICAL OMIT_TABLE
RSVD_TP
VSS VSS VSS VCC
RSVD RSVD RSVD RSVD
PLACE_NEAR=U0500.BT31:157mm
CFL-H-DDR4-IL-8+2
U0500
BGA
CFLH
SYM 12 OF 13
RESERVED
(IPU)
(IPU)
CFG_RCOMP
CFG16 CFG18 CFG17 CFG19
R0611
RSVD RSVD RSVD RSVD
RSVD
10K
5% 1/16W MF-LF
402
BT25 BP23
BN22 BN23 BP22
AU13 AY13 J24 J3
BN33
U0500
CFL-H-DDR4-IL-8+2
PROC_SELECT*
NC
1
2
BN1
BM30
BT34
BR30
J31
BM34
BP35
BT31
D31 E31
C36 D35
A32 B31
CATERR*
PECI
PROCHOT*
THERMTRIP*
PM_SYNC RESET* PROCPWRGD
CLK24N CLK24P
PCI_BCLKN PCI_BCLKP
BCLKN BCLKP
CRITICAL OMIT_TABLE
CPU_CFG_RCOMP CPU_CFG<16>
CPU_CFG<18> CPU_CFG<17> CPU_CFG<19>
NC NC NC NC
NC
BGA
CFLH
SYM 2 OF 13
THERMALPWRCLOCK
18 6
18
TP-P5
TP-P5
DDR3
(IPU) (IPU)
(IPD) (IPU)
(IPU)
(IPU)
JTAG
1
TP
TP0617
1
TP
TP0618
DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2
PROC_PRDY* PROC_PREQ*
PROC_TCK
PROC_TMS
PROC_TRST*
PROC_TDI
PROC_TDO
(IPU) (IPU) (IPU) (IPU)
BPM0* BPM1* BPM2* BPM3*
G1 H1 J2
BP27 BL30
BR28 BP28 BP30
BL32 BT28
BR27 BT27
BM31
BT30
1
R0690
49.9
1% 1/16W MF-LF 402
2
CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>
XDP_CPU_PRDY_L XDP_CPU_PREQ_L
XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L
XDP_CPU_TDI XDP_CPU_TDO
XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3>
OUT
IN
IN IN IN
IN
OUT
BI BI BI BI
18
18
18
18
1
R0614
100
2
1% 1/16W MF-LF 402
123 18 13
123 18 13
123 18
123 18
123 18 13
123 18
123 18
1
R0613
121
1% 1/16W MF-LF 402
2
1
R0612
121
1% 1/16W MF-LF 402
2
D
C
B
TP0601 TP0602 TP0603 TP0604 TP0605 TP0606 TP0607 TP0608 TP0609 TP0610 TP0611 TP0612 TP0613 TP0614 TP0615 TP0616
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
CPU_CFG<0>
1
CPU_CFG<1>
1
CPU_CFG<2>
1
CPU_CFG<3>
1
CPU_CFG<4>
1
CPU_CFG<5>
1
CPU_CFG<6>
1 1
CPU_CFG<7>
CPU_CFG<8>
1
CPU_CFG<9>
1
CPU_CFG<10>
1
CPU_CFG<11>
1
CPU_CFG<12>
1 1
CPU_CFG<13> CPU_CFG<14>
1 1
CPU_CFG<15>
NC NC
BN25 BN27 BN26 BN28 BR20
BM20
BT20 BP20 BR23 BR22
BT23
BT22
BM19
BR19 BP19
BT19
G3
G13
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
RSVD RSVD
(IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU)
RSVD RSVD
RSVD
RSVD
RSVD_TP RSVD_TP
VSS VSS
VSS VSS
RSVD RSVD RSVD
BR35 BR31
BN35
C30
BT2 BR1
W3 W2
V6 W1
H24 E30 F30
NC NC
NC
NC
TP_CPU_RSVD_TP_BT2 CPU_DC_BR1_BR2
NC NC NC
TP-P5
TP-P5
B
1
TP
1
TP0620
TP
TP0600
A
8
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_ITEM
CPUCFG5_PDCPUPEG:X8X8
TABLE_BOMGROUP_ITEM
CPUCFG6_PD,CPUCFG5_PDCPUPEG:X8X4X4
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
CPU Clock/Misc/JTAG/CFG
To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
6 OF 200
SHEET
6 OF 135
1
SIZE
D
Vinafix.com
678
3 245
1
D
C
B
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
120 26 23 22
120 26 23 22
21
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT
IN
OUT
MEM_A_DQ<45> MEM_A_DQ<41> MEM_A_DQ<44> MEM_A_DQ<40> MEM_A_DQ<47> MEM_A_DQ<43> MEM_A_DQ<46> MEM_A_DQ<42> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<53> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<48> MEM_A_DQ<62> MEM_A_DQ<63> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<35> MEM_A_DQ<37> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<34> MEM_A_DQ<36> MEM_A_DQ<26> MEM_A_DQ<24> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<25> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<1> MEM_A_DQ<4> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<0> MEM_A_DQ<5> MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<13> MEM_A_DQ<8> MEM_A_DQ<14> MEM_A_DQ<9> MEM_A_DQ<15> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<16> MEM_A_DQ<19>
MEM_A_PAR MEM_A_ALERT_L CPU_DIMM_VREFCA MEM_A_ACT_L
DDR0_DQ0
BR6
DDR0_DQ1
BT6
DDR0_DQ2
BP3
DDR0_DQ3
BR3
DDR0_DQ4
BN5
DDR0_DQ5
BP6
DDR0_DQ6
BP2
DDR0_DQ7
BN3
DDR0_DQ8
BL4
DDR0_DQ9
BL5
DDR0_DQ10
BL2
DDR0_DQ11
BM1
DDR0_DQ12
BK4
DDR0_DQ13
BK5
DDR0_DQ14
BK1
DDR0_DQ15
BK2
DDR0_DQ16
BG4
DDR0_DQ17
BG5
DDR0_DQ18
BF4
DDR0_DQ19
BF5
DDR0_DQ20
BG2
DDR0_DQ21
BG1
DDR0_DQ22
BF1
DDR0_DQ23
BF2
DDR0_DQ24
BD2
DDR0_DQ25
BD1
DDR0_DQ26
BC4
DDR0_DQ27
BC5
DDR0_DQ28
BD5
DDR0_DQ29
BD4
DDR0_DQ30
BC1
DDR0_DQ31
BC2
DDR0_DQ32
AB1
DDR0_DQ33
AB2
DDR0_DQ34
AA4
DDR0_DQ35
AA5
DDR0_DQ36
AB5
DDR0_DQ37
AB4
DDR0_DQ38
AA2
DDR0_DQ39
AA1
DDR0_DQ40
V5
DDR0_DQ41
V2
DDR0_DQ42
U1
DDR0_DQ43
U2
DDR0_DQ44
V1
DDR0_DQ45
V4
DDR0_DQ46
U5
DDR0_DQ47
U4
DDR0_DQ48
R2
DDR0_DQ49
P5
DDR0_DQ50
R4
DDR0_DQ51
P4
DDR0_DQ52
R5
DDR0_DQ53
P2
DDR0_DQ54
R1
DDR0_DQ55
P1
DDR0_DQ56
M4
DDR0_DQ57
M1
DDR0_DQ58
L4
DDR0_DQ59
L2
DDR0_DQ60
M5
DDR0_DQ61
M2
DDR0_DQ62
L5
DDR0_DQ63
L1
DDR0_PAR
AG3
DDR0_ALERT*
AU5
DDR_VREF_CA
BN13
DDR0_ACT*
AU3
U0500
BGA
SYM 3 OF 13
CFLH
CFL-H-DDR4-IL-8+2
CRITICAL OMIT_TABLE
DDR0_CKN0 DDR0_CKP0 DDR0_CKE0
DDR0_CKN1 DDR0_CKP1 DDR0_CKE1
DDR0_CKN2 DDR0_CKP2 DDR0_CKE2
DDR0_CKN3 DDR0_CKP3 DDR0_CKE3
DDR0_CS0* DDR0_CS1* DDR0_CS2* DDR0_CS3*
DDR0_ODT0 DDR0_ODT1 DDR0_ODT2 DDR0_ODT3
MEMORY CHANNEL DDR0
DDR0_ECC0 DDR0_ECC1 DDR0_ECC2 DDR0_ECC3 DDR0_ECC4 DDR0_ECC5 DDR0_ECC6 DDR0_ECC7
DDR0_DQSN0 DDR0_DQSN1 DDR0_DQSN2 DDR0_DQSN3 DDR0_DQSN4 DDR0_DQSN5 DDR0_DQSN6 DDR0_DQSN7 DDR0_DQSN8
DDR0_DQSP0 DDR0_DQSP1 DDR0_DQSP2 DDR0_DQSP3 DDR0_DQSP4 DDR0_DQSP5 DDR0_DQSP6 DDR0_DQSP7 DDR0_DQSP8
VSS
AG2 AG1 AT1
AK1 AK2 AT2
AK3 AL3 AT3
AL1 AL2 AT5
AD5 AE2 AD2 AE5
AD3 AE4 AE1 AD4
U38
BA2 BA1 AY4 AY5 BA5 BA4 AY1 AY2
BR5 BL3 BG3 BD3 AA3 U3 P3 L3 BA3
BP5 BK3 BF3 BC3 AB3 V3 R3 M3 AY3
NC NC
NC NC
NC NC
NC NC
NC NC NC NC NC NC NC NC
NC
NC
MEM_A_CLK_N<0> MEM_A_CLK_P<0> MEM_A_CKE<0>
NC_MEM_A_CLK_N<1> NC_MEM_A_CLK_P<1> MEM_A_CKE<1>
NC_MEM_A_CKE<2>
NC_MEM_A_CKE<3>
MEM_A_CS_L<0> MEM_A_CS_L<1>
MEM_A_ODT<0> MEM_A_ODT<1>
MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7> MEM_A_DQS_N<4> MEM_A_DQS_N<3> MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2>
MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7> MEM_A_DQS_P<4> MEM_A_DQS_P<3> MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2>
OUT OUT OUT
OUT OUT OUT
OUT
OUT
OUT OUT
OUT OUT
BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
120 26 23 22
120 26 23 22
120 26 23 22
120 26
120 26
120 26 23 22
120 26
120 26
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 25 24
120 26 25 24 120 26 23 22
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT
INOUT
MEM_B_DQ<22> MEM_B_DQ<16> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<20> MEM_B_DQ<23> MEM_B_DQ<19> MEM_B_DQ<21> MEM_B_DQ<11> MEM_B_DQ<14> MEM_B_DQ<9> MEM_B_DQ<12> MEM_B_DQ<15> MEM_B_DQ<13> MEM_B_DQ<8> MEM_B_DQ<10> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<7> MEM_B_DQ<1> MEM_B_DQ<4> MEM_B_DQ<0> MEM_B_DQ<25> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<26> MEM_B_DQ<31> MEM_B_DQ<24> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<35> MEM_B_DQ<32> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<60> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63> MEM_B_DQ<54> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<55> MEM_B_DQ<50> MEM_B_DQ<53> MEM_B_DQ<41> MEM_B_DQ<46> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<42> MEM_B_DQ<47> MEM_B_DQ<40> MEM_B_DQ<45>
MEM_B_PAR MEM_B_ALERT_L
DDR1_DQ0
BT11
DDR1_DQ1
BR11
DDR1_DQ2
BT9
DDR1_DQ3
BR8
DDR1_DQ4
BP11
DDR1_DQ5
BN11
DDR1_DQ6
BP8
DDR1_DQ7
BN8
DDR1_DQ8
BL12
DDR1_DQ9
BL11
DDR1_DQ10
BL8
DDR1_DQ11
BJ8
DDR1_DQ12
BJ11
DDR1_DQ13
BJ10
DDR1_DQ14
BL7
DDR1_DQ15
BJ7
DDR1_DQ16
BG11
DDR1_DQ17
BG10
DDR1_DQ18
BG8
DDR1_DQ19
BF8
DDR1_DQ20
BF11
DDR1_DQ21
BF10
DDR1_DQ22
BG7
DDR1_DQ23
BF7
DDR1_DQ24
BB11
DDR1_DQ25
BC11
DDR1_DQ26
BB8
DDR1_DQ27
BC8
DDR1_DQ28
BC10
DDR1_DQ29
BB10
DDR1_DQ30
BC7
DDR1_DQ31
BB7
DDR1_DQ32
AA11
DDR1_DQ33
AA10
DDR1_DQ34
AC11
DDR1_DQ35
AC10
DDR1_DQ36
AA7
DDR1_DQ37
AA8
DDR1_DQ38
AC8
DDR1_DQ39
AC7
DDR1_DQ40
W8
DDR1_DQ41
W7
DDR1_DQ42
V10
DDR1_DQ43
V11
DDR1_DQ44
W11
DDR1_DQ45
W10
DDR1_DQ46
V7
DDR1_DQ47
V8
DDR1_DQ48
R11
DDR1_DQ49
P11
DDR1_DQ50
P7
DDR1_DQ51
R8
DDR1_DQ52
R10
DDR1_DQ53
P10
DDR1_DQ54
R7
DDR1_DQ55
P8
DDR1_DQ56
L11
DDR1_DQ57
M11
DDR1_DQ58
L7
DDR1_DQ59
M8
DDR1_DQ60
L10
DDR1_DQ61
M10
DDR1_DQ62
M7
DDR1_DQ63
L8
DDR1_PAR
AJ7
AR8
DDR1_ALERT*
U0500
CFL-H-DDR4-IL-8+2
BGA
SYM 4 OF 13
CFLH
CRITICAL
OMIT_TABLE
DDR1_CKN0 DDR1_CKP0 DDR1_CKE0
DDR1_CKN1 DDR1_CKP1 DDR1_CKE1
DDR1_CKN2 DDR1_CKP2 DDR1_CKE2
DDR1_CKN3 DDR1_CKP3 DDR1_CKE3
DDR1_CS0* DDR1_CS1* DDR1_CS2* DDR1_CS3*
DDR1_ODT0 DDR1_ODT1 DDR1_ODT2 DDR1_ODT3
MEMORY CHANNEL DDR1
DDR1_ECC0 DDR1_ECC1 DDR1_ECC2 DDR1_ECC3 DDR1_ECC4 DDR1_ECC5 DDR1_ECC6 DDR1_ECC7
DDR1_DQSN0 DDR1_DQSN1 DDR1_DQSN2 DDR1_DQSN3 DDR1_DQSN4 DDR1_DQSN5 DDR1_DQSN6 DDR1_DQSN7 DDR1_DQSN8
DDR1_DQSP0 DDR1_DQSP1 DDR1_DQSP2 DDR1_DQSP3 DDR1_DQSP4 DDR1_DQSP5 DDR1_DQSP6 DDR1_DQSP7 DDR1_DQSP8
VSS
AN9 AM9 AT8
AM8 AM7 AT10
AM10 AM11 AT7
AJ11 AJ10 AT11
AF11 AE7 AF10 AE10
AF7 AE8 AE9 AE11
Y38
AW11 AY11 AY8 AW8
AY10 AW10 AY7 AW7
BN9 BL9 BG9 BC9 AC9
W9
R9
M9 AY9
BP9
BJ9 BF9 BB9 AA9 V9
P9
L9 AW9
NC NC
NC NC
NC NC
NC NC
NC NC NC NC
NC
NC
MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CKE<0>
NC_MEM_B_CLK_N<1> NC_MEM_B_CLK_P<1> MEM_B_CKE<1>
NC_MEM_B_CKE<2>
NC_MEM_B_CKE<3>
MEM_B_CS_L<0> MEM_B_CS_L<1>
MEM_B_ODT<0> MEM_B_ODT<1>
NC NC NC NC
MEM_B_DQS_N<2> MEM_B_DQS_N<1> MEM_B_DQS_N<0> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<7> MEM_B_DQS_N<6> MEM_B_DQS_N<5>
MEM_B_DQS_P<2> MEM_B_DQS_P<1> MEM_B_DQS_P<0> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<7> MEM_B_DQS_P<6> MEM_B_DQS_P<5>
OUT OUT OUT
OUT OUT OUT
OUT
OUT
OUT OUT
OUT OUT
BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI
120 26 25 24
120 26 25 24
120 26 25 24
120 26
120 26
120 26 25 24
D
120 26
120 26
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
C
128
128
128
128
128
128
128
128
B
128
128
128
128
128
128
128
128
A
21
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
OUT
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
CPU_DIMMB_VREFDQ
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
NC
DDR0_VREF_DQ
BP13
DDR1_VREF_DQ
BR13
DDR0_MA0
AH3
DDR0_MA1
AP4
DDR0_MA2
AN4
DDR0_MA3
AP5
DDR0_MA4
AP2
DDR0_MA5
AP1
DDR0_MA6
AP3
DDR0_MA7
AN1
DDR0_MA8
AN3
DDR0_MA9
AT4
DDR0_MA10
AH2
DDR0_MA11
AN2
DDR0_MA12
AU4
DDR0_MA13
AE3
DDR0_MA14
AG4
DDR0_MA15
AD1
DDR0_MA16
AH4
RSVD RSVD RSVD
DDR0_BA0
DDR0_BA1 DDR0_BG0 DDR0_BG1
AJ8 B30 BH30
AH5 AH1 AU1 AU2
NC NC NC
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
OUT OUT OUT OUT
120 26 25 24
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
OUT
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
MEM_B_ACT_L
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
AT9
AJ9 AK6 AK5
AL5 AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11 AR10
AF9
AH11
AF8
AH10
DDR1_ACT*
DDR1_MA0 DDR1_MA1 DDR1_MA2 DDR1_MA3 DDR1_MA4 DDR1_MA5 DDR1_MA6 DDR1_MA7 DDR1_MA8 DDR1_MA9 DDR1_MA10 DDR1_MA11 DDR1_MA12 DDR1_MA13 DDR1_MA14 DDR1_MA15 DDR1_MA16
RSVD
RSVD
DDR1_BA0
DDR1_BA1 DDR1_BG0 DDR1_BG1
BK28
BJ28
AH8 AH9 AR9 AR7
NC
NC
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0> MEM_B_BG<1>
BOM_COST_GROUP=CPU & CHIPSET
OUT OUT OUT OUT
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
CPU DDR4 Interfaces
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
051-04492
REVISION
2.15.0
2.15.0
BRANCH
PAGE
7 OF 200
7 OF 200
SHEET
7 OF 135
7 OF 135
8
67
35 4
2
1
Vinafix.com
678
3 245
1
D
C
B
A
6 8 58 117
PP1V05_S3
6 8 11
46 117
CPU_VCCST_PWRGD_R
8
6 11 117
PP1V05_S0SW
PULL-UPS FOR SENSE LINES
1
R0864
100
5% 1/20W MF 201
2
PPVCC_S0_CPU
1
1
R0865
100
5% 1/20W MF 201
2
R0866
100
5% 1/20W MF 201
2
AP38 AG12 AP37 AP36 AP35 AP32 AP31 AP30
AP13 AN38 AN37 AN36 AN35 AN34 AN33 AN32 AN31 AN14 AN13 AM36 AM35 AM34 AM33 AM32 AM31 AM30 AM29 AM14 AM13
AL38
AL37
AL36
AL35
AL32
AL31
AL30
AL29
AL13
AK38
AK37
AK36
AK35
AK34
AK33
AK32
AK31
AJ36 AJ35 AJ34 AJ33 AJ32 AJ31 AJ30 AJ29
AJ14 AH32 AH31 AH30 AH29 AH14 AH13 AG36 AG35 AG34 AG33 AG32 AG31 AG14
AF34 AF33 AF32 AF31 AF30 AF29
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCCST
H30
VCCST_PWRGD
H13
VCCSTG
G30
VCCSTG
H29
U0500
BGA
SYM 6 OF 13
POWER
CFL-H-DDR4-IL-8+2
CFLH
CRITICAL
OMIT_TABLE
VCCIO_SENSE
VSSIO_SENSE
VCCSA_SENSE
VSSSA_SENSE
PPVCC_S0_CPU PPVCCGT_S0_CPU PPVCCSA_S0_CPU
PPVCCIO_S0_CPU
1
R0861
100
5% 1/20W MF 201
2
PLACE_NEAR=U0500.H14:50.8mm PLACE_NEAR=U0500.AG37:50.8mm PLACE_NEAR=U0500.AH38:50.8mm PLACE_NEAR=U0500.M38:50.4mm
CPU_VCCIOSENSE_P CPU_VCCSASENSE_P
CPU_VCCGTSENSE_P
CPU_VCCSENSE_P
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA
VCCPLL VCCPLL
VCCPLL_OC VCCPLL_OC VCCPLL_OC
6 8 58 117
8 58 117
8 58 117 126
5 8 10 117 124
78 8
69 8
69 8
69 8
G15 G17 G19 G21 H15 H16 H17 H19 H20 H21 H26 H27 J15 J16 J17 J19 J20 J21 J26 J27
H14 J14
J30 K29 K30 K31 K32 K33 K34 K35 L31 L32 L35 L36 L37 L38 M29 M30 M31 M32 M33 M34 M35 M36
M38 M37
H28 J28
BH13 G11 BJ13
PPVCCIO_S0_CPU
CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N
PPVCCSA_S0_CPU
CPU_VCCSASENSE_P
CPU_VCCSASENSE_N
PP1V05_S3
Place C0802 on bottom side of U0500 Place C0803 on bottom side of U0500 PP1V2_S0SW
80 46
IN
6 8 11 46 117
PP1V05_S3
69
BI
6 8 11 46 117
5 8 10 117 124
OUT OUT
8 58 117 126
OUT OUT
69 8
69 9
11 117
CPU_VIDSOUT
C0802
1
1UF
20%
6.3V
2
X6S-CERM 0201
PP1V05_S3
78 8
78 9
C0803
1
1UF
20%
6.3V
2
X6S-CERM 0201
NOSTUFF
NOSTUFF
1
R0802
100
5% 1/20W MF 201
2
69
69
CPU_VIDALERT_L
IN
CPU_VIDSCLK
OUT
R0812
0
1 2
5% 1/16W MF-LF
402
117
PLACE_NEAR=U0500.H13:1MM
1
R0840
1K
1% 1/16W MF-LF 402
2
1
R0842
100
5% 1/20W MF 201
2
PP1V2_S3_CPUDDR
117
6 8 58 117
PPVCC_S0_CPU
69 8
OUT
69 9
OUT
1
R0800
56.2
1% 1/20W MF 201
2
R0810
220
1 2
5%
1/20W
MF
201
R0811
0
1 2
5% 1/16W MF-LF
402
PLACE_NEAR=U0500.H13:1MM
R0841
60.4
1 2
1%
1/20W
MF
201
TP0800 TP0801
6 8 58 117
CPU_VCCSENSE_P CPU_VCCSENSE_N
CPU_VIDALERT_R_L CPU_VIDSCLK_R CPU_VIDSOUT_R
TP_CPU_RSVD_TP75
1
TP
TP-P5
TP_CPU_RSVD_TP76
1
TP
TP-P5
PPVCC_S0_CPU
CPU_VCCST_PWRGD_RCPU_VCCST_PWRGD
NC NC NC NC
BL31
BL34 AP14 AP29
AA6
AE12
AF5
AF6 AG5 AG9
AJ12 AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5 J6
K12
K6
L12
L6 R6 T6
W6
Y12
U36 V13
AG37 AG38
BH31 BH32 BH29
Y7
Y8 E2 E1
Y9
Y13
W4
W34
Y10
W5
Y14
W12
Y37
W33
Y11
AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AB30 AB31 AA38 AB29
V14 V31 V32 V33 V34 V35 V36 V37
V38 W13 W14
RSVD RSVD RSVD RSVD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VCC VCC
VCC_SENSE VSS_SENSE
VIDALERT* VIDSCK VIDSOUT
VSS
VSS RSVD_TP RSVD_TP
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
CFL-H-DDR4-IL-8+2
U0500
BGA
CFLH
SYM 5 OF 13
CRITICAL
OMIT_TABLE
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
PPVCC_S0_CPU
AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38 K13 K14 L13 L14 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13 P14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y36
6 8 58 117
PPVCCGT_S0_CPU
8 58 117
BOM_COST_GROUP=CPU & CHIPSET
AT14 AT31 AT32 AT33 AT34 AT35 AT36 AT37
AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36
AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38
AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BE31 BE32 BE33
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
CFL-H-DDR4-IL-8+2
U0500
BGA
CFLH
SYM 7 OF 13
POWER
CRITICAL
OMIT_TABLE
VCCGT_SENSE
VSSGT_SENSE
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
BE34 BE35 BE36 BE37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38 BJ16 BJ17 BJ19 BJ20 BJ21 BJ23 BJ24 BJ26 BJ27 BJ37 BJ38 BK16 BK17 BK19 BK20 BK21 BK23 BK24 BK26 BK27 BL15 BL16 BL17 BL23 BL24 BL25 BL26 BL27 BL28 BL36 BL37 BM15 BM16 BM17 BM36 BM37 BN15 BN16 BN17 BN36 BN37 BN38 BP15 BP16 BP17 BP37 BP38 BR15 BR16 BR17 BR37 BT15 BT16 BT17 BT37
CPU_VCCGTSENSE_P
AH38
CPU_VCCGTSENSE_N
AH37
OUT OUT
CPU Power
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
8 OF 200
SHEET
8 OF 135
D
C
B
69 8
69 9
A
8
67
35 4
2
1
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678
3 245
1
D
C
B
A
A3 A4 A6
A9 A10 A12 A14 A16 A18 A20 A22 A24 A26 A34 A36 A37
AA12 AA29 AA30
AB6
AB33 AB34
AC1 AC2 AC3 AC4 AC5
AC6 AC12 AC37 AC38
AD6
AD7
AD8
AD9 AD10 AD11 AD12 AD29 AD30
AE6
AE33 AE34
AF1 AF2 AF3
AF4 AF12 AF13 AF14
AG6 AG7
AG8 AG10 AG11 AG13 AG29 AG30
AH6 AH12
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CFL-H-DDR4-IL-8+2
U0500
BGA
CFLH
SYM 8 OF 13
GROUND
CRITICAL OMIT_TABLE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AH33 AH34 AH35 AH36 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ13 AJ37 AJ38 AK4 AK29 AK30 AL4 AL7 AL8 AL9 AL10 AL12 AL14 AL33 AL34 AM1 AM2 AM3 AM4 AM5 AM12 AM37 AM38 AN5 AN6 AN12 AN29 AN30 AP8 AP9 AP10 AP11 AP12 AP33 AP34 AR1 AR2 AR3 AR4 AR5 AR13 AR14 AR29 AR30 AR31 AR32 AR33 AR34 AR35
AR36 AR37 AR38
AT6 AT29 AT30
AU6 AU7 AU8
AU9 AU10 AU11 AU12 AU33 AU34 AV37 AV38
AW1 AW2 AW3 AW4
AW5 AW12 AW29 AW30
AY12 AY14 AY33 AY34
B3 B9
B37 BA6 BA7 BA8 BA9
BA10 BA11 BA12 BA37 BA38
BB1 BB2 BB3 BB4 BB5 BB6
BB12 BB29 BB30
BC6
BC12 BC13 BC14 BC33 BC34
BD6 BD7 BD8 BD9
BD10 BD11 BD12 BD37 BD38
BE1 BE2 BE3 BE4 BE5 BE6
BE29 BE30
BF6
BF12 BF33 BF34
BG6
BG12 BG13 BG14
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
U0500
CFL-H-DDR4-IL-8+2
BGA
CFLH
SYM 9 OF 13
GROUND
CRITICAL
OMIT_TABLE
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BG37 BG38 BH1 BH2 BH3 BH4 BH5 BH6 BH7 BH8 BH9 BH10 BH11 BH12 BH14 BJ12 BJ14 BJ15 BJ18 BJ22 BJ25 BJ29 BJ30 BJ31 BJ32 BJ33 BJ34 BJ35 BJ36 BK6 BK13 BK14 BK15 BK18 BK22 BK25 BK29 BL6 BL13 BL14 BL18 BL19 BL20 BL21 BL22 BL29 BL33 BL35 BL38 BM2 BM3 BM5 BM6 BM7 BM8 BM9 BM11 BM12 BM13 BM14 BM18 BM21 BM22 BM23 BM24 BM25 BM26 BM27 BM28 BM29 BM33 BM35 BM38 BN2 BN19 C37 D3 D28 D30 D33 L33
A28
A30 BN4 BN7
BN12 BN14 BN18 BN20 BN21 BN24 BN29 BN30 BN31 BN34
BP7 BP12 BP14 BP18 BP21 BP24 BP25 BP26 BP29 BP33 BP34
BR7
BR9 BR12 BR14 BR18 BR21 BR24 BR25 BR26 BR29 BR34 BR36 BR38
BT3 BT4 BT5
BT8 BT12 BT14 BT18 BT21 BT24 BT26 BT29 BT32 BT35 BT36
C2 C5 C8
C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31
D6
D9 D10 D12 D14 D16 D18 D20 D22 D24 D26 D38
E4
E9 E34 E35 E38
F2
F3
F4
F5
F8
F9 F11 F13 F15 F17 F19
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CFL-H-DDR4-IL-8+2
U0500
BGA
CFLH
SYM 10 OF 13
GROUND
CRITICAL OMIT_TABLE
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
F21 F23 F25 F27 F29 F31 F36 G4 G5 G6 G8 G9 G10 G12 G14 G16 G18 G20 G22 G23 G24 G26 G28 H11 H12 H18 H22 H25 H32 H35 J4 J7 J10 J18 J22 J25 J32 J33 J36 K1 K2 K3 K4 K5 K7 K8 K9 K10 K11 K38 L29 L30 L34 M6 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N33 N34 P6 P12 P37 P38 R12 R29 R30 T1 T2 T3 T4 T5 T7 T8 T9 T10 T11 T12 T13 T14 T33 T34 U6 U37
CPU_VCCGTSENSE_N CPU_VCCIOSENSE_N
CPU_VCCSASENSE_N CPU_VCCSENSE_N
1
R0961
100
5% 1/20W MF 201
2
OUT
OUT OUT OUT
1
R0963
100
5% 1/20W MF 201
2
1
R0965
100
5% 1/20W MF 201
2
1
R0966
100
5% 1/20W MF 201
2
BOM_COST_GROUP=CPU & CHIPSET
69 8
78 8
69 8
69 8
D
C
B
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
CPU Ground
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
9 OF 200
SHEET
9 OF 135
8
67
35 4
2
1
Vinafix.com
678
3 245
1
D
PPVCC_S0_CPU
117 126
CPU VCORE Decoupling
Intel recommendation: 5x 220uF ESR 5m ohms ESL 1.9nH each,4x 47uF 0805 8x22uF 0603, 28x 10uF 0402, 3x 10uF 0402, 69x 1uF 0201 Board Edge: 2x 220uF, 4x 47uF rest on the back side Apple Implementation:
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
C1000
1
1UF
20% 4V
2
CERM-X6S 0201
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
1
C1023
1UF
20%
2
4V CERM-X6S 0201
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
C1001
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1024
1UF
20%
2
4V CERM-X6S 0201
C1002
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1025
1UF
20%
2
4V CERM-X6S 0201
C1003
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1026
1UF
20%
2
4V CERM-X6S 0201
C1004
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1027
1UF
20%
2
4V CERM-X6S 0201
C1005
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1028
1UF
20%
2
4V CERM-X6S 0201
C1006
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1029
1UF
20%
2
4V CERM-X6S 0201
C1007
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1030
1UF
20%
2
4V CERM-X6S 0201
Vcc CPU Core Decoupling from 20140905 BOM
C1008
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1031
1UF
20%
2
4V CERM-X6S 0201
C1009
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1032
1UF
20%
2
4V CERM-X6S 0201
C1010
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1033
1UF
20%
2
4V CERM-X6S 0201
C1011
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1034
1UF
20%
2
4V CERM-X6S 0201
C1012
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1035
1UF
20%
2
4V CERM-X6S 0201
C1013
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1036
1UF
20%
2
4V CERM-X6S 0201
C1014
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1037
1UF
20%
2
4V CERM-X6S 0201
C1015
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1038
1UF
20%
2
4V CERM-X6S 0201
C1016
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1039
1UF
20%
2
4V CERM-X6S 0201
C1017
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1040
1UF
20%
2
4V CERM-X6S 0201
C1018
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1041
1UF
20%
2
4V CERM-X6S 0201
C1019
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1042
1UF
20%
2
4V CERM-X6S 0201
C1020
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1043
1UF
20%
2
4V CERM-X6S 0201
C1021
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1044
1UF
20%
2
4V CERM-X6S 0201
C1022
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1045
1UF
20%
2
4V CERM-X6S 0201
D
C
1
C1046
1UF
20%
2
4V CERM-X6S 0201
1
C10A0
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1047
1UF
20%
2
4V CERM-X6S 0201
1
C10A3
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
1
C10A4
20UF
20%
2
2.5V X6S-CERM 0402-1
C10D1
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C1048
1UF
20% 4V CERM-X6S 0201
1
2
1
2
1
C1049
2
C10Z4
20UF
20%
2.5V X6S-CERM 0402-1
C10D2
20UF
20%
2.5V X6S-CERM 0402-1
1UF
20% 4V CERM-X6S 0201
1
C10A6
2
1
2
1
2
20UF
20%
2.5V X6S-CERM 0402-1
C10D3
20UF
20%
2.5V X6S-CERM 0402-1
C1050
1UF
20% 4V CERM-X6S 0201
C10A7
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C10D4
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1051
1UF
20%
2
4V CERM-X6S 0201
1
C1052
1UF
20%
2
4V CERM-X6S 0201
1
C1053
1UF
20%
2
4V CERM-X6S 0201
Place near inductors on bottom side.
1
C10A8
20UF
20%
2
2.5V X6S-CERM 0402-1
C10D5
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C10ZB
20UF
20%
2
2.5V X6S-CERM 0402-1
C10D6
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C10B0
20UF
20%
2
2.5V X6S-CERM 0402-1
C10E2
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
1
C1054
1UF
20%
2
4V CERM-X6S 0201
C10B1
20UF
20%
2.5V X6S-CERM 0402-1
C10E3
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C10B4
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
1
C1055
1UF
20%
2
4V CERM-X6S 0201
C10C0
1
2
C10N1
12PF
5% 25V NP0-C0G 0201
20UF
20%
2.5V X6S-CERM 0402-1
C10N2
1
2
1
C1056
1UF
20%
2
4V CERM-X6S 0201
12PF
5% 25V NP0-C0G 0201
C10C1
20UF
1
20%
2.5V X6S-CERM
2
0402-1
1
2
1
C1057
1UF
20%
2
4V CERM-X6S 0201
1
2
C10N3
12PF
5% 25V NP0-C0G 0201
C10C4
20UF
20%
2.5V X6S-CERM 0402-1
C10N4
1
12PF
5%
2
25V NP0-C0G 0201
1
C1058
1UF
20%
2
4V CERM-X6S 0201
1
C10C5
20UF
20%
2
2.5V X6S-CERM 0402-1
C10N5
1
12PF
5%
2
25V NP0-C0G 0201
1
C1059
2
1
C10C6
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
1
C1060
1UF
20% 4V CERM-X6S 0201
1
2
C10C7
20UF
20%
2.5V X6S-CERM 0402-1
1UF
20%
2
4V CERM-X6S 0201
Noise Floor caps
C10N6
12PF
5% 25V NP0-C0G 0201
C10N7
1
12PF
5%
2
25V NP0-C0G 0201
1
C1061
1UF
20%
2
4V CERM-X6S 0201
1
C1062
1UF
20%
2
4V CERM-X6S 0201
C
B
117 124 125
PP1V2_S3_CPUDDR
CRITICAL
1
C1069
220UF
20% 2V ELEC
2
SM
1
C10F0
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
Place on bottom side of U0500.
Place on bottom side of U0500.
Place on bottom side of U0500
Place on bottom side of U0500.
Place on bottom side of U0500
Place on bottom side of U0500
1
C10F1
2
CRITICAL
C1068
220UF
20% 2V ELEC SM
20UF
20%
2.5V X6S-CERM 0402-1
1
C10F2
20UF
20%
2
2.5V X6S-CERM 0402-1
CRITICAL
1
C1070
220UF
20% 2V
2
ELEC SM
1
C10F3
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C10F4
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C10F5
20UF
20%
2
2.5V X6S-CERM 0402-1
CRITICAL
1
C1072
220UF
20% 2V
2
ELEC SM
C10F6
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CRITICAL
1
C1073
220UF
20% 2V
2
ELEC SM
C10F7
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C10F8
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C10F9
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C10G0
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
B
C1080
1
20UF
20%
2
2.5V X6S-CERM 0402-1
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
1
C1090
20UF
20%
2
2.5V X6S-CERM 0402-1
C1081
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1091
20UF
20%
2
2.5V X6S-CERM 0402-1
C1082
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1092
20UF
20%
2
2.5V X6S-CERM 0402-1
C1083
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1093
20UF
20%
2
2.5V X6S-CERM 0402-1
C1084
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1094
20UF
20%
2
2.5V X6S-CERM 0402-1
C1085
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1095
20UF
20%
2
2.5V X6S-CERM 0402-1
CPU VDDQ Decoupling
Intel recommendation: 10x 10uF 0402, 4x 22uF 0602 Apple Implementation:
CRITICAL
1
C1096
220UF
20% 2V
2
ELEC SM
CPU VCCIO Decoupling
Intel recommendation: 3x 10uF 0402 (opposite CPU) Apple Implementation:
Place near U0500 on bottom side
A
5 8 117 124
PPVCCIO_S0_CPU
NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)
8
67
C1086
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C1087
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C1088
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C1089
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C108A
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C108B
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C108C
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
BOM_COST_GROUP=CPU & CHIPSET
35 4
C108D
20UF
20%
2.5V X6S-CERM 0402-1
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
CPU Decoupling 1
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
10 OF 200
SHEET
10 OF 135
1
A
Vinafix.com
678
3 245
1
D
PPVCCGT_S0_CPU
117 124 126
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
1
2
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
1
2
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
C1100
1UF
20% 4V CERM-X6S 0201
C1124
1UF
20% 4V CERM-X6S 0201
C1101
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1125
1UF
20%
2
4V CERM-X6S 0201
CPU VGTSlice Decoupling
Vcc GT Slice Core Decoupling from 20140905 BOM
Intel recommendation: 7x 220uF, 6x 47uF 0805, 6x 22uF 0603, 35x 10uF 0402, 68 1uF 0201 Apple Implementation:
C1102
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1126
1UF
20%
2
4V CERM-X6S 0201
C1103
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1127
1UF
20%
2
4V CERM-X6S 0201
C1104
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1128
1UF
20%
2
4V CERM-X6S 0201
C1105
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1129
1UF
20%
2
4V CERM-X6S 0201
C1106
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1130
1UF
20%
2
4V CERM-X6S 0201
C1107
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1131
1UF
20%
2
4V CERM-X6S 0201
C1108
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1132
1UF
20%
2
4V CERM-X6S 0201
C1109
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1133
1UF
20%
2
4V CERM-X6S 0201
Board Edge: 4x220uF, 7x 47uF rest on back side
C1110
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1134
1UF
20%
2
4V CERM-X6S 0201
C1111
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1135
1UF
20%
2
4V CERM-X6S 0201
C1112
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1136
1UF
20%
2
4V CERM-X6S 0201
C1113
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1137
1UF
20%
2
4V CERM-X6S 0201
C1114
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1138
1UF
20%
2
4V CERM-X6S 0201
C1115
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1139
1UF
20%
2
4V CERM-X6S 0201
C1116
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1140
1UF
20%
2
4V CERM-X6S 0201
C1117
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1141
1UF
20%
2
4V CERM-X6S 0201
C1118
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1142
1UF
20%
2
4V CERM-X6S 0201
C1119
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1143
1UF
20%
2
4V CERM-X6S 0201
C1120
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1144
1UF
20%
2
4V CERM-X6S 0201
C1121
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1145
1UF
20%
2
4V CERM-X6S 0201
C1122
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1146
1UF
20%
2
4V CERM-X6S 0201
C1123
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1147
1UF
20%
2
4V CERM-X6S 0201
D
C
1
C1148
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A0
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11F0
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1149
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A1
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11F1
1
20UF
20%
2
2.5V X6S-CERM 0402-1
NOSTUFF
C11A2
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
2
1
C1150
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A3
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11F2
20UF
20%
2.5V X6S-CERM 0402-1
1
C1151
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A4
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11F3
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1152
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A5
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11F4
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
NOSTUFF
C11A6
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11F5
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C1153
1UF
20% 4V CERM-X6S 0201
C11A7
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
2
1
C1154
2
NOSTUFF
C11F6
20UF
20%
2.5V X6S-CERM 0402-1
1UF
20% 4V CERM-X6S 0201
NOSTUFF
C11A8
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11F7
1
2
1
2
20UF
20%
2.5V X6S-CERM 0402-1
1
C1155
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A9
20UF
20%
2.5V X6S-CERM 0402-1
NOSTUFF
C11B0
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11E0
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1156
1UF
20%
2
4V CERM-X6S 0201
1
2
C11B1
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11E1
20UF
20%
2.5V X6S-CERM 0402-1
1
C1157
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11B2
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11E2
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1158
1UF
20%
2
4V CERM-X6S 0201
C11B3
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11E3
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1159
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11B4
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11E4
1
2
1
2
20UF
20%
2.5V X6S-CERM 0402-1
1
C1160
2
NOSTUFF
C11B5
20UF
20%
2.5V X6S-CERM 0402-1
NOSTUFF
C11E5
1
2
1UF
20% 4V CERM-X6S 0201
NOSTUFF
C11B6
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
20UF
20%
2.5V X6S-CERM 0402-1
1
C1161
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11B7
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C1162
1UF
20%
2
4V CERM-X6S 0201
C11B8
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
2
C11B9
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C1163
1UF
20% 4V CERM-X6S 0201
C11C0
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C1164
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11C1
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C1165
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11C2
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C1166
2
NOSTUFF
C11C3
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1UF
20% 4V CERM-X6S 0201
1
2
1
2
C11C4
20UF
20%
2.5V X6S-CERM 0402-1
C1167
1UF
20% 4V CERM-X6S 0201
C11C5
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11C6
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11C7
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11D4
1
2
1
2
20UF
20%
2.5V X6S-CERM 0402-1
NOSTUFF
C11C8
20UF
20%
2.5V X6S-CERM 0402-1
NOSTUFF
C11D3
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C11C9
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
2
C11D0
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11D2
20UF
20%
2.5V X6S-CERM 0402-1
NOSTUFF
C11D1
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C
CRITICAL
1
C1168
220UF
20% 2V
2
ELEC SM
CRITICAL
1
C1170
220UF
20% 2V
2
ELEC SM
CRITICAL
1
C1171
220UF
20% 2V
2
ELEC SM
CRITICAL
1
C1172
220UF
20% 2V
2
ELEC SM
B
PPVCCSA_S0_CPU
117
CRITICAL
1
C11K9
220UF
20% 2V
2
ELEC SM
Place on bottom side of U0500
Place on bottom side of U100.
Place on bottom side of U0500
1
C11H0
1UF
20%
2
4V CERM-X6S 0201
1
C11H1
1UF
20%
2
4V CERM-X6S 0201
1
C11H2
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
1
C11I0
20UF
20%
2
2.5V X6S-CERM 0402-1
NOSTUFF
1
C11I1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C11I2
20UF
20%
2
2.5V X6S-CERM 0402-1
NOSTUFF
1
C11I3
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C11I4
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C11I5
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C11I6
20UF
20%
2
2.5V X6S-CERM 0402-1
NOSTUFF
1
C11I7
20UF
20%
2
2.5V X6S-CERM 0402-1
PP1V05_S0SW
6 8 117
Place near U0500 on bottom side
Place near U0500 on bottom side
1
C11L1
1UF
20%
2
4V CERM-X6S 0201
1
C11L2
1UF
20%
2
4V CERM-X6S 0201
CPU VCCPLL and VCCST DecouplingCPU VCCSTG Decoupling
8 117
PP1V05_S3
1
C11M1
1UF
20%
2
4V CERM-X6S 0201
6 8 46
PP1V05_S3
117
1
C11M2
1UF
20%
2
4V CERM-X6S 0201
B
A
8
NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)
Place near U0500 on bottom side
Place near U0500 on bottom side
SYNC_MASTER=ANDY SYNC_DATE=01/17/2019
PAGE TITLE
A
CPU Decoupling 2
DRAWING NUMBER
CPU VCCSA Decoupling
Apple Inc.
Intel recommendation: 2x 220uF, 1x 47uF 0805. 1x 22uF. 7x 10uF 0402, 3x 1uF 0201_
2x 220uF, 1x 22uF on board edge, everything else on back side
Apple Implementation:
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-04492
REVISION
2.15.0
BRANCH
PAGE
11 OF 200
SHEET
11 OF 135
1
SIZE
D
Vinafix.com
678
3 245
1
OMIT_TABLE
D
121 46 18 12
121 46
121 46
121 46 35 20
121 114 46 34 18 12
80 77 12
135 121 77 39 12
IN
IN
IN
OUT
IN
IN
OUT
12
12
PM_SYSRST_L PM_PCH_SYS_PWROK PM_PCH_PWROK
PLT_RST_L PM_RSMRST_L
PM_PWRBTN_L SPIROM_USE_MLB PCH_BATLOW_L PM_SLP_S0_L
CNL-PCH-H-USFF-QNYP
SYSTEM POWER MANAGEMENT
(IPU)
AL17
AK16
SYS_RESET* SYS_PWROK PCH_PWROK
H23
GPP_B13/PLTRST*
U25
RSMRST*
J24
GPD3/PWRBTN*
K22 K20
GPD1/ACPRESENT
L22
GPD0/BATLOW*
L24
GPP_B12/SLP_S0*
U23
U1200
961822
BGA
SYM 4 OF 11
GPP_A14/SUS_STAT*/ESPI_RESET*
(IPU-RSMRST#)
DRAM_RESET*
(OD)
(IPD-DeepSx)
DSW_PWROK
GPD10/SLP_S5*
GPD5/SLP_S4* GPD4/SLP_S3*
WAKE*
SLP_SUS*
K25 H25 K23
P23
H22 J21
J25
PCH_DRAM_RESET_L PM_RSMRST_L PCIE_WAKE_L
ESPI_RESET_L
PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L
TP_PCH_SLP_SUS_L
12
OUT
OUT
OUT
OUT
OUT
26
121 114 46 34 18 12
121 120 39
121 12
121 12
135 121 107 27 14 12
120 12
PCH_STRP_GPD7
12
SPIROM_USE_MLB
12
PCIE_WAKE_L
12
PCH_BATLOW_L
12
PCH_ESPI_ALERT0_L PCH_GPP_A0_PU
12
PP3V3_S5
16 17 80
13 15 16 19 20 52 80
PP1V8_S5 PP1V8_S5
16 80
PP3V3_S5
16 17 80
R1204 R1205
R1206 R1208
R1209 R1210
100K 100K
100K
10K
100K 100K
1 2
1 2
1 2 1 2
1 2 1 2
1/20W5% MF 201
NOSTUFF
5% MF1/20W 201
5%
5% 201
1/20W MF
1/20W5% MF 201
201MF1/20W
2011/20W5% MF
D
C
120 77
IN
PMU_CLK32K_PCH
PP3V0_G3H_RTC
1
R1201
1M
5% 1/20W MF 201
2
PCH_INTRUDER_L
R1220
1 2
16 17 80
12
100K
1/20W
201
MF 5%
1
R1221
127K
1% 1/20W MF 201
2
123 120 41
123 120 41
120 36
120 36
123 119
123 119
OUT OUT
OUT OUT
OUT OUT
PCH_CLK32K_RTCX1
20
121 77
OUT
12
IN
NC_PCH_CLK32K_RTCX2 PCH_INTRUDER_L
PCH_RTC_RESET_L
PCIE_CLK100M_SOC_N PCIE_CLK100M_SOC_P
PCH_PCIE_CLK100M_WLAN_N PCH_PCIE_CLK100M_WLAN_P
EG_PEG_CLK100M_N EG_PEG_CLK100M_P
G24 G22
H20 F25 F23
AR10 AN10
AP9
AM9
AR8 AN8
RTCX1 RTCX2
INTRUDER* SRTCRST* RTCRST*
CLKOUT_PCIE_N0 CLKOUT_PCIE_P0
CLKOUT_PCIE_N1 CLKOUT_PCIE_P1
CLKOUT_PCIE_N2 CLKOUT_PCIE_P2
GPP_A0/RCIN*/ESPI_ALERT1*
GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1
RTC
ESPI/LPC
GPP_A7/PIRQA*/ESPI_ALERT0*
GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME*/ESPI_CS0*
GPP_A6/SERIRQ/ESPI_CS1*
OMIT_TABLE
U1200
CNL-PCH-H-USFF-QNYP
961822
BGA
SYM 2 OF 11
GPD7
XTAL_IN
XTAL_OUT
CLKIN_XTAL
R24 N20 N21 M20 M22 M25 N25 N24
J20
AN3 AN1
AR4
PCH_GPP_A0_PU
ESPI_IO<0> ESPI_IO<1> ESPI_IO<2> ESPI_IO<3> ESPI_CS_L PCH_SOC_SYNC
PCH_ESPI_ALERT0_L
PCH_STRP_GPD7
PCH_CLK24M_XTALIN PCH_CLK24M_XTALOUT
PCH_CLKIN_XTAL
12
OUT
120 41 12
12
BI BI BI BI BI
120 12
120 39
120 39
120 39
120 39
120 39
38 12
121 46 18 12
NEED TO CHANGE PER INTEL SPEC
SOC_CLKREQ_L
DEBUG_CLKREQ_L
12
PM_SYSRST_L
R1211 R1213
R1214
47K
47K
3.0K
1 2
1 2
1 2
201
201
NOSTUFF
5% MF 2011/20W
C
CRITICAL
C1250
12
1
R1251
200K
1% 1/20W MF 201
2
R1250
1 2
1/20W
0201
5% MF
Y1250
24MHZ-10PPM-8PF-30OHM
13
2.5X2.0-SM
24
0
120
PCH_CLK24M_XTALOUT_R
CRITICAL
10PF
1 2
5% 50V C0G
0201
CRITICAL
C1251
10PF
1 2
5% 50V C0G
0201
Ce1=Ce2=2*(C_L - C_S - C_I) = 2*(8-0.7)=14.6pF C_L = Load Capacitance = 8pF C_S = Trace Capacitace + XTAL Pad Capacitance = 0.7pF C_I= PCH Pin Capacitance = 0
B
123 120
123 120
123 120 27
123 120 27
123 120 107
123 120 107
OUT OUT
OUT OUT
OUT OUT
PCIE_CLK100M_DEBUG_N PCIE_CLK100M_DEBUG_P
PCIE_CLK100M_TBT_X_N PCIE_CLK100M_TBT_X_P
PCIE_CLK100M_TBT_T_N PCIE_CLK100M_TBT_T_P
NC NC
NC NC
CLKOUT_PCIE_N3
AM6
CLKOUT_PCIE_P3
AK6
CLKOUT_PCIE_N4
AM8
CLKOUT_PCIE_P4
AK8
CLKOUT_PCIE_N5
AL7
CLKOUT_PCIE_P5
AJ7
CLKOUT_PCIE_N6
AK1
CLKOUT_PCIE_P6
AK3
CLKOUT_PCIE_N7
AJ5
CLKOUT_PCIE_P7
AK4
CLOCK SIGNALS
GPP_A9/CLKOUT_LPC0
CLKOUT_CPUBCLK_N CLKOUT_CPUBCLK_P
CLKOUT_CPUNSSC_N CLKOUT_CPUNSSC_P
XCLK_BIASREF
/ESPI_CLK
AP2
M23
AR7 AP7
AR6 AN6
PCH_XCLK_BIASREF
ESPI_CLK60M_PCH
CPU_CLK100M_BCLK_N CPU_CLK100M_BCLK_P
CPU_CLK24M_NSSC_CLK_N CPU_CLK24M_NSSC_CLK_P
OUT
12
PP1V8_S5
36 77 80
120 39
135 121 77 39 12
PM_SLP_S0_L
R1236
100K
1 2
NOSTUFF
5% 201MF1/20W
B
OUT OUT
OUT OUT
121 12
121 12
135 121 107 27 14 12
135 121 77 39 12
120 6
120 6
120 6
120 6
PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L PCH_SOC_SYNC
38 12
PCH_CLKIN_XTAL
12
PCH_XCLK_BIASREF
12
R1230 R1231 R1232 R1233 R1215
R1235 R1234
PLACE_NEAR=U1200.AP2:2.54mm
100K 100K 100K 100K 100K
10K
60.4
1 2 1 2 1 2 1 2
1 2
1 2 1 2
5% 1/20W MF
MF5% 1/20W
1/20W MF 2015%
5% 1/20W MF
MF1/20W5% 201
MF1/20W 2011%
201 2011/20W MF5% 201
201
A
PP3V3_S5
R1207
10K
1 2
29 80
201
PM_PWRBTN_L
5% MF1/20W
12 77 80
PCI EXPRESS
CLOCKS & CONTROL
CLKOUT_CPUPCIBCLK_N
CLKOUT_CPUPCIBCLK_P
GPP_B5/SRCCLKREQ0* GPP_B6/SRCCLKREQ1* GPP_B7/SRCCLKREQ2* GPP_B8/SRCCLKREQ3* GPP_B9/SRCCLKREQ4*
GPP_B10/SRCCLKREQ5*
GPP_H0/SRCCLKREQ6* GPP_H1/SRCCLKREQ7*
AP5 AM5
W22 AB22 U20 V20 W20 V21
D12 A10
NC NC
CPU_CLK100M_PCIBCLK_N CPU_CLK100M_PCIBCLK_P
SOC_CLKREQ_L PCH_WLAN_CLKREQ_L PCH_GPU_CLKREQ_L DEBUG_CLKREQ_L
TBT_X_CLKREQ_L TBT_T_CLKREQ_L
12
OUT OUT
BI BI BI
IN IN
120 6
120 6
120 41 12
120 19
120 19
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
120 27 19
120 107 19
PCH RTC/CLK/ESPI/PM
DRAWING NUMBER
SIZE
051-04492
Apple Inc.
REVISION
A
D
2.15.0
BRANCH
PAGE
12 OF 200
SHEET
12 OF 135
BOM_COST_GROUP=CPU & CHIPSET
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
67
35 4
2
1
Vinafix.com
D
C
Intel Spec: 1k Pull-up for IO2 and IO3
PP1V8_S5
PPVCCSPI_PRIM_PCH
R1330 R1331 R1332
R1318 R1303
R1317
100K 100K 100K
100K
1 2
1 2
1 2
1 2
1K
1 2
1K
1 2
VCCSPI:3V3
VCCSPI:3V3
5% 1/20W
VCCSPI:3V3
NOSTUFF
5% 201MF1/20W
5% 1/20W 201MF
5% 2011/20W MF
1/20W
12 15 16 19 20 52 80
16
201MF5% 1/20W
MF 201
201MF5%
PCH_STRP_BSSB_SEL_GPIO
SPI_MOSI_R SPI_IO<2> SPI_IO<3>
PCH_STRP_NO_REBOOT
13
13
13
PCH_WLAN_DEV_WAKE
678
3 245
1
OMIT_TABLE
U1200
CNL-PCH-H-USFF-QNYP
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
18 13
18 13
OUT OUT
OUT OUT
OUT OUT
OUT OUT
IN IN
IN IN
IN IN
IN IN
DMI_S2N_N<0> DMI_S2N_P<0>
DMI_S2N_N<1> DMI_S2N_P<1>
DMI_S2N_N<2> DMI_S2N_P<2>
DMI_S2N_N<3> DMI_S2N_P<3>
DMI_N2S_N<0> DMI_N2S_P<0>
DMI_N2S_N<1> DMI_N2S_P<1>
DMI_N2S_N<2> DMI_N2S_P<2>
DMI_N2S_N<3> DMI_N2S_P<3>
H3 H1
J2 J1
K3 K1
L4 L2
C3
B2
C1
E1 E2
F1 F4
F3
DMI0_TXN DMI0_TXP
DMI1_TXN DMI1_TXP
DMI2_TXN DMI2_TXP
DMI3_TXN DMI3_TXP
DMI0_RXN DMI0_RXP
DMI1_RXN DMI1_RXP
DMI2_RXN DMI2_RXP
DMI3_RXN DMI3_RXP
DMI
CNL-PCH-H-USFF-QNYP
A24
AB1
AJ2 AJ4 AJ8
G2 G4 M1 M3
V1 V2
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
NC NC NC NC NC NC NC
36 13
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
NC NC NC NC NC NC NC NC
AJ10
AK10
AM10
AR24
961822
BGA
SYM 5 OF 11
(IPD)
CPU/MISC
GPP_B23/SML1ALERT*/PCHHOT*
CPUPWRGD
THRMTRIP*
GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 GPP_E3/CPU_GP0 GPP_E7/CPU_GP1
CPU_TRST*
PLTRST_CPU*
TRIGGER_IN
TRIGGER_OUT
PM_DOWN
OMIT_TABLE
U1200
961822
BGA
SYM 1 OF 11
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD
(IPD)
RSVD & TP PINS
AUDIO
GPP_D5/I2S2_SFRM/CNV_RF_RESET*
GPP_D6/I2S2_TXD/MODEM_CLKREQ
HDA_SDO/I2S0_TXD
HDA_RST*/I2S1_SCLK
HDACPU_SCLK
HDACPU_SDI
HDACPU_SDO
PECI
PRDY*
PREQ*
PM_SYNC
AC24 AD23 AD25
AD22 AC25 AD20 AJ13
AK13 AM13
L21 AJ21
AR16 AP12 AR12 V25
V24 B12 C13 U22
AR17 AM14 AJ16 AP14 AR13
AN13 AL12
AJ12
NC NC NC
PCH_PROCPWRGD PCH_PM_THRMTRIP_L_R PCH_PECI PCH_WLANBT_PERST_L
PCH_WLAN_DEV_WAKE XDP_PCH_OBSDATA_A2 XDP_PCH_OBSDATA_B2 PCH_STRP_BSSB_SEL_GPIO
XDP_CPU_TRST_L CPU_RESET_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L CPU_PCH_TRIGGER
PCH_CPU_TRIGGER_R CPU_PCH_PM_DOWN
PM_SYNC_R
PLACE_NEAR=U1200.AJ12:10mm
TP_HDA_SDI1 TP_HDA_SDO TP_HDA_RST PCH_DISPA_BCLK_R
PCH_DISPA_SDO_R
NC NC
TP-P5
TP-P5
TP-P5
PLACE_NEAR=U1200.AN13:5mm
1 2
R1319
1
TP
TP1306
1
TP
TP1307
1
TP
TP1308
R1320
1/20W MF 2015%
R1321
R1308 R1309 R1315
R1314
5% 201MF1/20W
1 2
1 2
PM_SYNC
33
33
33
MF 2015% 1/20W
0
1 2
OUT
36 13
OUT OUT
13
OUT
OUT
OUT
OUT
IN
1 2
1 2 1 2
37 36 20
WIFI controller wakes up by PCIE in-band signaling instead of PCH_WLAN_DEV_WAKE
18
18
BSS GPIO 0=BSSB CLK/DI on USB-SS
123 18 6
6
123 18 6
123 18 6
5
620
13
PCH_DISPA_BCLK PCH_DISPA_SDI PCH_DISPA_SDO
5%
1/20W
MF
1/20W5%
5%MF1/20W
33
1/20W 201MF5%
6
OUT
0201
201MF
201
CPU_PWRGD PCH_PMTHRMTRIP_L CPU_PECI
PCH_CPU_TRIGGER
NOSTUFF
1
R1326
150K
5% 1/20W MF 201
2
20
OUT
20
IN
20
OUT
OUT
IN
OUT
121 6
46
IN
BI
46 6
D
5
5
C
B
3117S0134
RES,MF,5%,1/20W,201,75K VCCSPI:1V8
R1330,R1331,R1332
TP1300 TP1301
123 18
123 18
123 18
123 18
123 18
123 18
TP TP
IN
IN
IN
OUT
IN
IN
1 1
TP_PCH_TP1_F22
TP-P5
TP_PCH_TP3_B24
TP-P5
PCH_ITP_PMODE XDP_PCH_TCK XDP_PCH_TDI XDP_PCH_TDO XDP_PCH_TMS XDP_PCH_JTAGX
(IPD)
(IPU)
(Undriven)
(IPU)
F22 B24
AN16 AP17 AR18
AM16
AL14
AN18
TP1
TP2
ITP_PMODE PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS
PCH_JTAGX
JTAG
B
OMIT_TABLE
A
18 13
18 13
13
CNL-PCH-H-USFF-QNYP
C23 E25 C25
D21 A20 E22 B21
SPI0_CLK SPI0_CS0* SPI0_CS1*
SPI0_MOSI SPI0_MISO SPI0_IO2 SPI0_IO3
(IPU 20K)
(IPU 20K)
(IPU 20K)
NC NC NC
BI
BI
BI
SPI_MOSI_R
NC
SPI_IO<2> SPI_IO<3>
U1200
961822
BGA
SYM 3 OF 11
SPI
GSPI
(IPD)
(IPD)
GPP_B18/GSPI0_MOSI
GPP_B22/GSPI1_MOSI
P20
P22
PCH_STRP_NO_REBOOT
TP_PCH_STRP_BOOT_SPI_L
13
No Rebort: 0=Disable; 1=Enable
BootBIOS Strap: 0=SPI; 1=LPC
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
8
PCH DMI/JTAG/SPI/HDA
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
13 OF 200
SHEET
13 OF 135
1
SIZE
D
Vinafix.com
678
3 245
1
D
121 29
121 29
29
29
121
121
121
121
BI BI
BI BI
IN IN
OUT OUT
USB3_EXTA_D2R_N USB3_EXTA_D2R_P
USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P
USB3_TEST_D2R_N USB3_TEST_D2R_P
USB3_TEST_R2D_N USB3_TEST_R2D_P
AA4 AA2
AD3
AD1
W3 W1
AC2 AC1
USB31_1_RXN USB31_1_RXP
USB31_1_TXN USB31_1_TXP
USB31_2_RXN USB31_2_RXP
USB31_2_TXN USB31_2_TXP
OMIT_TABLE
CNL-PCH-H-USFF-QNYP
U1200
961822
BGA
SYM 7 OF 11
USB2N_1 USB2P_1
USB2N_2 USB2P_2
USB2N_3 USB2P_3
USB2N_4 USB2P_4
AG1 AG2
AF1 AF3
AH1 AH3
AF4 AE5
USB_UPC_PCH_TA_N USB_UPC_PCH_TA_P
USB_UPC_PCH_TB_N USB_UPC_PCH_TB_P
USB_UPC_PCH_XA_N USB_UPC_PCH_XA_P
USB_UPC_PCH_XB_N USB_UPC_PCH_XB_P
OMIT_TABLE
BI BI
BI BI
BI BI
BI BI
121 120 110
121 120 110
121 120 111
121 120 111
120 30
120 30
120 31
120 31
120 36
120 36
120 36
120 36
121
121
121
121
IN IN
OUT OUT
IN IN
OUT OUT
PCH_PCIE_WLAN_D2R_N PCH_PCIE_WLAN_D2R_P
PCH_PCIE_WLAN_R2D_C_N PCH_PCIE_WLAN_R2D_C_P
USB3_TEST2_D2R_N USB3_TEST2_D2R_P
USB3_TEST2_R2D_N USB3_TEST2_R2D_P
NC NC
PCIE1_RXN/USB31_7_RXN
W4
PCIE1_RXP/USB31_7_RXP
W6
PCIE1_TXN/USB31_7_TXN
U1
PCIE1_TXP/USB31_7_TXP
U3
PCIE2_RXN/USB31_8_RXN
U6
PCIE2_RXP/USB31_8_RXP
V5
PCIE2_TXN/USB31_8_TXN
R2
PCIE2_TXP/USB31_8_TXP
R1
PCIE3_RXN/USB31_9_RXN
P4
PCIE3_RXP/USB31_9_RXP
R5
CNL-PCH-H-USFF-QNYP
U1200
961822
BGA
SYM 8 OF 11
PCIE/SATA/USB3
PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP
PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP
PCIE19_RXN/SATA6_RXN
PCIE19_RXP/SATA6_RXP
F6 D6
B4 A4
G8 G7
B5 A5
F8 D8
PCIE_SOC_D2R_N<0> PCIE_SOC_D2R_P<0>
PCIE_SOC_R2D_C_N<0> PCIE_SOC_R2D_C_P<0>
PCIE_SOC_D2R_N<1> PCIE_SOC_D2R_P<1>
PCIE_SOC_R2D_C_N<1> PCIE_SOC_R2D_C_P<1>
PCIE_SOC_D2R_N<2> PCIE_SOC_D2R_P<2>
IN IN
OUT OUT
IN IN
OUT OUT
IN IN
120 41
120 41
120 47
120 47
120 41
120 41
120 47
120 47
120 41
120 41
D
C
USB3
USB2
18
18
18
18
18
18
18
18 14
OUT OUT OUT
OUT OUT OUT OUT OUT
XDP_PCH_OBSFN_C0 XDP_PCH_OBSDATA_A0 XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_D0 XDP_PCH_OBSDATA_D1 XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TDI XDP_JTAG_ISP_TDO
NC NC
NC NC
NC NC
PCIE3_TXN/USB31_9_TXN
P3
PCIE3_TXP/USB31_9_TXP
P1
PCIE4_RXN/USB31_10_RXN
P6
PCIE4_RXP/USB31_10_RXP
N5
PCIE4_TXN/USB31_10_TXN
N2
PCIE4_TXP/USB31_10_TXP
N1
GPP_E0/SATAXPCIE0/SATAGP0
D16
GPP_E1/SATAXPCIE1/SATAGP1
F16
GPP_E2/SATAXPCIE2/SATAGP2
G14
GPP_F0/SATAXPCIE3/SATAGP3
C20
GPP_F1/SATAXPCIE4/SATAGP4
A19
GPP_F2/SATAXPCIE5/SATAGP5
B19
GPP_F3/SATAXPCIE6/SATAGP6
A22
GPP_F4/SATAXPCIE7/SATAGP7
G18
PCIE19_TXN/SATA6_TXN PCIE19_TXP/SATA6_TXP
PCIE20_RXN/SATA7_RXN
PCIE20_RXP/SATA7_RXP
PCIE20_TXN/SATA7_TXN PCIE20_TXP/SATA7_TXP
GPP_E4/SATA_DEVSLP0 GPP_E5/SATA_DEVSLP1 GPP_E6/SATA_DEVSLP2
GPP_F5/SATA_DEVSLP3 GPP_F6/SATA_DEVSLP4 GPP_F7/SATA_DEVSLP5 GPP_F8/SATA_DEVSLP6 GPP_F9/SATA_DEVSLP7
C6 A6
G9 E9
B7 A7
E14 F13 D13
F20 G19 D20 E19 F18
PCIE_SOC_R2D_C_N<2> PCIE_SOC_R2D_C_P<2>
PCIE_SOC_D2R_N<3> PCIE_SOC_D2R_P<3>
PCIE_SOC_R2D_C_N<3> PCIE_SOC_R2D_C_P<3>
XDP_PCH_OBSDATA_A3 XDP_PCH_OBSDATA_B0 XDP_PCH_OBSDATA_B1
TBT_X_PCI_RESET_L TBT_T_PCI_RESET_L TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN TBT_T_CIO_PWR_EN
OUT OUT OUT
OUT OUT OUT OUT OUT
OUT OUT
IN IN
OUT OUT
18
18
18
120 47
120 47
120 41
120 41
120 47
120 47
33 27 20
113 107 20
33 31 30 27 14
33 31 30 27 14
113 111 110 107 14
C
B
GPP_E9/USB2_OC0* GPP_E10/USB2_OC1* GPP_E11/USB2_OC2* GPP_E12/USB2_OC3*
GPP_F15/USB2_OC4* GPP_F16/USB2_OC5*
USB2_COMP
USB2_ID
USB2_VBUSSENSE
E12 G10 D10 F10
B17 D17
AB6 AE4 AE2
XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L
NC NC
USB2_COMP USB2_ID USB2_VBUSSENSE
18 14
18 14
18 14
18 14
PLACE_NEAR=U1200.AB6:10.0mm
1
R1410
1K
5% 1/20W MF 201
2
1
R1411
1K
5% 1/20W MF 201
2
1
R1470
113
1% 1/20W MF 201
2
113 111 110 107 14
33 27 14
113 107 14
1
R1400
100
1% 1/20W MF 201
2
OUT OUT OUT
TBT_T_USB_PWR_EN TBT_X_PLUG_EVENT_L TBT_T_PLUG_EVENT_L
PCH_PCIE_RCOMPP PCH_PCIE_RCOMPN
NC
GPP_F10/SATA_SCLOCK
D18
GPP_F11/SATA_SLOAD
C18
GPP_F12/SATA_SDATAOUT1
G16
GPP_F13/SATA_SDATAOUT0
E17
PCIE_RCOMPP
L5
PCIE_RCOMPN
K4
GPP_E8/SATALED*
G13
XDP_PCH_OBSDATA_B3
OUT
18
B
A
PM_SLP_S3_L
PM_SLP_S3_L
R1491 R1492 R1493 R1494
R1446 R1445
R1447 R1460
R1461 R1420
R1421 R1448
R1449
100K 100K 100K 100K
100K 100K
10K 10K
10K 10K
10K
100K 100K
PP3V3_S5
1 2
1 2
1 2
1 2
1 2 1 2
1 2
1 2 1 2
1 2 1 2
1 2
1 2
16 80
1/20W MF5%
5% MF1/20W
5% 1/20W MF
1/20W 201MF5%
MF 2015% 1/20W
MF5% 2011/20W MF 2011/20W5%
5% MF 2011/20W
1/20W5% 201MF
135 121 107 27 14 12
135 121 107 27 14 12
201
MF5% 1/20W
201
201
201
TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN TBT_T_CIO_PWR_EN TBT_T_USB_PWR_EN
TBT_T_PLUG_EVENT_L TBT_X_PLUG_EVENT_L
201MF1/20W5%
XDP_JTAG_ISP_TDO XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
2015% MF1/20W
XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L
33 31 30 27 14
33 31 30 27 14
113 111 110 107 14
113 111 110 107 14
113 107 14
33 27 14
18 14
18 14
18 14
18 14
18 14
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
PCH PCI-E/USB
MF1/20W 2015%
JTAG_ISP_TDI
JTAG_ISP_TCK
123 107 27 18
123 107 27 18
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
14 OF 200
SHEET
14 OF 135
BOM_COST_GROUP=CPU & CHIPSET
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
8
67
35 4
2
1
Vinafix.com
678
3 245
1
OMIT_TABLE
D
RAMCFG0:L
1
R1530
1K
5% 1/20W MF 201
2
RAMCFG1:L
1
R1531
1K
5% 1/20W MF 201
2
SPEED CONGIF4
2400MHZ
2667MHZ
1
2
R1532
1K
5% 1/20W MF
201
0
RAMCFG2:L
1
2
STORAGE
16GB
32GB
64GB
RAMCFG3:L
R1533
1K
5% 1/20W MF 201
CONGIF31CONGIF2
1
1
1
R1534
1K
5% 1/20W MF 201
2
RAMCFG4:L
VENDOR
1 1
10
0
SAMSUNG
MICRON
HYNIX
MLB_RAMCFG0 MLB_RAMCFG1
MLB_RAMCFG2 MLB_RAMCFG3
MLB_RAMCFG4
CONGIF1 CONGIF0
1
0
1
15
15
15
15
15
U1200
CNL-PCH-H-USFF-QNYP
1
0
95 15
95 15
19 15
OUT OUT
IN
EDP_IG_PANEL_PWR EDP_IG_BKLT_EN
BT_AUDIO_SYNC_LS3V3
NC
NC
NC
GPP_F14/PS_ON*
A18 A16
GPP_F19/EDP_VDDEN
C16
GPP_F20/EDP_BKLTEN
A14
GPP_F21/EDP_BKLTCTL
B14
GPP_F22/DDPF_CTRLCLK
A13
GPP_F23/DDPF_CTRLDATA
GPPF/
BACKLIGHT
J680 Display Port DDPF Disabled
GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I2/DDPD_HPD2_DISP_MISC2 GPP_I3/DDPF_HPD3_DISP_MISC3 GPP_I4/EDP_HPD/DISP_MISC4 GPP_I5/DDPB_CTRLCLK GPP_I6/DDPB_CTRLDATA GPP_I7/DDPC_CTRLCLK GPP_I8/DDPC_CTRLDATA GPP_I9/DDPD_CTRLCLK GPP_I10/DDPD_CTRLDATA GPP_I11/M2_SKT2_CFG0 GPP_I12/M2_SKT2_CFG1 GPP_I13/M2_SKT2_CFG2
GPPI/DISPLAY
PDG recommends to NC the HPD lines not being used
95 15
J680 Display Port DDPB/C/D Disabled
135 122 15
113 109 29 15
NC NC NC NC
IN
OUT
OUT
DP_INT_IG_HPD
USFF_MEM_OK
TBT_POC_RESET
NC NC NC NC NC NC
NC
AN23 AN25 AP24 AP22 AR22 AP19
AM19
AR20 AN20 AP21 AR21
AL24 AL25
AK25
961822
SYM 9 OF 11
GPPG
BGA
(IPD)
(IPD)
GPP_J0/CNV_PA_BLANKING
GPP_J1/CPU_C10_GATE*
GPP_J2 GPP_J3
GPP_J4/CNV_BRI_DT/UART0B_RTS*
GPP_J5/CNV_BRI_RSP/UART0B_RXD
GPP_J6/CNV_RGI_DT/UART0B_TXD
GPP_J7/CNV_RGI_RSP/UART0B_CTS*
GPP_J8/CNV_MFUART2_RXD
GPP_J9/CNV_MFUART2_TXD
GPP_J10
GPP_J11/A4WP_PRESENT
GPP_K20 GPP_K21
GPPJ_RCOMP_1P8
CNV_WR_CLKP CNV_WR_CLKN
CNV_WR_D0P
CNV_WR_D0N
AM18 AK18 AL19 AJ18 AJ22 AH23 AJ25 AH25 AK22 AK23 AM20 AK20
A8 C8
AJ17
AG24 AG25
AF23 AF25
SOC_SWD_MUX_SEL_PCH CPU_C10_GATE_L PCH_SWD_SOC_CLK PCH_SWD_SOC_IO PCH_STRP_XTAL_24MHZ MLB_RAMCFG2 PCH_STRP_CNV_L MLB_RAMCFG3 MLB_RAMCFG4 PCH_STRP_VCCPSPI_1V8 PCH_BT_ROM_BOOT_L NC_PCH_BT_DEV_WAKE
MLB_RAMCFG0 MLB_RAMCFG1
PCH_GPPJ_RCOMP_1P8
NC NC
NC NC
NO_TEST=1
121 15
OUT
135 79 78 76 15
GPP_J2:Unused GPP_J3:Unused
15
GPP_J4: 0=38.4MHz 1=24MHz XTAL
15
15
GPP_J6: 0=ENABLE 1=DISABLE
15
15
GPP_J9: 0=3.3V; 1=1.8V
15
36
15
15
15
D
C
PP1V8_S5
PP3V3_S5
PP3V3_S5
R1501 R1502
10K 10K
1 2 1 2
80
16 19 80
16 80
201MF5% 1/20W
5% 201
1/20W MF
JTAG_TBT_X_TMS JTAG_TBT_T_TMS
eSPI Flash Mode: 0=MAF; 1=SAF
19 15
15
PCH_STRP_SPIROM_SAF
15
PCH_STRP_GPP_H15
IN
WLAN_AUDIO_SYNC_LS3V3
GPP_H12/SML2ALERT*
A9
GPP_H15/SML3ALERT*
B9
GPP_H23/TIME_SYNC0
C10
(IPD)
/SMLINK
GPPH/I2C/INTEGRATED SENSOR
CNV_WR_D1P
CNV_WR_D1N
CNV_WT_CLKP
CNV_WT_CLKN
CNV_WT_D0P
CNV_WT_D0N
CNV_WT_D1P
CNV_WT_D1N
CNV_WT_RCOMP
AE22 AE24
AH22 AH20
AG21 AG20
AF22 AF20
AE21
NC NC
NC NC
NC NC
NC NC
NC
C
OMIT_TABLE
123 27 15
123 107 15
CNL-PCH-H-USFF-QNYP
U1200
961822
BGA
SYM 6 OF 11
B
PP1V8_S5
R1503 R1505
R1506 R1507
R1508 R1509
R1510 R1511
R1512 R1526 R1543 R1514 R1515
R1516 R1517
R1518
1K
47K 47K
47K 47K
47K 47K
1K
100K
20K
1K 100K 100K
100K
1K
1K
1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2
1 2
1 2
1 2 1 2
VCCSPI:1V8
1 2
VCCSPI:3V3
1 2
12 13 16 19 20 52 80
MF5% 1/20W
201
5% 1/20W
5% MF1/20W 5% 1/20W
5% 201MF1/20W 5%
1/20W5% 201MF
1/20W 2011%
1/20W MF 201
5%
5%
1/20W MF5%
5% 1/20W MF 201
MF 201
201MF1/20W5%
201
MF 201
MF 2011/20W
2011/20W5% MF
MF
1/20W5% MF
MF 2011/20W MF5% 2011/20W
201
201
PCH_STRP_ESPI PCH_UART_BT_D2R
PCH_UART_BT_R2D PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D
PCH_STRP_SPIROM_SAF PCH_STRP_GPP_H15
PCH_STRP_CNV_L PCH_STRP_XTAL_24MHZ PCH_SWD_SOC_CLK PCH_SWD_SOC_IO
CPU_C10_GATE_L
PCH_STRP_VCCPSPI_1V8
15
15
15
15
15
15
15
15
GPP_C0/SMBCLK
GPP_C1/SMBDATA
35 15
35 15
35 15
35 15
121 29 15
121 29 15
TP1501
135 79 78 76 15
39 20
39
TP-P5
123 27 15
123 107 15
TP
OUT IN
OUT OUT
SOC_PERST_L PCH_GCON_INT_L
1
TP_PCH_STRP_TOPBLK_SWP_L
PLACE_SIDE=BOTTOM
JTAG_TBT_X_TMS JTAG_TBT_T_TMS
NC
R22
P25
R21
AC20 AC21
AB20
GPP_A20/ISH_GP2 GPP_A21/ISH_GP3
GPP_B14/SPKR
GPP_D0/SPI1_CS*/SBK0/BK0 GPP_D1/SPI1_CLK/SBK1/BK1
GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
(IPD)
GPPA/
INTEGRATED SENSOR
GPPC/SMLINK/I2C/UART
(IPD)
(IPD)
GPP_C2/SMBALERT*
GPP_C5/SML0ALERT*
GPP_C8/UART0A_RXD
GPP_C9/UART0A_TXD
GPP_C10/UART0A_RTS*
GPP_C11/UART0A_CTS*
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
W23 W25 AA22
AB19
AA24 AA21 AA18 Y19
AB25 AB23
SMBUS_PCH_CLK SMBUS_PCH_DATA TP_PCH_STRP_TLSCONF
PCH_STRP_ESPI
PCH_UART_BT_D2R PCH_UART_BT_R2D PCH_UART_BT_RTS_L PCH_UART_BT_CTS_L
PCH_UART_DEBUG_D2R PCH_UART_DEBUG_R2D
OUT
BI
15
OUT OUT
OUT
52
IN
IN
IN
PROJ-SPECIFIC PULLUP
52
TLS: 0=Disbale; 1=Enable
GPP_C5: 0=LPC; 1=eSPI
35 15
35 15
35 15
35 15
121 29 15
121 29 15
B
A
R1537 R1536 R1522 R1523 R1524
R1542
R1527 R1528 R1529
100K
100K
100K
100K
100K
200
100K
100K
100K
1 2
1 2
1 2
1 2 1 2
1 2
1 2 1 2 1 2
1/20W MF5% 201
1/20W MF5% 201
1/20W MF 2015%
5% 1/20W MF 201
1% 1/20W 201MF
5% 1/20W MF 201
MF 2011/20W5%
USFF_MEM_OK
BT_AUDIO_SYNC_LS3V3 DP_INT_IG_HPD
TBT_POC_RESET WLAN_AUDIO_SYNC_LS3V3
201MF1/20W5%
PCH_GPPJ_RCOMP_1P8
15
EDP_IG_PANEL_PWR EDP_IG_BKLT_EN SOC_SWD_MUX_SEL_PCH
MF5% 2011/20W
135 122 15
19 15
95 15
113 109 29 15
19 15
95 15
95 15
121 15
GPPD/INTEGRATED SENSOR/UART/I2C GPPB
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
PCH GPIO/MISC/NCTF
SIZE
D
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
A
2.15.0
BRANCH
PAGE
15 OF 200
SHEET
15 OF 135
BOM_COST_GROUP=CPU & CHIPSET
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
67
35 4
2
1
Vinafix.com
D
C
B
PP1V05_PRIM
17 80 117
12 17 80
PP3V3_S5
17
PP1V05_PRIM_PCH_VCCAPLL_F
117
PP1V05_PRIM
117
PP1V05_PRIM
PP1V05_PRIM
117
PP1V05_PRIM_PCH_VCCAXTAL_F
17
AB12 AB14 AB17
AB7
AB9 AD12 AD14
AD9 AE11
AF7
H7 H9
J15 K14 K17
K7
K9 M7 M9
P12 P14 P17
P7
P9
T12 T14 T17
T7
T9
V12 V14 V17
V9
Y12 Y14 Y17
Y7
Y9
AD17 AE15 AE18
M17
V7
AF6
AG8
AC5
AJ6
AG5
AD7
PRIMARY WELL
VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05
PRIMARY WELL HVCMOS
VCCPRIM_3P3 VCCPRIM_3P3 VCCPRIM_3P3 VCCPRIM_3P3 VCCPRIM_3P3
VCCAPLL_1P05 VCCAPLL_1P05
VCCDUSB_1P05
VCCA_BCLK_1P05
VCCA_SRC_1P05
VCCA_XTAL_1P05
OMIT_TABLE
U1200
CNL-PCH-H-USFF-QNYP
961822
BGA
SYM 10 OF 11
POWER
DEEP SX WELL
GPPH/GPPK PRIMARY WELL
AUDIO PLL
MOD PHY PRIMARY
VCCAMPHYPLL_1P05
LDO
GPPA PRIMARY WELL
GPPB/GPPC PRIMARY WELL
GPPD PRIMARY WELL
GPPE/GPPEF PRIMARY WELL
RTC WELL SUPPLY
RTC LOGIC PW/VRM
SPI
VCCDPHY_1P24 VCCDPHY_1P24 VCCDPHY_1P24 VCCDPHY_1P24
VCCDSW_3P3
VCCDSW_1P05
VCCPHVLDO_1P8 VCCPHVLDO_1P8
VCCPGPPA
VCCPGPPBC
VCCPGPPD
VCCPGPPEF VCCPGPPEF
VCCPGPPHK
DCPRTC
VCCRTC VCCRTC
VCCSPI
AF19 AG18 AH17 AH19
M19 N18
M6
AF12 AF14
P19
T19
V19
M12 M14
K12
H17
G20 H19
K19
678
3 245
1
OMIT_TABLE
U1200
PP1V24_S5_PCH_VCCDPHY
PP3V3_S5
PP1V05_S5_PCH_VCCDSW
PP1V_PRIM_PCH_VCCAMPHYPLL_F
PP1V8_PCH_VCCPHYLDO
PP1V8_S5
PP1V8_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PPDCPRTC_PCH
PP3V0_G3H_RTC
VOLTAGE=3.3V
0201
PPVCCSPI_PRIM_PCH
0201
12 17 80
Internal Supply
17
17
Internal LDO, leave this pin as NC
17
12 80
12 13 15 19 20 52 80
15 80
14 80
15 19 80
17
12 17 80
R1601
1 2
MF 5%1/20W
VCCSPI:3V3
R1602
1 2
MF 5%1/20W
VCCSPI:1V8
17
CNL-PCH-H-USFF-QNYP
R6
VSS
U13
VSS
A12
VSS
A1
VSS
A2
VSS
AJ24
AA20
AC22
AJ14 AJ19 AJ20
AR14 AR19
AL22
AM12 AM17 AM21
AP25
AR25
PP3V3_S5
80
0
PP1V8_S5
80
AP4
D5
G17
J11 L20
AL1
AG4 AH9
AJ1 AJ9
AL2
AL4 AL9
AM7
AP1
AR1 AR2 AR5 AR9
E24
G1
B1
B25
D7
D9 D14 D19
E4
E7
J5 J8
G5 G12 G21 G25
H4
H6 H12 H14
J4
J6 J13 J22 J18
N15
R4 R8
L1 L6
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
0
961822
BGA
SYM 11 OF 11
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L8 L11 L13 L15 L18 L25 M4 N4 N6 N8 N11 N13 N22 U4 U8 R11 R13 R15 R18 R20 R25 U15 U11 W13 W18 U18 V4 V6 V22 W8 W11 W15 A25 AA1 AA5 A17 A21 AA25 AB3 AA6 AA8 AA11 AA13 AA15 AC4 AC6 AB4 AC8 AE1 AE6 AE8 AE13 AC11 AC13 AC15 AC18 AD4 AD6 AE20 AE25 AF9 AF17 AG6 AG15 AG22 AH4 AH6 AH7 B22
D
C
B
A
PP1V8_S5
17 80
Share with GPIO J Group Power
PP1V05_PRIM
17 117
PP1V8_S0_PCH_VCCHDA_F
17
AG11 AG13 AH12 AH14
K6
AD19
VCCPRIM_1P8 VCCPRIM_1P8 VCCPRIM_1P8 VCCPRIM_1P8
VCCPRIM_MPHY_1P05
HD AUDIO POWER
VCCHDA
ANALOG PLL USB2/VRM
Current data from LPT EDS (doc #486708, Rev 1.0).
BOM_COST_GROUP=CPU & CHIPSET
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
PCH Power
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
16 OF 200
SHEET
16 OF 135
A
8
67
35 4
2
1
Vinafix.com
678
3 245
1
D
PP1V05_PRIM
16 80 117
C1750
12 16 80
PP3V3_S5
16 80
PLACE_NEAR=U1200.K14:1MM
1
12PF
5%
25V
NP0-C0G
2
0201
PP1V8_S5
PLACE_NEAR=U1200.AB14:5MM
PLACE_NEAR=U1200.K14:1MM
C1715
1
0.1UF
10%
16V
2
X5R-CERM 0201
PLACE_NEAR=U1200.AE15:1MM
C1751
12PF
5%
25V
NP0-C0G
0201
PLACE_NEAR=U1200.AG13:2MM
C1716
1
0.1UF
10%
2
16V
X5R-CERM 0201
1
2
1
2
PLACE_NEAR=U1200.V9:3MM
PLACE_NEAR=U1200.AE15:1MM
PLACE_NEAR=U1200.AG13:2MM
C1752
12PF
5%
25V
NP0-C0G 0201
C1700
22UF
20%
X5R-CERM-1
6.3V
603
C1703
1
0.1UF
10%
16V
2
X5R-CERM 0201
1
C1705
1UF
20%
2
6.3V
X6S-CERM 0201
PLACE_NEAR=U1200.P9:1MM
1
2
C1701
1
1UF
10%
6.3V
2
CERM 402
PLACE_NEAR=U1200.AE15:1MM
C1702
1
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U1200.AH12:2MM
1
C1704
0.1UF
10%
2
16V
X5R-CERM 0201
17 16
PP1V05_S5_PCH_VCCDSW
PP3V0_G3H_RTC
12 16 80
PP1V05_PRIM
16 117
1
C1714
0.1UF
10%
16V
2
X5R-CERM 0201
PLACE_NEAR=U1200.N18:1MM PLACE_NEAR=U1200.N18:1MM
1
C1709
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U1200.G19:1MM PLACE_NEAR=U1200.H20:1MM
1
C1711
1UF
20%
6.3V
X6S-CERM
2
0201
PLACE_NEAR=U1200.K6:1MM PLACE_NEAR=U1200.K6:5MM PLACE_NEAR=U1200.K6:1MM
C1713
1
22UF
20%
6.3V
2
X5R-CERM-1 603
1
C1708
0.1UF
10%
16V
2
X5R-CERM 0201
1
C1710
0.1UF
10%
16V
X5R-CERM
2
0201
C1712
1
1UF
20%
2
6.3V
X6S-CERM 0201
VOLTAGE=1.05V
17 16
PP1V05_S5_PCH_VCCDSW
VOLTAGE=3.3V
PPDCPRTC_PCH
16
16
PP1V24_S5_PCH_VCCDPHY
PLACE_NEAR=U1200.N18:1MM
1
C1742
1UF
20%
6.3V
X6S-CERM
2
0201
PLACE_NEAR=U1200.H17:1MM
C1743
1
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U1200.AH19:3MM
NOSTUFF
C1740
1
4.7UF
20%
2
6.3V
X6S 0402
D
C
B
117
PP1V05_PRIM
80
PP1V8_S5
C1721
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
C1724
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
12 16 17 80
220-OHM-0.7A-0.28-OHM
PLACE_NEAR=U1200.AG8:3MM
1
2
L1703
1 2
0402-1
PLACE_NEAR=U1200.AG8:3MM
L1704
75OHM-25%-0.2A-1.3OHM
1 2
PLACE_NEAR=U1200.AD19:3MM
1
2
PLACE_NEAR=U1200.AD19:3MM
0402
PP3V3_S5
C1753
NP0-C0G
MAKE_BASE=TRUE
PP1V05_PRIM_PCH_VCCAPLL_F
PLACE_NEAR=U1200.AG8:1MM
1
C1722
3.0PF
+/-0.1PF
25V
2
NP0-C0G 0201
MAKE_BASE=TRUE
PP1V8_S0_PCH_VCCHDA_F
PLACE_NEAR=U1200.AD19:1MM
C1725
1
3.0PF
+/-0.1PF
2
25V
NP0-C0G 0201
PLACE_NEAR=U1200.AG8:1MM
PLACE_NEAR=U1200.M19:1MM PLACE_NEAR=U1200.M19:1MM PLACE_NEAR=U1200.M19:1MM
1
12PF
5%
2
25V
0201
1
C1720
4.7UF
20%
6.3V
X6S
2
0402
PLACE_NEAR=U1200.AD19:2MM
C1723
1
4.7UF
20%
2
6.3V
X6S 0402
C1707
0.1UF
C1706
1
0.1UF
20%
2
10V
CERM 402
20%
10V
CERM
402
1
2
PP1V05_PRIM_PCH_VCCAPLL_F
PP1V8_S0_PCH_VCCHDA_F
16
16
117
PP1V05_PRIM
PP1V05_PRIM
117
12 16 17 80
PP3V3_S5
C1755
12PF
5%
25V
NP0-C0G
0201
C1756
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
1
PLACE_NEAR=U1200.AD7:5MM
2
1
2
PLACE_NEAR=U1200.M6:3MM
PLACE_NEAR=U1200.AD7:4MM
PLACE_NEAR=U1200.M6:3MM
PLACE_NEAR=U1200.M19:2MM
1
C1741
1UF
20%
6.3V
X6S-CERM
2
0201
OMIT_TABLE
L1701
2.2UH-20%-0.19A-0.221OHM
1 2
0603
1
C1726
47UF
2
PLACE_NEAR=U1200.AD7:3MM
OMIT_TABLE
L1702
2.2UH-20%-0.19A-0.221OHM
1 2
0603
1
C1729
47UF
2
16
MAKE_BASE=TRUE
VOLTAGE=1.05V
PP1V05_PRIM_PCH_VCCAXTAL_F
1
C1727
0.1UF
10%
20%
6.3V
POLY-TANT 0805
MAKE_BASE=TRUE
2
16V
X5R-CERM 0201
PLACE_NEAR=U1200.AD7:3MM PLACE_NEAR=U1200.AD7:3MM
VOLTAGE=1V
PP1V_PRIM_PCH_VCCAMPHYPLL_F
1
C1730
0.1UF
20%
6.3V
POLY-TANT 0805
PLACE_NEAR=U1200.M6:3MM
PLACE_NEAR=U1200.M6:3MM
10%
16V
2
X5R-CERM 0201
PP1V8_PCH_VCCPHYLDO
PP1V05_PRIM_PCH_VCCAXTAL_F
1
C1728
1UF
20%
6.3V
2
X6S-CERM 0201
PP1V_PRIM_PCH_VCCAMPHYPLL_F
1
C1731
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U1200.M6:3MM
NOSTUFF
1
C1744
1UF
20%
6.3V
X6S-CERM
2
0201
C
16
B
16
A
Current data from LPT EDS (doc #486708, Rev 1.0).
8
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
2 L1701,L1702113S0022 RES,MF,1A MAX,0OHM,5%,0603
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
PCH Decoupling
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
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SHEET
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D
Vinafix.com
D
C
6
IN
6
IN
6
IN
6
IN
121 114 46 34 12
121 80
123 18 6
123 13
Extra BPM Testpoints
XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3>
IN
OUT
13
OUT
OUT
PM_RSMRST_L
PM_PWRBTN_L
SPI_MOSI_R SPI_MOSI_R_CONN
IN
XDP_CPU_TCK
XDP_PCH_JTAGX
1
TP
TP1800
TP-P6
1
TP
TP1801
TP-P6
1
TP
TP1802
TP-P6
1
TP
TP1803
TP-P6
R1800
PLACE_NEAR=U1200.H25:2.54MM
R1802
PLACE_NEAR=U1200.K22:5MM
R1803
PLACE_NEAR=U1200.D21:10MM
R1835
PLACE_NEAR=J1800.58:28MM
80
PP3V3_S5
PLACE_NEAR=J1800.48:2.54MM
XDP:YES
1K
1 2
5% 1/20W 201MF
XDP:YES
10
1.5K
1 2
XDP:YES
1 2
XDP:YES
1 2
XDP:YES
R1804
1K
5%
1/20W
MF
201
1/20W 201MF5%
1
2
MF5% 1/20W 201
678
3 245
1
Primary / Merged (CPU/PCH) Micro2-XDP
117
PP1V05_PRIM
PP1V05_S0SW
NOTE: This is not the standard XDP pinout.
XDP_CONN
DF40RC-60DP-0.4V
5%
1/20W
MF
201
1
XDP:YES
NO_XNET_CONNECTION
2
NC NC
NC
NC NC
XDP_PIN_1
OBSFN_A0 OBSFN_A1
OBSDATA_A0 OBSDATA_A1
OBSDATA_A2 OBSDATA_A3
OBSFN_B0 OBSFN_B1
OBSDATA_B0 OBSDATA_B1
OBSDATA_B2 OBSDATA_B3
HOOK0 HOOK1
VCC_OBS_AB
HOOK2 HOOK3
TCK1 TCK0 TMS
XDP:YES
C1800
0.1UF
6.3V
CERM-X5R
0201
PLACE_NEAR=J1800.42:28MM
PLACE_NEAR=J1800.44:28MM
SCL
10%
1
2
PULL CFG<3> LOW
WHEN XDP PRESENT
PLACE_NEAR=J1800.2:5MM
R1801
1.5K
XDP_PRESENT_CPU
123 13 6
123 13 6
BI
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
XDP_CPU_PREQ_L XDP_CPU_PRDY_L
CPU_CFG<0> CPU_CFG<1>
CPU_CFG<2> CPU_CFG<3>
CPU_CFG<4> CPU_CFG<5>
CPU_CFG<6> CPU_CFG<7>
XDP_PM_RSMRST_L XDP_CPU_PWRBTN_L
123 18 13
0201MF5%01/20W
OUT
XDP_PCH_TCK
XDP:YES
C1804
0.1UF
10%
6.3V
CERM-X5R
0201
1
2
J1800
M-ST-SM1
6162
12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 4142 4344 4546 4748 4950 5152 5354 5556 5758 5960
6364
518S0847
Use with 921-0133 Adapter Flex to support chipset debug.
OBSFN_C0 OBSFN_C1
OBSDATA_C0 OBSDATA_C1
OBSDATA_C2 OBSDATA_C3
OBSFN_D0 OBSFN_D1
OBSDATA_D0 OBSDATA_D1
OBSDATA_D2 OBSDATA_D3
ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7
TDOSDA TRSTn TDI
XDP_PRESENT#
XDP:YES
C1801
1
0.1UF
10%
2
6.3V CERM-X5R 0201
PLACE_NEAR=J1800.43:28MM
PLACE_NEAR=J1800.47:28MM
CPU_CFG<17> CPU_CFG<16>
CPU_CFG<8> CPU_CFG<9>
CPU_CFG<10> CPU_CFG<11>
CPU_CFG<19> CPU_CFG<18>
CPU_CFG<12> CPU_CFG<13>
CPU_CFG<14> CPU_CFG<15>
NC_ITPXDP_CLK100MP NC_ITPXDP_CLK100MN
PCH_ITP_PMODE XDP_DBRESET_L
XDP:YES
C1806
1
0.1UF
10%
2
6.3V CERM-X5R 0201
123 18 13
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
IN IN
120 20
120 20
1
R1830
1K
5% 1/20W MF 201
2
PLACE_NEAR=U0500.E8:2.54MM
ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.
R1821
PLACE_NEAR=J1800.51:2.54MM
R1822
PLACE_NEAR=J1800.53:2.54MM
R1823
PLACE_NEAR=J1800.55:2.54MM
R1824
PLACE_NEAR=J1800.57:2.54MM
123 18 13
123 18 13
123 18 13
IN
0
0
0
0
123 18 6
123
123 13
1 2
XDP:YES
1 2
XDP:YES
1 2
XDP:YES
1 2
XDP:YES
XDP_PCH_TDO
XDP_PCH_TDI
XDP_PCH_TMS
XDP_CPU_TDO
XDP_CPU_TCK
18 6
XDP_PCH_TCK
XDP_PCH_TRST_L
18
PROPER WAY TO TERMINATE?
5%
1/20W
1/20W5%
PLACE_NEAR=U1200.AM16:28MM
PLACE_NEAR=U1200.AR18:28MM
PLACE_NEAR=U1200.AL14:28MM
PLACE_NEAR=U0500.BT28:28MM
PLACE_NEAR=U0500.BR28:28MM
PLACE_NEAR=U1200.AP17:28MM
XDP:YES
1 2
XDP_CPU_TDO
MF 02011/20W
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS
MF
R1890 R1891 R1892 R1810
R1813 R1897
R1898
R1806
0
5%
1/20W
MF
0201
0201MF5%
0201MF1/20W5%
0201
PM_SYSRST_L
117
XDP:YES
100
51
100
51
51
51
OUT
OUT
OUT
2 1
XDP:YES
2 1
XDP:YES
2 1
XDP:YES
2 1
XDP:YES
2 1
NOSTUFF
2 1
NOSTUFF
IN
123 18 6
123 13 6
123 6
123 6
5%511/20W 201MF
5%
1/20W
5% 1/20W MF
1
BI
121 46 12
MF1/20W
MF1/20W
MF1/20W
MF
MF1/20W5% 201
2015%
201
2015%
2015%
201
D
C
B
14
14
13
14
14
14
13
14
14
14
14
PCH XDP Signals
These signals do not connect to the Primary (Merged) XDP connector in this architecture. The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation. They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.
PCH/XDP Signals
XDP_PCH_OBSDATA_A0
BI
XDP_PCH_OBSDATA_A1
BI
XDP_PCH_OBSDATA_A2
BI
XDP_PCH_OBSDATA_A3
BI
XDP_PCH_OBSDATA_B0
BI
XDP_PCH_OBSDATA_B1
BI
XDP_PCH_OBSDATA_B2
BI
XDP_PCH_OBSDATA_B3
BI
XDP_PCH_OBSFN_C0
BI
XDP_PCH_OBSDATA_D0
BI
XDP_PCH_OBSDATA_D1
BI
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
1
TP
TP1810
TP-P5
1
TP
TP1811
TP-P5
1
TP
TP1812
TP-P5
1
TP
TP1813
TP-P5
1
TP
TP1814
TP-P5
1
TP
TP1815
TP-P5
1
TP
TP1816
TP-P5
1
TP
TP1817
TP-P5
1
TP
TP1818
TP-P5
1
TP
TP1824
TP-P5
1
TP
TP1825
TP-P5
18 14
18 14
18 14
18 14
18 14
18 14
18 14
Non-XDP Signals
XDP_JTAG_ISP_TDO
BI
XDP_JTAG_ISP_TCK
BI
XDP_JTAG_ISP_TDI
BI
XDP_USB_EXTA_OC_L
BI
XDP_USB_EXTB_OC_L
BI
XDP_USB_EXTC_OC_L
BI
XDP_USB_EXTD_OC_L
BI
123 107 27 14
123 107 27 14
OUT
OUT
JTAG_ISP_TDI
JTAG_ISP_TCK
JTAG_ISP_TDO
R1840 R1841 R1842
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
0
1 2
0
1 2
0
1 2
1/20W 5% 0201 MF
1/20W 5% 0201 MF
1
TP
TP1819
TP-P5
1
TP
TP1826
TP-P5
1
TP
TP1827
TP-P5
1
TP
TP1820
TP-P5
1
TP
TP1821
TP-P5
1
TP
TP1822
TP-P5
1
TP
TP1823
TP-P5
XDP_JTAG_ISP_TDI
XDP_JTAG_ISP_TCK
MF02015%1/20W
XDP_JTAG_ISP_TDO
18 80
PP1V8_S5
XDP_PCH_TDO XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS
PP1V8_S5
XDP:YES
1
R1850
100K
5% 1/20W MF 201
2
18 80
1
C1830
XDP:YES
74AUP1G07GF
2 1 5
6
VCC
U1830
SOT891
(OD)
GND
3
2
YA
SPI_IO2_STRAP_L
4
NCNC
NCNC
XDP:YES
0.1UF
10% 10V X5R-CERM 0201
PLACE_NEAR=U1830.4:7.54MM
1.5K
NO_XNET_CONNECTION
PLACE_NEAR=U1830.4:2.54MM
49.9
NO_XNET_CONNECTION
R1831
1 2
XDP:YES
R1832
1 2
MF
5%
NOSTUFF
SPI_IO<2>
1/20W
201MF
(STRAP TO PCH)
1% 1/20W
201
XDP_PRESENT_L
NEED TO CONNECT TO VCCST, *STG POWER LOGIC
IN
IN
OUTIN
18 14
18 14
18 14 123 107 27
IN
18
OUT OUT
OUT
OUT
123 18 13
123 18 13
123 18 13
13
B
39
A
Unused GPIOs have TPs.
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.
110
111
30 29
31 29
UPC_TA_FAULT_L
IN
UPC_TB_FAULT_L
IN
UPC_XA_FAULT_L
IN
UPC_XB_FAULT_L
IN
R1843 R1844 R1845 R1846
0
1
0
1
0
1 2
0
1 2
2
2
XDP_USB_EXTC_OC_L
5%MF02011/20W
XDP_USB_EXTD_OC_L
5%MF02011/20W
XDP_USB_EXTA_OC_L
MF02011/20W 5%
XDP_USB_EXTB_OC_L
5%MF1/20W 0201
OUT
OUT
OUT
OUT
18 14
18 14
18 14
DESIGN: X502/MLB LAST CHANGE: Mon Jun 15 22:04:28 2015
18 14
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
CPU/PCH Merged XDP
SIZE
D
BOM_COST_GROUP=DEBUG
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
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PCIE CLKREQS
678
3 245
1
D
PP1V8_S5
PP3V3_S5
R1940
R1941
R1942
R1944
100K
100K
47K
47K
1 2
1 2
1 2
1 2
TBT_X_CLKREQ_L
TBT_T_CLKREQ_L
5% 201MF1/20W
120 12
120 12
PCH_WLAN_CLKREQ_L
PCH_GPU_CLKREQ_L
12 13 15 16 20 52 80
15 16 19 80
2015% 1/20W MF
201MF1/20W5%
2011/20W MF5%
5%
19 118 124
PP1V8_G3S_WLANBT
BYPASS=U1901::5MM
120 27 12
120 107 12
R1943
1K
1/20W MF 2015%
1 2
PCH_WLANBT_CLKREQ_R_L
37 36
36
BT_AUDIO_SYNC
IN
R1945
GPU_CLKREQ_L_R
GPU_CLKREQ_L_R
MAKE_BASE=TRUE
19
MF 2011/20W
1K
1 2
C1902
0.1UF
10% 16V
X5R-CERM
0201
1
2
NC
1
VCCA VCCB
U1901
SLSV1T34AMU-COMBO
2 4
5
UDFN
CRITICAL
NC
GND
PP3V3_S5
6
3
BYPASS=U1901::5MM
10% 16V
0201
1
2
C1903
0.1UF
X5R-CERM
BA
BT_AUDIO_SYNC_LS3V3
15 16 19 80
OUT
D
15
C
19 118 124
PP1V8_G3S_WLANBT
BYPASS=U1900::5MM
WLAN_AUDIO_SYNC
C1900
0.1UF
10%
X5R-CERM
0201
1
2
NC
PP3V3_S5
1
VCCA VCCB
U1900
SLSV1T34AMU-COMBO
2 4
5
UDFN
CRITICAL
NC
GND
6
BA
3
1
C1901
0.1UF
10% 16V
X5R-CERM
0201
BYPASS=U1900::5MM
216V
WLAN_AUDIO_SYNC_LS3V3
15 16 19 80
OUTIN
15 38 37 36
C
B
PP1V8_G3S
118
PLACE_NEAR=U1950.1:2mm
19
116 95
IN
EG_VR4_PGOOD
PP3V3_S0_GPU
1
C1950
0.1UF
10%
6.3V
2 6.3V
CERM-X5R 0201
8
1
VCCVL
U1950
NLSX4402
2 3
5
IO/VL1 IO/VL2
EN
UDFN-COMBO
GND
4
IO/VCC1 IO/VCC2
7 6
1
C1951
0.1UF
10%
2
CERM-X5R 0201
GPU_CLKREQ_LGPU_CLKREQ_L_R
NCNC
PLACE_NEAR=U1950.8:2mm
1
R1952
47K
5% 1/20W MF
2
201
117
97
BI
B
A
8
A
SYNC_DATE=01/17/2019SYNC_MASTER=ARMIN
PAGE TITLE
Chipset Support 1
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
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D
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678
3 245
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NC ALIASES 3
D
12 13 15 16 19 52 80
121 46 35 12
PP1V8_S5
IN
PLACE_NEAR=U2072.1:5MM
C2072
0.1UF
10% 16V
X5R-CERM
0201
NC_PCH_CLK32K_RTCX2
12
MAKE_BASE=TRUE
NC_PCH_CLK32K_RTCX2
SIGNAL ALIASES
PCH_DISPA_BCLK
13
PCH_DISPA_SDI
13
Platform Reset Connections
PP3V3_S5
1
2
2 4
1
VCCA VCCB
U2072
SLSV1T34AMU-COMBO
UDFN
6
95
BA
C2073
0.1UF
10% 16V
X5R-CERM
0201
PLT3V3_RST_LPLT_RST_L
PLACE_NEAR=U2072.6:5MM
1
2
80
PCH_DISPA_SDO
13
18 120
NC_ITPXDP_CLK100MN
18 120
NC_ITPXDP_CLK100MP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCH_DISPA_BCLK PCH_DISPA_SDI PCH_DISPA_SDO
TRUE
TRUE
NC_ITPXDP_CLK100MN NC_ITPXDP_CLK100MP
5
5
5
D
C
R2060
100K
5%
1/20W
MF
201
1
2
NC
5%
1/20W
MF
201
1
100K
2
100K
100K
100K
R2000
12
5% 1/20W MF
R2001
12
5% 2011/20W MF
12
R2002
5% 2011/20W MF
R2005
12
5% 1/20W
MF 201
TBT_X_PCI_RESET_L
201
TBT_T_PCI_RESET_L
PCH_WLANBT_PERST_L
SOC_PERST_L
OUT
OUT
OUT
OUT
33 27 14
113 107 14
37 36 13
39 15
5
NC
GND
3
R2061
100K
C
B
B
A
8
A
SYNC_MASTER=ANDY
PAGE TITLE
SYNC_DATE=02/19/2019
Chipset Support 2
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
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IV ALL RIGHTS RESERVED
2
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3 245
1
D
DDR4 VDDQ = 1.2V
----------------­ MIMINUM Step Size = 0.50% * VDDQ = 6.0mV per step
TYPICAL Step Size = 0.65% * VDDQ = 7.8mV per step MAXIMUM Step Size = 0.80% * VDDQ = 9.6mV per step
KBL PLATFORM GUIDE Page.102 FOR DDR4 X8 MEMORY DOWN
-------------------------------------------------­ DDR0_VREF_DQ = Not Used DDR1_VREF_DQ = Reference For Channel B
DDR_VREF_CA = Reference For Channel A
D
CPU-Based Margining
VRef Dividers
C
B
PP1V2_S3
117
C
1
R2241
1.8K
1% 1/20W MF
R2243
7
IN
7
IN
CPU_DIMMB_VREFDQ
1
2
CPU_DIMM_VREFCA
1
2
2.7
1 2
5%
1/20W
MF
201
PLACE_NEAR=R2241.2:1mm
C2240
0.022UF
10%
6.3V X5R-CERM 0201
MEM_VREFDQ_B_RC
R2263
2.7
1 2
5%
1/20W
MF
201
PLACE_NEAR=R2261.2:1mm
C2260
0.022UF
10%
6.3V X5R-CERM 0201
MEM_VREFCA_A_RC
R2242
1.8K
1/20W
R2240
24.9
1 2
1%
1/20W
MF
201
R2262
1.8K
1/20W
R2260
24.9
1 2
1%
1/20W
MF
201
1% MF
201
1% MF
201
1
2
1
2
201
2
PP0V6_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000
1
R2261
1.8K
1% 1/20W MF 201
2
PP0V6_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000
117
117
B
A
8
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
DDR4 VREF Margining
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
BOM_COST_GROUP=DRAM
67
35 4
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
22 OF 200
SHEET
21 OF 135
1
SIZE
D
Vinafix.com
678
3 245
1
D
C2307
0.47UF
CERM-X5R-1
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>
7
MEM_A_A<16>
22 23 26 120
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
20%
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
FBGA
VDD
VDDQ
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
VDD
VDD
VDD
VDD
OMIT_TABLE
U2300
16GB-64X8X2-2400
MT40A2G8-NRE
22 23 26 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
C2
MEM_A_DQ<0>
B7
MEM_A_DQ<1>
D3
MEM_A_DQ<2>
D7
MEM_A_DQ<3>
D2
MEM_A_DQ<4>
D8
MEM_A_DQ<5>
E3
MEM_A_DQ<6>
E7
MEM_A_DQ<7>
C3
MEM_A_DQS_P<0>
B3
MEM_A_DQS_N<0>
A7
PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
128 120
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120
120 26 23 22 7
22 7
128 120
22 7
26 23 22 7
120
128 120
22 7
128 120
22 7
128 120
22 7
128 120
22 7
128 120
22 7
128 120
128 120
22 23 26 117
26 23 22 7
C2317
0.47UF
20%
CERM-X5R-1
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
201
4V
1
2
NC
PP1V2_S3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
K2
BA0
K8
BA1
J2
BG0
J8
BG1
PAR
N3 H3
ACT*
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2310
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
22 23 26 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
C2
MEM_A_DQ<8>
B7
MEM_A_DQ<9>
D3
MEM_A_DQ<10>
D7
MEM_A_DQ<11>
D2
MEM_A_DQ<12>
D8 E3
MEM_A_DQ<14>
E7
MEM_A_DQ<15>
C3
MEM_A_DQS_P<1>
B3
MEM_A_DQS_N<1>
A7
PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
128 120
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23
120 26 23 22 7
22 23 26 117
120 26 23 22 7
120 7
120 26 23 22 7
22 7
26 23 22 7
120 22 7
128 120
26 23 22 7
120
26 23 22 7
120 22 7 128 120
22 7
128 120
22 7
128 120
128 120
128 120
22 7
26 23 22 7
26 23 22
120
PP1V2_S3
20%
4V
201
1
2
NC
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8
N7
K2
K8
J2 J8
N3
H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
16GB-64X8X2-2400
OMIT_TABLE
U2320
MT40A2G8-NRE
FBGA
C2327
0.47UF
CERM-X5R-1
MEM_A_A<0> MEM_A_DQ<16> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_DQ<19> MEM_A_A<4> MEM_A_A<5>MEM_A_DQ<13> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
22 23 26 117
VDD
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VDDQ
VDDQ
NF/TDQS_C
E8
VDDQ
VDDQ
DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
DQ0 DQ1 DQ2 DQ3
C2 B7
MEM_A_DQ<17>
D3
MEM_A_DQ<18>
D7 D2
MEM_A_DQ<20>
D8
MEM_A_DQ<21>
E3
MEM_A_DQ<22>
E7
MEM_A_DQ<23>
C3
MEM_A_DQS_P<2>
B3
MEM_A_DQS_N<2>
A7
PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
26 23 22 7
120 26 23
120 26 23
26 23 22 7
26 23 22 7
120 26 23
26 23 22 7
120 26 23
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22
120 26 23 22 7
22 23 26 117
120 26 23 22 7
120
120 26 23 22 7
120
22 7
128 120
22 7
128 120
120
120
22 7
128 120
120
22 7
128 120
128 120
128 120
7
120 7
26 23 22
120 7
26 23 22 7
26 23 22
C2337
0.47UF
20%
CERM-X5R-1
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2330
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
22 23 26 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
C2
MEM_A_DQ<24>
B7
MEM_A_DQ<25>
D3
MEM_A_DQ<26>
D7
MEM_A_DQ<27>
D2
MEM_A_DQ<28>
D8
MEM_A_DQ<29>
E3
MEM_A_DQ<30>
E7
MEM_A_DQ<31>
C3
MEM_A_DQS_P<3>
B3
MEM_A_DQS_N<3>
A7
PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
120 128
26 22 23 117
120 23 7 22 26
D
128 120
128 120
128 120
128 120
128 120
128 120
128 120
120 128
120 128
C
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1> MEM_A_ODT<1>
26 24 22
MEM_RESET_L
23 25
MEM_A_CLK_P<0>
7
MEM_A_CLK_N<0>
22 23 26 120
G3 G7
F3
G2 G8
F2
L1
F7 F8
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS
C8
E1
VSS
E9
VSS
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
VSSQ
A2
VSSQ
A8
VSSQ
D1
VREFCA
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VSSQ
ZQ
B1
PP2V5_S3
M9
J1
PP0V6_S3_MEM_VREFCA_A
G9
MEM_A_TEN MEM_A_TENMEM_A_TENMEM_A_TEN
B9
MEM_A_ZQ<0>
R2300
240
1%
1/20W
MF
201
2
1
C2308
0.047UF
10%
6.3V X5R 201
22 23 117
120 26 23 22
120 26 23 22 7
120 26 23 22 7
26 23 22 7
26 23 22 7
1
25 24 23 22
2
26 23 22 7
26 23 22 7
7
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1>
120
MEM_A_ODT<1>
120
MEM_RESET_L
26
MEM_A_CLK_P<0>
120
MEM_A_CLK_N<0>
120
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
VSS C8
VSS E1
VSS E9
VSS G1
VSS H9
VSS K1
VSS K9
VSS N1
VSSQ
VSSQ
A2
A8
VSSQ
VSSQ
D1
D9
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ A9
ZQ
B1
PP2V5_S3
M9
J1
PP0V6_S3_MEM_VREFCA_A
G9
B9
MEM_A_ZQ<1> MEM_A_ZQ<2>
R2310
1/20W
240
1% MF
201
2
1
C2318
0.047UF
10%
6.3V X5R 201
22 23 117
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
1
26 23 22 7
2
26 25 24 23 22
120 26 23 22 7
120 26 23 22 7
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1> MEM_A_ODT<1>
120
MEM_RESET_L
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
G3 G7
F3
G2 G8
F2
L1
F7 F8
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS
C8
E1
VSS
E9
VSS
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
VSSQ
A2
VSSQ
A8
VSSQ
D1
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VREFCA
ZQ
VSSQ
ZQ
B1 M9
J1
G9
B9
PP2V5_S3
0.047UF
MEM_A_ZQ<3>
R2330
240
1%
1/20W
MF
201
C2338
10%
6.3V X5R 201
2
1
1
2
B1
PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFCA_A
J1
10%
6.3V X5R 201
1
2
G9
B9
R2320
240
1%
1/20W
MF
201
C2328
0.047UF
2
1
22 23 117
120 26 23 22 7
120 26 23 22 7
23 22 7
120 26
26 23 22 7
26 23 22 7
25 24 23 22
26 23 22 7
26 23 22 7
120
120
26
120
120
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1> MEM_A_ODT<1>
MEM_RESET_L
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
VSS C8
VSS E1
VSS E9
VSS G1
VSS H9
VSS
VSS
K1
K9N1A2
VSS
VSSQ
VSSQ
A8
VSSQ
D1
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VREFCA
VSSQ
117 22 23
C
117
23 22
B
PP2V5_S3
C2350
1.0UF
20%
6.3V X5R
0201-1
PP1V2_S3
C2300
2.2UF
20%
6.3V
X5R-CERM
0201
22 23 117
1
2
1
C2351
1.0UF
0201-1
C2301
2.2UF
2
X5R-CERM
20%
6.3V X5R
20%
6.3V
0201
1
2
C2352
1.0UF
22 23 26 117
1
C2302
2.2UF
2
X5R-CERM
20%
6.3V X5R
0201-1
20%
6.3V
0201
1
2
1
C2353
1.0UF
0201-1
C2303
2.2UF
2
X5R-CERM
20%
6.3V X5R
20%
6.3V
0201
1
2
1
C2354
1.0UF
0201-1
C2310
2.2UF
2
X5R-CERM
20%
6.3V X5R
20%
6.3V
0201
1
2
1
C2355
1.0UF
6.3V
0201-1
C2311
2.2UF
2
6.3V
X5R-CERM
0201
Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)
20% X5R
1
2
C2356
1.0UF
20%
6.3V X5R
0201-1
1
2
C2357
1.0UF
0201-1
20%
6.3V X5R
1
2
C2358
1.0UF
0201-1
20%
6.3V X5R
1
2
C2359
1.0UF
0201-1
20%
6.3V X5R
1
2
C2360
1.0UF
0201-1
20%
6.3V X5R
1
2
C2361
1.0UF
0201-1
20%
6.3V X5R
1
2
C2362
VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)
20%
1
C2312
2.2UF
2
X5R-CERM
20%
6.3V 0201
1
C2313
2.2UF
2
X5R-CERM
20%
6.3V 0201
1
2
1
C2304
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2305
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2306
0.1UF
10%
2
6.3V CERM-X5R 0201
1.0UF
20%
6.3V X5R
0201-1
1
C2370
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2363
1.0UF
0201-1
1
C2309
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V X5R
1
2
C2364
1.0UF
0201-1
1
C2314
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V X5R
1
2
C2365
1.0UF
0201-1
1
C2315
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V X5R
1
2
1
C2316
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2371
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2319
0.1UF
10%
2
6.3V CERM-X5R 0201
B
A
PP1V2_S3
20%
6.3V 0201
1
2
C2320
2.2UF
X5R-CERM
PP1V2_S3
C2321
2.2UF
20%
6.3V
X5R-CERM
0201
1
C2380
0.1UF
10%
2
6.3V CERM-X5R 0201
22 23 26 117
1
2
C2322
22 23 26 117
1
2
1
2.2UF
20%
2
6.3V
X5R-CERM
0201
C2381
0.1UF
10%
6.3V CERM-X5R 0201
C2323
2.2UF
20%
6.3V
X5R-CERM
0201
1
C2382
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V 0201
1
C2331
2.2UF
2
X5R-CERM
1
C2384
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2330
2.2UF
2
X5R-CERM
1
C2383
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V 0201
1
C2332
2.2UF
2
X5R-CERM
1
C2385
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V 0201
1
C2333
2.2UF
2
X5R-CERM
1
C2386
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V 0201
1
2
1
C2324
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2325
0.1UF
10%
2
6.3V CERM-X5R 0201
5x 0.1uF per chip
1
C2387
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2388
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2326
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2389
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2390
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2372
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2391
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2329
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2392
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2334
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2393
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
2
1
C2394
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2335
0.1UF
10%
6.3V CERM-X5R 0201
1
C2395
2
1
2
0.1UF
10%
6.3V CERM-X5R 0201
C2336
0.1UF
10%
6.3V CERM-X5R 0201
1
C2396
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2397
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2373
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2398
0.1UF
10%
6.3V CERM-X5R 0201
1
C2339
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2399
0.1UF
10%
2
6.3V CERM-X5R 0201
BOM_COST_GROUP=DRAM
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
DDR4 SDRAM Channel A 1
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
23 OF 200
SHEET
22 OF 135
A
8
67
35 4
2
1
Vinafix.com
678
3 245
1
D
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
22 7 26 23
22 7
C
26 23
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 24 22 23 25
26 23 22 7
22 7
120 26 23
C2407
0.47UF
CERM-X5R-1
MEM_A_A<0>
120
MEM_A_A<1>
120
MEM_A_A<2>
120
MEM_A_A<3>
120
MEM_A_A<4>
120
MEM_A_A<5>
120
MEM_A_A<6>
120
MEM_A_A<7>
120
MEM_A_A<8>
120
MEM_A_A<9>
120
MEM_A_A<10>
120
MEM_A_A<11>
120
MEM_A_A<12>
120
MEM_A_A<13>
120
MEM_A_A<14>
120
MEM_A_A<15>
120
MEM_A_A<16>
120
MEM_A_BA<0>
120
MEM_A_BA<1>
120
MEM_A_BG<0>
120
MEM_A_BG<1>
120
120
MEM_A_PAR MEM_A_ACT_L
120
MEM_A_CKE<0>
120
MEM_A_CS_L<0>
120
MEM_A_ODT<0>
120
MEM_A_CKE<1>
120
MEM_A_CS_L<1>
120
MEM_A_ODT<1>
120
MEM_RESET_L
MEM_A_CLK_P<0>
120
MEM_A_CLK_N<0>
20%
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
G3 G7
F3
G2 G8
F2
L1
F7 F8
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS C8
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2400
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
VSS
VSS
VSS
K1
K9
VSS N1
VSS E1
VSS E9
VSS G1
H9
22 23 26 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A2
A8
D1
D9
A9
ZQ
C2
MEM_A_DQ<32>
B7
MEM_A_DQ<33>
D3
MEM_A_DQ<34>
D7
MEM_A_DQ<35>
D2
MEM_A_DQ<36>
D8
MEM_A_DQ<37>
E3
MEM_A_DQ<38>
E7
MEM_A_DQ<39>
C3
MEM_A_DQS_P<4>
B3
MEM_A_DQS_N<4>
A7 A3
NC
L9
MEM_A_ALERT_L
B1
PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_A
J1
G9
MEM_A_TEN
MEM_A_ZQ<4>
B9
R2400
240
1/20W
201
1% MF
2
1
C2408
0.047UF
10%
6.3V X5R 201
26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
22 23 26 117
120 26 23 22 7
120
26 23 22 7
7
120 26 23 22 7
22 23 117
120 26 23 22
120 26 23 22 7
120 26 23 22 7
26 23 22 7
26 23 22 7
1
25 24 23 22
2
26 23 22 7
26 23 22 7
128 120
22 7
120 26 23
128 120
22 7
120 26 23
128 120
22 7
120 26 23
120
22 7
128 120
120 26 23
22 7
128 120
120 26 23
22 7
128 120
120 26 23
22 7
128 120
120 26 23
128 120
22 7
128 120
120 26 23
120
26 23 22
7
23 22
117
120
120
26
120
120
C2417
0.47UF
CERM-X5R-1
20%
4V
201
1
2
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
NC
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1> MEM_A_ODT<1>
MEM_RESET_L
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
PP1V2_S3
C7F1F9H1J9M1N9A1B2B8C1C9E2
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
BA0
K2
BA1
K8
BG0
J2
BG1
J8
PAR
N3
ACT*
H3
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
C8
VDD
VDD
VDD
VDD
16GB-64X8X2-2400
OMIT_TABLE
VSS
E9
VSS
G1
VSS
VSS
E1
VDD
VDD
VDD
U2410
MT40A2G8-NRE
FBGA
VSS
VSS
VSS
K1
K9
H9
VDD
VSS
N1
22 23 26 117
E8
VDDQ
VDDQ
VSSQ
A8
VDDQ
VDDQ
NF/TDQS_C
VSSQ
VSSQ
A9
D1
D9
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
VPP0 VPP1
VREFCA
RFU/TEN
VSSQ
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VSSQ
A2
ZQ
PP1V2_S3
C2427
0.47UF
CERM-X5R-1
C2
MEM_A_DQ<40>
B7
MEM_A_DQ<41>
D3
MEM_A_DQ<42>
D7
MEM_A_DQ<43>
D2
MEM_A_DQ<44>
D8
MEM_A_DQ<45>
E3
MEM_A_DQ<46>
E7
MEM_A_DQ<47>
C3
MEM_A_DQS_P<5>
B3
MEM_A_DQS_N<5>
A7
PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
B1 M9
PP0V6_S3_MEM_VREFCA_A
J1
10%
6.3V X5R 201
1
2
G9
MEM_A_TEN MEM_A_TEN MEM_A_TEN
B9
MEM_A_ZQ<5>
R2410
240
1/20W
201
C2418
0.047UF
2
1% MF
1
128 120
22 7
120 26 23
128 120
22 7
120 26 23
22 7
128 120
120 26 23
128 120
22 7
120 26 23
128 120
22 7
120 26 23
128 120
22 7
120 26 23
128 120
22 7
120 26 23
128 120
22 7
120 26 23
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
128 120
128 120
120 26 23 22
120 26 23 22 7
22 23 26 117
120 26 23 22 7
120
26 23 22 7
7
120 26 23 22 7
22 23 117
120 26 23 22
120 26 23 22 7
120 26 23 22 7
120 26 23 22
26 23 22 7
26 23 22 7
25 24 23 22
26 23 22 7
26 23 22 7
7
120 7
26 23 22
120
26 23 22
7
7
117 23 22
120
120
26
120
120
MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1> MEM_A_ODT<1>
MEM_RESET_L
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
20%
4V
201
NC
1
2
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
BA0
K2
BA1
K8
BG0
J2
BG1
J8
PAR
N3
ACT*
H3
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
16GB-64X8X2-2400
OMIT_TABLE
VSS
VSS
VSS
E1
E9
C8
U2420
MT40A2G8-NRE
VSS
VSS
VSS
K1
H9
G1
FBGA
VSS K9
22 23 26 117
VDD
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VSSQ
VSS
A2
N1
VDDQ
VSSQ
VSSQ
A8
D1
VDDQ
NF/TDQS_C
VSSQ D9
E8
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
ZQ
VSSQ A9
C2
MEM_A_DQ<48>MEM_A_A<0>
B7
MEM_A_DQ<49>
D3
MEM_A_DQ<50>
D7
MEM_A_DQ<51>
D2
MEM_A_DQ<52>
D8
MEM_A_DQ<53>
E3
MEM_A_DQ<54>
E7
MEM_A_DQ<55>
C3
MEM_A_DQS_P<6>
B3
MEM_A_DQS_N<6>
A7
PP1V2_S3PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
B1
PP2V5_S3PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_A
J1
G9
C2428
0.047UF
B9
MEM_A_ZQ<6>
240
1%
1/20W
MF
201
2
1
R2420
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
10%
6.3V X5R 201
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
23 22 7
120 26
23 22 7
120 26
26 23 22 7
23 22 7
120 26
23 22 7
120 26
26 23 22 7
1
23 22 7
2
25 24 23 22
26 23 22 7
26 23 22 7
MEM_A_A<0>
120
MEM_A_A<1>
120
MEM_A_A<2>
120
MEM_A_A<3>
120
MEM_A_A<4>
120
MEM_A_A<5>
120
MEM_A_A<6>
120
MEM_A_A<7>
120
MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
128 120
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR
120
MEM_A_ACT_L
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1>
120
MEM_A_ODT<1>
120 26
MEM_RESET_L
26
MEM_A_CLK_P<0>
120
MEM_A_CLK_N<0>
120
C2437
0.47UF
20%
CERM-X5R-1
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
G3 G7
F3
G2 G8
F2
L1
F7 F8
C7F1F9H1J9M1N9
VDD
VDD
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
OMIT_TABLE
VSS
VSS
VSS
E1
E9
C8
22 23 26 117
A1B2B8C1C9E2E8
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
U2430
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
NF/DM*/DBI*/TDQS_T
VSSQ
VSSQ
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
A2
A8
VSSQ
D1
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/TDQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ
VSSQ
A9
D9
ZQ
MEM_A_DQ<56>
C2
MEM_A_DQ<57>
B7
MEM_A_DQ<58>
D3
MEM_A_DQ<59>
D7
MEM_A_DQ<60>
D2
MEM_A_DQ<61>
D8
MEM_A_DQ<62>
E3
MEM_A_DQ<63>
E7
MEM_A_DQS_P<7>
C3
MEM_A_DQS_N<7>
B3
PP1V2_S3
A7 A3
NC
MEM_A_ALERT_L
L9
B1
PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_A
J1
G9
MEM_A_ZQ<7>
B9
R2430
240
1%
1/20W
MF
201
C2438
0.047UF
2
1
10%
6.3V X5R 201
D
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
22 23 26 117
120 23 7 22 26
C
22 23 117
1
2
B
PP2V5_S3
C2450
1.0UF
20%
6.3V X5R
0201-1
PP1V2_S3
C2400
2.2UF
20%
6.3V
X5R-CERM
0201
22 23 117
1
2
1
2
C2451
1.0UF
0201-1
C2401
2.2UF
X5R-CERM
20%
6.3V X5R
20%
6.3V 0201
1
2
C2452
1.0UF
22 23 26 117
1
2
C2402
20%
6.3V X5R
0201-1
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
2
C2453
1.0UF
0201-1
C2403
2.2UF
X5R-CERM
20%
6.3V X5R
20%
6.3V 0201
1
2
1
2
C2454
1.0UF
0201-1
C2410
2.2UF
X5R-CERM
20%
6.3V X5R
20%
6.3V 0201
1
2
1
2
C2455
1.0UF
6.3V
0201-1
C2411
2.2UF
X5R-CERM
Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)
20% X5R
1
2
C2456
1.0UF
0201-1
20%
6.3V X5R
1
2
C2457
1.0UF
0201-1
20%
6.3V X5R
1
2
C2458
1.0UF
0201-1
20%
6.3V X5R
1
2
C2459
1.0UF
0201-1
20%
6.3V X5R
1
2
C2460
1.0UF
0201-1
20%
6.3V X5R
1
2
C2461
VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)
1
C2406
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
C2404
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2413
2.2UF
X5R-CERM
1
2
C2412
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
1
C2405
0.1UF
10%
6.3V
2
CERM-X5R 0201
1.0UF
20%
6.3V X5R
0201-1
C2470
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2462
1.0UF
0201-1
1
C2414
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
1
2
C2463
1.0UF
0201-1
1
C2409
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
1
2
C2464
1.0UF
C2416
1
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V X5R
0201-1
1
2
C2465
1.0UF
1
C2415
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
0201-1
1
B
2
1
C2419
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2471
1
0.1UF
10%
2
6.3V CERM-X5R 0201
A
PP1V2_S3
C2420
2.2UF
20%
6.3V
X5R-CERM
0201
PP1V2_S3
22 23 26 117
1
2
1
C2490
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2473
0.1UF
10%
6.3V CERM-X5R 0201
1
C2424
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2487
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
22 23 26 117
1
2
C2422
2.2UF
X5R-CERM
C2481
0.1UF
10%
6.3V CERM-X5R 0201
1
2
C2421
2.2UF
X5R-CERM
1
C2480
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2423
2.2UF
X5R-CERM
1
C2482
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2430
2.2UF
X5R-CERM
1
C2483
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2431
2.2UF
X5R-CERM
1
C2484
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2432
2.2UF
X5R-CERM
1
C2485
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2433
2.2UF
X5R-CERM
1
C2486
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
5x 0.1uF per chip
1
C2425
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2488
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2426
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2489
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2472
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2491
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2429
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2492
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2493
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2434
0.1UF
10%
6.3V CERM-X5R 0201
1
2
C2494
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2435
0.1UF
10%
6.3V CERM-X5R 0201
C2495
1
2
1
2
0.1UF
10%
6.3V CERM-X5R 0201
C2436
0.1UF
10%
6.3V CERM-X5R 0201
C2496
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2439
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2497
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2498
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2499
0.1UF
10%
6.3V
2
CERM-X5R 0201
BOM_COST_GROUP=DRAM
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
DDR4 SDRAM Channel A 2
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
24 OF 200
SHEET
23 OF 135
A
8
67
35 4
2
1
Vinafix.com
678
3 245
1
D
120 25
MEM_B_A<0>
7 24 26
MEM_B_A<1>
7 24 25
MEM_B_A<2>
26 120
MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>
25
MEM_B_A<16>
7 24 26 120
120 25
MEM_B_BA<0>
7 24 26
MEM_B_BA<1> MEM_B_BG<0>
25
MEM_B_BG<1>
7 24 26 120
MEM_B_PAR MEM_B_ACT_L
C2507
0.47UF
20%
CERM-X5R-1
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
FBGA
VDD
VDDQ
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
VDD
VDD
VDD
VDD
U2500
16GB-64X8X2-2400
MT40A2G8-NRE
OMIT_TABLE
24 25 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
C2
MEM_B_DQ<0>
B7
MEM_B_DQ<1>
D3
MEM_B_DQ<2>
D7
MEM_B_DQ<3>
D2
MEM_B_DQ<4>
D8
MEM_B_DQ<5>
E3
MEM_B_DQ<6>
E7
MEM_B_DQ<7>
C3
MEM_B_DQS_P<0>
B3
MEM_B_DQS_N<0>
A7
PP1V2_S3
A3
NC
L9
MEM_B_ALERT_L
128 120
24 7
120 26 25
128 120
24 7
120 26 25
26 25 24 7
128 120
24 7
120 26 25
128 120
24 7
120 26 25
24 7
128 120
120 26 25
128 120
24 7
120 26 25
26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
128 120
128 120
120 26 25 24
120 26 25 24 7
24 25 117
120 26 25 24
120 26 25 24 7
120
120 26 25 24 7
26 25 24 7
26 25 24
C2517
0.47UF
CERM-X5R-1
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2>
120
MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7>
120
MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
7
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0>
7
MEM_B_BG<1>
120 7
MEM_B_ACT_L
20%
4V
201
1
2
NC
PP1V2_S3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
BA0
K2
BA1
K8
BG0
J2
BG1
J8
N3
PAR ACT*
H3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2510
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
24 25 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
PP1V2_S3
20%
4V
201
1
2
NC
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
16GB-64X8X2-2400
OMIT_TABLE
U2520
MT40A2G8-NRE
FBGA
C2527
0.47UF
CERM-X5R-1
C2
MEM_B_DQ<8>
B7
MEM_B_DQ<9>
D3
MEM_B_DQ<10>
D7
MEM_B_DQ<11>
D2
MEM_B_DQ<12>
D8
MEM_B_DQ<13>
E3
MEM_B_DQ<14>
E7
MEM_B_DQ<15>
C3
MEM_B_DQS_P<1>
B3
MEM_B_DQS_N<1>
A7
PP1V2_S3 PP1V2_S3
A3
NC
L9
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7 120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
128 120
26 25 24 7
120 26 25 24 7
26 25 24 7
120 26 25 24 7
26 25 24 7
26 25 24
120
120 26 25 24 7
MEM_B_A<0>
120
MEM_B_A<1>
120
MEM_B_A<2>
120
MEM_B_A<3>
120
MEM_B_A<4>
120
MEM_B_A<5>
120
MEM_B_A<6>
120
MEM_B_A<7>
120
MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
MEM_B_BA<0>
120
MEM_B_BA<1> MEM_B_BG<0>
120
MEM_B_BG<1>
120 7
MEM_B_PARMEM_B_ALERT_LMEM_B_PAR MEM_B_ACT_L
24 25 117
VDD
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VDDQ
VDDQ
NF/TDQS_C
E8
VDDQ
VDDQ
DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
DQ0 DQ1 DQ2 DQ3
C2
MEM_B_DQ<16>
B7
MEM_B_DQ<17>
D3
MEM_B_DQ<18>
D7
MEM_B_DQ<19>
D2
MEM_B_DQ<20>
D8
MEM_B_DQ<21>
E3
MEM_B_DQ<22>
E7
MEM_B_DQ<23>
C3
MEM_B_DQS_P<2>
B3
MEM_B_DQS_N<2>
A7
PP1V2_S3
A3
NC
L9
MEM_B_ALERT_L
24 7
128 120
120 26 25
26 25 24 7
120 26 25
120 26 25
120 26 25
120 26 25
26 25 24 7
120 26 25
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
26 25 24 7
120 26 25 24 7
24 25 117
120 26 25 24
120 26 25 24 7
120
26 25 24 7
7
120 26 25 24 7
120
24 7
128 120
24 7
128 120
24 7
128 120
24 7
128 120
120
24 7
128 120
128 120
120
7
120
26 25 24
C2537
0.47UF
20%
CERM-X5R-1
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0> MEM_B_BG<1>
MEM_B_PAR MEM_B_ACT_L
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2530
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
24 25 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
C2
MEM_B_DQ<24>
B7
MEM_B_DQ<25>
D3
MEM_B_DQ<26>
D7
MEM_B_DQ<27>
D2
MEM_B_DQ<28>
D8
MEM_B_DQ<29>
E3
MEM_B_DQ<30>
E7
MEM_B_DQ<31>
C3
MEM_B_DQS_P<3>
B3
MEM_B_DQS_N<3>
A7 A3
NC
L9
MEM_B_ALERT_L
120 128
117 24 25
120 25 7 24 26
D
128 120
128 120
128 120
128 120
128 120
128 120
128 120
120 128
120 128
C
120
25 24 7
26
120
25 24 7
26
120 25
MEM_B_CKE<0>
7 24 26
MEM_B_CS_L<0>
7 24 25
MEM_B_ODT<0>
26 120
120 25
MEM_B_CKE<1>
7 24 26
MEM_B_CS_L<1>
7 24 25
MEM_B_ODT<1>
26 120
26 24
MEM_RESET_L
22 23 25
120 25
MEM_B_CLK_P<0>
7 24 26
7
MEM_B_CLK_N<0>
24 25 26 120
G3 G7
F3
G2 G8
F2
L1
F7 F8
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS
C8
E1
VSS
E9
VSS
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
VSSQ
A2
VSSQ
A8
VSSQ
D1
VREFCA
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VSSQ
ZQ
B1
PP2V5_S3 PP2V5_S3 PP2V5_S3 PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_B
J1
G9
MEM_B_TEN
B9
MEM_B_ZQ<0> MEM_B_ZQ<1>
R2500
240
1%
1/20W
MF
201
C2508
0.047UF
2
1
10%
6.3V X5R 201
26 25 24 7
120 26 25 24 7
120 26 25 24 7
25 24
117
26 25 24 7
1
26 25 24 7
2
25 24 23 22
26 25 24 7
26 25 24 7
MEM_B_CKE<0>
120
MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CKE<1> MEM_B_CS_L<1>
120
MEM_B_ODT<1>
120
MEM_RESET_L
26
MEM_B_CLK_P<0>
120
MEM_B_CLK_N<0>
120
CKE
G3
CS*
G7
F3
ODT
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
L1
RESET*
CK_T
F7
CK_C
F8
VSS C8
VSS E1
VSS E9
VSS G1
VSS H9
VSS K1
VSS K9
VSS N1
VSSQ
VSSQ
A2
A8
VSSQ
VSSQ
D1
D9
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ A9
ZQ
B1 M9
J1
PP0V6_S3_MEM_VREFCA_B
G9
B9
R2510
1/20W
240
201
2
1% MF
1
C2518
0.047UF
10%
6.3V X5R 201
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
1
2
26 25 24 23 22
120 26 25 24 7
120 26 25 24 7
26 25 24 7
26 25 24 7
120
120
MEM_B_CKE<0> MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CKE<1> MEM_B_CS_L<1> MEM_B_ODT<1>
MEM_RESET_L
MEM_B_CLK_P<0> MEM_B_CLK_N<0>
G3 G7
F3
G2 G8
F2
L1
F7 F8
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS
C8
E1
VSS
E9
VSS
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
VSSQ
A2
VSSQ
A8
VSSQ
D1
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VREFCA
VSSQ
ZQ
B1 M9
J1
PP0V6_S3_MEM_VREFCA_B
G9
C2528
0.047UF
B9
MEM_B_ZQ<2>
240
1%
1/20W
MF
201
2
1
R2520
6.3V
10% X5R
201
1
2
120 26 25 24 7
120 26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
25 24 23 22
26 25 24 7
26 25 24 7
26
MEM_B_CKE<0>
120
MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CKE<1>
120
MEM_B_CS_L<1>
120
MEM_B_ODT<1>
120
MEM_RESET_L
MEM_B_CLK_P<0>
120
MEM_B_CLK_N<0>
120
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
VSS C8
VSS E1
VSS E9
VSS G1
VSS H9
VSS
VSS
K1
K9N1A2
VSS
VSSQ
VSSQ
A8
VSSQ
D1
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VREFCA
VSSQ
ZQ
B1 M9
J1
PP0V6_S3_MEM_VREFCA_B
G9
MEM_B_TENMEM_B_TENMEM_B_TEN
B9
MEM_B_ZQ<3>
R2530
1/20W
240
1% MF
201
C2538
0.047UF
2
1
10%
6.3V X5R 201
C
117 24 25
1
2
B
PP2V5_S3
C2550
PP1V2_S3
C2500
2.2UF
20%
6.3V
X5R-CERM
0201
PP1V2_S3
1.0UF
20%
6.3V X5R
0201-1
1
2
1
2
C2501
2.2UF
20%
6.3V
X5R-CERM
0201
C2551
1.0UF
20%
6.3V X5R
0201-1
24 25 117
1
2
C2502
24 25 117
24 25 117
1
2
2.2UF
20%
6.3V
X5R-CERM
0201
C2552
1.0UF
20%
6.3V X5R
0201-1
1
2
C2503
1
2
2.2UF
20%
6.3V
X5R-CERM
0201
C2553
1.0UF
20%
6.3V X5R
0201-1
1
2
C2510
1
2
2.2UF
20%
6.3V
X5R-CERM
0201
C2554
1.0UF
20%
6.3V X5R
0201-1
1
2
C2511
1
2
2.2UF
20%
6.3V
X5R-CERM
0201
Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)
C2555
1.0UF
20%
6.3V X5R
0201-1
1
C2556
1.0UF
2
0201-1
20%
6.3V X5R
1
2
C2557
1.0UF
20%
6.3V X5R
0201-1
1
2
C2558
1.0UF
20%
6.3V X5R
0201-1
1
2
C2559
1.0UF
20%
6.3V X5R
0201-1
1
2
C2560
1.0UF
20%
6.3V X5R
0201-1
1
2
C2561
1.0UF
20%
6.3V X5R
0201-1
1
2
VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)
1
2
C2512
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
C2513
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
1
C2504
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2505
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2506
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2570
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2509
0.1UF
10%
6.3V
2
CERM-X5R 0201
VDD/VDDQ Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
C2562
1.0UF
20%
6.3V X5R
0201-1
1
2
1
C2514
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2563
1.0UF
20%
6.3V X5R
0201-1
1
2
1
2
C2515
0.1UF
10%
6.3V CERM-X5R 0201
C2564
1.0UF
20%
6.3V X5R
0201-1
1
C2516
2
1
2
0.1UF
10%
6.3V CERM-X5R 0201
C2565
1.0UF
20%
6.3V X5R
0201-1
1
C2571
2
1
2
0.1UF
10%
6.3V CERM-X5R 0201
1
C2519
0.1UF
10%
6.3V
2
CERM-X5R 0201
B
A
C2520
2.2UF
6.3V
X5R-CERM
0201
PP1V2_S3
20%
1
2
1
2
C2521
2.2UF
X5R-CERM
C2580
0.1UF
10%
6.3V CERM-X5R 0201
1
20%
2
6.3V 0201
24 25 117
1
C2581
2
C2522
0.1UF
10%
6.3V CERM-X5R 0201
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2582
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2523
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2583
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2530
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2584
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2531
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2585
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2532
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2586
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2533
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2524
0.1UF
10%
2
6.3V CERM-X5R 0201
5x 0.1uF per chip
1
C2587
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2588
2
1
2
0.1UF
10%
6.3V CERM-X5R 0201
C2525
0.1UF
10%
6.3V CERM-X5R 0201
C2589
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2526
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2590
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2572
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2591
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2529
0.1UF
10%
2
6.3V CERM-X5R 0201
C2592
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2534
0.1UF
10%
2
6.3V CERM-X5R 0201
C2593
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2535
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2594
0.1UF
10%
6.3V CERM-X5R 0201
1
C2536
0.1UF
10%
2
6.3V CERM-X5R 0201
C2595
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2573
0.1UF
10%
2
6.3V CERM-X5R 0201
C2596
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2539
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2597
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2598
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2599
0.1UF
10%
6.3V
2
CERM-X5R 0201
BOM_COST_GROUP=DRAM
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
DDR4 SDRAM Channel B 1
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
25 OF 200
SHEET
24 OF 135
A
8
67
35 4
2
1
Vinafix.com
678
3 245
1
D
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
24 7 25
24 7
C
26 25
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 24 22 23 25
26 25 24 7
24 7
120 26 25
C2607
0.47UF
CERM-X5R-1
MEM_B_A<0>
120
MEM_B_A<1>
120
MEM_B_A<2>
120
MEM_B_A<3>
120
MEM_B_A<4>
120
MEM_B_A<5>
120
MEM_B_A<6>
120
MEM_B_A<7>
120
MEM_B_A<8>
120
MEM_B_A<9>
120
MEM_B_A<10>
120
MEM_B_A<11>
120
MEM_B_A<12>
120
MEM_B_A<13>
120
MEM_B_A<14>
120
MEM_B_A<15>
120
MEM_B_A<16>
120
MEM_B_BA<0>
120
MEM_B_BA<1>
120
MEM_B_BG<0>
120
MEM_B_BG<1>
120
120 26
MEM_B_PAR
120
MEM_B_ACT_L
MEM_B_CKE<0>
120
MEM_B_CS_L<0>
120
MEM_B_ODT<0>
120
MEM_B_CKE<1>
120
MEM_B_CS_L<1>
120
MEM_B_ODT<1>
120
MEM_RESET_L
MEM_B_CLK_P<0>
120
20%
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
G3 G7
F3
G2 G8
F2
L1
F7 F8
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS C8
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2600
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
VSS
VSS
VSS
K1
K9
VSS N1
VSS E1
VSS E9
VSS G1
H9
24 25 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A2
A8
D1
D9
A9
ZQ
C2
MEM_B_DQ<32>
B7
MEM_B_DQ<33>
D3
MEM_B_DQ<34>
D7
MEM_B_DQ<35>
D2
MEM_B_DQ<36>
D8
MEM_B_DQ<37>
E3
MEM_B_DQ<38>
E7
MEM_B_DQ<39>
C3
MEM_B_DQS_P<4>
B3
MEM_B_DQS_N<4>
A7
PP1V2_S3
A3
NC
L9
MEM_B_ALERT_L
B1
PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_B
J1
MEM_B_TEN
G9
B9
MEM_B_ZQ<4>
R2600
26
240
1%
1/20W
MF
201
25 24
0.047UF
2
1
C2608
10%
6.3V X5R 201
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
26 25 24 7
120 26 25 24 7
26 25 24 7
120 26 25 24 7
120
26 25 24 7
7
120 26 25 24 7
26 25 24 7
120 26 25 24 7
120 26 25 24 7
26 25 24 7
26 25 24 7
1
25 24 23 22
2
26 25 24 7
26 25 24 7
120
128 120
24 7
120 26 25
128 120
24 7
120 26 25
128 120
24 7
120 26 25
128 120
120
120
26 25 24
120
117 25 24
120
120
26
120
120
C2617
0.47UF
CERM-X5R-1
MEM_B_A<0>
120
MEM_B_A<1> MEM_B_A<2>
120
MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6>
120
MEM_B_A<7>
120
MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
MEM_B_BA<0>
120
MEM_B_BA<1> MEM_B_BG<0> MEM_B_BG<1>
MEM_B_PAR MEM_B_ACT_L
MEM_B_CKE<0> MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CS_L<1> MEM_B_ODT<1>
MEM_RESET_L
MEM_B_CLK_P<0> MEM_B_CLK_N<0>
20%
4V
201
1
2
NC
PP1V2_S3
C7F1F9H1J9M1N9A1B2B8C1C9E2
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
BA0
K2
BA1
K8
BG0
J2
BG1
J8
PAR
N3
ACT*
H3
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
C8
VDD
VDD
VDD
VDD
16GB-64X8X2-2400
OMIT_TABLE
VSS
E9
VSS
G1
VSS
H9
VSS
E1
VDD
VDD
VDD
VDD
U2610
MT40A2G8-NRE
FBGA
VSS
VSS
VSS
VSS
K1
K9
N1
24 25 117
E8
VDDQ
VDDQ
VSSQ
A8
VDDQ
VDDQ
NF/TDQS_C
VSSQ
VSSQ
A9
D1
D9
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
VPP0 VPP1
VREFCA
RFU/TEN
VSSQ
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VSSQ
A2
ZQ
PP1V2_S3
C2627
0.47UF
CERM-X5R-1
C2
MEM_B_DQ<40>
B7
MEM_B_DQ<41>
D3
MEM_B_DQ<42>
D7
MEM_B_DQ<43>
D2
MEM_B_DQ<44>
D8
MEM_B_DQ<45>
E3
MEM_B_DQ<46>
E7
MEM_B_DQ<47>
C3
MEM_B_DQS_P<5>
B3
MEM_B_DQS_N<5> MEM_B_DQS_N<6>
A7
PP1V2_S3 PP1V2_S3
A3
NC
L9
MEM_B_ALERT_L
B1
PP2V5_S3 PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_B
J1
2
1% MF
1
C2618
0.047UF
10%
6.3V X5R 201
MEM_B_TEN MEM_B_TEN MEM_B_TEN
G9
B9
24 25 26
MEM_B_ZQ<5> MEM_B_ZQ<6>
R2610
240
1/20W
201
26 25 24 7 128 120
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
128 120
128 120 128 120
120 26 25 24
120 26 25 24 7
26 25 24 7
120 26 25 24 7
26 25 24
120
120 26 25 24 7
26 25 24 7
120 26 25 24 7
120 26 25 24 7
26 25 24 7
26 25 24 7
1
26 25 24 7
2
25 24 23 22
26 25 24 7
26 25 24 7
MEM_B_A<0> MEM_B_DQ<48>
120
MEM_B_A<1>
120
MEM_B_A<2>
120
MEM_B_A<3>
120
MEM_B_A<4>
120
MEM_B_A<5>
120
MEM_B_A<6>
120
MEM_B_A<7>
120
MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
7
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0>
120
MEM_B_BG<1>
120 7
26 25 24 7
MEM_B_PAR MEM_B_ACT_L
MEM_B_CKE<0>
120
MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CKE<1>
120
MEM_B_CS_L<1>
120
MEM_B_ODT<1>
120
MEM_RESET_L
26
MEM_B_CLK_P<0>
120
MEM_B_CLK_N<0>
120
20%
4V
201
NC
1
2
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
K2
BA0
K8
BA1
J2
BG0
J8
BG1
PAR
N3
ACT*
H3
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
16GB-64X8X2-2400
OMIT_TABLE
VSS
VSS
VSS
E1
E9
C8
U2620
MT40A2G8-NRE
VSS
VSS
VSS
K1
H9
G1
FBGA
VSS K9
24 25 117
VDD
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VSSQ
VSS
A2
N1
VDDQ
VSSQ
VSSQ
A8
D1
VDDQ
NF/TDQS_C
VSSQ D9
E8
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
ZQ
VSSQ A9
C2 B7
MEM_B_DQ<49>
D3
MEM_B_DQ<50>
D7
MEM_B_DQ<51>
D2
MEM_B_DQ<52>
D8
MEM_B_DQ<53>
E3
MEM_B_DQ<54>
E7
MEM_B_DQ<55>
C3
MEM_B_DQS_P<6>
B3
A7 A3
NC
L9
MEM_B_ALERT_L
B1 M9
J1
PP0V6_S3_MEM_VREFCA_BMEM_B_CKE<1>
G9
B9
R2620
1/20W
24 25 26
240
1% MF
201
C2628
0.047UF
2
1
10%
6.3V X5R 201
120 26 25
128 120
120 26 25
128 120
120 26 25
128 120
120 26 25
128 120
120 26 25
128 120
120 26 25
128 120
120 26 25
128 120
120 26 25
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
128 120
120 26 25
120 26 25 24 7
24 25 117
120 26 25 24
120 26 25 24 7
120
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
1
2
26 25 24 23 22
120 26 25 24 7
120 26 25 24 7
26 25 24
24 25 117
120 26 25 24
26 25 24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
26 25 24 7
C2637
0.47UF
20%
CERM-X5R-1
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0>
7
MEM_B_BG<1>
120
MEM_B_PAR
7
MEM_B_ACT_L
MEM_B_CKE<0>
7
MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CKE<1> MEM_B_CS_L<1> MEM_B_ODT<1>
120
MEM_RESET_L
MEM_B_CLK_P<0> MEM_B_CLK_N<0>MEM_B_CLK_N<0>
201
NC
4V
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
G3 G7
F3
G2 G8
F2
L1
F7 F8
C7F1F9H1J9M1N9
VDD
VDD
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
C8
OMIT_TABLE
VSS
VSS
VSS
E1
E9
24 25 117
A1B2B8C1C9E2E8
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
U2630
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
NF/DM*/DBI*/TDQS_T
VSSQ
VSSQ
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
A2
A8
VSSQ
D1
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/TDQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ
VSSQ
A9
D9
ZQ
MEM_B_DQ<56>
C2
MEM_B_DQ<57>
B7
MEM_B_DQ<58>
D3
MEM_B_DQ<59>
D7
MEM_B_DQ<60>
D2
MEM_B_DQ<61>
D8
MEM_B_DQ<62>
E3
MEM_B_DQ<63>
E7
MEM_B_DQS_P<7>
C3
MEM_B_DQS_N<7>
B3
PP1V2_S3
A7 A3
NC
MEM_B_ALERT_L
L9
B1
PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_B
J1
G9
MEM_B_ZQ<7>
B9
R2630
24 25 26
240
1%
1/20W
MF
201
C2638
0.047UF
2
1
10%
6.3V X5R 201
1
2
D
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
24 25 117
120 25 7 24 26
C
24 25 117
25 24
117
B
PP2V5_S3
C2650
1.0UF
20%
6.3V X5R
0201-1
PP1V2_S3
C2600
2.2UF
20%
6.3V
X5R-CERM
0201
PP1V2_S3
24 25 117
1
C2651
1.0UF
2
0201-1
1
2
C2601
2.2UF
X5R-CERM
20%
6.3V X5R
20%
6.3V 0201
1
2
24 25 117
1
2
24 25 117
C2652
1.0UF
20%
6.3V X5R
0201-1
C2602
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
2
C2653
1.0UF
20%
6.3V X5R
0201-1
C2603
2.2UF
20%
6.3V
X5R-CERM
0201
1
C2654
1.0UF
2
0201-1
1
2
C2610
2.2UF
X5R-CERM
20%
6.3V X5R
20%
6.3V 0201
1
C2655
1.0UF
2
1
2
C2611
6.3V
0201-1
2.2UF
20%
6.3V
X5R-CERM
0201
Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)
20% X5R
1
C2656
1.0UF
2
0201-1
20%
6.3V X5R
1
C2657
1.0UF
2
20%
6.3V X5R
0201-1
1
C2658
1.0UF
2
0201-1
20%
6.3V X5R
1
C2659
1.0UF
2
0201-1
20%
6.3V X5R
1
C2660
1.0UF
2
0201-1
20%
6.3V X5R
1
C2661
1.0UF
2
0201-1
20%
6.3V X5R
1
2
C2662
VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)
1
C2604
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2613
2.2UF
X5R-CERM
1
2
C2612
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
1
C2605
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2606
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2670
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2609
2
VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)
1.0UF
20%
6.3V X5R
0201-1
0.1UF
10%
6.3V CERM-X5R 0201
1
C2663
1.0UF
2
0201-1
1
C2614
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
1
C2664
1.0UF
2
0201-1
1
C2615
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
1
2
C2665
1.0UF
0201-1
1
C2616
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
1
2
1
C2671
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2619
0.1UF
10%
6.3V
2
CERM-X5R 0201
B
A
C2620
PP1V2_S3
2.2UF
20%
6.3V
X5R-CERM
0201
C2680
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2621
2.2UF
6.3V
X5R-CERM
0201
24 25 117
C2681
1
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
1
2
C2622
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
C2623
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
C2630
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
C2631
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
C2632
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
C2633
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
1
C2624
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2625
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2626
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2672
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2629
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2634
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2635
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2636
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2673
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2639
0.1UF
10%
6.3V
2
CERM-X5R 0201
5x 0.1uF per chip
A
D
C2682
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2683
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2684
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2685
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2686
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2687
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2688
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2689
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2690
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2691
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2692
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2693
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2694
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2695
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2696
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2697
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2698
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2699
1
0.1UF
10%
2
6.3V CERM-X5R 0201
BOM_COST_GROUP=DRAM
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
DDR4 SDRAM Channel B 2
SIZE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
26 OF 200
SHEET
25 OF 135
8
67
35 4
2
1
Vinafix.com
678
3 245
1
JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
D
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
PP0V6_S0_DDRVTT
26 117
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN IN IN IN
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3>
MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7>
MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11>
MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>
R2700 R2701 R2702 R2703
R2704 R2705 R2706 R2707
R2708 R2709 R2710 R2711
R2712 R2713 R2714 R2715
36 36 36 36
36 36 36
36 36
36 36 36
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
5%
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
201MF1/20W 1/20W 2015% 1/20W 2015% 1/20W36MF 2015%
1/20W36MF 2015% 1/20W MF362015%
MF MF
MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
201MF5%361/20W
C2701,C2721 FOR DESENSE IMPROVEMENT LOCATION DEPENDS ON DESENSE TEAM
C2701
C2700
1
2.2UF
20% 4V
2
X5R-CERM 0201
C2702
1
2.2UF
20% 4V
2
X5R-CERM 0201
C2704
1
2.2UF
20% 4V
2
X5R-CERM 0201
1
12PF
5%
2
NP0-C0G 0201 25V
C2703
1
2.2UF
20% 4V
2
X5R-CERM 0201
C2705
1
0.47UF
20% 4V
2
CERM-X5R-1 201
D
C
23 22
MEM_A_TEN
25 24
MEM_B_TEN
1
R2753
100
5% 1/20W MF 201
2
1
R2755
100
5% 1/20W MF 201
2
R2752
0
1 2
5%
1/20W
MF
0201
R2754
0
1 2
5%
1/20W
MF
0201
MEM_A_TEN_R
NOSTUFF
C2752
1
0.47UF
20% 4V
2
CERM-X5R-1 201
MEM_B_TEN_R
NOSTUFF
C2753
1
0.47UF
20% 4V
2
CERM-X5R-1 201
TP2700
1
TP
TP2701
1
TP
TP-P5
TP-P5
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN
MEM_A_A<16> MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0>
MEM_A_BG<1> MEM_A_CS_L<0> MEM_A_CS_L<1> MEM_A_CKE<0>
MEM_A_CKE<1> MEM_A_ODT<0> MEM_A_ODT<1> MEM_A_ACT_L
MEM_A_PAR
R2716 R2717 R2718 R2719
R2720 R2721 R2722 R2723
R2724 R2725 R2726 R2727
R2728
36 36 36
36 36 36 36
36 36 36 36
36
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2
26 117
PP0V6_S0_DDRVTT
C2707
C2706
1/20W36MF 2015%
201
MF1/20W5%
201
MF1/20W5% MF1/20W 2015%
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015%
1
0.47UF
20% 4V
2
CERM-X5R-1 201
C2708
1
0.47UF
20% 4V
2
CERM-X5R-1 201
C2710
1
0.47UF
20% 4V
2
CERM-X5R-1 201
1
0.47UF
20% 4V
2
CERM-X5R-1 201
1
C2711
2.2UF
20% 4V
2
X5R-CERM 0201
1
C2712
2.2UF
20% 4V
2
X5R-CERM 0201
C
B
120 23 22 7
120 23 22 7
120 25 24 7
120 25 24 7
7 120
7 120
7 120
7 120
7 120
7 120
7 120
7 120
MEM Clock Termination
Place RC end termination after last DRAM Place Source Cterm at neckdown at first DRAM
IN
IN
IN
IN
NC_MEM_A_CLK_N<1> NC_MEM_A_CLK_P<1> NC_MEM_A_CKE<2> NC_MEM_A_CKE<3> NC_MEM_B_CLK_N<1> NC_MEM_B_CLK_P<1> NC_MEM_B_CKE<2> NC_MEM_B_CKE<3>
MEM_A_CLK_N<0>
C2750
NOSTUFF
MEM_A_CLK_P<0>
NOSTUFF
MEM_B_CLK_P<0>
3300PF
10% 10V X7R-CERM 0201
C2760
3300PF
10% 10V X7R-CERM 0201
1
PLACE_NEAR=U2430.F8:10mm
2
PLACE_NEAR=U2630.F8:10mm
1
2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK_N<1> NC_MEM_A_CLK_P<1> NC_MEM_A_CKE<2> NC_MEM_A_CKE<3> NC_MEM_B_CLK_N<1> NC_MEM_B_CLK_P<1> NC_MEM_B_CKE<2> NC_MEM_B_CKE<3>
PLACE_NEAR=U2430.F8:8mm
PLACE_NEAR=U2430.F7:8mm
PLACE_NEAR=U2630.F8:8mm
PLACE_NEAR=U2630.F7:8mm
R2750
30
1 2
5%
1/20W
MF
201
R2751
30
1 2
5%
1/20W
MF
201
R2760
30
1 2
5%
1/20W
MF
201
R2761
30
1 2
5%
1/20W
MF
201
MEM_A_CLK0_TERM_R
MEM_B_CLK0_TERM_RMEM_B_CLK_N<0>
C2751
0.01UF
1 2
10% 25V
X5R-CERM
0201
C2761
0.01UF
1 2
10% 25V
X5R-CERM
0201
PP0V6_S0_DDRVTT
PP0V6_S0_DDRVTT
26 117
26 117
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3>
MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7>
MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11>
MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>
MEM_B_A<16> MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0>
MEM_B_BG<1> MEM_B_CS_L<0> MEM_B_CS_L<1> MEM_B_CKE<0>
MEM_B_CKE<1> MEM_B_ODT<0> MEM_B_ODT<1> MEM_B_ACT_L
MEM_B_PAR
R2770 R2771 R2772 R2773
R2774 R2775 R2776 R2777
R2778 R2779 R2780 R2781
R2782 R2783 R2784 R2785
R2786 R2787 R2788 R2789
R2790 R2791 R2792 R2793
R2794 R2795 R2796 R2797
R2798
36 36 36 36
36 36 36 36
36 36 36
36 36 36
36 36 36
36 36 36 36
36 36 36 36
36
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015% MF MF1/20W 2015%
MF5% MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015%
MF1/20W
MF1/20W 2015% MF MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015%
201MF
201
201
2015%
1/20W5%
1/20W 2015%
1/20W36MF 2015%
1/20W 201
1/20W36MF 2015%
5% MF
1/20W 201
5% MF1/20W
1/20W5% MF
5%361/20W MF 201
1/20W MF 2015% 1/20W 201MF5%
1/20W 2015%
C2720
1
2.2UF
20% 4V
2
X5R-CERM 0201
C2722
1
2.2UF
20% 4V
2
X5R-CERM 0201
1
C2724
2.2UF
20% 4V
2
X5R-CERM 0201
C2726
1
0.47UF
20% 4V
2
CERM-X5R-1 201
C2728
1
0.47UF
20% 4V
2
CERM-X5R-1 201
C2730
1
0.47UF
20% 4V
2
CERM-X5R-1 201
C2721
1
12PF
5%
2
NP0-C0G 0201 25V
C2723
1
2.2UF
20% 4V
2
X5R-CERM 0201
1
C2725
0.47UF
20%
2
4V CERM-X5R-1 201
C2727
1
0.47UF
20% 4V
2
CERM-X5R-1 201
1
C2734
2.2UF
20% 4V
2
X5R-CERM 0201
1
C2735
2.2UF
20% 4V
2
X5R-CERM 0201
B
A
8
PP1V2_S3
470
1%
1/20W
MF
201
1
2
120 23 22 7
120 25 24 7
12
R2730
IN IN
IN
MEM_A_ALERT_L MEM_B_ALERT_L
PCH_DRAM_RESET_L
1
51
1%
1/20W
MF
201
2
R2732
0
1 2
5%
1/20W
MF
0201
R2731
51
1%
1/20W
MF
201
1
2
R2733
BOM_COST_GROUP=DRAM
67
35 4
22 23 117
MEM_RESET_L
NOSTUFF
1
C2732
0.1UF
10%
6.3V CERM-X5R
2
0201
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
DDR4 Termination
DRAWING NUMBER
25 24 23 22
Apple Inc.
051-04492
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
27 OF 200
SHEET
26 OF 135
1
SIZE
D
Vinafix.com
678
3 245
1
D
C
B
A
1
R2890
3.3K
5% 1/20W MF 201
2
TBT_X_SPI_CLK TBT_X_SPI_MOSI
29 29
TBT_X_SPI_CS_L
29
123 27
TBT_X_ROM_WP_L
TBT_X_ROM_HOLD_L
120 97
120 97
120 97
120 97
120 97
120 97
120 97
120 97
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
DP_X_SNK0_ML_C_P<0>
DP_X_SNK0_ML_C_N<0>
DP_X_SNK0_ML_C_P<1>
DP_X_SNK0_ML_C_N<1>
DP_X_SNK0_ML_C_P<2>
DP_X_SNK0_ML_C_N<2>
DP_X_SNK0_ML_C_P<3> DP_X_SNK0_ML_P<3>
DP_X_SNK0_ML_C_N<3>
DP_X_SNK0_AUXCH_C_P
DP_X_SNK0_AUXCH_C_N DP_X_SNK0_AUXCH_N
DP_X_SNK1_ML_C_P<0>
DP_X_SNK1_ML_C_N<0>
DP_X_SNK1_ML_C_P<1>
DP_X_SNK1_ML_C_N<1>
DP_X_SNK1_ML_C_P<2>
DP_X_SNK1_ML_C_N<2>
DP_X_SNK1_ML_C_P<3>
DP_X_SNK1_ML_C_N<3>
DP_X_SNK1_AUXCH_C_P DP_X_SNK1_AUXCH_P
DP_X_SNK1_AUXCH_C_N
100K
1 2
10K
1 2
NOSTUFF
100K
1 2
100K
1 2
100K
1 2
100K
1 2
100K
1 2
100K
1 2
R2891
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
R2864 R2839
PU for NVM
R2863
5% 1/20W 201MF
R2873 R2862 R2872 R2860 R2861
1
3.3K
5%
1/20W
MF
201
1
2
R2893
3.3K
5% 1/20W MF 201
2
6
CLK
1
CS*
3
WP*(IO2)
7
HOLD*(IO3)
SNK0 AC Coupling
C2820
0.22UF
C2821
0.22UF
C2822
0.22UF
C2823
0.22UF
C2824
0.22UF
C2825
0.22UF
C2826
0.22UF
C2827
0.22UF
C2828
0.22UF
C2829
0.22UF
SNK1 AC Coupling
C2830
0.22UF
C2831
0.22UF
C2832
0.22UF
C2833
0.22UF
C2834
0.22UF
C2835
0.22UF
C2836
0.22UF
C2837
0.22UF
C2838
0.22UF
C2839
0.22UF
PP3V3_TBT_X_SX
TBT_X_BATLOW_L
201MF1/20W5%
201MF1/20W5%
TBT_X_TMU_CLK_IN
TBT_X_TMU_CLK_OUT
201MF1/20W5%
DP_XA_HPD
201MF1/20W5%
DP_XB_HPD
201MF1/20W5%
TBT_XA_USB2_MXCTL
201MF1/20W5%
TBT_XB_USB2_MXCTL
201MF1/20W5%
PP3V3_UPC_XB_LDO
8
VCC
U2890
8MBIT-3.0V
W25Q80DVUXIE
USON
OMIT_TABLE
CRITICAL
GND EPAD
4
9
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
6.3V20%
X5R
6.3V20%
X5R
6.3V20%
X5R
6.3V20%
X5R
20% 6.3V X5R
6.3V20%
X5R
6.3V 0201
20% X5R
X5R
20% 6.3V X5R
20% X5R
6.3V20%
X5R
6.3V20%
X5R
6.3V20%
X5R
6.3V20%
X5R
6.3V 020120%
X5R
6.3V20%
X5R
6.3V20%
X5R
6.3V20%
X5R
20% 6.3V X5R
6.3V
X5R
28 29
1
2
TBT_X_SPI_MISO
5%
1/20W
MF
201
5 2
1
2
R2892
3.3K
DI(IO0)
DO(IO1)
DP_X_SNK0_ML_P<0>
0201
DP_X_SNK0_ML_N<0>
0201
DP_X_SNK0_ML_P<1>
0201
DP_X_SNK0_ML_N<1>
0201
DP_X_SNK0_ML_P<2>
0201
DP_X_SNK0_ML_N<2>
0201
DP_X_SNK0_ML_N<3>
02016.3V20%
DP_X_SNK0_AUXCH_P
0201
02016.3V
DP_X_SNK1_ML_P<0>
0201
DP_X_SNK1_ML_N<0>
0201
DP_X_SNK1_ML_P<1>
0201
DP_X_SNK1_ML_N<1>
0201
DP_X_SNK1_ML_P<2>
DP_X_SNK1_ML_N<2>
0201
DP_X_SNK1_ML_P<3>
0201
DP_X_SNK1_ML_N<3>
0201
0201
DP_X_SNK1_AUXCH_N
020120%
27
27
27
120 30 27
120 31 27
27
27
27 29
C2890
1UF
10%
6.3V CERM 402
120 33
120 33
120 33
120 33
IN IN
IN IN
PCIE_TBT_X_R2D_P<0> PCIE_TBT_X_R2D_N<0>
PCIE_TBT_X_R2D_P<1> PCIE_TBT_X_R2D_N<1>
Y23 Y22
T23 T22
PCIE_RX0_P PCIE_RX0_N
PCIE_RX1_P PCIE_RX1_N
U2800
TITAN-RIDGE-DP
CSP
SYM 1 OF 2
OMIT_TABLE
PCIE_TX0_P PCIE_TX0_N
PCIE_TX1_P PCIE_TX1_N
V23 V22
P23 P22
CRITICAL
29
R2828
120 19 12
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
OUT
79 33 29 27
TBT_X_CLKREQ_L
120 95
120 95
1
R2825
100
5% 1/20W MF 201
2
PP3V3_TBT_X_SX
33 29
OUT
R2830
100K
1/20W
OUT
R2831
100K
1/20W
IN
1K
1 2
5%
1/20W
MF
201
1
5% MF
201
2
1
5% MF
201
2
123 107 18 14
123 107 18 14
1
R2829
100
5% 1/20W MF 201
2
NOSTUFF
1
R2836
2.2K
5% 1/20W MF 201
2
120 33
120 33
120 33
120 33
123 120 12
123 120 12
123 15
123 107 18
120 32
120 32
120 32
120 32
120 32
120 32
120 32
120 30 27
IN IN
IN IN
IN IN
IN IN IN
OUT
IN IN
OUT OUT
OUT OUT
IN IN
BI BI
IN
PCIE_TBT_X_R2D_P<2> PCIE_TBT_X_R2D_N<2>
PCIE_TBT_X_R2D_P<3> PCIE_TBT_X_R2D_N<3>
PCIE_CLK100M_TBT_X_P PCIE_CLK100M_TBT_X_N TBT_X_CLKREQ_R_L
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
DP_X_SNK0_ML_P<0> DP_X_SNK0_ML_N<0>
DP_X_SNK0_ML_P<1> DP_X_SNK0_ML_N<1>
DP_X_SNK0_ML_P<2> DP_X_SNK0_ML_N<2>
DP_X_SNK0_ML_P<3> DP_X_SNK0_ML_N<3>
DP_X_SNK0_AUXCH_P DP_X_SNK0_AUXCH_N DP_X_SNK0_HPD
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
DP_X_SNK1_ML_P<0> DP_X_SNK1_ML_N<0>
DP_X_SNK1_ML_P<1> DP_X_SNK1_ML_N<1>
DP_X_SNK1_ML_P<2> DP_X_SNK1_ML_N<2>
DP_X_SNK1_ML_P<3> DP_X_SNK1_ML_N<3>
DP_X_SNK1_AUXCH_P DP_X_SNK1_AUXCH_N DP_X_SNK1_HPD
JTAG_ISP_TDI JTAG_TBT_X_TMS JTAG_ISP_TCK JTAG_ISP_TDO
TBT_X_TEST_EN TBT_X_TEST_PWR_GOOD
USBC_XA_D2R_P<2> USBC_XA_D2R_N<2>
USBC_XA_R2D_CR_P<2> USBC_XA_R2D_CR_N<2>
USBC_XA_R2D_CR_P<1> USBC_XA_R2D_CR_N<1>
USBC_XA_D2R_P<1> USBC_XA_D2R_N<1>
USBC_XA_AUXLSX1 USBC_XA_AUXLSX2
DP_XA_HPD I2C_TBT_XA_INT_L TBT_XA_USB2_MXCTL
27
NC NC NC NC
NC NC
TBT_XA_USB2_RBIAS
PLACE_NEAR=U2800.H19:3MM
R2854
200
1/20W
PLACE_NEAR=U2800.H6:2MM PLACE_NEAR=U2800.J6:2MM
1% MF
201
1
TBT_X_RBIAS
2
1 2
TF 1/20W
R2855
4.75K
0.5% 0201
TBT_X_RSENSE
M23 M22
H23 H22
V19
T19
AC7
AB7
AB9 AC9
AC11 AB11
AB13 AC13
AA2
AC5 AB5 AC3 AB3
W20
Y20
W19
Y19
A15 B15
A17 B17
A19 B19
B21 A21
E20 D20
H19
A23
AC23
AC1
PCIE_RX2_P PCIE_RX2_N
PCIE_RX3_P PCIE_RX3_N
PCIE_REFCLK_100_IN_P PCIE_REFCLK_100_IN_N
Y6 N16
PCIE_CLKREQ*
DPSNK1_ML0_P DPSNK1_ML0_N
DPSNK1_ML1_P DPSNK1_ML1_N
DPSNK1_ML2_P DPSNK1_ML2_N
DPSNK1_ML3_P DPSNK1_ML3_N
N1
DPSNK1_AUX_P
N2
DPSNK1_AUX_N
SNK1_HPD
A5
DPSNK2_ML0_P
B5
DPSNK2_ML0_N
B3
DPSNK2_ML1_P
A3
DPSNK2_ML1_N
C2
DPSNK2_ML2_P
C1
DPSNK2_ML2_N
E2
DPSNK2_ML3_P
E1
DPSNK2_ML3_N
P1
DPSNK2_AUX_P
P2
DPSNK2_AUX_N
Y4
SNK2_HPD
U0_SSTXP1 U0_SSTXN1 U0_SSRXP1 U0_SSRXN1
TDI TMS TCK TDO
R4
TEST_EN
W5
TEST_PWR_GOOD ASSRXP2
ASSRXN2 ASSTXP2
ASSTXN2 ASSTXP1
ASSTXN1 ASSRXP1
ASSRXN1
H4
ASBU1
J4
ASBU2 PA_USB2_D_P
PA_USB2_D_N
T2
PA_HPD
M4
PA_I2C_INT
R2
PA_USB2_MXCTL PA_USB2_RBIAS
J6
RBIAS
J5
RSENSE
PA_MONDC
A1
PB_MONDC PC_MONDC USB_MONDC
D4
TEST_EDM
L8
FUSE_VQPS_64
SINK PORT 1SINK PORT 2
USBSSJTAG
PCIE GEN3
TBT PORT A
DEBUG
SOURCE PORT
LC GPIOPOC GPIOFLASH
TBT PORT B
PCIE_TX2_P PCIE_TX2_N
PCIE_TX3_P PCIE_TX3_N
PERST*
PCIE_RBIAS
DPSRC_ML0_P DPSRC_ML0_N
DPSRC_ML1_P DPSRC_ML1_N
DPSRC_ML2_P DPSRC_ML2_N
DPSRC_ML3_P DPSRC_ML3_N
DPSRC_AUX_P DPSRC_AUX_N
DPSRC_HPD
GPIO_0 GPIO_1 EE_WP*
TMU_CLKOUT
WAKE*
CIO_PLUG_EVENT*
TMU_CLKIN
I2C_SCL
I2C_SDA
USB_FORCE_PWR
FORCE_PWR
BATLOW*
SLP_S3*
RTD3_PWR_EN
RESET*
XTAL_25_IN
XTAL_25_OUT
EE_DI
EE_DO
EE_CS*
EE_CLK
BSSRXp2 BSSRXn2
BSSTXp2 BSSTXn2
BSSTXp1 BSSTXn1
BSSRXp1 BSSRXn1
BSBU1 BSBU2
PB_USB2_D_P
PB_USB2_D_N
PB_HPD
PB_I2C_INT
PB_USB2_MXCTL
PB_USB2_RBIAS
USB2_ATEST
PCIE_ATEST
MONDC_SVR
VGA_RES
ATEST_P ATEST_N
THERMDA
K23 K22
F23 F22
T4
AB21 AC21
AC19 AB19
AB17 AC17
AC15 AB15
N4 N5
R5
W1 W2
W4 Y1 Y2 AA1 W6
V2 V1 V5 V4 U2 U1 T5
E5 D22
D23 Y18
W16 W18 Y16
B7 A7
A9 B9
A11 B11
A13 B13
L4 L5
E19 D19
T1
M5 R1 F19
B23
AB23
D5
H5
J9
J11
V8
PCIE_TBT_X_D2R_C_P<0> PCIE_TBT_X_D2R_C_N<0>
PCIE_TBT_X_D2R_C_P<1> PCIE_TBT_X_D2R_C_N<1>
PCIE_TBT_X_D2R_C_P<2> PCIE_TBT_X_D2R_C_N<2>
PCIE_TBT_X_D2R_C_P<3> PCIE_TBT_X_D2R_C_N<3>
TBT_X_PCI_RESET_L TBT_X_PCIE_BIAS
NC_DP_X_SRC_ML_P<0> NC_DP_X_SRC_ML_N<0>
NC_DP_X_SRC_ML_P<1> NC_DP_X_SRC_ML_N<1>
NC_DP_X_SRC_ML_P<2> NC_DP_X_SRC_ML_N<2>
NC_DP_X_SRC_ML_P<3> NC_DP_X_SRC_ML_N<3>
NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N
DP_X_SRC_HPD
TBT_X_HDMI_DDC_DATA
TBT_X_HDMI_DDC_CLK TBT_X_ROM_WP_L TBT_X_TMU_CLK_OUT TBT_WAKE_3V3_L TBT_X_PLUG_EVENT_L TBT_X_TMU_CLK_IN
I2C_TBT_X_SCL I2C_TBT_X_SDA TBT_X_USB_PWR_EN TBT_X_CIO_PWR_EN TBT_X_BATLOW_L PM_SLP_S3_L TBT_X_RTD3_PWR_EN
USBC_X_RESET_L TBT_X_XTAL25M_IN
TBT_X_XTAL25M_OUT UPC_X_SPI_MOSI
UPC_X_SPI_MISO UPC_X_SPI_CS_L UPC_X_SPI_CLK
29
29
29
29
To SPI Flash
USBC_XB_D2R_P<2> USBC_XB_D2R_N<2>
USBC_XB_R2D_CR_P<2> USBC_XB_R2D_CR_N<2>
USBC_XB_R2D_CR_P<1> USBC_XB_R2D_CR_N<1>
USBC_XB_D2R_P<1> USBC_XB_D2R_N<1>
USBC_XB_AUXLSX1 USBC_XB_AUXLSX2
NC NC
DP_XB_HPD
IN
BI BI
120
31 27
120 31 120 30
I2C_TBT_XB_INT_L TBT_XB_USB2_MXCTL
27
TBT_XB_USB2_RBIAS
PLACE_NEAR=U2800.F19:3MM 1
R2853
200
1%
NC NC
NC NC
NC
TBTTHMSNS_X_D1_P
USE NEAREST GND BALL (AC22) FOR THERM_D_N
1/20W MF 201
2
OUT
BOM_COST_GROUP=TBT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
IN
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
29
OUT OUT
27
OUT OUT
IN IN
27
IN
IN
IN
OUT
IN IN
OUT OUT
OUT OUT
IN IN
PP3V3_TBT_X_SX
NOSTUFF
1
R2837
2.2K
5% 1/20W MF 201
2
57
120 33
120 33
120 33
120 33
120 33
120 33
120 33
120 33
PLACE_NEAR=U2800.N16:2MM
33 20 14
29
29
29
29
29
29
29
29
29
29
29
29
123 27
33 14
27
PU at PCH
33 29
120 29
120 29
120 32
120 32
120 32
120 32
120 32
120 32
120 32
120 32
IN
33 29
SYNC_MASTER=YANIR SYNC_DATE=01/17/2019
PAGE TITLE
R2851
3.01K
1 2
113 107 33 29
33 31 30 14
33 31 30 14
135 121 107 14 12
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
1%
1/20W
MF
201
PP3V3_UPC_XB_LDO
1
R2834
2.2K
5% 1/20W MF 201
2
1
R2835
2.2K
5% 1/20W MF 201
2
BI BI
79 33 29 27
33 29
33 29
PP3V3_TBT_X_SX
1
R2827
100K
5% 1/20W MF 201
2
USB-C HIGH SPEED 1
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
BRANCH
PAGE
28 OF 200
SHEET
27 OF 135
27 29
SIZE
D
33 27 29 79
D
C
B
A
8
67
35 4
2
1
Vinafix.com
678
3 245
1
D
C
B
A
C2930
1
4UF
20%
6.3V
2
CER-X5R 0201
1
C2931
4UF
20%
2
6.3V CER-X5R 0201
SOURCED BY INTERNAL SWITCH
1
C2932
2
C2968
1
10UF
20%
2
6.3V CERM-X5R 0402-4
1
C2984
1.0UF
20%
6.3V X5R
2
0201-1
4UF
20%
6.3V CER-X5R 0201
1
C2933
4UF
20%
2
6.3V CER-X5R 0201
C2964
1
1.0UF
20%
2
6.3V X5R 0201-1
1
C2985
1.0UF
20%
6.3V X5R
2
0201-1
SOURCED BY INTERNAL SWITCH
1
C2934
4UF
20%
6.3V
2
CER-X5R 0201
C2965
1
1.0UF
20%
2
6.3V X5R 0201-1
SOURCED BY INTERNAL SWITCH
1
C2935
4UF
20%
2
6.3V CER-X5R 0201
SOURCED BY INTERNAL SWITCH
C2966
1
1.0UF
20%
6.3V
2
X5R 0201-1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
1
2
VOLTAGE=3.3V
C2920
1.0UF
20%
6.3V X5R 0201-1
1
C2936
4UF
20%
6.3V
2
CER-X5R 0201
C2967
1
1.0UF
20%
2
6.3V X5R 0201-1
PP0V9_TBT_X_SVR
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
PP0V9_TBT_X_PCIE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V
PP3V3_TBT_X_ANA PP3V3_TBT_X_ANA_PCIE PP3V3_TBT_X_ANA_USB2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V
1
C2921
1.0UF
20%
2
6.3V X5R 0201-1
SOURCED BY INTERNAL SWITCH
H11
H9 H12 H13 H15 H16
T12 T13 T15
N6
T11
T9
E8 J18 L19
M19
L18
M18 M16
E16
L16
H18
W11
Y11
Y5
W12
Y12
Y8
AB4
AC4
C23 C22
W13
AB2
D6
W15
Y15
A4
B4
F2
D2
F1
D1
B1
B2
E18 V11 V12 V13
M6 N19 N18 E12 E13
F11 F12 F13 F15
J16
A2 F8 A6 A8 B8
AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22
AC6 AC8
B10 AC10 AC12 AC14 AC16 AC18 AC20 AC22
B12
B14
B16
B18
B20
B22
D8
D9 A10 D11 D12
VCC0P9_SVR_PAB_ANA
VCC0P9_SVR_PC_ANA
VCC0P9_SVR_DPAUX_ANA
VCC0P9_SVR_USB_ANA
VCC0P9_SVR_BRD_SENSE VCC0P9_PCIE
VCC0P9_ANA_PCIE_1
VCC0P9_ANA_PCIE_2
VCC3P3_ANA VCC3P3_ANA_PCIE VCC3P3_ANA_USB2
VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA
VSS
N15
VSS
L15
VSS
V18
VSS F4
VSS R9
VSS
R12
U2800
TITAN-RIDGE-DP
VSS
L12
CSP
SYM 2 OF 2
OMIT_TABLE
CRITICAL
VCC
VSS
VSS
VSS
VSS
VSS
VSS
L9
M9
M1
M15
R15
VSS M2
VCC3P3_LC
VCC3P3_SX
VCC3P3_S0
VCC3P3A
VCC3P3_SVR
VCC0P9_SVR
SVR_IND
SVR_VSS
VCC0P9_LC
VCC0P9_LVR
VCC0P9_LVR_SENSE
VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA
VSS
VSS
VSS
VSS
VSS
VSS
T6
V16
M12
N9
N12
T18
V6 F18
R6 L6 E6 G1
G2 H2
R8 R11 L11 M8 M13 R16 R13 J13 L13
124 28
N8 N11 N13 T8 T16 M11
L1 L2 K1 K2
J1 J2 H1
J8 H8 H6
D13
D15 D16 D18 E9 E11 E15 A12 E22 E23 F9 F20 F16 G22 G23 A14 H20 J19 J20 J22 A16 J23 L20 L22 L23 A18 M20 N20 N22 N23 R18 A20 R19 R20 R22 R23 T20 U23 U22 A22 V9 V15 V20 W8 B6 W9 W22 W23 Y9 Y13 AA22 AA23 AB6 E4 J15 AB1 AC2 F5 F6 J12
PP3V3_TBT_X_LC PP3V3_TBT_X_SX
C2991
1
2
1
C2975
10UF
20%
2
CERM-X5R 0402-4
PP0V9_TBT_X_SVR
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
DIDT=TRUE SWITCH_NODE=TRUE
VR0V9_IND_TBT_X
PP0V9_TBT_X_LC
PP0V9_TBT_X_LVR
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
Add XW or alias on support page
XW
XW2900
SM
1 2
PLACE_NEAR=U2800.V8:2MM
NO_XNET_CONNECTION=1
PP3V3_TBT_X_F
VOLTAGE=3.3V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
1.0UF
20%
6.3V X5R 0201-1
1
C2976
10UF
20%
26.3V
CERM-X5R 0402-4
1
C2977
10UF
20%
6.3V
26.3V
CERM-X5R 0402-4
CRITICAL
L2950
0.68UH-20%-6.1A-0.020OHM
1 2
1210
SOURCED BY
C2992
1.0UF
20%
6.3V X5R
0201-1
29
TBTTHMSNS_X_D1_N
1
2
C2993
INTERNAL SWITCH
1
1.0UF
20% X5R
2
6.3V
0201-1
C2990
1
C2978
10UF
20%
6.3V
2
CERM-X5R 0402-4
1
2
C2954
10UF
CERM-X5R
0402-4
57
OUT
C2995
1
2
1
C2910
4UF
20%
6.3V
2
CER-X5R 0201
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
1
2
1.0UF
20%
6.3V X5R
0201-1
1
2
C2950
10UF
20% 25V X5R-CERM 0603
1
20%
6.3V
2
C2994
1
47UF
2
20%
CER-X5R
0603
C2917
12PF
5% 25V NP0-C0G 0201
C2951
1
47UF
20%
6.3V
2
CER-X5R 0603
C2955
10UF
20%
6.3V
CERM-X5R
0402-4
2x 10uF outside BGA area
P0V9_TBT_X_SVR_AGND
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0V
BOM_COST_GROUP=TBT
47UF
20%
6.3V
CER-X5R
0603
1
26.3V
1
2
C2952
1
47UF
20%
6.3V
2
CER-X5R 0603
L2990
1 2
1/10W MF-LF
603
C2911
4UF
20%
6.3V CER-X5R 0201
0
5%
1
C2912
4UF
20%
6.3V
2 6.3V
CER-X5R 0201
INTERNAL SWITCHING VR OUTPUT
C2982
1
1.0UF
20%
6.3V
2
X5R 0201-1
33
27 29
FROM USB-C PORT CONTROLLER (UPC)
C2981
1
1.0UF
20%
6.3V
2
X5R 0201-1
PP3V3_S0SW_TBT_X_SNS
1
C2913
4UF
20%
2
CER-X5R 0201
SYNC_MASTER=ANDY SYNC_DATE=01/17/2019
PAGE TITLE
1
C2914
4UF
20%
6.3V
2
CER-X5R 0201
(SEE INTEL LAYOUT GUIDELINES)
C2983
1
1.0UF
20%
6.3V
2
X5R 0201-1
29 118 124
1
C2915
4UF
20%
6.3V
2
CER-X5R 0201
ISOLATE GND OF SVR_IND CAPS
AND GND OF VCC3P3_SVR CAPS
FROM SYSTEM GND IN LAYOUT
C2980
1
1.0UF
20%
6.3V
2
X5R 0201-1
1
2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V
C2916
4UF
20%
6.3V CER-X5R 0201
SOURCED BY INTERNAL SWITCH
USB-C HIGH SPEED 2
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
29 OF 200
SHEET
28 OF 135
D
C
B
A
8
67
35 4
2
1
Vinafix.com
678
3 245
1
D
C
B
121 14
121 14
TBT WAKE LEVEL SHIFTER
118
PP3V3_G3H_RTC_X
1
R3003
111
PP1V8_SLPS2R
30 31 80 110
Q3001
1
DMN32D2LFB4
DFN1006H4-3
SYM_VER_2
100K
5% 1/20W MF
2
201
SMC HAS IPU
39
TBT_WAKE_L
DP SRC OPTIONS
S G
2
D
TBT_WAKE_3V3_L
3
27
DP_X_SRC_HPD
R3017
100K
1 2
IF DP SRC NOT USED
=DP_X_SRC_ML_P<3..0>
27
=DP_X_SRC_ML_N<3..0>
27
NC_DP_X_SRC_ML_P<3..0> NC_DP_X_SRC_ML_N<3..0>
MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
Bus <3..0> doesn't resolve properly. but netlist is correct.
NC_DP_X_SRC_AUX_P
27
NC_DP_X_SRC_AUX_N
27
FUSES FOR UPC
NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N
CRITICAL
0603-1
MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
F3000
6A-32V
PPDCIN_G3H
29 109
1 2
PPDCIN_XA_G3H_F
CRITICAL
0603-1
F3001
6A-32V
1 2
PPDCIN_XB_G3H_F
Ridge 25MHz xtal
C3002
20PF
1 2
5% 25V C0G
0201
120 27
TBT_X_XTAL25M_OUT
IN
CRITICAL
Y3000
120 27
OUT
2 4
1 3
TBT_X_XTAL25M_IN
25MHZ-25PPM-20PF-50OHM
2.00X1.60-SM
C3003
20PF
1 2
5% 25V C0G
0201
DEBUG ALIASES
PCH UART (MOJO)
30
PCH_UART_DEBUG_R2D
30
PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D PCH_UART_DEBUG_D2R
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC UART
31
SMC_DEBUGPRT_TX SMC_DEBUGPRT_RX
31
SMC_DEBUGPRT_TX
MAKE_BASE=TRUE
SMC_DEBUGPRT_RX
MAKE_BASE=TRUE
SOC SWD
SWD_SOC_SWCLK
39
MAKE_BASE=TRUE
SWD_SOC_SWDIO
39
MAKE_BASE=TRUE
0
R3036
PLACE_NEAR=U3100.G2:5mm
R3037
PLACE_NEAR=U3100.G2:5mm
1 2
0
1 2
1/20W MF
SWD_SOC_SWCLK
5%0201
UPC_XB_DBG4
SWD_SOC_SWDIO
5%0201
UPC_XB_DBG5
MF1/20W
DCI
BI
BI
USB3_EXTA_D2R_P
MAKE_BASE=TRUE
USB3_EXTA_D2R_N
MAKE_BASE=TRUE
121 15
121 15
121 39
121 39
30 121
31
30 121
31
USB3_EXTA_D2R_P USB3_EXTA_D2R_N
INOUT
5%1/20W MF
201
Ridge and ACE PU/PDs
R3001
1 2
29
UPC_X_5V_EN
34
SPARE_UPC_XA_USB3_RP
30
SPARE_UPC_XA_USB3_RN
30
113 107 33 27
SPARE_UPC_XB_USB2_RP
31
SPARE_UPC_XB_USB2_RN
31
SPARE_UPC_XB_USB3_RP
31
SPARE_UPC_XB_USB3_RN
31
UPC_XA_FAULT_L
30 18
UPC_XB_FAULT_L
31 18
1/20W
1/20W 201
5% 1/20W
1/20W
5% 201MF
5% 1/20W MF
R3026 R3028
1/20W 2015%
MF
MF 2015%
MF5%
MF1/20W
201MF1/20W5%
100K
2011/20W5% MF
R3004
100K
1 2
R3008
100K
1 2
R3009
100K
1 2
2015%
R3014
100K
1 2
201MF
R3018
100K
1 2
R3020
100K
1 2
201
100K
1 2
100K
1 2
30
UPC_XA_GPIO4
123 31
UPC_XB_GPIO1
UPC_XB_GPIO4
31
UPC_XB_GPIO9
31
UPC_XB_GPIO10
31
PP3V3_S5
PP3V3_S5
R3002
5% MF
R3005
1/20W5% MF
R3007
MF
R3012
5% 201MF1/20W
R3016
MF5% 2011/20W
12 29 80
12 29 80
100K
1 2
2011/20W
1 2
100K
201
1 2
100K
2015% 1/20W
1 2
100K
1 2
100K
PP1V8_AWAKE
77 80
30
I2C_UPC_X_SDA2
31
I2C_UPC_X_SDA2
33
I2C_UPC_X_SDA2
I2C_UPC_X_SCL2
30
I2C_UPC_X_SCL2
31
I2C_UPC_X_SCL2
33
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R3006
MF 02015% 1/20W
0
1 2
I2C SERIES R'S
PLACE_NEAR=U3900.J4:5mm
R3021
1/20W MF 201
5%
R3025
MF1/20W5% 201
33
1 2
33
1 2
I2C_UPC_SDA
I2C_UPC_SDA
PLACE_NEAR=U3900.M3:10mm
I2C_UPC_SCL
I2C_UPC_SCL
SOC_USB_VBUS
121 38
51
51
51
51
SIGNAL ALIASES
UPC_X_5V_EN
30 29
123 31 29
RIDGE 0.9V SVR XW
XW3000
SM
P0V9_TBT_X_SVR_AGND
28
NO_XNET_CONNECTION=1
1 2
30
UPC_X_5V_EN
31
30
UPC_PMU_RESET UPC_PMU_RESET
31
UPC_X_5V_EN
MAKE_BASE=TRUE
UPC_PMU_RESET
MAKE_BASE=TRUE
34 29
121 109 77 67
Portable: rear connector->TBT ROM
Desktop: XA_SPI -> TBT ROM
front connector->GND
XB_SPI -> GND
FLASH ROM
TBT_X_SPI_CLK
27
TBT_X_SPI_CS_L
27
TBT_X_SPI_MOSI
27
TBT_X_SPI_MISO
27
TBT SPI ROM
Ace
R3011 R3013 R3015 R3019
R3022 R3023 R3024 R3027
R3029
USBC_DBG
R3030
USBC_DBG
R3031
USBC_DBG
R3032
USBC_DBG
R3033
USBC_DBG
1 2
15
1 2
15
1 2
15
1 2
15
1 2
15
1 2
15
1 2
15
1 2
100
1 2
15
1 2
15
1 2
15
1 2
15
1 2
UPC_XB_SPI_CLK UPC_XB_SPI_CS_L UPC_XB_SPI_MOSI UPC_XB_SPI_MISO
MF
MF
201MF5%151/20W
201MF5% 1/20W
2011/20W5%
2011/20W5%
Titan Ridge
UPC_X_SPI_CLK UPC_X_SPI_CS_L
1/20W5% 201MF
UPC_X_SPI_MOSI
1/20W 201MF5%
UPC_X_SPI_MISO
1/20W5%
MF5% 2011/20W
MF 201
ACE ARKANOID
TBT_X_SPI_ARK_CLK
5%
1/20W MF 201
AARDVARKANOID
TBT_X_SPI_DBG_CLK
5% 1/20W 201MF
TBT_X_SPI_DBG_CS_L
5% 1/20W MF 201
TBT_X_SPI_DBG_MOSI
5% MF 2011/20W
TBT_X_SPI_DBG_MISO
5% 1/20W MF 201
33
IN
IN
IN
OUT
IN
IN
IN
OUT
IN
IN
IN
OUT
31
31
31
31
27
27
27
27
33
33
33
33
D
POWER ALIASES
PP3V3_UPC_XB_LDO
27
PP3V3_UPC_XB_LDO
MAKE_BASE=TRUE
33 31 29
SIGNAL ALIASES
C
32
PPVBUS_USBC_XA
PPVBUS_USBC_XA
PPVBUS_USBC_XB
32
PPVBUS_USBC_XB
PPVBUS_USBC_XA
MAKE_BASE=TRUE
VOLTAGE=20V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PPVBUS_USBC_XB
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=20V
USBC_X_RESET_L
124 122 30 29
31
TP_USBC_XA_RESET_L
124 123 122 31 29
USBC_X_RESET_L
MAKE_BASE=TRUE
TP_USBC_XA_RESET_L
MAKE_BASE=TRUE
33 27
123 30
TBT to ACE
TBT_POC_RESET
PPVBUS_USBC_XA PPDCIN_XA_G3H_F PPVBUS_USBC_XB
31
PPDCIN_XB_G3H_F
31
PPDCIN_G3H
29 109
30
PP5V_S4_X_USBC PP5V_S4_X_USBC
31
PP5V_S4_X_USBC
34 124
28 118 124
PP3V3_S0SW_TBT_X_SNS
30
PP3V3_TBT_X_SX PP3V3_TBT_X_SX
31
27 28
PP3V3_TBT_X_SX
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=20V
VOLTAGE=5V
VOLTAGE=3.3V
PPVBUS_USBC_XA
PPDCIN_XA_G3H_F
PPVBUS_USBC_XB
PPDCIN_XB_G3H_F
PPDCIN_G3H
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
MAKE_BASE=TRUE
PP5V_S4_X_USBC
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200
PP3V3_S0SW_TBT_X_SNS
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PP3V3_TBT_X_SX
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
124 122 30 29
30 29
124 123 122 31 29
123 31 29
TBT_X_HDMI_DDC_DATA
124 121 68 53
27
TBT_X_HDMI_DDC_DATA
33
27
TBT_X_HDMI_DDC_CLK
TBT_X_HDMI_DDC_CLK
SOC_DFU_STATUS
MAKE_BASE=TRUE
SOC_FORCE_DFU
MAKE_BASE=TRUE
TBT_X_HDMI_DDC_DATA
MAKE_BASE=TRUE
SOC_DFU_STATUS
SOC_FORCE_DFU
Mobile Config
31
79 33 27
PP3V3_UPC_XB_LDO PP3V3_UPC_XA_LDO
30
PP3V3_UPC_XB_LDO PP3V3_UPC_XA_LDO
CC Aliases for X side
31
USBC_XB_CC1 USBC_XB_CC2
31
30
USBC_XA_CC1 USBC_XA_CC2
30
31
31
GND ALIASES
USBC_XB_CC1
MAKE_BASE=TRUE
USBC_XB_CC2
MAKE_BASE=TRUE
USBC_XA_CC1
MAKE_BASE=TRUE
USBC_XA_CC2
MAKE_BASE=TRUE
TBT_POC_RESET
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
122 32 31
122 32 31
122 32 30
122 32 30
33 31 29
33 30
113
109 15 33 31 30
TBT
Titan Ridge U2800
(MASTER)
I2C_TBT_X_SCL
33 27
I2C_TBT_X_SDA
33 27
I2C_TBT_XA_INT_L
33 27
I2C_TBT_XB_INT_L
33 27
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
(Write: 0x70 Read: 0x71)
I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XA_INT_L
Pri ACE
U3100
30
30
30
OUTIN
122 98
Sec ACE
U3200
(Write: 0x7E Read: 0x7F)
122 98
135 121 38 30
135 121 77 38 30
I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XB_INT_L
31
31
31
B
A
14
14
C3004
10%
BI
USB3_EXTA_R2D_C_P
0201 X5R-CERM
1 2
C3005
BI
USB3_EXTA_R2D_C_N
0201
DBG MUX PDs
30
UPC_XA_DBG_PD
30
UPC_XA_DBG_PD UPC_XA_DBG_PD
30
UPC_XA_DBG_PD
30
1 2
X5R-CERM
16V
USB3_EXTA_R2D_P
0.1UF
16V10%
USB3_EXTA_R2D_N
0.1UF
UPC_XA_DBG_PD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R3038
1/20W 201
MF5%
USB3_EXTA_R2D_P
USB3_EXTA_R2D_N
100K
1 2
31
GND
30
GND
30
31
30
30
30
31
GND GND
GND GND
NC_UPC_XA_VDDIO_CFG NC_UPC_XB_VDDIO_CFG
GND
GND GND GND
GND
31
GND
31
GND
31
GND
31
30
GND
MAKE_BASE=TRUE
NC for X side
NC_UPC_XA_VDDIO_CFG NC_UPC_XB_VDDIO_CFG
MAKE_BASE=TRUE MAKE_BASE=TRUE
BOM_COST_GROUP=TBT
SYNC_MASTER=YANIR SYNC_DATE=01/17/2019
PAGE TITLE
USB-C X Support
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
30 OF 200
SHEET
29 OF 135
A
8
67
35 4
2
1
Vinafix.com
678
X PRIMARY ACE USB-C PORT CONTROLLER (UPC)
3 245
1
D
C
124 122 30 29
TP must be present on GPIO0 or be accessible on connector even in production
PPVBUS_USBC_XA
ACE LDO CAN DRAW UP TO
5.9 MA WHILE PROGRAMMING OTP
MAX 100uF TOTAL ON RAIL
30 29
PP5V_S4_X_USBC
29
PPDCIN_XA_G3H_F
BUSPOWER needs to connect to GND on Desktop and LDO_3V3 on Mobile.
MRESET HIGH FORCES B17 RESET LOW
ACTIVE LOW RESET OUTPUT
USE GPIO8 FOR PMU RESET AFTER BOOT
I2C_ADDR CONTROLS ADDR BITS 3,2,1 GND I2C_ADDR ON PRIMARY ONLY
R_OSC NEEDS NEEDS 0.1% RES
I2C BUS 1 IS TBT / ACES
I2C BUS 2 IS SMC / ACES
Portable: rear connector->TBT ROM
Desktop: XA_SPI -> TBT ROM
front connector->GND
XB_SPI -> GND
R3103
15K
0.1% 1/20W TF-LF
0201
TO SMC
1
C3198
1.0UF
10% 25V
2
X6S 0402
29
33 31 29
123 33
135 121 77 38
33 31 27 14
29
29 18
33 31 27 14
121 39 31
29
135 121 38 29
135 121 77 38 29
29
1
29
2
29
29
29
29
51
29
29
29
29
1
2
IN IN
123 29
OUT
IN IN
OUT
29
OUT
IN OUT OUT
IN OUT
IN
29
30
30
BI BI OUT
BI BI OUT
IN
IN OUT
IN
C3199
1UF
10% 35V X5R 0402
1
C3101
1UF
10% 35V
2
X5R 0402
K
D3100
DSN2
NSR20F40NX_G
A
GND TBT_POC_RESET TP_USBC_XA_RESET_L
UPC_XA_SER_DBG PMU_ACTIVE_READY
TBT_X_CIO_PWR_EN UPC_X_5V_EN UPC_XA_GPIO4 UPC_XA_FAULT_L TBT_X_USB_PWR_EN SOC_DOCK_CONNECT UPC_PMU_RESET SOC_DFU_STATUS SOC_FORCE_DFU
PP3V3_UPC_XA_LDO GND
UPC_XA_R_OSC I2C_UPC_XA_DBG_CTL_SDA
I2C_UPC_XA_DBG_CTL_SCL I2C_TBT_X_SDA
I2C_TBT_X_SCL I2C_TBT_XA_INT_L
I2C_UPC_X_SDA2 I2C_UPC_X_SCL2
UPC_I2C_INT_L
GND GND GND GND
B13 A14 B17
A2 B1
D1
F1 C2 E2 B3 C4 D3 E4
F3
F7
A18
M19 M21
A16 B15
B5 A4 D7
B7 A6 C8
B9
B11 A10
A8
K9
L10M9N10
HRESET MRESET RESET*
GPIO0
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10
BUSPOWER I2C_ADDR
R_OSC I2CM_SDA_CNFG
I2CM_SCL_CNFG I2C_SDA1
I2C_SCL1 I2C_IRQ1*
I2C_SDA2 I2C_SCL2 I2C_IRQ2*
SPI_CLK SPI_MOSI SPI_MISO SPI_SSZ
K11
L12
M11
N12
N14
M13G2G4H1H3J2J4K1K3L2L4M1M3N2N4
PP_5V0
PP_CABLE
PP_HV
U3100
CD3217B12BCE
FCBGA
CRITICAL
OMIT_TABLE
DIGITAL CORE I/O & CONTROL POWER
TYPE-C
G6G8H5H7J6J8K5K7L6L8M5M7N6
VBUS
N8
VIN_3V3
VDDIO
VDDIO_CFG
LDO_3V3
VIN_LV
VOUT_LV
VRET
SS
LDO_CORE
VBUS_OPT
PP_HV_OPT
C_CC1
C_CC2
RPD_G1 RPD_G2
C_USB_TP C_USB_TN
C_USB_BP
C_USB_BN
C_SBU1 C_SBU2
C20 A12
D11 C22
D21 L20
L18 C16 L22
E22 D5 F5
M15 N16
M17 N18
L14 L16
K19 K21
J20 J22
J16 H15
NC_UPC_XA_VDDIO_CFG
NO_TEST=1
PP3V3_TBT_X_SX
UPC_XA_SS
SOFT START RAMP RATE = 9 * ISS / CSS ISS = 7 UA NOMIAL, 5.5 MA MIN, 8.5 MA MAX
PP1V5_UPC_XA_LDO_CORE
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PPVBUS_USBC_XA
PPDCIN_XA_G3H_F
USBC_XA_CC1
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200
USBC_XA_CC2
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200
USBC_XA_CC1 USBC_XA_CC2
USBC_XA_USB_TOP_P USBC_XA_USB_TOP_N
USBC_XA_USB_BOT_P USBC_XA_USB_BOT_N
USBC_XA_SBU1 USBC_XA_SBU2
1
C3100
10UF
20%
6.3V
2
CERM-X5R 0402-1
29
VOUT_3V3 FOR RIDGE
29
BI BI
BI BI
BI BI
BI BI
29 30 122 124 29 30
29
29
C3104
1
10UF
20%
2
6.3V CER-X6S 0402
122 32
122 32
122 32
122 32
122 32
122 32
1
C3114
220PF
10% 25V
2
X7R-CERM 201
1
C3108
10UF
20%
6.3V
2
CERM-X5R 0402-1
1
C3109
0.68UF
10%
6.3V
2
CERM 402
1
C3113
220PF
10% 25V
2
X7R-CERM 201
D
PP3V3_G3H_RTC_X
PP1V8_SLPS2R
1V8 SOURCE FOR ACE 1V8 GPIO
PP3V3_UPC_XA_LDO
VOLTAGE=3.3V
1
C3107
1.0UF
20%
6.3V
2
X5R 0201-1
118
29 31 80 110 111
33 30 29
C
BI
BI
122 32 29
122 32 29
PORT SIDE USB TOP PAIR
PORT SIDE USB BOTTOM PAIR
PORT SIDE USB SIDEBAND
B
120 14
120 14
33
BI
33
IN
PLACE_NEAR=U3100.H19:5mm
BI
BI
USB_UPC_PCH_XA_P
USB_UPC_PCH_XA_N
R3100 R3101
PLACE_NEAR=U3100.H21:5mm
0
1 2
5%0201 MF1/20W
1 2
5% MF020101/20W
33 31 30
33 31
121 38
121 38
29
29
120 27
120 27
120 27
29
29
29
29
121 29
121 29
29
29
IN
OUT
BI BI BI BI
BI BI
OUT
BI BI BI BI OUT
OUT OUT OUT
UPC_XA_SWD_DATA UPC_XA_SWD_CLK
UPC_XA_UART_RX UPC_XA_UART_TX
USB_UPC_PCH_XA_F_P
120
USB_UPC_PCH_XA_F_N
120
USB_SOC_P USB_SOC_N SPARE_UPC_XA_USB3_RP SPARE_UPC_XA_USB3_RN
USBC_XA_AUXLSX1 USBC_XA_AUXLSX2
DP_XA_HPD UPC_XA_DBG_PD
UPC_XA_DBG_PD
UPC_XA_DBG_PD UPC_XA_DBG_PD SWD_SOC_SWCLK SWD_SOC_SWDIO PCH_UART_DEBUG_R2D PCH_UART_DEBUG_D2R
E20 E16
B19 A20
H19 H21 G20 G22
F19 F21
J12
H11 C12 G12
F11
E8
E12 G16
F15 D15 D19
SWD_DATA SWD_CLK
UART_RX UART_TX
USB_RP1_P USB_RP1_N USB_RP2_P USB_RP2_N USB_RP3_P USB_RP3_N
AUX_P AUX_N
HPD DEBUG0
DEBUG1 DEBUG2 DEBUG3 DEBUG4 DEBUG5 DEBUG6 DEBUG7
PULL R3109 AND R3108 UP TO ACES LDO FOR 1ST RIDGE'S ACES PULL THEM DOWN TO GND FOR 2ND RIDGE'S ACES
GND_OPT GND_OPT GND_OPT
GNDPORT_MUX
GND
GND_OPT
C18 E18 D17 G18
PP3V3_UPC_XA_LDO
1M
1 2
1M
1 2
1M
1 2
R3109
5%
R3108
1/20W 201MF5%
R3105
33 30 29
I2C_UPC_XA_DBG_CTL_SCL
201MF1/20W
I2C_UPC_XA_DBG_CTL_SDA
UPC_XA_UART_RX
MF1/20W 2015%
30
30
33 31 30
B
A
8
H9
A22
N20
B21
K15
N22
PAGE TITLE
SYNC_DATE=01/17/2019SYNC_MASTER=YANIR
A
USB-C PORT CONTROLLER XA
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
BOM_COST_GROUP=USB-C
67
35 4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
31 OF 200
SHEET
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