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MacBook Pro A2141
boardview
135 pgs11.96 Mb2

Apple MacBook Pro A2141 boardview

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8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7
6 5 4 3
SCHEM,MLB,X970
2 1
ECNREV DESCRIPTION OF REVISION
CK APPD
DATE
2019-06-192
D
CSAPAGE
1 2 3 4
6 7 8 8 9 10
12 13
2
3
55
6
7
9
10
12
13
CONTENTS
MLB BOM Configuration 1 BOM Configuration 2 PD Parts CPU DMI/PEG/FDI/RSVD CPU Clock/Misc/JTAG/CFG CPU DDR4 Interfaces CPU Power CPU Ground CPU Decoupling 1 CPU Decoupling 211 PCH RTC/CLK/ESPI/PM PCH DMI/JTAG/SPI/HDA
ANDY
ANDY
01/17/2019 08/22/2018 08/22/2018 10/14/20184 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/201911 01/17/2019 01/17/2019
CSAPAGEDATESYNC
511 52 53
55 56
59 60 61 01/17/2019 62 63
52 53 54 5554 56 57 01/17/2019
59 60 62 01/17/2019 63 64 65
CONTENTS
ZIFENG
I2C Connections 2 02/14/2019 Power Sensors High Side Power Sensors Load Side Power Sensors Extended 1 Power Sensors Extended 2 Thermal Sensors Power Sensor Extended 3 Fans/SMC/AMUX Support 01/17/2019 Audio Placeholder Audio Jack Codec Audio Left Amplifiers Audio Right Amplifiers
ZIFENG
RAYMOND RAYMOND RAYMOND RAYMOND
ARMIN
ADRIEN ADRIEN ADRIEN
DATESYNC
02/14/2019I2C Connections 1
01/17/2019 02/12/2019 02/12/2019
02/12/20195857 01/17/201958
01/17/2019 01/17/2019
101 102 103
105 106 107 108
110 111 112 113
CSAPAGE
104 105 106 107 108 GPU Memory Rails 109 110 111 112 113
115 116
CONTENTS
GPU Navi14 GDDR6 CHs A, B GPU Navi14 GDDR6 CHs C, D GPU Core Rails Controller GPU Core GFX/SOC Phases104
GPU 1.8V / 0.75V USB-C HIGH SPEED 1 USB-C HIGH SPEED 2 USB-C T Support109 USB-C PORT CONTROLLER TA USB-C PORT CONTROLLER TB114 USB-C T CONNECTOR USBC T Connector Support
SEAN YANIR ANDY YANIR YANIR YANIR YANIR ANDY
DATESYNC
D
08/22/2018 08/22/2018 08/22/2018 08/22/2018 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 03/26/2019
C
14 01/17/2019 15 16 16 17 18 19 19
21 22 DDR4 SDRAM Channel A 1
24 25 26 27
14
15
17
18
20
23 01/17/2019
2423
25
26
27
28
PCH PCI-E/USB PCH GPIO/MISC/NCTF PCH Power PCH Decoupling CPU/PCH Merged XDP Chipset Support 1 Chipset Support 220 DDR4 VREF Margining
DDR4 SDRAM Channel A 2 DDR4 SDRAM Channel B 1 DDR4 SDRAM Channel B 2 DDR4 Termination USB-C HIGH SPEED 1
ARMIN ANDY
YANIR
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 02/19/2019 01/17/201922
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019
64 66
73 74 75
77
68 Trackpad Support
69
70
71
72
73
76
77
78
79
Audio Flex Connectors Keyboard Support
VR 3.3V G3H & Battery Conn PBUS Supply & Battery Charger IMVP IC IMVP VCC Block IMVP SA Block IMVP GT Block Power 5V 3.3V Supply VR 2.5V & 1.2V/VTT PMIC BUCKS AND SWs PMIC LDOs PMIC GPIOs & Control80
ADRIEN 01/17/2019 SHAN
RAYMOND
ARMIN
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/201976 01/17/2019
114 115 116 117 118 119 120 121 DFU TEST POINTS
123 124
126 127 06/05/2019
117 01/17/2019 118
120 121
123 124 125122 126 127 128125 10/14/2018 129 130
USB-C T 5V VR GPU 3.3V / Discharge GPU Sequencing & Straps119 Power Alias 1 Power Alias 2 Signal Alias122 High speed No Testpoints
FCT TESTPOINTS 2 ICT, MAC-1, & EE Testpoints Desense Caps 1 Desense Caps 2 Desense Caps 3 Desense Caps 4
TUZMAN J780 ZIFENG
ANDY ANDY ANDY ANDY ZIFENG ZIFENG
ZIFENG ZIFENG
09/05/2018 08/22/2018 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 03/26/2019 08/22/2018
08/22/2018
C
B
28 29 30
32 33 34 35 36 37 38 39 40 41 SoC PCIe
29 30 31 3231 33 34 35 36 37 38 39 40 41 42
USB-C HIGH SPEED 2 USB-C X Support USB-C PORT CONTROLLER XA USB-C PORT CONTROLLER XB USB-C X Connector USBC X Connector Support TBT 5V REGULATOR WIFI/BT: Support WIFI/BT: MODULE 1 AP & BT Conn SoC GPIO/SEP/USB/DDR/Test SoC AOP/AON/SMC SoC ISP/I2C/UART/SPI/I2S
ANDY
YANIR YANIR YANIR YANIR YANIR
METE
ANDY ANDY ANDY ANDY
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 02/19/2019 01/17/2019 01/17/2019
78 79 01/17/2019
81 84 82 83 84 85
87 90 88
90 91
81
82
85
86
87
88
91
92
93
94
VR VCCIO Power FETs SOC/PMIC Aliases LCD Backlight Driver eDP Display Connector SSD1 S4E 0 SSD1 S4E 1 SSD1 S4E 2 SSD1 S4E 3 SSD1 PMIC & VR SSD0 S4E 0 SSD0 S4E 1 SSD0 S4E 2 SSD0 S4E 3
ARMIN ARMIN
01/17/2019
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/201989 01/17/2019 01/17/2019
128 129 130 131 132 133 134 135 200
131 140 141 143
147 148
Memory Bite/Byte Swizzle Debug BOM 639 XTA BOM 639 XLA BOM 639 MISC144 BOM Alt Table
Dev Support 10/14/2018
LAST_MODIFICATION=Tue Jun 18 17:59:51 2019
ANDY
SEAN
01/17/2019 10/14/2018 10/14/2018 10/14/2018 10/14/2018 01/17/2019 01/17/2019More BOM Alt Table
B
A
42 43 44 45 46 47 48 49 50
43 44 45 46 47 48 49 50 51
SoC Power 1 SoC Power 2 SoC Power 3 SoC Ground SoC Shared Support SoC Project Support MESA SECURE ELEMENT DFR Support
LAST_MODIFICATION=Tue Jun 18 17:59:51 2019
ARMIN
ANDY ARMIN ANDY
ARMIN
01/17/2019 01/17/2019 01/17/2019 01/17/2019 01/17/2019 02/19/2019 01/17/2019 02/19/2019 01/17/2019
92 93 94
97 98 99 100
95
96
97
98
99
100
101
102
103
SSD0 PMIC & VR GPU VRAM CHs A, B GPU VRAM CHs C, D EDP Mux GPU PCC / Sensors96 GPU Navi14 PCIe / DP A / Misc GPU Navi14 DP / GPIO / Debug GPU Navi14 Power GPU Navi14 VSS & Decoupling
LAST_MODIFICATION=Tue Jun 18 17:59:51 2019
J187_ALAN J187_ALAN
J780 SEAN
SEAN
01/17/2019 09/18/2018 09/18/2018 08/22/201895 08/22/2018 08/22/2018 08/22/2018 08/22/2018 08/22/2018
CANDIDATE
DRAWING TITLE
SCHEM,MLB-NAVI,X970
SYNC_DATE=08/22/2018SYNC_MASTER=ZIFENG
A
DRAWING
TITLE=MLB ABBREV=ABBREV
LAST_MODIFIED=Tue Jun 18 17:59:51 2019
Schematic / PCB #'s
8
SIZEDRAWING NUMBER
Apple Inc.
051-04492
REVISION
D
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL1 SCH SCHSCHEM,MLB-NAVI,X970051-04492 CRITICAL1 PCBPCBPCBF,MLB-NAVI,X970820-01700
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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X970 BOM Groups
BOM GROUP BOM OPTIONS
SSD_LANDS:6 ALTERNATE,S4E_L6 SSD_LANDS:7 ALTERNATE,S4E_L6,S4E_L7 SSD_LANDS:8 ALTERNATE,S4E_L6,S4E_L7,S4E_L8
SCH,PCB,COMMON,ALTERNATE,COMMON1,COMMON2,COMMON3,PROGPARTSX970_COMMON CPUPEG:X8X4X4,EDP:YES,BOARD_ID:0X3A,SE:DEV_2019,EN_VP0R_LPS:YESCOMMON1 PCC:YES,RF_TUNING,BOARD_REV:010,BAT_I2C:3V3COMMON2 SKIP_5V3V3:AUDIBLE,XDP:YES,VCCSPI:3V3,SVID_PU:CORECOMMON3 LOADISNS,LOADRC:YES,SENSOR:DEVSNS ALTERNATE,SNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,WIFI_DBG,BOOTCFG0,ESPI_DBGDEVEL:ENG ALTERNATE,LOADRC:NODEVEL:PVT
BOM Variants
BOM NUMBER BOM NAME BOM OPTIONS
COMMON PARTS,MLB-NAVI,X970 X970_COMMON685-00271
SSD_LANDS:6685-00308 ITLC 6L Parts,MLB-NAVI,X970 SSD_LANDS:7685-00309 ITLC 7L Parts,MLB-NAVI,X970
685-00310 SSD_LANDS:8ITLC 8L Parts,MLB-NAVI,X970
DEVEL:ENG985-00889 DEV PARTS,MLB-NAVI,X970 685-00296 VRAM:MC-4GBVRAM PARTS,MICRON,4GB,MLB-NAVI,X970 685-00297 VRAM:SS-4GBVRAM PARTS,SAMSUNG,4GB,MLB-NAVI,X970 685-00298 VRAM:HY-8GBVRAM PARTS,HYNIX,8GB,MLB-NAVI,X970
VRAM:MC-8GBVRAM PARTS,MICRON,8GB,MLB-NAVI,X970685-00299 VRAM:SS-8GB685-00300 VRAM PARTS,SAMSUNG,8GB,MLB-NAVI,X970
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
685-00271 CRITICAL BOM_BASEBASE1 COMMON PARTS,MLB-NAVI,X970
CRITICAL1685-00309 7L SSD_BOM:7LITLC 7L Parts,MLB-NAVI,X970
685-00310 CRITICAL1 SSD_BOM:8L8LITLC 8L Parts,MLB-NAVI,X970
985-00889 1 DEVEL BOM_DEVCRITICALDEV PARTS,MLB-NAVI,X970
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
SSD_BOM:6LCRITICAL6L685-00308 1 ITLC 6L Parts,MLB-NAVI,X970
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Memory Options
BOM GROUP BOM OPTIONS
MEM:HY-16GB DRAM:HY-16GB,RAMCFG0:L MEM:MC-16GB DRAM:MC-16GB,RAMCFG1:L MEM:HY-32GB DRAM:HY-32GB,RAMCFG3:L,RAMCFG0:L MEM:MC-32GB DRAM:MC-32GB,RAMCFG3:L,RAMCFG1:L MEM:MC-64GB DRAM:MC-64GB,RAMCFG2:L,RAMCFG1:L
VRAM Options
BOM GROUP BOM OPTIONS
VRAM_SIZE:4GB,VRAM_IC:MC-4GBVRAM:MC-4GB VRAM_SIZE:4GB,VRAM_IC:SS-4GBVRAM:SS-4GB VRAM_SIZE:8GB,VRAM_IC:HY-8GBVRAM:HY-8GB VRAM_SIZE:8GB,VRAM_IC:MC-8GBVRAM:MC-8GB
VRAM:SS-8GB VRAM_SIZE:8GB,VRAM_IC:SS-8GB
SSD Options
BOM GROUP BOM OPTIONS
SSD:TS-256 SSD_NAND:TS-256,SOC:1GB,JTAG:L5 SSD:WD-256 SSD_NAND:WD-256,SOC:1GB,JTAG:L5
SSD_NAND:TS-512,SOC:1GB,JTAG:L5SSD:TS-512 SSD:SS-512 SSD_NAND:SS-512,SOC:1GB,JTAG:L5 SSD:WD-512 SSD_NAND:WD-512,SOC:1GB,JTAG:L5 SSD:TS-1TB SSD_NAND:TS-1TB,SOC:2GB,JTAG:L6,SSD_BOM:6L
SSD_NAND:WD-1TB,SOC:2GB,JTAG:L6,SSD_BOM:6LSSD:WD-1TB SSD:TS-2TB SSD_NAND:TS-2TB,SOC:2GB,JTAG:L7,SSD_BOM:7L SSD:WD-2TB SSD_NAND:WD-2TB,SOC:2GB,JTAG:L7,SSD_BOM:7L SSD:HY-4TB SSD_NAND:HY-4TB,SOC:2GB,SSD_BOM:8L SSD:WD-4TB SSD_NAND:WD-4TB,SOC:2GB,SSD_BOM:8L SSD:WD-8TB SSD_NAND:WD-8TB,SOC:2GB,SSD_BOM:8L
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
D
C
B
B
A
Board ID[7:0] = 8b'00111010 = 8h'3A
BOM GROUP BOM OPTIONS
BOARDID5,BOARDID4,BOARDID3,BOARDID1BOARD_ID:0X3A
8
SYNC_MASTER= SYNC_DATE=08/22/2018
PAGE TITLE
A
BOM Configuration 1
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
67
35 4
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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CPU
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
1 U0500 CRITICAL CPU:6C-2.6G337S00722
CPU,CFLH,SRF6U,PRQ,2.6,1.15,6C,BGA1440
CPU,CFLH,SRFD1,PRQ,2.3,1.2,8C,BGA1440
1337S00731 U0500
337S00724 CRITICAL CPU:8C-2.4G1
998-12472 1 CPU:INTERPOSER
DRAM
333S00200
333S00163
998-18918 8
CPU,CFLH,SRFD0,PRQ,2.4,1.25,8C,BGA1440
INTERPOSER,CFL-H,BGA1440
Note: Two rows per part for legibility
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,DDR4-2666,8GBIT,19NM,H,BGA78
8
IC,DDR4-2666,8GBIT,19NM,H,BGA78
8
IC,DDR4-2666,8GBIT,Z11B,18NM,M,BGA78
IC,DDR4-2666,8GBIT,Z11B,18NM,M,BGA78
8 CRITICAL
IC,DDR4-2666,16GBIT,19NM,H,BGA78
8333S00201
IC,DDR4-2666,16GBIT,19NM,H,BGA78
8333S00201
IC,DDR4-3200,16GBIT,16NM,ES,M,BGA78
IC,DDR4-3200,16GBIT,16NM,ES,M,BGA78
IC,DDR4-3200,32GBIT,16NM,ES,M,BGA78
IC,DDR4-3200,32GBIT,16NM,ES,M,BGA78
U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430
U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630
U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430
U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630
U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430
U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630
U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430
U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630
U2300,U2310,U2320,U2330,U2400,U2410,U2420,U2430
U2500,U2510,U2520,U2530,U2600,U2610,U2620,U2630
U0500
U0500 CRITICAL
CRITICAL333S00200 8 DRAM:HY-16GB
CRITICAL333S00163
CRITICAL DRAM:HY-32GB
CRITICAL998-18918 8
BOM OPTIONCRITICAL
CPU:8C-2.3GCRITICAL
BOM OPTIONCRITICAL
DRAM:HY-16GBCRITICAL
DRAM:MC-16GB
DRAM:MC-16GB
DRAM:HY-32GBCRITICAL
DRAM:MC-32GBCRITICAL998-18917 8
DRAM:MC-32GBCRITICAL8998-18917
DRAM:MC-64GB
DRAM:MC-64GBCRITICAL
GPU
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
CRITICAL GPU:ULA337S00719 1 UA000GPU,AMD,NAVI14,ULA,A0,ES,BGA1125
CRITICAL337S00720 1 UA000 GPU:PRAGPU,AMD,NAVI14,PROA,A0,ES,BGA1125
UA0001 CRITICAL998-19125 GPU,AMD,NAVI14,ULA,A0,ES,FF,PSL,BGA1125 GPU:UFS
1 CRITICALUA000998-19126 GPU,AMD,NAVI14,ULA,A0,ES,SS,PSL,BGA1125 GPU:USS
1 UA000998-19109 GPU,AMD,NAVI14,ULA,A0,ES,FF,MTAG,BGA1125 GPU:UFUCRITICAL
CRITICAL1 UA000998-19110 GPU,AMD,NAVI14,ULA,A0,ES,SS,MTAG,BGA1125 GPU:USU
CRITICAL GPU:ADPTR_VDDCR1 UA000998-19111 NAVI14 ADPTR,VDDGFX,VDDSOC,D406
BOM OPTIONCRITICAL
GPU:TDPCRITICALUA0001 GPU,AMD,NAVI14,ULA,A0,ES,TDP,BGA1125998-19127
GPU:ADPTR_VMEMCRITICALUA0001998-19112 NAVI14 ADPTR,VDDCI,MVDD,D407
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
Programmable Parts
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
UB090 CRITICAL1341S01436 TBT-T,R1 (VXXXX) PROTO-3,X970
341S01434 ROM,BT SFLASH (V37) PROTO-3,X970 CRITICAL1 U3750
U3710 CRITICALWIFI ROM (V01) WW1,X6651341S00725
341S01403 CRITICAL1
ROM,VBIOS,NAVI-14,PROA (VXXX) P-0-A,X970
ROM,VBIOS,NAVI-14,ULA (VXXX) P-0-A,X970
UA130 GPU:PRA
UA1301341S01404 GPU:ULA
H9M & Alternates
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
339S00373 1 SOC:2GBCRITICALU3900
339S00371 U3900
POP,GIBRALTAR+2GB 21NM,H,B0,SCK,CSP1406
POP,GIBRALTAR+1GB 21NM,H,B0,ATK,CSP1406
PART NUMBER
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
339S00372 339S00373 H9M 2GBANY ALL
339S00377 339S00373 H9M 2GBALLANY
339S00373 H9M 2GBANY ALL339S00378
339S00371339S00376 ANY ALL H9M 1GB
339S00371 ANY ALL339S00370 H9M 1GB
339S00375 ANY ALL H9M 1GB339S00371
SSD NAND
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
NAND,3DV4,64GBT,S4E,256G,T,SUB Y,SLGA110
NAND,3DV4,64GBT,S4E,256G,SD,SUBY,SLGA110
NAND,3DV4,128GBT,S4E,256G,T,SUBY,SLGA110
NAND,3DV5,128GBT,S4E,256G,SS,SLGA110
NAND,3DV4,128GBT,S4E,256G,SD,SBY,SLGA110
5 CRITICAL SSD_NAND:WD-512998-16970 U8600,U9100,U9200,U9300,U9400
NAND,3DV4,192GBT,XXX,S4E,256G,T,SLGA110
6 SSD_NAND:TS-1TB335S00395
NAND,3DV4,192GBT,XXX,S4E,256G,H,SLGA110 U8600,U8700,U9100,U9200,U9300,U9400
6 CRITICAL SSD_NAND:WD-1TB335S00407
U8600,U9100,U9200,U9300,U9400 SSD_NAND:TS-512998-16397
U8600,U8700,U9100,U9200,U9300,U9400
BOM OPTIONCRITICAL
CRITICALU28901 TBT-X,R0 (VXXXX) PROTO-3,X970341S01435
CRITICAL
BOM OPTIONCRITICAL
CRITICAL1 SOC:1GB
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BOM OPTIONCRITICAL
SSD_NAND:TS-256CRITICALU8600,U9100,U9200,U9300,U94005998-16395
CRITICAL5998-16969 U8600,U9100,U9200,U9300,U9400
SSD_NAND:WD-256
CRITICAL5
CRITICAL5 U8600,U9100,U9200,U9300,U9400
SSD_NAND:SS-512335S00424
CRITICAL
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
SSD NAND Substrate Alts
Sub1
TABLE_5_HEAD
TABLE_5_ITEM
998-16394 998-16395 ALLANY SSD NAND: TB_256
TABLE_5_ITEM
998-16944 998-16969 ANY ALL SSD NAND: WD_256
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
Sub2
PART NUMBER
998-16970 ALLANY998-16945 SSD NAND: WD_512
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
ALL998-16396 998-16397 ANY SSD NAND: TB_512
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
D
C
B
VRAM
333S00209
PCH CNL-H
IC,GDDR6,8GBIT,14GBPS,1.35V,18NM,M,BG180
4
IC,GDDR6,8GBIT,14GBPS,1.35V,18NM,S,BG180
IC,GDDR6,16GBIT,14GBPS,1.35V,19NM,H,B180
IC,GDDR6,16GBIT,14GBPS,1.35V,16NM,M,B180
IC,GDDR6,16GBIT,14GBPS,1.35V,18NM,S,B180
TABLE_5_ITEM
NAND,3DV4,192GBT,XXX,S4E,256G,T,SLGA110
1335S00395 CRITICAL
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
BOM OPTIONCRITICAL
TABLE_5_ITEM
U9600,U9610,U9700,U9710 CRITICAL VRAM_IC:MC-4GB4
TABLE_5_ITEM
CRITICAL VRAM_IC:SS-4GBU9600,U9610,U9700,U9710333S00210
TABLE_5_ITEM
CRITICALU9600,U9610,U9700,U9710 VRAM_IC:HY-8GB333S00211 4
TABLE_5_ITEM
CRITICAL VRAM_IC:MC-8GBU9600,U9610,U9700,U9710333S00212 4
TABLE_5_ITEM
335S00408 6 SSD_NAND:WD-2TB
335S00380 8 CRITICAL
335S00391
VRAM_IC:SS-8GBCRITICALU9600,U9610,U9700,U9710333S00213 4
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
BOM OPTIONCRITICAL
TABLE_5_ITEM
NAND,3DV4,320GBT,XXX,S4E,256G,T,SLGA110
1335S00407 SSD_NAND:WD-2TBCRITICAL
NAND,3DV4,192GBT,XXX,S4E,256G,H,SLGA110
NAND,3DV4,320GBT,XXX,S4E,256G,SD,SLGA110
NAND,3DV4,512GBT,S4E,256G,H,SLGA110
8 CRITICAL
NAND,3DV4,512GBT,XXX,S4E,256G,SD,SLGA110
NAND,3DV4,1TBT,XXX,S4E,512G,SD,SLGA110
8335S00433 CRITICAL
U8600,U8700,U9100,U9200,U9300,U9400
U8600,U8700,U9100,U9200,U9300,U9400
U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400
U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400
U8600,U8700,U8800,U8900,U9100,U9200,U9300,U9400
U8800
U8800
CRITICAL
CRITICAL
SSD_NAND:TS-2TB
SSD_NAND:TS-2TB335S00397 6
SSD_NAND:HY-4TB
SSD_NAND:WD-4TB
SSD_NAND:WD-8TB
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
Plasma Cleaned
POR
PART NUMBER
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
TABLE_ALT_ITEM
ANY ALL998-18459 335S00391 SSD NAND: WD-4TB Plasma
B
CRITICALU12001337S00552 IC,CNL PCH-H,USFF,SR40F,PRQ,BGA499
A
ACE & Ridges
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,TBT,TITAN RIDGE DP,SLMHS,PRQ,C1,CSP337
IC,CD3217,ACE2,B2,USB PWR SW W/HV,BGA123
U2800,UB000 CRITICAL2338S00441
U3100,U3200,UB300,UB400 CRITICAL353S01960 4
Power Controllers
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,ISL9240HIB0Z,PMU,SOUNA,WCSP40,2.1X3.3MM
1353S01525
IC,ISL95828A,IMVP8 CPU REG,QFN48,6X6MM
338S00267 1
353S02108
IC,PMU,CALPE,D2249A0,OTP-AI,CSP324,0.4P
IC,RAA225101A2,SVI2,CONTROLLER,QFN40,5X5
IC,SUPPLY,INTERSIL,ISL6277B,SVI2.0,QFN48
WIFI/BT Module & Alternate
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
IC,MODULE,WIFI/BT,MURATA,HARPOON,M,ES7.7,LGA385
PART NUMBER
ALLANY WIFI/BT Module339S00609339S00610
U7100 CRITICAL353S00928 1
UA600 CRITICAL1
UA8001353S01660
U3730 CRITICAL339S00609 1
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
CRITICALU7000
CRITICALU7800
CRITICAL
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
SYNC_MASTER= SYNC_DATE=08/22/2018
PAGE TITLE
A
BOM Configuration 2
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
3 OF 200
SHEET
3 OF 135
8
67
35 4
2
1
Page 4
Vinafix.com
D
C
B
A
1X 870-08567
PG0410
POGO-2.3OD-4.78H-X968
SM
1
3.4OD1.75ID-1.12H-SM
3.4OD1.75ID-1.12H-SM
3.4OD1.75ID-1.12H-SM
9X 870-08821
PG0411
POGO-2.3OD-4.63H-SM
SM-1
1
PG0421
POGO-2.3OD-4.63H-SM
SM-1
1
PG0440
POGO-2.3OD-4.63H-SM
SM-1
1
PG0441
POGO-2.3OD-4.63H-SM
SM-1
1
PG0430
POGO-2.3OD-4.63H-SM
SM-1
1
PG0471
POGO-2.3OD-4.63H-SM
SM-1
1
PG0470
POGO-2.3OD-4.63H-SM
SM-1
1
PG0401
POGO-2.3OD-4.63H-SM
SM-1
1
PG0400
POGO-2.3OD-4.63H-SM
SM-1
1
2.7X1.8R-1.4ID-0.91H-SM
2.7X1.8R-1.4ID-0.91H-SM
TOUCH-COWLING-HOOK-X378
3.4OD1.75ID-1.12H-SM
3.4OD1.75ID-1.45H-SM
3.4OD1.75ID-1.45H-SM
3.4OD1.75ID-1.9H-SM
3.4OD1.75ID-1.9H-SM
3.4OD1.75ID-1.9H-SM
3.4OD1.75ID-1.9H-SM
3.4OD1.75ID-2.12H-SM
Shield Can Through-Holes
APN 998-2691
DRAM
TH0400
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0401
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0402
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0403
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0404
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0405
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0406
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0407
TH-NSP
1
SL-1.2X0.4-1.5X0.7
H9MVRAM
TH0408
1
SL-1.2X0.4-1.5X0.7
TH0409
1
SL-1.2X0.4-1.5X0.7
TBT Left
TH0410
1
SL-1.2X0.4-1.5X0.7
TH0411
1
SL-1.2X0.4-1.5X0.7
TH-NSP
TH-NSP
TH-NSP
TH-NSP
APN 860-00392
BS0400
BS0410
BS0401
BS0411
APN 806-06520
BS0420
BS0421
APN 806-06521
BS0430
BS0450
BS0431
BS0441
APN 860-00469
BS0470
BS0471
APN 806-06600
BS0480
APN 806-20398
DFR Touch - TOP side
1
1
1
1
1
USB-C Left BOT side - North
USB-C Right BOT side - North
USB-C Left BOT side - South
USB-C Right BOT side - Left
DFR Touch BOT side
1
Angle Sensor BOT side
1
1
1
DFR Display BOT side - Left
Trackpad BOT side - Left
DFR Display BOT side - Right
1
Keyboard BOT side - Right
1
eDP TOP side - Left
1
eDP TOP side - Right
1
Audio Jack + Mesa BOT side - Southwest
OMIT_TABLE
BS0472
1
SM
GPU VR
TH0412
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0413
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TBT Right
TH0420
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TH0421
TH-NSP
1
SL-1.2X0.4-1.5X0.7
678
4X 860-00986 11X 860-01209
BM0488
2.8OD1.2ID-3.59H-SM
1
2
BM0485
2.8OD1.2ID-3.59H-SM
1 2
BM0487
2.8OD1.2ID-3.59H-SM
1
2
BM0489
2.8OD1.2ID-3.59H-SM
1 2
2X 860-01447
BM0407
2.8OD1.2ID-1.55H-SM
1
2
BM0413
2.8OD1.2ID-1.55H-SM
1
2
1X 860-01394
BM0482
3.14OD1.2ID-3.69H-SM
1
2
BM0403
2.8OD1.2ID-1.65H-SM
1 2
BM0410
2.8OD1.2ID-1.65H-SM
1 2
BM0408
2.8OD1.2ID-1.65H-SM
1 2
BM0406
2.8OD1.2ID-1.65H-SM
1 2
BM0402
2.8OD1.2ID-1.65H-SM
1 2
BM0483
2.8OD1.2ID-1.65H-SM
1 2
BM0409
2.8OD1.2ID-1.65H-SM
1 2
BM0405
2.8OD1.2ID-1.65H-SM
1 2
BM0412
2.8OD1.2ID-1.65H-SM
1 2
3X 860-01208
BM0400
2.8OD1.2ID-4.4H-SM
1 2
BM0484
2.8OD1.2ID-4.4H-SM
1
2
BM0486
2.8OD1.2ID-4.4H-SM
1
2
1X 860-01452
BM0411
3.21OD1.2ID-4.163H-SM
1
2
3 245
OMIT_TABLE
1
SH0400
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0416
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0415
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0405
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0407
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0410
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0411
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
Dummy Parts
Bumpers & Bridges
NOSTUFF
C0404
1UF
1 2
10%
402
CKPLUS_WAIVE=TERMSHORTED
CERM6.3V
C0406
1UF
1 2
10%
6.3V CERM
CKPLUS_WAIVE=TERMSHORTED
402
C0420
1.0UF
1 2
20%4V0201
CKPLUS_WAIVE=TERMSHORTED
X6S
NOSTUFF
C0421
1.0UF
1 2
20%
0201
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0422
1.0UF
1 2
20%
0201
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0423
1.0UF
1 2
20%
0201
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0424
1.0UF
1 2
20%
0201
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0425
1.0UF
1 2
20%
0201 X6S
4V
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0426
1.0UF
1 2
020120%
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0427
1
D
C
1.0UF
1 2
20%
OMIT_TABLE
1
SH0412
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0414
SM
SHIELD-DIPLEX-BLACK-X378A-X1099
CKPLUS_WAIVE=TERMSHORTED
CKPLUS_WAIVE=TERMSHORTED
CKPLUS_WAIVE=TERMSHORTED
0201 X6S
4V
NOSTUFF
C0428
1.0UF
1 2
0201
20%
4V X6S
NOSTUFF
C0429
1.0UF
1 2
20%
0201
4V X6S
NOSTUFF
C0430
B
1.0UF
OMIT_TABLE
1
SH0413
SM
1 2
0201
20%
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0431
1.0UF
Shield Cans & Cowlings
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
SH0400 CRITICAL806-20400 1 SHIELD,FENCE,DIPLEX,X968
1806-17829 SH0407 CRITICALSHIELD,FENCE,TR,RT,X1181
1 CRITICAL806-20399 SHIELD,FENCE,TR,LT,X968 SH0410
SH0411,SH0412806-21174 2 CRITICALSHIELD,FENCE,DRAM,X1181
2 CRITICAL806-15804 SH0413,SH0415SHIELD,SLED,GPU,X1183
2 CRITICAL806-13997 SH0414,SH0416SHIELD,SLED,CPU,X1181
1 CRITICAL806-20878 SH0420SHIELD,FENCE,VRAM,X968
1 CRITICAL806-20877 SH0421SHIELD,FENCE,VRAM,BTM,X968
SHIELD-DIPLEX-BLACK-X378A-X1099
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
CRITICALSH0405806-17111 1 SHIELD,FENCE,H9M,X1181
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL1806-20876 SHIELD,FENCE,GPU VR,X968 SH0422
TABLE_5_ITEM
CRITICAL1806-20398 TOP MODULE TOUCH,COWLING,SMT HOOK,X968 BS0472
SHIELD-DIPLEX-BLACK-X378A-X1099
SHIELD-DIPLEX-BLACK-X378A-X1099
OMIT_TABLE
1
SH0420
SM
OMIT_TABLE
1
SH0421
SM
OMIT_TABLE
1
SH0422
SM
SYNC_MASTER=
PAGE TITLE
PD Parts
Apple Inc.
1 2
0201
20%
4V X6S
CKPLUS_WAIVE=TERMSHORTED
NOSTUFF
C0432
1.0UF
1 2
20%
0201
4V X6S
CKPLUS_WAIVE=TERMSHORTED
DRAWING NUMBER
051-04492
REVISION
SYNC_DATE=10/14/2018
SIZE
D
A
2.15.0
SHIELD-DIPLEX-BLACK-X378A-X1099
BOM_COST_GROUP=MECHANICALS
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
BRANCH
PAGE
4 OF 200
SHEET
4 OF 135
8
67
35 4
2
1
Page 5
Vinafix.com
D
C
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
120 13
IN IN IN IN
IN IN IN IN
OUT OUT OUT OUT
OUT OUT OUT OUT
DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>
DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>
DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>
DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>
E8 F6 E5
J9
D8 E6 D5
J8
A8 B6 A5 B4
B8 C6 B5 D4
CFL-H-DDR4-IL-8+2
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
U0500
BGA
CFLH
SYM 1 OF 13
CRITICAL
OMIT_TABLE
DMI
678
PEG_RCOMP
PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8
PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15
PEG_RXP0
PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8 PEG_RXP9
PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15
G2
D25 F24 D23 F22 D21 F20 D19 F18 E17 E16 E15 E14 E13 E12 E11 E10
E25 E24 E23 E22 E21 E20 E19 E18 D17 F16 D15 F14 D13 F12 D11 F10
CPU_PEG_RCOMP
PEG_GPU_D2R_N<0> PEG_GPU_D2R_N<1> PEG_GPU_D2R_N<2> PEG_GPU_D2R_N<3> PEG_GPU_D2R_N<4> PEG_GPU_D2R_N<5> PEG_GPU_D2R_N<6> PEG_GPU_D2R_N<7> PCIE_TBT_X_D2R_N<0> PCIE_TBT_X_D2R_N<1> PCIE_TBT_X_D2R_N<2> PCIE_TBT_X_D2R_N<3> PCIE_TBT_T_D2R_N<0> PCIE_TBT_T_D2R_N<1> PCIE_TBT_T_D2R_N<2> PCIE_TBT_T_D2R_N<3>
PEG_GPU_D2R_P<0> PEG_GPU_D2R_P<1> PEG_GPU_D2R_P<2> PEG_GPU_D2R_P<3> PEG_GPU_D2R_P<4> PEG_GPU_D2R_P<5> PEG_GPU_D2R_P<6> PEG_GPU_D2R_P<7> PCIE_TBT_X_D2R_P<0> PCIE_TBT_X_D2R_P<1> PCIE_TBT_X_D2R_P<2> PCIE_TBT_X_D2R_P<3> PCIE_TBT_T_D2R_P<0> PCIE_TBT_T_D2R_P<1> PCIE_TBT_T_D2R_P<2> PCIE_TBT_T_D2R_P<3>
From Intel EDS PEG RCOMP Range = 24.76,25.25
Voltage = VCCIO (Page 121, Note 3)
PPVCCIO_S0_CPU
1
R0510
24.9
1% 1/16W MF-LF 402
2
PLACE_NEAR=U0500.G2:5mm
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
119
IN
5 8 10 117 124
119
NC_DDI1_ML_C_N<0>
NC_DDI1_ML_C_P<0>
119
119
NC_DDI1_ML_C_N<1> NC_DDI1_ML_C_P<1>
119
119
NC_DDI1_ML_C_N<2> NC_DDI1_ML_C_P<2>
119
119
NC_DDI1_ML_C_N<3> NC_DDI1_ML_C_P<3>
119
NC_DDI2_ML_C_N<0>
119
NC_DDI2_ML_C_P<0>
119
119
NC_DDI2_ML_C_N<1>
119
NC_DDI2_ML_C_P<1> NC_DDI2_ML_C_N<2>
119
NC_DDI2_ML_C_P<2>
119
119
NC_DDI2_ML_C_N<3>
119
NC_DDI2_ML_C_P<3>
NC_DDI3_ML_N<2>
119
NC_DDI3_ML_P<2>
119
119
NC_DDI3_ML_N<3> NC_DDI3_ML_P<3>
119
NC_DDI3_ML_N<0>
119
119
NC_DDI3_ML_P<0>
119
NC_DDI3_ML_N<1> NC_DDI3_ML_P<1>
119
Port D pins out of order to match Intel symbol.
K37 K36
J34
J35 H36 H37
J38
J37
H33 H34 G38
F37 F35 F34 E36 E37
E33 F33 B33
C33 D34
C34
B34 B36
3 245
CFL-H-DDR4-IL-8+2
DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3
DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3
DDI3_TXN2 DDI3_TXP2 DDI3_TXN3 DDI3_TXP3
DDI3_TXN0 DDI3_TXP0 DDI3_TXN1 DDI3_TXP1
U0500
BGA
CFLH
SYM 11 OF 13
CRITICAL
OMIT_TABLE
EDP
DIGITAL DISPLAY INTERFACES
EDP_AUXN EDP_AUXP
EDP_TXN0 EDP_TXN1 EDP_TXN2 EDP_TXN3
EDP_TXP0 EDP_TXP1 EDP_TXP2 EDP_TXP3
DISP_RCOMP
EDP_DISP_UTIL
DDI1_AUXN DDI1_AUXP
DDI2_AUXN DDI2_AUXP
DDI3_AUXN DDI3_AUXP
B26 C26
E29 E28 B29 B28
D29 F28 A29 C28
D37 A33
E27 D27
E26 F26
B27 A27
NC
DP_INT_IG_AUX_N DP_INT_IG_AUX_P
DP_INT_IG_ML_N<0> DP_INT_IG_ML_N<1> DP_INT_IG_ML_N<2> DP_INT_IG_ML_N<3>
DP_INT_IG_ML_P<0> DP_INT_IG_ML_P<1> DP_INT_IG_ML_P<2> DP_INT_IG_ML_P<3>
CPU_EDP_RCOMP
NC_DDI1_AUXCH_C_N NC_DDI1_AUXCH_C_P
NC_DDI2_AUXCH_C_N NC_DDI2_AUXCH_C_P
NC_DDI3_AUXCH_N NC_DDI3_AUXCH_P
119
119
119
119
119
119
1
120 95
120 95
120 95
120 95
120 95
120 95
120 95
120 95
120 95
120 95
PPVCCIO_S0_CPU
1
R0530
24.9
1% 1/16W MF-LF 402
2
PLACE_NEAR=U0500.D37:5mm
D
124
5 8 10
117
C
B
PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5
PCI EXPRESS BASED INTERFACE SIGNALS
PEG_TXN6 PEG_TXN7 PEG_TXN8
PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
A25 C24 A23 C22 A21 C20 A19 C18 B17 B16 B15 B14 B13 B12 B11 B10
B25 B24 B23 B22 B21 B20 B19 B18 A17 C16 A15 C14 A13 C12 A11 C10
PEG_GPU_R2D_C_N<0> PEG_GPU_R2D_C_N<1> PEG_GPU_R2D_C_N<2> PEG_GPU_R2D_C_N<3> PEG_GPU_R2D_C_N<4> PEG_GPU_R2D_C_N<5> PEG_GPU_R2D_C_N<6> PEG_GPU_R2D_C_N<7> PCIE_TBT_X_R2D_C_N<0> PCIE_TBT_X_R2D_C_N<1> PCIE_TBT_X_R2D_C_N<2> PCIE_TBT_X_R2D_C_N<3> PCIE_TBT_T_R2D_C_N<0> PCIE_TBT_T_R2D_C_N<1> PCIE_TBT_T_R2D_C_N<2> PCIE_TBT_T_R2D_C_N<3>
PEG_GPU_R2D_C_P<0> PEG_GPU_R2D_C_P<1> PEG_GPU_R2D_C_P<2> PEG_GPU_R2D_C_P<3> PEG_GPU_R2D_C_P<4> PEG_GPU_R2D_C_P<5> PEG_GPU_R2D_C_P<6> PEG_GPU_R2D_C_P<7> PCIE_TBT_X_R2D_C_P<0> PCIE_TBT_X_R2D_C_P<1> PCIE_TBT_X_R2D_C_P<2> PCIE_TBT_X_R2D_C_P<3> PCIE_TBT_T_R2D_C_P<0> PCIE_TBT_T_R2D_C_P<1> PCIE_TBT_T_R2D_C_P<2> PCIE_TBT_T_R2D_C_P<3>
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
TP-P5 TP-P5
TP-P5 TP-P5 TP-P5
TP0501 TP0502
TP0503 TP0504 TP0505
TP TP
TP TP TP
U0500
CFL-H-DDR4-IL-8+2
BGA
1 1
1 1 1
CPU_DC_B2_C1 CPU_IST_TRIG CPU_DC_B38_C38
NC
CPU_DC_BR2_BR1 CPU_DC_C1_B2 CPU_DC_C38_B38
NC
NC
BR33
AT13
AW13
NC
RSVD IST_TRIG
B2
RSVD
B38
RSVD
BP1
RSVD
BR2
RSVD
C1
RSVD
C38
SKTOCC* ZVM*
MSM*
CFLH
SYM 13 OF 13
PROC_TRIGIN
PROC_TRIGOUT
PROC_AUDIO_CLK
PROC_AUDIO_SDI
PROC_AUDIO_SDO
DDR_VTT_CNTL
PM_DOWN
Impedance Spectrum Tool
E3
H23 J23
G27 G25 G29
BT13 BP31
PCH_CPU_TRIGGER CPU_PCH_TRIGGER_R
PCH_DISPA_BCLK PCH_DISPA_SDO CPU_PROC_AUD_SDO_R
PM_MEMVTT_EN CPU_PCH_PM_DOWN_R
Each corner of CPU has two testpoints.
5
5
IN
IN IN
5
OUT
13
20
20
1
TP-P6
1
TP-P6
PLACE_NEAR=TP0506.1:5mm
121 74
A
TP0506
A
TP0507
B
Other corner test signals connected in daisy-chain fashion. Continuity should exist between both TP's on each corner.
R0524
5
CPU_PCH_TRIGGER_R
30
1 2
5%
1/20W
MF
201
CPU_PCH_TRIGGER
OUT
13
A
5
5
BOM_COST_GROUP=CPU & CHIPSET
CPU_PCH_PM_DOWN_R
CPU_PROC_AUD_SDO_R
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
R0525
20
1 2
5%
1/20W
MF
201
R0526
20
1 2
5%
1/20W
MF
201
CPU_PCH_PM_DOWN
PCH_DISPA_SDI
Apple Inc.
13
OUT
20
OUT
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
5 OF 200
SHEET
5 OF 135
A
SIZE
D
8
67
35 4
2
1
Page 6
Vinafix.com
678
3 245
1
D
C
8 11 117
8 11 46 117
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
PP1V05_S0SW PP1V05_S3
46
CPU_PROCHOT_L
IN
121 46
These can be placed close to
J1800 and only for debug access
NOSTUFF
R0649
1K
5%
1/20W
MF
201
CPU_CFG<16> CPU_CFG<9> CPU_CFG<3> CPU_CFG<1> CPU_CFG<0>
NOSTUFF
1K
5%
1/20W
MF
201
1
2
1
2
R0648
NOSTUFF
1
R0643
1K
5% 1/20W MF 201
2
NOSTUFF
R0641
1K
5%
1/20W
MF
201
1
2
NOSTUFF
1
R0640
1K
5% 1/20W MF 201
2
18 6
18 6
18 6
18 6
18 6
PP0600 PP0601
PP0602 PP0603
18 6
18 6
18 6
18 6
18 6
NOSTUFF
R0647
1K
5%
1/20W
MF
201
CPU_CFG<7> CPU_CFG<6> CPU_CFG<5> CPU_CFG<4>
CPUCFG6_PD
1
2
R0646
1K
5%
1/20W
MF
201
1
2
CPUCFG5_PD
1
R0645
1K
5% 1/20W MF 201
2
EDP:YES
R0644
1K
5%
1/20W
MF
201
CPU_CFG<2>
NOSTUFF
1
2
1
R0642
1K
5% 1/20W MF 201
2
P2MM
SM
1
PP
P2MM
SM
1
PP
P2MM
SM
1
PP
P2MM
SM
1
PP
OUT
CPU_RSVD_R14
CPU_RSVD_N29
CPU_RSVD_AE29
CPU_RSVD_AA14
TP0619
1
R0605
1K
1% 1/16W MF-LF 402
2
A
TP-P6
NOSTUFF
1
R0604
1K
1% 1/16W MF-LF 402
2
TP_CPU_RSVD_TP_D1
1
PPVCC_S0_CPU
8 58 117
6
6
6
6
1
R0601
1K
1% 1/16W MF-LF 402
2
6
6
6
6
CPU_RSVD_R14 CPU_RSVD_N29 CPU_RSVD_AE29 CPU_RSVD_AA14
77
OUT
PLACE_NEAR=U0500.BR30:5mm
R0603
499
1 2
1%
201
1/20W
MF
46 13
13
13
121 13
120 12
120 12
120 12
120 12
120 12
120 12
BI
IN IN IN
IN IN
IN IN
IN IN
D1
V30 V12 V29 Y35
R14
N29 AE29 AA14
CPU_CATERR_L
CPU_PECI
CPU_PROCHOT_R_L
PM_THRMTRIP_L
PM_SYNC CPU_RESET_L CPU_PWRGD
CPU_CLK24M_NSSC_CLK_N CPU_CLK24M_NSSC_CLK_P
CPU_CLK100M_PCIBCLK_N CPU_CLK100M_PCIBCLK_P
CPU_CLK100M_BCLK_N CPU_CLK100M_BCLK_P
CRITICAL OMIT_TABLE
RSVD_TP
VSS VSS VSS VCC
RSVD RSVD RSVD RSVD
PLACE_NEAR=U0500.BT31:157mm
CFL-H-DDR4-IL-8+2
U0500
BGA
CFLH
SYM 12 OF 13
RESERVED
(IPU)
(IPU)
CFG_RCOMP
CFG16 CFG18 CFG17 CFG19
R0611
RSVD RSVD RSVD RSVD
RSVD
10K
5% 1/16W MF-LF
402
BT25 BP23
BN22 BN23 BP22
AU13 AY13 J24 J3
BN33
U0500
CFL-H-DDR4-IL-8+2
PROC_SELECT*
NC
1
2
BN1
BM30
BT34
BR30
J31
BM34
BP35
BT31
D31 E31
C36 D35
A32 B31
CATERR*
PECI
PROCHOT*
THERMTRIP*
PM_SYNC RESET* PROCPWRGD
CLK24N CLK24P
PCI_BCLKN PCI_BCLKP
BCLKN BCLKP
CRITICAL OMIT_TABLE
CPU_CFG_RCOMP CPU_CFG<16>
CPU_CFG<18> CPU_CFG<17> CPU_CFG<19>
NC NC NC NC
NC
BGA
CFLH
SYM 2 OF 13
THERMALPWRCLOCK
18 6
18
TP-P5
TP-P5
DDR3
(IPU) (IPU)
(IPD) (IPU)
(IPU)
(IPU)
JTAG
1
TP
TP0617
1
TP
TP0618
DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2
PROC_PRDY* PROC_PREQ*
PROC_TCK
PROC_TMS
PROC_TRST*
PROC_TDI
PROC_TDO
(IPU) (IPU) (IPU) (IPU)
BPM0* BPM1* BPM2* BPM3*
G1 H1 J2
BP27 BL30
BR28 BP28 BP30
BL32 BT28
BR27 BT27
BM31
BT30
1
R0690
49.9
1% 1/16W MF-LF 402
2
CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>
XDP_CPU_PRDY_L XDP_CPU_PREQ_L
XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L
XDP_CPU_TDI XDP_CPU_TDO
XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3>
OUT
IN
IN IN IN
IN
OUT
BI BI BI BI
18
18
18
18
1
R0614
100
2
1% 1/16W MF-LF 402
123 18 13
123 18 13
123 18
123 18
123 18 13
123 18
123 18
1
R0613
121
1% 1/16W MF-LF 402
2
1
R0612
121
1% 1/16W MF-LF 402
2
D
C
B
TP0601 TP0602 TP0603 TP0604 TP0605 TP0606 TP0607 TP0608 TP0609 TP0610 TP0611 TP0612 TP0613 TP0614 TP0615 TP0616
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
TP-P6
A
CPU_CFG<0>
1
CPU_CFG<1>
1
CPU_CFG<2>
1
CPU_CFG<3>
1
CPU_CFG<4>
1
CPU_CFG<5>
1
CPU_CFG<6>
1 1
CPU_CFG<7>
CPU_CFG<8>
1
CPU_CFG<9>
1
CPU_CFG<10>
1
CPU_CFG<11>
1
CPU_CFG<12>
1 1
CPU_CFG<13> CPU_CFG<14>
1 1
CPU_CFG<15>
NC NC
BN25 BN27 BN26 BN28 BR20
BM20
BT20 BP20 BR23 BR22
BT23
BT22
BM19
BR19 BP19
BT19
G3
G13
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
RSVD RSVD
(IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU)
RSVD RSVD
RSVD
RSVD
RSVD_TP RSVD_TP
VSS VSS
VSS VSS
RSVD RSVD RSVD
BR35 BR31
BN35
C30
BT2 BR1
W3 W2
V6 W1
H24 E30 F30
NC NC
NC
NC
TP_CPU_RSVD_TP_BT2 CPU_DC_BR1_BR2
NC NC NC
TP-P5
TP-P5
B
1
TP
1
TP0620
TP
TP0600
A
8
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_ITEM
CPUCFG5_PDCPUPEG:X8X8
TABLE_BOMGROUP_ITEM
CPUCFG6_PD,CPUCFG5_PDCPUPEG:X8X4X4
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
CPU Clock/Misc/JTAG/CFG
To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
6 OF 200
SHEET
6 OF 135
1
SIZE
D
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678
3 245
1
D
C
B
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
120 26 23 22
120 26 23 22
21
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT
IN
OUT
MEM_A_DQ<45> MEM_A_DQ<41> MEM_A_DQ<44> MEM_A_DQ<40> MEM_A_DQ<47> MEM_A_DQ<43> MEM_A_DQ<46> MEM_A_DQ<42> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<53> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<48> MEM_A_DQ<62> MEM_A_DQ<63> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<35> MEM_A_DQ<37> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<34> MEM_A_DQ<36> MEM_A_DQ<26> MEM_A_DQ<24> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<25> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<1> MEM_A_DQ<4> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<0> MEM_A_DQ<5> MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<13> MEM_A_DQ<8> MEM_A_DQ<14> MEM_A_DQ<9> MEM_A_DQ<15> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<16> MEM_A_DQ<19>
MEM_A_PAR MEM_A_ALERT_L CPU_DIMM_VREFCA MEM_A_ACT_L
DDR0_DQ0
BR6
DDR0_DQ1
BT6
DDR0_DQ2
BP3
DDR0_DQ3
BR3
DDR0_DQ4
BN5
DDR0_DQ5
BP6
DDR0_DQ6
BP2
DDR0_DQ7
BN3
DDR0_DQ8
BL4
DDR0_DQ9
BL5
DDR0_DQ10
BL2
DDR0_DQ11
BM1
DDR0_DQ12
BK4
DDR0_DQ13
BK5
DDR0_DQ14
BK1
DDR0_DQ15
BK2
DDR0_DQ16
BG4
DDR0_DQ17
BG5
DDR0_DQ18
BF4
DDR0_DQ19
BF5
DDR0_DQ20
BG2
DDR0_DQ21
BG1
DDR0_DQ22
BF1
DDR0_DQ23
BF2
DDR0_DQ24
BD2
DDR0_DQ25
BD1
DDR0_DQ26
BC4
DDR0_DQ27
BC5
DDR0_DQ28
BD5
DDR0_DQ29
BD4
DDR0_DQ30
BC1
DDR0_DQ31
BC2
DDR0_DQ32
AB1
DDR0_DQ33
AB2
DDR0_DQ34
AA4
DDR0_DQ35
AA5
DDR0_DQ36
AB5
DDR0_DQ37
AB4
DDR0_DQ38
AA2
DDR0_DQ39
AA1
DDR0_DQ40
V5
DDR0_DQ41
V2
DDR0_DQ42
U1
DDR0_DQ43
U2
DDR0_DQ44
V1
DDR0_DQ45
V4
DDR0_DQ46
U5
DDR0_DQ47
U4
DDR0_DQ48
R2
DDR0_DQ49
P5
DDR0_DQ50
R4
DDR0_DQ51
P4
DDR0_DQ52
R5
DDR0_DQ53
P2
DDR0_DQ54
R1
DDR0_DQ55
P1
DDR0_DQ56
M4
DDR0_DQ57
M1
DDR0_DQ58
L4
DDR0_DQ59
L2
DDR0_DQ60
M5
DDR0_DQ61
M2
DDR0_DQ62
L5
DDR0_DQ63
L1
DDR0_PAR
AG3
DDR0_ALERT*
AU5
DDR_VREF_CA
BN13
DDR0_ACT*
AU3
U0500
BGA
SYM 3 OF 13
CFLH
CFL-H-DDR4-IL-8+2
CRITICAL OMIT_TABLE
DDR0_CKN0 DDR0_CKP0 DDR0_CKE0
DDR0_CKN1 DDR0_CKP1 DDR0_CKE1
DDR0_CKN2 DDR0_CKP2 DDR0_CKE2
DDR0_CKN3 DDR0_CKP3 DDR0_CKE3
DDR0_CS0* DDR0_CS1* DDR0_CS2* DDR0_CS3*
DDR0_ODT0 DDR0_ODT1 DDR0_ODT2 DDR0_ODT3
MEMORY CHANNEL DDR0
DDR0_ECC0 DDR0_ECC1 DDR0_ECC2 DDR0_ECC3 DDR0_ECC4 DDR0_ECC5 DDR0_ECC6 DDR0_ECC7
DDR0_DQSN0 DDR0_DQSN1 DDR0_DQSN2 DDR0_DQSN3 DDR0_DQSN4 DDR0_DQSN5 DDR0_DQSN6 DDR0_DQSN7 DDR0_DQSN8
DDR0_DQSP0 DDR0_DQSP1 DDR0_DQSP2 DDR0_DQSP3 DDR0_DQSP4 DDR0_DQSP5 DDR0_DQSP6 DDR0_DQSP7 DDR0_DQSP8
VSS
AG2 AG1 AT1
AK1 AK2 AT2
AK3 AL3 AT3
AL1 AL2 AT5
AD5 AE2 AD2 AE5
AD3 AE4 AE1 AD4
U38
BA2 BA1 AY4 AY5 BA5 BA4 AY1 AY2
BR5 BL3 BG3 BD3 AA3 U3 P3 L3 BA3
BP5 BK3 BF3 BC3 AB3 V3 R3 M3 AY3
NC NC
NC NC
NC NC
NC NC
NC NC NC NC NC NC NC NC
NC
NC
MEM_A_CLK_N<0> MEM_A_CLK_P<0> MEM_A_CKE<0>
NC_MEM_A_CLK_N<1> NC_MEM_A_CLK_P<1> MEM_A_CKE<1>
NC_MEM_A_CKE<2>
NC_MEM_A_CKE<3>
MEM_A_CS_L<0> MEM_A_CS_L<1>
MEM_A_ODT<0> MEM_A_ODT<1>
MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7> MEM_A_DQS_N<4> MEM_A_DQS_N<3> MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2>
MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7> MEM_A_DQS_P<4> MEM_A_DQS_P<3> MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2>
OUT OUT OUT
OUT OUT OUT
OUT
OUT
OUT OUT
OUT OUT
BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
120 26 23 22
120 26 23 22
120 26 23 22
120 26
120 26
120 26 23 22
120 26
120 26
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 25 24
120 26 25 24 120 26 23 22
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT
INOUT
MEM_B_DQ<22> MEM_B_DQ<16> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<20> MEM_B_DQ<23> MEM_B_DQ<19> MEM_B_DQ<21> MEM_B_DQ<11> MEM_B_DQ<14> MEM_B_DQ<9> MEM_B_DQ<12> MEM_B_DQ<15> MEM_B_DQ<13> MEM_B_DQ<8> MEM_B_DQ<10> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<7> MEM_B_DQ<1> MEM_B_DQ<4> MEM_B_DQ<0> MEM_B_DQ<25> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<26> MEM_B_DQ<31> MEM_B_DQ<24> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<35> MEM_B_DQ<32> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<60> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63> MEM_B_DQ<54> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<55> MEM_B_DQ<50> MEM_B_DQ<53> MEM_B_DQ<41> MEM_B_DQ<46> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<42> MEM_B_DQ<47> MEM_B_DQ<40> MEM_B_DQ<45>
MEM_B_PAR MEM_B_ALERT_L
DDR1_DQ0
BT11
DDR1_DQ1
BR11
DDR1_DQ2
BT9
DDR1_DQ3
BR8
DDR1_DQ4
BP11
DDR1_DQ5
BN11
DDR1_DQ6
BP8
DDR1_DQ7
BN8
DDR1_DQ8
BL12
DDR1_DQ9
BL11
DDR1_DQ10
BL8
DDR1_DQ11
BJ8
DDR1_DQ12
BJ11
DDR1_DQ13
BJ10
DDR1_DQ14
BL7
DDR1_DQ15
BJ7
DDR1_DQ16
BG11
DDR1_DQ17
BG10
DDR1_DQ18
BG8
DDR1_DQ19
BF8
DDR1_DQ20
BF11
DDR1_DQ21
BF10
DDR1_DQ22
BG7
DDR1_DQ23
BF7
DDR1_DQ24
BB11
DDR1_DQ25
BC11
DDR1_DQ26
BB8
DDR1_DQ27
BC8
DDR1_DQ28
BC10
DDR1_DQ29
BB10
DDR1_DQ30
BC7
DDR1_DQ31
BB7
DDR1_DQ32
AA11
DDR1_DQ33
AA10
DDR1_DQ34
AC11
DDR1_DQ35
AC10
DDR1_DQ36
AA7
DDR1_DQ37
AA8
DDR1_DQ38
AC8
DDR1_DQ39
AC7
DDR1_DQ40
W8
DDR1_DQ41
W7
DDR1_DQ42
V10
DDR1_DQ43
V11
DDR1_DQ44
W11
DDR1_DQ45
W10
DDR1_DQ46
V7
DDR1_DQ47
V8
DDR1_DQ48
R11
DDR1_DQ49
P11
DDR1_DQ50
P7
DDR1_DQ51
R8
DDR1_DQ52
R10
DDR1_DQ53
P10
DDR1_DQ54
R7
DDR1_DQ55
P8
DDR1_DQ56
L11
DDR1_DQ57
M11
DDR1_DQ58
L7
DDR1_DQ59
M8
DDR1_DQ60
L10
DDR1_DQ61
M10
DDR1_DQ62
M7
DDR1_DQ63
L8
DDR1_PAR
AJ7
AR8
DDR1_ALERT*
U0500
CFL-H-DDR4-IL-8+2
BGA
SYM 4 OF 13
CFLH
CRITICAL
OMIT_TABLE
DDR1_CKN0 DDR1_CKP0 DDR1_CKE0
DDR1_CKN1 DDR1_CKP1 DDR1_CKE1
DDR1_CKN2 DDR1_CKP2 DDR1_CKE2
DDR1_CKN3 DDR1_CKP3 DDR1_CKE3
DDR1_CS0* DDR1_CS1* DDR1_CS2* DDR1_CS3*
DDR1_ODT0 DDR1_ODT1 DDR1_ODT2 DDR1_ODT3
MEMORY CHANNEL DDR1
DDR1_ECC0 DDR1_ECC1 DDR1_ECC2 DDR1_ECC3 DDR1_ECC4 DDR1_ECC5 DDR1_ECC6 DDR1_ECC7
DDR1_DQSN0 DDR1_DQSN1 DDR1_DQSN2 DDR1_DQSN3 DDR1_DQSN4 DDR1_DQSN5 DDR1_DQSN6 DDR1_DQSN7 DDR1_DQSN8
DDR1_DQSP0 DDR1_DQSP1 DDR1_DQSP2 DDR1_DQSP3 DDR1_DQSP4 DDR1_DQSP5 DDR1_DQSP6 DDR1_DQSP7 DDR1_DQSP8
VSS
AN9 AM9 AT8
AM8 AM7 AT10
AM10 AM11 AT7
AJ11 AJ10 AT11
AF11 AE7 AF10 AE10
AF7 AE8 AE9 AE11
Y38
AW11 AY11 AY8 AW8
AY10 AW10 AY7 AW7
BN9 BL9 BG9 BC9 AC9
W9
R9
M9 AY9
BP9
BJ9 BF9 BB9 AA9 V9
P9
L9 AW9
NC NC
NC NC
NC NC
NC NC
NC NC NC NC
NC
NC
MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CKE<0>
NC_MEM_B_CLK_N<1> NC_MEM_B_CLK_P<1> MEM_B_CKE<1>
NC_MEM_B_CKE<2>
NC_MEM_B_CKE<3>
MEM_B_CS_L<0> MEM_B_CS_L<1>
MEM_B_ODT<0> MEM_B_ODT<1>
NC NC NC NC
MEM_B_DQS_N<2> MEM_B_DQS_N<1> MEM_B_DQS_N<0> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<7> MEM_B_DQS_N<6> MEM_B_DQS_N<5>
MEM_B_DQS_P<2> MEM_B_DQS_P<1> MEM_B_DQS_P<0> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<7> MEM_B_DQS_P<6> MEM_B_DQS_P<5>
OUT OUT OUT
OUT OUT OUT
OUT
OUT
OUT OUT
OUT OUT
BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI
120 26 25 24
120 26 25 24
120 26 25 24
120 26
120 26
120 26 25 24
D
120 26
120 26
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
C
128
128
128
128
128
128
128
128
B
128
128
128
128
128
128
128
128
A
21
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
OUT
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
CPU_DIMMB_VREFDQ
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
NC
DDR0_VREF_DQ
BP13
DDR1_VREF_DQ
BR13
DDR0_MA0
AH3
DDR0_MA1
AP4
DDR0_MA2
AN4
DDR0_MA3
AP5
DDR0_MA4
AP2
DDR0_MA5
AP1
DDR0_MA6
AP3
DDR0_MA7
AN1
DDR0_MA8
AN3
DDR0_MA9
AT4
DDR0_MA10
AH2
DDR0_MA11
AN2
DDR0_MA12
AU4
DDR0_MA13
AE3
DDR0_MA14
AG4
DDR0_MA15
AD1
DDR0_MA16
AH4
RSVD RSVD RSVD
DDR0_BA0
DDR0_BA1 DDR0_BG0 DDR0_BG1
AJ8 B30 BH30
AH5 AH1 AU1 AU2
NC NC NC
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
OUT OUT OUT OUT
120 26 25 24
120 26 23 22
120 26 23 22
120 26 23 22
120 26 23 22
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
OUT
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
MEM_B_ACT_L
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
AT9
AJ9 AK6 AK5
AL5 AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11 AR10
AF9
AH11
AF8
AH10
DDR1_ACT*
DDR1_MA0 DDR1_MA1 DDR1_MA2 DDR1_MA3 DDR1_MA4 DDR1_MA5 DDR1_MA6 DDR1_MA7 DDR1_MA8 DDR1_MA9 DDR1_MA10 DDR1_MA11 DDR1_MA12 DDR1_MA13 DDR1_MA14 DDR1_MA15 DDR1_MA16
RSVD
RSVD
DDR1_BA0
DDR1_BA1 DDR1_BG0 DDR1_BG1
BK28
BJ28
AH8 AH9 AR9 AR7
NC
NC
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0> MEM_B_BG<1>
BOM_COST_GROUP=CPU & CHIPSET
OUT OUT OUT OUT
120 26 25 24
120 26 25 24
120 26 25 24
120 26 25 24
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
CPU DDR4 Interfaces
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
051-04492
REVISION
2.15.0
2.15.0
BRANCH
PAGE
7 OF 200
7 OF 200
SHEET
7 OF 135
7 OF 135
8
67
35 4
2
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Page 8
Vinafix.com
678
3 245
1
D
C
B
A
6 8 58 117
PP1V05_S3
6 8 11
46 117
CPU_VCCST_PWRGD_R
8
6 11 117
PP1V05_S0SW
PULL-UPS FOR SENSE LINES
1
R0864
100
5% 1/20W MF 201
2
PPVCC_S0_CPU
1
1
R0865
100
5% 1/20W MF 201
2
R0866
100
5% 1/20W MF 201
2
AP38 AG12 AP37 AP36 AP35 AP32 AP31 AP30
AP13 AN38 AN37 AN36 AN35 AN34 AN33 AN32 AN31 AN14 AN13 AM36 AM35 AM34 AM33 AM32 AM31 AM30 AM29 AM14 AM13
AL38
AL37
AL36
AL35
AL32
AL31
AL30
AL29
AL13
AK38
AK37
AK36
AK35
AK34
AK33
AK32
AK31
AJ36 AJ35 AJ34 AJ33 AJ32 AJ31 AJ30 AJ29
AJ14 AH32 AH31 AH30 AH29 AH14 AH13 AG36 AG35 AG34 AG33 AG32 AG31 AG14
AF34 AF33 AF32 AF31 AF30 AF29
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCCST
H30
VCCST_PWRGD
H13
VCCSTG
G30
VCCSTG
H29
U0500
BGA
SYM 6 OF 13
POWER
CFL-H-DDR4-IL-8+2
CFLH
CRITICAL
OMIT_TABLE
VCCIO_SENSE
VSSIO_SENSE
VCCSA_SENSE
VSSSA_SENSE
PPVCC_S0_CPU PPVCCGT_S0_CPU PPVCCSA_S0_CPU
PPVCCIO_S0_CPU
1
R0861
100
5% 1/20W MF 201
2
PLACE_NEAR=U0500.H14:50.8mm PLACE_NEAR=U0500.AG37:50.8mm PLACE_NEAR=U0500.AH38:50.8mm PLACE_NEAR=U0500.M38:50.4mm
CPU_VCCIOSENSE_P CPU_VCCSASENSE_P
CPU_VCCGTSENSE_P
CPU_VCCSENSE_P
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA
VCCPLL VCCPLL
VCCPLL_OC VCCPLL_OC VCCPLL_OC
6 8 58 117
8 58 117
8 58 117 126
5 8 10 117 124
78 8
69 8
69 8
69 8
G15 G17 G19 G21 H15 H16 H17 H19 H20 H21 H26 H27 J15 J16 J17 J19 J20 J21 J26 J27
H14 J14
J30 K29 K30 K31 K32 K33 K34 K35 L31 L32 L35 L36 L37 L38 M29 M30 M31 M32 M33 M34 M35 M36
M38 M37
H28 J28
BH13 G11 BJ13
PPVCCIO_S0_CPU
CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N
PPVCCSA_S0_CPU
CPU_VCCSASENSE_P
CPU_VCCSASENSE_N
PP1V05_S3
Place C0802 on bottom side of U0500 Place C0803 on bottom side of U0500 PP1V2_S0SW
80 46
IN
6 8 11 46 117
PP1V05_S3
69
BI
6 8 11 46 117
5 8 10 117 124
OUT OUT
8 58 117 126
OUT OUT
69 8
69 9
11 117
CPU_VIDSOUT
C0802
1
1UF
20%
6.3V
2
X6S-CERM 0201
PP1V05_S3
78 8
78 9
C0803
1
1UF
20%
6.3V
2
X6S-CERM 0201
NOSTUFF
NOSTUFF
1
R0802
100
5% 1/20W MF 201
2
69
69
CPU_VIDALERT_L
IN
CPU_VIDSCLK
OUT
R0812
0
1 2
5% 1/16W MF-LF
402
117
PLACE_NEAR=U0500.H13:1MM
1
R0840
1K
1% 1/16W MF-LF 402
2
1
R0842
100
5% 1/20W MF 201
2
PP1V2_S3_CPUDDR
117
6 8 58 117
PPVCC_S0_CPU
69 8
OUT
69 9
OUT
1
R0800
56.2
1% 1/20W MF 201
2
R0810
220
1 2
5%
1/20W
MF
201
R0811
0
1 2
5% 1/16W MF-LF
402
PLACE_NEAR=U0500.H13:1MM
R0841
60.4
1 2
1%
1/20W
MF
201
TP0800 TP0801
6 8 58 117
CPU_VCCSENSE_P CPU_VCCSENSE_N
CPU_VIDALERT_R_L CPU_VIDSCLK_R CPU_VIDSOUT_R
TP_CPU_RSVD_TP75
1
TP
TP-P5
TP_CPU_RSVD_TP76
1
TP
TP-P5
PPVCC_S0_CPU
CPU_VCCST_PWRGD_RCPU_VCCST_PWRGD
NC NC NC NC
BL31
BL34 AP14 AP29
AA6
AE12
AF5
AF6 AG5 AG9
AJ12 AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5 J6
K12
K6
L12
L6 R6 T6
W6
Y12
U36 V13
AG37 AG38
BH31 BH32 BH29
Y7
Y8 E2 E1
Y9
Y13
W4
W34
Y10
W5
Y14
W12
Y37
W33
Y11
AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AB30 AB31 AA38 AB29
V14 V31 V32 V33 V34 V35 V36 V37
V38 W13 W14
RSVD RSVD RSVD RSVD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VCC VCC
VCC_SENSE VSS_SENSE
VIDALERT* VIDSCK VIDSOUT
VSS
VSS RSVD_TP RSVD_TP
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
CFL-H-DDR4-IL-8+2
U0500
BGA
CFLH
SYM 5 OF 13
CRITICAL
OMIT_TABLE
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
PPVCC_S0_CPU
AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38 K13 K14 L13 L14 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13 P14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y36
6 8 58 117
PPVCCGT_S0_CPU
8 58 117
BOM_COST_GROUP=CPU & CHIPSET
AT14 AT31 AT32 AT33 AT34 AT35 AT36 AT37
AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36
AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38
AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BE31 BE32 BE33
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
CFL-H-DDR4-IL-8+2
U0500
BGA
CFLH
SYM 7 OF 13
POWER
CRITICAL
OMIT_TABLE
VCCGT_SENSE
VSSGT_SENSE
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
BE34 BE35 BE36 BE37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38 BJ16 BJ17 BJ19 BJ20 BJ21 BJ23 BJ24 BJ26 BJ27 BJ37 BJ38 BK16 BK17 BK19 BK20 BK21 BK23 BK24 BK26 BK27 BL15 BL16 BL17 BL23 BL24 BL25 BL26 BL27 BL28 BL36 BL37 BM15 BM16 BM17 BM36 BM37 BN15 BN16 BN17 BN36 BN37 BN38 BP15 BP16 BP17 BP37 BP38 BR15 BR16 BR17 BR37 BT15 BT16 BT17 BT37
CPU_VCCGTSENSE_P
AH38
CPU_VCCGTSENSE_N
AH37
OUT OUT
CPU Power
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
8 OF 200
SHEET
8 OF 135
D
C
B
69 8
69 9
A
8
67
35 4
2
1
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D
C
B
A
A3 A4 A6
A9 A10 A12 A14 A16 A18 A20 A22 A24 A26 A34 A36 A37
AA12 AA29 AA30
AB6
AB33 AB34
AC1 AC2 AC3 AC4 AC5
AC6 AC12 AC37 AC38
AD6
AD7
AD8
AD9 AD10 AD11 AD12 AD29 AD30
AE6
AE33 AE34
AF1 AF2 AF3
AF4 AF12 AF13 AF14
AG6 AG7
AG8 AG10 AG11 AG13 AG29 AG30
AH6 AH12
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CFL-H-DDR4-IL-8+2
U0500
BGA
CFLH
SYM 8 OF 13
GROUND
CRITICAL OMIT_TABLE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AH33 AH34 AH35 AH36 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ13 AJ37 AJ38 AK4 AK29 AK30 AL4 AL7 AL8 AL9 AL10 AL12 AL14 AL33 AL34 AM1 AM2 AM3 AM4 AM5 AM12 AM37 AM38 AN5 AN6 AN12 AN29 AN30 AP8 AP9 AP10 AP11 AP12 AP33 AP34 AR1 AR2 AR3 AR4 AR5 AR13 AR14 AR29 AR30 AR31 AR32 AR33 AR34 AR35
AR36 AR37 AR38
AT6 AT29 AT30
AU6 AU7 AU8
AU9 AU10 AU11 AU12 AU33 AU34 AV37 AV38
AW1 AW2 AW3 AW4
AW5 AW12 AW29 AW30
AY12 AY14 AY33 AY34
B3 B9
B37 BA6 BA7 BA8 BA9
BA10 BA11 BA12 BA37 BA38
BB1 BB2 BB3 BB4 BB5 BB6
BB12 BB29 BB30
BC6
BC12 BC13 BC14 BC33 BC34
BD6 BD7 BD8 BD9
BD10 BD11 BD12 BD37 BD38
BE1 BE2 BE3 BE4 BE5 BE6
BE29 BE30
BF6
BF12 BF33 BF34
BG6
BG12 BG13 BG14
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
U0500
CFL-H-DDR4-IL-8+2
BGA
CFLH
SYM 9 OF 13
GROUND
CRITICAL
OMIT_TABLE
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BG37 BG38 BH1 BH2 BH3 BH4 BH5 BH6 BH7 BH8 BH9 BH10 BH11 BH12 BH14 BJ12 BJ14 BJ15 BJ18 BJ22 BJ25 BJ29 BJ30 BJ31 BJ32 BJ33 BJ34 BJ35 BJ36 BK6 BK13 BK14 BK15 BK18 BK22 BK25 BK29 BL6 BL13 BL14 BL18 BL19 BL20 BL21 BL22 BL29 BL33 BL35 BL38 BM2 BM3 BM5 BM6 BM7 BM8 BM9 BM11 BM12 BM13 BM14 BM18 BM21 BM22 BM23 BM24 BM25 BM26 BM27 BM28 BM29 BM33 BM35 BM38 BN2 BN19 C37 D3 D28 D30 D33 L33
A28
A30 BN4 BN7
BN12 BN14 BN18 BN20 BN21 BN24 BN29 BN30 BN31 BN34
BP7 BP12 BP14 BP18 BP21 BP24 BP25 BP26 BP29 BP33 BP34
BR7
BR9 BR12 BR14 BR18 BR21 BR24 BR25 BR26 BR29 BR34 BR36 BR38
BT3 BT4 BT5
BT8 BT12 BT14 BT18 BT21 BT24 BT26 BT29 BT32 BT35 BT36
C2 C5 C8
C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31
D6
D9 D10 D12 D14 D16 D18 D20 D22 D24 D26 D38
E4
E9 E34 E35 E38
F2
F3
F4
F5
F8
F9 F11 F13 F15 F17 F19
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CFL-H-DDR4-IL-8+2
U0500
BGA
CFLH
SYM 10 OF 13
GROUND
CRITICAL OMIT_TABLE
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
F21 F23 F25 F27 F29 F31 F36 G4 G5 G6 G8 G9 G10 G12 G14 G16 G18 G20 G22 G23 G24 G26 G28 H11 H12 H18 H22 H25 H32 H35 J4 J7 J10 J18 J22 J25 J32 J33 J36 K1 K2 K3 K4 K5 K7 K8 K9 K10 K11 K38 L29 L30 L34 M6 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N33 N34 P6 P12 P37 P38 R12 R29 R30 T1 T2 T3 T4 T5 T7 T8 T9 T10 T11 T12 T13 T14 T33 T34 U6 U37
CPU_VCCGTSENSE_N CPU_VCCIOSENSE_N
CPU_VCCSASENSE_N CPU_VCCSENSE_N
1
R0961
100
5% 1/20W MF 201
2
OUT
OUT OUT OUT
1
R0963
100
5% 1/20W MF 201
2
1
R0965
100
5% 1/20W MF 201
2
1
R0966
100
5% 1/20W MF 201
2
BOM_COST_GROUP=CPU & CHIPSET
69 8
78 8
69 8
69 8
D
C
B
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
CPU Ground
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
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SHEET
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1
D
PPVCC_S0_CPU
117 126
CPU VCORE Decoupling
Intel recommendation: 5x 220uF ESR 5m ohms ESL 1.9nH each,4x 47uF 0805 8x22uF 0603, 28x 10uF 0402, 3x 10uF 0402, 69x 1uF 0201 Board Edge: 2x 220uF, 4x 47uF rest on the back side Apple Implementation:
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
C1000
1
1UF
20% 4V
2
CERM-X6S 0201
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
1
C1023
1UF
20%
2
4V CERM-X6S 0201
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
C1001
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1024
1UF
20%
2
4V CERM-X6S 0201
C1002
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1025
1UF
20%
2
4V CERM-X6S 0201
C1003
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1026
1UF
20%
2
4V CERM-X6S 0201
C1004
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1027
1UF
20%
2
4V CERM-X6S 0201
C1005
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1028
1UF
20%
2
4V CERM-X6S 0201
C1006
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1029
1UF
20%
2
4V CERM-X6S 0201
C1007
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1030
1UF
20%
2
4V CERM-X6S 0201
Vcc CPU Core Decoupling from 20140905 BOM
C1008
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1031
1UF
20%
2
4V CERM-X6S 0201
C1009
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1032
1UF
20%
2
4V CERM-X6S 0201
C1010
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1033
1UF
20%
2
4V CERM-X6S 0201
C1011
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1034
1UF
20%
2
4V CERM-X6S 0201
C1012
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1035
1UF
20%
2
4V CERM-X6S 0201
C1013
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1036
1UF
20%
2
4V CERM-X6S 0201
C1014
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1037
1UF
20%
2
4V CERM-X6S 0201
C1015
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1038
1UF
20%
2
4V CERM-X6S 0201
C1016
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1039
1UF
20%
2
4V CERM-X6S 0201
C1017
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1040
1UF
20%
2
4V CERM-X6S 0201
C1018
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1041
1UF
20%
2
4V CERM-X6S 0201
C1019
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1042
1UF
20%
2
4V CERM-X6S 0201
C1020
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1043
1UF
20%
2
4V CERM-X6S 0201
C1021
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1044
1UF
20%
2
4V CERM-X6S 0201
C1022
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1045
1UF
20%
2
4V CERM-X6S 0201
D
C
1
C1046
1UF
20%
2
4V CERM-X6S 0201
1
C10A0
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1047
1UF
20%
2
4V CERM-X6S 0201
1
C10A3
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
1
C10A4
20UF
20%
2
2.5V X6S-CERM 0402-1
C10D1
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C1048
1UF
20% 4V CERM-X6S 0201
1
2
1
2
1
C1049
2
C10Z4
20UF
20%
2.5V X6S-CERM 0402-1
C10D2
20UF
20%
2.5V X6S-CERM 0402-1
1UF
20% 4V CERM-X6S 0201
1
C10A6
2
1
2
1
2
20UF
20%
2.5V X6S-CERM 0402-1
C10D3
20UF
20%
2.5V X6S-CERM 0402-1
C1050
1UF
20% 4V CERM-X6S 0201
C10A7
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C10D4
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1051
1UF
20%
2
4V CERM-X6S 0201
1
C1052
1UF
20%
2
4V CERM-X6S 0201
1
C1053
1UF
20%
2
4V CERM-X6S 0201
Place near inductors on bottom side.
1
C10A8
20UF
20%
2
2.5V X6S-CERM 0402-1
C10D5
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C10ZB
20UF
20%
2
2.5V X6S-CERM 0402-1
C10D6
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C10B0
20UF
20%
2
2.5V X6S-CERM 0402-1
C10E2
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
1
C1054
1UF
20%
2
4V CERM-X6S 0201
C10B1
20UF
20%
2.5V X6S-CERM 0402-1
C10E3
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C10B4
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
1
C1055
1UF
20%
2
4V CERM-X6S 0201
C10C0
1
2
C10N1
12PF
5% 25V NP0-C0G 0201
20UF
20%
2.5V X6S-CERM 0402-1
C10N2
1
2
1
C1056
1UF
20%
2
4V CERM-X6S 0201
12PF
5% 25V NP0-C0G 0201
C10C1
20UF
1
20%
2.5V X6S-CERM
2
0402-1
1
2
1
C1057
1UF
20%
2
4V CERM-X6S 0201
1
2
C10N3
12PF
5% 25V NP0-C0G 0201
C10C4
20UF
20%
2.5V X6S-CERM 0402-1
C10N4
1
12PF
5%
2
25V NP0-C0G 0201
1
C1058
1UF
20%
2
4V CERM-X6S 0201
1
C10C5
20UF
20%
2
2.5V X6S-CERM 0402-1
C10N5
1
12PF
5%
2
25V NP0-C0G 0201
1
C1059
2
1
C10C6
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
1
C1060
1UF
20% 4V CERM-X6S 0201
1
2
C10C7
20UF
20%
2.5V X6S-CERM 0402-1
1UF
20%
2
4V CERM-X6S 0201
Noise Floor caps
C10N6
12PF
5% 25V NP0-C0G 0201
C10N7
1
12PF
5%
2
25V NP0-C0G 0201
1
C1061
1UF
20%
2
4V CERM-X6S 0201
1
C1062
1UF
20%
2
4V CERM-X6S 0201
C
B
117 124 125
PP1V2_S3_CPUDDR
CRITICAL
1
C1069
220UF
20% 2V ELEC
2
SM
1
C10F0
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
Place on bottom side of U0500.
Place on bottom side of U0500.
Place on bottom side of U0500
Place on bottom side of U0500.
Place on bottom side of U0500
Place on bottom side of U0500
1
C10F1
2
CRITICAL
C1068
220UF
20% 2V ELEC SM
20UF
20%
2.5V X6S-CERM 0402-1
1
C10F2
20UF
20%
2
2.5V X6S-CERM 0402-1
CRITICAL
1
C1070
220UF
20% 2V
2
ELEC SM
1
C10F3
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C10F4
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C10F5
20UF
20%
2
2.5V X6S-CERM 0402-1
CRITICAL
1
C1072
220UF
20% 2V
2
ELEC SM
C10F6
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CRITICAL
1
C1073
220UF
20% 2V
2
ELEC SM
C10F7
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C10F8
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C10F9
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C10G0
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
B
C1080
1
20UF
20%
2
2.5V X6S-CERM 0402-1
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
1
C1090
20UF
20%
2
2.5V X6S-CERM 0402-1
C1081
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1091
20UF
20%
2
2.5V X6S-CERM 0402-1
C1082
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1092
20UF
20%
2
2.5V X6S-CERM 0402-1
C1083
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1093
20UF
20%
2
2.5V X6S-CERM 0402-1
C1084
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1094
20UF
20%
2
2.5V X6S-CERM 0402-1
C1085
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1095
20UF
20%
2
2.5V X6S-CERM 0402-1
CPU VDDQ Decoupling
Intel recommendation: 10x 10uF 0402, 4x 22uF 0602 Apple Implementation:
CRITICAL
1
C1096
220UF
20% 2V
2
ELEC SM
CPU VCCIO Decoupling
Intel recommendation: 3x 10uF 0402 (opposite CPU) Apple Implementation:
Place near U0500 on bottom side
A
5 8 117 124
PPVCCIO_S0_CPU
NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)
8
67
C1086
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C1087
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C1088
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C1089
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C108A
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C108B
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C108C
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
BOM_COST_GROUP=CPU & CHIPSET
35 4
C108D
20UF
20%
2.5V X6S-CERM 0402-1
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
CPU Decoupling 1
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
10 OF 200
SHEET
10 OF 135
1
A
Page 11
Vinafix.com
678
3 245
1
D
PPVCCGT_S0_CPU
117 124 126
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
1
2
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
1
2
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
Place on bottom side of U0500
C1100
1UF
20% 4V CERM-X6S 0201
C1124
1UF
20% 4V CERM-X6S 0201
C1101
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1125
1UF
20%
2
4V CERM-X6S 0201
CPU VGTSlice Decoupling
Vcc GT Slice Core Decoupling from 20140905 BOM
Intel recommendation: 7x 220uF, 6x 47uF 0805, 6x 22uF 0603, 35x 10uF 0402, 68 1uF 0201 Apple Implementation:
C1102
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1126
1UF
20%
2
4V CERM-X6S 0201
C1103
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1127
1UF
20%
2
4V CERM-X6S 0201
C1104
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1128
1UF
20%
2
4V CERM-X6S 0201
C1105
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1129
1UF
20%
2
4V CERM-X6S 0201
C1106
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1130
1UF
20%
2
4V CERM-X6S 0201
C1107
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1131
1UF
20%
2
4V CERM-X6S 0201
C1108
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1132
1UF
20%
2
4V CERM-X6S 0201
C1109
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1133
1UF
20%
2
4V CERM-X6S 0201
Board Edge: 4x220uF, 7x 47uF rest on back side
C1110
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1134
1UF
20%
2
4V CERM-X6S 0201
C1111
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1135
1UF
20%
2
4V CERM-X6S 0201
C1112
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1136
1UF
20%
2
4V CERM-X6S 0201
C1113
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1137
1UF
20%
2
4V CERM-X6S 0201
C1114
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1138
1UF
20%
2
4V CERM-X6S 0201
C1115
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1139
1UF
20%
2
4V CERM-X6S 0201
C1116
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1140
1UF
20%
2
4V CERM-X6S 0201
C1117
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1141
1UF
20%
2
4V CERM-X6S 0201
C1118
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1142
1UF
20%
2
4V CERM-X6S 0201
C1119
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1143
1UF
20%
2
4V CERM-X6S 0201
C1120
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1144
1UF
20%
2
4V CERM-X6S 0201
C1121
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1145
1UF
20%
2
4V CERM-X6S 0201
C1122
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1146
1UF
20%
2
4V CERM-X6S 0201
C1123
1
1UF
20% 4V
2
CERM-X6S 0201
1
C1147
1UF
20%
2
4V CERM-X6S 0201
D
C
1
C1148
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A0
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11F0
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1149
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A1
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11F1
1
20UF
20%
2
2.5V X6S-CERM 0402-1
NOSTUFF
C11A2
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
2
1
C1150
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A3
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11F2
20UF
20%
2.5V X6S-CERM 0402-1
1
C1151
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A4
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11F3
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1152
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A5
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11F4
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
2
NOSTUFF
C11A6
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11F5
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C1153
1UF
20% 4V CERM-X6S 0201
C11A7
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
2
1
C1154
2
NOSTUFF
C11F6
20UF
20%
2.5V X6S-CERM 0402-1
1UF
20% 4V CERM-X6S 0201
NOSTUFF
C11A8
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11F7
1
2
1
2
20UF
20%
2.5V X6S-CERM 0402-1
1
C1155
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11A9
20UF
20%
2.5V X6S-CERM 0402-1
NOSTUFF
C11B0
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11E0
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1156
1UF
20%
2
4V CERM-X6S 0201
1
2
C11B1
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11E1
20UF
20%
2.5V X6S-CERM 0402-1
1
C1157
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11B2
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11E2
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1158
1UF
20%
2
4V CERM-X6S 0201
C11B3
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11E3
1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C1159
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11B4
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11E4
1
2
1
2
20UF
20%
2.5V X6S-CERM 0402-1
1
C1160
2
NOSTUFF
C11B5
20UF
20%
2.5V X6S-CERM 0402-1
NOSTUFF
C11E5
1
2
1UF
20% 4V CERM-X6S 0201
NOSTUFF
C11B6
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
20UF
20%
2.5V X6S-CERM 0402-1
1
C1161
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11B7
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C1162
1UF
20%
2
4V CERM-X6S 0201
C11B8
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
2
C11B9
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C1163
1UF
20% 4V CERM-X6S 0201
C11C0
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C1164
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11C1
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C1165
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
C11C2
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C1166
2
NOSTUFF
C11C3
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1UF
20% 4V CERM-X6S 0201
1
2
1
2
C11C4
20UF
20%
2.5V X6S-CERM 0402-1
C1167
1UF
20% 4V CERM-X6S 0201
C11C5
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11C6
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11C7
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
C11D4
1
2
1
2
20UF
20%
2.5V X6S-CERM 0402-1
NOSTUFF
C11C8
20UF
20%
2.5V X6S-CERM 0402-1
NOSTUFF
C11D3
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C11C9
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
2
C11D0
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
NOSTUFF
C11D2
20UF
20%
2.5V X6S-CERM 0402-1
NOSTUFF
C11D1
1
20UF
20%
2
2.5V X6S-CERM 0402-1
C
CRITICAL
1
C1168
220UF
20% 2V
2
ELEC SM
CRITICAL
1
C1170
220UF
20% 2V
2
ELEC SM
CRITICAL
1
C1171
220UF
20% 2V
2
ELEC SM
CRITICAL
1
C1172
220UF
20% 2V
2
ELEC SM
B
PPVCCSA_S0_CPU
117
CRITICAL
1
C11K9
220UF
20% 2V
2
ELEC SM
Place on bottom side of U0500
Place on bottom side of U100.
Place on bottom side of U0500
1
C11H0
1UF
20%
2
4V CERM-X6S 0201
1
C11H1
1UF
20%
2
4V CERM-X6S 0201
1
C11H2
1UF
20%
2
4V CERM-X6S 0201
NOSTUFF
1
C11I0
20UF
20%
2
2.5V X6S-CERM 0402-1
NOSTUFF
1
C11I1
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C11I2
20UF
20%
2
2.5V X6S-CERM 0402-1
NOSTUFF
1
C11I3
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C11I4
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C11I5
20UF
20%
2
2.5V X6S-CERM 0402-1
1
C11I6
20UF
20%
2
2.5V X6S-CERM 0402-1
NOSTUFF
1
C11I7
20UF
20%
2
2.5V X6S-CERM 0402-1
PP1V05_S0SW
6 8 117
Place near U0500 on bottom side
Place near U0500 on bottom side
1
C11L1
1UF
20%
2
4V CERM-X6S 0201
1
C11L2
1UF
20%
2
4V CERM-X6S 0201
CPU VCCPLL and VCCST DecouplingCPU VCCSTG Decoupling
8 117
PP1V05_S3
1
C11M1
1UF
20%
2
4V CERM-X6S 0201
6 8 46
PP1V05_S3
117
1
C11M2
1UF
20%
2
4V CERM-X6S 0201
B
A
8
NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884)
Place near U0500 on bottom side
Place near U0500 on bottom side
SYNC_MASTER=ANDY SYNC_DATE=01/17/2019
PAGE TITLE
A
CPU Decoupling 2
DRAWING NUMBER
CPU VCCSA Decoupling
Apple Inc.
Intel recommendation: 2x 220uF, 1x 47uF 0805. 1x 22uF. 7x 10uF 0402, 3x 1uF 0201_
2x 220uF, 1x 22uF on board edge, everything else on back side
Apple Implementation:
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-04492
REVISION
2.15.0
BRANCH
PAGE
11 OF 200
SHEET
11 OF 135
1
SIZE
D
Page 12
Vinafix.com
678
3 245
1
OMIT_TABLE
D
121 46 18 12
121 46
121 46
121 46 35 20
121 114 46 34 18 12
80 77 12
135 121 77 39 12
IN
IN
IN
OUT
IN
IN
OUT
12
12
PM_SYSRST_L PM_PCH_SYS_PWROK PM_PCH_PWROK
PLT_RST_L PM_RSMRST_L
PM_PWRBTN_L SPIROM_USE_MLB PCH_BATLOW_L PM_SLP_S0_L
CNL-PCH-H-USFF-QNYP
SYSTEM POWER MANAGEMENT
(IPU)
AL17
AK16
SYS_RESET* SYS_PWROK PCH_PWROK
H23
GPP_B13/PLTRST*
U25
RSMRST*
J24
GPD3/PWRBTN*
K22 K20
GPD1/ACPRESENT
L22
GPD0/BATLOW*
L24
GPP_B12/SLP_S0*
U23
U1200
961822
BGA
SYM 4 OF 11
GPP_A14/SUS_STAT*/ESPI_RESET*
(IPU-RSMRST#)
DRAM_RESET*
(OD)
(IPD-DeepSx)
DSW_PWROK
GPD10/SLP_S5*
GPD5/SLP_S4* GPD4/SLP_S3*
WAKE*
SLP_SUS*
K25 H25 K23
P23
H22 J21
J25
PCH_DRAM_RESET_L PM_RSMRST_L PCIE_WAKE_L
ESPI_RESET_L
PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L
TP_PCH_SLP_SUS_L
12
OUT
OUT
OUT
OUT
OUT
26
121 114 46 34 18 12
121 120 39
121 12
121 12
135 121 107 27 14 12
120 12
PCH_STRP_GPD7
12
SPIROM_USE_MLB
12
PCIE_WAKE_L
12
PCH_BATLOW_L
12
PCH_ESPI_ALERT0_L PCH_GPP_A0_PU
12
PP3V3_S5
16 17 80
13 15 16 19 20 52 80
PP1V8_S5 PP1V8_S5
16 80
PP3V3_S5
16 17 80
R1204 R1205
R1206 R1208
R1209 R1210
100K 100K
100K
10K
100K 100K
1 2
1 2
1 2 1 2
1 2 1 2
1/20W5% MF 201
NOSTUFF
5% MF1/20W 201
5%
5% 201
1/20W MF
1/20W5% MF 201
201MF1/20W
2011/20W5% MF
D
C
120 77
IN
PMU_CLK32K_PCH
PP3V0_G3H_RTC
1
R1201
1M
5% 1/20W MF 201
2
PCH_INTRUDER_L
R1220
1 2
16 17 80
12
100K
1/20W
201
MF 5%
1
R1221
127K
1% 1/20W MF 201
2
123 120 41
123 120 41
120 36
120 36
123 119
123 119
OUT OUT
OUT OUT
OUT OUT
PCH_CLK32K_RTCX1
20
121 77
OUT
12
IN
NC_PCH_CLK32K_RTCX2 PCH_INTRUDER_L
PCH_RTC_RESET_L
PCIE_CLK100M_SOC_N PCIE_CLK100M_SOC_P
PCH_PCIE_CLK100M_WLAN_N PCH_PCIE_CLK100M_WLAN_P
EG_PEG_CLK100M_N EG_PEG_CLK100M_P
G24 G22
H20 F25 F23
AR10 AN10
AP9
AM9
AR8 AN8
RTCX1 RTCX2
INTRUDER* SRTCRST* RTCRST*
CLKOUT_PCIE_N0 CLKOUT_PCIE_P0
CLKOUT_PCIE_N1 CLKOUT_PCIE_P1
CLKOUT_PCIE_N2 CLKOUT_PCIE_P2
GPP_A0/RCIN*/ESPI_ALERT1*
GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1
RTC
ESPI/LPC
GPP_A7/PIRQA*/ESPI_ALERT0*
GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME*/ESPI_CS0*
GPP_A6/SERIRQ/ESPI_CS1*
OMIT_TABLE
U1200
CNL-PCH-H-USFF-QNYP
961822
BGA
SYM 2 OF 11
GPD7
XTAL_IN
XTAL_OUT
CLKIN_XTAL
R24 N20 N21 M20 M22 M25 N25 N24
J20
AN3 AN1
AR4
PCH_GPP_A0_PU
ESPI_IO<0> ESPI_IO<1> ESPI_IO<2> ESPI_IO<3> ESPI_CS_L PCH_SOC_SYNC
PCH_ESPI_ALERT0_L
PCH_STRP_GPD7
PCH_CLK24M_XTALIN PCH_CLK24M_XTALOUT
PCH_CLKIN_XTAL
12
OUT
120 41 12
12
BI BI BI BI BI
120 12
120 39
120 39
120 39
120 39
120 39
38 12
121 46 18 12
NEED TO CHANGE PER INTEL SPEC
SOC_CLKREQ_L
DEBUG_CLKREQ_L
12
PM_SYSRST_L
R1211 R1213
R1214
47K
47K
3.0K
1 2
1 2
1 2
201
201
NOSTUFF
5% MF 2011/20W
C
CRITICAL
C1250
12
1
R1251
200K
1% 1/20W MF 201
2
R1250
1 2
1/20W
0201
5% MF
Y1250
24MHZ-10PPM-8PF-30OHM
13
2.5X2.0-SM
24
0
120
PCH_CLK24M_XTALOUT_R
CRITICAL
10PF
1 2
5% 50V C0G
0201
CRITICAL
C1251
10PF
1 2
5% 50V C0G
0201
Ce1=Ce2=2*(C_L - C_S - C_I) = 2*(8-0.7)=14.6pF C_L = Load Capacitance = 8pF C_S = Trace Capacitace + XTAL Pad Capacitance = 0.7pF C_I= PCH Pin Capacitance = 0
B
123 120
123 120
123 120 27
123 120 27
123 120 107
123 120 107
OUT OUT
OUT OUT
OUT OUT
PCIE_CLK100M_DEBUG_N PCIE_CLK100M_DEBUG_P
PCIE_CLK100M_TBT_X_N PCIE_CLK100M_TBT_X_P
PCIE_CLK100M_TBT_T_N PCIE_CLK100M_TBT_T_P
NC NC
NC NC
CLKOUT_PCIE_N3
AM6
CLKOUT_PCIE_P3
AK6
CLKOUT_PCIE_N4
AM8
CLKOUT_PCIE_P4
AK8
CLKOUT_PCIE_N5
AL7
CLKOUT_PCIE_P5
AJ7
CLKOUT_PCIE_N6
AK1
CLKOUT_PCIE_P6
AK3
CLKOUT_PCIE_N7
AJ5
CLKOUT_PCIE_P7
AK4
CLOCK SIGNALS
GPP_A9/CLKOUT_LPC0
CLKOUT_CPUBCLK_N CLKOUT_CPUBCLK_P
CLKOUT_CPUNSSC_N CLKOUT_CPUNSSC_P
XCLK_BIASREF
/ESPI_CLK
AP2
M23
AR7 AP7
AR6 AN6
PCH_XCLK_BIASREF
ESPI_CLK60M_PCH
CPU_CLK100M_BCLK_N CPU_CLK100M_BCLK_P
CPU_CLK24M_NSSC_CLK_N CPU_CLK24M_NSSC_CLK_P
OUT
12
PP1V8_S5
36 77 80
120 39
135 121 77 39 12
PM_SLP_S0_L
R1236
100K
1 2
NOSTUFF
5% 201MF1/20W
B
OUT OUT
OUT OUT
121 12
121 12
135 121 107 27 14 12
135 121 77 39 12
120 6
120 6
120 6
120 6
PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L PCH_SOC_SYNC
38 12
PCH_CLKIN_XTAL
12
PCH_XCLK_BIASREF
12
R1230 R1231 R1232 R1233 R1215
R1235 R1234
PLACE_NEAR=U1200.AP2:2.54mm
100K 100K 100K 100K 100K
10K
60.4
1 2 1 2 1 2 1 2
1 2
1 2 1 2
5% 1/20W MF
MF5% 1/20W
1/20W MF 2015%
5% 1/20W MF
MF1/20W5% 201
MF1/20W 2011%
201 2011/20W MF5% 201
201
A
PP3V3_S5
R1207
10K
1 2
29 80
201
PM_PWRBTN_L
5% MF1/20W
12 77 80
PCI EXPRESS
CLOCKS & CONTROL
CLKOUT_CPUPCIBCLK_N
CLKOUT_CPUPCIBCLK_P
GPP_B5/SRCCLKREQ0* GPP_B6/SRCCLKREQ1* GPP_B7/SRCCLKREQ2* GPP_B8/SRCCLKREQ3* GPP_B9/SRCCLKREQ4*
GPP_B10/SRCCLKREQ5*
GPP_H0/SRCCLKREQ6* GPP_H1/SRCCLKREQ7*
AP5 AM5
W22 AB22 U20 V20 W20 V21
D12 A10
NC NC
CPU_CLK100M_PCIBCLK_N CPU_CLK100M_PCIBCLK_P
SOC_CLKREQ_L PCH_WLAN_CLKREQ_L PCH_GPU_CLKREQ_L DEBUG_CLKREQ_L
TBT_X_CLKREQ_L TBT_T_CLKREQ_L
12
OUT OUT
BI BI BI
IN IN
120 6
120 6
120 41 12
120 19
120 19
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
120 27 19
120 107 19
PCH RTC/CLK/ESPI/PM
DRAWING NUMBER
SIZE
051-04492
Apple Inc.
REVISION
A
D
2.15.0
BRANCH
PAGE
12 OF 200
SHEET
12 OF 135
BOM_COST_GROUP=CPU & CHIPSET
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
67
35 4
2
1
Page 13
Vinafix.com
D
C
Intel Spec: 1k Pull-up for IO2 and IO3
PP1V8_S5
PPVCCSPI_PRIM_PCH
R1330 R1331 R1332
R1318 R1303
R1317
100K 100K 100K
100K
1 2
1 2
1 2
1 2
1K
1 2
1K
1 2
VCCSPI:3V3
VCCSPI:3V3
5% 1/20W
VCCSPI:3V3
NOSTUFF
5% 201MF1/20W
5% 1/20W 201MF
5% 2011/20W MF
1/20W
12 15 16 19 20 52 80
16
201MF5% 1/20W
MF 201
201MF5%
PCH_STRP_BSSB_SEL_GPIO
SPI_MOSI_R SPI_IO<2> SPI_IO<3>
PCH_STRP_NO_REBOOT
13
13
13
PCH_WLAN_DEV_WAKE
678
3 245
1
OMIT_TABLE
U1200
CNL-PCH-H-USFF-QNYP
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
18 13
18 13
OUT OUT
OUT OUT
OUT OUT
OUT OUT
IN IN
IN IN
IN IN
IN IN
DMI_S2N_N<0> DMI_S2N_P<0>
DMI_S2N_N<1> DMI_S2N_P<1>
DMI_S2N_N<2> DMI_S2N_P<2>
DMI_S2N_N<3> DMI_S2N_P<3>
DMI_N2S_N<0> DMI_N2S_P<0>
DMI_N2S_N<1> DMI_N2S_P<1>
DMI_N2S_N<2> DMI_N2S_P<2>
DMI_N2S_N<3> DMI_N2S_P<3>
H3 H1
J2 J1
K3 K1
L4 L2
C3
B2
C1
E1 E2
F1 F4
F3
DMI0_TXN DMI0_TXP
DMI1_TXN DMI1_TXP
DMI2_TXN DMI2_TXP
DMI3_TXN DMI3_TXP
DMI0_RXN DMI0_RXP
DMI1_RXN DMI1_RXP
DMI2_RXN DMI2_RXP
DMI3_RXN DMI3_RXP
DMI
CNL-PCH-H-USFF-QNYP
A24
AB1
AJ2 AJ4 AJ8
G2 G4 M1 M3
V1 V2
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
NC NC NC NC NC NC NC
36 13
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
NC NC NC NC NC NC NC NC
AJ10
AK10
AM10
AR24
961822
BGA
SYM 5 OF 11
(IPD)
CPU/MISC
GPP_B23/SML1ALERT*/PCHHOT*
CPUPWRGD
THRMTRIP*
GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 GPP_E3/CPU_GP0 GPP_E7/CPU_GP1
CPU_TRST*
PLTRST_CPU*
TRIGGER_IN
TRIGGER_OUT
PM_DOWN
OMIT_TABLE
U1200
961822
BGA
SYM 1 OF 11
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD
(IPD)
RSVD & TP PINS
AUDIO
GPP_D5/I2S2_SFRM/CNV_RF_RESET*
GPP_D6/I2S2_TXD/MODEM_CLKREQ
HDA_SDO/I2S0_TXD
HDA_RST*/I2S1_SCLK
HDACPU_SCLK
HDACPU_SDI
HDACPU_SDO
PECI
PRDY*
PREQ*
PM_SYNC
AC24 AD23 AD25
AD22 AC25 AD20 AJ13
AK13 AM13
L21 AJ21
AR16 AP12 AR12 V25
V24 B12 C13 U22
AR17 AM14 AJ16 AP14 AR13
AN13 AL12
AJ12
NC NC NC
PCH_PROCPWRGD PCH_PM_THRMTRIP_L_R PCH_PECI PCH_WLANBT_PERST_L
PCH_WLAN_DEV_WAKE XDP_PCH_OBSDATA_A2 XDP_PCH_OBSDATA_B2 PCH_STRP_BSSB_SEL_GPIO
XDP_CPU_TRST_L CPU_RESET_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L CPU_PCH_TRIGGER
PCH_CPU_TRIGGER_R CPU_PCH_PM_DOWN
PM_SYNC_R
PLACE_NEAR=U1200.AJ12:10mm
TP_HDA_SDI1 TP_HDA_SDO TP_HDA_RST PCH_DISPA_BCLK_R
PCH_DISPA_SDO_R
NC NC
TP-P5
TP-P5
TP-P5
PLACE_NEAR=U1200.AN13:5mm
1 2
R1319
1
TP
TP1306
1
TP
TP1307
1
TP
TP1308
R1320
1/20W MF 2015%
R1321
R1308 R1309 R1315
R1314
5% 201MF1/20W
1 2
1 2
PM_SYNC
33
33
33
MF 2015% 1/20W
0
1 2
OUT
36 13
OUT OUT
13
OUT
OUT
OUT
OUT
IN
1 2
1 2 1 2
37 36 20
WIFI controller wakes up by PCIE in-band signaling instead of PCH_WLAN_DEV_WAKE
18
18
BSS GPIO 0=BSSB CLK/DI on USB-SS
123 18 6
6
123 18 6
123 18 6
5
620
13
PCH_DISPA_BCLK PCH_DISPA_SDI PCH_DISPA_SDO
5%
1/20W
MF
1/20W5%
5%MF1/20W
33
1/20W 201MF5%
6
OUT
0201
201MF
201
CPU_PWRGD PCH_PMTHRMTRIP_L CPU_PECI
PCH_CPU_TRIGGER
NOSTUFF
1
R1326
150K
5% 1/20W MF 201
2
20
OUT
20
IN
20
OUT
OUT
IN
OUT
121 6
46
IN
BI
46 6
D
5
5
C
B
3117S0134
RES,MF,5%,1/20W,201,75K VCCSPI:1V8
R1330,R1331,R1332
TP1300 TP1301
123 18
123 18
123 18
123 18
123 18
123 18
TP TP
IN
IN
IN
OUT
IN
IN
1 1
TP_PCH_TP1_F22
TP-P5
TP_PCH_TP3_B24
TP-P5
PCH_ITP_PMODE XDP_PCH_TCK XDP_PCH_TDI XDP_PCH_TDO XDP_PCH_TMS XDP_PCH_JTAGX
(IPD)
(IPU)
(Undriven)
(IPU)
F22 B24
AN16 AP17 AR18
AM16
AL14
AN18
TP1
TP2
ITP_PMODE PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS
PCH_JTAGX
JTAG
B
OMIT_TABLE
A
18 13
18 13
13
CNL-PCH-H-USFF-QNYP
C23 E25 C25
D21 A20 E22 B21
SPI0_CLK SPI0_CS0* SPI0_CS1*
SPI0_MOSI SPI0_MISO SPI0_IO2 SPI0_IO3
(IPU 20K)
(IPU 20K)
(IPU 20K)
NC NC NC
BI
BI
BI
SPI_MOSI_R
NC
SPI_IO<2> SPI_IO<3>
U1200
961822
BGA
SYM 3 OF 11
SPI
GSPI
(IPD)
(IPD)
GPP_B18/GSPI0_MOSI
GPP_B22/GSPI1_MOSI
P20
P22
PCH_STRP_NO_REBOOT
TP_PCH_STRP_BOOT_SPI_L
13
No Rebort: 0=Disable; 1=Enable
BootBIOS Strap: 0=SPI; 1=LPC
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
8
PCH DMI/JTAG/SPI/HDA
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
13 OF 200
SHEET
13 OF 135
1
SIZE
D
Page 14
Vinafix.com
678
3 245
1
D
121 29
121 29
29
29
121
121
121
121
BI BI
BI BI
IN IN
OUT OUT
USB3_EXTA_D2R_N USB3_EXTA_D2R_P
USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P
USB3_TEST_D2R_N USB3_TEST_D2R_P
USB3_TEST_R2D_N USB3_TEST_R2D_P
AA4 AA2
AD3
AD1
W3 W1
AC2 AC1
USB31_1_RXN USB31_1_RXP
USB31_1_TXN USB31_1_TXP
USB31_2_RXN USB31_2_RXP
USB31_2_TXN USB31_2_TXP
OMIT_TABLE
CNL-PCH-H-USFF-QNYP
U1200
961822
BGA
SYM 7 OF 11
USB2N_1 USB2P_1
USB2N_2 USB2P_2
USB2N_3 USB2P_3
USB2N_4 USB2P_4
AG1 AG2
AF1 AF3
AH1 AH3
AF4 AE5
USB_UPC_PCH_TA_N USB_UPC_PCH_TA_P
USB_UPC_PCH_TB_N USB_UPC_PCH_TB_P
USB_UPC_PCH_XA_N USB_UPC_PCH_XA_P
USB_UPC_PCH_XB_N USB_UPC_PCH_XB_P
OMIT_TABLE
BI BI
BI BI
BI BI
BI BI
121 120 110
121 120 110
121 120 111
121 120 111
120 30
120 30
120 31
120 31
120 36
120 36
120 36
120 36
121
121
121
121
IN IN
OUT OUT
IN IN
OUT OUT
PCH_PCIE_WLAN_D2R_N PCH_PCIE_WLAN_D2R_P
PCH_PCIE_WLAN_R2D_C_N PCH_PCIE_WLAN_R2D_C_P
USB3_TEST2_D2R_N USB3_TEST2_D2R_P
USB3_TEST2_R2D_N USB3_TEST2_R2D_P
NC NC
PCIE1_RXN/USB31_7_RXN
W4
PCIE1_RXP/USB31_7_RXP
W6
PCIE1_TXN/USB31_7_TXN
U1
PCIE1_TXP/USB31_7_TXP
U3
PCIE2_RXN/USB31_8_RXN
U6
PCIE2_RXP/USB31_8_RXP
V5
PCIE2_TXN/USB31_8_TXN
R2
PCIE2_TXP/USB31_8_TXP
R1
PCIE3_RXN/USB31_9_RXN
P4
PCIE3_RXP/USB31_9_RXP
R5
CNL-PCH-H-USFF-QNYP
U1200
961822
BGA
SYM 8 OF 11
PCIE/SATA/USB3
PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP
PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP
PCIE19_RXN/SATA6_RXN
PCIE19_RXP/SATA6_RXP
F6 D6
B4 A4
G8 G7
B5 A5
F8 D8
PCIE_SOC_D2R_N<0> PCIE_SOC_D2R_P<0>
PCIE_SOC_R2D_C_N<0> PCIE_SOC_R2D_C_P<0>
PCIE_SOC_D2R_N<1> PCIE_SOC_D2R_P<1>
PCIE_SOC_R2D_C_N<1> PCIE_SOC_R2D_C_P<1>
PCIE_SOC_D2R_N<2> PCIE_SOC_D2R_P<2>
IN IN
OUT OUT
IN IN
OUT OUT
IN IN
120 41
120 41
120 47
120 47
120 41
120 41
120 47
120 47
120 41
120 41
D
C
USB3
USB2
18
18
18
18
18
18
18
18 14
OUT OUT OUT
OUT OUT OUT OUT OUT
XDP_PCH_OBSFN_C0 XDP_PCH_OBSDATA_A0 XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_D0 XDP_PCH_OBSDATA_D1 XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TDI XDP_JTAG_ISP_TDO
NC NC
NC NC
NC NC
PCIE3_TXN/USB31_9_TXN
P3
PCIE3_TXP/USB31_9_TXP
P1
PCIE4_RXN/USB31_10_RXN
P6
PCIE4_RXP/USB31_10_RXP
N5
PCIE4_TXN/USB31_10_TXN
N2
PCIE4_TXP/USB31_10_TXP
N1
GPP_E0/SATAXPCIE0/SATAGP0
D16
GPP_E1/SATAXPCIE1/SATAGP1
F16
GPP_E2/SATAXPCIE2/SATAGP2
G14
GPP_F0/SATAXPCIE3/SATAGP3
C20
GPP_F1/SATAXPCIE4/SATAGP4
A19
GPP_F2/SATAXPCIE5/SATAGP5
B19
GPP_F3/SATAXPCIE6/SATAGP6
A22
GPP_F4/SATAXPCIE7/SATAGP7
G18
PCIE19_TXN/SATA6_TXN PCIE19_TXP/SATA6_TXP
PCIE20_RXN/SATA7_RXN
PCIE20_RXP/SATA7_RXP
PCIE20_TXN/SATA7_TXN PCIE20_TXP/SATA7_TXP
GPP_E4/SATA_DEVSLP0 GPP_E5/SATA_DEVSLP1 GPP_E6/SATA_DEVSLP2
GPP_F5/SATA_DEVSLP3 GPP_F6/SATA_DEVSLP4 GPP_F7/SATA_DEVSLP5 GPP_F8/SATA_DEVSLP6 GPP_F9/SATA_DEVSLP7
C6 A6
G9 E9
B7 A7
E14 F13 D13
F20 G19 D20 E19 F18
PCIE_SOC_R2D_C_N<2> PCIE_SOC_R2D_C_P<2>
PCIE_SOC_D2R_N<3> PCIE_SOC_D2R_P<3>
PCIE_SOC_R2D_C_N<3> PCIE_SOC_R2D_C_P<3>
XDP_PCH_OBSDATA_A3 XDP_PCH_OBSDATA_B0 XDP_PCH_OBSDATA_B1
TBT_X_PCI_RESET_L TBT_T_PCI_RESET_L TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN TBT_T_CIO_PWR_EN
OUT OUT OUT
OUT OUT OUT OUT OUT
OUT OUT
IN IN
OUT OUT
18
18
18
120 47
120 47
120 41
120 41
120 47
120 47
33 27 20
113 107 20
33 31 30 27 14
33 31 30 27 14
113 111 110 107 14
C
B
GPP_E9/USB2_OC0* GPP_E10/USB2_OC1* GPP_E11/USB2_OC2* GPP_E12/USB2_OC3*
GPP_F15/USB2_OC4* GPP_F16/USB2_OC5*
USB2_COMP
USB2_ID
USB2_VBUSSENSE
E12 G10 D10 F10
B17 D17
AB6 AE4 AE2
XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L
NC NC
USB2_COMP USB2_ID USB2_VBUSSENSE
18 14
18 14
18 14
18 14
PLACE_NEAR=U1200.AB6:10.0mm
1
R1410
1K
5% 1/20W MF 201
2
1
R1411
1K
5% 1/20W MF 201
2
1
R1470
113
1% 1/20W MF 201
2
113 111 110 107 14
33 27 14
113 107 14
1
R1400
100
1% 1/20W MF 201
2
OUT OUT OUT
TBT_T_USB_PWR_EN TBT_X_PLUG_EVENT_L TBT_T_PLUG_EVENT_L
PCH_PCIE_RCOMPP PCH_PCIE_RCOMPN
NC
GPP_F10/SATA_SCLOCK
D18
GPP_F11/SATA_SLOAD
C18
GPP_F12/SATA_SDATAOUT1
G16
GPP_F13/SATA_SDATAOUT0
E17
PCIE_RCOMPP
L5
PCIE_RCOMPN
K4
GPP_E8/SATALED*
G13
XDP_PCH_OBSDATA_B3
OUT
18
B
A
PM_SLP_S3_L
PM_SLP_S3_L
R1491 R1492 R1493 R1494
R1446 R1445
R1447 R1460
R1461 R1420
R1421 R1448
R1449
100K 100K 100K 100K
100K 100K
10K 10K
10K 10K
10K
100K 100K
PP3V3_S5
1 2
1 2
1 2
1 2
1 2 1 2
1 2
1 2 1 2
1 2 1 2
1 2
1 2
16 80
1/20W MF5%
5% MF1/20W
5% 1/20W MF
1/20W 201MF5%
MF 2015% 1/20W
MF5% 2011/20W MF 2011/20W5%
5% MF 2011/20W
1/20W5% 201MF
135 121 107 27 14 12
135 121 107 27 14 12
201
MF5% 1/20W
201
201
201
TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN TBT_T_CIO_PWR_EN TBT_T_USB_PWR_EN
TBT_T_PLUG_EVENT_L TBT_X_PLUG_EVENT_L
201MF1/20W5%
XDP_JTAG_ISP_TDO XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
2015% MF1/20W
XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L
33 31 30 27 14
33 31 30 27 14
113 111 110 107 14
113 111 110 107 14
113 107 14
33 27 14
18 14
18 14
18 14
18 14
18 14
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
PCH PCI-E/USB
MF1/20W 2015%
JTAG_ISP_TDI
JTAG_ISP_TCK
123 107 27 18
123 107 27 18
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
14 OF 200
SHEET
14 OF 135
BOM_COST_GROUP=CPU & CHIPSET
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SIZE
D
8
67
35 4
2
1
Page 15
Vinafix.com
678
3 245
1
OMIT_TABLE
D
RAMCFG0:L
1
R1530
1K
5% 1/20W MF 201
2
RAMCFG1:L
1
R1531
1K
5% 1/20W MF 201
2
SPEED CONGIF4
2400MHZ
2667MHZ
1
2
R1532
1K
5% 1/20W MF
201
0
RAMCFG2:L
1
2
STORAGE
16GB
32GB
64GB
RAMCFG3:L
R1533
1K
5% 1/20W MF 201
CONGIF31CONGIF2
1
1
1
R1534
1K
5% 1/20W MF 201
2
RAMCFG4:L
VENDOR
1 1
10
0
SAMSUNG
MICRON
HYNIX
MLB_RAMCFG0 MLB_RAMCFG1
MLB_RAMCFG2 MLB_RAMCFG3
MLB_RAMCFG4
CONGIF1 CONGIF0
1
0
1
15
15
15
15
15
U1200
CNL-PCH-H-USFF-QNYP
1
0
95 15
95 15
19 15
OUT OUT
IN
EDP_IG_PANEL_PWR EDP_IG_BKLT_EN
BT_AUDIO_SYNC_LS3V3
NC
NC
NC
GPP_F14/PS_ON*
A18 A16
GPP_F19/EDP_VDDEN
C16
GPP_F20/EDP_BKLTEN
A14
GPP_F21/EDP_BKLTCTL
B14
GPP_F22/DDPF_CTRLCLK
A13
GPP_F23/DDPF_CTRLDATA
GPPF/
BACKLIGHT
J680 Display Port DDPF Disabled
GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I2/DDPD_HPD2_DISP_MISC2 GPP_I3/DDPF_HPD3_DISP_MISC3 GPP_I4/EDP_HPD/DISP_MISC4 GPP_I5/DDPB_CTRLCLK GPP_I6/DDPB_CTRLDATA GPP_I7/DDPC_CTRLCLK GPP_I8/DDPC_CTRLDATA GPP_I9/DDPD_CTRLCLK GPP_I10/DDPD_CTRLDATA GPP_I11/M2_SKT2_CFG0 GPP_I12/M2_SKT2_CFG1 GPP_I13/M2_SKT2_CFG2
GPPI/DISPLAY
PDG recommends to NC the HPD lines not being used
95 15
J680 Display Port DDPB/C/D Disabled
135 122 15
113 109 29 15
NC NC NC NC
IN
OUT
OUT
DP_INT_IG_HPD
USFF_MEM_OK
TBT_POC_RESET
NC NC NC NC NC NC
NC
AN23 AN25 AP24 AP22 AR22 AP19
AM19
AR20 AN20 AP21 AR21
AL24 AL25
AK25
961822
SYM 9 OF 11
GPPG
BGA
(IPD)
(IPD)
GPP_J0/CNV_PA_BLANKING
GPP_J1/CPU_C10_GATE*
GPP_J2 GPP_J3
GPP_J4/CNV_BRI_DT/UART0B_RTS*
GPP_J5/CNV_BRI_RSP/UART0B_RXD
GPP_J6/CNV_RGI_DT/UART0B_TXD
GPP_J7/CNV_RGI_RSP/UART0B_CTS*
GPP_J8/CNV_MFUART2_RXD
GPP_J9/CNV_MFUART2_TXD
GPP_J10
GPP_J11/A4WP_PRESENT
GPP_K20 GPP_K21
GPPJ_RCOMP_1P8
CNV_WR_CLKP CNV_WR_CLKN
CNV_WR_D0P
CNV_WR_D0N
AM18 AK18 AL19 AJ18 AJ22 AH23 AJ25 AH25 AK22 AK23 AM20 AK20
A8 C8
AJ17
AG24 AG25
AF23 AF25
SOC_SWD_MUX_SEL_PCH CPU_C10_GATE_L PCH_SWD_SOC_CLK PCH_SWD_SOC_IO PCH_STRP_XTAL_24MHZ MLB_RAMCFG2 PCH_STRP_CNV_L MLB_RAMCFG3 MLB_RAMCFG4 PCH_STRP_VCCPSPI_1V8 PCH_BT_ROM_BOOT_L NC_PCH_BT_DEV_WAKE
MLB_RAMCFG0 MLB_RAMCFG1
PCH_GPPJ_RCOMP_1P8
NC NC
NC NC
NO_TEST=1
121 15
OUT
135 79 78 76 15
GPP_J2:Unused GPP_J3:Unused
15
GPP_J4: 0=38.4MHz 1=24MHz XTAL
15
15
GPP_J6: 0=ENABLE 1=DISABLE
15
15
GPP_J9: 0=3.3V; 1=1.8V
15
36
15
15
15
D
C
PP1V8_S5
PP3V3_S5
PP3V3_S5
R1501 R1502
10K 10K
1 2 1 2
80
16 19 80
16 80
201MF5% 1/20W
5% 201
1/20W MF
JTAG_TBT_X_TMS JTAG_TBT_T_TMS
eSPI Flash Mode: 0=MAF; 1=SAF
19 15
15
PCH_STRP_SPIROM_SAF
15
PCH_STRP_GPP_H15
IN
WLAN_AUDIO_SYNC_LS3V3
GPP_H12/SML2ALERT*
A9
GPP_H15/SML3ALERT*
B9
GPP_H23/TIME_SYNC0
C10
(IPD)
/SMLINK
GPPH/I2C/INTEGRATED SENSOR
CNV_WR_D1P
CNV_WR_D1N
CNV_WT_CLKP
CNV_WT_CLKN
CNV_WT_D0P
CNV_WT_D0N
CNV_WT_D1P
CNV_WT_D1N
CNV_WT_RCOMP
AE22 AE24
AH22 AH20
AG21 AG20
AF22 AF20
AE21
NC NC
NC NC
NC NC
NC NC
NC
C
OMIT_TABLE
123 27 15
123 107 15
CNL-PCH-H-USFF-QNYP
U1200
961822
BGA
SYM 6 OF 11
B
PP1V8_S5
R1503 R1505
R1506 R1507
R1508 R1509
R1510 R1511
R1512 R1526 R1543 R1514 R1515
R1516 R1517
R1518
1K
47K 47K
47K 47K
47K 47K
1K
100K
20K
1K 100K 100K
100K
1K
1K
1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2
1 2
1 2
1 2 1 2
VCCSPI:1V8
1 2
VCCSPI:3V3
1 2
12 13 16 19 20 52 80
MF5% 1/20W
201
5% 1/20W
5% MF1/20W 5% 1/20W
5% 201MF1/20W 5%
1/20W5% 201MF
1/20W 2011%
1/20W MF 201
5%
5%
1/20W MF5%
5% 1/20W MF 201
MF 201
201MF1/20W5%
201
MF 201
MF 2011/20W
2011/20W5% MF
MF
1/20W5% MF
MF 2011/20W MF5% 2011/20W
201
201
PCH_STRP_ESPI PCH_UART_BT_D2R
PCH_UART_BT_R2D PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D
PCH_STRP_SPIROM_SAF PCH_STRP_GPP_H15
PCH_STRP_CNV_L PCH_STRP_XTAL_24MHZ PCH_SWD_SOC_CLK PCH_SWD_SOC_IO
CPU_C10_GATE_L
PCH_STRP_VCCPSPI_1V8
15
15
15
15
15
15
15
15
GPP_C0/SMBCLK
GPP_C1/SMBDATA
35 15
35 15
35 15
35 15
121 29 15
121 29 15
TP1501
135 79 78 76 15
39 20
39
TP-P5
123 27 15
123 107 15
TP
OUT IN
OUT OUT
SOC_PERST_L PCH_GCON_INT_L
1
TP_PCH_STRP_TOPBLK_SWP_L
PLACE_SIDE=BOTTOM
JTAG_TBT_X_TMS JTAG_TBT_T_TMS
NC
R22
P25
R21
AC20 AC21
AB20
GPP_A20/ISH_GP2 GPP_A21/ISH_GP3
GPP_B14/SPKR
GPP_D0/SPI1_CS*/SBK0/BK0 GPP_D1/SPI1_CLK/SBK1/BK1
GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
(IPD)
GPPA/
INTEGRATED SENSOR
GPPC/SMLINK/I2C/UART
(IPD)
(IPD)
GPP_C2/SMBALERT*
GPP_C5/SML0ALERT*
GPP_C8/UART0A_RXD
GPP_C9/UART0A_TXD
GPP_C10/UART0A_RTS*
GPP_C11/UART0A_CTS*
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
W23 W25 AA22
AB19
AA24 AA21 AA18 Y19
AB25 AB23
SMBUS_PCH_CLK SMBUS_PCH_DATA TP_PCH_STRP_TLSCONF
PCH_STRP_ESPI
PCH_UART_BT_D2R PCH_UART_BT_R2D PCH_UART_BT_RTS_L PCH_UART_BT_CTS_L
PCH_UART_DEBUG_D2R PCH_UART_DEBUG_R2D
OUT
BI
15
OUT OUT
OUT
52
IN
IN
IN
PROJ-SPECIFIC PULLUP
52
TLS: 0=Disbale; 1=Enable
GPP_C5: 0=LPC; 1=eSPI
35 15
35 15
35 15
35 15
121 29 15
121 29 15
B
A
R1537 R1536 R1522 R1523 R1524
R1542
R1527 R1528 R1529
100K
100K
100K
100K
100K
200
100K
100K
100K
1 2
1 2
1 2
1 2 1 2
1 2
1 2 1 2 1 2
1/20W MF5% 201
1/20W MF5% 201
1/20W MF 2015%
5% 1/20W MF 201
1% 1/20W 201MF
5% 1/20W MF 201
MF 2011/20W5%
USFF_MEM_OK
BT_AUDIO_SYNC_LS3V3 DP_INT_IG_HPD
TBT_POC_RESET WLAN_AUDIO_SYNC_LS3V3
201MF1/20W5%
PCH_GPPJ_RCOMP_1P8
15
EDP_IG_PANEL_PWR EDP_IG_BKLT_EN SOC_SWD_MUX_SEL_PCH
MF5% 2011/20W
135 122 15
19 15
95 15
113 109 29 15
19 15
95 15
95 15
121 15
GPPD/INTEGRATED SENSOR/UART/I2C GPPB
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
PCH GPIO/MISC/NCTF
SIZE
D
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
A
2.15.0
BRANCH
PAGE
15 OF 200
SHEET
15 OF 135
BOM_COST_GROUP=CPU & CHIPSET
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
67
35 4
2
1
Page 16
Vinafix.com
D
C
B
PP1V05_PRIM
17 80 117
12 17 80
PP3V3_S5
17
PP1V05_PRIM_PCH_VCCAPLL_F
117
PP1V05_PRIM
117
PP1V05_PRIM
PP1V05_PRIM
117
PP1V05_PRIM_PCH_VCCAXTAL_F
17
AB12 AB14 AB17
AB7
AB9 AD12 AD14
AD9 AE11
AF7
H7 H9
J15 K14 K17
K7
K9 M7 M9
P12 P14 P17
P7
P9
T12 T14 T17
T7
T9
V12 V14 V17
V9
Y12 Y14 Y17
Y7
Y9
AD17 AE15 AE18
M17
V7
AF6
AG8
AC5
AJ6
AG5
AD7
PRIMARY WELL
VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05 VCCPRIM_1P05
PRIMARY WELL HVCMOS
VCCPRIM_3P3 VCCPRIM_3P3 VCCPRIM_3P3 VCCPRIM_3P3 VCCPRIM_3P3
VCCAPLL_1P05 VCCAPLL_1P05
VCCDUSB_1P05
VCCA_BCLK_1P05
VCCA_SRC_1P05
VCCA_XTAL_1P05
OMIT_TABLE
U1200
CNL-PCH-H-USFF-QNYP
961822
BGA
SYM 10 OF 11
POWER
DEEP SX WELL
GPPH/GPPK PRIMARY WELL
AUDIO PLL
MOD PHY PRIMARY
VCCAMPHYPLL_1P05
LDO
GPPA PRIMARY WELL
GPPB/GPPC PRIMARY WELL
GPPD PRIMARY WELL
GPPE/GPPEF PRIMARY WELL
RTC WELL SUPPLY
RTC LOGIC PW/VRM
SPI
VCCDPHY_1P24 VCCDPHY_1P24 VCCDPHY_1P24 VCCDPHY_1P24
VCCDSW_3P3
VCCDSW_1P05
VCCPHVLDO_1P8 VCCPHVLDO_1P8
VCCPGPPA
VCCPGPPBC
VCCPGPPD
VCCPGPPEF VCCPGPPEF
VCCPGPPHK
DCPRTC
VCCRTC VCCRTC
VCCSPI
AF19 AG18 AH17 AH19
M19 N18
M6
AF12 AF14
P19
T19
V19
M12 M14
K12
H17
G20 H19
K19
678
3 245
1
OMIT_TABLE
U1200
PP1V24_S5_PCH_VCCDPHY
PP3V3_S5
PP1V05_S5_PCH_VCCDSW
PP1V_PRIM_PCH_VCCAMPHYPLL_F
PP1V8_PCH_VCCPHYLDO
PP1V8_S5
PP1V8_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PPDCPRTC_PCH
PP3V0_G3H_RTC
VOLTAGE=3.3V
0201
PPVCCSPI_PRIM_PCH
0201
12 17 80
Internal Supply
17
17
Internal LDO, leave this pin as NC
17
12 80
12 13 15 19 20 52 80
15 80
14 80
15 19 80
17
12 17 80
R1601
1 2
MF 5%1/20W
VCCSPI:3V3
R1602
1 2
MF 5%1/20W
VCCSPI:1V8
17
CNL-PCH-H-USFF-QNYP
R6
VSS
U13
VSS
A12
VSS
A1
VSS
A2
VSS
AJ24
AA20
AC22
AJ14 AJ19 AJ20
AR14 AR19
AL22
AM12 AM17 AM21
AP25
AR25
PP3V3_S5
80
0
PP1V8_S5
80
AP4
D5
G17
J11 L20
AL1
AG4 AH9
AJ1 AJ9
AL2
AL4 AL9
AM7
AP1
AR1 AR2 AR5 AR9
E24
G1
B1
B25
D7
D9 D14 D19
E4
E7
J5 J8
G5 G12 G21 G25
H4
H6 H12 H14
J4
J6 J13 J22 J18
N15
R4 R8
L1 L6
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
0
961822
BGA
SYM 11 OF 11
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L8 L11 L13 L15 L18 L25 M4 N4 N6 N8 N11 N13 N22 U4 U8 R11 R13 R15 R18 R20 R25 U15 U11 W13 W18 U18 V4 V6 V22 W8 W11 W15 A25 AA1 AA5 A17 A21 AA25 AB3 AA6 AA8 AA11 AA13 AA15 AC4 AC6 AB4 AC8 AE1 AE6 AE8 AE13 AC11 AC13 AC15 AC18 AD4 AD6 AE20 AE25 AF9 AF17 AG6 AG15 AG22 AH4 AH6 AH7 B22
D
C
B
A
PP1V8_S5
17 80
Share with GPIO J Group Power
PP1V05_PRIM
17 117
PP1V8_S0_PCH_VCCHDA_F
17
AG11 AG13 AH12 AH14
K6
AD19
VCCPRIM_1P8 VCCPRIM_1P8 VCCPRIM_1P8 VCCPRIM_1P8
VCCPRIM_MPHY_1P05
HD AUDIO POWER
VCCHDA
ANALOG PLL USB2/VRM
Current data from LPT EDS (doc #486708, Rev 1.0).
BOM_COST_GROUP=CPU & CHIPSET
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
PCH Power
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
16 OF 200
SHEET
16 OF 135
A
8
67
35 4
2
1
Page 17
Vinafix.com
678
3 245
1
D
PP1V05_PRIM
16 80 117
C1750
12 16 80
PP3V3_S5
16 80
PLACE_NEAR=U1200.K14:1MM
1
12PF
5%
25V
NP0-C0G
2
0201
PP1V8_S5
PLACE_NEAR=U1200.AB14:5MM
PLACE_NEAR=U1200.K14:1MM
C1715
1
0.1UF
10%
16V
2
X5R-CERM 0201
PLACE_NEAR=U1200.AE15:1MM
C1751
12PF
5%
25V
NP0-C0G
0201
PLACE_NEAR=U1200.AG13:2MM
C1716
1
0.1UF
10%
2
16V
X5R-CERM 0201
1
2
1
2
PLACE_NEAR=U1200.V9:3MM
PLACE_NEAR=U1200.AE15:1MM
PLACE_NEAR=U1200.AG13:2MM
C1752
12PF
5%
25V
NP0-C0G 0201
C1700
22UF
20%
X5R-CERM-1
6.3V
603
C1703
1
0.1UF
10%
16V
2
X5R-CERM 0201
1
C1705
1UF
20%
2
6.3V
X6S-CERM 0201
PLACE_NEAR=U1200.P9:1MM
1
2
C1701
1
1UF
10%
6.3V
2
CERM 402
PLACE_NEAR=U1200.AE15:1MM
C1702
1
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U1200.AH12:2MM
1
C1704
0.1UF
10%
2
16V
X5R-CERM 0201
17 16
PP1V05_S5_PCH_VCCDSW
PP3V0_G3H_RTC
12 16 80
PP1V05_PRIM
16 117
1
C1714
0.1UF
10%
16V
2
X5R-CERM 0201
PLACE_NEAR=U1200.N18:1MM PLACE_NEAR=U1200.N18:1MM
1
C1709
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U1200.G19:1MM PLACE_NEAR=U1200.H20:1MM
1
C1711
1UF
20%
6.3V
X6S-CERM
2
0201
PLACE_NEAR=U1200.K6:1MM PLACE_NEAR=U1200.K6:5MM PLACE_NEAR=U1200.K6:1MM
C1713
1
22UF
20%
6.3V
2
X5R-CERM-1 603
1
C1708
0.1UF
10%
16V
2
X5R-CERM 0201
1
C1710
0.1UF
10%
16V
X5R-CERM
2
0201
C1712
1
1UF
20%
2
6.3V
X6S-CERM 0201
VOLTAGE=1.05V
17 16
PP1V05_S5_PCH_VCCDSW
VOLTAGE=3.3V
PPDCPRTC_PCH
16
16
PP1V24_S5_PCH_VCCDPHY
PLACE_NEAR=U1200.N18:1MM
1
C1742
1UF
20%
6.3V
X6S-CERM
2
0201
PLACE_NEAR=U1200.H17:1MM
C1743
1
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U1200.AH19:3MM
NOSTUFF
C1740
1
4.7UF
20%
2
6.3V
X6S 0402
D
C
B
117
PP1V05_PRIM
80
PP1V8_S5
C1721
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
C1724
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
12 16 17 80
220-OHM-0.7A-0.28-OHM
PLACE_NEAR=U1200.AG8:3MM
1
2
L1703
1 2
0402-1
PLACE_NEAR=U1200.AG8:3MM
L1704
75OHM-25%-0.2A-1.3OHM
1 2
PLACE_NEAR=U1200.AD19:3MM
1
2
PLACE_NEAR=U1200.AD19:3MM
0402
PP3V3_S5
C1753
NP0-C0G
MAKE_BASE=TRUE
PP1V05_PRIM_PCH_VCCAPLL_F
PLACE_NEAR=U1200.AG8:1MM
1
C1722
3.0PF
+/-0.1PF
25V
2
NP0-C0G 0201
MAKE_BASE=TRUE
PP1V8_S0_PCH_VCCHDA_F
PLACE_NEAR=U1200.AD19:1MM
C1725
1
3.0PF
+/-0.1PF
2
25V
NP0-C0G 0201
PLACE_NEAR=U1200.AG8:1MM
PLACE_NEAR=U1200.M19:1MM PLACE_NEAR=U1200.M19:1MM PLACE_NEAR=U1200.M19:1MM
1
12PF
5%
2
25V
0201
1
C1720
4.7UF
20%
6.3V
X6S
2
0402
PLACE_NEAR=U1200.AD19:2MM
C1723
1
4.7UF
20%
2
6.3V
X6S 0402
C1707
0.1UF
C1706
1
0.1UF
20%
2
10V
CERM 402
20%
10V
CERM
402
1
2
PP1V05_PRIM_PCH_VCCAPLL_F
PP1V8_S0_PCH_VCCHDA_F
16
16
117
PP1V05_PRIM
PP1V05_PRIM
117
12 16 17 80
PP3V3_S5
C1755
12PF
5%
25V
NP0-C0G
0201
C1756
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
1
PLACE_NEAR=U1200.AD7:5MM
2
1
2
PLACE_NEAR=U1200.M6:3MM
PLACE_NEAR=U1200.AD7:4MM
PLACE_NEAR=U1200.M6:3MM
PLACE_NEAR=U1200.M19:2MM
1
C1741
1UF
20%
6.3V
X6S-CERM
2
0201
OMIT_TABLE
L1701
2.2UH-20%-0.19A-0.221OHM
1 2
0603
1
C1726
47UF
2
PLACE_NEAR=U1200.AD7:3MM
OMIT_TABLE
L1702
2.2UH-20%-0.19A-0.221OHM
1 2
0603
1
C1729
47UF
2
16
MAKE_BASE=TRUE
VOLTAGE=1.05V
PP1V05_PRIM_PCH_VCCAXTAL_F
1
C1727
0.1UF
10%
20%
6.3V
POLY-TANT 0805
MAKE_BASE=TRUE
2
16V
X5R-CERM 0201
PLACE_NEAR=U1200.AD7:3MM PLACE_NEAR=U1200.AD7:3MM
VOLTAGE=1V
PP1V_PRIM_PCH_VCCAMPHYPLL_F
1
C1730
0.1UF
20%
6.3V
POLY-TANT 0805
PLACE_NEAR=U1200.M6:3MM
PLACE_NEAR=U1200.M6:3MM
10%
16V
2
X5R-CERM 0201
PP1V8_PCH_VCCPHYLDO
PP1V05_PRIM_PCH_VCCAXTAL_F
1
C1728
1UF
20%
6.3V
2
X6S-CERM 0201
PP1V_PRIM_PCH_VCCAMPHYPLL_F
1
C1731
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U1200.M6:3MM
NOSTUFF
1
C1744
1UF
20%
6.3V
X6S-CERM
2
0201
C
16
B
16
A
Current data from LPT EDS (doc #486708, Rev 1.0).
8
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
2 L1701,L1702113S0022 RES,MF,1A MAX,0OHM,5%,0603
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
PCH Decoupling
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
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SHEET
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Page 18
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D
C
6
IN
6
IN
6
IN
6
IN
121 114 46 34 12
121 80
123 18 6
123 13
Extra BPM Testpoints
XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3>
IN
OUT
13
OUT
OUT
PM_RSMRST_L
PM_PWRBTN_L
SPI_MOSI_R SPI_MOSI_R_CONN
IN
XDP_CPU_TCK
XDP_PCH_JTAGX
1
TP
TP1800
TP-P6
1
TP
TP1801
TP-P6
1
TP
TP1802
TP-P6
1
TP
TP1803
TP-P6
R1800
PLACE_NEAR=U1200.H25:2.54MM
R1802
PLACE_NEAR=U1200.K22:5MM
R1803
PLACE_NEAR=U1200.D21:10MM
R1835
PLACE_NEAR=J1800.58:28MM
80
PP3V3_S5
PLACE_NEAR=J1800.48:2.54MM
XDP:YES
1K
1 2
5% 1/20W 201MF
XDP:YES
10
1.5K
1 2
XDP:YES
1 2
XDP:YES
1 2
XDP:YES
R1804
1K
5%
1/20W
MF
201
1/20W 201MF5%
1
2
MF5% 1/20W 201
678
3 245
1
Primary / Merged (CPU/PCH) Micro2-XDP
117
PP1V05_PRIM
PP1V05_S0SW
NOTE: This is not the standard XDP pinout.
XDP_CONN
DF40RC-60DP-0.4V
5%
1/20W
MF
201
1
XDP:YES
NO_XNET_CONNECTION
2
NC NC
NC
NC NC
XDP_PIN_1
OBSFN_A0 OBSFN_A1
OBSDATA_A0 OBSDATA_A1
OBSDATA_A2 OBSDATA_A3
OBSFN_B0 OBSFN_B1
OBSDATA_B0 OBSDATA_B1
OBSDATA_B2 OBSDATA_B3
HOOK0 HOOK1
VCC_OBS_AB
HOOK2 HOOK3
TCK1 TCK0 TMS
XDP:YES
C1800
0.1UF
6.3V
CERM-X5R
0201
PLACE_NEAR=J1800.42:28MM
PLACE_NEAR=J1800.44:28MM
SCL
10%
1
2
PULL CFG<3> LOW
WHEN XDP PRESENT
PLACE_NEAR=J1800.2:5MM
R1801
1.5K
XDP_PRESENT_CPU
123 13 6
123 13 6
BI
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
XDP_CPU_PREQ_L XDP_CPU_PRDY_L
CPU_CFG<0> CPU_CFG<1>
CPU_CFG<2> CPU_CFG<3>
CPU_CFG<4> CPU_CFG<5>
CPU_CFG<6> CPU_CFG<7>
XDP_PM_RSMRST_L XDP_CPU_PWRBTN_L
123 18 13
0201MF5%01/20W
OUT
XDP_PCH_TCK
XDP:YES
C1804
0.1UF
10%
6.3V
CERM-X5R
0201
1
2
J1800
M-ST-SM1
6162
12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 4142 4344 4546 4748 4950 5152 5354 5556 5758 5960
6364
518S0847
Use with 921-0133 Adapter Flex to support chipset debug.
OBSFN_C0 OBSFN_C1
OBSDATA_C0 OBSDATA_C1
OBSDATA_C2 OBSDATA_C3
OBSFN_D0 OBSFN_D1
OBSDATA_D0 OBSDATA_D1
OBSDATA_D2 OBSDATA_D3
ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7
TDOSDA TRSTn TDI
XDP_PRESENT#
XDP:YES
C1801
1
0.1UF
10%
2
6.3V CERM-X5R 0201
PLACE_NEAR=J1800.43:28MM
PLACE_NEAR=J1800.47:28MM
CPU_CFG<17> CPU_CFG<16>
CPU_CFG<8> CPU_CFG<9>
CPU_CFG<10> CPU_CFG<11>
CPU_CFG<19> CPU_CFG<18>
CPU_CFG<12> CPU_CFG<13>
CPU_CFG<14> CPU_CFG<15>
NC_ITPXDP_CLK100MP NC_ITPXDP_CLK100MN
PCH_ITP_PMODE XDP_DBRESET_L
XDP:YES
C1806
1
0.1UF
10%
2
6.3V CERM-X5R 0201
123 18 13
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
IN IN
120 20
120 20
1
R1830
1K
5% 1/20W MF 201
2
PLACE_NEAR=U0500.E8:2.54MM
ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.
R1821
PLACE_NEAR=J1800.51:2.54MM
R1822
PLACE_NEAR=J1800.53:2.54MM
R1823
PLACE_NEAR=J1800.55:2.54MM
R1824
PLACE_NEAR=J1800.57:2.54MM
123 18 13
123 18 13
123 18 13
IN
0
0
0
0
123 18 6
123
123 13
1 2
XDP:YES
1 2
XDP:YES
1 2
XDP:YES
1 2
XDP:YES
XDP_PCH_TDO
XDP_PCH_TDI
XDP_PCH_TMS
XDP_CPU_TDO
XDP_CPU_TCK
18 6
XDP_PCH_TCK
XDP_PCH_TRST_L
18
PROPER WAY TO TERMINATE?
5%
1/20W
1/20W5%
PLACE_NEAR=U1200.AM16:28MM
PLACE_NEAR=U1200.AR18:28MM
PLACE_NEAR=U1200.AL14:28MM
PLACE_NEAR=U0500.BT28:28MM
PLACE_NEAR=U0500.BR28:28MM
PLACE_NEAR=U1200.AP17:28MM
XDP:YES
1 2
XDP_CPU_TDO
MF 02011/20W
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS
MF
R1890 R1891 R1892 R1810
R1813 R1897
R1898
R1806
0
5%
1/20W
MF
0201
0201MF5%
0201MF1/20W5%
0201
PM_SYSRST_L
117
XDP:YES
100
51
100
51
51
51
OUT
OUT
OUT
2 1
XDP:YES
2 1
XDP:YES
2 1
XDP:YES
2 1
XDP:YES
2 1
NOSTUFF
2 1
NOSTUFF
IN
123 18 6
123 13 6
123 6
123 6
5%511/20W 201MF
5%
1/20W
5% 1/20W MF
1
BI
121 46 12
MF1/20W
MF1/20W
MF1/20W
MF
MF1/20W5% 201
2015%
201
2015%
2015%
201
D
C
B
14
14
13
14
14
14
13
14
14
14
14
PCH XDP Signals
These signals do not connect to the Primary (Merged) XDP connector in this architecture. The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation. They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.
PCH/XDP Signals
XDP_PCH_OBSDATA_A0
BI
XDP_PCH_OBSDATA_A1
BI
XDP_PCH_OBSDATA_A2
BI
XDP_PCH_OBSDATA_A3
BI
XDP_PCH_OBSDATA_B0
BI
XDP_PCH_OBSDATA_B1
BI
XDP_PCH_OBSDATA_B2
BI
XDP_PCH_OBSDATA_B3
BI
XDP_PCH_OBSFN_C0
BI
XDP_PCH_OBSDATA_D0
BI
XDP_PCH_OBSDATA_D1
BI
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
1
TP
TP1810
TP-P5
1
TP
TP1811
TP-P5
1
TP
TP1812
TP-P5
1
TP
TP1813
TP-P5
1
TP
TP1814
TP-P5
1
TP
TP1815
TP-P5
1
TP
TP1816
TP-P5
1
TP
TP1817
TP-P5
1
TP
TP1818
TP-P5
1
TP
TP1824
TP-P5
1
TP
TP1825
TP-P5
18 14
18 14
18 14
18 14
18 14
18 14
18 14
Non-XDP Signals
XDP_JTAG_ISP_TDO
BI
XDP_JTAG_ISP_TCK
BI
XDP_JTAG_ISP_TDI
BI
XDP_USB_EXTA_OC_L
BI
XDP_USB_EXTB_OC_L
BI
XDP_USB_EXTC_OC_L
BI
XDP_USB_EXTD_OC_L
BI
123 107 27 14
123 107 27 14
OUT
OUT
JTAG_ISP_TDI
JTAG_ISP_TCK
JTAG_ISP_TDO
R1840 R1841 R1842
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
0
1 2
0
1 2
0
1 2
1/20W 5% 0201 MF
1/20W 5% 0201 MF
1
TP
TP1819
TP-P5
1
TP
TP1826
TP-P5
1
TP
TP1827
TP-P5
1
TP
TP1820
TP-P5
1
TP
TP1821
TP-P5
1
TP
TP1822
TP-P5
1
TP
TP1823
TP-P5
XDP_JTAG_ISP_TDI
XDP_JTAG_ISP_TCK
MF02015%1/20W
XDP_JTAG_ISP_TDO
18 80
PP1V8_S5
XDP_PCH_TDO XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS
PP1V8_S5
XDP:YES
1
R1850
100K
5% 1/20W MF 201
2
18 80
1
C1830
XDP:YES
74AUP1G07GF
2 1 5
6
VCC
U1830
SOT891
(OD)
GND
3
2
YA
SPI_IO2_STRAP_L
4
NCNC
NCNC
XDP:YES
0.1UF
10% 10V X5R-CERM 0201
PLACE_NEAR=U1830.4:7.54MM
1.5K
NO_XNET_CONNECTION
PLACE_NEAR=U1830.4:2.54MM
49.9
NO_XNET_CONNECTION
R1831
1 2
XDP:YES
R1832
1 2
MF
5%
NOSTUFF
SPI_IO<2>
1/20W
201MF
(STRAP TO PCH)
1% 1/20W
201
XDP_PRESENT_L
NEED TO CONNECT TO VCCST, *STG POWER LOGIC
IN
IN
OUTIN
18 14
18 14
18 14 123 107 27
IN
18
OUT OUT
OUT
OUT
123 18 13
123 18 13
123 18 13
13
B
39
A
Unused GPIOs have TPs.
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.
110
111
30 29
31 29
UPC_TA_FAULT_L
IN
UPC_TB_FAULT_L
IN
UPC_XA_FAULT_L
IN
UPC_XB_FAULT_L
IN
R1843 R1844 R1845 R1846
0
1
0
1
0
1 2
0
1 2
2
2
XDP_USB_EXTC_OC_L
5%MF02011/20W
XDP_USB_EXTD_OC_L
5%MF02011/20W
XDP_USB_EXTA_OC_L
MF02011/20W 5%
XDP_USB_EXTB_OC_L
5%MF1/20W 0201
OUT
OUT
OUT
OUT
18 14
18 14
18 14
DESIGN: X502/MLB LAST CHANGE: Mon Jun 15 22:04:28 2015
18 14
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
CPU/PCH Merged XDP
SIZE
D
BOM_COST_GROUP=DEBUG
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
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67
35 4
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PCIE CLKREQS
678
3 245
1
D
PP1V8_S5
PP3V3_S5
R1940
R1941
R1942
R1944
100K
100K
47K
47K
1 2
1 2
1 2
1 2
TBT_X_CLKREQ_L
TBT_T_CLKREQ_L
5% 201MF1/20W
120 12
120 12
PCH_WLAN_CLKREQ_L
PCH_GPU_CLKREQ_L
12 13 15 16 20 52 80
15 16 19 80
2015% 1/20W MF
201MF1/20W5%
2011/20W MF5%
5%
19 118 124
PP1V8_G3S_WLANBT
BYPASS=U1901::5MM
120 27 12
120 107 12
R1943
1K
1/20W MF 2015%
1 2
PCH_WLANBT_CLKREQ_R_L
37 36
36
BT_AUDIO_SYNC
IN
R1945
GPU_CLKREQ_L_R
GPU_CLKREQ_L_R
MAKE_BASE=TRUE
19
MF 2011/20W
1K
1 2
C1902
0.1UF
10% 16V
X5R-CERM
0201
1
2
NC
1
VCCA VCCB
U1901
SLSV1T34AMU-COMBO
2 4
5
UDFN
CRITICAL
NC
GND
PP3V3_S5
6
3
BYPASS=U1901::5MM
10% 16V
0201
1
2
C1903
0.1UF
X5R-CERM
BA
BT_AUDIO_SYNC_LS3V3
15 16 19 80
OUT
D
15
C
19 118 124
PP1V8_G3S_WLANBT
BYPASS=U1900::5MM
WLAN_AUDIO_SYNC
C1900
0.1UF
10%
X5R-CERM
0201
1
2
NC
PP3V3_S5
1
VCCA VCCB
U1900
SLSV1T34AMU-COMBO
2 4
5
UDFN
CRITICAL
NC
GND
6
BA
3
1
C1901
0.1UF
10% 16V
X5R-CERM
0201
BYPASS=U1900::5MM
216V
WLAN_AUDIO_SYNC_LS3V3
15 16 19 80
OUTIN
15 38 37 36
C
B
PP1V8_G3S
118
PLACE_NEAR=U1950.1:2mm
19
116 95
IN
EG_VR4_PGOOD
PP3V3_S0_GPU
1
C1950
0.1UF
10%
6.3V
2 6.3V
CERM-X5R 0201
8
1
VCCVL
U1950
NLSX4402
2 3
5
IO/VL1 IO/VL2
EN
UDFN-COMBO
GND
4
IO/VCC1 IO/VCC2
7 6
1
C1951
0.1UF
10%
2
CERM-X5R 0201
GPU_CLKREQ_LGPU_CLKREQ_L_R
NCNC
PLACE_NEAR=U1950.8:2mm
1
R1952
47K
5% 1/20W MF
2
201
117
97
BI
B
A
8
A
SYNC_DATE=01/17/2019SYNC_MASTER=ARMIN
PAGE TITLE
Chipset Support 1
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
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19 OF 200
SHEET
19 OF 135
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Page 20
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678
3 245
1
NC ALIASES 3
D
12 13 15 16 19 52 80
121 46 35 12
PP1V8_S5
IN
PLACE_NEAR=U2072.1:5MM
C2072
0.1UF
10% 16V
X5R-CERM
0201
NC_PCH_CLK32K_RTCX2
12
MAKE_BASE=TRUE
NC_PCH_CLK32K_RTCX2
SIGNAL ALIASES
PCH_DISPA_BCLK
13
PCH_DISPA_SDI
13
Platform Reset Connections
PP3V3_S5
1
2
2 4
1
VCCA VCCB
U2072
SLSV1T34AMU-COMBO
UDFN
6
95
BA
C2073
0.1UF
10% 16V
X5R-CERM
0201
PLT3V3_RST_LPLT_RST_L
PLACE_NEAR=U2072.6:5MM
1
2
80
PCH_DISPA_SDO
13
18 120
NC_ITPXDP_CLK100MN
18 120
NC_ITPXDP_CLK100MP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCH_DISPA_BCLK PCH_DISPA_SDI PCH_DISPA_SDO
TRUE
TRUE
NC_ITPXDP_CLK100MN NC_ITPXDP_CLK100MP
5
5
5
D
C
R2060
100K
5%
1/20W
MF
201
1
2
NC
5%
1/20W
MF
201
1
100K
2
100K
100K
100K
R2000
12
5% 1/20W MF
R2001
12
5% 2011/20W MF
12
R2002
5% 2011/20W MF
R2005
12
5% 1/20W
MF 201
TBT_X_PCI_RESET_L
201
TBT_T_PCI_RESET_L
PCH_WLANBT_PERST_L
SOC_PERST_L
OUT
OUT
OUT
OUT
33 27 14
113 107 14
37 36 13
39 15
5
NC
GND
3
R2061
100K
C
B
B
A
8
A
SYNC_MASTER=ANDY
PAGE TITLE
SYNC_DATE=02/19/2019
Chipset Support 2
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
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IV ALL RIGHTS RESERVED
2
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678
3 245
1
D
DDR4 VDDQ = 1.2V
----------------­ MIMINUM Step Size = 0.50% * VDDQ = 6.0mV per step
TYPICAL Step Size = 0.65% * VDDQ = 7.8mV per step MAXIMUM Step Size = 0.80% * VDDQ = 9.6mV per step
KBL PLATFORM GUIDE Page.102 FOR DDR4 X8 MEMORY DOWN
-------------------------------------------------­ DDR0_VREF_DQ = Not Used DDR1_VREF_DQ = Reference For Channel B
DDR_VREF_CA = Reference For Channel A
D
CPU-Based Margining
VRef Dividers
C
B
PP1V2_S3
117
C
1
R2241
1.8K
1% 1/20W MF
R2243
7
IN
7
IN
CPU_DIMMB_VREFDQ
1
2
CPU_DIMM_VREFCA
1
2
2.7
1 2
5%
1/20W
MF
201
PLACE_NEAR=R2241.2:1mm
C2240
0.022UF
10%
6.3V X5R-CERM 0201
MEM_VREFDQ_B_RC
R2263
2.7
1 2
5%
1/20W
MF
201
PLACE_NEAR=R2261.2:1mm
C2260
0.022UF
10%
6.3V X5R-CERM 0201
MEM_VREFCA_A_RC
R2242
1.8K
1/20W
R2240
24.9
1 2
1%
1/20W
MF
201
R2262
1.8K
1/20W
R2260
24.9
1 2
1%
1/20W
MF
201
1% MF
201
1% MF
201
1
2
1
2
201
2
PP0V6_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000
1
R2261
1.8K
1% 1/20W MF 201
2
PP0V6_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000
117
117
B
A
8
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
DDR4 VREF Margining
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
BOM_COST_GROUP=DRAM
67
35 4
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
22 OF 200
SHEET
21 OF 135
1
SIZE
D
Page 22
Vinafix.com
678
3 245
1
D
C2307
0.47UF
CERM-X5R-1
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>
7
MEM_A_A<16>
22 23 26 120
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
20%
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
FBGA
VDD
VDDQ
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
VDD
VDD
VDD
VDD
OMIT_TABLE
U2300
16GB-64X8X2-2400
MT40A2G8-NRE
22 23 26 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
C2
MEM_A_DQ<0>
B7
MEM_A_DQ<1>
D3
MEM_A_DQ<2>
D7
MEM_A_DQ<3>
D2
MEM_A_DQ<4>
D8
MEM_A_DQ<5>
E3
MEM_A_DQ<6>
E7
MEM_A_DQ<7>
C3
MEM_A_DQS_P<0>
B3
MEM_A_DQS_N<0>
A7
PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
128 120
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120
120 26 23 22 7
22 7
128 120
22 7
26 23 22 7
120
128 120
22 7
128 120
22 7
128 120
22 7
128 120
22 7
128 120
22 7
128 120
128 120
22 23 26 117
26 23 22 7
C2317
0.47UF
20%
CERM-X5R-1
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
201
4V
1
2
NC
PP1V2_S3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
K2
BA0
K8
BA1
J2
BG0
J8
BG1
PAR
N3 H3
ACT*
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2310
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
22 23 26 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
C2
MEM_A_DQ<8>
B7
MEM_A_DQ<9>
D3
MEM_A_DQ<10>
D7
MEM_A_DQ<11>
D2
MEM_A_DQ<12>
D8 E3
MEM_A_DQ<14>
E7
MEM_A_DQ<15>
C3
MEM_A_DQS_P<1>
B3
MEM_A_DQS_N<1>
A7
PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
128 120
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23
120 26 23 22 7
22 23 26 117
120 26 23 22 7
120 7
120 26 23 22 7
22 7
26 23 22 7
120 22 7
128 120
26 23 22 7
120
26 23 22 7
120 22 7 128 120
22 7
128 120
22 7
128 120
128 120
128 120
22 7
26 23 22 7
26 23 22
120
PP1V2_S3
20%
4V
201
1
2
NC
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8
N7
K2
K8
J2 J8
N3
H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
16GB-64X8X2-2400
OMIT_TABLE
U2320
MT40A2G8-NRE
FBGA
C2327
0.47UF
CERM-X5R-1
MEM_A_A<0> MEM_A_DQ<16> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_DQ<19> MEM_A_A<4> MEM_A_A<5>MEM_A_DQ<13> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
22 23 26 117
VDD
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VDDQ
VDDQ
NF/TDQS_C
E8
VDDQ
VDDQ
DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
DQ0 DQ1 DQ2 DQ3
C2 B7
MEM_A_DQ<17>
D3
MEM_A_DQ<18>
D7 D2
MEM_A_DQ<20>
D8
MEM_A_DQ<21>
E3
MEM_A_DQ<22>
E7
MEM_A_DQ<23>
C3
MEM_A_DQS_P<2>
B3
MEM_A_DQS_N<2>
A7
PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
26 23 22 7
120 26 23
120 26 23
26 23 22 7
26 23 22 7
120 26 23
26 23 22 7
120 26 23
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22
120 26 23 22 7
22 23 26 117
120 26 23 22 7
120
120 26 23 22 7
120
22 7
128 120
22 7
128 120
120
120
22 7
128 120
120
22 7
128 120
128 120
128 120
7
120 7
26 23 22
120 7
26 23 22 7
26 23 22
C2337
0.47UF
20%
CERM-X5R-1
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2330
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
22 23 26 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
C2
MEM_A_DQ<24>
B7
MEM_A_DQ<25>
D3
MEM_A_DQ<26>
D7
MEM_A_DQ<27>
D2
MEM_A_DQ<28>
D8
MEM_A_DQ<29>
E3
MEM_A_DQ<30>
E7
MEM_A_DQ<31>
C3
MEM_A_DQS_P<3>
B3
MEM_A_DQS_N<3>
A7
PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
120 128
26 22 23 117
120 23 7 22 26
D
128 120
128 120
128 120
128 120
128 120
128 120
128 120
120 128
120 128
C
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1> MEM_A_ODT<1>
26 24 22
MEM_RESET_L
23 25
MEM_A_CLK_P<0>
7
MEM_A_CLK_N<0>
22 23 26 120
G3 G7
F3
G2 G8
F2
L1
F7 F8
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS
C8
E1
VSS
E9
VSS
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
VSSQ
A2
VSSQ
A8
VSSQ
D1
VREFCA
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VSSQ
ZQ
B1
PP2V5_S3
M9
J1
PP0V6_S3_MEM_VREFCA_A
G9
MEM_A_TEN MEM_A_TENMEM_A_TENMEM_A_TEN
B9
MEM_A_ZQ<0>
R2300
240
1%
1/20W
MF
201
2
1
C2308
0.047UF
10%
6.3V X5R 201
22 23 117
120 26 23 22
120 26 23 22 7
120 26 23 22 7
26 23 22 7
26 23 22 7
1
25 24 23 22
2
26 23 22 7
26 23 22 7
7
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1>
120
MEM_A_ODT<1>
120
MEM_RESET_L
26
MEM_A_CLK_P<0>
120
MEM_A_CLK_N<0>
120
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
VSS C8
VSS E1
VSS E9
VSS G1
VSS H9
VSS K1
VSS K9
VSS N1
VSSQ
VSSQ
A2
A8
VSSQ
VSSQ
D1
D9
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ A9
ZQ
B1
PP2V5_S3
M9
J1
PP0V6_S3_MEM_VREFCA_A
G9
B9
MEM_A_ZQ<1> MEM_A_ZQ<2>
R2310
1/20W
240
1% MF
201
2
1
C2318
0.047UF
10%
6.3V X5R 201
22 23 117
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
1
26 23 22 7
2
26 25 24 23 22
120 26 23 22 7
120 26 23 22 7
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1> MEM_A_ODT<1>
120
MEM_RESET_L
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
G3 G7
F3
G2 G8
F2
L1
F7 F8
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS
C8
E1
VSS
E9
VSS
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
VSSQ
A2
VSSQ
A8
VSSQ
D1
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VREFCA
ZQ
VSSQ
ZQ
B1 M9
J1
G9
B9
PP2V5_S3
0.047UF
MEM_A_ZQ<3>
R2330
240
1%
1/20W
MF
201
C2338
10%
6.3V X5R 201
2
1
1
2
B1
PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFCA_A
J1
10%
6.3V X5R 201
1
2
G9
B9
R2320
240
1%
1/20W
MF
201
C2328
0.047UF
2
1
22 23 117
120 26 23 22 7
120 26 23 22 7
23 22 7
120 26
26 23 22 7
26 23 22 7
25 24 23 22
26 23 22 7
26 23 22 7
120
120
26
120
120
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1> MEM_A_ODT<1>
MEM_RESET_L
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
VSS C8
VSS E1
VSS E9
VSS G1
VSS H9
VSS
VSS
K1
K9N1A2
VSS
VSSQ
VSSQ
A8
VSSQ
D1
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VREFCA
VSSQ
117 22 23
C
117
23 22
B
PP2V5_S3
C2350
1.0UF
20%
6.3V X5R
0201-1
PP1V2_S3
C2300
2.2UF
20%
6.3V
X5R-CERM
0201
22 23 117
1
2
1
C2351
1.0UF
0201-1
C2301
2.2UF
2
X5R-CERM
20%
6.3V X5R
20%
6.3V
0201
1
2
C2352
1.0UF
22 23 26 117
1
C2302
2.2UF
2
X5R-CERM
20%
6.3V X5R
0201-1
20%
6.3V
0201
1
2
1
C2353
1.0UF
0201-1
C2303
2.2UF
2
X5R-CERM
20%
6.3V X5R
20%
6.3V
0201
1
2
1
C2354
1.0UF
0201-1
C2310
2.2UF
2
X5R-CERM
20%
6.3V X5R
20%
6.3V
0201
1
2
1
C2355
1.0UF
6.3V
0201-1
C2311
2.2UF
2
6.3V
X5R-CERM
0201
Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)
20% X5R
1
2
C2356
1.0UF
20%
6.3V X5R
0201-1
1
2
C2357
1.0UF
0201-1
20%
6.3V X5R
1
2
C2358
1.0UF
0201-1
20%
6.3V X5R
1
2
C2359
1.0UF
0201-1
20%
6.3V X5R
1
2
C2360
1.0UF
0201-1
20%
6.3V X5R
1
2
C2361
1.0UF
0201-1
20%
6.3V X5R
1
2
C2362
VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)
20%
1
C2312
2.2UF
2
X5R-CERM
20%
6.3V 0201
1
C2313
2.2UF
2
X5R-CERM
20%
6.3V 0201
1
2
1
C2304
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2305
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2306
0.1UF
10%
2
6.3V CERM-X5R 0201
1.0UF
20%
6.3V X5R
0201-1
1
C2370
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2363
1.0UF
0201-1
1
C2309
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V X5R
1
2
C2364
1.0UF
0201-1
1
C2314
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V X5R
1
2
C2365
1.0UF
0201-1
1
C2315
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V X5R
1
2
1
C2316
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2371
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2319
0.1UF
10%
2
6.3V CERM-X5R 0201
B
A
PP1V2_S3
20%
6.3V 0201
1
2
C2320
2.2UF
X5R-CERM
PP1V2_S3
C2321
2.2UF
20%
6.3V
X5R-CERM
0201
1
C2380
0.1UF
10%
2
6.3V CERM-X5R 0201
22 23 26 117
1
2
C2322
22 23 26 117
1
2
1
2.2UF
20%
2
6.3V
X5R-CERM
0201
C2381
0.1UF
10%
6.3V CERM-X5R 0201
C2323
2.2UF
20%
6.3V
X5R-CERM
0201
1
C2382
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V 0201
1
C2331
2.2UF
2
X5R-CERM
1
C2384
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2330
2.2UF
2
X5R-CERM
1
C2383
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V 0201
1
C2332
2.2UF
2
X5R-CERM
1
C2385
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V 0201
1
C2333
2.2UF
2
X5R-CERM
1
C2386
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V 0201
1
2
1
C2324
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2325
0.1UF
10%
2
6.3V CERM-X5R 0201
5x 0.1uF per chip
1
C2387
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2388
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2326
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2389
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2390
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2372
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2391
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2329
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2392
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2334
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2393
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
2
1
C2394
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2335
0.1UF
10%
6.3V CERM-X5R 0201
1
C2395
2
1
2
0.1UF
10%
6.3V CERM-X5R 0201
C2336
0.1UF
10%
6.3V CERM-X5R 0201
1
C2396
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2397
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2373
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2398
0.1UF
10%
6.3V CERM-X5R 0201
1
C2339
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2399
0.1UF
10%
2
6.3V CERM-X5R 0201
BOM_COST_GROUP=DRAM
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
DDR4 SDRAM Channel A 1
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
23 OF 200
SHEET
22 OF 135
A
8
67
35 4
2
1
Page 23
Vinafix.com
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3 245
1
D
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
22 7 26 23
22 7
C
26 23
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 24 22 23 25
26 23 22 7
22 7
120 26 23
C2407
0.47UF
CERM-X5R-1
MEM_A_A<0>
120
MEM_A_A<1>
120
MEM_A_A<2>
120
MEM_A_A<3>
120
MEM_A_A<4>
120
MEM_A_A<5>
120
MEM_A_A<6>
120
MEM_A_A<7>
120
MEM_A_A<8>
120
MEM_A_A<9>
120
MEM_A_A<10>
120
MEM_A_A<11>
120
MEM_A_A<12>
120
MEM_A_A<13>
120
MEM_A_A<14>
120
MEM_A_A<15>
120
MEM_A_A<16>
120
MEM_A_BA<0>
120
MEM_A_BA<1>
120
MEM_A_BG<0>
120
MEM_A_BG<1>
120
120
MEM_A_PAR MEM_A_ACT_L
120
MEM_A_CKE<0>
120
MEM_A_CS_L<0>
120
MEM_A_ODT<0>
120
MEM_A_CKE<1>
120
MEM_A_CS_L<1>
120
MEM_A_ODT<1>
120
MEM_RESET_L
MEM_A_CLK_P<0>
120
MEM_A_CLK_N<0>
20%
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
G3 G7
F3
G2 G8
F2
L1
F7 F8
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS C8
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2400
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
VSS
VSS
VSS
K1
K9
VSS N1
VSS E1
VSS E9
VSS G1
H9
22 23 26 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A2
A8
D1
D9
A9
ZQ
C2
MEM_A_DQ<32>
B7
MEM_A_DQ<33>
D3
MEM_A_DQ<34>
D7
MEM_A_DQ<35>
D2
MEM_A_DQ<36>
D8
MEM_A_DQ<37>
E3
MEM_A_DQ<38>
E7
MEM_A_DQ<39>
C3
MEM_A_DQS_P<4>
B3
MEM_A_DQS_N<4>
A7 A3
NC
L9
MEM_A_ALERT_L
B1
PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_A
J1
G9
MEM_A_TEN
MEM_A_ZQ<4>
B9
R2400
240
1/20W
201
1% MF
2
1
C2408
0.047UF
10%
6.3V X5R 201
26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
22 23 26 117
120 26 23 22 7
120
26 23 22 7
7
120 26 23 22 7
22 23 117
120 26 23 22
120 26 23 22 7
120 26 23 22 7
26 23 22 7
26 23 22 7
1
25 24 23 22
2
26 23 22 7
26 23 22 7
128 120
22 7
120 26 23
128 120
22 7
120 26 23
128 120
22 7
120 26 23
120
22 7
128 120
120 26 23
22 7
128 120
120 26 23
22 7
128 120
120 26 23
22 7
128 120
120 26 23
128 120
22 7
128 120
120 26 23
120
26 23 22
7
23 22
117
120
120
26
120
120
C2417
0.47UF
CERM-X5R-1
20%
4V
201
1
2
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
NC
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1> MEM_A_ODT<1>
MEM_RESET_L
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
PP1V2_S3
C7F1F9H1J9M1N9A1B2B8C1C9E2
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
BA0
K2
BA1
K8
BG0
J2
BG1
J8
PAR
N3
ACT*
H3
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
C8
VDD
VDD
VDD
VDD
16GB-64X8X2-2400
OMIT_TABLE
VSS
E9
VSS
G1
VSS
VSS
E1
VDD
VDD
VDD
U2410
MT40A2G8-NRE
FBGA
VSS
VSS
VSS
K1
K9
H9
VDD
VSS
N1
22 23 26 117
E8
VDDQ
VDDQ
VSSQ
A8
VDDQ
VDDQ
NF/TDQS_C
VSSQ
VSSQ
A9
D1
D9
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
VPP0 VPP1
VREFCA
RFU/TEN
VSSQ
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VSSQ
A2
ZQ
PP1V2_S3
C2427
0.47UF
CERM-X5R-1
C2
MEM_A_DQ<40>
B7
MEM_A_DQ<41>
D3
MEM_A_DQ<42>
D7
MEM_A_DQ<43>
D2
MEM_A_DQ<44>
D8
MEM_A_DQ<45>
E3
MEM_A_DQ<46>
E7
MEM_A_DQ<47>
C3
MEM_A_DQS_P<5>
B3
MEM_A_DQS_N<5>
A7
PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
B1 M9
PP0V6_S3_MEM_VREFCA_A
J1
10%
6.3V X5R 201
1
2
G9
MEM_A_TEN MEM_A_TEN MEM_A_TEN
B9
MEM_A_ZQ<5>
R2410
240
1/20W
201
C2418
0.047UF
2
1% MF
1
128 120
22 7
120 26 23
128 120
22 7
120 26 23
22 7
128 120
120 26 23
128 120
22 7
120 26 23
128 120
22 7
120 26 23
128 120
22 7
120 26 23
128 120
22 7
120 26 23
128 120
22 7
120 26 23
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
128 120
128 120
120 26 23 22
120 26 23 22 7
22 23 26 117
120 26 23 22 7
120
26 23 22 7
7
120 26 23 22 7
22 23 117
120 26 23 22
120 26 23 22 7
120 26 23 22 7
120 26 23 22
26 23 22 7
26 23 22 7
25 24 23 22
26 23 22 7
26 23 22 7
7
120 7
26 23 22
120
26 23 22
7
7
117 23 22
120
120
26
120
120
MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR MEM_A_ACT_L
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1> MEM_A_ODT<1>
MEM_RESET_L
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
20%
4V
201
NC
1
2
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
BA0
K2
BA1
K8
BG0
J2
BG1
J8
PAR
N3
ACT*
H3
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
16GB-64X8X2-2400
OMIT_TABLE
VSS
VSS
VSS
E1
E9
C8
U2420
MT40A2G8-NRE
VSS
VSS
VSS
K1
H9
G1
FBGA
VSS K9
22 23 26 117
VDD
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VSSQ
VSS
A2
N1
VDDQ
VSSQ
VSSQ
A8
D1
VDDQ
NF/TDQS_C
VSSQ D9
E8
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
ZQ
VSSQ A9
C2
MEM_A_DQ<48>MEM_A_A<0>
B7
MEM_A_DQ<49>
D3
MEM_A_DQ<50>
D7
MEM_A_DQ<51>
D2
MEM_A_DQ<52>
D8
MEM_A_DQ<53>
E3
MEM_A_DQ<54>
E7
MEM_A_DQ<55>
C3
MEM_A_DQS_P<6>
B3
MEM_A_DQS_N<6>
A7
PP1V2_S3PP1V2_S3
A3
NC
L9
MEM_A_ALERT_L
B1
PP2V5_S3PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_A
J1
G9
C2428
0.047UF
B9
MEM_A_ZQ<6>
240
1%
1/20W
MF
201
2
1
R2420
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
10%
6.3V X5R 201
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
120 26 23 22 7
23 22 7
120 26
23 22 7
120 26
26 23 22 7
23 22 7
120 26
23 22 7
120 26
26 23 22 7
1
23 22 7
2
25 24 23 22
26 23 22 7
26 23 22 7
MEM_A_A<0>
120
MEM_A_A<1>
120
MEM_A_A<2>
120
MEM_A_A<3>
120
MEM_A_A<4>
120
MEM_A_A<5>
120
MEM_A_A<6>
120
MEM_A_A<7>
120
MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15> MEM_A_A<16>
128 120
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0> MEM_A_BG<1>
MEM_A_PAR
120
MEM_A_ACT_L
MEM_A_CKE<0> MEM_A_CS_L<0> MEM_A_ODT<0>
MEM_A_CKE<1> MEM_A_CS_L<1>
120
MEM_A_ODT<1>
120 26
MEM_RESET_L
26
MEM_A_CLK_P<0>
120
MEM_A_CLK_N<0>
120
C2437
0.47UF
20%
CERM-X5R-1
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
G3 G7
F3
G2 G8
F2
L1
F7 F8
C7F1F9H1J9M1N9
VDD
VDD
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
OMIT_TABLE
VSS
VSS
VSS
E1
E9
C8
22 23 26 117
A1B2B8C1C9E2E8
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
U2430
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
NF/DM*/DBI*/TDQS_T
VSSQ
VSSQ
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
A2
A8
VSSQ
D1
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/TDQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ
VSSQ
A9
D9
ZQ
MEM_A_DQ<56>
C2
MEM_A_DQ<57>
B7
MEM_A_DQ<58>
D3
MEM_A_DQ<59>
D7
MEM_A_DQ<60>
D2
MEM_A_DQ<61>
D8
MEM_A_DQ<62>
E3
MEM_A_DQ<63>
E7
MEM_A_DQS_P<7>
C3
MEM_A_DQS_N<7>
B3
PP1V2_S3
A7 A3
NC
MEM_A_ALERT_L
L9
B1
PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_A
J1
G9
MEM_A_ZQ<7>
B9
R2430
240
1%
1/20W
MF
201
C2438
0.047UF
2
1
10%
6.3V X5R 201
D
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
22 23 26 117
120 23 7 22 26
C
22 23 117
1
2
B
PP2V5_S3
C2450
1.0UF
20%
6.3V X5R
0201-1
PP1V2_S3
C2400
2.2UF
20%
6.3V
X5R-CERM
0201
22 23 117
1
2
1
2
C2451
1.0UF
0201-1
C2401
2.2UF
X5R-CERM
20%
6.3V X5R
20%
6.3V 0201
1
2
C2452
1.0UF
22 23 26 117
1
2
C2402
20%
6.3V X5R
0201-1
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
2
C2453
1.0UF
0201-1
C2403
2.2UF
X5R-CERM
20%
6.3V X5R
20%
6.3V 0201
1
2
1
2
C2454
1.0UF
0201-1
C2410
2.2UF
X5R-CERM
20%
6.3V X5R
20%
6.3V 0201
1
2
1
2
C2455
1.0UF
6.3V
0201-1
C2411
2.2UF
X5R-CERM
Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)
20% X5R
1
2
C2456
1.0UF
0201-1
20%
6.3V X5R
1
2
C2457
1.0UF
0201-1
20%
6.3V X5R
1
2
C2458
1.0UF
0201-1
20%
6.3V X5R
1
2
C2459
1.0UF
0201-1
20%
6.3V X5R
1
2
C2460
1.0UF
0201-1
20%
6.3V X5R
1
2
C2461
VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)
1
C2406
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
C2404
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2413
2.2UF
X5R-CERM
1
2
C2412
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
1
C2405
0.1UF
10%
6.3V
2
CERM-X5R 0201
1.0UF
20%
6.3V X5R
0201-1
C2470
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2462
1.0UF
0201-1
1
C2414
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
1
2
C2463
1.0UF
0201-1
1
C2409
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
1
2
C2464
1.0UF
C2416
1
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
6.3V X5R
0201-1
1
2
C2465
1.0UF
1
C2415
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
0201-1
1
B
2
1
C2419
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2471
1
0.1UF
10%
2
6.3V CERM-X5R 0201
A
PP1V2_S3
C2420
2.2UF
20%
6.3V
X5R-CERM
0201
PP1V2_S3
22 23 26 117
1
2
1
C2490
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2473
0.1UF
10%
6.3V CERM-X5R 0201
1
C2424
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2487
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
22 23 26 117
1
2
C2422
2.2UF
X5R-CERM
C2481
0.1UF
10%
6.3V CERM-X5R 0201
1
2
C2421
2.2UF
X5R-CERM
1
C2480
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2423
2.2UF
X5R-CERM
1
C2482
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2430
2.2UF
X5R-CERM
1
C2483
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2431
2.2UF
X5R-CERM
1
C2484
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2432
2.2UF
X5R-CERM
1
C2485
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2433
2.2UF
X5R-CERM
1
C2486
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
5x 0.1uF per chip
1
C2425
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2488
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2426
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2489
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2472
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2491
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2429
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2492
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2493
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2434
0.1UF
10%
6.3V CERM-X5R 0201
1
2
C2494
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2435
0.1UF
10%
6.3V CERM-X5R 0201
C2495
1
2
1
2
0.1UF
10%
6.3V CERM-X5R 0201
C2436
0.1UF
10%
6.3V CERM-X5R 0201
C2496
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2439
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2497
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2498
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2499
0.1UF
10%
6.3V
2
CERM-X5R 0201
BOM_COST_GROUP=DRAM
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
DDR4 SDRAM Channel A 2
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
24 OF 200
SHEET
23 OF 135
A
8
67
35 4
2
1
Page 24
Vinafix.com
678
3 245
1
D
120 25
MEM_B_A<0>
7 24 26
MEM_B_A<1>
7 24 25
MEM_B_A<2>
26 120
MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>
25
MEM_B_A<16>
7 24 26 120
120 25
MEM_B_BA<0>
7 24 26
MEM_B_BA<1> MEM_B_BG<0>
25
MEM_B_BG<1>
7 24 26 120
MEM_B_PAR MEM_B_ACT_L
C2507
0.47UF
20%
CERM-X5R-1
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
FBGA
VDD
VDDQ
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
VDD
VDD
VDD
VDD
U2500
16GB-64X8X2-2400
MT40A2G8-NRE
OMIT_TABLE
24 25 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
C2
MEM_B_DQ<0>
B7
MEM_B_DQ<1>
D3
MEM_B_DQ<2>
D7
MEM_B_DQ<3>
D2
MEM_B_DQ<4>
D8
MEM_B_DQ<5>
E3
MEM_B_DQ<6>
E7
MEM_B_DQ<7>
C3
MEM_B_DQS_P<0>
B3
MEM_B_DQS_N<0>
A7
PP1V2_S3
A3
NC
L9
MEM_B_ALERT_L
128 120
24 7
120 26 25
128 120
24 7
120 26 25
26 25 24 7
128 120
24 7
120 26 25
128 120
24 7
120 26 25
24 7
128 120
120 26 25
128 120
24 7
120 26 25
26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
128 120
128 120
120 26 25 24
120 26 25 24 7
24 25 117
120 26 25 24
120 26 25 24 7
120
120 26 25 24 7
26 25 24 7
26 25 24
C2517
0.47UF
CERM-X5R-1
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2>
120
MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7>
120
MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
7
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0>
7
MEM_B_BG<1>
120 7
MEM_B_ACT_L
20%
4V
201
1
2
NC
PP1V2_S3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
BA0
K2
BA1
K8
BG0
J2
BG1
J8
N3
PAR ACT*
H3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2510
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
24 25 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
PP1V2_S3
20%
4V
201
1
2
NC
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
16GB-64X8X2-2400
OMIT_TABLE
U2520
MT40A2G8-NRE
FBGA
C2527
0.47UF
CERM-X5R-1
C2
MEM_B_DQ<8>
B7
MEM_B_DQ<9>
D3
MEM_B_DQ<10>
D7
MEM_B_DQ<11>
D2
MEM_B_DQ<12>
D8
MEM_B_DQ<13>
E3
MEM_B_DQ<14>
E7
MEM_B_DQ<15>
C3
MEM_B_DQS_P<1>
B3
MEM_B_DQS_N<1>
A7
PP1V2_S3 PP1V2_S3
A3
NC
L9
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7 120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
128 120
26 25 24 7
120 26 25 24 7
26 25 24 7
120 26 25 24 7
26 25 24 7
26 25 24
120
120 26 25 24 7
MEM_B_A<0>
120
MEM_B_A<1>
120
MEM_B_A<2>
120
MEM_B_A<3>
120
MEM_B_A<4>
120
MEM_B_A<5>
120
MEM_B_A<6>
120
MEM_B_A<7>
120
MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
MEM_B_BA<0>
120
MEM_B_BA<1> MEM_B_BG<0>
120
MEM_B_BG<1>
120 7
MEM_B_PARMEM_B_ALERT_LMEM_B_PAR MEM_B_ACT_L
24 25 117
VDD
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VDDQ
VDDQ
NF/TDQS_C
E8
VDDQ
VDDQ
DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
DQ0 DQ1 DQ2 DQ3
C2
MEM_B_DQ<16>
B7
MEM_B_DQ<17>
D3
MEM_B_DQ<18>
D7
MEM_B_DQ<19>
D2
MEM_B_DQ<20>
D8
MEM_B_DQ<21>
E3
MEM_B_DQ<22>
E7
MEM_B_DQ<23>
C3
MEM_B_DQS_P<2>
B3
MEM_B_DQS_N<2>
A7
PP1V2_S3
A3
NC
L9
MEM_B_ALERT_L
24 7
128 120
120 26 25
26 25 24 7
120 26 25
120 26 25
120 26 25
120 26 25
26 25 24 7
120 26 25
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
26 25 24 7
120 26 25 24 7
24 25 117
120 26 25 24
120 26 25 24 7
120
26 25 24 7
7
120 26 25 24 7
120
24 7
128 120
24 7
128 120
24 7
128 120
24 7
128 120
120
24 7
128 120
128 120
120
7
120
26 25 24
C2537
0.47UF
20%
CERM-X5R-1
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0> MEM_B_BG<1>
MEM_B_PAR MEM_B_ACT_L
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2530
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
24 25 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
C2
MEM_B_DQ<24>
B7
MEM_B_DQ<25>
D3
MEM_B_DQ<26>
D7
MEM_B_DQ<27>
D2
MEM_B_DQ<28>
D8
MEM_B_DQ<29>
E3
MEM_B_DQ<30>
E7
MEM_B_DQ<31>
C3
MEM_B_DQS_P<3>
B3
MEM_B_DQS_N<3>
A7 A3
NC
L9
MEM_B_ALERT_L
120 128
117 24 25
120 25 7 24 26
D
128 120
128 120
128 120
128 120
128 120
128 120
128 120
120 128
120 128
C
120
25 24 7
26
120
25 24 7
26
120 25
MEM_B_CKE<0>
7 24 26
MEM_B_CS_L<0>
7 24 25
MEM_B_ODT<0>
26 120
120 25
MEM_B_CKE<1>
7 24 26
MEM_B_CS_L<1>
7 24 25
MEM_B_ODT<1>
26 120
26 24
MEM_RESET_L
22 23 25
120 25
MEM_B_CLK_P<0>
7 24 26
7
MEM_B_CLK_N<0>
24 25 26 120
G3 G7
F3
G2 G8
F2
L1
F7 F8
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS
C8
E1
VSS
E9
VSS
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
VSSQ
A2
VSSQ
A8
VSSQ
D1
VREFCA
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VSSQ
ZQ
B1
PP2V5_S3 PP2V5_S3 PP2V5_S3 PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_B
J1
G9
MEM_B_TEN
B9
MEM_B_ZQ<0> MEM_B_ZQ<1>
R2500
240
1%
1/20W
MF
201
C2508
0.047UF
2
1
10%
6.3V X5R 201
26 25 24 7
120 26 25 24 7
120 26 25 24 7
25 24
117
26 25 24 7
1
26 25 24 7
2
25 24 23 22
26 25 24 7
26 25 24 7
MEM_B_CKE<0>
120
MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CKE<1> MEM_B_CS_L<1>
120
MEM_B_ODT<1>
120
MEM_RESET_L
26
MEM_B_CLK_P<0>
120
MEM_B_CLK_N<0>
120
CKE
G3
CS*
G7
F3
ODT
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
L1
RESET*
CK_T
F7
CK_C
F8
VSS C8
VSS E1
VSS E9
VSS G1
VSS H9
VSS K1
VSS K9
VSS N1
VSSQ
VSSQ
A2
A8
VSSQ
VSSQ
D1
D9
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ A9
ZQ
B1 M9
J1
PP0V6_S3_MEM_VREFCA_B
G9
B9
R2510
1/20W
240
201
2
1% MF
1
C2518
0.047UF
10%
6.3V X5R 201
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
1
2
26 25 24 23 22
120 26 25 24 7
120 26 25 24 7
26 25 24 7
26 25 24 7
120
120
MEM_B_CKE<0> MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CKE<1> MEM_B_CS_L<1> MEM_B_ODT<1>
MEM_RESET_L
MEM_B_CLK_P<0> MEM_B_CLK_N<0>
G3 G7
F3
G2 G8
F2
L1
F7 F8
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS
C8
E1
VSS
E9
VSS
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
VSSQ
A2
VSSQ
A8
VSSQ
D1
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VREFCA
VSSQ
ZQ
B1 M9
J1
PP0V6_S3_MEM_VREFCA_B
G9
C2528
0.047UF
B9
MEM_B_ZQ<2>
240
1%
1/20W
MF
201
2
1
R2520
6.3V
10% X5R
201
1
2
120 26 25 24 7
120 26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
25 24 23 22
26 25 24 7
26 25 24 7
26
MEM_B_CKE<0>
120
MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CKE<1>
120
MEM_B_CS_L<1>
120
MEM_B_ODT<1>
120
MEM_RESET_L
MEM_B_CLK_P<0>
120
MEM_B_CLK_N<0>
120
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
VSS C8
VSS E1
VSS E9
VSS G1
VSS H9
VSS
VSS
K1
K9N1A2
VSS
VSSQ
VSSQ
A8
VSSQ
D1
RFU/TEN
VSSQ
A9
D9
VPP0
VPP1
VREFCA
VSSQ
ZQ
B1 M9
J1
PP0V6_S3_MEM_VREFCA_B
G9
MEM_B_TENMEM_B_TENMEM_B_TEN
B9
MEM_B_ZQ<3>
R2530
1/20W
240
1% MF
201
C2538
0.047UF
2
1
10%
6.3V X5R 201
C
117 24 25
1
2
B
PP2V5_S3
C2550
PP1V2_S3
C2500
2.2UF
20%
6.3V
X5R-CERM
0201
PP1V2_S3
1.0UF
20%
6.3V X5R
0201-1
1
2
1
2
C2501
2.2UF
20%
6.3V
X5R-CERM
0201
C2551
1.0UF
20%
6.3V X5R
0201-1
24 25 117
1
2
C2502
24 25 117
24 25 117
1
2
2.2UF
20%
6.3V
X5R-CERM
0201
C2552
1.0UF
20%
6.3V X5R
0201-1
1
2
C2503
1
2
2.2UF
20%
6.3V
X5R-CERM
0201
C2553
1.0UF
20%
6.3V X5R
0201-1
1
2
C2510
1
2
2.2UF
20%
6.3V
X5R-CERM
0201
C2554
1.0UF
20%
6.3V X5R
0201-1
1
2
C2511
1
2
2.2UF
20%
6.3V
X5R-CERM
0201
Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)
C2555
1.0UF
20%
6.3V X5R
0201-1
1
C2556
1.0UF
2
0201-1
20%
6.3V X5R
1
2
C2557
1.0UF
20%
6.3V X5R
0201-1
1
2
C2558
1.0UF
20%
6.3V X5R
0201-1
1
2
C2559
1.0UF
20%
6.3V X5R
0201-1
1
2
C2560
1.0UF
20%
6.3V X5R
0201-1
1
2
C2561
1.0UF
20%
6.3V X5R
0201-1
1
2
VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)
1
2
C2512
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
C2513
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
1
C2504
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2505
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2506
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2570
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2509
0.1UF
10%
6.3V
2
CERM-X5R 0201
VDD/VDDQ Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
C2562
1.0UF
20%
6.3V X5R
0201-1
1
2
1
C2514
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2563
1.0UF
20%
6.3V X5R
0201-1
1
2
1
2
C2515
0.1UF
10%
6.3V CERM-X5R 0201
C2564
1.0UF
20%
6.3V X5R
0201-1
1
C2516
2
1
2
0.1UF
10%
6.3V CERM-X5R 0201
C2565
1.0UF
20%
6.3V X5R
0201-1
1
C2571
2
1
2
0.1UF
10%
6.3V CERM-X5R 0201
1
C2519
0.1UF
10%
6.3V
2
CERM-X5R 0201
B
A
C2520
2.2UF
6.3V
X5R-CERM
0201
PP1V2_S3
20%
1
2
1
2
C2521
2.2UF
X5R-CERM
C2580
0.1UF
10%
6.3V CERM-X5R 0201
1
20%
2
6.3V 0201
24 25 117
1
C2581
2
C2522
0.1UF
10%
6.3V CERM-X5R 0201
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2582
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2523
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2583
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2530
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2584
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2531
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2585
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2532
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2586
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2533
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
C2524
0.1UF
10%
2
6.3V CERM-X5R 0201
5x 0.1uF per chip
1
C2587
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2588
2
1
2
0.1UF
10%
6.3V CERM-X5R 0201
C2525
0.1UF
10%
6.3V CERM-X5R 0201
C2589
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2526
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2590
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2572
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2591
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2529
0.1UF
10%
2
6.3V CERM-X5R 0201
C2592
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2534
0.1UF
10%
2
6.3V CERM-X5R 0201
C2593
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2535
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2594
0.1UF
10%
6.3V CERM-X5R 0201
1
C2536
0.1UF
10%
2
6.3V CERM-X5R 0201
C2595
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2573
0.1UF
10%
2
6.3V CERM-X5R 0201
C2596
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2539
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2597
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2598
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2599
0.1UF
10%
6.3V
2
CERM-X5R 0201
BOM_COST_GROUP=DRAM
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
DDR4 SDRAM Channel B 1
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
25 OF 200
SHEET
24 OF 135
A
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67
35 4
2
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Page 25
Vinafix.com
678
3 245
1
D
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
24 7 25
24 7
C
26 25
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 24 22 23 25
26 25 24 7
24 7
120 26 25
C2607
0.47UF
CERM-X5R-1
MEM_B_A<0>
120
MEM_B_A<1>
120
MEM_B_A<2>
120
MEM_B_A<3>
120
MEM_B_A<4>
120
MEM_B_A<5>
120
MEM_B_A<6>
120
MEM_B_A<7>
120
MEM_B_A<8>
120
MEM_B_A<9>
120
MEM_B_A<10>
120
MEM_B_A<11>
120
MEM_B_A<12>
120
MEM_B_A<13>
120
MEM_B_A<14>
120
MEM_B_A<15>
120
MEM_B_A<16>
120
MEM_B_BA<0>
120
MEM_B_BA<1>
120
MEM_B_BG<0>
120
MEM_B_BG<1>
120
120 26
MEM_B_PAR
120
MEM_B_ACT_L
MEM_B_CKE<0>
120
MEM_B_CS_L<0>
120
MEM_B_ODT<0>
120
MEM_B_CKE<1>
120
MEM_B_CS_L<1>
120
MEM_B_ODT<1>
120
MEM_RESET_L
MEM_B_CLK_P<0>
120
20%
4V
201
NC
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
G3 G7
F3
G2 G8
F2
L1
F7 F8
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
VSS C8
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U2600
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
OMIT_TABLE
VSS
VSS
VSS
K1
K9
VSS N1
VSS E1
VSS E9
VSS G1
H9
24 25 117
E8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/DM*/DBI*/TDQS_T
NF/TDQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A2
A8
D1
D9
A9
ZQ
C2
MEM_B_DQ<32>
B7
MEM_B_DQ<33>
D3
MEM_B_DQ<34>
D7
MEM_B_DQ<35>
D2
MEM_B_DQ<36>
D8
MEM_B_DQ<37>
E3
MEM_B_DQ<38>
E7
MEM_B_DQ<39>
C3
MEM_B_DQS_P<4>
B3
MEM_B_DQS_N<4>
A7
PP1V2_S3
A3
NC
L9
MEM_B_ALERT_L
B1
PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_B
J1
MEM_B_TEN
G9
B9
MEM_B_ZQ<4>
R2600
26
240
1%
1/20W
MF
201
25 24
0.047UF
2
1
C2608
10%
6.3V X5R 201
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
26 25 24 7
120 26 25 24 7
26 25 24 7
120 26 25 24 7
120
26 25 24 7
7
120 26 25 24 7
26 25 24 7
120 26 25 24 7
120 26 25 24 7
26 25 24 7
26 25 24 7
1
25 24 23 22
2
26 25 24 7
26 25 24 7
120
128 120
24 7
120 26 25
128 120
24 7
120 26 25
128 120
24 7
120 26 25
128 120
120
120
26 25 24
120
117 25 24
120
120
26
120
120
C2617
0.47UF
CERM-X5R-1
MEM_B_A<0>
120
MEM_B_A<1> MEM_B_A<2>
120
MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6>
120
MEM_B_A<7>
120
MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
MEM_B_BA<0>
120
MEM_B_BA<1> MEM_B_BG<0> MEM_B_BG<1>
MEM_B_PAR MEM_B_ACT_L
MEM_B_CKE<0> MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CS_L<1> MEM_B_ODT<1>
MEM_RESET_L
MEM_B_CLK_P<0> MEM_B_CLK_N<0>
20%
4V
201
1
2
NC
PP1V2_S3
C7F1F9H1J9M1N9A1B2B8C1C9E2
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
BA0
K2
BA1
K8
BG0
J2
BG1
J8
PAR
N3
ACT*
H3
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
C8
VDD
VDD
VDD
VDD
16GB-64X8X2-2400
OMIT_TABLE
VSS
E9
VSS
G1
VSS
H9
VSS
E1
VDD
VDD
VDD
VDD
U2610
MT40A2G8-NRE
FBGA
VSS
VSS
VSS
VSS
K1
K9
N1
24 25 117
E8
VDDQ
VDDQ
VSSQ
A8
VDDQ
VDDQ
NF/TDQS_C
VSSQ
VSSQ
A9
D1
D9
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
VPP0 VPP1
VREFCA
RFU/TEN
VSSQ
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VSSQ
A2
ZQ
PP1V2_S3
C2627
0.47UF
CERM-X5R-1
C2
MEM_B_DQ<40>
B7
MEM_B_DQ<41>
D3
MEM_B_DQ<42>
D7
MEM_B_DQ<43>
D2
MEM_B_DQ<44>
D8
MEM_B_DQ<45>
E3
MEM_B_DQ<46>
E7
MEM_B_DQ<47>
C3
MEM_B_DQS_P<5>
B3
MEM_B_DQS_N<5> MEM_B_DQS_N<6>
A7
PP1V2_S3 PP1V2_S3
A3
NC
L9
MEM_B_ALERT_L
B1
PP2V5_S3 PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_B
J1
2
1% MF
1
C2618
0.047UF
10%
6.3V X5R 201
MEM_B_TEN MEM_B_TEN MEM_B_TEN
G9
B9
24 25 26
MEM_B_ZQ<5> MEM_B_ZQ<6>
R2610
240
1/20W
201
26 25 24 7 128 120
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
128 120
128 120 128 120
120 26 25 24
120 26 25 24 7
26 25 24 7
120 26 25 24 7
26 25 24
120
120 26 25 24 7
26 25 24 7
120 26 25 24 7
120 26 25 24 7
26 25 24 7
26 25 24 7
1
26 25 24 7
2
25 24 23 22
26 25 24 7
26 25 24 7
MEM_B_A<0> MEM_B_DQ<48>
120
MEM_B_A<1>
120
MEM_B_A<2>
120
MEM_B_A<3>
120
MEM_B_A<4>
120
MEM_B_A<5>
120
MEM_B_A<6>
120
MEM_B_A<7>
120
MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
7
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0>
120
MEM_B_BG<1>
120 7
26 25 24 7
MEM_B_PAR MEM_B_ACT_L
MEM_B_CKE<0>
120
MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CKE<1>
120
MEM_B_CS_L<1>
120
MEM_B_ODT<1>
120
MEM_RESET_L
26
MEM_B_CLK_P<0>
120
MEM_B_CLK_N<0>
120
20%
4V
201
NC
1
2
C7F1F9H1J9M1N9A1B2B8C1C9E2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
L3
A0
L7
A1
M3
A2
K7
A3
K3
A4
L8
A5
L2
A6
M8
A7
M2
A8
M7
A9
J3
A10/AP
N2
A11
J7
A12/BC*
N8
A13
H2
WE*/A14
H7
CAS*/A15
H8
RAS*/A16
N7
A17/NC
K2
BA0
K8
BA1
J2
BG0
J8
BG1
PAR
N3
ACT*
H3
CKE
G3
CS*
G7
ODT
F3
C0/CKE1
G2
C1/CS1*
G8
C2/ODT1
F2
RESET*
L1
CK_T
F7
CK_C
F8
16GB-64X8X2-2400
OMIT_TABLE
VSS
VSS
VSS
E1
E9
C8
U2620
MT40A2G8-NRE
VSS
VSS
VSS
K1
H9
G1
FBGA
VSS K9
24 25 117
VDD
VDDQ
VDDQ
NF/DM*/DBI*/TDQS_T
VSSQ
VSS
A2
N1
VDDQ
VSSQ
VSSQ
A8
D1
VDDQ
NF/TDQS_C
VSSQ D9
E8
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
ZQ
VSSQ A9
C2 B7
MEM_B_DQ<49>
D3
MEM_B_DQ<50>
D7
MEM_B_DQ<51>
D2
MEM_B_DQ<52>
D8
MEM_B_DQ<53>
E3
MEM_B_DQ<54>
E7
MEM_B_DQ<55>
C3
MEM_B_DQS_P<6>
B3
A7 A3
NC
L9
MEM_B_ALERT_L
B1 M9
J1
PP0V6_S3_MEM_VREFCA_BMEM_B_CKE<1>
G9
B9
R2620
1/20W
24 25 26
240
1% MF
201
C2628
0.047UF
2
1
10%
6.3V X5R 201
120 26 25
128 120
120 26 25
128 120
120 26 25
128 120
120 26 25
128 120
120 26 25
128 120
120 26 25
128 120
120 26 25
128 120
120 26 25
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
128 120
120 26 25
120 26 25 24 7
24 25 117
120 26 25 24
120 26 25 24 7
120
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
120 26 25 24 7
1
2
26 25 24 23 22
120 26 25 24 7
120 26 25 24 7
26 25 24
24 25 117
120 26 25 24
26 25 24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
24 7
26 25 24 7
C2637
0.47UF
20%
CERM-X5R-1
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15> MEM_B_A<16>
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0>
7
MEM_B_BG<1>
120
MEM_B_PAR
7
MEM_B_ACT_L
MEM_B_CKE<0>
7
MEM_B_CS_L<0> MEM_B_ODT<0>
MEM_B_CKE<1> MEM_B_CS_L<1> MEM_B_ODT<1>
120
MEM_RESET_L
MEM_B_CLK_P<0> MEM_B_CLK_N<0>MEM_B_CLK_N<0>
201
NC
4V
PP1V2_S3
1
2
L3 L7
M3
K7 K3
L8
L2 M8 M2 M7
J3
N2
J7
N8 H2 H7 H8 N7
K2 K8
J2
J8
N3 H3
G3 G7
F3
G2 G8
F2
L1
F7 F8
C7F1F9H1J9M1N9
VDD
VDD
VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 WE*/A14 CAS*/A15 RAS*/A16 A17/NC
BA0 BA1 BG0 BG1
PAR ACT*
CKE CS* ODT
C0/CKE1 C1/CS1* C2/ODT1
RESET*
CK_T CK_C
C8
OMIT_TABLE
VSS
VSS
VSS
E1
E9
24 25 117
A1B2B8C1C9E2E8
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
U2630
16GB-64X8X2-2400
MT40A2G8-NRE
FBGA
NF/DM*/DBI*/TDQS_T
VSSQ
VSSQ
G1
VSS
H9
VSS
K1
VSS
K9
VSS
N1
VSS
A2
A8
VSSQ
D1
VDDQ
VDDQ
VDDQ
DQ0 DQ1 DQ2
DQ3 DQ4/NC DQ5/NC DQ6/NC DQ7/NC
DQS_T
DQS_C
NF/TDQS_C
ALERT*
VPP0
VPP1
VREFCA
RFU/TEN
VSSQ
VSSQ
A9
D9
ZQ
MEM_B_DQ<56>
C2
MEM_B_DQ<57>
B7
MEM_B_DQ<58>
D3
MEM_B_DQ<59>
D7
MEM_B_DQ<60>
D2
MEM_B_DQ<61>
D8
MEM_B_DQ<62>
E3
MEM_B_DQ<63>
E7
MEM_B_DQS_P<7>
C3
MEM_B_DQS_N<7>
B3
PP1V2_S3
A7 A3
NC
MEM_B_ALERT_L
L9
B1
PP2V5_S3
M9
PP0V6_S3_MEM_VREFCA_B
J1
G9
MEM_B_ZQ<7>
B9
R2630
24 25 26
240
1%
1/20W
MF
201
C2638
0.047UF
2
1
10%
6.3V X5R 201
1
2
D
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
128 120
24 25 117
120 25 7 24 26
C
24 25 117
25 24
117
B
PP2V5_S3
C2650
1.0UF
20%
6.3V X5R
0201-1
PP1V2_S3
C2600
2.2UF
20%
6.3V
X5R-CERM
0201
PP1V2_S3
24 25 117
1
C2651
1.0UF
2
0201-1
1
2
C2601
2.2UF
X5R-CERM
20%
6.3V X5R
20%
6.3V 0201
1
2
24 25 117
1
2
24 25 117
C2652
1.0UF
20%
6.3V X5R
0201-1
C2602
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
1
2
C2653
1.0UF
20%
6.3V X5R
0201-1
C2603
2.2UF
20%
6.3V
X5R-CERM
0201
1
C2654
1.0UF
2
0201-1
1
2
C2610
2.2UF
X5R-CERM
20%
6.3V X5R
20%
6.3V 0201
1
C2655
1.0UF
2
1
2
C2611
6.3V
0201-1
2.2UF
20%
6.3V
X5R-CERM
0201
Vpp Bypassing Placeholder (NOTE: 4x 1uF per chip)
20% X5R
1
C2656
1.0UF
2
0201-1
20%
6.3V X5R
1
C2657
1.0UF
2
20%
6.3V X5R
0201-1
1
C2658
1.0UF
2
0201-1
20%
6.3V X5R
1
C2659
1.0UF
2
0201-1
20%
6.3V X5R
1
C2660
1.0UF
2
0201-1
20%
6.3V X5R
1
C2661
1.0UF
2
0201-1
20%
6.3V X5R
1
2
C2662
VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)
1
C2604
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V 0201
1
2
C2613
2.2UF
X5R-CERM
1
2
C2612
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
1
C2605
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2606
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2670
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2609
2
VDD/VDDQ Bypassing (NOTE: 4x 2.2uF and 5x 0.1uF per chip)
1.0UF
20%
6.3V X5R
0201-1
0.1UF
10%
6.3V CERM-X5R 0201
1
C2663
1.0UF
2
0201-1
1
C2614
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
1
C2664
1.0UF
2
0201-1
1
C2615
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
1
2
C2665
1.0UF
0201-1
1
C2616
0.1UF
10%
6.3V
2
CERM-X5R 0201
20%
6.3V X5R
1
2
1
C2671
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2619
0.1UF
10%
6.3V
2
CERM-X5R 0201
B
A
C2620
PP1V2_S3
2.2UF
20%
6.3V
X5R-CERM
0201
C2680
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
2
C2621
2.2UF
6.3V
X5R-CERM
0201
24 25 117
C2681
1
0.1UF
10%
2
6.3V CERM-X5R 0201
20%
1
2
C2622
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
C2623
2.2UF
20%
6.3V
X5R-CERM
0201
1
2
C2630
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
C2631
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
C2632
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
C2633
2.2UF
X5R-CERM
20%
6.3V 0201
1
2
1
C2624
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2625
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2626
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2672
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2629
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2634
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2635
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2636
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2673
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2639
0.1UF
10%
6.3V
2
CERM-X5R 0201
5x 0.1uF per chip
A
D
C2682
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2683
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2684
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2685
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2686
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2687
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2688
1
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2689
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2690
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2691
0.1UF
10%
2
6.3V CERM-X5R 0201
1
C2692
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2693
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2694
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2695
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
C2696
0.1UF
10%
6.3V
2
CERM-X5R 0201
C2697
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2698
1
0.1UF
10%
2
6.3V CERM-X5R 0201
C2699
1
0.1UF
10%
2
6.3V CERM-X5R 0201
BOM_COST_GROUP=DRAM
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
DDR4 SDRAM Channel B 2
SIZE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
26 OF 200
SHEET
25 OF 135
8
67
35 4
2
1
Page 26
Vinafix.com
678
3 245
1
JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
D
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
PP0V6_S0_DDRVTT
26 117
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN IN IN IN
MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3>
MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7>
MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11>
MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>
R2700 R2701 R2702 R2703
R2704 R2705 R2706 R2707
R2708 R2709 R2710 R2711
R2712 R2713 R2714 R2715
36 36 36 36
36 36 36
36 36
36 36 36
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
5%
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
201MF1/20W 1/20W 2015% 1/20W 2015% 1/20W36MF 2015%
1/20W36MF 2015% 1/20W MF362015%
MF MF
MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
201MF5%361/20W
C2701,C2721 FOR DESENSE IMPROVEMENT LOCATION DEPENDS ON DESENSE TEAM
C2701
C2700
1
2.2UF
20% 4V
2
X5R-CERM 0201
C2702
1
2.2UF
20% 4V
2
X5R-CERM 0201
C2704
1
2.2UF
20% 4V
2
X5R-CERM 0201
1
12PF
5%
2
NP0-C0G 0201 25V
C2703
1
2.2UF
20% 4V
2
X5R-CERM 0201
C2705
1
0.47UF
20% 4V
2
CERM-X5R-1 201
D
C
23 22
MEM_A_TEN
25 24
MEM_B_TEN
1
R2753
100
5% 1/20W MF 201
2
1
R2755
100
5% 1/20W MF 201
2
R2752
0
1 2
5%
1/20W
MF
0201
R2754
0
1 2
5%
1/20W
MF
0201
MEM_A_TEN_R
NOSTUFF
C2752
1
0.47UF
20% 4V
2
CERM-X5R-1 201
MEM_B_TEN_R
NOSTUFF
C2753
1
0.47UF
20% 4V
2
CERM-X5R-1 201
TP2700
1
TP
TP2701
1
TP
TP-P5
TP-P5
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
120 23 22 7
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN
MEM_A_A<16> MEM_A_BA<0> MEM_A_BA<1> MEM_A_BG<0>
MEM_A_BG<1> MEM_A_CS_L<0> MEM_A_CS_L<1> MEM_A_CKE<0>
MEM_A_CKE<1> MEM_A_ODT<0> MEM_A_ODT<1> MEM_A_ACT_L
MEM_A_PAR
R2716 R2717 R2718 R2719
R2720 R2721 R2722 R2723
R2724 R2725 R2726 R2727
R2728
36 36 36
36 36 36 36
36 36 36 36
36
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2
26 117
PP0V6_S0_DDRVTT
C2707
C2706
1/20W36MF 2015%
201
MF1/20W5%
201
MF1/20W5% MF1/20W 2015%
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015%
1
0.47UF
20% 4V
2
CERM-X5R-1 201
C2708
1
0.47UF
20% 4V
2
CERM-X5R-1 201
C2710
1
0.47UF
20% 4V
2
CERM-X5R-1 201
1
0.47UF
20% 4V
2
CERM-X5R-1 201
1
C2711
2.2UF
20% 4V
2
X5R-CERM 0201
1
C2712
2.2UF
20% 4V
2
X5R-CERM 0201
C
B
120 23 22 7
120 23 22 7
120 25 24 7
120 25 24 7
7 120
7 120
7 120
7 120
7 120
7 120
7 120
7 120
MEM Clock Termination
Place RC end termination after last DRAM Place Source Cterm at neckdown at first DRAM
IN
IN
IN
IN
NC_MEM_A_CLK_N<1> NC_MEM_A_CLK_P<1> NC_MEM_A_CKE<2> NC_MEM_A_CKE<3> NC_MEM_B_CLK_N<1> NC_MEM_B_CLK_P<1> NC_MEM_B_CKE<2> NC_MEM_B_CKE<3>
MEM_A_CLK_N<0>
C2750
NOSTUFF
MEM_A_CLK_P<0>
NOSTUFF
MEM_B_CLK_P<0>
3300PF
10% 10V X7R-CERM 0201
C2760
3300PF
10% 10V X7R-CERM 0201
1
PLACE_NEAR=U2430.F8:10mm
2
PLACE_NEAR=U2630.F8:10mm
1
2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK_N<1> NC_MEM_A_CLK_P<1> NC_MEM_A_CKE<2> NC_MEM_A_CKE<3> NC_MEM_B_CLK_N<1> NC_MEM_B_CLK_P<1> NC_MEM_B_CKE<2> NC_MEM_B_CKE<3>
PLACE_NEAR=U2430.F8:8mm
PLACE_NEAR=U2430.F7:8mm
PLACE_NEAR=U2630.F8:8mm
PLACE_NEAR=U2630.F7:8mm
R2750
30
1 2
5%
1/20W
MF
201
R2751
30
1 2
5%
1/20W
MF
201
R2760
30
1 2
5%
1/20W
MF
201
R2761
30
1 2
5%
1/20W
MF
201
MEM_A_CLK0_TERM_R
MEM_B_CLK0_TERM_RMEM_B_CLK_N<0>
C2751
0.01UF
1 2
10% 25V
X5R-CERM
0201
C2761
0.01UF
1 2
10% 25V
X5R-CERM
0201
PP0V6_S0_DDRVTT
PP0V6_S0_DDRVTT
26 117
26 117
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
120 25 24 7
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN IN IN IN
IN
MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3>
MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7>
MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11>
MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>
MEM_B_A<16> MEM_B_BA<0> MEM_B_BA<1> MEM_B_BG<0>
MEM_B_BG<1> MEM_B_CS_L<0> MEM_B_CS_L<1> MEM_B_CKE<0>
MEM_B_CKE<1> MEM_B_ODT<0> MEM_B_ODT<1> MEM_B_ACT_L
MEM_B_PAR
R2770 R2771 R2772 R2773
R2774 R2775 R2776 R2777
R2778 R2779 R2780 R2781
R2782 R2783 R2784 R2785
R2786 R2787 R2788 R2789
R2790 R2791 R2792 R2793
R2794 R2795 R2796 R2797
R2798
36 36 36 36
36 36 36 36
36 36 36
36 36 36
36 36 36
36 36 36 36
36 36 36 36
36
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015% MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015% MF MF1/20W 2015%
MF5% MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015%
MF1/20W
MF1/20W 2015% MF MF1/20W 2015% MF1/20W 2015%
MF1/20W 2015%
201MF
201
201
2015%
1/20W5%
1/20W 2015%
1/20W36MF 2015%
1/20W 201
1/20W36MF 2015%
5% MF
1/20W 201
5% MF1/20W
1/20W5% MF
5%361/20W MF 201
1/20W MF 2015% 1/20W 201MF5%
1/20W 2015%
C2720
1
2.2UF
20% 4V
2
X5R-CERM 0201
C2722
1
2.2UF
20% 4V
2
X5R-CERM 0201
1
C2724
2.2UF
20% 4V
2
X5R-CERM 0201
C2726
1
0.47UF
20% 4V
2
CERM-X5R-1 201
C2728
1
0.47UF
20% 4V
2
CERM-X5R-1 201
C2730
1
0.47UF
20% 4V
2
CERM-X5R-1 201
C2721
1
12PF
5%
2
NP0-C0G 0201 25V
C2723
1
2.2UF
20% 4V
2
X5R-CERM 0201
1
C2725
0.47UF
20%
2
4V CERM-X5R-1 201
C2727
1
0.47UF
20% 4V
2
CERM-X5R-1 201
1
C2734
2.2UF
20% 4V
2
X5R-CERM 0201
1
C2735
2.2UF
20% 4V
2
X5R-CERM 0201
B
A
8
PP1V2_S3
470
1%
1/20W
MF
201
1
2
120 23 22 7
120 25 24 7
12
R2730
IN IN
IN
MEM_A_ALERT_L MEM_B_ALERT_L
PCH_DRAM_RESET_L
1
51
1%
1/20W
MF
201
2
R2732
0
1 2
5%
1/20W
MF
0201
R2731
51
1%
1/20W
MF
201
1
2
R2733
BOM_COST_GROUP=DRAM
67
35 4
22 23 117
MEM_RESET_L
NOSTUFF
1
C2732
0.1UF
10%
6.3V CERM-X5R
2
0201
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
DDR4 Termination
DRAWING NUMBER
25 24 23 22
Apple Inc.
051-04492
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
27 OF 200
SHEET
26 OF 135
1
SIZE
D
Page 27
Vinafix.com
678
3 245
1
D
C
B
A
1
R2890
3.3K
5% 1/20W MF 201
2
TBT_X_SPI_CLK TBT_X_SPI_MOSI
29 29
TBT_X_SPI_CS_L
29
123 27
TBT_X_ROM_WP_L
TBT_X_ROM_HOLD_L
120 97
120 97
120 97
120 97
120 97
120 97
120 97
120 97
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
DP_X_SNK0_ML_C_P<0>
DP_X_SNK0_ML_C_N<0>
DP_X_SNK0_ML_C_P<1>
DP_X_SNK0_ML_C_N<1>
DP_X_SNK0_ML_C_P<2>
DP_X_SNK0_ML_C_N<2>
DP_X_SNK0_ML_C_P<3> DP_X_SNK0_ML_P<3>
DP_X_SNK0_ML_C_N<3>
DP_X_SNK0_AUXCH_C_P
DP_X_SNK0_AUXCH_C_N DP_X_SNK0_AUXCH_N
DP_X_SNK1_ML_C_P<0>
DP_X_SNK1_ML_C_N<0>
DP_X_SNK1_ML_C_P<1>
DP_X_SNK1_ML_C_N<1>
DP_X_SNK1_ML_C_P<2>
DP_X_SNK1_ML_C_N<2>
DP_X_SNK1_ML_C_P<3>
DP_X_SNK1_ML_C_N<3>
DP_X_SNK1_AUXCH_C_P DP_X_SNK1_AUXCH_P
DP_X_SNK1_AUXCH_C_N
100K
1 2
10K
1 2
NOSTUFF
100K
1 2
100K
1 2
100K
1 2
100K
1 2
100K
1 2
100K
1 2
R2891
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
R2864 R2839
PU for NVM
R2863
5% 1/20W 201MF
R2873 R2862 R2872 R2860 R2861
1
3.3K
5%
1/20W
MF
201
1
2
R2893
3.3K
5% 1/20W MF 201
2
6
CLK
1
CS*
3
WP*(IO2)
7
HOLD*(IO3)
SNK0 AC Coupling
C2820
0.22UF
C2821
0.22UF
C2822
0.22UF
C2823
0.22UF
C2824
0.22UF
C2825
0.22UF
C2826
0.22UF
C2827
0.22UF
C2828
0.22UF
C2829
0.22UF
SNK1 AC Coupling
C2830
0.22UF
C2831
0.22UF
C2832
0.22UF
C2833
0.22UF
C2834
0.22UF
C2835
0.22UF
C2836
0.22UF
C2837
0.22UF
C2838
0.22UF
C2839
0.22UF
PP3V3_TBT_X_SX
TBT_X_BATLOW_L
201MF1/20W5%
201MF1/20W5%
TBT_X_TMU_CLK_IN
TBT_X_TMU_CLK_OUT
201MF1/20W5%
DP_XA_HPD
201MF1/20W5%
DP_XB_HPD
201MF1/20W5%
TBT_XA_USB2_MXCTL
201MF1/20W5%
TBT_XB_USB2_MXCTL
201MF1/20W5%
PP3V3_UPC_XB_LDO
8
VCC
U2890
8MBIT-3.0V
W25Q80DVUXIE
USON
OMIT_TABLE
CRITICAL
GND EPAD
4
9
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
6.3V20%
X5R
6.3V20%
X5R
6.3V20%
X5R
6.3V20%
X5R
20% 6.3V X5R
6.3V20%
X5R
6.3V 0201
20% X5R
X5R
20% 6.3V X5R
20% X5R
6.3V20%
X5R
6.3V20%
X5R
6.3V20%
X5R
6.3V20%
X5R
6.3V 020120%
X5R
6.3V20%
X5R
6.3V20%
X5R
6.3V20%
X5R
20% 6.3V X5R
6.3V
X5R
28 29
1
2
TBT_X_SPI_MISO
5%
1/20W
MF
201
5 2
1
2
R2892
3.3K
DI(IO0)
DO(IO1)
DP_X_SNK0_ML_P<0>
0201
DP_X_SNK0_ML_N<0>
0201
DP_X_SNK0_ML_P<1>
0201
DP_X_SNK0_ML_N<1>
0201
DP_X_SNK0_ML_P<2>
0201
DP_X_SNK0_ML_N<2>
0201
DP_X_SNK0_ML_N<3>
02016.3V20%
DP_X_SNK0_AUXCH_P
0201
02016.3V
DP_X_SNK1_ML_P<0>
0201
DP_X_SNK1_ML_N<0>
0201
DP_X_SNK1_ML_P<1>
0201
DP_X_SNK1_ML_N<1>
0201
DP_X_SNK1_ML_P<2>
DP_X_SNK1_ML_N<2>
0201
DP_X_SNK1_ML_P<3>
0201
DP_X_SNK1_ML_N<3>
0201
0201
DP_X_SNK1_AUXCH_N
020120%
27
27
27
120 30 27
120 31 27
27
27
27 29
C2890
1UF
10%
6.3V CERM 402
120 33
120 33
120 33
120 33
IN IN
IN IN
PCIE_TBT_X_R2D_P<0> PCIE_TBT_X_R2D_N<0>
PCIE_TBT_X_R2D_P<1> PCIE_TBT_X_R2D_N<1>
Y23 Y22
T23 T22
PCIE_RX0_P PCIE_RX0_N
PCIE_RX1_P PCIE_RX1_N
U2800
TITAN-RIDGE-DP
CSP
SYM 1 OF 2
OMIT_TABLE
PCIE_TX0_P PCIE_TX0_N
PCIE_TX1_P PCIE_TX1_N
V23 V22
P23 P22
CRITICAL
29
R2828
120 19 12
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
OUT
79 33 29 27
TBT_X_CLKREQ_L
120 95
120 95
1
R2825
100
5% 1/20W MF 201
2
PP3V3_TBT_X_SX
33 29
OUT
R2830
100K
1/20W
OUT
R2831
100K
1/20W
IN
1K
1 2
5%
1/20W
MF
201
1
5% MF
201
2
1
5% MF
201
2
123 107 18 14
123 107 18 14
1
R2829
100
5% 1/20W MF 201
2
NOSTUFF
1
R2836
2.2K
5% 1/20W MF 201
2
120 33
120 33
120 33
120 33
123 120 12
123 120 12
123 15
123 107 18
120 32
120 32
120 32
120 32
120 32
120 32
120 32
120 30 27
IN IN
IN IN
IN IN
IN IN IN
OUT
IN IN
OUT OUT
OUT OUT
IN IN
BI BI
IN
PCIE_TBT_X_R2D_P<2> PCIE_TBT_X_R2D_N<2>
PCIE_TBT_X_R2D_P<3> PCIE_TBT_X_R2D_N<3>
PCIE_CLK100M_TBT_X_P PCIE_CLK100M_TBT_X_N TBT_X_CLKREQ_R_L
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
DP_X_SNK0_ML_P<0> DP_X_SNK0_ML_N<0>
DP_X_SNK0_ML_P<1> DP_X_SNK0_ML_N<1>
DP_X_SNK0_ML_P<2> DP_X_SNK0_ML_N<2>
DP_X_SNK0_ML_P<3> DP_X_SNK0_ML_N<3>
DP_X_SNK0_AUXCH_P DP_X_SNK0_AUXCH_N DP_X_SNK0_HPD
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
DP_X_SNK1_ML_P<0> DP_X_SNK1_ML_N<0>
DP_X_SNK1_ML_P<1> DP_X_SNK1_ML_N<1>
DP_X_SNK1_ML_P<2> DP_X_SNK1_ML_N<2>
DP_X_SNK1_ML_P<3> DP_X_SNK1_ML_N<3>
DP_X_SNK1_AUXCH_P DP_X_SNK1_AUXCH_N DP_X_SNK1_HPD
JTAG_ISP_TDI JTAG_TBT_X_TMS JTAG_ISP_TCK JTAG_ISP_TDO
TBT_X_TEST_EN TBT_X_TEST_PWR_GOOD
USBC_XA_D2R_P<2> USBC_XA_D2R_N<2>
USBC_XA_R2D_CR_P<2> USBC_XA_R2D_CR_N<2>
USBC_XA_R2D_CR_P<1> USBC_XA_R2D_CR_N<1>
USBC_XA_D2R_P<1> USBC_XA_D2R_N<1>
USBC_XA_AUXLSX1 USBC_XA_AUXLSX2
DP_XA_HPD I2C_TBT_XA_INT_L TBT_XA_USB2_MXCTL
27
NC NC NC NC
NC NC
TBT_XA_USB2_RBIAS
PLACE_NEAR=U2800.H19:3MM
R2854
200
1/20W
PLACE_NEAR=U2800.H6:2MM PLACE_NEAR=U2800.J6:2MM
1% MF
201
1
TBT_X_RBIAS
2
1 2
TF 1/20W
R2855
4.75K
0.5% 0201
TBT_X_RSENSE
M23 M22
H23 H22
V19
T19
AC7
AB7
AB9 AC9
AC11 AB11
AB13 AC13
AA2
AC5 AB5 AC3 AB3
W20
Y20
W19
Y19
A15 B15
A17 B17
A19 B19
B21 A21
E20 D20
H19
A23
AC23
AC1
PCIE_RX2_P PCIE_RX2_N
PCIE_RX3_P PCIE_RX3_N
PCIE_REFCLK_100_IN_P PCIE_REFCLK_100_IN_N
Y6 N16
PCIE_CLKREQ*
DPSNK1_ML0_P DPSNK1_ML0_N
DPSNK1_ML1_P DPSNK1_ML1_N
DPSNK1_ML2_P DPSNK1_ML2_N
DPSNK1_ML3_P DPSNK1_ML3_N
N1
DPSNK1_AUX_P
N2
DPSNK1_AUX_N
SNK1_HPD
A5
DPSNK2_ML0_P
B5
DPSNK2_ML0_N
B3
DPSNK2_ML1_P
A3
DPSNK2_ML1_N
C2
DPSNK2_ML2_P
C1
DPSNK2_ML2_N
E2
DPSNK2_ML3_P
E1
DPSNK2_ML3_N
P1
DPSNK2_AUX_P
P2
DPSNK2_AUX_N
Y4
SNK2_HPD
U0_SSTXP1 U0_SSTXN1 U0_SSRXP1 U0_SSRXN1
TDI TMS TCK TDO
R4
TEST_EN
W5
TEST_PWR_GOOD ASSRXP2
ASSRXN2 ASSTXP2
ASSTXN2 ASSTXP1
ASSTXN1 ASSRXP1
ASSRXN1
H4
ASBU1
J4
ASBU2 PA_USB2_D_P
PA_USB2_D_N
T2
PA_HPD
M4
PA_I2C_INT
R2
PA_USB2_MXCTL PA_USB2_RBIAS
J6
RBIAS
J5
RSENSE
PA_MONDC
A1
PB_MONDC PC_MONDC USB_MONDC
D4
TEST_EDM
L8
FUSE_VQPS_64
SINK PORT 1SINK PORT 2
USBSSJTAG
PCIE GEN3
TBT PORT A
DEBUG
SOURCE PORT
LC GPIOPOC GPIOFLASH
TBT PORT B
PCIE_TX2_P PCIE_TX2_N
PCIE_TX3_P PCIE_TX3_N
PERST*
PCIE_RBIAS
DPSRC_ML0_P DPSRC_ML0_N
DPSRC_ML1_P DPSRC_ML1_N
DPSRC_ML2_P DPSRC_ML2_N
DPSRC_ML3_P DPSRC_ML3_N
DPSRC_AUX_P DPSRC_AUX_N
DPSRC_HPD
GPIO_0 GPIO_1 EE_WP*
TMU_CLKOUT
WAKE*
CIO_PLUG_EVENT*
TMU_CLKIN
I2C_SCL
I2C_SDA
USB_FORCE_PWR
FORCE_PWR
BATLOW*
SLP_S3*
RTD3_PWR_EN
RESET*
XTAL_25_IN
XTAL_25_OUT
EE_DI
EE_DO
EE_CS*
EE_CLK
BSSRXp2 BSSRXn2
BSSTXp2 BSSTXn2
BSSTXp1 BSSTXn1
BSSRXp1 BSSRXn1
BSBU1 BSBU2
PB_USB2_D_P
PB_USB2_D_N
PB_HPD
PB_I2C_INT
PB_USB2_MXCTL
PB_USB2_RBIAS
USB2_ATEST
PCIE_ATEST
MONDC_SVR
VGA_RES
ATEST_P ATEST_N
THERMDA
K23 K22
F23 F22
T4
AB21 AC21
AC19 AB19
AB17 AC17
AC15 AB15
N4 N5
R5
W1 W2
W4 Y1 Y2 AA1 W6
V2 V1 V5 V4 U2 U1 T5
E5 D22
D23 Y18
W16 W18 Y16
B7 A7
A9 B9
A11 B11
A13 B13
L4 L5
E19 D19
T1
M5 R1 F19
B23
AB23
D5
H5
J9
J11
V8
PCIE_TBT_X_D2R_C_P<0> PCIE_TBT_X_D2R_C_N<0>
PCIE_TBT_X_D2R_C_P<1> PCIE_TBT_X_D2R_C_N<1>
PCIE_TBT_X_D2R_C_P<2> PCIE_TBT_X_D2R_C_N<2>
PCIE_TBT_X_D2R_C_P<3> PCIE_TBT_X_D2R_C_N<3>
TBT_X_PCI_RESET_L TBT_X_PCIE_BIAS
NC_DP_X_SRC_ML_P<0> NC_DP_X_SRC_ML_N<0>
NC_DP_X_SRC_ML_P<1> NC_DP_X_SRC_ML_N<1>
NC_DP_X_SRC_ML_P<2> NC_DP_X_SRC_ML_N<2>
NC_DP_X_SRC_ML_P<3> NC_DP_X_SRC_ML_N<3>
NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N
DP_X_SRC_HPD
TBT_X_HDMI_DDC_DATA
TBT_X_HDMI_DDC_CLK TBT_X_ROM_WP_L TBT_X_TMU_CLK_OUT TBT_WAKE_3V3_L TBT_X_PLUG_EVENT_L TBT_X_TMU_CLK_IN
I2C_TBT_X_SCL I2C_TBT_X_SDA TBT_X_USB_PWR_EN TBT_X_CIO_PWR_EN TBT_X_BATLOW_L PM_SLP_S3_L TBT_X_RTD3_PWR_EN
USBC_X_RESET_L TBT_X_XTAL25M_IN
TBT_X_XTAL25M_OUT UPC_X_SPI_MOSI
UPC_X_SPI_MISO UPC_X_SPI_CS_L UPC_X_SPI_CLK
29
29
29
29
To SPI Flash
USBC_XB_D2R_P<2> USBC_XB_D2R_N<2>
USBC_XB_R2D_CR_P<2> USBC_XB_R2D_CR_N<2>
USBC_XB_R2D_CR_P<1> USBC_XB_R2D_CR_N<1>
USBC_XB_D2R_P<1> USBC_XB_D2R_N<1>
USBC_XB_AUXLSX1 USBC_XB_AUXLSX2
NC NC
DP_XB_HPD
IN
BI BI
120
31 27
120 31 120 30
I2C_TBT_XB_INT_L TBT_XB_USB2_MXCTL
27
TBT_XB_USB2_RBIAS
PLACE_NEAR=U2800.F19:3MM 1
R2853
200
1%
NC NC
NC NC
NC
TBTTHMSNS_X_D1_P
USE NEAREST GND BALL (AC22) FOR THERM_D_N
1/20W MF 201
2
OUT
BOM_COST_GROUP=TBT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
IN
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
29
OUT OUT
27
OUT OUT
IN IN
27
IN
IN
IN
OUT
IN IN
OUT OUT
OUT OUT
IN IN
PP3V3_TBT_X_SX
NOSTUFF
1
R2837
2.2K
5% 1/20W MF 201
2
57
120 33
120 33
120 33
120 33
120 33
120 33
120 33
120 33
PLACE_NEAR=U2800.N16:2MM
33 20 14
29
29
29
29
29
29
29
29
29
29
29
29
123 27
33 14
27
PU at PCH
33 29
120 29
120 29
120 32
120 32
120 32
120 32
120 32
120 32
120 32
120 32
IN
33 29
SYNC_MASTER=YANIR SYNC_DATE=01/17/2019
PAGE TITLE
R2851
3.01K
1 2
113 107 33 29
33 31 30 14
33 31 30 14
135 121 107 14 12
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
1%
1/20W
MF
201
PP3V3_UPC_XB_LDO
1
R2834
2.2K
5% 1/20W MF 201
2
1
R2835
2.2K
5% 1/20W MF 201
2
BI BI
79 33 29 27
33 29
33 29
PP3V3_TBT_X_SX
1
R2827
100K
5% 1/20W MF 201
2
USB-C HIGH SPEED 1
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
BRANCH
PAGE
28 OF 200
SHEET
27 OF 135
27 29
SIZE
D
33 27 29 79
D
C
B
A
8
67
35 4
2
1
Page 28
Vinafix.com
678
3 245
1
D
C
B
A
C2930
1
4UF
20%
6.3V
2
CER-X5R 0201
1
C2931
4UF
20%
2
6.3V CER-X5R 0201
SOURCED BY INTERNAL SWITCH
1
C2932
2
C2968
1
10UF
20%
2
6.3V CERM-X5R 0402-4
1
C2984
1.0UF
20%
6.3V X5R
2
0201-1
4UF
20%
6.3V CER-X5R 0201
1
C2933
4UF
20%
2
6.3V CER-X5R 0201
C2964
1
1.0UF
20%
2
6.3V X5R 0201-1
1
C2985
1.0UF
20%
6.3V X5R
2
0201-1
SOURCED BY INTERNAL SWITCH
1
C2934
4UF
20%
6.3V
2
CER-X5R 0201
C2965
1
1.0UF
20%
2
6.3V X5R 0201-1
SOURCED BY INTERNAL SWITCH
1
C2935
4UF
20%
2
6.3V CER-X5R 0201
SOURCED BY INTERNAL SWITCH
C2966
1
1.0UF
20%
6.3V
2
X5R 0201-1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
1
2
VOLTAGE=3.3V
C2920
1.0UF
20%
6.3V X5R 0201-1
1
C2936
4UF
20%
6.3V
2
CER-X5R 0201
C2967
1
1.0UF
20%
2
6.3V X5R 0201-1
PP0V9_TBT_X_SVR
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
PP0V9_TBT_X_PCIE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V
PP3V3_TBT_X_ANA PP3V3_TBT_X_ANA_PCIE PP3V3_TBT_X_ANA_USB2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V
1
C2921
1.0UF
20%
2
6.3V X5R 0201-1
SOURCED BY INTERNAL SWITCH
H11
H9 H12 H13 H15 H16
T12 T13 T15
N6
T11
T9
E8 J18 L19
M19
L18
M18 M16
E16
L16
H18
W11
Y11
Y5
W12
Y12
Y8
AB4
AC4
C23 C22
W13
AB2
D6
W15
Y15
A4
B4
F2
D2
F1
D1
B1
B2
E18 V11 V12 V13
M6 N19 N18 E12 E13
F11 F12 F13 F15
J16
A2 F8 A6 A8 B8
AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22
AC6 AC8
B10 AC10 AC12 AC14 AC16 AC18 AC20 AC22
B12
B14
B16
B18
B20
B22
D8
D9 A10 D11 D12
VCC0P9_SVR_PAB_ANA
VCC0P9_SVR_PC_ANA
VCC0P9_SVR_DPAUX_ANA
VCC0P9_SVR_USB_ANA
VCC0P9_SVR_BRD_SENSE VCC0P9_PCIE
VCC0P9_ANA_PCIE_1
VCC0P9_ANA_PCIE_2
VCC3P3_ANA VCC3P3_ANA_PCIE VCC3P3_ANA_USB2
VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA
VSS
N15
VSS
L15
VSS
V18
VSS F4
VSS R9
VSS
R12
U2800
TITAN-RIDGE-DP
VSS
L12
CSP
SYM 2 OF 2
OMIT_TABLE
CRITICAL
VCC
VSS
VSS
VSS
VSS
VSS
VSS
L9
M9
M1
M15
R15
VSS M2
VCC3P3_LC
VCC3P3_SX
VCC3P3_S0
VCC3P3A
VCC3P3_SVR
VCC0P9_SVR
SVR_IND
SVR_VSS
VCC0P9_LC
VCC0P9_LVR
VCC0P9_LVR_SENSE
VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA
VSS
VSS
VSS
VSS
VSS
VSS
T6
V16
M12
N9
N12
T18
V6 F18
R6 L6 E6 G1
G2 H2
R8 R11 L11 M8 M13 R16 R13 J13 L13
124 28
N8 N11 N13 T8 T16 M11
L1 L2 K1 K2
J1 J2 H1
J8 H8 H6
D13
D15 D16 D18 E9 E11 E15 A12 E22 E23 F9 F20 F16 G22 G23 A14 H20 J19 J20 J22 A16 J23 L20 L22 L23 A18 M20 N20 N22 N23 R18 A20 R19 R20 R22 R23 T20 U23 U22 A22 V9 V15 V20 W8 B6 W9 W22 W23 Y9 Y13 AA22 AA23 AB6 E4 J15 AB1 AC2 F5 F6 J12
PP3V3_TBT_X_LC PP3V3_TBT_X_SX
C2991
1
2
1
C2975
10UF
20%
2
CERM-X5R 0402-4
PP0V9_TBT_X_SVR
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
DIDT=TRUE SWITCH_NODE=TRUE
VR0V9_IND_TBT_X
PP0V9_TBT_X_LC
PP0V9_TBT_X_LVR
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
Add XW or alias on support page
XW
XW2900
SM
1 2
PLACE_NEAR=U2800.V8:2MM
NO_XNET_CONNECTION=1
PP3V3_TBT_X_F
VOLTAGE=3.3V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
1.0UF
20%
6.3V X5R 0201-1
1
C2976
10UF
20%
26.3V
CERM-X5R 0402-4
1
C2977
10UF
20%
6.3V
26.3V
CERM-X5R 0402-4
CRITICAL
L2950
0.68UH-20%-6.1A-0.020OHM
1 2
1210
SOURCED BY
C2992
1.0UF
20%
6.3V X5R
0201-1
29
TBTTHMSNS_X_D1_N
1
2
C2993
INTERNAL SWITCH
1
1.0UF
20% X5R
2
6.3V
0201-1
C2990
1
C2978
10UF
20%
6.3V
2
CERM-X5R 0402-4
1
2
C2954
10UF
CERM-X5R
0402-4
57
OUT
C2995
1
2
1
C2910
4UF
20%
6.3V
2
CER-X5R 0201
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
1
2
1.0UF
20%
6.3V X5R
0201-1
1
2
C2950
10UF
20% 25V X5R-CERM 0603
1
20%
6.3V
2
C2994
1
47UF
2
20%
CER-X5R
0603
C2917
12PF
5% 25V NP0-C0G 0201
C2951
1
47UF
20%
6.3V
2
CER-X5R 0603
C2955
10UF
20%
6.3V
CERM-X5R
0402-4
2x 10uF outside BGA area
P0V9_TBT_X_SVR_AGND
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0V
BOM_COST_GROUP=TBT
47UF
20%
6.3V
CER-X5R
0603
1
26.3V
1
2
C2952
1
47UF
20%
6.3V
2
CER-X5R 0603
L2990
1 2
1/10W MF-LF
603
C2911
4UF
20%
6.3V CER-X5R 0201
0
5%
1
C2912
4UF
20%
6.3V
2 6.3V
CER-X5R 0201
INTERNAL SWITCHING VR OUTPUT
C2982
1
1.0UF
20%
6.3V
2
X5R 0201-1
33
27 29
FROM USB-C PORT CONTROLLER (UPC)
C2981
1
1.0UF
20%
6.3V
2
X5R 0201-1
PP3V3_S0SW_TBT_X_SNS
1
C2913
4UF
20%
2
CER-X5R 0201
SYNC_MASTER=ANDY SYNC_DATE=01/17/2019
PAGE TITLE
1
C2914
4UF
20%
6.3V
2
CER-X5R 0201
(SEE INTEL LAYOUT GUIDELINES)
C2983
1
1.0UF
20%
6.3V
2
X5R 0201-1
29 118 124
1
C2915
4UF
20%
6.3V
2
CER-X5R 0201
ISOLATE GND OF SVR_IND CAPS
AND GND OF VCC3P3_SVR CAPS
FROM SYSTEM GND IN LAYOUT
C2980
1
1.0UF
20%
6.3V
2
X5R 0201-1
1
2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V
C2916
4UF
20%
6.3V CER-X5R 0201
SOURCED BY INTERNAL SWITCH
USB-C HIGH SPEED 2
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
29 OF 200
SHEET
28 OF 135
D
C
B
A
8
67
35 4
2
1
Page 29
Vinafix.com
678
3 245
1
D
C
B
121 14
121 14
TBT WAKE LEVEL SHIFTER
118
PP3V3_G3H_RTC_X
1
R3003
111
PP1V8_SLPS2R
30 31 80 110
Q3001
1
DMN32D2LFB4
DFN1006H4-3
SYM_VER_2
100K
5% 1/20W MF
2
201
SMC HAS IPU
39
TBT_WAKE_L
DP SRC OPTIONS
S G
2
D
TBT_WAKE_3V3_L
3
27
DP_X_SRC_HPD
R3017
100K
1 2
IF DP SRC NOT USED
=DP_X_SRC_ML_P<3..0>
27
=DP_X_SRC_ML_N<3..0>
27
NC_DP_X_SRC_ML_P<3..0> NC_DP_X_SRC_ML_N<3..0>
MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
Bus <3..0> doesn't resolve properly. but netlist is correct.
NC_DP_X_SRC_AUX_P
27
NC_DP_X_SRC_AUX_N
27
FUSES FOR UPC
NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N
CRITICAL
0603-1
MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
F3000
6A-32V
PPDCIN_G3H
29 109
1 2
PPDCIN_XA_G3H_F
CRITICAL
0603-1
F3001
6A-32V
1 2
PPDCIN_XB_G3H_F
Ridge 25MHz xtal
C3002
20PF
1 2
5% 25V C0G
0201
120 27
TBT_X_XTAL25M_OUT
IN
CRITICAL
Y3000
120 27
OUT
2 4
1 3
TBT_X_XTAL25M_IN
25MHZ-25PPM-20PF-50OHM
2.00X1.60-SM
C3003
20PF
1 2
5% 25V C0G
0201
DEBUG ALIASES
PCH UART (MOJO)
30
PCH_UART_DEBUG_R2D
30
PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D PCH_UART_DEBUG_D2R
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC UART
31
SMC_DEBUGPRT_TX SMC_DEBUGPRT_RX
31
SMC_DEBUGPRT_TX
MAKE_BASE=TRUE
SMC_DEBUGPRT_RX
MAKE_BASE=TRUE
SOC SWD
SWD_SOC_SWCLK
39
MAKE_BASE=TRUE
SWD_SOC_SWDIO
39
MAKE_BASE=TRUE
0
R3036
PLACE_NEAR=U3100.G2:5mm
R3037
PLACE_NEAR=U3100.G2:5mm
1 2
0
1 2
1/20W MF
SWD_SOC_SWCLK
5%0201
UPC_XB_DBG4
SWD_SOC_SWDIO
5%0201
UPC_XB_DBG5
MF1/20W
DCI
BI
BI
USB3_EXTA_D2R_P
MAKE_BASE=TRUE
USB3_EXTA_D2R_N
MAKE_BASE=TRUE
121 15
121 15
121 39
121 39
30 121
31
30 121
31
USB3_EXTA_D2R_P USB3_EXTA_D2R_N
INOUT
5%1/20W MF
201
Ridge and ACE PU/PDs
R3001
1 2
29
UPC_X_5V_EN
34
SPARE_UPC_XA_USB3_RP
30
SPARE_UPC_XA_USB3_RN
30
113 107 33 27
SPARE_UPC_XB_USB2_RP
31
SPARE_UPC_XB_USB2_RN
31
SPARE_UPC_XB_USB3_RP
31
SPARE_UPC_XB_USB3_RN
31
UPC_XA_FAULT_L
30 18
UPC_XB_FAULT_L
31 18
1/20W
1/20W 201
5% 1/20W
1/20W
5% 201MF
5% 1/20W MF
R3026 R3028
1/20W 2015%
MF
MF 2015%
MF5%
MF1/20W
201MF1/20W5%
100K
2011/20W5% MF
R3004
100K
1 2
R3008
100K
1 2
R3009
100K
1 2
2015%
R3014
100K
1 2
201MF
R3018
100K
1 2
R3020
100K
1 2
201
100K
1 2
100K
1 2
30
UPC_XA_GPIO4
123 31
UPC_XB_GPIO1
UPC_XB_GPIO4
31
UPC_XB_GPIO9
31
UPC_XB_GPIO10
31
PP3V3_S5
PP3V3_S5
R3002
5% MF
R3005
1/20W5% MF
R3007
MF
R3012
5% 201MF1/20W
R3016
MF5% 2011/20W
12 29 80
12 29 80
100K
1 2
2011/20W
1 2
100K
201
1 2
100K
2015% 1/20W
1 2
100K
1 2
100K
PP1V8_AWAKE
77 80
30
I2C_UPC_X_SDA2
31
I2C_UPC_X_SDA2
33
I2C_UPC_X_SDA2
I2C_UPC_X_SCL2
30
I2C_UPC_X_SCL2
31
I2C_UPC_X_SCL2
33
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R3006
MF 02015% 1/20W
0
1 2
I2C SERIES R'S
PLACE_NEAR=U3900.J4:5mm
R3021
1/20W MF 201
5%
R3025
MF1/20W5% 201
33
1 2
33
1 2
I2C_UPC_SDA
I2C_UPC_SDA
PLACE_NEAR=U3900.M3:10mm
I2C_UPC_SCL
I2C_UPC_SCL
SOC_USB_VBUS
121 38
51
51
51
51
SIGNAL ALIASES
UPC_X_5V_EN
30 29
123 31 29
RIDGE 0.9V SVR XW
XW3000
SM
P0V9_TBT_X_SVR_AGND
28
NO_XNET_CONNECTION=1
1 2
30
UPC_X_5V_EN
31
30
UPC_PMU_RESET UPC_PMU_RESET
31
UPC_X_5V_EN
MAKE_BASE=TRUE
UPC_PMU_RESET
MAKE_BASE=TRUE
34 29
121 109 77 67
Portable: rear connector->TBT ROM
Desktop: XA_SPI -> TBT ROM
front connector->GND
XB_SPI -> GND
FLASH ROM
TBT_X_SPI_CLK
27
TBT_X_SPI_CS_L
27
TBT_X_SPI_MOSI
27
TBT_X_SPI_MISO
27
TBT SPI ROM
Ace
R3011 R3013 R3015 R3019
R3022 R3023 R3024 R3027
R3029
USBC_DBG
R3030
USBC_DBG
R3031
USBC_DBG
R3032
USBC_DBG
R3033
USBC_DBG
1 2
15
1 2
15
1 2
15
1 2
15
1 2
15
1 2
15
1 2
15
1 2
100
1 2
15
1 2
15
1 2
15
1 2
15
1 2
UPC_XB_SPI_CLK UPC_XB_SPI_CS_L UPC_XB_SPI_MOSI UPC_XB_SPI_MISO
MF
MF
201MF5%151/20W
201MF5% 1/20W
2011/20W5%
2011/20W5%
Titan Ridge
UPC_X_SPI_CLK UPC_X_SPI_CS_L
1/20W5% 201MF
UPC_X_SPI_MOSI
1/20W 201MF5%
UPC_X_SPI_MISO
1/20W5%
MF5% 2011/20W
MF 201
ACE ARKANOID
TBT_X_SPI_ARK_CLK
5%
1/20W MF 201
AARDVARKANOID
TBT_X_SPI_DBG_CLK
5% 1/20W 201MF
TBT_X_SPI_DBG_CS_L
5% 1/20W MF 201
TBT_X_SPI_DBG_MOSI
5% MF 2011/20W
TBT_X_SPI_DBG_MISO
5% 1/20W MF 201
33
IN
IN
IN
OUT
IN
IN
IN
OUT
IN
IN
IN
OUT
31
31
31
31
27
27
27
27
33
33
33
33
D
POWER ALIASES
PP3V3_UPC_XB_LDO
27
PP3V3_UPC_XB_LDO
MAKE_BASE=TRUE
33 31 29
SIGNAL ALIASES
C
32
PPVBUS_USBC_XA
PPVBUS_USBC_XA
PPVBUS_USBC_XB
32
PPVBUS_USBC_XB
PPVBUS_USBC_XA
MAKE_BASE=TRUE
VOLTAGE=20V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PPVBUS_USBC_XB
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=20V
USBC_X_RESET_L
124 122 30 29
31
TP_USBC_XA_RESET_L
124 123 122 31 29
USBC_X_RESET_L
MAKE_BASE=TRUE
TP_USBC_XA_RESET_L
MAKE_BASE=TRUE
33 27
123 30
TBT to ACE
TBT_POC_RESET
PPVBUS_USBC_XA PPDCIN_XA_G3H_F PPVBUS_USBC_XB
31
PPDCIN_XB_G3H_F
31
PPDCIN_G3H
29 109
30
PP5V_S4_X_USBC PP5V_S4_X_USBC
31
PP5V_S4_X_USBC
34 124
28 118 124
PP3V3_S0SW_TBT_X_SNS
30
PP3V3_TBT_X_SX PP3V3_TBT_X_SX
31
27 28
PP3V3_TBT_X_SX
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=20V
VOLTAGE=5V
VOLTAGE=3.3V
PPVBUS_USBC_XA
PPDCIN_XA_G3H_F
PPVBUS_USBC_XB
PPDCIN_XB_G3H_F
PPDCIN_G3H
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
MAKE_BASE=TRUE
PP5V_S4_X_USBC
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200
PP3V3_S0SW_TBT_X_SNS
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PP3V3_TBT_X_SX
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
124 122 30 29
30 29
124 123 122 31 29
123 31 29
TBT_X_HDMI_DDC_DATA
124 121 68 53
27
TBT_X_HDMI_DDC_DATA
33
27
TBT_X_HDMI_DDC_CLK
TBT_X_HDMI_DDC_CLK
SOC_DFU_STATUS
MAKE_BASE=TRUE
SOC_FORCE_DFU
MAKE_BASE=TRUE
TBT_X_HDMI_DDC_DATA
MAKE_BASE=TRUE
SOC_DFU_STATUS
SOC_FORCE_DFU
Mobile Config
31
79 33 27
PP3V3_UPC_XB_LDO PP3V3_UPC_XA_LDO
30
PP3V3_UPC_XB_LDO PP3V3_UPC_XA_LDO
CC Aliases for X side
31
USBC_XB_CC1 USBC_XB_CC2
31
30
USBC_XA_CC1 USBC_XA_CC2
30
31
31
GND ALIASES
USBC_XB_CC1
MAKE_BASE=TRUE
USBC_XB_CC2
MAKE_BASE=TRUE
USBC_XA_CC1
MAKE_BASE=TRUE
USBC_XA_CC2
MAKE_BASE=TRUE
TBT_POC_RESET
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
122 32 31
122 32 31
122 32 30
122 32 30
33 31 29
33 30
113
109 15 33 31 30
TBT
Titan Ridge U2800
(MASTER)
I2C_TBT_X_SCL
33 27
I2C_TBT_X_SDA
33 27
I2C_TBT_XA_INT_L
33 27
I2C_TBT_XB_INT_L
33 27
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
(Write: 0x70 Read: 0x71)
I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XA_INT_L
Pri ACE
U3100
30
30
30
OUTIN
122 98
Sec ACE
U3200
(Write: 0x7E Read: 0x7F)
122 98
135 121 38 30
135 121 77 38 30
I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XB_INT_L
31
31
31
B
A
14
14
C3004
10%
BI
USB3_EXTA_R2D_C_P
0201 X5R-CERM
1 2
C3005
BI
USB3_EXTA_R2D_C_N
0201
DBG MUX PDs
30
UPC_XA_DBG_PD
30
UPC_XA_DBG_PD UPC_XA_DBG_PD
30
UPC_XA_DBG_PD
30
1 2
X5R-CERM
16V
USB3_EXTA_R2D_P
0.1UF
16V10%
USB3_EXTA_R2D_N
0.1UF
UPC_XA_DBG_PD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R3038
1/20W 201
MF5%
USB3_EXTA_R2D_P
USB3_EXTA_R2D_N
100K
1 2
31
GND
30
GND
30
31
30
30
30
31
GND GND
GND GND
NC_UPC_XA_VDDIO_CFG NC_UPC_XB_VDDIO_CFG
GND
GND GND GND
GND
31
GND
31
GND
31
GND
31
30
GND
MAKE_BASE=TRUE
NC for X side
NC_UPC_XA_VDDIO_CFG NC_UPC_XB_VDDIO_CFG
MAKE_BASE=TRUE MAKE_BASE=TRUE
BOM_COST_GROUP=TBT
SYNC_MASTER=YANIR SYNC_DATE=01/17/2019
PAGE TITLE
USB-C X Support
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
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30 OF 200
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8
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X PRIMARY ACE USB-C PORT CONTROLLER (UPC)
3 245
1
D
C
124 122 30 29
TP must be present on GPIO0 or be accessible on connector even in production
PPVBUS_USBC_XA
ACE LDO CAN DRAW UP TO
5.9 MA WHILE PROGRAMMING OTP
MAX 100uF TOTAL ON RAIL
30 29
PP5V_S4_X_USBC
29
PPDCIN_XA_G3H_F
BUSPOWER needs to connect to GND on Desktop and LDO_3V3 on Mobile.
MRESET HIGH FORCES B17 RESET LOW
ACTIVE LOW RESET OUTPUT
USE GPIO8 FOR PMU RESET AFTER BOOT
I2C_ADDR CONTROLS ADDR BITS 3,2,1 GND I2C_ADDR ON PRIMARY ONLY
R_OSC NEEDS NEEDS 0.1% RES
I2C BUS 1 IS TBT / ACES
I2C BUS 2 IS SMC / ACES
Portable: rear connector->TBT ROM
Desktop: XA_SPI -> TBT ROM
front connector->GND
XB_SPI -> GND
R3103
15K
0.1% 1/20W TF-LF
0201
TO SMC
1
C3198
1.0UF
10% 25V
2
X6S 0402
29
33 31 29
123 33
135 121 77 38
33 31 27 14
29
29 18
33 31 27 14
121 39 31
29
135 121 38 29
135 121 77 38 29
29
1
29
2
29
29
29
29
51
29
29
29
29
1
2
IN IN
123 29
OUT
IN IN
OUT
29
OUT
IN OUT OUT
IN OUT
IN
29
30
30
BI BI OUT
BI BI OUT
IN
IN OUT
IN
C3199
1UF
10% 35V X5R 0402
1
C3101
1UF
10% 35V
2
X5R 0402
K
D3100
DSN2
NSR20F40NX_G
A
GND TBT_POC_RESET TP_USBC_XA_RESET_L
UPC_XA_SER_DBG PMU_ACTIVE_READY
TBT_X_CIO_PWR_EN UPC_X_5V_EN UPC_XA_GPIO4 UPC_XA_FAULT_L TBT_X_USB_PWR_EN SOC_DOCK_CONNECT UPC_PMU_RESET SOC_DFU_STATUS SOC_FORCE_DFU
PP3V3_UPC_XA_LDO GND
UPC_XA_R_OSC I2C_UPC_XA_DBG_CTL_SDA
I2C_UPC_XA_DBG_CTL_SCL I2C_TBT_X_SDA
I2C_TBT_X_SCL I2C_TBT_XA_INT_L
I2C_UPC_X_SDA2 I2C_UPC_X_SCL2
UPC_I2C_INT_L
GND GND GND GND
B13 A14 B17
A2 B1
D1
F1 C2 E2 B3 C4 D3 E4
F3
F7
A18
M19 M21
A16 B15
B5 A4 D7
B7 A6 C8
B9
B11 A10
A8
K9
L10M9N10
HRESET MRESET RESET*
GPIO0
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10
BUSPOWER I2C_ADDR
R_OSC I2CM_SDA_CNFG
I2CM_SCL_CNFG I2C_SDA1
I2C_SCL1 I2C_IRQ1*
I2C_SDA2 I2C_SCL2 I2C_IRQ2*
SPI_CLK SPI_MOSI SPI_MISO SPI_SSZ
K11
L12
M11
N12
N14
M13G2G4H1H3J2J4K1K3L2L4M1M3N2N4
PP_5V0
PP_CABLE
PP_HV
U3100
CD3217B12BCE
FCBGA
CRITICAL
OMIT_TABLE
DIGITAL CORE I/O & CONTROL POWER
TYPE-C
G6G8H5H7J6J8K5K7L6L8M5M7N6
VBUS
N8
VIN_3V3
VDDIO
VDDIO_CFG
LDO_3V3
VIN_LV
VOUT_LV
VRET
SS
LDO_CORE
VBUS_OPT
PP_HV_OPT
C_CC1
C_CC2
RPD_G1 RPD_G2
C_USB_TP C_USB_TN
C_USB_BP
C_USB_BN
C_SBU1 C_SBU2
C20 A12
D11 C22
D21 L20
L18 C16 L22
E22 D5 F5
M15 N16
M17 N18
L14 L16
K19 K21
J20 J22
J16 H15
NC_UPC_XA_VDDIO_CFG
NO_TEST=1
PP3V3_TBT_X_SX
UPC_XA_SS
SOFT START RAMP RATE = 9 * ISS / CSS ISS = 7 UA NOMIAL, 5.5 MA MIN, 8.5 MA MAX
PP1V5_UPC_XA_LDO_CORE
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PPVBUS_USBC_XA
PPDCIN_XA_G3H_F
USBC_XA_CC1
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200
USBC_XA_CC2
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200
USBC_XA_CC1 USBC_XA_CC2
USBC_XA_USB_TOP_P USBC_XA_USB_TOP_N
USBC_XA_USB_BOT_P USBC_XA_USB_BOT_N
USBC_XA_SBU1 USBC_XA_SBU2
1
C3100
10UF
20%
6.3V
2
CERM-X5R 0402-1
29
VOUT_3V3 FOR RIDGE
29
BI BI
BI BI
BI BI
BI BI
29 30 122 124 29 30
29
29
C3104
1
10UF
20%
2
6.3V CER-X6S 0402
122 32
122 32
122 32
122 32
122 32
122 32
1
C3114
220PF
10% 25V
2
X7R-CERM 201
1
C3108
10UF
20%
6.3V
2
CERM-X5R 0402-1
1
C3109
0.68UF
10%
6.3V
2
CERM 402
1
C3113
220PF
10% 25V
2
X7R-CERM 201
D
PP3V3_G3H_RTC_X
PP1V8_SLPS2R
1V8 SOURCE FOR ACE 1V8 GPIO
PP3V3_UPC_XA_LDO
VOLTAGE=3.3V
1
C3107
1.0UF
20%
6.3V
2
X5R 0201-1
118
29 31 80 110 111
33 30 29
C
BI
BI
122 32 29
122 32 29
PORT SIDE USB TOP PAIR
PORT SIDE USB BOTTOM PAIR
PORT SIDE USB SIDEBAND
B
120 14
120 14
33
BI
33
IN
PLACE_NEAR=U3100.H19:5mm
BI
BI
USB_UPC_PCH_XA_P
USB_UPC_PCH_XA_N
R3100 R3101
PLACE_NEAR=U3100.H21:5mm
0
1 2
5%0201 MF1/20W
1 2
5% MF020101/20W
33 31 30
33 31
121 38
121 38
29
29
120 27
120 27
120 27
29
29
29
29
121 29
121 29
29
29
IN
OUT
BI BI BI BI
BI BI
OUT
BI BI BI BI OUT
OUT OUT OUT
UPC_XA_SWD_DATA UPC_XA_SWD_CLK
UPC_XA_UART_RX UPC_XA_UART_TX
USB_UPC_PCH_XA_F_P
120
USB_UPC_PCH_XA_F_N
120
USB_SOC_P USB_SOC_N SPARE_UPC_XA_USB3_RP SPARE_UPC_XA_USB3_RN
USBC_XA_AUXLSX1 USBC_XA_AUXLSX2
DP_XA_HPD UPC_XA_DBG_PD
UPC_XA_DBG_PD
UPC_XA_DBG_PD UPC_XA_DBG_PD SWD_SOC_SWCLK SWD_SOC_SWDIO PCH_UART_DEBUG_R2D PCH_UART_DEBUG_D2R
E20 E16
B19 A20
H19 H21 G20 G22
F19 F21
J12
H11 C12 G12
F11
E8
E12 G16
F15 D15 D19
SWD_DATA SWD_CLK
UART_RX UART_TX
USB_RP1_P USB_RP1_N USB_RP2_P USB_RP2_N USB_RP3_P USB_RP3_N
AUX_P AUX_N
HPD DEBUG0
DEBUG1 DEBUG2 DEBUG3 DEBUG4 DEBUG5 DEBUG6 DEBUG7
PULL R3109 AND R3108 UP TO ACES LDO FOR 1ST RIDGE'S ACES PULL THEM DOWN TO GND FOR 2ND RIDGE'S ACES
GND_OPT GND_OPT GND_OPT
GNDPORT_MUX
GND
GND_OPT
C18 E18 D17 G18
PP3V3_UPC_XA_LDO
1M
1 2
1M
1 2
1M
1 2
R3109
5%
R3108
1/20W 201MF5%
R3105
33 30 29
I2C_UPC_XA_DBG_CTL_SCL
201MF1/20W
I2C_UPC_XA_DBG_CTL_SDA
UPC_XA_UART_RX
MF1/20W 2015%
30
30
33 31 30
B
A
8
H9
A22
N20
B21
K15
N22
PAGE TITLE
SYNC_DATE=01/17/2019SYNC_MASTER=YANIR
A
USB-C PORT CONTROLLER XA
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
BOM_COST_GROUP=USB-C
67
35 4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
31 OF 200
SHEET
30 OF 135
1
SIZE
D
Page 31
Vinafix.com
678
X SECONDARY ACE USB-C PORT CONTROLLER (UPC)
3 245
1
D
C
124 123 122 29
123 29
29
PPVBUS_USBC_XB
ACE LDO CAN DRAW UP TO
5.9 MA WHILE PROGRAMMING OTP
MAX 100uF TOTAL ON RAIL
PPDCIN_XB_G3H_F
PP5V_S4_X_USBC
MRESET HIGH FORCES B17 RESET LOW ACTIVE LOW RESET OUTPUT
TP must be present on GPIO0 or be accesible even in production
BUSPOWER pulled down on Desktop and Pulled up on Mobile
I2C_ADDR CONTROLS ADDR BITS 3,2,1 GND I2C_ADDR ON PRIMARY ONLY
R_OSC NEEDS NEEDS 0.1% RES
I2C BUS 1 IS TBT / ACES
I2C BUS 2 IS SMC / ACES
Portable: rear connector->TBT ROM
Desktop: XA_SPI -> TBT ROM
front connector->GND
XB_SPI -> GND
R3203
15K
0.1% 1/20W TF-LF
0201
TO SMC
1
C3298
1.0UF
10% 25V
2
X6S 0402
33 30 29
123 33
33 30 27 14
33 30 27 14
121 39 30
1
2
29
29
29
29 18
29
29
29
29
29
29
29
51
29
29
29
29
IN IN
OUT
OUT
123 29
IN
OUT
29
OUT
IN OUT OUT
29
29
IN
31
31
BI BI OUT
BI BI OUT
IN IN
OUT
IN
1
C3299
1UF
10% 35V X5R
2
0402
1
C3201
1UF
10% 35V
2
X5R 0402
K
A
GND TBT_POC_RESET
USBC_X_RESET_L
UPC_XB_SER_DBG UPC_XB_GPIO1
TBT_X_CIO_PWR_EN UPC_X_5V_EN UPC_XB_GPIO4 UPC_XB_FAULT_L TBT_X_USB_PWR_EN
SOC_DOCK_CONNECT
UPC_PMU_RESET UPC_XB_GPIO9 UPC_XB_GPIO10
PP3V3_UPC_XB_LDO
UPC_XB_R_OSC I2C_UPC_XB_DBG_CTL_SDA
I2C_UPC_XB_DBG_CTL_SCL I2C_TBT_X_SDA
I2C_TBT_X_SCL I2C_TBT_XB_INT_L
I2C_UPC_X_SDA2 I2C_UPC_X_SCL2
UPC_I2C_INT_L
UPC_XB_SPI_CLK UPC_XB_SPI_MOSI UPC_XB_SPI_MISO UPC_XB_SPI_CS_L
D3200
DSN2
NSR20F40NX_G
NC
B13 A14 B17
A18
M19 M21
A16 B15
B11 A10
HRESET MRESET RESET*
A2 B1
D1
GPIO1
F1
GPIO2
C2
GPIO3
E2
GPIO4
B3
GPIO5
C4
GPIO6
D3
GPIO7
E4
GPIO8
F3
GPIO9
F7
GPIO10 BUSPOWER I2C_ADDR
R_OSC I2CM_SDA_CNFG
I2CM_SCL_CNFG
B5
I2C_SDA1
A4
I2C_SCL1
D7
I2C_IRQ1*
B7
I2C_SDA2
A6
I2C_SCL2
C8
I2C_IRQ2*
B9
SPI_CLK SPI_MOSI SPI_MISO
A8
SPI_SSZ
K9
GPIO0
L10M9N10
K11
L12
M11
N12
N14
M13G2G4H1H3J2J4K1K3L2L4M1M3N2N4
PP_5V0
PP_CABLE
PP_HV
U3200
CD3217B12BCE
FCBGA
CRITICAL
OMIT_TABLE
DIGITAL CORE I/O & CONTROL POWER
TYPE-C
G6G8H5H7J6J8K5K7L6L8M5M7N6
VBUS
N8
VIN_3V3
VDDIO
VDDIO_CFG
LDO_3V3
VIN_LV
VOUT_LV
VRET
SS
LDO_CORE
VBUS_OPT
PP_HV_OPT
C_CC1
C_CC2
RPD_G1 RPD_G2
C_USB_TP C_USB_TN
C_USB_BP
C_USB_BN
C_SBU1 C_SBU2
C20 A12
D11 C22
D21 L20
L18 C16 L22
E22 D5 F5
M15 N16
M17 N18
L14 L16
K19 K21
J20 J22
J16 H15
PP3V3_G3H_RTC_X
PP1V8_SLPS2R NC_UPC_XB_VDDIO_CFG
PP3V3_UPC_XB_LDO
PP3V3_TBT_X_SX
UPC_XB_SS
SOFT START RAMP RATE = 9 * ISS / CSS ISS = 7 UA NOMIAL, 5.5 MA MIN, 8.5 MA MAX
PP1V5_UPC_XB_LDO_CORE
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PPVBUS_USBC_XB PPDCIN_XB_G3H_F
USBC_XB_CC1
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200
USBC_XB_CC2
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200
USBC_XB_CC1 USBC_XB_CC2
USBC_XB_USB_TOP_P USBC_XB_USB_TOP_N
USBC_XB_USB_BOT_P USBC_XB_USB_BOT_N
USBC_XB_SBU1 USBC_XB_SBU2
NO_TEST=1
29
29
1
C3200
10UF
20%
6.3V
2
CERM-X5R 0402-1
29
1
2
118
VOUT_3V3 FOR RIDGE
29
C3204
10UF
20%
6.3V CER-X6S 0402
29
BI
29
BI
32
BI
32
BI
32
BI
32
BI
BI BI
122 32
122 32
1
2
1
2
C3209
0.68UF
10%
6.3V CERM 402
C3214
220PF
10% 25V X7R-CERM 201
1
C3208
10UF
20%
6.3V
2
CERM-X5R 0402-1
1
C3213
220PF
10% 25V
2
X7R-CERM 201
D
1V8 SOURCE FOR ACE 1V8 GPIO
VOLTAGE=3.3V
1
C3207
1.0UF
20%
6.3V
2
X5R 0201-1
BI
BI
122 32 29
122 32 29
PORT SIDE USB TOP PAIR
PORT SIDE USB BOTTOM PAIR
PORT SIDE USB SIDEBAND
29 30 80 110 111
33 31 29
C
B
120 14
120 14
33
33
PLACE_NEAR=U3200.H19:5mm
BI
BI
USB_UPC_PCH_XB_P
USB_UPC_PCH_XB_N
R3200 R3201
PLACE_NEAR=U3200.H21:5mm
0
1 2
0201 5%
0
1 2
1/20W MF
MF1/20W0201 5%
33 31 30
33 30
29
29
29
29
120 27
120 27
120 27
29
29
29
29
29
29
29
29
UPC_XB_SWD_DATA
BI
UPC_XB_SWD_CLK
IN
UPC_XA_UART_TX
IN
UPC_XA_UART_RX
OUT
USB_UPC_XB_F_P
120
USB_UPC_XB_F_N
120
SPARE_UPC_XB_USB2_RP
BI
SPARE_UPC_XB_USB2_RN
BI
SPARE_UPC_XB_USB3_RP
BI
SPARE_UPC_XB_USB3_RN
BI
USBC_XB_AUXLSX1
BI
USBC_XB_AUXLSX2
BI
DP_XB_HPD
OUT
USB3_EXTA_D2R_P
BI
USB3_EXTA_D2R_N
BI
USB3_EXTA_R2D_P
BI
USB3_EXTA_R2D_N
BI
UPC_XB_DBG4
BI
UPC_XB_DBG5
BI
SMC_DEBUGPRT_TX
BI
SMC_DEBUGPRT_RX
BI
E20 E16
B19 A20
H19 H21 G20 G22
F19 F21
J12
H11 C12 G12
F11
E8
E12
G16
F15 D15 D19
SWD_DATA SWD_CLK
UART_RX UART_TX
USB_RP1_P USB_RP1_N USB_RP2_P USB_RP2_N USB_RP3_P USB_RP3_N
AUX_P AUX_N
HPD DEBUG0
DEBUG1 DEBUG2 DEBUG3 DEBUG4 DEBUG5 DEBUG6 DEBUG7
PULL I2C BUS UP TO ACES LDO FOR 1ST RIDGE'S ACES PULL THEM DOWN TO GND FOR 2ND RIDGE'S ACES
GND_OPT GND_OPT GND_OPT
GNDPORT_MUX
GND
GND_OPT
C18 E18 D17 G18
GND GND GND GND
29
29
29
29
PP3V3_UPC_XB_LDO
1M
1 2
1M
1 2
1M
1 2
R3209 R3208
R3205
33 31 29
I2C_UPC_XB_DBG_CTL_SCL
MF1/20W5% 201
I2C_UPC_XB_DBG_CTL_SDA
2011/20W5% MF
UPC_XA_UART_TX
201MF1/20W5%
31
31
33 31 30
B
A
8
H9
A22
N20
B21
K15
N22
PAGE TITLE
YANIR
SYNC_DATE=01/17/2019
A
USB-C PORT CONTROLLER XB
SIZE
D
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=USB-C
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
32 OF 200
SHEET
31 OF 135
1
Page 32
Vinafix.com
29
PPVBUS_USBC_XB
678
K
1610-COMBO
ESDA25P35-1U1M-COMBO
D3302
A
3 245
PLACE VBUS CAP NEAR EACH VBUS PIN
BYPASS=J3300.58::10MM
CRITICAL
1
C3350
0.01UF
10% 25V
2
X5R-CERM 0201
BYPASS=J3300.58::10MM
CRITICAL
1
C3352
0.01UF
10% 25V
2
X5R-CERM 0201
BYPASS=J3300.58::10MM
CRITICAL
1
C3353
0.01UF
10% 25V
2
X5R-CERM 0201
BYPASS=J3300.58::12MM
CRITICAL
1
C3362
0.01UF
10% 25V
2
X5R-CERM 0201
1
PLACE_NEAR=J3300.58:7mm
D3303
TVS2200
WSON
4
IN
5
IN
6
IN
GND
GND
GND
1
2
3
EPAD
7
D
C
B
CC1
TBT_R2D0
TBT_D2R0
SBU2 USB2 BOT
USB2 BOT
SBU1
TBT_R2D1
TBT_D2R1
CC2
122 31 29
120 27
120 27
120 27
120 27
122 31
31
31
122 30
122 30
120 27
120 27
120 27
120 27
122 30 29
29 32
BI
IN
IN
OUT
OUT
BI BI BI
BI BI BI
IN
IN
OUT
OUT BI
D3374
USBC_XB_CC1
USBC_XB_R2D_CR_N<1>
USBC_XB_R2D_CR_P<1>
USBC_XB_D2R_N<1>
USBC_XB_D2R_P<1> USBC_XB_SBU2
USBC_XB_USB_BOT_N USBC_XB_USB_BOT_P
2
GND_VOID=TRUE
D3386
1
SESDL2011
DSN2-THICKSTNCL
USBC_XA_USB_BOT_N USBC_XA_USB_BOT_P
USBC_XA_SBU1
USBC_XA_R2D_CR_P<2>
USBC_XA_R2D_CR_N<2>
USBC_XA_D2R_P<2>
USBC_XA_D2R_N<2>
USBC_XA_CC2
2
GND_VOID=TRUE
2
GND_VOID=TRUE
D3375
1
SESDL2011
DSN2-THICKSTNCL
PPVBUS_USBC_XA
1
SESDL2011
DSN2-THICKSTNCL
2
GND_VOID=TRUE
D3371
1
2
GND_VOID=TRUE
D3376
1
R3371
R3370 R3352
R3353
2
D3372
SESDL2011
DSN2-THICKSTNCL
1
2
GND_VOID=TRUE
SESDL2011
DSN2-THICKSTNCL
GND_VOID=TRUE
2
D3373
1
R3373
GND_VOID=TRUE
1 2
5% 1/20W MF 201
R3372
GND_VOID=TRUE
1 2
5% 2011/20W
R3326
GND_VOID=TRUE
1 2
5% 201
1/20W MF
GND_VOID=TRUE
1 2
D3377
SESDL2011
DSN2-THICKSTNCL
K
1
1610-COMBO
SESDL2011
DSN2-THICKSTNCL
ESDA25P35-1U1M-COMBO
D3301
A
1 2
GND_VOID=TRUE
1 2
GND_VOID=TRUE
1 2
GND_VOID=TRUE
1 2
GND_VOID=TRUE
GND_VOID=TRUE
SESDL2011
DSN2-THICKSTNCL
MF
2
1/20W MF 201
5%
2
5% MF 201
1/20W
120 120
2
1/20W MF5%
120
2
1/20W MF5%
120
2
2
USBC_XA_R2D_C_P<2>
120
USBC_XA_R2D_C_N<2>
2
R3327
MF22015% 1/20W
2
DZ3301
PLACE_NEAR=J3300.59:5mm
1
5.5V-6.2PF
0201-THICKSTNCL
D3305
TVS2200
WSON
IN IN IN
GND
GND
EPAD
7
3
GND
1
2
USBC_XB_R2D_C_N<1>
USBC_XB_R2D_C_P<1>
USBC_XB_D2R_R_N<1>
201
USBC_XB_D2R_R_P<1>
201
D3354
ESD8011
X3DFN2-THICKSTNCL
GND_VOID=TRUE
2
1
GND_VOID=TRUE
2
1
USBC_XA_D2R_R_P<2>
USBC_XA_D2R_R_N<2>
GND_VOID=TRUE
2
2
D3312
X3DFN2-THICKSTNCL
ESD8011
4 5 6
1
1
C3381
C3380
D3349
ESD8011
X3DFN2-THICKSTNCL
C3383
1 2
GND_VOID=TRUE
C3382
1 2
GND_VOID=TRUE
GND_VOID=TRUE
D3328
X3DFN2-THICKSTNCL
ESD8011
C3391
C3390
1 2
GND_VOID=TRUE
1 2
GND_VOID=TRUE
2
0.33UF
0.33UF
10%
201MF5% 1/20W
R3351
1
DZ3350
5.5V-6.2PF
0201-THICKSTNCL
1 2
GND_VOID=TRUE
1 2
GND_VOID=TRUE
220K
C3373
C3372
10% X5R 020125V
0.33UF
0.33UF
10%
2
1
5.5V-6.2PF
DZ3303
0201-THICKSTNCL
MF 201
2
2
GND_VOID=TRUE
R3325
1
1
1/20W5% 201MF
220K
BYPASS=J3300.59::10MM
CRITICAL
1
C3301
0.01UF
10% 25V
2
X5R-CERM 0201
1 2
GND_VOID=TRUE
1 2
GND_VOID=TRUE
GND_VOID=TRUE
2
2
1
1
0.22UF
0.22UF
0.22UF
X5R10%
0.22UF
25V X5R10%
MF
220K
5%
020125V10%
020125V
2
GND_VOID=TRUE
MF5% 201
R3349
1
1/20W
220K
CER-X5R
CER-X5R
201
GND_VOID=TRUE
R3350
1/20W
120
USBC_XA_R2D_P<2>
X5R25V10% 0201
120
USBC_XA_R2D_N<2>
USBC_XA_D2R_CR_P<2>
0201CER-X5R25V10%
USBC_XA_D2R_CR_N<2>
0201CER-X5R25V
201
201
GND_VOID=TRUE
R3324
220K
5% 1/20W
220K
GND_VOID=TRUE
GND_VOID=TRUE
2
2
R3329
1
1
1/20W MF5%
R3328
220K
5% 1/20W MF
BYPASS=J3300.59::10MM
PLACE VBUS CAP NEAR EACH VBUS PIN
CRITICAL
1
C3302
0.01UF
10% 25V
2
X5R-CERM 0201
CRITICAL
1
C3308
0.01UF
10% 25V
2
X5R-CERM 0201
BYPASS=J3300.59::10MM
BYPASS=J3300.59::10MM
USBC_XB_R2D_N<1>
020125V
USBC_XB_R2D_P<1>
0201
USBC_XB_D2R_CR_N<1>
120
USBC_XB_D2R_CR_P<1>
201
2
GND_VOID=TRUE
MF
2
DZ3352
R3348
1
1/20W
BYPASS=J3300.59::10MM
1
2
1
2
5.5V-6.2PF
220K
0201-THICKSTNCL
5%
1
BYPASS=J3300.59::10MM
CRITICAL
C3303
0.01UF
10% 25V X5R-CERM 0201
CRITICAL
C3309
0.01UF
10% 25V X5R-CERM 0201
BYPASS=J3300.59::10MM
CRITICAL
1
C3312
0.01UF
10% 25V
2
X5R-CERM 0201
CRITICAL
1
C3305
0.01UF
10% 25V
2
X5R-CERM 0201
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
J3300
20875-056E-01
F-ST-SM
PWR
57 58
SIGNAL
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
PWR
59 60
GND
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
TP_USBC_PP20V_XB
120
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
USBC_XA_D2R_CR_N<1>
TP_USBC_PP20V_XA
122
120
USBC_XB_R2D_N<2>
USBC_XB_R2D_P<2>
USBC_XA_R2D_P<1> USBC_XA_R2D_N<1>
122
GND_VOID=TRUE
2
2
1
1
5% MF1/20W 201
GND_VOID=TRUE
220K
R3319
BYPASS=J3300.58::10MM BYPASS=J3300.58::10MM BYPASS=J3300.58::10MM
C3392 C3393
USBC_XB_D2R_CR_N<2> USBC_XB_D2R_CR_P<2>
201
GND_VOID=TRUE
201MF
2
220K
1
1/20W5%
MF
220K
1/20W5% 201
R3318
GND_VOID=TRUE
2
R3354
1
C3370
C3371
2011/20W MF
220K
R3321
5%
201 MF1/20W5%
220K
R3358
5% 1/20W MF
220K
GND_VOID=TRUE
1 2
GND_VOID=TRUE
1 2
C3384
C3385
GND_VOID=TRUE
GND_VOID=TRUE
2
2
MF 201
1
1
1/20W5%
GND_VOID=TRUE
GND_VOID=TRUE
2
2
R3356
1
1
10% 0201X5R
GND_VOID=TRUE
1 2
GND_VOID=TRUE
1 2
220K
R3320
CRITICAL
1
C3356
0.01UF
10% 25V
2
X5R-CERM 0201
GND_VOID=TRUE
1 2
GND_VOID=TRUE
1 2
10% 25V 0201X5R
C3386 C3387
201
R3355
DZ3353
5.5V-6.2PF
0201-THICKSTNCL
5% 1/20W MF
220K
0.22UF
25V
X5R10% 0201
0.22UF
25V
0.33UF
020110% CER-X5R25V
0.33UF
CER-X5R
020110%25V
DZ3300
PPVBUS_USBC_XA
CRITICAL
1
C3357
0.01UF
10% 25V
2
X5R-CERM 0201
0.22UF
25V
0.22UF
GND_VOID=TRUE
1 2
1 2
GND_VOID=TRUE
2
1
120
120
5.5V-6.2PF
0201-THICKSTNCL
0.33UF
0.33UF
CER-X5R 020125V 10%
USBC_XA_R2D_C_P<1>
USBC_XA_R2D_C_N<1>
USBC_XA_D2R_R_P<1>USBC_XA_D2R_CR_P<1>
USBC_XA_D2R_R_N<1>
2
1
CRITICAL
1
C3358
0.01UF
10% 25V
2
X5R-CERM 0201
120
USBC_XB_R2D_C_N<2>
0201X5R10%
120
USBC_XB_R2D_C_P<2>
020110% CER-X5R25V
ESD8011
D3358
GND_VOID=TRUE
2
ESD8011
D3304
X3DFN2-THICKSTNCL
1
29 32
USBC_XB_D2R_R_N<2> USBC_XB_D2R_R_P<2>
GND_VOID=TRUE
2
X3DFN2-THICKSTNCL
1
GND_VOID=TRUE
2
D3329
1
GND_VOID=TRUE
2
ESD8011
D3360
1
R3374
1/20W 201
R3375
1/20W
X3DFN2-THICKSTNCL
GND_VOID=TRUE
1 2
GND_VOID=TRUE
1 2
R3323
R3322
2
ESD8011
X3DFN2-THICKSTNCL
DZ3302
5.5V-6.2PF
1
0201-THICKSTNCL
GND_VOID=TRUE
R3376
R3377
2
1
5%1/20W MF2201
1 2
1/20W MF
5% 201
GND_VOID=TRUE
1 2
1/20W MF5% 201
R3359
1/20W MF2201
R3357
1/20W 5% MF2201
DZ3351
5.5V-6.2PF
0201-THICKSTNCL
2
MF5%
2
2015% MF
GND_VOID=TRUE
1 2
GND_VOID=TRUE
1 2
GND_VOID=TRUE
1 2
5%
GND_VOID=TRUE
1 2
2
MF1/20W 5%
201
2
2
2
GND_VOID=TRUE
D3382
1
2
GND_VOID=TRUE
D3378
1
USBC_XB_CC2 USBC_XB_R2D_CR_N<2>
USBC_XB_R2D_CR_P<2>
USBC_XB_USB_TOP_P USBC_XB_USB_TOP_N USBC_XB_D2R_N<2>
USBC_XB_D2R_P<2>
USBC_XB_SBU1
2
GND_VOID=TRUE
D3383
1
SESDL2011
DSN2-THICKSTNCL
SESDL2011
USBC_XA_SBU2
USBC_XA_R2D_CR_P<1>
USBC_XA_R2D_CR_N<1>
USBC_XA_USB_TOP_P USBC_XA_USB_TOP_N
USBC_XA_D2R_P<1>
USBC_XA_D2R_N<1>
2
GND_VOID=TRUE
D3379
1
SESDL2011
DSN2-THICKSTNCL
SESDL2011
DSN2-THICKSTNCL
D3384
DSN2-THICKSTNCL
D3380
2
GND_VOID=TRUE
D3385
1
SESDL2011
DSN2-THICKSTNCL
USBC_XA_CC1
2
GND_VOID=TRUE
1
SESDL2011
DSN2-THICKSTNCL
2
D3381
1
BI
IN
IN
BI BI
OUT
OUT
BI
2
GND_VOID=TRUE
1
SESDL2011
DSN2-THICKSTNCL
IN
IN
OUT
OUT
GND_VOID=TRUE
SESDL2011
DSN2-THICKSTNCL
D
122 31 29
CC2
120 27
122 31
TBT_R2D1
USB2 TOP
TBT_D2R1
SBU1
120 27
31
31
120 27
120 27
C
122
122 30
120 27
120 27
122 30
122 30
120 27
120 27
30 29
SBU2
TBT_R2D0
USB2 BOT
TBT_D2R0
CC1
BI
BI BI
BI
B
A
8
LAST CHANGE: Wed Apr 1 22:57:37 2015
A
SYNC_DATE=01/17/2019SYNC_MASTER=YANIR
PAGE TITLE
USB-C X Connector
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
BOM_COST_GROUP=USB-C
67
35 4
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
33 OF 200
SHEET
32 OF 135
1
SIZE
D
Page 33
Vinafix.com
D
C
678
AARDVARKANOID CONN
Place on bottom
PP3V3_UPC_XB_LDO
31 29
UPC_XB_SWD_DATA
31
UPC_XB_SWD_CLK
31
TBT_X_SPI_DBG_MISO
29
33 29 27
33 29 27 30 29
I2C_TBT_X_SDA I2C_TBT_X_SCL PP3V3_UPC_XA_LDO
1
TP-P5
1
TP-P5
1
TP-P5
1
TP-P5
1
TP-P5
1
TP-P5
TP TP TP TP TP TP
TP3006 TP3007 TP3008 TP3009 TP3010 TP3011
TP3000 TP3001 TP3002 TP3003 TP3004 TP3005
TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5
A A A A A A
1
TBT_X_SPI_DBG_CS_L
1
TBT_X_SPI_DBG_CLK
1
TBT_X_SPI_DBG_MOSI
1
UPC_XA_SWD_CLK
1
UPC_XA_SWD_DATA
1
29
29
29
30
30
ACE ARKANOID CONN
Place on bottom
J3000
505070-1222
M-ST-SM
13 14
1 2 3 4 5 6 7 8 9 10
11 12
15 16
I2C_TBT_XA_INT_L I2C_TBT_X_SDA
I2C_TBT_X_SCL
UPC_XA_SER_DBG UPC_XB_SER_DBG
UPC_XA_UART_RX
29 27
33 29 27
33 29 27
123 30
123 31
31 30
29 27
29
29
113 51 39
29
31 30
USBC_DBG
I2C_TBT_XB_INT_L I2C_UPC_X_SCL2 I2C_UPC_X_SDA2
UPC_I2C_INT_L
TBT_X_SPI_ARK_CLK UPC_XA_UART_TX
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
3 245
Ridge PCIE Caps
GND_VOID=TRUE
IN
IN
IN
IN
IN
IN
IN
PCIE_TBT_X_R2D_C_P<0>
GND_VOID=TRUE
PCIE_TBT_X_R2D_C_N<0>
GND_VOID=TRUE
PCIE_TBT_X_R2D_C_P<1>
0201 X5R
GND_VOID=TRUE
PCIE_TBT_X_R2D_C_N<1>
GND_VOID=TRUE
PCIE_TBT_X_R2D_C_P<2>
0201
GND_VOID=TRUE
PCIE_TBT_X_R2D_C_N<2>
GND_VOID=TRUE
PCIE_TBT_X_R2D_C_P<3>
PCIE_TBT_X_R2D_C_N<3>
IN
PCIE_TBT_X_D2R_C_P<0>
IN
PCIE_TBT_X_D2R_C_N<0>
IN
PCIE_TBT_X_D2R_C_P<1>
IN
PCIE_TBT_X_D2R_C_N<1>
IN
PCIE_TBT_X_D2R_C_P<2>
IN
PCIE_TBT_X_D2R_C_N<2>
IN
PCIE_TBT_X_D2R_C_P<3>
IN
PCIE_TBT_X_D2R_C_N<3>
IN
0201
GND_VOID=TRUE
0201
0201
X5R0201
X5R
6.3V
6.3V
20%6.3VX5R0201
20%6.3VX5R0201
20%6.3V
20%6.3V
20%6.3VX5R
20%6.3VX5R0201
20%6.3VX5R
20%6.3VX5R0201
20%6.3VX5R0201
20%X5R0201
20%6.3VX5R0201
20%6.3VX5R
20%6.3VX5R
20%0201 6.3V
20%6.3V0201 X5R
20%X5R0201
12
C3040
0.22UF
12
C3041
0.22UF
12
C3042
0.22UF
12
C3043
0.22UF
12
C3044
0.22UF
12
C3045
0.22UF
12
C3046
0.22UF
12
C3047
0.22UF
12
C3050
0.22UF
C3051
12
0.22UF
C3052
12
0.22UF
C3053
12
0.22UF
C3054
12
0.22UF
12
C3055
0.22UF
C3056
12
0.22UF
12
C3057
0.22UF
PCIE_TBT_X_R2D_P<0>
PCIE_TBT_X_R2D_N<0>
PCIE_TBT_X_R2D_P<1>
PCIE_TBT_X_R2D_N<1>
PCIE_TBT_X_R2D_P<2>
PCIE_TBT_X_R2D_N<2>
PCIE_TBT_X_R2D_P<3>
PCIE_TBT_X_R2D_N<3>
GND_VOID=TRUE
PCIE_TBT_X_D2R_P<0>
GND_VOID=TRUE
PCIE_TBT_X_D2R_N<0>
GND_VOID=TRUE
PCIE_TBT_X_D2R_P<1>
GND_VOID=TRUE
PCIE_TBT_X_D2R_N<1>
GND_VOID=TRUE
PCIE_TBT_X_D2R_P<2>
GND_VOID=TRUE
PCIE_TBT_X_D2R_N<2>
GND_VOID=TRUE
PCIE_TBT_X_D2R_P<3>
GND_VOID=TRUE
PCIE_TBT_X_D2R_N<3>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
1
D
C
B
27 14
113 107 29 27
31 30 27 14
31 30 27 14
29 30 31
28
RIDGE ARKANOID CONN
USBC_DBG
TBT_X_PLUG_EVENT_L
TBT_WAKE_3V3_L TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
TBT_POC_RESET PP3V3_TBT_X_F
Place on bottom
J3001
M-ST-SM
13 14
1 2 3 4 5 6 7 8 9 10
11 12
15 16
505070-1222
TBT_X_PCI_RESET_L USBC_X_RESET_L
PP3V3_TBT_X_LC PP3V3_TBT_X_ANA_PCIE TBT_X_HDMI_DDC_DATA
PP3V3_TBT_X_SX
28
29
27 20 14
29 27
79 29 27
28
B
A
8
DESIGN: X1032/MLB_P4BP LAST CHANGE: Fri Jan 6 16:01:21 2017
SYNC_MASTER=YANIR SYNC_DATE=01/17/2019
PAGE TITLE
A
USBC X Connector Support
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
BOM_COST_GROUP=USB-C
67
35 4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
.
BRANCH
PAGE
34 OF 200
SHEET
33 OF 135
1
SIZE
D
Page 34
Vinafix.com
678
3 245
1
D
29 34 124
PP5V_S4_X_USBC
2
XW3502
R3503
NO_XNET_CONNECTION=1
SM
27.4K
0.1%
1/20W
MF
0201
1
1
2
2
XW3501
SM
1
P5VUSBC_X_SENSE_DIV_XW
P5VUSBC_X_RTN_DIV_XW
1
R3531
27.4K
0.1% 1/20W MF 0201
2
NO_XNET_CONNECTION=1
1
R3517
191K
0.1% 1/20W MF 0201
2
C3517
1
22PF
5% 50V
2
C0G 0201
PP5V_USBC_X_VCC
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V
C3522
1
2.2UF
10% 10V
2
X6S-CERM 0402
34
34
118
PP5V_G3S
UPC_X_5V_EN_R
P5VUSBC_X_SENSE_DIV
P5VUSBC_X_SREF
P5VUSBC_X_VO
P5VUSBC_X_OCSET
P5VUSBC_X_PGOOD
P5VUSBC_X_RTN_DIV
P5VUSBC_X_FSEL
10 7 12 11
14
4
13
2.2
5%
1/20W
MF
201
1
2
19
20
PVCCVCC
R3501
U3500
ISL95870AHRUZ-_R5749
EN FB SREF VO OCSET PGOOD RTN FSEL
UTQFN
CRITICAL
BOOT
UGATE
PHASE
LGATE
C3521
1
10UF
20% 10V
2
X5R-CERM 0402-7
1815 17 16 1
114 117 124
PPBUS_G3H
2.2
5%
1/20W
MF
201
1
2
R3509
P5VUSBC_X_VBST
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE
DIDT=TRUE SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
P5VUSBC_X_DRVH
P5VUSBC_X_LL
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 SWITCH_NODE=TRUE
DIDT=TRUE
P5VUSBC_X_DRVL
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE
P5VUSBC_X_BOOT_RC
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE
1
C3516
0.1UF
10% 16V
2
X7R-CERM 0402
R3539
0
1 2
5%
1/20W
P5VUSBC_X_DRVH_R
MF
0201
DIDT=TRUE SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
HSG
1 2
3 4
TANT-POLY CASE-B3-1
CAPDERATE
20% 16V
1
2
C3504
33UF
Q3501
FDPC1012S
LLP
SW
C3503
33UF
20%
16V TANT-POLY CASE-B3-1
V+
8
V+
9
LSG
7
CAPDERATE
1
2
CAPDERATE
C3502
33UF
20%
16V TANT-POLY CASE-B3-1
C3500
1
2
1
2.2UF
20% 25V
2
X5R-CERM 0402-1
1
2
L3500
1.5UH-20%-12.5A-0.017OHM
1 2
PIMB062D-SM
C3501
2.2UF
20% 25V X5R-CERM 0402-1
P5VUSBC_X_R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=5V
P5VUSBC_X_POS
CRITICAL
R3530
0.002
1%
1/2W
MF
0306
12 34
C3505
2.2UF
20% 25V
X5R-CERM
0402-1
PP5V_S4_X_USBC
C3511
C3510
1
12PF
5% 25V
2
NP0-C0G 0201
2.4G DESENSE
CAPDERATE
1
C3506
2.2UF
2
X5R-CERM
0402-1
20% 25V
1
2
1
C3508
150UF
2
1
3.0PF
+/-0.1PF 25V
2
NP0-C0G 0201
5G DESENSE
20%
6.3V TANT-POLY CASE-B1S-1
CAPDERATE
1
C3507
150UF
20%
6.3V
2
TANT-POLY CASE-B1S-1
29 34 124
D
C
C3526
1
10PF
5% 50V
2
C0G 0201
1
R3504
10K
0.1% 1/20W MF 0201-1
2
1
R3502
10K
0.1% 1/20W MF 0201-1
2
C3523
0.1UF
X5R-CERM
C3515
1
10PF
5% 50V
2
C0G 0201
10% 16V
0201
SET0
P5VUSBC_X_SET0
P5VUSBC_X_SET1
1
2
1
R3518
95.3K
0.1% 1/20W MF 0201
2
P5VUSBC_X_SET_R
R3500
11K
1 2
1%
1/20W
MF
201
NOSTUFF
R3513
5%
1/20W
MF
0201
1
0
2
8
SET1
9 6
VID0 VID1
5
353S01281
3
GND
GND
GND
VER-1
PGNDGND
2
5
6
10
1%
1/20W
MF
201
1
C3570
2
2200PF
12
10% 25V
CER-X7R
0201
R3521
2.87K
P5VUSBC_X_NEG
1
R3572
2.87K
1% 1/20W MF 201
2
1
2
CAPDERATE
Vout = 5.230V Freq = 500 kHz
Max OCP = 15.71A Nom OCP = 12.2A
C3509
150UF
20%
6.3V TANT-POLY CASE-B1S-1
C
Min OCP = 7.94A IccMax = 6.6A
P5VUSBC_X_AGND
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0V
XW3500
SM
1 2
PLACE_NEAR=U3500.2:1mm
34
P5VUSBC_X_PGOOD
P2MM
SM
1
PP
PP3500
B
BYPASS=U3540.5::8MM
121 114 46 18 12
29
118
PP3V3_G3H_RTC_X
IN
IN
PM_RSMRST_L
UPC_X_5V_EN
C3540
1
0.1UF
20% 10V X7R-CERM
2
0402
6
NOSTUFF
R3540
0
1 2
5%
1/20W
MF
0201
B
U3540
5
231
74AUP1T97GM
SOT886
4
UPC_X_5V_EN_R
34
A
8
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
TBT 5V REGULATOR
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=USB-C
67
35 4
IV ALL RIGHTS RESERVED
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122 118 36 35
15
15
121 46 35 20 12
PP1V8_G3S_WLANBT
BYPASS=U3640::5mm
IN
IN IN
PCH_UART_BT_RTS_L
PCH_UART_BT_R2D PLT_RST_L
C3640
0.1UF
X5R-CERM
10%
10V
0201
1
2
8
VCC
U3640
74LVC2G126GT/S500
2 1 5 7
1OE
A2 2OE
SOT833
GND
4
Y1A1
Y2
6
3
BT UART BUFFERS
UART_BT_BUF_CTS_L
UART_BT_BUF_R2D
NOSTUFF
1
R3641
100K
5% 1/20W MF 201
2
NOSTUFF
1
R3642
100K
5% 1/20W MF 201
2
OUT
OUT
D
36
36
C
122 118 36 35
36
IN
36
IN
PP1V8_G3S_WLANBT
NOSTUFF
1
R3651
100K
5% 1/20W MF 201
2
121 46 35 20 12
NOSTUFF
1
R3652
100K
5% 1/20W MF 201
2
UART_BT_BUF_RTS_L
UART_BT_BUF_D2R PLT_RST_L
BYPASS=U3650::5mm
C3650
0.1UF
X5R-CERM
10%
10V
0201
1
2
8
VCC
U3650
74LVC2G126GT/S500
2 1 5 7
1OE
A2 2OE
SOT833
GND
4
Y1A1
Y2
PCH_UART_BT_CTS_L
6
PCH_UART_BT_D2R
3
OUT
OUT
15
15
C
B
B
A
8
SYNC_MASTER=METE SYNC_DATE=01/17/2019
PAGE TITLE
A
WIFI/BT: Support
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
BOM_COST_GROUP=WIRELESS
67
35 4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
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D
C
B
PP1V8_G3S_WLANBT
100K
10K
100K
TP-P5
TP3700 TP3701 TP3705 TP3720 TP3704 TP3706
TP3715 TP3717 TP3721 TP3722 TP3716
TP3719
PP3734 PP3736 PP3733 PP3735
TP3730 TP3731 TP3732 TP3733 TP3734 TP3735 TP3736 TP3737 TP3738 TP3739 TP3740 TP3741 TP3742
122 118 36 35
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
P2MM P2MM P2MM P2MM
SM
SM
SM
SM
PP
PP
PP
PP
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
PP1V8_G3S_WLANBT
R3751
100K
1/20W
BT_SPI2_CSN
36
122 118 36 35
NOSTUFF
1 2
1 2
1 2
1
WLAN_JTAG_SEL
TOP
1
WLAN_JTAG_TCK
TOP
1
WLAN_JTAG_TDI
TOP
1
WLAN_JTAG_TMS
TOP
1
WLAN_JTAG_TRST_L
TOP
1
WLAN_JTAG_TDO
TOP
1
BT_AUDIO_SYNC
1
WLAN_AUDIO_SYNC
1
BT_DEV_WAKE
1
BT_HOST_WAKE
1
WLAN_HOST_WAKE
1
TP_BT_GPIO_4 TP_WLAN_GPIO_13
1
TP_WLAN_GPIO_21
1
TP_WLAN_PMU_TEST
1
TP_WLAN_GPIO_12
1
1
BT_SPI2_CSN
1
BT_SPI2_CLK
1
BT_SPI2_MISO
1
BT_SPI2_MOSI
1
BT_SFLASH_CS_L
1
BT_SFLASH_WP_L
1
BT_SFLASH_HOLD_L
1
SPROM_DOUT
1
SPROM_DIN
1
WIFI_SROM_ORG
1
SPROM_CLK
1
SPROM_CS_R
1
SPROM_CS
1
5% MF
201
2
36
R3714
R3702
5%
R3719
R3752
100K
5%
1/20W
MF
201
36
201MF1/20W5%
UART_BT_LH_D2R
47 36
WLAN_JTAG_SEL:
201MF1/20W
WLAN_JTAG_SEL
LOW: GPIOs HIGH: JTAG Active
201MF1/20W5%
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
47 36
36 19
39 36
39 36
36
36
36
36
36
PP3730 PP3731
TP3703 TP3743 TP3744 TP3745
38 37 36 19
39 37 36
P2MM
P2MM
A A A A
SM
SM
TP-P5
TP-P5
TP-P5
TP-P5
PP
PP
122 118 36 35 36
1 1
BLUETOOTH SERIAL FLASH
WLAN_AUDIO_SYNC
1
R3753
2
R3754
1K
1 2
5%
1/20W
MF
201
1
10K
5%
1/20W
MF
201
2
36
BT_SPI2_CLK
BT_SFLASH_CS_L
BT_SFLASH_WP_L
BT_SFLASH_HOLD_L
38 37 36 19
PCH_PCIE_CLK100M_WLAN_P PCH_PCIE_CLK100M_WLAN_N
1
WLANBT_PCIE_WAKE_L
1
PP1V5_WLANBT
TOP
1
PP1V2_WLANBT
TOP
1
PPVIN_RFLDO_WLANBT
TOP
PP1V8_G3S_WLANBT
8
VCC
U3750
2MBIT
6
1
3
7
SCLK
36
CS* WP*
HOLD*
USON
MX25L2006EZUI-12G
OMIT_TABLE
SO/SIO1
GND
THRM
PAD
4
9
36
36
40 37
SI/SIO0
36
36
OUT
5
2
120 36 12
120 36 12
R3791
1
100K
5% 1/20W MF 201
2
PLACE_NEAR=U3750.8:2MM
1
C3710
0.1UF
10%
6.3V
2
CERM-X5R 0201
BT_SPI2_MOSI
40 37
OUT
36
BT_SPI2_MISO
1
2
36
PP3V3_G3S_WLAN
36 118 124
PLACE_NEAR=U3730.42:15MM
1
C3712
10UF
20%
2
6.3V CERM-X5R 0402-4
120 37
120 37
120 37
120 37
120 37
120 37
BI BI BI BI BI BI
47 36
R3790
100K
5% 1/20W MF 201
PLACE_NEAR=U3750.8:4MM
1
C3716
10UF
20%
6.3V
2
CERM-X5R 0402-4
40 37
40 37
38 37 36 19
OUT
39 37 36
PLACE_NEAR=U3730.17:15MM
1
C3713
10UF
20%
2
6.3V CERM-X5R 0402-4
1
2
50_G_0_MATCH 50_A_0_MATCH 50_G_1_MATCH 50_A_1_MATCH 50_G_2_MATCH 50_A_2_MATCH
WLAN_JTAG_SEL
36
WLAN_JTAG_TCK
36
WLAN_JTAG_TDI
WLAN_JTAG_TMS
36
36
WLAN_JTAG_TRST_L WLAN_JTAG_TDO
36
UART_WLAN_R2D
IN
UART_WLAN_D2R UART_WLAN_D2R_CTS_L UART_WLAN_R2D_RTS_L
IN
SPROM_DOUT
36
SPROM_DIN
36
SPROM_CLK
36
SPROM_CS
36
TP_WLAN_GPIO_13
36
TP_WLAN_GPIO_21
36
WLAN_AUDIO_SYNC WLAN_SROM_STRAP
36
TP_WLAN_PMU_TEST
36
TP_WLAN_GPIO_12
36
WLAN_HOST_WAKE PCH_WLAN_DEV_WAKE
13
PLACE_NEAR=U3730.74:15MM
C3714
10UF
20%
6.3V CERM-X5R 0402-4
91 87 76 72 49 65
44
NC
1 81 82 83 84 85
93 94 95 96
67 68 69 70
97
100
99 98
159
NC
161 163
78 79
PLACE_NEAR=U3730.30:15MM
1
C3715
10UF
20%
6.3V
2
CERM-X5R 0402-4
2G_ANT_CORE0 5G_ANT_CORE0 2G_ANT_CORE1 5G_ANT_CORE1 2G_ANT_CORE2 5G_ANT_CORE2
BT_ONLY_ANT WL_JTAG_SEL
WL_JTAG_TCK WL_JTAG_TDI WL_JTAG_TMS WL_JTAG_TRST WL_JTAG_TDO
WL_UART_RX WL_UART_TX WL_UART_RTS WL_UART_CTS
WL_SPROM_MO WL_SPROM_MI WL_SPROM_CLK WL_SPROM_CS
WL_GPIO_13 WL_GPIO_21 WL_GPIO_20
WL_GPIO_17 WL_PMU_TEST_O WL_GPIO_14 WL_GPIO_12
WL_HOST_WAKE WL_DEV_WAKE
(EXT PULL NEEDED)
(IPD)
CKPLUS_WAIVE=NDIFPR_BADTERM
29
30
VDDBAT_HP
28
VDDBAT_LP
42
VDD3P3_BT
35
VDD3P3_PAD
897463
VDD3P3_FEM_CORE0
U3730
LBEE5ZZ1HP-049
LGA
SYM 1 OF 3
OMIT_TABLE CRITICAL
(GPIO2 - 100K IPU VDDIO) (GPIO4 - IPD) (GPIO3 - 100K IPU VDDIO) (GPIO6 - ACTIVE LOW) (GPIO5)
(100K IPU VDDIO) (EXT PU NEEDED) (ACTIVE LOW, EXT PU NEEDED) (ACTIVE LOW, 100K IPU VDDIO)
(ACTIVE HIGH)
(NC) (NC) (WIFI TIME SYNC, EXT PD NEEDED)
(ACTIVE LOW SROM PRESENCE) (NOTE DEFINED) (NC) (NC)
BT_REG_ON
WL_REG_ON
20
19
BT_PWR_EN
WLAN_PWR_EN
77
77 37
VDD1P5_1X1
SR1P4_VLX
SR1P8_VLX
23
21
22
PP1V5_WLANBT
36
24
34
P1V5_WLANBT_VLX
36
PPVIN_RFLDO_WLANBT
PVIN_RFLDO_WLANBT_VLX
36
(I2S:EXT PD NEEDED, UART:NONE?)
VIN_RFLDO
SR1P2_VLX
25
26
P1V2_WLANBT_VLX
36
36
CKPLUS_WAIVE=NDIFPR_BADTERM
17
18
2
VDDIO_PMU
VDDIO_RFSW
VDD3P3_SD&OTP
VDD3P3_FEM_CORE1
VDD3P3_FEM_CORE2
BT_GPIO_2/BT_SF_STRAP
(I2S:IPD, UART:IPU)
(I2S:IPD, UART:NONE) (I2S:IPD, UART:NONE)
(BT TIME STAMP) (BT TIME SYNC)
(IPD)
(H9M PULL NEEDED)
VDD1P2_3X3
CLK32K
32
PP1V2_WLANBT
36
52
33
PMU_CLK32K_WLANBT_R
3
VDDIO_DIG
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_CLKREQ*
PCIE_WAKE*
BT_UART_RX
BT_UART_TX BT_UART_CTS BT_UART_RTS
BT_JTAG_STRAP
BT_SF_MISO BT_SF_MOSI
BT_I2S_CLK
BT_DEV_WAKE
BT_HOST_WAKE
PCIE_TX_P
PCIE_TX_N PCIE_RX_P PCIE_RX_N
PERST*
BT_SF_CS
BT_SF_CLK
BT_I2S_WS
BT_I2S_DO
BT_I2S_DI
BT_GPIO_3
BT_GPIO_4
PP1V8_G3S_WLANBT
1
C3711
0.1UF
10%
6.3V
2
CERM-X5R 0201
6
PCH_PCIE_CLK100M_WLAN_P
5
PCH_PCIE_CLK100M_WLAN_N
9
PCH_PCIE_WLAN_D2R_C_P
8
PCH_PCIE_WLAN_D2R_C_N
12
PCH_PCIE_WLAN_R2D_P
11
PCH_PCIE_WLAN_R2D_N
14
PCH_WLANBT_CLKREQ_R_L
15
WLANBT_PCIE_WAKE_L
16
PCH_WLANBT_PERST_L
54
UART_BT_BUF_R2D
55
UART_BT_BUF_D2R
56
UART_BT_BUF_CTS_L
57
UART_BT_BUF_RTS_L
53
PCH_BT_ROM_BOOT_L
60 36
37 38 39
40 41 123 124
59 58
61 62
NC
BT_SPI2_CSN BT_SPI2_CLK BT_SPI2_MISO
BT_SPI2_MOSI
UART_BT_LH_R2D
NC
UART_BT_LH_D2R
NC
BT_AUDIO_SYNC
TP_BT_GPIO_4
BT_DEV_WAKE
BT_HOST_WAKE
36
36
36
36
36
36
IN IN
IN
IN
OUT
IN
OUT
IN
OUT
BI
IN
OUT
36 19
35
35
35
35
47
D
122 118 36 35
C3721
120 36 12
120 36 12
C3722
C3723
37 19
C3724
37 20 13
120
120
120
120
0.1UF
12
GND_VOID=TRUEGND_VOID=TRUE
0.1UF
12
GND_VOID=TRUEGND_VOID=TRUE
0.1UF
12
GND_VOID=TRUEGND_VOID=TRUE
0.1UF
12
GND_VOID=TRUEGND_VOID=TRUE
PCH_PCIE_WLAN_D2R_P
0201X6S6.3V10%
PCH_PCIE_WLAN_D2R_N
0201X6S6.3V10%
PCH_PCIE_WLAN_R2D_C_P
0201X6S6.3V10%
PCH_PCIE_WLAN_R2D_C_N
0201X6S6.3V10%
OUT
OUT
IN
IN
120 14
120 14
14 120
14 120
C
PP1V8_S5
R3715
47 36
39 36
39 36
10K
5%
1/20W
MF
201
1
2
15
IN
12 77 80
B
BOOT_STRAPS
WLAN_SROM_STRAP
36
A
WLAN_SROM_STRAP: LOW: SROM Enabled HIGH: SROM Disabled
R3705
10K
5%
1/20W
MF
201
MIN_LINE_WIDTH=0.2000
PP3V3_G3S_WLAN
36 118 124
8
VCC
U3710
CAS93C86B
1
SPROM_CS
36
2
R3701
10K
5%
1/20W
MF
201
201 MF 1/20W 5%
1
2
1K
R3704
1 2
SPROM_DOUT
36
SPROM_CS_R SPROM_CLK
36
NC
3 4 1
36
CS
2
SK
7
PE
UDFN8
OMIT_TABLE
5
DODI
6
ORG
EPADGND
9
WLAN SERIAL EEPROM
PLACE_NEAR=U3710.8:2MM
1
C3717
0.1UF
10%
6.3V
2
CERM-X5R 0201
SPROM_DIN
36
WIFI_SROM_ORG
R3712
1
10K
5%
1/20W
MF
2
201
36
P1V5_WLANBT_VLX
36
36
36
DIDT=TRUE SWITCH_NODE=TRUE
P1V2_WLANBT_VLX
DIDT=TRUE SWITCH_NODE=TRUE
PVIN_RFLDO_WLANBT_VLX
DIDT=TRUE SWITCH_NODE=TRUE
1UH-20%-4.1A-0.048OHM
L3701
2.2UH-1.2A
1 2
0806
PLACE_NEAR=U3730.23:10MM
L3702
1 2
2520-1
PLACE_NEAR=U3730.25:10MM
L3703
2.2UH-1.2A
0806
PLACE_NEAR=U3730.24:5MM
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.5V
PP1V5_WLANBT_C
PLACE_NEAR=L3701.2:10MM
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.2V
PP1V2_WLANBT_C
PLACE_NEAR=L3702.2:10MM
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V
12
PPVIN_RFLDO_WLANBT_C
PLACE_NEAR=L3703.1:5MM
C3701
1
C3702
1
C3703
1
121 77 37
234
234
234
7.5UF
0402-THICKSTNCL
7.5UF
0402-THICKSTNCL
7.5UF
20% 4V
0402-THICKSTNCL
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.5V
PP1V5_WLANBT
4V20%
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.2V
PP1V2_WLANBT
4V20%
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V
PPVIN_RFLDO_WLANBT
36
36
36
BOM_COST_GROUP=WIRELESS
PAGE TITLE
WIFI/BT: MODULE 1
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
37 OF 200
SHEET
36 OF 135
SIZE
D
A
SYNC_DATE=01/17/2019SYNC_MASTER=ANDY
8
67
35 4
2
1
Page 37
Vinafix.com
678
J3802
505070-1222
M-ST-SM
13 14
WIFI_DBG
3 245
1
D
C
B
A
10 13 27 31 43 45 46 47 48 50 51 64 66 71 73 75 77 80 86 88 90 92
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
4 7
GND
THRM_PAD
U3730
LBEE5ZZ1HP-049
LGA
SYM 2 OF 3
CRITICAL
OMIT_TABLE
THRM_PAD
154 155 156 157 158 160 162 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232
233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308
U3730
LBEE5ZZ1HP-049
LGA
SYM 3 OF 3
CRITICAL
OMIT_TABLE
THRM_PAD THRM_PAD
309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385
40 36
39 36
77 36
36 20 13
UART_WLAN_R2D
WLAN_HOST_WAKE WLAN_PWR_EN PCH_WLANBT_PERST_L
NC NC
1 2 3 4 5 6 7 8 9 10
11 12
15
16
UART_WLAN_D2R UART_WLAN_R2D_RTS_L UART_WLAN_D2R_CTS_L PCH_WLANBT_CLKREQ_R_L WLAN_AUDIO_SYNC PMU_CLK32K_WLANBT_R
40 36
40 36
40 36
36 19
38 36 19
121 77 36
DEBUG CONNECTORS
RF_TUNING
RF_TUNING
RF_TUNING
CORE0 DIPLEXER AND MATCHING NETWORK
CRITICAL
J3810
20449-001E-03
F-ST-SM
120
2
3
1
4
NO STUFF
C3817
0.2PF
+/-0.05PF
25V
COG-CERM
0201
DPX205950DT-9063C2SJ
L3810
0
1 2
5%
1/20W
1
2
MF
0201
RF_TUNING
50_0_COM50_0_ANT CRITICAL
C3816
1
0.2PF
+/-0.05PF
25V
2
COG-CERM 0201
RF_TUNING
U3810
CRITICAL
2
COM
RF_TUNING
CORE1 DIPLEXER AND MATCHING NETWORK
CRITICAL
J3820
20449-001E-03
F-ST-SM
120
2
3
1
4
50_1_ANT
NO STUFF
C3827
0.2PF
+/-0.05PF
COG-CERM
25V
0201
DPX205950DT-9163C2SJ
L3820
0
1 2
5%
1/20W
1
2
MF
0201
RF_TUNING
CRITICAL
C3826
1
2
50_1_COM
0.2PF
+/-0.05PF
25V
COG-CERM 0201
RF_TUNING
U3820
2
COM
RF_TUNING
0805
GND
5
CORE2/Aux DIPLEXER AND MATCHING NETWORK
CRITICAL
J3830
20449-001E-03
F-ST-SM
2
3
1
4
50_2_ANT
RF_TUNING
C3837
0.2PF
+/-0.05PF
COG-CERM
0201
25V
1
2
L3830
0
1 2
5%
1/20W
MF
0201
RF_TUNING
50_2_COM
CRITICAL
C3836
1
0.2PF
+/-0.05PF
25V
2
COG-CERM 0201
NO STUFF
RF_TUNING
COM
2
DPX205950DT-9063C2SJ
U3830
50_A_0_DIPLEXER
120
NO STUFF
0805
HI
LO
GND
1
3
5
HI
LO
1
3
1
3
5
GND
LO
HI
CRITICAL
0805
C3815
0.2PF
+/-0.05PF
COG-CERM
4 6
50_G_0_DIPLEXER
120
50_A_1_DIPLEXER
120
NO STUFF
C3825
0.2PF
+/-0.05PF
COG-CERM
6 4
50_G_1_DIPLEXER
120
NO STUFF
C3822
0.2PF
+/-0.05PF
COG-CERM
50_G_2_DIPLEXER
C3835
0.2PF
+/-0.05PF
COG-CERM
NO STUFF
6 4
50_A_2_DIPLEXER
120 120 36
RF_TUNING
C3832
0.2PF
+/-0.05PF
COG-CERM
25V
0201
25V
0201
0201
25V
0201
25V
0201
25V
1
2
1
2
1
2
1
2
1
2
1
2
BOM_COST_GROUP=WIRELESS
L3814
0
1 2
5%
1/20W
MF
0201
RF_TUNING
L3811
0
1 2
NO STUFF
C3812
0.2PF
+/-0.05PF
25V
COG-CERM 0201
5%
1/20W
MF
0201
RF_TUNING
L3824
0
1 2
5%
1/20W
MF
0201
RF_TUNING
L3821
0
1 2
5%
1/20W
MF
0201
RF_TUNING
L3834
0
1 2
5%
1/20W
MF
0201
RF_TUNING
L3831
1.5NH+/-0.1NH-1.0A
1 2
0201
RF_TUNING
SYNC_MASTER=ANDY
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
50_A_0_MATCH
NO STUFF
C3813
1
0.2PF
+/-0.05PF
2
25V
COG-CERM 0201
50_G_0_MATCH
NO STUFF
1
CRITICAL
L3812
5.1NH-3%-0.4A
0201
2
50_A_1_MATCH
NO STUFF
C3823
1
0.2PF
+/-0.05PF
2
25V
COG-CERM 0201
50_G_1_MATCH
NO STUFF
1
CRITICAL
L3822
5.1NH-3%-0.4A
0201
2
50_G_2_MATCH
NO STUFF
C3833
1
0.2PF
+/-0.05PF
25V
2
COG-CERM 0201
50_A_2_MATCH
NO STUFF
1
CRITICAL
L3832
5.1NH-3%-0.4A
0201
2
AP & BT Conn
Apple Inc.
120 36
120 36
120 36
120 36
120 36
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
38 OF 200
SHEET
37 OF 135
SYNC_DATE=01/17/2019
SIZE
D
D
C
B
A
8
67
35 4
2
1
Page 38
Vinafix.com
Note 1) IPU represents SW configured state, not HW default
678
3 245
1
D
C
47
47
47
61
49
12
48
48
47
46
63 62
63 62
46
66
91 90 89 88 86 85 84 83
49
46
46
46
121 92 87 47
122 50
OUT OUT OUT
IN
OUT
IN
IN OUT OUT
IN
IN OUT
IN OUT OUT OUT
IN
IN
IN OUT
IN
NC_PLCAM_TX_THROTTLE NC_GNSS_HOST_TIME NC_GNSS_DEV_WAKE CODEC_INT_L SE_CTLR_FW_DWLD PCH_SOC_SYNC MESA_INT MESA_PWR_EN NC_WLAN_DEV_WAKE BOARD_REV0 SPKRAMP_INT_L SPKRAMP_RESET_L BOARD_REV1 TPAD_SPI_EN SSD_BFH SE_DEV_WAKE BOOT_CONFIG0 BOOT_CONFIG1 BOOT_CONFIG2 SSD_PMU_RESET_L DFR_DISP_INT
A13 A12 B12
AJ36
R36
AB36
AC36
V34 V36
AA36
U36 U35 V32 R32
L36
M33
J33 P33 K32
J32
AA34
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20
(IPD) (IPD)
(IPU)
(IPD)
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 3 OF 18
GPIO/TEST/MISC
(IPD)
(IPD)
(IPD)
TMR32_PWM0 TMR32_PWM1 TMR32_PWM2
CFSB
FORCE_DFU
DFU_STATUS
HOLD_RESET
ANALOGMUX_OUT
TST_CLKOUT
TESTMODE
DROOP
SOCHOT
XO0
120
XI0
120
L33 L35 K36
K34
W32 V33
J34 AN36
P32 C12
L32 L34
AV23 AV24
WLAN_AUDIO_SYNC_R
DFR_PWR_EN SOC_KBD_BKLT_PWM
PMU_ACTIVE_READY SOC_FORCE_DFU
SOC_DFU_STATUS SOC_HOLD_RESET NC_SOC_AMUXOUT
TP_SOC_TST_CLKOUT SOC_TESTMODE
PMU_DROOP_L SOC_SOCHOT_L
SOC_XTAL24M_OUT SOC_XTAL24M_IN
R3900
0
1 2
5%
1/20W
MF
0201
NOSTUFF
OUT OUT
IN
IN
OUT
38
47
123
123 38
IN
OUT
1
2
CRITICAL
WLAN_AUDIO_SYNC
50
47
135 121 77 30
135 121 77 30 29
135 121 30 29
77
121 77 38
R3940
511K
1% 1/20W MF 201
R3941
0
1 2
5%
1/20W
MF
0201
24MHZ-30PPM-9.5PF-60OHM
C3940
12PF
25V CERM 0201
5%
IN
SOC_XTAL24M_OUT_R
CRITICAL
Y3940
1.60X1.20MM-SM
1 3
NC GND
1
2
2
4
1
2
37 36 19
C3941
12PF
5% 25V CERM 0201
D
C
CRITICAL
B
46
46
64
64
64
121 30
121 30
121 29
BI OUT
OUT OUT OUT
BI BI
IN
I2C_SEP_SDA I2C_SEP_SCL
SEP_CAM_DISABLE_L SEP_DMIC_DISABLE_L SEP_DISABLE_STROBE
USB_SOC_P USB_SOC_N
NC_SOC_USB_ID
47
SOC_USB_VBUS SOC_USB_REXT
1
R3960
200
1% 1/20W MF 201
2
AV8
SEP_I2C0_SDA
AT7
SEP_I2C0_SCL
AU9
SEP_SPI0_MISO
AV9
SEP_SPI0_MOSI
AT8
SEP_SPI0_SCLK
B23
USB_DP
A23
USB_DM
D23
USB_ID
E23
USB_VBUS
F22
USB_REXT
(IPD)
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 7 OF 18
SEP/USB/DDR
DDR0_RREF DDR1_RREF DDR2_RREF DDR3_RREF
DDR0_ZQ DDR3_ZQ
DDR0_RET* DDR1_RET* DDR2_RET* DDR3_RET*
DDR0_SYS_ALIVE DDR1_SYS_ALIVE DDR2_SYS_ALIVE DDR3_SYS_ALIVE
H3 H35 AL3 AL35
N2 AF36
H4 H34 AL4 AL34
G3 G35 AM3 AM35
240
1%
1/20W
MF
201
1
2
R3970
SOC_DDR0_RREF SOC_DDR1_RREF SOC_DDR2_RREF SOC_DDR3_RREF
SOC_DDR0_ZQ SOC_DDR3_ZQ
AON_SLEEP1_RESET_L
PMU_SYS_ALIVE
R3971
240
1%
1/20W
MF
201
IN
IN
PP1V1_SLPDDR
240
1%
1/20W
MF
201
1
2
121 95 92 87 77 39
R3973
1
2
R3972
39
240
1%
1/20W
MF
201
1
2
R3974
240
1%
1/20W
MF
201
1
2
R3975
240
1%
1/20W
MF
201
1
2
80
B
A
PP1V8_SLPS2R
R3939 R3976 R3977
47K 10K 10K
8
1 2 1 2 1 2
47 80
1/20W MF
MF
SOC_SOCHOT_L
2015%
SOC_TESTMODE
2015% 1/20W MF
SOC_HOLD_RESET
2015% 1/20W
38
SYNC_MASTER=ANDY SYNC_DATE=01/17/2019
PAGE TITLE
A
SoC GPIO/SEP/USB/DDR/Test
DRAWING NUMBER
051-04492
Apple Inc.
121 77 38
123 38
BOM_COST_GROUP=SOC
67
35 4
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
REVISION
2.15.0
BRANCH
PAGE
39 OF 200
SHEET
38 OF 135
1
SIZE
D
Page 39
Vinafix.com
D
678
3 245
1
OMIT_TABLE
CRITICAL
U3900
H9M
47
47
47
47
47
20 15
47
47
47
47
47
OUT OUT
IN IN IN IN
IN OUT OUT
OUT BI
NC_WLAN_CONTEXT_A NC_WLAN_CONTEXT_B NC_GYRO_INT1 NC_GYRO_INT2 SE_HOST_WAKE_R SOC_PERST_L NC_ALTIMETER_INT NC_SPI_GYRO_CS_L SPI_AOP_MA781_CS_L
NC_I2C_AOP_SCL NC_I2C_AOP_SDA
AOP_FUNC[0]
D3
AOP_FUNC[1]
F4
AOP_FUNC[2]
M6
AOP_FUNC[3]
D4
AOP_FUNC[4]
F3
AOP_FUNC[5]
K6
AOP_FUNC[6]
E4
AOP_FUNC[7]
J3
AOP_FUNC[8]
H6
AOP_I2C0_SCL
N6
AOP_I2C0_SDA
G5
(IPD) (IPD)
(IPD)
BGA
SYM 6 OF 18
AOP
(IPU) (IPU) (IPU)
(IPD) (IPD)
AOP_PDM_CLK0 AOP_PDM_CLK1 AOP_PDM_CLK2 AOP_PDM_CLK3 AOP_PDM_CLK4
AOP_PDM_DATA0 AOP_PDM_DATA1
AOP_SPI_MOSI
AOP_SPI_SCLK
AOP_SPI_MISO
PDM_DMIC_CLK0_R
P6
PDM_DMIC_CLK1_R
K2
SMC_FIXTURE_MODE_L
J6
NC_PLCAM_PROX_INT_L
L6
NC_PLCAM_ROMEO_B2B_DETECT
L5
PDM_DMIC_DATA0
J5
PDM_DMIC_DATA1
K4
SPI_AOP_SENSOR_MOSI_R
D2
SPI_AOP_SENSOR_CLK_R
F2
SPI_AOP_SENSOR_MISO
E2
OUT OUT
IN IN IN
IN IN
OUT OUT
IN
47
47
47
47
47
64
64
47
47
47
D
C
77
77
OUT BI
SPMI_CLK SPMI_DATA
R4036 R4037
PLACE_NEAR=U3900.AD6:5MM PLACE_NEAR=U7800.M7:5MM
20 20
1 2 1 2
5% MF1/20W 5% MF
1/20W 201
122 50
46
119 97
47
18
61
36
47
47
47
47
47
77
201
123 121 77
IN IN IN
OUT
IN OUT OUT
IN OUT
IN
IN
IN
IN
IN
DFR_TOUCH_INT_L
GFX_SELF_THROTTLE_1V8 SMC_GPU_THRMTRIP XDP_PRESENT_L CODEC_RESET_L BT_DEV_WAKE NC_PCIEDN_WAKE_L NC_ENET_LOW_PWR TPAD_SPI_INT_L NC_SDCONN_STATE_CHANGE_L NC_ENET_MEDIA_SENSE PMU_INT_L
SPMI_CLK_R SPMI_DATA_R
PMU_CLK32K_SOC
AL6
AON_GPIO0
AE6
AON_GPIO1
AT5
AON_GPIO2
AN4
AON_GPIO3 AON_GPIO4
AK4
AON_GPIO5
AV5
AON_GPIO6
AR3
AON_GPIO7
AG6
AON_GPIO8
AU5
AON_GPIO9
AP2
AON_GPIO10
AR4
AON_GPIO11
AN3
AON_GPIO12
AT6
AON_SPMI_SCLK
AD6
AON_SPMI_SDATA
AR2
RT_CLK32768
AR5
(IPU)
(IPU)
(IPU) (IPD) (IPU)
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 5 OF 18
AON
(IPU) (IPU) (IPU)(IPD)
(IPD)
(IPU)
AON_SLEEP1_RESET*
JTAG_TCK JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
JTAG_SEL
DOCK_CONNECT
AON_SWD0_TMS AON_SWD1_TMS
AON_SWD01_TCK
WDOG
AK6 AN5 AH6 AP4 AJ6 AC6
AN2 AJ4
AH4 AJ2
AJ5 AF6
SWD_SOC_SWCLK SWD_SOC_SWDIOCPU_SMC_THRMTRIP_L TP_JTAG_SOC_TDI TP_JTAG_SOC_TDO TP_JTAG_SOC_TRST_L SOC_JTAG_SEL
(DAP=0, TAP=1)
SOC_DOCK_CONNECT NC_SWD_WLAN_SWDIO
NC_MESA_MENUKEY_L NC_SWD_WLAN_SWCLK
SOC_WDOG
AON_SLEEP1_RESET_L
CKPLUS_WAIVE=SINGLE_COMP_NET
121
121
123
OUT
OUT
OUT
29
IN
29
BI
123 39
IN
47
BI
47
IN
47
38
121 39 31 30
121 77
C
B
121 77 64
120 39 12
120 39 12
120 39 12
120 39 12
120 12
120 39 12
121 120 12
46
46
123 46
123 46
46
121 46
135 121 77 12
69 47 46
121 95 92 87 77 38
121 51
121 51
51
51
51
51
51
51
121 51
121 51
51
51
BI BI BI BI
IN IN IN
IN
OUT
OUT OUT
OUT OUT
IN
BI
IN
OUT BI
OUT BI
OUT BI
OUT BI
OUT BI
OUT BI
SOC_COLD_RESET_L
R4039
1/20W MF 201
5%
IN
PMU_COLD_RESET_L
1 2
ESPI_IO<0> ESPI_IO<1> ESPI_IO<2> ESPI_IO<3>
ESPI_CLK60M_PCH
ESPI_CS_L ESPI_RESET_L
SMC_PECI_RX SMC_PECI_TX
SMC_PCH_PWROK SMC_PCH_SYS_PWROK
SMC_RSMRST_L SMC_SYSRST_L
PM_SLP_S0_L SMC_PROCHOT_L
PMU_SYS_ALIVE I2C_UPC_SCL
I2C_UPC_SDA I2C_SNS0_S0_SCL
I2C_SNS0_S0_SDA I2C_SNS1_S0_SCL
I2C_SNS1_S0_SDA I2C_DISP_SCL
I2C_DISP_SDA I2C_PWR_SCL
I2C_PWR_SDA I2C_SNS_G3S_SCL
I2C_SNS_G3S_SDA
4.7K
COLD_RESET*
AK2
CFSB_AON
AK3
SMC_ESPI_IO0
V2
SMC_ESPI_IO1
U3
SMC_ESPI_IO2
U4
SMC_ESPI_IO3
V8
SMC_ESPI_CLK
U2
SMC_ESPI_CS*
V7
SMC_ESPI_RESET*
V6
SMC_PECI_IN
M5
SMC_PECI_OUT
T6
PCH_PWROK
W7
SYS_PWROK
W8
RSMRST*
W6
SYS_RESET*
W4
SLP_S0B
AA4
PROCHOT*
R5
SYS_ALIVE
AA6
SMC_I2C0_SCL
M3
SMC_I2C0_SDA
J4
SMC_I2C1_SCL
N4
SMC_I2C1_SDA
P4
SMC_I2C2_SCL
U5
SMC_I2C2_SDA
M2
SMC_I2C3_SCL
U6
SMC_I2C3_SDA
R4
SMC_I2C4_SCL
P3
SMC_I2C4_SDA
T4
SMC_I2C5_SCL
R2
SMC_I2C5_SDA
P2
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 9 OF 18
SMC
(IPD)
(IPD)
(IPD)
(IPD) (IPD)
(IPD)
(IPU)
(IPU) (IPU) (IPD)
SMC_GPIO0 SMC_GPIO1 SMC_GPIO2 SMC_GPIO3 SMC_GPIO4 SMC_GPIO5 SMC_GPIO6 SMC_GPIO7 SMC_GPIO8
SMC_GPIO9 SMC_GPIO10 SMC_GPIO11 SMC_GPIO12 SMC_GPIO13 SMC_GPIO14 SMC_GPIO15
SMC_ADC0 SMC_ADC1 SMC_ADC2 SMC_ADC3 SMC_ADC4 SMC_ADC5 SMC_ADC6 SMC_ADC7
REFP_ADC
REFM_ADC
123 58 56 54 53 46
SMC_PWM0
SMC_TACH0
SMC_PWM1
SMC_TACH1
SMC_PWM2
Y4 Y8 Y5 AA2 Y7 Y6 AB2 AD5 AD2 AB4 AC2 AC3 AA8 AB3 AE2 L4
AG2 AC4 AH3 AD4 AB6 AH2 AG4 AC5
AF4 AG3
J2 L3
R6 L2
M4
CODEC_WAKE_L BT_HOST_WAKE WLAN_HOST_WAKE GFX_THROTTLE_1V8_L LID_OPEN_SMC_IN PCC_EVENT NC_TPAD_VIBE_L TPAD_KBD_WAKE_L NC_LIDOPEN_PSU12VPGOOD_ACDCBURST_L NC_SPI_DESCRIPTOR_OVERRIDE_L DISP_GCON_INT_L PCH_GCON_INT_L NC_TPAD_ACTUATOR_DISABLE_L TBT_WAKE_L UPC_I2C_INT_L NC_GNSS_HOST_WAKE
SMC_DCIN_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_CPU_HI_ISENSE SMC_GPU_HS_ISENSE SMC_P3V3_WLAN_ISENSE SMC_P3V3_CAPLE_ISENSE
PP1V25_SLPS2R_SMC_AVREF GND_SMC_AVSS
46
PLACE_NEAR=U3900.AF3:4MM
SMC_FAN_0_PWM SMC_FAN_0_TACH
SMC_FAN_1_PWM SMC_FAN_1_TACH
NC_SMC_LED_ONEWIRE
IN IN IN
OUT
IN IN
OUT
IN
BI
OUT
IN
OUT
BI IN IN IN
IN IN IN IN IN IN IN IN
OUT
IN
OUT
IN
BI
61
36
37 36
119 98
47
96
47
47
47
47
95
15
47
29
113 51 33
47
59
59
59
59
59
59
59
59
XW4089
SM
1 2
59
59
59
59
47
B
A
PP1V8_S5
R4046 R4047 R4054 R4055 R4056 R4057 R4059
8
10K 100K 100K 100K 100K 100K 100K
1 2 1 2 1 2 1 2 1 2 1 2 1 2
80
5% 1/20W MF
MF 1/20W 2015% MF 1/20W 2015% MF 1/20W 2015% MF
SOC_JTAG_SEL
201
SOC_DOCK_CONNECT
2015% 1/20W MF
ESPI_IO<0>
201MF1/20W5%
ESPI_IO<1>
2011/20W5%
ESPI_IO<2> ESPI_IO<3> ESPI_CS_L
51
OUT
51
BI
123 39
121 39 31 30
120 39 12
120 39 12
120 39 12
120 39 12
120 39 12
I2C_SSD_SCL I2C_SSD_SDA
SMC_I2C6_SCL
R3
SMC_I2C6_SDA
T2
(IPU)
67
SMC_UART0_RXD
SMC_UART0_TXD
SWD_OUT0_TCK
SWD_OUT0_TMS
SWD_OUT1_TCK
SWD_OUT1_TMS
V4 V5
AE3 AA5
AF2 AA7
SMC_DEBUGPRT_RX SMC_DEBUGPRT_TX
SSD0_SWCLK_UART_R2D SSD0_SWDIO_UART_D2R
SSD1_SWCLK_UART_R2D SSD1_SWDIO_UART_D2R
IN
OUT
OUT
BI
OUT
BI
121 29
121 29
123 91 90 89 88
123 91 90 89 88
86 85 84 83
123
123 86 85 84 83
SYNC_MASTER=ANDY
PAGE TITLE
SoC AOP/AON/SMC
DRAWING NUMBER
SYNC_DATE=02/19/2019
SIZE
051-04492
Apple Inc.
REVISION
A
D
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
40 OF 200
SHEET
39 OF 135
1
Page 40
Vinafix.com
D
678
3 245
1
OMIT_TABLE
CRITICAL
U3900
H9M
123 82
123 82
47
47
123 82
123 82
47
47
47
47
B27
IN IN IN IN
IN IN
IN IN IN IN
MIPI_FTCAM_DATA_P<0> MIPI_FTCAM_DATA_N<0> GND GND
MIPI_FTCAM_CLK_P MIPI_FTCAM_CLK_N
GND GND GND GND
MIPI0C_DATA0_P
A27
MIPI0C_DATA0_N
B25
MIPI0C_DATA1_P
A25
MIPI0C_DATA1_N
B26
MIPI0C_CLK_P
A26
MIPI0C_CLK_N
B28
MIPI1C_DATA0_P
A28
MIPI1C_DATA0_N
B30
MIPI1C_DATA1_P
A30
MIPI1C_DATA1_N
BGA
SYM 4 OF 18
ISP
ISP_I2C0_SDA
ISP_I2C0_SCL
ISP_I2C1_SDA
ISP_I2C1_SCL
SENSOR0_CLK
SENSOR0_RST
SENSOR0_ISTRB
SENSOR1_CLK
SENSOR1_RST
SENSOR1_ISTRB
AF32 AH36
AB32 AG32
AK35 AK34 AJ33
AD33 AC32 AC34
I2C_FTCAM_SDA I2C_FTCAM_SCL
NC_I2C_PLCAM_SDA NC_I2C_PLCAM_SCL
NC_FTCAM_CLK12M_R NC_FTCAM_RESET_L DFR_TOUCH_RESET_L
NC_PLCAM_RX_CLK12M_R NC_PLCAM_RX_RESET_L DFR_DISP_RESET_L
BI
OUT
BI
OUT
OUT OUT OUT
OUT OUT OUT
52
52
47
47
47
47
52
52
D
122 50
122 50
C
1
R4100
4.02K
1% 1/20W MF 201
2
47
47
50
50
50
50
1
R4101
4.02K
1% 1/20W MF 201
2
IN IN
OUT OUT
OUT OUT
GND GND
MIPI_DFR_DATA_P MIPI_DFR_DATA_N
MIPI_DFR_CLK_P MIPI_DFR_CLK_N
SOC_MIPI0C_REXT SOC_MIPI1C_REXT SOC_MIPID_REXT
1
R4102
4.02K
1% 1/20W MF 201
2
B29
MIPI1C_CLK_P
A29
MIPI1C_CLK_N
B33
MIPID_DATA0_P
A33
MIPID_DATA0_N
B32
MIPID_CLK_P
A32
MIPID_CLK_N
F23
MIPI0C_REXT
F26
MIPI1C_REXT
F27
MIPID_REXT
(IPD)
(IPD)
SENSOR2_CLK
SENSOR2_RST
SENSOR_INT
DISP_TE DISP_VSYNC CLK32K_OUT
AD32 AJ32 AA33
H32 T36 AK33
NC_PLCAM_TX_CLK12M_R NC_PLCAM_TX_RESET_L NC_PLCAM_TX_INT
DFR_DISP_TE BOARD_REV2 DFR_TOUCH_CLK32K_RESET_L
OUT OUT
IN
IN
IN
OUT
47
47
47
122 50
46
122 50
C
52
52
52
52
52
52
122 52
122 52
52
52
52
52
47
47
BI OUT
BI OUT
BI OUT
BI OUT
BI OUT
BI OUT
IN IN
I2C_SPKRAMP_L_SDA I2C_SPKRAMP_L_SCL
I2C_SPKRAMP_R_SDA I2C_SPKRAMP_R_SCL
I2C_CODEC_SDA I2C_CODEC_SCL
I2C_ALS_SDA I2C_ALS_SCL
I2C_DFR_SDA I2C_DFR_SCL
NC_I2C_SOC_5_SDA NC_I2C_SOC_5_SCL
NC_SPKR_ID1 NC_SPKR_ID0
AE35 AD35
AF34
AG35
M34
R33 Y32
AE34
T34
U32 R35
U33 P34
R34
I2C0_SDA I2C0_SCL
I2C1_SDA I2C1_SCL
I2C2_SDA I2C2_SCL
I2C3_SDA I2C3_SCL
I2C4_SDA I2C4_SCL
I2C5_SDA I2C5_SCL
I2C6_SDA I2C6_SCL
(IPU) (IPU)
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 2 OF 18
I2C/UART/SPI/I2S
(IPU)
SPI0_MISO SPI0_MOSI
SPI0_SCLK
SPI0_SSIN
SPI1_MISO SPI1_MOSI
SPI1_SCLK
SPI1_SSIN
SPI2_MISO SPI2_MOSI
SPI2_SCLK
SPI2_SSIN
SPI3_MISO SPI3_MOSI
SPI3_SCLK
SPI3_SSIN
AR9 AR7 AU7 AT9
P36 N34 P35 T32
A19 A20 C19 A18
C17 C18 B18 A17
SPI_SOCROM_MISO SPI_SOCROM_MOSI_R SPI_SOCROM_CLK_R SPI_SOCROM_CS_L
SPI_TPAD_MISO SPI_TPAD_MOSI_R SPI_TPAD_CLK_R SPI_TPAD_CS_L
SPI_MESA_MISO SPI_MESA_MOSI_R SPI_MESA_CLK_R WLAN_JTAG_TDI
SPI_DFR_MISO SPI_DFR_MOSI_R SPI_DFR_CLK_R SPI_DFR_CS_L
IN
OUT
IN OUT OUT OUT
IN OUT OUT OUT
IN OUT OUT OUT
46
46
47
47
66
48
47
47
47
47
47
47
PLACE_NEAR=U3900.AR7:5MM PLACE_NEAR=U3900.AU7:5MM
R4171 R4172
47 46
122 50
20 20
1 2 1 2
5% 1/20W MF
1/20W MF5%
SPI_SOCROM_MOSI
201
SPI_SOCROM_CLK
201
OUT OUT
46
46
B
121
121
49
49
49
49
47
47
47
47
47
47
47
47
37 36
37 36
37 36
37 36
IN OUT
IN OUT IN OUT
IN OUT IN OUT
IN OUT IN OUT
IN OUT IN OUT
SOC_DEBUGPRT_RX SOC_DEBUGPRT_TX
UART_SE_D2R UART_SE_R2D UART_SE_D2R_CTS_L UART_SE_R2D_RTS_L
NC_UART_BT_D2R NC_UART_BT_R2D NC_UART_BT_D2R_CTS_L NC_UART_BT_R2D_RTS_L
UART_BT_LH_D2R UART_BT_LH_R2D NC_UART_GNSS_D2R_CTS_L NC_UART_GNSS_R2D_RTS_L
UART_WLAN_D2R UART_WLAN_R2D UART_WLAN_D2R_CTS_L UART_WLAN_R2D_RTS_L
UART0_RXD
Y33
UART0_TXD
Y34
UART1_RXD
B15
UART1_TXD
A15
UART1_CTS*
C15
UART1_RTS*
D15
UART2_RXD
J36
UART2_TXD
J35
UART2_CTS*
N32
UART2_RTS*
M32
UART3_RXD
M36
UART3_TXD
N36
UART3_CTS*
M35
UART3_RTS*
U34
UART4_RXD
B14
UART4_TXD
A14
UART4_CTS*
C14
UART4_RTS*
C13
(IPU)
(IPD)
(IPD)
(IPD)
(IPD)
I2S0_DIN
I2S0_DOUT
I2S0_BCLK I2S0_LRCK
I2S0_MCK
I2S1_DIN
I2S1_DOUT
I2S1_BCLK I2S1_LRCK
I2S1_MCK
I2S2_DIN
I2S2_DOUT
I2S2_BCLK I2S2_LRCK
I2S2_MCK
I2S3_DIN
I2S3_DOUT
I2S3_BCLK I2S3_LRCK
I2S3_MCK
AC33 AG34 AA32 AG33 AR35
B20 C20 C21 A21 D21
AH34 AB34 AF33 AH35 AR33
AD36 AB35 AE36 W34 AG36
I2S_SPKRAMP_L_D2R I2S_SPKRAMP_L_R2D_R I2S_SPKRAMP_L_BCLK_R I2S_SPKRAMP_L_LRCLK NC_DFR_TOUCH_RSVD
I2S_SPKRAMP_R_D2R I2S_SPKRAMP_R_R2D_R I2S_SPKRAMP_R_BCLK_R I2S_SPKRAMP_R_LRCLK NC_PCHROM_SW_EN
I2S_CODEC_D2R I2S_CODEC_R2D_R I2S_CODEC_BCLK_R I2S_CODEC_LRCLK NC_I2S_CODEC_MCLK
NC_I2S_HAWKING_D2R NC_I2S_CODEC1_R2D_R NC_I2S_HAWKING_BCLK NC_I2S_HAWKING_LRCLK NC_I2S_CODEC1_MCLK
IN OUT OUT OUT
BI
IN OUT OUT OUT OUT
IN OUT OUT OUT OUT
IN OUT OUT OUT OUT
63 62
B
47
47
47
47
47
47
47
47
47
61
47
47
47
47
47
47
47
47
47
A
8
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
SoC ISP/I2C/UART/SPI/I2S
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
41 OF 200
SHEET
40 OF 135
1
SIZE
D
Page 41
Vinafix.com
678
3 245
1
OMIT_TABLE
CRITICAL
D
120 14
120 14
120 14
120 14
120 14
120 14
120 14
120 14
OUT OUT
OUT OUT
OUT OUT
OUT OUT
PCIE_SOC_D2R_P<0> PCIE_SOC_D2R_N<0>
PCIE_SOC_D2R_P<1> PCIE_SOC_D2R_N<1>
PCIE_SOC_D2R_P<2> PCIE_SOC_D2R_N<2>
PCIE_SOC_D2R_P<3> PCIE_SOC_D2R_N<3>
(All Caps)
GND_VOID=TRUE
C4210
1 2
0.22UF
C4211
1 2
0.22UF
C4212
1 2
0.22UF
C4213
1 2
0.22UF
C4214
1 2
0.22UF
C4215
1 2
0.22UF
C4216
1 2
0.22UF
C4217
1 2
0.22UF
20% 0201X5R6.3V
20% 6.3V 0201X5R
6.3V X5R 020120%
X5R
6.3V20% 0201
6.3V X5R20% 0201
X5R
U3900
H9M
B10
PCIE_SOC_D2R_C_P<0> PCIE_SOC_D2R_C_N<0>
120 47
120 47
0201X5R6.3V20%
IN IN
PCIE_SOC_R2D_P<0> PCIE_SOC_R2D_N<0>
PCIE_SOC_D2R_C_P<1> PCIE_SOC_D2R_C_N<1>
120 47
120 47
020120% 6.3V
IN IN
PCIE_SOC_R2D_P<1> PCIE_SOC_R2D_N<1>
PCIE_SOC_D2R_C_P<2> PCIE_SOC_D2R_C_N<2>
120 47
120 47
0201X5R20% 6.3V
IN IN
PCIE_SOC_R2D_P<2> PCIE_SOC_R2D_N<2>
PCIE_SOC_D2R_C_P<3> PCIE_SOC_D2R_C_N<3>
120 47
120 47
IN IN
PCIE_SOC_R2D_P<3> PCIE_SOC_R2D_N<3>
PCIE_UP_TX0_P
C10
PCIE_UP_TX0_N
E10
PCIE_UP_RX0_P
F10
PCIE_UP_RX0_N
A9
PCIE_UP_TX1_P
B9
PCIE_UP_TX1_N
D9
PCIE_UP_RX1_P
E9
PCIE_UP_RX1_N
B8
PCIE_UP_TX2_P
C8
PCIE_UP_TX2_N
E8
PCIE_UP_RX2_P
F8
PCIE_UP_RX2_N
A7
PCIE_UP_TX3_P
B7
PCIE_UP_TX3_N
D7
PCIE_UP_RX3_P
E7
PCIE_UP_RX3_N
BGA
SYM 1 OF 18
PCIE UP/DN
PCIE_DN_TX0_P PCIE_DN_TX0_N PCIE_DN_RX0_P
PCIE_DN_RX0_N
PCIE_DN_TX1_P PCIE_DN_TX1_N PCIE_DN_RX1_P
PCIE_DN_RX1_N
PCIE_DN_TX2_P PCIE_DN_TX2_N PCIE_DN_RX2_P
PCIE_DN_RX2_N
PCIE_DN_TX3_P PCIE_DN_TX3_N PCIE_DN_RX3_P
PCIE_DN_RX3_N
AV31 AU31 AR31 AP31
AU30 AT30 AP30 AN30
AV29 AU29 AR29 AP29
AU28 AT28 AP28 AN28
NC_PCIE_WLAN_R2D_C_P NC_PCIE_WLAN_R2D_C_N NC_PCIE_WLAN_D2R_P NC_PCIE_WLAN_D2R_N
NC_PCIE_ENET_R2D_C_P NC_PCIE_ENET_R2D_C_N NC_PCIE_ENET_D2R_P NC_PCIE_ENET_D2R_N
NC_PCIE_DN2_R2D_CP NC_PCIE_DN2_R2D_CN NC_PCIE_DN2_D2RP NC_PCIE_DN2_D2RN
NC_PCIE_DN3_R2D_CP NC_PCIE_DN3_R2D_CN NC_PCIE_DN3_D2RP NC_PCIE_DN3_D2RN
47
47
47
47
47
47
47
47
OUT OUT
IN IN
OUT OUT
IN IN
47
47
47
47
47
47
47
47
D
C
120 12
OUT
SOC_CLKREQ_L
R4218
1K
1 2
5%
201MF1/20W
123 120 12
123 120 12
B21
SOC_CLKREQ_R_L
IN IN
PCIE_CLK100M_SOC_P PCIE_CLK100M_SOC_N
SOC_PCIE_UP_REXT
1
R4200
3.01K
1% 1/20W MF 201
2
PCIE_UP_CLKREQ*
G13
PCIE_UP_EXT_REFCLK_P
G12
PCIE_UP_EXT_REFCLK_N
G11
PCIE_UP_REXT
PCIE_DN_REFCLK0_P PCIE_DN_REFCLK0_N
PCIE_DN_CLKREQ0*
PCIE_DN_PERST0*
PCIE_DN_REFCLK1_P PCIE_DN_REFCLK1_N
PCIE_DN_CLKREQ1*
PCIE_DN_PERST1*
PCIE_DN_REFCLK2_P PCIE_DN_REFCLK2_N
PCIE_DN_CLKREQ2*
PCIE_DN_PERST2*
PCIE_DN_REFCLK3_P PCIE_DN_REFCLK3_N
PCIE_DN_CLKREQ3*
PCIE_DN_PERST3*
PCIE_DN_EXT_REFCLK_P
PCIE_DN_EXT_REFCLK_N
AP26 AR26 AM33 AN34
AN25 AP25 AN35 AK32
AU26 AV26 AH32 AE32
AT25 AU25 AJ34 AK36
AM27 AM26
NC_PCIE_CLK100M_WLAN_P NC_PCIE_CLK100M_WLAN_N NC_WLAN_CLKREQ_L NC_WLAN_PERST_L
NC_PCIE_CLK100M_ENET_P NC_PCIE_CLK100M_ENET_N ENET_CLKREQ_L NC_ENET_RESET_L
NC_PCIE_CLK100M_DN2P NC_PCIE_CLK100M_DN2N NC_PCIEDN2_CLKREQ_L NC_PCIEDN2_RESET_L
NC_PCIE_CLK100M_DN3P NC_PCIE_CLK100M_DN3N NC_PCIEDN3_CLKREQ_L NC_PCIEDN3_RESET_L
41
47
47
47
47
47
47
47
47
OUT OUT
IN
OUT
OUT OUT
OUT
47
47
47
47
47
47
(UID_MODE strap on A00)
47
C
B
120 88
120 88
120 88
120 88
120 89
120 89
120 89
120 89
OUT OUT
IN IN
OUT OUT
IN IN
PCIE_SSD0_R2D_C_P<0> PCIE_SSD0_R2D_C_N<0> PCIE_SSD0_D2R_P<0> PCIE_SSD0_D2R_N<0>
PCIE_SSD0_R2D_C_P<1> PCIE_SSD0_R2D_C_N<1> PCIE_SSD0_D2R_P<1> PCIE_SSD0_D2R_N<1>
AU11
PCIE_STG0_TX0_P
AT11
PCIE_STG0_TX0_N
AP11
PCIE_STG0_RX0_P
AN11
PCIE_STG0_RX0_N
AV12
PCIE_STG0_TX1_P
AU12
PCIE_STG0_TX1_N
AR12
PCIE_STG0_RX1_P
AP12
PCIE_STG0_RX1_N
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 8 OF 18
PCIE STG 0/1
PCIE_DN_REXT
PCIE_STG1_TX0_P PCIE_STG1_TX0_N PCIE_STG1_RX0_P
PCIE_STG1_RX0_N
PCIE_STG1_TX1_P PCIE_STG1_TX1_N PCIE_STG1_RX1_P
PCIE_STG1_RX1_N
AM25
AU16 AT16 AP16 AN16
AV17 AU17 AR17 AP17
SOC_PCIE_DN_REXT
R4201
3.01K
PCIE_SSD1_R2D_C_P<0> PCIE_SSD1_R2D_C_N<0> PCIE_SSD1_D2R_P<0> PCIE_SSD1_D2R_N<0>
PCIE_SSD1_R2D_C_P<1> PCIE_SSD1_R2D_C_N<1> PCIE_SSD1_D2R_P<1> PCIE_SSD1_D2R_N<1>
1%
1/20W
MF
201
1
2
OUT OUT
IN IN
OUT OUT
IN IN
120 83
120 83
120 83
120 83
120 84
120 84
120 84
120 84
B
120 90
120 90
120 90
120 90
120 91
120 91
120 91
120 91
123 89 88
123 89 88
123 88 47
123 89 47
123 91 90
123 91
123 90 47
123 91 47
91 90 89 88 47
90
OUT OUT
IN IN
OUT OUT
IN IN
OUT OUT
IN IN
OUT OUT
IN IN
OUT
PCIE_SSD0_R2D_C_P<2> PCIE_SSD0_R2D_C_N<2> PCIE_SSD0_D2R_P<2> PCIE_SSD0_D2R_N<2>
PCIE_SSD0_R2D_C_P<3> PCIE_SSD0_R2D_C_N<3> PCIE_SSD0_D2R_P<3> PCIE_SSD0_D2R_N<3>
PCIE_CLK100M_SSD0_01_P PCIE_CLK100M_SSD0_01_N SSD0_CLKREQ0_L SSD0_CLKREQ1_L
PCIE_CLK100M_SSD0_23_P PCIE_CLK100M_SSD0_23_N SSD0_CLKREQ2_L SSD0_CLKREQ3_L
SSD0_PCIE_RESET_L
AU13
PCIE_STG0_TX2_P
AT13
PCIE_STG0_TX2_N
AP13
PCIE_STG0_RX2_P
AN13
PCIE_STG0_RX2_N
AV14
PCIE_STG0_TX3_P
AU14
PCIE_STG0_TX3_N
AR14
PCIE_STG0_RX3_P
AP14
PCIE_STG0_RX3_N
AP21
PCIE_STG0_REFCLK01_P
AR21
PCIE_STG0_REFCLK01_N
AT33
PCIE_STG0_CLKREQ0*
AR34
PCIE_STG0_CLKREQ1*
AN22
PCIE_STG0_REFCLK23_P
AP22
PCIE_STG0_REFCLK23_N
AP34
PCIE_STG0_CLKREQ2*
AN33
PCIE_STG0_CLKREQ3*
AR36
PCIE_STG0_PERST*
PCIE_STG1_TX2_P PCIE_STG1_TX2_N PCIE_STG1_RX2_P
PCIE_STG1_RX2_N
PCIE_STG1_TX3_P PCIE_STG1_TX3_N PCIE_STG1_RX3_P
PCIE_STG1_RX3_N
PCIE_STG1_REFCLK01_P PCIE_STG1_REFCLK01_N
PCIE_STG1_CLKREQ0* PCIE_STG1_CLKREQ1*
PCIE_STG1_REFCLK23_P PCIE_STG1_REFCLK23_N
PCIE_STG1_CLKREQ2* PCIE_STG1_CLKREQ3*
PCIE_STG1_PERST*
AU18 AT18 AP18 AN18
AV19 AU19 AR19 AP19
AU21 AV21 B17 D18
AT22 AU22 C16 A16
AP36
PCIE_SSD1_R2D_C_P<2> PCIE_SSD1_R2D_C_N<2> PCIE_SSD1_D2R_P<2> PCIE_SSD1_D2R_N<2>
PCIE_SSD1_R2D_C_P<3> PCIE_SSD1_R2D_C_N<3> PCIE_SSD1_D2R_P<3> PCIE_SSD1_D2R_N<3>
PCIE_CLK100M_SSD1_01_P PCIE_CLK100M_SSD1_01_N SSD1_CLKREQ0_L SSD1_CLKREQ1_L
PCIE_CLK100M_SSD1_23_P PCIE_CLK100M_SSD1_23_N SSD1_CLKREQ2_L SSD1_CLKREQ3_L
SSD1_PCIE_RESET_L
OUT OUT
IN IN
OUT OUT
IN IN
OUT OUT
IN IN
OUT OUT
IN IN
OUT
120 85
120 85
120 85
120 85
120 86
120 86
120 86
120 86
123 84 83
123 84 83
83 47
123 84 47
123 86 85
123 86 85
85 47
86 47
86 85 84 83 47
A
PP1V8_AWAKE
R4232
8
47K
1 2
46 47 80
1/20W
5% MF 201
ENET_CLKREQ_L
41
47
67
OUT
SSD0_CLK24M_R
SOC_PCIE_STG0_REXT
1
R4250
3.01K
1% 1/20W MF 201
2
AP7
PCIE_STG0_NANDCLK
AM14
PCIE_STG0_EXT_REFCLK_P
AM15
PCIE_STG0_EXT_REFCLK_N
AM16
PCIE_STG0_REXT
PCIE_STG1_NANDCLK
PCIE_STG1_EXT_REFCLK_P
PCIE_STG1_EXT_REFCLK_N
PCIE_STG1_REXT
AV7
AM19 AM20
AM21
SSD1_CLK24M_R
SOC_PCIE_STG1_REXT
R4251
3.01K
1%
1/20W
MF
201
47
OUT
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
SoC PCIe
DRAWING NUMBER
051-04492
1
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
2
BOM_COST_GROUP=SOC
35 4
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
42 OF 200
SHEET
41 OF 135
1
SIZE
D
Page 42
Vinafix.com
678
3 245
1
D
C
Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3
PPVDDCPU_AWAKE
80
0.625V - 1.06V
12.5A Max
C4300
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4305
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4320
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4330
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
C4301
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4306
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4321
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4331
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
C4302
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4307
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4322
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4332
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
C4303
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4308
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4323
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4333
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
C4304
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4309
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4324
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4334
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
AA12 AA14 AA16 AB11 AB13 AB15 AC12 AC14 AC16 AD11 AD13 AD15 AD17 AE10 AE12 AE14 AE16 AE18
P11 P13 P15
P17 R12 R14 R16
T11 T13
T15 U12 U14 U16
V17 W12 W14 W16
Y17
VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU
OMIT_TABLE CRITICAL
U3900
H9M
BGA
SYM 10 OF 18
VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM VDD_CPU_SRAM
VDD_CPU_SENSE VSS_CPU_SENSE
AA10 AB17 AC10 R10 T17 U10 V11 V13 V15 W10 Y11 Y13 Y15
SOC_VDDCPU_SENSE
N18
NC_SOC_VSSCPU_SENSE
N17
C4350
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4355
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4360
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4351
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4356
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
OUT
47
C4352
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
77 47
C4353
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4354
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4357
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
PPVDDCPUSRAM_AWAKE
0.8V - 1.06V
0.9A Max
80
D
C
B
A
80
PP0V82_SLPDDR
3.93A Max
234
234
C4370
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4380
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4385
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
234
C4371
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4381
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4386
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
234
C4372
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
234
C4373
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
OMIT_TABLE CRITICAL
U3900
H9M
VDD_SOC VDD_SOC
AA20
VDD_SOC
AA22
VDD_SOC
AA24
VDD_SOC
AA26
VDD_SOC
AA28
VDD_SOC
AC18
VDD_SOC
AC20
VDD_SOC
AC22
VDD_SOC
AC24
VDD_SOC
AC26
VDD_SOC
AC28
VDD_SOC
AE20
VDD_SOC
AE22
VDD_SOC
AE24
VDD_SOC
AE26
VDD_SOC
AE28
VDD_SOC
AG10
VDD_SOC
AG12
VDD_SOC
AG14
VDD_SOC
AG16
VDD_SOC
AG18
VDD_SOC
AG20
VDD_SOC
AG22
VDD_SOC
AG24
VDD_SOC
AG26
VDD_SOC
AG28
VDD_SOC
AJ10
VDD_SOC
AJ12
VDD_SOC
AJ14
VDD_SOC
AJ16
VDD_SOC
AJ18
VDD_SOC
AJ20
VDD_SOC
AJ22
VDD_SOC
AJ24
VDD_SOC
AJ26
VDD_SOC
AJ28
VDD_SOC
J10
VDD_SOC
J12
VDD_SOC
J14
VDD_SOC
J16
VDD_SOC
J18
VDD_SOC
J20
BGA
SYM 11 OF 18
VDD_SOC_SENSE
VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_SOC
VSS_SENSE
J22 J24 J26 J28 L10 L12 L14 L16 L18 L20 L22 L24 L26 L28 N10 N12 N14 N16 N20 N22 N24 N26 N28 R18 R20 R22 R24 R26 R28 U18 U20 U22 U24 U26 U28 W20 W22 W24 W26 W28
AD27 AD28
SOC_VDDSOC_SENSE NC_SOC_VSSSOC_SENSE
47
47
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
IV ALL RIGHTS RESERVED
SoC Power 1
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
43 OF 200
SHEET
42 OF 135
B
A
SIZE
D
8
67
35 4
2
1
Page 43
Vinafix.com
D
C
B
A
678
Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3
80
PP1V1_SLPDDR
0.86A Max
C4451
2.2UF
20%
4V
X6S-CERM
0201
C4455
2.2UF
20%
X6S-CERM
0201
0402-THICKSTNCL
0402-THICKSTNCL
0402-THICKSTNCL
80
PP0V9_SLPDDR
1.9A Max
43 80
PP0V9_SLPDDR
80
25mA Max
PP0V9_SLPDDR
330mA Max
C4400
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4405
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4410
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
9mA Max
80
PP0V9_SLPDDR PP0V9_SLPDDR
80
5mA Max
80
PP0V8_SLPS2R
102mA Max
C4401
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4406
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4411
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4425
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4402
9.1UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4420
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4423
2.2UF
20%
X6S-CERM
0201
C4426
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
4V
C4450
2.2UF
X6S-CERM
C4454
2.2UF
X6S-CERM
1
20%
4V
2
0201
1
20%
4V
2 4V
0201
U3900
H9M
BGA
AB19 AB21 AB23 AB25
AB27 AD19 AD21 AD23 AD25
AF11
AF13
AF15
AF17
AF19
AF21
AF23
AF25
AF27 AH11 AH13 AH15 AH17 AH19 AH21 AH23 AH25 AH27 AK11
1
2
VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED
K11
VDD_FIXED
K13
VDD_FIXED
K15
VDD_FIXED
K17
VDD_FIXED_CPU
W18
VDD_FIXED_USB
G22
VDD_FIXED_MIPI
H23
VDD_FIXED_MIPI
H25
VDD_FIXED_MIPI
H27
VDD_LOW
AB9
VDD_LOW
AD9
VDD_LOW
P9
VDD_LOW
T9
VDD_LOW
V9
VDD_LOW
Y9
VDD_FIXED_UP_PCIE_ANA
H11
VDD_FIXED_UP_PCIE_ANA
H13
VDD_FIXED_UP_PCIE_ANA
H15
VDD_FIXED_UP_PCIE_CLK
J15
VDD_FIXED_UP_PCIE_CLK
J11
VDD_FIXED_UP_PCIE_CLK
J13
SYM 12 OF 18
OMIT_TABLE CRITICAL
VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED VDD_FIXED
VDD_FIXED_STG0_PCIE_ANA VDD_FIXED_STG0_PCIE_ANA VDD_FIXED_STG0_PCIE_ANA
VDD_FIXED_STG0_PCIE_CLK VDD_FIXED_STG0_PCIE_CLK VDD_FIXED_STG0_PCIE_CLK
VDD_FIXED_STG1_PCIE_ANA VDD_FIXED_STG1_PCIE_ANA VDD_FIXED_STG1_PCIE_ANA
VDD_FIXED_STG1_PCIE_CLK VDD_FIXED_STG1_PCIE_CLK VDD_FIXED_STG1_PCIE_CLK
VDD_FIXED_DN_PCIE_ANA VDD_FIXED_DN_PCIE_ANA VDD_FIXED_DN_PCIE_ANA
VDD_FIXED_DN_PCIE_CLK VDD_FIXED_DN_PCIE_CLK VDD_FIXED_DN_PCIE_CLK
VDD_FIXED_PCIE_REFBUF VDD_FIXED_PCIE_REFBUF VDD_FIXED_PCIE_REFBUF VDD_FIXED_PCIE_REFBUF VDD_FIXED_PCIE_REFBUF
K19 K21 K23 K25 K27 M11 M13 M15 M17 M19 M21 M23 M25 M27 P19 P21 P23 P25 P27 T19 T21 T23 T25 T27 V19 V21 V23 V25 V27 Y19 Y21 Y23 Y25 Y27
AL14 AL16 AL12
AK13 AK15 AK17
AL18 AL20 AL22
AK19 AK21 AL17
AL26 AL28
AL30 AK25
AK27 AK29
AK23 AJ15
AL24 AJ21 AJ27
C4452
1
2.2UF
2
1
X6S-CERM
C4456
2.2UF
2 4V
C4430
4.3UF
20%
4V
CERM
1
234
C4435
4.3UF
20%
4V
CERM
1
234
C4440
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4445
4.3UF
20%
4V
CERM
1
234
X6S-CERM
C2
E1
20%
4V
0201
20%
0201
1
2
1
2
C4453
2.2UF
20%
4V
X6S-CERM
0201
C4457
2.2UF
20%
4V
X6S-CERM
0201
1
2
1
2
G1
H8
J9
K8
L9
M8
N9
P1 R1 U1
C36 E37
G37
H30
J29
K30
L29
M30
N29 P37 R37 U37
AB1 AD1 AE1
AF9
AG8
AH9
AJ8
AK9
AL8
AM1
AP1
AT2
AB37 AD30 AD37 AE29 AE37
AF30
AG29
AH30
AJ29
AM37
AP37
AT36
PP0V9_SLPDDR
C4431
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
PP0V9_SLPDDR
C4436
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
PP0V9_SLPDDR
C4441
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
PP0V9_SLPDDR_SOC_PCIEREFBUF
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V
VDDIO11_DDR0 VDDIO11_DDR0 VDDIO11_DDR0 VDDIO11_DDR0 VDDIO11_DDR0 VDDIO11_DDR0 VDDIO11_DDR0 VDDIO11_DDR0 VDDIO11_DDR0 VDDIO11_DDR0 VDDIO11_DDR0 VDDIO11_DDR0
VDDIO11_DDR1 VDDIO11_DDR1 VDDIO11_DDR1 VDDIO11_DDR1 VDDIO11_DDR1 VDDIO11_DDR1 VDDIO11_DDR1 VDDIO11_DDR1 VDDIO11_DDR1 VDDIO11_DDR1 VDDIO11_DDR1 VDDIO11_DDR1
VDDIO11_DDR2 VDDIO11_DDR2 VDDIO11_DDR2 VDDIO11_DDR2 VDDIO11_DDR2 VDDIO11_DDR2 VDDIO11_DDR2 VDDIO11_DDR2 VDDIO11_DDR2 VDDIO11_DDR2 VDDIO11_DDR2 VDDIO11_DDR2
VDDIO11_DDR3 VDDIO11_DDR3 VDDIO11_DDR3 VDDIO11_DDR3 VDDIO11_DDR3 VDDIO11_DDR3 VDDIO11_DDR3 VDDIO11_DDR3 VDDIO11_DDR3 VDDIO11_DDR3 VDDIO11_DDR3 VDDIO11_DDR3
R4445
1/20W
0201
OMIT_TABLE CRITICAL
U3900
H9M
SYM 13 OF 18
330mA Max
330mA Max
330mA Max
0
5% MF
PP0V9_SLPDDR
12
BGA
43 80
43 80
43 80
3 245
VDDIO11_PLL_DDR VDDIO11_PLL_DDR VDDIO11_PLL_DDR VDDIO11_PLL_DDR
VDDIO11_RET_DDR VDDIO11_RET_DDR VDDIO11_RET_DDR VDDIO11_RET_DDR
G9 G29 AM9 AK30
G4 G34 AM4 AM34
45mA Max
PP1V1_SLPDDR
80
C4460
1
0.22UF
20%
6.3V
2
X6S-CERM 0201
C4470
1
2.2UF
20% 4V
2 4V
X6S-CERM 0201
43 80
C4461
1
0.22UF
20%
6.3V
2
X6S-CERM 0201
C4471
1
2.2UF
20%
2 4V
X6S-CERM 0201
BOM_COST_GROUP=SOC
8mA Max
1
R4460
5.1
1 2
1/20W MF1%
0201
L4460
120-OHM-25%-0.48A-0.21DCR
1 2
0201
PP1V1_SLPDDR_SOC_VDDIOPLLDDR_F
C4462
1
0.22UF
20%
6.3V
2
X6S-CERM 0201
C4463
1
0.22UF
20%
6.3V
2
X6S-CERM 0201
PP1V1_SLPS2R
C4472
1
2.2UF
20%
2 4V
X6S-CERM 0201
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
C4473
1
2.2UF
20%
2
X6S-CERM 0201
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V
Current included in VDD2
80
SoC Power 2
DRAWING NUMBER
051-04492
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
REVISION
2.15.0
BRANCH
PAGE
44 OF 200
SHEET
43 OF 135
D
C
B
A
SIZE
D
8
67
35 4
2
1
Page 44
Vinafix.com
678
Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3
3 245
1
D
C
B
A
PP1V8_AWAKE
80
40mA Max
PP1V8_SLPS2R
80
1mA Max
PP1V8_SLPS2R
80
1mA Max
80
PP1V8_SLPS2R 20mA Max
C4521
2.2UF
20%
4V
X6S-CERM
0201
80
PP1V8_SLPS2R
80
134mA Max
1
2
C4522
2.2UF
20%
4V
X6S-CERM
0201
PP1V8_AWAKE 2mA Max
PP1V8_AWAKE
80
20mA Max
80
PP1V8_AWAKE 1mA Max
R4546
49.9
1 2
1/20W
1
2
C4510
1% MF
201
R4519
49.9
1 2
1%
1/20W
MF
201
C4523
2.2UF
20%
X6S-CERM
0201
C4540
C4500
2.2UF
X6S-CERM
2.2UF
20%
4V
X6S-CERM
0201
1
4V
2
0.1UF
10%
6.3V X6S
0201
1
20%
4V
2
0201
1
2
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 VOLTAGE=1.8V
C4501
2.2UF
X6S-CERM
0201
C4511
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
1
20%
4V
2 4V
C4512
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
C4502
2.2UF
X6S-CERM
0201
PP1V8_SLPS2R_SOC_LPADC_RC PP1V8_SLPS2R_SOC_LPOSC_RC
VOLTAGE=1.8V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
C4524
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
R4530
0
1 2
5%
1/20W
MF
0201
PP1V8_AWAKE
80
C4525
4.3UF
20%
4V
CERM
0402-THICKSTNCL
1
234
MIN_NECK_WIDTH=0.1000 MIN_LINE_WIDTH=0.2000 VOLTAGE=1.8V
PP1V8_AWAKE_SOC_TSADC_RC
C4530
1
1UF
20% 16V
2
CER-X5R 0201
C4519
2.2UF
20%
4V
X6S-CERM
0201
C4526
4.3UF
CERM
0402-THICKSTNCL
1
234
7mA Max
C4535
2.2UF
20%
4V
X6S-CERM
0201
1
PP1V8_AWAKE_SOC_FMON_RC
2
1 2
R4545
49.9
1%
1/20W
MF
201
C4545
1
2
VOLTAGE=1.8V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
1UF
20% 16V CER-X5R 0201
1
20%
2
C4513
1
2
20%
4V
1
2
0.1UF
10%
6.3V X6S
0201
0402-THICKSTNCL
C4503
2.2UF
20%
4V
X6S-CERM
0201
1
2
C4515
20UF
20%
2.5V
X6S-CERM
0402
C4527
4.3UF
20%
4V
CERM
1
234
C4536
0.1UF
10%
6.3V X6S
0201
D
OMIT_TABLE CRITICAL
U3900
H9M
A4
VDD1 VDD12_CPU_UVD VDD1
AV34
1
2
1
2
1
2
AV4
B35
W1
W37
Y1
Y37
AA9
P8 R9
T8
U9
W9
AC9 AD8
AE9 AB8
AB10
AA29 AB30 AC29
P30
R29
T30
U29
V30
W29
Y30
G16 G18 G20 H17 H19 H21
AK31
AM31
AL11
AM10
AA18
P16
AD16
AF18
H28 G23
G25 G27
H22
AF12
AM30
AK12
VDD1 VDD1 VDD1 VDD1 VDD1 VDD1
VDDIO18_AOP1 VDDIO18_AOP1 VDDIO18_AOP1 VDDIO18_AOP1 VDDIO18_AOP1 VDDIO18_AOP1
VDDIO18_AOP2 VDDIO18_AOP2 VDDIO18_AOP2
VDD18_LPADC VDD18_LPOSC
VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP1
VDDIO18_GRP2 VDDIO18_GRP2 VDDIO18_GRP2 VDDIO18_GRP2 VDDIO18_GRP2 VDDIO18_GRP2
VDDIO18_GRP3 VDDIO18_GRP3
VDDIO18_GRP4 VDDIO18_GRP4
VDD18_TSADC VDD18_TSADC VDD18_TSADC VDD18_TSADC VDD18_TSADC
VDD18_MIPI VDD18_MIPI VDD18_MIPI
VDD18_USB VDD18_FMON VDD18_EFUSE1
VDD18_EFUSE2
BGA
SYM 14 OF 18
VDD12_PLL_CPU
VDD12_PCIE_REFBUF VDD12_PCIE_REFBUF
VDD12_DN_PCIE VDD12_UP_PCIE
VDD12_STG0_PCIE VDD12_STG1_PCIE
VDD12_PLL_SOC VDD12_PLL_SOC VDD12_PLL_SOC
VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2
VDD11_XTAL
VDD33_USB
Y18
V18 AK24
AM23
AM29 G14
AM13 AM18
AC23 AD24 AE23
AG1 AG37 AJ1 AJ37 AK1 AK37 AU3 AU34 AU35 AU4 B3 B4 C34 D34 J1 J37 K1 K37 M1 M37 W3 W35 Y3 Y35
AN23
F21
PP1V2_AWAKE
10mA Max
C4550
1
2.2UF
20% 4V
2
X6S-CERM 0201
VOLTAGE=1.2V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PP1V2_AWAKE_SOC_PLLCPU_F PP1V2_AWAKE_SOC_PCIEREFBUF_F
VOLTAGE=1.2V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PP1V2_AWAKE_SOC_PCIEPLL_F
VOLTAGE=1.2V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PP1V2_AWAKE_SOC_PLLSOC_F
VOLTAGE=1.2V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
C4580
1
2.2UF
20%
2
4V X6S-CERM 0201
PP1V1_SLPDDR_SOC_XTAL_F
VOLTAGE=1.1V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
C4581
1
2.2UF
20% 4V
2
X6S-CERM 0201
PP3V3_AWAKE
C4582
1
2
80
12mA Max
1
C4595
0.1UF
10%
2
6.3V X6S 0201
80
C4560
0.1UF
10%
6.3V X6S
0201
C4565
2.2UF
20%
4V
X6S-CERM
0201
C4570
0.1UF
10% X6S
0201
2.2UF
20% 4V X6S-CERM 0201
C4590
C4555
0.1UF
R4560
1 2
5%
1
2
1
2
1
2
0.1UF
10%
6.3V X6S
0201
1/20W
MF
0201
C4566
2.2UF
X6S-CERM
C4571
0.1UF
PP1V1_SLPS2R
C4583
1
2.2UF
20%
2
4V X6S-CERM 0201
1%
240-OHM-25%-0.42A-0.31DCR
1
2
1
10%
6.3V
2
X6S
0201
0
C4561
1
0.1UF
10%
6.3V
2
X6S 0201
1
20%
4V
2
0201
1
10%
6.3V
26.3V
X6S
0201
R4590
5.1
1 2
L4590
1 2
0201
R4555
0
1 2
5%
1/20W
MF
0201
C4567
2.2UF
20%
X6S-CERM
0201
R4570
0
1 2
5%
1/20W
MF
0201
0201MF1/20W
PP1V2_AWAKE
PP1V2_AWAKE
C4562
1
2.2UF
20% 4V
2
X6S-CERM 0201
1
4V
2
1
C4572
2.2UF
20% 4V
2
X6S-CERM 0201
1.74A Max
PP1V1_SLPDDR
C4591
1
2.2UF
20% 4V
2
X6S-CERM 0201
C4568
2.2UF
X6S-CERM
20%
4V
0201
1
2
PP1V2_AWAKE
80
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
13mA Max
80mA Max
R4565
0
1 2
5%
1/20W
MF
0201
31mA Max
4mA Max
80
44 80
PP1V2_AWAKE
80
80
C
44 80
60mA Max
B
A
SoC Power 3
SIZE
D
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
IV ALL RIGHTS RESERVED
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
45 OF 200
SHEET
44 OF 135
8
67
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2
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D
C
B
A1 A10 A11
A2 A22 A24
A3 A31 A34 A35 A36 A37
A5
A6
A8 AA1
AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AA27
AA3
AA30 AA31 AA35 AA37 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AB26 AB28 AB29 AB31 AB33
AB5 AB7
AC1 AC11 AC13 AC15 AC17 AC19 AC21 AC25 AC27 AC30 AC31 AC35 AC37
AC7
AC8 AD10 AD12 AD14 AD18 AD20 AD22 AD26 AD29
AD3 AD31 AD34
AD7
AE11 AE13 AE15 AE17 AE19 AE21 AE25 AE27 AE30 AE31 AE33
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
U3900
H9M
BGA
SYM 15 OF 18
OMIT_TABLE CRITICAL
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE4 AE5 AE7 AE8 AF1 AF10 AF14 AF16 AF20 AF22 AF24 AF26 AF28 AF29 AF3 AF31 AF35 AF37 AF5 AF7 AF8 AG11 AG13 AG15 AG17 AG19 AG21 AG23 AG25 AG27 AG30 AG31 AG5 AG7 AG9 AH1 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH29 AH31 AH33 AH37 AH5 AH7 AH8 AJ11 AJ13 AJ17 AJ19 AJ23 AJ25 AJ3 AJ30 AJ31 AJ35 AJ7 AJ9 AK10 AK14 AK16 AK18 AK20 AK22 AK26 AK28 AK5 AK7 AK8 AL1 AL10 AL13 AL15 AL19 AL2
AL21 AL23 AL25 AL27 AL29 AL31 AL32 AL33 AL36 AL37
AL5 AL7
AL9 AM11 AM12 AM17
AM2 AM22 AM24 AM28 AM32 AM36
AM5
AM6
AM7
AM8
AN1 AN10 AN12 AN14 AN15 AN17 AN19 AN20 AN21 AN24 AN26 AN27 AN29 AN31 AN32 AN37
AN6
AN7
AN8
AN9
AP10 AP15 AP20 AP23 AP24 AP27
AP3 AP32 AP33 AP35
AP5
AP6
AP8
AP9
AR1 AR10 AR11 AR13 AR15 AR16 AR18 AR20 AR22 AR23 AR24 AR25 AR27 AR28 AR30 AR32 AR37
AR6
AR8
AT1 AT10 AT12 AT14 AT15 AT17
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
U3900
H9M
BGA
SYM 16 OF 18
OMIT_TABLE CRITICAL
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AT19 AT20 AT21 AT23 AT24 AT26 AT27 AT29 AT3 AT31 AT32 AT34 AT35 AT37 AT4 AU1 AU10 AU15 AU2 AU20 AU23 AU24 AU27 AU32 AU33 AU36 AU37 AU6 AU8 AV1 AV10 AV11 AV13 AV15 AV16 AV18 AV2 AV20 AV22 AV25 AV27 AV28 AV3 AV30 AV32 AV33 AV35 AV36 AV37 AV6 B1 B11 B13 B16 B19 B2 B22 B24 B31 B34 B36 B37 B5 B6 C1 C11 C22 C23 C24 C25 C26 C27 C28 C29 C3 C30 C31 C32 C33 C35 C37 C4 C5 C6
C7 C9
D1 D10 D11 D12 D13 D14 D16 D17 D19 D20 D22 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D35 D36 D37
D5
D6
D8
E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E24 E25 E26 E27 E28 E29
E3 E30 E31 E32 E33 E34 E35 E36
E5
E6
F1 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F24 F25 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
F5
F6
F7
F9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
U3900
H9M
BGA
SYM 17 OF 18
OMIT_TABLE CRITICAL
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
G10 G15 G17 G19 G2 G21 G24 G26 G28 G30 G31 G32 G33 G36 G6 G7 G8 H1 H10 H12 H14 H16 H18 H2 H20 H24 H26 H29 H31 H33 H36 H37 H5 H7 H9 J17 J19 J21 J23 J25 J27 J30 J31 J7 J8 K10 K12 K14 K16 K18 K20 K22 K24 K26 K28 K29 K3 K31 K33 K35 K5 K7 K9 L1 L11 L13 L15 L17 L19 L21 L23 L25 L27 L30 L31 L37 L7 L8 M10 M12 M14 M16 M18 M20
M22 M24 M26 M28 M29 M31
M7 M9
N1 N11 N13 N15 N19 N21 N23 N25 N27
N3 N30 N31 N33 N35 N37
N5
N7
N8 P10 P12 P14 P18 P20 P22 P24 P26 P28 P29 P31
P5
P7 R11 R13 R15 R17 R19 R21 R23 R25 R27 R30 R31
R7
R8
T1 T10 T12 T14 T16 T18 T20 T22 T24 T26 T28 T29
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
U3900
H9M
BGA
SYM 18 OF 18
OMIT_TABLE CRITICAL
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
T3 T31 T33 T35 T37 T5 T7 U11 U13 U15 U17 U19 U21 U23 U25 U27 U30 U31 U7 U8 V1 V10 V12 V14 V16 V20 V22 V24 V26 V28 V29 V3 V31 V35 V37 W11 W13 W15 W17 W19 W2 W21 W23 W25 W27 W30 W31 W33 W36 W5 Y10 Y12 Y14 Y16 Y2 Y20 Y22 Y24 Y26 Y28 Y29 Y31 Y36
D
C
B
A
8
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
SoC Ground
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
46 OF 200
SHEET
45 OF 135
1
SIZE
D
Page 46
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D
38
38
38
46 40
46 40
46 40
66 47
47 40
66 47
Boot Config
OUT OUT OUT
BOOT_CONFIG0 BOOT_CONFIG1 BOOT_CONFIG2
Board ID
OUT OUT OUT OUT OUT OUT
SPI_SOCROM_CLK SPI_SOCROM_MOSI SPI_SOCROM_MISO SPI_TPAD_MOSI SPI_TPAD_MISO SPI_TPAD_CLK
BOOTCFG0
1
R4700
1K
5% 1/20W MF 201
2
BOARDID0
1
R4710
3.0K
5% 1/20W MF 201
2
BOOTCFG1
1
R4701
1K
5% 1/20W MF 201
2
BOARDID1
1
R4711
3.0K
5% 1/20W MF 201
2
PP1V8_AWAKE
BOOTCFG2
1
R4702
1K
5% 1/20W MF 201
2
BOARDID2
1
R4712
3.0K
5% 1/20W MF 201
2
BOARDID3
1
R4713
3.0K
5% 1/20W MF 201
2
41 46 47 80
BOOTCFG2
0 0 1 1
BOARDID4
1
R4714
3.0K
5% 1/20W MF 201
2
BOOTCFG0
0 1
BOOTCFG1
0 1 0 1
PP1V8_AWAKE
BOARDID5
1
R4715
3.0K
5% 1/20W MF 201
2
Test Mode
Disabled
Enabled
Frequency
40 MHz
6 MHz
24 MHz
Invalid
39
41 46 47 80
PECI Level Shifting
PP1V05_S3
U4750
74AUC1G126
A2
BGA-YZP
B1
A
126
BYPASS=U4750::5MM
C4750
0.1UF
X5R-CERM
PLACE_NEAR=U3900.T6:15MM
R4750
IN
SMC_PECI_TX
5% 1/20W
80
0
1 2
SMC_PECI_TX_R
0201MF
PP1V8_S5
BYPASS=U4755::5MM
C4755
0.1UF
10% 10V
X5R-CERM
0201
39
PP4700
OUT
SMC_PECI_RX
SM
P3MM
1
PP
10% 10V
0201
1
2
1
2
74AVC1T45
A
3 4
5
DIR
OE
C1
1
U4755
SOT886
GND
2
C2
Y
CRITICAL
A1
6
VCCBVCCA
B
BYPASS=U4755::5MM
C4756
1
0.1UF
10% 10V
2
X5R-CERM 0201
CPU_PECI
NOSTUFF
R4755
330
5%
1/20W
MF
201
40 46
40
1
2
117
PP1V8_AWAKE
80
SPI_SOCROM_CLK
IN
SPI_SOCROM_CS_L
IN
SPI_SOCROM_WP_L
123
BI
13 6
R4770
100K
5%
1/20W
MF
201
SoC ROM
BYPASS=U4770::5MM
C4770
CRITICAL
8
VCC
U4770
USON
10K
5%
1/20W
MF
201
1
2
6 5
SCLK SI/SIO0
4MX8-1.8V
1
2
R4771
1
0.1UF
10% 10V
2
X5R-CERM 0201
SPI_SOCROM_MOSI
IN
MX25U3235F
1
CS* WP*/SIO2
3 7
RESET*/SIO3
VER 2
GND
4
SO/SIO1
EPAD
EPAD 9
10
SPI_SOCROM_MISO_R SPI_SOCROM_MISO
2
PLACE_NEAR=U4770.2:5MM
R4773
20
1 2
5% 2011/20WMF
OUT
D
40 46
40 46
C
B
Board Revision
38
OUT
38
OUT
40
OUT
SEP EEPROM
PP1V8_AWAKE
80
38
IN
BOARD_REV0 BOARD_REV1 BOARD_REV2
R4730
2.2K
5%
1/20W
MF
201
PP1V8_AWAKE
BOARDREV0
1
R4720
1K
5% 1/20W MF 201
2
IC,SLG4AP41484,THERMTRIP,STQFN14
BOARDREV1
1
R4721
1K
5% 1/20W MF 201
2
BOARDREV2
1
R4722
1K
5% 1/20W MF 201
2
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
U4740
(Write: 0xA2, Read 0xA3) No Pull-up or TP on SDA in POR
BYPASS=U4730.A1::3mm
1
2
1
C4730
0.1UF
10% 10V
2
X5R-CERM 0201
A1B2
VCCVSS
R4731
2.2K
5%
1/20W
MF
201
1
2
U4730
M34128-FCS6_P/T
B1 A2
SCL
WLCSP
CRITICAL
SDA
I2C_SEP_SDAI2C_SEP_SCL
CRITICAL343S00234 1
41 46 47 80
BI
38
121 39
123 39 121 12
123 39
46 39
IN IN OUT
IN IN
SMC AVREF Supply
Footprint supports 353S01042 alternate
PP1V8_SLPS2R
BYPASS=U4780::3MM
C4780
1.0UF
0201-1
20%
6.3V X5R
1
2
U4780
REF3312AIRSE
UQFN-COMBO
IN
5
CRITICAL
GND 4
OUT
NC0 NC1
NC2
NC3 NC4
8
1
2
3 6 7
NC NC NC NC NC
80
PP1V25_SLPS2R_SMC_AVREF
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 VOLTAGE=1.25V
C4781
1
1.0UF
20%
6.3V
2
X5R 0201-1
GND_SMC_AVSS
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 VOLTAGE=0V
80
PP1V8_SLPS2R
SMC_PCH_SYS_PWROK
SMC_PCH_PWROK SMC_RSMRST_L
BYPASS=U4780::6MM
R4760
100K
5%
1/20W
MF
201
123 58 56 54 53 39
2
1
39
R4761
100K
5%
1/20W
MF
201
2
1
PCH PM Level Shifting
R4762
100K
5%
1/20W
MF
201
BYPASS=U4760::5MM
C4760
0.1UF
X5R-CERM
1
R4763
100K
1/20W
2
5% MF
201
10% 10V
0201
1
2
1
2
6
1A1
8
2A1
4
1DIR
1
1OE*
7
1A2
9
2A2
5
2DIR
16
2OE*
3
U4760
SN74AVC4T245RSV
2
VCCBVCCA
PQFP
1B1 2B1
1B2 2B2
CRITICAL
GND
10
11
BYPASS=U4760::5MM
C4765
1
2
15 13
14 12
0.1UF
10% 10V X5R-CERM 0201
1
R4765
100K
5% 1/20W MF 201
2
PROCHOT Isolation
PP1V8_S5
80
69 47 39
SMC_PROCHOT_L CPU_PROCHOT_LCPU_PROCHOT_OUT_L
1
R4767
100K
5% 1/20W MF 201
2
1
R4766
100K
5% 1/20W MF 201
2
1
2
NC
PP3V3_S5
1
R4768
100K
5% 1/20W MF 201
2
PM_SYSRST_R_L
CRITICAL
R4790
10K
5% 1/20W MF 201
2 1 5
MF1/20W 2015%
BYPASS=U4790::5MM
6
VCC
U4790
74LVC1G07FW5
DFN1010-THICKSTNCL
A
GND
3
Y
4
NCNC
80
R4769
2.2K
1 2
C4790
0.1UF
10%
6.3V
CERM-X5R
0201
NC
PM_SYSRST_LSMC_SYSRST_L PM_PCH_SYS_PWROK
PM_PCH_PWROK PM_RSMRST_L
1
2
R4791
75
1 2
1/20W 201
5% MF
OUT
OUT OUT
C
121 18 12
121 12
121 114 34 18 12
B
6
OUTIN
THRMTRIP# Isolation
A
Qualifier with RSMRST#
PP1V05_S3
6 8 11 46 117
10%
6.3V 0201
1
2
VCC
2
A Y
1
B
5
NC
GND
U4710
74AUP1G08GF
6
SOT891
3
4
CRITICAL
46 39
121 77
C4710
0.1UF
CERM-X5R
SMC_RSMRST_L CPU_VCCST_PWRGD
IN
ALL_SYS_PWRGD
IN
NC
97 47
121 119 116 115 97
OUT
GPU_GFX_OVERTEMP
IN
GPU_RESET_L
IN
80 8
15K
1 2
5%1/20W MF
R4740
201
15K
1 2
5%201 1/20WMF
R4741
R4742
18K
1%
1/20W
MF
201
121 35 20 12
1
R4743
2
121 6
18K
1%
1/20W
MF
201
80
PP1V8_S5
BYPASS=U4740::5MM
C4740
0.1UF
10%
6.3V
CERM-X5R
0201
1
2
1
VDD
U4740
SLG4AP41484
STQFN
PM_THRMTRIP_L
IN
GPU_GFX_OVERTEMP_R
GPU_RESET_L_R
PLT_RST_L
IN
1
2
5 13
CPU_THERMTRIP*_IN
2
GPU_THERMTRIP_IN
3
GPU_RESET*_IN
4
PLT_RST*
OMIT_TABLE
GND
9
CPU_THERMTRIP*_TO_CALPE
THERMTRIP*_TO_PCH
GPU_THERMTRIP_TO_CALPE
GPU_THERMTRIP_TO_H9M
CPU_THERMTRIP*_TO_H9M
NC NC NC
SOC_PM_THRMTRIP_L_R
PP1V05_S3
6 8 11 46 117
PCH_PMTHRMTRIP_L_R
8 12
SOC_GPU_THRMTRIP SMC_GPU_THRMTRIP
10
CPU_SMC_THRMTRIP_L
11 6
7 14
NC NC NC
R4744
15K
1 2
5% 2011/20W MF
R4745
1 2
1/20W MF0201
77
OUT
47
OUT
39
OUT
BOM_COST_GROUP=SOC
SOC_PM_THRMTRIP_L
1
R4747
1K
1% 1/16W MF-LF 402
0
5%
2
PCH_PMTHRMTRIP_L
SYNC_MASTER=ARMIN
PAGE TITLE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
77
OUT
1
R4746
22K
5%
1/20W
MF
201
2
13
OUT
SoC Shared Support
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
47 OF 200
SHEET
46 OF 135
SYNC_DATE=01/17/2019
SIZE
D
A
8
67
35 4
2
1
Page 47
Vinafix.com
D
C
B
120 14
120 14
120 14
120 14
120 14
120 14
120 14
PCIe Up R2D AC Caps
IN IN
IN IN
IN IN
IN
PCIE_SOC_R2D_C_P<0> PCIE_SOC_R2D_C_N<0>
PCIE_SOC_R2D_C_P<1> PCIE_SOC_R2D_C_N<1>
PCIE_SOC_R2D_C_P<2> PCIE_SOC_R2D_C_N<2>
PCIE_SOC_R2D_C_P<3> PCIE_SOC_R2D_C_N<3>
C4820 C4821
C4822 C4823
C4824 C4825
C4826 C4827
(All Caps)
GND_VOID=TRUE
0.22UF
GND_VOID=TRUE GND_VOID=TRUE
0.22UF
GND_VOID=TRUE
0.22UF
GND_VOID=TRUE
0.22UF
GND_VOID=TRUE
0.22UF
GND_VOID=TRUE
0.22UF
0.22UF
0.22UF
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
GND_VOID=TRUE
20%
6.3V 0201
20%
GND_VOID=TRUE
20% 0201
6.3V X5R
GND_VOID=TRUE
6.3V
20% X5R 0201
GND_VOID=TRUE
6.3V
GND_VOID=TRUE
20%
6.3V
GND_VOID=TRUEGND_VOID=TRUE
20% 6.3V 0201
GND_VOID=TRUEGND_VOID=TRUE
20% 02016.3V
X5R
X5R
X5R
X5R
02016.3V
PCIE_SOC_R2D_P<0> PCIE_SOC_R2D_N<0>
PCIE_SOC_R2D_P<1> PCIE_SOC_R2D_N<1>
0201X5R20%
PCIE_SOC_R2D_P<2> PCIE_SOC_R2D_N<2>
0201X5R
PCIE_SOC_R2D_P<3> PCIE_SOC_R2D_N<3>
GPIO Source Termination
40
IN
40
IN
62
IN OUT
40
IN OUT
40
IN
63
IN OUT
40
IN
40
IN
61
IN OUT
40 66 46
IN OUT
40
IN
40
IN
40
IN
122 50 40
47 39
47 39
122 47
46 40 66
40
UART_BT_LH_R2D UART_BT_LH_D2R
40
NC_SWD_WLAN_SWDIO
39
39
NC_SWD_WLAN_SWCLK
40
WLAN_JTAG_TDI
39
NC_SMC_LED_ONEWIRE NC_WLAN_CONTEXT_B
39
OUT IN
40
IN
40
IN
41
IN
41
IN
39
IN
39
IN
IN
IN
OUT
OUT IN
39 49
OUT IN
I2S_SPKRAMP_L_R2D_R I2S_SPKRAMP_L_BCLK_R I2S_SPKRAMP_L_LRCLK_R I2S_SPKRAMP_R_R2D_R I2S_SPKRAMP_R_BCLK_R I2S_SPKRAMP_R_LRCLK_R I2S_CODEC_R2D_R I2S_CODEC_BCLK_R I2S_CODEC_LRCLK_R SPI_TPAD_MOSI_R SPI_TPAD_CLK_R SPI_MESA_MOSI_R SPI_MESA_CLK_R SPI_DFR_MISO_R SPI_DFR_MOSI_R SPI_DFR_CLK_R
SSD0_CLK24M_R SSD1_CLK24M_R
PDM_DMIC_CLK0_R PDM_DMIC_CLK1_R
SPI_AOP_SENSOR_MOSI_R
SPI_AOP_SENSOR_CLK_R
PLACE_NEAR=U3900.AG34:5MM
PLACE_NEAR=U3900.AA32:5MM
PLACE_NEAR=U3900.AA32:10MM
PLACE_NEAR=U3900.C20:5MM
PLACE_NEAR=U3900.C21:5MM
PLACE_NEAR=U3900.C21:10MM
PLACE_NEAR=U3900.AB34:5MM
PLACE_NEAR=U3900.AF33:5MM
PLACE_NEAR=U3900.AF33:5MM
PLACE_NEAR=U3900.N34:5MM
PLACE_NEAR=U3900.P35:5MM
PLACE_NEAR=U3900.A20:5MM
PLACE_NEAR=U3900.C19:5MM
PLACE_NEAR=J5100.7:5MM
PLACE_NEAR=U3900.C18:5MM
PLACE_NEAR=U3900.B18:5MM
PLACE_NEAR=U3900.AP7:5MM
PLACE_NEAR=U3900.AV7:5MM
PLACE_NEAR=U3900.P6:15MM
PLACE_NEAR=U3900.K2:15MM
PLACE_NEAR=U3900.D2:10MM
PLACE_NEAR=U3900.F2:15MM
SPI_AOP_MA781_MISO
PLACE_NEAR=J4802.8:15MM
SPI_TPAD_MISO
PLACE_NEAR=U3900.P36:20MM
SE_HOST_WAKE_R
R4843 R4844 R4863 R4845 R4846 R4864 R4847 R4848 R4865 R4851 R4852 R4853 R4854 R4866 R4855
R4856 R4857
R4858 R4859
R4860
R4812 R4813 R4811
R4809
R4807
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
20 20
20 20
20
20
20
20
0
NO_TEST=1
NO_TEST=1
NO_TEST=1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
NC_SWD_WLAN_SWDIO NC_SWD_WLAN_SWCLK WLAN_JTAG_TDI
I2S_SPKRAMP_L_R2D
1/20W5% MF
I2S_SPKRAMP_L_BCLK I2S_SPKRAMP_L_LRCLK I2S_SPKRAMP_R_R2D
5% MF 2011/20W
I2S_SPKRAMP_R_BCLK
5% 201MF
1/20W
I2S_SPKRAMP_R_LRCLK
5% MF1/20W
I2S_CODEC_R2D
1/20W 201
I2S_CODEC_BCLK
5%
I2S_CODEC_LRCLK
5% MF 2011/20W
SPI_TPAD_MOSI SPI_TPAD_CLK
5% 201MF1/20W
SPI_MESA_MOSI
5%1/20W MF 201
MF1/20W
MF5%
MF 2011/20W
MF1/20W
SPI_MESA_CLK SPI_DFR_MISO
5%
SPI_DFR_MOSI
5%
SPI_DFR_CLK
1/20W
SSD0_CLK24M
5%
SSD1_CLK24M
5% 201
MF1/20W 201
MF5% 201
MF1/20W 201
MF1/20W
201
201MF5%1/20W
2015%
201
2015%
2015% MF1/20W
201MF1/20W
AUD_DMIC0_CLK_CONN
5%
201MF1/20W
AUD_DMIC1_CLK_CONN
5% 1/20W
201MF
SPI_AOP_MA781_MOSI
5% MF
1/20W
12
SPI_AOP_MA781_CLK
1/20W5% MF
12
SPI_AOP_SENSOR_MISO
1/20W
MF5%
SPI_TPAD_MISO_R
12
SE_HOST_WAKE
1/20W5%
MF
201
201
201MF1/20W5%
0201
UART_BT_LH_R2D UART_BT_LH_D2R
NC_SMC_LED_ONEWIRE
NC_WLAN_CONTEXT_B
201
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
36
36
36
OUT OUT
OUT OUT
OUT OUT
OUT OUTIN
IN
62
62
40
63
63
40
61
61
40
48
48
678
* Tentative
120 41
120 41
120 41
120 41
PVT*
EVT*
Proto 3
120 41
120 41
Proto 0a
BOM GROUP BOM OPTIONS
BOARDREV2,BOARDREV1,BOARDREV0BOARD_REV:111
BOARDREV2,BOARDREV1BOARD_REV:110 BOARDREV2,BOARDREV0BOARD_REV:101
BOARDREV2BOARD_REV:100 BOARD_REV:011 BOARDREV1,BOARDREV0 BOARD_REV:010 BOARDREV1 BOARD_REV:001 BOARDREV0 BOARD_REV:000
No Connects
39
NC_GYRO_INT1
39
120 41
120 41 120 14
66 46
122 50
122 50
90 88 47
85 83 47
122 64
122 64
122 47
122 47
47 39
NC_GYRO_INT2 NC_SPI_GYRO_CS_L
39
SPI_AOP_MA781_CS_L
39
NC_ALTIMETER_INT
39
NC_PMU_CLK32K_GNSS_R
77
39
NC_LIDOPEN_PSU12VPGOOD_ACDCBURST_L
LID_OPEN_SMC_IN
39
40
NC_UART_GNSS_D2R_CTS_L
40
NC_UART_GNSS_R2D_RTS_L
NC_GNSS_HOST_TIME
38
NC_GNSS_HOST_WAKE
39
NC_GNSS_DEV_WAKE
38
NC_ENET_MEDIA_SENSE
39
NC_ENET_LOW_PWR
39
NC_I2S_HAWKING_D2R
40
NC_I2S_HAWKING_LRCLK
40
NC_I2S_HAWKING_BCLK
40
NC_I2S_CODEC1_R2D_R
40
NC_PLCAM_RX_CLK12M_R
40
NC_PLCAM_RX_RESET_L
40
NC_PLCAM_TX_CLK12M_R
40
NC_PLCAM_TX_RESET_L
40
NC_PLCAM_TX_INT
40
NC_PLCAM_TX_THROTTLE
38
NC_PLCAM_PROX_INT_L
39
NC_PLCAM_ROMEO_B2B_DETECT
39
NC_PCHROM_SW_EN
40
NC_SDCONN_STATE_CHANGE_L
39
NC_FTCAM_RESET_L
40
NC_FTCAM_CLK12M_R
40
NC_I2S_CODEC_MCLK
40
40
NC_I2S_CODEC1_MCLK
39
NC_SPI_DESCRIPTOR_OVERRIDE_L NC_I2C_AOP_SCL
39
NC_I2C_AOP_SDA
39
38
NC_SOC_USB_ID
38
NC_SOC_AMUXOUT
NC_SPKR_ID1
40
NC_SPKR_ID0
40
NC_PCIEDN_WAKE_L
39
NC_MESA_MENUKEY_L
39
NC_AUD_PWR_EN
77
NC_PCIE_CLK100M_DN2P
41
41
NC_PCIE_CLK100M_DN2N
41
NC_PCIEDN2_CLKREQ_L NC_PCIEDN2_RESET_L
41
NC_UART_BT_R2D
40
40
NC_UART_BT_D2R NC_UART_BT_R2D_RTS_L
40
NC_UART_BT_D2R_CTS_L
40
NC_PCIE_DN2_R2D_CP
41
NC_PCIE_DN2_R2D_CN
41
41
NC_PCIE_DN2_D2RP NC_PCIE_DN2_D2RN
41
NC_TPAD_ACTUATOR_DISABLE_L
39
NC_WLAN_CONTEXT_A
39
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
NO_TEST=1 NO_TEST=1 NO_TEST=1
NO_TEST=1 NO_TEST=1
NO_TEST=1
NC_GYRO_INT1 NC_GYRO_INT2 NC_SPI_GYRO_CS_L SPI_AOP_MA781_CS_L NC_ALTIMETER_INT
NC_PMU_CLK32K_GNSS_R
NC_LIDOPEN_PSU12VPGOOD_ACDCBURST_L
LID_OPEN_SMC_IN NC_UART_GNSS_D2R_CTS_L NC_UART_GNSS_R2D_RTS_L
NC_GNSS_HOST_TIME NC_GNSS_HOST_WAKE
NC_GNSS_DEV_WAKE NC_ENET_MEDIA_SENSE NC_ENET_LOW_PWR NC_I2S_HAWKING_D2R NC_I2S_HAWKING_LRCLK NC_I2S_HAWKING_BCLK NC_I2S_CODEC1_R2D_R
NC_PLCAM_RX_CLK12M_R NC_PLCAM_RX_RESET_L NC_PLCAM_TX_CLK12M_R NC_PLCAM_TX_RESET_L NC_PLCAM_TX_INT NC_PLCAM_TX_THROTTLE NC_PLCAM_PROX_INT_L NC_PLCAM_ROMEO_B2B_DETECT NC_PCHROM_SW_EN
NC_SDCONN_STATE_CHANGE_L
NC_FTCAM_RESET_L NC_FTCAM_CLK12M_R NC_I2S_CODEC_MCLK NC_I2S_CODEC1_MCLK
NC_SPI_DESCRIPTOR_OVERRIDE_L
NC_I2C_AOP_SCL NC_I2C_AOP_SDA NC_SOC_USB_ID
NC_SOC_AMUXOUT
NC_SPKR_ID1
NC_SPKR_ID0
NC_PCIEDN_WAKE_L NC_MESA_MENUKEY_L
NC_AUD_PWR_EN NC_PCIE_CLK100M_DN2P NC_PCIE_CLK100M_DN2N NC_PCIEDN2_CLKREQ_L NC_PCIEDN2_RESET_L
NC_UART_BT_R2D
NC_UART_BT_D2R
NC_UART_BT_R2D_RTS_L
NC_UART_BT_D2R_CTS_L NC_PCIE_DN2_R2D_CP NC_PCIE_DN2_R2D_CN NC_PCIE_DN2_D2RP NC_PCIE_DN2_D2RN NC_TPAD_ACTUATOR_DISABLE_L NC_WLAN_CONTEXT_A
47
NC_WLAN_CLKREQ_L
41
NC_WLAN_PERST_L
41
NC_PCIE_ENET_R2D_C_P
122 47
41
NC_PCIE_ENET_R2D_C_N
41
NC_PCIE_ENET_D2R_P
41
NC_PCIE_ENET_D2R_N
41
NC_PCIE_CLK100M_ENET_P
41
NC_PCIE_CLK100M_ENET_N
41
NC_PCIE_CLK100M_WLAN_P
41
NC_PCIE_CLK100M_WLAN_N
41
NC_PCIE_DN3_R2D_CN
41
NC_PCIE_DN3_D2RP
41
NC_PCIE_DN3_D2RN
41
NC_PCIE_CLK100M_DN3P
41
NC_PCIE_CLK100M_DN3N
41
NC_PCIEDN3_CLKREQ_L
41
NC_PCIEDN3_RESET_L
41
NC_PCIE_WLAN_R2D_C_P
41
NC_PCIE_WLAN_R2D_C_N
41
NC_PCIE_WLAN_D2R_P
41
NC_PCIE_WLAN_D2R_N
41
NC_SOC_VSSCPU_SENSE
42
NC_SOC_VSSSOC_SENSE
42
NC_DFR_TOUCH_RSVD
40
NC_PCIE_DN3_R2D_CP
41
NC_TPAD_VIBE_L
39
NC_ENET_RESET_L
41
NC_WLAN_DEV_WAKE
38
3 245
PP1V8_G3S
PP1V8_SLPS2R
PP1V8_AWAKE
R4883 R4884 R4887 R4888 R4889 R4890 R4891 R4892 R4895
R3611 R3612 R3613 R4820
R4885 R4886 R4893 R4894
R4870
47K 47K 47K 47K 47K 47K 47K 47K
100K
100K 100K 100K 100K
100K
47K
100K
47K
0
1 2 1 2 1 2 1 2 1 2 1 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE MAKE_BASE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
38 80
41 46 80
5% MF1/20W 201
1/20W MF5% 201
5% 1/20W MF 201
MF5% 1/20W 201
2
1/20W5% MF 5% 1/20W 201MF 5% 1/20W
1/20W5% MF
1/20W 2015% MF 5% 2011/20W 5% 201MF1/20W
5% 2011/20W MF
1/20W5% 201 5%
1/20W5% MF 0201
MF 201
MF1/20W5% 201
MF1/20W5% 201
MF
MF MF 2011/20W MF 2011/20W5%
42
77 42
92 91 90 89 88
87 86 85 84 83
69 47 46 39
77 68
122 47
SOC_VDDSOC_SENSE
IN
SOC_VDDCPU_SENSE
IN
SSD0_OCARINA_WP_L
IN
SSD1_OCARINA_WP_L
IN
SMC_PROCHOT_L
IN
IN
IN
CHGR_INT_L ANGLE_SENSOR_MGL
INT PU SOC 50k
SMC_FIXTURE_MODE_L
39
NC_WLAN_CLKREQ_L NC_WLAN_PERST_L NC_PCIE_ENET_R2D_C_P NC_PCIE_ENET_R2D_C_N NC_PCIE_ENET_D2R_P NC_PCIE_ENET_D2R_N NC_PCIE_CLK100M_ENET_P NC_PCIE_CLK100M_ENET_N NC_PCIE_CLK100M_WLAN_P NC_PCIE_CLK100M_WLAN_N
NC_PCIE_DN3_R2D_CN NC_PCIE_DN3_D2RP NC_PCIE_DN3_D2RN NC_PCIE_CLK100M_DN3P NC_PCIE_CLK100M_DN3N NC_PCIEDN3_CLKREQ_L NC_PCIEDN3_RESET_L NC_PCIE_WLAN_R2D_C_P NC_PCIE_WLAN_R2D_C_N NC_PCIE_WLAN_D2R_P NC_PCIE_WLAN_D2R_N NC_SOC_VSSCPU_SENSE NC_SOC_VSSSOC_SENSE NC_DFR_TOUCH_RSVD NC_PCIE_DN3_R2D_CP NC_TPAD_VIBE_L NC_ENET_RESET_L NC_WLAN_DEV_WAKE
122 121 118 49
SSD0_CLKREQ0_L SSD0_CLKREQ1_L SSD0_CLKREQ2_L SSD0_CLKREQ3_L SSD1_CLKREQ0_L
201
SSD1_CLKREQ1_L SSD1_CLKREQ2_L SSD1_CLKREQ3_L
201
SSD_PMU_RESET_L SPI_AOP_SENSOR_MOSI_R
SPI_AOP_SENSOR_CLK_R SPI_AOP_SENSOR_MISO SPI_AOP_MA781_CS_L
SSD0_PCIE_RESET_L SSD0_CLK24M SSD1_PCIE_RESET_L SSD1_CLK24M I2S_SPKRAMP_R_D2R
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
121
SMC_FIXTURE_MODE_L
MAKE_BASE
83 41
85 41
86 41
47 39
47 39
122 47
40
P5MM-SP
P5MM-SP
123 88 41
123 89 41
123 90 41
123 91 41
123 84 41
121 92 87 38
47 39
90 88 47
85 83 47
SM
SM
91 90 89 88 41
86 85 84 83 41
P3MM
P3MM
SM-SP
SM-SP
P3MM
P2MM P2MM
SM
SM
SM
1
1
PP
PP4800
1
PP
PP4801
1
PP
PP4802
1
PP
PP4803
1
PP
PP4808
1
PP
PP4809
PP
PP4810
D
FIXMODE_NO
1
R4801
100K
5% 1/20W MF 201
2
C
B
A
47 80
PPBUS_G3H
117
PP3V3_S5
BYPASS=U4801::5MM
1
R4802
665K
0.1% 1/20W TK 0201
2
PBUS_DIVIDER_REF
47
PBUS_DIVIDER
1
R4800
127K
0.1% 1/20W MF 0201
2
Droop Circuit
PP3V3_S5
47 80
10%
6.3V 0201
NOSTUFF
1
C4805
10%
2
1
2
3
1
0.1UF
6.3V CERM-X5R
0201
VCC+
GND
U4801
5
LMV331
SC70-5
CRITICAL
2
80
IN
4
NC NC NC
C4804
0.1UF
CERM-X5R
R4806
100K
5% 1/20W MF 201
UVP_DIS_L PBUS_DIVIDER_OUT
BYPASS=U4800::5MM
C4803
1
2
ENABLE
9
COMP_INPUT
5 8
NC
11
0.1UF
10%
6.3V
CERM-X5R
0201
1
2
1
VDD
U4800
SLG4AP41473
STQFN
CRITICAL
DUMMY_OUTPU_COMP
THROTTLE*_TEST_OUTPUT
GND
7
VREF_1V2 CPU_THROTTLE* GPU_THROTTLE*
Signal Aliases
TPAD_KBD_WAKE_L
39
TPAD_SPI_INT_L
39
GPU_GFX_OVERTEMP
SMC_GPU_THRMTRIP
39
SOC_KBD_BKLT_PWM
38
40
40
40
40
40
40
40
40
32
NC
10
PBUS_DIVIDER_REF
12
SMC_PROCHOT_L
6
GFX_THROTTLE_1V8_R_L
4
U4800_PIN4
TP-P5
1
TP
TP4808
OUT
47
4639 6947
0201
NOSTUFF
R4803
GND GND GND GND GND GND GND GND
1/20WMF
0
12
GFX_THROTTLE_1V8_L
5%
MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE
OUT
119
TPAD_KBD_WAKE_L TPAD_SPI_INT_L GPU_GFX_OVERTEMP SMC_GPU_THRMTRIP SOC_KBD_BKLT_PWM
122 47
122 47
122 47
122 47
ANGLE_SENSOR_ND SPI_AOP_MA781_CS_L ANGLE_SENSOR_MGL
SPI_AOP_MA781_CLK
MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE
66
46
81
122 66
97 46
Note GPIO4 = LID_OPEN_SMC_IN
ANGLE_SENSOR_ND
122 47
ANGLE_SENSOR_MGL
Lid Detect Sensors
J4802
503548-1220
516S0873
F-ST-SM
13 14
1 2 3 4 5 6 7 8 9 10
11 12
15 16
BYPASS=J4802::5MM BYPASS=J4802::5MM
1
C4830
1.0UF
20%
6.3V
2
X5R 0201-1
PP3V3_G3H_RTC_X PP1V8_SLPS2R
SPI_AOP_MA781_MISO
SPI_AOP_MA781_MOSI
1
C4831
1.0UF
20%
6.3V
2
X5R 0201-1
PP1V8_SLPS2R
80
1
R4899
2
BOM_COST_GROUP=SOC
10K
5% 1/20W MF
201
2
1
118
80
BYPASS=U4802::5MM
C4802
0.1UF
CERM-X5R
6
SOT891
NC
NC
SYNC_MASTER=ANDY SYNC_DATE=02/19/2019
PAGE TITLE
4
U4802
35
74LVC1G32
1
10%
2
6.3V 0201
IPD_LID_OPEN
122 66 64 50
R4896
1K
12
LID_OPEN_SMC_IN
MF1/20W 5% 201
47
SoC Project Support
122 47
Apple Inc.
122 47
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
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1
MESA FLEX CONNECTOR
D
ESD Filters
ISOLATE FROM OTHER COMPONENTS/NETS AS MUCH AS POSSIBLE
48
PP1V8_MESA
1
R4924
100K
5% 1/20W MF
40
38
OUT
OUT
SPI_MESA_MISO
MESA_INT
48
MESA_BOOST_EN
2
201
R4912
0
1 2
5%
1/20W
MF
0201
R4953
680
1 2
5%
1/20W
MF
201
R4954
680
1 2
5%
1/20W
MF
201
C4952
1
56PF
5% 25V
2
NP0-C0G 0201
C4953
1
100PF
5%
2
25V C0G 0201
C4954
1
100PF
5% 25V
2
C0G 0201
122
122 48
MLB = RECEPTACLE = 516S00203 FLEX = PLUG = 516S00115
PP3V0_MESA_FILT_CONN
SPI_MESA_MISO_CONN MESA_INT_CONN MESA_BOOST_EN_CONN
NC_TP_J4900_8
122
NC_TP_J4900_10
122
516S00203
J4900
505066-1222
F-ST-SM1
1314
12 34 56 78 910 1112
1516
PP1V8_MESA_FILT_CONN
PMU_ONOFF_R_L_CONN SPI_MESA_MOSI_CONN SPI_MESA_CLK_CONN PP16V0_MESA_FILT_CONN
ESD Filters
OPTIONS ARE TO CATER FOR MESA MODULE PIN 5&7 DIFFEENCES
ISOLATE FROM OTHER COMPONENTS/NETS AS MUCH AS POSSIBLE
PP3V3_G3H_T
48 118
PMU_LDO3_OUT_R
122 48
C4950
122 48
56PF
NP0-C0G
0201
5%
25V
1
2
R4955
12
5% 1/20W0MF 0201
R4956
0
12
C4955
100PF
5% 25V C0G
0201
1
2
5% MF1/20W
0201
76
PP1V8_SLPS2R
80
PMU_ONOFF_R_L
SPI_MESA_MOSI
C4956
NOSTUFF
1
R4971
100K
5% 1/20W MF 201
2
47
IN
1
R4914
100K
5% 1/20W MF 201
2
NOSTUFF
1
R4915
100K
5% 1/20W MF 201
2
1
2
1
0.1UF
10% 10V
2
X5R-CERM 0201
U4901
74AUP1T97
5
SOT891
4
6
3
TO SMC-RESET & PMIC 3V3 LEVELS
PMU_ONOFF_L
OUT
135 122 77 67
D
R4951
C4951
56PF
5% 25V
NP0-C0G
0201
56
12
5%
1
2
1/20W
MF
201
SPI_MESA_CLK
47
IN
C
MESA POWER SEQUENCING REQUIREMENTS: Power On: 1V8 -> 3V3 -> 16V0
Output Voltage
Iout (max avg)
OCP (min)
Active Discharge
Max Output Cap
16.0V +/- 2%
6mA
13 mA
15 mA sink
0.5uF @ 16V
C4910
10UF
CERM-X5R
0402-9
BYPASS=U4900.A2::4MM
PLACE_NEAR=U4900:5MM
L4901
1.0UH-0.4A-0.636OHM
1 2
0402
20%
6.3V
1
2
MESA_BOOST_EN
48
FROM MODULE MOJAVE HAS IPD
MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.449 DIDT=TRUE
PP3V3_G3H_MESA_SW
1
R4923
100K
5% 1/20W MF 201
2
MOJAVE 16V BOOST
U4900
LM3638A0
BGA
B1
SW A2 C3 B2
A3 C2
VIN
EN_M
EN_S
LDOIN
AGNDPGND
B3
A1
PP17V0_MOJAVE_LDOIN
VOUT
PMID
C1
1
C4923
2.2UF
20%
2
25V X5R 0402-3
Load Cap:6.6uF nom EDP:13.75mA
C4924
1
2.2UF
20%
2
25V X5R 0402-3
C4925
1
2.2UF
20% 25V
2
X5R 0402-3
VOLTAGE=16V MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
PP16V0_MESA
C4926
1
56PF
5%
2
25V NP0-C0G 0201
BYPASS=U4900.C3::3MM BYPASS=U4900.C3::4MM BYPASS=U4900.C3::6MM
EMC Filter
VOLTAGE=16V MIN_LINE_WIDTH=0.2000
FL4900
80-OHM-25%-500MA
1 2
0201
MIN_NECK_WIDTH=0.1200
PP16V0_MESA_FILT_CONN
1
C4927
100PF
5% 25V C0G
2
0201
C
122 48
B
A
Output Voltage
Iout (max avg)
Dropout Voltage
OCP (min)
Active Discharge
Output Voltage
Iout (max avg)
Dropout Voltage
OCP (min)
Active Discharge 230 Ohm Typ
Max Output Cap
PP3V3_G3H_T
48 118
3.0V +/- 2%
250mA
155mV
250 mA
280 Ohm Typ
1.825V +/- 2%
250mA
50mV Typ @ 100mA
250 mA
10uF
1
C4912
1UF
10%
2
10V X5R-CERM 0402
BYPASS=U4920.4::3MM
BYPASS=U4910.4::10MM
C4911
1
1UF
10%
2
10V X5R-CERM 0402
1.8V MESA
U4920
LP5907SNX-1.825
X2SON-COMBO-THICKSTNCL
4 1
VIN
EN
3
3.0V MESA
U4910
NCP160AMX300
4
IN
3
EN
VOUT
EPADGND
2
5
XDFN-COMBO-THICKSTNCL
EPADGND
5
2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.89
Load Cap:3.4uF nom EDP:0.5mA
48
PP1V8_MESA
BYPASS=U4920.1::3MM
1
C4914
1UF
10%
2
10V X5R-CERM 0402
OUT
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.0V
Load Cap:14.3uF nom EDP:100mA
PP3V0_MESA
1
BYPASS=U4910.1::10MM
C4916
1
1UF
10% 10V
2
X5R-CERM 0402
EMC Filter
80-OHM-25%-500MA
1
C4918
2.2UF
20%
2
6.3V X5R-CERM 0201
C4920
1
2.2UF
20%
2
6.3V X5R-CERM 0201
FL4920
1 2
0201
C4921
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
1
C4917
100PF
5% 25V C0G
2
0201
EMC Filter
FL4910
80-OHM-25%-500MA
1 2
C4922
1
2.2UF
20%
2
6.3V X5R-CERM 0201
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.89
PP1V8_MESA_FILT_CONN
0201
C4928
1
0.1UF
10% 10V
2
X6S-CERM 0201
122 48
VOLTAGE=3.0V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PP3V0_MESA_FILT_CONN
C4929
1
100PF
5%
2
25V C0G 0201
B
122 48
SYNC_MASTER=ARMIN SYNC_DATE=01/17/2019
PAGE TITLE
A
8
PP1V8_G3S
118
38
IN
MESA_PWR_EN
1
R4922
100K
5% 1/20W MF 201
2
MESA
SIZE
D
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
BOM_COST_GROUP=T151
67
35 4
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
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1
VENUS
D
PP1V8_G3S
49 118
PP3V3_G3S_T
118
BYPASS=U5000::10MM
20%
6.3V X5R
20%
6.3V 0201
1
2
1
2
C5094
1.0UF
0201-1
BYPASS=U5000::10MM
C5051
2.2UF
X5R-CERM
BYPASS=U5000::10MM
10% 10V
0201
20%
6.3V 0201
1
2
1
2
C5008
0.1UF
X5R-CERM
BYPASS=U5000::10MM
C5001
2.2UF
X5R-CERM
BYPASS=U5000::3MM
10% 10V
0201
20%
6.3V X5R
1
2
1
2
C5091
0.1UF
X5R-CERM
BYPASS=U5000::10MM
C5002
1.0UF
0201-1
PP_VDD_SE_VDDA PP_VDD_SE_VDDC
VOLTAGE=1.8V
PP_VDD_SE_VDDNV
BYPASS=U5000::5MM
20%
6.3V X5R
0201
1
PP_VDD_SE_VDDPLL
MIN_NECK_WIDTH=0.0850
2
MIN_LINE_WIDTH=0.0920
PP_VDD_SE_VHV
C5093
0.22UF
PP_VDD_SE_VREF
BYPASS=U5000::6MM
B5B6B7
NCNCNC
A6A7A8
E1
A3
H5
B1
NC
C2
C1
C3
E5
B3
H2
NC
H3C4F1
D2
NC
G1
VOLTAGE=1.1V
VOLTAGE=1.8V
VOLTAGE=1.8V
VOLTAGE=1.8V VOLTAGE=0.9V
1
C5016
0.1UF
10% 10V
2
X5R-CERM 0201
BYPASS=U5000::3MM
1
C5017
0.22UF
20%
6.3V
2
X5R 0201
BYPASS=U5000::6MM
1
C5013
0.22UF
20%
6.3V
2
X5R 0201
BYPASS=U5000::5MM
1
C5019
0.22UF
20%
6.3V
2
X5R 0201
BYPASS=U5000::7MM
1
C5020
0.22UF
20%
6.3V
2
X5R 0201
D
C
49 38
Always on GPIOs
IN
R5012 R5013
49 118
SE_CTLR_FW_DWLD
47K 47K
1 2 1 2
PP1V8_G3S
1/20W
1
R5015
22K
5%
1/20W
MF
201
2
MF 5%201 MF1/20W 5%
49 40
49 40
49 40
49 40
49 38
201
IN
OUT
IN
OUT
OUT
IN
SE_GPIO2_AO SE_GPIO3_AO
UART_SE_R2D_RTS_L UART_SE_D2R_CTS_L UART_SE_R2D UART_SE_D2R
SE_HOST_WAKE
SE_DEV_WAKE
NC
NC NC
NC NC NC
H8
NFC_CLK_REQ
J8
NFC_DWL_REQ
E4
NFC_GPIO0
F3
NFC_GPIO1
G6
NFC_GPIO2_AO
G5
NFC_GPIO3_AO
F2
NFC_HSU_CTS
F5
NFC_HSU_RTS
E3
NFC_HSU_RX
F4
NFC_HSU_TX
H7
NFC_IRQ
A5
NFC_SIM_SWIO1
B8
NFC_SIM_SWIO2
C8
NFC_SIM_SWIO3
G7
NFC_WKUP_REQ
G3
NFC_CLK_32K
PMUVCC3
PMUVCC2
PMUVCC1
SIMVCC1
SIMVCC2
SIMVCC3
VBAT
VBATPWR
VDDA
VDDC
VDDCIN
VDDBOOST
VDDIO
VDDIO_SE
U5000
SN100VUK-B20147
WLCSP-1
OMIT_TABLE
DIS SEDIG NFC
VDDPA
VDDNV
VHV
VDDPLL
SE_I2C_SCL SE_I2C_SDA
SE_ISO_CLK
SE_ISO_RST
SE_SPI_CLK
SE_SPI_MISO SE_SPI_MOSI
VUP
VREF
SE_GPIO0 SE_GPIO1
SE_ISO_IO
SE_SPI_CS
BOOST_LX
F8 D4
G8 F7
D6 D7 D3
E8 E6 E7 D5
A1
TP_SE_GPIO0 TP_SE_GPIO1
TP_SE_I2C_SCL TP_SE_I2C_SDA
NC NC NC
NC NC NC NC
NC
C
B
77 49
SE_PWR_EN
IN
R5010 R5011
10K 10K
SE_XTAL1
Avoid false wakeup
1 2 1 2
2015% 1/20W MF 2011/20W5% MF
NC NC
NC
SE_RXP SE_RXN
NC NC
NC NC
NC
H6
NFC_XTAL1
B4
NFC_SIM_SWCTRL1
C6
NFC_SIM_SWCTRL2
J7
NFC_XTAL2
J5
RXP
J4
RXN
J1
TX1
J3
TX2
G2
TXVCASC
H1
TXVCM VEN
J6
VTUNE
ANALOG SIGNAL
VSS_DIG
VSS_DIG
VSS_DIG
C5C7D8
VSS_NFC
VSS_PA
J2
G4
VSS_PLL
VSS_PMU
H4
D1
VSS_PWR
VSS_PWR
A2
B2
VSS_SUB
VSS_REF
E2
A4
B
VSS_SUB
F6
A
PP1V8_G3S
R5001 R5002 R5003 R5004
R5000 R5005 R5006
8
100K 100K 100K 100K
100K 100K 100K
1 2 1 2 1 2 1 2
1 2 1 2
1 2
122 121 118 47
5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201
5% 1/20W MF 201
MF1/20W5% 201 MF1/20W5% 201
UART_SE_R2D UART_SE_D2R UART_SE_R2D_RTS_L UART_SE_D2R_CTS_L
SE_CTLR_FW_DWLD SE_DEV_WAKE SE_PWR_EN
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
998-15216 U5000 CRITICAL SE:DEV_2019
1
338S00445 1
49 40
49 40
49 40
49 40
49 38
49 38
77 49
67
IC,SN100V,DEV,B2,WLCSP72
IC,SN100V,PROD,B2,WLCSP72
U5000 SE:PROD_2019CRITICAL
SYNC_DATE=02/19/2019SYNC_MASTER=ANDY
PAGE TITLE
A
SECURE ELEMENT
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
35 4
IV ALL RIGHTS RESERVED
2
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49 OF 135
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D
C
122 66 64 47
IPD_LID_OPEN
PP5V_G3S118
R5102
100K
1/20W
5% MF
201
12
IPD_LID_OPEN_R
L5199
1.2UH-20%-0.12A-1.17OHM
1 2
0402
C5100
1
G
122 50
122 40
122 47
122 50 40
4.7UF
20% 25V X5R
0402
2
S
D
3
DFR_LID_OPEN_L
122
TP_DFR_TOUCH_RSVD
SPI_DFR_CS_L
IN IN
I2C_DFR_SCL_R
52
52
I2C_DFR_SDA_R DFR_TOUCH_RESET_L
IN
122 52 50
1
2
PP1V8_SLPS2RSW_DFR PP5V_G3S_DFR_FILT
VOLTAGE=5V
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
PP1V8_SLPS2RSW_DFR
Q5100
DMP31D0UFB4
DFN1006H4-3
C5101
4.7UF
20% 25V X5R
0402
122 52 50
DFR Touch Conn
J5100
AA07-S022VA1
F-ST-SM
1
2
24 23
12 34 56 78 910 1112 1314 1516 1718 1920 2122
25 26
TP_DFR_TOUCH_PANEL_DETECT DFR_DISP_VSYNC
SPI_DFR_MISO_R SPI_DFR_CLKSPI_DFR_MOSI
DFR_TOUCH_INT_L DFR_TOUCH_CLK32K_RESET_L
TP_DFR_TOUCH_ROM_WC PP1V8_SLPS2RSW_DFR
122
OUT
OUT
122
D
122 50
122 50 47
IN
IN
122 47
122 50 39
122 40
122 52 50
C
B
50 118
122 52 50
PP3V3_G3H_DFR
P1V8_SLPS2RSW_DFR_R
PP1V8_SLPS2RSW_DFR
Slew Rate
R(on) @ 3.3V
Current
Load Cap
R5112
24K
1 2
5%
1/20W
MF
201
2.5V/ms
43 mOhm Typ 55 mOhm Max
1A Max
22.2uF nom
U5111
SLG5AP1449V
STDFN
1
ON
GND
4
DFR Disp Conn
J5110
DF40SG(1.5)-26DS-0.4V
122 50
122 40
122 38
122 50 40
2
D
3
S
OUT
OUT
IN
122
DFR_DISP_VSYNC
DFR_DISP_TE
DFR_DISP_INT DFR_DISP_RESET_L
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
EDP: 145mA
PP3V3_G3HSW_DFR
C5110
0.1UF
10%
6.3V X5R
0201
1
2
F-ST-SM
GND
122
122
GND
122
122
GND
GND
2728
12
34 56
78
910 1112
1314
1516 1718 1920 2122 2324
2526
2930
GND_VOID=TRUE
MIPI_DFR_CLK_CONN_FILT_P MIPI_DFR_CLK_CONN_FILT_N
GND_VOID=TRUE
GND_VOID=TRUE
MIPI_DFR_DATA_CONN_FILT_P MIPI_DFR_DATA_CONN_FILT_N
GND_VOID=TRUE
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
PP1V8_SLPS2RSW_DFR
I2C_DFR_SCL_R I2C_DFR_SDA_R
C5111
1
1.0UF
20%
6.3V
2
X5R 0201-1
EDP: 57mA
IN
BI
GND_VOID=TRUE GND_VOID=TRUE
52
52
L5110
3.25-OHM-0.1A-2.4GHZ TAM0605-4SM
4
3.25-OHM-0.1A-2.4GHZ
4
GND_VOID=TRUE
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
SYM_VER-2
L5111
TAM0605-4SM
SYM_VER-2
PLACE_NEAR=J5110:5mm
1
23
1
GND_VOID=TRUE GND_VOID=TRUEGND_VOID=TRUE
23
1
C5171
1UF
10%
10V
2
X5R-CERM 0402
MIPI_DFR_CLK_P MIPI_DFR_CLK_N
GND_VOID=TRUE GND_VOID=TRUE
MIPI_DFR_DATA_P MIPI_DFR_DATA_N
1
C5103
1UF
10%
10V
2
X5R-CERM 0402
40
IN
40
IN
40
IN
40
IN
U5104
NCP160AMX180
XDFN-COMBO-THICKSTNCL
OUT
1
EPAD GND
5
2
IN
EN
PP3V3_G3H_DFR
4 3
DFR_PWR_EN_R
C5104
1UF
20%
16V
CER-X5R
0201
1
2 1/20W
1
R5101
100K
5% MF
201
2
1
2
R5111
1 2
50 118
C5102
1UF
10%
10V
X5R-CERM 0402
1K
5%
1/20W
MF
201
DFR_PWR_EN
B
38
IN
A
122 52 50
50 40
122
122 50 39
122 50 47
122 50 40
122 50
PP1V8_SLPS2RSW_DFR
DFR_TOUCH_RESET_L DFR_TOUCH_INT_L SPI_DFR_MISO_R DFR_DISP_RESET_L DFR_LID_OPEN_L
1
R5103
4.7K
5% 1/20W MF 201
2
1
R5106
100K
5% 1/20W MF 201
2
1
R5104
100K
5% 1/20W MF 201
2
1
R5107
100K
5% 1/20W MF 201
2
1
R5105
100K
5% 1/20W MF 201
2
BOM_COST_GROUP=T151
PAGE TITLE
DFR Support
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
51 OF 200
SHEET
50 OF 135
SIZE
D
A
SYNC_DATE=01/17/2019SYNC_MASTER=ARMIN
8
67
35 4
2
1
Page 51
Vinafix.com
678
3 245
1
D
51 39
51 80
PP1V8_S5
SMC (SoC)
U3900
(MASTER)
I2C_SNS0_S0_SCL
MAKE_BASE=TRUE
I2C_SNS0_S0_SDA
MAKE_BASE=TRUE
SMC I2C "1" S0 Connections
R5205
R5206
2.2K
5% 1/16W MF-LF
402
1
1
2.2K
5% 1/16W MF-LF 402
2
2
51
LEVEL
SHIFTER
I2C_SNS0_S0_5V_SCL
MAKE_BASE=TRUE
I2C_SNS0_S0_5V_SDA
51
MAKE_BASE=TRUE
EADC1
U5700
(Write: 0x10 Read: 0x11)
I2C_SNS0_S0_5V_SCL
I2C_SNS0_S0_5V_SDA
EADC2
U5710
(Write: 0x12 Read: 0x13)
I2C_SNS0_S0_5V_SCL
SMC I2C "3" S0 Connections
51 80
PP1V8_S5
PP1V8_S5
51 80
C5210
1
0.1UF
10%
6.3V
R5216
SMC (SoC)
U3900
(MASTER)
56
56
I2C_DISP_SCL
39
MAKE_BASE=TRUE
I2C_DISP_SDA
39
MAKE_BASE=TRUE
R5215
2.2K
5%
1/20W
MF
201
1
1
2.2K
5% 1/20W MF 201
82
2
2
PANEL_P3V3_EN
IN
I2C_DISP_SCL I2C_DISP_SDA
2
CERM-X5R 0201
1
VCCA
U5210
TXS0102DQM
5
OE A1
2
A2
3
X2SON
CRITICAL
8
VCCB
B1
B2
GND
4
PP3V3_S0SW_LCD
C5211
1
0.1UF
10% 10V X5R-CERM
2
0201
7 6
R5218
1
2.2K
5%
1/20W
MF
2
201
122 82
1
R5219
2.2K
5% 1/20W MF
2
201
Internal DP
J8500
16 addresses
(Write: 0x20 Read: 0x21)
thru
(Write: 0x3E Read: 0x3F)
( when VRR_FLAG = 0 )
I2C_TCON_SCL I2C_TCON_SDA
122 82 51 39
D
122 82
GMUX IOEXP
U9801
(WRITE 0X44 READ 0X45)
56
I2C_DISP_SCL
95
C
51 80
LOADISNS
R5270
100K
5%
1/20W
MF
201
51 39
51 39
PP1V8_S5
1
C5270
1
2
0.1UF
10%
6.3V CERM-X5R
2
0201
LOADISNS MLBSNS_I2CLS_EN I2C_SNS0_S0_SCL
I2C_SNS0_S0_SDA
SMC I2C "2" S0 Connections
1
VCCA
U5270
TXS0102DQM
5
OE A1
2
A2
3
X2SON
CRITICAL
LOADISNS
GND
VCCB
4
PP5V_G3S
LOADISNS
C5271
0.1UF
10% 10V X5R-CERM 0201
8
B1
7
B2
6
NOSTUFF
1
R5278
2
CKPLUS_WAIVE=I2C_PULLUP CKPLUS_WAIVE=I2C_PULLUP
1
2.2K
5%
1/20W
MF
201
2
118
NOSTUFF
1
R5279
2.2K
5% 1/20W MF 201
2
I2C_SNS0_S0_5V_SCL
51
I2C_SNS0_S0_5V_SDA
I2C_SNS0_S0_5V_SDA
56
I2C_DISP_SDA
SMC I2C "4" G3H Connections
PP1V8_SLPS2R
80
5%
1/20W
MF
201
1
2
121 39
121 39
SMC (SoC)
U3900
(MASTER)
I2C_PWR_SCL
MAKE_BASE=TRUE
I2C_PWR_SDA
MAKE_BASE=TRUE
R5220
4.7K
R5221
1
4.7K
5% 1/20W MF 201
2
95
Battery
J6950
(Write:0x16 Read:0x17) I2C_PWR_SCL I2C_PWR_SDA
67 121
67 121
C
B
PP1V8_S5
51 80
SMC (SoC)
U3900
(MASTER)
I2C_SNS1_S0_SCL
39
MAKE_BASE=TRUE
I2C_SNS1_S0_SDA
39
MAKE_BASE=TRUE
TBT LEFT THERM
TMP461: U5850
(Write: 0x98 Read: 0x99)
I2C_SNS1_S0_SCL
57
57
I2C_SNS1_S0_SDA
R5250
2.2K
5%
1/20W
MF
201
R5251
1
2
1
2.2K
5% 1/20W MF 201
2
CPU, Mem, Airflow,
Fixstack Prox
WLAN,FB
TMP468:U5870
(Write: 0x90 Read: 0x91)
I2C_SNS1_S0_SCL
I2C_SNS1_S0_SDA
57
57
PP1V8_G3S
118
SMC (SoC)
U3900
(MASTER)
I2C_SNS_G3S_SCL
39
MAKE_BASE=TRUE
I2C_SNS_G3S_SDA
39
MAKE_BASE=TRUE
SMC I2C "5" G3S Connections
R5225
2.2K
5% 1/16W MF-LF
402
1
2
1
R5226
2.2K
5% 1/16W MF-LF
2
402
(WRITE: 0X98 READ: 0X99)
I2C_SNS_G3S_SCL I2C_SNS_G3S_SDA
Trackpad
J6800
(See trackpad)
(10K IPU)
(10K IPU)
66
66
CALPE
U7800
(Write:0xE8 Read:0xE9)
I2C_PWR_SCL
77
I2C_PWR_SDA
77
SMC I2C "6" G3H Connections
Battery Charger
U7000 (Write:0x12 Read:0x13) I2C_PWR_SCL
I2C_PWR_SDA
68
68
SSD 0
TBT RIGHT THERM
TMP461: U5800
(Write: 0x96 Read: 0x97)
I2C_SNS1_S0_SCL
I2C_SNS1_S0_SDA
57
57
SMC I2C "0" G3H Connections
80
PP1V8_SLPS2R
SMC (SoC)
U3900
(MASTER)
I2C_UPC_SCL
39 121
MAKE_BASE=TRUE
39
I2C_UPC_SDA
121
MAKE_BASE=TRUE
39 33
UPC_I2C_INT_L
113
MAKE_BASE=TRUE
USB-C PORT CONTROLLER TA
CD3215A (ACE) - UB300
(IPU)
1
R5246
2.2K
5% 1/20W MF
2
201
1
R5200
1K
5%
1/20W
MF
201
2
1
R5201
1K
5%
1/20W
MF
201
2
USB-C PORT CONTROLLER XA
CD3215A (ACE) - U3100
(WRITE: 0X70 READ: 0X71)
I2C_UPC_SCL I2C_UPC_SDA
UPC_I2C_INT_L
USB-C PORT CONTROLLER XB
29
29
30
80
PP1V8_SLPS2R
SMC (SoC)
U3900
(MASTER)
I2C_SSD_SCL
39
MAKE_BASE=TRUE
I2C_SSD_SDA
39
MAKE_BASE=TRUE
R5230
1K
5%
1/20W
MF
201
Ocarina
(Write:0xF2 Read:0xF3)
R5291
33
1 2
5%1/20W MF 201 5%1/20W 201MF
1 2
I2C_SSD0_SCL
CKPLUS_WAIVE=I2C_PULLUP
I2C_SSD0_SDA
CKPLUS_WAIVE=I2C_PULLUP
92
92
33
1
2
1
R5231
1K
5% 1/20W MF 201
2
R5290
SSD 1
Ocarina
(Write:0xF0 Read:0xF1)
R5242
33
1 2
5%1/20W MF 201 5%1/20W 201MF
1 2
I2C_SSD1_SCL
CKPLUS_WAIVE=I2C_PULLUP
I2C_SSD1_SDA
CKPLUS_WAIVE=I2C_PULLUP
87
87
33
R5243
B
A
116
(WRITE: 0X76 READ: 0X77)
I2C_UPC_SCL
109
109
51 80
PP1V8_S5
1
2
C5260
0.1UF
10%
6.3V CERM-X5R 0201
1
VCCA
PP3V3_S0_GPU
C5261
0.1UF
X5R-CERM
1
0201
8
VCCB
2
10% 10V
U5260
IN
PM_ALL_GPU_PGOOD I2C_SNS1_S0_SCL I2C_SNS1_S0_SDA
TXS0102DQM
OE
5
A1
2
A2
3
X2SON
CRITICAL
GND
B1
7
B2
6
4
98 117
GPU DIE
UA000
(Write: 0x82 Read: 0x83)
GPU_SMB_CLK GPU_SMB_DAT
98
BI
98
BI
111
I2C_UPC_SDA
110
USB-C PORT CONTROLLER TB
UPC_I2C_INT_L
CD3215A (ACE) - UB400
(WRITE: 0X78 READ: 0X79)
I2C_UPC_SCL
109
I2C_UPC_SDA
109
UPC_I2C_INT_L
CD3215A (ACE) - U3200
(WRITE: 0X7E READ: 0X7F)
I2C_UPC_SCL I2C_UPC_SDA
UPC_I2C_INT_L
29
29
31
SYNC_MASTER=ZIFENG SYNC_DATE=02/14/2019
PAGE TITLE
A
I2C Connections 1
SIZE
D
BOM_COST_GROUP=SMC
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
52 OF 200
SHEET
51 OF 135
8
67
35 4
2
1
Page 52
Vinafix.com
678
3 245
1
D
AP I2C "0" G3S Connections
118
PP1V8_G3S
AP (SoC)
U3900
(MASTER)
I2C_SPKRAMP_L_SCL
40
I2C_SPKRAMP_L_SDA
40
AP I2C "1" G3S Connections
PP1V8_G3S
118
AP (SoC)
U3900
(MASTER)
I2C_SPKRAMP_R_SCL
40
MAKE_BASE=TRUE
I2C_SPKRAMP_R_SDA
40
MAKE_BASE=TRUE
R5300
2.2K
1/20W
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R5305
2.2K
1/20W
5% MF
201
5% MF
201
AP I2C "5" Awake Connections
I2C Device Address
AP (SoC)
Left Speaker Amps
U6400
1
2
1
R5301
2.2K
5% 1/20W MF 201
2
(WRITE:0X62,READ 0X63)
U6420
(WRITE:0X64,READ 0X65)
U6460
(WRITE:0X6A,READ 0X6B)
I2C_SPKRAMP_L_SCL I2C_SPKRAMP_L_SDA
62
62
NC_I2C_SOC_5_SCL
40
40
NC_I2C_SOC_5_SDA
U3900
(MASTER)
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_I2C_SOC_5_SCL NC_I2C_SOC_5_SDA
Device SMC IF
ACE XA ACE XB ACE TA
I2C0 I2C0 I2C0
ADDR. (8b)
0X70/1 0X7E/F
D
0X76/7
ISP I2C "1" G3S Connections
ACE TB
ISP (SoC)
U3900
(MASTER)
NC_I2C_PLCAM_SCL
40
NC_I2C_PLCAM_SDA
40
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Right Speaker Amps
U6500
1
2
1
R5306
2.2K
5% 1/20W MF 201
2
(WRITE:0X62,READ 0X63)
U6520
(WRITE:0X64,READ 0X65)
U6560
(WRITE:0X6A,READ 0X6B)
I2C_SPKRAMP_R_SCL I2C_SPKRAMP_R_SDA
63
63
ISP I2C "0" G3S Connections
PP1V8_G3S
82 118
NC_I2C_PLCAM_SCL NC_I2C_PLCAM_SDA
Temp. Sensor Left
Temp. Sensor Right
CPU,MEM,WLAN Thermal
GPU Analog Die Thermal
GPU Digital Die Thermal
EADC1 EADC2
TCON
GMUX IOEXP
I2C0 I2C1 I2C1 I2C2 I2C2 I2C2 I2C2 I2C2 I2C3 I2C3
0X78/9 0X10/1 0X12/3 0X98/9 0X96/7 0X90/1 0X92/3 0X82/3 0X20/1 0X44/5
C
B
40
40
122 40
122 40
AP I2C "2" Codec Connections
AP (SoC)
U3900
(MASTER)
I2C_CODEC_SCL
MAKE_BASE=TRUE
I2C_CODEC_SDA
MAKE_BASE=TRUE
AP I2C "3" G3S Connections
118
AP (SoC)
U3900
(MASTER)
I2C_ALS_SCL
MAKE_BASE=TRUE
I2C_ALS_SDA
MAKE_BASE=TRUE
61 118
PP1V8_G3S
PP1V8_G3S
R5310
2.2K
5%
1/20W
MF
201
R5315
1.1K
5%
1/20W
MF
201
ISP (SoC)
U3900
(MASTER)
40
I2C_FTCAM_SCL
MAKE_BASE=TRUE
40
I2C_FTCAM_SDA
MAKE_BASE=TRUE
1
2
1
R5311
2.2K
5% 1/20W MF 201
2
Audio Codec
U6300
(WRITE:0X90,READ 0X91)
I2C_CODEC_SCL I2C_CODEC_SDA
61
61
CNL-H uSFF SMBUS Connections
12 13 15 16 19 20 80
R5335
1.1K
1/20W
1
5% MF
201
PP1V8_S5
2
2
1.1K
5%
1/20W
MF
201
FaceTime Camera
J8500
(WRITE:0X6C,READ 0X6D)
I2C_FTCAM_SCL I2C_FTCAM_SDA
82
82
Left Spkr Amp.(U6400) Left Spkr Amp.(U6420)
R5336
1
Charger Battery
Calpe
Trackpad
SSD0 SSD1
Left Spkr Amp.(U6460)
5% MF
201
1
2
PCH
U1200
(MASTER)
SMBUS_PCH_CLK
15
15
SMBUS_PCH_DATA
1
1
2
R5316
1.1K
5%
1/20W
MF
201
2
(See camera flex)
(WRITE:0X52,READ:0X53)
I2C_ALS_SCL I2C_ALS_SDA
ALS
J8500
82
82
R5360
2.2K
1/20W
1
R5361
2.2K
5% 1/20W MF 201
2
Right Spkr Amp.(U6500) Right Spkr Amp.(U6520) Right Spkr Amp.(U6560)
Audio Codec
ALS
DFR Display
DFR Touch
I2C4 I2C4 I2C4 I2C5 I2C6 I2C6
SoC IF
I2C0 I2C0 I2C0 I2C1 I2C1 I2C1 I2C2 I2C3 I2C4 I2C4
0X12/3 0X16/7 0XE8/9 0X98/9 0XF2/3 0XF0/1
0X62/3 0X64/5 0X6A/B 0X62/3 0X63/4 0X6A/B 0X90/1 0X52/3 0X98/9 0XA0/1
C
B
40
AP (SoC)
U3900
CKPLUS_WAIVE=I2C_PULLUP
BI
CKPLUS_WAIVE=I2C_PULLUP
(MASTER) I2C_DFR_SCL I2C_DFR_SDA
AP I2C "4" DFR Connections
122 50
R5322
5%1/20WMF201
R5323
5%1/20W201 MF
PP1V8_SLPS2RSW_DFR
R5320
2.2K
1/20W
201
15
I2C_DFR_SCL_R
12
MAKE_BASE=TRUE
15
I2C_DFR_SDA_R
12
MAKE_BASE=TRUE
5% MF
R5321
1
2
1
2.2K
5% 1/20W MF 201
2
DFR Display
J5110
(Write:0x98 Read:0x99) I2C_DFR_SCL_R I2C_DFR_SDA_R
NC. NC.Spkr ID1 NC.Spkr ID0
I2C5 I2C6_SDA I2C6_SCL
ISP IF
FT Camera
NC.
I2C1
0X6C/DI2C0
AOP IF
50 40
OUTIN
50
BI
NC.
NC.
PULL-UP
I2C0
PCH IF
A
8
DFR Touch ROM
(Write:0xA0 Read:0xA1) I2C_DFR_SCL_R I2C_DFR_SDA_R
J5100
OUT
BI
50
50
SYNC_MASTER=ZIFENG SYNC_DATE=02/14/2019
PAGE TITLE
A
I2C Connections 2
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
BOM_COST_GROUP=SMC
67
35 4
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
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1
D
DC-IN Voltage Sense (VD0R)
Gain: 0.05322x Vnominal: 20 V, Range: 23.49 V SMC ADC: 00 Enables DC-In VSense divider when AC present.
2.2KHz
124 121 68 29
PPDCIN_G3H
PLACE_NEAR=U3900.AG2:5MM
1%
1/20W
MF
201
1%
1/20W
MF
201
1
2
1
2
R5498
84.5K
R5499
4.75K
PLACE_NEAR=U3900.AG2:5MM
Rthevenin = 4497 Ohms
SMC_DCIN_VSENSE
PLACE_NEAR=U3900.AG2:5MM
C5499
1
0.022UF
10%
6.3V
2
X5R-CERM 0201
GND_SMC_AVSS
OUT
J152 Sensor Settings
OTHER 5V High Side Current Sense (IO5R)
Gain: 200x, EDP: 1.766 A
IC Vmax SMC Sample Freq. ADR RC filter
H9M CALPE EADC 5.0
123 59
123 58 56 54 53 46 39
Vref
1.25
1.5
2.5
1.8
5.0
10kHz 100Hz
0.1ms 10ms 100ms1-2Hz (10Hz)
117
117
Rsense: 0.005 (R5410) or Rsense SHORT Vsense: 8.83 mV, Range: 3.3 A CALPE: AMUX_B7
PLACE_NEAR=U5410.2:10MM
PPBUS_G3H
CRITICAL
R5410
0.005
SENSOR:DEV
123
1%
1/3W
MF
0306
123
ISNS_HS_OTHER5V_P
ISNS_HS_OTHER5V_N
4
PPBUS_HS_OTH5V
PLACE_NEAR=U5410.4:10MM
PP3V3_G3SSW_SNS
53 118
LOADISNS
CRITICAL
2 3
4 5
IN+ IN+
IN­IN-
6
V+
U5410
INA210A
UQFN
200x
GND
9
OUT
REF
NC NC
LOADISNS
BYPASS=U5410.6::5MM
C5411
1
0.1UF
10%
6.3V
2
CERM-X5R 0201
10
HS_OTHER5V_IOUT
8 1
NC
7
NC
PLACE_NEAR=U7800.H13:15MM
LOADISNS
R5418
NOSTUFF
1
R5417
15K
5% 1/20W MF 201
2
9.09K
1 2
1%
1/20W
MF
201
PMU_OTHER5V_HI_ISENSE
R5419
9.09K
1%
1/20W
MF
201
LOADRC:YES
PLACE_NEAR=U7800.H13:15MM
59
D
OUT
1
2
PLACE_NEAR=U7800.H13:15MM
1
C5419
2.2UF
20%
2
6.3V X5R-CERM 0201
LOADISNS
GND_CALPE_AVSS
58 55 54 53
123 96 76
C
DC-IN Current Sense (ID0R)
DISCharger Gain: 20x, EDP: 4.6 A Rsense: 0.010 (R7020) SMC ADC: 01
68
IN
CHGR_AMON SMC_DCIN_ISENSE
PLACE_NEAR=U3900.AC4:5MM
R5439
4.53K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U3900.AC4:5MM
1
C5439
0.022UF
10%
6.3V
2
X5R-CERM 0201
GND_SMC_AVSS
EN_VP0R_LPS:NO
OUT
LEFT SIDE 3.3V High Side Current Sense (IOLR)
Gain: 200x, EDP: 4.82 A Rsense: 0.003 (R5440) or Rsense SHORT
Vsense: 14.46 mV, Range: 5.5 A SMC ADC:TBD
CALPE: AMUX_B5
117
123 59
117
123 58 56 54 53 46 39
PPBUS_G3H
SENSOR:DEV
PPBUS_HS_3V3G3HRTC_X
CRITICAL
R5440
0.003
1/2W 0306
123
PLACE_NEAR=U5440.2:10MM
123
1% MF
ISNS_HS_3V3_X_P
ISNS_HS_3V3_X_N
4
PLACE_NEAR=U5440.4:10MM
53 118
PP3V3_G3SSW_SNS
LOADISNS
2 3
4 5
U5440
IN+ IN+
INA210A
CRITICAL
200x
IN­IN-
6
V+
UQFN
GND
9
OUT
REF
NC NC
LOADISNS
BYPASS=U5440.6::5MM
1
C5441
0.1UF
10%
6.3V CERM-X5R
2
0201
10
HS_3V3_X_IOUT
8 1
NC
7
NC
NOSTUFF
1
R5447
15K
5% 1/20W MF 201
2
LOADISNS
R5448
9.09K
1 2
1%
1/20W
MF
201
LOADRC:YES
PLACE_NEAR=U7800.G14:15MM
PMU_3V3_X_HI_ISENSE
PLACE_NEAR=U7800.G14:15MM
1
C5449
2.2UF
20%
6.3V X5R-CERM
2
0201
1%
1/20W
MF
201
1
2
R5449
9.09K
GND_CALPE_AVSS
PLACE_NEAR=U7800.G14:15MM
59
OUT
LOADISNS
123
C
55 54 53 96 76 58
B
A
PBUS Voltage Sense (VP0R)
Gain: 0.08513x Vnominal: 13.1 V, Range: 14.68 V SMC ADC: 02 Enables PBUS VSense divider when in S0.
PPBUS_G3H
117
PLACE_NEAR=R5400.1:75 MM
XW5480
SM
1 2
1
R5482
100K
1% 1/20W MF
201
2
EN_VP0R_LPS:NO
PP3V3_G3SSW_SNS
53 54 55 56 58 118
PBUSVSENS_EN_L_DIV
2
EN_VP0R_LPS:NO
R5481
100K
201 MF 1/20W
1
1%
PBUS_S0_VSENSE_IN
EN_VP0R_LPS:YES
R5441
0
1 2
5%
1/20W
MF
0201
2
1
5
4
Discharger BMON Current Sense (IPBR)
Charger Gain: 8X OR 64x, Use 8X, EDP: 25 A Rsense: 0.005 (R7060) SMC ADC: 03
68
IN OUT
CHGR_BMON
PLACE_NEAR=U3900.AD4:15MM
R5429
4.53K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U3900.AD4:15MM
SMC_BMON_ISENSE
NOSTUFF
1%
1/20W
MF
201
1
2
PLACE_NEAR=U3900.AD4:15MM
1
C5429
0.022UF
10%
6.3V
2
X5R-CERM 0201
R5428
9.09K
GND_SMC_AVSS
CPU High Side Curent Sense (IC0R)
Gain: 100x, EDP: 16.8 A
117
117
Rsense: 0.001 (R5400) Vsense: 16.8 mV, Range: 25 A SMC ADC: 04
3.3KHz
PLACE_NEAR=R5400.3:5MM
PPBUS_G3H
ISNS_HS_COMPUTING_P
1%
1W MF-3 0612
123
PLACE_NEAR=U5400.3:10MM PLACE_NEAR=U5400.4:10MM
ISNS_HS_COMPUTING_N
4
R5400
0.001
123
CRITICAL
PPBUS_HS_CPU
IN+
2 3
IN+
IN-
4
IN-
5
PLACE_NEAR=R5400.4:5MM
BYPASS=U5400.6::5MM
118
PP3V3_G3SSW_SNS
6
V+
U5400
INA214A
UQFN
CRITICAL
100x
GND
9
OUT
REF
NC NC
10 8 1
7
1
C5401
0.1UF
10%
6.3V
2
CERM-X5R 0201
ISNS_HS_COMPUTING_OUT
NOSTUFF
NC NC
1
R5405
15K
5% 1/20W MF 201
PLACE_NEAR=U5400.6:5MM
2
PLACE_NEAR=U3900.AB6:10MM
CRITICAL
Q5480
NTUD3169CZ
SOT-963
N-CHANNEL
D
G
S
D
6
PBUSVSENS_EN_L
3
PBUS_S0_VSENSE
R5488
G
S
P-CHANNEL
R5489
PLACE_NEAR=U3900.AH3:15MM
123 59
123 58 56 54 53 46 39
PLACE_NEAR=U3900.AB6:10MM
R5409
9.09K
1 2
1%
1/20W
MF
201
1%
1/20W
MF
201
1
2
R5401
9.09K
SMC_CPU_HI_ISENSE
PLACE_NEAR=U3900.AB6:5MM
1
C5409
0.022UF
10%
6.3V
2
X5R-CERM 0201
PLACE_NEAR=U3900.AH3:15MM
1
59K
1%
1/20W
MF
201
2
Rthevenin = 5023 Ohms
SMC_PBUS_VSENSE
1
5.49K
1%
1/20W
MF
2
201
1
2
GND_SMC_AVSS
C5489
0.022UF
10%
6.3V X5R-CERM 0201
PLACE_NEAR=U3900.AH3:15MM
GND_SMC_AVSS
OUT
59
RIGHT SIDE 3.3V High Side Current Sense (IORR)
Gain: 100x, EDP: 10.6 A Rsense: 0.003 (R5460) or Rsense SHORT
OUT
Vsense: 31.8 mV, Range: 11 A SMC ADC:TBD
CALPE: AMUX_B6
117
123 59
117
123 58 56 54 53 46 39
LCD Backlight Current Sense (IBLR)
PPBUS_G3H
SENSOR:DEV
PPBUS_HS_3V3G3H_T
CRITICAL
R5460
0.002
1%
1/2W
MF
123
0306
PLACE_NEAR=R5460.3:10MM
123
ISNS_HS_3V3_T_P
ISNS_HS_3V3_T_N
4
PLACE_NEAR=R5460.4:10MM
PP3V3_G3SSW_SNS
53 118
LOADISNS
2 3
4 5
U5460
IN+ IN+
IN­IN-
INA214A
CRITICAL
100x
6
V+
UQFN
GND
9
OUT
REF
NC NC
10
ISNS_HS_3V3_T_OUT
8 1
NC
7
NC
Gain: 100x. EDP: 0.87 A Rsense: 0.025 (R8400) Vsense: 21.75 mV, Range: 1.32 A
123 81
123 81
EADC1: CH0
PLACE_NEAR=R8400.4:10MM
IN
IN
ISNS_LCDBKLT_P
ISNS_LCDBKLT_N
PLACE_NEAR=R8400.3:10MM
PP3V3_G3SSW_SNS
53 54 55 56 58 118
LOADISNS
6
V+
U5450
IN+
2 3
IN+
IN-
4
IN-
5
INA214A
UQFN
CRITICAL
100x
GND
9
OUT
REF
NC NC
LOADISNS
C5450
1
0.1UF
10%
6.3V
2
CERM-X5R 0201
BYPASS=U5450.6::5MM
10 8 1
NC
7
NC
NOSTUFF
1
R5455
6.04K
1% 1/20W MF 201
2
PLACE_NEAR=U5450.10:5MM
LOADISNS
R5459
45.3K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U5700.22:5MM
1
2
GND_EADC1_COM
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
117S0008 LOADRC:NO3
123 58 56 54 53 46 39
RES,MTL FLIM,100K,1/16W,0201,SMD,LF
R5449,R5469,R5419
BOM_COST_GROUP=SENSORS
LOADISNS
BYPASS=U5460.6::5MM
C5461
1
0.1UF
10%
6.3V CERM-X5R
2
0201
NOSTUFF
1
R5467
15K
5% 1/20W MF 201
2
LOADISNS
R5468
9.09K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U7800.H14:15MM
R5469
9.09K
LOADRC:YES
PLACE_NEAR=U7800.H14:15MM
EADC1_LCDBKLT_ISENSEISNS_LCDBKLT_IOUT
C5459
2.2UF
20%
6.3V X5R-CERM 0201
PLACE_NEAR=U5700.22:5MM
LOADISNS
123 58 56 55
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
Power Sensors High Side
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
PMU_3V3_T_HI_ISENSE
PLACE_NEAR=U7800.H14:15MM
1
C5469
2.2UF
20%
6.3V X5R-CERM
2
0201
LOADISNS
1%
1/20W
MF
201
1
2
GND_CALPE_AVSS
56
OUT
59
OUT
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
54 OF 200
SHEET
53 OF 135
123
55 54 53 96 76 58
B
A
SIZE
D
8
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2
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Page 54
Vinafix.com
D
C
117
118
PPVCCPRIMCORE_PRIM_REG
SENSOR:DEV
PP1V05_PRIM
R5560
0.001
1/3W
1% MF
0306
123
4
ISNS_1V0_P
ISNS_1V0_N
123
Measure current for engineering build only.
123
DDR4 1.2V Current Sense (IM0C)
Gain: 100x, EDP: 11 A Rsense: 0.002 (R7718) or XWTBD Vsense: 22.2 mV, Range: 16.5 A CALPE: AMUX_A7
123 74
123 74
ISNS_CPUDDR_P
IN
ISNS_CPUDDR_N
IN
53 54 55 56 58 118
PP3V3_G3SSW_SNS
LOADISNS
V+
U5570
INA214A
2
IN+
3
IN+
IN-
4
IN-
5
UQFN
CRITICAL
100x
GND
6
10
OUT
8
REF
1
NC
7
NC
9
LOADISNS
BYPASS=U5570::5MM
C5570
1
0.1UF
10%
6.3V
2
CERM-X5R 0201
ISNS_DDR_IOUT
NC NC
678
PLACE_NEAR=U7800.F14:15MM
LOADISNS
R5579
9.09K
1 2
1%
1/20W
MF
201
LOADRC:YES
PLACE_NEAR=U7800.F14:15MM
R5576
9.09K
1/20W
PMU_DDR1V2_ISENSE
LOADISNS
C5579
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
PLACE_NEAR=U7800.F14:15MM
1% MF
201
1
2
OUT
59
70
70
70
70
70
70
3 245
CPU Core Curent Sense (ICAC)
Gain: 89.48x, EDP: 128 A Rsense: 3x of 0.00075 R7210,R7220,R7230),Rsum: 0.00025 Vsense:16.75 mV, Range: 134.11 A CALPE AMUX: A0
118
LOADISNS
IN
CPUCORE_ISNS1_P
NO_XNET_CONNECTION=1 PLACE_NEAR=R7210:5MM
LOADISNS
IN
CPUCORE_ISNS2_P
NO_XNET_CONNECTION=1 PLACE_NEAR=R7220:5MM
LOADISNS
IN
CPUCORE_ISNS3_P
NO_XNET_CONNECTION=1 PLACE_NEAR=R7230:5MM
LOADISNS
IN
CPUCORE_ISNS1_N
NO_XNET_CONNECTION=1 PLACE_NEAR=R7210:5MM
LOADISNS
IN
CPUCORE_ISNS2_N
NO_XNET_CONNECTION=1 PLACE_NEAR=R7220:5MM
LOADISNS
IN
CPUCORE_ISNS3_N
NO_XNET_CONNECTION=1 PLACE_NEAR=R7230:5MM
R5545
4.42K
1 2
R5546
1 2
R5550
1 2
R5547
1 2
R5548
1 2
R5551
4.42K
1 2
MF0.1%
4.42K
0.1%
1/20W
4.42K
0.1%
1/20W
4.42K
MF0.1%
1/20W
4.42K
0.1%
1/20W
0.1% MF
1/20W
02011/20W
MF
0201
MF
0201
0201
MF
0201
0201
CPUVR_ISNS_P
NO_XNET_CONNECTION=1
CPUVR_ISNS_N
LOADISNS
R5542
2.55K
1 2
0.1%
1/20W
MF
0201
LOADISNS
R5543
2.55K
1 2
0.1%
1/20W
MF
0201
CPUVR_ISNS_R_P
LOADISNS
1
R5544
360K
0.1% 1/20W MF
2
0201
CPUVR_ISNS_R_N
PP3V3_G3SSW_SNS
LOADISNS
1
3
LOADISNS
R5541
360K
1 2
0.1%
1/20W
0201
WLANBT 3V3 Current Sense (IAPC)
Gain: 145x, EDP: 1.5 A Rsense: 0.005 (R5530) or Rsense SHORT Vsense: 7.5 mV, Range: 1.72 A SMC: ADC 06
CRITICAL
U5540
ISL28133
SC70-5
V+
V-
2 5
MF
NO_XNET_CONNECTION=1
CPUVR_ISUM_IOUT
4
LOADISNS
BYPASS=U5540.5::5MM
C5540
1
0.1UF
10%
2
6.3V X7R 0201
PLACE_NEAR=U7800.A16:15MM
LOADISNS
R5540
9.09K
1 2
1%
1/20W
MF
201
R5549
9.09K
1/20W
LOADRC:YES
PMU_CPU_ISENSE
1% MF
201
1
D
59
OUT
PLACE_NEAR=U7800.A16:15MM
C5549
1
2
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
LOADISNS
GND_CALPE_AVSS
123 96
7658 55 54 53
C
B
117
117
CPUDDR 1.2V Curent Sense (IMCC)
Gain: 200x, EDP: 2.8 A Rsense: 0.005 (R5510) Vsense: 14 mV, Range: 3 A CALPE: AMUX_A6
PP1V2_S3
SENSOR:DEV
PP1V2_S3_CPUDDR
R5510
0.005
1/3W
1% MF
123
0306
PLACE_NEAR=R5510.4:5MM
ISNS_CPUVDDQ_P
4
123
ISNS_CPUVDDQ_N
PLACE_NEAR=R5510.3:5MM
PP3V3_G3SSW_SNS
53 54 55 56 58 118
LOADISNS
2 3
4 5
U5510
INA210A
IN+ IN+
CRITICAL
200x
IN­IN-
6
V+
UQFN
GND
9
OUT
REF
NC NC
LOADISNS
BYPASS=U5510::5MM
1
C5510
0.1UF
10%
2
6.3V CERM-X5R 0201
10 8 1
7
ISNS_CPUDDR_IOUT
NC NC
LOADISNS
R5518
9.09K
1 2
1%
1/20W
MF
201
LOADRC:YES
PLACE_NEAR=U7800.E14:15MM
PLACE_NEAR=U7800.E14:15MM
PMU_CPUDDR_ISENSE
R5519
9.09K
1%
1/20W
MF
201
GND_CALPE_AVSS
118
118
59
OUT
1
2
PLACE_NEAR=U7800.E14:15MM
1
C5519
2.2UF
20%
6.3V
2
X5R-CERM 0201
LOADISNS
123 96 76 58 55 54 53
PP3V3_G3S_X
PLACE_NEAR=R5532.1:10MM
SENSOR:DEV
PLACE_NEAR=R5533.1:10MM
PP3V3_G3S_WLAN
PP5V_G3S
56 118
123
0306
MF
1/3W
1%
0.005
R5530
4
ISNS_WLAN_N
ISNS_WLAN_P
123
LOADISNS
D5530
SC2
A K
DSF01S30SCAP
LOADISNS
R5533
120
1 2
R5532
120
1 2
0.1%
LOADISNS
PP5V_G3S_ISNS_D
LOADISNS
BYPASS=U5530::5MM
1
C5530
0.1UF
10%
6.3V
2
CERM-X5R 0201
ISNS_WLAN_R_N
MF
02011/20W 0.1%
ISNS_WLAN_R_P
MF 02011/20W
LOADISNS
Q5530
DMP31D0UFB4
DFN1006H4-3
ISNS_P3V3S_WLAN_IOUT
2
S
3
D
LOADISNS CRITICAL
U5530
6
4
3
MAX4239ATT+T
TDFN
EPAD
5
2
7
1
IAPC_OPA_OUT
G
1
LOADISNS
1
R5535
100K
5% 1/20W MF 201
2
LOADISNS
1
R5534
17.4K
0.1% 1/20W MF 0201
2
LOADISNS
R5538
4.53K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U3900.AG4:10MM
SMC_P3V3_WLAN_ISENSE
PLACE_NEAR=U3900.AG4:5MM
1
C5539
0.022UF
10%
6.3V
2
X5R-CERM 0201
59
LOADRC:YES
GND_SMC_AVSS
123 58 56 53 46 39
B
2.5V Current Sense (IM1C)
Gain: 200x, EDP: 2.24 A Rsense: 0.005 (R7724) or Rsense SHORT Vsense: 11.2 mV, Range: 3.3 A EADC2: CH0
PLACE_NEAR=R7724.3:5MM
123 74
123 74
PLACE_NEAR=R7724.4:5MM
IN
IN
ISNS_2V5_S3_P
ISNS_2V5_S3_N
PP3V3_G3SSW_SNS
53 54 55 56 58 118
LOADISNS
U5590
INA210A
IN+
2 3
4 5
CRITICAL
IN+
IN­IN-
200x
6
V+
UQFN
GND
9
OUT
REF
NC NC
10 8 1
7
GND_CALPE_AVSS
LOADISNS
BYPASS=U5590.6::5MM
1
C5590
0.1UF
10%
6.3V
2
CERM-X5R 0201
PLACE_NEAR=U5710.22:5MM
LOADISNS
R5599
DDR2V5_IOUT EADC2_DDR2V5_ISENSE
1
R5595
NC NC
20K
5% 1/20W MF 201
2
NOSTUFF
PLACE_NEAR=U5590.10:5MM
45.3K
1 2
1%
1/20W
MF
201
LOADISNS
1
C5599
2.2UF
20%
6.3V X5R-CERM
2
0201
PLACE_NEAR=U5710.22:5MM
GND_EADC2_COM
OUT
123 96 58 56 55
56
123 96 76 58 55 54 53
WLANBT 1V8 Current Sense (IA8C)
Gain: 200x, EDP: 0.1 A Rsense: 0.05 (R5520) or Rsense SHORT Vsense: 5 mV, Range: 0.3 A CALPE: AMUX_A5
118
PP1V8_G3S_WLANBT
118
PP1V8_G3S
SENSOR:DEV
R5520
0.05
1%
1/3W
MF
123
0306
123
PLACE_NEAR=U5520.2:10MM
ISNS_WL1V8_P
ISNS_WL1V8_N
4 PLACE_NEAR=U5520.4:10MM
PP3V3_G3SSW_SNS
LOADISNS
IN+
2
CRITICAL
3
IN+
IN-
4
IN-
5
6
V+
U5520
INA210A
UQFN
200x
GND
9
OUT
REF
NC NC
BYPASS=U5520.6::5MM
C5520
1
2
10
ISNS_WL1V8_IOUT
8 1
NC
7
NC
LOADISNS
0.1UF
10%
6.3V CERM-X5R 0201
LOADISNS
R5528
9.09K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U7800.D15:15MM
PLACE_NEAR=U7800.D15:15MM
PMU_P1V8_WLAN_ISENSE
R5529
9.09K
1/20W
201
LOADRC:YES
1
1% MF
2
C5529
2.2UF
20%
2
6.3V X5R-CERM 0201
LOADISNS
1
GND_CALPE_AVSS
59
OUT
PLACE_NEAR=U7800.D15:15MM
123 96 76 58 55 54 53
No need for pull-down for leakage since the input voltage is less than 5v
A
8
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
5117S0008 LOADRC:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF
R5576,R5519,R5549,C5539,R5529
67
A
SYNC_DATE=02/12/2019SYNC_MASTER=RAYMOND
PAGE TITLE
Power Sensors Load Side
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SENSORS
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
55 OF 200
SHEET
54 OF 135
1
SIZE
D
Page 55
Vinafix.com
678
3 245
1
D
C
PP3V3_G3W_SSD0 HIGH SIDE CURRENT SENSE (KEY IH0C)
GAIN: 200X, EDP: 1.48 A RSENSE: 0.005 (RK710) OR RSENSE SHORT VSENSE: 13 MV, RANGE: 2.5 A
CALPE: AMUX_B3
PP3V3_G3H_RTC_X
118
SENSOR:DEV
PP3V3_G3H_SSD0_SNS
118
GAIN: 200X, EDP: 0.5 A
RSENSE: 0.005 (RK610) OR RSENSE SHORT VSENSE: 13 MV, RANGE: 2.5 A
CALPE: AMUX_B1
PPBUS_G3H
117
SENSOR:DEV
PPBUS_G3H_SSD0_SNS
118
123
1%
1/3W
MF
0306
123
R5600
0.005
123
CRITICAL
1%
1/3W
MF
0306
123
R5620
0.005
123
CRITICAL
53 54 55 56 58 118
PLACE_NEAR=R5600.3:5MM
ISNS_P3V3_G3W_SSD0_P
ISNS_P3V3_G3W_SSD0_N
4
PLACE_NEAR=R5600.4:5MM
53 54 55 56 58 118
PLACE_NEAR=R5620.3:5MM
ISNS_PPBUS_MAIN_SSD0_P
ISNS_PPBUS_MAIN_SSD0_N
4
PLACE_NEAR=R5620.4:5MM
PP3V3_G3SSW_SNS
LOADISNS
V+
U5600
2
IN+
3
IN+
IN-
4 5
IN-
PP3V3_G3SSW_SNS
INA210A
UQFN
CRITICAL
200x
GND
LOADISNS
2
IN+
3
4 5
CRITICAL
IN+
IN­IN-
6
OUT
REF
NC NC
9
6
V+
U5620
INA210A
UQFN
200x
GND
9
LOADISNS
C5600
1
0.1UF
10%
6.3V
2
CERM-X5R 0201
HS_P3V3_G3W_SSD0_OUT
10 8 1
NC
7
NC
LOADISNS
1
C5620
0.1UF
10%
6.3V CERM-X5R
2
0201
10
OUT
REF
NC NC
HS_PBUS_MAIN_SSD0_OUT
8 1
NC
7
NC
1
PLACE_NEAR=U5620.6:5MM
2
PLACE_NEAR=U7800.F13:16MM
NOSTUFF
R5623
15K
5% 1/20W MF 201
LOADISNS
R5601
9.09K
1 2
1%
1/20W
MF
201
LOADISNS
R5621
9.09K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U7800.E13:15MM
PLACE_NEAR=U7800.F13:16MM
PMU_P3V3_G3W_SSD0_ISENSE
PLACE_NEAR=U7800.F13:16MM
C5601
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
LOADISNS
GND_CALPE_AVSS
1%
1/20W
MF
201
1
2
R5602
9.09K
LOADRC:YES
PLACE_NEAR=U7800.E13:15MM
PMU_PBUS_MAIN_SSD0_ISENSE
PLACE_NEAR=U7800.E13:15MM
C5621
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
LOADISNS
1%
1/20W
MF
201
1
2
R5622
9.09K
LOADRC:YES
PP3V3_G3W_SSD1 HIGH SIDE CURRENT SENSE (KEY IH1C)
GAIN: 200X, EDP: 1.48 A RSENSE: 0.005 (RK760) OR RSENSE SHORT VSENSE: 13 MV, RANGE: 2.5 A
CALPE: AMUX_B4
53 54 55 56 58 118
PP3V3_G3SSW_SNS
OUT
PP3V3_G3H_T
59
118
SENSOR:DEV
CRITICAL
R5610
0.005
123
118
PP3V3_G3H_SSD1_SNS
123 96 76 58 55 54 53
1%
1/3W
MF
0306
PLACE_NEAR=R5610.3:10MM
ISNS_P3V3_G3W_SSD1_P
123
ISNS_P3V3_G3W_SSD1_N
4
PLACE_NEAR=R5610.4:10MM
LOADISNS
2
IN+
3
IN+
IN-
4 5
IN-
6
V+
U5610
INA210A
UQFN
CRITICAL
200x
GND
9
OUT
REF
NC NC
10 8 1
7
PPBUS SSD1 HIGH SIDE CURRENT SENSE (KEY IH1R)PP12V SSD0 HIGH SIDE CURRENT SENSE (KEY IH0R)
GAIN: 200X, EDP: 0.5 A RSENSE: 0.005 (R5607) OR RSENSE SHORT
VSENSE: 13 MV, RANGE: 2.5 A
CALPE: AMUX_B2
PPBUS_G3H
117
PLACE_NEAR=R5630.3:10MM
SENSOR:DEV
123
1%
1/3W
MF
0306
123
ISNS_PPBUS_MAIN_SSD1_P ISNS_PPBUS_MAIN_SSD1_N
4
PLACE_NEAR=R5630.4:10MM
59
OUT OUT
118
R5630
0.005
123
CRITICAL
PPBUS_G3H_SSD1_SNS
PP3V3_G3SSW_SNS
53 54 55 56 58 118
LOADISNS
6
V+
U5630
2 3
4 5
INA210A
IN+
CRITICAL
IN+
200x
IN­IN-
UQFN
GND
9
OUT
REF
NC NC
LOADISNS
C5610
1
0.1UF
10%
6.3V
2
CERM-X5R 0201
HS_P3V3_G3W_SSD1_OUT
NC NC
LOADISNS
C5630
1
0.1UF
10%
6.3V
2
CERM-X5R 0201
HS_PBUS_MAIN_SSD1_OUT
10 8 1
NC
7
NC
NOSTUFF
1
R5633
15K
5% 1/20W MF 201
PLACE_NEAR=U5630.6:5MM
2
LOADISNS
R5611
9.09K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U7800.G13:15MM
LOADISNS
R5631
9.09K
1 2
PLACE_NEAR=U7800.G13:15MM
PMU_P3V3_G3W_SSD1_ISENSE
PLACE_NEAR=U7800.G13:15MM
C5611
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
LOADISNS
GND_CALPE_AVSS
1%
1/20W
MF
201
1
2
R5612
9.09K
LOADRC:YES
PLACE_NEAR=U7800.E12:15MM
PMU_PBUS_MAIN_SSD1_ISENSE
1%
1/20W
MF
201
R5632
9.09K
LOADRC:YES
1%
1/20W
MF
201
1
2
1
2
OUT
PLACE_NEAR=U7800.E12:15MM
C5631
2.2UF
20%
6.3V X5R-CERM 0201
LOADISNS
D
59
123 96 76 58 55 54 53
59
C
B
LCD Panel Current Sense (ILDC)
Gain: 200x. EDP: 1 A RSENSE: 0.01 (R8520) or Rsense SHORT Vsense: 5 mV, Range: 1.25 A
EADC1: CH1
PLACE_NEAR=R8520.1:5MM
123 82
IN
PP3V3_G3SSW_SNS
53 54 55 56 58 118
LOADISNS
ISNS_LCDPANEL_P
ISNS_LCDPANEL_N
2
IN+
3
CRITICAL
IN+
4
IN-
5
IN-
6
V+
U5640
INA210A
UQFN
200x
GND
9
OUT
REF
NC NC
10 8 1
7
BYPASS=U5640.6::5MM
LOADISNS
1
C5640
0.1UF
10%
6.3V
2
CERM-X5R 0201
ISNS_LCDPANEL_IOUT
NC NC
1
R5645
51K
5% 1/20W MF 201
2
NOSTUFF
LOADISNS
R5649
45.3K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U5700.23:15MM
EADC1_LCDPANEL_ISENSE
1
C5649
2.2UF
20%
6.3V
2
X5R-CERM 0201
PLACE_NEAR=U5700.23:15MM
LOADISNS GND_EADC1_COM
GND_CALPE_AVSS
123 96 76 58 55 54 53
PLACE_NEAR=U7800.E12:15MM
GND_CALPE_AVSS
123 96 76 58 55 54 53
Keyboard backlight Current Sense (IKBC)
Gain: 200x, EDP: 0.23 A Rsense: 0.025 (R5660) or Rsense SHORT
56 123 82
OUTIN
118
123 58 56 53
118
PP5V_G3S
PP5V_G3S_KBDLED
Vsense: 5.75 mV, Range: 0.66 A EADC2: CH7
ISNS_KBDLED_P
123
123
ISNS_KBDLED_N
123
4
SENSOR:DEV
CRITICAL
R5660
0.025
1%
1/3W
MF
0306
PP3V3_G3SSW_SNS
53 54 55 56 58 118
LOADISNS
2 3
4 5
IN+
CRITICAL
IN+
IN­IN-
6
V+
U5660
INA210A
UQFN
200x
GND
9
OUT
REF
NC NC
LOADISNS
BYPASS=U5660.6::5MM
C5660
1
0.1UF
10%
6.3V
2
CERM-X5R 0201
ISNS_KBDLED_IOUT EADC2_PP5VGS_KBDLED_ISENSE
10 8 1
7
NC NC
1
R5661
20K
5% 1/20W MF 201
2
NOSTUFF
LOADISNS
PLACE_NEAR=U5710.5:5MM
R5666
45.3K
1 2
1%
1/20W
MF
201
C5666
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
LOADISNS
PLACE_NEAR=U5710.5:5MM
PLACE_NEAR=U5660.10:5MM
GND_EADC2_COM
OUT
B
56
123 96 58 56 54
A
118
118
T139 Current Sense resistor
EDP: 0.06 A Rsense: 0.05 (R5680) or Rsense SHORT
PP3V3_G3H_RTC_X
SENSOR:DEV
PP3V3_G3H_DFR
1%
1/3W
MF
0306
123
R5680
0.005
CRITICAL
ISNS_T139_P
NO_XNET_CONNECTION=1
ISNS_T139_N
4
123
123
117S0008 LOADRC:NO4
RES,MTL FLIM,100K,1/16W,0201,SMD,LF
R5602,R5612,R5622,R5632
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
A
SYNC_DATE=02/12/2019SYNC_MASTER=RAYMOND
PAGE TITLE
Power Sensors Extended 1
SIZE
D
BOM_COST_GROUP=SENSORS
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
56 OF 200
SHEET
55 OF 135
8
67
35 4
2
1
Page 56
Vinafix.com
D
R5755 if stuff 537k ISLC FATP high
0.7,DFU also high but not fail
118
118
678
Thunderbolt TBT RIGHT Current Sense (IURC)
Gain: 200x. EDP: 0.6 A Rsense: 0.025 (R5720) or Rsense SHORT Vsense: 15 mV, Range: 0.66 A EADC2: CH2
PP3V3_S0SW_TBT_T
SENSOR:DEV
R5720
CRITICAL
PP3V3_S0SW_TBT_T_SNS
0.025
1%
1/3W
MF
0306
123
PLACE_NEAR=U5720.2:10MM
123
ISNS_TBT_T_P
ISNS_TBT_T_N
4
53 54 55 56 58 118
PP3V3_G3SSW_SNS
LOADISNS
6
V+
U5720
INA210A
2
IN+
3
IN+
IN-
4 5
IN-
UQFN
CRITICAL
200x
GND
9
OUT
REF
NC NC
10
8 1
7
BYPASS=U5720.6::5MM
LOADISNS
1
C5720
0.1UF
10%
6.3V CERM-X5R
2
0201
ISNS_TBT_T_IOUT
1
R5725
NC NC
20K
5% 1/20W MF 201
2
NOSTUFF
PLACE_NEAR=U5720.10:5MM
LOADISNS
PLACE_NEAR=U5710.24:5MM
R5729
45.3K
1 2
1%
1/20W
MF
201
EADC2_TBT_T_ISENSE
1
C5729
2.2UF
20%
6.3V X5R
2
0201
LOADISNS
PLACE_NEAR=U5710.24:5MM
GND_EADC2_COM
56
3 245
1
CPU GT Current Sense (ICTC)
Gain: 240.78x, EDP: 32 A Rsense: 2x of 0.00075 (R7410, R7420), Rsum: 0.000375 Vsense: 12 mV, Range:36.55 A EADC1: CH3
R5745
72
CPUGT_ISNS1_P
IN
PLACE_NEAR=R7410.4:5MM
NO_XNET_CONNECTION=1
LOADISNS
72
CPUGT_ISNS2_P
IN
PLACE_NEAR=R7420.4:5MM
NO_XNET_CONNECTION=1
LOADISNS
LOADISNS
72
123 96 58 56 55 54
CPUGT_ISNS1_N CPUGT_ISNS_R_N
IN
PLACE_NEAR=R7410.3:5MM
NO_XNET_CONNECTION=1
4.42K
1 2
0.1%
1/20W
MF
0201
R5746
4.42K
1 2
0.1%
1/20W
MF
0201
R5748
4.42K
1 2
0.1%
1/20W
MF
0201
LOADISNS
CPUGT_ISNS_R_P
LOADISNS
R5742
2.94K
1 2
1%
1/20W
MF
201
R5743
2.94K
1 2
1%
1/20W
MF
201
CPUGT_ISNS_P
1
R5744
1M
1% 1/20W MF 201
2
NO_XNET_CONNECTION=1
CPUGT_ISNS_N
118
PP3V3_G3SSW_SNS
LOADISNS CRITICAL
U5740
ISL28133
V+
V-
2 5
SC70-5
4
CPUGT_ISUM_IOUT
LOADISNS
1
3
R5741
1M
1 2
1%
1/20W
MF
201
NO_XNET_CONNECTION=1
1
R5740
20K
5% 1/20W MF 201
2
PLACE_NEAR=U5740.4:5MM
BYPASS=U5740.5::5MM
LOADISNS
1
C5740
0.1UF
10%
6.3V
2
X7R 0201
LOADISNS
R5749
45.3K
1 2
1%
1/20W
MF
201
NOSTUFF
PLACE_NEAR=U5700.1:15MM
EADC1_CPUGT_ISENSE
C5749
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
LOADISNS
PLACE_NEAR=U5700.1:15MM
GND_EADC1_COM
D
56
123 58 56 55 53
C
B
A
Thunderbolt TBT LEFT Current Sense (IULC)
Gain: 200x. EDP: 0.6 A Rsense: 0.025 (R5730) or Rsense SHORT Vsense: 15 mV, Range: 0.66 A EADC1: CH7
118
118
PP3V3_S0SW_TBT_X
PP3V3_S0SW_TBT_X_SNS
Calpe 3V3 Current Sense (ISLC)
Gain: 200x, EDP: 8 A RSENSE: 0.001 (R5750) Vsense: 8 mV, Range: 15 A SMC ADC:07
PP3V3_G3H_T
118
PP3V3_G3H_SOCPMU
118
54 56 118
PP5V_G3S
53
IN
55
IN
56
56
123 58
123 58
123 58 56 55 53
IN
56
IN
56
CRITICAL
SENSOR:DEV
0306
123
MF
1/3W
1%
0.025
R5730
R5750
0.001
1/2W
1%
0306
MF
123
LOADISNS
R5700
0
1 2
5%
1/20W
MF
0201
BYPASS=U5700.12::6MM
EADC1_LCDBKLT_ISENSE EADC1_LCDPANEL_ISENSE EADC1_VCCIO_ISENSE EADC1_CPUGT_ISENSE EADC1_CPUGT_VSENSE EADC1_CPUSA_ISENSE EADC1_CPUSA_VSENSE EADC1_TBT_X_ISENSE
VOLTAGE=0V
GND_EADC1_COM
PLACE_NEAR=U5700.6:1MM
PP5V_EADC1_AVDD
PLACE_NEAR=U5700.25:1MM
53 54 55 56 58 118
PLACE_NEAR=U5730.2:10MM
4
ISNS_TBT_X_P
ISNS_TBT_X_N
123
PLACE_NEAR=U5750.2:5:10MM
4
123
ISNS_CALPE_P
MAKE_BASE=TRUE
123
ISNS_CALPE_N
MAKE_BASE=TRUE
PLACE_NEAR=U5750.4:3:10MM
1
C5701
0.1UF
10%
10V
2
X5R-CERM
0201
PP3V3_G3SSW_SNS
C5702
1
4.7UF
20%
10V
X5R-CERM
2
0402
BYPASS=U5700.12::5MM
LOADISNS
XW5700
SM
LOADISNS
22 23 24
1 2 3 4 5
6
12
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
COM
LOADISNS
U5730
INA210A
2
IN+
3
IN+
4
IN-
5
IN-
PP3V3_G3SSW_SNS
53 54 55 56 58 118
UQFN
CRITICAL
200x
IN+
2 3
IN+
IN-
4
IN-
5
EADC1
12
13
DVDDAVDD
U5700
LTC2309
QFN
CRITICAL
LOADISNS
GND
9
1011181920
BYPASS=U5700.8::5MM
BYPASS=U5730.6::5MM
1
C5730
6
V+
GND
9
OUT
REF
NC NC
6
V+
10 8 1
7
0.1UF
10%
6.3V CERM-X5R
2
0201
NC NC
U5750
INA210A
UQFN
CRITICAL
200x
GND
9
1
C5703
0.1UF
10%
10V
2
X5R-CERM 0201
LOADISNS
21
BYPASS=U5700.21::5MM
AD0 AD1
SDA
SCL
VREF
REFCOMP
THRM
PAD
25
OUT
REF
NC NC
1
2
14 15
17 16
7
8
(Write: 0x10 Read: 0x11)
I2C_SNS0_S0_5V_SDA I2C_SNS0_S0_5V_SDA I2C_SNS0_S0_5V_SCL
PP2V5_ADC1_VREF
ADC1_REFCOMP
1
C5705
0.1UF
10%
6.3V
CERM-X5R
2
0201
LOADISNS
LOADISNS
ISNS_TBT_X_IOUT
1
R5735
20K
5% 1/20W MF
2
201
NOSTUFF
PLACE_NEAR=U5730.10:5MM
BYPASS=U5750.6::5MM
1
C5750
0.1UF
10%
6.3V
2
CERM-X5R 0201
10
ISNS_CALPE_IOUT
8 1
NC
7
NC
NOSTUFF
1
R5751
15K
5% 1/20W MF 201
PLACE_NEAR=U5750.6:5MM
2
C5704
4.7UF
20%
10V
X5R-CERM 0402
BYPASS=U5700.21::5MM
LOADISNS
1
C5700
2.2UF
20%
6.3V
X5R-CERM
2
0201
1
C5706
10UF
20%
10V
X5R-CERM
2
0402-10
LOADISNS
BYPASS=U5700.7::5MM
LOADISNS
BYPASS=U5700.8::5MM
LOADISNS
PLACE_NEAR=U5700.5:5MM
R5739
45.3K
1 2
1%
1/20W
MF
201
R5759
7.5K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U3900.AC5:5MM
51
IN
EADC1_TBT_X_ISENSE
PLACE_NEAR=U3900.AC5:5MM
123 96 58 56 55 54
1
C5739
2.2UF
20%
6.3V
2
X5R-CERM 0201
LOADISNS
PLACE_NEAR=U5700.5:5MM
GND_EADC1_COM
SMC_P3V3_CAPLE_ISENSE
R5755
4.99K
1%
1/20W
MF
201
1
2
1
C5759
0.022UF
10%
6.3V X5R-CERM
2
0201
GND_SMC_AVSS
LOADISNS
54 56 118
PP5V_G3S
1 2
BYPASS=U5710.12::5MM
54
123 96
123 96
EADC2_DDR2V5_ISENSE
IN
EADC2_GPU_MEM_VDDCI_ISENSE
IN
56
EADC2_TBT_T_ISENSE EADC2_GPU_MEM_VDDIO_ISENSE
IN
EADC2_IN_CH4
58
58
55
EADC2_GPU_VDD_0P75_ISENSE
IN
EADC2_GPU_VDD_1P8_ISENSE
IN
EADC2_PP5VGS_KBDLED_ISENSE
IN
GND_EADC2_COM
VOLTAGE=0V
56
123 58 56 55 53
59
OUT
PLACE_NEAR=U3900.AC5:5MM
R5710
0
5%
1/20W
MF
0201
C5711
1
0.1UF
10%
2
6.3V
CERM-X5R 0201
LOADISNS
BYPASS=U5710.12::5MM
0
5%
1/20W
MF
0201
1
2
R5713
PLACE_NEAR=U5710.6:1MM
PLACE_NEAR=U5710.25:1MM
72
CPUGT_ISNS2_N
IN
PLACE_NEAR=R7420.3:5MM
CPU SA Current Sense (ICSC)
Gain: 100x, EDP: 11.1 A Rsense: 0.002 (R7370) Vsense: 22.2 mV, Range: 16.5 A EADC1: CH5
CPU VCCIO Current Sense (ICIC)
Gain: 100x, EDP: 6.4 A Rsense: 0.003 (R8102) Vsense: 19.2 mV, Range: 11 A EADC1: CH2
123 58 54 53 46 39
EADC2
PP5V_EADC2_AVDD
C5712
1
4.7UF
20%
2
10V
X5R-CERM 0402
LOADISNS
CH0
22
CH1
23
CH2
24
CH3
1
CH4
2
CH5
3
CH6
4
CH7
5
COM
6
XW5710
SM
12
CRITICAL
LOADISNS
9
1011181920
LOADISNS
NO_XNET_CONNECTION=1
123 71
123 71
123 78
123 78
C5713
1
0.1UF
10%
10V
2
X5R-CERM 0201
LOADISNS
12
13
DVDDAVDD
BYPASS=U5710.21::5MM
21
U5710
LTC2309
QFN
GND
BYPASS=U5710.8::5MM
THRM
AD0 AD1
SDA
SCL
VREF
REFCOMP
PAD
25
14 15
17 16
7
8
1
2
R5757
4.42K
1 2
0.1%
1/20W
MF
0201
IN
IN
IN
IN
ADC2_REFCOMP
C5715
0.1UF
10%
6.3V
CERM-X5R 0201
LOADISNS
CPUSA_ISNS_P
PLACE_NEAR=R7370.3:10MM
CPUSA_ISNS_N
PLACE_NEAR=R7370.4:10MM
ISNS_CPUVCCIO_POS
PLACE_NEAR=R8102.3:5MM
ISNS_CPUVCCIO_NEG
PLACE_NEAR=R8102.4:5MM
BYPASS=U5710.21::5MM
C5714
1
4.7UF
20%
10V
2
X5R-CERM 0402
LOADISNS
EADC2_AD0
R5712
100K
1 2
5% MF
PP5V_G3S
BOMOPTION=NOSTUFF
2011/20W
I2C_SNS0_S0_5V_SCL
PP2V5_ADC2_VREF
1
C5716
10UF
20%
10V
2
X5R-CERM 0402-10
BYPASS=U5710.8::5MM
LOADISNS
53 54 55 56 58 118
PP3V3_G3SSW_SNS
LOADISNS
V+
6
U5770
IN+
2 3
IN+
IN-
4
IN-
5
53 54 55 56 58
PP3V3_G3SSW_SNS
118
LOADISNS
INA214A
UQFN
CRITICAL
100x
GND
9
6
V+
OUT
REF
NC NC
10 8 1
7
U5780
IN+
2 3
IN+
IN-
4
IN-
5
(Write: 0x12 Read: 0x13)
54 56 118
51 51
BIBI
51
IN
1
C5710
2.2UF
20%
2
6.3V
X5R-CERM 0201
BYPASS=U5710.7::5MM
LOADISNS
INA214A
UQFN
CRITICAL
100x
GND
9
BOM_COST_GROUP=SENSORS
OUT
REF
NC NC
10 8 1
7
LOADISNS
LOADISNS
BYPASS=U5770.6::5MM
C5770
1
0.1UF
10%
2
6.3V X7R 0201
ISNS_CPUSA_IOUT
1
R5775
NC NC
20K
5% 1/20W MF 201
2
NOSTUFF
PLACE_NEAR=U5770.10:5MM
LOADISNS
BYPASS=U5780.6::5MM
1
C5780
0.1UF
10%
6.3V
2
X7R 0201
ISNS_VCCIO_IOUT
1
R5785
NC NC
20K
5% 1/20W MF 201
2
NOSTUFF
LOADISNS
PLACE_NEAR=U5700.3:5MM
R5779
45.3K
1 2
1%
1/20W
MF
201
EADC1_CPUSA_ISENSE
C5779
1
2.2UF
20%
2
6.3V X5R-CERM 0201
LOADISNS
PLACE_NEAR=U5700.3:5MM
GND_EADC1_COM
LOADISNS
R5789
45.3K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U5700.24:5MM
EADC1_VCCIO_ISENSE
C5789
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
LOADISNS
PLACE_NEAR=U5700.24:5MM
GND_EADC1_COM
PAGE TITLE
Power Sensors Extended 2
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
56
56
DRAWING NUMBER
REVISION
BRANCH
PAGE
SHEET
123 58 56 55 53
123 58 56 55 53
051-04492
2.15.0
57 OF 200
56 OF 135
SIZE
D
C
B
A
SYNC_DATE=01/17/2019SYNC_MASTER=RAYMOND
8
67
35 4
2
1
Page 57
Vinafix.com
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3 245
1
D
Thermal Sensor A: Thunderbolt Die, Airflow Left
U5850 I2C Address:TMP461 A1->Floating A0->Floating 0X98/0X99
Thermal Diode: TBT Die (TTLD)
Placement Note: The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AC22.
Thermal Sensor C: Thunderbolt Die, Air Flow Right
U5800 I2C Address:TMP461 A1->Floating A0->GND 0X96/0X97
28
27
R5850
PP1V8_S5
80
BI
BI
TBTTHMSNS_X_D1_P
TBTTHMSNS_X_D1_N
TBTTHMSNS_X_D1_P
MAKE_BASE=TRUE
TBTTHMSNS_X_D1_N
MAKE_BASE=TRUE
PLACE_NEAR=U5850.2:5MM
PLACE_NEAR=U5850.3:5MM
Note: Use GND pin AC22 on U2800 for N leg.
47
1 2
5%
1/20W
MF
201
C5851
2200PF
10% 10V
X7R-CERM
0201
PP1V8_S5_TBTTHMSNS_X_R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V
1
2
2
D+
3
D-
5
NC NC
A0
10
TMP461-S
CRITICAL
1
V+
U5850
WQFN
ALERT*/THERM2*
GND
6
Thermal Diode: Airflow Left Proximity (TaLC)
SCL
SDA
THERM*A1
BYPASS=U5850.1::6MM
C5850
1
0.1UF
10%
2
6.3V CERM-X5R 0201
9 8 7 4
I2C_SNS1_S0_SCL I2C_SNS1_S0_SDA
NC NC
51
BI
D
51
BI
C
THERMAL DIODE: CPU PROX (KEY TC0P)
Placement Note:
Place Q5871 under the CPU ON BOTTOM SIDE
TSNS_T1_DX1_P
Q5871.3:2MM
3
1
Q5871
PMBT3904MB
SOT883
2
C5871
1
100PF
5% 25V
0201
C0G
2
NO_XNET_CONNECTION=1
57
Thermal Diode: TBT Die (TTRD)
Placement Note:
The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AC22.
THERMAL DIODE: FIN STACK LEFT (KEY TH2H)
Placement Note:
Place Q5872,AIRFLOW THERMAL INDICATOR,ABOVETHE X100, ON THE TOP SIDE
TSNS_T1_DX2_P
Q5872.3:2MM
3
1
Q5872
PMBT3904MB
SOT883
2
C5872
1
100PF
0201 5% 25V
2
C0G
NO_XNET_CONNECTION=1
57
107
108
PP1V8_S5
80
TBTTHMSNS_T_D1_P
BI
TBTTHMSNS_T_D1_N
BI
Note: Use GND pin AC22 on UB000 for N leg.
TBTTHMSNS_T_D1_P
MAKE_BASE=TRUE
TBTTHMSNS_T_D1_N
MAKE_BASE=TRUE
R5800
47
1 2
5%
1/20W
MF
201
PLACE_NEAR=U5800.2:5MM
C5801
2200PF
X7R-CERM
PLACE_NEAR=U5800.3:5MM
Placement Note: Place U5850 on the TOP side, on the left portion of the board, 1" to the right of USB connector.
PP1V8_S5_TBTTHMSNS_T_R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V
1
10% 10V
2
0201
2
D+
3
D-
5
A0
NC
10
1
CRITICAL
V+
U5800
TMP461
QFN
ALERT*/THERM2*
GND
6
BYPASS=U5800.1::5MM
1
C5800
0.1UF
10%
6.3V
2
CERM-X5R 0201
I2C_SNS1_S0_SCL
9
SCL
8
SDA
THERM*A1
I2C_SNS1_S0_SDA
7 4
NC NC
51
BI
51
BI
C
B
TSNS_T1_DX1_N
57
THERMAL DIODE: FIN STACK RIGHT (KEY TH1H)
Placement Note:
Place Q5873 AT THE CORNER NEAR RIGHT FAN, ON THE TOP SIDE
TSNS_T1_DX3_P
Q5873.3:2MM
3
1
Q5873
PMBT3904MB
SOT883
2
C5873
1
100PF
5%
2
020125V
C0G
NO_XNET_CONNECTION=1
TSNS_T1_DX3_N
THERMAL DIODE: X100 PROXIMITY (KEY TW0P)
57
57
TSNS_T1_DX2_N
57
THERMAL DIODE: Memory Proximity (KEY TM0P)
Place Q5874 between two rows of Memory devices, between channel A and CHANNEHL b PN BOTTOM SIDES
TSNS_T1_DX4_P
57
Q5874.3:2MM
3
1
Q5874
PMBT3904MB
SOT883
2
C5874
1
100PF
5% 0402 50V C0G
2
NO_XNET_CONNECTION=1
TSNS_T1_DX4_N
57
THERMAL DIODE: GPU PROXIMITY(TG0P )
80
MLB THERMAL SENSE 1 (TMP468)
I2C DEVICE ADDRESS 0X48: I2C WRITE 0X90, I2C READ 0X91
TSNS_T1_DX1_P
57
TSNS_T1_DX2_P
57
TSNS_T1_DX3_P
57
TSNS_T1_DX4_P
57
TSNS_T1_DX5_P
57
TSNS_T1_DX6_P
57
TSNS_T1_DX7_P
57
TSNS_T1_DX8_P
57
PP1V8_S5
R5870
10
1 2
5%
1/20W
MF
201
Thermal Diode: Airflow Right Proximity (TaRC)
Placement Note: Place U5800 on the TOP side, on the left portion of the board, 1" to the right of USB connector.
PP1V8_S5_CPUTHMSNS_R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1020
VOLTAGE=1.8V
A1 B1 C1 D1 A2 B2 C2 D2
D1+ D2+ D3+ D4+ D5+ D6+ D7+ D8+
D3
V+
U5870
TMP468
DSBGA
CRITICAL
SCL
SDA
THERM2*
THERM*
1
C5870
2
D4
C4
C3
B3
0.1UF
10%
6.3V CERM-X5R 0201
I2C_SNS1_S0_SCL I2C_SNS1_S0_SDA
NC NC
51
IN
51
BI
B
A
Place Q5875 near X100 on bottom
TSNS_T1_DX5_P
Q5875.3:2MM
3
1
Q5875
PMBT3904MB
SOT883
2
C5875
1
100PF
5%
0402
50V
C0G
2
NO_XNET_CONNECTION=1
TSNS_T1_DX5_N
THERMAL DIODE: GPU VR PROXIMITY(TG1P )
57
57
Place Q5877 near GPU VR, Bottom side
TSNS_T1_DX7_P
Q5877.3:2MM
3
1
Q5877
PMBT3904MB
SOT883
2
C5877
1
100PF
5%
0402
50V C0G
2
NO_XNET_CONNECTION=1
TSNS_T1_DX7_N
57
57
Place Q5876 near GPU, Top side, Opposite side of GPU
TSNS_T1_DX6_P
57
Q5876.3:2MM
3
1
Q5876
PMBT3904MB
SOT883
2
C5876
1
100PF
5% 50V
0402
C0G
2
NO_XNET_CONNECTION=1
TSNS_T1_DX6_N
57
THERMAL DIODE: GPU VRAM PROXIMITY(TGVP )
Place Q5878 near GPU VRAM.
TSNS_T1_DX8_P
Q5878.3:2MM
3
1
Q5878
PMBT3904MB
SOT883
2
C5878
1
100PF
5%
0402
50V C0G
2
NO_XNET_CONNECTION=1
TSNS_T1_DX8_N
57
57
57
TSNS_T1_DX1_N
57
TSNS_T1_DX2_N
57
TSNS_T1_DX3_N
57
TSNS_T1_DX4_N
57
TSNS_T1_DX5_N
57
TSNS_T1_DX6_N
TSNS_T1_DX7_N
57
TSNS_T1_DX8_N
57
XW5801
NO_XNET_CONNECTION=1
XW5802
NO_XNET_CONNECTION=1
XW5803
NO_XNET_CONNECTION=1
XW5804
NO_XNET_CONNECTION=1
XW5805
NO_XNET_CONNECTION=1
XW5806
NO_XNET_CONNECTION=1
XW5807
NO_XNET_CONNECTION=1
XW5808
NO_XNET_CONNECTION=1
NO_XNET_CONNECTION=1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
SM
SM
SM
SM
SM
SM
SM
SM
U5870.A3:10MM U5870.A3:10MM U5870.A3:10MM
U5870.A3:10MM U5870.A3:10MM
U5870.A3:10MM
MLB PROX 2 is read from the on-chip temp sensors U5870
U5870.A3:10MM
NOSTUFF
1
C5891
2.2PF
+/-0.1PF 25V
2
C0G-CERM 0201
U5870.B1:10MM
NOSTUFF
1
C5880
2.2PF
+/-0.1PF 25V
2
C0G-CERM 0201
NO_XNET_CONNECTION=1
Place U5870 near Calpe (U7800)
U5870.B1:10MM
NOSTUFF
1
C5881
2.2PF
+/-0.1PF 25V
2
C0G-CERM 0201
NO_XNET_CONNECTION=1
TSNS_T1_DN
CPUTHMSNS_ADD
1
R5880
100K
5% 1/20W MF 201
2
A3
B4
D-
ADD
BOM_COST_GROUP=SENSORS
GND
A4
SYNC_MASTER=RAYMOND SYNC_DATE=02/12/2019
PAGE TITLE
Thermal Sensors
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
58 OF 200
SHEET
57 OF 135
A
8
67
35 4
2
1
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D
CPU Core Voltage Sense (VCAC)
CALPE : AMUX-A1
XW5900
PPVCC_S0_CPU
6 8 117
SM
1 2
PLACE_NEAR=R7210.2:5 MM
CPUVSENSE_IN
PLACE_NEAR=U7800.A15:5MM
R5900
1 2
CPU GT Voltage Sense (VCTC)
EADC1: CH4
XW5910
SM
PPVCCGT_S0_CPU
8 117
1 2
PLACE_NEAR=R7410.2:5 MM
CPUGTVSENSE_IN
PLACE_NEAR=U5700.2:5MM
4.53K
1%
1/20W
MF
201
R5910
45.3K
1 2
1%
1/20W
MF
201
CPU SA Voltage Sense (VCSC)
EADC1: CH6
XW5930
SM
PMU_CPU_VSENSE CPUSAVSENSE_IN
C5900
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
PLACE_NEAR=U7800.A15:5MM
OUT OUT
GND_CALPE_AVSS
EADC1_CPUGT_VSENSE
1
C5910
2.2UF
20%
2
6.3V
X5R-CERM 0201
PLACE_NEAR=U5700.2:5MM
OUT
GND_EADC1_COM
123 59 123 56
123 96 76 58 55 54 53
123 56
123 58 56 55 53
PPVCCSA_S0_CPU
8 117 126
1 2
GPU SENSORS
R5930
45.3K
1 2
1%
1/20W
MF
201
EADC1_CPUSA_VSENSE
C5930
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
GND_EADC1_COM
GPU GFX Voltage Sense (VG0C)
Voltage Range: 0.7-1.075V CALPE: AMUX-A3
(PRODUCTION)
126 123 121 104 100 99
123 58 56 55 53
PPGFX_S0_GPU
XW5980
SM
1 2
R5980
GPUCOREVSENSE_IN PMU_GPU_GFX_VSENSE
4.53K
1 2
1/20W
PLACE_NEAR=U7800.B14:5MM
1% MF
201
PLACE_NEAR=U7800.B14:5MM
C5980
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
GND_CALPE_AVSS
VOLTAGE=0V
OUT
123
123 59
D
9676 58 55 54 53
GPU SOC Voltage Sense (VG1C)
Voltage Range: 0.7-1.075V
CALPE: AMUX-B0
XW5982
(PRODUCTION)
126 123 121 104 99
PPSOC_S0_GPU
SM
1 2
GPUSOCVSENSE_IN
R5982
45.3K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U7800.D13:5MM
PMU_GPU_SOC_VSENSE
PLACE_NEAR=U7800.D13:5MM
1
C5982
2.2UF
20%
2
6.3V
X5R-CERM 0201
OUT
123 59
C
126 123 106
126 123 121 116 99 98 97 94 93
115 105 103
127
GPU 1.8V Current Sense (IG3C)
Gain: 200x, EDP: 3A Rsense: 0.002 (R5960) Vsense: 6mV, Range: 8.25A EADC2: CH6
PP1V8_S0_GPU_REG
SENSOR:DEV
CRITICAL
PP1V8_S0_GPU
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V
R5960
0.002
1%
1/2W
MF
0306
123
PLACE_NEAR=R5960.3:5MM
ISNS_GPU_1V8_P
4
ISNS_GPU_1V8_N
PLACE_NEAR=R5960.4:5MM
PP3V3_G3SSW_SNS
53 54 55 56 58 118
LOADISNS
IN+
2 3
IN+
IN-
4
IN-
5
6
V+
U5960
INA210A
UQFN
CRITICAL
200x
GND
9
OUT
REF
NC NC
LOADISNS
BYPASS=U5960.6::5MM
C5960
1
0.1UF
10%
2
6.3V
CERM-X5R 0201
ISNS_GPU1V8_IOUT
10 8 1
NC
7
NC
1
R5961
20K
5% 1/20W MF 201
2
NOSTUFF
PLACE_NEAR=U5960.10:5MM
LOADISNS
PLACE_NEAR=U5710.3:5MM
R5962
45.3K
1 2
1%
1/20W
MF
201
EADC2_GPU_VDD_1P8_ISENSE
C5962
1
2.2UF
20%
2
6.3V
X5R-CERM 0201
GND_EADC2_COM
LOADISNS
PLACE_NEAR=U5710.3:5MM
OUT
56
GND_CALPE_AVSS
123 96 76 58 55 54 53
GPU HIGH SIDE Current Sense (IG0R)
Gain: 200x, EDP: 4 A Rsense: 0.002 (R5990) or Rsense SHORT Vsense: 8 mV, Range: 7.82 A SMC ADC: 05
(PRODUCTION)
117
117
123 96 58 56 55 54
PPBUS_G3H
PPBUS_HS_GPU
CRITICAL
R5990
0612
CYN
1W 1%
0.002
2
4
3
1
PLACE_NEAR=R5990.4:8MM
123
ISNS_GPU_HS_N
123
53 54 55 56 58 118
PP3V3_G3SSW_SNS
PLACE_NEAR=R5990.3:8MM
BYPASS=U5990.6::5MM
C5990
1
6
V+
U5990
INA210A
IN+
2 3
IN+
UQFN
CRITICAL
200x
IN-
4
IN-
5
GND
9
OUT
REF
NC NC
10 8 1
7
0.1UF
10%
2
6.3V
CERM-X5R 0201
ISNS_GPU_HS_IOUT
NOSTUFF
1
NC NC
R5994
15K
5% 1/20W MF 201
2
PLACE_NEAR=U5990.6:5MM
R5992
7.5K
1 2
1%
1/20W
MF
201
PLACE_NEAR=U3900.AH2:5MM
SMC_GPU_HS_ISENSEISNS_GPU_HS_P
PLACE_NEAR=U3900.AH2:5MM
1
C5992
0.022UF
10%
6.3V
X5R-CERM
2
0201
GND_SMC_AVSS
1%
1/20W
MF
201
1
2
R5993
4.99K
PLACE_NEAR=U3900.AH2:5MM
OUT
59
123 56 54 53 46 39
C
B
GPU 0.75V Current Sense (IG5C)
Gain: 100x, EDP: 10A Rsense: 0.002 (RA950) Vsense: 20mV, Range: 16.5A EADC2: CH5
123 106
123 106
IN
IN
PVDD075GPU_ISNS_P
PVDD075GPU_ISNS_N
53 54 55 56 58 118
PP3V3_G3SSW_SNS
2
IN+
3
IN+
4
IN-
5
IN-
LOADISNS
6
V+
U5970
INA214A
UQFN
CRITICAL
100x
GND
9
OUT
REF
NC NC
10
ISNS_GPUFBIC_IOUT
8 1
NC
7
NC
LOADISNS
BYPASS=U5970.6::5MM
C5970
1
0.1UF
10%
2
6.3V
CERM-X5R 0201
1
R5971
20K
5% 1/20W MF 201
2
NOSTUFF
PLACE_NEAR=U5970.10:5MM
LOADISNS
PLACE_NEAR=U5710.3:5MM
R5972
45.3K
1 2
1%
1/20W
MF
201
EADC2_GPU_VDD_0P75_ISENSE
C5972
1
2.2UF
20%
2
6.3V
X5R-CERM 0201
GND_EADC2_COM
LOADISNS
PLACE_NEAR=U5710.3:5MM
OUT
123 96 58 56 55 54
B
56
A
8
SYNC_MASTER=
PAGE TITLE
SYNC_DATE=01/17/2019
A
Power Sensor Extended 3
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SENSORS
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
59 OF 200
SHEET
58 OF 135
1
SIZE
D
Page 59
Vinafix.com
D
C
FAN CONNECTOR
PP1V8_G3S
59 118
R6000
47K
5%
1/20W
MF
201
12
S G
DMN32D2LFB4
SYM_VER_2
DFN1006H4-3
R6050
47K
1/20W
201
12
SYM_VER_2
39
SMC_FAN_0_PWM
IN
59 118
PP1V8_G3S
NOSTUFF
R6001
100K
1/20W
R6002
100K
1/20W
NOSTUFF
R6051
100K
1/20W
5% MF
201
5% MF
201
5% MF
201
R6005
59 39
1
2
1
2
OUT
SMC_FAN_0_TACH
47K
1 2
5%
1/20W
MF
201
R6055
59 39
1
2
SMC_FAN_1_TACH
OUT
47K
1 2
5%
1/20W
MF
201
1
2
FAN_LT_TACH
Q6000
D
FAN_LT_PWM
3
1
5% MF
2
FAN_RT_TACH
Q6050
DMN32D2LFB4
DFN1006H4-3
678
3 245
1
H9M SMC ADC Assignments
MAKE_BASE=TRUE
123 53
J6001
FF14A-6C-R11DL-B-3H
PP5V_G3S
59 118
122 59
FAN_LT_TACH TP_FAN_LT_OTP1
F-RT-SM
7
1 2 3 4 5 6
8
PP5V_G3S
59 118
122 59 122 59
122 59 122 59
FAN_RT_PWMFAN_LT_PWM
FAN_RT_TACH TP_FAN_RT_OTP1 TP_FAN_RT_OTP2TP_FAN_LT_OTP2
FF14A-6C-R11DL-B-3H
J6000
F-RT-SM
7
1 2 3 4 5 6
8
123 53
123 53
123 53
53
58
54
56
IN
IN
IN
IN
IN
IN
IN
IN
SMC_DCIN_VSENSE
MAKE_BASE=TRUE
SMC_DCIN_ISENSE
MAKE_BASE=TRUE
SMC_PBUS_VSENSE
MAKE_BASE=TRUE
SMC_BMON_ISENSE
MAKE_BASE=TRUE
SMC_CPU_HI_ISENSE
MAKE_BASE=TRUE
SMC_GPU_HS_ISENSE
MAKE_BASE=TRUE
SMC_P3V3_WLAN_ISENSE
MAKE_BASE=TRUE
SMC_P3V3_CAPLE_ISENSE
SMC_DCIN_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_CPU_HI_ISENSE SMC_GPU_HS_ISENSE SMC_P3V3_WLAN_ISENSE SMC_P3V3_CAPLE_ISENSE
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
39
39
39
39
39
39
39
39
D
CALPE AMUX Assignments
77
OUT
122 59
FANTACH_DEBUG
59 39
SMC_FAN_0_TACH
SMC_FAN_1_TACH
59 39
122 59
R6060
0
1 2
5%
1/20W
MF
0201
FANTACH_DEBUG
R6061
0
1 2
5%
1/20W
MF
0201
UPC_TA_DBG0
110
UPC_TA_DBG1
110
77
OUT
77
OUT
77
OUT
77
OUT
77
OUT
77
OUT
77
OUT
77 123 58
OUT IN
77
OUT
77
OUT
77
OUT
77
OUT
77
OUT
77
OUT
77
OUT
PMU_CPU_ISENSE PMU_CPU_VSENSE PMU_GPU_GFX_ISENSE PMU_GPU_GFX_VSENSE PMU_GPU_SOC_ISENSE PMU_P1V8_WLAN_ISENSE PMU_CPUDDR_ISENSE PMU_DDR1V2_ISENSE
PMU_GPU_SOC_VSENSE
PMU_PBUS_MAIN_SSD0_ISENSE PMU_PBUS_MAIN_SSD1_ISENSE PMU_P3V3_G3W_SSD0_ISENSE PMU_P3V3_G3W_SSD1_ISENSE PMU_3V3_X_HI_ISENSE PMU_3V3_T_HI_ISENSE PMU_OTHER5V_HI_ISENSE
MAKE_BASE=TRUE
PMU_CPU_ISENSE
MAKE_BASE=TRUE
PMU_CPU_VSENSE
MAKE_BASE=TRUE
PMU_GPU_GFX_ISENSE
MAKE_BASE=TRUE
PMU_GPU_GFX_VSENSE
MAKE_BASE=TRUE
PMU_GPU_SOC_ISENSE
MAKE_BASE=TRUE
PMU_P1V8_WLAN_ISENSE
MAKE_BASE=TRUE
PMU_CPUDDR_ISENSE
MAKE_BASE=TRUE
PMU_DDR1V2_ISENSE
MAKE_BASE=TRUE
PMU_GPU_SOC_VSENSE
MAKE_BASE=TRUE
PMU_PBUS_MAIN_SSD0_ISENSE
MAKE_BASE=TRUE
PMU_PBUS_MAIN_SSD1_ISENSE
MAKE_BASE=TRUE
PMU_P3V3_G3W_SSD0_ISENSE
MAKE_BASE=TRUE
PMU_P3V3_G3W_SSD1_ISENSE
MAKE_BASE=TRUE
PMU_3V3_X_HI_ISENSE
MAKE_BASE=TRUE
PMU_3V3_T_HI_ISENSE
MAKE_BASE=TRUE
PMU_OTHER5V_HI_ISENSE
54
IN
IN
IN
IN
IN
IN
IN
IN
123 58
123 96
123 58
123 96
54
54
54
C
55
IN
55
IN
55
IN
55
IN
53
IN
53
IN
53
IN
B
39
SMC_FAN_1_PWM
IN
R6052
100K
5%
1/20W
MF
201
S G
1
D
FAN_RT_PWM
3
122 59
B
2
A
8
SYNC_MASTER=ARMIN SYNC_DATE=01/17/2019
PAGE TITLE
A
Fans/SMC/AMUX Support
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=FAN
67
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IV ALL RIGHTS RESERVED
2
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PAGE
60 OF 200
SHEET
59 OF 135
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SIZE
D
Page 60
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678
3 245
1
D
D
C
C
B
B
A
8
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
Audio Placeholder
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=AUDIO
67
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IV ALL RIGHTS RESERVED
2
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AUDIO JACK CODEC I2C ADDRESS
678
3 245
1
D
AD1 GND GND
1.8V
1.8V
AD0
ADDRESS 0x48 <--GND
1.8V 0x49 GND
1.8V
0x4A 0x4B
PP1V8_AUDIO
61
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
118 61 52
PP1V8_G3S
1 2
FERR-22-OHM-1A-0.055OHM
VOLTAGE=1.8V
FERR-22-OHM-1A-0.055OHM
R6361
0
5%
1/20W
MF
0201
1 2
1 2
61 122 124
PP1V8_AUDIO
VOLTAGE=1.8V
L6300
0201
L6303
0201
GND_AUDIO_CODEC
61
MAX CURRENT = 100mA
PP1V8_L83_VCP
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V
MAX CURRENT = 5mA
PP1V8_L83_VA
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V
C6301
1
2.2UF
10%
2
10V
X5R-CERM 0402
PLACE_NEAR=U6300.B1:5 MM
D
C
B
A
64
64
L6301
PP1V8_G3S
118 61 52
FERR-22-OHM-1A-0.055OHM
1 2
0201
C6303
0.1UF
X7R-CERM
10%
16V
0402
1
2
L6302
FERR-22-OHM-1A-0.055OHM
PP3V3_G3H_T
118
0201
NOSTUFF
D6300
X3-WLB1608
PP3V3_G3S_T
118
64
OUT
61 122 124
64
OUT
64
64
PP3V3_L83_VP
61
IN IN
AUD_RING_SENSE AUD_TIP_SENSE
AUD_HP_PORT_L
GND_AUDIO_CODEC
AUD_HP_PORT_R
IN
IN
NOSTUFF
R6309
AUD_HS_MIC_P
AUD_HS_MIC_N
470K
5%
1/20W
MF
201
1
2
1
2
R6310
470K
5% 1/20W MF 201
NOSTUFF
1
R6300
1K
5% 1/20W MF 201
2
1
R6301
1K
5% 1/20W MF 201
2
64
64
64
64
C6309
4.7UF
20%
6.3V X5R
0402
IN
IN
BI
BI
1
2
A K
SDM2U30CSP-7B-55
AUD_HP_SENSE_L
AUD_HP_SENSE_R
AUD_HP_PORT_CH_GND
AUD_HP_PORT_US_GND
L83_HSBIAS_FILT
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
PLACE_NEAR=U6300.F3:5 MM
PLACE_NEAR=U6300.E3:5 MM
L83_HSBIAS_FILT_REF
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
21
MAX CURRENT = 3mA
PP1V8_L83_VL
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V
PLACE_NEAR=U6300.A3:3 MM
MAX CURRENT = 1mA
61
PP3V3_L83_VP
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PLACE_NEAR=U6300.D7:5 MM
C6304
1
10UF
20%
10V
2
X5R-CERM 0402-7
VOLTAGE=3.3V
XW6300
SM
1 2
D5
HPSENSA
E5
HPOUTA
F5
HPSENSB
G5
HPOUTB
F1
HS4
E2
HS_CLAMP2
E1
HSIN+
G2
HS3
F2
HS_CLAMP1
D1
HSIN-
F4
HS4_REF
G4
HS3_REF
G3
RING_SENSE
E4
TIP_SENSE
F3
HSBIAS_FILT
E3
HSBIAS_FILT_REF
NC
A3
D7
VP
VL VA VCP
A7
VD_FILT
B1
CRITICAL
U6300
CS42L83A
WLCSP-SKT
GNDL
B3
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=0V
B6
C7
GNDHS GNDAGNDD
G1
D6
+VCP_FILT
-VCP_FILT GNDCP
VL_SEL
DIGLDO_PDN*
INT*
WAKE*
RESET*
SPDIF_TX
SWIRE_SEL
ASP_LRCK/FSYNC
SWIRE_SD/ASP_SDIN
ASP_SDOUT
SWIRE_CLK/ASP_SCLK
AD0 AD1
SDA
SCL
FLYP FLYC FLYN
FILT_P
C2
D2
PLACE_NEAR=U6300.C1:5 MM
PLACE_NEAR=U6300.C2:5 MM
PLACE_NEAR=U6300.D6:5 MM
PLACE_NEAR=U6300.E6:5 MM
L83_VCP_FILTP
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
PLACE_NEAR=U6300.G6:5 MM
L83_VCP_FILTN
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
E6 G6
F6 C4 D4 B7 C6 C5
A6
NC
D3 B5 A5 A4 B4
C3 B2
A1 A2 E7 F7 G7
L83_FILT
C1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
L83_SDOUT
C6310
10UF
20%
10V
X5R
0603
1
2
C6302
2.2UF
1 2
10%
10V
X5R-CERM
0402
C6305
4.7UF
1 2
20%
10V
X5R-CERM
0402
C6306
4.7UF
1 2
20%
10V
X5R-CERM
0402
PLACE_NEAR=U6300.A4:5mm
I2C_CODEC_SDA I2C_CODEC_SCL
L83_FLYP
L83_FLYC
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
L83_FLYN
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
PLACE_NEAR=U6300.F6:5 MM
PLACE_NEAR=U6300.F6:5 MM
R6307
33
1 2
1/20W 2015% MF
L83_VCP_FILT_GND
PP1V8_G3S
118 61 52
PP1V8_AUDIO
61
52
BI
52
IN
C6307
2.2UF
X5R-CERM
C6308
2.2UF
X5R-CERM
10%
10V
0402
10%
10V
0402
1
2
1
2
XW6301
SM
1 2
1
R6302
47K
5% 1/20W MF 201
2
1
2
1
2
I2S_CODEC_LRCLK_R
I2S_CODEC_R2D
I2S_CODEC_D2R
I2S_CODEC_BCLK
PLACE_NEAR=U6300.E7:5 MM
PLACE_NEAR=U6300.F7:5 MM PLACE_NEAR=U6300.F7:5 MM
PLACE_NEAR=U6300.G7:5 MM
BOM_COST_GROUP=AUDIO
PP1V8_G3S
R6303
47K
5% 1/20W MF 201
CODEC_INT_L CODEC_WAKE_L
R6304
47K
5% 1/20W MF 201
118 61 52
CODEC_RESET_L
C6320
1
1000PF
10%
25V
2
X7R 0201
OUT
OUT
OUT
IN
IN
IN
C
38
39
39
IN
B
47
47
40
47
DESIGN: X502/DEV_MLB_U LAST CHANGE: Wed Feb 18 17:31:01 2015
A
SYNC_DATE=01/17/2019SYNC_MASTER=ADRIEN
PAGE TITLE
Audio Jack Codec
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
63 OF 200
SHEET
61 OF 135
8
67
35 4
2
1
Page 62
Vinafix.com
D
62 47
63 62 40
62 47
62 47
PP1V8_G3S
62 118
I2S_SPKRAMP_L_R2D
IN
I2S_SPKRAMP_L_D2R
BI
I2S_SPKRAMP_L_LRCLK_R
IN
IN
I2S_SPKRAMP_L_BCLK
R6405
33
1 2
5% MF1/20W
MAX CURRENT = 15mA PER AMPLIFIER
PLACE_NEAR=U6400.C1:5 MM
1
C6400
1UF
20% 16V
2
CER-X5R 0201
63 62 38
62 52
62 52
PLACE_NEAR=U6400.E1:5 MM
BI
IN
63 62 38
62
I2S_SPKRAMP_L_D2R_R1
201
PLACE_NEAR=U6400.C1:3 MM
1
C6401
0.1UF
10% 25V
2
X5R 0201
I2C_SPKRAMP_L_SDA I2C_SPKRAMP_L_SCL
SPKRAMP_INT_L SPKRAMP_LW1_MODE
PLACE_NEAR=U6400.D2:5 MM
1
C6402
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6400.D2:3 MM
1
C6403
0.1UF
10% 25V
2
X5R 0201
678
MAX CURRENT = 2A PER AMPLIFIER
C1
AVDD IOVDD
TAS5770LC0YFF
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
D3 A5
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
D2
U6400
DSBGA
CRITICAL
GND
C2
PGND
A4
B4
C4
C5
VBAT
VSNS_P
VSNS_N
BST_P OUT_P OUT_P
BST_N
OUT_N OUT_N
AREG DREG
B2 A3 B3 A1
A2
B5 B1
D5
D1
PLACE_NEAR=U6400.C4:3 MM
1
C6404
0.1UF
10% 25V
2
X5R 0201
BYPASS=U6400.B2:B3:5 MM
NO_XNET_CONNECTION=1
PLACE_NEAR=U6400.C4:10 MM
CRITICAL
1
C6405
10UF
20% 25V
2
X5R-CERM 0603
SPKRAMP_LW1_BSTPSPKRAMP_RESET_L
DIDT=TRUE
SPKRAMP_LW1_OUTP SPKRAMP_LW1_SNSP
SPKRAMP_LW1_BSTN
DIDT=TRUE
SPKRAMP_LW1_OUTN SPKRAMP_LW1_SNSN
SPKRAMP_LW1_AREG
SPKRAMP_LW1_DREG
1
C6407
0.1UF
10% 25V
2
X5R 0201
1
C6408
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6400.C4:10 MM
CRITICAL
1
C6406
10UF
20% 25V
2
X5R-CERM 0603
C6411
0.1UF
1 2
10% 25V X5R
0201
C6412
0.1UF
1 2
10% 25V X5R
0201
1
C6409
0.1UF
10% 25V
2
X5R 0201
PLACE_NEAR=U6400.C4:10 MM
CRITICAL
1
C6450
10UF
20% 25V
2
X5R-CERM 0603
PLACE_NEAR=U6400.C4:10 MM
CRITICAL
1
C6451
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
R6406
1 2
PLACE_NEAR=U6400.A3:10 MM
BYPASS=U6400.A2:A5:5 MM NO_XNET_CONNECTION=1
0% 1/4W 0603MF
CRITICAL
R6407
1 2
PLACE_NEAR=U6400.A5:10 MM
0% 1/4W MF
1
C6410
1UF
20% 16V
2
CER-X5R 0201
PPBUS_G3H_SPKRAMPL
62
0
1 2
SM
XW6400
PLACE_NEAR=J6400.1:3 MM
0
0603
1 2
SM
XW6401
PLACE_NEAR=J6400.2:3 MM
PLACE_NEAR=U6400.D1:3 MM PLACE_NEAR=U6400.D1:5 MM PLACE_NEAR=U6400.D5:3 MM PLACE_NEAR=U6400.D5:5 MM
0.01
1
C6490
3.0PF
+/-0.1PF
2
25V NP0-C0G 0201
DIDT=TRUE
DIDT=TRUE
PLACE_NEAR=J6400.2:5 MM
NOSTUFF
C6413
220PF
10% 25V
X7R-CERM
201
SENSOR:DEV
CRITICAL
122
1
2
R6470
12 34
TP_ISNS_SKPRLP
0612-6 MF0.5%1W
TP_ISNS_SKPRLN
NO_XNET_CONNECTION=1
SPKRCONN_LW1_OUTP
122
LEFT WOOFER 1
SPKRCONN_LW1_OUTN
PLACE_NEAR=J6400.1:5 MM
NOSTUFF
1
C6414
220PF
10% 25V
2
X7R-CERM 201
3 245
PP1V8_G3S
62 118
PPBUS_G3H
63 117
63 62 38
63 62 38
OUT
IN
SPKRAMP_INT_L SPKRAMP_RESET_L
NOSTUFF
R6400
47K
5%
1/20W
MF
201
1
1
2
1
R6401
47K
5% 1/20W MF 201
2
D
APN: 518S0818
J6400
FF14A-6C-R11DL-B-3H
F-RT-SM
7
1 2 3 4 5 6
8
C
B
62 47
63 62 40
62 47
62 47
PP1V8_G3S
62 118
I2S_SPKRAMP_L_R2D
I2S_SPKRAMP_L_D2R
5% MF1/20W
I2S_SPKRAMP_L_LRCLK_R
I2S_SPKRAMP_L_BCLK
R6425
33
1 2
MAX CURRENT = 15mA PER AMPLIFIER
PLACE_NEAR=U6420.C1:5 MM
1
C6420
1UF
20% 16V
2
CER-X5R 0201
63 62 38
52 62
52 62
63 62 38
62
PLACE_NEAR=U6420.E1:5 MM
I2S_SPKRAMP_L_D2R_R2
201
PLACE_NEAR=U6420.C1:3 MM
1
C6421
0.1UF
10% 25V
2
X5R 0201
SPKRAMP_RESET_L I2C_SPKRAMP_L_SDA
I2C_SPKRAMP_L_SCL SPKRAMP_INT_L SPKRAMP_LW2_MODE
PLACE_NEAR=U6420.D2:5 MM
1
C6422
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6420.D2:3 MM
1
C6423
0.1UF
10% 25V
2
X5R 0201
MAX CURRENT = 2A PER AMPLIFIER
C1
AVDD IOVDD
D2
C4
C5
VBAT
U6420
TAS5770LC0YFF
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
D3 A5
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
DSBGA
CRITICAL
GND
C2
PGND
A4
B4
BST_P OUT_P OUT_P
VSNS_P
BST_N
OUT_N OUT_N
VSNS_N
AREG DREG
B2 A3 B3 A1
A2
B5 B1
D5
D1
PLACE_NEAR=U6420.C4:3 MM
1
C6424
0.1UF
10% 25V
2
X5R 0201
BYPASS=U6420.B2:B3:5 MM
NO_XNET_CONNECTION=1
PLACE_NEAR=U6420.C4:10 MM
CRITICAL
1
C6425
10UF
20% 25V
2
X5R-CERM 0603
SPKRAMP_LW2_BSTP
DIDT=TRUE
SPKRAMP_LW2_OUTP SPKRAMP_LW2_SNSP
SPKRAMP_LW2_BSTN
DIDT=TRUE
SPKRAMP_LW2_OUTN SPKRAMP_LW2_SNSN
SPKRAMP_LW2_AREG
SPKRAMP_LW2_DREG
1
C6427
0.1UF
10% 25V
2
X5R 0201
1
C6428
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6420.C4:10 MM
CRITICAL
1
C6426
10UF
20% 25V
2
X5R-CERM 0603
C6431
0.1UF
1 2
10% 25V X5R
0201
C6432
0.1UF
1 2
10% 25V X5R
0201
1
C6429
0.1UF
10% 25V
2
X5R 0201
PLACE_NEAR=U6420.C4:10 MM
CRITICAL
1
C6454
10UF
20% 25V
2
X5R-CERM 0603
PLACE_NEAR=U6420.C4:10 MM
CRITICAL
1
C6455
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
R6426
PPBUS_G3H_SPKRAMPL
0
1 2
0% MF
PLACE_NEAR=U6420.A3:10 MM
BYPASS=U6420.A2:A5:5 MM NO_XNET_CONNECTION=1
1/4W
0603
CRITICAL
R6427
0
1 2
MF0% 1/4W
PLACE_NEAR=U6420.A5:10 MM
1
C6430
1UF
20% 16V
2
CER-X5R 0201
0603
PLACE_NEAR=U6420.D1:3 MM PLACE_NEAR=U6420.D1:5 MM PLACE_NEAR=U6420.D5:3 MM PLACE_NEAR=U6420.D5:5 MM
1 2
SM
XW6420
PLACE_NEAR=J6400.3:3 MM
1 2
SM
PLACE_NEAR=J6400.4:10 MM
XW6421
PLACE_NEAR=J6400.4:3 MM
62
NOSTUFF
C6433
220PF
10% 25V
X7R-CERM
201
I2C bus 0 ADDRESS
CHANNEL
L WF 1 L WF 2
C
L TW
SPKRCONN_LW2_OUTP
122
MODE PIN GND 470 to GND 470 to IOVDD 2k2 to GND 2k2 to IOVDD 10k to GND 10k to IOVDD 47k to IOVDD
7-BIT
0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38
PP1V8_G3S
62 118
NOSTUFF
1
LEFT WOOFER 2
SPKRAMP_LW1_MODE
62
SPKRCONN_LW2_OUTN
122
PLACE_NEAR=J6400.3:5 MM
NOSTUFF
1
2
1
C6434
220PF
10% 25V
2
X7R-CERM 201
SPKRAMP_LW2_MODE
62
SPKRAMP_LT_MODE
62
R6480
10K
5% 1/20W MF 201
2
1
R6481
470
5% 1/20W MF 201
2
NOSTUFF
1
R6482
2.2K
5% 1/20W MF 201
2
1
R6483
0
5% 1/20W MF 0201
2
1
R6484
2.2K
5% 1/20W MF 201
2
NOSTUFF
1
R6485
0
5% 1/20W MF 0201
2
B
A
62 47
63 62 40
62 47
62 47
PP1V8_G3S
62 118
I2S_SPKRAMP_L_R2D
I2S_SPKRAMP_L_D2R
5% MF1/20W
I2S_SPKRAMP_L_LRCLK_R
I2S_SPKRAMP_L_BCLK
R6465
33
1 2
MAX CURRENT = 15mA PER AMPLIFIER
PLACE_NEAR=U6460.C1:5 MM
1
C6460
1UF
20% 16V
2
CER-X5R 0201
63 62 38
52 62
52 62
63 62 38
62
PLACE_NEAR=U6460.E1:5 MM
I2S_SPKRAMP_L_D2R_R3
201
PLACE_NEAR=U6460.C1:3 MM
1
C6461
0.1UF
10% 25V
2
X5R 0201
SPKRAMP_RESET_L I2C_SPKRAMP_L_SDA
I2C_SPKRAMP_L_SCL SPKRAMP_INT_L SPKRAMP_LT_MODE
PLACE_NEAR=U6460.D2:5 MM
1
C6462
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6460.D2:3 MM
1
C6463
0.1UF
10% 25V
2
X5R 0201
MAX CURRENT = 2A PER AMPLIFIER
C1
AVDD IOVDD
D2
C4
C5
VBAT
U6460
TAS5770LC0YFF
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
D3 A5
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
DSBGA
CRITICAL
GND
C2
PGND
A4
B4
BST_P OUT_P OUT_P
VSNS_P
BST_N
OUT_N OUT_N
VSNS_N
AREG DREG
B2 A3 B3 A1
A2
B5 B1
D5
D1
PLACE_NEAR=U6460.C4:10 MM
PLACE_NEAR=U6460.C4:3 MM
1
C6464
0.1UF
10% 25V
2
X5R 0201
BYPASS=U6460.B2:B3:5 MM
NO_XNET_CONNECTION=1
CRITICAL
1
C6465
10UF
20% 25V
2
X5R-CERM 0603
SPKRAMP_LT_BSTP
DIDT=TRUE
SPKRAMP_LT_OUTP SPKRAMP_LT_SNSP
SPKRAMP_LT_BSTN
DIDT=TRUE
SPKRAMP_LT_OUTN SPKRAMP_LT_SNSN
SPKRAMP_LT_AREG
SPKRAMP_LT_DREG
1
C6467
0.1UF
10% 25V
2
X5R 0201
1
C6468
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6460.C4:10 MM
CRITICAL
1
C6466
10UF
20% 25V
2
X5R-CERM 0603
C6471
0.1UF
1 2
10% 25V X5R
0201
C6472
0.1UF
1 2
10% 25V X5R
0201
1
C6469
0.1UF
10% 25V
2
X5R 0201
PLACE_NEAR=U6460.C4:10 MM
CRITICAL
1
C6452
10UF
20% 25V
2
X5R-CERM 0603
PLACE_NEAR=U6460.C4:10 MM
CRITICAL
1
C6453
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
R6466
PPBUS_G3H_SPKRAMPL
0
1 2
1/4W 0603MF
PLACE_NEAR=U6460.A3:10 MM
BYPASS=U6460.A2:A5:5 MM NO_XNET_CONNECTION=1
0%
CRITICAL
R6467
0
1 2
PLACE_NEAR=U6460.A5:10 MM
0% 1/4W MF 0603
1
C6470
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6460.D1:3 MM PLACE_NEAR=U6460.D1:5 MM PLACE_NEAR=U6460.D5:3 MM PLACE_NEAR=U6460.D5:5 MM
62
1 2
SM
XW6460
PLACE_NEAR=J6400.5:3 MM
1 2
SM
XW6461
PLACE_NEAR=J6400.6:3 MM
PLACE_NEAR=J6400.6:5 MM
NOSTUFF
C6473
220PF
10% 25V
X7R-CERM
201
CAPDERATE
1
C6480
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
1
C6481
33UF
20% 16V
2
TANT-POLY CASE-B3-1
PPBUS_G3H_SPKRAMPL
CAPDERATE
1
C6482
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
1
C6483
33UF
20% 16V
2
TANT-POLY CASE-B3-1
62
PPBUS_G3H_SPKRAMPL
62
CAPDERATE
1
C6487
33UF
20%
2
16V TANT-POLY CASE-B3-1
SPKRCONN_LT_OUTP
122
CAPDERATE
1
C6484
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
1
C6485
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
1
C6486
33UF
20% 16V
2
TANT-POLY CASE-B3-1
LEFT TWEETER
SPKRCONN_LT_OUTN
122
SYNC_MASTER=ADRIEN SYNC_DATE=01/17/2019
PLACE_NEAR=J6400.5:5 MM
NOSTUFF
1
2
1
C6474
220PF
10% 25V
2
X7R-CERM 201
PAGE TITLE
Audio Left Amplifiers
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
SIZE
2.15.0
BRANCH
PAGE
64 OF 200
SHEET
62 OF 135
BOM_COST_GROUP=AUDIO
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
A
D
8
67
35 4
2
1
Page 63
Vinafix.com
678
3 245
1
D
63 47
63 62 40
63 47
63 47
PP1V8_G3S
63 118
I2S_SPKRAMP_R_R2D
IN
I2S_SPKRAMP_L_D2R
BI
I2S_SPKRAMP_R_LRCLK_R
IN
IN
I2S_SPKRAMP_R_BCLK
R6505
33
1 2
1/20W 201MF5%
MAX CURRENT = 15mA PER AMPLIFIER
PLACE_NEAR=U6500.C1:5 MM
1
C6500
1UF
20% 16V
2
CER-X5R 0201
63 62 38
63 52
63 52
PLACE_NEAR=U6500.E1:5 MM
BI
IN
63 62 38
63
I2S_SPKRAMP_R_D2R_R1
PLACE_NEAR=U6500.C1:3 MM
1
C6501
0.1UF
10% 25V
2
X5R 0201
SPKRAMP_RESET_L I2C_SPKRAMP_R_SDA
I2C_SPKRAMP_R_SCL SPKRAMP_INT_L SPKRAMP_RW1_MODE
PLACE_NEAR=U6500.D2:5 MM
1
C6502
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6500.D2:3 MM
1
C6503
0.1UF
10% 25V
2
X5R 0201
MAX CURRENT = 2A PER AMPLIFIER
C1
AVDD IOVDD
D2
C4
C5
VBAT
U6500
TAS5770LC0YFF
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
D3 A5
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
DSBGA
CRITICAL
GND
C2
PGND
A4
B4
BST_P OUT_P OUT_P
VSNS_P
BST_N OUT_N OUT_N
VSNS_N
AREG DREG
B2 A3 B3 A1
A2
B5 B1
D5
D1
PLACE_NEAR=U6500.C4:3 MM
1
C6504
0.1UF
10% 25V
2
X5R 0201
BYPASS=U6500.B2:B3:5 MM
NO_XNET_CONNECTION=1
PLACE_NEAR=U6500.C4:10 MM
CRITICAL
1
C6505
10UF
20% 25V
2
X5R-CERM 0603
SPKRAMP_RW1_BSTP
DIDT=TRUE
SPKRAMP_RW1_OUTP SPKRAMP_RW1_SNSP
SPKRAMP_RW1_BSTN
DIDT=TRUE
SPKRAMP_RW1_OUTN SPKRAMP_RW1_SNSN
SPKRAMP_RW1_AREG
SPKRAMP_RW1_DREG
1
C6507
0.1UF
10% 25V
2
X5R 0201
1
C6508
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6500.C4:10 MM
CRITICAL
1
C6506
10UF
20%
2
X5R-CERM 0603
C6511
0.1UF
1 2
10% 25V X5R
0201
C6512
0.1UF
1 2
10% 25V X5R
0201
1
C6509
0.1UF
10% 25V
2
X5R 0201
BYPASS=U6500.A2:A5:5 MM NO_XNET_CONNECTION=1
PLACE_NEAR=U6500.C4:10 MM
CRITICAL
1
C6550
10UF
20% 25V
225V
X5R-CERM 0603
PLACE_NEAR=U6500.C4:10 MM
CRITICAL
1
C6551
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
R6506
0
1 2
MF0% 1/4W
PLACE_NEAR=U6500.A3:10 MM
0603
PLACE_NEAR=J6500.1:3 MM
CRITICAL
R6507
0
1 2
1/4W MF 0603
PLACE_NEAR=U6500.A5:10 MM
0%
1
C6510
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=J6500.2:3 MM
PLACE_NEAR=U6500.D1:3 MM PLACE_NEAR=U6500.D1:5 MM PLACE_NEAR=U6500.D5:3 MM PLACE_NEAR=U6500.D5:5 MM
PPBUS_G3H
1 2
SM
XW6500
1 2
SM
XW6501
62 63 117
DIDT=TRUE
DIDT=TRUE
PLACE_NEAR=J6500.2:5 MM
NOSTUFF
C6513
220PF
10% 25V
X7R-CERM
201
122
1
2
122
SPKRCONN_RW1_OUTP
RIGHT WOOFER 1
SPKRCONN_RW1_OUTN
PLACE_NEAR=J6500.1:5 MM
NOSTUFF
1
C6514
220PF
10% 25V
2
X7R-CERM 201
APN: 518S0818
J6500
FF14A-6C-R11DL-B-3H
F-RT-SM
7
1 2 3 4 5 6
8
D
C
B
63 47
63 62 40
63 47
63 47
PP1V8_G3S
63 118
I2S_SPKRAMP_R_R2D
I2S_SPKRAMP_L_D2R
I2S_SPKRAMP_R_LRCLK_R
I2S_SPKRAMP_R_BCLK
R6525
33
1 2
MF1/20W5%
MAX CURRENT = 15mA PER AMPLIFIER
PLACE_NEAR=U6520.C1:5 MM
1
C6520
1UF
20% 16V
2
CER-X5R 0201
63 62 38
52 63
52 63
63 62 38
63
PLACE_NEAR=U6520.E1:5 MM
I2S_SPKRAMP_R_D2R_R2
201
PLACE_NEAR=U6520.C1:3 MM
1
C6521
0.1UF
10% 25V
2
X5R 0201
SPKRAMP_RESET_L I2C_SPKRAMP_R_SDA
I2C_SPKRAMP_R_SCL SPKRAMP_INT_L SPKRAMP_RW2_MODE
PLACE_NEAR=U6520.D2:5 MM
1
C6522
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6520.D2:3 MM
1
C6523
0.1UF
10% 25V
2
X5R 0201
MAX CURRENT = 2A PER AMPLIFIER
C1
AVDD IOVDD
D2
C4
C5
VBAT
U6520
TAS5770LC0YFF
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
D3 A5
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
DSBGA
CRITICAL
GND
C2
PGND
A4
B4
BST_P OUT_P OUT_P
VSNS_P
BST_N OUT_N OUT_N
VSNS_N
AREG DREG
B2 A3 B3 A1
A2
B5 B1
D5
D1
PLACE_NEAR=U6520.C4:3 MM
1
C6524
0.1UF
10% 25V
2
X5R 0201
BYPASS=U6520.B2:B3:5 MM
NO_XNET_CONNECTION=1
PLACE_NEAR=U6520.C4:10 MM
CRITICAL
1
C6525
10UF
20% 25V
2 25V
X5R-CERM 0603
SPKRAMP_RW2_BSTP
DIDT=TRUE
SPKRAMP_RW2_OUTP SPKRAMP_RW2_SNSP
SPKRAMP_RW2_BSTN
DIDT=TRUE
SPKRAMP_RW2_OUTN SPKRAMP_RW2_SNSN
SPKRAMP_RW2_AREG
SPKRAMP_RW2_DREG
1
C6527
0.1UF
10% 25V
2
X5R 0201
1
C6528
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6520.C4:10 MM
CRITICAL
1
C6526
10UF
20%
2
X5R-CERM 0603
C6531
0.1UF
1 2
10% 25V X5R
0201
C6532
0.1UF
1 2
10% 25V X5R
0201
1
C6529
0.1UF
10% 25V
2
X5R 0201
BYPASS=U6520.A2:A5:5 MM NO_XNET_CONNECTION=1
PLACE_NEAR=U6520.C4:10 MM
CRITICAL
1
C6554
10UF
20% 25V
2
X5R-CERM 0603
PLACE_NEAR=U6520.C4:10 MM
CRITICAL
1
C6555
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
R6526
0
1 2
PLACE_NEAR=U6520.A3:10 MM
1/4W0% MF 0603
PLACE_NEAR=J6500.3:3 MM
CRITICAL
R6527
0
1 2
PLACE_NEAR=U6520.A5:10 MM
1
C6530
1UF
20% 16V
2
CER-X5R 0201
0603MF1/4W0%
PLACE_NEAR=J6500.4:3 MM
PLACE_NEAR=U6520.D1:3 MM PLACE_NEAR=U6520.D1:5 MM PLACE_NEAR=U6520.D5:3 MM PLACE_NEAR=U6520.D5:5 MM
PPBUS_G3H
1 2
SM
XW6520
1 2
SM
XW6521
62 63 117
122
PLACE_NEAR=J6500.4:5 MM
NOSTUFF
C6533
220PF
10% 25V
X7R-CERM
201
1
2
122
SPKRCONN_RW2_OUTP
RIGHT WOOFER 2
SPKRCONN_RW2_OUTN
PLACE_NEAR=J6500.3:10 MM
NOSTUFF
1
C6534
220PF
10% 25V
2
X7R-CERM 201
GND 470 to GND 470 to IOVDD 2k2 to GND 2k2 to IOVDD 10k to GND 10k to IOVDD 47k to IOVDD
63 118
SPKRAMP_RW1_MODE
63
SPKRAMP_RW2_MODE
63
SPKRAMP_RT_MODE
63
MODE PIN
PP1V8_G3S
I2C BUS 1 ADDRESS
7-BIT
0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38
NOSTUFF
1
R6580
10K
5% 1/20W MF 201
2
1
R6581
470
5% 1/20W MF 201
2
CHANNEL
R WF 1 R WF 2
R TW
1
R6582
2.2K
5% 1/20W MF 201
2
1
R6583
0
5% 1/20W MF 0201
2
NOSTUFF
1
R6584
2.2K
5% 1/20W MF 201
2
NOSTUFF
1
R6585
0
5% 1/20W MF 0201
2
C
B
A
63 47
63 62 40
63 47
63 47
PP1V8_G3S
63 118
I2S_SPKRAMP_R_R2D
I2S_SPKRAMP_L_D2R
I2S_SPKRAMP_R_LRCLK_R
I2S_SPKRAMP_R_BCLK
R6565
33
1 2
1/20W MF5%
MAX CURRENT = 15mA PER AMPLIFIER
PLACE_NEAR=U6560.C1:5 MM
1
C6560
1UF
20% 16V
2
CER-X5R 0201
63 62 38
52 63
52 63
63 62 38
63
PLACE_NEAR=U6560.E1:5 MM
I2S_SPKRAMP_R_D2R_R3
201
PLACE_NEAR=U6560.C1:3 MM
1
C6561
0.1UF
10% 25V
2
X5R 0201
SPKRAMP_RESET_L I2C_SPKRAMP_R_SDA
I2C_SPKRAMP_R_SCL SPKRAMP_INT_L SPKRAMP_RT_MODE
PLACE_NEAR=U6560.D2:5 MM
1
C6562
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6560.D2:3 MM
1
C6563
0.1UF
10% 25V
2
X5R 0201
MAX CURRENT = 2A PER AMPLIFIER
C1
AVDD IOVDD
D2
C4
C5
VBAT
U6560
TAS5770LC0YFF
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
D3 A5
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
DSBGA
CRITICAL
GND
C2
PGND
A4
B4
BST_P OUT_P OUT_P
VSNS_P
BST_N OUT_N OUT_N
VSNS_N
AREG DREG
B2 A3 B3 A1
A2
B5 B1
D5
D1
PLACE_NEAR=U6560.C4:3 MM
1
C6564
0.1UF
10% 25V
2
X5R 0201
BYPASS=U6560.B2:B3:5 MM
NO_XNET_CONNECTION=1
PLACE_NEAR=U6560.C4:10 MM
CRITICAL
1
C6565
10UF
20%
2 25V
25V X5R-CERM 0603
SPKRAMP_RT_BSTP
DIDT=TRUE
SPKRAMP_RT_OUTP SPKRAMP_RT_SNSP
SPKRAMP_RT_BSTN
DIDT=TRUE
SPKRAMP_RT_OUTN SPKRAMP_RT_SNSN
SPKRAMP_RT_AREG
SPKRAMP_RT_DREG
1
C6567
0.1UF
10% 25V
2
X5R 0201
1
C6568
1UF
20% 16V
2
CER-X5R 0201
PLACE_NEAR=U6560.C4:10 MM
CRITICAL
1
C6566
10UF
20%
2
X5R-CERM 0603
PLACE_NEAR=U6560.C4:10 MM
CRITICAL
C6571
0.1UF
1 2
10% 25V X5R
0201
C6572
0.1UF
1 2
10% 25V X5R
0201
1
C6569
0.1UF
10% 25V
2
X5R 0201
BYPASS=U6560.A2:A5:5 MM NO_XNET_CONNECTION=1
PLACE_NEAR=U6560.C4:10 MM
CRITICAL
1
C6552
10UF
20% 25V
2
X5R-CERM 0603
1
C6553
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
R6566
0
1 2
PLACE_NEAR=U6560.A3:10 MM
06031/4W0% MF
PLACE_NEAR=J6500.5:3 MM
CRITICAL
R6567
0
1 2
PLACE_NEAR=U6560.A5:10 MM
1
C6570
1UF
20% 16V
2
CER-X5R 0201
MF1/4W0% 0603
PLACE_NEAR=J6500.6:3 MM
PLACE_NEAR=U6560.D1:3 MM PLACE_NEAR=U6560.D1:5 MM PLACE_NEAR=U6560.D5:3 MM PLACE_NEAR=U6560.D5:5 MM
PPBUS_G3H
1 2
SM
XW6560
1 2
SM
XW6561
62 63 117
122
122
PLACE_NEAR=J6500.6:5 MM
NOSTUFF
C6573
220PF
10% 25V
X7R-CERM
201
1
2
1
2
SPKRCONN_RT_OUTP
RIGHT TWEETER
SPKRCONN_RT_OUTN
PLACE_NEAR=J6500.5:5 MM
NOSTUFF
C6574
220PF
10% 25V X7R-CERM 201
BOM_COST_GROUP=AUDIO
PPBUS_G3H
62 63 117
CAPDERATE
1
C6580
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
1
C6581
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
1
C6582
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
1
C6583
33UF
20% 16V
2
TANT-POLY CASE-B3-1
PPBUS_G3H
62 63 117
CAPDERATE
1
C6584
33UF
20% 16V
2
TANT-POLY CASE-B3-1
SYNC_MASTER=ADRIEN SYNC_DATE=01/17/2019
PAGE TITLE
CAPDERATE
1
C6585
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
1
C6586
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
1
C6587
33UF
20% 16V
2
TANT-POLY CASE-B3-1
Audio Right Amplifiers
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
65 OF 200
SHEET
63 OF 135
A
8
67
35 4
2
1
Page 64
Vinafix.com
678
PP1V8_SLPS2R
80
3 245
1
D
38
38
121 77 39
122 66 50 47
PLACE_NEAR=U6650.1:5MM
C6650
0.1UF
X5R-CERM
BYPASS=U6650.1:U6650.8:8MM
SEP_CAM_DISABLE_L
IN
SEP_DMIC_DISABLE_L
IN
SEP_DISABLE_STROBE
IN
PMU_COLD_RESET_L
IN
IPD_LID_OPEN
IN
LID_CTRL_DMIC
10% 10V
0201
DMIC Secure Disable
1
2
1
R6651
2
1K
5% 1/20W MF 201
1
VDD
U6650
2
CAM_DIS*
3
DMIC_DIS*
4
DIS_STROBE
9
PMU_COLD_RST*
13
LID_RIGHT
14
LID_LEFT
6
SEL
SLG4AP41496V
(IPD)
(IPD)
(IPD)
STQFN
(PUSH-PULL)
CRITICAL
(IPD)
CAM_DIS_OUT*
(PUSH-PULL)
DMIC_DIS_OUT*
CAM_DIS_OUT
DMIC_DIS_OUT
(IPD)
RFU
12
SEP_CAM_DISABLE_DFF_L
7
SEP_DMIC_DISABLE_Q_L
10 11
5
NC NC
NC
OUT
82 38
122 64
AUD_DMIC0_DATA_CONN
PP1V8_G3S
64 118
U6640
74LVC1G08GM
SOT886-COMBO
CRITICAL
1
B
2
A
6
NC
3
5
NC
R6648
1 2
1/20W MF
NOSTUFF
0
Y
5%
0201
PLACE_NEAR=U6640.4:5MM
C6641
1
0.1UF
20% 10V
2
X7R-CERM 0402
PDM_DMIC_DATA0_RR
4
PLACE_NEAR=U6640.4:5MM
R6647
33
1 2
1/20W
MF
5%
201
PDM_DMIC_DATA0
OUT
D
39
C
APN: 518S0818
FF14A-6C-R11DL-B-3H
J6640
F-RT-SM
7
1 2 3 4 5 6
8
AUD_DMIC0_CLK_CONN AUD_DMIC0_DATA_CONN PP1V8_DMIC AUD_DMIC1_CLK_CONN
AUD_DMIC1_DATA_CONN
Digital Mic Flex Connector
IN
64 122
IN
122 64
122 47
122 47
1
C6640
1UF
20% 16V
2
CER-X5R 0201
L6640
FERR-470-OHM
1 2
0201
PP1V8_G3S
118
GND
8
122 64
PP1V8_G3S
64 118
AUD_DMIC1_DATA_CONN
U6641
74LVC1G08GM
SOT886-COMBO
CRITICAL
1
2
B
A
NC
5
NC
6
Y
3
R6650
1 2
0201MF01/20W
5%
NOSTUFF
PLACE_NEAR=U6641.4:5MM
C6642
1
0.1UF
20% 10V X7R-CERM
2
0402
4
PDM_DMIC_DATA1_RR
PLACE_NEAR=U6641.4:5MM
R6649
1 2
33
1/20W
MF 201
5%
PDM_DMIC_DATA1
OUT
39
C
B
A
61
61
61
61
61
61
61
61
61
61
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
AUD_HP_PORT_L
AUD_HP_PORT_R
AUD_HP_PORT_US_GND
AUD_HP_PORT_CH_GND
AUD_HP_SENSE_L
AUD_HP_SENSE_R
AUD_TIP_SENSE
AUD_RING_SENSE
AUD_HS_MIC_P
AUD_HS_MIC_N
CRITICAL
FL6601
120-OHM-25%-1.3A
1 2
0402
120-OHM-25%-1.3A
1 2
CRITICAL
FL6603
120-OHM-25%-1.3A
1 2
0402
120-OHM-25%-1.3A
1 2
CRITICAL
FL6606
120-OHM-25%-1.3A
1 2
0402
120-OHM-25%-1.3A
1 2
R6600
2.0K
1/20W
5% MF
201
12
R6601
CRITICAL
FL6602
120-OHM-25%-1.3A
1 2
0402
120-OHM-25%-1.3A
1 2
CRITICAL
FL6600
0402
CRITICAL
FL6605
0402
CRITICAL
FL6607
0402
2.0K
1/20W
5% MF
201
12
CRITICAL
FL6604
0402
AUD_CONN_HP_LEFT
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000
AUD_CONN_HP_RIGHT
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000
AUD_CONN_RING2
MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1000
AUD_CONN_SLEEVE
MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1000
AUD_CONN_HP_SENSE_L
AUD_CONN_HP_SENSE_R
AUD_CONN_TIP_SENSE
AUD_CONN_RING_SENSE
AUD_CONN_SLEEVE_XW
MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0920
AUD_CONN_RING2_XW
MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0920
Audio Jack Flex Connector
APN: 510S0009
J6600
51138-0274
F-ST-SM
22 21
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20
23 24
AUD_CONN_HP_LEFT
AUD_CONN_HP_RIGHT
AUD_CONN_RING2
AUD_CONN_SLEEVE
BOM_COST_GROUP=AUDIO
122 64
122 64
122 64
122 64
DESIGN: X502/DEV_MLB_U LAST CHANGE: Wed Feb 18 17:12:24 2015
SYNC_MASTER=ADRIEN SYNC_DATE=01/17/2019
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
Audio Flex Connectors
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
BRANCH
PAGE
66 OF 200
SHEET
64 OF 135
B
A
SIZE
D
8
67
35 4
2
1
Page 65
Vinafix.com
678
3 245
1
D
C
3.3V RSLOC ISOLATION KEYS/ASIC RESET
123 121 118 65
PP1V8_G3S
65 118
OUT123_EN
122 65
122 65
122 65
KBD_RIGHT_SHIFT_KEY KBD_LEFT_OPTION_KEY KBD_CONTROL_KEY
R6703
121 118 65 122 65
123
0201 1/20W MF 5%
PP3V3_G3H_T
0
1 2
R6723
122 66 65
KBD_I2C_INT_L
MF
33
1 2
1/20W
PP3V3_G3H_RSLOC
1%
201
PP3V3_G3H_T
PLACE_NEAR=U6703.10:5MM
1
R6750
0
5% 1/20W MF 0201
2
4
OE
1
IN_1
2
IN_2
3
IN_3
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
IOXP2_INT_L
65
KEYBOARD INTERFACE - IO EXPANDER
MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.6000
VOLTAGE=3.3V
C6750
1
1.0UF
20%
2
10V
X5R-CERM 0201-1
SLG4AP4815V
10
VDD
U6703
TQFN
GND EPAD
5
11
PLACE_NEAR=U6703.10:2MM
1
C6751
0.1UF
10% 10V
2
X5R-CERM 0201
OUT_1 OUT_2 OUT_3
OUT_ALL#
IN_1/IN_2/IN_3 = 100K INTERNAL PULLDOWN343S00073 OUT_1/OUT_2/OUT_3 = 12.5K INTERNAL PULL-UP
9
KBD_RIGHT_SHIFT_L
8
KBD_LEFT_OPTION_L
7
KBD_CONTROL_L
6
RSLOC_RST_L
1 2
MF
1/20W
PP1V8_G3S
R6752
33
1%
201
123 65
123 65
123 65
PMU_RSLOC_RST_L
OUT
122 66 65
122 66 65
122 66 65
KBD_I2C_SDA
KBD_I2C_SCL
PLACE_NEAR=J6800.9:10MM
PLACE_NEAR=J6800.8:10MM
DZ6710
5.5V-0.28PF
2
0201-THICKSTNCL
PLACE_NEAR=J6800.7:10MM
DZ6711
5.5V-0.28PF
2
0201-THICKSTNCL
2
MEMBRANE ZIF CONNECTOR
518S0752
FF14A-30C-R11DL-B-3H
J6701
F-RT-SM
CRITICAL
32
DZ6712
KBD_I2C_INT_L
1
1
5.5V-0.28PF
0201-THICKSTNCL
DZ6701
PESD3V3L5UF
SOT886
NC
135 122 77 67
122 65
PP3V3_G3H_RSLOC
1
3 4
2
6
KBD_CONTROL_KEY
PLACE_NEAR=J6701.30:5MM
5
KBD_LEFT_OPTION_KEY
KBD_RIGHT_SHIFT_KEY
122 65
122 65
122 65
DZ6706
PESD3V3L5UF
SOT886
122 65
KBD_DRIVE_Y4
PLACE_NEAR=J6701.6:5MM
1
6
KBD_DRIVE_Y3
122 65
1
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
KBD_CONTROL_KEY KBD_LEFT_OPTION_KEY
KBD_RIGHT_SHIFT_KEY
PP3V3_G3H_RSLOC
KBD_CAP_CATHODE
KBD_DRIVE_Y0 KBD_DRIVE_Y6 KBD_DRIVE_Y7 KBD_DRIVE_Y5 KBD_SENSE_X8
KBD_SENSE_X7
KBD_SENSE_X6 KBD_ID1
NC
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
KBD_SENSE_X10
KBD_SENSE_X11
KBD_SENSE_X4 KBD_SENSE_X12 KBD_SENSE_X9 KBD_SENSE_X3 KBD_SENSE_X5 KBD_SENSE_X2 KBD_SENSE_X1 KBD_SENSE_X0 KBD_DRIVE_Y4 KBD_DRIVE_Y3
KBD_DRIVE_Y1
KBD_DRIVE_Y2
PP1V8_G3S
65 118
25
30 29 28 27 26
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
D
C
B
PP1V8_G3S
65 118
R6720
10K
1%
1/20W
MF
201
31
5
1
2
R6721
1K
1%
1/20W
MF
201
1
2
1
C6720
1.0UF
20%
2
10V
X5R-CERM 0201-1
1
R6722
100K
1% 1/20W MF 201
2
23
21
VDD/P
1
C6721
0.1UF
10%
10V
X5R-CERM
2
0201
VDD/I2C-BUS
IOXP2_INT_L
65
122
IOXP2_ADDR
123 65
123 65
IOXP_I2C_SCL
IOXP_I2C_SDA
IOXP2_RESET_L
10%
10V
0201
1
2
C6723
0.1UF
X5R-CERM
WRITE ADDRESS = 0X42 READ ADDRESS = 0X43
22 1
INT*
18 19
20 24
ADDR SCL
SDA RESET*
U6702
PCAL6416A
HWQFN
P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7
P1_0 P1_1 P1_2
311S0665
P1_3 P1_4 P1_5 P1_6 P1_7
PAD
VSS
THRM
KBD_SENSE_X0
2
KBD_SENSE_X1
3
KBD_SENSE_X2
4
KBD_SENSE_X3
5
KBD_SENSE_X4
6
KBD_SENSE_X5
7
KBD_SENSE_X6
8
KBD_SENSE_X7
10
KBD_SENSE_X8
11
KBD_SENSE_X9
12
KBD_SENSE_X10
13
KBD_SENSE_X11
14
KBD_SENSE_X12
15
KBD_CONTROL_L
16
KBD_LEFT_OPTION_L
17
KBD_RIGHT_SHIFT_L
1
C6722
0.1UF
10%
10V
X5R-CERM
2
0201
1
R6730
10K
1% 1/20W MF 201
2
65 122
123 65
123 65
123 65
1
R6731
10K
1% 1/20W MF 201
2
65 122
1
R6732
10K
1% 1/20W MF 201
2
65 122
1
R6733
10K
1% 1/20W MF 201
2
65 122
1
R6734
10K
1% 1/20W MF 201
2
65 122
1
R6735
10K
1% 1/20W MF 201
2
65 122
1
R6736
10K
1% 1/20W MF 201
2
65 122
1
R6737
10K
1% 1/20W MF 201
2
65 122
1
R6738
10K
1% 1/20W MF 201
2
65 122
1
R6739
10K
1% 1/20W MF 201
2
65 122
1
R6740
10K
1% 1/20W MF 201
2
65 122
1
R6741
10K
1% 1/20W MF 201
2
1
R6742
10K
1% 1/20W MF 201
2
122 65
122 65
122 65
PP1V8_G3S
65 118
KBD_SENSE_X3
PLACE_NEAR=J6701.11:5MM
KBD_SENSE_X0
3 4
2
DZ6705
PESD3V3L5UF
SOT886
1
3 4
6
5
KBD_DRIVE_Y1
KBD_DRIVE_Y2
KBD_SENSE_X5
KBD_SENSE_X2
KBD_SENSE_X1
122 65
122 65
DZ6703
PESD3V3L5UF
SOT886
122 65
122 65
KBD_SENSE_X8
NC
122 65
1
3 4
2
122 65
6
5
KBD_SENSE_X7
PLACE_NEAR=J6701.20:5MM
KBD_SENSE_X6
KBD_ID1
122 65
122 65
122 65
B
A
122 66 65
122 66 65
KBD_ID_DETECT1
65
KBD_ID_DETECT2
65
KBD_CAPSLOCK_LED
122 65
PP1V8_G3S
65 118
KBD_I2C_SCL KBD_I2C_SDA
KBD_ID PIN
ANSI
ISO
JIS GND
FLOAT
HIGH PP1V8_G3S
R6710
1.3K
1/20W
R6717 R6719
201 1/20WMF 1%
R6718
1
1% MF
201
2
CONNECTION ON MEMBRANE KBD
NC
GND
1 2
1%1/20W2011KMF
1 2
1 2
1%1/16W402 MF
1
R6711
1.3K
1% 1/20W MF 201
2
MF 1%
1K
18
R6712
33
201
1/20W
1/20W
201
12
12
1%MF
33
R6713
KBD_ID1
KBD_CAP_CATHODE
R6714
10K
1%
1/20W
MF
201
123 65
122 65
122 65
9
25
2
DZ6702
132S0320 138S0847
1
2
1
R6715
100K
1% 1/20W MF 201
2
138S0706
1
C6710
1.0UF
20%
10V
2
X5R-CERM 0201-1
23
21
VDD/P
1
C6712
0.1UF
10%
10V
2
X5R-CERM 0201
1
C6713
0.1UF
10%
10V
2
X5R-CERM 0201
1
C6714
10UF
20% 10V
2
X5R-CERM 0402-7
DZ6704
122 65
KBD_CAP_CATHODE
1
PESD3V3L5UF
SOT886
2
6
5
KBD_SENSE_X11
KBD_SENSE_X4
KBD_SENSE_X12
122 65
122 65 122 65
122 65
122 65
KBD_DRIVE_Y5 KBD_DRIVE_Y7
3 4
BOM_COST_GROUP=KEYBOARD
IOXP1_INT_L
IOXP_I2C_SCL IOXP_I2C_SDA
IOXP1_RESET_L
C6711
0.1UF
X5R-CERM
10% 10V
0201
22 1
INT*
18
ADDR
19
SCL
20
123 65
1
2
24
SDA RESET*
WRITE ADDRESS = 0X40 READ ADDRESS = 0X41
VDD/I2C-BUS
U6701
PCAL6416A
HWQFN
VSS
THRM
9
25
PAD
P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7
P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7
KBD_DRIVE_Y0
2
KBD_DRIVE_Y1
3
KBD_DRIVE_Y2
4
KBD_DRIVE_Y3
5
KBD_DRIVE_Y4
6
KBD_DRIVE_Y5
7
KBD_DRIVE_Y6
8
KBD_DRIVE_Y7
10 11 12
KBD_ID_DETECT2
13 14 15 16
KBD_ID_DETECT1
17
CAPSLOCK_LED_EN
311S0665
OUT OUT OUT OUT OUT OUT OUT OUT
NC
65
NC NC NC
D6710
65
SOD962-COMBO
A K
123 122
PMEG3002ESF
122 65
122 65
122 65
122 65
122 65
122 65
122 65
122 65
KBD_CAPSLOCK_LED
3
D
122 65
122 65
122 65
KBD_SENSE_X10
KBD_SENSE_X9
PLACE_NEAR=J6701.12:5MM
1
3 4
Q6710
CAPSLOCK_LED_DRV
1
100K
1%
1/20W
MF
201
R6716
2
G
1
S
2
DMN32D2LFB4
DFN1006H4-3
SYM_VER_1
PESD3V3L5UF
SOT886
6
5
KBD_DRIVE_Y0
PLACE_NEAR=J6701.25:5MM
KBD_DRIVE_Y6
122 65
122 65
2
SYNC_MASTER=SHAN SYNC_DATE=01/17/2019
PAGE TITLE
Keyboard Support
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
67 OF 200
SHEET
65 OF 135
A
8
67
35 4
2
1
Page 66
Vinafix.com
678
TPAD SPI AWAKE , G3S POWER RAILS ISOLATION, PULL-UPS ON G3S SIDE NEED TO MATCH BOARD_ID
3 245
1
D
PP1V8_AWAKE
40
IN
47 46
47 46
47
IN
IN
OUT
SPI_TPAD_CS_L
SPI_TPAD_CLK
SPI_TPAD_MOSI
SPI_TPAD_MISO_R
1
R6887
100K
5% 1/20W MF 201
2
BYPASS=U6860::5MM
C6860
0.1UF
10% 10V
X5R-CERM
0201
R6880 pulled up to match Board ID strapping
PP1V8_G3S_TPAD_CONN
BYPASS=U6860::10MM
C6861
1
14
2
1
15
2
16
3 5
4 6
7
R6812
U6860
SN74AVC4T774
A1 DIR1
A2 DIR2
A3 DIR3
A4 DIR4
OE*
QFN
GND
0
NOSTUFF
13
VCCBVCCA
12
B1
11
B2
10
B3
9
B4
8
12
02015% 1/20W MF
1
0.1UF
10% 10V
2
X5R-CERM 0201
SPI_TPAD3V3_CLK_R
SPI_TPAD3V3_MOSI_R
1
R6821
100K
5% 1/20W MF 201
2
1
R6880
100K
5% 1/20W MF 201
2
1
R6811
100K
5% 1/20W MF 201
2
PLACE_NEAR=U6860.9:2MM
PLACE_NEAR=U6860.8:2MM
1
R6814
100K
5% 1/20W MF 201
2
R6876
20
1 2
MF5%
2011/20W
R6875
20
1 2
MF
5%
1/20W
201
SPI_TPAD_CS_CONN_L
SPI_TPAD_CLK_CONN
SPI_TPAD_MOSI_CONN
SPI_TPAD_MISO_CONN
122 66 121 80
122 66
122 66
122 66
122 66
IN
122 66
122 65
122 65
122 65
118
122 64 50 47
122 66
I2C_TPAD_CONN_SCL
KBD_I2C_INT_L
KBD_I2C_SDA
KBD_I2C_SCL
PP3V3_G3S_T IPD_LID_OPEN
ACT_GND
TPAD CONNECTOR
118
J6800
DF40PC-40DS-0.4V-51
F-ST-SM
12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940
TPAD_KBD_WAKE_L SPI_TPAD_INT_CONN_LI2C_TPAD_CONN_SDA SPI_TPAD_MOSI_CONN SPI_TPAD_CS_CONN_L SPI_TPAD_MISO_CONN SPI_TPAD_EN_CONN SPI_TPAD_CLK_CONN PP5V_G3S_TPAD_CONN
122
PP1V8_G3S_TPAD_CONN
PP1V8_G3S
VOLTAGE=5V
VOLTAGE=1.8V
122 66
ACT_GND
1
R6865
100K
5% 1/20W MF 201
2
122 47
122 66 122 66
122 66
122 66
122 66
122 66
122 66
122 66
C6800
0.1UF
SM
12
XW6801
10% 25V X5R 402
L6800
FERR-120-OHM-1.5A
1 2
0402A
1
2
PP5V_G3S
D
118
C
TPAD I2C, INT
I2C_SNS_G3S_SCL
51
I2C_SNS_G3S_SDA
51
201 5%MF
R6813
R6822
R6823
R6877
30
1 2
1/20W
R6878
30
1 2
1/20W5%MF201
0
NOSTUFF
0
NOSTUFF
0
NOSTUFF
12
MF1/20W5% 0201
PPBUS_G3H
117
12
0201MF1/20W5%
516S00177, MATE WITH 516S00054
C
12
0201MF1/20W5%
CKPLUS_WAIVE=I2C_PULLUP
I2C_TPAD_CONN_SCL
OUT
122 66
I2C_TPAD_CONN_SDA
BI
CKPLUS_WAIVE=I2C_PULLUP
122 66
B
A
PP1V8_G3S_TPAD_CONN
122 66
R6846
47
TPAD_SPI_INT_L
OUT
0
12
1/20W
0201MF5%
TPAD SPI_EN G3S POWER DOMAIN
PP1V8_G3S_TPAD_CONN
122 66
38
BYPASS=U6850::5mm
TPAD_SPI_EN
IN
C6850
0.1UF
10% 10V
X5R-CERM
0201
NOSTUFF
1
2
R6851
0
NC
NC
2
OE*
12
5% MF1/20W 0201
5
6
3
1
1
R6863
100K
5% 1/20W MF 201
2
NOSTUFF
U6850
74LVC1G125FW5
X1-DFN1010
4
SPI_TPAD_INT_CONN_L
1
R6852
100K
5% 1/20W MF 201
2
MIN_LINE_WIDTH=0.2000
122 66
1.8V TRACKPAD
U6801
MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V
Load Cap:3.2uF nom EDP:0.42mA
B
SCY99258
SPI_TPAD_EN_CONN
PP3V3_G3H_T
118
U6801_PWR_EN
C6801
1
1UF
10% 10V
2
X5R-CERM 0402
BYPASS=U6801.4::3MM
PP1V8_G3S
118
IN
122 66
R6801
0
12
(Placeholder for 450mA part symbol)
02015% MF1/20W
4
3
XDFN-COMBO-THICKSTNCL
IN EN
GND EPAD
2
OUT
5
1
BYPASS=U6801.1::3MM
C6802
1
1UF
10%
2 X5R-CERM
10V X5R-CERM 0402
SYNC_MASTER=RAYMOND
PAGE TITLE
PP1V8_G3S_TPAD_CONN
C6803
1
2.2UF
20%
6.3V
2
0201
122 66
SYNC_DATE=01/17/2019
A
8
Trackpad Support
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
BOM_COST_GROUP=KEYBOARD
67
35 4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
68 OF 200
SHEET
66 OF 135
1
SIZE
D
Page 67
Vinafix.com
J80 Battery Hotbar Flex Pads 998-03902
678
3 245
1
Flex Pad TO MLB 998-03780.
CRITICAL
OMIT_TABLE
J6950
PWR-MLB-X363
HB-SM
10
D
9 8 3
2 7
1
6
5
4
17
16
15
14
13
12
11
C6950
0.1UF
10%
25V
X5R 402
PPVBAT_G3H_CONN
1
2
C6960
1UF
10%
25V
X5R
603-1
APN:518S0818
J6951
FF14A-6C-R11DL-B-3H
121 68
1
2
F-RT-SM
7
1 2 3 4 5 6
8
NC
NC
SYS_DETECT_L
I2C_PWR_SCL I2C_PWR_SDA
TP_BMON_IOUT
NOSTUFF
1
R6950
10K
5% 1/20W MF 201
2
RCLAMP3552T
CRITICAL
U6950
SLP1006N3T
PP3V3_G3H_RTC_X
1
IN
BI
121
1
2
Q6955
DMN32D2LFB4
DFN1006H4-3
SYM_VER_1
121 51
121 51
3
D
SYS_DETECT
121
G
1
S
R6955
5%
10K
MF-LF 402
2
1/16W
118
D
DBG_BTN
2
3
SW6900
SOX-152HNT
SM
1 2
PLACE_SIDE=TOP
C
BMU POWER FLEX HOTBAR'd TO THE MLB:
1 J6950PCBA,FLEX,BMU PWR,X363632-00862 CRITICAL
SMC Reset Circuit
Right Shift & Left Option Control followed by ON OFF button press.
118
PP3V3_G3H_RTC_X
BYPASS=U6940::4MM
C6940
0.1UF
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
135 122 77 48
135 122 77 65
IN IN
PMU_ONOFF_L PMU_RSLOC_RST_L
10%
25V
X5R
0201
1
2
3 4
SLG4AP41183
BTN1 BTN2
1
VDD
U6940
STQFN
RESET
CRITICAL
GND
7
NC NC NC NC NC NC NC
10
2 5 6 8 9 11 12
CHGR_RST_IN_R CHGR_RST_IN
NC NC NC NC NC NC NC
Power Button
R6940
1K
1 2
5% 1/16W MF-LF
402
R6941
1K
1 2
5% 1/16W MF-LF
402
UPC_PMU_RESET
OUT
OUT
C
68
121 109 77 29
B
A
PPBUS_HS_3V3G3HRTC_X
117
R6900
0
0%
1/4W
MF
0603
1
2
1
2
CAPDERATE
PPVIN_G3H_P3V3G3HRTC_R
C6900
2.2UF
20%
25V
X5R-CERM 0402-1
CAPDERATE
C6901
1
2.2UF
20%
2
25V
X5R-CERM 0402-1
121 68
1
C6963
2
CAPDERATE
IN
MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.2000
VOLTAGE=13.1V
33UF
20% 16V TANT-POLY CASE-B3-1
CAPDERATE
CHGR_EN_MVR
1
C6964
33UF
20% 16V
2
TANT-POLY CASE-B3-1
C6961
1
2.2UF
20%
2
25V
X5R-CERM 0402-1
R6968
0
12
5%
1/20W
MF
0201
C6998
0.033UF
10%
50V
X7R
0402
C6962
1
2.2UF
20%
2
25V
X5R-CERM 0402-1
CHGR_EN_MVR_R
P3V3G3HRTC_SS
1
2
GND_P3V3G3HRTC_AGND
VOLTAGE=0V MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
3.3V G3H VR
U6960
TPS62180
VIN1
A1
VIN1
B1
VIN1
C1 D1
VIN2 VIN2
E1
F1
VIN2 EN VO
E4 D4
SS/TR
AGND
C4
BGA
CRITICAL
PGND
PGND
PGND
A3
B3
C3
D3
XW6960
SM
1 2
PGND
PGND
E3
PGND
F3
SW1 SW1 SW1
SW2 SW2 SW2
PG
FB
P3V3G3HRTC_PHASE1
DIDT=TRUE
A2 B2 C2
P3V3G3HRTC_PHASE2
D2
DIDT=TRUE
E2 F2
A4
P3V3G3HRTC_PGOOD
F4
P3V3G3HRTC_FB
B4
R6967
100K
5%
1/20W
MF
201
APN 152S1617
L6960
1UH-20%-4.8A-0.032OHM
1 2
CRITICAL
1210
L6961
1UH-20%-4.8A-0.032OHM
1 2
10%
16V
0201
1210
1
2
CRITICAL
C6969
220PF
CER-X7R
12
R6970
1/20W
P3V3G3HRTC_FB_R
R6976
1/20W
<Ra>
0201
R6971
365K
0.1%
1/20W
<Rb>
0201
R6972
113K
0.1%
1/20W
0201
1
10
5% MF
201
2
1
0
5% MF
TF
MF
Vout = 0.8 * (1 + <Ra>/<Rb>) = 3.384V
For tuning
2
P3V3G3HRTC_RA_R
1
2
1
2
Vout = 3.384V 6A Max Output f = 1.25 MHZ
PP3V3_G3H_RTC_REG_R
1
C6972
10UF
20%
2
10V
X5R-CERM 0402-7
BOM_COST_GROUP=PLATFORM POWER
1
C6973
10UF
20%
2
10V
X5R-CERM 0402-7
MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
1
C6976
10UF
20%
2
10V
X5R-CERM 0402-7
1
C6977
10UF
20%
2
10V
X5R-CERM 0402-7
SYNC_MASTER=
PAGE TITLE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
PP3V3_G3H_RTC_X
R6934
CRITICAL
1
C6970
150UF
20%
6.3V
2
TANT CASE-B-SM
CAPDERATE
0
0%
1/4W
MF
0603
1
2
1
R6935
0
0% 1/4W MF 0603
2
CRITICAL
1
C6971
150UF
20%
6.3V
2
TANT CASE-B-SM
CAPDERATE
VR 3.3V G3H & Battery Conn
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
CAPDERATE
CRITICAL
1
C6974
150UF
20%
6.3V
2
TANT CASE-B-SM
118
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
69 OF 200
SHEET
67 OF 135
SYNC_DATE=01/17/2019
SIZE
D
B
A
8
67
35 4
2
1
Page 68
Vinafix.com
678
3 245
1
D
C
B
CRITICAL
1
C7042
6.8UF
20% 35V-0.09OHM
2
POLY-TANT CASE-B1-2-SM
CRITICAL
1
C7043
6.8UF
20% 35V-0.09OHM
2
POLY-TANT CASE-B1-2-SM
CRITICAL
1
C7024
6.8UF
20% 35V-0.09OHM
2
POLY-TANT CASE-B1-2-SM
124 121 68 53 29
CRITICAL
1
C7025
6.8UF
20% 35V-0.09OHM
2
POLY-TANT CASE-B1-2-SM
CRITICAL
1
C7026
6.8UF
20% 35V-0.09OHM
2
POLY-TANT CASE-B1-2-SM
From USB-C Source
PPDCIN_G3H
NO STUFF
C7016
0.01UF
X5R-CERM
10% 25V
0201
1
2
CRITICAL
1
C7027
6.8UF
20% 35V-0.09OHM
2
POLY-TANT CASE-B1-2-SM
1
R7021
1.00
1% 1/20W MF-LF 0201
2
CHGR_CSI_P
C7021
1
0.047UF
10%
2
50V CER-X7R 0402
1
R7015
750K
1% 1/20W MF 201
2
CHGR_AUX_DET
1
R7016
255K
1% 1/20W MF 201
2
CRITICAL
1
C7028
6.8UF
20% 35V-0.09OHM
2
POLY-TANT CASE-B1-2-SM
(AMON)
CRITICAL
R7020
0.01
0.5%
0.5W MF
0306
123 123
PLACE_NEAR=U7000.C5:1MM
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1200
VOLTAGE=20V
PPDCIN_G3H_CHGR PPVBAT_G3H_CHGR_REG
12 34
CHGR_CSI_R_NCHGR_CSI_R_P
CRITICAL
1
C7029
6.8UF
20% 35V-0.09OHM
2
POLY-TANT CASE-B1-2-SM
1% 1/20W MF-LF
0201
1
2
R7022
1.00
CHGR_CSI_N
C7022
0.047UF
CER-X7R
10% 50V
0402
1
2
C7032
1
2.2UF
20% 35V
2
X5R-CERM 0402
1
2
3
13
D1
DFN
Q7030
FDMD8800
G1
12
CHGR_GATE_Q1
C7075
1
2.2UF
20%
2
25V X6S-CERM 0402
C7033
1
2.2UF
20% 35V
2
X5R-CERM 0402
PLACE_NEAR=Q7030.2:5mm
CHGR_PHASE1
7
8
9
10
5
6
S1/D2
G1R
11
G2
4
CHGR_GATE_Q2
CHGR_LX1
C7030
1
0.1UF
10% 25V
2 25V
X7R-CERM-1 0402
CHGR_BOOT1_RC
1
R7030
0
5% 1/16W MF-LF 402
2
CHGR_BOOT1
R7075
4.7
1 2
5%
1/20W
MF
201
CHGR_VDDPCHGR_VDDA
C7077
10UF
20% 25V
X5R-CERM
0603
A2F5D2
C7034
1
2.2UF
20% 35V
2
X5R-CERM 0402
PLACE_NEAR=Q7030.1:3mm
C7035
1
2.2UF
20% 35V
2
X5R-CERM 0402
152S00413
L7030
2.7UH-20%-21.5A-0.0135OHM
1 2
IHLP4040CZ-PIMA103T-SM-COMBO
CHGR_PHASE2
CRITICAL
6
14
S2
14
S2
CHGR_GATE_Q3
C7040
0.1UF
X7R-CERM-1
CHGR_BOOT2_RC
R7040
CHGR_BOOT2
1
2
9
10
5
G2
4
CHGR_LX2
1
10%
0402
1/16W MF-LF
0
5%
402
2
1
2
8
7
S1/D2
G1R
11
G1
12
CRITICAL
1
C7050
68UF
20%
2
16V POLY-TANT CASE-D2E-SM
1
2
3
13
D1
DFN
FDMD8800
CHGR_GATE_Q4
(PBUS)
CHGR_CSO_R_P
123
1
R7061
1.00
1% 1/20W MF-LF 0201
2
Q7040
CRITICAL
1
C7051
68UF
20%
2
16V POLY-TANT CASE-D2E-SM
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1200
VOLTAGE=12.6V
(BMON)
1
2
CRITICAL
R7060
0.005
1% 1W MF
0612-5
NO_XNET_CONNECTION=1
12 34
123
CHGR_CSO_R_N
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1200
VOLTAGE=12.6V
PPVBAT_G3H_CHGR_R
CRITICAL
C7052
68UF
20% 16V POLY-TANT CASE-D2E-SM
C7066
2.2UF
20% 25V X5R
0402-1
R7062
1.00
1% 1/20W MF-LF
0201
CRITICAL
1
C7056
68UF
20%
2
16V POLY-TANT CASE-D2E-SM
1
C7053
2.2UF
20%
2
25V X5R 0402-1
1
C7055
2.2UF
20%
2
25V X5R 0402-1
1
C7057
2.2UF
20%
2
25V X5R 0402-1
1
C7058
2.2UF
20%
2
25V X5R 0402-1
1
C7054
1000PF
10%
2
25V X7R 0201
D
CRITICAL
F7000
12AMP-32V
1 2
1206
PPBUS_G3H
To System
117 124
CRITICAL
F7001
12AMP-32V
1 2
1206
1
C7069
2.2UF
2
0402-1
20% 25V X5R
1
2
C7067
0.1UF
10% 25V X5R
0201
1
2
C7068
0.01UF
10% 25V
X5R-CERM
0201
1
2
C
CRITICAL
Q7065
SI7137DP
SO-8
SYM-VER-2
S
3
D
2 1
G
1
C7064
1000PF
2
1 2
10% 25V X7R
0201
4
SYM_VER_1
5
3
D
S
2
To/From Battery
PPVBAT_G3H_CONN
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200
VOLTAGE=12.6V
PLACE_NEAR=Q7065.5:2MM
1
C7060
0.1UF
10%
2
25V X5R 0201
CRITICAL
Q7070
DMN32D2LFB4
DFN1006H4-3
G
SAVE_BAT_G
1
R7071
200K
1 2
121 67
PPDCIN_G3H
5%MF2011/20W
B
124
53 29 121 68
A
51
51
67
3.3V = Tuba
1.8V = Suona
80
PP1V8_SLPS2R
BI
I2C_PWR_SDA I2C_PWR_SCL
IN
CHGR_RST_IN
IN
121 68
PPVBAT_G3H_CHGR_REG
C7080
1.0UF
20% 10V
X5R-CERM
0201-1
1
2
C7081
2.2UF
20% 35V
X5R-CERM
0402
PLACE_NEAR=U7000.A5:2MM
VDDA
WCSP
AGND E3
VDDP
PGND E2
GATE_Q1
BOOT1
LX1 GATE_Q2 GATE_Q3
LX2
BOOT2
GATE_Q4
PBUS CSOP CSON
BGATE
VBAT
EN_VR1
SMC_RST*
IRQ* CBC_ON EN_MVR
AUX_OK
AMON BMONNC2
H1 F1 G1 E1 D1 B1 C1 A1
CHGR_PBUS_SENSE
A3
CHGR_CSO_P
A4 B4
CHGR_CSO_N CHGR_BGATE
B3 C3
CHGR_VBAT TP_CHGR_EN_VR1
F2 H4
TP_CHGR_SMC_RST_L
H3
CHGR_INT_L
H2G4
CHGR_CBC_ON
F4
CHGR_EN_MVR NC_CHGR_AUX_OK
F3 D4
CHGR_AMON
C4
CHGR_BMON
OUT OUT OUT OUT OUT OUT
77
80
53
53
2
PLACE_NEAR=Q7040.1:1MM
XW7000
SM
1
PLACE_NEAR=U7000.A4:1MM
C7020
0.47UF
12
20%
4V
CERM-X5R-1
201
77 47
10% 50V
0402
1
2
121 67
C7061
0.047UF
CER-X7R
1
C7062
0.047UF
10%
2
50V CER-X7R 0402
TP-P5
A
TP7000
1
C7063
4700PF
10%
2
25V CER-X5R 0201
1
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
1
R7063
1K
MF 1%
201
1/20W
2
PBUS Supply & Battery Charger
SAVE_BAT_S
1
R7070
24K
5% 1/20W MF 201
2
Apple Inc.
K
A
CRITICAL
D7070
GDZ5V6LP3-55
DFN0201-THICKSTNCL
DRAWING NUMBER
051-04492
REVISION
A
SIZE
D
C7023
0.47UF
12
P_IN
20%
4V
CERM-X5R-1
201
CHGR_COMP
NOSTUFF
1
2
C7070
0.12UF
10% 10V X5R 0402
1
2
1
C7071
0.12UF
10%
2
10V X5R 0402
NOSTUFF
1
R7074
100K
5% 1/20W MF 201
2
B5
C5
CSIN
D5
CSIP
PBUS_PWR
A5
D3
AUX_DET
VDDIO1P8
G5
SDA
H5
SCL
SMC_RST_IN
G2
HPWR_EN*
G3
COMP
E5
CELL
NC0
B2
NC1
C2
E4
U7000
ISL9240
OMIT_TABLE
2.15.0
BRANCH
PAGE
70 OF 200
SHEET
68 OF 135
BOM_COST_GROUP=PLATFORM POWER
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
67
35 4
2
1
Page 69
Vinafix.com
678
3 245
1
D
C
B
A
9 8
8
72 69
72 69
72 69
71 69
9 8
IN
IN
8
CPU_VCCGTSENSE_N
CPUGT_ISUMP
CPUGT_ISUMN
CPUGT_ISEN1
CPUGT_ISEN2
R7160
88.7K
1 2
1%
1/20W
MF
201
IN
IN
CPUSA_ISUMP
CPUSA_ISUMN
CPU_VCCSASENSE_P
CPU_VCCSASENSE_N
72
IN
IN
IN
IN
71
IN
IN
C7154
0.01UF
X7R-CERM
C7160
150PF
C7181
220PF
10% 25V
X7R-CERM
201
C7182
0.01UF
X7R-CERM
0201
R7190
100K
1%
1/20W
MF
201
C7151
1
10%
2
10V
0201
IMON_B_CPUGT
12
5%
50V
CER-C0G
0201
1
2
1
10%
2
10V
12
C7190
150PF
5%
50V
CER-C0G
0201
C7153
0.01UF
R7181
1K
1 2
1%
1/20W
MF
201
12
NO_XNET_CONNECTION=1
NO_XNET_CONNECTION=1
10% 16V X7R
0201
1
2
499
1%
1/20W
MF
201
1
2
1
2
69
12
C7141
330PF
220PF
10% 25V
X7R-CERM
201
10% 10V
X7R-CERM
0201
R7180
SA_ISUMN_R
IMON_C_CPUSA
NO_XNET_CONNECTION=1
NO_XNET_CONNECTION=1
C7171
330PF
10% 16V X7R
0201
R7142
0
1 2
5%
1/20W
MF
0201
1
C7142
2
C7152
1
0.01UF
10%
2
10V X7R-CERM 0201
R7172
1 2
1/20W
0201
1
2
FB_GT_R
XW7140
SM
1 2
330PF
10% 16V X7R 0201
R7150
332
1%
1/20W
MF
201
R7151
1K
1 2
1%
GT_ISUMN_R
1/20W
MF
201
C7161
6800PF
10% 10V
X7R-CERM
0201
C7180
3300PF
1 2
10% 10V
X7R-CERM
0201
69
FB_SA_R
0
5% MF
XW7170
1 2
1
C7172
330PF
10%
2
16V X7R 0201
R7143
1.8K
1 2
1%
1/20W
MF
C7144
3300PF
FB_B_GT_R
12
10% 10V
X7R-CERM
0201
201
RTN_B_CPUGT
12
CPU VCC GT + GTx Merged
C7162
68PF
5% 25V C0G
12
0201
COMP_B_CPUGT_L
CPUSA_ISUMN_R
C7191
6800PF
X7R-CERM
0201
R7173
2.49K
C7174
1000PF
FB_C_SA_R
12
10% 25V X5R
0201
SM
RTN_C_CPUSA
R7144
1K
1%
1/20W
MF
201
69
CPUGT_ISUMN_R
C7150
3300PF
1 2
10% 10V
X7R-CERM
0201
12
12
10% 10V
1%
1/20W
MF
201
COMP_B_CPUGT
R7161
4.64K
1%
1/20W
MF
201
69
C7192
150PF
CER-C0G
COMP_C_CPUSA_L
12
R7174
1/20W
FB_B_CPUGT
R7145
12
CPU VCC SA
12
5%
50V
0201
1K
1% MF
201
69
1 2
PPBUS_HS_CPU
117
12
12
560
1%
1/20W
MF
201
R7191
FB_B_CPUGT_RC
1
2
72 69
72 69
72 69
69
71 69
2.7K
1/20W
1% MF
201
12
FB_C_CPUSA
R7175
560
1 2
1%
1/20W
MF
201
69
C7143
1.2NF
+/-10% 10V CERM 0201-1
R7101
1 2
69
72
OUT
72
OUT
72
OUT
IN
69 69
IN IN
69
69
69
69
69
71
OUT
71
OUT
IN
69
69
69
69
69
69
69
69
69
69
COMP_C_CPUSA
FB_C_CPUSA_RC
1
C7173
680PF
10%
2
25V X7R-CERM 0201
CPUGT_FCCM CPUGT_PWM1
CPUGT_PWM2
CPUGT_ISUMP CPUGT_ISUMN_R
CPUGT_ISEN1 CPUGT_ISEN2
COMP_B_CPUGT FB_B_CPUGT RTN_B_CPUGT IMON_B_CPUGT NTC_B_CPUGT
CPUSA_FCCM CPUSA_PWM CPUSA_ISUMP
CPUSA_ISUMN_R COMP_C_CPUSA FB_C_CPUSA RTN_C_CPUSA IMON_C_CPUSA PROG1_CPUCOREVR
PROG2_CPUCOREVR PROG3_CPUCOREVR PROG4_CPUCOREVR PROG5_CPUCOREVR
10
5%
1/20W
MF
201
1
2
69
1
R7111
110K
1% 1/20W MF 201
2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=12.6V
C7101
0.22UF
10% 25V X7R 0402
FCCM_B PWM1_B
PWM2_B
ISUMP_B ISUMN_B
ISEN1_B ISEN2_B
COMP_B FB_B RTN_B
IMON_B
NTC_B
FCCM_C
34
PWM_C
32
ISUMP_C
33
ISUMN_C
29
COMP_C FB_C
30
RTN_C
31 45
IMON_C
28
PROG1
40
PROG2
39
PROG3
38
PROG4
37
PROG5
36
PROG1_CPUCOREVR
1
R7112
215K
1% 1/20W MF 201
2
1
2
42
41 VIN
VCC
U7100
ISL95828HRTZ
LLP
OMIT_TABLE
THRM_PAD 49
69
PROG2_CPUCOREVR
PROG3_CPUCOREVR
R7113
1.87K
1% 1/20W MF 201
1
R7114
182K
1% 1/20W MF 201
2
PP5V_COREVR_VCCPPVIN_S0_CPUVR_VIN
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=5V
FCCM_A
PWM1_A PWM2_A PWM3_A
ISUMP_A
ISUMN_A
ISEN1_A ISEN2_A ISEN3_A
COMP_A
FB_A
RTN_A
IMON_A
NTC_A
VR_HOT*
VR_READY
VR_ENABLE
SDA
ALERT*
SCLK
PSYS
69
2411 2512
2613 27
197 208
219 2210 23
164 175 186 142 153
46 4735 48
43 44
1
CPUCORE_FCCM CPUCORE_PWM1
CPUCORE_PWM2 CPUCORE_PWM3
CPUCORE_ISUMP CPUCORE_ISUMN_R
CPUCORE_ISEN1 CPUCORE_ISEN2 CPUCORE_ISEN3
COMP_A_CPUCORE FB_A_CPUCORE RTN_A_CPUCORE IMON_A_CPUCORE NTC_A_CPUCORE
CPUCORE_PROCHOT_R_L CPUVR_PGOOD CPU_VR_EN_R
CPUCORE_VIDSOUT_R CPUCORE_VIDALERT_R_L CPUCORE_VIDSCLK_R
69
PROG4_CPUCOREVR
PROG5_CPUCOREVR
1
R7115
121K
1% 1/20W MF 201
2
R7100
1
1 2
5%
1/20W
MF
201
1
C7100
1UF
10%
2
10V CER-X6S 0402
CPUCORE_PSYS
C7108
1
4700PF
10%
2
10V X7R 201
69
PP5V_G3S
OUT
OUT OUT OUT
69
69
69
69
69
R7106
49.9
1 2
1/20W
PP5V_G3S
NOSTUFF
1
R7107
12.1K
1% 1/20W MF 201
2
1
R7108
12.1K
1% 1/20W MF 201
2
69
IN
IN IN IN
1% MF
201
70
70
70
70
70 69
70 69
70 69
70 69
OUT
CPU VCC Core
PP1V8_S5
1
R7163
10K
5% 1/20W MF 201
2
R7102
100
1 2
80
R7103
0
1 2
5%
1/20W
MF
0201
1/20W
SVID_PU:CORE
1
R7110
45.3
1% 1/20W MF 201
2
R7105
0
1 2
5%
1/20W
MF
0201
NTC_B_CPUGT
69
69 69
69
69 70 71 118
5% MF
201
R7104
10
1 2
5%
1/20W
MF
201
69 70 71 118
FB_A_CPUCORECPU_VCCGTSENSE_P
FB_A_CPUCORE_RC
C7148
390PF
5% 25V C0G
0201
1 2
1
2
R7149
560
1%
1/20W
MF
201
R7148
1K
1 2
1%
1/20W
MF
201
RTN_A_CPUCORE
69
R7154
CPUCORE_ISUMN_R
69
74 78 80
SMC_PROCHOT_L
CPU_VCCST_PWRGD
PP1V05_S3
SVID_PU:CORE
1
R7109
100
1% 1/20W MF 201
2
CPU_VIDSOUT
CPU_VIDALERT_L
CPU_VIDSCLK
C7155
3300PF
1 2
10% 10V
X7R-CERM
0201
OUT
IN
CORE_ISUMN_R
BI
IN
IN
1 2
47 46 39
80
8
8
8
R7121
17.8K
1 2
1/20W
1%
201
MF
NTC_B_CPUGT_R
R7120
17.8K
1 2
1/20W
1%
201
MF
NTC_A_CPUCORE_RNTC_A_CPUCORE
1
R7123
220KOHM-3%
0201
2
NTC_A_CPUCORE_XW
2
XW7123
BOM_COST_GROUP=CPU & CHIPSET
SM
1
442
1%
1/20W
MF
201
117
R7147
4.75K
1 2
1%
1/20W
MF
201
FB_CORE_R
FB_A_CORE_R
R7155
1K
1 2
1%
1/20W
MF
201
COMP_A_CPUCORE
69
1
R7124
220KOHM-3%
0201
2
NTC_B_CPUCORE_XW
2
XW7124
SM
1
R7146
0
C7147
470PF
1 2
10% 16V
X5R-X7R-CERM
0201
XW7141
SM
12
1/20W
0201
NO_XNET_CONNECTION=1
C7146
330PF
10% 16V X7R
0201
1
C7156
220PF
10%
2
25V X7R-CERM 201
1
C7157
0.01UF
10%
2
10V X7R-CERM 0201
1
C7149
0.01UF
10%
2
10V X7R-CERM 0201
IMON_A_CPUCORE
69
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
12
5% MF
1
2
R7193
2.87K
1 2
NO_XNET_CONNECTION=1
C7145
1
330PF
10%
2
16V X7R 0201
1
C7158
0.01UF
10%
2
10V X7R-CERM 0201
1%
1/20W
MF
201
COMP_A_CPUCORE_L
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPUCORE_ISUMP
CPUCORE_ISUMN
CPUCORE_ISEN1 CPUCORE_ISEN2 CPUCORE_ISEN3
1
C7159
0.01UF
10%
2
10V X7R-CERM 0201
C7193
56PF
1 2
5%
25V
NP0-C0G
0201
R7194
102K
1 2
C7195
150PF
1 2
5%
50V
CER-C0G
0201
1/20W
C7194
6800PF
1 2
10% 10V
X7R-CERM
0201
1% MF
201
8
IN
9 8
IN
70 69
IN
70
IN
70 69
IN
70 69
IN
70 69
IN
IMVP IC
SIZE
D
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
BRANCH
PAGE
71 OF 200
SHEET
69 OF 135
D
C
B
A
8
67
35 4
2
1
Page 70
Vinafix.com
678
3 245
1
D
PPBUS_HS_CPU
70 117
PP5V_G3S
69 70 71 118
70 117
PPBUS_HS_CPU
R7216
1
1 2
5% 1/16W MF-LF
402
PVCCCORE_PH1_AGND
70
70 69
69
IN
IN
CPUCORE_FCCM
CPUCORE_PWM1
CPU VCC Phase 1
PVCCCORE_PH1_VCC
20% 25V
0402
1
2
PVCCCORE_PH1_AGND
70
C7217
2.2UF
X6S-CERM
NC NC
29
3
VCC
PVCC
353S00519 & 353S00831
U7210
VIN
8 9
2 1
31
VIN FCCM PWM
NC NC
FDMF5808A
PQFN-COMBO-THICKSTNCL
CRITICAL
AGND
AGND 4
32
PLACE_NEAR=U7210.32:2MM
PGND
PGND 12
28
XW7210
SM
OMIT_TABLE
SW SW
GL0 GL1
GH
5 7 16
24 27
3330 6
BOOT
PHASE
12
NC NC
NC
1
C7216
2.2UF
20% 25V
2
X6S-CERM 0402
CRITICAL
1
C7251
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
CPUCORE_SW1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE
CPUCORE_BOOT1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
CPUCORE_BP1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
CAPDERATE
CPUCORE_PHASE1
CRITICAL
1
C7252
33UF
20% 16V
2
TANT-POLY CASE-B3-1
R7219
0
5% 1/16W MF-LF
402
C7219
0.22UF
10% 25V X7R
0402
CRITICAL
1
C7253
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CRITICAL
1
C7254
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
CAPDERATE
L7211
0.15UH-20%-50A-0.0008OHM
1 2
PILE083T
CRITICAL
1
R7218
2.2
5% 1/10W MF-LF 603
1
2
1
2
2
CPUCORE_SW1_SNUB
DIDT=TRUE
1
2
NOSTUFF
C7218
0.001UF
10% 50V X7R-CERM 0402
NOSTUFF
CRITICAL
1
C7255
33UF
2
CAPDERATE
PPVCC_CPU_PH1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V
NO_XNET_CONNECTION
20% 16V TANT-POLY CASE-B3-1
CAPDERATE
R7212
1/20W
CRITICAL
1
2
1
1K
1%
MF
201
2
C7256
33UF
20% 16V TANT-POLY CASE-B3-1
R7210
0.0005
1% 1W MF
0612-2
1 2 3 4
1
R7213
200K
1% 1/20W MF 201
2
CRITICAL
1
C7257
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
CRITICAL
CPUCORE_ISNS1_P CPUCORE_ISNS1_N
1
R7211
2.2
NO_XNET_CONNECTION
1% 1/20W MF 201
2
NO_XNET_CONNECTION
7x 33uF B3
1
C7258
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
1
C7259
33UF
2
CAPDERATE
OUT OUT
CPUCORE_ISUMN
CPUCORE_ISEN1
CPUCORE_ISUMP
20% 16V TANT-POLY CASE-B3-1
54
70 54
6X 2.2UF 0402
THESE TWO CAPS ARE FOR EMC
1
C7290
0.001UF
10%
2
50V X7R-CERM 0402
OUT
69
OUT
OUT
70 69
70 69
1
C7291
2
R7214
200K
1/20W
0.001UF
10% 50V X7R-CERM 0402
12
1%
MF
201
R7215
200K
1%
1/20W
MF
201
CRITICAL
1
C7295
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
CPUCORE_ISNS2_N
NO_XNET_CONNECTION
CPUCORE_ISNS3_N
12
NO_XNET_CONNECTION
CRITICAL
1
C7260
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
70 54
CRITICAL
1
C7261
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
70 54
CAPDERATE
CRITICAL
1
C7262
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CRITICAL
1
C7263
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CAPDERATE
CRITICAL
1
2
CAPDERATE
PPVCC_S0_CPU
Vout = 0.55 - 1.5V ICCMAX = 128A F = 750kHz
C7264
33UF
20% 16V TANT-POLY CASE-B3-1
117
CAPDERATE
CRITICAL
1
C7265
33UF
20% 16V
2
TANT-POLY CASE-B3-1
D
C
B
69 70 71
PP5V_G3S
118
PVCCCORE_PH2_AGND
70
CPU VCC Phase 2
70 69
69
R7226
1
1 2
5% 1/16W MF-LF
402
IN
IN
CPUCORE_FCCM
CPUCORE_PWM2
PVCCCORE_PH2_VCC
20% 25V
0402
1
2
PVCCCORE_PH2_AGND
70
C7227
2.2UF
X6S-CERM
NC NC
29
3
VCC
PVCC
353S00519 & 353S00831
U7220
8 9
2 1
31
VIN VIN
FCCM PWM
NC NC
FDMF5808A
PQFN-COMBO-THICKSTNCL
CRITICAL
AGND
AGND 4
32
PGND
PGND 12
28
XW7220
SM
OMIT_TABLE
SW SW
GL0 GL1
GH
5 7 16
24 27
3330 6
BOOT
PHASE
12
NC NC
NC
1
C7226
2.2UF
20% 25V
2
X6S-CERM 0402
CPUCORE_SW2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE
CPUCORE_BOOT2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
CPUCORE_BP2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
CPUCORE_PHASE2
R7229
1/16W MF-LF
C7229
0.22UF
10% 25V X7R
0402
5%
402
L7221
0.15UH-20%-50A-0.0008OHM
1 2
PILE083T
CRITICAL
1
R7228
2.2
5% 1/10W MF-LF
1
0
2
1
2
603
2
CPUCORE_SW2_SNUB
DIDT=TRUE
1
2
NOSTUFF
C7228
0.001UF
10% 50V X7R-CERM 0402
NOSTUFF
PPVCC_CPU_PH2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V
NO_XNET_CONNECTION
R7222
1K
1%
1/20W
MF
201
R7220
0.0005
1 2 3 4
1
2
C7271
2.2UF
20% 25V
X6S-CERM
0402
1% 1W MF
0612-2
1
2
1
R7223
200K
1% 1/20W MF 201
2
1
2
C7272
X6S-CERM
CRITICAL
CPUCORE_ISNS2_P CPUCORE_ISNS2_N
R7221
2.2
1%
NO_XNET_CONNECTION
1/20W MF 201
NO_XNET_CONNECTION
2.2UF
20% 25V
0402
1
2
C7273
X6S-CERM
CPUCORE_ISUMN
CPUCORE_ISEN2
CPUCORE_ISUMP
2.2UF
20% 25V
0402
1
2
OUT OUT
C7274
2.2UF
X6S-CERM
54
70 54
20% 25V
0402
OUT
OUT
OUT
THESE TWO CAPS ARE FOR EMC
1
1
C7275
2.2UF
2
70 69
69
70 69
X6S-CERM
0402
20% 25V
R7224
1
2
200K
1%
1/20W
MF
201
C7299
2.2UF
X6S-CERM
12
R7225
200K
1%
1/20W
MF
201
1
20% 25V
2
0402
CPUCORE_ISNS1_N
NO_XNET_CONNECTION
CPUCORE_ISNS3_N
12
NO_XNET_CONNECTION
C7292
0.001UF
10%
2
50V X7R-CERM 0402
70 54
1
C7293
0.001UF
10%
2
50V X7R-CERM 0402
70 54
C
B
A
PPBUS_HS_CPU
70 117
69 70 71
PP5V_G3S
118
PVCCCORE_PH3_AGND
70
CPU VCC Phase 3
70 69
69
R7236
1
1 2
5% 1/16W MF-LF
402
IN
IN
CPUCORE_FCCM
CPUCORE_PWM3
PVCCCORE_PH3_VCC
C7237
2.2UF
X6S-CERM
20% 25V
0402
1
2
PVCCCORE_PH3_AGND
70
NC NC
PLACE_NEAR=U7220.32:2MM
29
3
VCC
PVCC
353S00519 & 353S00831
U7230
VIN
8 9
2 1
31
VIN FCCM PWM
NC NC
FDMF5808A
PQFN-COMBO-THICKSTNCL
CRITICAL
AGND
AGND 4
32
PLACE_NEAR=U7230.32:2MM
PGND
PGND 12
28
XW7230
SM
OMIT_TABLE
SW SW
GL0 GL1
GH
5 7 16
24 27
3330 6
BOOT
PHASE
12
NC NC
NC
1
C7236
2.2UF
20%
2
25V X6S-CERM 0402
CPUCORE_SW3
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE
CPUCORE_BOOT3
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
CPUCORE_BP3
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
CPUCORE_PHASE3
R7239
1/16W MF-LF
C7239
0.22UF
10% 25V X7R
0402
5%
402
R7230
0.0005
L7231
0.15UH-20%-50A-0.0008OHM
1 2
PILE083T
CRITICAL
1
R7238
2.2
5% 1/10W MF-LF 603
1
0
2
1
2
2
CPUCORE_SW3_SNUB
DIDT=TRUE
1
2
NOSTUFF
C7238
0.001UF
10% 50V X7R-CERM 0402
NOSTUFF
PPVCC_CPU_PH3
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.15V
NO_XNET_CONNECTION
CRITICAL
R7232
1K
1%
1/20W
MF
201
1
2
1% 1W MF
0612-2
1
2
12 34
1
R7231
2.2
1% 1/20W MF 201
2
R7233
200K
1% 1/20W MF 201
CPUCORE_ISNS3_P CPUCORE_ISNS3_N
NO_XNET_CONNECTION
NO_XNET_CONNECTION
OUT OUT
CPUCORE_ISUMN
CPUCORE_ISEN3
CPUCORE_ISUMP
54
70 54
U7210,U7220,U7230
IMVP VCC Block
Apple Inc.
OUT
OUT
OUT
69
IC,SIC635,DRMOS,IMVP-8,40A,PQFN31,5X5
70 69
R7234
200K
1%
1/20W
MF
201
R7235
70 69
CPUCORE_ISNS1_N
12
NO_XNET_CONNECTION
200K
1/20W
1%
MF
201
12
CPUCORE_ISNS2_N
NO_XNET_CONNECTION
70 54
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
70 54
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL353S00519 3
A
DRAWING NUMBER
051-04492
REVISION
SIZE
D
2.15.0
BRANCH
PAGE
72 OF 200
SHEET
70 OF 135
BOM_COST_GROUP=CPU & CHIPSET
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
67
35 4
2
1
Page 71
Vinafix.com
678
3 245
1
D
PPBUS_HS_CPU
117
69 70 118
PP5V_G3S
1 2
PVCCCSA_AGND
71
69
IN
69
IN
CPU VCCSA
R7375
1
5% 1/16W MF-LF
402
PVCCCSA_VCIN
CPUSA_FCCM
CPUSA_PWM
20% 25V
0402
1
2
NC
C7377
2.2UF
X6S-CERM
OMIT_TABLE
353S00525 & 353S4471
2
11
VCIN
VDRV
U7370
SIC535CD
6
VIN
1
ZCD_EN*
12
PWM
3
NC
XW7370
PLACE_NEAR=U7370.10:2MM
MLP4535
CRITICAL
PGND
PGND
7
10
SM
12
PVCCCSA_AGND
71
CGND
13
BOOT
PHASE
VSWH
GL GL
5
8
9 14
CAPDERATE
CAPDERATE
CAPDERATE
CAPDERATE
3X 33UF B3 2X 2.2UF 0402
CRITICAL
1
C7380
33UF
20%
2
16V TANT-POLY
1
C7376
2.2UF
20% 25V
2
X6S-CERM 0402
CPUVR_SWSA
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
4
NC NC
CPUSA_BOOTSA
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
CPUSA_PHASESA
CPUSA_BPSA
DIDT=TRUE
C7379
0.22UF
R7379
0
5% 1/16W MF-LF
402
10% 25V X7R
0402
1
2
1
2
152S00689/152S00707
CRITICAL
L7330
0.47UH-20%-17.5A-0.0047OHM
1 2
PIMA052D-SM
1
R7378
2.2
5% 1/10W MF-LF 603
NOSTUFF
2
CPUSA_SW_SNUB
DIDT=TRUE
C7378
1
0.001UF
10% 50V
2
X7R-CERM 0402
NOSTUFF
PPVCCSA_CPU_R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.15VSWITCH_NODE=TRUE
CRITICAL
R7370
0.002
1%
1/2W
MF
0306
1 2 3 4
R7372
1 2
CASE-B3-1
CPUSA_ISNS_P CPUSA_ISNS_N
NO_XNET_CONNECTION=1
0
5%
1/20W
MF
0201
R7374
1 2
1K
1%
1/20W
MF
201
CRITICAL
1
C7381
33UF
20%
2
16V TANT-POLY CASE-B3-1
CPUSA_ISUMN
CPUSA_ISUMP
NO_XNET_CONNECTION=1
CRITICAL
1
C7382
33UF
20%
2
16V TANT-POLY CASE-B3-1
OUT OUT
1
C7383
33UF
20%
2
16V TANT-POLY CASE-B3-1
C7395
2.2UF
20% 25V
X6S-CERM
0402
1
2
C7396
2.2UF
20% 25V
X6S-CERM
0402
1
2
D
PPVCCSA_S0_CPU
123 56
123 56
69
OUT
69
OUT
Vout = 0.55 - 1.15V ICCMAX = 11.1A F = 750kHz
117
C
IC,SIC635,DRMOS,IMVP-8,40A,PQFN31,5X5
U7370
C
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL353S00525 1
B
B
A
8
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
IMVP SA Block
SIZE
D
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
73 OF 200
SHEET
71 OF 135
1
Page 72
Vinafix.com
678
3 245
1
D
CPU VCCGT Phase 1
72 117
PPBUS_HS_CPU
72 118
PP5V_G3S
R7416
1 2
PVCCCGT_PH1_AGND
72
72 69
69
1
5% 1/16W MF-LF
402
CAPDERATE
CRITICAL
1
C7400
33UF
20%
2
TANT-POLY CASE-B3-1
PVCCCGT_PH1_VCC
29
3
C7417
2.2UF
X6S-CERM
IN
IN
CPUGT_FCCM
CPUGT_PWM1
20% 25V
0402
1
VCC
2
PVCC
U7410
SW SW
GL0 GL1
GH
5 7 16
24 27
3330
6
NC NC
NC
8 9
2 1
NC
31
NC
PVCCCGT_PH1_AGND
72
VIN VIN
FCCM PWM
NC NC
FDMF5808A
PQFN
CRITICAL
AGND
AGND
4
32
PGND
12
XW7410
SM
BOOT
PHASE
PGND
28
12
C7416
1
2.2UF
20% 25V
2
X6S-CERM 0402
CPUGT_BOOT1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
CPUGT_PHASE1
CPUGT_SW1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE
CPUGT_BP1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
C7419
0.22UF
CAPDERATE
CRITICAL
1
C7401
33UF
20% 16V
216V
TANT-POLY CASE-B3-1
1/16W MF-LF
10% 25V X7R
0402
5%
402
1
0
2
1
2
R7419
0.22UH-20%-22A-0.0042OHM
CAPDERATE
CRITICAL
1
C7402
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CRITICAL
L7410
1 2
IHLP2020BD-SM
152S00412
1
R7418
2.2
5% 1/10W MF-LF 603
2
CPUGT_SW1_SNUB
DIDT=TRUE
1
2
NOSTUFF
C7418
0.001UF
10% 50V X7R-CERM 0402
NOSTUFF
CAPDERATE
CRITICAL
1
C7403
33UF
20% 16V
2
TANT-POLY CASE-B3-1
PPVCCGT_CPU_PH1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V
NO_XNET_CONNECTION
CRITICAL
1
C7404
33UF
2
CRITICAL
CAPDERATE
20% 16V TANT-POLY CASE-B3-1
R7412
1K
1/20W
201
1
1%
MF
2
PLACE_NEAR=U7410.4:2MM
CAPDERATE
CRITICAL
1
C7405
33UF
20% 16V
2
TANT-POLY CASE-B3-1
R7410
0.001
1%
1/2W
MF
0306
1 2 3 4
1
2
1
R7413
200K
1% 1/20W MF 201
2
CRITICAL
1
C7406
33UF
20% 16V
2
TANT-POLY CASE-B3-1
CPUGT_ISNS1_P CPUGT_ISNS1_N
R7411
2.2
1% 1/20W MF 201
NO_XNET_CONNECTION
NO_XNET_CONNECTION
CAPDERATE
CPUGT_ISUMN
CPUGT_ISEN1
CPUGT_ISUMP
4x 2.2uF 0402
7X 33UF B3
56
OUT OUT
72 56
OUT
OUT
OUT
69
PPVCCGT_S0_CPU
117
D
Vout = 0.55 - 1.5V ICCMAX = 32A F = 750kHz
72 69
R7414
200K
1%
1/20W
MF
201
72 69
CPUGT_ISNS2_N
12
NO_XNET_CONNECTION
72 56
C
B
CPU VCCGT Phase 2
PPBUS_HS_CPU
72 117
R7426
72 118
PP5V_G3S
PVCCCGT_PH2_AGND
72
1 2
1
5% 1/16W MF-LF
402
PVCCCGT_PH2_VCC
C7427
2.2UF
X6S-CERM
72 69
69
IN
IN
1
20% 25V
2
0402
CPUGT_FCCM
CPUGT_PWM2
8 9
2 1
NC
31
NC
PVCCCGT_PH2_AGND
72
72 118
PP5V_G3S
VIN VIN
FCCM PWM
NC NC
29
3
VCC
PVCC
U7420
FDMF5808A
PQFN
CRITICAL
AGND
AGND
4
32
PGND
12
28
PHASE
PGND
BOOT
SW SW
GL0 GL1
GH
5 7 16
24 27
3330
6
1
2
NC NC
NC
C7426
2.2UF
20% 25V X6S-CERM 0402
CPUGT_BOOT2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
CPUGT_PHASE2
CPUGT_SW2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE
CPUGT_BP2
MIN_LINE_WIDTH=0.2000
DIDT=TRUEMIN_NECK_WIDTH=0.1200
R7429
1/16W MF-LF
C7429
0.22UF
10% 25V X7R
0402
5%
402
C7420
2.2UF
20% 25V
X6S-CERM
0402
CRITICAL
L7420
0.22UH-20%-22A-0.0042OHM
1 2
IHLP2020BD-SM
152S00412
1
R7428
2.2
5% 1/10W MF-LF 603
1
0
2
1
2
2
CPUGT_SW2_SNUB
DIDT=TRUE
1
2
NOSTUFF
C7428
0.001UF
10% 50V X7R-CERM 0402
NOSTUFF
1
C7421
2.2UF
2
PPVCCGT_CPU_PH2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.5V
X6S-CERM
NO_XNET_CONNECTION
20% 25V
0402
1
2
R7422
1K
1%
1/20W
MF
201
C7422
2.2UF
X6S-CERM
0402
R7420
0.001
1
2
20% 25V
1%
1/2W
MF
0306
1
2
12 34
1
R7421
2.2
1% 1/20W MF 201
2
1
R7423
200K
1% 1/20W MF 201
2
C7423
2.2UF
X6S-CERM
0402
20% 25V
1
2
CRITICAL
CPUGT_ISNS2_P CPUGT_ISNS2_N
NO_XNET_CONNECTION
NO_XNET_CONNECTION
CPUGT_ISUMN
CPUGT_ISEN2
CPUGT_ISUMP
OUT OUT
56
C
72 56
69
72 69
R7424
200K
1%
1/20W
MF
201
72 69
CPUGT_ISNS1_N
12
NO_XNET_CONNECTION
72 56
B
OUT
OUT
OUT
XW7420
SM
12
PLACE_NEAR=U7420.4:2MM
A
8
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
IMVP GT Block
SIZE
D
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
74 OF 200
SHEET
72 OF 135
1
Page 73
Vinafix.com
678
3 245
1
D
C
B
PPBUS_HS_OTH5V
117
PP5V_G3S
73 118
VOUT = 5V
1.58A MAX OUTPUT F = 500 KHZ
C7606
2.2UF
20% 25V
X6S-CERM
0402
C7608
1
2.2UF
20% 25V
2
X6S-CERM 0402
P5VG3S_VFB1_R
1
R7677
200
1% 1/20W MF 201
2
5VG3S_VFB1_RR
1
R7678
41.2K
0.1% 1/16W MF 0402
2
1
R7679
10K
0.1% 1/16W MF 0402
2
1
2
CAPDERATE
C7600
33UF
TANT-POLY CASE-B3-1
CAPDERATE
TANT-POLY
CASE-B1S-1
1
C7605
150UF
20%
6.3V
2
TANT-POLY CASE-B1S-1
CAPDERATE
1
20% 16V
2 25V
C7607
150UF
20%
6.3V
XW7675
XW7671
NO_XNET_CONNECTION=1
5V S0 - V5
1
C7601
2.2UF
20%
2
X6S-CERM 0402
1
OMIT_TABLE
CRITICAL
L7600
2.2UH-20%-4.5A-0.043OHM
PIMA042T-COMBO
2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
1
2
2
SM
1
SM
P5VG3S_VSW
NO STUFF
1
R7674
1
5% 1/10W MF-LF
PLACE_NEAR=C7607.1:3MM
PLACE_NEAR=L7600.1:3MM
2
1
603
2
P5VG3S_SNUBR
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE SWITCH_NODE=TRUE
PLACE_NEAR=L7600.2:3MM
2
XW7670
SM
1
NO_XNET_CONNECTION=1
P5VG3S_CSP1_R P3V3S5_COMP2_R
1
C7602
2.2UF
20% 25V
2
X6S-CERM 0402
1
6 7 8
NO STUFF
C7674
1
0.0033UF
10% 50V
2
X7R-CERM 0402
DIDT=TRUE
CRITICAL
U7600
CSD58879Q3D
Q3D
VIN
VSW
PGND
9
TG
TGR
BG
R7672
4.87K
3
4
5
1%
1/20W
MF
201
1
2
PPBUS_HS_3V3G3H_T
117
C7650
1.0UF
0402
P5VG3S_TG
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 GATE_NODE=TRUE DIDT=TRUE
SKIP_5V3V3:AUDIBLE
P5VG3S_VBST_R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000
C7609
1
0.1UF
10% 25V
2
X6S-CERM 0201
MIN_LINE_WIDTH=0.2000 GATE_NODE=TRUE DIDT=TRUE MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000 DIDT=TRUESWITCH_NODE=TRUE MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000 DIDT=TRUE MIN_NECK_WIDTH=0.1200
C7673
0.1UF
1 2
10%
6.3V X6S
0201
R7673
698
1 2
1%
1/20W
MF
201
R7609
0
5%
1/20W
MF
0201
1
2
GATE_NODE=TRUE DIDT=TRUE
C7678
270PF
10% 16V
X7R-CERM
0201-1
SKIP_5V3V3:INAUDIBLE
1
R7665
1
5% 1/20W MF 201
2
1
2
1
10%
2
25V X6S
0
5%
1/20W
MF
0201
1
2
P5VP3V3_SKIPSEL
P5VG3S_VBST
DIDT=TRUESWITCH_NODE=TRUE
R7651
P5VG3S_DRVH P5VG3S_SW P5VG3S_DRVL P3V3G3H_DRVL P5VG3S_CSP1
P5VG3S_CSN1
P5VG3S_VFB1 P5VG3S_COMP1
P5VG3S_EN_R P3V3G3H_EN
73 73
121 77 73 121 77 73
BOMOPTION=NOSTUFF
1
R7676
10K
1% 1/20W MF 201
2
P5VS4_COMP1_R
C7679
1
2
(P5VP3V3_VREF2)
P5VG3S_PGOOD P3V3MAIN_PGOOD
4700PF
10% 10V X7R 201
GND_5V3V3_AGND
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000 VOLTAGE=0V
73 118
PP5V_G3S
1
R7650
0
5%
1/20W
MF
0201
2
R7675
3.92K
1/20W
201
118
PP1V8_G3S
2
V5SW
6
SKIPSEL1
19
SKIPSEL2
14
OCSEL
31
VBST1 VBST2
1
DRVH1 DRVH2
32
SW1 SW2
30
DRVL1
7
CSP1
8
CSN1 CSN2
11
MODE
9
10
COMP1 COMP2
4
EN1 EN2
5
PGOOD1 PGOOD2
1
1% MF
2
PLACE_NEAR=U7650.28:1MM
23
VIN
CRITICAL
U7650
GND
28
2
XW7650
SM
1
29
VREG5
QFN
22
VREG3
TPS51980B
THRM_PAD
33
P5VP3V3_VREG3 P5VP3V3_VREF2
13
VREF2
EN
DRVL2
CSP2
RF
VFB2VFB1
12
26 24 25 27 18
17 3
16 15
21 20
P5V_3V3G3H_EN
P3V3G3H_VBST P3V3G3H_DRVH P3V3G3H_SW
DIDT=TRUE
P3V3G3H_CSP2 P3V3G3H_CSN2
P3V3G3H_RF P3V3G3H_VFB2 P3V3G3H_COMP2
C7652
0.22UF
10% 10V
CERM
402
SWITCH_NODE=TRUEDIDT=TRUE
1
R7695
3.92K
1% 1/20W MF 201
2
(P5VP3V3_VREF2)
PP3V3_G3H_T
73 118
1
2
BOMOPTION=NOSTUFF
2700PF
PP5V_S5_LDO
CRITICAL
C7651
1
10UF
20%
2
10V X5R-CERM 0402-7
C7653
1
2.2UF
10% 10V
2
X5R-CERM 0402
73
MIN_LINE_WIDTH=0.2000DIDT=TRUE GATE_NODE=TRUE MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000
GATE_NODE=TRUE MIN_LINE_WIDTH=0.2000
10K
1%
1/20W
MF
201
1
2
1
2
1
2
R7696
C7699
10% 16V X7R
0201
VOUT = 5V 100MA MAX OUTPUT
R7685
1
1 2
5%
1/20W
MF
201
P3V3G3H_VBST_R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000
1
R7669
0
5% 1/20W MF 0201
2
MIN_NECK_WIDTH=0.1200
MIN_NECK_WIDTH=0.1200
R7655
200K
1%
1/20W
MF
201
P3V3G3H_TG
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE GATE_NODE=TRUE
X6S-CERM
1
2
C7698
330PF
10% 16V X7R 0201
0.1UF
3.3V DSW - V6
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000
VOLTAGE=5V
U7660
CSD58873Q3D
Q3D
9
10% 25V
0201
C7693
0.1UF
1 2
10%
6.3V X6S
0201
1
2
C7671
R7693
1.37K
1 2
1%
1/20W
MF
201
TG
3
TGR
4
BG
5
CRITICAL
R7692
1
3.83K
1% 1/20W MF 201
2
P3V3G3H_CSP2_R
CAPDERATE
CRITICAL
1
C7660
33UF
20% 16V
2
TANT-POLY CASE-B3-1
APN: 152S0269
1
2
1
L7660
1.0UH-20%-14A-0.0107OHM
VIN
1
6
VSW
PGND
7
P3V3G3H_VSW
8
P3V3G3H_SNUBR
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE
SWITCH_NODE=TRUE
NO STUFF
C7694
1
0.001UF
10%
2
X7R-CERM 0402
DIDT=TRUE
PIMB062D-SM
2
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
NO STUFF
R7694
NO_XNET_CONNECTION=1
1
10
5% 1/10W MF-LF
603
2
XW7690
SM
CAPDERATE
CRITICAL
C7661
33UF
20% 16V TANT-POLY CASE-B3-1
CAPDERATE
1
C7665
150UF
2
CAPDERATE
CRITICAL
1
C7662
33UF
20% 16V
2
TANT-POLY CASE-B3-1
20%
6.3V TANT-POLY CASE-B1S-1
C7666
150UF
20%
6.3V
TANT-POLY
CASE-B1S-1
CAPDERATE
PLACE_NEAR=C7665.1:6MM
2
XW7695
SM
1
PLACE_NEAR=L7660.1:3MM
P3V3G3H_VFB2_R
2
PLACE_NEAR=L7660.2:3MM
XW7691
SM
250V
1
P3V3G3H_VFB2_RR
NO_XNET_CONNECTION=1
1
R7697
R7698
R7699
931
1/20W
201
110K
0.1%
1/16W
402
47K
0.1%
1/16W
0402
PP3V3_G3H_T
CAPDERATE
1
2
1
2
C7669
2.2UF
20% 25V
X6S-CERM
0402
1
1% MF
2
1
MF
2
1
TK
2
CAPDERATE
CRITICAL
1
C7680
33UF
20% 16V
2
TANT-POLY CASE-B3-1
VOUT = 3.3V
12.2A MAX OUTPUT F = 500 KHZ
C7667
150UF
20%
6.3V TANT-POLY CASE-B1S-1
C7668
150UF
20%
6.3V
TANT-POLY
CASE-B1S-1
1
2 25V
2.2UF
X6S-CERM
1
C7672
150UF
2
1
2
CAPDERATE
CASE-B1S-1
C7670
2.2UF
20%
X6S-CERM
0402
C7664
20%
6.3V TANT-POLY CASE-B1S-1
C7676
TANT-POLY
1
20% 25V
2
0402
73 118
CAPDERATE
150UF
20%
6.3V
1
2
C7663
2.2UF
20% 25V
X6S-CERM
0402
CAPDERATE
1
2
D
1
2
C
B
A
152S00703 1
IND,MLD,2.2UH,20%,43mOHM,5.5A,4.2x4x2MM
L7600
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL
121 77
PMU_PVDDMAIN_EN
IN
R7653
47K
5%
1/20W
MF
201
1
5%
1/20W
MF
201
2
R7681
1/20W
47K
5% MF
201
P5VG3S_EN_RP5VG3S_EN
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
1
Power 5V 3.3V Supply
DRAWING NUMBER
SIZE
051-04492
Apple Inc.
2
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=PLATFORM POWER
IV ALL RIGHTS RESERVED
REVISION
2.15.0
BRANCH
PAGE
76 OF 200
SHEET
73 OF 135
A
D
1
2
R7690
100K
R7670
100K
121 77 73
R7652
3.3K
1 2
MF1/20W 2015%
NOSTUFF
R7671
0
1 2
5%
1/20W
MF
1
0201
P5V_3V3G3H_EN
C7642
1
2
C7640
2.2UF
2
X5R-CERM
NOSTUFF
OUT
1000PF
10%
25V X7R 0201
20%
6.3V 0201
P5VG3S_PGOOD
73
P3V3G3H_EN
1
2
1
5%
1/20W
MF
201
2
121 77 73
73 73
121 77
IN
P3V3MAIN_PGOOD
OUT
R7691
0
1 2
5%
1/20W
MF
0201
C7641
2.2UF
20%
6.3V
X5R-CERM
0201
NOSTUFF
8
67
35 4
2
1
Page 74
Vinafix.com
678
3 245
1
D
117
PPBUS_HS_CPU
CRITICAL
1
C7700
12PF
5%
2
25V NP0-C0G 0201
CRITICAL
1
C7701
3.0PF
+/-0.1PF
2
25V NP0-C0G 0201
CAPDERATE
CRITICAL
1
C7702
33UF
20%
2
16V TANT-POLY CASE-B3-1
135 77
CRITICAL
1
C7703
2.2UF
20%
2
25V X6S-CERM 0402
IN
1
C7704
2.2UF
20%
2
25V X6S-CERM 0402
PVDDQ_EN
R8153
47K
5%
1/20W
MF
201
CRITICAL
1/20W
R7700
R7709
1
2
1/20W
0201
0
5% MF
10
5% MF
201
1
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=2.5V
2
PPVIN_S3_DDR2V5_RC
PVPP_EN_R
12
C7705
0.1UF
10% 25V X6S
0402
NOSTUFF
2.5V VPP
D7700
SOD523
AK
PP1V2_S3
74 117 124
Output voltage: Max peak current: Switching freq:
11
12
CRITICAL
PVIN
PVIN
U7700
TPS62130B-S
PGND
15
VQFN
PGND
16
CRITICAL
AGND
6
17
10
AVIN
8
DEF
13
EN
7
FSW
1
2
SS/TR
PAD
THRM
SW SW SW
VOS
FB
PG
DIDT=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
1
REG_PHASE_2V5S3
2 3
14
REG_VOS_P2V5S3 ISNS_2V5_S3_N
5
REG_FB_P2V5S3
4
P2V5_VPP_PGOOD
9
REG_SSTR_P2V5S3
XW7700
SM
12
74
C7706
1
2
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
1.5UH-20%-3.9A-0.048OHM
4700PF
10%
10V
X7R 201
AGND_P2V5S3
L7700
12
1210
P2V5S3_REG
MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0920
VOLTAGE=2.5V
1
R7702
162K
0.1% 1/16W TK 0402
2
<Ra>
1
R7703
76.8K
0.1% 1/16W MF 0402
2
<Rb>
P2V5S3_FSW
SENSOR:DEV
R7724
0.005
0306
MF
1/3W
1%
1 2
12 34
ISNS_2V5_S3_P
R7701
10
5% 1/20W MF 201
XW7701
SM
1 2
OUT
OUT
54 123
54 123
CRITICAL
1
C7707
100UF
20%
2
6.3V POLY-TANT CASE-A3
2.5 V
2.24 A 1250 kHz
CRITICAL
1
C7708
100UF
20%
2
6.3V TANT-POLY CASE-A3-LLP
NOSTUFF
CRITICAL
C7709
1
100UF
20%
2
6.3V TANT-POLY CASE-A3-LLP
NOSTUFF
1
C7764
10UF
20% 4V
2
X6S 0402
PMEG3010EB/S500
D7701
NOSTUFF
PMEG3010EB/S500
1
C7765
10UF
20% 4V
2
X6S 0402
SOD523
AK
PP2V5_S3
117
D
C
B
74 117 124
118
74
74
BYPASS=U7701.6::5mm
C7715
0.1UF
117
PP1V05_PRIM
10%
6.3V X6S
0201
1
2
PP1V2_S3
PP5V_G3S
MEMVTT_EN P2V5_VPP_PGOOD
PLACE_NEAR=U7701.19:5mm
1
R7711
3.3K
1% 1/20W MF 201
2
P1V2REG_VREF_R
1
R7717
21K
0.1% 1/20W MF 0201
2
PLACE_NEAR=U7701.8:5mm
1
R7712
48.7K
0.1% 1/20W MF 0201
2
R7754
0
1 2
1/20WMF0201
5%
R7756
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PLACE_NEAR=U7701.19:3mm
BYPASS=U7701.8::5mm
C7716
1
0.01UF
10%
2
10V X7R-CERM 0201
P1V2REG_AGND
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=0V
VOLTAGE=5V
PP5V_EDRAM_V5IN
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
0
5%
1/20W
MF
0201
121
R7713
47K
1/20W
201
LEVEL SHIFT
1% MF
1
2
1
2
1
R7755
0
5% 1/20W MF 0201
2
MEMVTT_EN_R PVDDQ_EN_R
P1V2REG_VREF
PVCCEDRAM_REFIN P1V2REG_MODE
P1V2REG_TRIP
1
R7714
57.6K
1% 1/20W MF 201
2
PLACE_NEAR=U7701.18:3mm
PP1V8_S5
BYPASS=U7701.12::10mm
C7710
1
10UF
20%
2
10V X5R-CERM 0402-7
V5IN
12 15
S3
17
S5
16
VREF
6
REFIN
8
MODE
19
TRIP
18
PGND GND
10
80
BYPASS=U7701.2::10mm
BYPASS=U7701.2::10mm
1
C7714
10UF
20%
2
10V X5R-CERM
2
VLDOIN
VBST
U7701
DRVH
TPS51916
QFN
CRITICAL
VTT THRM
GND PAD
7
4
PLACE_NEAR=U7701.21:1mm
XW7702
DRVL
PGOOD
VDDQSNS
VTT
VTTSNS
VTTREF
21
2
SM
1
1
C7711
10UF
20%
2
10V X5R-CERM
SW
0402-7
14 13
11 20 9 3 1
5
P1V2_VBST
SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
SWITCH_NODE=TRUE
PVTT_VTTSNS
PPVTT_VTTREF
VOLTAGE=0.6V
C7740
0.22UF
10% 16V
CERM
402
1.2V VDDQ & 0.6V VTT
R7730
2.2
5%
1/20W
MF
201
P1V2_DRVH
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
P1V2_SW
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
DIDT=TRUESWITCH_NODE=TRUE
P1V2_DRVL
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PVDDQ_PGOOD
R7757
0201
1
2
DIDT=TRUE
0
5%MF
1/20W
DIDT=TRUE SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
120402-7
P1V2_BOOT_RC
R7733
1
1 2
5%
1/20W
MF
201
R7732
1
1 2
5%
122
77 74
1/20W
MF
201
DIDT=TRUEGATE_NODE=TRUE
OUT
PLACE_NEAR=U7701.1:5mm
12
DDRREG_VTTSNS
C7730
1
0.1UF
10%
2
25V X6S-CERM 0201
P1V2_DRVH_R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 SWITCH_NODE=TRUE DIDT=TRUE
P1V2_DRVL_R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE
XW7705
SM
1 2
117
PPBUS_HS_CPU
Q7700
CSD58873Q3D
TG
3
TGR
4
BG
5
Q3D
VSW
9
C7731
1
15UF
20%
2
2V X6S 0402
VIN
PGND
1
6 7 8
C7732
1
15UF
20%
2
2V X6S 0402
1
2
CAPDERATE
C7725
33UF
20%
16V TANT-POLY CASE-B3-1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.2V
123 54
123 54
OUT OUT
CRITICAL
1
2
1
C7723
2.2UF
20%
2
25V X6S-CERM 0402
ISNS_CPUDDR_P ISNS_CPUDDR_N
CRITICAL
1
C7713
330UF
20%
2
2.0V POLY-TANT CASE-B2-SM1
1
C7717
330UF
20%
2
2.0V POLY-TANT CASE-B2-SM1
CAPDERATE
C7721
33UF
TANT-POLY CASE-B3-1
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
SWITCH_NODE=TRUE DIDT=TRUE
P1V2_PHASE PP1V2_S3_REG_R
NOSTUFF
R7710
2.2
5% 1/10W MF-LF
603
NOSTUFF
C7712
0.001UF
10% 50V
X7R-CERM
0402
1
20%
2
16V
1
DIDT=TRUE
2
SWITCH_NODE=TRUE
P1V2_LL_SNUB
1
2
CAPDERATE
C7722
33UF
20%
16V TANT-POLY CASE-B3-1
152S00140
L7701
0.68UH-20%-14A
1 2
PILE063T-SM
P1V2_SNS
C7733
1
15UF
20%
2
2V X6S 0402
C7734
1
15UF
20%
2
2V X6S 0402
C7736
1
15UF
20%
2
2V X6S 0402
C7737
1
15UF
20%
2
2V X6S 0402
1
2
1
C7738
15UF
20%
2
X6S 0402
C7724
2.2UF
20% 25V X6S-CERM 0402
R7718
0.002
1% 1W
CYN
0612
CRITICAL
R7741
1 2
1/20W
12 34
1
C7718
330UF
20%
2
POLY-TANT CASE-B2-SM1
10
5% MF
201
1
C7739
15UF
20% 2V
22V
X6S 0402
CRITICAL
1
C7719
10UF
20% 4V
22.0V
X6S 0402
CRITICAL
1
C7720
10UF
20% 4V
2
X6S 0402
P1V2_SNS_R
MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0920
1
C7793
15UF
20% 2V
2
X6S 0402
1
C7794
15UF
20% 2V
2
X6S 0402
CRITICAL
1
C7727
220UF
20% 2V
2
ELEC SM
PP0V6_S0_DDRVTT
1
C7795
15UF
20% 2V
2
X6S 0402
1
C7796
15UF
20%
2
2V X6S 0402
PP1V2_S3
Vout = 1.2V
8.2A MAX OUTPUT F = 400 KHZ
CRITICAL
1
C7728
220UF
20%
2
2V ELEC SM
PLACE_NEAR=C7713.1:5mm
117
74 117 124
2
XW7710
SM
1
C
B
A
121 5
PP2V5_S3
PP1V8_S5
IN
R7758
R7716
1.5K
100K
C7790
0.1UF
10% 10V
X5R-CERM
0201
1 2
1 2
1
2
NC
117
69 78 80
1
VCCA VCCB
U7790
SLSV1T34AMU-COMBO
2 4
5
UDFN
CRITICAL
NC
GND
201MF1/20W1%
201MF1/20W5%
6
BA
3
P2V5_VPP_PGOOD
PVDDQ_PGOOD
C7791
1
0.1UF
10% 10V
2
X5R-CERM 0201
R7791
100K
5%
1/20W
MF
201
TPS51916 Ileak) = +/-1uA Vih(min) = 1.5V 33uW when driven-low
MEMVTT_ENPM_MEMVTT_EN
1
2
74
122 77 74
74
BOM_COST_GROUP=PLATFORM POWER
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
VR 2.5V & 1.2V/VTT
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
77 OF 200
SHEET
74 OF 135
A
8
67
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Vinafix.com
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C
B
A
678
3 245
1
Note : Design based on Calpe ERS - D2449-A0-110-00_0v3.pdf (Radar# 24696002) System Block Diagram - T290 Power System Architecture . v9 Optimize componentS for individual projects based on EDP(A)
CRITICAL
OMIT_TABLE
CRITICAL
L7806
U7800
118
PP3V3_G3H_SOCPMU
C7801
1
10UF
20%
2
6.3V CER-X6S 0402
1
C7810
10UF
20%
2
6.3V CER-X6S 0402
PLACE_NEAR=U7800.R1:5MM
1
2
PLACE_NEAR=U7800.R1:5MM
C7860
1
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U7800.A11:5MM
C7865
1
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U7800.L1:5MM
1
2
PLACE_NEAR=U7800.B18:5MM
1
2
C7891
1UF
20%
6.3V X6S-CERM 0201
C7861
1UF
20%
6.3V X6S-CERM 0201
C7866
1UF
20%
6.3V X6S-CERM 0201
C7802
1
10UF
20%
2
6.3V CER-X6S 0402
1
C7809
10UF
20%
2
6.3V CER-X6S 0402
PLACE_NEAR=U7800.R1:5MM
PLACE_NEAR=U7800.G1:5MM
PLACE_NEAR=U7800.K18:5MM
1
C7892
1UF
20%
6.3V
2
X6S-CERM 0201
C7862
1
1UF
20%
6.3V
2
X6S-CERM 0201
C7867
1
1UF
20%
6.3V
2
X6S-CERM 0201
C7803
1
10UF
20%
2
6.3V CER-X6S 0402
1
C7808
10UF
20%
2
6.3V CER-X6S 0402
C7804
1
10UF
20%
2
6.3V CER-X6S 0402
1
C7807
10UF
20%
2
6.3V CER-X6S 0402
PLACE_NEAR=U7800.R1:10MM
1
C7893
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U7800.C1:5MM
C7863
1
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U7800.P18:5MM
C7868
1
1UF
20%
6.3V
2
X6S-CERM 0201
C7805
1
10UF
20%
2
6.3V CER-X6S 0402
1
C7806
10UF
20%
2
6.3V CER-X6S 0402
PLACE_NEAR=U7800.R1:5MM
1
C7894
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U7800.A7:5MM
C7864
1
1UF
20%
6.3V
2
X6S-CERM 0201
PLACE_NEAR=U7800.F18:5MM
C7869
1
1UF
20%
6.3V
2
X6S-CERM 0201
121 75
Resistor Divider from PBUS VDD_HI < 3.1V
77
IN
PMU_VDD_HI
PP1V8_SLPS2R_PMUVDDGPIO
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V
C7800
1
0.1UF
10%
6.3V
2
X6S 0201
NC NC
Note : All Bucks are default Local Sense
Buck 0,2, and 8 have option for Remote Sense for Future Use.
NC
NC NC
NC NC
NC
CRITICAL
L7821
118 124
PPVCCPRIMCORE_PRIM_REG
Vout = 1.05V Iout_Max = 6A F = 3MHz
1
C7899
20UF
20%
2
2.5V X6S-CERM 0402
1
C7898
20UF
20%
2
2.5V X6S-CERM 0402
C7872
1
20UF
20%
2
2.5V X6S-CERM 0402
1
C7877
20UF
20%
2
2.5V X6S-CERM 0402
1
C7882
20UF
20%
2
2.5V X6S-CERM 0402
C7873
1
20UF
20%
2
2.5V X6S-CERM 0402
1
C7878
20UF
20%
2
2.5V X6S-CERM 0402
1
C7883
20UF
20%
2
2.5V X6S-CERM 0402
C7874
1
20UF
20%
2
2.5V X6S-CERM 0402
1
C7879
20UF
20%
2
2.5V X6S-CERM 0402
1
C7884
20UF
20%
2
2.5V X6S-CERM 0402
C7875
1
20UF
20%
2
2.5V X6S-CERM 0402
1
C7880
20UF
20%
2
2.5V X6S-CERM 0402
1
C7885
20UF
20%
2
2.5V X6S-CERM 0402
C7876
1
20UF
20%
2
2.5V X6S-CERM 0402
1
C7881
20UF
20%
2
2.5V X6S-CERM 0402
1
C7886
20UF
20%
2
2.5V X6S-CERM 0402
0.47UH-20%-4.8A-0.034OHM
0.47UH-20%-4.8A-0.034OHM
PLACE_NEAR=L7822.1:5MM
1 2
0806-COMBO
CRITICAL
L7822
1 2
0806-COMBO
NOSTUFF
R7820
1 2
5%0201 1/20WMF
R7821
1 2
5%0201 MF 1/20W
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE SWITCH_NODE=TRUE
0
0
SWITCH_NODE=TRUE DIDT=TRUE MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.6000
PVCCPRIMCORE_SW0
PVCCPRIMCORE_SW1
PVCCPRIMCORE_FB
80
IN
PPVCCPRIM_FETIN
NC NC NC
NC
NC NC NC
NC
VDD_MAIN_E
P5
VDD_MAIN_N
D10
VDD_MAIN_S
P9
VDD_MAIN_W
K14
VDD_HI
K13
VDD_GPIO
J11
C1 C2
VDD_BUCK0_01
C3 G1
G2
VDD_BUCK0_23
G3 R1
VDD_BUCK16
R2
L1 L2
VDD_BUCK2
L3
B16 B17
VDD_BUCK3
B18
A7
VDD_BUCK4
B7
A11
VDD_BUCK5
B11
F17
VDD_BUCK7
F18
K16 K17
VDD_BUCK8
K18 P16
P17
VDD_BUCK910
P18
T1
BUCK6_LX0
T2
BUCK6_IN
R7
BUCK6_FB
T4
E17
BUCK7_LX0
E18
G17
BUCK7_LX1
G18
BUCK7_RTP
F15
BUCK7_RTN
G15
L16 L17
BUCK8_LX0
L18
J16 J17
BUCK8_LX1
J18
BUCK8_FB
L14
P12 R12
BUCK8_IN
T12 U12 V12
N16 N17
BUCK9_LX0
N18
BUCK9_RTP
P14
BUCK9_RTN
N14
R16 R17
BUCK10_LX0
R18
BUCK10_FB
R14
CALPE-PMU
BGA
SYM 2 OF 4
BUCK0_LX0
BUCK0_LX1
BUCK0_LX2
BUCK0_LX3
BUCK1_LX0
BUCK2_LX0
BUCK2_LX1
BUCK3_LX0
BUCK4_LX0
BUCK4_LX1
BUCK5_LX0
BUCK5_LX1
BUCK3_SW1 BUCK3_SW2 BUCK3_SW3 BUCK3_SW4 BUCK3_SW5
BUCK4_SW1 BUCK6_SW1 BUCK8_SW1
BUCK8_SW2
123
123
123
123
BUCK0_FB
123
BUCK1_FB
123
123
BUCK2_FB
123
BUCK3_FB
BUCK3_IN
123
123
BUCK4_FB
BUCK4_IN
123
123
BUCK5_FB
PVDDCPUAWAKE_SW0
B1
SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200
B2
MIN_LINE_WIDTH=0.6000 DIDT=TRUE
B3
PVDDCPUAWAKE_SW1
D1
SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200
D2
MIN_LINE_WIDTH=0.6000 DIDT=TRUE
D3
0.22UH-20%-6.7A-0.023OHM
PVDDCPUAWAKE_SW2
F1
SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200
F2
MIN_LINE_WIDTH=0.6000 DIDT=TRUE
F3
PVDDCPUAWAKE_SW3
H1
SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200
H2
MIN_LINE_WIDTH=0.6000 DIDT=TRUE
H3
PVDDCPUAWAKE_FB
G5
80
IN
PVDDCPUSRAMAWAKE_SW0
P1
SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200
P2
MIN_LINE_WIDTH=0.6000 DIDT=TRUE
PVDDCPUSRAMAWAKE_FB
R4
P0V8SLPDDR_SW0
K1
SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200
K2
MIN_LINE_WIDTH=0.6000 DIDT=TRUE
K3
P0V8SLPDDR_SW1
M1
SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200
M2
MIN_LINE_WIDTH=0.6000 DIDT=TRUE
M3
P0V8SLPDDR_FB
L5
80
IN
P1V8SLPS2R_SW0
C16
SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200
C17
MIN_LINE_WIDTH=0.6000 DIDT=TRUE
C18
D14
R9 T10 T9 U10 U9 V10 V9
A8 B8
A6 B6
D7
P7
A10 B10
A12 B12
D12
T8 T11 V11 V8 R8
P6 R6 P13
R13
P1V8SLPS2R_FB
PP1V8_SLPS2R
P1V1SLPS2R_SW0
SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.6000 DIDT=TRUE
P1V1SLPS2R_SW1
SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.6000 DIDT=TRUE
P0V9SLPDDR_SW0
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200 SWITCH_NODE=TRUE DIDT=TRUE
P0V9SLPDDR_SW1
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200
SWITCH_NODE=TRUE
DIDT=TRUE
P0V9SLPDDR_FB
NC NC NC
1UH-20%-3.8A-0.055OHM
1 2
2016-COMBO
CRITICAL
L7807
0.22UH-20%-6.7A-0.023OHM
1 2
PINA20121T-SM
CRITICAL
L7808
1 2
PINA20121T-SM
CRITICAL
L7809
0.22UH-20%-6.7A-0.023OHM
1 2
PINA20121T-SM
R7806
0
1 2
1/20W0201 5% MF
L7810
1.0UH-20%-2.6A-0.095OHM
1 2
0805-COMBO
R7811
0
1 2
5% MF
0201
1/20W
1UH-20%-4.7A-0.04OHM
1 2
2520
L7811
CRITICAL
CRITICAL
CRITICAL
PLACE_NEAR=L7810.2:5MM
L7812
0.47UH-20%-4.8A-0.034OHM
1 2
0806
NOSTUFF
R7812
0
1 2
MF
L7813
1UH-20%-3.8A-0.055OHM
1 2
2016-COMBO
R7813
0
1 2
5% 1/20WMF
PLACE_NEAR=L7813.2:5MM
5% 1/20W
CRITICAL
0201
80
CRITICAL
L7814
1UH-20%-3.8A-0.055OHM
1 2
2016-COMBO
CRITICAL
L7815
0.47UH-20%-4.8A-0.034OHM
1 2
0806-COMBO
P1V1SLPS2R_FB
R7814
0
1 2
1/20W
0201
5%
MF
L7816
1 2
2016-COMBO
1UH-20%-3.8A-0.055OHM
CRITICAL
L7817
0.47UH-20%-4.8A-0.034OHM
1 2
0806-COMBO
R7816
0
1 2
1/20W
0201
MF
CRITICAL
PLACE_NEAR=L7816.2:5MM
5%
C7821
1
20UF
20%
2.5V
2
X6S-CERM 0402
1
C7812
20UF
20%
2
2.5V X6S-CERM 0402
PLACE_NEAR=L7806.2:5MM
C7833
1
20UF
20%
2
2.5V X6S-CERM 0402
0201
PLACE_NEAR=L7812.2:5MM
C7839
1
20UF
20%
2
2.5V X6S-CERM 0402
C7846
1
20UF
20%
2
2.5V X6S-CERM 0402
PLACE_NEAR=L7815.2:5MM
1
C7852
20UF
20%
2
2.5V X6S-CERM 0402
C7822
1
2
1
C7811
2
1
2
C7840
1
20UF
20%
2
2.5V X6S-CERM 0402
PP1V8_AWAKE PP1V8_SLPS2R_PMUVDDGPIO PP1V8_S5 NC_PP1V8_S3 NC_PP1V8_S0
PP1V05_S3
C7823
1
20UF
20%
2.5V X6S-CERM 0402
20UF
20%
2.5V X6S-CERM 0402
C7829
1
10UF
20% 4V
2
X6S 0402-1
C7834
20UF
20%
2.5V X6S-CERM 0402
C7847
1
20UF
20%
2
2.5V X6S-CERM 0402
1
C7853
20UF
20%
2
2.5V X6S-CERM 0402
20UF
20%
2.5V
2
X6S-CERM 0402
1
C7826
20UF
20%
2
2.5V X6S-CERM 0402
C7830
1
10UF
20% 4V
2
X6S 0402-1
C7835
1
20UF
20%
2
2.5V X6S-CERM 0402
C7841
1
20UF
20%
2
2.5V X6S-CERM 0402
C7848
1
2
20UF
20%
2.5V X6S-CERM 0402
1
C7854
20UF
20%
2
2.5V X6S-CERM 0402
Supplied Current
80 135
121 75
80
80
80
0.3A
0.3A
1.0A
1.0A
0.5A
0.5A
0.3A
0.3A
117
0.3A
BOM_COST_GROUP=SOC
C7824
1
20UF
20%
2.5V
2
X6S-CERM 0402
1
C7827
20UF
20%
2
2.5V X6S-CERM 0402
C7836
1
2
C7842
1
20UF
20%
2
2.5V X6S-CERM 0402
1
2
PPVDDCPU_AWAKE
C7825
1
20UF
20%
2.5V
2
X6S-CERM 0402
1
C7828
20UF
20%
2
2.5V X6S-CERM 0402
1
C7813
20UF
20%
2
2.5V X6S-CERM 0402
Vout = 0.625V - 1.06V Iout_Max = 13.4A F = 2MHz & 4MHz
PPVDDCPUSRAM_AWAKE
Vout = 0.8V - 1.06V Iout_Max = 1A F = 3MHz
PP0V82_SLPDDR
20UF
20%
2.5V X6S-CERM 0402
C7837
1
20UF
20%
2
2.5V X6S-CERM 0402
C7838
1
20UF
20%
2
2.5V X6S-CERM 0402
C7814
1
20UF
20%
2
2.5V X6S-CERM 0402
C7815
1
20UF
20%
2
2.5V X6S-CERM 0402
Vout = 0.82V Iout_Max = 6A F = 3MHz
PP1V8_SLPS2R
C7843
1
20UF
20%
2
2.5V X6S-CERM 0402
C7844
1
20UF
20%
2
2.5V X6S-CERM 0402
C7845
1
20UF
20%
2
2.5V X6S-CERM 0402
Vout = 1.8V Iout_Max = 2.5A F = 3MHz
PP1V1_SLPS2R
C7849
20UF
20%
2.5V X6S-CERM 0402
C7850
1
20UF
20%
2
2.5V X6S-CERM 0402
C7851
1
20UF
20%
2
2.5V X6S-CERM 0402
C7816
1
20UF
20%
2
2.5V X6S-CERM 0402
C7817
1
20UF
20%
2
2.5V X6S-CERM 0402
Vout = 1.1V Iout_Max = 4A
F = 3MHz
PP0V9_SLPDDR
Vout = 0.9V
1
C7855
20UF
20%
2
2.5V X6S-CERM 0402
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
1
C7856
20UF
20%
2
2.5V X6S-CERM 0402
1
C7818
20UF
20%
2
2.5V X6S-CERM 0402
1
C7819
20UF
20%
2
2.5V X6S-CERM 0402
Iout_Max = 4A F = 3MHz
PMIC BUCKS AND SWs
DRAWING NUMBER
051-04492
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
REVISION
2.15.0
BRANCH
PAGE
78 OF 200
SHEET
75 OF 135
80 124
80 124
80
80 124 135
80 124
SIZE
80 124
D
D
C
B
A
8
67
35 4
2
1
Page 76
Vinafix.com
678
3 245
1
D
118
PP3V3_G3H_SOCPMU
80
PP1V1_SLPS2R
118
PP3V3_G3H_RTC_X PP1V8_SLPS2R
80
C7903
1
0.1UF
10%
6.3V
2
X6S 0201
C7904
1
0.1UF
10%
6.3V
2
X6S 0201
C7909
1
0.1UF
10%
6.3V
2
X6S 0201
CRITICAL
OMIT_TABLE
U7800
CALPE-PMU
BGA
N11
V3P3
N12
V14 U15
LDO1_IN
U14 U17
LDO2_IN
U16 P8
SYM 1 OF 4
LDO_CORE
LDO0 LDO1LDO0_IN LDO2 LDO3
HIO_SW_EN
HIO_SW
L8
V15
N6
T13 U13 V13
C7910
0.1UF
LDO_CORE
PMU_LDO3_OUT_R
1 2
6.3V
10%
D
X6S0201
PP0V8_SLPS2R PP3V0_G3H_RTC
PP1V2_AWAKE
CPU_C10_GATE_L
PP1V05_S0SW
80
80
80
117
48
IN
135 79 78 15
Max Current = 150mA Max Current = 10mA Max Current = 300mA
Max Current = 3A
C
B
A
XW7903
SHORT-14L-0.1MM-SM
PLACE_NEAR=U7800.V5:3mm
1 2
For SI
XW7902
SHORT-14L-0.1MM-SM
PLACE_NEAR=U7800.E4:3mm
1 2
PP7902
P3MM
SM
1
PP
XW7901
SHORT-14L-0.1MM-SM
PP7901
P3MM
SM
PP
GND_PMU_XW2
VOLTAGE=0V
1
GND_PMU_XW1
VOLTAGE=0V
GND_PMU_XW3
VOLTAGE=0V
12
PLACE_NEAR=U7800.J15:3mm
A1 E1 E2
VSS_BUCK0
E3 A2 A3
J1 J2
VSS_BUCK02
J3
B5
VSS_BUCK4
A5
A13
VSS_BUCK5
B13
U1
VSS_BUCK6
U2
T16
VSS_BUCK10
T17 T18
N1 N2
VSS_BUCK21
N3 D16 D17
VSS_BUCK37
D18
B9
VSS_BUCK45
A9 H16 H17
VSS_BUCK78
H18
M16 M17
VSS_BUCK89
M18
VSS_RTC
V5
AVSS_C
M9
AVSS_S
R11
PVSS_N
E11
PVSS_S
U11
PVSS_SE
T5
PVSS_SW
V16
VSSA_BUCK0
E4
VSSA_BUCK1_6/AVSS_SE
R5
VSSA_BUCK2
M4
VSSA_BUCK3
C13
VSSA_BUCK4_5
C10
VSSA_BUCK7
H15
VSSA_BUCK8/AVSS_W
J15
VSSA_BUCK9
M15
VSSA_BUCK10/AVSS_SW
T14
CALPE-PMU
SYM 4 OF 4
CRITICAL
OMIT_TABLE
U7800
BGA
123 96 58 55 54 53
118
PP3V3_G3H_RTC_X
A4 A17 A18 B4 B15 C4 C5 C6 C7 C8 C9 C12 C15 D4 E15 E16 F4 F12 F16 G4 G12 G16 H4 H12
VSS
J4
GND_CALPE_AVSS
J12 K4 K15 L15 N4 N15 P3 P4 P11 P15 R3 R15 T3 T15 U18 U3 U4 U5 U8 V1 V2 V17 V18
135 121 77
1
C7920
1500PF
10%
10V
2
X7R 0201
R7900
1 2
PLACE_NEAR=U7800.J12:3mm
XW7900
SM
1 2
P1V1SLPDDR_RAMP
IN
P1V1_SLPDDR_SOCFET_EN
0
5%
118
PP3V3_G3H_PMU_VINRTC_R
02011/20W MF
C7907
1
10UF
20%
6.3V
2
CER-X6S 0402
PP3V3_G3H_RTC_X
C7921
1
0.1UF
10%
6.3V
2
X6S 0201
C7908
1
10UF
20%
6.3V
2
CER-X6S 0402
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
C7912
1
1UF
20%
6.3V
2
X6S-CERM 0201
C7913
1
1UF
20%
6.3V
2
X6S-CERM 0201
1.1V SLPDDR SWITCH
1
VDD
U7901
SLG5AP1668V
7 3
CAP ON S
2 5
TDFN8
GND
8
D
LDO_RTC
T6
PP1V1_SLPS2R
PP1V1_SLPDDR
VIN_RTC
U6
VIN_RTC_E
H5
VIN_RTC_N
D11
VIN_RTC_S
P10
VIN_RTC_W
M14
VOUT_RTC
VPUMP
V3P3_SW1 V3P3_SW2
80
80
Part : SLG5AP1668V R(ON) : 7.8 mohm (Typical) , 9.6 mohm (max) Current: 5.3A Max
V7
T7 U7
R10
N13 N10
C7905
1
2
1
C7906
2.2UF
10%
10V
2
X6S-CERM 0402
PMU_VPUMP
2.2UF
10%
10V
X6S-CERM 0402
C7911
1
0.1UF
10%
6.3V
2
X6S 0201
1
C7914
2.2UF
10%
2
10V
X6S-CERM 0402
BOM_COST_GROUP=SOC
LDO_RTC
C7902
1
0.01UF
10%
10V
2
X5R-CERM 0201
PP3V3_AWAKE PP3V3_S5
C7901
1
0.1UF
10%
6.3V
2
X6S 0201
PP3V3_G3H_SOCPMU
80
80
SYNC_MASTER=ARMIN SYNC_DATE=01/17/2019
PAGE TITLE
118
Max Current = 300mA Max Current = 500mA
PMIC LDOs
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
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SHEET
76 OF 135
C
B
A
8
67
35 4
2
1
Page 77
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D
123 121 39
120 12
OUT
OUT
PMU_CLK32K_SOC
PMU_CLK32K_PCH
R8012
33
5%
1/20W
MF
201
678
3 245
1
CRITICAL
OMIT_TABLE
U7800
121 39
121 38
121 109 67 29
1
2
121 77 64 39
1
R8011
33
5% 1/20W MF
121 77 38 30
201
2
121 39 12
135
135
46
46
IN IN IN IN IN
OUT
IN
OUT
SOC_WDOG SOC_SOCHOT_L UPC_PMU_RESET SOC_PM_THRMTRIP_L SOC_GPU_THRMTRIP
PMU_COLD_RESET_L
PM_SLP_S0_L PMU_ACTIVE_READY PMU_CLK32K_SOC_R
PMU_CLK32K_PCH_R
121 37 36
47
OUT OUT
80
PMU_CLK32K_WLANBT_R NC_PMU_CLK32K_GNSS_R
NC_PMU_CLK32K
RESET_IN1
F5
RESET_IN2
E5
RESET_IN3
K5
RESET_IN4
K6
RESET_IN5
N5
RESET*
L13
SYS_SLEEP*
M12
J5
ACTIVE_RDY
H6
CLKOUT0_32K
H7
CLKOUT1_32K
J7
CLKOUT2_32K
K7
CLKOUT3_32K CLKOUT4_32K
K8
(IPD)
(IPD)
(IPD)
CALPE-PMU
BGA
SYM 3 OF 4
IREF
VREF
VDROOP
L12
K12
L7
PMU_IREF
PMU_VREF
PMU_DROOP_L
C8001
1
0.1UF
10%
6.3V
2
X6S 0201
1
R8001
200K
1% 1/20W MF 201
2
OUT
D
77 38
C
121 95 92 87 77 39 38
135 121 38 30 29
OUT
SOC_FORCE_DFU
R8010
2.2K
Use SOC's Internal Pull Up
1 2
39
51
51
39
39
121 77 46
80 12
Caution : AMUX programmed with Gain 1 should not have inputs greater than 1.5V
OUT
OUT
IN BI
IN BI OUT OUT
PMU_SYS_ALIVE PMU_FORCE_DFU
MF1/20W 201 5%
PMU_INT_L I2C_PWR_SCL
I2C_PWR_SDA
SPMI_CLK SPMI_DATA ALL_SYS_PWRGD PM_PWRBTN_L
PMU_CPU_ISENSE
59
59
PMU_CPU_VSENSE PMU_GPU_GFX_ISENSE
59
PMU_GPU_GFX_VSENSE
59
59
PMU_GPU_SOC_ISENSE
59
PMU_P1V8_WLAN_ISENSE PMU_CPUDDR_ISENSE
59
PMU_DDR1V2_ISENSE
59
NC_PMU_AMUX_AY
80
SYS_ALIVE
L11
FORCE_DFU
D6
IRQ*
L9
SCL
M11
SDA
L10
SCLK
M8
SDATA
M7
SYS_ACTIVE
K11
SYS_BTN
C11
AMUX_A0
A16
AMUX_A1
A15
AMUX_A2
A14
AMUX_A3
B14
AMUX_A4
C14
AMUX_A5
D15
AMUX_A6
E14
AMUX_A7
F14
AMUX_AY
J14
(IPU) (IPU)
VDROOP_DET
CHG_CBC_ON
NCHG_INT
CHG_POK
VPWR_EN
LDO1_POK
PFN
VIN_BBAT
BUTTON1 BUTTON2
M5 D9
J6 L4
D5 M13 D8 V6
N7 M6
SOC_VDDCPU_SENSE CHGR_CBC_ON
CHGR_INT_L GND
PMU_PVDDMAIN_EN
PCH_RTC_RESET_L
NC
GND
PMU_ONOFF_L PMU_RSLOC_RST_L
80
IN
IN IN IN
OUT
OUT
IN IN
47 42
68
68 47
80
121 73
121 12
To be Grounded on Portables Only, RC on Coin Cell on Desktops
C
135 122 77 67 48
135 122 77 67 65
B
PP1V05_S3
PP3V3_G3H_RTC_X
PP1V8_AWAKE
PP1V8_S5
117
118
29 80
12 36 80
120
PMU_XTAL1_R
CRITICAL
Y8001
32.768KHZ-20PPM-12.5PF
C8002
1
22PF
5%
2
50V C0G 0201
1 2
1.60X1.00-SM
R8013
0
1 2
MF1/20W 0201
5%
C8003
1
22PF
5% 50V
2
C0G 0201
NOSTUFF
59
PMU_GPU_SOC_VSENSE PMU_PBUS_MAIN_SSD0_ISENSE
59
PMU_PBUS_MAIN_SSD1_ISENSE
59
59
PMU_P3V3_G3W_SSD0_ISENSE
59
PMU_P3V3_G3W_SSD1_ISENSE PMU_3V3_X_HI_ISENSE
59
PMU_3V3_T_HI_ISENSE
59
59
PMU_OTHER5V_HI_ISENSE
80
NC_PMU_AMUX_BY
PMU_XTAL1 PMU_XTAL2
120
1
R8018
1M
5% 1/20W MF 201
2
77 6
IN
PMU_VDD_MAX
C8004
1
0.1UF
10%
6.3V
2
X6S 0201
NC NC
CPU_CATERR_L
D13 E13 E12
F13 G13 G14
H14 H13
J13
N9
M10
V3 V4
L6
N8
E6
AMUX_B0 AMUX_B1 AMUX_B2 AMUX_B3 AMUX_B4 AMUX_B5 AMUX_B6 AMUX_B7 AMUX_BY
LS_BID1 LS_BID2
XTAL1 XTAL2
SYS_ERR*
VDD_MAX VDD_OTP
(IPU) (IPU)
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8
GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25
P3V3MAIN_PGOOD
E9
NC_P3V3G3W_EN
E8
NC_P3V3G3W_PGOOD
E7
P5VG3S_EN
F6
P5VG3S_PGOOD
F7
P3V3G3S_EN
F8
P1V8G3S_EN
F9
CPUVR_PGOOD
F10
PVCCIO_EN
G10
PVCCIO_PGOOD
G9
PVDDQ_EN
G8
PVDDQ_PGOOD
G7
NC_AUD_PWR_EN
G6
WLAN_PWR_EN
H8
BT_PWR_EN
H9
SE_PWR_EN
J9
SENSOR_PWR_EN
J8
PVCCPLLOC_EN
K9
NC_PVCCEOPIOEDRAM_P2V7NAND_PGOOD
K10
NC_PEARL_P2V7NAND_EN
J10
UVP_DIS_L
H10
NC_NAND_RESET_L_SD_PWR_EN
H11
NC_NAND_WP_L_ENET_PWR_EN
G11
TBT_PWR_EN
F11
P1V1_SLPDDR_SOCFET_EN
E10
IN
OUT
IN
OUT
IN OUT OUT
IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
IN OUT OUT OUT OUT OUT OUT
80
80
78
47
36
49
79
79
80
80
80
80
80
79
121 73
121 73
121 73
121 79
135 121 79
121 80
121 78
135 74
122 74
37 36
B
135 121 76
A
PP1V8_SLPS2R
R8002 R8003
10K 10K
R8006
R8005
R8015 R8014 R8017
R8007
10K
10K
10K 10K
51
47K
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
NOSTUFF
80
PMU_COLD_RESET_L
MF1/20W 201 5%
PMU_SYS_ALIVE
MF1/20W 201 5%
PMU_DROOP_L
MF1/20W 201 5%
ALL_SYS_PWRGD
MF1/20W 201 5%
PMU_ONOFF_L
MF1/20W 201 5%
PMU_RSLOC_RST_L
MF1/20W 201 5%
CPU_CATERR_L
MF1/20W201 5%
PMU_ACTIVE_READY
MF1/20W201 5%
121 77 64 39
121 95 92 87 77 39 38
77 38
121 77 46
135 122 77 67 48
135 122 77 67 65
77 6
135 121 77 38 30
117
PPBUS_G3H
NOSTUFF
C8051
220PF
10% 16V
CER-X7R
0201
0.1%
1/20W
TK
0201
1
2
PMU_VDD_HI
1
R8051
357K
0.1% 1/20W MF 0201-1
2
OUT
75
PBUS Rising Vth
7.49V 6.97V3S
Falling Vth
BOM_COST_GROUP=SOC
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
PMIC GPIOs & Control
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
80 OF 200
SHEET
77 OF 135
A
R8050
887K
1
2
8
67
35 4
2
1
Page 78
Vinafix.com
678
3 245
1
D
C
8
9 8
D
0.95V VCCIO
PP5V_G3S
118
PVCCIO_BOOT_RC
IN IN
CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N
XW8102
SM
2
1
1
R8150
75
1% 1/20W MF 201
2
Vout = 0.5V * (1 + Ra / Rb)
PP5V_G3S_VCCIOVCC
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=5V
R8144
CPU_VCCIOSENSEPOS_RCPU_VCCIOSENSENEG_R
NO_XNET_CONNECTION=1
R8160
4.42K
1%
1/20W
MF
201
<Ra>
R8162
4.99K
1%
1/20W
MF
201
<Rb> <Rb>
1
2
1
2
1
R8161
4.42K
0.1% 1/20W MF 0201
2
<Ra>
1
R8180
4.99K
0.1% 1/20W MF 0201
2
C8160
10PF
NO_XNET_CONNECTION=1
1
5%
2
C0G
0201
C8161
1
10PF
5% 50V
250V
C0G 0201
C8170
3300PF
1 2
5.0% 50V
CERM 0603
C8163
1
270PF
5% 50V
2
C0G 0402
C8162
2.2UF
20% 25V
X6S-CERM
0402
1
2
PVCCIOS0_EN_FILT_BUF
78
PVCCIOS0_FB PVCCIOS0_SREF PVCCIOS0_VO
78
PVCCOIOS0_OCSET
78
77 78
OUT
PVCCIO_PGOOD PVCCIOS0_RTN PVCCIOS0_FSEL
1
R8164
100K
1% 1/20W MF 201
2
PVCCIOS0_AGND
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=0V
EN FB
6
SREF
4
VO
8
OCSET
7
PGOOD
9 2
RTN
5
FSEL
XW8101
PLACE_NEAR=U8110.1:1mm
1
2.2
5%
1/20W
MF
201
2
13
14
PVCCVCC
1
2
U8110
ISL95870HRUZ
1 2
UTQFN
CRITICAL
PGNDGND
1
SM
BOOT UGATE PHASE
LGATE
16
C8143
10UF
20% 10V X5R-CERM 0402-7
123 11 10 15
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE
2.2
5%
1/20W
MF
201
1
2
R8145
PVCCIO_VBST
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE
PVCCIO_DRVH
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE
PVCCIO_LL
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE
PVCCIO_DRVL_R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 DIDT=TRUE GATE_NODE=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 GATE_NODE=TRUE DIDT=TRUE
PVCCIO_DRVL
C8144
1
0.1UF
20%
2
16V X6S-CERM 0201
PVCCIO_DRVH_R
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
1
R8146
1
5% 1/16W MF-LF 402
2
2
GATE_NODE=TRUEDIDT=TRUE
Q8102
CSD58873Q3D
TG
3
TGR
4
BG
5
R8148
1
5% 1/16W MF-LF
1
402
Q3D
VSW
9
VIN
PGND
CAPDERATE
C8153
1
33UF
20% 16V
2
TANT-POLY CASE-B3-1
1
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 DIDT=TRUE
6 7
PVCCIO_PHASE
8
1
R8116
2.2
5% 1/10W MF-LF 603
2
DIDT=TRUE
0.56UH-20%-16A-0.0072OHM
NOSTUFF
PVCCIO_LL_SNUB
NOSTUFF
C8120
1
0.001UF
10% 50V
2
X7R-CERM 0402
CAPDERATE
1
C8152
33UF
20%
2
16V TANT-POLY CASE-B3-1
L8102
1 2
PILA052D-SM
PPBUS_HS_CPU
1
C8151
2.2UF
20%
2
25V X6S-CERM 0402
PP0V95_S0_CPUVCCIO_REG_R
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
VOLTAGE=0.95V
1
C8150
2.2UF
20%
2
25V X6S-CERM 0402
PVCCIOS0_CS_P
CRITICAL
NO_XNET_CONNECTION=1
PVCCOIOS0_OCSET
78
NO_XNET_CONNECTION=1
C8142
X5R-X7R-CERM
NO_XNET_CONNECTION=1
117
CRITICAL
R8142
3.83K
1%
1/20W
MF
201
470PF
10% 16V
0201
R8102
0.002
1% 1W
CYN
0612
1 2 3 4
1
2
1
2
CRITICAL
C8174
10UF
0402
R8171
10
1 2
1%
MF 201
R8170
10
1 2
MF
20%
4V
X6S
1/20W
1/20W1%
201
1
2
ISNS_CPUVCCIO_POS
ISNS_CPUVCCIO_NEG
PVCCIOS0_CS_N
Vout = 0.95V IccMax = A F = 600kHz
PPVCCIO_S0_CPU
CRITICAL
C8175
10UF
20%
4V
X6S
0402
1
2
1
C8164
220UF
20% 2V
2
ELEC SM
CRITICAL
OUT
OUT
CRITICAL
1
C8165
220UF
20% 2V
2
ELEC SM
123 56
123 56
117 124
C
B
A
PP1V8_S5
R8152
135 79 76 15
121 77
80
PP3V3_S5
IN
IN
69 74 80
100K
1 2
CPU_C10_GATE_L
PVCCIO_EN
C8176
1
0.1UF
10%
6.3V
2
CERM-X5R 0201
R8143
3.83K
1%
1/20W
MF
201
12
PVCCIO_PGOOD
2015% 1/20W MF
PVCCIOS0_VO
78
78 77
B
VCCIO ENABLE LOGIC
C8191
1
0.1UF
10%
6.3V
2
CERM-X5R
U8111
5
6
231
74AUP1T97GM
SOT886
4
PVCCIOS0_EN
5%
1/20W
MF
201
1
2
R8159
100K
NOSTUFF
R8158
3.92K
201 MF 1%
12
PVCCIOS0_EN_R
1/20W
0201
1
C8190
330PF
5% 25V
2
C0G 0201
0201
1
R8190
0
5%MF
1/20W
U8112
74AUP2G17GM/S500-COMBO-1
SOT886
6
PVCCIOS0_EN_FILT PVCCIOS0_EN_FILT_BUF
2 5
C8192
100PF
1 2
5% 25V C0G
0201
NOSTUFF
12
U8112
74AUP2G17GM/S500-COMBO-1
SOT886
3
2 5
4
R8191
47K
5%
1/20W
MF
201
78
1
2
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
VR VCCIO
SIZE
D
BOM_COST_GROUP=PLATFORM POWER
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
81 OF 200
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78 OF 135
8
67
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678
3 245
1
D
121 79 77
C8215
4700PF
10% 10V X7R
3.3V G3 Standby Switch X
PP3V3_G3H_RTC_X
118
C8216
1
1
VDD
U8215
SLG5AP1445V
P3V3G3SX_SS
IN
1
2
P3V3G3S_EN
R8200
47K
1/20W
5% MF
201
7 3
CAP
2 5
ON S
1
2201
TDFN8
GND
8
D
Part R(on)
@ 3.6V Current
SLG5AP1445V
7.8 mOhm Typ
8.5 mOhm Max 4A Max
0.1UF
10% 10V
2
X5R-CERM 0201
PP3V3_G3H_RTC_X PP3V3_G3S_X
118
118
121 79 77
C8210
4700PF
10% 10V X7R 201
1
2
3.3V G3 Standby Switch T
PP3V3_G3H_T
118
C8211
1
1
VDD
U8210
SLG5AP1630V
P3V3G3ST_SS
IN IN
P3V3G3S_EN
R8220
NOSTUFF
47K
5%
1/20W
MF
201
7 3
CAP
2 5
ON S
1
2
STDFN
GND
8
D
Part R(on)
@ 3.6V
SLG5AP1630V 17 mOhm Typ
19 mOhm Max
Current 4A Max
0.1UF
10% 10V
2
X5R-CERM 0201
PP3V3_G3H_T PP3V3_G3S_T
118
118
C8220
4700PF
10% 10V X7R 201
1
2
1.8V G3 Standby Switch
PP3V3_G3H_T
118
1
VDD
U8220
SLG5AP1630V
P1V8G3S_SS P1V8G3S_EN
NOSTUFF
R8221
47K
5%
1/20W
MF
201
1
2
7 3
CAP
2 5
ON S
STDFN
GND
8
D
Part R(on)
@ 3.6V Current
C8221
1
0.1UF
10% 10V
2
X5R-CERM 0201
PP1V8_SLPS2R PP1V8_G3S
SLG5AP1630V 17 mOhm Typ
19 mOhm Max 4A Max
D
80
118
C
118
33 29 27
79 77
PP3V3_G3H_RTC_X
PP3V3_TBT_X_SX
TBT_PWR_EN
R8292
0
1 2
0201MF5% 1/20W
R8295
0
1 2
1/20W5% MF 0201
3.3V S0SW TBT X Switch
0
5%
1/20W
MF
0201
1
2
U8297
SLG5AP1756V
7
CAP
2 5
ON
1
CMP
TDFN
CRITICAL
GND
8
R8294
NOSTUFF
P3V3TBTX_CMP
P3V3TBTX_RAMP TBT_X_PWR_EN_U8297
1
C8298
4700PF
10% 10V
2
X7R 201
D
S
Part
1.1V S0SW VCCPLL_OC Switch
117
C
117
1
C8297
1.0UF
20%
6.3V
2
X5R 0201-1
77
135 78 76 15
80
PP3V3_S5
C8240
0.1UF
80
PP1V8_S5
U8245
74AUP1G08GF
SOT891
6
VCC
IN
IN
PVCCPLLOC_EN CPU_C10_GATE_L
C8245
0.1UF
10%
6.3V
CERM-X5R
0201
NC
1
2
2
A Y
AND
1
B
5
NC
GND
3
P1V1S0SW_FET_EN
4
1
R8245
100K
5% 1/20W MF 201
2
C8242
100PF
5% 25V C0G
0201
P1V1S0SW_RAMP
1
2
CERM-X5R
10%
6.3V 0201
1
1
2
VDD
U8240
SLG5AP1635V
7 3
CAP ON
2 5
STDFN
CRITICAL
GND
8
D
S
Part Type R(on)
Current
PP1V2_S3
C8241
1
1.0UF
20%
6.3V
2
X5R 0201-1
SLG5AP1635V Load Switch
27.5 mOhm Typ 31 mOhm Max@ 3.3V
2.5A Max
PP1V2_S0SW
EDP: 130mA
VCCPLL_OC has turn-on requirement of
3
PP3V3_S0SW_TBT_X
118
11uS min and 240uS max from EN to 1.1V
SLG5AP1756V
B
118
113 109 107
79 77
3.3V S0SW TBT T Switch
PP3V3_G3H_T
R8299
0
5%
1/20W
MF
R8290
0
PP3V3_TBT_T_SX
1 2
5% 1/20W MF 0201
R8296
0
TBT_PWR_EN TBT_T_PWR_EN_U8295
1 2
5% 1/20W MF 0201
P3V3TBTT_CMP
P3V3TBTT_RAMP
1
C8296
4700PF
10% 10V
2
X7R 201
0201
NOSTUFF
Type R(on)
@ 4A Current
Load Switch
7.8 mOhm Typ
8.5 mOhm Max 4A Max
B
3.3V Sensor Switch
LOADISNS
U8250
PP3V3_G3H_T
118
1
1
2
U8295
SLG5AP1756V
7
CAP
2 5
ON
1
CMP
TDFN
CRITICAL
GND
8
D
S
Part
3
C8295
1.0UF
20%
6.3V
2
X5R 0201-1
PP3V3_S0SW_TBT_T
SLG5AP1756V
118
77
IN
SENSOR_PWR_EN
C8250
1.0UF
20%
6.3V X5R
0201-1
LOADISNS
2
1
1
2
SLG5AP1569V
STDFN
CRITICAL
VIN ON
GND
4
VOUT
Part
Type
@ 3.6V
Current
PP3V3_G3SSW_SNS
3
SLGAP1569V
Load Switch
34 mOhm TypR(on) 46 mOhm Max
1A Max
118
A
8
Type R(on)
@ 4A Current
67
Load Switch
7.8 mOhm Typ
8.5 mOhm Max 4A Max
BOM_COST_GROUP=PLATFORM POWER
35 4
SYNC_MASTER=ARMIN
PAGE TITLE
Power FETs
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
82 OF 200
SHEET
79 OF 135
1
SIZE
D
SYNC_DATE=01/17/2019
A
Page 80
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678
PMIC Buck0 - SoC VDD_CPU PMIC Buck4 - SDRAM VDD2 NC Aliases
3 245
1
D
C
B
75 124
PPVDDCPU_AWAKE
PMIC Buck1 - SoC VDD_CPU_SRAM
75 124
PPVDDCPUSRAM_AWAKE
PMIC Buck2 - SoC VDD_SOC
PP0V82_SLPDDR
75
PMIC BUCK3 - SoC AOP/SMC/VDD1
PP1V8_SLPS2R
75 124 135
PMIC BUCK3 SW 1
PP1V8_AWAKE
75 135
PMIC BUCK3 SW 3
PPVDDCPU_AWAKE
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.06V MAKE_BASE=TRUE
PPVDDCPU_AWAKE
PPVDDCPUSRAM_AWAKE
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.06V MAKE_BASE=TRUE
PPVDDCPUSRAM_AWAKE
PP0V82_SLPDDR
MIN_LINE_WIDTH=0.7000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.82V MAKE_BASE=TRUE
PP0V82_SLPDDR
PP1V8_SLPS2R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V MAKE_BASE=TRUE
PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_AWAKE
MIN_NECK_WIDTH=0.1200
PP1V8_AWAKE PP1V8_AWAKE PP1V8_AWAKE PP1V8_AWAKE PP1V8_AWAKE PP1V8_AWAKE PP1V8_AWAKE PP1V8_AWAKE PP1V8_AWAKE PP1V8_AWAKE PP1V8_AWAKE
VOLTAGE=1.8VMIN_LINE_WIDTH=0.2000 MAKE_BASE=TRUE
123 121 121
42 80
75 124
PP1V1_SLPS2R
PP1V1_SLPS2R
MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V MAKE_BASE=TRUE
PP1V1_SLPS2R PP1V1_SLPS2R PP1V1_SLPS2R PP1V1_SLPS2R
121
42
Buck 4 Ext. SW U7901 - VDDIO_DDR & PLL
76
PP1V1_SLPDDR
123 121
PP1V1_SLPDDR
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.1V MAKE_BASE=TRUE
PP1V1_SLPDDR PP1V1_SLPDDR
42 80
PP1V1_SLPDDR PP1V1_SLPDDR
123 122 121
PMIC Buck5 - VDD_FIXED
75
79
76
46
77
64
46
38 47
44
44
44
44
68
51
51
51
47
29 30 31 110 111
135
PP0V9_SLPDDR
75 124
PMIC LDO0 - VDD_LOW
76
PP0V8_SLPS2R
PP0V9_SLPDDR
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.9V MAKE_BASE=TRUE
PP0V9_SLPDDR PP0V9_SLPDDR PP0V9_SLPDDR PP0V9_SLPDDR PP0V9_SLPDDR
PP0V8_SLPS2R
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=0.8V MAKE_BASE=TRUE
PP0V8_SLPS2R
PMIC LDO2 - PCIE_REFBUF/PLL
48
47
121 66
29 77
46
44
44
44
44
44
41 46 47
46
76
PP1V2_AWAKE
PMIC V3P3 SW 1 - USB
76
PP3V3_AWAKE
PP1V2_AWAKE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.2V MAKE_BASE=TRUE
PP1V2_AWAKE PP1V2_AWAKE PP1V2_AWAKE PP1V2_AWAKE
PP3V3_AWAKE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_AWAKE
121
43
43
43
43
43
121
43
121
44
44
44
44
121
44
76
76
43
44
121
38
43
43
44
77
77
77
77
77
77
77
NC_PVCCEOPIOEDRAM_P2V7NAND_PGOOD NC_PEARL_P2V7NAND_EN UVP_DIS_L NC_NAND_RESET_L_SD_PWR_EN NC_NAND_WP_L_ENET_PWR_EN NC_P3V3G3W_PGOOD NC_P3V3G3W_EN
Alternate Feedback Sesne
75
75
75
OUT
OUT
OUT
PVDDCPUAWAKE_FB Buck0 - Remote
PLACE_NEAR=R7806.1:5MM
P0V8SLPDDR_FB Buck2 - Remote
PLACE_NEAR=R7812.1:5MM
PVCCPRIMCORE_FB Buck8 - Remote
PLACE_NEAR=R7820.2:5MM
NOSTUFF
R8320
0
1 2
5% 1/16W MF-LF
402
R8321
0
1 2
5% 1/16W MF-LF
402
R8322
0
1 2
5% 1/16W MF-LF
402
MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE
PVDDCPUAWAKE_FB_R
P0V8SLPDDR_FB_R
PVCCPRIMCORE_FB_R
NC_PVCCEOPIOEDRAM_P2V7NAND_PGOOD NC_PEARL_P2V7NAND_EN UVP_DIS_L NC_NAND_RESET_L_SD_PWR_EN NC_NAND_WP_L_ENET_PWR_EN NC_P3V3G3W_PGOOD NC_P3V3G3W_EN
XW8320
SM
1 2
PLACE_NEAR=U3900.AA12:4MM
XW8321
SM
1 2
PLACE_NEAR=U3900.AA20:6MM
XW8322
SM
1 2
PLACE_NEAR=U1200.AB12:4MM
PPVDDCPU_AWAKE
PP0V82_SLPDDR
PP1V05_PRIM
47
D
42 80
42 80
C
16 17 117
B
A
PP1V8_S5
75
75
75
PMIC BUCK3 SW 4/5
NC_PP1V8_S3 NC_PP1V8_S0
PP1V8_S5
PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5 PP1V8_S5
NC_PP1V8_S3
MAKE_BASE=TRUE
NC_PP1V8_S0
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=1.8V MAKE_BASE=TRUE
121
46
16 17
39
12 16
12 13 15 16 19 20 52
15
17
12 36 77
51
51
51
46
69 74 78
95
79
74
16
57
57
57
46
18
PMIC V3P3 SW 2 (Internal) -
PP3V3_S5
76
PMIC LDO 1 - PCH VCCRTC
76
PP3V0_G3H_RTC
PP3V3_S5
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1500 VOLTAGE=3.3V MAKE_BASE=TRUE
PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5
PP3V0_G3H_RTC
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200 VOLTAGE=3.0V MAKE_BASE=TRUE
PP3V0_G3H_RTC
121
12 16 17
46
78
15 16 19
14 16
15 16
18
20
12 16 17
79
12 29
95 115 126
135
16
47
121
12 16 17
121 18
121 77
46 8
77
77
NC_CHGR_AUX_OK PM_PWRBTN_L CPUVR_PGOOD CPU_VCCST_PWRGD NC_PMU_CLK32K NC_PMU_AMUX_BY NC_PMU_AMUX_AY
GND GND
MAKE_BASE MAKE_BASE MAKE_BASE MAKE_BASE
MAKE_BASE MAKE_BASE MAKE_BASE
MAKE_BASE MAKE_BASE
NC_CHGR_AUX_OK PM_PWRBTN_L CPUVR_PGOOD CPU_VCCST_PWRGD NC_PMU_CLK32K NC_PMU_AMUX_BY NC_PMU_AMUX_AY
68
12 77
69
69
77
77
77
SYNC_MASTER=ARMIN SYNC_DATE=01/17/2019
PAGE TITLE
SOC/PMIC Aliases
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
83 OF 200
SHEET
80 OF 135
A
8
67
35 4
2
1
Page 81
Vinafix.com
Page Notes
Power aliases required by this page:
- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)
- =PP5V_G3S_BKLT (5V BACKLIGHT DRIVER INPUT)
678
PBUS LINE WIDTHS
3 245
1
L8452
47-OHM-25%-300MA
PPVOUT_S0_LCDBKLT_F
PLACE_NEAR=D8410.K:8MM PLACE_NEAR=D8410.K:12MM PLACE_NEAR=D8410.K:12MM PLACE_NEAR=D8410.K:8MM PLACE_NEAR=D8410.K:8MM
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200
VOLTAGE=59V
1 2
0402
PPVOUT_S0_LCDBKLT
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200
VOLTAGE=59V
MAKE_BASE=TRUE
124
122 82 81
D
C
B
PPBUS_G3H
117
SENSOR ON PAGE 54 USES R8400 TO MEASURE THE
POWER GOING TO LCD BACKLIGHT
740S0159
F8400
3AMP-32V
1 2
0603-COMBO
PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW
81
PPVIN_S0SW_LCDBKLT_FET
VOLTAGE=12.6V
MIN_NECK_WIDTH=0.0850 MIN_LINE_WIDTH=0.0920
123 53
123 53
ISNS_LCDBKLT_P
OUT
ISNS_LCDBKLT_N
OUT
GND_BKLT_SGND
81
SOC_KBD_BKLT_PWM
47
GND_BKLT_SGND
81
122 82
122 82
I2C ID DEDICATED.ONLY CONNECTS TO JERRY
1
R8440
1M
5% 1/20W MF 201
2
81 118
PP5V_G3S
IN
BI
CRITICAL
R8400
0.025
1% 1W MF
0612-1
1 2 3 4
IN
PP3V3_G3S_X
118
PLACE_NEAR=U8472.6:5MM
1
R8481
100K
1% 1/20W MF 201
2
I2C_BKLT_SCL
I2C_BKLT_SDA
MIN_LINE_WIDTH=0.6000
PPVIN_S0SW_LCDBKLT_R
VOLTAGE=12.6V
1
C8400
1000PF
10%
2
16V X7R-1 0201
1
C8483
0.1UF
16V
X5R-CERM
2
0201
1
R8452
1.8K
5% 1/20W MF 201
2
10%
1
2
1
R8401
80.6K
1% 1/16W MF-LF 402
2
1
R8402
63.4K
1% 1/16W MF-LF 402
2
PLACE_NEAR=U8400.5:5MM PLACE_NEAR=U8400.5:5MM
81
R8442
81
1 2
GND_BKLT_SGND
U8472
74AUP1T97GM
5
SOT886
4
6
3
1
R8453
1.8K
5% 1/20W MF 201
2
R8451
1 2
1/20W
PLACE_NEAR=U8400.16:10MM
0201
CRITICAL
Q8400
FDC638APZ_SBMS001
SSOT6-HF
4
3
6 5 2 1
LCDBKLT_EN_L
PP5V_G3S
81 118
R8444
C8440
GND_BKLT_SGND
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000
BKLT_SD
BKLT_SENSE_OUT
0
5%
1/20W
MF
0201
BKLT_PWM_KEYB_3V3
PLACE_NEAR=U8400.15:10MM
0
5% MF
BKLT_EN_REDP_BKLT_EN
1
2
R8450
0
1 2
5%
1/20W
MF
0201
NO STUFF
C8442
1
33PF
5%
2
25V NP0-C0G 0201
R8480
100K
1% 1/20W MF 201
BKLT_SCL
BKLT_SDA
10
1/16W MF-LF
402
4.7UF
20% 25V X5R
0402
NOSTUFF
1
C8401
2
1
5%
2
81
1
2
0.001UF
10% 50V CERM 402
1
R8445
10
5% 1/16W MF-LF 402
2
PP5V_G3S_BKLT_A
81
VOLTAGE=5V
MIN_NECK_WIDTH=0.1000 MIN_LINE_WIDTH=0.6000
PP5V_G3S_BKLT_D
1
C8441
4.7UF
20%
2
25V X5R 0402
11
SD
9
VSENSE_N VSENSE_P
10 19
SENSE_OUT
17
EN
12
PWM_KEYB
15
SCL
16
SDA
GND_SW 24
PPVIN_S0SW_LCDBKLT
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200MIN_NECK_WIDTH=0.1200
VOLTAGE=12.6V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200
VOLTAGE=5V
18
5
VDDA
VDDD
U8400
WQFN
LP8548B1SQX06
SW SW
FB
GD
ISET_KEYB
KEYB1
GNDD 3
SM
KEYB2
SW2
FB2
THRM
GNDA
PAD
22
25
GND_BKLT_SGND
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
VOLTAGE=0V
(IPU)
(IPU)
GND_SW
GND_SW2 7
23
XW8400
1 2
DIDT=TRUE
VOLTAGE=59V
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.3000
2
LCDBKLT_SW
1
LCDBKLT_FB
21 4
LCDBKLT_FET_DRV
20 13
14 6
8
PLACE_NEAR=L8410.1:5MM PLACE_NEAR=L8410.1:5MM PLACE_NEAR=L8410.1:5MM
CRITICAL
1
C8410
4.7UF
10%
2
25V X6S-CERM 0603
PLACEMENT_NOTE:
SANDWICH C8210 AND C8211 SANDWICH C8410 AND C8411
SWITCH_NODE=TRUE
BKLT_ISET_KEYB
BKLT_KEYB1
BKLT_KEYB2 KBDBKLT_SW2
PPVOUT_BKLT_FB2
1
R8454
31.6K
1% 1/20W MF 201
2
PP5V_G3S_KBDLED
118
PLACE_NEAR=Q8401.5:3MM
CRITICAL
15UH-20%-1.9A-0.24OHM
1 2
CRITICAL
1
C8411
4.7UF
10%
2
25V X6S-CERM 0603
LCDBKLT_FET_DRV_R
81
81 81
MF-LF 1/16W 1%402
1
C8452
2.2UF
10% 25V
2
X5R-CERM 603
81
1
C8412
0.1UF
10%
2
25V X5R 402
1
2
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
10
1 2
81
MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.2500
SWITCH_NODE=TRUE
DIDT=TRUE
1
2
L8410
PIME062D-SM
152S00253
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.6000
VOLTAGE=59V
81
PPVIN_SW_LCDBKLT_SW
4
R8433
10
5% 1/16W MF-LF 402
VOLTAGE=5V
R8435
MF-LF 1/16W402 1%
MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.2000
VOLTAGE=40V
1 2
L8450
10UH-20%-1.4A-0.17OHM
1 2
PST041H-SM
1
C8450
0.1UF
10% 16V X5R-CERM 0201
C8451
2.2UF
10% 25V
2
X5R-CERM 603
371S00077107S00034
D8410
SOD123-COMBO
A K
PMEG10020ELR-DFLS2100
CRITICAL
MAKE_BASE=TRUE
1
C8499
12PF
5% 100V CERM 0402
2
5
376S0678
CRITICAL
Q8401
SI7812DN
PWRPK-1212-8
1 2 3
DIDT=TRUEGATE_NODE=TRUE
10
PLACE_NEAR=U8400.1:5MM
R8436
PMEG6010ER/S500
PLACE_NEAR=D8410.K:6MM
KBDLED_CATHODE1 KBDLED_CATHODE2
XW8450
D8450
SOD123W
A K
SM
1
2
2
XW8410
2
PLACE_NEAR=C8458.1:10MM
1
SM
1
1
LCDBKLT_TB_XWR
R8431
28.7K
1% 1/16W MF-LF 402
2
1
R8432
150K
1% 1/16W MF-LF 402
2
122 81
122 81
PPVOUT_S0_KBDLED_R
1
C8458
2.2UF
10% 50V
2
X5R 0603
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
C8453
2.2UF
10% 50V X5R 0603
1
C8456
2.2UF
10% 50V
2
X5R 0603
1
C8459
2
1
C8454
2.2UF
10% 50V
2
X5R 0603
1
C8457
2.2UF
10% 50V
2
X5R 0603
2.2UF
10% 50V X5R 0603
CRITICAL
C8460
1
2.2UF
10%
2
100V X5R 1206
PLACE_NEAR=D8410.K:8MM PLACE_NEAR=D8410.K:8MM PLACE_NEAR=D8410.K:8MM PLACE_NEAR=D8410.K:8MM PLACE_NEAR=D8410.K:8MM
CRITICAL
1
C8465
2.2UF
10%
2
100V X5R 1206
PLACE_NEAR=D8410.K:12MM PLACE_NEAR=D8410.K:12MM PLACE_NEAR=D8410.K:12MM PLACE_NEAR=D8410.K:12MM
CRITICAL
1
C8470
2.2UF
10%
2
100V X5R 1206
NOSTUFF
C8430
1
100PF
5%
2
100V C0G-CERM 0603
KBDLED_CATHODE1
122 81
122 81
PPVOUT_S0_KBDLED
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000
VOLTAGE=40V
C8455
1
0.001UF
10% 50V
2
X7R-CERM 0402
C8491
122 81
1
12PF
5%
2
100V CERM 0402
KBDLED_CATHODE2
1
C8494
2
C8490
1
12PF
5% 100V
2
CERM 0402
1
C8493
2.2UF
10% 50V
2
X5R 0603
CRITICAL
C8461
1
2.2UF
10%
2
100V X5R 1206
CRITICAL
1
C8466
2.2UF
10%
2
100V X5R 1206
CRITICAL
1
C8471
2.2UF
10%
2
100V X5R 1206
R8446
0
1 2
5% 1/16W MF-LF
402
2.2UF
10% 50V X5R 0603
CRITICAL
C8462
1
2.2UF
10%
2
100V X5R 1206
CRITICAL
1
C8467
2.2UF
10%
2
100V X5R 1206
CRITICAL
1
C8472
2.2UF
10%
2
100V X5R 1206
VOUT = 52V TYP, 59V MAX IOUT = 0.135A TYP, 0.15A MAX FS = 625KHZ TYP (+/- 7%)
FF14A-6C-R11DL-B-3H
J8400
F-RT-SM
7
1 2 3
NC
4
NC
5 6
8
FF14A-6C-R11DL-B-3H
NC NC
CRITICAL
1
2
1
2
1
2
J8401
F-RT-SM
7
1 2 3 4 5 6
8
C8463
2.2UF
10% 100V X5R 1206
CRITICAL
C8468
2.2UF
10% 100V X5R 1206
CRITICAL
C8473
2.2UF
10% 100V X5R 1206
CRITICAL
C8464
1
2.2UF
10%
2
100V X5R 1206
CRITICAL
1
C8469
2.2UF
10%
2
100V X5R 1206
D
C
B
A
8
81
81
81
124 122 82 81
81
81
81
81
81
81
81
81
81
122 81
PP5V_G3S_BKLT_D PP5V_G3S_BKLT_A BKLT_EN_R PPVOUT_S0_LCDBKLT LCDBKLT_FB LCDBKLT_FET_DRV_R LCDBKLT_SW BKLT_SD LCDBKLT_EN_L PPVIN_S0SW_LCDBKLT
PPVIN_S0SW_LCDBKLT_FET
PPVIN_SW_LCDBKLT_SW
KBDBKLT_SW2 PPVOUT_S0_KBDLED
TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5 TP-P5
1
TP
TPA8400
1
TP
TPA8401
1
TP
TPA8402
1
TP
TPA8403
1
TP
TPA8404
1
TP
TPA8405
1
TP
TPA8406
1
TP
TPA8407
1
TP
TPA8408
1
TP
TPA8410
1
TP
TPA8411
1
TP
TPA8412
1
TP
TPA8414
1
TP
TPA8415
67
LCD BKLT LINE WIDTHS
124 122 82 81
IN
PPVOUT_S0_LCDBKLT
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1200
VOLTAGE=59V
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
LCD Backlight Driver
DRAWING NUMBER
051-04492
Apple Inc.
REVISION
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=DISPLAY
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
84 OF 200
SHEET
81 OF 135
1
SIZE
D
Page 82
Vinafix.com
678
3 245
1
D
C
B
LCD PANEL INTERFACE (eDP) + Camera (MIPI)
PP5V_G3S
118
1
VDD
U8500
TDFN
GND
8
51
D8518
SOD962-COMBO
PMEG3002ESF
BYPASS=U8510::5MM
C8570
1
0.1UF
10% 10V
2
X5R-CERM 0201
3 84
6 10
5 11
PP3V3_G3S_X
D
AK
EDP_PANEL_PWR_BUF_EN
1
C8511
0.1UF
10%
2
10V X5R-CERM 0201
NC NC NC
NC NC
R8544
0
1 2
5%
1/20W
MF
0201
1
C8512
10UF
20%
2
10V X5R-CERM 0402-7
LCD_PWR_SLEW_3V3
C8516
1
0.47UF
10%
6.3V
2
CERM-X5R 0201
122 82
HOST SIDE
NOSTUFF
1
R8505
100K
5% 1/20W MF 201
2
SEP_CAM_DISABLE_DFF_R_L
S OUTPUT L Camera Disable
H Camera Enable
123 40
123 40
123 40
123 40
52
52
82 118
PP3V3_G3S_X
MIPI_FTCAM_CLK_P
MIPI_FTCAM_CLK_N
MIPI_FTCAM_DATA_P<0>
MIPI_FTCAM_DATA_N<0>
I2C_FTCAM_SDA
I2C_FTCAM_SCL
PP3V3_G3H_RTC_X
82 118
95 82
IN
EDP_PANEL_PWR_EN
EDP_PANEL_PWR_EN
95 82
EDP_PANEL_PWR_DLY_EN
82
R8517
330
1 2
2015%
1/20W
MF
R8515
150K
1 2
5%
1/20W
MF
201
PANEL_P5V_EN_D
1
R8570
100K
5% 1/20W MF 201
2
SMCRST_TIEOFF
LCD_PWR_SLEW
PANEL_P5V_EN
D8517
SOD962-COMBO
A K
PMEG3002ESF
R8518
330
1 2
1/20W
MF
EDP_PANEL_PWR_DLY_EN
1
R8571
100K
5% 1/20W MF 201
2
PM_SLP_TIEOFF
2
EDP_PANEL_PWR_EN PM_SLP_S3_L
12 9
SMC_RESET_INPUT_L
1
TP
TP-P5 TP-P5
TPA8500
1
TP
TPA8501
64
IN
CRITICAL
SLG5AP1443V
7 3
CAP
2 5
ON S
C8515
1
0.1UF
10% 10V
2
X5R-CERM 0201
R8516
200K
1 2
1%
1/20W
MF
201
PANEL_P3V3_EN_D
2015%
1
VDD
SLG4AP4998
PANEL_PWR_EN_CONN
STQFN
SMC_RESET_OUTPUT_L
X604_DISP_SMC_RST_L
GND
7
SEP_CAM_DISABLE_DFF_L
C8509
1
4700PF
10% 10V
2
X7R 201
U8510
PANEL_FET_EN_DLY
X604_DISP_PWR_EN
82 118
PANEL_P3V3_EN
NC0 NC1
VOLTAGE=5V
PP5V_S0SW_LCD
82 118
PP3V3_G3H_RTC_X
CRITICAL
SLG5AP1443V
7 3
CAP
2 5
ON S
C8513
1
4700PF
10% 10V
2
X7R 201
1
VDD
U8501
TDFN
GND
8
BYPASS=U8502::5MM
C8502
1
0.1UF
10%
2
10V X5R-CERM 0201
D
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
11
1
20%
2
X5R
CRITICAL
NX3DV642GU
QFN-COMBO
CLK+
1
CLK-
2
1D+
3
1D-
4
2D+
5
2D-
6
8
OE*
CONTROL
S
VOLTAGE=3.3V
PP3V3_S0SW_LCD_R
C8510
1.0UF
6.3V
0201-1
10
VCC
U8502
LOGIC
GND
9
123 55
CLK1+
CLK2+
CLK1-
CLK2-
1D1+
1D2+
1D1-
1D2-
2D1+
2D2+
2D1-
2D2-
NC NC
Alternate: OnSemi FSA642 (353S01346)
ISNS_LCDPANEL_P
55 123
ISNS_LCDPANEL_N
17
22
GND_VOID=TRUE
16
23
GND_VOID=TRUE
15
20
GND_VOID=TRUE
14
21
GND_VOID=TRUE
13
19
12
18
7 24
NC
NC
82
MIPI_FTCAM_DATA_ISOL_P<0>
82
MIPI_FTCAM_DATA_ISOL_N<0>
122 82
MIPI_FTCAM_CLK_ISOL_P
82
MIPI_FTCAM_CLK_ISOL_N
82
118
PP5V_G3S
SENSOR:DEV
R8520
0.01
1/3W 0306
1 2 3 4
NO_XNET_CONNECTION=1
1% MF
PP3V3_S0SW_LCD
MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000 VOLTAGE=3.3V
DP_INT_HPD
1
R8551
100K
5% 1/20W MF 201
2
MIPI_FTCAM_CLK_ISOL_P
MIPI_FTCAM_CLK_ISOL_N
MIPI_FTCAM_DATA_ISOL_P<0>
MIPI_FTCAM_DATA_ISOL_N<0>
I2C_CAM_ISOL_SDA
I2C_CAM_ISOL_SCL
NC NC
82
82
122 95 82
82
82
MIPIC FILTERING
122 82 51
PP1V8_G3S
52 118
L8502
3.25-OHM-0.1A-2.4GHZ TAM0605-4SM
SYM_VER-1
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
1
2 3
L8503
3.25-OHM-0.1A-2.4GHZ TAM0605-4SM
SYM_VER-1
1
2 3
L8504
FERR-120-OHM-1.5A
1 2
0402A
122 82 51
122 82
122 95 82
122 95 82
122 95
122 95
122 95
122 95
122 95
122 95
122 95
122 95
PP3V3_S0SW_LCD
BKLT_PWM_MLB2TCON
BI BI
BI BI
BI BI
BI BI
BI BI
122 82
122 82
122 82
122 82
1
R8510
100K
5% 1/20W MF 201
2
EDP_INT_AUX_N EDP_INT_AUX_P
EDP_INT_ML_N<0> EDP_INT_ML_P<0>
EDP_INT_ML_N<1> EDP_INT_ML_P<1>
EDP_INT_ML_N<2> EDP_INT_ML_P<2>
EDP_INT_ML_N<3> EDP_INT_ML_P<3>
MIPI_FTCAM_DATA_CONN_N<0> MIPI_FTCAM_DATA_CONN_P<0>
MIPI_FTCAM_CLK_CONN_N MIPI_FTCAM_CLK_CONN_P
PLACE_NEAR=J8500.33:6mm
GND_VOID=TRUE
4
MIPI_FTCAM_DATA_CONN_P<0>
GND_VOID=TRUE
MIPI_FTCAM_DATA_CONN_N<0>
GND_VOID=TRUE
4
MIPI_FTCAM_CLK_CONN_P
GND_VOID=TRUE
MIPI_FTCAM_CLK_CONN_N
PP5V_S0_ALSCAM_F
VOLTAGE=5V
1
R8511
100K
5% 1/20W MF 201
2
PLACE_NEAR=J8500.39:5mm
1
C8504
0.1UF
10% 10V
2
X5R-CERM 0201
GND_VOID=TRUE
GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE
NOSTUFF
1
R8508
10K
5% 1/20W MF 201
2
1
R8507
10K
5% 1/20W MF 201
2
20759-042E-02
122 82
C8500
82
1000PF
82 122
122
122 82
100V
X7R-CERM
0603
LCD Panel HPD & AUX strapping
NO_XNET_CONNECTION=1
122 82
NO_XNET_CONNECTION=1
J8500
F-ST-SM
43 44
PWR
SIGNAL
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
PWR
45 46
GND
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
PPVOUT_S0_LCDBKLT
1
10%
2
PP3V3_G3H_RTC_X
82 118
122 95 82
122 95 82
EDP_INT_AUX_N
EDP_INT_AUX_P
PP3V3_S0SW_LCDPPVOUT_S0_LCDBKLT
EDP_PANEL_PWR_BUF_EN DP_INT_HPD LCD_MUX_SEL
BKLT_PWM_MLB2TCON
I2C_BKLT_SDA I2C_BKLT_SCL I2C_TCON_SDA I2C_TCON_SCL
I2C_ALS_SDA
I2C_ALS_SCL I2C_CAM_ISOL_SCL I2C_CAM_ISOL_SDA
PP5V_S0_ALSCAM_FPP5V_S0SW_LCD
NOSTUFF
NOSTUFF
1
2
1
2
CKPLUS_WAIVE=I2C_PULLUP CKPLUS_WAIVE=I2C_PULLUP
124 122 82 81
R8503
1M
5% 1/20W MF 201
R8502
1M
5% 1/20W MF 201
122 82 51 124 122 82 81
122 82
122 95 82
122 95
122 82
BI
122
BI
122
BI BI
52
BI
52
BI
CKPLUS_WAIVE=I2C_PULLUP CKPLUS_WAIVE=I2C_PULLUP
122 82
122 82
122 82 122 82
D
C
82 81
82 81
122 51
122 51
B
A
8
PP3V3_S0SW_LCD PP5V_S0SW_LCD PP5V_S0_ALSCAM_F I2C_BKLT_SDA I2C_BKLT_SCL
NOSTUFF
C8554
1
12PF
5% 25V NP0-C0G
2
0201
C8550
1
12PF
5% 25V NP0-C0G
2
0201
C8551
1
12PF
5% 25V NP0-C0G
2
0201
C8552
1
12PF
5% 25V NP0-C0G
2
0201
NOSTUFF
C8553
1
12PF
5% 25V NP0-C0G
2
0201
BOM_COST_GROUP=DISPLAY
67
35 4
122 82 51
122 82
122 82
122 82 81
122 82 81
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
eDP Display Connector
SIZE
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
A
D
2.15.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
85 OF 200
SHEET
82 OF 135
1
Page 83
Vinafix.com
678
3 245
1
D
126 121 87 86 85 84 83
120 83
120 83
120 83
120 83
OUT
OUT
IN
IN
PCIE_SSD1_R2D_P<0>
PCIE_SSD1_R2D_N<0>
PCIE_SSD1_D2R_C_P<0>
PCIE_SSD1_D2R_C_N<0>
C8603 C8604 C8601 C8602
GND_VOID=TRUE
GND_VOID=TRUE
2
GND_VOID=TRUE
GND_VOID=TRUE
12
GND_VOID=TRUE
12
GND_VOID=TRUE
1
GND_VOID=TRUE
12
GND_VOID=TRUE
0.22UF
6.3V 10% 0201X5R-CERM
0.22UF
6.3V X5R-CERM 020110%
0.22UF
0.22UF
6.3V 10% X5R-CERM 0201
PCIE_SSD1_R2D_C_P<0>
PCIE_SSD1_R2D_C_N<0>
PCIE_SSD1_D2R_P<0>
X5R-CERM 020110%6.3V
PCIE_SSD1_D2R_N<0>
IN
IN
OUT
OUT
120 41
120 41
120 41
120 41
S4E0
PP1V8_SSD1 PP0V9_SSD1
126
D
121 87 86 85 84 83
C
126 123 121 87 86 85 84
PP2V5_NAND_SSD1
C8648
1
10UF
20%
2
6.3V CERM-X6S 0402
CRITICAL
C8632
1
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
C8636
4.3UF
3
C8649
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
1
20%
2
4
4V
CERM
0402-THICKSTNCL
CRITICAL
C8650
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
C8637
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
126 121 87 86 85 84 83
NOSTUFF
1
R8630
0
5% 1/20W MF 0201
2
PP0V9_SSD1
SSD1_S4E0_VPP
F3
VPP
R2
R4
VDD_PLL
L12
VCC
G4
E12
D3
P9
T5
K9
N2
VDDIO
J2
E10
E2
R8
R6
L8
VDD
L6
G8
G6
G12J4L2
ANI0_VREF
ANI1_VREF
AVDD18_PLL
J6
N8
J8
PCI_VDD_1
PCI_VDD_2
PCI_AVDD_H
TP_SSD1_S4E0_ANI1_VREF TP_SSD1_S4E0_ANI0_VREF
PP1V8_SSD1_S4E0_AVDD18_PLL PP1V8_SSD1_S4E0_PCI_AVDD_H
PP0V9_SSD1
N6
M9
121
121
126 121 87 86 85 84 83
1
C8610
10UF
20%
6.3V CERM-X6S
2
0402
CRITICAL
C8646
1
1.0UF
20% 10V
2
X5R-CERM 0201-1
1
C8644
1.0UF
20% 10V
2
X5R-CERM 0201-1
C8611
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
C8647
1
0.1UF
10% 16V
2
X5R-CERM 0201
1
C8645
0.1UF
10% 16V
2
X5R-CERM 0201
C8612
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
C8613
1
0.1UF
10%
2
16V X5R-CERM 0201
R8601
0
5%
1 2
1/20W
MF
0201
R8699
0
1 2
5%
1/20W
MF
0201
C8614
1
0.1UF
10%
2
16V X5R-CERM 0201
C8615
1
0.1UF
10%
2
16V X5R-CERM 0201
PP1V8_SSD1
126
121 87 86 85 84 83
C
B
121 87 86 85 84 83
126
PP1V8_SSD1
1
R8602
47K
1% 1/20W MF 201
2
NOSTUFF
1
R8603
47K
1% 1/20W MF 201
2
87 86 85 84
91 90 89 88 86 85 84 38
86 85 84 83
86 85 84
123
87 86 85 84 83
86 85 84 47 41
123 86 85 84 39
123 86 85 84 39
123
86 84
TPA8601
123 86 85 84
87 86 85 84 47
123
IN IN IN
IN
OUT
IN
IN
BI
OUT
OUT
TP
TP-P6
IN
IN
SSD1_OCARINA_LPB_L SSD_BFH SSD1_S4E_BOOT2
83
SSD1_S4E0_SWD_UID0 SSD1_S4E_UART_RX
83
SSD1_S4E0_SWD_UID1 SSD1_S4E0_UART_TX SSD1_OCARINA_PFN
SSD1_PCIE_RESET_L SSD1_SWDIO_UART_D2R SSD1_SWCLK_UART_R2D SSD1_S4E0_JTAG_TDO
1
SSD1_S4E0_JTAG_TDI SSD1_S4E_JTAG_SEL
83
SSD1_S4E0_DROOP_L SSD1_OCARINA_WP_L
B3
EXT_D0/BOOT0
C4
EXT_D1/BOOT1
B5
EXT_D2/BOOT2/SPINAND_SCLK EXT_D3/SWD_UID0/SPINAND_MISO
C6
EXT_D4/UART_RX
B7
EXT_D5/SWD_UID1/SPINAND_MOSI
C8
EXT_D6/UART_TX
B9
EXT_D7/SPF
B11
E8
EXT_NCE/PERST*
D7
EXT_NRE/JTAG_TMS
E6
EXT_NWE/JTAG_TCK
E4
EXT_RNB/JTAG_TDO
D5
EXT_CLE/JTAG_TDI
D9
EXT_ALE/JTAG_SEL
T3
DROOP_N
G2
WP_N
U8600
H23QFG82D6ADS-64GB
LGA
OMIT_TABLE
CRITICAL
PCI_AVDD_CLK_1
PCI_AVDD_CLK_2
PCIE_REFCLK_P
PCIE_REFCLK_M PCIE_CLKREQ_N
PCI_RESREF
PCIE_RX0_P
PCIE_RX0_M
PCIE_TX0_P
PCIE_TX0_M
CLK_IN
RESET*
TRST*
ZQ_C ZQ_N
M3 K11
GND_VOID=TRUE
J12
GND_VOID=TRUE
P5 H7 M11
GND_VOID=TRUE
N12
GND_VOID=TRUE
R12
GND_VOID=TRUE
T11
GND_VOID=TRUE
L4 G10 K3
C10
SSD1_CLK24M_01 PCIE_CLK100M_SSD1_01_P
PCIE_CLK100M_SSD1_01_N SSD1_CLKREQ0_L SSD1_S4E0_PCIE_RESREF
PCIE_SSD1_R2D_P<0> PCIE_SSD1_R2D_N<0>
PCIE_SSD1_D2R_C_P<0> PCIE_SSD1_D2R_C_N<0>
SSD1_OCARINA_RESET_L SSD1_S4E_JTAG_TRST_L SSD1_S4E0_ZQ_C
SSD1_S4E0_ZQ_L
84
IN IN
OUT
IN IN
OUT OUT
R8640
100
1 2
MF 2011/20W 1%
123 84 41
123 84 41
47 41
120 83
120 83
120 83
120 83
SSD1_CLK24M
1
R8604
3.01K
1% 1/20W MF 201
2
IN
86 85 84
IN
85 47
B
87 86 85 84
A
1
R8620
100K
1% 1/20W MF 201
2 201
1
R8608
100K
1% 1/20W MF
2 201
SSD1_OCARINA_PFN
SSD1_S4E0_DROOP_L
83
SSD1_S4E_BOOT2 SSD1_S4E0_SWD_UID0 SSD1_S4E0_SWD_UID1
1
R8609
100K
1% 1/20W MF
2
83
83
PLACE_NEAR=U8600.C10:5mm
87 86 85 84 83
T1
T7
U8
U10
U12
86 85 84 83
T13
R10
P13
P11
T9
U2
U4
U6
P7
P3
P1
N10
N4
M13
M7
M5
M1
L10
K13
K7
VSS
K5
K1
J10
H13
H11
H9
H5
H3
H1
F13
F11
F9
F7
F5
F1
D13
D11
D1
C12
C2
B13
B1
A12
A10
A8
A6
A4
A2
1
R8605
300
1% 1/20W MF 201
2
R8606
1
100
1% 1/20W MF 201
2
1
R8600
100K
1% 1/20W MF 201
2
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
SSD1 S4E 0
SIZE
D
BOM_COST_GROUP=SDD
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
86 OF 200
SHEET
83 OF 135
8
67
35 4
2
1
Page 84
Vinafix.com
678
3 245
1
D
S4E1
126 121 87 86 85 84 83 126 121 87 86 85 84 83
126 123 121 87 86 85 84 83
126 121 87 86 85 84 83
NOSTUFF
1
R8730
0
5% 1/20W MF 0201
2
PP1V8_SSD1 PP0V9_SSD1
PP2V5_NAND_SSD1
TP_SSD1_S4E1_ANI1_VREF TP_SSD1_S4E1_ANI0_VREF
PP0V9_SSD1
PP1V8_SSD1_S4E1_AVDD18_PLL PP1V8_SSD1_S4E1_PCI_AVDD_H
SSD1_S4E1_VPP
F3
VPP
R2
R4
VDD_PLL
L12
VCC
G4
E12
D3
P9
T5
K9
N2
VDDIO
J2
E10
E2
R8
R6
L8
VDD
L6
G8
G6
ANI0_VREF
ANI1_VREF
PP0V9_SSD1
G12J4L2
J8
PCI_VDD_2
AVDD18_PLL
N8
PCI_VDD_1
J6
PCI_AVDD_H
M9
N6
120 84
120 84
120 84
120 84
121
121
OUT
OUT
IN
IN
84
84
PCIE_SSD1_R2D_P<1>
PCIE_SSD1_R2D_N<1>
PCIE_SSD1_D2R_C_P<1>
PCIE_SSD1_D2R_C_N<1>
126 121 87 86 85 84 83
S4E_L6
12
GND_VOID=TRUEGND_VOID=TRUE
12
S4E_L6
GND_VOID=TRUEGND_VOID=TRUE
S4E_L6
GND_VOID=TRUE GND_VOID=TRUE
6.3V 020110% X5R-CERM
GND_VOID=TRUE
12
S4E_L6
12
GND_VOID=TRUE
0.22UF
X5R-CERM
0.22UF
0201 X5R-CERM
0.22UF
0.22UF
C8703
10% 6.3V0201
C8704
6.3V
10%
C8701
C8702
6.3V0201 10%X5R-CERM
PCIE_SSD1_R2D_C_P<1>
PCIE_SSD1_R2D_C_N<1>
PCIE_SSD1_D2R_P<1>
PCIE_SSD1_D2R_N<1>
IN
IN
OUT
OUT
120 41
120 41
120 41
120 41
D
C
87 86 85 83
91 90 89 88 86 85 83 38
86 85 83
86 85 83
123
87 86 85 83
86 85 83 47 41
123 86 85 83 39
123 86 85 83 39
123 86 85
123 86 83
123 86 85 83
87 86 85 83 47
IN IN IN
IN
OUT
IN
IN
OUT
OUT
IN
IN
IN
U8700
H23QFG82D6ADS-64GB
SSD1_OCARINA_LPB_L SSD_BFH SSD1_S4E_BOOT2
84
SSD1_S4E1_SWD_UID0 SSD1_S4E_UART_RX
84
SSD1_S4E1_SWD_UID1 SSD1_S4E1_UART_TX SSD1_OCARINA_PFN SSD1_PCIE_RESET_L
SSD1_SWDIO_UART_D2R
BI
SSD1_SWCLK_UART_R2D SSD1_S4E1_JTAG_TDO SSD1_S4E0_JTAG_TDO SSD1_S4E_JTAG_SEL
84
SSD1_S4E1_DROOP_L
SSD1_OCARINA_WP_L
B3
EXT_D0/BOOT0
C4
EXT_D1/BOOT1
B5
EXT_D2/BOOT2/SPINAND_SCLK EXT_D3/SWD_UID0/SPINAND_MISO
C6
EXT_D4/UART_RX
B7
EXT_D5/SWD_UID1/SPINAND_MOSI
C8
EXT_D6/UART_TX
B9
EXT_D7/SPF
B11
E8
EXT_NCE/PERST*
D7
EXT_NRE/JTAG_TMS
E6
EXT_NWE/JTAG_TCK
E4
EXT_RNB/JTAG_TDO
D5
EXT_CLE/JTAG_TDI
D9
EXT_ALE/JTAG_SEL
T3
DROOP_N
G2
WP_N
U2
U4
U6
U12
U10
U8
T13
T9
T7
T1
R10
P13
P11
P7
P3
P1
N10
N4
M13
M7
M5
M1
L10
LGA
OMIT_TABLE
CRITICAL
VSS
K1
K5
K13
K7
J10
H13
H11
H9
H5
H3
H1
F13
F11
F9
F7
F5
F1
D13
D11
D1
PCI_AVDD_CLK_1
PCI_AVDD_CLK_2
PCIE_REFCLK_P
PCIE_REFCLK_M PCIE_CLKREQ_N
PCI_RESREF
PCIE_RX0_P
PCIE_RX0_M
PCIE_TX0_P
PCIE_TX0_M
B1
C12
C2
B13
A12
A10
CLK_IN
RESET*
TRST*
ZQ_C ZQ_N
A6
A8
GND_VOID=TRUE
GND_VOID=TRUE
A2
A4
M3 K11
GND_VOID=TRUE
J12
GND_VOID=TRUE
P5 H7 M11
GND_VOID=TRUE
N12
GND_VOID=TRUE
R12 T11
L4 G10 K3
C10
SSD1_CLK24M_01 PCIE_CLK100M_SSD1_01_P PCIE_CLK100M_SSD1_01_N
SSD1_CLKREQ1_L SSD1_S4E1_PCIE_RESREF
PCIE_SSD1_R2D_P<1> PCIE_SSD1_R2D_N<1>
PCIE_SSD1_D2R_C_P<1> PCIE_SSD1_D2R_C_N<1>
SSD1_OCARINA_RESET_L SSD1_S4E_JTAG_TRST_L
SSD1_S4E1_ZQ_C SSD1_S4E1_ZQ_L
S4E_L6
1
R8705
300
1% 1/20W MF 201
2
83
IN
84
86 85 83
120 84
120
120 84
120 84
123 83 41
123 83 41
S4E_L6
1
R8704
3.01K
1% 1/20W MF 201
2
87 86 85 83
C
IN IN
123 47 41
IN IN
OUT OUT
S4E_L6
1
R8706
100
1% 1/20W MF 201
2
B
87 86 85 84 83
126 121
PP1V8_SSD1
S4E_L6
R8702
1
47K
1% 1/20W MF 201
2
S4E_L6
1
R8709
100K
1% 1/20W MF 201
2
S4E_L6
1
R8708
100K
1% 1/20W MF 201
2
SSD1_S4E1_DROOP_L
SSD1_S4E1_SWD_UID1
84
84
B
S4E VDDIO
S4E VDD
126 121 87 86 85 84 83 84
PP0V9_SSD1SSD1_S4E1_SWD_UID0
S4E_L6
1
C8710
10UF
20%
6.3V CERM-X6S
2
0402
CRITICAL
S4E_L6
C8711
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L6
C8712
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L6
1
C8713
0.1UF
16V
10%
2
X5R-CERM 0201
S4E_L6
1
C8714
0.1UF
16V
10%
2
X5R-CERM 0201
S4E_L6
1
C8715
0.1UF
16V
10%
2
X5R-CERM 0201
126 121 87 86 85 84 83
126 121 87 86 85 84 83
PP1V8_SSD1
VCC CAP
PP1V8_SSD1
S4E_L6
1
C8732
10UF
6.3V20%
2
CERM-X6S 0402
CRITICAL
S4E_L6
R8700
0
5%
1 2
1/20W
MF
0201
S4E_L6
C8736
4.3UF
3
2
4
CERM
S4E_L6
1
C8744
1.0UF
20%10V
2
X5R-CERM 0201-1
S4E_L6
C8737
1
1
20%
4V
0402-THICKSTNCL
CRITICAL
2.2UF
20%
6.3V
2
X5R-CERM 0201
PP1V8_SSD1_S4E1_PCI_AVDD_H
S4E_L6
1
C8745
0.1UF
16V
10%
2
X5R-CERM 0201
A
8
126 123 121 87 86 85 84 83
67
PP2V5_NAND_SSD1
S4E_L6
1
C8748
10UF
20%
2
6.3V CERM-X6S 0402
CRITICAL
S4E_L6
1
C8749
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L6
1
C8750
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L6
R8701
0
5%
1 2
1/20W
MF
0201
PP1V8_SSD1_S4E1_AVDD18_PLL
S4E_L6
C8746
1
1.0UF
20%10V X5R-CERM
2
0201-1
S4E_L6
C8747
1
0.1UF
16V10% X5R-CERM
2
0201
BOM_COST_GROUP=SDD
35 4
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
SSD1 S4E 1
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
87 OF 200
SHEET
84 OF 135
1
A
Page 85
Vinafix.com
678
3 245
1
D
126 123 121 87 86 85 84 83
126 121 87 86 85 84 83
NOSTUFF
1
R8830
0
5% 1/20W MF 0201
2
S4E2
126 121 87 86 85 84 83 126 121 87 86 85 84 83
PP2V5_NAND_SSD1
PP0V9_SSD1
SSD1_S4E2_VPP
PP1V8_SSD1 PP0V9_SSD1
F3
VPP
R2
R4
VDD_PLL
L12
VCC
G4
E12
D3
P9
T5
K9
N2
VDDIO
J2
E10
E2
R8
R6
L8
VDD
L6
G8
G6
G12J4L2
ANI0_VREF
ANI1_VREF
J8
PCI_VDD_1
PCI_VDD_2
AVDD18_PLL
PP1V8_SSD1_S4E2_AVDD18_PLL PP1V8_SSD1_S4E2_PCI_AVDD_H
J6
N8
PCI_AVDD_H
TP_SSD1_S4E2_ANI1_VREF TP_SSD1_S4E2_ANI0_VREF
PP0V9_SSD1
N6
M9
121
121
120 85
120 85
120 85
120 85
126 121 87 86 85 84 83
OUT
OUT
IN
IN
PCIE_SSD1_R2D_P<2>
PCIE_SSD1_R2D_N<2>
PCIE_SSD1_D2R_C_P<2>
PCIE_SSD1_D2R_C_N<2>
C8803 C8804
C8801 C8802
0.22UF
GND_VOID=TRUE GND_VOID=TRUE
0.22UF
0.22UF
GND_VOID=TRUE GND_VOID=TRUE
0.22UF
GND_VOID=TRUE GND_VOID=TRUE
S4E_L7
12
S4E_L7
12
GND_VOID=TRUEGND_VOID=TRUE
S4E_L7
12
S4E_L7
12
PCIE_SSD1_R2D_C_P<2>
PCIE_SSD1_R2D_C_N<2>
X5R-CERM 0201 6.3V
PCIE_SSD1_D2R_P<2>
PCIE_SSD1_D2R_N<2>
6.3V 10%0201X5R-CERM
10%
10%6.3V0201X5R-CERM
10%6.3VX5R-CERM 0201
IN
IN
OUT
OUT
120 41
120 41
120 41
120 41
D
C
87 86 84 83
91 90 89 88 86 84 83 38
86 84 83
86 84 83
123
87 86 84 83
86 84 83 47 41
123 86 84 83 39
123 86 84 83 39
123 86
123 86 84
123 86 84 83
87 86 84 83 47
BI
OUT
OUT
IN
IN IN IN
IN
OUT
IN
IN
IN
IN
SSD1_OCARINA_LPB_L SSD_BFH SSD1_S4E_BOOT2 SSD1_S4E2_SWD_UID0
85
SSD1_S4E_UART_RX SSD1_S4E2_SWD_UID1
85
SSD1_S4E2_UART_TX SSD1_OCARINA_PFN
SSD1_PCIE_RESET_L
SSD1_SWDIO_UART_D2R SSD1_SWCLK_UART_R2D
SSD1_S4E2_JTAG_TDO SSD1_S4E1_JTAG_TDO SSD1_S4E_JTAG_SEL SSD1_S4E2_DROOP_L
85
SSD1_OCARINA_WP_L
B3
EXT_D0/BOOT0
C4
EXT_D1/BOOT1
B5
EXT_D2/BOOT2/SPINAND_SCLK EXT_D3/SWD_UID0/SPINAND_MISO
C6
EXT_D4/UART_RX
B7
EXT_D5/SWD_UID1/SPINAND_MOSI
C8
EXT_D6/UART_TX
B9
EXT_D7/SPF
B11
E8
EXT_NCE/PERST*
D7
EXT_NRE/JTAG_TMS
E6
EXT_NWE/JTAG_TCK
E4
EXT_RNB/JTAG_TDO
D5
EXT_CLE/JTAG_TDI
D9
EXT_ALE/JTAG_SEL
T3
DROOP_N
G2
WP_N
U8800
H23QFG82D6ADS-64GB
LGA
OMIT_TABLE
CRITICAL
PCI_AVDD_CLK_1
PCI_AVDD_CLK_2
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_CLKREQ_N
PCI_RESREF
PCIE_RX0_P
PCIE_RX0_M
PCIE_TX0_P
PCIE_TX0_M
CLK_IN
RESET*
TRST*
M3 K11
GND_VOID=TRUE
J12
GND_VOID=TRUE
P5 H7 M11
GND_VOID=TRUE
N12
GND_VOID=TRUE
R12
GND_VOID=TRUE
T11
GND_VOID=TRUE
L4 G10
SSD1_CLK24M_23
86
PCIE_CLK100M_SSD1_23_P PCIE_CLK100M_SSD1_23_N
SSD1_CLKREQ2_L SSD1_S4E2_PCIE_RESREF PCIE_SSD1_R2D_P<2>
PCIE_SSD1_R2D_N<2>
PCIE_SSD1_D2R_C_P<2> PCIE_SSD1_D2R_C_N<2>
SSD1_OCARINA_RESET_L SSD1_S4E_JTAG_TRST_L
S4E_L7
R8840
100
1 2
SSD1_CLK24M
201 MF 1%
1/20W
IN IN
OUT OUT
IN
IN
IN IN
OUT
87 86 84 83
S4E_L7
1
R8804
3.01K
1% 1/20W MF 201
2
120 85
120 85
120 85
120 85
86 84 83
83 47
123 86 41
123 86 41
47 41
C
B
121 87 86 85 84 83
126
PP1V8_SSD1
S4E_L7
1
R8802
47K
1% 1/20W MF 201
2
S4E_L7
1
R8809
100K
1% 1/20W MF 201
2
SSD1_S4E2_SWD_UID1
85
U12
U10
U8
U6
U4
U2
T13
T9
T7
T1
R10
P13
P11
P7
P3
P1
N10
N4
M13
M7
M5
M1
L10
K13
K7
VSS
K5
K1
J10
H13
H11
H9
H5
H3
H1
F13
F11
F9
F7
F5
F1
D13
D11
D1
C12
C2
B13
B1
A12
A10
A8
ZQ_C ZQ_N
A4
A6
A2
K3 C10
SSD1_S4E2_ZQ_C SSD1_S4E2_ZQ_L
S4E_L7
1
R8805
300
1% 1/20W MF 201
2
S4E_L7
1
R8806
100
1% 1/20W MF 201
2
B
S4E_L7
1
R8808
100K
1% 1/20W MF 201
2
SSD1_S4E2_DROOP_L
SSD1_S4E2_SWD_UID0
85
85
126 121 87 86 85 84 83
S4E VDD
PP0V9_SSD1
S4E_L7
1
C8810
10UF
20%
6.3V CERM-X6S
2
0402
CRITICAL
S4E_L7
C8811
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L7
C8812
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L7
1
C8813
0.1UF
10% 16V X5R-CERM
2
0201
VCC CAP
S4E_L7
1
C8814
0.1UF
10% 16V X5R-CERM
2
0201
S4E_L7
1
C8815
0.1UF
10% 16V X5R-CERM
2
0201
126 121 87 86 85 84 83
126 121 87 86 85 84 83
S4E VDDIO
PP1V8_SSD1
PP1V8_SSD1
S4E_L7
1
C8832
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
S4E_L7
R8800
0
5%
1 2
1/20W
MF
0201
S4E_L7
C8836
4.3UF
3
2
4
CERM
PP1V8_SSD1_S4E2_PCI_AVDD_H
S4E_L7
1
C8844
1.0UF
20% 10V X5R-CERM
2
0201-1
1
20%
4V
0402-THICKSTNCL
CRITICAL
S4E_L7
1
C8845
0.1UF
10% 16V X5R-CERM
2
0201
S4E_L7
C8837
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
85
A
8
126 123 121 87 86 85 84 83
67
PP2V5_NAND_SSD1
S4E_L7
C8848
1
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
S4E_L7
C8849
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L7
C8850
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L7
R8801
0
5%
1 2
1/20W
MF
0201
85
PP1V8_SSD1_S4E2_AVDD18_PLL
S4E_L7
1
C8846
1.0UF
20% 10V X5R-CERM
2
0201-1
S4E_L7
1
C8847
0.1UF
10% 16V X5R-CERM
2
0201
35 4
BOM_COST_GROUP=SDD
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
SSD1 S4E 2
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
88 OF 200
SHEET
85 OF 135
1
A
Page 86
Vinafix.com
678
3 245
1
D
126 123 121 87 86 85 84 83
126 121 87 86 85 84 83
NOSTUFF
1
R8930
0
5% 1/20W MF 0201
2
S4E3
126 121 87 86 85 84 83 126 121 87 86 85 84 83
PP1V8_SSD1
PP2V5_NAND_SSD1
PP0V9_SSD1
SSD1_S4E3_VPP
D3
E12
G4
L12
F3
VPP
R2
R4
VDD_PLL
VCC
P9
T5
K9
N2
VDDIO
J2
E10
E2
R8
R6
L8
VDD
L6
G8
G6
ANI1_VREF
PP0V9_SSD1
G12J4L2
ANI0_VREF
J8
PCI_VDD_2
AVDD18_PLL
J6
N8
PCI_VDD_1
PCI_AVDD_H
TP_SSD1_S4E3_ANI1_VREF TP_SSD1_S4E3_ANI0_VREF
PP1V8_SSD1_S4E3_AVDD18_PLL PP1V8_SSD1_S4E3_PCI_AVDD_H PP0V9_SSD1
N6
M9
120 86
120 86
120 86
121
120 86
121
86
86
126 121 87 86 85 84 83
PCIE_SSD1_R2D_P<3>
OUT
OUT
PCIE_SSD1_D2R_C_P<3>
IN
PCIE_SSD1_D2R_C_N<3>
IN
C8903
GND_VOID=TRUE GND_VOID=TRUE
C8904
GND_VOID=TRUE
C8901
GND_VOID=TRUE
C8902
GND_VOID=TRUE GND_VOID=TRUE
0.22UF
12
12
0.22UF
GND_VOID=TRUE
0.22UF
12
GND_VOID=TRUE
0.22UF
12
10% 0201 X5R-CERM 6.3V
S4E_L8
S4E_L8
020110% 6.3V
10% 0201 X5R-CERM 6.3V
X5R-CERM
S4E_L8
S4E_L8
PCIE_SSD1_R2D_C_P<3>
PCIE_SSD1_R2D_C_N<3>PCIE_SSD1_R2D_N<3>
PCIE_SSD1_D2R_P<3>
PCIE_SSD1_D2R_N<3>
6.3V10% X5R-CERM0201
IN
IN
OUT
OUT
120 41
120 41
120 41
120 41
D
C
86 85 84 83
126 121 87
PP1V8_SSD1
S4E_L8
R8902
1
47K
1% 1/20W MF 201
2
S4E_L8
1
R8908
100K
1% 1/20W MF 201
2
87 85 84 83
91 90 89 88 85 84 83 38
85 84 83
85 84 83
123
87 85 84 83
85 84 83 47 41
123 85 84 83 39
123 85 84 83 39
S4E_L8
1
R8909
100K
1% 1/20W MF 201
2
TPA8901
123 86 85
123 85 84 83
87 85 84 83 47
TP-P6
SSD1_S4E3_SWD_UID0 SSD1_S4E3_SWD_UID1 SSD1_S4E3_DROOP_L
IN IN IN
86
IN
86
OUT
IN
IN
BI
OUT
123 86
TP
IN
IN
IN
SSD1_OCARINA_LPB_L SSD_BFH
SSD1_S4E_BOOT2 SSD1_S4E3_SWD_UID0 SSD1_S4E_UART_RX SSD1_S4E3_SWD_UID1 SSD1_S4E3_UART_TX SSD1_OCARINA_PFN SSD1_PCIE_RESET_L
SSD1_SWDIO_UART_D2R SSD1_SWCLK_UART_R2D SSD1_S4E3_JTAG_TDO
1
SSD1_S4E2_JTAG_TDO SSD1_S4E_JTAG_SEL SSD1_S4E3_DROOP_L
86
SSD1_OCARINA_WP_L
86
86
86
B3
EXT_D0/BOOT0
C4
EXT_D1/BOOT1
B5
EXT_D2/BOOT2/SPINAND_SCLK EXT_D3/SWD_UID0/SPINAND_MISO
C6
EXT_D4/UART_RX
B7
EXT_D5/SWD_UID1/SPINAND_MOSI
C8
EXT_D6/UART_TX
B9
EXT_D7/SPF
B11
E8
EXT_NCE/PERST*
D7
EXT_NRE/JTAG_TMS
E6
EXT_NWE/JTAG_TCK
E4
EXT_RNB/JTAG_TDO
D5
EXT_CLE/JTAG_TDI
D9
EXT_ALE/JTAG_SEL
T3
DROOP_N
G2
WP_N
U2
U4
U6
U12
U10
U8
T13
T9
T7
T1
R10
P13
P11
P7
P3
P1
N10
N4
M13
M7
U8900
H23QFG82D6ADS-64GB
LGA
OMIT_TABLE
CRITICAL
VSS
K1
K5
L10
K13
K7
J10
M5
M1
H13
H11
H9
H5
H3
H1
F13
F11
F9
F7
F5
F1
D13
D11
PCI_AVDD_CLK_1
PCI_AVDD_CLK_2
B1
C2
D1
C12
B13
CLK_IN
PCIE_REFCLK_P
PCIE_REFCLK_M PCIE_CLKREQ_N
PCI_RESREF
PCIE_RX0_P
PCIE_RX0_M
PCIE_TX0_P
PCIE_TX0_M
RESET*
TRST*
ZQ_C ZQ_N
A4
A6
A8
A10
A12
SSD1_CLK24M_23
M3
PCIE_CLK100M_SSD1_23_P
K11
GND_VOID=TRUE
J12
PCIE_CLK100M_SSD1_23_N
GND_VOID=TRUE
SSD1_CLKREQ3_L
P5
SSD1_S4E3_PCIE_RESREF
H7
PCIE_SSD1_R2D_P<3>
M11
GND_VOID=TRUE
N12
PCIE_SSD1_R2D_N<3>
GND_VOID=TRUE
PCIE_SSD1_D2R_C_P<3>
R12
GND_VOID=TRUE
T11
PCIE_SSD1_D2R_C_N<3>
GND_VOID=TRUE
SSD1_OCARINA_RESET_L
L4
SSD1_S4E_JTAG_TRST_L
G10
SSD1_S4E3_ZQ_C
K3
SSD1_S4E3_ZQ_L
C10
A2
IN
S4E_L8
1
R8905
300
1% 1/20W MF 201
2
85
1
2
S4E_L8
R8906
100
1% 1/20W MF 201
IN IN
OUT
IN IN
OUT OUT
87 85 84 83
85 84 83
123 85 41
123 85 41
47 41
120 86
120 86
120 86
120 86
S4E_L8
1
R8904
3.01K
1% 1/20W
MF 201
2
C
B
A
JTAG Stuffing Option
SSD1_S4E0_JTAG_TDO
83 84 123
SSD1_S4E1_JTAG_TDO
84 85 123
SSD1_S4E2_JTAG_TDO
85 86 123
JTAG:L5
JTAG:L6
JTAG:L7
0
1 2
0
1 2
0
1 2
R8990
1/20W
MF5%
R8991 R8992
5% 1/20W MF
SSD1_S4E3_JTAG_TDO
0201
0201MF1/20W5%
0201
126 121 87 86 85 84 83
S4E VDD
PP0V9_SSD1
S4E_L8
1
C8910
10UF
20%
6.3V CERM-X6S
2
0402
CRITICAL
123 86
S4E_L8
C8911
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L8
1
C8912
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L8
1
C8913
0.1UF
10% 16V
2
X5R-CERM 0201
VCC CAP
PP2V5_NAND_SSD1
S4E_L8
1
C8948
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
S4E_L8
1
C8949
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L8
1
C8950
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L8
1
C8914
0.1UF
10% 16V
2
X5R-CERM 0201
S4E_L8
1
C8915
0.1UF
10% 16V
2
X5R-CERM 0201
S4E VDDIO
126 121 87 86 85 84 83
126 121 87 86 85 84 83 86
PP1V8_SSD1 PP1V8_SSD1_S4E3_PCI_AVDD_H
126 123 121 87 86 85 84 83
PP1V8_SSD1
S4E_L8
1
C8932
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
S4E_L8
R8900
1 2
1/20W
0201
S4E_L8
R8901
0
5%
1 2
1/20W
MF
0201
0
5%
MF
S4E_L8
C8936
4.3UF
3
86
1
2
1
20%
2
4
4V
CERM
0402-THICKSTNCL
CRITICAL
S4E_L8
1
C8944
1.0UF
20% 10V
2
X5R-CERM 0201-1
1
2
PP1V8_SSD1_S4E3_AVDD18_PLL
S4E_L8
C8946
1.0UF
20% 10V X5R-CERM 0201-1
1
2
S4E_L8
C8937
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
S4E_L8
C8945
0.1UF
10% 16V X5R-CERM 0201
S4E_L8
C8947
0.1UF
10% 16V X5R-CERM 0201
BOM_COST_GROUP=SDD
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
SSD1 S4E 3
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
89 OF 200
SHEET
86 OF 135
B
A
8
67
35 4
2
1
Page 87
Vinafix.com
678
TH1a
TH1b
3 245
1
D
PPBUS_G3H_SSD1_SNS
118
87
SSD1_VR_P2V5_EN
1
C9073
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
R9098
0
1 2
5%
1/20W
MF
0201
1
C9074
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
1
C9080
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
SSD1_VR_P2V5_EN_R
CRITICAL
1
C9081
10UF
20% 25V
2
X5R-CERM 0603
87
SSD1_VR_P2V5_EN_R
87
SSD1_TPS62180_SS
1
C9082
2200PF
10% 25V CER-X7R
2
0201
PLACE_NEAR=U9080.C4:5MM
87
P2V5_SSD1_AGND
U9080
TPS62180
VIN1
A1
VIN1
B1
VIN1
C1 D1
VIN2 VIN2
E1
VIN2
F1
EN VO
E4 D4
SS/TR
AGND C4
BGA
CRITICAL
PGND
PGND
PGND
A3
B3
C3
SM
1 2
PGND D3
XW9000
PGND
PGND F3
E3
SW1 SW1 SW1
SW2 SW2 SW2
PG
FB
A2 B2 C2
D2 E2 F2
A4 F4 B4
P2V5_SW1_TPS62180_SSD1
DIDT=TRUE
SWITCH_NODE=TRUE
P2V5_SW2_TPS62180_SSD1
DIDT=TRUE
SWITCH_NODE=TRUE
87
SSD1_VR_P2V5_PGOOD
SSD1_TPS62180_FB
CRITICAL
L9080
1UH-20%-4.8A-0.032OHM
1 2
1210
CRITICAL
L9081
1UH-20%-4.8A-0.032OHM
1 2
1210
SSD1_TPS62180_FB_R
PP2V5_NAND_SSD1
1
R9088
100K
1% 1/20W MF 201
2
87
P2V5_SSD1_AGND
1
C9085
47PF
5% 25V
2
C0G 0201
126 123 121 87 86 85 84 83
1
R9083
10.2
1% 1/20W MF
2
201
1
R9081
221K
0.1% 1/20W TF 0201
2
1
R9080
475K
0.1% 1/20W TK 0201
2
C9086
1
20UF
20%
2
10V X5R 0402
CRITICAL
C9087
1
20UF
20%
2
10V X5R 0402
CRITICAL
C9088
1
20UF
20%
2
10V X5R 0402
CRITICAL
C9089
1
20UF
20%
2
10V X5R 0402
CRITICAL
CAPDERATE
1
C9090
150UF
20%
6.3V
2
TANT-POLY CASE-B1S-1
CRITICAL
PP2V5_NAND_SSD1
CAPDERATE
1
C9091
150UF
20%
6.3V
2
TANT-POLY CASE-B1S-1
CRITICAL
VOLTAGE=2.5V
CAPDERATE
1
C9092
150UF
20%
6.3V
2
TANT CASE-B-SM
CRITICAL
126 123 121 87 86 85 84 83
D
C
B
PP3V3_G3H_SSD1_SNS
87 118
CRITICAL
PP3V3_G3H_SSD1_SNS
87 118
PLACE C2000-C2002 NEAR OCARINA PINS E7/E8 PLACE C2003-C2005 NEAR OCARINA PINS A7/A8 PLACE C2006 NEAR OCARINA PIN B4
C9000
1
2
1
R9010
100K
1% 1/20W MF 201
2
10UF
20%
6.3V CERM-X6S 0402
1
R9011
100K
1% 1/20W MF 201
2
1
R9012
0
5% 1/20W MF 0201
2
C9001
1
10UF
20%
2
6.3V CERM-X6S 0402
CRITICAL
121 95 92 77 39 38
C9002
1
0.1UF
20%
2
16V X6S-CERM 0201
This sets the address to 0xF0 for STG1
51
51
86 85 84 83
86 85 84 83
121 92 47 38
86 85 84 83
87
86 85 84 83 47
C9003
1
4.7UF
20%
2
6.3V X6S 0402
CRITICAL
C9004
1
4.7UF
20%
2
6.3V X6S 0402
CRITICAL
SSD1_OCARINA_FORCE_EN I2C_SSD1_SCL
I2C_SSD1_SDA SSD1_OCARINA_LPB_L
SSD1_OCARINA_PFN
SSD1_OCARINA_PGOOD SSD_PMU_RESET_L SSD1_VR_P2V5_PGOOD
SSD1_OCARINA_POK2 SSD1_OCARINA_RESET_L PMU_SYS_ALIVE SSD1_VR_P2V5_EN
NC_SSD1_OCARINA_VEN2 SSD1_OCARINA_WP_L
C9005
1
0.1UF
20%
2
16V X6S-CERM 0201
CAPDERATE
1
C9006
150UF
20%
6.3V
2
TANT-POLY CASE-B1S-1
CRITICAL
F3
ATM
D2
ADDR FORCE_EN
E1
G2
I2C_SCL I2C_SDA
G3
LPBN
F4
PFN*
G5
PGOOD
G6
D1
PMIC_RESET*
D3
POK1
F1
POK2
E5
RESET*
F2
SYS_ALIVE VEN1
F5
VEN2
E4
WP*
G4
OCARINA I2C BASE ADDRESS
STG0: F2 STG1: F0
E8
E7
A8
VDD_BUCK0
VDD_BUCK1
VDD_BUCK0
A7B5B4
VDD_MAIN
VDD_BUCK1
VDD_LDO
U9000
D2499A0P0VLAVAG2
WLCSP
CRITICAL
R2081:200K->2.7V, 221K->2.519V NAND VCC
SSD1_OCARINA_VDD_LDO
SSD1_OCARINA_NAND_VCC_DET PP1V8_SSD1
C1
G1
VCC_DET
V_BUF_1.8V
TCAL
VREF
IREF
TDEV1 TDEV2
VR1_DISCHG VR2_DISCHG
BUCK0_FB_DIS BUCK1_FB_DIS
BUCK0_LX0 BUCK0_LX0
BUCK0_LX1 BUCK0_LX1
BUCK1_LX0 BUCK1_LX0
1
C9009
0.1UF
10% 16V
2
X5R-CERM 0201
SSD1_OCARINA_TCAL
A4
SSD1_OCARINA_VREF
B3 B2
SSD1_OCARINA_IREF SSD1_OCARINA_TDEV1
B1 C2
SSD1_OCARINA_TDEV2 PP2V5_NAND_SSD1
A3 A1
NC_SSD1_OCARINA_VR2_DIS
P0V9_SSD1_FB_DIS
D5
P1V8_SSD1_FB_DIS
C5
F8 F7
D8 D7
B8 B7
P0V9_LX0_SSD1
P0V9_LX1_SSD1
P1V8_LX0_SSD1
126 121 87 86 85 84 83
SWITCH_NODE=TRUE DIDT=TRUE
SWITCH_NODE=TRUE DIDT=TRUE
SWITCH_NODE=TRUE DIDT=TRUE
1
C9007
0.22UF
20%
2
6.3V X6S-CERM 0201
TPA9000
1
A
TP-P6
87
87
126 123
L9021
1UH-20%-4.8A-0.032OHM
1 2
CRITICAL
1210
CRITICAL
87
SSD1_OCARINA_TDEV1
1
R9002
100K-1%-0.001A
0201
2
CRITICAL
1
R9005
200K
0.1% 1/20W TF 0201
2
85 84 83 12187 86
0.47UH-20%-6.7A-0.023OHM
1 2
0.47UH-20%-6.7A-0.023OHM
CRITICAL
1 2
1
C9008
2
L9020
1210
L9030
1210
0.1UF
16V
20% X6S-CERM 0201
CRITICAL
1
R9001
18.2K
0.1% 1/20W TK 0201
2
1
R9000
8.06K
0.1% 1/20W TK 0201
2
1
2
CRITICAL
C9030
1
20UF
20%
2
10V X5R 0402
C9020
20UF
20% 10V X5R 0402
C9031
1
20UF
20%
2
10V X5R 0402
CRITICAL
87
1
2
R9020
1 2
C9021
1
20UF
20%
2
10V X5R 0402
CRITICAL
C9032
1
2
CRITICAL
SSD1_OCARINA_TDEV2
1
R9004
100K-1%-0.001A
0201
CRITICAL
0
PLACE_NEAR=C9025.1:7MM
1/20W 5% MF0201
R9003
18.2K
0.1% 1/20W TK 0201
2
R9030
0
1
2
CRITICAL
20UF
20% 10V X5R 0402
1 2
C9022
20UF
20% 10V X5R 0402
C9033
1
20UF
20%
2
10V X5R 0402
CRITICAL
PLACE_NEAR=C9035.1:5MM
1/20W 0201
C9023
1
20UF
20%
2
10V X5R 0402
CRITICAL
C9034
1
20UF
20%
2
10V X5R 0402
CRITICAL
5% MF
C9024
1
20UF
20%
2
10V X5R 0402
CRITICAL
1
2
PP0V9_SSD1
C9025
1
20UF
20%
2
10V X5R 0402
CRITICAL
C9035
20UF
20% 10V X5R 0402
CRITICAL
PP1V8_SSD1
PP0V9_SSD1
1
C9026
20UF
20% 10V
2
X5R 0402
CRITICAL
PP1V8_SSD1
1
C9027
20UF
20% 10V
2
X5R 0402
CRITICAL
126
126
C
126 121 87 86 85 84 83
126 121 87 86 85 84 83
121 87 8685 84 83 87
B
12187 86 85 84 83
A
VSS
VSS
VSS
A6A5B6
VSS
VSS A2
C3C4D6
VSS
VSS
VSS D4
VSS
VSS E6
E2F6E3
VSS
VSS(VSS_BUCK0)
VSS(VSS_BUCK0)
VSS
G8
G7
VSS(VSS_BUCK01)
VSS(VSS_BUCK01)
VSS(VSS_BUCK01) C8C7C6
BOM_COST_GROUP=SDD
SYNC_MASTER=
PAGE TITLE
SSD1 PMIC & VR
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SYNC_DATE=01/17/2019
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
90 OF 200
SHEET
87 OF 135
A
SIZE
D
8
67
35 4
2
1
Page 88
Vinafix.com
678
3 245
1
D
C
126 121 92 91 90 89 88
126 123 121 92 91 90 89
VCC CAP
PP1V8_SSD0
CRITICAL
PP2V5_NAND_SSD0
C9148
1
10UF
20%
2
6.3V CERM-X6S 0402
1
C9132
10UF
20%
2
6.3V CERM-X6S 0402
CRITICAL
C9136
4.3UF
3
C9149
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
120 88
120 88
120 88
S4E0
C9137
1
1
20%
4V
2
4
CERM
0402-THICKSTNCL
CRITICAL
2.2UF
20%
6.3V
2
X5R-CERM 0201
120 88
OUT
OUT
IN
IN
TP_SSD0_S4E0_ANI1_VREF
C9150
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
126 121 92 91 90 89 88
PP0V9_SSD0
SSD0_S4E0_VPP
TP_SSD0_S4E0_ANI0_VREF PP1V8_SSD0_S4E0_AVDD18_PLL
PP1V8_SSD0_S4E0_PCI_AVDD_H PP0V9_SSD0
121
PCIE_SSD0_R2D_P<0>
PCIE_SSD0_R2D_N<0>
PCIE_SSD0_D2R_C_P<0>
PCIE_SSD0_D2R_C_N<0>
1
C9110
10UF
20%
6.3V CERM-X6S
2
0402
CRITICAL
C9146
121
126 121 92 91 90 89 88
1
1.0UF
10V20% X5R-CERM
2
0201-1
C9103
GND_VOID=TRUE GND_VOID=TRUE
C9104
C9101
GND_VOID=TRUE GND_VOID=TRUE
C9102
C9111
1
2.2UF
20%
2
X5R-CERM 0201
C9147
1
0.1UF
16V
10% X5R-CERM
2
0201
1
26.3V
NOSTUFF
1
R9130
0
5% 1/20W MF 0201
2
F3
VPP
R2
R4
VDD_PLL
L12
VCC
G4
E12
D3
P9
T5
K9
N2
VDDIO
J2
E10
E2
R8
R6
L8
VDD
L6
G8
G6
G12J4L2
ANI0_VREF
ANI1_VREF
AVDD18_PLL
J6
N8
J8
PCI_VDD_1
PCI_VDD_2
PCI_AVDD_H
M9
N6
1
C9144
1.0UF
20% 10V
2
X5R-CERM 0201-1
1
C9145
0.1UF
10% 16V
2
X5R-CERM 0201
0.22UF
12
0.22UF
12
GND_VOID=TRUEGND_VOID=TRUE
0.22UF
12
0.22UF
12
GND_VOID=TRUEGND_VOID=TRUE
C9112
2.2UF
20%
6.3V X5R-CERM 0201
R9101
1 2
1/20W
0201
R9199
X5R-CERM 0201 10% 6.3V
X5R-CERM 0201 10% 6.3V
X5R-CERM 0201 6.3V10%
1
C9113
0.1UF
10% 16V X5R-CERM
2
0201
0
5%
MF
0
5%
1 2
1/20W
MF
0201
PCIE_SSD0_R2D_C_P<0>
PCIE_SSD0_R2D_C_N<0>
PCIE_SSD0_D2R_P<0>
PCIE_SSD0_D2R_N<0>
0201X5R-CERM 6.3V10%
1
C9114
0.1UF
10% 16V X5R-CERM
2
0201
1
C9115
0.1UF
10% 16V X5R-CERM
2
0201
IN
IN
OUT
OUT
120 41
120 41
120 41
120 41
PP0V9_SSD0
PP1V8_SSD0
126
126
D
121 92 91 90 89 88
121 92 91 90 89 88
C
B
90 89 88
126 121 92 91
PP1V8_SSD0
1
R9102
47K
1% 1/20W MF 201
2
NOSTUFF
1
R9103
47K
1% 1/20W MF 201
2
92 91 90 89
91 90 89 86 85 84 83 38
91 90 89 88
91 90 89
123
92 91 90 89 88
91 90 89 47 41
123 91 90 89 39
123 91 90 89 39
123 89
TPA9101
123 91 90 89
92 91 90 89 47
123
IN IN IN
IN
OUT IN
IN
BI
OUT
OUT
TP
TP-P6
IN
123 88
IN
SSD0_OCARINA_LPB_L SSD_BFH SSD0_S4E_BOOT2
88
SSD0_S4E0_SWD_UID0 SSD0_S4E_UART_RX
88
SSD0_S4E0_SWD_UID1 SSD0_S4E0_UART_TX SSD0_OCARINA_PFN
SSD0_PCIE_RESET_L SSD0_SWDIO_UART_D2R SSD0_SWCLK_UART_R2D SSD0_S4E0_JTAG_TDO
1
SSD0_S4E0_JTAG_TDI SSD0_S4E_JTAG_SEL SSD0_S4E0_DROOP_L SSD0_OCARINA_WP_L
B3
EXT_D0/BOOT0
C4
EXT_D1/BOOT1
B5
EXT_D2/BOOT2/SPINAND_SCLK EXT_D3/SWD_UID0/SPINAND_MISO
C6
EXT_D4/UART_RX
B7
EXT_D5/SWD_UID1/SPINAND_MOSI
C8
EXT_D6/UART_TX
B9
EXT_D7/SPF
B11
E8
EXT_NCE/PERST*
D7
EXT_NRE/JTAG_TMS
E6
EXT_NWE/JTAG_TCK
E4
EXT_RNB/JTAG_TDO
D5
EXT_CLE/JTAG_TDI
D9
EXT_ALE/JTAG_SEL
T3
DROOP_N
G2
WP_N
U9100
H23QFG82D6ADS-64GB
LGA
OMIT_TABLE
CRITICAL
PCI_AVDD_CLK_1
PCI_AVDD_CLK_2
PCIE_REFCLK_P
PCIE_REFCLK_M PCIE_CLKREQ_N
PCI_RESREF
PCIE_RX0_P
PCIE_RX0_M
PCIE_TX0_P
PCIE_TX0_M
CLK_IN
RESET*
TRST*
ZQ_C ZQ_N
M3 K11
GND_VOID=TRUE
J12
GND_VOID=TRUE
P5 H7 M11
GND_VOID=TRUE
N12
GND_VOID=TRUE
R12
GND_VOID=TRUE
T11
GND_VOID=TRUE
L4
91 90 89
G10 K3
C10
SSD0_CLK24M_01
89
PCIE_CLK100M_SSD0_01_P PCIE_CLK100M_SSD0_01_N
SSD0_CLKREQ0_L
SSD0_S4E0_PCIE_RESREF
PCIE_SSD0_R2D_P<0> PCIE_SSD0_R2D_N<0>
PCIE_SSD0_D2R_C_P<0> PCIE_SSD0_D2R_C_N<0>
SSD0_OCARINA_RESET_L SSD0_S4E_JTAG_TRST_L
SSD0_S4E0_ZQ_C SSD0_S4E0_ZQ_L
R9140
49.9
1 2
IN IN
OUT
1% MF1/20W 201
123 89 41
123 89 41
123 47 41
IN IN
OUT OUT
SSD0_CLK24M
1
120 88
120 88
120 88
120 88
R9104
3.01K
1% 1/20W MF 201
2
IN
90 47
B
IN
92 91 90 89
A
1
R9120
100K
1% 1/20W MF 201
2
1
R9108
100K
1% 1/20W MF 201
2
SSD0_OCARINA_PFN SSD0_S4E0_DROOP_L
SSD0_S4E_BOOT2
SSD0_S4E0_SWD_UID0 SSD0_S4E0_SWD_UID1
1
R9109
100K
1% 1/20W MF 201
2
88
88
PLACE_NEAR=U9100.C10:5mm
92 91 90 89 88
K13
K7
VSS
K5
K1
J10
H13
H11
H9
H5
H3
H1
F13
F11
F9
F7
F5
F1
D13
D11
D1
C12
C2
B13
B1
A12
A10
A8
A6
A4
A2
123 88
T1
T7
U8
U10
U12
91 90 89 88
T13
R10
P13
P11
T9
U2
U4
U6
P7
P3
P1
N10
N4
M13
M7
M5
M1
L10
R9105
1
300
1% 1/20W MF 201
2
R9106
100
1
1% 1/20W MF 201
2
R9100
100K
1
1% 1/20W MF 201
2
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
SSD0 S4E 0
SIZE
D
BOM_COST_GROUP=SDD
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
91 OF 200
SHEET
88 OF 135
8
67
35 4
2
1
Page 89
Vinafix.com
678
3 245
1
S4E1
D
C
92 91 90 88
91 90 88 86 85 84 83 38
91 90 88
91 90 88
123
92 91 90 88
91 90 88 47 41
123 91 90 88 39
123 91 90 88 39
123 90
123 88
123 91 90 88
92 91 90 88 47
IN IN IN
89
IN
89
OUT IN
IN
BI
OUT
OUT
IN
IN
123 89
IN
NOSTUFF
1
R9230
0
5% 1/20W MF 0201
2
SSD0_OCARINA_LPB_L SSD_BFH SSD0_S4E_BOOT2 SSD0_S4E1_SWD_UID0 SSD0_S4E_UART_RX SSD0_S4E1_SWD_UID1 SSD0_S4E1_UART_TX SSD0_OCARINA_PFN SSD0_PCIE_RESET_L
SSD0_SWDIO_UART_D2R SSD0_SWCLK_UART_R2D SSD0_S4E1_JTAG_TDO SSD0_S4E0_JTAG_TDO SSD0_S4E_JTAG_SEL SSD0_S4E1_DROOP_L SSD0_OCARINA_WP_L
126 123 121 92 91 90 89 88
126 121 92 91 90 89 88
B3
EXT_D0/BOOT0
C4
EXT_D1/BOOT1
B5
EXT_D2/BOOT2/SPINAND_SCLK EXT_D3/SWD_UID0/SPINAND_MISO
C6
EXT_D4/UART_RX
B7
EXT_D5/SWD_UID1/SPINAND_MOSI
C8
EXT_D6/UART_TX
B9
EXT_D7/SPF
B11
E8
EXT_NCE/PERST*
D7
EXT_NRE/JTAG_TMS
E6
EXT_NWE/JTAG_TCK
E4
EXT_RNB/JTAG_TDO
D5
EXT_CLE/JTAG_TDI
D9
EXT_ALE/JTAG_SEL
T3
DROOP_N
G2
WP_N
U8
U10
U12
126 121 92 91 90 89 88 126 121 92 91 90 89 88
PP2V5_NAND_SSD0
PP1V8_SSD0 PP0V9_SSD0
TP_SSD0_S4E1_ANI1_VREF TP_SSD0_S4E1_ANI0_VREF
PP0V9_SSD0
PP1V8_SSD0_S4E1_AVDD18_PLL
PP1V8_SSD0_S4E1_PCI_AVDD_H
SSD0_S4E1_VPP
F3
VPP
R2
R4
VDD_PLL
L12
VCC
G4
E12
D3
P9
T5
K9
N2
VDDIO
J2
E10
E2
R8
R6
L8
VDD
L6
G8
G6
G12J4L2
ANI0_VREF
ANI1_VREF
J8
PCI_VDD_2
AVDD18_PLL
U9200
H23QFG82D6ADS-64GB
LGA
OMIT_TABLE
CRITICAL
VSS
F1
F5
F7
U6
U4
U2
T13
T9
T7
T1
R10
P13
P11
P7
P3
P1
N10
N4
M13
M7
M5
M1
L10
K13
K7
K5
K1
J10
H13
H11
H9
H5
H3
H1
F13
F11
F9
D13
J6
N8
PCI_VDD_1
PCI_AVDD_H
PCI_AVDD_CLK_2
D1
C12
D11
N6
M9
PCI_AVDD_CLK_1
PCIE_REFCLK_P
PCIE_REFCLK_M PCIE_CLKREQ_N
PCI_RESREF
PCIE_RX0_P
PCIE_RX0_M
PCIE_TX0_P
PCIE_TX0_M
B1
C2
B13
A12
A10
89
PP0V9_SSD0
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
A2
A4
M3 K11
J12 P5 H7 M11
N12
R12 T11
L4 G10 K3
C10
CLK_IN
RESET*
TRST*
ZQ_C ZQ_N
A6
A8
121
121
89
120 89
120 89
120 89
120 89
126 121 92 91 90 89 88
OUT
OUT
IN
IN
SSD0_CLK24M_01 PCIE_CLK100M_SSD0_01_P
123 88 41
PCIE_CLK100M_SSD0_01_N SSD0_CLKREQ1_L
SSD0_S4E1_PCIE_RESREF PCIE_SSD0_R2D_P<1> PCIE_SSD0_R2D_N<1>
PCIE_SSD0_D2R_C_P<1> PCIE_SSD0_D2R_C_N<1>
SSD0_OCARINA_RESET_L SSD0_S4E_JTAG_TRST_L SSD0_S4E1_ZQ_C SSD0_S4E1_ZQ_L
PCIE_SSD0_R2D_P<1>
PCIE_SSD0_R2D_N<1>
PCIE_SSD0_D2R_C_P<1>
PCIE_SSD0_D2R_C_N<1>
88
IN
123 47 41
120 89
120 89
120 89
120 89
1
R9205
300
1% 1/20W MF 201
2
IN IN
OUT OUT
1
R9206
100
1% 1/20W MF 201
2
C9203
GND_VOID=TRUE
C9204
GND_VOID=TRUE GND_VOID=TRUE
C9201
GND_VOID=TRUE GND_VOID=TRUE
C9202
GND_VOID=TRUE GND_VOID=TRUE
R9204
1
3.01K
1% 1/20W MF 201
2
91 90 88
12
GND_VOID=TRUE
12
12
12
0.22UF
0.22UF
0.22UF
0.22UF
PCIE_SSD0_R2D_C_P<1>
X5R-CERM0201
10%6.3V
PCIE_SSD0_R2D_C_N<1>
10%6.3V X5R-CERM0201
PCIE_SSD0_D2R_P<1>
X5R-CERM 10%6.3V 0201
PCIE_SSD0_D2R_N<1>
02016.3V
IN
10%X5R-CERM
92 91 90 88
IN
IN
OUT
OUT
120 41
120 41
120 41
120 41
D
C
B
92 91 90 89 88
126 121
PP1V8_SSD0
R9202
1
47K
1% 1/20W MF 201
2
1
R9209
100K
1% 1/20W MF 201
2
1
R9208
100K
1% 1/20W MF 201
2
SSD0_S4E1_SWD_UID0
SSD0_S4E1_DROOP_L
SSD0_S4E1_SWD_UID1
89
89
B
S4E VDDIO
S4E VDD
126 121 92 91 90 89 88
123 89
PP0V9_SSD0
1
C9210
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
C9212
C9211
1
2.2UF
20%
6.3V
2 X5R-CERM
X5R-CERM 0201
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
1
C9213
0.1UF
10%
2
16V X5R-CERM 0201
1
C9214
0.1UF
10%
2
16V X5R-CERM 0201
1
C9215
0.1UF
16V
2
10% X5R-CERM 0201
126 121 92 91 90 89 88
126 121 92 91 90 89 88
PP1V8_SSD0
VCC CAP
126 123 121 92 91 90 89 88
PP2V5_NAND_SSD0
PP1V8_SSD0
C9232
1
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
R9200
0
5%
1 2
1/20W
MF
0201
C9236
4.3UF
3
2
4
1
C9244
1.0UF
20%10V
2
X5R-CERM 0201-1
C9237
1
1
20%
4V
CERM
0402-THICKSTNCL
CRITICAL
2.2UF
20%
6.3V
2
0201
PP1V8_SSD0_S4E1_PCI_AVDD_H
1
C9245
0.1UF
10%
16V
2
X5R-CERM 0201
A
8
1
C9248
10UF
20%
2
6.3V CERM-X6S 0402
CRITICAL
67
1
C9249
2.2UF
20%
6.3V
2
X5R-CERM 0201
1
C9250
2.2UF
20%
2
6.3V X5R-CERM 0201
R9201
0
5%
1 2
1/20W
MF
0201
PP1V8_SSD0_S4E1_AVDD18_PLL
C9246
1
1.0UF
20% 10V
2
X5R-CERM 0201-1
C9247
1
0.1UF
10% 16V
2
X5R-CERM 0201
BOM_COST_GROUP=SDD
35 4
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
SSD0 S4E 1
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
92 OF 200
SHEET
89 OF 135
1
A
Page 90
Vinafix.com
678
3 245
1
D
126 123 121 92 91 90 89 88
126 121 92 91 90 89 88
NOSTUFF
1
R9330
0
5% 1/20W MF
2
0201
S4E2
126 121 92 91 90 89 88 126 121 92 91 90 89 88
PP2V5_NAND_SSD0
PP0V9_SSD0
SSD0_S4E2_VPP
PP1V8_SSD0 PP0V9_SSD0
F3
VPP
R2
R4
VDD_PLL
L12
VCC
G4
E12
D3
P9
T5
K9
N2
VDDIO
J2
E10
E2
R8
R6
L8
VDD
L6
G8
G6
G12J4L2
ANI0_VREF
ANI1_VREF
AVDD18_PLL
N8
J8
PCI_VDD_1
PCI_VDD_2
J6
PCI_AVDD_H
120 90
120 90
120 90
120 90
TP_SSD0_S4E2_ANI1_VREF TP_SSD0_S4E2_ANI0_VREF
PP1V8_SSD0_S4E2_AVDD18_PLL PP1V8_SSD0_S4E2_PCI_AVDD_H
PP0V9_SSD0
N6
M9
OUT
OUT
PCIE_SSD0_R2D_N<2>
GND_VOID=TRUE
PCIE_SSD0_D2R_C_P<2>
PCIE_SSD0_R2D_P<2>
IN
GND_VOID=TRUE GND_VOID=TRUE
PCIE_SSD0_D2R_C_N<2>
IN
121
121
126 121 92 91 90 89 88
GND_VOID=TRUE
2
GND_VOID=TRUEGND_VOID=TRUE
GND_VOID=TRUE
2
GND_VOID=TRUE
1
12
1
12
0.22UF
0201 6.3V10% X5R-CERM
0.22UF
0201 10%
0.22UF
0.22UF
0201 X5R-CERM6.3V10%
C9303 C9304 C9301
6.3V10%0201
C9302
X5R-CERM6.3V
X5R-CERM
PCIE_SSD0_R2D_C_P<2>
PCIE_SSD0_R2D_C_N<2>
PCIE_SSD0_D2R_P<2>
PCIE_SSD0_D2R_N<2>
IN
IN
OUT
OUT
120 41
120 41
120 41
120 41
D
C
126 121 92 91 90 89 88
PP1V8_SSD0
R9302
1
47K
1% 1/20W MF 201
2
R9309
1
100K
1% 1/20W MF 201
2
92 91 89 88
91 89 88 86 85 84 83 38
91 89 88
91 89 88
123
92 91 89 88
91 89 88 47 41
123 91 89 88 39
123 91 89 88 39
123 91
123 89
123 91 89 88
92 91 89 88 47
IN IN IN
90
IN
90
OUT
IN
IN
BI
OUT
OUT
IN
IN
123 90
IN
SSD0_OCARINA_LPB_L SSD_BFH SSD0_S4E_BOOT2 SSD0_S4E2_SWD_UID0 SSD0_S4E_UART_RX SSD0_S4E2_SWD_UID1 SSD0_S4E2_UART_TX SSD0_OCARINA_PFN
SSD0_PCIE_RESET_L SSD0_SWDIO_UART_D2R SSD0_SWCLK_UART_R2D SSD0_S4E2_JTAG_TDO SSD0_S4E1_JTAG_TDO SSD0_S4E_JTAG_SEL SSD0_S4E2_DROOP_L SSD0_OCARINA_WP_L
B3
EXT_D0/BOOT0
C4
EXT_D1/BOOT1
B5
EXT_D2/BOOT2/SPINAND_SCLK EXT_D3/SWD_UID0/SPINAND_MISO
C6
EXT_D4/UART_RX
B7
EXT_D5/SWD_UID1/SPINAND_MOSI
C8
EXT_D6/UART_TX
B9
EXT_D7/SPF
B11
E8
EXT_NCE/PERST*
D7
EXT_NRE/JTAG_TMS
E6
EXT_NWE/JTAG_TCK
E4
EXT_RNB/JTAG_TDO
D5
EXT_CLE/JTAG_TDI
D9
EXT_ALE/JTAG_SEL
T3
DROOP_N
G2
WP_N
U2
U4
U6
U12
U10
U8
T13
T9
T7
T1
R10
P13
P11
P7
P3
P1
N10
N4
M13
M7
U9300
H23QFG82D6ADS-64GB
LGA
OMIT_TABLE
CRITICAL
VSS
K1
K5
L10
K13
K7
J10
M5
M1
H13
H11
H9
H5
H3
H1
F13
F11
F9
F7
F5
F1
D13
D11
PCI_AVDD_CLK_1
PCI_AVDD_CLK_2
C2
D1
C12
B13
CLK_IN
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_CLKREQ_N
PCI_RESREF
PCIE_RX0_P
PCIE_RX0_M
PCIE_TX0_P
PCIE_TX0_M
RESET*
TRST*
ZQ_C ZQ_N
A6
A12
A10
A8
B1
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
A2
A4
M3 K11
J12 P5 H7 M11
N12
R12 T11
L4 G10 K3
C10
SSD0_CLK24M_23
91
PCIE_CLK100M_SSD0_23_P PCIE_CLK100M_SSD0_23_N
SSD0_CLKREQ2_L SSD0_S4E2_PCIE_RESREF
PCIE_SSD0_R2D_P<2> PCIE_SSD0_R2D_N<2>
PCIE_SSD0_D2R_C_P<2> PCIE_SSD0_D2R_C_N<2>
SSD0_OCARINA_RESET_L
SSD0_S4E_JTAG_TRST_L SSD0_S4E2_ZQ_C
SSD0_S4E2_ZQ_L
R9340
1 2
1
R9305
300
1% 1/20W MF 201
2
49.9
1/20W 201
1
R9306
100
1% 1/20W MF 201
2
SSD0_CLK24M
MF 1%
IN IN
OUT
IN IN
OUT OUT
IN
123 91 41
123 91 41
123 47 41
120 90
120 90
120 90
120 90
1
R9304
3.01K
1% 1/20W MF 201
2
91 89 88
88 47
C
IN
92 91 89 88
B
1
R9308
100K
1% 1/20W MF 201
2
SSD0_S4E2_SWD_UID1 SSD0_S4E2_DROOP_L
SSD0_S4E2_SWD_UID0
90
123 90
90
126 121 92 91 90 89 88
S4E VDD
PP0V9_SSD0
C9310
1
10UF
20%
6.3V CERM-X6S
2
0402
CRITICAL
C9311
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
VCC CAP
C9312
1
2.2UF
20%
6.3V
2
X5R-CERM 0201
1
C9313
0.1UF
10% 16V
2
X5R-CERM 0201
1
C9314
0.1UF
10% 16V
2
X5R-CERM 0201
1
C9315
0.1UF
10% 16V
2
X5R-CERM 0201
126 121 92 91 90 89 88
126 121 92 91 90 89 88
PP1V8_SSD0
S4E VDDIO
PP1V8_SSD0
1
C9332
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
R9300
0
5%
1 2
1/20W
MF
0201
C9336
4.3UF
3
4
C9337
1
1
20%
4V
2
CERM
0402-THICKSTNCL
CRITICAL
2.2UF
20%
6.3V
2
X5R-CERM 0201
PP1V8_SSD0_S4E2_PCI_AVDD_H
1
C9344
1.0UF
20% 10V X5R-CERM
2
0201-1
1
C9345
0.1UF
10% 16V X5R-CERM
2
0201
B
A
8
126 123 121 92 91 90 89 88
67
PP2V5_NAND_SSD0
1
C9348
10UF
20%
2
6.3V CERM-X6S 0402
CRITICAL
1
C9349
2.2UF
20%
2
X5R-CERM 0201
1
C9350
2.2UF
20%
6.3V
26.3V
X5R-CERM 0201
R9301
0
5%
1 2
1/20W
MF
0201
PP1V8_SSD0_S4E2_AVDD18_PLL
C9346
1
1.0UF
20% 10V X5R-CERM
2
0201-1
C9347
1
0.1UF
10% 16V X5R-CERM
2
0201
BOM_COST_GROUP=SDD
35 4
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
SSD0 S4E 2
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
93 OF 200
SHEET
90 OF 135
1
A
Page 91
Vinafix.com
678
3 245
1
D
126 123 121 92 91 90 89 88
126 121 92 91 90 89 88
NOSTUFF
1
R9430
0
5% 1/20W MF 0201
2
PP2V5_NAND_SSD0
PP0V9_SSD0
SSD0_S4E3_VPP
F3
VPP
R2
R4
VDD_PLL
L12
VCC
G4
S4E3
D3
E12
P9
T5
K9
N2
VDDIO
J2
E10
E2
R8
R6
L8
VDD
L6
G8
G6
PP0V9_SSD0PP1V8_SSD0
G12J4L2
ANI0_VREF
ANI1_VREF
AVDD18_PLL
J6
N8
J8
PCI_VDD_1
PCI_VDD_2
PCI_AVDD_H
126 121 92 91 90 89 88 126 121 92 91 90 89 88
TP_SSD0_S4E3_ANI1_VREF TP_SSD0_S4E3_ANI0_VREF PP1V8_SSD0_S4E3_AVDD18_PLL
PP1V8_SSD0_S4E3_PCI_AVDD_H PP0V9_SSD0
N6
M9
120 91
120 91
120 91
121
121
OUT
OUT
IN
IN
91
91
PCIE_SSD0_R2D_P<3>
PCIE_SSD0_R2D_N<3>
PCIE_SSD0_D2R_C_P<3>
PCIE_SSD0_D2R_C_N<3>
126 121 92 91 90 89 88
C9403
GND_VOID=TRUE GND_VOID=TRUE
6.3V 020110%X5R-CERM
C9404
GND_VOID=TRUE
X5R-CERM
C9401
X5R-CERM 10%
C9402
GND_VOID=TRUE
6.3V
X5R-CERM 10% 0201
12
0.22UF
12
0.22UF
GND_VOID=TRUE
0201
10%6.3V
12
0.22UF
GND_VOID=TRUEGND_VOID=TRUE
02016.3V
12
0.22UF
GND_VOID=TRUE
PCIE_SSD0_R2D_C_P<3>
PCIE_SSD0_R2D_C_N<3>
PCIE_SSD0_D2R_P<3>
PCIE_SSD0_D2R_N<3>
IN
IN
OUT
OUT
120 41
120 41
120 41
120 41
D
C
92 90 89 88
90 89 88 86 85 84 83 38
90 89 88
90 89 88
123
92 90 89 88
90 89 88 47 41
123 90 89 88 39
123 90 89 88 39
TPA9401
123 90 89 88
92 90 89 88 47
123
123 90
IN IN IN
IN
OUT
IN
IN
BI
OUT
TP
TP-P6
IN
IN
123 91
IN
SSD0_OCARINA_LPB_L SSD_BFH
SSD0_S4E_BOOT2
91
SSD0_S4E3_SWD_UID0 SSD0_S4E_UART_RX
91
SSD0_S4E3_SWD_UID1 SSD0_S4E3_UART_TX SSD0_OCARINA_PFN
SSD0_PCIE_RESET_L SSD0_SWDIO_UART_D2R
SSD0_SWCLK_UART_R2D
SSD0_S4E3_JTAG_TDO
1
SSD0_S4E2_JTAG_TDO SSD0_S4E_JTAG_SEL SSD0_S4E3_DROOP_L SSD0_OCARINA_WP_L
B3
EXT_D0/BOOT0
C4
EXT_D1/BOOT1
B5
EXT_D2/BOOT2/SPINAND_SCLK EXT_D3/SWD_UID0/SPINAND_MISO
C6
EXT_D4/UART_RX
B7
EXT_D5/SWD_UID1/SPINAND_MOSI
C8
EXT_D6/UART_TX
B9
EXT_D7/SPF
B11
E8
EXT_NCE/PERST*
D7
EXT_NRE/JTAG_TMS
E6
EXT_NWE/JTAG_TCK
E4
EXT_RNB/JTAG_TDO
D5
EXT_CLE/JTAG_TDI
D9
EXT_ALE/JTAG_SEL
T3
DROOP_N
G2
WP_N
U9400
H23QFG82D6ADS-64GB
LGA
OMIT_TABLE
CRITICAL
PCI_AVDD_CLK_1
PCI_AVDD_CLK_2
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_CLKREQ_N
PCI_RESREF
PCIE_RX0_P
PCIE_RX0_M
PCIE_TX0_P
PCIE_TX0_M
CLK_IN
RESET*
TRST*
M3 K11
GND_VOID=TRUE
J12
GND_VOID=TRUE
P5 H7 M11
GND_VOID=TRUE
N12
GND_VOID=TRUE
R12
GND_VOID=TRUE
T11
GND_VOID=TRUE
L4 G10
SSD0_CLK24M_23 PCIE_CLK100M_SSD0_23_P
PCIE_CLK100M_SSD0_23_N SSD0_CLKREQ3_L
SSD0_S4E3_PCIE_RESREF
PCIE_SSD0_R2D_P<3> PCIE_SSD0_R2D_N<3>
PCIE_SSD0_D2R_C_P<3> PCIE_SSD0_D2R_C_N<3>
SSD0_OCARINA_RESET_L SSD0_S4E_JTAG_TRST_L
IN
IN IN
OUT
IN IN
OUT OUT
90
123 90 41
123 90 41
123 47 41
1
120 91
120 91
2
120 91
120 91
IN
90 89 88
92 90 89 88
R9404
3.01K
1% 1/20W MF 201
C
B
126
90 89 88
121 92 91
PP1V8_SSD0
R9402
1
47K
1% 1/20W MF 201
2
1
R9408
100K
1% 1/20W MF 201
2
1
R9409
100K
1% 1/20W MF 201
2
SSD0_S4E3_SWD_UID0
SSD0_S4E3_SWD_UID1
SSD0_S4E3_DROOP_L
91
91
U12
U10
U8
U6
U4
U2
T13
T9
T7
T1
R10
P13
P11
P7
P3
P1
N10
N4
M13
M7
M5
M1
L10
K13
K7
VSS
K5
K1
J10
H13
H11
H9
H5
H3
H1
F13
F11
F9
F7
F5
F1
D13
D11
D1
C12
C2
B13
B1
A12
A10
A8
ZQ_C ZQ_N
A6
A4
A2
K3 C10
SSD0_S4E3_ZQ_C SSD0_S4E3_ZQ_L
1
R9405
300
1% 1/20W MF 201
2
1
R9406
100
1% 1/20W MF 201
2
B
123 91
S4E VDDIO
126 121 92 91 90 89 88
S4E VDD
PP0V9_SSD0
C9410
1
10UF
20%
6.3V
2 16V
CERM-X6S 0402
CRITICAL
PP2V5_NAND_SSD0
C9413
C9411
1
2.2UF
20%
6.3V
2 6.3V
X5R-CERM 0201
C9412
1
2.2UF
20%
2
X5R-CERM 0201
1
0.1UF
10%
2
X5R-CERM 0201
VCC CAP
C9414
1
0.1UF
10% 16V
2
X5R-CERM 0201
C9415
1
0.1UF
10% 16V
2
X5R-CERM 0201
126 121 92 91 90 89 88
PP1V8_SSD0
126 123 121 92 91 90 89 88
PP1V8_SSD0
CRITICAL
C9432
1
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
R9400
0
5%
1 2
1/20W
MF
0201
C9436
4.3UF
3
2
4
1
C9444
1.0UF
20% 10V
2
X5R-CERM 0201-1
C9437
1
1
4V
CERM
0402-THICKSTNCL
2.2UF
20%
6.3V
220%
X5R-CERM 0201
PP1V8_SSD0_S4E3_PCI_AVDD_H
91 126 121 92 91 90 89 88
1
C9445
0.1UF
10% 16V
2
X5R-CERM 0201
A
8
1
C9448
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
1
C9449
2.2UF
20%
2
6.3V X5R-CERM 0201
67
1
C9450
2.2UF
20%
6.3V
2
X5R-CERM 0201
1
C9451
2.2UF
20%
6.3V
2
X5R-CERM 0201
1
C9452
2.2UF
20%
6.3V
2
X5R-CERM 0201
R9401
0
5%
1 2
1/20W
MF
0201
PP1V8_SSD0_S4E3_AVDD18_PLL
C9446
1
1.0UF
20% 10V X5R-CERM
2
0201-1
C9447
1
0.1UF
10% 16V X5R-CERM
2
0201
91
SYNC_MASTER= SYNC_DATE=01/17/2019
PAGE TITLE
A
SSD0 S4E 3
DRAWING NUMBER
051-04492
Apple Inc.
BOM_COST_GROUP=SDD
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
35 4
2
REVISION
2.15.0
BRANCH
PAGE
94 OF 200
SHEET
91 OF 135
1
SIZE
D
Page 92
Vinafix.com
678
TH0a
TH0b
3 245
1
D
118
PPBUS_G3H_SSD0_SNS
CRITICAL
C9573
1
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
C9574
1
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
C9580
1
10UF
20% 25V
2
X5R-CERM 0603
CRITICAL
C9581
1
10UF
20% 25V
2
X5R-CERM 0603
92
CRITICAL
1
C9583
0.1UF
20% 16V
2
X6S-CERM 0201
1
2
SSD0_VR_P2V5_EN_R SSD0_TPS62180_SS
1
C9582
2200PF
10% 25V CER-X7R
2
0201
P2V5_SSD0_AGND
A1
CRITICAL
C9584
0.1UF
20% 16V X6S-CERM 0201
PLACE_NEAR=U9580.C4:5MM
B1 C1
D1 E1
F1 E4 D4
U9580
TPS62180
CRITICAL
AGND
PGND
A3
1 2
BGA
PGND
B3
SM
PGND
C3
PGND
D3
PGND
E3
PGND
F3
SW1 SW1 SW1
SW2 SW2 SW2
PG
92
FB
VIN1 VIN1 VIN1
VIN2 VIN2 VIN2
EN VO SS/TR
C4
XW9500
A2 B2 C2
D2 E2 F2
A4 F4 B4
CRITICAL
P2V5_SW1_TPS62180_SSD0
DIDT=TRUE
SWITCH_NODE=TRUE
CRITICAL
P2V5_SW2_TPS62180_SSD0
DIDT=TRUE
SWITCH_NODE=TRUE
SSD0_VR_P2V5_PGOOD
SSD0_TPS62180_FB
1
R9588
2
L9580
1UH-20%-4.8A-0.032OHM
1 2
1210
L9581
1UH-20%-4.8A-0.032OHM
1 2
1210
PP2V5_NAND_SSD0
100K
1% 1/20W MF 201
P2V5_SSD0_AGND
92
VOLTAGE=2.5V
1
R9583
10.2
1% 1/20W MF 201
SSD0_TPS62180_FB_R
C9585
1
47PF
5% 25V
2
C0G 0201
2
1
R9580
475K
0.1% 1/20W TK 0201
2
126 123 121 92 91 90 89 88
1
R9581
221K
0.1% 1/20W TF 0201
2
1
C9586
20UF
20% 10V
2
X5R 0402
CRITICAL
1
C9587
20UF
20% 10V
2
X5R 0402
CRITICAL
1
C9588
20UF
20% 10V
2
X5R 0402
CRITICAL
1
C9589
20UF
20% 10V
2
X5R 0402
CRITICAL
1
C9590
150UF
20%
6.3V
2
TANT-POLY CASE-B1S-1
CRITICAL CAPDERATE
1
C9591
150UF
20%
6.3V
2
TANT-POLY CASE-B1S-1
CRITICAL CAPDERATE
PP2V5_NAND_SSD0
1
C9592
150UF
20%
6.3V
2
TANT-POLY CASE-B1S-1
CRITICAL CAPDERATE
126 123 121 92 91 90 89 88
D
C
B
SSD0_VR_P2V5_EN
92
R9598
0
1 2
5%
1/20W
MF
0201
SSD0_VR_P2V5_EN_R
PP3V3_G3H_SSD0_SNS
92 118
PP3V3_G3H_SSD0_SNS
92 118
92
PLACE C2000-C2002 NEAR OCARINA PINS E7/E8 PLACE C2003-C2005 NEAR OCARINA PINS A7/A8 PLACE C2006 NEAR OCARINA PIN B4
PP3V3_G3H_SSD0_SNS
92 118
C9500
1
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
1
R9510
100K
1% 1/20W MF 201
2
C9501
1
10UF
20%
6.3V
2
CERM-X6S 0402
CRITICAL
1
R9506
10K
5% 1/20W MF 201
2
1
R9511
100K
1% 1/20W MF 201
2
121 87 47 38
C9502
1
0.1UF
20% 16V
2
X6S-CERM 0201
This sets the addres to 0xF2 for STG0
C9503
1
4.7UF
20%
6.3V
2
X6S 0402
CRITICAL
C9504
1
4.7UF
20%
6.3V
2
X6S 0402
CRITICAL
SSD0_STG01_ADDR
SSD0_OCARINA_FORCE_EN
I2C_SSD0_SCL
51
I2C_SSD0_SDA
51
91 90 89 88
91 90 89 88
SSD0_OCARINA_LPB_L SSD0_OCARINA_PFN SSD0_OCARINA_PGOOD
SSD_PMU_RESET_L SSD0_VR_P2V5_PGOOD
92
SSD0_OCARINA_POK2
SSD0_OCARINA_RESET_L
121 95
77
PMU_SYS_ALIVE
38 39 87
SSD0_VR_P2V5_EN
92
NC_SSD0_OCARINA_VEN2 SSD0_OCARINA_WP_L
91 90 89 88 47
1
R9512
0
5% 1/20W MF 0201
2
91 90 89 88
C9505
1
0.1UF
20% 16V
2
X6S-CERM 0201
1
2
CRITICAL CAPDERATE
F3
ATM
D2
ADDR
E1
FORCE_EN
G2
I2C_SCL
G3
I2C_SDA
F4
LPBN
G5
PFN*
G6
PGOOD
D1
PMIC_RESET*
D3
POK1
F1
POK2
E5
RESET*
F2
SYS_ALIVE
F5
VEN1
E4
VEN2
G4
WP*
OCARINA I2C BASE ADDRESS
C9506
150UF
20%
6.3V TANT-POLY CASE-B1S-1
STG0: F2 STG1: F0
E8
E7
A8
VDD_BUCK0
VDD_BUCK0
D2499A0P0VLAVAG2
A7B5B4
VDD_BUCK1
VDD_MAIN
VDD_BUCK1
U9500
WLCSP
CRITICAL
G1
VCC_DET
VDD_LDO
SSD0_OCARINA_NAND_VCC_DET
PP1V8_SSD0
C1
V_BUF_1.8V
VR1_DISCHG VR2_DISCHG
BUCK0_FB_DIS BUCK1_FB_DIS
BUCK0_LX0 BUCK0_LX0
BUCK0_LX1 BUCK0_LX1
BUCK1_LX0 BUCK1_LX0
TCAL VREF
IREF
TDEV1 TDEV2
A4 B3
B2 B1
C2
A3 A1
D5 C5
F8 F7
D8 D7
B8 B7
C9509
1
0.1UF
10%
16V
2
X5R-CERM 0201
SSD0_OCARINA_TCAL SSD0_OCARINA_VREF
SSD0_OCARINA_IREF SSD0_OCARINA_TDEV1
SSD0_OCARINA_TDEV2
PP2V5_NAND_SSD0 NC_SSD0_OCARINA_VR2_DIS
P0V9_SSD0_FB_DIS P1V8_SSD0_FB_DIS
P0V9_LX0_SSD0
P0V9_LX1_SSD0
P1V8_LX0_SSD0
SSD0_OCARINA_VDD_LDO
1
C9507
1
TPA9500
126 121 92 91 90 89 88
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
TP-P6
92
92
A
0.22UF
20%
2
6.3V X6S-CERM 0201
SSD0_OCARINA_TDEV1
1
I26
R9502
100K-1%-0.001A
0201
2
CRITICAL
126 123 121 92 91 90 89 88
L9521
CRITICAL
1 2
1210
0.47UH-20%-6.7A-0.023OHM
L9520
1 2
1210
0.47UH-20%-6.7A-0.023OHM
L9530
1 2
1210
CRITICAL
92
1
R9501
18.2K
0.1% 1/20W TK 0201
2
1
R9505
200K
0.1% 1/20W TF 0201
2
1
C9508
0.1UF
20% 16V
2
X6S-CERM 0201
1UH-20%-4.8A-0.032OHM
CRITICAL
1
C9530
20UF
20% 10V X5R
2
0402
CRITICAL
1
C9520
20UF
20% 10V
2
X5R 0402
CRITICAL
1
2
CRITICAL
1
C9521
20UF
20% 10V
2
X5R 0402
CRITICAL
C9531
20UF
20% 10V X5R 0402
1
2
SSD0_OCARINA_TDEV2
1
I22
R9504
100K-1%-0.001A
0201
2
CRITICAL
1
R9500
8.06K
0.1% 1/20W TK 0201
2
1
C9522
20UF
20% 10V
2
X5R 0402
CRITICAL
C9532
20UF
20% 10V X5R 0402
CRITICAL
1
C9533
20UF
20% 10V X5R
2
0402
CRITICAL
1
R9503
18.2K
0.1% 1/20W TK 0201
2
1
C9523
20UF
20% 10V
2
X5R 0402
CRITICAL
1
2
92
R9520
0
1
1/20W
0201
PLACE_NEAR=C9535.1:5MM
2
5%
PLACE_NEAR=C9525.1:5MM
MF
PP0V9_SSD0
1
C9524
20UF
20% 10V
2
X5R 0402
CRITICAL
1
2
PP1V8_SSD0
C9534
20UF
20% 10V X5R 0402
CRITICAL
1
C9535
20UF
20% 10V X5R
2
0402
CRITICAL
PP0V9_SSD0
R9530
0
1 2
5%
1/20W
MF
0201
C9525
20UF
20% 10V X5R 0402
CRITICAL
1
2
CRITICAL
PP1V8_SSD0
1
C9526
20UF
20% 10V X5R 0402
C9527
20UF
20% 10V X5R
2
0402
CRITICAL
126 121 92 91 90 89 88
C
126 121 92 91 90 89 88
126 121
92 91 90 89 88
B
121 92 89 88 91 90
126
A
VSS
VSS
A6A5B6
VSS
A2
VSS
VSS
C3C4D6
VSS
VSS
D4
VSS
E6
VSS
VSS
E2F6E3
VSS
VSS(VSS_BUCK0)
VSS(VSS_BUCK0)
VSS
G8
G7
VSS(VSS_BUCK01)
VSS(VSS_BUCK01)
VSS(VSS_BUCK01)
C8C7C6
SYNC_MASTER=
PAGE TITLE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SSD
IV ALL RIGHTS RESERVED
SSD0 PMIC & VR
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
SYNC_DATE=01/17/2019
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
95 OF 200
SHEET
92 OF 135
A
SIZE
D
8
67
35 4
2
1
Page 93
Vinafix.com
678
3 245
1
D
C
B1 D1
F1 G1 M1
N1
R1
U1
A2
V2
C3
D3
F3 G3 M3
N3
R3
T3
A4
E4
H4
L4 P4 V4 C5 T5
C10
T10 A11 E11
H11
L11 P11 V11
C12 D12
F12
G12
M12
N12 R12
T12 A13 V13 B14
D14
F14
G14
M14
N14 R14 U14
VSS
U9600
TN-ED-03
FBGA
OMIT_TABLE
SYM 2 OF 2
VDD
TN-ED-03-GDDR6-2CHN
VDDQ
VPP
VREFC
A1 V1 H2 L2 E5 P5 E10 P10 H13 L13 A14 V14
C1 E1 H1 L1 P1 T1 J2 K2 C4 F4 N4 T4 B5 U5 B10 U10 C11 F11 N11 T11 J13 K13 C14 E14 H14 L14 P14 T14
A5 V5 A10 V10
K1
1
C9600
1UF
20% 4V
2
CERM-X6S 0201
1
C9605
1UF
20% 4V
2
CERM-X6S 0201
1
C9610
1UF
20% 4V
2
CERM-X6S 0201
1
C9615
1UF
20% 4V
2
CERM-X6S 0201
1
C9620
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9630
1UF
20% 4V
2
CERM-X6S 0201
GPU_VRAM_A_VREFC
1
C9601
1UF
20% 4V
2
CERM-X6S 0201
1
C9606
1UF
20% 4V
2
CERM-X6S 0201
1
C9611
1UF
20% 4V
2
CERM-X6S 0201
1
C9616
1UF
20% 4V
2
CERM-X6S 0201
1
C9621
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9631
1UF
20% 4V
2
CERM-X6S 0201
1
C9602
1UF
20% 4V
2
CERM-X6S 0201
1
C9607
1UF
20% 4V
2
CERM-X6S 0201
1
C9612
1UF
20% 4V
2
CERM-X6S 0201
1
C9617
1UF
20% 4V
2
CERM-X6S 0201
1
C9632
1UF
20% 4V
2
CERM-X6S 0201
1
C9603
1UF
20% 4V
2
CERM-X6S 0201
1
C9608
1UF
20% 4V
2
CERM-X6S 0201
1
C9613
1UF
20% 4V
2
CERM-X6S 0201
1
C9618
1UF
20% 4V
2
CERM-X6S 0201
1
C9633
1UF
20% 4V
2
CERM-X6S 0201
PP1V35_MEMIO_S0_GPU
1
C9604
1UF
20% 4V
2
CERM-X6S 0201
1
C9609
1UF
20% 4V
2
CERM-X6S 0201
1
C9614
1UF
20% 4V
2
CERM-X6S 0201
1
C9619
1UF
20% 4V
2
CERM-X6S 0201
127 126
1
C9639
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9690
1UF
20% 4V
2
CERM-X6S 0201
1
R9690
2.37K
1% 1/20W MF 201
2
1
R9691
5.49K
1% 1/20W MF 201
2
127 126
123 121 115 105 101 99 94 93
B1 D1
F1
G1
M1
U9610
TN-ED-03
FBGA
OMIT_TABLE
SYM 2 OF 2
N1 R1
VDD
U1 A2 V2 C3 D3
F3
G3
TN-ED-03-GDDR6-2CHN
M3
N3 R3
T3 A4 E4 H4
L4 P4 V4 C5
T5
C10
T10
A11
VSS
VDDQ
E11 H11
L11 P11 V11 C12 D12
F12
G12
123121 116 115 105 103 99 98 97 94 93 58
M12
N12 R12
127 126 123 121 115 105
T12
10199 94 93
A13 V13 B14 D14
F14
VPP G14 M14
N14 R14
VREFC
U14
A1 V1 H2 L2 E5 P5 E10 P10 H13 L13 A14 V14
C1 E1 H1 L1 P1 T1 J2 K2 C4 F4 N4 T4 B5 U5 B10 U10 C11 F11 N11 T11 J13 K13 C14 E14 H14 L14 P14 T14
A5 V5 A10 V10
K1
1
C9640
1UF
20% 4V
2
CERM-X6S 0201
1
C9645
1UF
20% 4V
2
CERM-X6S 0201
1
C9650
1UF
20% 4V
2
CERM-X6S 0201
1
C9655
1UF
20% 4V
2
CERM-X6S 0201
1
C9660
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9670
1UF
20% 4V
2
CERM-X6S 0201
GPU_VRAM_B_VREFC
Tie to GND for internal VREFCTie to GND for internal VREFC
1
C9641
1UF
20% 4V
2
CERM-X6S 0201
1
C9646
1UF
20% 4V
2
CERM-X6S 0201
1
C9651
1UF
20% 4V
2
CERM-X6S 0201
1
C9656
1UF
20% 4V
2
CERM-X6S 0201
1
C9661
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9671
1UF
20% 4V
2
CERM-X6S 0201
1
C9642
1UF
20% 4V
2
CERM-X6S 0201
1
C9647
1UF
20% 4V
2
CERM-X6S 0201
1
C9652
1UF
20% 4V
2
CERM-X6S 0201
1
C9657
1UF
20% 4V
2
CERM-X6S 0201
1
C9672
1UF
20% 4V
2
CERM-X6S 0201
1
C9643
1UF
20% 4V
2
CERM-X6S 0201
1
C9648
1UF
20% 4V
2
CERM-X6S 0201
1
C9653
1UF
20% 4V
2
CERM-X6S 0201
1
C9658
1UF
20% 4V
2
CERM-X6S 0201
1
C9673
1UF
20% 4V
2
CERM-X6S 0201
PP1V35_MEMIO_S0_GPU
1
C9644
1UF
20% 4V
2
CERM-X6S 0201
1
C9649
1UF
20% 4V
2
CERM-X6S 0201
1
C9654
1UF
20% 4V
2
CERM-X6S 0201
1
C9659
1UF
20% 4V
2
CERM-X6S 0201
PP1V8_S0_GPUPP1V8_S0_GPU
1
C9679
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9691
1UF
20% 4V
2
CERM-X6S 0201
127 126
PP1V35_MEMIO_S0_GPUPP1V35_MEMIO_S0_GPU
1
R9692
2.37K
1% 1/20W MF 201
2
1
R9693
5.49K
1% 1/20W MF 201
2
127 126 123 121 115 105 101 99 94 93
GDDR6 JTAG SIGNALS HAVE VDDQ LOGIC LEVEL
R9610
0
GPU_VRAM_D_TDO
94
127 126 123 121 115 105 101 99 94 93
123 94 93
123121 116 115 105 103 99 98 97 94 93 58
1 2
5%
R9611
0
1 2
1/20W
5%
R9612
0
1 2
1/20W
5%
R9613
0
1 2
1/20W
5%
R9614
0
1 2
1/20W
5%
PP1V35_MEMIO_S0_GPU
GPU_VRAM_TMS
GPU_VRAM_A_TDIGPU_VRAM_CONN_TDO
MF1/20W
0201
GPU_VRAM_B_TDIGPU_VRAM_A_TDO
MF
0201
GPU_VRAM_C_TDIGPU_VRAM_B_TDO
MF
0201
GPU_VRAM_D_TDIGPU_VRAM_C_TDO
MF
0201
GPU_VRAM_CONN_TDI
MF
0201
1
R9615
100K
5% 1/20W MF 201
2
127 126 123 121 115 105 101 99 94 93
93 123
93 93
94 93
94 94
D
123
C
B
A
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
123 94 93
123 94 93
121 101
IN IN IN IN IN IN IN IN IN IN
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT
IN IN
IN IN
IN
IN
BI BI
IN
GPU_VRAM_A1_CA<0> GPU_VRAM_A1_CA<1> GPU_VRAM_A1_CA<2> GPU_VRAM_A1_CA<3> GPU_VRAM_A1_CA<4> GPU_VRAM_A1_CA<5> GPU_VRAM_A1_CA<6> GPU_VRAM_A1_CA<7> GPU_VRAM_A1_CA<8> GPU_VRAM_A1_CA<9>
GPU_VRAM_A1_DQ<3> GPU_VRAM_A1_DQ<7> GPU_VRAM_A1_DQ<6> GPU_VRAM_A1_DQ<4> GPU_VRAM_A1_DQ<2> GPU_VRAM_A1_DQ<5> GPU_VRAM_A1_DQ<1> GPU_VRAM_A1_DQ<0> GPU_VRAM_A1_DQ<8> GPU_VRAM_A1_DQ<15> GPU_VRAM_A1_DQ<9> GPU_VRAM_A1_DQ<11> GPU_VRAM_A1_DQ<13> GPU_VRAM_A1_DQ<12> GPU_VRAM_A1_DQ<14> GPU_VRAM_A1_DQ<10>
GPU_VRAM_A1_EDC<0> GPU_VRAM_A1_EDC<1>
GPU_VRAM_A1_ZQ GPU_VRAM_A1_WCK_N<0>
GPU_VRAM_A1_WCK_P<0> GPU_VRAM_A1_WCK_N<1>
GPU_VRAM_A1_WCK_P<1> GPU_VRAM_A1_CKE_L GPU_VRAM_A1_CABI GPU_VRAM_A1_DBI<0>
GPU_VRAM_A1_DBI<1> GPU_VRAM_TCK
GPU_VRAM_A_TDI
93
GPU_VRAM_A_TDO
93
GPU_VRAM_TMS GPU_VRAM_A_RST_L
H3 L3
CA0_A
G11 M11
H12 L12
H10 L10
B11 U11 A12 V12 B12 U12 B13 U13 E12 P12 E13 P13
G13
C13 T13
D10 D11
G10 M10
D13 R13
N10
CA1_A
G4 M4
CA2_A CA3_A
H5 L5
CA4_A CA5_A
J12 K12
CA6_A
J11 K11
CA7_A
J4 K4
CA8_A
J3 K3
CA9_A
B4 U4
DQ0_A
A3 V3
DQ1_A
B3 U3
DQ2_A
B2 U2
DQ3_A
E3 P3
DQ4_A
E2 P2
DQ5_A
F2 N2
DQ6_A
G2 M2
DQ7_A DQ8_A DQ9_A DQ10_A DQ11_A DQ12_A DQ13_A
F13 N13
DQ14_A DQ15_A
C2 T2
EDC0_A EDC1_A
J14 K14
ZQ_A
D5
WCK0_C_A
D4
WCK0_T_A WCK1_C_A,NC
WCK1_T_A,NC CKE_A*
J5 K5
CABI_A*
D2 R2
DBI0_A* DBI1_A*
N5
TCK
F10
F5
J1
TDI TDO TMS
RESET*
(IPU, LOGIC H) (TRI-STATE)
(IPU, H=INACTIVE STATE)
U9600
TN-ED-03
FBGA
OMIT_TABLE
SYM 1 OF 2
TN-ED-03-GDDR6-2CHN
DQ IN
SAME BYTE
ARE
SWAPPABLE
WCK0_C_B,NC
WCK0_T_B,NC
CA0_B CA1_B CA2_B CA3_B CA4_B CA5_B CA6_B CA7_B CA8_B CA9_B
DQ0_B DQ1_B DQ2_B DQ3_B DQ4_B DQ5_B DQ6_B DQ7_B DQ8_B
DQ9_B DQ10_B DQ11_B DQ12_B DQ13_B DQ14_B DQ15_B
EDC0_B EDC1_B
ZQ_B
WCK1_C_B
WCK1_T_B
CKE_B*
CABI_B*
DBI0_B* DBI1_B*
CK_C
CK_T
NC NC
M13
R10 R11
R5 R4
K10 J10
G5 M5
GPU_VRAM_A0_CA<0> GPU_VRAM_A0_CA<1> GPU_VRAM_A0_CA<2> GPU_VRAM_A0_CA<3> GPU_VRAM_A0_CA<4> GPU_VRAM_A0_CA<5> GPU_VRAM_B0_CA<5> GPU_VRAM_A0_CA<6> GPU_VRAM_A0_CA<7> GPU_VRAM_A0_CA<8> GPU_VRAM_A0_CA<9>
GPU_VRAM_A0_DQ<0> GPU_VRAM_A0_DQ<1> GPU_VRAM_A0_DQ<3> GPU_VRAM_A0_DQ<2> GPU_VRAM_A0_DQ<5> GPU_VRAM_A0_DQ<4> GPU_VRAM_A0_DQ<6> GPU_VRAM_A0_DQ<7> GPU_VRAM_A0_DQ<15> GPU_VRAM_A0_DQ<14> GPU_VRAM_A0_DQ<12> GPU_VRAM_A0_DQ<13> GPU_VRAM_A0_DQ<10> GPU_VRAM_A0_DQ<11> GPU_VRAM_A0_DQ<9> GPU_VRAM_A0_DQ<8>
GPU_VRAM_A0_EDC<0> GPU_VRAM_A0_EDC<1>
IN IN IN IN IN IN IN IN IN IN
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
GPU_VRAM_A0_ZQ GPU_VRAM_A0_WCK_N<1>
GPU_VRAM_A0_WCK_P<1> GPU_VRAM_A0_WCK_N<0>
GPU_VRAM_A0_WCK_P<0> GPU_VRAM_A0_CKE_L GPU_VRAM_A0_CABI GPU_VRAM_A0_DBI<0>
GPU_VRAM_A0_DBI<1> GPU_VRAM_A_CK_N
GPU_VRAM_A_CK_P
NC NC
101
IN
101
IN
101
IN
101
IN
101
IN
101
IN
101
BI
101
BI
101
IN
101
IN
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
93
101
101
101
101
101
101
101
101
123 94 93
123 94 93
121 101
IN IN IN IN IN IN IN IN IN IN
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT
IN IN
IN IN
IN
IN
BI BI
IN
GPU_VRAM_B0_CA<0> GPU_VRAM_B0_CA<1> GPU_VRAM_B0_CA<2> GPU_VRAM_B0_CA<3> GPU_VRAM_B0_CA<4>
GPU_VRAM_B0_CA<6> GPU_VRAM_B0_CA<7> GPU_VRAM_B0_CA<8> GPU_VRAM_B0_CA<9>
GPU_VRAM_B0_DQ<7> GPU_VRAM_B0_DQ<5> GPU_VRAM_B0_DQ<6> GPU_VRAM_B0_DQ<4>
GPU_VRAM_B0_DQ<3> GPU_VRAM_B0_DQ<1> GPU_VRAM_B0_DQ<0> GPU_VRAM_B0_DQ<14> GPU_VRAM_B0_DQ<15> GPU_VRAM_B0_DQ<13> GPU_VRAM_B0_DQ<12> GPU_VRAM_B0_DQ<10> GPU_VRAM_B0_DQ<11> GPU_VRAM_B0_DQ<8> GPU_VRAM_B0_DQ<9>
GPU_VRAM_B0_EDC<0> GPU_VRAM_B0_EDC<1>
GPU_VRAM_B0_ZQ GPU_VRAM_B0_WCK_N<0>
GPU_VRAM_B0_WCK_P<0> GPU_VRAM_B0_WCK_N<1>
GPU_VRAM_B0_WCK_P<1> GPU_VRAM_B0_CKE_L GPU_VRAM_B0_CABI GPU_VRAM_B0_DBI<0>
GPU_VRAM_B0_DBI<1> GPU_VRAM_TCK
GPU_VRAM_B_TDI
93
GPU_VRAM_B_TDO
93
GPU_VRAM_TMS GPU_VRAM_B_RST_L
H3 L3
CA0_A
G11 M11
H12 L12
H10 L10
B11 U11 A12 V12 B12 U12 B13 U13 E12 P12 E13 P13
G13 M13
C13 T13
D10 D11
G10 M10
D13 R13
N10
CA1_A
G4 M4
CA2_A CA3_A
H5 L5
CA4_A CA5_A
J12 K12
CA6_A
J11 K11
CA7_A
J4 K4
CA8_A
J3 K3
CA9_A
B4 U4
DQ0_A
A3 V3
DQ1_A
B3 U3
DQ2_A
B2 U2
DQ3_A
E3 P3
DQ4_A
E2 P2
DQ5_A
F2 N2
DQ6_A
G2 M2
DQ7_A DQ8_A DQ9_A DQ10_A DQ11_A DQ12_A DQ13_A
F13 N13
DQ14_A DQ15_A
C2 T2
EDC0_A EDC1_A
J14 K14
ZQ_A
D5
WCK0_C_A
D4
WCK0_T_A WCK1_C_A,NC
WCK1_T_A,NC CKE_A*
J5 K5
CABI_A*
D2 R2
DBI0_A* DBI1_A*
N5
TCK
F10
TDI TDO
F5
TMS
J1
RESET*
U9610
TN-ED-03
FBGA
OMIT_TABLE
SYM 1 OF 2
TN-ED-03-GDDR6-2CHN
DQ IN
SAME BYTE
ARE
SWAPPABLE
WCK0_C_B,NC
WCK0_T_B,NC
CA0_B CA1_B CA2_B CA3_B CA4_B CA5_B CA6_B CA7_B CA8_B CA9_B
DQ0_B DQ1_B DQ2_B DQ3_B DQ4_B DQ5_B DQ6_B DQ7_B DQ8_B
DQ9_B DQ10_B DQ11_B DQ12_B DQ13_B DQ14_B DQ15_B
EDC0_B EDC1_B
ZQ_B
WCK1_C_B
WCK1_T_B
CKE_B*
CABI_B*
DBI0_B* DBI1_B*
CK_C
CK_T
NC NC
R10 R11
R5 R4
K10 J10
G5 M5
GPU_VRAM_B1_CA<0> GPU_VRAM_B1_CA<1> GPU_VRAM_B1_CA<2> GPU_VRAM_B1_CA<3> GPU_VRAM_B1_CA<4> GPU_VRAM_B1_CA<5> GPU_VRAM_B1_CA<6> GPU_VRAM_B1_CA<7> GPU_VRAM_B1_CA<8> GPU_VRAM_B1_CA<9>
GPU_VRAM_B1_DQ<6> GPU_VRAM_B1_DQ<7> GPU_VRAM_B1_DQ<4> GPU_VRAM_B1_DQ<2> GPU_VRAM_B1_DQ<3>GPU_VRAM_B0_DQ<2> GPU_VRAM_B1_DQ<0> GPU_VRAM_B1_DQ<1> GPU_VRAM_B1_DQ<5> GPU_VRAM_B1_DQ<15> GPU_VRAM_B1_DQ<13> GPU_VRAM_B1_DQ<11> GPU_VRAM_B1_DQ<14> GPU_VRAM_B1_DQ<8> GPU_VRAM_B1_DQ<10> GPU_VRAM_B1_DQ<9> GPU_VRAM_B1_DQ<12>
GPU_VRAM_B1_EDC<0> GPU_VRAM_B1_EDC<1>
GPU_VRAM_B1_ZQ GPU_VRAM_B1_WCK_N<1>
GPU_VRAM_B1_WCK_P<1> GPU_VRAM_B1_WCK_N<0>
GPU_VRAM_B1_WCK_P<0> GPU_VRAM_B1_CKE_L GPU_VRAM_B1_CABI GPU_VRAM_B1_DBI<0>
GPU_VRAM_B1_DBI<1> GPU_VRAM_B_CK_N
GPU_VRAM_B_CK_P
NC NC
BOM_COST_GROUP=GRAPHICS
IN IN IN IN IN IN IN IN IN IN
OUT OUT
IN IN
IN IN
IN
IN
IN IN
101
101
101
101
101
101
101
101
101
101
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
BI
101
101
93 93 93
101
101
101
101
101
101
101
BI
101
BI
101
101
GPU_VRAM_A0_ZQ
93
GPU_VRAM_A1_ZQ
93
GPU_VRAM_B0_ZQ
93
GPU_VRAM_B1_ZQ
93
1
R9620
120
1% 1/20W MF 201
2
SYNC_MASTER=J187_ALAN
PAGE TITLE
GPU VRAM CHs A, B
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
1
R9621
120
1% 1/20W MF 201
2
1
R9622
120
1% 1/20W MF 201
2
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
96 OF 200
SHEET
93 OF 135
1
R9623
120
1% 1/20W MF 201
2
SYNC_DATE=09/18/2018
SIZE
B
A
D
8
67
35 4
2
1
Page 94
Vinafix.com
678
3 245
1
D
C
B1 D1
F1 G1 M1
N1
R1
U1
A2
V2
C3
D3
F3 G3 M3
N3
R3
T3
A4
E4
H4
L4 P4 V4 C5 T5
C10
T10 A11 E11
H11
L11 P11 V11
C12 D12
F12
G12
M12
N12 R12
T12 A13 V13 B14
D14
F14
G14
M14
N14 R14 U14
VSS
U9700
TN-ED-03
FBGA
OMIT_TABLE
SYM 2 OF 2
VDD
TN-ED-03-GDDR6-2CHN
VDDQ
VPP
VREFC
A1 V1 H2 L2 E5 P5 E10 P10 H13 L13 A14 V14
C1 E1 H1 L1 P1 T1 J2 K2 C4 F4 N4 T4 B5 U5 B10 U10 C11 F11 N11 T11 J13 K13 C14 E14 H14 L14 P14 T14
A5 V5 A10 V10
K1
1
C9700
1UF
20% 4V
2
CERM-X6S 0201
1
C9705
1UF
20% 4V
2
CERM-X6S 0201
1
C9710
1UF
20% 4V
2
CERM-X6S 0201
1
C9715
1UF
20% 4V
2
CERM-X6S 0201
1
C9720
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9730
1UF
20% 4V
2
CERM-X6S 0201
1
C9701
1UF
20% 4V
2
CERM-X6S 0201
1
C9706
1UF
20% 4V
2
CERM-X6S 0201
1
C9711
1UF
20% 4V
2
CERM-X6S 0201
1
C9716
1UF
20% 4V
2
CERM-X6S 0201
1
C9721
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9731
1UF
20% 4V
2
CERM-X6S 0201
1
C9702
1UF
20% 4V
2
CERM-X6S 0201
1
C9707
1UF
20% 4V
2
CERM-X6S 0201
1
C9712
1UF
20% 4V
2
CERM-X6S 0201
1
C9717
1UF
20% 4V
2
CERM-X6S 0201
1
C9732
1UF
20% 4V
2
CERM-X6S 0201
1
C9703
1UF
20% 4V
2
CERM-X6S 0201
1
C9708
1UF
20% 4V
2
CERM-X6S 0201
1
C9713
1UF
20% 4V
2
CERM-X6S 0201
1
C9718
1UF
20% 4V
2
CERM-X6S 0201
1
C9733
1UF
20% 4V
2
CERM-X6S 0201
PP1V35_MEMIO_S0_GPU
1
C9704
1UF
20% 4V
2
CERM-X6S 0201
127 126
123 121 115 105 101 99 94 93
B1 D1
F1
G1
M1
N1 R1
U9710
TN-ED-03
FBGA
OMIT_TABLE
SYM 2 OF 2
VDD
U1 A2
1
C9709
1UF
20% 4V
2
CERM-X6S 0201
V2 C3 D3
F3
G3
TN-ED-03-GDDR6-2CHN
M3
N3 R3
1
C9714
1UF
20% 4V
2
CERM-X6S 0201
T3 A4 E4 H4
L4 P4 V4
1
C9719
1UF
20% 4V
2
CERM-X6S 0201
C5
T5
C10
T10
A11
VSS
VDDQ
E11 H11
L11 P11 V11 C12 D12
F12
G12
PP1V8_S0_GPU PP1V8_S0_GPU
1
C9739
20UF
20%
2.5V
2
X6S-CERM 0402-1
127 126
PP1V35_MEMIO_S0_GPU PP1V35_MEMIO_S0_GPU
1
R9790
2.37K
1% 1/20W MF 201
2
123121 116 115 105 103 99 98 97 94 93 58
M12
N12 R12
127 126 123 121 115 105
T12
10199 94 93 127 126 123 121 115 105 101 99 94 93
A13 V13 B14 D14
F14
VPP
G14
1
C9790
1UF
20% 4V
2
CERM-X6S 0201
1
R9791
5.49K
1% 1/20W MF 201
2
M14
N14 R14 U14
VREFC
A1 V1 H2 L2 E5 P5 E10 P10 H13 L13 A14 V14
C1 E1 H1 L1 P1 T1 J2 K2 C4 F4 N4 T4 B5 U5 B10 U10 C11 F11 N11 T11 J13 K13 C14 E14 H14 L14 P14 T14
A5 V5 A10 V10
K1
PP1V35_MEMIO_S0_GPU
1
C9740
1UF
20% 4V
2
CERM-X6S 0201
1
C9745
1UF
20% 4V
2
CERM-X6S 0201
1
C9750
1UF
20% 4V
2
CERM-X6S 0201
1
C9755
1UF
20% 4V
2
CERM-X6S 0201
1
C9760
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9770
1UF
20% 4V
2
CERM-X6S 0201
GPU_VRAM_D_VREFCGPU_VRAM_C_VREFC
Tie to GND for internal VREFCTie to GND for internal VREFC
1
C9741
1UF
20% 4V
2
CERM-X6S 0201
1
C9746
1UF
20% 4V
2
CERM-X6S 0201
1
C9751
1UF
20% 4V
2
CERM-X6S 0201
1
C9756
1UF
20% 4V
2
CERM-X6S 0201
1
C9761
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9771
1UF
20% 4V
2
CERM-X6S 0201
1
C9742
1UF
20% 4V
2
CERM-X6S 0201
1
C9747
1UF
20% 4V
2
CERM-X6S 0201
1
C9752
1UF
20% 4V
2
CERM-X6S 0201
1
C9757
1UF
20% 4V
2
CERM-X6S 0201
1
C9772
1UF
20% 4V
2
CERM-X6S 0201
1
C9743
1UF
20% 4V
2
CERM-X6S 0201
1
C9748
1UF
20% 4V
2
CERM-X6S 0201
1
C9753
1UF
20% 4V
2
CERM-X6S 0201
1
C9758
1UF
20% 4V
2
CERM-X6S 0201
1
C9773
1UF
20% 4V
2
CERM-X6S 0201
1
C9744
1UF
20% 4V
2
CERM-X6S 0201
1
C9749
1UF
20% 4V
2
CERM-X6S 0201
1
C9754
1UF
20% 4V
2
CERM-X6S 0201
1
C9759
1UF
20% 4V
2
CERM-X6S 0201
1
C9779
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
C9791
1UF
20% 4V
2
CERM-X6S 0201
127 126
1
R9792
2.37K
1% 1/20W MF 201
2
1
R9793
5.49K
1% 1/20W MF 201
2
127 126 123 121 115 105 101 99 94 93
D
123121 116 115 105 103 99 98 97 94 93 58
C
B
A
102
IN
102
IN
102
IN
102
IN
102
IN
102
IN
102
IN
102
IN
102
IN
102
IN
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
OUT
102
OUT
94 94
102
IN
102
IN
102
IN
102
IN
102
IN
102
IN
102
BI
102
BI
123 94 93
123 94 93
121 102
IN
GPU_VRAM_C0_CA<0> GPU_VRAM_C0_CA<1> GPU_VRAM_C0_CA<2> GPU_VRAM_C0_CA<3> GPU_VRAM_C0_CA<4> GPU_VRAM_C0_CA<5> GPU_VRAM_C0_CA<6> GPU_VRAM_C0_CA<7> GPU_VRAM_C0_CA<8> GPU_VRAM_C0_CA<9>
GPU_VRAM_C0_DQ<8> GPU_VRAM_C0_DQ<10> GPU_VRAM_C0_DQ<9> GPU_VRAM_C0_DQ<11> GPU_VRAM_C0_DQ<13> GPU_VRAM_C0_DQ<12> GPU_VRAM_C0_DQ<14> GPU_VRAM_C0_DQ<15> GPU_VRAM_C0_DQ<7> GPU_VRAM_C0_DQ<5> GPU_VRAM_C0_DQ<6> GPU_VRAM_C0_DQ<4> GPU_VRAM_C0_DQ<2> GPU_VRAM_C0_DQ<3> GPU_VRAM_C0_DQ<1> GPU_VRAM_C0_DQ<0>
GPU_VRAM_C0_EDC<1> GPU_VRAM_C0_EDC<0>
GPU_VRAM_C0_ZQ GPU_VRAM_C0_WCK_N<1>
GPU_VRAM_C0_WCK_P<1> GPU_VRAM_C0_WCK_N<0>
GPU_VRAM_C0_WCK_P<0> GPU_VRAM_C0_CKE_L GPU_VRAM_C0_CABI GPU_VRAM_C0_DBI<1>
GPU_VRAM_C0_DBI<0> GPU_VRAM_TCK
GPU_VRAM_C_TDI
93
GPU_VRAM_C_TDO
93
GPU_VRAM_TMS GPU_VRAM_C_RST_L
H3 L3
CA0_A
G11 M11
H12 L12
H10 L10
B11 U11 A12 V12 B12 U12 B13 U13 E12 P12 E13 P13
G13 M13
C13 T13
D10 D11
G10 M10
D13 R13
N10
CA1_A
G4 M4
CA2_A CA3_A
H5 L5
CA4_A CA5_A
J12 K12
CA6_A
J11 K11
CA7_A
J4 K4
CA8_A
J3 K3
CA9_A
B4 U4
DQ0_A
A3 V3
DQ1_A
B3 U3
DQ2_A
B2 U2
DQ3_A
E3 P3
DQ4_A
E2 P2
DQ5_A
F2 N2
DQ6_A
G2
DQ7_A DQ8_A DQ9_A DQ10_A DQ11_A DQ12_A DQ13_A
F13 N13
DQ14_A DQ15_A
C2 T2
EDC0_A EDC1_A
J14 K14
ZQ_A
D5
WCK0_C_A
D4
WCK0_T_A WCK1_C_A,NC
WCK1_T_A,NC CKE_A*
J5 K5
CABI_A*
D2 R2
DBI0_A* DBI1_A*
N5
TCK
F10
TDI TDO
F5
TMS
J1
RESET*
U9700
TN-ED-03
FBGA
OMIT_TABLE
SYM 1 OF 2
TN-ED-03-GDDR6-2CHN
DQ IN
SAME BYTE
ARE
SWAPPABLE
WCK0_C_B,NC
WCK0_T_B,NC
CA0_B CA1_B CA2_B CA3_B CA4_B CA5_B CA6_B CA7_B CA8_B CA9_B
DQ0_B DQ1_B DQ2_B DQ3_B DQ4_B DQ5_B DQ6_B DQ7_B DQ8_B
DQ9_B DQ10_B DQ11_B DQ12_B DQ13_B DQ14_B DQ15_B
EDC0_B EDC1_B
ZQ_B
WCK1_C_B
WCK1_T_B
CKE_B*
CABI_B*
DBI0_B* DBI1_B*
CK_C
CK_T
NC NC
M2
R10 R11
R5 R4
K10 J10
G5 M5
GPU_VRAM_C1_CA<0> GPU_VRAM_C1_CA<1> GPU_VRAM_C1_CA<2> GPU_VRAM_C1_CA<3> GPU_VRAM_C1_CA<4> GPU_VRAM_C1_CA<5> GPU_VRAM_C1_CA<6> GPU_VRAM_C1_CA<7> GPU_VRAM_C1_CA<8> GPU_VRAM_C1_CA<9>
GPU_VRAM_C1_DQ<8> GPU_VRAM_C1_DQ<11> GPU_VRAM_C1_DQ<9> GPU_VRAM_C1_DQ<13> GPU_VRAM_C1_DQ<15> GPU_VRAM_C1_DQ<14> GPU_VRAM_C1_DQ<12> GPU_VRAM_C1_DQ<10> GPU_VRAM_C1_DQ<7> GPU_VRAM_C1_DQ<5> GPU_VRAM_C1_DQ<3> GPU_VRAM_C1_DQ<6> GPU_VRAM_C1_DQ<1> GPU_VRAM_C1_DQ<4> GPU_VRAM_C1_DQ<0> GPU_VRAM_C1_DQ<2>
GPU_VRAM_C1_EDC<1> GPU_VRAM_C1_EDC<0>
GPU_VRAM_C1_ZQ GPU_VRAM_C1_WCK_N<0>
GPU_VRAM_C1_WCK_P<0> GPU_VRAM_C1_WCK_N<1>
GPU_VRAM_C1_WCK_P<1> GPU_VRAM_C1_CKE_L GPU_VRAM_C1_CABI GPU_VRAM_C1_DBI<1>
GPU_VRAM_C1_DBI<0> GPU_VRAM_C_CK_N
GPU_VRAM_C_CK_P
NC NC
IN IN IN IN IN IN IN IN IN IN
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT
IN IN
IN IN
IN
IN
BI BI
IN IN
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
102
123 94 93
123 94 93
121 102
IN IN IN IN IN IN IN IN IN IN
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT
IN IN
IN IN
IN
IN
BI BI
IN
GPU_VRAM_D1_CA<0> GPU_VRAM_D1_CA<1> GPU_VRAM_D1_CA<2> GPU_VRAM_D1_CA<3> GPU_VRAM_D1_CA<4> GPU_VRAM_D1_CA<5> GPU_VRAM_D1_CA<6> GPU_VRAM_D1_CA<7> GPU_VRAM_D1_CA<8> GPU_VRAM_D1_CA<9>
GPU_VRAM_D1_DQ<8> GPU_VRAM_D1_DQ<11> GPU_VRAM_D1_DQ<9> GPU_VRAM_D1_DQ<12> GPU_VRAM_D1_DQ<10> GPU_VRAM_D1_DQ<13> GPU_VRAM_D1_DQ<14> GPU_VRAM_D1_DQ<15> GPU_VRAM_D1_DQ<0> GPU_VRAM_D1_DQ<1> GPU_VRAM_D1_DQ<2> GPU_VRAM_D1_DQ<3> GPU_VRAM_D1_DQ<5> GPU_VRAM_D1_DQ<4> GPU_VRAM_D1_DQ<6> GPU_VRAM_D1_DQ<7>
GPU_VRAM_D1_EDC<1> GPU_VRAM_D1_EDC<0>
GPU_VRAM_D1_ZQ GPU_VRAM_D1_WCK_N<1>
GPU_VRAM_D1_WCK_P<1> GPU_VRAM_D1_WCK_N<0>
GPU_VRAM_D1_WCK_P<0> GPU_VRAM_D1_CKE_L GPU_VRAM_D1_CABI GPU_VRAM_D1_DBI<1>
GPU_VRAM_D1_DBI<0> GPU_VRAM_TCK
GPU_VRAM_D_TDI
93
GPU_VRAM_D_TDO
93
GPU_VRAM_TMS GPU_VRAM_D_RST_L
H3 L3
CA0_A
G11 M11
H12 L12
H10 L10
B11 U11 A12 V12 B12 U12 B13 U13 E12 P12 E13 P13
G13 M13
C13 T13
D10 D11
G10 M10
D13 R13
N10
CA1_A
G4 M4
CA2_A CA3_A
H5 L5
CA4_A CA5_A
J12 K12
CA6_A
J11 K11
CA7_A
J4 K4
CA8_A
J3 K3
CA9_A
B4 U4
DQ0_A
A3 V3
DQ1_A
B3 U3
DQ2_A
B2 U2
DQ3_A
E3 P3
DQ4_A
E2 P2
DQ5_A
F2 N2
DQ6_A
G2 M2
DQ7_A DQ8_A DQ9_A DQ10_A DQ11_A DQ12_A DQ13_A
F13 N13
DQ14_A DQ15_A
C2 T2
EDC0_A EDC1_A
J14 K14
ZQ_A
D5
WCK0_C_A
D4
WCK0_T_A WCK1_C_A,NC
WCK1_T_A,NC CKE_A*
J5 K5
CABI_A*
D2 R2
DBI0_A* DBI1_A*
N5
TCK
F10
TDI TDO
F5
TMS
J1
RESET*
U9710
TN-ED-03
FBGA
OMIT_TABLE
SYM 1 OF 2
TN-ED-03-GDDR6-2CHN
DQ IN
SAME BYTE
ARE
SWAPPABLE
WCK0_C_B,NC
WCK0_T_B,NC
CA0_B CA1_B CA2_B CA3_B CA4_B CA5_B CA6_B CA7_B CA8_B CA9_B
DQ0_B DQ1_B DQ2_B DQ3_B DQ4_B DQ5_B DQ6_B DQ7_B DQ8_B
DQ9_B DQ10_B DQ11_B DQ12_B DQ13_B DQ14_B DQ15_B
EDC0_B EDC1_B
ZQ_B
WCK1_C_B
WCK1_T_B
CKE_B*
CABI_B*
DBI0_B* DBI1_B*
CK_C
CK_T
NC NC
R10 R11
R5 R4
K10 J10
G5 M5
GPU_VRAM_D0_CA<0> GPU_VRAM_D0_CA<1> GPU_VRAM_D0_CA<2> GPU_VRAM_D0_CA<3> GPU_VRAM_D0_CA<4> GPU_VRAM_D0_CA<5> GPU_VRAM_D0_CA<6> GPU_VRAM_D0_CA<7> GPU_VRAM_D0_CA<8> GPU_VRAM_D0_CA<9>
GPU_VRAM_D0_DQ<8> GPU_VRAM_D0_DQ<10> GPU_VRAM_D0_DQ<9> GPU_VRAM_D0_DQ<11> GPU_VRAM_D0_DQ<13> GPU_VRAM_D0_DQ<12> GPU_VRAM_D0_DQ<14> GPU_VRAM_D0_DQ<15> GPU_VRAM_D0_DQ<4> GPU_VRAM_D0_DQ<0> GPU_VRAM_D0_DQ<3> GPU_VRAM_D0_DQ<2> GPU_VRAM_D0_DQ<5> GPU_VRAM_D0_DQ<1> GPU_VRAM_D0_DQ<6> GPU_VRAM_D0_DQ<7>
GPU_VRAM_D0_EDC<1> GPU_VRAM_D0_EDC<0>
GPU_VRAM_D0_ZQ GPU_VRAM_D0_WCK_N<0>
GPU_VRAM_D0_WCK_P<0> GPU_VRAM_D0_WCK_N<1>
GPU_VRAM_D0_WCK_P<1> GPU_VRAM_D0_CKE_L GPU_VRAM_D0_CABI GPU_VRAM_D0_DBI<1>
GPU_VRAM_D0_DBI<0> GPU_VRAM_D_CK_N
GPU_VRAM_D_CK_P
NC NC
BOM_COST_GROUP=GRAPHICS
IN IN IN IN IN IN IN IN IN IN
OUT OUT
IN IN
IN IN
IN
IN
IN IN
102
102
102
102
102
102
102
102
102
102
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
102
BI
GPU_VRAM_C0_ZQ
102
BI
102
BI
102
BI
102
BI
102
102
94 94
102
102
102
102
102
102
102
BI
102
BI
102
102
94
GPU_VRAM_C1_ZQ
94
GPU_VRAM_D0_ZQ
94
GPU_VRAM_D1_ZQ
94
1
R9720
120
1% 1/20W MF 201
2
PAGE TITLE
GPU VRAM CHs C, D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
1
R9721
120
1% 1/20W MF 201
2
1
R9722
120
1% 1/20W MF 201
2
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
97 OF 200
SHEET
94 OF 135
1
R9723
120
1% 1/20W MF 201
2
SYNC_DATE=09/18/2018SYNC_MASTER=J187_ALAN
SIZE
B
A
D
8
67
35 4
2
1
Page 95
Vinafix.com
678
3 245
1
D
C
PP3V3_S5
80 95 115 126
PP1V8_S5
80 95
PP1V8_S5
80 95
R9802
0
1 2
5%
1/20W
MF
0201
R9803
0
1 2
5%
1/20W
MF
0201
39
OUT
51
IN
51
BI
121 95
GMUX GPIO Expander
PP3V3_S5_GPIOX_R
VOLTAGE=3.3V
PP1V8_S5_GPIOX_R
VOLTAGE=1.8V
DISP_GCON_INT_L
I2C_DISP_SCL I2C_DISP_SDA
DISP_GCON_RESET_L
1
R9804
10K
5% 1/20W MF 201
2
NOSTUFF
1
R9805
0
5% 1/20W MF 0201
2
1
R9801
10K
5% 1/20W MF 201
2
NOSTUFF
GMUX_IOEXP_ADDR_SEL
1
C9801
0.1UF
10%
6.3V
2
CERM-X5R 0201
NC NC NC NC
C4 A5 A3
A2 B4
B2 B3 C2 C3
INT* ADDR SCL
SDA RESET*
NC
A1
A4
VDD(P)
VDD(I2C-BUS)
U9801
PCAL6524
VFBGA
I2C Addr: Read: 45h Write: 44h
VSS
A6
1
C9802
0.1UF
10%
6.3V
2
CERM-X5R 0201
P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7
P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7
P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7
B1 D4 C1 D2 D1 E1 D3 F1
E2 F2 E3 F3 F4 E4 F5 E5
F6 E6 D5 D6 C5 C6 B5 B6
PP3V3_S5
80 95 115 126
EG_VR0_PGOOD EG_VR1_PGOOD EG_VR2_PGOOD EG_VR3_PGOOD EG_VR4_PGOOD
DP_INT_HPD_R
USBC_HPD_DET
TP_BKLT_FAULT_L DP_INT_EG_HPD
DP_INT_IG_HPD
EDP_MUXSEL_OVR
EDP_IG_PANEL_PWR EDP_IG_BKLT_EN EG_LCD_PWR_EN EG_BKLT_EN TP_BKLT_BOOST_EN
EG_VR0_EN EG_VR1_EN EG_VR2_EN EG_VR3_EN EG_VR4_EN
EG_RESET_L_BUFF EDP_PANEL_PWR_EN EDP_BKLT_EN
1
C9860
0.1UF
10%
6.3V
2
CERM-X5R 0201
95
95
95
OUT OUT
OUT OUT
OUT OUT
DP 2:1 Analog MUX
PP3V3_S5
80 95 115 126
Do we need to hook this upto G3W???
A2
J4
120 98
120 98
120 98
120 98
120 98
120 98
120 98
120 98 122 82
120 98
120 98
IN IN
IN IN
IN IN
IN IN OUT
BI BI
R9850
IN IN IN IN IN
BI BI
IN IN IN IN
116 95
116 95
116
116
116
95 19
LAST RAIL PGOOD HAS TO BE VR4_PGOOD
116
R9806
200
1 2
5%
98 95
95 15
15
15
98
98
116 95
116 95
116 95
116 95
95 82
95 81
1/20W
MF
201
95 15
122 82
OUT
IN
R9807
100K
1/20W
201
98 95
DP_INT_HPD
LCD_MUX_SEL
1
5% MF
2
DP_INT_EG_HPD
122 95 82
PP3V3_S5
80 95 115 126
4.7K
2.26K
4.7K
1 2
MF 1/20W5%201
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
120 5
R9851
1 2
MF
R9819
1 2
IN IN
IN IN
IN IN
IN IN
BI BI
5% 1/20W201
1%201
1
2
1/20WMF
R9852
100K
5% 1/20W MF 201
DP_INT_EG_ML_P<0> DP_INT_EG_ML_N<0>
DP_INT_EG_ML_P<1> DP_INT_EG_ML_N<1>
DP_INT_EG_ML_P<2> DP_INT_EG_ML_N<2>
DP_INT_EG_ML_P<3> DP_INT_EG_ML_N<3>
DP_INT_EG_AUX_P DP_INT_EG_AUX_N
NC NC
DP_INT_EG_HPD_R
DP_INT_IG_ML_P<0> DP_INT_IG_ML_N<0>
DP_INT_IG_ML_P<1> DP_INT_IG_ML_N<1>
DP_INT_IG_ML_P<2> DP_INT_IG_ML_N<2>
DP_INT_IG_ML_P<3> DP_INT_IG_ML_N<3>
DP_INT_IG_AUX_P DP_INT_IG_AUX_N
NC NC
DP_INT_IG_HPD_RDP_INT_IG_HPD
EDP_MUXSEL_OVR LCD_MUX_EN
B4 A4
B5 A5
B6 A6
A8 A9
H9
J9
H8
J8 J2
B8 B9
D8 D9
E8 E9
F8 F9
H6
J6
H5
J5
H3
A1 B7
DIN1_0+ DIN1_0-
DIN1_1+ DIN1_1-
DIN1_2+ DIN1_2-
DIN1_3+ DIN1_3-
DAUX1+ DAUX1-
DDC_CLK1 DDC_DAT1
HPD_1
DIN2_0+ DIN2_0-
DIN2_1+ DIN2_1-
DIN2_2+ DIN2_2-
DIN2_3+ DIN2_3-
DAUX2+ DAUX2-
DDC_CLK2 DDC_DAT2
HPD_2
VDD
VDD
U9850
CBTL06142EEE
TFBGA
CRITICAL
DOUT_0+
DOUT_0-
DOUT_1+
DOUT_1-
DOUT_2+
IGEG
DOUT_2-
Panel
DOUT_3+
DOUT_3-
AUX+
AUX-
HPDIN
MUXSEL
GPU_SEL XSD*
GND
B3
C8G8H4
MUXSEL is default low. EG is the default option
DDC_AUX_SEL
GND
GND
GND
GND
H7
G2
GND
B2 B1
D2 D1
E2 E1
F2 F1
H2 H1
J1
C2
1
C9850
0.1UF
20%
2
10V
X7R-CERM 0402
EDP_INT_ML_P<0> EDP_INT_ML_N<0>
EDP_INT_ML_P<1> EDP_INT_ML_N<1>
EDP_INT_ML_P<2> EDP_INT_ML_N<2>
EDP_INT_ML_P<3> EDP_INT_ML_N<3>
EDP_INT_AUX_P EDP_INT_AUX_N
DP_INT_HPD
Pulldown is on eDP connector page
1
C9851
0.1UF
20%
2
10V
X7R-CERM 0402
OUT
OUT OUT
OUT OUT
OUT OUT
BI BI
D
122 82
122 82
122 82
122 82
122 82
122 82
122 82
122 82
122 82
C
IN
122 95 82
B
A
R9820 R9821 R9822 R9823 R9824 R9825 R9826 R9827 R9828 R9830 R9832 R9833
47K 47K 47K 47K
47K 100K 100K 100K 100K 100K
47K
47K
1 2
1 2
1 2
1 2
1 2
1 2
1 2 1 2
1 2
1 2
1 2
1 2
U9860
74LVC1G11GW-S500 SOT363
95
116 95
20
IN
5%2011/20W MF
5%2011/20W MF
5%2011/20W MF
5%2011/20W MF
5%2011/20W MF
5%2011/20W MF
5%2011/20W MF
5%2011/20W MF
5%2011/20W MF 5%2011/20W MF
5%2011/20W MF
5%2011/20W MF
EG_VR0_EN EG_VR1_EN EG_VR2_EN EG_VR3_EN EG_VR4_EN
DP_INT_EG_HPD DP_X_SNK0_HPD_EG DP_X_SNK1_HPD_EG DP_T_SNK0_HPD_EG DP_T_SNK1_HPD_EG EDP_PANEL_PWR_EN EDP_BKLT_EN
116 95
116 95
116 95
116 95
116 95
98 95
98 95
98 95
98 95
98 95
95 82
95 81
120 27
120 27
120 107
120 107
116 95 19
IN IN
IN IN
IN
DP_X_SNK0_HPD DP_X_SNK1_HPD
DP_T_SNK0_HPD DP_T_SNK1_HPD
EG_VR4_PGOOD
EG_RESET_L_BUFF
EG_VR0_PGOOD
PLT3V3_RST_L
PP3V3_S5
80 95 115 126
HPD_X_SNK0
2 12
HPD_X_SNK1
3 11
4 10
HPD_T_SNK0
5 9
HPD_T_SNK1
6 8
GPU_RESET_L HPD_DET_ANY
1
A
3
B
6
C
VDD
U9840
SLG4AP41422
STQFN
GND
5
VCC
Y
GND
2
1
C9840
0.1UF
10%
6.3V
2
CERM-X5R 0201
1
HPD_X_SNK0_ISO HPD_X_SNK1_ISO
HPD_T_SNK0_ISO HPD_T_SNK1_ISO
7
4
GPU_RESET_L
1
R9860
100K
5% 1/20W MF 201
2
DP_X_SNK0_HPD_EG DP_X_SNK1_HPD_EG
DP_T_SNK0_HPD_EG DP_T_SNK1_HPD_EG
USBC_HPD_DET
OUT
119
95
OUT OUT
OUT OUT
PP1V8_S5
80 95
98 95
98 95
98 95
98 95
121 92 87 77 39 38
1
1
R9810
100K
5% 1/20W MF 201
2
P1V8S5_VALID
IN
PMU_SYS_ALIVE
C9810
0.1UF
10%
6.3V
2
CERM-X5R 0201
U9810
74LVC1G08GM
6
1
B
2
A
SOT886-COMBO
NC
3
5
NC
DISP_GCON_RESET_L_R
4
Y
SYNC_MASTER=
PAGE TITLE
R9812
0
1 2
5%
1/20W
MF
0201
DISP_GCON_RESET_L
121 95
SYNC_DATE=08/22/2018
EDP Mux
SIZE
Apple Inc.
DRAWING NUMBER
051-04492
REVISION
B
A
D
2.15.0
BRANCH
PAGE
98 OF 200
SHEET
95 OF 135
BOM_COST_GROUP=GRAPHICS
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
67
35 4
2
1
Page 96
Vinafix.com
678
3 245
1
D
C
GPU_VDDCR_GFX_ISNS4_P
104
GPU_VDDCR_GFX_ISNS3_P
104
GPU_VDDCR_GFX_ISNS2_P
104
GPU_VDDCR_GFX_ISNS1_P
104
GPU_VDDCR_GFX_ISNS1_N
104
GPU_VDDCR_GFX_ISNS2_N
104
GPU_VDDCR_GFX_ISNS3_N
104
GPU_VDDCR_GFX_ISNS4_N
104
PP3V3_S0_GPU
96 117
Four Phase Suming Amp
NO_XNET_CONNECTION=1
R9900
R9920
R9921
R9922
R9923
R9924
R9925
R9907
PCC:YES
1 2
1/20W TK
0.1%0201
NO_XNET_CONNECTION=1
PCC:YES
1 2
0.1% 1/20W
NO_XNET_CONNECTION=1
PCC:YES
1 2
0201 0.1%
NO_XNET_CONNECTION=1
1 2
0201
NO_XNET_CONNECTION=1
1 2
NO_XNET_CONNECTION=1
1 2
NO_XNET_CONNECTION=1
1 2
NO_XNET_CONNECTION=1
1 2
0201
1/20W
PCC:YES
PCC:YES
0.1%
PCC:YES
0.1% 1/20W0201
PCC:YES
PCC:YES
0.1% 1/20W TK
2.43K
2.43K
TK0201
2.43K
TK
123
2.43K
TK1/20W0.1%
2.43K
TK1/20W0201
2.43K
TK
2.43K
TK1/20W0201 0.1%
2.43K
Gain xx.xx
GFXGPU_SUM_R_P
GFXGPU_SUM_R_N
123
R9926
1 2
0.1%0201
R9927
1 2
0.1% 1/20W TK0201
PCC:YES
2.43K
1/20W
PCC:YES
2.43K
GFXGPU_SUM_P
TK
GFXGPU_SUM_N
Trip Point Voltage Gen
Footprint supports 353S01042 alternate
U9902
PCC:YES
R9909
2.2
1 2
5%
1/20W
MF
201
PCC:YES
1
C9906
1UF
20%
6.3V
2
X6S-CERM 0201
PP3V3_VREF_PCC
VOLTAGE=3.3V
REF3312AIRSE
UQFN-COMBO
PCC:YES
5
IN
GND
4
OUT
NC0 NC1
NC2
NC3 NC4
8
1
NC
2
NC
3
NC
6
NC
7
NC
PP3V3_S0_GPU
96 117
PCC:YES
0.1%
1/20W
TF
0201
1
2
NO_XNET_CONNECTION=1
R9928
221K
VOLTAGE=1.25V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
PP1V25_VREF_PCC
R9929
1 2
PCC:YES
1
C9907
1UF
20%
6.3V
2
X6S-CERM 0201
3
2
221K
0.1%
1/20W
TF
0201
7
V+
U9900
OPA388
VSSOP
PCC:YES
IN+
IN-
V-
4
PCC:YES NO_XNET_CONNECTION=1
PCC:YES
R9910
3.32K
1 2
0.1%
1/20W
0201
OUT
NC0 NC1 NC2
6
1 5 8
TP9900
A
MF
NC NC NC
TP-P6
PCC:YES
BYPASS=U9900.7::7MM
1
C9901
0.1UF
10%
6.3V
2
X6S 0201
PCC_GFXGPU_SUM
1
GPU_PCC_COMP_NEG
GPU_PCC_COMP_POS
PCC:YES
1
R9912
15.2K
0.1% 1/20W TK 0201
2
R9905
1/20W05%
PCC:YES
1 2
1
2
TP9901
A
MF0201
NOSTUFF
C9909
1000PF
5%
25V
C0G 0201
1
TP-P6
GPU GFX Current Sense (IG0C)
EDP: 135A, 0.7-1.075V OPAMP GAIN: 1X
CALPE: AMUX-A2
PP3V3_S0_GPU
96 117
LOADISNS
R9901
0
12
GPU_VDDCR_GFX_IMON
103
5%
1/20W
MF
0201
NOSTUFF
1
C9911
2.2UF
20%
6.3V
2
X5R-CERM 0201
LOADISNS
R9902
NOSTUFF
PP3V3_S0_GPU
PCC:YES
C9908
1
0.1UF
10%
6.3V
2
X6S 0201
BYPASS=U9901.5::5MM
PCC:YES
U9901
4
-
3
+
5
VCC
GND
2
TLV3201AIDCK
SC70
1
PCC:YES
301K
R9906
1 2
1/20W 0.1%
0201
96 117
TK
PVDDCRGFXGPU_IMON_R
PVDDCRGFXGPU_IMON_FB
1
10K
0.1%
1/20W
MF
0201-1
2
1
+
3
-
R9903
1 2
1/20W
0201
LOADISNS
U9903
52
NCS2003XV53T2G
SOT553
VCC
VSS
4
0
5% MF
ADC INPUT: 1.209VIMON ICCMAX: 1.209V
BYPASS=U9903.5::5MM
1
C9910
0.1UF
10%
6.3V
2
X7R 0201
ISNS_GPUGFX_IOUT
PP3V3_S0_GPU
1
R9908
10K
5% 1/20W MF 201
2
ALWAYS STUFF ME COMPARATOR IS PUSH PULL BUT MAY BE UNSTUFFED
PCC flag to GPU
NOSTUFF
1
C9905
0.22UF
20%
6.3V
2
X6S-CERM 0201
LOADISNS
LOADISNS
R9904
4.53K
1 2
1%
1/20W
MF
201
96 117
Active LOW
GPU_PCC_ALERT_L
1
TP-P6
A
TP9902
PLACE_NEAR=U7800.A14:5MM
PMU_GPU_GFX_ISENSE
PLACE_NEAR=U7800.A14:5MM
LOADISNS
1
C9904
2.2UF
20%
6.3V
2
X5R-CERM 0201
GND_CALPE_AVSS
98
OUT
OUT
D
123 59
123 96 76 58 55 54 53
C
B
A
GPU SOC Current Sense (IG1C)
EDP: 15A, 0.7-1.075V OPAMP GAIN = 1X IMON ICCMAX = 1.185V ADC INPUT = 1.185V
PP3V3_S0_GPU
CALPE: AMUX-A4
GPU_VDDCR_SOC_IMON PVDDCRSOCGPU_IMON_R
103
PLACE_NEAR=UA600.33:5mm
R9954
0
12
5%
1/20W
MF
0201
LOADISNS
R9955
LOADISNS
96 117
PVDDCRSOCGPU_IMON_FB
1
10K
0.1%
1/20W
MF
0201-1
2
1
+
3
-
R9957
0
1 2
5%
1/20W
MF
0201
LOADISNS
U9950
52
NCS2003XV53T2G
SOT553
VCC
VSS
4
BYPASS=U9950.5::5MM
1
C9950
0.1UF
10%
6.3V
X7R
2
0201
ISNS_GPU_SOC_IOUT
GPU MEM VDDCI Current Sense (IG2C)
EDP: 15A, 0.85V OPAMP GAIN = 3X IMON ICCMAX = 1.185V ADC INPUT = 3.555V
PP3V3_S0_GPU
96 117
EADC2: CH1
1
PVDDCIMEMGPU_IMON
105
PLACE_NEAR=UA800.3:5MM
R9990
0
12
PVDDCIMEMGPU_IMON_R
5%
1/20W
MF
0201
LOADISNS
R9991
LOADISNS
10K
0.1%
1/20W
MF
0201-1
PVDDCIMEMGPU_IMON_FB
1
2
52
1
+
VCC
3
VSS
-
R9992
20K
1 2
1%
1/20W
MF
201
LOADISNS
LOADISNS
U9990
NCS2003XV53T2G
SOT553
4
ISNS_GPUMVDDCI_IOUT
2
LOADISNS
LOADISNS
BYPASS=U9990.5::5MM
C9900
0.1UF
10%
6.3V
X7R 0201
LOADISNS
R9994
45.3K
1 2
1%
1/20W
MF
201
R9959
4.53K
1 2
1%
1/20W
MF
LOADISNS
201
LOADISNS
PLACE_NEAR=U7800.C14:5MM
PMU_GPU_SOC_ISENSE
1
C9959
2.2UF
20%
6.3V
2
X5R-CERM 0201
GND_CALPE_AVSS
PLACE_NEAR=U5710.1:5mm
EADC2_GPU_MEM_VDDCI_ISENSE
PLACE_NEAR=U5710.1:5mm
LOADISNS
C9994
1
2.2UF
20%
2
6.3V
X5R 0201
GND_EADC2_COM
OUT
PLACE_NEAR=U7800.C14:5MM
OUT
123 96 58 56 55 54
Comparator
PCC_EVENT
1
R9915
100K
5%
1/20W
MF
201
2
123 59
Tying off H9M signal
OUT
39
B
GPU MEM VDDIO Current Sense (IG6C)
EDP: 26.5A, 1.35V
ADC INPUT: 3.624VIMON ICCMAX: 1.208VOPAMP GAIN: 3X
EADC2: CH3
PP3V3_S0_GPU
96 117
123 96 76 58 55 54 53
PLACE_NEAR=UA800.11:5MM
LOADISNS
PVDDIOMEMGPU_IMON
105
R9964
0
12
5%
1/20W
MF
0201
LOADISNS
PVDDIOMEMGPU_IMON_R
PVDDIOMEMGPU_IMON_FB
10K
0.1%
1/20W
MF
1
2
R9965
0201-1
LOADISNS
1
+
3
-
R9967
20K
1 2
1%
1/20W
MF
201
U9960
52
NCS2003XV53T2G
SOT553
VCC
VSS
4
GPUVDDIOMEM_ISUM_OUT
LOADISNS
123 56
BOM_COST_GROUP=GRAPHICS
BYPASS=U9960.5::5MM
LOADISNS
1
C9970
0.1UF
10%
6.3V
2
X7R 0201
R9969
45.3K
1 2
LOADISNS
1%
1/20W
MF
201
PLACE_NEAR=U5710.1:15MM
EADC2_GPU_MEM_VDDIO_ISENSE
1
C9969
2.2UF
20%
6.3V
2
X5R-CERM 0201
GND_EADC2_COM
SYNC_MASTER=J780
PAGE TITLE
GPU PCC / Sensors
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
LOADISNS
PLACE_NEAR=U5710.1:15MM
OUT
123 96 58 56 55 54
DRAWING NUMBER
123 56
051-04492
REVISION
2.15.0
BRANCH
PAGE
99 OF 200
SHEET
96 OF 135
SYNC_DATE=08/22/2018
SIZE
D
A
8
67
35 4
2
1
Page 97
Vinafix.com
678
3 245
1
D
C
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
CA000 CA001
6.3V
0201 X5R-CERM
10%
CA002
6.3V
10% 0201
CA003
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
PEG_GPU_R2D_C_P<0> PEG_GPU_R2D_C_N<0>
PEG_GPU_R2D_C_P<1> PEG_GPU_R2D_C_N<1>
PEG_GPU_R2D_C_P<2> PEG_GPU_R2D_C_N<2>
PEG_GPU_R2D_C_P<3> PEG_GPU_R2D_C_N<3>
PEG_GPU_R2D_C_P<4> PEG_GPU_R2D_C_N<4>
PEG_GPU_R2D_C_P<5> PEG_GPU_R2D_C_N<5>
PEG_GPU_R2D_C_P<6> PEG_GPU_R2D_C_N<6>
6.3V
CA004
6.3V
10% 0201
CA005
6.3V X5R-CERM10% 0201
CA006
6.3V
10% 0201 X5R-CERM
CA007
6.3V 0201
CA008
10%
CA009
10%
CA010
6.3V 10%
02016.3V
0201
CA011
IN IN
PEG_GPU_R2D_C_P<7> PEG_GPU_R2D_C_N<7>
10%
6.3V 0201
CA012
10%6.3V 0201
CA013
0201 X5R-CERM6.3V
10%
CA014
020110%6.3V
CA015
6.3V
020110% X5R-CERM
12
0.22UF
X5R-CERM02016.3V 10%
GND_VOID=TRUE
12
0.22UF
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
X5R-CERM10% 0201
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
GND_VOID=TRUE
12
0.22UF
GND_VOID=TRUE
12
0.22UF
X5R-CERM10%
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
X5R-CERM6.3V 0201
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
GND_VOID=TRUE
120 119
120 119
19
IN IN
BI
123
PEG_GPU_R2D_P<0> PEG_GPU_R2D_N<0>
PEG_GPU_R2D_P<1> PEG_GPU_R2D_N<1>
PEG_GPU_R2D_P<2> PEG_GPU_R2D_N<2>
PEG_GPU_R2D_P<3> PEG_GPU_R2D_N<3>
PEG_GPU_R2D_P<4> PEG_GPU_R2D_N<4>
PEG_GPU_R2D_P<5> PEG_GPU_R2D_N<5>
PEG_GPU_R2D_P<6> PEG_GPU_R2D_N<6>
PEG_GPU_R2D_P<7> PEG_GPU_R2D_N<7>
EG_PEG_CLK100M_P EG_PEG_CLK100M_N
GPU_CLKREQ_L
GPU_RESET_R_L
AR15 AP15
AN16
AM16
AR17 AP17
AN18
AM18
AR19 AP19
AN20
AM20
AR21 AP21
AN22
AM22
AN14
AM14
AP13 AN12
PCIE_RX0P PCIE_RX0N
PCIE_RX1P PCIE_RX1N
PCIE_RX2P PCIE_RX2N
PCIE_RX3P PCIE_RX3N
PCIE_RX4P PCIE_RX4N
PCIE_RX5P PCIE_RX5N
PCIE_RX6P PCIE_RX6N
PCIE_RX7P PCIE_RX7N
PCIE_REFCLKP PCIE_REFCLKN
CLKREQ* PERST*
UA000
NAVI14
BGA
SYM 1 OF 12
OMIT_TABLE
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
AJ14 AH14
AL15 AK15
AJ16 AH16
AL17 AK17
AJ18 AH18
AL19 AK19
AJ20 AH20
AL21 AK21
PEG_GPU_D2R_C_P<0>
120
PEG_GPU_D2R_C_N<0>
120
PEG_GPU_D2R_C_P<1>
120
PEG_GPU_D2R_C_N<1>
120
PEG_GPU_D2R_C_P<2>
120
PEG_GPU_D2R_C_N<2>
120
PEG_GPU_D2R_C_P<3>
120
PEG_GPU_D2R_C_N<3>
120
PEG_GPU_D2R_C_P<4>
120
PEG_GPU_D2R_C_N<4>
120
PEG_GPU_D2R_C_P<5>
120
PEG_GPU_D2R_C_N<5>
120
PEG_GPU_D2R_C_P<6>
120
PEG_GPU_D2R_C_N<6>
120
PEG_GPU_D2R_C_P<7>
120
PEG_GPU_D2R_C_N<7>
120
CA016 CA017
CA018
6.3V 10%
CA019 CA020
6.3V 10% 0201
CA021 CA022
10% X5R-CERM0201
6.3V
CA023 CA024
10%6.3V
CA025 CA026
6.3V 10% 0201
CA027 CA028
6.3V 10% 0201
CA029
6.3V 10% 0201
CA030
6.3V 10% 0201
CA031
6.3V 10% X5R-CERM0201
020110%6.3V
020110%6.3V X5R-CERM
0201
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
X5R-CERM6.3V 10% 0201
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
X5R-CERM6.3V 10% 0201
GND_VOID=TRUE
12
0.22UF
GND_VOID=TRUE
12
0.22UF
X5R-CERM6.3V 10% 0201
GND_VOID=TRUE
12
0.22UF
X5R-CERM0201
GND_VOID=TRUE
12
0.22UF
X5R-CERM6.3V 10% 0201
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
X5R-CERM6.3V 10% 0201
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
X5R-CERM
GND_VOID=TRUE
12
0.22UF
GND_VOID=TRUE
PEG_GPU_D2R_P<0> PEG_GPU_D2R_N<0>
PEG_GPU_D2R_P<1> PEG_GPU_D2R_N<1>
PEG_GPU_D2R_P<2> PEG_GPU_D2R_N<2>
PEG_GPU_D2R_P<3> PEG_GPU_D2R_N<3>
PEG_GPU_D2R_P<4> PEG_GPU_D2R_N<4>
PEG_GPU_D2R_P<5> PEG_GPU_D2R_N<5>
PEG_GPU_D2R_P<6> PEG_GPU_D2R_N<6>
PEG_GPU_D2R_P<7> PEG_GPU_D2R_N<7>
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
120 119
D
C
B
PP3V3_S0_GPU
97 98 99 116 117
1
RA018
10K
5% 1/20W MF 201
2
1
RA019
10K
5% 1/20W MF 201
2
NOSTUFF
121 119 116 115 46
1
RA020
10K
5% 1/20W MF 201
2
1
RA021
10K
5% 1/20W MF 201
2
NOSTUFF
PP3V3_S0_GPU
97 98 99 116 117
IN
1
RA022
10K
5% 1/20W MF 201
2
NOSTUFF
1
RA023
10K
5% 1/20W MF 201
2
GPU_RESET_L
TP-P5
TPA000 TPA001
TP-P5
47 46
TP-P5
TPA002 TPA003
TP-P5
1
RA014
100K
5% 1/20W MF 201
2
RA002
1 2
A A
OUT
A A
116
IN
116
IN
116
IN
116
IN
116
IN
116
IN
116
IN
116
IN
0
5%
1/20W
MF
0201
1
TP_GPU_A1_DETECT
1
TP_GPU_ALERT_L GPU_GFX_OVERTEMP
1
TP_GPU_BAMACO_EN
1
TP_GPU_PX_EN
GPU_OSC_GAIN0 GPU_OSC_GAIN1 GPU_OSC_GAIN2
GPU_PINSTRAP_0 GPU_PINSTRAP_1 GPU_PINSTRAP_2 GPU_PINSTRAP_3 GPU_PINSTRAP_4 GPU_PINSTRAP_5 GPU_PINSTRAP_6 GPU_PINSTRAP_7
GPU_PROCHOT_L
GPU_PWRBRK_L
NC NC
NC NC
B2
AJ22
AR29 AH22
AR26
AN29 AP29
AN9
AP9
AR9
AJ5
AJ4 AG6 AG5
AF7 AF5 AF4
AF8 AN27 AP30
AR30
A1_DETECT ALERT*
CTF BAMACO_EN
PX_EN
FANIN FANOUT
OSC_GAIN0 OSC_GAIN1 OSC_GAIN2
PINSTRAP_0 PINSTRAP_1 PINSTRAP_2 PINSTRAP_3 PINSTRAP_4 PINSTRAP_5 PINSTRAP_6 PINSTRAP_7
PROCHOT* PUMPIN
PUMPOUT PWRBRK*
Oscillator
Gain
UA000
NAVI14
BGA
SYM 3 OF 12
OMIT_TABLE
USB_OBS
USB_OCP0
USB_PD_INTERRUPT
(Unused)
Port A USB
USBC0_RXP1/USB_0_RXP0/TXCAP_DPA3P
USBC0_RXN1/USB_0_RXN0/TXCAM_DPA3N
USBC0_TXP1/USB_0_TXP0/TX0P_DPA2P
USBC0_TXN1/USB_0_TXN0/TX0M_DPA2N
Pinstraps
DisplayPort A
(Unused)
USB-PD I2C
USB_VAUX_PRESENT
USB20_DP0
USB20_DM0
USB20_TXRTUNE
USBC0_RXP2/TX2P_DPA0P
USBC0_RXN2/TX2M_DPA0N
USBC0_TXP2/TX1P_DPA1P
USBC0_TXN2/TX1M_DPA1N
USBPD_I2C_MASTER_SCL
USBPD_I2C_MASTER_SDA
USBPD_I2C_SLAVE_SCL
USBPD_I2C_SLAVE_SDA
XTRIG6 XTRIG7
AG8 AR3 AN6 AM5 AL1
AL2 AM3 AF1
AF2 AG2
AG3 AJ2
AJ1 AK3
AK2 AR5
AP5 AP4
AN4 AC9
AD8AK13
GPU_USB_OBS
GPU_USB_OCP0
GPU_USB_PD_INTERRUPT
GPU_USB_VAUX_PRESENT
NC NC
NC
DP_X_SNK0_ML_C_P<3> DP_X_SNK0_ML_C_N<3>
DP_X_SNK0_ML_C_P<2> DP_X_SNK0_ML_C_N<2>
DP_X_SNK0_ML_C_P<0> DP_X_SNK0_ML_C_N<0>
DP_X_SNK0_ML_C_P<1> DP_X_SNK0_ML_C_N<1>
OUT OUT
OUT OUT
OUT OUT
OUT OUT
GPU_USBPD_I2C_MASTER_SCL GPU_USBPD_I2C_MASTER_SDA
GPU_USBPD_I2C_SLAVE_SCL GPU_USBPD_I2C_SLAVE_SDA
GPU_XTRIG7
GPU_XTRIG6
PP3V3_S0_GPU
1
RA003
10K
5% 1/20W MF 201
2
1
RA000
10K
5% 1/20W MF 201
2
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
1
RA011
10K
5% 1/20W MF 201
2
1
RA004
10K
5% 1/20W MF 201
2
1
RA001
10K
5% 1/20W MF 201
2
1
RA010
10K
5% 1/20W MF 201
2
1
RA013
10K
5% 1/20W MF 201
2
97 98 99 116 117
PP3V3_S0_GPU
1
RA012
10K
5% 1/20W MF 201
2
97 98 99 116 117
1
RA006
2.2K
5% 1/20W MF 201
2
NOSTUFF
PP1V8_S0_GPU
1
RA007
2.2K
5% 1/20W MF 201
2
NOSTUFF
127 126 123
121 116 115 105 103 99 98 97 94 93 58
B
A
1
RA009
0
5% 1/20W MF 0201
2
GPU_PS_EN
AH9
97 98 99 116 117
PS_EN
PP3V3_S0_GPU
1
RA008
10K
5% 1/20W MF 201
2
PP1V8_S0_GPU
1
CA033
0.1UF
10% 16V
6
2
NC
NC
3
UA001
74LVC1G04S500
SOT891
2
X5R-CERM 0201
4
15
GFX_SELF_THROTTLE_1V8
NCNC
127 126 123
OUT
119 39
121 116 115 105 103 99 98 97 94 93 58
BOM_COST_GROUP=GRAPHICS
SYNC_MASTER=SEAN
PAGE TITLE
SYNC_DATE=08/22/2018
A
GPU Navi14 PCIe / DP A / Misc
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
100 OF 200
SHEET
97 OF 135
8
67
35 4
2
1
Page 98
Vinafix.com
D
C
B
A
123
97 98 99 116 117
98
98
OUT
121 116 115 105 103 99 98 97 94 93 58
119 39
121 116 115 105 103 99 98 97 94 93 58
123 115
123 115
123 115
123 115
123 115
123 115
TPA108
115
TPA109 TPA110 TPA111 TPA112 TPA113
GPU_JTAG_TRST_L GPU_JTAG_TDI GPU_JTAG_TCK GPU_JTAG_TMS GPU_JTAG_TDO GPU_JTAG_TESTEN
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
GFX_THROTTLE_1V8_L
IN
1
GPU_DBREQ_L
PLACE_SIDE=BOTTOM
1
PLACE_SIDE=BOTTOM
1
PLACE_SIDE=BOTTOM
1
PLACE_SIDE=BOTTOM
1
PLACE_SIDE=BOTTOM
1
PLACE_SIDE=BOTTOM
127 126 123
127 126 123
PP3V3_S0_GPU
1
RA130
10K
5% 1/20W MF 201
2
GPU_ROM_SCLK
GPU_ROM_CS_L
GPU_ROM_WP_L
1
RA133
10K
5% 1/20W MF 201
2
NOSTUFF
121 116 115 105 103 99 98 97 94 93 58
SVI2 VR Bus 0:
Main: VDDCR_GFX 2nd: VDDCR_SOC
SVI2 VR Bus 1:
Main: VDDIO_MEM 2nd: VDDCI_MEM
PP1V8_S0_GPU
RA113
100K
1%
1/20W
MF
201
1
2
1
VCCA VCCB
UA160
SLSV1T34AMU
2 4
UDFN
CRITICAL
5
NC
NC
GND
3
PP1V8_S0_GPU
1K
5%
1/20W
MF
201
RA146
1
2
1/20W
RA141
NOSTUFF
1
1K
5% MF
201
2
127 126 123
RA140
121 116 115 105 103 99 98 97 94 93 58
1K
5%
1/20W
MF
201
1
2
PP1V8_S0_GPU
GPU Boot ROM
1
RA131
10K
5% 1/20W MF 201
2
GPU_ROM_HOLD_L
1
RA132
10K
5% 1/20W MF 201
2
6 1
3
7
UA130
8MBIT-3.0V
W25Q80DVUXIE
CLK CS* WP*(IO2) HOLD*(IO3)
OMIT_TABLE
GND EPAD
4
PP3V3_S0_GPU
6
BA
RA142
1K
5%
1/20W
MF
201
NOSTUFF
RA147
CA150
1.0UF
20%
6.3V
X5R
0201-1
8
VCC
USON
9
1
2
1/20W
201
1
2
DI(IO0)
DO(IO1)
127 126 123
TPA114 TPA115 TPA116 TPA117
103
105
103
105
103
IN
105
IN
98
98
98
RA143
1K
5%
1/20W
MF
201
NOSTUFF
1
1K
5% MF
2
RA150
3.3
1 2
5%
1/20W
MF
201
1
CA134
0.1UF
2
5
GPU_ROM_MOSI
2
GPU_ROM_MISO_R
678
CA100
0.1UF
0201
1 2
10%
GPU_PLLCHARZ1_H_C GPU_PLLCHARZ1_L_C
RA101
51.1
1%
1/20W
MF
201
1
2
1
RA100
51.1
1% 1/20W MF 201
2
0201
CA101
PP1V8_S0_GPU
1
RA120
10K
5% 1/20W MF 201
1
A A A A
1 1 1
TP-P5 TP-P5 TP-P5 TP-P5
2
1
RA121
10K
5% 1/20W MF 201
2
1
RA122
10K
5% 1/20W MF 201
2
1
RA123
10K
5% 1/20W MF 201
2
TPA119
TPA104
OUT OUT OUT OUT
GPU_GPIO_SVC0 GPU_GPIO_SVC1 GPU_GPIO_SVD0
GPU_GPIO_SVD1
97 98 99 116 117
***Series R Values TBD***
RA107 RA108 RA109 RA110
33 33
33
1 2 1 2 1 2 1 2
5% 1/20W 201MF 5% 201 5% 1/20W33MF 201 5% 201MF1/20W
MF1/20W
TPA105
TPA100 TPA101 TPA102 TPA103
PVDDCOREGPU_VRHOT_L PVDDMEMGPU_VRHOT_L GPU_VRHOT_BOTH_L GPU_ROM_SCLK GPU_ROM_MOSI
GPU_ROM_CS_L
1
2
RA144
5%
33
1 2
MF
1/20W
1/20W
MF
1 2
33
5%
201
201
RA148
PP1V8_GPU_OSC
VOLTAGE=1.8
1
CA151
0.1UF
10%
6.3V
2
CERM-X5R 0201
10%
6.3V
CERM-X5R 0201
98
PLACE_NEAR=UA130.2:5mm
GPU_ROM_MISO
98
GPU_ROM_MOSI
98
GPU_ROM_SCLK
98
GPU_ROM_CS_L
98
RA106 RA105 RA102 RA103
RA104
51 117
PP3V3_S0_GPU
1
RA145
1K
5% 1/20W MF 201
2
NOSTUFF
1
CA140
0.01UF
10% 10V
2
X5R-CERM 0201
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1200
1
CA152
0.1UF
10%
6.3V
2
CERM-X5R 0201
RA134
33
1 2
5%
1/20W
MF
201
1
TP-P5
1
TP-P5
1
TP-P5
1
TP-P5
1 2
0
1 2
0
1 2 1 2
33
1 2
51
IN
51
BI
1
RA152
4.7K
5% 1/20W MF 201
2
GPU_OSC_EN
GPU_ROM_MISO
A
TPA130
A
TPA131
A
TPA132
A
TPA133
1
RA111
4.7K
5% 1/20W MF 201
2
5% 1/20W
98
0201MF5% 1/20W 0201MF
201MF5%331/20W
PLACE_NEAR=UA000.P5:5mm
2011/20W MF5%
PLACE_NEAR=UA000.P7:5mm
MF1/20W332015%
PLACE_NEAR=UA000.P4:5mm
TPA107
1
RA112
4.7K
5% 1/20W MF 201
2
4
VDD
TPA122 TPA120
TPA106
YA150
100MHZ-10PPM-15PF-1.8V
2.5X2.0-SM
STANDBY
GND
OUT
2
TP-P5
TP-P5
TP-P5
16V
X5R-CERM X5R-CERM
16V
10%
1 2
0.1UF
A A A A
120
31
95
OUT
A
TP-P5
A
TP-P5
A
TP-P5
103
IN
105
IN
1
TP-P5
1
TP-P5
1
TP-P5
1
TP-P5
96
IN
98
116
IN
116
IN
116
IN
A
116
IN
116
IN
A A
116
IN
A
TP-P5
95
IN
95
IN
95
IN
95
IN
95
IN
TPA118
A
TP-P5
1
RA129
10K
5% 1/20W MF 201
2
GPU_PLLCHARZ1_H GPU_PLLCHARZ1_L
EG_BKLT_EN
1
TP_EG_BKLT_PWM
GPU_BP_0 GPU_BP_1 GPU_BP_2 GPU_BP_3
1
GPU_WAKE_L
>>Reserved
1
GPU_ANALOGIO
GPU_GPIO_SVC0_R GPU_GPIO_SVC1_R GPU_GPIO_SVD0_R GPU_GPIO_SVD1_R GPU_GPIO_SVT0 GPU_GPIO_SVT1
TP_GPU_GPIO0 TP_GPU_GPIO1 TP_GPU_GPIO2 TP_GPU_GPIO3 GPU_PCC_ALERT_L GFX_THROTTLE_L
GPU_ROM_SCLK_R GPU_ROM_MOSI_R GPU_ROM_MISO GPU_ROM_CS_L_R GPU_PINSTRAP_GPIO11 GPU_PINSTRAP_GPIO12 GPU_PINSTRAP_GPIO13
1
TP_GPU_GPIO14 GPU_PINSTRAP_GPIO15 GPU_PINSTRAP_GPIO16
1
TP_GPU_GPIO17
1
TP_GPU_GPIO18 GPU_PINSTRAP_GPIO19
1
TP_GPU_GPIO20
GPU_SMB_CLK GPU_SMB_DAT
GPU_JTAG_TRST_R_L
GPU_DBREQ_R_L
DP_T_SNK1_HPD_EG DP_T_SNK0_HPD_EG DP_X_SNK1_HPD_EG DP_X_SNK0_HPD_EG DP_INT_EG_HPD
GPU_XTALIN
1
GPU_TS_A
121
NC NC
NC NC
NC NC
NC NC
NC
AP12 AR12
AP11 AN11
AJ6
AK5
AL4 AL5
AR13
AB8 AD5
AE6 AD7 AE8 AD4 AE5
U9
W6
AN25 AP25
N5 N6 N8 R6 R5 T8 T7 P5 P7 N4 P4 T4 U8 T5 R8 U5 U6 V4 V8 V7 V5
AN10 AP10
J1
G3
J2
G2
F1 F2
M4
AB7
W8
Y4
Y5 AB9 AC8
W5
AP7 AR7
AP27 AR27
AH23
PLLCHARZ1_H PLLCHARZ1_L
BL_ENABLE BL_PWM_DIM
BP_0 BP_1 BP_2 BP_3
WAKE* ANALOGIO GPIO_SVC0
GPIO_SVC1 GPIO_SVD0 GPIO_SVD1 GPIO_SVT0 GPIO_SVT1
SWAPLOCKA SWAPLOCKB
SCL SDA
GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7_ROMSCK GPIO_8_ROMSI GPIO_9_ROMSO GPIO_10_ROMCSB GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15
GPIO_17 GPIO_18 GPIO_19 GPIO_20
SMBCLK SMBDAT
TRST* TDI TCK TMS TDO TESTEN DBREQ*
GENERICA GENERICB GENERICC_HPD2 GENERICD_HPD3 GENERICE_HPD4 GENERICF_HPD5 HPD1
XTALIN XTALOUT
DPLUS DMINUS
TS_A
UA000
NAVI14
BGA
SYM 2 OF 12
OMIT_TABLE
Port A on PCIe page
VR SVI2
DisplayPort D DisplayPort C DisplayPort B
GPIOs
DisplayPort E
SMBus
JTAG Debug
Hot Plug Detect
DisplayPort
DisplayPort Aux Channels
TXCBP_DPB3P
TXCBM_DPB3N
TX0P_DPB2P
TX0M_DPB2N
TX1P_DPB1P
TX1M_DPB1N
TX2P_DPB0P
TX2M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
TX0P_DPD2P
TX0M_DPD2N
TX1P_DPD1P
TX1M_DPD1N
TX2P_DPD0P
TX2M_DPD0N
TXCEP_DPE3P
TXCEM_DPE3N
TX0P_DPE2P
TX0M_DPE2N
TX1P_DPE1P
TX1M_DPE1N
TX2P_DPE0P
TX2M_DPE0N
DIGONGPIO_16
TEMPIN
TEMPINRETURN
TEST6
TEST_PG
TEST_PG_BACO
TEST_PG_S5P
GENLK_CLK
GENLK_VSYNC
DDCAUX1P
DDCAUX1N
DP EDP A
DDCAUX2P
DP D
DDCAUX2N
DDCAUX3P
DDCAUX3N
DDCAUX4P
DDCAUX4N
DP B DP C
DDCAUX5P
DDCAUX5N
DDCVGACLK
DDCVGADATA
RSVD0 RSVD1 RSVD2
AB2 AB1
AC3 AC2
AD2 AD1
AE3 AE2
V2 V1
W3 W2
Y2 Y1
AA3 AA2
P2 P1
R3 R2
T2 T1
U3 U2
K2 K1
L3 L2
M2 M1
N3 N2
AR11 AL23
AK23
AL13 AK7 AJ9
AK10 W9
Y9 Y7
Y8 AA8
AA9 AA5
AA6 AB4
AB5 AC5
AC6 AN26
AP26 AH10
AJ11 AL24
3 245
DP_X_SNK1_ML_C_P<3> DP_X_SNK1_ML_C_N<3>
DP_X_SNK1_ML_C_P<2> DP_X_SNK1_ML_C_N<2>
DP_X_SNK1_ML_C_P<1> DP_X_SNK1_ML_C_N<1>
DP_X_SNK1_ML_C_P<0> DP_X_SNK1_ML_C_N<0>
DP_T_SNK0_ML_C_P<3> DP_T_SNK0_ML_C_N<3>
DP_T_SNK0_ML_C_P<2> DP_T_SNK0_ML_C_N<2>
DP_T_SNK0_ML_C_P<1> DP_T_SNK0_ML_C_N<1>
DP_T_SNK0_ML_C_P<0> DP_T_SNK0_ML_C_N<0>
DP_T_SNK1_ML_C_P<3> DP_T_SNK1_ML_C_N<3>
DP_T_SNK1_ML_C_P<2> DP_T_SNK1_ML_C_N<2>
DP_T_SNK1_ML_C_P<1> DP_T_SNK1_ML_C_N<1>
DP_T_SNK1_ML_C_P<0> DP_T_SNK1_ML_C_N<0>
DP_INT_EG_ML_P<3> DP_INT_EG_ML_N<3>
DP_INT_EG_ML_P<2> DP_INT_EG_ML_N<2>
DP_INT_EG_ML_P<1> DP_INT_EG_ML_N<1>
DP_INT_EG_ML_P<0> DP_INT_EG_ML_N<0>
EG_LCD_PWR_EN
NC NC
GPU_TEST6 GPU_TEST_PG GPU_TEST_PG_BACO GPU_TEST_PG_S5P
NC NC
DP_INT_EG_AUX_P DP_INT_EG_AUX_N
DP_T_SNK1_AUXCH_C_P DP_T_SNK1_AUXCH_C_N
DP_T_SNK0_AUXCH_C_P DP_T_SNK0_AUXCH_C_N
DP_X_SNK1_AUXCH_C_P DP_X_SNK1_AUXCH_C_N
DP_X_SNK0_AUXCH_C_P DP_X_SNK0_AUXCH_C_N
NC NC
NC NC NC
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
BI BI
BI BI
BI BI
BI BI
BI BI
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 27
120 107
120 107
120 107
120 107
120 107
120 107
120 107
120 107
120 107
120 107
120 107
120 107
120 107
120 107
120 107
120 107
120 95
120 95
120 95
120 95
120 95
120 95
120 95
120 95
1
120 95
120 95
120 107
120 107
120 107
120 107
120 27
120 27
120 27
120 27
2
BOM_COST_GROUP=GRAPHICS
95
OUT
RA160
10K
5% 1/20W MF 201
1
1
2
122 113 109
SYNC_MASTER=
PAGE TITLE
1
RA162
1K
5% 1/20W MF 201
2
RA161
0
5% 1/20W MF 0201
Tieing off Ridge GPIOs Both SNK0 and SNK1 shown as always available
122 29
122 29
122 109
IN
BI
IN
BI
1
RA163
1K
5% 1/20W MF 201
2
PP3V3_S0SW_TBT_T_SNS
118
PP3V3_S0SW_TBT_X_SNS
118
TBT_X_HDMI_DDC_CLK TBT_X_HDMI_DDC_DATA TBT_T_HDMI_DDC_CLK TBT_T_HDMI_DDC_DATA
PP1V8_S0_GPU
1
RA164
1K
5% 1/20W MF 201
2
1
RA165
100K
1% 1/20W MF 201
2
1
RA167
100K
1% 1/20W MF 201
2
1
RA166
100K
1% 1/20W MF 201
2
1
RA168
100K
1% 1/20W MF 201
2
127 126 123 121 116
GPU Navi14 DP / GPIO / Debug
DRAWING NUMBER
051-04492
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
REVISION
2.15.0
BRANCH
PAGE
101 OF 200
SHEET
98 OF 135
115 105 103 99 98 97 94 93 58
SIZE
D
SYNC_DATE=08/22/2018
D
C
B
A
8
67
35 4
2
1
Page 99
Vinafix.com
678
3 245
1
D
C
B
A
100 99 58
123 121 104
126
PPGFX_S0_GPU
N11 N13 N15 N17 N19 N21 N23 P12 P14 P16 P18 P20 P22 R11 R13 R15 R17 R19 R21 R23
T12 T14 T16 T18 T20
T22 U11 U13 U15 U17 U19 U21 U23 V12 V14 V16 V18 V20 V22
W11 W13 W15 W17 W19 W21 W23
Y12 Y14 Y16 Y18 Y20 Y22
AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB12 AB14 AB16 AB18 AB20 AB22 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD12 AD14 AD16 AD18 AD20 AD22 AE11 AE13 AE15 AE17 AE19 AE21 AE23
VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX VDDCR_GFX
UA000
NAVI14
BGA
SYM 8 OF 12
OMIT_TABLE
VDDCI_MEM VDDCI_MEM VDDCI_MEM VDDCI_MEM VDDCI_MEM VDDCI_MEM VDDCI_MEM VDDCI_MEM VDDCI_MEM VDDCI_MEM VDDCI_MEM
VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM VDDIO_MEM
VDDIO_18_S5
VDDIO_33
VDDIO_33_S5
VDD_075 VDD_075 VDD_075 VDD_075
VDD_18 VDD_18 VDD_18
VDD_18_S5P VDD_33_S5P
VDDCR_075_S5
VDDCR_075_S5P
VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC VDDCR_SOC
VDDCR_SOC FB_VDDCR_SOC FB_VDDCR_GFX
FB_VDDIO_MEM
FB_VDDCI_MEM
FB_VSS_A FB_VSS_B
DPB_ZVSS DPC_ZVSS DPD_ZVSS
DPE_ZVSS
PCIE_ZVSS
USB_ZVSS
M9 M14 M16 M18 M20 M22 P24 T24 V24 Y24 AB24
L7 L11 L13 L15 L17 L19 L21 L23 L25 N25 R25 U25 W25 AA25 AC25 AE25
AM7 AL12
AL11 AM23
AP23 AP24 AR24
AC10 AD9 AE10 AL9
AL10 AN24
AM24 AF10
AF12 AF14 AF16 AF18 AF20 AF22 AF24 AG11 AG13 AG15 AG17 AG19 AG21 AG23
AJ12 AH12 N9 P9
AH11 N10
V9 T9 R9 P8 AR23 AL6
PP0V85_MEMCI_S0_GPU
CA208
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA211
1
1UF
20%
2
4V
CERM-X6S 0201
PP1V35_MEMIO_S0_GPU
CA22B
1
1UF
20%
4V
2
CERM-X6S 0201
CA21B
1
20UF
20%
2
2.5V
X6S-CERM 0402-1
PLACE_NEAR=UA000.AM23:5mm
1
CA2B2
1UF
20%
2
4V
CERM-X6S 0201
CA2B1
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
GPU_VDDCR_SOC_FB GPU_VDDCR_GFX_FB GPU_VDDIO_MEM_FB GPU_VDDCI_MEM_FB
GPU_VDDCR_RTN GPU_VDD_MEM_RTN
GPU_DPB_ZVSS
GPU_DPC_ZVSS
GPU_DPD_ZVSS
GPU_DPE_ZVSS
GPU_PCIE_ZVSS
GPU_DPA_ZVSS
CA209
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA212
1
1UF
20%
2
4V
CERM-X6S 0201
CA22C
1
1UF
20%
4V
2
CERM-X6S 0201
CA21C
1
20UF
20%
2
2.5V
X6S-CERM 0402-1
1
CA259
1UF
20%
2
4V
CERM-X6S 0201
CA207
1
1.0UF
20%
2
6.3V
X5R 0201-1
1
CA2A9
1UF
20%
2
4V
CERM-X6S 0201
CA2A8
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
RA201
200
1% 1/20W MF 201
2
PLACE_NEAR=UA000.V9:5mm
1
2
1
2
1
2
1
2
PP3V3_S0_GPU
1
2
1
2
1
2
1
2
1
2
PLACE_NEAR=UA000.T9:5mm
126 121 115 105 99
CA20B
20UF
20%
2.5V
X6S-CERM 0402-1
CA213
1UF
20%
4V
CERM-X6S 0201
CA22D
1UF
20%
4V
CERM-X6S 0201
CA21D
20UF
20%
2.5V
X6S-CERM 0402-1
CA25A
1UF
20%
4V
CERM-X6S 0201
CA24C
1UF
20%
4V
CERM-X6S 0201
CA2A6
1UF
20%
4V
CERM-X6S 0201
CA2A7
20UF
20%
2.5V
X6S-CERM 0402-1
OUT
OUT
OUT
OUT
OUT OUT
RA202
200
1% 1/20W MF 201
CA20D
CA20C
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA214
1
1UF
20%
2
4V
CERM-X6S 0201
127 126 123 121 115 105 101 99 94 93
CA22E
1
1UF
20%
4V
2
CERM-X6S 0201
CA21E
1
20UF
20%
2
2.5V
X6S-CERM 0402-1
97 98 116 117
CA24D
1
1UF
20%
2
4V
CERM-X6S 0201
1
CA2A5
1UF
20%
2
4V
CERM-X6S 0201
CA2A4
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
103 99
Route VDDCR_FB nets with VDDCR_RTN
103 99
Route VDD_MEM_FB nets with VDD_MEM_RTN
105 99
105 99
103 99
105 99
1
RA203
200
1% 1/20W MF 201
2
PLACE_NEAR=UA000.R9:5mm
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA215
1
1UF
20%
2
4V
CERM-X6S 0201
CA22F
1
1UF
20%
4V
2
CERM-X6S 0201
CA21F
1
20UF
20%
2
2.5V
X6S-CERM 0402-1
CA24E
1
1UF
20%
2
4V
CERM-X6S 0201
1
CA2A0
1UF
20%
2
4V
CERM-X6S 0201
CA299
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
RA204
200
1% 1/20W MF 201
2
PLACE_NEAR=UA000.P8:5mm
CA20E
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA216
1
1UF
20%
2
4V
CERM-X6S 0201
CA230
1
1UF
20%
4V
2
CERM-X6S 0201
CA220
1
20UF
20%
2
2.5V
X6S-CERM 0402-1
CA29D
1
10UF
20%
6.3V
2
CER-X6S 0402
CA24F
1
1UF
20%
2
4V
CERM-X6S 0201
1
CA260
1UF
20%
2
4V
CERM-X6S 0201
CA298
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
RA205
200
1% 1/20W MF 201
2
PLACE_NEAR=UA000.AR23:5mm
CA20F
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA217
1
1UF
20%
2
4V
CERM-X6S 0201
CA231
1
1UF
20%
4V
2
CERM-X6S 0201
CA221
1
20UF
20%
2
2.5V
X6S-CERM 0402-1
CA29E
1
10UF
20%
6.3V
2
CER-X6S 0402
CA250
1
1UF
20%
2
4V
CERM-X6S 0201
1
CA261
1UF
20%
2
4V
CERM-X6S 0201
CA296
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
RA206
200
1% 1/20W MF 201
2
PLACE_NEAR=UA000.AL6:5mm
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
CA20A
20UF
20%
2.5V
X6S-CERM 0402-1
CA218
1UF
20%
4V
CERM-X6S 0201
CA232
1UF
20%
4V
CERM-X6S 0201
CA222
20UF
20%
2.5V
X6S-CERM 0402-1
CA251
10UF
20%
6.3V
CER-X6S 0402
CA249
20UF
20%
2.5V
X6S-CERM 0402-1
CA297
1UF
20%
4V
CERM-X6S 0201
CA295
20UF
20%
2.5V
X6S-CERM 0402-1
CRITICAL
CA200
1
220UF
20%
2V
2
ELEC SM
CA219
1
1UF
20%
2
4V
CERM-X6S 0201
CA233
1
1UF
20%
4V
2
CERM-X6S 0201
CA223
1
20UF
20%
2
2.5V
X6S-CERM 0402-1
CA252
1
10UF
20%
6.3V
2
CER-X6S 0402
CA24A
1
20UF
20%
2
2.5V
X6S-CERM 0402-1
1
CA292
1UF
20%
2
4V
CERM-X6S 0201
CA290
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
126 123 121 104 100 99 58
127 126 123 121 115 105 101 99 94 93
CRITICAL
CA201
1
220UF
20%
2V
2
ELEC SM
CA21A
1
1UF
20%
2
4V
CERM-X6S 0201
CA234
1
1UF
20%
4V
2
CERM-X6S 0201
CA224
1
20UF
20%
2
2.5V
X6S-CERM 0402-1
CA253
1
10UF
20%
6.3V
2
CER-X6S 0402
PP0V75_S0_GPU
CA24B
1
20UF
20%
2
2.5V
X6S-CERM 0402-1
1
CA291
1UF
20%
2
4V
CERM-X6S 0201
CA289
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
103 99
CRITICAL
CA243
1
220UF
20%
2V
2
ELEC SM
1
CA235
1UF
20%
2
4V
CERM-X6S 0201
1
CA225
20UF
20%
2
2.5V
X6S-CERM 0402-1
CA254
1
1UF
20%
4V
2
CERM-X6S 0201
1
CA288
1UF
20%
2
4V
CERM-X6S 0201
CA286
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CRITICAL
1
CA244
220UF
20%
2V
2
ELEC SM
1
CA236
1UF
20%
2
4V
CERM-X6S 0201
1
CA226
20UF
20%
2
2.5V
X6S-CERM 0402-1
CA255
1
1UF
20%
4V
2
CERM-X6S 0201
1
CA287
1UF
20%
2
4V
CERM-X6S 0201
CA285
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
Feedback path if GPU is unpopulated
PPGFX_S0_GPU
GPU_VDDCR_SOC_FB
PP1V35_MEMIO_S0_GPU
PP0V85_MEMCI_S0_GPU
105 99
103 99
GPU_VDD_MEM_RTN GPU_VDDCR_RTN
CRITICAL
1
CA247
220UF
20%
2V
2
ELEC SM
1
CA237
1UF
20%
2
4V
CERM-X6S 0201
1
CA227
20UF
20%
2
2.5V
X6S-CERM 0402-1
CA256
1
1UF
20%
4V
2
CERM-X6S 0201
127 126 124 123 121 115 106
1
CA284
1UF
20%
2
4V
CERM-X6S 0201
CA282
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
RA210 RA211 RA212 RA213
201MF 1/20W5%
MF
MF
MF 201 1/20W
1 2
NO_XNET_CONNECTION=1
1 2
NO_XNET_CONNECTION=1
1 2
NO_XNET_CONNECTION=1
1 2
NO_XNET_CONNECTION=1
1
RA214
100
5% 1/20W MF 201
2
NO_XNET_CONNECTION=1
1
2
1
2
1
2
1
2
1
2
1
2
CRITICAL
CA248
220UF
20%
2V
ELEC SM
CA238
1UF
20%
4V
CERM-X6S 0201
CA228
20UF
20%
2.5V
X6S-CERM 0402-1
CA257
1UF
20%
4V
CERM-X6S 0201
CA283
1UF
20%
4V
CERM-X6S 0201
CA281
20UF
20%
2.5V
X6S-CERM 0402-1
100 100 100
5%
100
5%
1
2
NO_XNET_CONNECTION=1
GPU_VDDCR_GFX_FB PPSOC_S0_GPU
1/20W201 5%
GPU_VDDIO_MEM_FB
1/20W201
GPU_VDDCI_MEM_FB
RA215
100
5% 1/20W MF 201
CRITICAL
1
CA29F
220UF
20%
2V
2
ELEC SM
1
CA239
1UF
20%
2
4V
CERM-X6S 0201
1
CA229
20UF
20%
2
2.5V
X6S-CERM 0402-1
CA258
1
1UF
20%
4V
2
CERM-X6S 0201
1
CA280
1UF
20%
2
4V
CERM-X6S 0201
CA278
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
CA23A
1UF
20%
2
4V
CERM-X6S 0201
1
CA22A
20UF
20%
2
2.5V
X6S-CERM 0402-1
PP1V8_S0_GPU
VOLTAGE=1.8V MIN_NECK_WIDTH=0.1200 MIN_LINE_WIDTH=0.2000
1
CA279
1UF
20%
2
4V
CERM-X6S 0201
CA277
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
103 99
105 99
105 99 126 121 115 105 99
BOM_COST_GROUP=GRAPHICS
CA23B
1
1UF
20%
4V
2
CERM-X6S 0201
CRITICAL
CA202
1
220UF
20%
2
2V
ELEC SM
1
CA276
1UF
20%
2
4V
CERM-X6S 0201
CA275
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
126 123 121 104 99 58
CA23C
1
2
CRITICAL
CA203
1
2
126
CA245
1UF
20%
4V
CERM-X6S
0201
126 123 121 104 99 58
1
CA273
2
CA274
1
2
1UF
20%
4V
CERM-X6S 0201
220UF
20%
2V
ELEC SM
1
2
1UF
20%
4V
CERM-X6S 0201
20UF
20%
2.5V
X6S-CERM 0402-1
CA23D
1
1UF
20%
4V
2
CERM-X6S 0201
CRITICAL
CA204
1
220UF
20%
2
2V
ELEC SM
MAKE_BASE=TRUE
PPSOC_S0_GPU
1
CA272
1UF
20%
2
4V
CERM-X6S 0201
CA271
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA23E
1
1UF
20%
4V
2
CERM-X6S 0201
CRITICAL
CA205
1
220UF
20%
2
2V
ELEC SM
PP1V8_S0_GPU
1
CA246
1UF
20%
4V
2
CERM-X6S 0201
Replace RA200 with inductor for additional filtering Suggested APN: 152S01107
CA23F
1
1UF
20%
4V
2
CERM-X6S 0201
CRITICAL
CA206
1
220UF
20%
2
2V
ELEC SM
97 94 93 58
127 126
1
2
1
2
CRITICAL
CA2B0
1
CA270
2
CA268
1
2
SYNC_MASTER=SEAN
PAGE TITLE
1UF
20%
4V
CERM-X6S 0201
20UF
20%
2.5V
X6S-CERM 0402-1
1
220UF
20%
2V
2
ELEC SM
1
CA269
1UF
20%
2
4V
CERM-X6S 0201
CA267
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
2
1
2
1
2
GPU Navi14 Power
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
CA240
1UF
20%
4V
CERM-X6S 0201
NOSTUFF
CRITICAL
CA26A
220UF
20%
2V
ELEC SM
CRITICAL
CA2A3
220UF
20%
2V
ELEC SM
CA266
1UF
20%
4V
CERM-X6S 0201
CA264
20UF
20%
2.5V
X6S-CERM 0402-1
CA241
1
1UF
20%
4V
2
CERM-X6S 0201
123 121 116 115 105 103 98
CRITICAL
CA2A2
1
220UF
20%
2V
2
ELEC SM
1
CA265
1UF
20%
2
4V
CERM-X6S 0201
CA263
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA242
1
1UF
20%
4V
2
CERM-X6S 0201
CRITICAL
CA2A1
1
220UF
20%
2V
2
ELEC SM
1
CA262
1UF
20%
2
4V
CERM-X6S 0201
CA2B3
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
102 OF 200
SHEET
99 OF 135
SYNC_DATE=08/22/2018
SIZE
D
D
C
B
A
8
67
35 4
2
1
Page 100
Vinafix.com
678
3 245
1
D
126 123 121 104 99 58
PPGFX_S0_GPU
CA307
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA318
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA329
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA309
CA308
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA319
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA32A
1
20UF
20%
2.5V
2 2.5V
X6S-CERM 0402-1
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA31A
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA32B
1
20UF
20%
2
X6S-CERM 0402-1
CA30B
CA30A
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA31B
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA32C
1
20UF
20%
2.5V
2 2.5V
X6S-CERM 0402-1
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA31C
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA32D
1
20UF
20%
2
X6S-CERM 0402-1
CA30C
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA31D
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA32E
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA30D
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA31E
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA32F
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA30E
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA31F
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA330
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA30F
1
20UF
20%
2
X6S-CERM 0402-1
CA320
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA331
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA311
CA310
1
20UF
20%
2.5V
22.5V
X6S-CERM 0402-1
CA321
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA332
1
20UF
20%
2.5V
2 2.5V
X6S-CERM 0402-1
1
20UF
20%
2
X6S-CERM 0402-1
CA322
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA333
1
20UF
20%
2
X6S-CERM 0402-1
CA312
1
20UF
20%
2.5V
22.5V
X6S-CERM 0402-1
CA323
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA334
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA313
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA324
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA335
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA314
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA325
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA336
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA315
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA326
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA337
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA317
CA316
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA327
1
20UF
20%
2.5V
2 2.5V
X6S-CERM 0402-1
CA338
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA328
1
20UF
20%
2
X6S-CERM 0402-1
CA339
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA34B
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA354
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA35D
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA34C
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA355
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA35E
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA34D
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA356
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA35F
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA34E
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA357
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA360
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA34F
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA358
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA361
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA350
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA359
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA362
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA351
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA35A
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA363
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA352
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA35B
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA364
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA353
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA35C
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA365
1
2.2UF
20% 4V
2
X6S-CERM 0201
D
C
B
A
A2 A5
A7 A10 A12 A14 A16 A18 A20 A22 A24 A26 A29 A31 A34
B1
B4
B6
B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B30 B32 B34 B35
C5
C7 C10 C12 C14 C16 C18 C20 C22 C24 C26 C29 C31
D6
D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D30 D34
E2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
2
UA000
NAVI14
BGA
SYM 9 OF 12
OMIT_TABLE
CA33A
20UF
20%
2.5V X6S-CERM 0402-1
CA33B
1
2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
20UF
20%
2.5V X6S-CERM 0402-1
E5 E7 E10 E12 E14 E16 E18 E20 E22 E24 E26 E29 E31 E33 E35 F3 F6 F9 F11 F13 F15 F17 F19 F21 F23 F25 F27 F30 F32 F34 G1 G4 G7 G10 G12 G14 G16 G18 G20 G22 G24 G26 G31 G33 G35 H9 H11 H13 H15 H17 H19 H21 H23 H25 H27 J3 J5 J8 J12
CA33C
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
J14 J16 J18 J20 J22 J24 J28 J30 J32 J34
K3
K6 K29 K31 K33 K35
L1
L4 L28 L30 L32 L34
M3 M5
M8 M10 M11 M13 M15 M17 M19 M21 M23 M24 M27 M29 M31 M33 M35
N1
N7 N12 N14 N16 N18 N20 N22 N24 N28 N30 N32 N34
P3
P6 P10 P11 P13 P15 P17
CA33D
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CA33E
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
UA000
NAVI14
BGA
SYM 10 OF 12
OMIT_TABLE
CA33F
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CA340
1
20UF
20%
2.5V
2 2.5V
X6S-CERM 0402-1
P19 P21 P23 P27 P29 P31 P33 P35 R1 R4 R7 R10 R12 R14 R16 R18 R20 R22 R24 R28 R30 R32 R34 T3 T6 T10 T11 T13 T15 T17 T19 T21 T23 T27 T29 T31 T33 T35 U1 U4 U7 U10 U12 U14 U16 U18 U20 U22 U24 U28 U30 U32 U34 V3 V6 V10 V11 V13 V15
CA341
1
20UF
20%
2 2.5V
X6S-CERM 0402-1
V17
VSS
V19
VSS
V21
VSS
V23
VSS
V27
VSS
V29
VSS
V31
VSS
V33
VSS
V35
VSS
W1
VSS
W4
VSS
W7
VSS
W10 W12 W14 W16 W18 W20 W22 W24 W28 W30 W32 W34
AA1 AA4
AA7 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA24 AA28 AA30 AA32 AA34
AB3
AB6 AB10 AB11 AB13
Y3
Y6 Y10 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y27 Y29 Y31 Y33 Y35
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CA342
1
20UF
20%
2
X6S-CERM 0402-1
1
2
UA000
NAVI14
BGA
SYM 11 OF 12
OMIT_TABLE
CA343
20UF
20%
2.5V X6S-CERM 0402-1
CA344
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AB15 AB17 AB19 AB21 AB23 AB27 AB29 AB31 AB33 AB35 AC1 AC4 AC7 AC12 AC14 AC16 AC18 AC20 AC22 AC24 AC28 AC30 AC32 AC34 AD3 AD6 AD10 AD11 AD13 AD15 AD17 AD19 AD21 AD23 AD27 AD29 AD31 AD33 AD35 AE1 AE4 AE7 AE9 AE12 AE14 AE16 AE18 AE20 AE22 AE24 AE28 AE30 AE32 AE34 AF3 AF6 AF11 AF13 AF15
CA345
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
AF17
AF19 AF21 AF23 AF29 AF31 AF33 AF35
AG1 AG4
AG7 AG12 AG14 AG16 AG18 AG20 AG22 AG24 AG28 AG30 AG32 AG34
AH13 AH15 AH17 AH19 AH21 AH24 AH27
AJ3
AJ7 AJ10 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ29 AJ31 AJ33 AJ35
AK1 AK4 AK6
AK9 AK11 AK12 AK14 AK16 AK18 AK20 AK22 AK26 AK30 AK32 AK34
CA346
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CA347
1
20UF
20%
2.5V
2 2.5V
X6S-CERM 0402-1
CA348
1
20UF
20%
2
X6S-CERM 0402-1
UA000
NAVI14
BGA
SYM 12 OF 12
OMIT_TABLE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CA349
1
2
AL3
AL7 AL14 AL16 AL18 AL20 AL22 AL27 AL31 AL33 AL35 AM2 AM6 AM9 AM10 AM11 AM12 AM13 AM15 AM17 AM19 AM21 AM25 AM29 AM34 AN1 AN5 AN7 AN13 AN15 AN17 AN19 AN21 AN23 AN30 AP1 AP2 AP6 AP14 AP16 AP18 AP20 AP22 AP31 AP34 AP35 AR2 AR6 AR10 AR14 AR16 AR18 AR20 AR22 AR25 AR34
20UF
20%
2.5V X6S-CERM 0402-1
CA34A
1
20UF
20%
2.5V
2
X6S-CERM 0402-1
CA366
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA36F
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA378
1
2.2UF
20% 4V
2
X6S-CERM 0201
CRITICAL
CA300
1
220UF
20% 2V
2
ELEC SM
CRITICAL
1
CA305
220UF
20% 2V
2
ELEC SM
CA367
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA370
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA379
1
2.2UF
20% 4V
2
X6S-CERM 0201
CRITICAL
CA301
1
220UF
20% 2V
2
ELEC SM
CRITICAL
1
CA306
220UF
20% 2V
2
ELEC SM
CA368
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA371
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA37A
1
2.2UF
20% 4V
2
X6S-CERM 0201
CRITICAL
CA302
1
220UF
20% 2V
2
ELEC SM
CRITICAL
1
CA390
220UF
20% 2V
2
ELEC SM
1
2
1
2
BOM_COST_GROUP=GRAPHICS
CA369
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA372
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA37B
1
2.2UF
20% 4V
2
X6S-CERM 0201
CRITICAL
CA303
220UF
20% ELEC
SM
CRITICAL
CA391
220UF
20% 2V ELEC SM
CA36A
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA373
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA37C
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA36B
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA374
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA37D
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA36C
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA375
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA37E
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA36D
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA376
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA36E
1
2.2UF
20% 4V
2
X6S-CERM 0201
CA377
1
2.2UF
20% 4V
2
X6S-CERM 0201
CRITICAL
CA304
1
220UF
20% 2V
22V
ELEC SM
CRITICAL
1
CA392
220UF
20% 2V
2
ELEC SM
SYNC_MASTER= SYNC_DATE=08/22/2018
PAGE TITLE
GPU Navi14 VSS & Decoupling
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-04492
REVISION
2.15.0
BRANCH
PAGE
103 OF 200
SHEET
100 OF 135
C
B
A
8
67
35 4
2
1
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