Apple macbook pro a1502 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

3456

REV ECN

DESCRIPTION OF REVISION

12

CK
APPD

DATE

8

0003549590

ENGINEERING RELEASED

2014-12-19

X304 MLB SCHEMATIC - DVT

Fri Dec 19 12:14:48 2014

D

C

B

Page DateSync

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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8

9
10
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42

(.csa)

1

Table of Contents

2

BOM Configuration

3

BOM Configuration

4

PD Parts

5

CPU GFX,NCTF,RSVD

6

CPU Misc,JTAG,CFG,RSVD

7

CPU LPDDR3 Interfaces

8

CPU & PCH Power

9

CPU & PCH Grounds

10

CPU Decoupling

12

PCH Decoupling

13

PCH Audio/JTAG/SATA/CLK

14

PCH PM/PCI/GFX

15

PCH PCIe,USB,LPC,SPI,SMBus

16

PCH GPIO/MISC/LPIO

18

CPU/PCH Merged XDP

19

Chipset Support

20

Project Chipset Support

22

LPDDR3 VREF Margining

23

LPDDR3 DRAM Channel A (00-31)

24

LPDDR3 DRAM Channel A (32-63)

25

LPDDR3 DRAM Channel B (00-31)

26

LPDDR3 DRAM Channel B (32-63)

27

LPDDR3 DRAM Termination

28

Thunderbolt Host (1 of 2)

29

Thunderbolt Host (2 of 2)

30

Thunderbolt Mobile Support

32

Thunderbolt Connector A

33

Thunderbolt Connector B

34

DDC Crossbar

35

Wireless Support

37

SSD Connector

39

Camera (1 of 2)

40

Camera (2 of 2)

46

External A USB3 Connector

48

Keyboard & Trackpad (1 of 2)

49

Keyboard & Trackpad (2 of 2)

50

SMC

51

SMC Shared Support

52

SMC Project Support

53

SMBus Connections

54

Power Sensors: High Side

Contents

YHARTANTO_J44

SHART_J44

J14

LDUNN_J44

J41

J41

J41

J41

J41

J41

J41

J41

J41

J41

J41

WFERRY_J43

J41

J41

YHARTANTO_J44

J41_MLB

J41_MLB

J41_MLB

J41_MLB

J41_MLB

T29_RR

T29_RR

T29_RR

T29_RR

T29_RR

J14

J41

YHARTANTO_J44

J45

J41

J41

JACK_J52

JACK_J52

JACK_J52

JACK_J52

JACK_J52

GKOO_J52

JACK_J52

12/21/2012

11/27/2012

09/04/2012

01/13/2013

10/23/2012

10/23/2012

10/23/2012

10/23/2012

10/23/2012

10/23/2012

10/23/2012

12/17/2012

02/21/2013

10/23/2012

01/19/2013

12/21/2012

01/30/2013

10/23/2012

01/02/2013

02/06/2013

02/06/2013

02/06/2013

02/06/2013

02/06/2013

01/19/2013

12/17/2012

11/19/2012

10/26/2012

10/26/2012

10/23/2012

11/01/2012

12/18/2012

01/24/2013

12/21/2012

10/23/2012

01/28/2014

01/31/2014

11/07/2013

10/24/2013

11/07/2013

12/06/2013

12/15/2013

(.csa)

Page Sync Date

55

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

Power Sensors: Load Side

56

Power Sensors: Extended

58

Thermal Sensors

60

Fan

61

SPI Debug Connector

62

Audio: Codec,Analog

63

Audio: Codec,Digital

64

Audio: Speaker Amps

65

Audio: Jack Support

66

Audio: Jack Translators

70

DC-In & Battery Connectors

71

PBus Supply & Battery Charger

72

CPU VR12.6 VCC Regulator IC

73

CPU VR12.6 VCC Power Stage

74

LPDDR3 Supply

75

5V & 3.3V Power Supply

76

1.05V Power Supply

77

LCD & KBD Backlight Driver

78

Misc Power Supplies

79

X239 Power Supply

80

Power FETs

81

Power Control

83

eDP Display Connector

95

RIO Connector

97

Display Mux: HDMI vs DP

100

Power Aliases

102

Signal Aliases

103

Memory Bit & Byte Swizzle

104

Functional & ICT Test

110

PCB Rule Definitions

111

CPU Constraints

112

USB Constraints

113

PCH Constraints

114

Memory Constraints

115

TBT,DP,HDMI Constraints

116

Camera Constraints

117

SMC Constraints

118

Project Specific Constraints

119

PCIe Constraints

120

Reference

Contents

JACK_J52

JACK_J52

YHARTANTO_J44

J41

YHARTANTO_J44

JCURCIO_J44

JCURCIO_J44

DIRK_J44

JCURCIO_J44

JCURCIO_J44

YHARTANTO_J44

AHARTMAN_J52

J41

J41

J41_MLB

J14

AHARTMAN_J52

SHART_J44

AHARTMAN_J52

AHARTMAN_J52

J41

AHARTMAN_J52

GKOO_J52

GKOO_J52

SRAMAN_J44

SHART_J44

SHART_J44

AHARTMAN_J52

GKOO_J52

YHARTANTO_J44

YHARTANTO_J44

YHARTANTO_J44

YHARTANTO_J44

YHARTANTO_J44

GKOO_J52

YHARTANTO_J44

YHARTANTO_J44

YHARTANTO_J44

YHARTANTO_J44

J14

12/06/2013

10/26/2013

01/07/2013

10/23/2012

01/09/2013

05/13/2013

07/25/2013

01/09/2013

07/25/2013

05/13/2013

01/09/2013

11/06/2013

10/23/2012

10/23/2012

05/21/2013

10/23/2012

10/29/2013

11/20/2012

11/06/2013

11/06/2013

10/23/2012

11/06/2013

05/04/2014

05/01/2014

01/29/2013

01/14/2013

11/19/2012

10/29/2013

12/06/2013

12/14/2012

01/13/2013

01/07/2013

01/08/2013

01/02/2013

12/06/2013

01/09/2013

01/02/2013

01/04/2013

01/13/2013

10/23/2012

D

C

B

A

Schematic / PCB #’s

PART NUMBER

051-1573

820-4924

QTY

1

8 7 6 5 4 2 1

DESCRIPTION

SCHEM,MLB,X304

PCBF,MLB,X304

REFERENCE DES

SCH1

PCB

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

SIZE

A

D

DRAWING TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SCHEM,MLB,X304

Apple Inc.

R

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

1 OF 120

SHEET

1 OF 82

3

8 7 6 5 4 3

12

BOM Groups

BOM GROUP

X304_COMMON
X304_COMMON1
X304_COMMON2
X304_COMMON3

X304_PROGPARTS
X304_DEVEL:ENG

D

X304_DEVEL:DVT
X304_DEVEL:PVT

ENGISNS

ALTERNATE,COMMON,X304_COMMON1,X304_COMMON2,X304_COMMON3,X304_COMMON4,X304_PROGPARTS
TBTHV:P15V,SKIP_5V3V3:AUDIBLE,PANEL:NEW,SSD_CLKREQ:BI
EDP,EDP_LS_CAP,CAMERA_3V3:S0,CAM_WAKE:NO,CAM_XTAL:NO,VCORE_FETS

XDP,SAMCONN,BKLT:PROD,CPUTHRM:ALRT,LOADRC:NO,OTHERRC:NO,DDRRC:NO,TBTRC:NO,BMONRC:NO,TPADRC:NO

SMC_PROG:PROTO0,BOOTROM_PROG,TBTROM_PROG

ALTERNATE,ENGISNS,XDP_CONN,DBGLED

ALTERNATE,ENGISNS,XDP_CONN,S0PGOOD_ISL
ALTERNATE
LOADISNS,OTHERISNS,DDRISNS,TBTISNS,BMONISNS,TPADISNS

Module Parts

PART NUMBER

337S00107
337S00108
337S00109

998-7866
338S1247
338S1264
376S1194

376S1193
376S00036
376S00037

QTY

1

CPU,BW,SR26K,PRQ,F0-B2,2.7,28W,1.05,1168

1

1
1

IC,BCM15700A2KFEB4G,S2 CMRA,8X8,208FCBGA

1
2
2
2
2

DESCRIPTION

CPU,BW,SR26H,PRQ,F0-B2,2.9,28W,1.1,1168

CPU,BW,SR26E,PRQ,F0-B2,3.1,28W,1.1,1168

INTERPOSER,BGA1168P, SINGLE SIDE

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,52A,5.9MO,3.3X3.3 DFN8

MOSFET,N-CH,30V,64A,3.5MO,3.3X3.3 DFN8

C

Programmables (All Builds)

TBT

PART NUMBER

341S00192

SMC

EFI ROM

341S00235

QTY

1

1

1

DESCRIPTION

T29,EPROM,FALCON RIDGE (V27.1) EVT2,X304

IC,SMC-B1,EXT(V2.21A5) PROTO 0,X304

EFI ROM,MLB (V0145) DVT,X304

REFERENCE DES

U0500
U0500
U0500

U0500
U2800

U3900
Q7310,Q7320
Q7311,Q7321
Q7310,Q7320
Q7311,Q7321

REFERENCE DES

U2890

U5000

U6100

BOM OPTIONS

CRITICAL

CRITICAL
CRITICAL1CPU_BDW23:2.9G
CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

CPU_BDW23:2.7G

CPU_BDW23:3.1G

VCORE_FET:VSHY

VCORE_FET:VSHY
VCORE_FET:ONSMI
VCORE_FET:ONSMI

CRITICAL

CRITICAL

CRITICAL341S3982

CRITICAL

SMC_PROG:PROTO0

BOM OPTION

CPU_SOCKET

BOM OPTION

TBTROM_PROG

BOOTROM_PROG

DVT

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Strategic Silicon

PART#

337S00068

337S00069

337S00070

337S00071

353S00200

333S0790 07

333S00004

338S1247 01

353S3931

353S00095

343S0511 01

338S1264S201

333S0700

333S0704

343S0649

353S4080

353S2888

353S2958

353S2929

353S00036

353S4160

343S0666 01

341S00192

341S00235

STRATEGIC VALUE

08

08

08

08

07

07333S0786

07333S0784

07333S0792

07

02311S0597

01359S0197

01

01353S3812

01353S3814

01

01353S3328

01

01

01353S3054

01

01

01

01

01

01

01

01341S3982

01

01

COMMENT

CPU

CPU

CPU

CPU

TPAD ELEC FUSE

SYS MEMORY HYNIX

SYS MEMORY HYNIX

SYS MEMORY MICRON

SYS MEMORY MICRON

SYS MEMORY SAMSUNG

KEYBOARD I2C EXPANDER

GREEN CLOCK

FALCON RIDGE

TBT PWR MUX

TBT MUX

TBT MUX

DDC CROSSBAR

DDC CROSSBAR

PCIE DELAY IC

S2 MEMORY

S2 MEMORY

USB POWER/SAFETY

SMC RESET CHIP

AUDIO

AUDIO AMPS

AUDIO AMPS

BAT CHARGER

VR12.6 CONTROLLER

BEN

SAK, HDMI SELECT

SMC

T29 ROM

EFI ROM

TABLE_STRATEGIC_HEAD

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

D

C

Variable BOM Groups

BOM GROUP

X304_COMMON4

Development/Base BOMs

B

PART NUMBER

685-1314
985-1319

QTY

1
1

Sub-BOMs

PART NUMBER

QTY

1

Main DRAM SPD Straps

BOM GROUP

RAM_16G_HYNIX_1600
RAM_16G_HYNIX_1866

RAM_8G_HYNIX_1600
RAM_8G_HYNIX_1866
RAM_4G_HYNIX_1600
RAM_4G_HYNIX_1866

RAM_16G_ELPIDA_1600

A

RAM_16G_ELPIDA_1866

RAM_8G_ELPIDA_1600
RAM_8G_ELPIDA_1866
RAM_4G_ELPIDA_1600

RAM_4G_ELPIDA_1866
RAM_8G_SAMSUNG_1600
RAM_8G_SAMSUNG_1866
RAM_4G_SAMSUNG_1600
RAM_4G_SAMSUNG_1866

DESCRIPTION

X304 MLB COMMON BOM

X304 MLB DEVEL BOM

DESCRIPTION

VCORE FET,VSHY,X304

BOM OPTIONS

SMCBOARDID:16

REFERENCE DES

BASE

DEVEL

REFERENCE DES

VCOREFETS

CRITICAL

CRITICAL
CRITICAL

CRITICAL

CRITICAL685-1318

BOM OPTIONS

16G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

16G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

8G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

8G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

4G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

4G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

16G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

16G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

8G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

8G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

4G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

8G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

8G_SAMSUNG_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

4G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

4G_SAMSUNG_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTION

BASE_BOM

DEVEL_BOM

BOM OPTION

VCORE_FETS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Main DRAM Parts

PART NUMBER

333S0783
333S0784
333S0785
333S0786
333S0787
333S0788
333S0789
333S0790
333S0791
333S0792
333S0793

333S0794
333S00003
333S00004
333S00001
333S00002

QTY

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

4
4

IC,SDRAM,29nm 16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,29nm 16Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,29nm 8Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,29nm 8Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,25nm 16Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,25nm 16Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,25nm 8Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,25nm 8Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,23nm 16Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,23nm 16Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,23nm 8Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,23nm 8Gb,LPDDR3-1866,178P FBGA

4

S2 DRAM Parts

PART NUMBER

333S0700

QTY

IC,SDRAM,4GBIT.DDR3L-1600,HUMA,96B BGA

1

DESCRIPTION

DESCRIPTION

REFERENCE DES

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

REFERENCE DES

6 3

U4000

CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

CRITICAL

BOM OPTION

16G_HYNIX_1600
16G_HYNIX_1866

8G_HYNIX_1600
8G_HYNIX_1866
4G_HYNIX_1600

4G_HYNIX_1866
16G_ELPIDA_1600
16G_ELPIDA_1866

8G_ELPIDA_1600
8G_ELPIDA_1866
4G_ELPIDA_1600

4G_ELPIDA_1866
8G_SAMSUNG_1600
8G_SAMSUNG_1866
4G_SAMSUNG_1600
4G_SAMSUNG_1866

BOM OPTION

SYNC_MASTER=SHART_J44

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/27/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

2 OF 120

SHEET

2 OF 82

124578

SIZE

B

A

D

8 7 6 5 4 3

12

BOM Variants

BOM NUMBER

685-1314

985-1319
639-00772
639-00773
639-00774

D

639-00775
639-00776
639-00777
639-00778
639-00779
639-00780
639-00781
639-00782
639-00783
639-00784
639-00785
639-00786

COMMON,MLB,X304
DEV,MLB,X304
MLB,BDW2+3,2.7GHz,8GB-HY-1866,X304
MLB,BDW2+3,2.7GHz,16GB-HY-1866,X304
MLB,BDW2+3,2.7GHz,8GB-EP-1866,X304
MLB,BDW2+3,2.7GHz,16GB-EP-1866,X304
MLB,BDW2+3,2.7GHz,8GB-SM-1866,X304
MLB,BDW2+3,2.9GHz,8GB-HY-1866,X304
MLB,BDW2+3,2.9GHz,16GB-HY-1866,X304
MLB,BDW2+3,2.9GHz,8GB-EP-1866,X304
MLB,BDW2+3,2.9GHz,16GB-EP-1866,X304
MLB,BDW2+3,2.9GHz,8GB-SM-1866,X304
MLB,BDW2+3,3.1GHz,8GB-HY-1866,X304
MLB,BDW2+3,3.1GHz,16GB-HY-1866,X304
MLB,BDW2+3,3.1GHz,8GB-EP-1866,X304
MLB,BDW2+3,3.1GHz,16GB-EP-1866,X304
MLB,BDW2+3,3.1GHz,8GB-SM-1866,X304

BOM NAME

X304_COMMON
X304_DEVEL:ENG
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_16G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_16G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_SAMSUNG_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_16G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_16G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_SAMSUNG_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_16G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_16G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_SAMSUNG_1866

BOM OPTIONS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

C

BOM NUMBER

639-00035
639-00036

685-1318
685-00022

BOM NAME

PCBA,MLB,NO CPU,X304
PCBA,MLB,CPU SOCKET,X304
VCORE FET,VSHY,X304

BASE_BOM,DEVEL_BOM,RAM_8G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_SOCKET,RAM_8G_HYNIX_1866
VCORE_FET:VSHY

VCORE FET,ONSMI,X304 VCORE_FET:ONSMI

BOM OPTIONS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

B

Alternate Parts

PART NUMBER

685-00022

A

ALTERNATE FOR
PART NUMBER

685-1318
333S0700333S0704

BOM OPTION

REF DES

ALL
ALL

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Onsemi alt to Vishay for CPU Core Mosfets

TABLE_ALT_ITEM

Elpida alt to Hynix for S2 Camera DDR3 Memory

6 3

Alternate Parts

PART NUMBER

376S1053

138S0739

138S0725

376S00074

376S1129

353S3452

128S0364
107S0254
138S0843

197S0542 197S0544
197S0545 Epson alt to TXC197S0544

107S0248
127S0164
353S4070 353S4069
353S4068 353S4069

311S0649
138S0614
155S0694 155S0387

740S00003

138S0738

353S00095

311S00007
128S0398
128S0386
128S0397 128S0325

377S00011

377S0155 377S0184
155S0914
371S0558
128S0436
128S0445 128S0392

353S00034

311S00014

311S00008

197S0479 197S0478 Epson alt to NDK

311S00013

376S00014

371S00019

371S00018

311S00015

371S00017

353S00107

107S00024

372S0186 372S0185

353S00135

353S00133

131S00040

107S00015

107S00031

107S00029

ALTERNATE FOR
PART NUMBER

376S0604
128S0329128S0311 NEC alt to Sanyo
138S0706

BOM OPTION

REF DES

ALL
ALL
ALL

COMMENTS:

ALL
152S1645152S0461
376S0820376S1080

138S0724
376S0855
376S0855
376S1128376S1089
353S1286

128S0264
107S0241
138S0674

138S0811138S0846

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

107S0250
127S0162

ALL

ALL

ALL

ALL
353S3812353S3814
311S0541
138S0578

ALL

ALL

ALL

ALL
155S0513155S0660

740S0135
138S1101
353S3328
311S0426
128S0220
128S0284

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL
377S0184

ALL

ALL
155S0897
371S0713
128S0392

ALL

ALL

ALL

ALL
353S2220
311S0515
311S0271

ALL

ALL

ALL

ALL
311S0508
376S0761

ALL

ALL

ALL

ALL
311S0450
371S0749

353S3239
107S0226

ALL

ALL

ALLANY

ALL

ALL
353S3987
353S2220
353S2741 Onsemi alt to TI

ALL353S00231

ALL

ALL

ALL131S00041
107S00011
107S00032
107S00030

ALL

ALL

ALL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Diodes alt to Fairchild

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Samsung alt to Murata

TABLE_ALT_ITEM

Epson alt to NDK197S0480197S0481

TABLE_ALT_ITEM

Cyntec alt to Vishay

TABLE_ALT_ITEM

Diodes alt to On Semi

TABLE_ALT_ITEM

Samsung alt to Murata

TABLE_ALT_ITEM

Toshiba alt for Diodes Dual

TABLE_ALT_ITEM

NXP Alt for Diodes Dual

TABLE_ALT_ITEM

NXP Alt for Diodes Single

TABLE_ALT_ITEM

Maxim alt to Microchip

TABLE_ALT_ITEM

Sanyo 2nd Factory alt

TABLE_ALT_ITEM

Cyntec alt to TFT

TABLE_ALT_ITEM

Samsung alt to Murata (BKLT)

TABLE_ALT_ITEM

Samsung alt to Murata (BKLT)

TABLE_ALT_ITEM

NDK alt to TXC

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TFT alt to Cyntec

TABLE_ALT_ITEM

Rohm alt to Vishay

TABLE_ALT_ITEM

Pericom alt to TI DP Mux U9750

TABLE_ALT_ITEM

NXP alt to TI DP Mux U9750

TABLE_ALT_ITEM

TI alt to NXP

TABLE_ALT_ITEM

ONsemi alt to Toshiba

TABLE_ALT_ITEM

Murata, TDK, Samsung, Taiyo Yuden alt to Murata, TDK

TABLE_ALT_ITEM

Murata alt to TDK

TABLE_ALT_ITEM

Murata alt to TDK

TABLE_ALT_ITEM

AEM alt to Tyco

TABLE_ALT_ITEM

Samsung alt to Murata for LCD BKL caps

TABLE_ALT_ITEM

Pericom alt to TI

TABLE_ALT_ITEM

Diodes alt to NXP

TABLE_ALT_ITEM

Kemet alt to Sanyo

TABLE_ALT_ITEM

Kemet alt to Sanyo

TABLE_ALT_ITEM

Kemet alt to Sanyo

TABLE_ALT_ITEM

Infineon alt to Infineon

TABLE_ALT_ITEM

On Semi alt to Infineon

TABLE_ALT_ITEM

Panasonic alt to TDK

TABLE_ALT_ITEM

ST Micro alt to Diodes

TABLE_ALT_ITEM

Kemet alt to Sanyo

TABLE_ALT_ITEM

Panasonic alt to Sanyo

TABLE_ALT_ITEM

Pericom alt to Fairchild

TABLE_ALT_ITEM

Diodes alt to NXP

TABLE_ALT_ITEM

Diodes alt to NXP

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Diodes alt to NXP

TABLE_ALT_ITEM

Toshiba alt to Vishay

TABLE_ALT_ITEM

Rohm alt to Rohm371S0463

TABLE_ALT_ITEM

Rohm alt to Rohm371S0619

TABLE_ALT_ITEM

Diodes alt to NXP

TABLE_ALT_ITEM

Diodes alt to Onsemi

TABLE_ALT_ITEM

Onsemi alt to Intersil

TABLE_ALT_ITEM

Yageo alt to Cyntec

TABLE_ALT_ITEM

NXP alt to Diodes

TABLE_ALT_ITEM

NXP alt to TI

TABLE_ALT_ITEM

Onsemi alt to Fairchild

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Murata alt to Taiyo Yuden

TABLE_ALT_ITEM

TFT alt to Cyntec

TABLE_ALT_ITEM

TFT alt to Cyntec

TABLE_ALT_ITEM

TFT alt to Cyntec

SYNC_MASTER=J14

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/04/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

3 OF 120

SHEET

3 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Shield Cans

1

SH0451

SM

SHLD-J44-MLB

USB Cage

D

C

Mounting Holes & Slots

OMIT

ZT0411

4P5R2P3-3P5B

1

OMIT

ZT0413

6.19X4.60-SNOWMAN

1

OMIT

ZT0414

6.19X4.60-SNOWMAN

1

TH0400

TH-NSP

1

SL-1.1X0.5-1.4x0.8

TH0403

TH-NSP

1

SL-1.1X0.5-1.4x0.8

TH0404

TH-NSP

1

SL-1.1X0.45-1.4x0.75

TH0405

TH-NSP

1

SL-1.1X0.45-1.4x0.75

1

SH0450

SM

SHIELD-FENCE-MLB-T29-X304

TBT Cage

ABOVE GUMSTICK CARD IN MIDDLE OF BOARD
(998-1195)

SNOWMAN-SHAPED SLOT AT LEFT OF MEMORY BANK
(998-5879)

SNOWMAN-SHAPED SLOT AT RIGHT OF MEMORY BANK
(998-5879)

Upper TBT can Ground slot
(862-0118)

Lower TBT can Ground slot
(862-0118)

USB can Ground slot
(998-3975)

USB can Ground slot
(998-3975)

SH0452

SM

SHLD-FENCE-MLB-DRAM-X304

1

789

101112131415161718

Memory Shield CAN (806-00037)

192202122232425262728

293303132333435363738

39440

4142434445464748495505152535455565758

D

5966061626364

C

Rubber Mount Standoffs (860-1448)

SH0460

2.9OD1.2ID-1.35H-SM

1

2

B

SH0462

2.9OD1.2ID-1.35H-SM

1

2

SH0464

2.9OD1.2ID-1.35H-SM

1

2

SH0466

2.9OD1.2ID-1.35H-SM

1

2

SH0468

A

1

2

SH0461

2.9OD1.2ID-1.35H-SM

1

2

SH0465

2.9OD1.2ID-1.35H-SM

1

2

SH0463

2.9OD1.2ID-1.35H-SM

1

2

SH0467

2.9OD1.2ID-1.35H-SM

1

2

SH0469

2.9OD1.2ID-1.35H-SM2.9OD1.2ID-1.35H-SM

1

2

THERMAL MODULE STANDOFF (860-00165)

SH0420

1

SH0426

4.5OD1.85ID-1.78H-SM 4.5OD1.85ID-1.78H-SM

1

SH0421

4.5OD1.85ID-1.78H-SM4.5OD1.85ID-1.78H-SM

1

SH0427

1

RIO FLEX BRACKET BOSSES (860-00166)

SH0443

3.5OD1.85ID-2.0H

1

6 3

FAN STANDOFF (860-00183)SSD STANDOFF (860-00164)

SH0440

5.0OD2.0H

1

POGO PINS (870-00607)

SH0435 & SH0436 removed.

SH0432

POGO-2.3OD-5.5H-X304

SM

1

SH0433

POGO-2.3OD-5.5H-X304

SM

1

IPD FLEX BRACKET BOSSES (860-00166)

SH0471

3.5OD1.85ID-2.0H

1

BOM_COST_GROUP=PD PARTS

SH0441

STDOFF-4.5ID1.73H-SM

1

SYNC_MASTER=LDUNN_J44

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PD Parts

Apple Inc.

R

SYNC_DATE=01/13/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

4 OF 120

SHEET

4 OF 82

124578

SIZE

B

A

D

8 7 6 5 4 3

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

DDI Port Assignments:

D

TBT Sink 0

TBT Sink 1
(MUXed with HDMI
if necessary)

DP_TBTSNK0_ML_C_N<0>

25 77

OUT

DP_TBTSNK0_ML_C_P<0>

25 77

OUT

DP_TBTSNK0_ML_C_N<1>

25 77

OUT

DP_TBTSNK0_ML_C_P<1>

25 77

OUT

DP_TBTSNK0_ML_C_N<2>

25 77

OUT

DP_TBTSNK0_ML_C_P<2>

25 77

OUT

DP_TBTSNK0_ML_C_N<3>

25 77

OUT

DP_TBTSNK0_ML_C_P<3>

25 77

OUT

=DP_TBTSNK1_ML_C_N<0>

69

OUT

=DP_TBTSNK1_ML_C_P<0>

69

OUT

=DP_TBTSNK1_ML_C_N<1>

69

OUT

=DP_TBTSNK1_ML_C_P<1>

69

OUT

=DP_TBTSNK1_ML_C_N<2>

69

OUT

=DP_TBTSNK1_ML_C_P<2>

69

OUT

=DP_TBTSNK1_ML_C_N<3>

69

OUT

=DP_TBTSNK1_ML_C_P<3>

69

OUT

C54
C55
B58
C58
B55
A55
A57
B57

C51
C50
C53
B54
C49
B50
A53
B53

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

SYM 1 OF 19

DDI

EDP

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP_AUXN
EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

C45
B46
A47
B47

C47
C46
A49
B49

A45
B45

D20
A43

DP_INT_ML_C_N<0>
DP_INT_ML_C_P<0>
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<1>

DP_INT_ML_C_N<2>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<3>
DP_INT_ML_C_P<3>

DP_INT_AUXCH_C_N
DP_INT_AUXCH_C_P

MCP_EDP_RCOMP

73

TP_EDP_DISP_UTIL

65 77

OUT

65 77

OUT

65 77

OUT

65 77

OUT

65 77

OUT

65 77

OUT

65 77

OUT

65 77

OUT

65 77

BI

65 77

BI

eDP Port Assignment:

Internal panel

PPVCOMP_S0_CPU

1

R0530

24.9

1%
1/20W
MF
201

2

8

12

D

OMIT_TABLE

CRITICAL

U0500

AT2
AU44
AV44

D15

F22

H22

J21

BROADWELL-ULT

2C+GT2

BGA

SYM 17 OF 19

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 18 OF 19

SPARE

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD

DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF

N23

RSVD

R23

RSVD

T23

RSVD

U10

RSVD

AL1

RSVD

AM11

RSVD

AP7

RSVD

AU10

RSVD

AU15

RSVD

AW14

RSVD

AY14

RSVD

C

NO_TEST NO_TEST

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE
TRUE

TRUE

AY2

DAISY_CHAIN_NCTF

AY3

DAISY_CHAIN_NCTF

AY60

DAISY_CHAIN_NCTF

AY61

DAISY_CHAIN_NCTF

AY62

DAISY_CHAIN_NCTF

B2

DAISY_CHAIN_NCTF

B3

DAISY_CHAIN_NCTF

B61

DAISY_CHAIN_NCTF

B62

DAISY_CHAIN_NCTF

B63

DAISY_CHAIN_NCTF

C1

DAISY_CHAIN_NCTF

C2

DAISY_CHAIN_NCTF

TP0531

TP0501

TP

TP-P6

TP

TP-P6

5

5

1

5

5

1

5

5

MCP_DC_AW2_AY2
MCP_DC_AW3_AY3
MCP_DC_AY60
MCP_DC_AW61_AY61
MCP_DC_AW62_AY62
MCP_DC_B2
MCP_DC_A3_B3
MCP_DC_A61_B61
MCP_DC_B62_B63

MCP_DC_C1_C2

B

NC NC

MCP Daisy-Chain Strategy:

Each corner of CPU has two testpoints.
Other corner test signals connected in
daisy-chain fashion. Continuity should
exist between both TP’s on each corner.

A3
A4

A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63

NCNC
NCNC
NCNC

NCNC
NCNC
NCNC
NC
NC
NC
NC

MCP_DC_A3_B3

TRUE

MCP_DC_A4
MCP_DC_A60

MCP_DC_A61_B61

TRUE

MCP_DC_A62
MCP_DC_AV1
MCP_DC_AW1
MCP_DC_AW2_AY2

TRUE

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW61_AY61

TRUE

MCP_DC_AW62_AY62

TRUE

MCP_DC_AW63

C

5

1

TP

TP0500

TP-P6
1

TP

TP0510

TP-P6

5

1

TP

TP0511

TP-P6
1

TP

TP0520

TP-P6
1

TP

TP-P6

1

TP

TP-P6

TP0521

TP0530

5

5

5

5

B

A

BOM_COST_GROUP=CPU

6 3

SYNC_MASTER=J41

PAGE TITLE

CPU GFX,NCTF,RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

5 OF 120

SHEET

5 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

OMIT_TABLE

CRITICAL

U0500

D

=PP1V05_S0_CPU_VCCST

8

15 16 17 55 68

R0650

1/20W

PLACE_NEAR=U0500.AU60:12.7mm

PLACE_NEAR=U0500.AV60:12.7mm

200

201

38 39 55 73

BI

1

1%
MF

2

R0610

CPU_PROCHOT_L

1

121

1/20W

201

1%
MF

2

R0652

PLACE_NEAR=U0500.C61:12.7mm

R0651

PLACE_NEAR=U0500.AU61:12.7mm

1/20W

201

100

1/20W

201

1

62

5%
MF

2

R0611

56

12

5%

1/20W

MF

201

R0620

10K

1/20W

201

1

5%
MF

2

1

1%
MF

2

CPU_CATERR_L

38 73

OUT

CPU_PECI

39 73

BI

CPU_PROCHOT_R_L

73

CPU_PWRGD

CPU_SM_RCOMP<0>

73

CPU_SM_RCOMP<1>

73

CPU_SM_RCOMP<2>

73

=MEM_RESET_L

70

OUT

CPU_MEMVTT_PWR_EN_LSVDDQ

17

OUT

D61

K61

N62

K63

C61

AU60
AV60
AU61

AV15

AV61

PROC_DETECT*

CATERR*

PECI

PROCHOT*

PROCPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

SM_DRAMRST*

SM_PG_CNTL1

NC

BROADWELL-ULT

2C+GT2

BGA

SYM 2 OF 19

MISC

PWR

DDR3

(IPU)

JTAG

THERMAL

(IPD)

(IPU)

(IPU)

PRDY*

(IPU)

PREQ*

(IPU)

PROC_TCK
PROC_TMS

PROC_TRST*

PROC_TDI
PROC_TDO

BPM0*

(IPU)

BPM1*

(IPU)

BPM2*

(IPU)

BPM3*

(IPU)

BPM4*

(IPU)

BPM5*

(IPU)

BPM6*

(IPU)

BPM7*

(IPU)

J62
K62

E60
E61
E59

F63
F62

J60
H60
H61
H62
K59
H63
K60
J61

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

16 73

OUT

16 73

IN

16 73

IN

16 73

IN

16

IN

16 73

IN

16 73

OUT

16 73

BI

16 73

BI

16 73

BI

16 73

BI

16 73

BI

16 73

BI

16 73

BI

16 73

BI

12

D

C

B

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE
CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID
CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED
CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE
CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

These can be placed close to J1800

A

NOSTUFF

R0640

1/20W

and are only for debug access

HSW_PRE_ES2

1

1

R0639

1K

1K

5%

5%
1/20W

MF

MF

201

201

2

2

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid
issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

CPU_CFG<4>

EDP

1

R0634

1K

5%
1/20W
MF
201

2

NOSTUFF

R0638

1/20W

6

16 73

201

NOSTUFF

1

1

R0631

1K

1K

5%

5%
1/20W

MF

MF
201

2

2

CPU_CFG<10>
CPU_CFG<9>
CPU_CFG<8>
CPU_CFG<1>
CPU_CFG<0>

NOSTUFF

1

R0630

1K

5%
1/20W
MF
201

2

C

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

CPU_CFG<0>

6

16 73

BI

CPU_CFG<1>

6

16 73

BI

CPU_CFG<2>

16 73

BI

CPU_CFG<3>

16 73

BI

CPU_CFG<4>

6

16 73

BI

CPU_CFG<5>

16 73

BI

CPU_CFG<6>

16 73

BI

CPU_CFG<7>

16 73

BI

CPU_CFG<8>

6

16 73

BI

CPU_CFG<9>

6

16 73

BI

CPU_CFG<10>

6

16 73

BI

CPU_CFG<11>

16 73

BI

CPU_CFG<12>

16 73

BI

CPU_CFG<13>

16 73

BI

CPU_CFG<14>

16 73

BI

CPU_CFG<15>

16 73

BI

CPU_CFG<16>

16 73

BI

CPU_CFG<18>

16 73

BI

CPU_CFG<17>

16 73

BI

CPU_CFG<19>

16 73

BI

CPU_CFG_RCOMP

6

16 73

6

16 73

6

16 73

6

16 73

6

16 73

R0680

49.9

1/20W

201

1%
MF

1

2

PCH_TD_IREF

1

R0685

8.25K

1%
1/20W
MF
201

2

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

J20
H18
B12

E1
D1

RSVD

RSVD
RSVD
RSVD
RSVD
TD_IREF

NC
NC

NC
NC
NC

6 3

(IPU)

(IPU)
(IPU)

(IPU)

(IPU)
(IPU)

(IPU)
(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)
(IPU)

(IPU)

(IPU)

(IPU)
(IPU)

(IPU)
(IPU)

SYM 19 OF 19

RESERVED

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD_B43

RSVD_TP
RSVD_TP

RSVD_TP

RSVD

RSVD
RSVD

PROC_OPI_COMP

RSVD
RSVD

RSVD
RSVD

VSS
VSS

AV63
AU63

C63
C62

B43

A51
B51

L60

N60

W23
Y22

AY15

AV62
D58

P22
N21

P20
R20

NC

NC

NC
NC

73

NC
NC

NC
NC

TP_MCP_RSVD_AV63
TP_MCP_RSVD_AU63

TP_MCP_RSVD_C63
TP_MCP_RSVD_C62

TP_MCP_RSVD_A51
TP_MCP_RSVD_B51

TP_MCP_RSVD_L60

CPU_OPI_RCOMP

1

R0690

49.9

1%
1/20W
MF
201

2

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

PAGE TITLE

CPU Misc,JTAG,CFG,RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

6 OF 120

SHEET

6 OF 82

124578

SIZE

B

A

D

8 7 6 5 4 3

12

OMIT_TABLE

MEM_A_DQ<0>

70 71 76

BI

MEM_A_DQ<1>

70 71 76

BI

MEM_A_DQ<2>

70 71 76

BI

MEM_A_DQ<3>

70 71 76

BI

MEM_A_DQ<4>

70 71 76

BI

MEM_A_DQ<5>

70 71 76

BI

MEM_A_DQ<6>

70 71 76

BI

MEM_A_DQ<7>

70 71 76

BI

MEM_A_DQ<8>

70 71 76

D

C

B

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 3 OF 19

MEMORY CHANNEL A

LPDDR3

RSVD1

RSVD2

CAB3

CAB2
CAB1

CAB4
CAB6

CAA5

CAB9

CAB8
CAB5

CAA0

CAA2

CAA4
CAA3

CAA1

CAB7
CAA7

CAA6
CAB0

CAA9

CAA8

SM_VREF_CA

SM_VREF_DQ0

SM_VREF_DQ1

CRITICAL

SA_CLK0*

SA_CLK0

SA_CLK1*

SA_CLK1

SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3

SA_CS0*
SA_CS1*

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_BA0
SA_BA1
SA_BA2

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

AU37
AV37
AW36
AY36

AU43
AW43
AY42
AY43

AP33
AR32

AP32

AY34
AW34
AU34

AU35
AV35
AY41

AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

AP49

AR51

AP51

MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CLK_N<1>
MEM_A_CLK_P<1>

MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_CKE<2>
MEM_A_CKE<3>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

=MEM_A_ODT<0>

=MEM_A_RAS_L
=MEM_A_WE_L
=MEM_A_CAS_L

=MEM_A_BA<0>
=MEM_A_BA<1>
=MEM_A_BA<2>

=MEM_A_A<0>
=MEM_A_A<1>
=MEM_A_A<2>
=MEM_A_A<3>
=MEM_A_A<4>
=MEM_A_A<5>
=MEM_A_A<6>
=MEM_A_A<7>
=MEM_A_A<8>
=MEM_A_A<9>
=MEM_A_A<10>
=MEM_A_A<11> MEM_B_DQ<34>
=MEM_A_A<12>
=MEM_A_A<13>
=MEM_A_A<14>
=MEM_A_A<15>

MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

CPU_DIMM_VREFCA
CPU_DIMMA_VREFDQ
CPU_DIMMB_VREFDQ

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

20 24 76

20 24 76

21 24 76

21 24 76

20 24 76

20 24 76

21 24 76

21 24 76

20 21 24 76

20 21 24 76

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

19 76

19 76

19 76

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>

MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>

MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>

MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>

MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18

OMIT_TABLE

CRITICAL

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10 SB_CS0*
SB_DQ11 SB_CS1*
SB_DQ12
SB_DQ13 SB_ODT0
SB_DQ14
SB_DQ15 SB_RAS*
SB_DQ16
SB_DQ17 SB_CAS*
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33 SB_MA10
SB_DQ34 SB_MA11
SB_DQ35 SB_MA12
SB_DQ36
SB_DQ37 SB_MA14
SB_DQ38 SB_MA15
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 4 OF 19

MEMORY CHANNEL B

LPDDR3

RSVD3

RSVD4

CAB3

CAB2
CAB1

CAB4
CAB6

CAA5

CAB9

CAB8
CAB5

CAA0

CAA2

CAA4
CAA3

CAA1

CAB7
CAA7

CAA6
CAB0

CAA9

CAA8

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3

SB_WE*

SB_BA0
SB_BA1
SB_BA2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9

SB_MA13

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

AY49
AU50
AW49
AV50

AM32
AK32

AL32

AM35
AK35
AM33

AL35
AM36
AU49

AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>

MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_CKE<2>
MEM_B_CKE<3>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

=MEM_B_ODT<0>

=MEM_B_RAS_LMEM_B_DQ<15>
=MEM_B_WE_L
=MEM_B_CAS_L

=MEM_B_BA<0>MEM_B_DQ<19>
=MEM_B_BA<1>MEM_B_DQ<20>
=MEM_B_BA<2>MEM_B_DQ<21>

=MEM_B_A<0>
=MEM_B_A<1>
=MEM_B_A<2>
=MEM_B_A<3>
=MEM_B_A<4>
=MEM_B_A<5>
=MEM_B_A<6>
=MEM_B_A<7>
=MEM_B_A<8>
=MEM_B_A<9>
=MEM_B_A<10>MEM_B_DQ<33>
=MEM_B_A<11>
=MEM_B_A<12>
=MEM_B_A<13>
=MEM_B_A<14>
=MEM_B_A<15>MEM_B_DQ<38>

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

22 24 76

22 24 76

23 24 76

23 24 76

22 24 76

22 24 76

23 24 76

23 24 76

22 23 24 76

22 23 24 76

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

D

C

B

A

SYNC_MASTER=J41

PAGE TITLE

CPU LPDDR3 Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU

IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

7 OF 120

SHEET

7 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

BDW-ULT current estimates from Broadwell Mobile ULT Processor EDS vol.1 Doc# 514405, Rev.: 0.9v1
Wildcat Point-LP current estimates from Wildcat Point-LP PCH EDS, Doc# 515621, Rev. 0.9
Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

D

C

=PP1V05_S0SW_PCH_VCCHSIO

11 68

1838mA Max

=PP1V05_S0_PCH_VCCIO_HSIO

68

29mA Max[1]

PP1V05_S0SW_PCH_VCCUSB3PLL

11 14

41mA Max

PP1V05_S0SW_PCH_VCCSATA3PLL

B

A

11 12

42mA Max

WF: RSVD on Sawtooth Peak rev 1.0

PP1V05_S0_PCH_VCCAPLL_OPI

11

57mA Max

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

11 17 63

11mA Max

=PP3V3_SUS_PCH_VCCSUS_GPIO

11 68

59mA Max[1]

=PP3V3_S5_PCH_VCCDSW

11 68

114mA Max

=PP3V3_S0_PCH_VCC3_3_GPIO

11 68

40mA Max[1]

PP1V05_S0_PCH_VCC_ICC

11

VCCCLK: 200mA Max

PP1V05_S0_PCH_VCCACLKPLL

11 12

31mA Max

=PP1V05_S0_PCH_VCCCLK

11 68

VCCCLK: 200mA Max

WF: RSVD on Sawtooth Peak rev 1.0

=PP3V3_SUS_PCH_VCCSUS_ICC

68

3.3mA Max[1]

K9

VCCHSIO

L10

VCCHSIO

M9

VCCHSIO

N8

VCC1_05

P9

VCC1_05

B18

VCCUSB3PLL

B11

VCCSATA3PLL

Y20

VCCAPLL

NC

AA21

VCCAPLL

W21

VCCAPLL

J13

DCPSUS3

NC

AH14

VCCHDA

VRM/USB2/AZALIA

AH13

DCPSUS2

NC

AC9

VCCSUS3_3

AA9

VCCSUS3_3

AH10

VCCDSW3_3

V8

VCC3_3

W9

VCC3_3

J18

VCCCLK

K19

VCCCLK

A20

VCCACLKPLL

J17

VCCCLK

R21

VCCCLK

T21

VCCCLK

K18

RSVD

NC

M20

RSVD

NC

V21

RSVD

NC

AE20

VCCSUS3_3

AE21

VCCSUS3_3

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 13 OF 19

HSIO

OPI

AZALIA/HDA

USB3

GPIO/LCC

ICC

LPT LP POWER

VCCSUS3_3

SPI RTC

DCPSUSBYP

CORE

DCPSUSBYP

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

VCCTS1_5

USB2

VCCRTC

DCPRTC

VCCSPI

VCCASW
VCCASW

VCC1P05
VCC1P05
VCC1P05
VCC1P05
VCC1P05

VCCASW
VCCASW
VCCASW

DCPSUS1
DCPSUS1

VCC3_3
VCC3_3

VCCSDIO
VCCSDIO

DCPSUS4

RSVD

VCC1_05
VCC1_05

=PPVMEMIO_S0_CPU

10 68

1.4A Max (DDR3: 1.5-1.35V)

1.1A Max (LPDDR3: 1.2V)

=PPVCC_S0_CPU

8

10 44 68

1

R0860

100

=PP1V05_S0_CPU_VCCST

6 8

15 16 17 55 68

CPU_VIDALERT_L

55 73

IN

CPU_VIDSCLK

55 73

OUT

CPU_VIDSOUT

55 73

BI

AH11

=PP3V3_SUS_PCH_VCCSUS_RTC

0.3mA Max[1]

AG10

AE7

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

Y8

=PP3V3_SUS_PCH_VCC_SPI

18mA Max

AG14

=PP1V05_S0M_PCH_VCCASW

AG13

185mA Max[1]

J11

=PP1V05_S0_PCH_VCC

H11

1499mA Max[1]

H15
AE8
AF22

AG19

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_LINE_WIDTH=0.2 mm

AG20

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

AE9

=PP1V05_S0M_PCH_VCCASW

AF9

473mA Max[1]

AG8

AD10

NC

AD8

NC

J15

=PP1V5_S0_PCH_VCCTS

3mA Max

K14

=PP3V3_S0_PCH_VCCTS

K16

1mA Max[1]

U8

=PP3V3R1V8_S0_PCH_VCCSDIO

T9

17mA Max

AB8

NC

AC20

AG16
AG17

WF: RSVD on Sawtooth Peak rev 1.0

NC

=PP1V05_S0_PCH_VCCIO_USB2

213mA Max[1]

R0800

75

1%

1/20W

MF

201

R0811

0

1 2

5%

1/20W

MF

0201

11 68

BYPASS=U0500.AE7::6.35mm

11 14 68

8

11 68

Powered in DeepSx

8

68

11 68

11 40 68

11 68

1

2

11 68

11 68

R0810

1 2

R0812

1 2

1

R0802

130

1%
1/20W
MF
201

2

43

5%

1/20W

MF

201

0

5%

1/20W

MF

0201

1

C0895

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=U0500.AG19:2.54MM

R0899

5.11

1 2

1%
1/20W
MF-LF

201

PLACE_NEAR=U0500.C50:50.8mm

Max load: 300mA

Max load: 300mA

R0802.2:

PLACE_NEAR=U0500.L63:2.54mm

R0810.2:

PLACE_NEAR=U0500.L62:38.1mm

R0800.2:

PLACE_NEAR=R0810.1:2.54mm

1

C0892

0.1UF

PPVOUT_S5_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

20%
10V

CERM

402

C0891

0.1UF

2

BYPASS=U0500.AG10::6.35mm

CPU_VCCSENSE_P

55 73

OUT

TP_PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

PPVCOMP_S0_CPU

5

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

NOTE: Aliases not used on CPU supply outputs
to avoid any extraneous connections.

=PPVRTC_G3_PCH

1

1

C0890

20%
10V

CERM

402

1UF

10%

6.3V

2

2

CERM
402

BYPASS=U0500.AG10::6.35mm

BYPASS=U0500.AG10::6.35mm

1

C0899

1UF

10%

6.3V

2

CERM
402

BYPASS=R0899:U0500:2.54mm

1/20W

201

5%
MF

2

CPU_VIDALERT_R_L

73

CPU_VIDSCLK_R

73

CPU_VIDSOUT_R

73

CPU_VCCST_PWRGD

16 17 73

IN

CPU_VR_EN

17 55

OUT

CPU_VR_READY

17

IN

CPU_PWR_DEBUG

16

IN

TP_CPU_RSVD_P60
TP_CPU_RSVD_P61

18

TP_CPU_RSVD_N59
TP_CPU_RSVD_N61

18

=PP1V05_S0_CPU_VCCST

6 8

15 16 17 55 68

???mA Max

12 13 68

6 3

L59
J58

AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

F59
N58

AC58

E63

AB23

A59

E20
AD23
AA23
AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59
AD60
AD59
AA59
AE60
AC59
AG58

U59

V59

AC22
AE22
AE23

AB57
AD57
AG57

C24

C28

C32

RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VCC
RSVD
RSVD

VCC_SENSE

RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD

VIDALERT*
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

VSS
PWR_DEBUG*
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCST
VCCST
VCCST

VCC
VCC
VCC
VCC
VCC
VCC

NC
NC

NC
NC

NC

NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC

BOM_COST_GROUP=CPU

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 12 OF 19

HSW ULT POWER

SYNC_MASTER=J41

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

32A Max

=PPVCC_S0_CPU

C36

CPU & PCH Power

Apple Inc.

R

12

8

10 44 68

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

8 OF 120

SHEET

8 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SYM 14 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29

AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49

AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63

AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

A11
A14
A18
A24
A28

D

C

B

A32
A36
A40
A44
A48
A52
A56

AA1
AA58
AB10
AB20
AB22

AB7
AC61
AD21

AD3
AD63
AE10

AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18

AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

BROADWELL-ULT

VSS
VSS
VSS
VSS

AP3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AR5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AU1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

OMIT_TABLE

CRITICAL

U0500

2C+GT2

BGA

SYM 15 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

BROADWELL-ULT

D33

VSS

D34

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D5

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

D8

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

H13

VSS

OMIT_TABLE

CRITICAL

U0500

2C+GT2

BGA

SYM 16 OF 19

VSS_SENSE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

V58
AH46
V23
E62
AH16

CPU_VCCSENSE_N

1

R0960

100

5%

PLACE_NEAR=U0500.E62:50.8mm

1/20W
MF
201

2

D

C

55 73

OUT

B

A

BOM_COST_GROUP=CPU

6 3

SYNC_MASTER=J41

PAGE TITLE

CPU & PCH Grounds

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

9 OF 120

SHEET

9 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 0.9 unless stated otherwise

CPU VCC Decoupling

=PPVCC_S0_CPU

8

44 68

D

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff
Apple implementation : 18x 22uF 0603 stuff, 80x 22uF 0603 nostuff

CRITICAL

1

C1000

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1001

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1002

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1003

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1018

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1004

10UF

20%
4V 4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1019

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1020

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1021

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1030

12PF

2% 2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1008

10UF

20%

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1009

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL CRITICAL

1

C1010

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1011

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1012

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL CRITICAL

1

C104E

12PF

50V

2

C0G-CERM
0402

1

C104F

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1014

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C105A

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C105B

10UF

20%
4V

2

X6S

0402

NO STUFF

CRITICAL

1

C105C

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C106D

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C105D

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C106E

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C105E

10UF

20%
4V

2

X6S
0402

NO STUFF

12

CRITICAL

1

C105F

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

D

CRITICAL

1

C1070

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1085

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C

B

C1022

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

NO STUFF

1

C1039

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1056

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C109B

10UF

20%
4V

2

X6S
0402

CRITICAL

1

C1031

470UF-0.0045OHM

20%

2.5V

23

POLY-TANT
SM

CRITICAL

1

C1086

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1023

12PF

2%
50V

2

C0G-CERM
0402

1

C1044

12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C1057

10UF

20%
4V

2

X6S
0402

1

C109C

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1072

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1087

12PF

2%
50V

2

C0G-CERM
0402

1

C1024

12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C1045

10UF

20%
4V

2

X6S
0402

1

C1058

12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C109D

10UF

20%
4V

2

X6S
0402

CRITICAL

1

C1073

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1088

10UF

20%
4V

2

X6S
0402

NO STUFF

NO STUFF

1

C1025

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1046

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1059

10UF

20%
4V

2

X6S
0402

1

C109E

12PF

2%
50V

2

C0G-CERM
0402

PART NUMBER

138S0942

CRITICAL

1

C1074

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1089

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1026

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

NO STUFF

1

C1047

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1062

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C109F

10UF

20%
4V

2

X6S
0402

QTY

18

CRITICAL

1

C1075

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1090

10UF

20%
4V

2

X6S
0402

NO STUFF

NO STUFF

1

C1027

10UF

20%
4V

2

0402

NO STUFF

1

C1048

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1063

10UF

20%
4V

2

X6S
0402

1

C108A

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1091

12PF

50V

2

C0G-CERM
0402

NO STUFF

1

C1028

10UF

20%
4V

2

X6SX6S
0402

1

C1049

12PF

2%
50V

2

C0G-CERM
0402

1

C1064

12PF

2%
50V

2

C0G-CERM
0402

1

C108B

12PF

2%
50V

2

C0G-CERM
0402

DESCRIPTION

CAP,CER,10UF,20%,4V,X6S,HRZTL,0402

CRITICAL

1

C1077

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1092

12PF

2%2%
50V

2

C0G-CERM
0402

NO STUFF

1

C1029

10UF

20%
4V

2

X6S
0402

CRITICAL

1

C1065

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

NO STUFF

1

C108C

10UF

20%
4V

2

X6S
0402

REFERENCE DES

CRITICAL

1

C1093

12PF

2%
50V

2

C0G-CERM

NO STUFF

1

C1032

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1066

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C108D

10UF

20%
4V

2

X6S
0402

1

2

1

2

1

2

1

2

CRITICAL

CRITICAL

CRITICAL

C1094

12PF

2%
50V
C0G-CERM
04020402

C1033

12PF

2%
50V
C0G-CERM
0402

NO STUFF

C1067

10UF

20%
4V
X6S
0402

NO STUFF

C108E

10UF

20%
4V
X6S
0402

CRITICAL

1

C1095

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1034

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

1

C1068

12PF

2%
50V

2

C0G-CERM
0402

1

C108F

12PF

2%
50V

2

C0G-CERM
0402

BOM OPTION

CRITICAL

1

C1081

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1096

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1035

2%
50V

2

C0G-CERM
0402

1

C1069

12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C107A

10UF

20%
4V

2

X6S
0402

C1000,C1004,C1008,C1012,C1018,C1019,C1020,C1022,C1026,C1034,C1065,C1070,C1074,C105A,C105C,C105D,C104F,C105F

CRITICAL

1

C1082

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1097

12PF

2%
50V

2

C0G-CERM
0402

1

C1036

12PF12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C1098

10UF

20%
4V

2

X6S
0402

1

C107B

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1083

12PF

2%
50V

2

C0G-CERM
0402

1

C1037

12PF

2%
50V

2

C0G-CERM
0402

1

C1099

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1084

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1038

12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C109A

10UF

20%
4V

2

X6S
0402

C

B

CPU VDDQ DECOUPLING

=PPVMEMIO_S0_CPU

8

68

Intel recommendation (Table 5-4): 2x 2.2uF 0402, 6x 10uF 0603
Apple implementation : 2x 2.2uF 0402, 6x 10uF 0402

CPU VCC Decoupling

1

C1040

2.2UF 2.2UF

20%

6.3V

2

CERM
402-LF

1

C1050

10UF

20%

6.3V

2

A

CERM-X5R
0402-1

OMIT_TABLE

1

C1060

270UF

20%
2V

2

TANT
CASE-B2-SM

1

C1041

20%

6.3V

2

CERM
402-LF

1

C1051

10UF

20%

6.3V

2

CERM-X5R
0402-1

OMIT_TABLE

NO STUFF

1

C1061

270UF

20%
2V

2

TANT
CASE-B2-SM

1

C1042

2.2UF

20%

6.3V

2

CERM
402-LF

1

C1052

10UF

20%

6.3V

2

CERM-X5R

0402-1

OMIT_TABLE

1x Bulk nostuff, Harris Beach has 2x nostuff

1

C1043

2.2UF

20%

6.3V

2

CERM
402-LF

1

C1053

10UF

20%

6.3V

2

CERM-X5R
0402-1

OMIT_TABLE

PART NUMBER

138S0801

Added 2 extra 2.2uF per Harris Beach v0.9 schematic

1

C1054

10UF

20%

6.3V

2

CERM-X5R
0402-1

OMIT_TABLE

QTY

6

6 3

1

C1055

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1079

12PF

5%
25V

2

NP0-C0G
0201

OMIT_TABLE

DESCRIPTION

CAP,CER,10UF,20%,6.3V,HRZTL,0402

NOTE: 38X capacitors are STUFFED and have been changed to 12pF for Noise Floor Reasons (Radar # 17754026).

1

C1080

12PF

5%
25V

2

NP0-C0G
0201

REFERENCE DES

CRITICAL

CRITICAL

BOM OPTION

C1050,C1051,C1052,C1053,C1054,C1055

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

10 OF 120

SHEET

10 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

PCH VCCASW BYPASS
PCH VCCDSW3_3 BYPASS
(PCH 3.3V DSW PWR)

=PP3V3_S5_PCH_VCCDSW

8

68

PCH VCCSPI BYPASS

D

(PCH 3.3V SPI PWR)

=PP3V3_SUS_PCH_VCC_SPI

8

14 68

PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND PWR)

=PP3V3_SUS_PCH_VCCSUS_GPIO

8

68

PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND RTC PWR)

=PP3V3_SUS_PCH_VCCSUS_RTC

8

68

C

PCH VCCSDIO BYPASS
(PCH 3.3V/1.8V SDIO PWR)

=PP3V3R1V8_S0_PCH_VCCSDIO

8

40 68

NO STUFF

C1200

BYPASS=U0500.AH10::6.35mm

NO STUFF

C1202

0.1UF

BYPASS=U0500.Y8::6.35mm

C1204

22UF

X5R-CERM-1

BYPASS=U0500.AC9::12.7mm

C1206

BYPASS=U0500.AH11::6.35mm

C1208

BYPASS=U0500.U8::6.35mm

1UF

6.3V
CERM

CERM

6.3V

1UF

6.3V
CERM

1UF

6.3V
CERM

10%

402

20%
10V

402

20%

603

10%

402

10%
402

1

2

1

2

1

2

1

2

1

2

PCH VCC3_3 BYPASS
(PCH 3.3V GPIO/LPC PWR)

=PP3V3_S0_PCH_VCC3_3_GPIO =PP1V05_S0_PCH_VCCIO_USB2

8

68

1

C1212

22UF

20%

6.3V

C1214

0.1UF

CERM

603

20%
10V

402

2

1

2

R1270

0

1 2

1/16W
MF-LF

PP1V05_S0_PCH_VCCACLKPLL_R

MIN_LINE_WIDTH=0.2 MM

5%

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

402

PCH VCC3_3 BYPASS
(PCH 3.3V THERMAL PWR)

=PP3V3_S0_PCH_VCCTS

8

68

68

X5R-CERM-1

BYPASS=U0500.V8::12.7mm

BYPASS=U0500.K14::6.35mm

=PP1V05_S0_PCH_PLLFILTERS

??mA Max

(PCH 1.05V ME CORE PWR)

=PP1V05_S0M_PCH_VCCASW

8

68

BYPASS=U0500.AE9::12.7mm

PCH VCC BYPASS

(PCH 1.05V CORE PWR)

=PP1V05_S0_PCH_VCC

8

68

BYPASS=U0500.J11::12.7mm

PCH VCCHSIO BYPASS

(PCH 1.05V PCIe/SATA/USB3 PWR)

=PP1V05_S0SW_PCH_VCCHSIO

8

68

BYPASS=U0500.K9::6.35mm

2.2UH-240MA-0.221OHM

NO STUFF

C1250

22UF

20%

6.3V

X5R-CERM-1

603

BYPASS=U0500.AE9::6.35mm

C1255

10UF

20%

6.3V
X5R
603

BYPASS=U0500.J11::6.35mm

C1260

1UF

10%

6.3V

CERM

402

BYPASS=U0500.L10::6.35mm

CRITICAL

L1270

1 2

0603

C1270

47UF

20%
X6S

BYPASS=U0500.A20::12.7mm

0805

1

1

C1251

1UF

10%

6.3V

2

2

CERM
402

1

1

C1256

1UF

10%

6.3V

2

2

CERM
402

BYPASS=U0500.AE8::6.35mm

1

C1261

1UF

10%

6.3V

2

CERM

402

BYPASS=U0500.M9::6.35mm

1

C1271

47UF

4V

BYPASS=U0500.A20::12.7mm

20%

2

X6S

0805

BYPASS=U0500.A20::6.35mm

1

C1257

1UF

10%

6.3V

2

CERM
402

1

1

C1262

10UF

20%

6.3V

2

2

CERM-X5R
0402-1

OMIT_TABLE

PCH VCCACLKPLL FILTER/BYPASS
(PCH 1.05V ACLK PLL PWR)

PP1V05_S0_PCH_VCCACLKPLL

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

1

C1272

1UF

4V

10%
10V

2

2

X5R
402

68

68

31mA Max

PCH VCCIO BYPASS
(PCH 1.05V USB2 PWR)

8

BYPASS=U0500.AG16::6.35mm

PCH VCCCLK BYPASS
(PCH 1.05V CLK PWR)

=PP1V05_S0_PCH_VCCCLK

8

C1266

1UF

6.3V
CERM

BYPASS=U0500.J17::6.35mm

8

12

C1264

1UF

6.3V
CERM

1

C1267

10%
402

BYPASS=U0500.R21::6.35mm

1UF

6.3V

2

CERM

10%

402

10%
402

1

2

D

1

2

C

PCH VCCSUSHDA BYPASS
(PCH 3.3V/1.5V HDA PWR)

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

8

17 63

BYPASS=U0500.AH14::6.35mm

B

A

PART NUMBER

QTY

1

Wildcat Point-LP current estimates from Wildcat Point-LP PCH EDS, Doc# 515621, Rev. 0.9

as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

DESCRIPTION

CAP,CER,10UF,20%,6.3V,HRZTL,0402

C1210

1UF

10%

6.3V
CERM

402

REFERENCE DES

1

2

C1262

CRITICAL

CRITICAL138S0801

CRITICAL

L1275

2.2UH-240MA-0.221OHM

1 2

0603

C1275

BYPASS=U0500.J18::12.7mm

PCH OPI VCCAPLL FILTER/BYPASS
(PCH 1.05V OPI PLL PWR)

PP1V05_S0_PCH_VCCAPLL_OPI

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

1

C1282

1UF

10%
10V

2

2

X5R
402

PCH VCCSATA3PLL FILTER/BYPASS
(PCH 1.05V SATA3 PLL PWR)

PP1V05_S0SW_PCH_VCCSATA3PLL

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

1

C1292

1UF

10%
10V

2

2

X5R
402

PCH VCCUSB3PLL FILTER/BYPASS
(PCH 1.05V USB3 PLL PWR)

PP1V05_S0SW_PCH_VCCUSB3PLL

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

C1297

1UF

10%
10V

2

X5R
402

1

47UF

C1276

20%

4V

2

X6S

0805

BYPASS=U0500.J18::12.7mm

BYPASS=U0500.J18::6.35mm

47UF

20%
X6S

0805

57mA Max

41mA Max

BOM OPTION

R1275

0

1 2

1/16W
MF-LF

R1280

1 2

1/16W
MF-LF

2.2UH-240MA-0.221OHM

=PP1V05_S0SW_PCH_VCCPLL_HSIO

68

83mA Max 42mA Max

2.2UH-240MA-0.221OHM

2.2UH-240MA-0.221OHM

BYPASS=U0500.B18::12.7mm

PP1V05_S0_PCH_VCC_ICC_R

MIN_LINE_WIDTH=0.2 MM

5%

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

402

0

5%

CRITICAL

402

NO STUFF

L1280

1 2

0603

NO STUFF

C1280

47UF

CERM-X5R

BYPASS=U0500.AA21::12.7mm

BYPASS=U0500.B11::12.7mm

0805-1

CRITICAL

L1290

1 2

0603

C1290

47UF

0805

CRITICAL

L1295

1 2

0603

C1295

47UF

0805

NO STUFF

1

C1281

20%

4V

BYPASS=U0500.AA21::12.7mm

20%

4V

X6S

BYPASS=U0500.B11::12.7mm

20%

4V

X6S

47UF

20%

2

CERM-X5R

0805-1

BYPASS=U0500.AA21::6.35mm

NO STUFF

1

C1291

47UF

20%

2

CERM-X5R

0805-1

BYPASS=U0500.B11::6.35mm

1

2

BYPASS=U0500.B18::6.35mm

4V

4V

6 3

PCH VCCCLK FILTER/BYPASS
(PCH 1.05V VCCCLK PWR)

PP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

1

C1277

1UF

4V

10%
10V

2

2

X5R
402

??mA Max

8

B

8

8

12

SIZE

A

D

SYNC_MASTER=J41

8

14

BOM_COST_GROUP=CPU

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PCH Decoupling

Apple Inc.

R

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

12 OF 120

SHEET

11 OF 82

124578

8 7 6 5 4 3

=PPVRTC_G3_PCH

8

13 68

OMIT_TABLE

BROADWELL-ULT

(IPD)

(IPD)

(IPU)

(IPU)

CRITICAL

U0500

2C+GT2

BGA

SYM 5 OF 19

RTC

AUDIO

JTAG

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

(IPU)

SATA_IREF

SATA_RCOMP

RSVD

RSVD

J5
H5

B15
A15

J8
H8

A17
B17

J6
H6

B14
C15

F5
E5

C17
D17

V1
U1
V6
AC1

A12

L11
K10

C12

U3

PCIE_SSD_D2R_N<3>
PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_C_N<3>
PCIE_SSD_R2D_C_P<3>

PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<2>
PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_C_N<0>
PCIE_SSD_R2D_C_P<0>

XDP_SSD_PCIE3_SEL_L
XDP_SSD_PCIE2_SEL_L
XDP_SSD_PCIE1_SEL_L
XDP_SSD_PCIE0_SEL_L

NC
NC

PCH_SATA_RCOMP

75

PCH_SATALED_L

PCIe Port assignments:

32 71 81

IN

32 71 81

IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN
IN

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

16

16

16

16

SSD Lane 3

SSD Lane 2

SSD Lane 1

SSD Lane 0

PP1V05_S0SW_PCH_VCCSATA3PLL

1

R1370

3.01K

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.C12:2.54mm

12

SATA Port assignments:

Primary HDD/SSD

Reserved: ODD

Unused

Secondary HDD/SSD

8

11

1

1

R1300

1/20W

20K

1

R1303

20K

5%

5%
1/20W

MF

201

MF
201

2

2

R1302

D

1

C1300

1UF

10%
10V
X5R
402

1

C1303

1UF

10%
10V

2

2

X5R
402

C

330K

1/20W

5%

MF

201

2

49 75

OUT

49 75

OUT

49 75

OUT

49 75

OUT

1

R1301

1M

5%
1/20W
MF
201

2

PCH_INTRUDER_L

75

PCH_INTVRMEN

75

PCH_SRTCRST_L

75

RTC_RESET_L

75

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDOUT

R1310

R1311

R1312

R1313

PCH_CLK32K_RTCX1

17 75

IN

PCH_CLK32K_RTCX2

17

OUT

33

1 2

33

1 2

1 2

33

1 2

HDA_BIT_CLK_R

75

MF

5%

1/20W

PLACE_NEAR=U0500.AW8:1.27mm

HDA_SYNC_R

75

1/20W

5%

PLACE_NEAR=U0500.AV11:1.27mm

HDA_RST_R_L

75

1/20W

5% MF33201

PLACE_NEAR=U0500.AU8:1.27mm

HDA_SDIN0

49 71 75

IN

TP_HDA_SDIN1

69

HDA_SDOUT_R

17 75

1/20W

PLACE_NEAR=U0500.AU11:1.27mm

TP_PCH_I2S1_TXD

69

TP_PCH_I2S1_SFRM

69

TP_PCH_I2S1_SCLK

69

XDP_PCH_TRST_L

16

IN

XDP_PCH_TCK

16 73

IN IN

XDP_PCH_TDI

16 73

IN

XDP_PCH_TDO

16 73

OUT

XDP_PCH_TMS

16 73

IN

PCH_JTAGX

16 73

BI

201

MF

201

MF5%

201

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER*

AV7

INTVRMEN

AV6

SRTCRST*

AU7

RTCRST*

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

AY10
AU12

AU11

AW10
AV10

AY8

AU62
AE62
AD61
AE61
AD62
AL11

NC

AC4

NC

AE63

AV2

NC

(IPD-PLTRST#)

HDA_RST*/I2S_MCLK

HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

(IPD-PLTRST#)

HDA_DOCK_EN*/I2S1_TXD
HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

PCH_TRST*

PCH_TCK

PCH_TDI

PCH_TDO

PCH_TMS

RSVD

RSVD

JTAGX

RSVD SATALED*

12

D

C

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

TP_PCIE_CLK100M_ENETSDN

69

TP_PCIE_CLK100M_ENETSDP

69

ENETSD_CLKREQ_L

12 71

PCIE_CLK100M_CAMERA_N

34 71 81

OUT

PCIE_CLK100M_CAMERA_P

34 71 81

OUT

CAMERA_CLKREQ_L

12 33

IN

PCIE_CLK100M_AP_N

66 71 81

B

OUT

66 71 81

OUT

12 66

IN

69

69

12

25 71 81

OUT

25 71 81

OUT

12 25

IN

32 71 81

OUT

32 71 81

OUT

12 32

IN

PCIE_CLK100M_AP_P

AP_CLKREQ_L

TP_PCIE_CLK100M_FWN
TP_PCIE_CLK100M_FWP

FW_CLKREQ_L

PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P

SSD_CLKREQ_L

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0*/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1*/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2*/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3*/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4*/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5*/GPIO23

A

=PP3V3_S0_PCH_GPIO

R1375
R1340

R1341
R1342
R1343
R1344
R1345

100K

100K
100K

20K
100K
100K

10K

1 2

1 2

1 2

1 2
1 2

1 2

1 2

13 15 18 26 65 68

5% MF

1/20W

5%

1/20W

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W

MF

MF
MF

MF5%

MF

PCH_SATALED_L

201

ENETSD_CLKREQ_L

201

CAMERA_CLKREQ_L

201

AP_CLKREQ_L

201

FW_CLKREQ_L

201

TBT_CLKREQ_L

201

SSD_CLKREQ_L

201

12

12 71

12 33

12 66

12

12 25

12 32

6 3

SYM 6 OF 19

XTAL24_IN

XTAL24_OUT

CLOCK SIGNALS

RSVD
RSVD

DIFFCLK_BIASREF

TESTLOW
TESTLOW
TESTLOW
TESTLOW

CLKOUT_LPC_0

CLKOUT_LPC_1

(IPD-PWROK)

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

A25
B25

K21
M21

C26

C35
C34
AK8
AL8

AN15
AP15

B35
A35

PCH_CLK24M_XTALIN
PCH_CLK24M_XTALOUT

NC
NC

PCH_DIFFCLK_BIASREF

PCH_TESTLOW_C35
PCH_TESTLOW_C34
PCH_TESTLOW_AK8
PCH_TESTLOW_AL8

LPC_CLK24M_SMC_R

17 75

IN

17 75

OUT

PP1V05_S0_PCH_VCCACLKPLL

1

R1380

3.01K

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.C26:2.54mm

10K

R1390
R1391
R1392
R1393

OUT

17 75

10K
10K
10K

1 2
1 2

1 2

1 2

8

11

B

MF5%

1/20W

5%

1/20W

1/20W

5%
5%

1/20W

201

201

MF

MF

201

MF

201

TP_LPC_CLK24M_LPCPLUS

TP_ITPXDP_CLK100MN
TP_ITPXDP_CLK100MP

69

69

SIZE

A

D

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

PAGE TITLE

PCH Audio/JTAG/SATA/CLK

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/17/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

13 OF 120

SHEET

12 OF 82

124578

8 7 6 5 4 3

12

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

D

SLP_S0# Isolation

=PP3V3_S0_PCH_GPIO

12 13 15 18 26 65 68

1

C1420

0.1UF

10%
10V

2

X5R-CERM
0201

6

2

08

1

NC

3

5

13 18 38

OUT

PM_SLP_S0_L

CRITICAL

74LVC1G08

SOT891

4

U1420

R1400 kept for debug purposes.

40

IN

NO STUFF

R1400

1/20W

0201

40

OUT

1

0

5%
MF

2

17 38 71 75

IN

16 17 38 75

IN

17 75

IN

17

IN

15 16 18

OUT

64 75

IN

13 16 38 75

IN

38 39

IN

13 27 38

IN

69

PCH_SUSACK_L
PM_SYSRST_L
PM_PCH_SYS_PWROK
PM_PCH_PWROK
PM_PCH_APWROK
PLT_RESET_L
PM_RSMRST_L
PCH_SUSWARN_L
PM_PWRBTN_L
SMC_ADAPTER_EN
PM_BATLOW_L
PCH_PM_SLP_S0_L
TP_PCH_SLP_WLAN_L

AK2

SUSACK*

AC3

SYS_RESET*

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST*

AW6

RSMRST*

AV4

SUSWARN*/SUSPWRDNACK/GPIO30

AL7

PWRBTN*

AJ8

ACPRESENT/GPIO31

AN4

BATLOW*/GPIO72

SLP_S0*

AM5

SLP_WLAN*/GPIO29

SYM 8 OF 19

SYSTEM POWER MANAGEMENT

(IPU)

(IPD-DeepSx)

(IPU)

(IPD-DeepSx)

DSWVRMEN

DPWROK

WAKE*

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

AW7
AV5
AJ5
V5
AG4
AE6
AP5
AJ6
AT4
AL5
AP4
AJ7AF3

PCH_DSWVRMEN

75

PM_DSW_PWRGD
PCIE_WAKE_L
PM_CLKRUN_L
LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
TP_PM_SLP_A_L
PM_SLP_SUS_L
TP_PCH_SLP_LAN_L

13 31 33 75

IN

13 38 71

BI

38 71

OUT

39

OUT

13 38 64

OUT

13 18 31 37 38 64 66

OUT

13 17 18 38 64 66 71

OUT

71

13 64

OUT

69

=PPVRTC_G3_PCH

1

R1450

330K

5%
1/20W
MF
201

2

38 75

IN

1

R1451

100K

5%
1/20W
MF
201

2

8

12 68

D

NC

SLP_S0# can be driven high outside of S0
U1420 ensures signal will only be high in S0.

C

AD4

B8
A9
C6

U6
P4
N4
N2

U7
L1
L3
R5
L4

EDP_BKLCTL

EDP_BKLEN

EDP_VDDEN

PIRQA*/GPIO77
PIRQB*/GPIO78
PIRQC*/GPIO79
PIRQD*/GPIO80

PME*

GPIO55
GPIO52
GPIO54
GPIO51
GPIO53

EDP_BKLT_PWM

65 71

OUT

EDP_BKLT_EN

13 65

OUT

EDP_PANEL_PWR

13 65

OUT

TBT_PWR_REQ_L

13 26

IN

SMC_RUNTIME_SCI_L

13 38

IN

AUD_IP_PERIPHERAL_DET

13 71

IN

SSD_BOOT

13 32

OUT

TP_PCI_PME_L

69

ODD_PWR_EN_L

13 71

OUT

DP_AUXCH_ISOL_L

13 69

OUT

ENET_LOW_PWR

13 71

OUT

AUD_PWR_EN

13 64

OUT

AUD_IPHS_SWITCH_EN

13 71

OUT

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

SYM 9 OF 19

(IPU)

BGA

eDP

SIDEBAND

PCI

DDPB_CTRLCLK

DDPB_CTRLDATA

(IPD-PLTRST#)

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DISPLAY

DDPB_AUXN
DDPC_AUXN

DDPB_AUXP
DDPC_AUXP

DDPB_HPD

DDPC_HPD

EDP_HPD

B9
C9

D9
D11

C5
B6

B5
A6

C8
A8
D6

DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA

=DP_TBTSNK1_DDC_CLK
=DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_AUXCH_C_N
=DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P
=DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK0_HPD
=DP_TBTSNK1_HPD
DP_INT_HPD

C

30

OUT

30

BI

69

OUT

69

BI

25 77

BI

69

BI

25 77

BI

69

BI

25

IN

69

IN

65

IN

SIZE

B

A

D

B

=PP3V3_S5_PCH_GPIO
=PP3V3_S0_PCH_GPIO

R1405
R1410
R1452
R1455
R1460

R1461
R1462
R1463
R1464

R1430

A

R1431
R1440

R1441
R1442
R1443

R1445
R1446
R1447
R1448
R1449

1K
10K
10K
10K

100K
100K
100K
100K
100K

100K
100K

100K

10K

100K
100K

100K
100K
100K
100K
100K

1 2

1 2

1 2

1 2

1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2

15 68

12 13 15 18 26 65 68

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

5%

1/20W
1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W
1/20W

5%

1/20W

1/20W
1/20W

5%

1/20W
1/20W
1/20W

PM_PWRBTN_L

MF

201

PM_BATLOW_L

MF

201

PCIE_WAKE_L

MF

201

PM_CLKRUN_L

MF

201

PM_SLP_S5_L

MF

201

PM_SLP_S4_L

MF

201

PM_SLP_S3_L

201

MF

PM_SLP_S0_L

201

MF

PM_SLP_SUS_L

201

MF

EDP_BKLT_EN

201

MF

EDP_PANEL_PWR

201

MF

TBT_PWR_REQ_L

MF

2015%

SMC_RUNTIME_SCI_L

MF

201

AUD_IP_PERIPHERAL_DET

MF 2015%

SSD_BOOT

201

MF

ODD_PWR_EN_L

MF

2015%

DP_AUXCH_ISOL_L

MF 201

ENET_LOW_PWR

MF5% 201

AUD_PWR_EN

MF

2015%

AUD_IPHS_SWITCH_EN

MF

2015%

13 16 38 75

13 27 38

13 31 33 75

13 38 71

13 38 64

13 18 31 37 38 64 66

13 17 18 38 64 66 71

13 18 38

13 64

13 65

13 65

13 26

13 38

13 71

13 32

13 71

13 69

13 71

13 64

13 71

6 3

BOM_COST_GROUP=CPU

PAGE TITLE

PCH PM/PCI/GFX

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/21/2013SYNC_MASTER=J41

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

SHEET

124578

8.0.0
dvt1

14 OF 120

13 OF 82

8 7 6 5 4 3

12

PCIe Port Assignments:

Thunderbolt lane 0

D

C

38 71 75

38 71 75

B

38 71 75

38 71 75

38 71 75

Thunderbolt lane 1

Thunderbolt lane 2

Thunderbolt lane 3

AirPort

Reserved: FireWire

SD Card Reader
(& Ethernet if combo)

Camera

LPC_AD<0>

BI

LPC_AD<1>

BI

LPC_AD<2>

BI

LPC_AD<3>

BI

LPC_FRAME_L

OUT

PP1V05_S0SW_PCH_VCCUSB3PLL

8

11

PLACE_NEAR=U0500.A27:2.54mm

R1540
R1541
R1542
R1543

R1544

33
33
33
33

33

1 2
1 2
1 2
1 2

1 2

R1500

3.01K

1/20W

201

5% 201MF
5% 201MF
5% 201MF
5% 201MF

5% 201MF

PCIE_TBT_D2R_N<0>

25 71 81

IN

PCIE_TBT_D2R_P<0>

25 71 81

IN

PCIE_TBT_R2D_C_N<0>

25 71 81

OUT

PCIE_TBT_R2D_C_P<0>

25 71 81

OUT

PCIE_TBT_D2R_N<1>

25 71 81

IN

PCIE_TBT_D2R_P<1>

25 71 81

IN

PCIE_TBT_R2D_C_N<1>

25 71 81

OUT

PCIE_TBT_R2D_C_P<1>

25 71 81

OUT

PCIE_TBT_D2R_N<2>

25 71 81

IN

PCIE_TBT_D2R_P<2>

25 71 81

IN

PCIE_TBT_R2D_C_N<2>

25 71 81

OUT

PCIE_TBT_R2D_C_P<2>

25 71 81

OUT

PCIE_TBT_D2R_N<3>

25 71 81

IN

PCIE_TBT_D2R_P<3>

25 71 81

IN

PCIE_TBT_R2D_C_N<3>

25 71 81

OUT

PCIE_TBT_R2D_C_P<3>

25 71 81

OUT

PCIE_AP_D2R_N

66 71 81

IN

PCIE_AP_D2R_P

66 71 81

IN

PCIE_AP_R2D_C_N

66 71 81

OUT

PCIE_AP_R2D_C_P

66 71 81

OUT

TP_PCIE_FW_D2RN

69

TP_PCIE_FW_D2RP

69

TP_PCIE_FW_R2D_CN

69

TP_PCIE_FW_R2D_CP

69

USB3RPCIE_SD_D2R_N

66 71 74

IN

USB3RPCIE_SD_D2R_P

66 71 74

IN

USB3RPCIE_SD_R2D_C_N

66 74

OUT

USB3RPCIE_SD_R2D_C_P

66 74

OUT

PCIE_CAMERA_D2R_N

34 71 81

IN

PCIE_CAMERA_D2R_P

34 71 81

IN

PCIE_CAMERA_R2D_C_N

34 81

OUT

PCIE_CAMERA_R2D_C_P

34 81

OUT

PCH_PCIE_RCOMP

75

1

1%
MF

2

1/20W
1/20W
1/20W
1/20W

1/20W

47 75

47 75

47 75

47 75

14 47 75

14 47 75

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

LPC_FRAME_R_L

SPI_CLK_R

OUT

SPI_CS0_R_L

OUT

TP_SPI_CS1_L

69

TP_SPI_CS2_L

69

SPI_MOSI_R

BI

SPI_MISO

BI

SPI_IO<2>

BI

SPI_IO<3>

BI

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

AU14
AW12
AY12
AW11

AV12

AA3

AC2

AA2

AA4

AF1

E13
A27

Y7

Y4

Y6

RSVD
RSVD
PCIE_RCOMP
PCIE_IREF

(IPU)

LAD0
LAD1
LAD2
LAD3

LFRAME*

SPI_CLK

SPI_CS0*

SPI_CS1*

SPI_CS2*

SPI_MOSI

(IPU/IPD)

SPI_MISO

SPI_IO2

(IPU)

SPI_IO3

(IPU)

NC
NC

OMIT_TABLE

CRITICAL

BROADWELL-ULT

SYM 11 OF 19

OMIT_TABLE

CRITICAL

BROADWELL-ULT

SYM 7 OF 19

LPC

SMBUS

(IPU)

SML1ALERT*/PCHHOT*/GPIO73

(IPU)

(IPU)

(IPU)

SPI

(IPU)

C-LINK

U0500

2C+GT2

BGA

USB

PCI-E

U0500

2C+GT2

BGA

SML0ALERT*/GPIO60

(IPU/IPD)

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

(IPD)

USB3RN1
USB3RP1

USB3TN1
USB3TP1

USB3RN2
USB3RP2

USB3TN2
USB3TP2

USBRBIAS*

USBRBIAS

RSVD
RSVD

OC0*/GPIO40
OC1*/GPIO41
OC2*/GPIO42
OC3*/GPIO43

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1DATA/GPIO74

(IPU/IPD)

CL_CLK

CL_DATA

CL_RST*

AN8
AM8

AR7
AT7

AR8
AP8

AR10
AT10

AM15
AL15

AM13
AN13

AP11
AN11

AR13
AP13

G20
H20

C33
B34

E18
F18

B33
A33

AJ10
AJ11

AN10
AM10

AL3
AT1
AH2
AV3B27

AN2

AP2
AH1

AL2

AN1
AK1

AU4

AU3
AH3

AF2

AD2

AF4

USB_EXTA_N
USB_EXTA_P

USB_EXTB_N
USB_EXTB_P

USB_BT_N
USB_BT_P

USB_IR_N
USB_IR_P

USB_TPAD_N
USB_TPAD_P

TP_USB_5N
TP_USB_5P

TP_USB_CAMERAN
TP_USB_CAMERAP

TP_USB_SDN
TP_USB_SDP

USB3_EXTA_D2R_N
USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_N
USB3_EXTB_D2R_P

USB3_EXTB_R2D_C_N
USB3_EXTB_R2D_C_P

PCH_USB_RBIAS

74

NC
NC

XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L

PCH_SMBALERT_L
SMBUS_PCH_CLK

SMBUS_PCH_DATA

WOL_EN
SML_PCH_0_CLK

SML_PCH_0_DATA

PCH_SML1ALERT_L
SML_PCH_1_CLK

SML_PCH_1_DATA

TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L

35 74

BI

35 74

BI

66 74

BI

66 74

BI

31 74

BI

31 74

BI

69

BI

69

BI

36 71 74

BI

36 71 74

BI

69

69

69

69

69

69

35 71 74

IN

35 71 74

IN

35 71 74

OUT

35 71 74

OUT

66 71 74

IN

66 71 74

IN

66 71 74

OUT

66 71 74

OUT

14 16

IN

14 16

IN

14 16

IN

14 16

IN

14

41 71 75

OUT

41 71 75

BI

14 71

OUT

41 75

OUT

41 75

BI

40

OUT

41 75

OUT

41 75

BI

69

69

69

USB Port Assignments:

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

BT

IR

Trackpad

Unused

Reserved: Camera

Reserved: SD (HS)

USB3 Port Assignments:

Ext A (SS)

Ext B (SS)

PLACE_NEAR=U0500.AJ10:2.54mm

1

R1570

22.6

1%
1/20W
MF
201

2

SML1ALERT# pull-up not provided on this
page, may be wire-ORed into other signals.
Otherwise, 100k pull-up to 3.3V SUS required.

D

C

B

=PP3V3_SUS_PCH_GPIO

A

=PP3V3_SUS_PCH_VCC_SPI

100K

R1580
R1581
R1582
R1583

R1548
R1549

R1590
R1591

100K
100K
100K

1K
1K

100K
100K

1 2
1 2
1 2

1 2

1 2
1 2

1 2
1 2

68

8

11 68

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L

SPI_IO<2>
SPI_IO<3>

PCH_SMBALERT_L
WOL_EN

14 16

14 16

14 16

14 16

14 47 75

14 47 75

14

14 71

6 3

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

PAGE TITLE

PCH PCIe,USB,LPC,SPI,SMBus

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=10/23/2012

051-1573

8.0.0

dvt1

15 OF 120

14 OF 82

SIZE

A

D

D

C

B

A

BOM GROUP

RAMCFG_SLOT

RAMCFG3:H

R1631

100K

1/20W

201

=TBT_GO2SX_BIDIR

69

BI

15 36 71

IN

8 7 6 5 4 3

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

OMIT_TABLE

BROADWELL-ULT

P1
AU2
AM7
AD6

Y1

T3
AD5
AN5
AD7
AN3
AG6
AP1
AL4
AT5
AK4
AB6

U4

Y3

P3

Y2
AT3
AH4
AM4
AG5
AG3
AM3
AM2

P2

C4

L2

N5

V2

SYM 10 OF 19

BMBUSY*/GPIO76

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

GPIO16

GPIO17

GPIO24

GPIO27

GPIO28

GPIO26

GPIO56

GPIO57

GPIO58

GPIO59

GPIO44

GPIO47

GPIO48

GPIO49

GPIO50

HSIOPC/GPIO71

GPIO13

GPIO14

GPIO25

GPIO45

GPIO46

GPIO9

GPIO10

DEVSLP0/GPIO33

SDIO_POWER_EN/GPIO70

DEVSLP1/GPIO38

DEVSLP2/GPIO39

SPKR/GPIO81

(IPD-PLTRST#)

CRITICAL

U0500

2C+GT2

BGA

(IPD-RSMRST#)

(IPD-DeepSx)

THERMTRIP*

RCIN*/GPIO82

PCH_OPI_COMP

CPU/MISC

GSPI0_CS*/GPIO83

GSPI0_CLK/GPIO84

GSPI0_MISO/GPIO85
(IPD)

GSPI0_MOSI/GPIO86
(IPD-PLTRST#)

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI1_MISO/GPIO89
(IPD)

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

UART1_RXD/GPIO0

LPIO

GPIO

UART1_TXD/GPIO1

UART1_RST*/GPIO2

UART1_CTS*/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66

(IPD-PLTRST#)

SDIO_D1/GPIO67

SDIO_D2/GPIO68

SDIO_D3/GPIO69

PP3V3_S0_EDP_SW

41 65

SERIRQ

RSVD
RSVD

=PP1V05_S0_CPU_VCCST

6 8

16 17 55 68

D60
V4
T4
AW15
AF20

AB21

R6
L6
N6
L8

R7
L5
N7
K2

J1
K3
J2
G1

K4
G2
J3
J4

F2
F3

G4
F1

E3
F4
D3
E4
C3
E2

PM_THRMTRIP_L
=TBT_CIO_PLUG_EVENT
LPC_SERIRQ
PCH_OPI_COMP

75

NC
NC

PCH_GSPI0_CS_L
PCH_GSPI0_CLK
PCH_GSPI0_MISO
PCH_GSPI0_MOSI

TPAD_SPI_CS_L
TPAD_SPI_CLK
TPAD_SPI_MISO
TPAD_SPI_MOSI

AP_S0IX_WAKE_L
HDMITBTMUX_FLAG_L
JTAG_ISP_TDO
AP_RESET_L

PCH_UART1_RXD
PCH_UART1_TXD
PCH_UART1_RTS_L
PCH_UART1_CTS_L

PCH_I2C0_SDA
PCH_I2C0_SCL

PCH_I2C1_SDA
PCH_I2C1_SCL

TBT_POC_RESET_L
BT_PWRRST_L
PCH_STRP_TOPBLK_SWP_L
ENET_MEDIA_SENSE
LCD_IRQ_L
LCD_PSR_EN

R1694

1 2

10K

5%

1/20W

MF

201

R1650

1/20W

=PP3V3_S0_PCH_GPIO

RAMCFG2:H

1

1

R1636

100K

5%

5%
1/20W

MF

MF
201

2

2

TPAD_SPI_INT_L

=PP3V3_S0_PCH_GPIO

12 13 15 18 26 65 68

=PP3V3_S5_PCH_GPIO
=PP3V3_S3RS4_PCH_GPIO
=PP3V3_S3SW_SD_RESET
=PP3V3_S3_PCH_GPIO
=PP3V3_S3RS0_CAMPWREN
=PP3V3_S0_PCH_GPIO
=PP3V3_S0RTBTLC_PCH_GPIO

TBTLC for CR, S0 for RR

R1610
R1614

R1615
R1616

R1617
R1618
R1619
R1620

R1622
R1623
R1624
R1625
R1626
R1627
R1628
R1629
R1630

R1632
R1633

R1637
R1638

R1652
R1670
R1691
R1693

R1695

12 13 15 18 26 65 68

RAMCFG1:H RAMCFG0:H

D1600

A K

BAT54XV2T1

SOD-523

R1600

R1635

100K

1/20W

1M

1/20W

201

201

5%
MF

1

1

5%
MF

2

2

1

2

TPAD_SPI_INT_GPIO28_L

1

R1681

0

5%

1/20W

MF
0201

2

1

R1682

0

5%

1/20W

MF

2

0201

TPAD_SPI_INT_GPIO46_L

13 68

68

68

68

18 44

12 13 15 18 26 65 68

68

100K
100K

100K

100K
100K
100K
100K
100K

100K
100K
100K
100K
100K
100K
100K
100K
100K

100K
100K

100K
100K

10K
100K
100K
100K

100K

1 2

1 2
1 2

SD_ON_MLB

1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2

1 2

1 2

1 2

1/20W

5% 201

1/20W
1/20W

5% MF

1/20W
1/20W

5%

1/20W

5% 201

1/20W

5%

1/20W

5%

1/20W

5%

1/20W
1/20W

5%
5%

1/20W
1/20W

5%

1/20W
1/20W
1/20W
1/20W

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W

1/20W

5% 201

1/20W

1/20W

5% MF 201

1/20W

1/20W

BOM OPTIONS

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

GPIO12:

R1611

100K

5%
1/20W
MF
201

XDP_MLB_RAMCFG0
XDP_MLB_RAMCFG1
XDP_MLB_RAMCFG2
XDP_MLB_RAMCFG3

13 15 16 18

32

18 33

R1641

MF

MF
MF5% 201

MF
MF
MF 201
MF 201

MF 201
MF 2015%

MF
MF5%

MF 2015%
MF 2015%

MF

MF5%

MF

MF

MF5%

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS
RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

15 16 18

15 16 18

15 16 18

15 16 18

PLT_RESET_L

IN

1

R1621

100K

5%

1/20W

MF

201

2

18

OUT

15

15

1

R1639

100K

1/20W

OUT

OUT

R1680

5%
MF

201

100K

5%

1/20W

MF

2

201

1 2

XDP_PCH_GPIO76
XDP_LPCPLUS_GPIO

2015%

XDP_PCH_GPIO17

SD_RESET_L

201

SMC_WAKE_SCI_L

201

TPAD_SPI_INT_L
TPAD_USB_IF_EN
SSD_PWR_EN

HDD_PWR_EN
XDP_SDCONN_STATE_CHANGE_L
SD_PWR_EN

201MF

TBT_PWR_EN

201

XDP_JTAG_ISP_TCK

201

XDP_JTAG_ISP_TDI

201MF

JTAG_TBT_TMS_PCH
PCH_HSIO_PWR_EN
TPAD_SPI_IF_EN

201MF5%

SPIROM_USE_MLB

201

CAMERA_PWR_EN_PCH

201MF

SSD_SR_EN_L

201

AP_S0IX_WAKE_SEL

201

LPC_SERIRQ
JTAG_ISP_TDO

2015%

BT_PWRRST_L
ENET_MEDIA_SENSE

201

LCD_PSR_EN

201MF5%

XDP_PCH_GPIO76

15 16

BI

XDP_MLB_RAMCFG0

15 16 18

BI

HDMI_TBT_MUX_SEL_GPIO12
TP_MEM_VDD_SEL_1V5_L
XDP_LPCPLUS_GPIO

15 16

BI

XDP_PCH_GPIO17

15 16

IN

SD_RESET_L

15 66

OUT

SMC_WAKE_SCI_L

15 38

IN

TPAD_SPI_INT_GPIO28_L

15

TPAD_USB_IF_EN

15 37

SSD_PWR_EN

15 32 64

OUT

PCH_TBT_PCIE_RESET_L
HDD_PWR_EN

15 71

OUT

XDP_SDCONN_STATE_CHANGE_L

15 16

BI

SD_PWR_EN

15 66

OUT

TBT_PWR_EN

15 25

OUT

XDP_JTAG_ISP_TCK

15 16

OUT

XDP_JTAG_ISP_TDI

15 16

OUT

JTAG_TBT_TMS_PCH

15 18

OUT

PCH_HSIO_PWR_EN

15 63

OUT

TPAD_SPI_IF_EN

15 37

OUT

XDP_MLB_RAMCFG3

15 16 18

BI

SPIROM_USE_MLB

15 47 71

BI

CAMERA_PWR_EN_PCH

15 18

OUT

TPAD_SPI_INT_GPIO46_L

15

XDP_MLB_RAMCFG1

15 16 18

1

2

BI

XDP_MLB_RAMCFG2

15 16 18

BI

SSD_SR_EN_L

15 32

OUT

AP_S0IX_WAKE_SEL

15 31

OUT

SSD_RESET_L

CAM_PCIE_RESET_L

PCH_TCO_TIMER_DISABLE

201MF5%1K1/20W

15 16

15 16

15 16

R1616 should also be stuffed if

15 66

platform does not use SD card

15 38

15 36 71

15 37

15 32 64

15 71

15 16

15 66

15 25

15 16

15 16

15 18

15 63

15 37

STUFFED R1632

15 47 71

15 18

15 32

15 31

15 38 71

15 18

15 71

15 71

15 65

6 3

12

1

1K

5%
MF

201

2

39 75

OUT

18

IN

15 38 71

BI

15

15

15

15

15 37 75

OUT

15 37 75

OUT

15 37 75

IN

15 37 75

OUT

15 31

IN

15 67

IN

15 18

IN

15

15

15

15

15

15

15

15

26

OUT

15 71

OUT

40

IN

15 71

IN

65 71

IN

15 65

OUT

Pull-up/down on chipset support page (depends on TBT controller)
Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.
Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

PLACE_NEAR=U0500.AW15:2.54mm

1

R1655

49.9

1%
1/20W
MF
201

2

PLT_RESET_L

1

R1671

100K

5%
1/20W
MF
201

2

66

OUT

IN

13 15 16 18

Pull-up on TBT page

Requires connection to SMC via 1K series R

=PP3V3_S0_PCH_GPIO

12 13 15 18 26 65 68

100K

PCH_GSPI0_CS_L

15

PCH_GSPI0_CLK

15

PCH_GSPI0_MISO

15

PCH_GSPI0_MOSI

15

TPAD_SPI_CS_L

15 37 75

TPAD_SPI_CLK

15 37 75

TPAD_SPI_MISO

15 37 75

TPAD_SPI_MOSI

15 37 75

AP_S0IX_WAKE_L

15 31

HDMITBTMUX_FLAG_L

15 67

PCH_UART1_RXD

15

PCH_UART1_TXD

15

PCH_UART1_RTS_L

15

PCH_UART1_CTS_L

15

PCH_I2C0_SDA

15

PCH_I2C0_SCL

15

PCH_I2C1_SDA

15

PCH_I2C1_SCL

15

BOM_COST_GROUP=CPU

R1660
R1661
R1662
R1663

R1664
R1665
R1666
R1667

R1668
R1669

R1672
R1673
R1674
R1675

R1676
R1677

R1678
R1679

SYNC_MASTER=J41 SYNC_DATE=01/19/2013

PAGE TITLE

PCH GPIO/MISC/LPIO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

100K
100K
100K

47K
47K
47K
47K

100K
100K

100K
100K
100K
100K

100K
100K

100K
100K

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2

1/20W

5% 201MF

1/20W

5% 201

1/20W

5%

1/20W

5% 201

1/20W

5%

1/20W
1/20W

5% 201

1/20W

5%

1/20W

5% MF
5% 201

1/20W

5%

1/20W
1/20W
1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W
1/20W

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

MF
MF 201
MF

MF5% 201
MF

201

MF

201MF

201

MF

201MF

MF 2015%

MF 2015%
MF 2015%

051-1573

8.0.0
dvt1

16 OF 120

15 OF 82

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

12

=PP1V05_S0_XDP

XDP

10%

6.3V
0201

68

1

R1830

150

5%
1/16W
MF-LF
402

2

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2
HOOK3

TCK1
TCK0

XDP

1

1

R1831

1K

5%
1/16W

2

MF-LF
402

2

C1800

0.1UF

CERM-X5R

Extra BPM Testpoints

XDP_BPM_L<2>

6

73

IN

XDP_BPM_L<3>

6

73

IN

XDP_BPM_L<4>

6

73

IN

XDP_BPM_L<5>

6

73

IN

XDP_BPM_L<6>

6

73

IN

XDP_BPM_L<7>

6

73

IN

D

CPU_VCCST_PWRGD

8

17 73

IN

PM_PWRBTN_L

13 38 75

OUT

PM_PCH_SYS_PWROK

13 17 38 75

OUT

XDP_CPU_TCK

6

16 73

C

12 16 73

OUT

OUT

PCH_JTAGX

1

TP

TP1802

TP-P6

1

TP

TP1803

TP-P6

1

TP

TP1804

TP-P6

1

TP

TP1805

TP-P6

1

TP

TP1806

TP-P6

1

TP

TP1807

TP-P6

PLACE_NEAR=U0500.C61:2.54mm

PLACE_NEAR=U5000.J3:2.54mm

R1800
R1802

R1804

R1835

1K

0

0

0

XDP

1 2

5% 201

XDP

1 2

5%

XDP

1 2

5%

XDP

1 2

5%
PLACE_NEAR=J1800.58:28mm

1/20W

1/20W

1/16W

1/20W

MF

MF

MF-LF

MF

0201

402

0201

XDP_CPU_PREQ_L

6

73

BI

XDP_CPU_PRDY_L

6

73

IN

CPU_CFG<0>

6

73

IN

CPU_CFG<1>

6

73

IN

CPU_CFG<2>

6

73

IN

CPU_CFG<3>

6

73

IN

XDP_BPM_L<0>

6

73

IN

XDP_BPM_L<1>

6

73

IN

CPU_CFG<4>

6

73

IN

CPU_CFG<5>

6

73

IN

CPU_CFG<6>

6

73

IN

CPU_CFG<7>

6

73

IN

XDP_CPU_VCCST_PWRGD

73

XDP_CPU_PWRBTN_L

75

CPU_PWR_DEBUG

8

OUT

XDP_SYS_PWROK

75

=SMBUS_XDP_SDA

41

BI

=SMBUS_XDP_SCL

41

IN

XDP_PCH_TCK

12 16 73

OUT

C1804

0.1UF

CERM-X5R

XDP_CPU_PRESENT_L

PCH XDP Signals

These signals do not connect to XDP connector in this architecture, only accessible
via Top-Side Probe. Nets are listed here to show XDP associations and to make clear
what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

PCH/XDP Signals

XDP_MLB_RAMCFG0

15 18

B

A

BI

XDP_USB_EXTA_OC_L

14 35

OUT

XDP_USB_EXTB_OC_L

14

OUT

XDP_USB_EXTC_OC_L

14

OUT

XDP_USB_EXTD_OC_L

14

IN

XDP_SDCONN_STATE_CHANGE_L

15

OUT

XDP_MLB_RAMCFG1

15 18

BI

XDP_MLB_RAMCFG2

15 18

BI

XDP_MLB_RAMCFG3

15 18

BI

XDP_JTAG_ISP_TCK

15 18

IN

XDP_SSD_PCIE3_SEL_L

12

OUT

XDP_SSD_PCIE2_SEL_L

12

OUT

XDP_SSD_PCIE1_SEL_L

12

OUT

XDP_SSD_PCIE0_SEL_L

12

OUT

XDP_LPCPLUS_GPIO

15

BI

XDP_PCH_GPIO17

15

OUT

XDP_PCH_GPIO76

15

BI

XDP_JTAG_ISP_TDI

15 18

IN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

R1881
R1882
R1883
R1884

MAKE_BASE=TRUE

MAKE_BASE=TRUE

Unused & MLB_RAMCFGx GPIOs have TPs.
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.
SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.
NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.
SSD_PCIEx_SEL_L straps are connected via 1K to common net.
LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

1

TP

TP1870

TP-P6

1

TP

TP1873

TP-P6

1

TP

TP1874

TP-P6

1

TP

TP1876

TP-P6

1

TP

TP1877

TP-P6

1

TP

TP1878

TP-P6

1K

1 2

1K

1 2

1K

1 2

1K

1 2

5% 201

5% 201

5% 201

5% 201

1

TP

TP1886

TP-P6

1

TP

TP1887

TP-P6

1/20W

1/20W

1/20W

1/20W

MF

MF

MF

MF

Non-XDP Signals

USB_EXTA_OC_L
USB_EXTB_OC_L

SDCONN_STATE_CHANGE_L

JTAG_ISP_TCK

NOTE: Must not short XDP pins together!

SSD_PCIE_SEL_L
LPCPLUS_GPIO

JTAG_ISP_TDI

IN

66

IN

18

IN

OUT

32

IN

71

BI

OUT

Merged (CPU/PCH) Micro2-XDP

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7

TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R
0201

SDA
SCL

XDP

10%

6.3V
0201

DF40RC-60DP-0.4V

1

2

CRITICAL
XDP_CONN

J1800

M-ST-SM1

62

61

1

2

3

4

5

6

78

10

9
1112
1314
1516
1718
19

20

2122
2324
2526
2728
29

30

3132
3334
3536
3738
39

40

4142
4344
4546
4748
49

50

5152
5354
5556
5758
59

60

6364

518S0847

CPU JTAG Isolation

=PP5V_S0_XDPJTAGISOL

68

=PP3V3_S5_XDPJTAGISOL

68

1

C1845

0.1UF

10%
16V

2

17 38 64

IN

X5R-CERM

ALL_SYS_PWRGD

0201

NC

74LVC1G07GF

2

A

1

NC NC

6

VCC

U1845

SOT891

GND

3

CPU_CFG<17>
CPU_CFG<16>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<10>
CPU_CFG<11>

CPU_CFG<19>
CPU_CFG<18>

CPU_CFG<12>
CPU_CFG<13>

CPU_CFG<14>
CPU_CFG<15>

NC
NC

XDP_CPURST_L
XDP_DBRESET_L

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

XDP_TRST_L

73

XDP

1

C1806

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=J1800.53:28mm

PLACE_NEAR=J1800.55:28mm

1

R1845

330K

5%
1/20W
MF
201

2

Y

4

5

NC

PLACE_NEAR=J1800.57:28mm

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

17 75

OUT

CRITICAL

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

PLACE_NEAR=J1800.51:28mm

CRITICAL

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

CRITICAL

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

XDP_JTAG_CPU_ISOL_L

R1805

XDP

Q1840

SOT563

XDP

Q1840

SOT563

CRITICAL

XDP

Q1842

SOT563

XDP

Q1842

SOT563

D

3

D

6

D

3

D

6

BOM_COST_GROUP=CPU SUPPORT

1K

VER 3

VER 3

VER 3

VER 3

XDP_CPU_TDO

6

16 73

XDP_CPU_TCK

6

16 73

PLACE_NEAR=U0500.F62:28mm

PLACE_NEAR=U0500.E60:28mm

R1810

R1813

TDI and TMS are terminated in CPU.

XDP

1 2

PLT_RESET_L

5% 201

1/20W

PLACE_NEAR=U0500.AG7:2.54mm

MF

XDP_PCH_TDO

XDP_PCH_TDI
XDP_PCH_TMS

5

S G

4

2

S G

1

5

S G

4

2

S G

1

XDP_CPU_TDO

XDP_CPUPCH_TRST_L

MAKE_BASE=TRUE

XDP_CPU_TRST_L
XDP_PCH_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

PCH_JTAGX

12 16 73

XDP_PCH_TDO

12 16 73

XDP_PCH_TDI

12 16 73

XDP_PCH_TMS

12 16 73

XDP_PCH_TCK

12 16 73

XDP_PCH_TRST_L

12 16

PLACE_NEAR=U0500.AE63:28mm

PLACE_NEAR=U0500.AE61:28mm

PLACE_NEAR=U0500.AD61:28mm

PLACE_NEAR=U0500.AD62:28mm

PLACE_NEAR=U0500.AE62:28mm

PLACE_NEAR=U0500.AU62:28mm

SYNC_MASTER=WFERRY_J43

PAGE TITLE

R1899
R1890

R1891
R1892

R1896

R1897

CPU/PCH Merged XDP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

=PP1V05_S0_CPU_VCCST

6 8

15 17 55 68

XDP

51

1 2

XDP

51

2 1

13 15 18

IN

12 16 73

IN

12 16 73

OUT

12 16 73

OUT

6

16 73

IN

73

6

OUT

12 16

OUT

6

73

OUT

6

73

OUT

=PP1V05_SUS_PCH_JTAG

68

NO STUFF

1K

2 1

XDP

51

2 1

XDP

51

2 1

XDP

51

2 1

NO STUFF

51

2 1

NO STUFF

51

2 1

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

SYNC_DATE=12/21/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

18 OF 120

SHEET

16 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

System RTC Power Source & 32kHz / 25MHz Clock Generator

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

This looks a little ugly to support
new and old parts. With GreenCLK Rev C
pin 5 must receive S5 power (Stuff R2042)

D

GreenCLK 25MHz Power
Must be powered if any VDDIO is powered.

CAM XTAL Power
TBT XTAL Power

C1905

12PF

0201

C1906

5%

CERM

12PF

1 2

5%

25V
CERM
0201

12

NC
NC

SYSCLK_CLK25M_X2

74

25V

CRITICAL

1 3

Y1905

2 4

SM-3.2X2.5MM

25.000MHZ-12PF-20PPM
OMIT

NOTE: 30 PPM or better required for RTC accuracy

C

C1915

6.8PF

1 2

+/-0.1PF

25V
C0G

NC

0201

NC

C1916

6.8PF

1 2

+/-0.1PF

25V
C0G

0201

LPC_CLK24M_SMC_R

12 75

IN

13

PLACE_NEAR=U0500.AN15:5.1mm

PCH 24MHz Crystal

PCH_CLK24M_XTALOUT_R

75

CRITICAL

Y1915

NC

24.000MHZ-20PPM-6PF

24

NC

3.20X2.50MM-SM1

PCH 24MHz Outputs

B

=PP3V3_S3RS0_SYSCLKGEN

18

=PPVDDIO_S3RS0_CAMCLK

33

=PPVDDIO_TBTLC_CLK

68

C1924

0.1UF

X5R-CERM

R1905

1 2

R1927

22

1 2

5%

1/20W

MF

201

10%
16V

0201

0

5%

1/20W

MF

0201

R1915

0

1 2

5%

1/20W

MF

0201

=PPVBAT_G3H_SYSCLK

68

Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)

=PP3V3_S5_SYSCLK

18 68

Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5

1

C1922

0.1UF

10%

2

16V

X5R-CERM

0201

CKPLUS_WAIVE=PwrTerm2Gnd

SYSCLK_CLK25M_X2_R

74

NO STUFF

1

R1906

1M

5%
1/20W
MF
201

2

SYSCLK_CLK25M_X1

74

PCH_CLK24M_XTALOUT

1

R1916

1M

5%
1/20W
MF
201

2

PCH_CLK24M_XTALIN

LPC_CLK24M_SMC

MAKE_BASE=TRUE

LPC_CLK_SMC

No bypass necessary

1

1

C1902

1UF

20%

6.3V

2

2

X5R
0201

71 75

OUT

11

14

IN

OUT

38

5

2

NC

VDD

U1900

SLG3NB148CV

TQFN

CRITICAL

GND

71016

32.768K

THRM

PAD

17

NO_TEST=TRUE

VIOE_25M_A

6

VIOE_25M_B
VIOE_25M_C

3

X2

4

X1

NC_RTC_CLK32K_RTCX2

MAKE_BASE=TRUE

12 75

12 75

13

VBAT and +V3.3A are
internally ORed to
create VDD_RTC_OUT.

VG3HOT

+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.

25M_A
25M_B
25M_C

VOUT

12

9
8
15

1

PCH_CLK32K_RTCX1

NC

SYSCLK_CLK25M_CAMERA
SYSCLK_CLK25M_TBT
=PPVRTC_G3_OUT

1

2

PCH_CLK32K_RTCX2

For SB RTC Power

C1910

1UF

20%

6.3V
X5R
0201

PCH Reset Button

17 68

XDP_DBRESET_L

OUT

OUT
OUT

68

IN

=PP3V3_S0_SB_PM

XDP

R1996

1 2

1/20W

0201

MF
5%

12 75

34 74

25 74

12

12

Memory VTT Enable Level-Shifter

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

=PP1V2_S3_MEM_VTTPWRCTL

1

R1995

10K

5%
1/20W
MF
201

2

0

PM_SYSRST_L

NO STUFF

1

R1997

0

5%
1/16W
MF-LF
402

2

SILK_PART=SYS RESET

13 38 71 75 16 75

BIIN

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

8

11 63

68

CPU_MEMVTT_PWR_EN_LSVDDQ

6

IN

C1970

0.1UF

X5R-CERM

0201

10%
16V

1

2

NC

6

VCC

U1970

74AUP1G07GF

SOT891

2

A Y

1

NC NC

GND

3

=PP3V3_S0_MEM_VTTPWRCTL

1

R1970

330K

5%
1/20W
MF
201

2

4

5

NC

=PP5V_S0_PCH_STRAP

68

PCH ME Disable Strap

SIGNAL_MODEL=DMN5L06VK_7

SIGNAL_MODEL=DMN5L06VK_7

SPI_DESCRIPTOR_OVERRIDE_L

38

IN

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

=PP3V3_S5_CSPWRGD

68

16 17 38 64

13 18 38 64 66 71

IN

Q1920

DMN5L06VK-7

SOT563

DMN5L06VK-7

D

3

Q1920

SOT563

VER 3

VER 3

2

5

SPI_DESCRIPTOR_OVERRIDE_LS5V

S G

SPI_DESCRIPTOR_OVERRIDE

4

6

D

SG

1

VCCST (1.05V S0) PWRGD

C1930

0.1UF

X5R-CERM

ALL_SYS_PWRGD
PM_SLP_S3_L

10%
16V

0201

1

2

NC

CRITICAL

U1930

74AUP1G09

SOT891

VCC

2

1

B

5

NC

GND

4

YA

3 6

=PP1V05_S0_CPU_VCCST

1

R1931

10K

5%
1/20W
MF
201

2

CPU_VCCST_PWRGD

68

TPS51916 I(leak) = +/- 1uA,
Vih(min) = 1.8V
33uW when driven-low

MEMVTT_PWR_EN

MAKE_BASE=TRUE

=DDRVTT_EN

1

R1921

2

57

OUT

1

R1920

100K

5%
1/20W
MF
201

2

1K

5%
1/20W
MF
201

HDA_SDOUT_R

IPD = 9-50k

8

OUT

6 8

16 73

15 16 55 68

D

12 75

OUT

C

B

=PP3V42_G3H_CSPWRGD

68

=PP3V3_S0_SB_PM

17 68

1

CPU_VR_EN

8

55

IN

1

R1955

10K

5%

A

CPU_VR_READY

8

OUT

MAKE_BASE=TRUE

CPUVR_PGOOD

55

IN

1/20W

NO STUFF

MF

201

R1951

2

0

1 2

5%

1/20W

MF

0201

ALL_SYS_PWRGD

16 17 38 64

IN

CPUVR_PGOOD_R

SMC_DELAYED_PWRGD

26 27 38 39 75

IN

R1950

10K

1/20W

5%
MF

201

2

PCH PWROK Generation

BYPASS=U1950::5MM

1

C1950

0.1UF

10%

1

2

A

U1950

B

16V

2

X5R-CERM
0201

74LVC2G08GT/S505

8

SOT833

7

Y

08

4

PM_S0_PGOOD

75

NO STUFF

R1963

R1961

100K

1/20W

201

1/20W

5%
MF

0201

1

2

NO STUFF

2

2

R1960

0

0

5%

5%
1/20W

MF

MF
0201

1

1

WF: Do we need this?

CKPLUS_WAIVE=UNCONNECTED_PINS

8

74LVC2G08GT/S505

SOT833

5

A

3

SYS_PWROK_R

75

Y

U1950

6

08

B

4

CKPLUS_WAIVE=UNCONNECTED_PINS

R1962

1K

1 2

5%

1/20W

MF

201

6 3

PM_PCH_APWROK
PM_PCH_PWROK

MAKE_BASE=TRUE

PM_PCH_SYS_PWROK

OUT

13

OUT

13 75

OUT

13 16 38 75

PART NUMBER

197S0480

QTY

1

DESCRIPTION

XTAL,25MHZ,20PPM,12PF,3.2X2.5X.6MM,85C

BOM_COST_GROUP=CPU SUPPORT

REFERENCE DES

CRITICAL

Y1905

PAGE TITLE

Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM OPTION

SYNC_DATE=01/30/2013SYNC_MASTER=J41

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

SHEET

124578

8.0.0
dvt1

19 OF 120

17 OF 82

SIZE

A

D

8 7 6 5 4 3

12

Platform Reset Connections

=PP3V3_S3_SYSCLKGEN

PLT_RESET_L

13 15 16

IN

=PP3V3_S0_SYSCLKGEN

68

D

=PP3V3_S5_SYSCLK

17 68

=PP3V3_S0_RSTBUF

68

CRITICAL

5

MC74VHC1G08

1

C2071

0.1UF

10%
16V

2

X5R-CERM
0201

1

2

U2071

3

SC70-HF

4

PLT_RST_BUF_L

1

R2070

100K

5%
1/20W
MF
201

2

PCH_TBT_PCIE_RESET_L

15

IN

MAKE_BASE=TRUE

C

DBGLED

=PP3V3_S5_DBGLEDS

68

PLACE_SIDE=BOTTOM

B

R2094

0

12

5%
1/16W
MF-LF

402

DBGLED

1

R2090

20K

5%

1/20W

MF

201

DBGLED_S5

DBGLED

A

D2090

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

PLACE_SIDE=BOTTOM

K

SILK_PART=S5_ON

2

64

13 31 37 38 64 66

13 17 38 64 66 71

13 38

PP3V3_S5_DBGLED

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=3.3V

DBGLED_S4 DBGLED_S3

DBGLED

A

D2091

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

PLACE_SIDE=BOTTOM

K

SILK_PART=STBY_ON

DBGLED_S4_D

Q2090

DMN5L06VK-7

S4_PWR_EN

IN

PM_SLP_S4_L

IN

PM_SLP_S3_L

IN

PM_SLP_S0_L

IN

A

Scrub for Layout Optimization

Buffered

R2072

0

1 2

5%

1/20W

MF

0201

NO STUFF

R2089

0

1 2

5%

1/20W

MF

0201

Power State Debug LEDs

(For development only)

DBGLED

1

R2091

20K

5%

1/20W

MF

201

2

DBGLED

A

D2092

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

PLACE_SIDE=BOTTOM

K

SILK_PART=S3_ON

6

D

SG

1

DBGLED_S3_D

DMN5L06VK-7

DBGLED

SOT563

VER 3

2

SMC_LRESET_L

CAM_PCIE_RESET_L

TBT_PCIE_RESET_L

DBGLED

1

R2092

20K

5%

1/20W

MF

201

2

DBGLED

Q2090

SOT563

VER 3

3

D

5

SG

4

38

OUT

15 33

OUT

25

OUT

To SMC

16

OUT

DBGLED

R2093

20K

5%

1/20W

MF

201

DBGLED_S0I3

DBGLED

A

D2093

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

PLACE_SIDE=BOTTOM

K

SILK_PART=S0I3_ON

DBGLED_S0I3_D

DBGLED

Q2091

DMN5L06VK-7

SOT563

VER 3

2

SMC_PME_S4_DARK_L

38 39

=SMC_PME_SDCONN_L

=PP3V3_S3_SDBUF

68

SDCONN_STATE_CHANGE_L

To PCH

1

2

DBGLED_S0

A

K

DBGLED_S0_D

6

D

SG

1

BYPASS=U2030.5::5MM

R2095

DBGLED

D2095

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

PLACE_SIDE=BOTTOM
SILK_PART=S0_ON

DBGLED

Q2091

DMN5L06VK-7

SOT563

VER 3

DBGLED

20K

1/20W

5

SDCONN_STATE_CHANGE Isolation

Q2030

DMN5L06VK-7

SOT563

1

C2031

0.1UF

10%

6.3V

2

CERM-X5R

0201

1

5%
MF

201

2

3

D

SG

4

BYPASS=U2030::3mm

R2034

1/20W

BYPASS=U2030::3mm

C2034

0.1UF

X5R-CERM

0201

6 3

GreenCLK 25MHz Power

NO STUFF

R2040

0

1 2

5%

1/20W

MF

0201

NO STUFF

R2041

0

1 2

5%

1/20W

MF

0201

R2042

0

1 2

5%

1/20W

MF

0201

=PP3V3_S4_SMC

39 40 68

5

SMC_PME_SDCONN

VER 3

D

S G

3

4

Y A

4

CRITICAL

U2031

74AUP1G09

SOT891

VCC

2

1

B

5

NC

GND

3 6

NC

=PP3V3_S3RS0_CAMPWREN

1

10K

5%
MF

201

2

CAMERA_PWR_EN_RC

1

10%
10V

2

CAMERA_PWR_EN_PCH

15

IN

I1608

=PP3V3_S3RS0_SYSCLKGEN
PP3V3_S5RS3RS0_SYSCLKGEN

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

R2041/2 should be stuffed for
GreekCLK A or B depending on S2 rail

17 68

R2042 should be stuffed for GreenCLK C

1

R2032

470K

5%
1/20W
MF
201

2

2

S G

1

R2031

470K

1/20W

201

1

5%
MF

2

Q2030

DMN5L06VK-7

SOT563

VER 3

D

6

SDCONN_STATE_CHANGE_RIO

15 44

=PP3V3_S4_CAMPWREN

BYPASS=U2030::3mm

C2030

0.1UF

10%
10V

X5R-CERM

0201

1

2

1

2

U2030

CRITICAL

5

MC74VHC1G08

SC70-HF

4

3

CAMERA_PWR_EN_R

=PP3V3_S0_PCH_GPIO

12 13 15 26 65 68

THUNDERBOLT PULL-UP

REDWOOD RIDGE PLUG_EVENT IS ACTIVE-LOW, ALWAYS DRIVEN (PULL-UP)

=TBT_CIO_PLUG_EVENT

15

OUT

MAKE_BASE

TBT_CIO_PLUG_EVENT_L

TRUE

Redwood Ridge JTAG Isolation

TBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

PP3V3_TBTLC

25 26 68

1

1

1

R2061

100K

1/20W

201

From RR

From PCH

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK
and TDI as well for PCH glitch-prevention.

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for
Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs
different isolation techniques will likely be necessary.
Multi-router designs also require different circuitry.

66

IN

JTAG_TBT_TDO

25

IN

JTAG_TBT_TMS_PCH

15

IN

S0 pull-up on PCH page

JTAG_ISP_TCK

16

IN

MAKE_BASE=TRUE

JTAG_ISP_TDI

16

IN

MAKE_BASE=TRUE

Renaming the pins N61 and P61 to remove automatic diffpari property

Pin N61 needs a TP for Power to perform iFDIM test

TP_CPU_RSVD_N61

8

TP_CPU_RSVD_P61

8

C2060

0.1UF

5%
MF

20%
10V

2

CERM
402

2

VCC

U2060

74LVC2G07

SOT891

1

1A 1Y

3

2A 2Y

GND

2 5

JTAG_TBT_TCK
JTAG_TBT_TDI

TP_CPU_RSVDN61

MAKE_BASE=TRUE

TP_CPU_RSVDP61

MAKE_BASE=TRUE

RAM Configuration Straps

Pull-downs for chip-down RAM systems

XDP_MLB_RAMCFG0

15 16

OUT

XDP_MLB_RAMCFG1

15 16

OUT

XDP_MLB_RAMCFG2

15 16

OUT

XDP_MLB_RAMCFG3

15 16

68

R2033

33

1 2

5%

1/20W

MF

201

CAMERA_PWR_EN

OUT

OUT

RAMCFG3:L

R2050

33

SYNC_MASTER=J41

PAGE TITLE

10K

1/20W

201

5%
MF

RAMCFG2:L

1

R2051

2

Project Chipset Support

R2030

0

1 2

5%

1/20W

MF

0201

NOSTUFF

BOM_COST_GROUP=CPU SUPPORT

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

R

R2062

100K

5%
1/20W
MF
201

2

S0 pull-up on PCH page

JTAG_ISP_TDO

6

JTAG_TBT_TMS

4

RAMCFG1:L

1

R2052

10K

5%

1/20W

201

MF

1/20W

2

R2015

100K

1/20W

1

10K

5%
MF

201

2

1

5%
MF

201

2

OUT

OUT

25

OUT

25

OUT

RAMCFG0:L

R2053

1/20W

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

SHEET

124578

25 75

IN

To PCH

15

To RR

25

1

10K

5%
MF

201

2

SYNC_DATE=10/23/2012

8.0.0
dvt1

20 OF 120

18 OF 82

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

NOTE: CPU DAC output step sizes:
DDR3 (1.5V) 7.70mV per step
DDR3L (1.35V) 6.99mV per step
LPDDR3 (1.2V) ?.??mV per step

CPU_DIMMA_VREFDQ

7

76

IN

C

CPU_DIMMB_VREFDQ

7

76

IN

CPU_DIMM_VREFCA

7

76

IN

NOTE: CPU has single output for VREFCA.
VREFCA. Connected to 4 DRAMs.

CPU-Based Margining

VRef Dividers

Always used, regardless
of margining option.

R2223

10

1 2

1%

PLACE_NEAR=R2221.2:1mm

1/20W

MF

201

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_A_RC

R2243

10

1 2

1%

PLACE_NEAR=R2241.2:1mm

1/20W

MF

201

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_B_RC

R2263

5.1

1 2

1%

PLACE_NEAR=R2261.2:1mm

1/20W

MF

0201

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFCA_RC

R2222

8.2K

1/20W

R2220

24.9

1 2

1%

1/20W

MF

201

R2242

8.2K

1/20W

R2240

24.9

1 2

1%

1/20W

MF

201

R2262

8.2K

1/20W

R2260

24.9

1 2

1%

1/20W

MF

201

201

201

201

=PPDDR_S3_MEMVREF

1

R2221

8.2K

1%
1/20W
MF
201

2

PPVREF_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

1

1%
MF

2

1

R2241

8.2K

1%
1/20W
MF
201

2

PPVREF_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

1

1%
MF

2

1

R2261

8.2K

1%
1/20W
MF
201

2

PPVREF_S3_MEM_VREFCA

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

1

1%
MF

2

68

68

68

68

B

D

C

B

A

DAC Channel:

PCA9557D Pin:

Nominal value

Margined target:

DAC range:

VRef current:

DAC step size:

MEM A VREF DQ

A

1

MEM B VREF DQ

LPDDR3 (1.2V)

0.600V (DAC: 0x2E.5)

0.300V - 0.900V (+/- 300mV)

0.000V - 1.199V (0x00 - 0x5D)

+73uA - -73uA (- = sourced)

6.36mV / step @ output

MEM A VREF CA

B

2

C

3

DDR3L (1.35V)

0.675V (DAC: 0x34)

0.337V - 1.013V (+/- 337.5mV)

0.000V - 1.354V (0x00 - 0x69)

+82uA - -82uA (- = sourced)

6.36mV / step @ output

MEM B VREF CA

C

4

MEM VREG

D

LPDDR3 (1.2V)

1.200V (DAC: 0x5D)

0.800V - 1.600V (+/- 400mV)

0.000V - 2.397V (0x00 - 0xBA)

+21uA - -21uA (- = sourced)

4.28mV / step @ output

5

DDR3L (1.35V)

1.343V (DAC: 0x68)

0.972V - 1.714V (+/- 371mV)

0.000V - 2.694V (0x00 - 0xD1)

+25uA - -25uA (- = sourced)

3.53mV / step @ output

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider
DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

6 3

BOM_COST_GROUP=CPU SUPPORT

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

LPDDR3 VREF Margining

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/02/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

22 OF 120

SHEET

19 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL A (0-31)

U2300

LPDDR3-1600-32GB

EDFB232A1MA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

1

C2301

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2321

1UF

10%
10V

2

X5R
402

FBGA

1

C2302

1UF

10%
10V

2

X5R
402

1

C2322

1UF

10%
10V

2

X5R
402

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2303

1UF

10%
10V

2

X5R
402

1

C2323

10UF

20%
25V

2

X5R-CERM
0603

=MEM_A_DQ<0>
=MEM_A_DQ<1>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<4>
=MEM_A_DQ<5>
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQ<12>
=MEM_A_DQ<13>
=MEM_A_DQ<14>
=MEM_A_DQ<15>
=MEM_A_DQ<16>
=MEM_A_DQ<17>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<20>
=MEM_A_DQ<21>
=MEM_A_DQ<22>
=MEM_A_DQ<23>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
=MEM_A_DQ<26>
=MEM_A_DQ<27>
=MEM_A_DQ<28>
=MEM_A_DQ<29>
=MEM_A_DQ<30>
=MEM_A_DQ<31>

=MEM_A_DQS_N<0>
=MEM_A_DQS_N<1>
=MEM_A_DQS_N<2>
=MEM_A_DQS_N<3>

=MEM_A_DQS_P<0>
=MEM_A_DQS_P<1>
=MEM_A_DQS_P<2>
=MEM_A_DQS_P<3>

1

C2304

1UF

10%
10V

2

X5R
402

1

C2324

10UF

20%
25V

2

X5R-CERM
0603

1

C2305

1UF

10%
10V

2

X5R
402

CRITICAL

1

C2335

12PF

2%
50V

2

C0G-CERM
0402

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

1

C2306

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2336

12PF

2%
50V

2

C0G-CERM
0402

1

C2307

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2337

12PF

2%
50V

2

C0G-CERM
0402

=PP1V8_S3_MEM

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

CRITICAL

1

C2334

12PF

2%
50V

2

C0G-CERM
0402

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2300

0.1UF

10%

16V

2

X5R-CERM
0201

1

C2320

1UF

10%
10V

2

X5R
402

J11

A12
A13

B13

T13

U12
U13

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

K3

CKE0

K4

CKE1

J3

CK_T

J2

CK_C

L3

CS0*

L4

CS1*

L8

DM0

G8

DM1

P8

DM2

D8

DM3

J8

ODT

B3

ZQ0

B4

ZQ1

H4

VREFCA
VREFDQ

A1
A2

B1

T1

NU

U1
U2

MEM_A_CAA<0>

24 70 76

IN

MEM_A_CAA<1>

24 70 76

IN

MEM_A_CAA<2>

24 70 76

IN

MEM_A_CAA<3>

24 70 76

IN

MEM_A_CAA<4>

24 70 76

IN

MEM_A_CAA<5>

24 70 76

IN

MEM_A_CAA<6>

24 70 76

IN

MEM_A_CAA<7>

24 70 76

IN

MEM_A_CAA<8>

24 70 76

IN

MEM_A_CAA<9>

24 70 76

IN

MEM_A_CKE<0>

7

24 76

IN

MEM_A_CKE<1>

7

24 76

IN

MEM_A_CLK_P<0>

7

24 76

IN

MEM_A_CLK_N<0>

7

24 76

C

R2300

243

1/20W

201 201

1

1%
MF

2

R2301

243

1/20W

1

1%
MF

2

C2340

0.047UF

6.3V

10%
X5R

201

1

1

C2341

0.047UF

10%

6.3V

2

2

X5R
201

IN

MEM_A_CS_L<0>

7

21 24 76

IN

MEM_A_CS_L<1>

7

21 24 76

IN

MEM_A_ODT<0>

21 24 70 76

IN

MEM_A_ZQ<0>
MEM_A_ZQ<1>

PP0V6_S3_MEM_VREFCA_A

21 68 76

PP0V6_S3_MEM_VREFDQ_A

21 68 76

B

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

A10

U10

H12

K12

A11
C12

E12
G12

H11

J10

K11
L12

N12
R12
U11

A3
A4
A5
A6

U3
U4
U5
U6

A8
A9
D4
D5
D6
G5
H5
H6

J5
J6
K5
K6

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

E8

H8
H9

J9

K8

N8

U2300

LPDDR3-1600-32GB

EDFB232A1MA

FBGA

SYM 2 OF 2

VDD1

OMIT_TABLE

CRITICAL

VDD2

VDDCA

VDDQ

VSSCA

VSSQ

VSS

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

D

C

B

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

1

C2310

1UF

A

=PP1V8_S3_MEM

20 21 22 23 68

10%
10V

2

X5R
402

1

C2330

1UF

10%
10V

2

X5R
402

1

C2311

1UF

10%
10V

2

X5R
402

1

C2331

1UF

10%
10V

2

X5R
402

1

C2312

10UF

20%
25V

2

X5R-CERM
0603

1

C2332

10UF

20%
25V

2

X5R-CERM
0603

1

C2333

10UF

20%
25V

2

X5R-CERM
0603

6 3

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

CRITICAL

1

C2338

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C2339

12PF

2%
50V

2

C0G-CERM
0402

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel A (00-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

23 OF 120

SHEET

20 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL A (32-63)

U2400

LPDDR3-1600-32GB

EDFB232A1MA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

1

C2401

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2421

1UF

10%
10V

2

X5R
402

FBGA

1

C2402

1UF

10%
10V

2

X5R
402

1

C2422

1UF

10%
10V

2

X5R
402

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2403

1UF

10%
10V

2

X5R
402

1

C2423

10UF

20%
25V

2

X5R-CERM
0603

=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<36>
=MEM_A_DQ<37>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DQ<42>
=MEM_A_DQ<43>
=MEM_A_DQ<44>
=MEM_A_DQ<45>
=MEM_A_DQ<46>
=MEM_A_DQ<47>
=MEM_A_DQ<48>
=MEM_A_DQ<49>
=MEM_A_DQ<50>
=MEM_A_DQ<51>
=MEM_A_DQ<52>
=MEM_A_DQ<53>
=MEM_A_DQ<54>
=MEM_A_DQ<55>
=MEM_A_DQ<56>
=MEM_A_DQ<57>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
=MEM_A_DQ<60>
=MEM_A_DQ<61>
=MEM_A_DQ<62>
=MEM_A_DQ<63>

=MEM_A_DQS_N<4>
=MEM_A_DQS_N<5>
=MEM_A_DQS_N<6>
=MEM_A_DQS_N<7>

=MEM_A_DQS_P<4>
=MEM_A_DQS_P<5>
=MEM_A_DQS_P<6>
=MEM_A_DQS_P<7>

1

C2404

1UF

10%
10V

2

X5R
402

1

C2424

10UF

20%
25V

2

X5R-CERM
0603

1

C2405

1UF

10%
10V

2

X5R
402

CRITICAL

1

C2434

12PF

2%
50V

2

C0G-CERM
0402

A10

U10

H12

K12

A11
C12

E12
G12

H11

J10

K11
L12

N12
R12
U11

A3
A4
A5
A6

U3
U4
U5
U6

A8
A9
D4
D5
D6
G5
H5
H6

J5
J6
K5
K6

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

E8

H8
H9

J9

K8

N8

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

1

C2406

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2435

12PF

2%
50V

2

C0G-CERM
0402

1

C2407

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2436

12PF

2%
50V

2

C0G-CERM
0402

=PP1V8_S3_MEM

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2400

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2420

1UF

10%
10V

2

X5R
402

J11

A12
A13

B13

T13

U12
U13

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

K3

CKE0

K4

CKE1

J3

CK_T

J2

CK_C

L3

CS0*

L4

CS1*

L8

DM0

G8

DM1

P8

DM2

D8

DM3

J8

ODT

B3

ZQ0

B4

ZQ1

H4

VREFCA
VREFDQ

A1
A2

B1

T1

NU

U1
U2

MEM_A_CAB<0>

24 70 76

IN

MEM_A_CAB<1>

24 70 76

IN

MEM_A_CAB<2>

24 70 76

IN

MEM_A_CAB<3>

24 70 76

IN

MEM_A_CAB<4>

24 70 76

IN

MEM_A_CAB<5>

24 70 76

IN

MEM_A_CAB<6>

24 70 76

IN

MEM_A_CAB<7>

24 70 76

IN

MEM_A_CAB<8>

24 70 76

IN

MEM_A_CAB<9>

24 70 76

IN

MEM_A_CKE<2>

7

24 76

IN

MEM_A_CKE<3>

7

24 76

IN

MEM_A_CLK_P<1>

7

24 76

IN

MEM_A_CLK_N<1>

7

24 76

C

R2400

243

1/20W

1

1%
MF

201

2

R2401

243

1/20W

1

1%
MF

201

2

0.047UF

C2440

6.3V

1

1

C2441

10%
X5R

201

0.047UF

10%

6.3V

2

2

X5R
201

IN

MEM_A_CS_L<0>

7

20 24 76

IN

MEM_A_CS_L<1>

7

20 24 76

IN

MEM_A_ODT<0>

20 24 70 76

IN

MEM_A_ZQ<2>
MEM_A_ZQ<3>

PP0V6_S3_MEM_VREFCA_A

20 68 76

PP0V6_S3_MEM_VREFDQ_A

20 68 76

B

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

U2400

LPDDR3-1600-32GB

EDFB232A1MA

FBGA

SYM 2 OF 2

VDD1

OMIT_TABLE

CRITICAL

VDD2

VDDCA

VDDQ

VSSCA

VSSQ

VSS

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

D

C

B

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

1

C2410

1UF

A

=PP1V8_S3_MEM

20 21 22 23 68

10%
10V

2

X5R
402

1

C2430

1UF

10%
10V

2

X5R
402

1

C2411

1UF

10%
10V

2

X5R
402

1

C2431

1UF

10%
10V

2

X5R
402

1

C2412

10UF

20%
25V

2

X5R-CERM
0603

1

C2432

10UF

20%
25V

2

X5R-CERM
0603

1

C2433

10UF

20%
25V

2

X5R-CERM
0603

6 3

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

CRITICAL

1

C2437

12PF

2%
50V

2

C0G-CERM
0402

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

24 OF 120

SHEET

21 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL B (0-31)

U2500

LPDDR3-1600-32GB

EDFB232A1MA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

1

C2501

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2521

1UF

10%
10V

2

X5R
402

FBGA

1

C2502

1UF

10%
10V

2

X5R
402

1

C2522

1UF

10%
10V

2

X5R
402

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2503

1UF

10%
10V

2

X5R
402

1

C2523

10UF

20%
25V

2

X5R-CERM
0603

=MEM_B_DQ<0>
=MEM_B_DQ<1>
=MEM_B_DQ<2>
=MEM_B_DQ<3>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQ<6>
=MEM_B_DQ<7>
=MEM_B_DQ<8>
=MEM_B_DQ<9>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_B_DQ<12>
=MEM_B_DQ<13>
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQ<18>
=MEM_B_DQ<19>
=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DQ<22>
=MEM_B_DQ<23>
=MEM_B_DQ<24>
=MEM_B_DQ<25>
=MEM_B_DQ<26>
=MEM_B_DQ<27>
=MEM_B_DQ<28>
=MEM_B_DQ<29>
=MEM_B_DQ<30>
=MEM_B_DQ<31>

=MEM_B_DQS_N<0>
=MEM_B_DQS_N<1>
=MEM_B_DQS_N<2>
=MEM_B_DQS_N<3>

=MEM_B_DQS_P<0>
=MEM_B_DQS_P<1>
=MEM_B_DQS_P<2>
=MEM_B_DQS_P<3>

1

C2504

1UF

10%
10V

2

X5R
402

1

C2524

10UF

20%
25V

2

X5R-CERM
0603

1

C2505

1UF

10%
10V

2

X5R
402

CRITICAL

1

C2534

12PF

2%
50V

2

C0G-CERM
0402

A10

U10

H12

K12

A11
C12

E12
G12

H11

J10

K11
L12

N12
R12
U11

A3
A4
A5
A6

U3
U4
U5
U6

A8
A9
D4
D5
D6
G5
H5
H6

J5
J6
K5
K6

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

E8

H8
H9

J9

K8

N8

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

1

C2506

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2535

12PF

2%
50V

2

C0G-CERM
0402

1

C2507

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2536

12PF

2%
50V

2

C0G-CERM
0402

=PP1V8_S3_MEM

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2500

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2520

1UF

10%
10V

2

X5R
402

J11

A12
A13

B13

T13

U12
U13

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

K3

CKE0

K4

CKE1

J3

CK_T

J2

CK_C

L3

CS0*

L4

CS1*

L8

DM0

G8

DM1

P8

DM2

D8

DM3

J8

ODT

B3

ZQ0

B4

ZQ1

H4

VREFCA
VREFDQ

A1
A2

B1

T1

NU

U1
U2

MEM_B_CAA<0>

24 70 76

IN

MEM_B_CAA<1>

24 70 76

IN

MEM_B_CAA<2>

24 70 76

IN

MEM_B_CAA<3>

24 70 76

IN

MEM_B_CAA<4>

24 70 76

IN

MEM_B_CAA<5>

24 70 76

IN

MEM_B_CAA<6>

24 70 76

IN

MEM_B_CAA<7>

24 70 76

IN

MEM_B_CAA<8>

24 70 76

IN

MEM_B_CAA<9>

24 70 76

IN

MEM_B_CKE<0>

7

24 76

IN

MEM_B_CKE<1>

7

24 76

IN

MEM_B_CLK_P<0>

7

24 76

IN

MEM_B_CLK_N<0>

7

24 76

C

R2500

243

1/20W

1

1%
MF

201

2

R2501

243

1/20W

1

1%
MF

201

2

0.047UF

C2540

6.3V

1

1

C2541

10%
X5R

201

0.047UF

10%

6.3V

2

2

X5R
201

IN

MEM_B_CS_L<0>

7

23 24 76

IN

MEM_B_CS_L<1>

7

23 24 76

IN

MEM_B_ODT<0>

23 24 70 76

IN

MEM_B_ZQ<0>
MEM_B_ZQ<1>

PP0V6_S3_MEM_VREFCA_B

23 68 76

PP0V6_S3_MEM_VREFDQ_B

23 68 76

B

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

U2500

LPDDR3-1600-32GB

EDFB232A1MA

FBGA

SYM 2 OF 2

VDD1

OMIT_TABLE

CRITICAL

VDD2

VDDCA

VDDQ

VSSCA

VSSQ

VSS

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

D

C

B

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

1

C2510

1UF

A

=PP1V8_S3_MEM

20 21 22 23 68

10%
10V

2

X5R
402

1

C2530

1UF

10%
10V

2

X5R
402

1

C2511

1UF

10%
10V

2

X5R
402

1

C2531

1UF

10%
10V

2

X5R
402

1

C2512

10UF

20%
25V

2

X5R-CERM
0603

1

C2532

10UF

20%
25V

2

X5R-CERM
0603

1

C2533

10UF

20%
25V

2

X5R-CERM
0603

6 3

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

CRITICAL

1

C2537

12PF

2%
50V

2

C0G-CERM
0402

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel B (00-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

25 OF 120

SHEET

22 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL B (32-63)

U2600

LPDDR3-1600-32GB

EDFB232A1MA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

1

C2601

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2621

1UF

10%
10V

2

X5R
402

FBGA

1

C2602

1UF

10%
10V

2

X5R
402

1

C2622

1UF

10%
10V

2

X5R
402

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2603

1UF

10%
10V

2

X5R
402

1

C2623

10UF

20%
25V

2

X5R-CERM
0603

=MEM_B_DQ<32>
=MEM_B_DQ<33>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<36>
=MEM_B_DQ<37>
=MEM_B_DQ<38>
=MEM_B_DQ<39>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DQ<44>
=MEM_B_DQ<45>
=MEM_B_DQ<46>
=MEM_B_DQ<47>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<52>
=MEM_B_DQ<53>
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<56>
=MEM_B_DQ<57>
=MEM_B_DQ<58>
=MEM_B_DQ<59>
=MEM_B_DQ<60>
=MEM_B_DQ<61>
=MEM_B_DQ<62>
=MEM_B_DQ<63>

=MEM_B_DQS_N<4>
=MEM_B_DQS_N<5>
=MEM_B_DQS_N<6>
=MEM_B_DQS_N<7>

=MEM_B_DQS_P<4>
=MEM_B_DQS_P<5>
=MEM_B_DQS_P<6>
=MEM_B_DQS_P<7>

1

C2604

1UF

10%
10V

2

X5R
402

1

C2624

10UF

20%
25V

2

X5R-CERM
0603

1

C2605

1UF

10%
10V

2

X5R
402

CRITICAL

1

C2634

12PF

2%
50V

2

C0G-CERM
0402

A10

U10

H12

K12

A11
C12

E12
G12

H11

J10

K11
L12

N12
R12
U11

A3
A4
A5
A6

U3
U4
U5
U6

A8
A9
D4
D5
D6
G5
H5
H6

J5
J6
K5
K6

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

E8

H8
H9

J9

K8

N8

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

1

C2606

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2635

12PF

2%
50V

2

C0G-CERM
0402

1

C2607

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2636

12PF

2%
50V

2

C0G-CERM
0402

=PP1V8_S3_MEM

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2600

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2620

1UF

10%
10V

2

X5R
402

J11

A12
A13

B13

T13

U12
U13

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

K3

CKE0

K4

CKE1

J3

CK_T

J2

CK_C

L3

CS0*

L4

CS1*

L8

DM0

G8

DM1

P8

DM2

D8

DM3

J8

ODT

B3

ZQ0

B4

ZQ1

H4

VREFCA
VREFDQ

A1
A2

B1

T1

NU

U1
U2

MEM_B_CAB<0>

24 70 76

IN

MEM_B_CAB<1>

24 70 76

IN

MEM_B_CAB<2>

24 70 76

IN

MEM_B_CAB<3>

24 70 76

IN

MEM_B_CAB<4>

24 70 76

IN

MEM_B_CAB<5>

24 70 76

IN

MEM_B_CAB<6>

24 70 76

IN

MEM_B_CAB<7>

24 70 76

IN

MEM_B_CAB<8>

24 70 76

IN

MEM_B_CAB<9>

24 70 76

IN

MEM_B_CKE<2>

7

24 76

IN

MEM_B_CKE<3>

7

24 76

IN

MEM_B_CLK_P<1>

7

24 76

IN

MEM_B_CLK_N<1>

7

24 76

C

R2600

243

1/20W

1

1%
MF

201

2

R2601

243

1/20W

1

1%
MF

201

2

0.047UF

C2640

6.3V

1

1

C2641

10%
X5R

201

0.047UF

10%

6.3V

2

2

X5R
201

IN

MEM_B_CS_L<0>

7

22 24 76

IN

MEM_B_CS_L<1>

7

22 24 76

IN

MEM_B_ODT<0>

22 24 70 76

IN

MEM_B_ZQ<2>
MEM_B_ZQ<3>

PP0V6_S3_MEM_VREFCA_B

22 68 76

PP0V6_S3_MEM_VREFDQ_B

22 68 76

B

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

U2600

LPDDR3-1600-32GB

EDFB232A1MA

FBGA

SYM 2 OF 2

VDD1

OMIT_TABLE

CRITICAL

VDD2

VDDCA

VDDQ

VSSCA

VSSQ

VSS

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

D

C

B

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

1

C2610

1UF

A

=PP1V8_S3_MEM

20 21 22 23 68

10%
10V

2

X5R
402

1

C2630

1UF

10%
10V

2

X5R
402

1

C2611

1UF

10%
10V

2

X5R
402

1

C2631

1UF

10%
10V

2

X5R
402

1

C2612

10UF

20%
25V

2

X5R-CERM
0603

1

C2632

10UF

20%
25V

2

X5R-CERM
0603

1

C2633

10UF

20%
25V

2

X5R-CERM
0603

6 3

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

CRITICAL

1

C2637

12PF

2%
50V

2

C0G-CERM
0402

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

26 OF 120

SHEET

23 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

Intel recommends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

=PP0V6_S0_MEM_VTT_A

68 68

MEM_A_CAA<9>

20 70 76

IN

MEM_A_CAA<8>

20 70 76

IN

MEM_A_CAA<6>

20 70 76

IN

MEM_A_CAA<7>

20 70 76

IN

MEM_A_CAA<5>

20 70 76

IN

MEM_A_CLK_P<0>

7

20 76

IN

MEM_A_CLK_N<0>

7

20 76

IN

MEM_A_CKE<1>

7

20 76

IN

MEM_A_CKE<0>

7

20 76

IN

MEM_A_CAA<4>

20 70 76

IN

MEM_A_CAA<3>

20 70 76

IN

MEM_A_CAA<2>

20 70 76

IN

MEM_A_CAA<1> MEM_B_CAA<1>

20 70 76

IN

MEM_A_CAA<0>

20 70 76

IN

MEM_A_CAB<9>

21 70 76

IN

MEM_A_CAB<8>

21 70 76

IN

MEM_A_CAB<6>

21 70 76

IN

MEM_A_CAB<7>

21 70 76

IN

MEM_A_CAB<5>

21 70 76

IN

MEM_A_CLK_P<1>

7

21 76

IN

MEM_A_CLK_N<1>

7

21 76

IN

MEM_A_CKE<2>

7

21 76

IN

MEM_A_CKE<3>

7

21 76

IN

MEM_A_CAB<4>

21 70 76

IN

MEM_A_CAB<2>

21 70 76

IN

MEM_A_CAB<3>

21 70 76

IN

MEM_A_CAB<1>

21 70 76

IN

MEM_A_CAB<0>

21 70 76

IN

MEM_A_CS_L<0>

7

20 21 76

IN

MEM_A_CS_L<1>

7

20 21 76

IN

MEM_A_ODT<0>

20 21 70 76

IN

R2700
R2701
R2702
R2703
R2704
R2705
R2706
R2707
R2708
R2709
R2710
R2711
R2712
R2713
R2714
R2715
R2716
R2717
R2718
R2719
R2720
R2721
R2722
R2723
R2724
R2725
R2726
R2727
R2728
R2729
R2730

56
56
56
56
56
39
39
82
82
56
56
56
56
56
56
56
56

82

56

56

82
82

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1/20W

201 MF1%

1/20W
1/20W

1%
1%

1/20W

201 MF1%

1/20W

1%

1/20W
1/20W

201

1/20W

201

1%

1/20W

201 MF
201 MF

1%

1/20W

201 MF

1%

1/20W
1/20W

1%

1/20W

201

1/20W

201

1/20W
1/20W

2011%
201

1/20W

1%

201

1/20W56MF1%
1/20W
1/20W39201 MF1%
1/20W392011%

1% 201

1/20W

1% 201

1/20W82MF

20156MF

1/20W

1%
1%561/20W

201 MF

1%

201

1/20W
1%561/20W
1% 201 MF

1/20W
1% 20182MF

1/20W
1% MF201

1/20W
1% 201 MF

1/20W

MF2011%

MF201
MF201

MF201
MF1%
MF1%

MF201
MF2011%
MF1%
MF1%
MF
MF

MF562011%

MF
MF

MF
MF201

1

C2700

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2701

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2703

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2705

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2707

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2709

0.47UF

20%
4V

2

CERM-X5R-1
201

CRITICAL

1

C2720

22UF

20%

6.3V

2

X5R-CERM-1
603

1

C2730

12PF

5%
25V

2

NP0-C0G
0201

1

C2702

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2704

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2706

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2708

0.47UF

20%
4V

2

CERM-X5R-1
201

=PP0V6_S0_MEM_VTT_B

MEM_B_CAA<9>

22 70 76

IN

MEM_B_CAA<8>

22 70 76

IN

MEM_B_CAA<7>

22 70 76

IN

MEM_B_CAA<6>

22 70 76

IN

MEM_B_CAA<5>

22 70 76

IN

MEM_B_CLK_P<0>

7

22 76

IN

MEM_B_CLK_N<0>

7

22 76

IN

MEM_B_CKE<1>

7

22 76

IN

MEM_B_CKE<0>

7

22 76

IN

MEM_B_CAA<4>

22 70 76

IN

MEM_B_CAA<2>

22 70 76

IN

MEM_B_CAA<3>

22 70 76

IN

22 70 76

IN

MEM_B_CAA<0>

22 70 76

IN

MEM_B_CAB<9>

23 70 76

IN

MEM_B_CAB<8>

23 70 76

IN

MEM_B_CAB<7>

23 70 76

IN

MEM_B_CAB<6>

23 70 76

IN

MEM_B_CAB<5>

23 70 76

IN

MEM_B_CLK_N<1>

7

23 76

IN

MEM_B_CLK_P<1>

7

23 76

IN

MEM_B_CKE<2>

7

23 76

IN

MEM_B_CKE<3>

7

23 76

IN

MEM_B_CAB<4>

23 70 76

IN

MEM_B_CAB<2>

23 70 76

IN

MEM_B_CAB<3>

23 70 76

IN

MEM_B_CAB<1>

23 70 76

IN

MEM_B_CAB<0>

23 70 76

IN

MEM_B_CS_L<0>

7

22 23 76

IN

MEM_B_CS_L<1>

7

22 23 76

IN

MEM_B_ODT<0>

22 23 70 76

IN

R2740
R2741
R2742
R2743
R2744
R2745
R2746
R2747
R2748
R2749
R2750
R2751
R2752
R2753
R2754
R2755
R2756
R2757
R2758
R2759
R2760
R2761
R2762
R2763
R2764
R2765
R2766
R2767
R2768
R2769
R2770

56
56
56
56
56
39
39

82
56
56
56
56
56
56
56
56
56

39
39
82
82
56
56
56
56
56

82

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1%

1/20W

201

1% MF

1/20W

201

1/20W

1% MF201

1/20W

1% MF201
1% 201 MF

1/20W

1% 201 MF

1/20W

1% 201 MF

1/20W
1/20W

1% 20182MF

2011%

1/20W
1/20W

1% MF201

1/20W

201

1/20W

201

1/20W

1% 201 MF

1/20W

1%

201 MF

1/20W

201 MF1%

1/20W

201 MF1%

1/20W

201 MF1%

1/20W

201 MF1%561/20W

1/20W

2011%
1/20W
1/20W

2011%
1/20W

1% MF

1/20W

201

1%

201

1/20W

201

1/20W

1%
1%

201 MF

1/20W

1%

201 MF

1/20W

2011%

1/20W82MF

1% 201

1/20W

1% 20182MF

1/20W

MF

MF

MF2011%
MF1%
MF1%

MF
MF2011%
MF
MF2011%

MF
MF

MF

1

C2710

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2711

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2713

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2715

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2717

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2719

0.47UF

20%
4V

2

CERM-X5R-1
201

CRITICAL

1

C2740

22UF

20%

6.3V

2

X5R-CERM-1
603

1

C2731

12PF

5%
25V

2

NP0-C0G
0201

1

C2712

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2714

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2716

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2718

0.47UF

20%
4V

2

CERM-X5R-1
201

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Termination

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=02/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

27 OF 120

SHEET

24 OF 82

124578

8 7 6 5 4 3

CRITICAL

OMIT_TABLE

U2800

FALCON RIDGE

FCBGA

SYM 1 OF 2

PCIE GEN2

RSVD_GND

GPIO_16/DEVICE_PCIE_RST_N

MISC

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P
REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMU_CLK_OUT

DPSRC_3_P
DPSRC_3_N

DPSRC_2_P
DPSRC_2_N

DPSRC_1_P
DPSRC_1_N

DPSRC_0_P
DPSRC_0_N

DISPLAY PORT

GPIO_2/TMU_CLK_IN/AC_PRESENT

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

GPIO_8/EN_CIO_PWR_N_OD

PB_CIO2_TX_P/DPSRC_0_P
PB_CIO2_TX_N/DPSRC_0_N

PB_CONFIG1/CIO_2_LSEO
PB_CONFIG2/CIO_2_LSOE

PB_CIO3_TX_P/DPSRC_2_P
PB_CIO3_TX_N/DPSRC_2_N

PORTS

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

DPSRC_AUX_P
DPSRC_AUX_N

DPSRC_HPD_OD

GPIO_3/FORCE_PWR
GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD
GPIO_7_OD/CIO_SCL_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_RX_P
PB_CIO2_RX_N

PB_CIO3_RX_P
PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO
PB_LSRX/CIO_3_LSOE

PB_DPSRC_1_P
PB_DPSRC_1_N

PB_DPSRC_3_P
PB_DPSRC_3_N

PB_DPSRC_HPD

GPIO_1/PB_HV_EN/BYP0

PETP_0
PETN_0

PETP_1
PETN_1

PETP_2
PETN_2

PETP_3
PETN_3

RSENSE

RBIAS

GPIO_17
GPIO_18
GPIO_19

GPIO_14
GPIO_15

PB_AUX_P
PB_AUX_N

AD5

PCIE_TBT_D2R_C_P<0>

81

AD7

PCIE_TBT_D2R_C_N<0>

81

AD9

PCIE_TBT_D2R_C_P<1>

71 81
81

AD11

PCIE_TBT_D2R_C_N<1>

71

81

AD13

PCIE_TBT_D2R_C_P<2>

71
81

AD15

PCIE_TBT_D2R_C_N<2>

71

81

AD17

PCIE_TBT_D2R_C_P<3>

71
81

AD19

PCIE_TBT_D2R_C_N<3>

71

U20

TBT_RSENSE

W20

TBT_RBIAS

AD1
L8

Used for straps in host mode

W6

TP_TBT_PCIE_RESET0_L

AB3

TBT_DFT_STRAP_1

AD3

TBT_ROM_SECURITY_XOR

V1

TBT_DFT_STRAP_3

V3

TBT_CLKREQ_L

AB21

PCIE_CLK100M_TBT_P

AD21

PCIE_CLK100M_TBT_N

AA24

SYSCLK_CLK25M_TBT_R

74

AB23

TP_TBT_XTAL25OUT

AA4

TBT_TMU_CLK_OUT

A14

TP_DP_TBTSRC_ML_CP<3>

B15

TP_DP_TBTSRC_ML_CN<3>

A12

TP_DP_TBTSRC_ML_CP<2>

B13

TP_DP_TBTSRC_ML_CN<2>

A10

TP_DP_TBTSRC_ML_CP<1>

B11

TP_DP_TBTSRC_ML_CN<1>

A8

TP_DP_TBTSRC_ML_CP<0>

B9

TP_DP_TBTSRC_ML_CN<0>

J4

TP_DP_TBTSRC_AUXCH_CP

J2

TP_DP_TBTSRC_AUXCH_CN

AC2

DP_TBTSRC_HPD

U2

TBT_GPIO2

L6

TBT_PWR_EN

H5

=TBT_WAKE_L

Y7

TBT_CIO_PLUG_EVENT_L

Y1

HDMITBTMUX_SEL_TBT

T7

TBT_GPIO7

V7

TBT_EN_CIO_PWR_L

M7

=TBT_BATLOW_L

T1

TBTDP_AUXIO_EN

T3

TBT_DDC_XBAR_EN_L

R24

TBT_B_R2D_C_P<0>

N24

TBT_B_R2D_C_N<0>

R22

TBT_B_D2R_P<0>

N22

TBT_B_D2R_N<0>

D3

TBT_B_CONFIG1_BUF

M1

TBT_B_CONFIG2_RC

W24

TBT_B_R2D_C_P<1>

U24

TBT_B_R2D_C_N<1>

W22

TBT_B_D2R_P<1>

U22

TBT_B_D2R_N<1>

M5

TBT_B_LSTX

P7

TBT_B_LSRX

A20

DP_TBTPB_ML_C_P<1>

B21

DP_TBTPB_ML_C_N<1>

A22

DP_TBTPB_ML_C_P<3>

B23

DP_TBTPB_ML_C_N<3>

K3

DP_TBTPB_AUXCH_C_P

K1

DP_TBTPB_AUXCH_C_N

N6

DP_TBTPB_HPD

F1

TBT_B_HV_EN
TBT_B_CIO_SEL
TBT_B_DP_PWRDN

C2840
C2841

C2842
C2843

C2844
C2845

C2846
C2847

1

R2855

1K

1%
1/20W
MF
201

2

69

12

OUT

12 71 81

IN

12 71 81

IN

69

69

69

69

69

69

69

69

69

69

69

25

15

IN

39

OUT

18 75

OUT

25 69

IN

25 26

OUT

25 27

IN

25 28 29

OUT

25 30

OUT

29 71 77

OUT

29 71 77

OUT

29 71 77

IN

29 71 77

IN

29

IN

29

IN

29 71 77

OUT

29 71 77

OUT

29 71 77

IN

29 71 77

IN

29

OUT

29

IN

29 77

OUT

29 77

OUT

29 77

OUT

29 77

OUT

BI
BI

29

IN

25 29 30

OUT

29

OUT

25 29

OUT

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

29 77

29 77

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

PCIE_TBT_D2R_P<0>

X5R-CERM

10% 16V

PCIE_TBT_D2R_N<0>

10% 16V

X5R-CERM

PCIE_TBT_D2R_P<1>

X5R-CERM

10% 16V

PCIE_TBT_D2R_N<1>

X5R-CERM

10% 16V

PCIE_TBT_D2R_P<2>

X5R-CERM

10% 16V

PCIE_TBT_D2R_N<2>

10% 16V

X5R-CERM

PCIE_TBT_D2R_P<3>

X5R-CERM

10% 16V

PCIE_TBT_D2R_N<3>

X5R-CERM

16V10%

Security strap setting is XORed with
bit in the flash, so the active-level
depends on the code in the flash.

0201

0201

0201

0201

0201

0201

0201

0201

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

If strap != bit then security is enabled?

Divides 3.3V to 1.8V

R2895

806

NO STUFF

R2899

10K

5%

1/20W

MF

201

R2878

100K 100K

5%

1/20W

MF

201

1 2

1

1

R2896

1K

5%
1/20W
MF
201

2

2

PP3V3_TBTLC

1

1

R2879

5%
1/20W
MF
201

2

2

NOTE: The following pins require testpoints:
0 - GPIO_13
1 - GPIO_1
2 - GPIO_2
3 - GPIO_3
4 - GPIO_5
5 - PCIE_RST_1_N
6 - PCIE_RST_2_N
7 - PCIE_RST_3_N

SYSCLK_CLK25M_TBT

1%

1/20W

MF

201

25 26

25 30

25 69

25 28 29

25

SYNC_MASTER=T29_RR

PAGE TITLE

TBT_EN_CIO_PWR_L
TBT_DDC_XBAR_EN_L
HDMITBTMUX_SEL_TBT
TBTDP_AUXIO_EN
DP_TBTSRC_HPD

18 25 26 68

25 27

25 28

25 29

25 27 28

25 29 30

Thunderbolt Host (1 of 2)

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=TBT

IV ALL RIGHTS RESERVED

PP3V3_TBTLC

18 25 26 68

PP3V3_TBTLC

18 25 26 68

=PP3V3_S4_TBT

25 26 27 68

=PP3V3_S4_TBT

25 26 27 68

=TBT_BATLOW_L
TBT_A_DP_PWRDN
TBT_B_DP_PWRDN
TBT_A_HV_EN
TBT_B_HV_EN

8 - GPIO_15
9 - GPIO_11
10 - GPIO_14
11 - GPIO_0
12 - GPIO_12
13 - GPIO_10
14 - PB_LSTX
15 - PB_LSRX

Apple Inc.

R

1

R2861

10K

5% 5%
1/20W
MF
201

2

17 74

IN

1

R2881

100K

5%

1/20W

MF

201

2

1

R2884

100K

5%

1/20W

MF

201

2

10K

1/20W

201

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1

5%
MF

2

1 2

10%

1 2

10%

1 2

10%

1 2

10%

1 2

10%

1 2

10%

1 2

10%

1 2

10%

R2815

NOSTUFF

1

R2825

100

5%
1/20W
MF
201

2

13

OUT

R2830

100K

1/20W

67

OUT

R2831

100K

1/20W

201

201

OMIT

NONE
NONE
NONE
0201

5%
MF

5%
MF

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

1

2

1

2

1

2

81

PCIE_TBT_R2D_P<0>

71

0201

PCIE_TBT_R2D_N<0>

71 81

0201

81

PCIE_TBT_R2D_P<1>

71

0201

PCIE_TBT_R2D_N<1>

71 81

0201

81

PCIE_TBT_R2D_P<2>

71

0201

PCIE_TBT_R2D_N<2>

71 81

0201

81

PCIE_TBT_R2D_P<3>

71

0201

PCIE_TBT_R2D_N<3>

71 81

0201

TBT_PCIE_RESET_L

18

IN

TBT_PWR_ON_POC_RST_L

26

IN

TP_TBT_MONDC0

69

TP_TBT_MONDC1

69

DEBUG: For monitoring current/voltage

TBT_MONOBSP
TBT_MONOBSN

DEBUG: For monitoring clock

TP_TBT_THERM_DP

45

Use AA8 GND ball for THERM_DN

TBT_SPI_MOSI

77

TBT_SPI_MISO

77

TBT_SPI_CS_L

77

TBT_SPI_CLK

77

JTAG_TBT_TDI

18

IN

JTAG_TBT_TMS

18

IN

JTAG_TBT_TCK

18

IN

JTAG_TBT_TDO

18

OUT

TBT_TEST_EN
TBT_TEST_PWR_GOOD

DP_TBTSNK0_ML_P<3>

25 77

DP_TBTSNK0_ML_N<3>

25 77

DP_TBTSNK0_ML_P<2>

25 77

DP_TBTSNK0_ML_N<2>

25 77

DP_TBTSNK0_ML_P<1>

25 77

DP_TBTSNK0_ML_N<1>

25 77

DP_TBTSNK0_ML_P<0>

25 77

DP_TBTSNK0_ML_N<0>

25 77

DP_TBTSNK0_AUXCH_P

25 77

DP_TBTSNK0_AUXCH_N

25 77

DP_TBTSNK0_HPD

DP_TBTSNK1_ML_P<3>

25 77

DP_TBTSNK1_ML_N<3>

25 77

DP_TBTSNK1_ML_P<2>

25 77

DP_TBTSNK1_ML_N<2>

25 77

DP_TBTSNK1_ML_P<1>

25 77

DP_TBTSNK1_ML_N<1>

25 77

DP_TBTSNK1_ML_P<0>

25 77

DP_TBTSNK1_ML_N<0>

25 77

DP_TBTSNK1_AUXCH_P

25 77

DP_TBTSNK1_AUXCH_N

25 77

DP_TBTSNK1_HPD

TBT_A_R2D_C_P<0>

28 71 77

OUT

TBT_A_R2D_C_N<0>

28 71 77

OUT

TBT_A_D2R_P<0>

28 71 77

IN

TBT_A_D2R_N<0>

28 71 77

IN

TBT_A_CONFIG1_BUF

28

IN

TBT_A_CONFIG2_RC

28

IN

TBT_A_R2D_C_P<1>

28 71 77

OUT

TBT_A_R2D_C_N<1>

28 71 77

OUT

TBT_A_D2R_P<1>

28 71 77

IN

TBT_A_D2R_N<1>

28 71 77

IN

TBT_A_LSTX

28

OUT

TBT_A_LSRX

28

IN

DP_TBTPA_ML_C_P<1>

28 77

OUT

DP_TBTPA_ML_C_N<1>

28 77

OUT

DP_TBTPA_ML_C_P<3>

28 77

OUT

DP_TBTPA_ML_C_N<3>

28 77

OUT

DP_TBTPA_AUXCH_C_P

28 77

BI

DP_TBTPA_AUXCH_C_N

28 77

BI

DP_TBTPA_HPD

28

IN

TBT_A_HV_EN

25 27 28

OUT

TBT_A_CIO_SEL

28

OUT

TBT_A_DP_PWRDN

25 28

OUT

AB9

PERP_0

AA10

PERN_0

AA12

PERP_1

AB13

PERN_1

AB15

PERP_2

AA16

PERN_2

AA18

PERP_3

AB19

PERN_3

P5

PERST_OD_N

R4

PWR_ON_POC_RSTN

AD23

MONDC0

AC24

MONDC1

W18

MONOBSP

W16

MONOBSN

AB7

THERMDA

AA2

EE_DI

Y3

EE_DO

T5

EE_CS_N

U8

EE_CLK

W2

TDI

AB1

TMS

AA6

TCK

U6

TDO

R6

TEST_EN

W8

TEST_PWR_GOOD

E14

DPSNK0_3_P

D13

DPSNK0_3_N

E16

DPSNK0_2_P

D15

DPSNK0_2_N

E18

DPSNK0_1_P

D17

DPSNK0_1_N

E20

DPSNK0_0_P

D19

DPSNK0_0_N

G4

DPSNK0_AUX_P

G2

DPSNK0_AUX_N

AB5

DPSNK0_HPD

E6

DPSNK1_3_P

D5

DPSNK1_3_N

E8

DPSNK1_2_P

D7

DPSNK1_2_N

E10

DPSNK1_1_P

D9

DPSNK1_1_N

E12

DPSNK1_0_P

D11

DPSNK1_0_N

H3

DPSNK1_AUX_P

H1

DPSNK1_AUX_N

U4

DPSNK1_HPD

G24

PA_CIO0_TX_P/DPSRC_0_P

E24

PA_CIO0_TX_N/DPSRC_0_N

G22

PA_CIO0_RX_P

E22

PA_CIO0_RX_N

P1

PA_CONFIG1/CIO_0_LSEO

K5

PA_CONFIG2/CIO_0_LSOE

L24

PA_CIO1_TX_P/DPSRC_2_P

J24

PA_CIO1_TX_N/DPSRC_2_N

L22

PA_CIO1_RX_P

J22

PA_CIO1_RX_N

N8

PA_LSTX/CIO_1_LSEO

J6

PA_LSRX/CIO_1_LSOE

A16

PA_DPSRC_1_P

B17

PA_DPSRC_1_N

A18

PA_DPSRC_3_P

B19

PA_DPSRC_3_N

L4

PA_AUX_P

L2

PA_AUX_N

M3

PA_DPSRC_HPD

R8

GPIO_0/PA_HV_EN/BYP0

N2 R2

GPIO_10/PA_CIO_SEL/BYP1

P3 F3

GPIO_12/PA_DP_PWRDN/BYP2

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

PCIE_TBT_R2D_C_P<0>

14 71 81

IN

PCIE_TBT_R2D_C_N<0>

14 71 81

IN

PCIE_TBT_R2D_C_P<1>

14 71 81

IN

PCIE_TBT_R2D_C_N<1>

14 71 81

IN

PCIE_TBT_R2D_C_P<2>

14 71 81

D

BYPASS=U2890::2mm

1

201

1

R2891

3.3K

5%

5%
1/20W

MF

MF
201

2

2

R2890

3.3K

1/20W

(TBT_SPI_CLK)
(TBT_SPI_CS_L)

TBTROM_WP_L

C

TBTROM_HOLD_L

C2890

1UF

10%

6.3V
CERM

402

1

2

5 2

6

1

3

DI/IO0

U2890

CLK

4MBIT

W25X40CLXIG

CS*

WP*

HOLD*

GND

479

8

VCC

DO/IO1

USON

THRM_PAD

CRITICAL
OMIT_TABLE

IN

PCIE_TBT_R2D_C_N<2>

14 71 81

IN

PCIE_TBT_R2D_C_P<3>

14 71 81

IN

PCIE_TBT_R2D_C_N<3>

14 71 81

IN

(TBT_SPI_MISO)(TBT_SPI_MOSI)

R2892

3.3K

1/20W

201

18 25 26 68

1

5%
MF

2

C2800
C2801

C2802
C2803

C2804
C2805

C2806
C2807

PP3V3_TBTLC

1

R2893

3.3K

5%
1/20W
MF
201

2

R2829

SNK0 AC Coupling

DP_TBTSNK0_ML_C_P<0>

5

77

IN

DP_TBTSNK0_ML_C_N<0>

5

77

IN

DP_TBTSNK0_ML_C_P<1>

5

77

IN

DP_TBTSNK0_ML_C_N<1>

5

77

IN

B

DP_TBTSNK0_ML_C_P<2>

5

77

IN

DP_TBTSNK0_ML_C_N<2>

5

77

IN

DP_TBTSNK0_ML_C_P<3>

5

77

IN

DP_TBTSNK0_ML_C_N<3>

5

77

IN

DP_TBTSNK0_AUXCH_C_P

13 77

BI

DP_TBTSNK0_AUXCH_C_N

13 77

BI

C2820
C2821

C2822
C2823

C2824
C2825

C2826
C2827

C2828
C2829

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

DP_TBTSNK0_ML_P<0>

10% 16V

0201

X5R-CERM

DP_TBTSNK0_ML_N<0>

10% 16V

0201

X5R-CERM

DP_TBTSNK0_ML_P<1>

16V10%

0201

X5R-CERM

DP_TBTSNK0_ML_N<1>

10% 16V

0201

X5R-CERM

DP_TBTSNK0_ML_P<2>

16V10%

0201

X5R-CERM

DP_TBTSNK0_ML_N<2>

10% 16V

0201

X5R-CERM

DP_TBTSNK0_ML_P<3>

16V10%

0201

X5R-CERM

DP_TBTSNK0_ML_N<3>

10% 16V

0201

X5R-CERM

DP_TBTSNK0_AUXCH_P

16V10%

0201

X5R-CERM

DP_TBTSNK0_AUXCH_N

10% 16V

0201

X5R-CERM

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

SNK1 AC Coupling

DP_TBTSNK1_ML_C_P<0>

67 77

IN

DP_TBTSNK1_ML_C_N<0>

67 77

IN

DP_TBTSNK1_ML_C_P<1>

67 77

IN

DP_TBTSNK1_ML_C_N<1>

67 77

IN

DP_TBTSNK1_ML_C_P<2>

67 77

A

IN

DP_TBTSNK1_ML_C_N<2>

67 77

IN

DP_TBTSNK1_ML_C_P<3>

67 77

IN

DP_TBTSNK1_ML_C_N<3>

67 77

IN

DP_TBTSNK1_AUXCH_C_P

67 77

BI

DP_TBTSNK1_AUXCH_C_N

67 77

BI

C2830
C2831

C2832
C2833

C2834
C2835

C2836
C2837

C2838
C2839

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

DP_TBTSNK1_ML_P<0>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_N<0>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_P<1>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_N<1>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_P<2>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_N<2>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_P<3>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_N<3>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_AUXCH_P

10% 16V

0201

X5R-CERM

DP_TBTSNK1_AUXCH_N

10% 16V

0201

X5R-CERM

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

6 3

12

NO STUFF

1

R2867

10K

5%
1/20W
MF
201

2

1

5%
MF

201

2

1

5%
MF

201

2

1

10K

5%
MF

201

2

1

10K

5% 5%
MF

201

2

1

R2863

10K

2

1

R2882

100K

2

1

R2883

100K

2

NO STUFF

1

R2886

10K

2

1

R2887

10K

2

1

R2862

10K

5%
1/20W
MF
201

2

R2880

100K

1/20W

R2832

100K

1/20W

NO STUFF

R2885

1/20W

R2888

1/20W

SYNC_DATE=01/19/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

28 OF 120

SHEET

25 OF 82

124578

1/20W
MF
201

5%
1/20W
MF
201

5%
1/20W
MF
201

5%
1/20W
MF
201

1/20W
MF
201

SIZE

D

C

B

A

D