Apple macbook pro a1502 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

3456

REV ECN

DESCRIPTION OF REVISION

12

CK
APPD

DATE

8

0003549590

ENGINEERING RELEASED

2014-12-19

X304 MLB SCHEMATIC - DVT

Fri Dec 19 12:14:48 2014

D

C

B

Page DateSync

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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8

9
10
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42

(.csa)

1

Table of Contents

2

BOM Configuration

3

BOM Configuration

4

PD Parts

5

CPU GFX,NCTF,RSVD

6

CPU Misc,JTAG,CFG,RSVD

7

CPU LPDDR3 Interfaces

8

CPU & PCH Power

9

CPU & PCH Grounds

10

CPU Decoupling

12

PCH Decoupling

13

PCH Audio/JTAG/SATA/CLK

14

PCH PM/PCI/GFX

15

PCH PCIe,USB,LPC,SPI,SMBus

16

PCH GPIO/MISC/LPIO

18

CPU/PCH Merged XDP

19

Chipset Support

20

Project Chipset Support

22

LPDDR3 VREF Margining

23

LPDDR3 DRAM Channel A (00-31)

24

LPDDR3 DRAM Channel A (32-63)

25

LPDDR3 DRAM Channel B (00-31)

26

LPDDR3 DRAM Channel B (32-63)

27

LPDDR3 DRAM Termination

28

Thunderbolt Host (1 of 2)

29

Thunderbolt Host (2 of 2)

30

Thunderbolt Mobile Support

32

Thunderbolt Connector A

33

Thunderbolt Connector B

34

DDC Crossbar

35

Wireless Support

37

SSD Connector

39

Camera (1 of 2)

40

Camera (2 of 2)

46

External A USB3 Connector

48

Keyboard & Trackpad (1 of 2)

49

Keyboard & Trackpad (2 of 2)

50

SMC

51

SMC Shared Support

52

SMC Project Support

53

SMBus Connections

54

Power Sensors: High Side

Contents

YHARTANTO_J44

SHART_J44

J14

LDUNN_J44

J41

J41

J41

J41

J41

J41

J41

J41

J41

J41

J41

WFERRY_J43

J41

J41

YHARTANTO_J44

J41_MLB

J41_MLB

J41_MLB

J41_MLB

J41_MLB

T29_RR

T29_RR

T29_RR

T29_RR

T29_RR

J14

J41

YHARTANTO_J44

J45

J41

J41

JACK_J52

JACK_J52

JACK_J52

JACK_J52

JACK_J52

GKOO_J52

JACK_J52

12/21/2012

11/27/2012

09/04/2012

01/13/2013

10/23/2012

10/23/2012

10/23/2012

10/23/2012

10/23/2012

10/23/2012

10/23/2012

12/17/2012

02/21/2013

10/23/2012

01/19/2013

12/21/2012

01/30/2013

10/23/2012

01/02/2013

02/06/2013

02/06/2013

02/06/2013

02/06/2013

02/06/2013

01/19/2013

12/17/2012

11/19/2012

10/26/2012

10/26/2012

10/23/2012

11/01/2012

12/18/2012

01/24/2013

12/21/2012

10/23/2012

01/28/2014

01/31/2014

11/07/2013

10/24/2013

11/07/2013

12/06/2013

12/15/2013

(.csa)

Page Sync Date

55

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

Power Sensors: Load Side

56

Power Sensors: Extended

58

Thermal Sensors

60

Fan

61

SPI Debug Connector

62

Audio: Codec,Analog

63

Audio: Codec,Digital

64

Audio: Speaker Amps

65

Audio: Jack Support

66

Audio: Jack Translators

70

DC-In & Battery Connectors

71

PBus Supply & Battery Charger

72

CPU VR12.6 VCC Regulator IC

73

CPU VR12.6 VCC Power Stage

74

LPDDR3 Supply

75

5V & 3.3V Power Supply

76

1.05V Power Supply

77

LCD & KBD Backlight Driver

78

Misc Power Supplies

79

X239 Power Supply

80

Power FETs

81

Power Control

83

eDP Display Connector

95

RIO Connector

97

Display Mux: HDMI vs DP

100

Power Aliases

102

Signal Aliases

103

Memory Bit & Byte Swizzle

104

Functional & ICT Test

110

PCB Rule Definitions

111

CPU Constraints

112

USB Constraints

113

PCH Constraints

114

Memory Constraints

115

TBT,DP,HDMI Constraints

116

Camera Constraints

117

SMC Constraints

118

Project Specific Constraints

119

PCIe Constraints

120

Reference

Contents

JACK_J52

JACK_J52

YHARTANTO_J44

J41

YHARTANTO_J44

JCURCIO_J44

JCURCIO_J44

DIRK_J44

JCURCIO_J44

JCURCIO_J44

YHARTANTO_J44

AHARTMAN_J52

J41

J41

J41_MLB

J14

AHARTMAN_J52

SHART_J44

AHARTMAN_J52

AHARTMAN_J52

J41

AHARTMAN_J52

GKOO_J52

GKOO_J52

SRAMAN_J44

SHART_J44

SHART_J44

AHARTMAN_J52

GKOO_J52

YHARTANTO_J44

YHARTANTO_J44

YHARTANTO_J44

YHARTANTO_J44

YHARTANTO_J44

GKOO_J52

YHARTANTO_J44

YHARTANTO_J44

YHARTANTO_J44

YHARTANTO_J44

J14

12/06/2013

10/26/2013

01/07/2013

10/23/2012

01/09/2013

05/13/2013

07/25/2013

01/09/2013

07/25/2013

05/13/2013

01/09/2013

11/06/2013

10/23/2012

10/23/2012

05/21/2013

10/23/2012

10/29/2013

11/20/2012

11/06/2013

11/06/2013

10/23/2012

11/06/2013

05/04/2014

05/01/2014

01/29/2013

01/14/2013

11/19/2012

10/29/2013

12/06/2013

12/14/2012

01/13/2013

01/07/2013

01/08/2013

01/02/2013

12/06/2013

01/09/2013

01/02/2013

01/04/2013

01/13/2013

10/23/2012

D

C

B

A

Schematic / PCB #’s

PART NUMBER

051-1573

820-4924

QTY

1

8 7 6 5 4 2 1

DESCRIPTION

SCHEM,MLB,X304

PCBF,MLB,X304

REFERENCE DES

SCH1

PCB

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

SIZE

A

D

DRAWING TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SCHEM,MLB,X304

Apple Inc.

R

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

1 OF 120

SHEET

1 OF 82

3

8 7 6 5 4 3

12

BOM Groups

BOM GROUP

X304_COMMON
X304_COMMON1
X304_COMMON2
X304_COMMON3

X304_PROGPARTS
X304_DEVEL:ENG

D

X304_DEVEL:DVT
X304_DEVEL:PVT

ENGISNS

ALTERNATE,COMMON,X304_COMMON1,X304_COMMON2,X304_COMMON3,X304_COMMON4,X304_PROGPARTS
TBTHV:P15V,SKIP_5V3V3:AUDIBLE,PANEL:NEW,SSD_CLKREQ:BI
EDP,EDP_LS_CAP,CAMERA_3V3:S0,CAM_WAKE:NO,CAM_XTAL:NO,VCORE_FETS

XDP,SAMCONN,BKLT:PROD,CPUTHRM:ALRT,LOADRC:NO,OTHERRC:NO,DDRRC:NO,TBTRC:NO,BMONRC:NO,TPADRC:NO

SMC_PROG:PROTO0,BOOTROM_PROG,TBTROM_PROG

ALTERNATE,ENGISNS,XDP_CONN,DBGLED

ALTERNATE,ENGISNS,XDP_CONN,S0PGOOD_ISL
ALTERNATE
LOADISNS,OTHERISNS,DDRISNS,TBTISNS,BMONISNS,TPADISNS

Module Parts

PART NUMBER

337S00107
337S00108
337S00109

998-7866
338S1247
338S1264
376S1194

376S1193
376S00036
376S00037

QTY

1

CPU,BW,SR26K,PRQ,F0-B2,2.7,28W,1.05,1168

1

1
1

IC,BCM15700A2KFEB4G,S2 CMRA,8X8,208FCBGA

1
2
2
2
2

DESCRIPTION

CPU,BW,SR26H,PRQ,F0-B2,2.9,28W,1.1,1168

CPU,BW,SR26E,PRQ,F0-B2,3.1,28W,1.1,1168

INTERPOSER,BGA1168P, SINGLE SIDE

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,52A,5.9MO,3.3X3.3 DFN8

MOSFET,N-CH,30V,64A,3.5MO,3.3X3.3 DFN8

C

Programmables (All Builds)

TBT

PART NUMBER

341S00192

SMC

EFI ROM

341S00235

QTY

1

1

1

DESCRIPTION

T29,EPROM,FALCON RIDGE (V27.1) EVT2,X304

IC,SMC-B1,EXT(V2.21A5) PROTO 0,X304

EFI ROM,MLB (V0145) DVT,X304

REFERENCE DES

U0500
U0500
U0500

U0500
U2800

U3900
Q7310,Q7320
Q7311,Q7321
Q7310,Q7320
Q7311,Q7321

REFERENCE DES

U2890

U5000

U6100

BOM OPTIONS

CRITICAL

CRITICAL
CRITICAL1CPU_BDW23:2.9G
CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

CPU_BDW23:2.7G

CPU_BDW23:3.1G

VCORE_FET:VSHY

VCORE_FET:VSHY
VCORE_FET:ONSMI
VCORE_FET:ONSMI

CRITICAL

CRITICAL

CRITICAL341S3982

CRITICAL

SMC_PROG:PROTO0

BOM OPTION

CPU_SOCKET

BOM OPTION

TBTROM_PROG

BOOTROM_PROG

DVT

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Strategic Silicon

PART#

337S00068

337S00069

337S00070

337S00071

353S00200

333S0790 07

333S00004

338S1247 01

353S3931

353S00095

343S0511 01

338S1264S201

333S0700

333S0704

343S0649

353S4080

353S2888

353S2958

353S2929

353S00036

353S4160

343S0666 01

341S00192

341S00235

STRATEGIC VALUE

08

08

08

08

07

07333S0786

07333S0784

07333S0792

07

02311S0597

01359S0197

01

01353S3812

01353S3814

01

01353S3328

01

01

01353S3054

01

01

01

01

01

01

01

01341S3982

01

01

COMMENT

CPU

CPU

CPU

CPU

TPAD ELEC FUSE

SYS MEMORY HYNIX

SYS MEMORY HYNIX

SYS MEMORY MICRON

SYS MEMORY MICRON

SYS MEMORY SAMSUNG

KEYBOARD I2C EXPANDER

GREEN CLOCK

FALCON RIDGE

TBT PWR MUX

TBT MUX

TBT MUX

DDC CROSSBAR

DDC CROSSBAR

PCIE DELAY IC

S2 MEMORY

S2 MEMORY

USB POWER/SAFETY

SMC RESET CHIP

AUDIO

AUDIO AMPS

AUDIO AMPS

BAT CHARGER

VR12.6 CONTROLLER

BEN

SAK, HDMI SELECT

SMC

T29 ROM

EFI ROM

TABLE_STRATEGIC_HEAD

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

TABLE_STRATEGIC__ITEM

D

C

Variable BOM Groups

BOM GROUP

X304_COMMON4

Development/Base BOMs

B

PART NUMBER

685-1314
985-1319

QTY

1
1

Sub-BOMs

PART NUMBER

QTY

1

Main DRAM SPD Straps

BOM GROUP

RAM_16G_HYNIX_1600
RAM_16G_HYNIX_1866

RAM_8G_HYNIX_1600
RAM_8G_HYNIX_1866
RAM_4G_HYNIX_1600
RAM_4G_HYNIX_1866

RAM_16G_ELPIDA_1600

A

RAM_16G_ELPIDA_1866

RAM_8G_ELPIDA_1600
RAM_8G_ELPIDA_1866
RAM_4G_ELPIDA_1600

RAM_4G_ELPIDA_1866
RAM_8G_SAMSUNG_1600
RAM_8G_SAMSUNG_1866
RAM_4G_SAMSUNG_1600
RAM_4G_SAMSUNG_1866

DESCRIPTION

X304 MLB COMMON BOM

X304 MLB DEVEL BOM

DESCRIPTION

VCORE FET,VSHY,X304

BOM OPTIONS

SMCBOARDID:16

REFERENCE DES

BASE

DEVEL

REFERENCE DES

VCOREFETS

CRITICAL

CRITICAL
CRITICAL

CRITICAL

CRITICAL685-1318

BOM OPTIONS

16G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

16G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

8G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

8G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

4G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

4G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

16G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

16G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

8G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

8G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

4G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

8G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

8G_SAMSUNG_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

4G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

4G_SAMSUNG_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTION

BASE_BOM

DEVEL_BOM

BOM OPTION

VCORE_FETS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Main DRAM Parts

PART NUMBER

333S0783
333S0784
333S0785
333S0786
333S0787
333S0788
333S0789
333S0790
333S0791
333S0792
333S0793

333S0794
333S00003
333S00004
333S00001
333S00002

QTY

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

4
4

IC,SDRAM,29nm 16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,29nm 16Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,29nm 8Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,29nm 8Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,25nm 16Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,25nm 16Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,25nm 8Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,25nm 8Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,23nm 16Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,23nm 16Gb,LPDDR3-1866,178P FBGA

4

IC,SDRAM,23nm 8Gb,LPDDR3-1600,178P FBGA

4

IC,SDRAM,23nm 8Gb,LPDDR3-1866,178P FBGA

4

S2 DRAM Parts

PART NUMBER

333S0700

QTY

IC,SDRAM,4GBIT.DDR3L-1600,HUMA,96B BGA

1

DESCRIPTION

DESCRIPTION

REFERENCE DES

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

U2300,U2400,U2500,U2600

REFERENCE DES

6 3

U4000

CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

CRITICAL

BOM OPTION

16G_HYNIX_1600
16G_HYNIX_1866

8G_HYNIX_1600
8G_HYNIX_1866
4G_HYNIX_1600

4G_HYNIX_1866
16G_ELPIDA_1600
16G_ELPIDA_1866

8G_ELPIDA_1600
8G_ELPIDA_1866
4G_ELPIDA_1600

4G_ELPIDA_1866
8G_SAMSUNG_1600
8G_SAMSUNG_1866
4G_SAMSUNG_1600
4G_SAMSUNG_1866

BOM OPTION

SYNC_MASTER=SHART_J44

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/27/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

2 OF 120

SHEET

2 OF 82

124578

SIZE

B

A

D

8 7 6 5 4 3

12

BOM Variants

BOM NUMBER

685-1314

985-1319
639-00772
639-00773
639-00774

D

639-00775
639-00776
639-00777
639-00778
639-00779
639-00780
639-00781
639-00782
639-00783
639-00784
639-00785
639-00786

COMMON,MLB,X304
DEV,MLB,X304
MLB,BDW2+3,2.7GHz,8GB-HY-1866,X304
MLB,BDW2+3,2.7GHz,16GB-HY-1866,X304
MLB,BDW2+3,2.7GHz,8GB-EP-1866,X304
MLB,BDW2+3,2.7GHz,16GB-EP-1866,X304
MLB,BDW2+3,2.7GHz,8GB-SM-1866,X304
MLB,BDW2+3,2.9GHz,8GB-HY-1866,X304
MLB,BDW2+3,2.9GHz,16GB-HY-1866,X304
MLB,BDW2+3,2.9GHz,8GB-EP-1866,X304
MLB,BDW2+3,2.9GHz,16GB-EP-1866,X304
MLB,BDW2+3,2.9GHz,8GB-SM-1866,X304
MLB,BDW2+3,3.1GHz,8GB-HY-1866,X304
MLB,BDW2+3,3.1GHz,16GB-HY-1866,X304
MLB,BDW2+3,3.1GHz,8GB-EP-1866,X304
MLB,BDW2+3,3.1GHz,16GB-EP-1866,X304
MLB,BDW2+3,3.1GHz,8GB-SM-1866,X304

BOM NAME

X304_COMMON
X304_DEVEL:ENG
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_16G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_16G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_SAMSUNG_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_16G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_16G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_SAMSUNG_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_16G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_16G_ELPIDA_1866
BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_SAMSUNG_1866

BOM OPTIONS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

C

BOM NUMBER

639-00035
639-00036

685-1318
685-00022

BOM NAME

PCBA,MLB,NO CPU,X304
PCBA,MLB,CPU SOCKET,X304
VCORE FET,VSHY,X304

BASE_BOM,DEVEL_BOM,RAM_8G_HYNIX_1866
BASE_BOM,DEVEL_BOM,CPU_SOCKET,RAM_8G_HYNIX_1866
VCORE_FET:VSHY

VCORE FET,ONSMI,X304 VCORE_FET:ONSMI

BOM OPTIONS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

B

Alternate Parts

PART NUMBER

685-00022

A

ALTERNATE FOR
PART NUMBER

685-1318
333S0700333S0704

BOM OPTION

REF DES

ALL
ALL

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Onsemi alt to Vishay for CPU Core Mosfets

TABLE_ALT_ITEM

Elpida alt to Hynix for S2 Camera DDR3 Memory

6 3

Alternate Parts

PART NUMBER

376S1053

138S0739

138S0725

376S00074

376S1129

353S3452

128S0364
107S0254
138S0843

197S0542 197S0544
197S0545 Epson alt to TXC197S0544

107S0248
127S0164
353S4070 353S4069
353S4068 353S4069

311S0649
138S0614
155S0694 155S0387

740S00003

138S0738

353S00095

311S00007
128S0398
128S0386
128S0397 128S0325

377S00011

377S0155 377S0184
155S0914
371S0558
128S0436
128S0445 128S0392

353S00034

311S00014

311S00008

197S0479 197S0478 Epson alt to NDK

311S00013

376S00014

371S00019

371S00018

311S00015

371S00017

353S00107

107S00024

372S0186 372S0185

353S00135

353S00133

131S00040

107S00015

107S00031

107S00029

ALTERNATE FOR
PART NUMBER

376S0604
128S0329128S0311 NEC alt to Sanyo
138S0706

BOM OPTION

REF DES

ALL
ALL
ALL

COMMENTS:

ALL
152S1645152S0461
376S0820376S1080

138S0724
376S0855
376S0855
376S1128376S1089
353S1286

128S0264
107S0241
138S0674

138S0811138S0846

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

107S0250
127S0162

ALL

ALL

ALL

ALL
353S3812353S3814
311S0541
138S0578

ALL

ALL

ALL

ALL
155S0513155S0660

740S0135
138S1101
353S3328
311S0426
128S0220
128S0284

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL
377S0184

ALL

ALL
155S0897
371S0713
128S0392

ALL

ALL

ALL

ALL
353S2220
311S0515
311S0271

ALL

ALL

ALL

ALL
311S0508
376S0761

ALL

ALL

ALL

ALL
311S0450
371S0749

353S3239
107S0226

ALL

ALL

ALLANY

ALL

ALL
353S3987
353S2220
353S2741 Onsemi alt to TI

ALL353S00231

ALL

ALL

ALL131S00041
107S00011
107S00032
107S00030

ALL

ALL

ALL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Diodes alt to Fairchild

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Samsung alt to Murata

TABLE_ALT_ITEM

Epson alt to NDK197S0480197S0481

TABLE_ALT_ITEM

Cyntec alt to Vishay

TABLE_ALT_ITEM

Diodes alt to On Semi

TABLE_ALT_ITEM

Samsung alt to Murata

TABLE_ALT_ITEM

Toshiba alt for Diodes Dual

TABLE_ALT_ITEM

NXP Alt for Diodes Dual

TABLE_ALT_ITEM

NXP Alt for Diodes Single

TABLE_ALT_ITEM

Maxim alt to Microchip

TABLE_ALT_ITEM

Sanyo 2nd Factory alt

TABLE_ALT_ITEM

Cyntec alt to TFT

TABLE_ALT_ITEM

Samsung alt to Murata (BKLT)

TABLE_ALT_ITEM

Samsung alt to Murata (BKLT)

TABLE_ALT_ITEM

NDK alt to TXC

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TFT alt to Cyntec

TABLE_ALT_ITEM

Rohm alt to Vishay

TABLE_ALT_ITEM

Pericom alt to TI DP Mux U9750

TABLE_ALT_ITEM

NXP alt to TI DP Mux U9750

TABLE_ALT_ITEM

TI alt to NXP

TABLE_ALT_ITEM

ONsemi alt to Toshiba

TABLE_ALT_ITEM

Murata, TDK, Samsung, Taiyo Yuden alt to Murata, TDK

TABLE_ALT_ITEM

Murata alt to TDK

TABLE_ALT_ITEM

Murata alt to TDK

TABLE_ALT_ITEM

AEM alt to Tyco

TABLE_ALT_ITEM

Samsung alt to Murata for LCD BKL caps

TABLE_ALT_ITEM

Pericom alt to TI

TABLE_ALT_ITEM

Diodes alt to NXP

TABLE_ALT_ITEM

Kemet alt to Sanyo

TABLE_ALT_ITEM

Kemet alt to Sanyo

TABLE_ALT_ITEM

Kemet alt to Sanyo

TABLE_ALT_ITEM

Infineon alt to Infineon

TABLE_ALT_ITEM

On Semi alt to Infineon

TABLE_ALT_ITEM

Panasonic alt to TDK

TABLE_ALT_ITEM

ST Micro alt to Diodes

TABLE_ALT_ITEM

Kemet alt to Sanyo

TABLE_ALT_ITEM

Panasonic alt to Sanyo

TABLE_ALT_ITEM

Pericom alt to Fairchild

TABLE_ALT_ITEM

Diodes alt to NXP

TABLE_ALT_ITEM

Diodes alt to NXP

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Diodes alt to NXP

TABLE_ALT_ITEM

Toshiba alt to Vishay

TABLE_ALT_ITEM

Rohm alt to Rohm371S0463

TABLE_ALT_ITEM

Rohm alt to Rohm371S0619

TABLE_ALT_ITEM

Diodes alt to NXP

TABLE_ALT_ITEM

Diodes alt to Onsemi

TABLE_ALT_ITEM

Onsemi alt to Intersil

TABLE_ALT_ITEM

Yageo alt to Cyntec

TABLE_ALT_ITEM

NXP alt to Diodes

TABLE_ALT_ITEM

NXP alt to TI

TABLE_ALT_ITEM

Onsemi alt to Fairchild

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Murata alt to Taiyo Yuden

TABLE_ALT_ITEM

TFT alt to Cyntec

TABLE_ALT_ITEM

TFT alt to Cyntec

TABLE_ALT_ITEM

TFT alt to Cyntec

SYNC_MASTER=J14

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/04/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

3 OF 120

SHEET

3 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Shield Cans

1

SH0451

SM

SHLD-J44-MLB

USB Cage

D

C

Mounting Holes & Slots

OMIT

ZT0411

4P5R2P3-3P5B

1

OMIT

ZT0413

6.19X4.60-SNOWMAN

1

OMIT

ZT0414

6.19X4.60-SNOWMAN

1

TH0400

TH-NSP

1

SL-1.1X0.5-1.4x0.8

TH0403

TH-NSP

1

SL-1.1X0.5-1.4x0.8

TH0404

TH-NSP

1

SL-1.1X0.45-1.4x0.75

TH0405

TH-NSP

1

SL-1.1X0.45-1.4x0.75

1

SH0450

SM

SHIELD-FENCE-MLB-T29-X304

TBT Cage

ABOVE GUMSTICK CARD IN MIDDLE OF BOARD
(998-1195)

SNOWMAN-SHAPED SLOT AT LEFT OF MEMORY BANK
(998-5879)

SNOWMAN-SHAPED SLOT AT RIGHT OF MEMORY BANK
(998-5879)

Upper TBT can Ground slot
(862-0118)

Lower TBT can Ground slot
(862-0118)

USB can Ground slot
(998-3975)

USB can Ground slot
(998-3975)

SH0452

SM

SHLD-FENCE-MLB-DRAM-X304

1

789

101112131415161718

Memory Shield CAN (806-00037)

192202122232425262728

293303132333435363738

39440

4142434445464748495505152535455565758

D

5966061626364

C

Rubber Mount Standoffs (860-1448)

SH0460

2.9OD1.2ID-1.35H-SM

1

2

B

SH0462

2.9OD1.2ID-1.35H-SM

1

2

SH0464

2.9OD1.2ID-1.35H-SM

1

2

SH0466

2.9OD1.2ID-1.35H-SM

1

2

SH0468

A

1

2

SH0461

2.9OD1.2ID-1.35H-SM

1

2

SH0465

2.9OD1.2ID-1.35H-SM

1

2

SH0463

2.9OD1.2ID-1.35H-SM

1

2

SH0467

2.9OD1.2ID-1.35H-SM

1

2

SH0469

2.9OD1.2ID-1.35H-SM2.9OD1.2ID-1.35H-SM

1

2

THERMAL MODULE STANDOFF (860-00165)

SH0420

1

SH0426

4.5OD1.85ID-1.78H-SM 4.5OD1.85ID-1.78H-SM

1

SH0421

4.5OD1.85ID-1.78H-SM4.5OD1.85ID-1.78H-SM

1

SH0427

1

RIO FLEX BRACKET BOSSES (860-00166)

SH0443

3.5OD1.85ID-2.0H

1

6 3

FAN STANDOFF (860-00183)SSD STANDOFF (860-00164)

SH0440

5.0OD2.0H

1

POGO PINS (870-00607)

SH0435 & SH0436 removed.

SH0432

POGO-2.3OD-5.5H-X304

SM

1

SH0433

POGO-2.3OD-5.5H-X304

SM

1

IPD FLEX BRACKET BOSSES (860-00166)

SH0471

3.5OD1.85ID-2.0H

1

BOM_COST_GROUP=PD PARTS

SH0441

STDOFF-4.5ID1.73H-SM

1

SYNC_MASTER=LDUNN_J44

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PD Parts

Apple Inc.

R

SYNC_DATE=01/13/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

4 OF 120

SHEET

4 OF 82

124578

SIZE

B

A

D

8 7 6 5 4 3

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

DDI Port Assignments:

D

TBT Sink 0

TBT Sink 1
(MUXed with HDMI
if necessary)

DP_TBTSNK0_ML_C_N<0>

25 77

OUT

DP_TBTSNK0_ML_C_P<0>

25 77

OUT

DP_TBTSNK0_ML_C_N<1>

25 77

OUT

DP_TBTSNK0_ML_C_P<1>

25 77

OUT

DP_TBTSNK0_ML_C_N<2>

25 77

OUT

DP_TBTSNK0_ML_C_P<2>

25 77

OUT

DP_TBTSNK0_ML_C_N<3>

25 77

OUT

DP_TBTSNK0_ML_C_P<3>

25 77

OUT

=DP_TBTSNK1_ML_C_N<0>

69

OUT

=DP_TBTSNK1_ML_C_P<0>

69

OUT

=DP_TBTSNK1_ML_C_N<1>

69

OUT

=DP_TBTSNK1_ML_C_P<1>

69

OUT

=DP_TBTSNK1_ML_C_N<2>

69

OUT

=DP_TBTSNK1_ML_C_P<2>

69

OUT

=DP_TBTSNK1_ML_C_N<3>

69

OUT

=DP_TBTSNK1_ML_C_P<3>

69

OUT

C54
C55
B58
C58
B55
A55
A57
B57

C51
C50
C53
B54
C49
B50
A53
B53

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

SYM 1 OF 19

DDI

EDP

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP_AUXN
EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

C45
B46
A47
B47

C47
C46
A49
B49

A45
B45

D20
A43

DP_INT_ML_C_N<0>
DP_INT_ML_C_P<0>
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<1>

DP_INT_ML_C_N<2>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<3>
DP_INT_ML_C_P<3>

DP_INT_AUXCH_C_N
DP_INT_AUXCH_C_P

MCP_EDP_RCOMP

73

TP_EDP_DISP_UTIL

65 77

OUT

65 77

OUT

65 77

OUT

65 77

OUT

65 77

OUT

65 77

OUT

65 77

OUT

65 77

OUT

65 77

BI

65 77

BI

eDP Port Assignment:

Internal panel

PPVCOMP_S0_CPU

1

R0530

24.9

1%
1/20W
MF
201

2

8

12

D

OMIT_TABLE

CRITICAL

U0500

AT2
AU44
AV44

D15

F22

H22

J21

BROADWELL-ULT

2C+GT2

BGA

SYM 17 OF 19

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 18 OF 19

SPARE

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD

DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF

N23

RSVD

R23

RSVD

T23

RSVD

U10

RSVD

AL1

RSVD

AM11

RSVD

AP7

RSVD

AU10

RSVD

AU15

RSVD

AW14

RSVD

AY14

RSVD

C

NO_TEST NO_TEST

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE
TRUE

TRUE

AY2

DAISY_CHAIN_NCTF

AY3

DAISY_CHAIN_NCTF

AY60

DAISY_CHAIN_NCTF

AY61

DAISY_CHAIN_NCTF

AY62

DAISY_CHAIN_NCTF

B2

DAISY_CHAIN_NCTF

B3

DAISY_CHAIN_NCTF

B61

DAISY_CHAIN_NCTF

B62

DAISY_CHAIN_NCTF

B63

DAISY_CHAIN_NCTF

C1

DAISY_CHAIN_NCTF

C2

DAISY_CHAIN_NCTF

TP0531

TP0501

TP

TP-P6

TP

TP-P6

5

5

1

5

5

1

5

5

MCP_DC_AW2_AY2
MCP_DC_AW3_AY3
MCP_DC_AY60
MCP_DC_AW61_AY61
MCP_DC_AW62_AY62
MCP_DC_B2
MCP_DC_A3_B3
MCP_DC_A61_B61
MCP_DC_B62_B63

MCP_DC_C1_C2

B

NC NC

MCP Daisy-Chain Strategy:

Each corner of CPU has two testpoints.
Other corner test signals connected in
daisy-chain fashion. Continuity should
exist between both TP’s on each corner.

A3
A4

A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63

NCNC
NCNC
NCNC

NCNC
NCNC
NCNC
NC
NC
NC
NC

MCP_DC_A3_B3

TRUE

MCP_DC_A4
MCP_DC_A60

MCP_DC_A61_B61

TRUE

MCP_DC_A62
MCP_DC_AV1
MCP_DC_AW1
MCP_DC_AW2_AY2

TRUE

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW61_AY61

TRUE

MCP_DC_AW62_AY62

TRUE

MCP_DC_AW63

C

5

1

TP

TP0500

TP-P6
1

TP

TP0510

TP-P6

5

1

TP

TP0511

TP-P6
1

TP

TP0520

TP-P6
1

TP

TP-P6

1

TP

TP-P6

TP0521

TP0530

5

5

5

5

B

A

BOM_COST_GROUP=CPU

6 3

SYNC_MASTER=J41

PAGE TITLE

CPU GFX,NCTF,RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

5 OF 120

SHEET

5 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

OMIT_TABLE

CRITICAL

U0500

D

=PP1V05_S0_CPU_VCCST

8

15 16 17 55 68

R0650

1/20W

PLACE_NEAR=U0500.AU60:12.7mm

PLACE_NEAR=U0500.AV60:12.7mm

200

201

38 39 55 73

BI

1

1%
MF

2

R0610

CPU_PROCHOT_L

1

121

1/20W

201

1%
MF

2

R0652

PLACE_NEAR=U0500.C61:12.7mm

R0651

PLACE_NEAR=U0500.AU61:12.7mm

1/20W

201

100

1/20W

201

1

62

5%
MF

2

R0611

56

12

5%

1/20W

MF

201

R0620

10K

1/20W

201

1

5%
MF

2

1

1%
MF

2

CPU_CATERR_L

38 73

OUT

CPU_PECI

39 73

BI

CPU_PROCHOT_R_L

73

CPU_PWRGD

CPU_SM_RCOMP<0>

73

CPU_SM_RCOMP<1>

73

CPU_SM_RCOMP<2>

73

=MEM_RESET_L

70

OUT

CPU_MEMVTT_PWR_EN_LSVDDQ

17

OUT

D61

K61

N62

K63

C61

AU60
AV60
AU61

AV15

AV61

PROC_DETECT*

CATERR*

PECI

PROCHOT*

PROCPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

SM_DRAMRST*

SM_PG_CNTL1

NC

BROADWELL-ULT

2C+GT2

BGA

SYM 2 OF 19

MISC

PWR

DDR3

(IPU)

JTAG

THERMAL

(IPD)

(IPU)

(IPU)

PRDY*

(IPU)

PREQ*

(IPU)

PROC_TCK
PROC_TMS

PROC_TRST*

PROC_TDI
PROC_TDO

BPM0*

(IPU)

BPM1*

(IPU)

BPM2*

(IPU)

BPM3*

(IPU)

BPM4*

(IPU)

BPM5*

(IPU)

BPM6*

(IPU)

BPM7*

(IPU)

J62
K62

E60
E61
E59

F63
F62

J60
H60
H61
H62
K59
H63
K60
J61

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

16 73

OUT

16 73

IN

16 73

IN

16 73

IN

16

IN

16 73

IN

16 73

OUT

16 73

BI

16 73

BI

16 73

BI

16 73

BI

16 73

BI

16 73

BI

16 73

BI

16 73

BI

12

D

C

B

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE
CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID
CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED
CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE
CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

These can be placed close to J1800

A

NOSTUFF

R0640

1/20W

and are only for debug access

HSW_PRE_ES2

1

1

R0639

1K

1K

5%

5%
1/20W

MF

MF

201

201

2

2

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid
issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

CPU_CFG<4>

EDP

1

R0634

1K

5%
1/20W
MF
201

2

NOSTUFF

R0638

1/20W

6

16 73

201

NOSTUFF

1

1

R0631

1K

1K

5%

5%
1/20W

MF

MF
201

2

2

CPU_CFG<10>
CPU_CFG<9>
CPU_CFG<8>
CPU_CFG<1>
CPU_CFG<0>

NOSTUFF

1

R0630

1K

5%
1/20W
MF
201

2

C

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

CPU_CFG<0>

6

16 73

BI

CPU_CFG<1>

6

16 73

BI

CPU_CFG<2>

16 73

BI

CPU_CFG<3>

16 73

BI

CPU_CFG<4>

6

16 73

BI

CPU_CFG<5>

16 73

BI

CPU_CFG<6>

16 73

BI

CPU_CFG<7>

16 73

BI

CPU_CFG<8>

6

16 73

BI

CPU_CFG<9>

6

16 73

BI

CPU_CFG<10>

6

16 73

BI

CPU_CFG<11>

16 73

BI

CPU_CFG<12>

16 73

BI

CPU_CFG<13>

16 73

BI

CPU_CFG<14>

16 73

BI

CPU_CFG<15>

16 73

BI

CPU_CFG<16>

16 73

BI

CPU_CFG<18>

16 73

BI

CPU_CFG<17>

16 73

BI

CPU_CFG<19>

16 73

BI

CPU_CFG_RCOMP

6

16 73

6

16 73

6

16 73

6

16 73

6

16 73

R0680

49.9

1/20W

201

1%
MF

1

2

PCH_TD_IREF

1

R0685

8.25K

1%
1/20W
MF
201

2

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

J20
H18
B12

E1
D1

RSVD

RSVD
RSVD
RSVD
RSVD
TD_IREF

NC
NC

NC
NC
NC

6 3

(IPU)

(IPU)
(IPU)

(IPU)

(IPU)
(IPU)

(IPU)
(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)
(IPU)

(IPU)

(IPU)

(IPU)
(IPU)

(IPU)
(IPU)

SYM 19 OF 19

RESERVED

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD_B43

RSVD_TP
RSVD_TP

RSVD_TP

RSVD

RSVD
RSVD

PROC_OPI_COMP

RSVD
RSVD

RSVD
RSVD

VSS
VSS

AV63
AU63

C63
C62

B43

A51
B51

L60

N60

W23
Y22

AY15

AV62
D58

P22
N21

P20
R20

NC

NC

NC
NC

73

NC
NC

NC
NC

TP_MCP_RSVD_AV63
TP_MCP_RSVD_AU63

TP_MCP_RSVD_C63
TP_MCP_RSVD_C62

TP_MCP_RSVD_A51
TP_MCP_RSVD_B51

TP_MCP_RSVD_L60

CPU_OPI_RCOMP

1

R0690

49.9

1%
1/20W
MF
201

2

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

PAGE TITLE

CPU Misc,JTAG,CFG,RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

6 OF 120

SHEET

6 OF 82

124578

SIZE

B

A

D

8 7 6 5 4 3

12

OMIT_TABLE

MEM_A_DQ<0>

70 71 76

BI

MEM_A_DQ<1>

70 71 76

BI

MEM_A_DQ<2>

70 71 76

BI

MEM_A_DQ<3>

70 71 76

BI

MEM_A_DQ<4>

70 71 76

BI

MEM_A_DQ<5>

70 71 76

BI

MEM_A_DQ<6>

70 71 76

BI

MEM_A_DQ<7>

70 71 76

BI

MEM_A_DQ<8>

70 71 76

D

C

B

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 3 OF 19

MEMORY CHANNEL A

LPDDR3

RSVD1

RSVD2

CAB3

CAB2
CAB1

CAB4
CAB6

CAA5

CAB9

CAB8
CAB5

CAA0

CAA2

CAA4
CAA3

CAA1

CAB7
CAA7

CAA6
CAB0

CAA9

CAA8

SM_VREF_CA

SM_VREF_DQ0

SM_VREF_DQ1

CRITICAL

SA_CLK0*

SA_CLK0

SA_CLK1*

SA_CLK1

SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3

SA_CS0*
SA_CS1*

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_BA0
SA_BA1
SA_BA2

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

AU37
AV37
AW36
AY36

AU43
AW43
AY42
AY43

AP33
AR32

AP32

AY34
AW34
AU34

AU35
AV35
AY41

AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

AP49

AR51

AP51

MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CLK_N<1>
MEM_A_CLK_P<1>

MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_CKE<2>
MEM_A_CKE<3>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

=MEM_A_ODT<0>

=MEM_A_RAS_L
=MEM_A_WE_L
=MEM_A_CAS_L

=MEM_A_BA<0>
=MEM_A_BA<1>
=MEM_A_BA<2>

=MEM_A_A<0>
=MEM_A_A<1>
=MEM_A_A<2>
=MEM_A_A<3>
=MEM_A_A<4>
=MEM_A_A<5>
=MEM_A_A<6>
=MEM_A_A<7>
=MEM_A_A<8>
=MEM_A_A<9>
=MEM_A_A<10>
=MEM_A_A<11> MEM_B_DQ<34>
=MEM_A_A<12>
=MEM_A_A<13>
=MEM_A_A<14>
=MEM_A_A<15>

MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

CPU_DIMM_VREFCA
CPU_DIMMA_VREFDQ
CPU_DIMMB_VREFDQ

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

20 24 76

20 24 76

21 24 76

21 24 76

20 24 76

20 24 76

21 24 76

21 24 76

20 21 24 76

20 21 24 76

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

19 76

19 76

19 76

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

70 71 76

BI

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>

MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>

MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>

MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>

MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18

OMIT_TABLE

CRITICAL

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10 SB_CS0*
SB_DQ11 SB_CS1*
SB_DQ12
SB_DQ13 SB_ODT0
SB_DQ14
SB_DQ15 SB_RAS*
SB_DQ16
SB_DQ17 SB_CAS*
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33 SB_MA10
SB_DQ34 SB_MA11
SB_DQ35 SB_MA12
SB_DQ36
SB_DQ37 SB_MA14
SB_DQ38 SB_MA15
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 4 OF 19

MEMORY CHANNEL B

LPDDR3

RSVD3

RSVD4

CAB3

CAB2
CAB1

CAB4
CAB6

CAA5

CAB9

CAB8
CAB5

CAA0

CAA2

CAA4
CAA3

CAA1

CAB7
CAA7

CAA6
CAB0

CAA9

CAA8

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3

SB_WE*

SB_BA0
SB_BA1
SB_BA2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9

SB_MA13

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

AY49
AU50
AW49
AV50

AM32
AK32

AL32

AM35
AK35
AM33

AL35
AM36
AU49

AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>

MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_CKE<2>
MEM_B_CKE<3>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

=MEM_B_ODT<0>

=MEM_B_RAS_LMEM_B_DQ<15>
=MEM_B_WE_L
=MEM_B_CAS_L

=MEM_B_BA<0>MEM_B_DQ<19>
=MEM_B_BA<1>MEM_B_DQ<20>
=MEM_B_BA<2>MEM_B_DQ<21>

=MEM_B_A<0>
=MEM_B_A<1>
=MEM_B_A<2>
=MEM_B_A<3>
=MEM_B_A<4>
=MEM_B_A<5>
=MEM_B_A<6>
=MEM_B_A<7>
=MEM_B_A<8>
=MEM_B_A<9>
=MEM_B_A<10>MEM_B_DQ<33>
=MEM_B_A<11>
=MEM_B_A<12>
=MEM_B_A<13>
=MEM_B_A<14>
=MEM_B_A<15>MEM_B_DQ<38>

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

22 24 76

22 24 76

23 24 76

23 24 76

22 24 76

22 24 76

23 24 76

23 24 76

22 23 24 76

22 23 24 76

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

70 76

D

C

B

A

SYNC_MASTER=J41

PAGE TITLE

CPU LPDDR3 Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU

IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

7 OF 120

SHEET

7 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

BDW-ULT current estimates from Broadwell Mobile ULT Processor EDS vol.1 Doc# 514405, Rev.: 0.9v1
Wildcat Point-LP current estimates from Wildcat Point-LP PCH EDS, Doc# 515621, Rev. 0.9
Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

D

C

=PP1V05_S0SW_PCH_VCCHSIO

11 68

1838mA Max

=PP1V05_S0_PCH_VCCIO_HSIO

68

29mA Max[1]

PP1V05_S0SW_PCH_VCCUSB3PLL

11 14

41mA Max

PP1V05_S0SW_PCH_VCCSATA3PLL

B

A

11 12

42mA Max

WF: RSVD on Sawtooth Peak rev 1.0

PP1V05_S0_PCH_VCCAPLL_OPI

11

57mA Max

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

11 17 63

11mA Max

=PP3V3_SUS_PCH_VCCSUS_GPIO

11 68

59mA Max[1]

=PP3V3_S5_PCH_VCCDSW

11 68

114mA Max

=PP3V3_S0_PCH_VCC3_3_GPIO

11 68

40mA Max[1]

PP1V05_S0_PCH_VCC_ICC

11

VCCCLK: 200mA Max

PP1V05_S0_PCH_VCCACLKPLL

11 12

31mA Max

=PP1V05_S0_PCH_VCCCLK

11 68

VCCCLK: 200mA Max

WF: RSVD on Sawtooth Peak rev 1.0

=PP3V3_SUS_PCH_VCCSUS_ICC

68

3.3mA Max[1]

K9

VCCHSIO

L10

VCCHSIO

M9

VCCHSIO

N8

VCC1_05

P9

VCC1_05

B18

VCCUSB3PLL

B11

VCCSATA3PLL

Y20

VCCAPLL

NC

AA21

VCCAPLL

W21

VCCAPLL

J13

DCPSUS3

NC

AH14

VCCHDA

VRM/USB2/AZALIA

AH13

DCPSUS2

NC

AC9

VCCSUS3_3

AA9

VCCSUS3_3

AH10

VCCDSW3_3

V8

VCC3_3

W9

VCC3_3

J18

VCCCLK

K19

VCCCLK

A20

VCCACLKPLL

J17

VCCCLK

R21

VCCCLK

T21

VCCCLK

K18

RSVD

NC

M20

RSVD

NC

V21

RSVD

NC

AE20

VCCSUS3_3

AE21

VCCSUS3_3

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 13 OF 19

HSIO

OPI

AZALIA/HDA

USB3

GPIO/LCC

ICC

LPT LP POWER

VCCSUS3_3

SPI RTC

DCPSUSBYP

CORE

DCPSUSBYP

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

VCCTS1_5

USB2

VCCRTC

DCPRTC

VCCSPI

VCCASW
VCCASW

VCC1P05
VCC1P05
VCC1P05
VCC1P05
VCC1P05

VCCASW
VCCASW
VCCASW

DCPSUS1
DCPSUS1

VCC3_3
VCC3_3

VCCSDIO
VCCSDIO

DCPSUS4

RSVD

VCC1_05
VCC1_05

=PPVMEMIO_S0_CPU

10 68

1.4A Max (DDR3: 1.5-1.35V)

1.1A Max (LPDDR3: 1.2V)

=PPVCC_S0_CPU

8

10 44 68

1

R0860

100

=PP1V05_S0_CPU_VCCST

6 8

15 16 17 55 68

CPU_VIDALERT_L

55 73

IN

CPU_VIDSCLK

55 73

OUT

CPU_VIDSOUT

55 73

BI

AH11

=PP3V3_SUS_PCH_VCCSUS_RTC

0.3mA Max[1]

AG10

AE7

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

Y8

=PP3V3_SUS_PCH_VCC_SPI

18mA Max

AG14

=PP1V05_S0M_PCH_VCCASW

AG13

185mA Max[1]

J11

=PP1V05_S0_PCH_VCC

H11

1499mA Max[1]

H15
AE8
AF22

AG19

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_LINE_WIDTH=0.2 mm

AG20

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

AE9

=PP1V05_S0M_PCH_VCCASW

AF9

473mA Max[1]

AG8

AD10

NC

AD8

NC

J15

=PP1V5_S0_PCH_VCCTS

3mA Max

K14

=PP3V3_S0_PCH_VCCTS

K16

1mA Max[1]

U8

=PP3V3R1V8_S0_PCH_VCCSDIO

T9

17mA Max

AB8

NC

AC20

AG16
AG17

WF: RSVD on Sawtooth Peak rev 1.0

NC

=PP1V05_S0_PCH_VCCIO_USB2

213mA Max[1]

R0800

75

1%

1/20W

MF

201

R0811

0

1 2

5%

1/20W

MF

0201

11 68

BYPASS=U0500.AE7::6.35mm

11 14 68

8

11 68

Powered in DeepSx

8

68

11 68

11 40 68

11 68

1

2

11 68

11 68

R0810

1 2

R0812

1 2

1

R0802

130

1%
1/20W
MF
201

2

43

5%

1/20W

MF

201

0

5%

1/20W

MF

0201

1

C0895

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=U0500.AG19:2.54MM

R0899

5.11

1 2

1%
1/20W
MF-LF

201

PLACE_NEAR=U0500.C50:50.8mm

Max load: 300mA

Max load: 300mA

R0802.2:

PLACE_NEAR=U0500.L63:2.54mm

R0810.2:

PLACE_NEAR=U0500.L62:38.1mm

R0800.2:

PLACE_NEAR=R0810.1:2.54mm

1

C0892

0.1UF

PPVOUT_S5_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

20%
10V

CERM

402

C0891

0.1UF

2

BYPASS=U0500.AG10::6.35mm

CPU_VCCSENSE_P

55 73

OUT

TP_PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

PPVCOMP_S0_CPU

5

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

NOTE: Aliases not used on CPU supply outputs
to avoid any extraneous connections.

=PPVRTC_G3_PCH

1

1

C0890

20%
10V

CERM

402

1UF

10%

6.3V

2

2

CERM
402

BYPASS=U0500.AG10::6.35mm

BYPASS=U0500.AG10::6.35mm

1

C0899

1UF

10%

6.3V

2

CERM
402

BYPASS=R0899:U0500:2.54mm

1/20W

201

5%
MF

2

CPU_VIDALERT_R_L

73

CPU_VIDSCLK_R

73

CPU_VIDSOUT_R

73

CPU_VCCST_PWRGD

16 17 73

IN

CPU_VR_EN

17 55

OUT

CPU_VR_READY

17

IN

CPU_PWR_DEBUG

16

IN

TP_CPU_RSVD_P60
TP_CPU_RSVD_P61

18

TP_CPU_RSVD_N59
TP_CPU_RSVD_N61

18

=PP1V05_S0_CPU_VCCST

6 8

15 16 17 55 68

???mA Max

12 13 68

6 3

L59
J58

AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

F59
N58

AC58

E63

AB23

A59

E20
AD23
AA23
AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59
AD60
AD59
AA59
AE60
AC59
AG58

U59

V59

AC22
AE22
AE23

AB57
AD57
AG57

C24

C28

C32

RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VCC
RSVD
RSVD

VCC_SENSE

RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD

VIDALERT*
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

VSS
PWR_DEBUG*
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCST
VCCST
VCCST

VCC
VCC
VCC
VCC
VCC
VCC

NC
NC

NC
NC

NC

NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC

BOM_COST_GROUP=CPU

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 12 OF 19

HSW ULT POWER

SYNC_MASTER=J41

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

32A Max

=PPVCC_S0_CPU

C36

CPU & PCH Power

Apple Inc.

R

12

8

10 44 68

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

8 OF 120

SHEET

8 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SYM 14 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29

AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49

AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63

AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

A11
A14
A18
A24
A28

D

C

B

A32
A36
A40
A44
A48
A52
A56

AA1
AA58
AB10
AB20
AB22

AB7
AC61
AD21

AD3
AD63
AE10

AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18

AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

BROADWELL-ULT

VSS
VSS
VSS
VSS

AP3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AR5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AU1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

OMIT_TABLE

CRITICAL

U0500

2C+GT2

BGA

SYM 15 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

BROADWELL-ULT

D33

VSS

D34

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D5

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

D8

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

H13

VSS

OMIT_TABLE

CRITICAL

U0500

2C+GT2

BGA

SYM 16 OF 19

VSS_SENSE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

V58
AH46
V23
E62
AH16

CPU_VCCSENSE_N

1

R0960

100

5%

PLACE_NEAR=U0500.E62:50.8mm

1/20W
MF
201

2

D

C

55 73

OUT

B

A

BOM_COST_GROUP=CPU

6 3

SYNC_MASTER=J41

PAGE TITLE

CPU & PCH Grounds

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

9 OF 120

SHEET

9 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 0.9 unless stated otherwise

CPU VCC Decoupling

=PPVCC_S0_CPU

8

44 68

D

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff
Apple implementation : 18x 22uF 0603 stuff, 80x 22uF 0603 nostuff

CRITICAL

1

C1000

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1001

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1002

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1003

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1018

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1004

10UF

20%
4V 4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1019

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1020

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1021

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1030

12PF

2% 2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1008

10UF

20%

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1009

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL CRITICAL

1

C1010

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1011

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1012

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL CRITICAL

1

C104E

12PF

50V

2

C0G-CERM
0402

1

C104F

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1014

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C105A

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C105B

10UF

20%
4V

2

X6S

0402

NO STUFF

CRITICAL

1

C105C

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C106D

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C105D

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C106E

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C105E

10UF

20%
4V

2

X6S
0402

NO STUFF

12

CRITICAL

1

C105F

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

D

CRITICAL

1

C1070

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1085

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C

B

C1022

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

NO STUFF

1

C1039

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1056

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C109B

10UF

20%
4V

2

X6S
0402

CRITICAL

1

C1031

470UF-0.0045OHM

20%

2.5V

23

POLY-TANT
SM

CRITICAL

1

C1086

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1023

12PF

2%
50V

2

C0G-CERM
0402

1

C1044

12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C1057

10UF

20%
4V

2

X6S
0402

1

C109C

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1072

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1087

12PF

2%
50V

2

C0G-CERM
0402

1

C1024

12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C1045

10UF

20%
4V

2

X6S
0402

1

C1058

12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C109D

10UF

20%
4V

2

X6S
0402

CRITICAL

1

C1073

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1088

10UF

20%
4V

2

X6S
0402

NO STUFF

NO STUFF

1

C1025

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1046

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1059

10UF

20%
4V

2

X6S
0402

1

C109E

12PF

2%
50V

2

C0G-CERM
0402

PART NUMBER

138S0942

CRITICAL

1

C1074

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

CRITICAL

1

C1089

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1026

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

NO STUFF

1

C1047

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1062

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C109F

10UF

20%
4V

2

X6S
0402

QTY

18

CRITICAL

1

C1075

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1090

10UF

20%
4V

2

X6S
0402

NO STUFF

NO STUFF

1

C1027

10UF

20%
4V

2

0402

NO STUFF

1

C1048

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1063

10UF

20%
4V

2

X6S
0402

1

C108A

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1091

12PF

50V

2

C0G-CERM
0402

NO STUFF

1

C1028

10UF

20%
4V

2

X6SX6S
0402

1

C1049

12PF

2%
50V

2

C0G-CERM
0402

1

C1064

12PF

2%
50V

2

C0G-CERM
0402

1

C108B

12PF

2%
50V

2

C0G-CERM
0402

DESCRIPTION

CAP,CER,10UF,20%,4V,X6S,HRZTL,0402

CRITICAL

1

C1077

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1092

12PF

2%2%
50V

2

C0G-CERM
0402

NO STUFF

1

C1029

10UF

20%
4V

2

X6S
0402

CRITICAL

1

C1065

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

NO STUFF

1

C108C

10UF

20%
4V

2

X6S
0402

REFERENCE DES

CRITICAL

1

C1093

12PF

2%
50V

2

C0G-CERM

NO STUFF

1

C1032

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1066

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C108D

10UF

20%
4V

2

X6S
0402

1

2

1

2

1

2

1

2

CRITICAL

CRITICAL

CRITICAL

C1094

12PF

2%
50V
C0G-CERM
04020402

C1033

12PF

2%
50V
C0G-CERM
0402

NO STUFF

C1067

10UF

20%
4V
X6S
0402

NO STUFF

C108E

10UF

20%
4V
X6S
0402

CRITICAL

1

C1095

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1034

10UF

20%
4V

2

X6S
0402

OMIT_TABLE

1

C1068

12PF

2%
50V

2

C0G-CERM
0402

1

C108F

12PF

2%
50V

2

C0G-CERM
0402

BOM OPTION

CRITICAL

1

C1081

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1096

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1035

2%
50V

2

C0G-CERM
0402

1

C1069

12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C107A

10UF

20%
4V

2

X6S
0402

C1000,C1004,C1008,C1012,C1018,C1019,C1020,C1022,C1026,C1034,C1065,C1070,C1074,C105A,C105C,C105D,C104F,C105F

CRITICAL

1

C1082

10UF

20%
4V

2

X6S
0402

NO STUFF

CRITICAL

1

C1097

12PF

2%
50V

2

C0G-CERM
0402

1

C1036

12PF12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C1098

10UF

20%
4V

2

X6S
0402

1

C107B

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1083

12PF

2%
50V

2

C0G-CERM
0402

1

C1037

12PF

2%
50V

2

C0G-CERM
0402

1

C1099

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C1084

10UF

20%
4V

2

X6S
0402

NO STUFF

1

C1038

12PF

2%
50V

2

C0G-CERM
0402

NO STUFF

1

C109A

10UF

20%
4V

2

X6S
0402

C

B

CPU VDDQ DECOUPLING

=PPVMEMIO_S0_CPU

8

68

Intel recommendation (Table 5-4): 2x 2.2uF 0402, 6x 10uF 0603
Apple implementation : 2x 2.2uF 0402, 6x 10uF 0402

CPU VCC Decoupling

1

C1040

2.2UF 2.2UF

20%

6.3V

2

CERM
402-LF

1

C1050

10UF

20%

6.3V

2

A

CERM-X5R
0402-1

OMIT_TABLE

1

C1060

270UF

20%
2V

2

TANT
CASE-B2-SM

1

C1041

20%

6.3V

2

CERM
402-LF

1

C1051

10UF

20%

6.3V

2

CERM-X5R
0402-1

OMIT_TABLE

NO STUFF

1

C1061

270UF

20%
2V

2

TANT
CASE-B2-SM

1

C1042

2.2UF

20%

6.3V

2

CERM
402-LF

1

C1052

10UF

20%

6.3V

2

CERM-X5R

0402-1

OMIT_TABLE

1x Bulk nostuff, Harris Beach has 2x nostuff

1

C1043

2.2UF

20%

6.3V

2

CERM
402-LF

1

C1053

10UF

20%

6.3V

2

CERM-X5R
0402-1

OMIT_TABLE

PART NUMBER

138S0801

Added 2 extra 2.2uF per Harris Beach v0.9 schematic

1

C1054

10UF

20%

6.3V

2

CERM-X5R
0402-1

OMIT_TABLE

QTY

6

6 3

1

C1055

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1079

12PF

5%
25V

2

NP0-C0G
0201

OMIT_TABLE

DESCRIPTION

CAP,CER,10UF,20%,6.3V,HRZTL,0402

NOTE: 38X capacitors are STUFFED and have been changed to 12pF for Noise Floor Reasons (Radar # 17754026).

1

C1080

12PF

5%
25V

2

NP0-C0G
0201

REFERENCE DES

CRITICAL

CRITICAL

BOM OPTION

C1050,C1051,C1052,C1053,C1054,C1055

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

10 OF 120

SHEET

10 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

PCH VCCASW BYPASS
PCH VCCDSW3_3 BYPASS
(PCH 3.3V DSW PWR)

=PP3V3_S5_PCH_VCCDSW

8

68

PCH VCCSPI BYPASS

D

(PCH 3.3V SPI PWR)

=PP3V3_SUS_PCH_VCC_SPI

8

14 68

PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND PWR)

=PP3V3_SUS_PCH_VCCSUS_GPIO

8

68

PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND RTC PWR)

=PP3V3_SUS_PCH_VCCSUS_RTC

8

68

C

PCH VCCSDIO BYPASS
(PCH 3.3V/1.8V SDIO PWR)

=PP3V3R1V8_S0_PCH_VCCSDIO

8

40 68

NO STUFF

C1200

BYPASS=U0500.AH10::6.35mm

NO STUFF

C1202

0.1UF

BYPASS=U0500.Y8::6.35mm

C1204

22UF

X5R-CERM-1

BYPASS=U0500.AC9::12.7mm

C1206

BYPASS=U0500.AH11::6.35mm

C1208

BYPASS=U0500.U8::6.35mm

1UF

6.3V
CERM

CERM

6.3V

1UF

6.3V
CERM

1UF

6.3V
CERM

10%

402

20%
10V

402

20%

603

10%

402

10%
402

1

2

1

2

1

2

1

2

1

2

PCH VCC3_3 BYPASS
(PCH 3.3V GPIO/LPC PWR)

=PP3V3_S0_PCH_VCC3_3_GPIO =PP1V05_S0_PCH_VCCIO_USB2

8

68

1

C1212

22UF

20%

6.3V

C1214

0.1UF

CERM

603

20%
10V

402

2

1

2

R1270

0

1 2

1/16W
MF-LF

PP1V05_S0_PCH_VCCACLKPLL_R

MIN_LINE_WIDTH=0.2 MM

5%

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

402

PCH VCC3_3 BYPASS
(PCH 3.3V THERMAL PWR)

=PP3V3_S0_PCH_VCCTS

8

68

68

X5R-CERM-1

BYPASS=U0500.V8::12.7mm

BYPASS=U0500.K14::6.35mm

=PP1V05_S0_PCH_PLLFILTERS

??mA Max

(PCH 1.05V ME CORE PWR)

=PP1V05_S0M_PCH_VCCASW

8

68

BYPASS=U0500.AE9::12.7mm

PCH VCC BYPASS

(PCH 1.05V CORE PWR)

=PP1V05_S0_PCH_VCC

8

68

BYPASS=U0500.J11::12.7mm

PCH VCCHSIO BYPASS

(PCH 1.05V PCIe/SATA/USB3 PWR)

=PP1V05_S0SW_PCH_VCCHSIO

8

68

BYPASS=U0500.K9::6.35mm

2.2UH-240MA-0.221OHM

NO STUFF

C1250

22UF

20%

6.3V

X5R-CERM-1

603

BYPASS=U0500.AE9::6.35mm

C1255

10UF

20%

6.3V
X5R
603

BYPASS=U0500.J11::6.35mm

C1260

1UF

10%

6.3V

CERM

402

BYPASS=U0500.L10::6.35mm

CRITICAL

L1270

1 2

0603

C1270

47UF

20%
X6S

BYPASS=U0500.A20::12.7mm

0805

1

1

C1251

1UF

10%

6.3V

2

2

CERM
402

1

1

C1256

1UF

10%

6.3V

2

2

CERM
402

BYPASS=U0500.AE8::6.35mm

1

C1261

1UF

10%

6.3V

2

CERM

402

BYPASS=U0500.M9::6.35mm

1

C1271

47UF

4V

BYPASS=U0500.A20::12.7mm

20%

2

X6S

0805

BYPASS=U0500.A20::6.35mm

1

C1257

1UF

10%

6.3V

2

CERM
402

1

1

C1262

10UF

20%

6.3V

2

2

CERM-X5R
0402-1

OMIT_TABLE

PCH VCCACLKPLL FILTER/BYPASS
(PCH 1.05V ACLK PLL PWR)

PP1V05_S0_PCH_VCCACLKPLL

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

1

C1272

1UF

4V

10%
10V

2

2

X5R
402

68

68

31mA Max

PCH VCCIO BYPASS
(PCH 1.05V USB2 PWR)

8

BYPASS=U0500.AG16::6.35mm

PCH VCCCLK BYPASS
(PCH 1.05V CLK PWR)

=PP1V05_S0_PCH_VCCCLK

8

C1266

1UF

6.3V
CERM

BYPASS=U0500.J17::6.35mm

8

12

C1264

1UF

6.3V
CERM

1

C1267

10%
402

BYPASS=U0500.R21::6.35mm

1UF

6.3V

2

CERM

10%

402

10%
402

1

2

D

1

2

C

PCH VCCSUSHDA BYPASS
(PCH 3.3V/1.5V HDA PWR)

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

8

17 63

BYPASS=U0500.AH14::6.35mm

B

A

PART NUMBER

QTY

1

Wildcat Point-LP current estimates from Wildcat Point-LP PCH EDS, Doc# 515621, Rev. 0.9

as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

DESCRIPTION

CAP,CER,10UF,20%,6.3V,HRZTL,0402

C1210

1UF

10%

6.3V
CERM

402

REFERENCE DES

1

2

C1262

CRITICAL

CRITICAL138S0801

CRITICAL

L1275

2.2UH-240MA-0.221OHM

1 2

0603

C1275

BYPASS=U0500.J18::12.7mm

PCH OPI VCCAPLL FILTER/BYPASS
(PCH 1.05V OPI PLL PWR)

PP1V05_S0_PCH_VCCAPLL_OPI

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

1

C1282

1UF

10%
10V

2

2

X5R
402

PCH VCCSATA3PLL FILTER/BYPASS
(PCH 1.05V SATA3 PLL PWR)

PP1V05_S0SW_PCH_VCCSATA3PLL

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

1

C1292

1UF

10%
10V

2

2

X5R
402

PCH VCCUSB3PLL FILTER/BYPASS
(PCH 1.05V USB3 PLL PWR)

PP1V05_S0SW_PCH_VCCUSB3PLL

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

C1297

1UF

10%
10V

2

X5R
402

1

47UF

C1276

20%

4V

2

X6S

0805

BYPASS=U0500.J18::12.7mm

BYPASS=U0500.J18::6.35mm

47UF

20%
X6S

0805

57mA Max

41mA Max

BOM OPTION

R1275

0

1 2

1/16W
MF-LF

R1280

1 2

1/16W
MF-LF

2.2UH-240MA-0.221OHM

=PP1V05_S0SW_PCH_VCCPLL_HSIO

68

83mA Max 42mA Max

2.2UH-240MA-0.221OHM

2.2UH-240MA-0.221OHM

BYPASS=U0500.B18::12.7mm

PP1V05_S0_PCH_VCC_ICC_R

MIN_LINE_WIDTH=0.2 MM

5%

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

402

0

5%

CRITICAL

402

NO STUFF

L1280

1 2

0603

NO STUFF

C1280

47UF

CERM-X5R

BYPASS=U0500.AA21::12.7mm

BYPASS=U0500.B11::12.7mm

0805-1

CRITICAL

L1290

1 2

0603

C1290

47UF

0805

CRITICAL

L1295

1 2

0603

C1295

47UF

0805

NO STUFF

1

C1281

20%

4V

BYPASS=U0500.AA21::12.7mm

20%

4V

X6S

BYPASS=U0500.B11::12.7mm

20%

4V

X6S

47UF

20%

2

CERM-X5R

0805-1

BYPASS=U0500.AA21::6.35mm

NO STUFF

1

C1291

47UF

20%

2

CERM-X5R

0805-1

BYPASS=U0500.B11::6.35mm

1

2

BYPASS=U0500.B18::6.35mm

4V

4V

6 3

PCH VCCCLK FILTER/BYPASS
(PCH 1.05V VCCCLK PWR)

PP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V

1

1

C1277

1UF

4V

10%
10V

2

2

X5R
402

??mA Max

8

B

8

8

12

SIZE

A

D

SYNC_MASTER=J41

8

14

BOM_COST_GROUP=CPU

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PCH Decoupling

Apple Inc.

R

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

12 OF 120

SHEET

11 OF 82

124578

8 7 6 5 4 3

=PPVRTC_G3_PCH

8

13 68

OMIT_TABLE

BROADWELL-ULT

(IPD)

(IPD)

(IPU)

(IPU)

CRITICAL

U0500

2C+GT2

BGA

SYM 5 OF 19

RTC

AUDIO

JTAG

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

(IPU)

SATA_IREF

SATA_RCOMP

RSVD

RSVD

J5
H5

B15
A15

J8
H8

A17
B17

J6
H6

B14
C15

F5
E5

C17
D17

V1
U1
V6
AC1

A12

L11
K10

C12

U3

PCIE_SSD_D2R_N<3>
PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_C_N<3>
PCIE_SSD_R2D_C_P<3>

PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<2>
PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_C_N<0>
PCIE_SSD_R2D_C_P<0>

XDP_SSD_PCIE3_SEL_L
XDP_SSD_PCIE2_SEL_L
XDP_SSD_PCIE1_SEL_L
XDP_SSD_PCIE0_SEL_L

NC
NC

PCH_SATA_RCOMP

75

PCH_SATALED_L

PCIe Port assignments:

32 71 81

IN

32 71 81

IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN
IN

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

32 71 81

16

16

16

16

SSD Lane 3

SSD Lane 2

SSD Lane 1

SSD Lane 0

PP1V05_S0SW_PCH_VCCSATA3PLL

1

R1370

3.01K

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.C12:2.54mm

12

SATA Port assignments:

Primary HDD/SSD

Reserved: ODD

Unused

Secondary HDD/SSD

8

11

1

1

R1300

1/20W

20K

1

R1303

20K

5%

5%
1/20W

MF

201

MF
201

2

2

R1302

D

1

C1300

1UF

10%
10V
X5R
402

1

C1303

1UF

10%
10V

2

2

X5R
402

C

330K

1/20W

5%

MF

201

2

49 75

OUT

49 75

OUT

49 75

OUT

49 75

OUT

1

R1301

1M

5%
1/20W
MF
201

2

PCH_INTRUDER_L

75

PCH_INTVRMEN

75

PCH_SRTCRST_L

75

RTC_RESET_L

75

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDOUT

R1310

R1311

R1312

R1313

PCH_CLK32K_RTCX1

17 75

IN

PCH_CLK32K_RTCX2

17

OUT

33

1 2

33

1 2

1 2

33

1 2

HDA_BIT_CLK_R

75

MF

5%

1/20W

PLACE_NEAR=U0500.AW8:1.27mm

HDA_SYNC_R

75

1/20W

5%

PLACE_NEAR=U0500.AV11:1.27mm

HDA_RST_R_L

75

1/20W

5% MF33201

PLACE_NEAR=U0500.AU8:1.27mm

HDA_SDIN0

49 71 75

IN

TP_HDA_SDIN1

69

HDA_SDOUT_R

17 75

1/20W

PLACE_NEAR=U0500.AU11:1.27mm

TP_PCH_I2S1_TXD

69

TP_PCH_I2S1_SFRM

69

TP_PCH_I2S1_SCLK

69

XDP_PCH_TRST_L

16

IN

XDP_PCH_TCK

16 73

IN IN

XDP_PCH_TDI

16 73

IN

XDP_PCH_TDO

16 73

OUT

XDP_PCH_TMS

16 73

IN

PCH_JTAGX

16 73

BI

201

MF

201

MF5%

201

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER*

AV7

INTVRMEN

AV6

SRTCRST*

AU7

RTCRST*

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

AY10
AU12

AU11

AW10
AV10

AY8

AU62
AE62
AD61
AE61
AD62
AL11

NC

AC4

NC

AE63

AV2

NC

(IPD-PLTRST#)

HDA_RST*/I2S_MCLK

HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

(IPD-PLTRST#)

HDA_DOCK_EN*/I2S1_TXD
HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

PCH_TRST*

PCH_TCK

PCH_TDI

PCH_TDO

PCH_TMS

RSVD

RSVD

JTAGX

RSVD SATALED*

12

D

C

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

TP_PCIE_CLK100M_ENETSDN

69

TP_PCIE_CLK100M_ENETSDP

69

ENETSD_CLKREQ_L

12 71

PCIE_CLK100M_CAMERA_N

34 71 81

OUT

PCIE_CLK100M_CAMERA_P

34 71 81

OUT

CAMERA_CLKREQ_L

12 33

IN

PCIE_CLK100M_AP_N

66 71 81

B

OUT

66 71 81

OUT

12 66

IN

69

69

12

25 71 81

OUT

25 71 81

OUT

12 25

IN

32 71 81

OUT

32 71 81

OUT

12 32

IN

PCIE_CLK100M_AP_P

AP_CLKREQ_L

TP_PCIE_CLK100M_FWN
TP_PCIE_CLK100M_FWP

FW_CLKREQ_L

PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P

SSD_CLKREQ_L

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0*/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1*/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2*/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3*/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4*/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5*/GPIO23

A

=PP3V3_S0_PCH_GPIO

R1375
R1340

R1341
R1342
R1343
R1344
R1345

100K

100K
100K

20K
100K
100K

10K

1 2

1 2

1 2

1 2
1 2

1 2

1 2

13 15 18 26 65 68

5% MF

1/20W

5%

1/20W

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W

MF

MF
MF

MF5%

MF

PCH_SATALED_L

201

ENETSD_CLKREQ_L

201

CAMERA_CLKREQ_L

201

AP_CLKREQ_L

201

FW_CLKREQ_L

201

TBT_CLKREQ_L

201

SSD_CLKREQ_L

201

12

12 71

12 33

12 66

12

12 25

12 32

6 3

SYM 6 OF 19

XTAL24_IN

XTAL24_OUT

CLOCK SIGNALS

RSVD
RSVD

DIFFCLK_BIASREF

TESTLOW
TESTLOW
TESTLOW
TESTLOW

CLKOUT_LPC_0

CLKOUT_LPC_1

(IPD-PWROK)

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

A25
B25

K21
M21

C26

C35
C34
AK8
AL8

AN15
AP15

B35
A35

PCH_CLK24M_XTALIN
PCH_CLK24M_XTALOUT

NC
NC

PCH_DIFFCLK_BIASREF

PCH_TESTLOW_C35
PCH_TESTLOW_C34
PCH_TESTLOW_AK8
PCH_TESTLOW_AL8

LPC_CLK24M_SMC_R

17 75

IN

17 75

OUT

PP1V05_S0_PCH_VCCACLKPLL

1

R1380

3.01K

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.C26:2.54mm

10K

R1390
R1391
R1392
R1393

OUT

17 75

10K
10K
10K

1 2
1 2

1 2

1 2

8

11

B

MF5%

1/20W

5%

1/20W

1/20W

5%
5%

1/20W

201

201

MF

MF

201

MF

201

TP_LPC_CLK24M_LPCPLUS

TP_ITPXDP_CLK100MN
TP_ITPXDP_CLK100MP

69

69

SIZE

A

D

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

PAGE TITLE

PCH Audio/JTAG/SATA/CLK

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/17/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

13 OF 120

SHEET

12 OF 82

124578

8 7 6 5 4 3

12

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

BGA

D

SLP_S0# Isolation

=PP3V3_S0_PCH_GPIO

12 13 15 18 26 65 68

1

C1420

0.1UF

10%
10V

2

X5R-CERM
0201

6

2

08

1

NC

3

5

13 18 38

OUT

PM_SLP_S0_L

CRITICAL

74LVC1G08

SOT891

4

U1420

R1400 kept for debug purposes.

40

IN

NO STUFF

R1400

1/20W

0201

40

OUT

1

0

5%
MF

2

17 38 71 75

IN

16 17 38 75

IN

17 75

IN

17

IN

15 16 18

OUT

64 75

IN

13 16 38 75

IN

38 39

IN

13 27 38

IN

69

PCH_SUSACK_L
PM_SYSRST_L
PM_PCH_SYS_PWROK
PM_PCH_PWROK
PM_PCH_APWROK
PLT_RESET_L
PM_RSMRST_L
PCH_SUSWARN_L
PM_PWRBTN_L
SMC_ADAPTER_EN
PM_BATLOW_L
PCH_PM_SLP_S0_L
TP_PCH_SLP_WLAN_L

AK2

SUSACK*

AC3

SYS_RESET*

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST*

AW6

RSMRST*

AV4

SUSWARN*/SUSPWRDNACK/GPIO30

AL7

PWRBTN*

AJ8

ACPRESENT/GPIO31

AN4

BATLOW*/GPIO72

SLP_S0*

AM5

SLP_WLAN*/GPIO29

SYM 8 OF 19

SYSTEM POWER MANAGEMENT

(IPU)

(IPD-DeepSx)

(IPU)

(IPD-DeepSx)

DSWVRMEN

DPWROK

WAKE*

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

AW7
AV5
AJ5
V5
AG4
AE6
AP5
AJ6
AT4
AL5
AP4
AJ7AF3

PCH_DSWVRMEN

75

PM_DSW_PWRGD
PCIE_WAKE_L
PM_CLKRUN_L
LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
TP_PM_SLP_A_L
PM_SLP_SUS_L
TP_PCH_SLP_LAN_L

13 31 33 75

IN

13 38 71

BI

38 71

OUT

39

OUT

13 38 64

OUT

13 18 31 37 38 64 66

OUT

13 17 18 38 64 66 71

OUT

71

13 64

OUT

69

=PPVRTC_G3_PCH

1

R1450

330K

5%
1/20W
MF
201

2

38 75

IN

1

R1451

100K

5%
1/20W
MF
201

2

8

12 68

D

NC

SLP_S0# can be driven high outside of S0
U1420 ensures signal will only be high in S0.

C

AD4

B8
A9
C6

U6
P4
N4
N2

U7
L1
L3
R5
L4

EDP_BKLCTL

EDP_BKLEN

EDP_VDDEN

PIRQA*/GPIO77
PIRQB*/GPIO78
PIRQC*/GPIO79
PIRQD*/GPIO80

PME*

GPIO55
GPIO52
GPIO54
GPIO51
GPIO53

EDP_BKLT_PWM

65 71

OUT

EDP_BKLT_EN

13 65

OUT

EDP_PANEL_PWR

13 65

OUT

TBT_PWR_REQ_L

13 26

IN

SMC_RUNTIME_SCI_L

13 38

IN

AUD_IP_PERIPHERAL_DET

13 71

IN

SSD_BOOT

13 32

OUT

TP_PCI_PME_L

69

ODD_PWR_EN_L

13 71

OUT

DP_AUXCH_ISOL_L

13 69

OUT

ENET_LOW_PWR

13 71

OUT

AUD_PWR_EN

13 64

OUT

AUD_IPHS_SWITCH_EN

13 71

OUT

OMIT_TABLE

CRITICAL

U0500

BROADWELL-ULT

2C+GT2

SYM 9 OF 19

(IPU)

BGA

eDP

SIDEBAND

PCI

DDPB_CTRLCLK

DDPB_CTRLDATA

(IPD-PLTRST#)

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DISPLAY

DDPB_AUXN
DDPC_AUXN

DDPB_AUXP
DDPC_AUXP

DDPB_HPD

DDPC_HPD

EDP_HPD

B9
C9

D9
D11

C5
B6

B5
A6

C8
A8
D6

DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA

=DP_TBTSNK1_DDC_CLK
=DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_AUXCH_C_N
=DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P
=DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK0_HPD
=DP_TBTSNK1_HPD
DP_INT_HPD

C

30

OUT

30

BI

69

OUT

69

BI

25 77

BI

69

BI

25 77

BI

69

BI

25

IN

69

IN

65

IN

SIZE

B

A

D

B

=PP3V3_S5_PCH_GPIO
=PP3V3_S0_PCH_GPIO

R1405
R1410
R1452
R1455
R1460

R1461
R1462
R1463
R1464

R1430

A

R1431
R1440

R1441
R1442
R1443

R1445
R1446
R1447
R1448
R1449

1K
10K
10K
10K

100K
100K
100K
100K
100K

100K
100K

100K

10K

100K
100K

100K
100K
100K
100K
100K

1 2

1 2

1 2

1 2

1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2

15 68

12 13 15 18 26 65 68

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

5%

1/20W
1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W
1/20W

5%

1/20W

1/20W
1/20W

5%

1/20W
1/20W
1/20W

PM_PWRBTN_L

MF

201

PM_BATLOW_L

MF

201

PCIE_WAKE_L

MF

201

PM_CLKRUN_L

MF

201

PM_SLP_S5_L

MF

201

PM_SLP_S4_L

MF

201

PM_SLP_S3_L

201

MF

PM_SLP_S0_L

201

MF

PM_SLP_SUS_L

201

MF

EDP_BKLT_EN

201

MF

EDP_PANEL_PWR

201

MF

TBT_PWR_REQ_L

MF

2015%

SMC_RUNTIME_SCI_L

MF

201

AUD_IP_PERIPHERAL_DET

MF 2015%

SSD_BOOT

201

MF

ODD_PWR_EN_L

MF

2015%

DP_AUXCH_ISOL_L

MF 201

ENET_LOW_PWR

MF5% 201

AUD_PWR_EN

MF

2015%

AUD_IPHS_SWITCH_EN

MF

2015%

13 16 38 75

13 27 38

13 31 33 75

13 38 71

13 38 64

13 18 31 37 38 64 66

13 17 18 38 64 66 71

13 18 38

13 64

13 65

13 65

13 26

13 38

13 71

13 32

13 71

13 69

13 71

13 64

13 71

6 3

BOM_COST_GROUP=CPU

PAGE TITLE

PCH PM/PCI/GFX

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/21/2013SYNC_MASTER=J41

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

SHEET

124578

8.0.0
dvt1

14 OF 120

13 OF 82

8 7 6 5 4 3

12

PCIe Port Assignments:

Thunderbolt lane 0

D

C

38 71 75

38 71 75

B

38 71 75

38 71 75

38 71 75

Thunderbolt lane 1

Thunderbolt lane 2

Thunderbolt lane 3

AirPort

Reserved: FireWire

SD Card Reader
(& Ethernet if combo)

Camera

LPC_AD<0>

BI

LPC_AD<1>

BI

LPC_AD<2>

BI

LPC_AD<3>

BI

LPC_FRAME_L

OUT

PP1V05_S0SW_PCH_VCCUSB3PLL

8

11

PLACE_NEAR=U0500.A27:2.54mm

R1540
R1541
R1542
R1543

R1544

33
33
33
33

33

1 2
1 2
1 2
1 2

1 2

R1500

3.01K

1/20W

201

5% 201MF
5% 201MF
5% 201MF
5% 201MF

5% 201MF

PCIE_TBT_D2R_N<0>

25 71 81

IN

PCIE_TBT_D2R_P<0>

25 71 81

IN

PCIE_TBT_R2D_C_N<0>

25 71 81

OUT

PCIE_TBT_R2D_C_P<0>

25 71 81

OUT

PCIE_TBT_D2R_N<1>

25 71 81

IN

PCIE_TBT_D2R_P<1>

25 71 81

IN

PCIE_TBT_R2D_C_N<1>

25 71 81

OUT

PCIE_TBT_R2D_C_P<1>

25 71 81

OUT

PCIE_TBT_D2R_N<2>

25 71 81

IN

PCIE_TBT_D2R_P<2>

25 71 81

IN

PCIE_TBT_R2D_C_N<2>

25 71 81

OUT

PCIE_TBT_R2D_C_P<2>

25 71 81

OUT

PCIE_TBT_D2R_N<3>

25 71 81

IN

PCIE_TBT_D2R_P<3>

25 71 81

IN

PCIE_TBT_R2D_C_N<3>

25 71 81

OUT

PCIE_TBT_R2D_C_P<3>

25 71 81

OUT

PCIE_AP_D2R_N

66 71 81

IN

PCIE_AP_D2R_P

66 71 81

IN

PCIE_AP_R2D_C_N

66 71 81

OUT

PCIE_AP_R2D_C_P

66 71 81

OUT

TP_PCIE_FW_D2RN

69

TP_PCIE_FW_D2RP

69

TP_PCIE_FW_R2D_CN

69

TP_PCIE_FW_R2D_CP

69

USB3RPCIE_SD_D2R_N

66 71 74

IN

USB3RPCIE_SD_D2R_P

66 71 74

IN

USB3RPCIE_SD_R2D_C_N

66 74

OUT

USB3RPCIE_SD_R2D_C_P

66 74

OUT

PCIE_CAMERA_D2R_N

34 71 81

IN

PCIE_CAMERA_D2R_P

34 71 81

IN

PCIE_CAMERA_R2D_C_N

34 81

OUT

PCIE_CAMERA_R2D_C_P

34 81

OUT

PCH_PCIE_RCOMP

75

1

1%
MF

2

1/20W
1/20W
1/20W
1/20W

1/20W

47 75

47 75

47 75

47 75

14 47 75

14 47 75

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

LPC_FRAME_R_L

SPI_CLK_R

OUT

SPI_CS0_R_L

OUT

TP_SPI_CS1_L

69

TP_SPI_CS2_L

69

SPI_MOSI_R

BI

SPI_MISO

BI

SPI_IO<2>

BI

SPI_IO<3>

BI

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

AU14
AW12
AY12
AW11

AV12

AA3

AC2

AA2

AA4

AF1

E13
A27

Y7

Y4

Y6

RSVD
RSVD
PCIE_RCOMP
PCIE_IREF

(IPU)

LAD0
LAD1
LAD2
LAD3

LFRAME*

SPI_CLK

SPI_CS0*

SPI_CS1*

SPI_CS2*

SPI_MOSI

(IPU/IPD)

SPI_MISO

SPI_IO2

(IPU)

SPI_IO3

(IPU)

NC
NC

OMIT_TABLE

CRITICAL

BROADWELL-ULT

SYM 11 OF 19

OMIT_TABLE

CRITICAL

BROADWELL-ULT

SYM 7 OF 19

LPC

SMBUS

(IPU)

SML1ALERT*/PCHHOT*/GPIO73

(IPU)

(IPU)

(IPU)

SPI

(IPU)

C-LINK

U0500

2C+GT2

BGA

USB

PCI-E

U0500

2C+GT2

BGA

SML0ALERT*/GPIO60

(IPU/IPD)

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

(IPD)

USB3RN1
USB3RP1

USB3TN1
USB3TP1

USB3RN2
USB3RP2

USB3TN2
USB3TP2

USBRBIAS*

USBRBIAS

RSVD
RSVD

OC0*/GPIO40
OC1*/GPIO41
OC2*/GPIO42
OC3*/GPIO43

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1DATA/GPIO74

(IPU/IPD)

CL_CLK

CL_DATA

CL_RST*

AN8
AM8

AR7
AT7

AR8
AP8

AR10
AT10

AM15
AL15

AM13
AN13

AP11
AN11

AR13
AP13

G20
H20

C33
B34

E18
F18

B33
A33

AJ10
AJ11

AN10
AM10

AL3
AT1
AH2
AV3B27

AN2

AP2
AH1

AL2

AN1
AK1

AU4

AU3
AH3

AF2

AD2

AF4

USB_EXTA_N
USB_EXTA_P

USB_EXTB_N
USB_EXTB_P

USB_BT_N
USB_BT_P

USB_IR_N
USB_IR_P

USB_TPAD_N
USB_TPAD_P

TP_USB_5N
TP_USB_5P

TP_USB_CAMERAN
TP_USB_CAMERAP

TP_USB_SDN
TP_USB_SDP

USB3_EXTA_D2R_N
USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_N
USB3_EXTB_D2R_P

USB3_EXTB_R2D_C_N
USB3_EXTB_R2D_C_P

PCH_USB_RBIAS

74

NC
NC

XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L

PCH_SMBALERT_L
SMBUS_PCH_CLK

SMBUS_PCH_DATA

WOL_EN
SML_PCH_0_CLK

SML_PCH_0_DATA

PCH_SML1ALERT_L
SML_PCH_1_CLK

SML_PCH_1_DATA

TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L

35 74

BI

35 74

BI

66 74

BI

66 74

BI

31 74

BI

31 74

BI

69

BI

69

BI

36 71 74

BI

36 71 74

BI

69

69

69

69

69

69

35 71 74

IN

35 71 74

IN

35 71 74

OUT

35 71 74

OUT

66 71 74

IN

66 71 74

IN

66 71 74

OUT

66 71 74

OUT

14 16

IN

14 16

IN

14 16

IN

14 16

IN

14

41 71 75

OUT

41 71 75

BI

14 71

OUT

41 75

OUT

41 75

BI

40

OUT

41 75

OUT

41 75

BI

69

69

69

USB Port Assignments:

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

BT

IR

Trackpad

Unused

Reserved: Camera

Reserved: SD (HS)

USB3 Port Assignments:

Ext A (SS)

Ext B (SS)

PLACE_NEAR=U0500.AJ10:2.54mm

1

R1570

22.6

1%
1/20W
MF
201

2

SML1ALERT# pull-up not provided on this
page, may be wire-ORed into other signals.
Otherwise, 100k pull-up to 3.3V SUS required.

D

C

B

=PP3V3_SUS_PCH_GPIO

A

=PP3V3_SUS_PCH_VCC_SPI

100K

R1580
R1581
R1582
R1583

R1548
R1549

R1590
R1591

100K
100K
100K

1K
1K

100K
100K

1 2
1 2
1 2

1 2

1 2
1 2

1 2
1 2

68

8

11 68

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L

SPI_IO<2>
SPI_IO<3>

PCH_SMBALERT_L
WOL_EN

14 16

14 16

14 16

14 16

14 47 75

14 47 75

14

14 71

6 3

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

PAGE TITLE

PCH PCIe,USB,LPC,SPI,SMBus

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=10/23/2012

051-1573

8.0.0

dvt1

15 OF 120

14 OF 82

SIZE

A

D

D

C

B

A

BOM GROUP

RAMCFG_SLOT

RAMCFG3:H

R1631

100K

1/20W

201

=TBT_GO2SX_BIDIR

69

BI

15 36 71

IN

8 7 6 5 4 3

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

OMIT_TABLE

BROADWELL-ULT

P1
AU2
AM7
AD6

Y1

T3
AD5
AN5
AD7
AN3
AG6
AP1
AL4
AT5
AK4
AB6

U4

Y3

P3

Y2
AT3
AH4
AM4
AG5
AG3
AM3
AM2

P2

C4

L2

N5

V2

SYM 10 OF 19

BMBUSY*/GPIO76

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

GPIO16

GPIO17

GPIO24

GPIO27

GPIO28

GPIO26

GPIO56

GPIO57

GPIO58

GPIO59

GPIO44

GPIO47

GPIO48

GPIO49

GPIO50

HSIOPC/GPIO71

GPIO13

GPIO14

GPIO25

GPIO45

GPIO46

GPIO9

GPIO10

DEVSLP0/GPIO33

SDIO_POWER_EN/GPIO70

DEVSLP1/GPIO38

DEVSLP2/GPIO39

SPKR/GPIO81

(IPD-PLTRST#)

CRITICAL

U0500

2C+GT2

BGA

(IPD-RSMRST#)

(IPD-DeepSx)

THERMTRIP*

RCIN*/GPIO82

PCH_OPI_COMP

CPU/MISC

GSPI0_CS*/GPIO83

GSPI0_CLK/GPIO84

GSPI0_MISO/GPIO85
(IPD)

GSPI0_MOSI/GPIO86
(IPD-PLTRST#)

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI1_MISO/GPIO89
(IPD)

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

UART1_RXD/GPIO0

LPIO

GPIO

UART1_TXD/GPIO1

UART1_RST*/GPIO2

UART1_CTS*/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66

(IPD-PLTRST#)

SDIO_D1/GPIO67

SDIO_D2/GPIO68

SDIO_D3/GPIO69

PP3V3_S0_EDP_SW

41 65

SERIRQ

RSVD
RSVD

=PP1V05_S0_CPU_VCCST

6 8

16 17 55 68

D60
V4
T4
AW15
AF20

AB21

R6
L6
N6
L8

R7
L5
N7
K2

J1
K3
J2
G1

K4
G2
J3
J4

F2
F3

G4
F1

E3
F4
D3
E4
C3
E2

PM_THRMTRIP_L
=TBT_CIO_PLUG_EVENT
LPC_SERIRQ
PCH_OPI_COMP

75

NC
NC

PCH_GSPI0_CS_L
PCH_GSPI0_CLK
PCH_GSPI0_MISO
PCH_GSPI0_MOSI

TPAD_SPI_CS_L
TPAD_SPI_CLK
TPAD_SPI_MISO
TPAD_SPI_MOSI

AP_S0IX_WAKE_L
HDMITBTMUX_FLAG_L
JTAG_ISP_TDO
AP_RESET_L

PCH_UART1_RXD
PCH_UART1_TXD
PCH_UART1_RTS_L
PCH_UART1_CTS_L

PCH_I2C0_SDA
PCH_I2C0_SCL

PCH_I2C1_SDA
PCH_I2C1_SCL

TBT_POC_RESET_L
BT_PWRRST_L
PCH_STRP_TOPBLK_SWP_L
ENET_MEDIA_SENSE
LCD_IRQ_L
LCD_PSR_EN

R1694

1 2

10K

5%

1/20W

MF

201

R1650

1/20W

=PP3V3_S0_PCH_GPIO

RAMCFG2:H

1

1

R1636

100K

5%

5%
1/20W

MF

MF
201

2

2

TPAD_SPI_INT_L

=PP3V3_S0_PCH_GPIO

12 13 15 18 26 65 68

=PP3V3_S5_PCH_GPIO
=PP3V3_S3RS4_PCH_GPIO
=PP3V3_S3SW_SD_RESET
=PP3V3_S3_PCH_GPIO
=PP3V3_S3RS0_CAMPWREN
=PP3V3_S0_PCH_GPIO
=PP3V3_S0RTBTLC_PCH_GPIO

TBTLC for CR, S0 for RR

R1610
R1614

R1615
R1616

R1617
R1618
R1619
R1620

R1622
R1623
R1624
R1625
R1626
R1627
R1628
R1629
R1630

R1632
R1633

R1637
R1638

R1652
R1670
R1691
R1693

R1695

12 13 15 18 26 65 68

RAMCFG1:H RAMCFG0:H

D1600

A K

BAT54XV2T1

SOD-523

R1600

R1635

100K

1/20W

1M

1/20W

201

201

5%
MF

1

1

5%
MF

2

2

1

2

TPAD_SPI_INT_GPIO28_L

1

R1681

0

5%

1/20W

MF
0201

2

1

R1682

0

5%

1/20W

MF

2

0201

TPAD_SPI_INT_GPIO46_L

13 68

68

68

68

18 44

12 13 15 18 26 65 68

68

100K
100K

100K

100K
100K
100K
100K
100K

100K
100K
100K
100K
100K
100K
100K
100K
100K

100K
100K

100K
100K

10K
100K
100K
100K

100K

1 2

1 2
1 2

SD_ON_MLB

1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2

1 2

1 2

1 2

1/20W

5% 201

1/20W
1/20W

5% MF

1/20W
1/20W

5%

1/20W

5% 201

1/20W

5%

1/20W

5%

1/20W

5%

1/20W
1/20W

5%
5%

1/20W
1/20W

5%

1/20W
1/20W
1/20W
1/20W

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W

1/20W

5% 201

1/20W

1/20W

5% MF 201

1/20W

1/20W

BOM OPTIONS

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

GPIO12:

R1611

100K

5%
1/20W
MF
201

XDP_MLB_RAMCFG0
XDP_MLB_RAMCFG1
XDP_MLB_RAMCFG2
XDP_MLB_RAMCFG3

13 15 16 18

32

18 33

R1641

MF

MF
MF5% 201

MF
MF
MF 201
MF 201

MF 201
MF 2015%

MF
MF5%

MF 2015%
MF 2015%

MF

MF5%

MF

MF

MF5%

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS
RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

15 16 18

15 16 18

15 16 18

15 16 18

PLT_RESET_L

IN

1

R1621

100K

5%

1/20W

MF

201

2

18

OUT

15

15

1

R1639

100K

1/20W

OUT

OUT

R1680

5%
MF

201

100K

5%

1/20W

MF

2

201

1 2

XDP_PCH_GPIO76
XDP_LPCPLUS_GPIO

2015%

XDP_PCH_GPIO17

SD_RESET_L

201

SMC_WAKE_SCI_L

201

TPAD_SPI_INT_L
TPAD_USB_IF_EN
SSD_PWR_EN

HDD_PWR_EN
XDP_SDCONN_STATE_CHANGE_L
SD_PWR_EN

201MF

TBT_PWR_EN

201

XDP_JTAG_ISP_TCK

201

XDP_JTAG_ISP_TDI

201MF

JTAG_TBT_TMS_PCH
PCH_HSIO_PWR_EN
TPAD_SPI_IF_EN

201MF5%

SPIROM_USE_MLB

201

CAMERA_PWR_EN_PCH

201MF

SSD_SR_EN_L

201

AP_S0IX_WAKE_SEL

201

LPC_SERIRQ
JTAG_ISP_TDO

2015%

BT_PWRRST_L
ENET_MEDIA_SENSE

201

LCD_PSR_EN

201MF5%

XDP_PCH_GPIO76

15 16

BI

XDP_MLB_RAMCFG0

15 16 18

BI

HDMI_TBT_MUX_SEL_GPIO12
TP_MEM_VDD_SEL_1V5_L
XDP_LPCPLUS_GPIO

15 16

BI

XDP_PCH_GPIO17

15 16

IN

SD_RESET_L

15 66

OUT

SMC_WAKE_SCI_L

15 38

IN

TPAD_SPI_INT_GPIO28_L

15

TPAD_USB_IF_EN

15 37

SSD_PWR_EN

15 32 64

OUT

PCH_TBT_PCIE_RESET_L
HDD_PWR_EN

15 71

OUT

XDP_SDCONN_STATE_CHANGE_L

15 16

BI

SD_PWR_EN

15 66

OUT

TBT_PWR_EN

15 25

OUT

XDP_JTAG_ISP_TCK

15 16

OUT

XDP_JTAG_ISP_TDI

15 16

OUT

JTAG_TBT_TMS_PCH

15 18

OUT

PCH_HSIO_PWR_EN

15 63

OUT

TPAD_SPI_IF_EN

15 37

OUT

XDP_MLB_RAMCFG3

15 16 18

BI

SPIROM_USE_MLB

15 47 71

BI

CAMERA_PWR_EN_PCH

15 18

OUT

TPAD_SPI_INT_GPIO46_L

15

XDP_MLB_RAMCFG1

15 16 18

1

2

BI

XDP_MLB_RAMCFG2

15 16 18

BI

SSD_SR_EN_L

15 32

OUT

AP_S0IX_WAKE_SEL

15 31

OUT

SSD_RESET_L

CAM_PCIE_RESET_L

PCH_TCO_TIMER_DISABLE

201MF5%1K1/20W

15 16

15 16

15 16

R1616 should also be stuffed if

15 66

platform does not use SD card

15 38

15 36 71

15 37

15 32 64

15 71

15 16

15 66

15 25

15 16

15 16

15 18

15 63

15 37

STUFFED R1632

15 47 71

15 18

15 32

15 31

15 38 71

15 18

15 71

15 71

15 65

6 3

12

1

1K

5%
MF

201

2

39 75

OUT

18

IN

15 38 71

BI

15

15

15

15

15 37 75

OUT

15 37 75

OUT

15 37 75

IN

15 37 75

OUT

15 31

IN

15 67

IN

15 18

IN

15

15

15

15

15

15

15

15

26

OUT

15 71

OUT

40

IN

15 71

IN

65 71

IN

15 65

OUT

Pull-up/down on chipset support page (depends on TBT controller)
Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.
Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

PLACE_NEAR=U0500.AW15:2.54mm

1

R1655

49.9

1%
1/20W
MF
201

2

PLT_RESET_L

1

R1671

100K

5%
1/20W
MF
201

2

66

OUT

IN

13 15 16 18

Pull-up on TBT page

Requires connection to SMC via 1K series R

=PP3V3_S0_PCH_GPIO

12 13 15 18 26 65 68

100K

PCH_GSPI0_CS_L

15

PCH_GSPI0_CLK

15

PCH_GSPI0_MISO

15

PCH_GSPI0_MOSI

15

TPAD_SPI_CS_L

15 37 75

TPAD_SPI_CLK

15 37 75

TPAD_SPI_MISO

15 37 75

TPAD_SPI_MOSI

15 37 75

AP_S0IX_WAKE_L

15 31

HDMITBTMUX_FLAG_L

15 67

PCH_UART1_RXD

15

PCH_UART1_TXD

15

PCH_UART1_RTS_L

15

PCH_UART1_CTS_L

15

PCH_I2C0_SDA

15

PCH_I2C0_SCL

15

PCH_I2C1_SDA

15

PCH_I2C1_SCL

15

BOM_COST_GROUP=CPU

R1660
R1661
R1662
R1663

R1664
R1665
R1666
R1667

R1668
R1669

R1672
R1673
R1674
R1675

R1676
R1677

R1678
R1679

SYNC_MASTER=J41 SYNC_DATE=01/19/2013

PAGE TITLE

PCH GPIO/MISC/LPIO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

100K
100K
100K

47K
47K
47K
47K

100K
100K

100K
100K
100K
100K

100K
100K

100K
100K

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2

1/20W

5% 201MF

1/20W

5% 201

1/20W

5%

1/20W

5% 201

1/20W

5%

1/20W
1/20W

5% 201

1/20W

5%

1/20W

5% MF
5% 201

1/20W

5%

1/20W
1/20W
1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W
1/20W

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

MF
MF 201
MF

MF5% 201
MF

201

MF

201MF

201

MF

201MF

MF 2015%

MF 2015%
MF 2015%

051-1573

8.0.0
dvt1

16 OF 120

15 OF 82

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

12

=PP1V05_S0_XDP

XDP

10%

6.3V
0201

68

1

R1830

150

5%
1/16W
MF-LF
402

2

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2
HOOK3

TCK1
TCK0

XDP

1

1

R1831

1K

5%
1/16W

2

MF-LF
402

2

C1800

0.1UF

CERM-X5R

Extra BPM Testpoints

XDP_BPM_L<2>

6

73

IN

XDP_BPM_L<3>

6

73

IN

XDP_BPM_L<4>

6

73

IN

XDP_BPM_L<5>

6

73

IN

XDP_BPM_L<6>

6

73

IN

XDP_BPM_L<7>

6

73

IN

D

CPU_VCCST_PWRGD

8

17 73

IN

PM_PWRBTN_L

13 38 75

OUT

PM_PCH_SYS_PWROK

13 17 38 75

OUT

XDP_CPU_TCK

6

16 73

C

12 16 73

OUT

OUT

PCH_JTAGX

1

TP

TP1802

TP-P6

1

TP

TP1803

TP-P6

1

TP

TP1804

TP-P6

1

TP

TP1805

TP-P6

1

TP

TP1806

TP-P6

1

TP

TP1807

TP-P6

PLACE_NEAR=U0500.C61:2.54mm

PLACE_NEAR=U5000.J3:2.54mm

R1800
R1802

R1804

R1835

1K

0

0

0

XDP

1 2

5% 201

XDP

1 2

5%

XDP

1 2

5%

XDP

1 2

5%
PLACE_NEAR=J1800.58:28mm

1/20W

1/20W

1/16W

1/20W

MF

MF

MF-LF

MF

0201

402

0201

XDP_CPU_PREQ_L

6

73

BI

XDP_CPU_PRDY_L

6

73

IN

CPU_CFG<0>

6

73

IN

CPU_CFG<1>

6

73

IN

CPU_CFG<2>

6

73

IN

CPU_CFG<3>

6

73

IN

XDP_BPM_L<0>

6

73

IN

XDP_BPM_L<1>

6

73

IN

CPU_CFG<4>

6

73

IN

CPU_CFG<5>

6

73

IN

CPU_CFG<6>

6

73

IN

CPU_CFG<7>

6

73

IN

XDP_CPU_VCCST_PWRGD

73

XDP_CPU_PWRBTN_L

75

CPU_PWR_DEBUG

8

OUT

XDP_SYS_PWROK

75

=SMBUS_XDP_SDA

41

BI

=SMBUS_XDP_SCL

41

IN

XDP_PCH_TCK

12 16 73

OUT

C1804

0.1UF

CERM-X5R

XDP_CPU_PRESENT_L

PCH XDP Signals

These signals do not connect to XDP connector in this architecture, only accessible
via Top-Side Probe. Nets are listed here to show XDP associations and to make clear
what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

PCH/XDP Signals

XDP_MLB_RAMCFG0

15 18

B

A

BI

XDP_USB_EXTA_OC_L

14 35

OUT

XDP_USB_EXTB_OC_L

14

OUT

XDP_USB_EXTC_OC_L

14

OUT

XDP_USB_EXTD_OC_L

14

IN

XDP_SDCONN_STATE_CHANGE_L

15

OUT

XDP_MLB_RAMCFG1

15 18

BI

XDP_MLB_RAMCFG2

15 18

BI

XDP_MLB_RAMCFG3

15 18

BI

XDP_JTAG_ISP_TCK

15 18

IN

XDP_SSD_PCIE3_SEL_L

12

OUT

XDP_SSD_PCIE2_SEL_L

12

OUT

XDP_SSD_PCIE1_SEL_L

12

OUT

XDP_SSD_PCIE0_SEL_L

12

OUT

XDP_LPCPLUS_GPIO

15

BI

XDP_PCH_GPIO17

15

OUT

XDP_PCH_GPIO76

15

BI

XDP_JTAG_ISP_TDI

15 18

IN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

R1881
R1882
R1883
R1884

MAKE_BASE=TRUE

MAKE_BASE=TRUE

Unused & MLB_RAMCFGx GPIOs have TPs.
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.
SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.
NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.
SSD_PCIEx_SEL_L straps are connected via 1K to common net.
LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

1

TP

TP1870

TP-P6

1

TP

TP1873

TP-P6

1

TP

TP1874

TP-P6

1

TP

TP1876

TP-P6

1

TP

TP1877

TP-P6

1

TP

TP1878

TP-P6

1K

1 2

1K

1 2

1K

1 2

1K

1 2

5% 201

5% 201

5% 201

5% 201

1

TP

TP1886

TP-P6

1

TP

TP1887

TP-P6

1/20W

1/20W

1/20W

1/20W

MF

MF

MF

MF

Non-XDP Signals

USB_EXTA_OC_L
USB_EXTB_OC_L

SDCONN_STATE_CHANGE_L

JTAG_ISP_TCK

NOTE: Must not short XDP pins together!

SSD_PCIE_SEL_L
LPCPLUS_GPIO

JTAG_ISP_TDI

IN

66

IN

18

IN

OUT

32

IN

71

BI

OUT

Merged (CPU/PCH) Micro2-XDP

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7

TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R
0201

SDA
SCL

XDP

10%

6.3V
0201

DF40RC-60DP-0.4V

1

2

CRITICAL
XDP_CONN

J1800

M-ST-SM1

62

61

1

2

3

4

5

6

78

10

9
1112
1314
1516
1718
19

20

2122
2324
2526
2728
29

30

3132
3334
3536
3738
39

40

4142
4344
4546
4748
49

50

5152
5354
5556
5758
59

60

6364

518S0847

CPU JTAG Isolation

=PP5V_S0_XDPJTAGISOL

68

=PP3V3_S5_XDPJTAGISOL

68

1

C1845

0.1UF

10%
16V

2

17 38 64

IN

X5R-CERM

ALL_SYS_PWRGD

0201

NC

74LVC1G07GF

2

A

1

NC NC

6

VCC

U1845

SOT891

GND

3

CPU_CFG<17>
CPU_CFG<16>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<10>
CPU_CFG<11>

CPU_CFG<19>
CPU_CFG<18>

CPU_CFG<12>
CPU_CFG<13>

CPU_CFG<14>
CPU_CFG<15>

NC
NC

XDP_CPURST_L
XDP_DBRESET_L

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

XDP_TRST_L

73

XDP

1

C1806

0.1UF

10%

6.3V

2

CERM-X5R
0201

PLACE_NEAR=J1800.53:28mm

PLACE_NEAR=J1800.55:28mm

1

R1845

330K

5%
1/20W
MF
201

2

Y

4

5

NC

PLACE_NEAR=J1800.57:28mm

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

6

73

IN

17 75

OUT

CRITICAL

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

PLACE_NEAR=J1800.51:28mm

CRITICAL

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

CRITICAL

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

XDP_JTAG_CPU_ISOL_L

R1805

XDP

Q1840

SOT563

XDP

Q1840

SOT563

CRITICAL

XDP

Q1842

SOT563

XDP

Q1842

SOT563

D

3

D

6

D

3

D

6

BOM_COST_GROUP=CPU SUPPORT

1K

VER 3

VER 3

VER 3

VER 3

XDP_CPU_TDO

6

16 73

XDP_CPU_TCK

6

16 73

PLACE_NEAR=U0500.F62:28mm

PLACE_NEAR=U0500.E60:28mm

R1810

R1813

TDI and TMS are terminated in CPU.

XDP

1 2

PLT_RESET_L

5% 201

1/20W

PLACE_NEAR=U0500.AG7:2.54mm

MF

XDP_PCH_TDO

XDP_PCH_TDI
XDP_PCH_TMS

5

S G

4

2

S G

1

5

S G

4

2

S G

1

XDP_CPU_TDO

XDP_CPUPCH_TRST_L

MAKE_BASE=TRUE

XDP_CPU_TRST_L
XDP_PCH_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

PCH_JTAGX

12 16 73

XDP_PCH_TDO

12 16 73

XDP_PCH_TDI

12 16 73

XDP_PCH_TMS

12 16 73

XDP_PCH_TCK

12 16 73

XDP_PCH_TRST_L

12 16

PLACE_NEAR=U0500.AE63:28mm

PLACE_NEAR=U0500.AE61:28mm

PLACE_NEAR=U0500.AD61:28mm

PLACE_NEAR=U0500.AD62:28mm

PLACE_NEAR=U0500.AE62:28mm

PLACE_NEAR=U0500.AU62:28mm

SYNC_MASTER=WFERRY_J43

PAGE TITLE

R1899
R1890

R1891
R1892

R1896

R1897

CPU/PCH Merged XDP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

=PP1V05_S0_CPU_VCCST

6 8

15 17 55 68

XDP

51

1 2

XDP

51

2 1

13 15 18

IN

12 16 73

IN

12 16 73

OUT

12 16 73

OUT

6

16 73

IN

73

6

OUT

12 16

OUT

6

73

OUT

6

73

OUT

=PP1V05_SUS_PCH_JTAG

68

NO STUFF

1K

2 1

XDP

51

2 1

XDP

51

2 1

XDP

51

2 1

NO STUFF

51

2 1

NO STUFF

51

2 1

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

5% 201

1/20W

MF

SYNC_DATE=12/21/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

18 OF 120

SHEET

16 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

System RTC Power Source & 32kHz / 25MHz Clock Generator

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

This looks a little ugly to support
new and old parts. With GreenCLK Rev C
pin 5 must receive S5 power (Stuff R2042)

D

GreenCLK 25MHz Power
Must be powered if any VDDIO is powered.

CAM XTAL Power
TBT XTAL Power

C1905

12PF

0201

C1906

5%

CERM

12PF

1 2

5%

25V
CERM
0201

12

NC
NC

SYSCLK_CLK25M_X2

74

25V

CRITICAL

1 3

Y1905

2 4

SM-3.2X2.5MM

25.000MHZ-12PF-20PPM
OMIT

NOTE: 30 PPM or better required for RTC accuracy

C

C1915

6.8PF

1 2

+/-0.1PF

25V
C0G

NC

0201

NC

C1916

6.8PF

1 2

+/-0.1PF

25V
C0G

0201

LPC_CLK24M_SMC_R

12 75

IN

13

PLACE_NEAR=U0500.AN15:5.1mm

PCH 24MHz Crystal

PCH_CLK24M_XTALOUT_R

75

CRITICAL

Y1915

NC

24.000MHZ-20PPM-6PF

24

NC

3.20X2.50MM-SM1

PCH 24MHz Outputs

B

=PP3V3_S3RS0_SYSCLKGEN

18

=PPVDDIO_S3RS0_CAMCLK

33

=PPVDDIO_TBTLC_CLK

68

C1924

0.1UF

X5R-CERM

R1905

1 2

R1927

22

1 2

5%

1/20W

MF

201

10%
16V

0201

0

5%

1/20W

MF

0201

R1915

0

1 2

5%

1/20W

MF

0201

=PPVBAT_G3H_SYSCLK

68

Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)

=PP3V3_S5_SYSCLK

18 68

Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5

1

C1922

0.1UF

10%

2

16V

X5R-CERM

0201

CKPLUS_WAIVE=PwrTerm2Gnd

SYSCLK_CLK25M_X2_R

74

NO STUFF

1

R1906

1M

5%
1/20W
MF
201

2

SYSCLK_CLK25M_X1

74

PCH_CLK24M_XTALOUT

1

R1916

1M

5%
1/20W
MF
201

2

PCH_CLK24M_XTALIN

LPC_CLK24M_SMC

MAKE_BASE=TRUE

LPC_CLK_SMC

No bypass necessary

1

1

C1902

1UF

20%

6.3V

2

2

X5R
0201

71 75

OUT

11

14

IN

OUT

38

5

2

NC

VDD

U1900

SLG3NB148CV

TQFN

CRITICAL

GND

71016

32.768K

THRM

PAD

17

NO_TEST=TRUE

VIOE_25M_A

6

VIOE_25M_B
VIOE_25M_C

3

X2

4

X1

NC_RTC_CLK32K_RTCX2

MAKE_BASE=TRUE

12 75

12 75

13

VBAT and +V3.3A are
internally ORed to
create VDD_RTC_OUT.

VG3HOT

+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.

25M_A
25M_B
25M_C

VOUT

12

9
8
15

1

PCH_CLK32K_RTCX1

NC

SYSCLK_CLK25M_CAMERA
SYSCLK_CLK25M_TBT
=PPVRTC_G3_OUT

1

2

PCH_CLK32K_RTCX2

For SB RTC Power

C1910

1UF

20%

6.3V
X5R
0201

PCH Reset Button

17 68

XDP_DBRESET_L

OUT

OUT
OUT

68

IN

=PP3V3_S0_SB_PM

XDP

R1996

1 2

1/20W

0201

MF
5%

12 75

34 74

25 74

12

12

Memory VTT Enable Level-Shifter

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

=PP1V2_S3_MEM_VTTPWRCTL

1

R1995

10K

5%
1/20W
MF
201

2

0

PM_SYSRST_L

NO STUFF

1

R1997

0

5%
1/16W
MF-LF
402

2

SILK_PART=SYS RESET

13 38 71 75 16 75

BIIN

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

8

11 63

68

CPU_MEMVTT_PWR_EN_LSVDDQ

6

IN

C1970

0.1UF

X5R-CERM

0201

10%
16V

1

2

NC

6

VCC

U1970

74AUP1G07GF

SOT891

2

A Y

1

NC NC

GND

3

=PP3V3_S0_MEM_VTTPWRCTL

1

R1970

330K

5%
1/20W
MF
201

2

4

5

NC

=PP5V_S0_PCH_STRAP

68

PCH ME Disable Strap

SIGNAL_MODEL=DMN5L06VK_7

SIGNAL_MODEL=DMN5L06VK_7

SPI_DESCRIPTOR_OVERRIDE_L

38

IN

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

=PP3V3_S5_CSPWRGD

68

16 17 38 64

13 18 38 64 66 71

IN

Q1920

DMN5L06VK-7

SOT563

DMN5L06VK-7

D

3

Q1920

SOT563

VER 3

VER 3

2

5

SPI_DESCRIPTOR_OVERRIDE_LS5V

S G

SPI_DESCRIPTOR_OVERRIDE

4

6

D

SG

1

VCCST (1.05V S0) PWRGD

C1930

0.1UF

X5R-CERM

ALL_SYS_PWRGD
PM_SLP_S3_L

10%
16V

0201

1

2

NC

CRITICAL

U1930

74AUP1G09

SOT891

VCC

2

1

B

5

NC

GND

4

YA

3 6

=PP1V05_S0_CPU_VCCST

1

R1931

10K

5%
1/20W
MF
201

2

CPU_VCCST_PWRGD

68

TPS51916 I(leak) = +/- 1uA,
Vih(min) = 1.8V
33uW when driven-low

MEMVTT_PWR_EN

MAKE_BASE=TRUE

=DDRVTT_EN

1

R1921

2

57

OUT

1

R1920

100K

5%
1/20W
MF
201

2

1K

5%
1/20W
MF
201

HDA_SDOUT_R

IPD = 9-50k

8

OUT

6 8

16 73

15 16 55 68

D

12 75

OUT

C

B

=PP3V42_G3H_CSPWRGD

68

=PP3V3_S0_SB_PM

17 68

1

CPU_VR_EN

8

55

IN

1

R1955

10K

5%

A

CPU_VR_READY

8

OUT

MAKE_BASE=TRUE

CPUVR_PGOOD

55

IN

1/20W

NO STUFF

MF

201

R1951

2

0

1 2

5%

1/20W

MF

0201

ALL_SYS_PWRGD

16 17 38 64

IN

CPUVR_PGOOD_R

SMC_DELAYED_PWRGD

26 27 38 39 75

IN

R1950

10K

1/20W

5%
MF

201

2

PCH PWROK Generation

BYPASS=U1950::5MM

1

C1950

0.1UF

10%

1

2

A

U1950

B

16V

2

X5R-CERM
0201

74LVC2G08GT/S505

8

SOT833

7

Y

08

4

PM_S0_PGOOD

75

NO STUFF

R1963

R1961

100K

1/20W

201

1/20W

5%
MF

0201

1

2

NO STUFF

2

2

R1960

0

0

5%

5%
1/20W

MF

MF
0201

1

1

WF: Do we need this?

CKPLUS_WAIVE=UNCONNECTED_PINS

8

74LVC2G08GT/S505

SOT833

5

A

3

SYS_PWROK_R

75

Y

U1950

6

08

B

4

CKPLUS_WAIVE=UNCONNECTED_PINS

R1962

1K

1 2

5%

1/20W

MF

201

6 3

PM_PCH_APWROK
PM_PCH_PWROK

MAKE_BASE=TRUE

PM_PCH_SYS_PWROK

OUT

13

OUT

13 75

OUT

13 16 38 75

PART NUMBER

197S0480

QTY

1

DESCRIPTION

XTAL,25MHZ,20PPM,12PF,3.2X2.5X.6MM,85C

BOM_COST_GROUP=CPU SUPPORT

REFERENCE DES

CRITICAL

Y1905

PAGE TITLE

Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM OPTION

SYNC_DATE=01/30/2013SYNC_MASTER=J41

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

SHEET

124578

8.0.0
dvt1

19 OF 120

17 OF 82

SIZE

A

D

8 7 6 5 4 3

12

Platform Reset Connections

=PP3V3_S3_SYSCLKGEN

PLT_RESET_L

13 15 16

IN

=PP3V3_S0_SYSCLKGEN

68

D

=PP3V3_S5_SYSCLK

17 68

=PP3V3_S0_RSTBUF

68

CRITICAL

5

MC74VHC1G08

1

C2071

0.1UF

10%
16V

2

X5R-CERM
0201

1

2

U2071

3

SC70-HF

4

PLT_RST_BUF_L

1

R2070

100K

5%
1/20W
MF
201

2

PCH_TBT_PCIE_RESET_L

15

IN

MAKE_BASE=TRUE

C

DBGLED

=PP3V3_S5_DBGLEDS

68

PLACE_SIDE=BOTTOM

B

R2094

0

12

5%
1/16W
MF-LF

402

DBGLED

1

R2090

20K

5%

1/20W

MF

201

DBGLED_S5

DBGLED

A

D2090

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

PLACE_SIDE=BOTTOM

K

SILK_PART=S5_ON

2

64

13 31 37 38 64 66

13 17 38 64 66 71

13 38

PP3V3_S5_DBGLED

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=3.3V

DBGLED_S4 DBGLED_S3

DBGLED

A

D2091

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

PLACE_SIDE=BOTTOM

K

SILK_PART=STBY_ON

DBGLED_S4_D

Q2090

DMN5L06VK-7

S4_PWR_EN

IN

PM_SLP_S4_L

IN

PM_SLP_S3_L

IN

PM_SLP_S0_L

IN

A

Scrub for Layout Optimization

Buffered

R2072

0

1 2

5%

1/20W

MF

0201

NO STUFF

R2089

0

1 2

5%

1/20W

MF

0201

Power State Debug LEDs

(For development only)

DBGLED

1

R2091

20K

5%

1/20W

MF

201

2

DBGLED

A

D2092

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

PLACE_SIDE=BOTTOM

K

SILK_PART=S3_ON

6

D

SG

1

DBGLED_S3_D

DMN5L06VK-7

DBGLED

SOT563

VER 3

2

SMC_LRESET_L

CAM_PCIE_RESET_L

TBT_PCIE_RESET_L

DBGLED

1

R2092

20K

5%

1/20W

MF

201

2

DBGLED

Q2090

SOT563

VER 3

3

D

5

SG

4

38

OUT

15 33

OUT

25

OUT

To SMC

16

OUT

DBGLED

R2093

20K

5%

1/20W

MF

201

DBGLED_S0I3

DBGLED

A

D2093

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

PLACE_SIDE=BOTTOM

K

SILK_PART=S0I3_ON

DBGLED_S0I3_D

DBGLED

Q2091

DMN5L06VK-7

SOT563

VER 3

2

SMC_PME_S4_DARK_L

38 39

=SMC_PME_SDCONN_L

=PP3V3_S3_SDBUF

68

SDCONN_STATE_CHANGE_L

To PCH

1

2

DBGLED_S0

A

K

DBGLED_S0_D

6

D

SG

1

BYPASS=U2030.5::5MM

R2095

DBGLED

D2095

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

PLACE_SIDE=BOTTOM
SILK_PART=S0_ON

DBGLED

Q2091

DMN5L06VK-7

SOT563

VER 3

DBGLED

20K

1/20W

5

SDCONN_STATE_CHANGE Isolation

Q2030

DMN5L06VK-7

SOT563

1

C2031

0.1UF

10%

6.3V

2

CERM-X5R

0201

1

5%
MF

201

2

3

D

SG

4

BYPASS=U2030::3mm

R2034

1/20W

BYPASS=U2030::3mm

C2034

0.1UF

X5R-CERM

0201

6 3

GreenCLK 25MHz Power

NO STUFF

R2040

0

1 2

5%

1/20W

MF

0201

NO STUFF

R2041

0

1 2

5%

1/20W

MF

0201

R2042

0

1 2

5%

1/20W

MF

0201

=PP3V3_S4_SMC

39 40 68

5

SMC_PME_SDCONN

VER 3

D

S G

3

4

Y A

4

CRITICAL

U2031

74AUP1G09

SOT891

VCC

2

1

B

5

NC

GND

3 6

NC

=PP3V3_S3RS0_CAMPWREN

1

10K

5%
MF

201

2

CAMERA_PWR_EN_RC

1

10%
10V

2

CAMERA_PWR_EN_PCH

15

IN

I1608

=PP3V3_S3RS0_SYSCLKGEN
PP3V3_S5RS3RS0_SYSCLKGEN

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

R2041/2 should be stuffed for
GreekCLK A or B depending on S2 rail

17 68

R2042 should be stuffed for GreenCLK C

1

R2032

470K

5%
1/20W
MF
201

2

2

S G

1

R2031

470K

1/20W

201

1

5%
MF

2

Q2030

DMN5L06VK-7

SOT563

VER 3

D

6

SDCONN_STATE_CHANGE_RIO

15 44

=PP3V3_S4_CAMPWREN

BYPASS=U2030::3mm

C2030

0.1UF

10%
10V

X5R-CERM

0201

1

2

1

2

U2030

CRITICAL

5

MC74VHC1G08

SC70-HF

4

3

CAMERA_PWR_EN_R

=PP3V3_S0_PCH_GPIO

12 13 15 26 65 68

THUNDERBOLT PULL-UP

REDWOOD RIDGE PLUG_EVENT IS ACTIVE-LOW, ALWAYS DRIVEN (PULL-UP)

=TBT_CIO_PLUG_EVENT

15

OUT

MAKE_BASE

TBT_CIO_PLUG_EVENT_L

TRUE

Redwood Ridge JTAG Isolation

TBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

PP3V3_TBTLC

25 26 68

1

1

1

R2061

100K

1/20W

201

From RR

From PCH

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK
and TDI as well for PCH glitch-prevention.

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for
Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs
different isolation techniques will likely be necessary.
Multi-router designs also require different circuitry.

66

IN

JTAG_TBT_TDO

25

IN

JTAG_TBT_TMS_PCH

15

IN

S0 pull-up on PCH page

JTAG_ISP_TCK

16

IN

MAKE_BASE=TRUE

JTAG_ISP_TDI

16

IN

MAKE_BASE=TRUE

Renaming the pins N61 and P61 to remove automatic diffpari property

Pin N61 needs a TP for Power to perform iFDIM test

TP_CPU_RSVD_N61

8

TP_CPU_RSVD_P61

8

C2060

0.1UF

5%
MF

20%
10V

2

CERM
402

2

VCC

U2060

74LVC2G07

SOT891

1

1A 1Y

3

2A 2Y

GND

2 5

JTAG_TBT_TCK
JTAG_TBT_TDI

TP_CPU_RSVDN61

MAKE_BASE=TRUE

TP_CPU_RSVDP61

MAKE_BASE=TRUE

RAM Configuration Straps

Pull-downs for chip-down RAM systems

XDP_MLB_RAMCFG0

15 16

OUT

XDP_MLB_RAMCFG1

15 16

OUT

XDP_MLB_RAMCFG2

15 16

OUT

XDP_MLB_RAMCFG3

15 16

68

R2033

33

1 2

5%

1/20W

MF

201

CAMERA_PWR_EN

OUT

OUT

RAMCFG3:L

R2050

33

SYNC_MASTER=J41

PAGE TITLE

10K

1/20W

201

5%
MF

RAMCFG2:L

1

R2051

2

Project Chipset Support

R2030

0

1 2

5%

1/20W

MF

0201

NOSTUFF

BOM_COST_GROUP=CPU SUPPORT

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

R

R2062

100K

5%
1/20W
MF
201

2

S0 pull-up on PCH page

JTAG_ISP_TDO

6

JTAG_TBT_TMS

4

RAMCFG1:L

1

R2052

10K

5%

1/20W

201

MF

1/20W

2

R2015

100K

1/20W

1

10K

5%
MF

201

2

1

5%
MF

201

2

OUT

OUT

25

OUT

25

OUT

RAMCFG0:L

R2053

1/20W

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

SHEET

124578

25 75

IN

To PCH

15

To RR

25

1

10K

5%
MF

201

2

SYNC_DATE=10/23/2012

8.0.0
dvt1

20 OF 120

18 OF 82

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

NOTE: CPU DAC output step sizes:
DDR3 (1.5V) 7.70mV per step
DDR3L (1.35V) 6.99mV per step
LPDDR3 (1.2V) ?.??mV per step

CPU_DIMMA_VREFDQ

7

76

IN

C

CPU_DIMMB_VREFDQ

7

76

IN

CPU_DIMM_VREFCA

7

76

IN

NOTE: CPU has single output for VREFCA.
VREFCA. Connected to 4 DRAMs.

CPU-Based Margining

VRef Dividers

Always used, regardless
of margining option.

R2223

10

1 2

1%

PLACE_NEAR=R2221.2:1mm

1/20W

MF

201

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_A_RC

R2243

10

1 2

1%

PLACE_NEAR=R2241.2:1mm

1/20W

MF

201

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFDQ_B_RC

R2263

5.1

1 2

1%

PLACE_NEAR=R2261.2:1mm

1/20W

MF

0201

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM
0201

MEM_VREFCA_RC

R2222

8.2K

1/20W

R2220

24.9

1 2

1%

1/20W

MF

201

R2242

8.2K

1/20W

R2240

24.9

1 2

1%

1/20W

MF

201

R2262

8.2K

1/20W

R2260

24.9

1 2

1%

1/20W

MF

201

201

201

201

=PPDDR_S3_MEMVREF

1

R2221

8.2K

1%
1/20W
MF
201

2

PPVREF_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

1

1%
MF

2

1

R2241

8.2K

1%
1/20W
MF
201

2

PPVREF_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

1

1%
MF

2

1

R2261

8.2K

1%
1/20W
MF
201

2

PPVREF_S3_MEM_VREFCA

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

1

1%
MF

2

68

68

68

68

B

D

C

B

A

DAC Channel:

PCA9557D Pin:

Nominal value

Margined target:

DAC range:

VRef current:

DAC step size:

MEM A VREF DQ

A

1

MEM B VREF DQ

LPDDR3 (1.2V)

0.600V (DAC: 0x2E.5)

0.300V - 0.900V (+/- 300mV)

0.000V - 1.199V (0x00 - 0x5D)

+73uA - -73uA (- = sourced)

6.36mV / step @ output

MEM A VREF CA

B

2

C

3

DDR3L (1.35V)

0.675V (DAC: 0x34)

0.337V - 1.013V (+/- 337.5mV)

0.000V - 1.354V (0x00 - 0x69)

+82uA - -82uA (- = sourced)

6.36mV / step @ output

MEM B VREF CA

C

4

MEM VREG

D

LPDDR3 (1.2V)

1.200V (DAC: 0x5D)

0.800V - 1.600V (+/- 400mV)

0.000V - 2.397V (0x00 - 0xBA)

+21uA - -21uA (- = sourced)

4.28mV / step @ output

5

DDR3L (1.35V)

1.343V (DAC: 0x68)

0.972V - 1.714V (+/- 371mV)

0.000V - 2.694V (0x00 - 0xD1)

+25uA - -25uA (- = sourced)

3.53mV / step @ output

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider
DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

6 3

BOM_COST_GROUP=CPU SUPPORT

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

LPDDR3 VREF Margining

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/02/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

22 OF 120

SHEET

19 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL A (0-31)

U2300

LPDDR3-1600-32GB

EDFB232A1MA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

1

C2301

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2321

1UF

10%
10V

2

X5R
402

FBGA

1

C2302

1UF

10%
10V

2

X5R
402

1

C2322

1UF

10%
10V

2

X5R
402

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2303

1UF

10%
10V

2

X5R
402

1

C2323

10UF

20%
25V

2

X5R-CERM
0603

=MEM_A_DQ<0>
=MEM_A_DQ<1>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<4>
=MEM_A_DQ<5>
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQ<12>
=MEM_A_DQ<13>
=MEM_A_DQ<14>
=MEM_A_DQ<15>
=MEM_A_DQ<16>
=MEM_A_DQ<17>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<20>
=MEM_A_DQ<21>
=MEM_A_DQ<22>
=MEM_A_DQ<23>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
=MEM_A_DQ<26>
=MEM_A_DQ<27>
=MEM_A_DQ<28>
=MEM_A_DQ<29>
=MEM_A_DQ<30>
=MEM_A_DQ<31>

=MEM_A_DQS_N<0>
=MEM_A_DQS_N<1>
=MEM_A_DQS_N<2>
=MEM_A_DQS_N<3>

=MEM_A_DQS_P<0>
=MEM_A_DQS_P<1>
=MEM_A_DQS_P<2>
=MEM_A_DQS_P<3>

1

C2304

1UF

10%
10V

2

X5R
402

1

C2324

10UF

20%
25V

2

X5R-CERM
0603

1

C2305

1UF

10%
10V

2

X5R
402

CRITICAL

1

C2335

12PF

2%
50V

2

C0G-CERM
0402

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

1

C2306

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2336

12PF

2%
50V

2

C0G-CERM
0402

1

C2307

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2337

12PF

2%
50V

2

C0G-CERM
0402

=PP1V8_S3_MEM

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

CRITICAL

1

C2334

12PF

2%
50V

2

C0G-CERM
0402

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2300

0.1UF

10%

16V

2

X5R-CERM
0201

1

C2320

1UF

10%
10V

2

X5R
402

J11

A12
A13

B13

T13

U12
U13

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

K3

CKE0

K4

CKE1

J3

CK_T

J2

CK_C

L3

CS0*

L4

CS1*

L8

DM0

G8

DM1

P8

DM2

D8

DM3

J8

ODT

B3

ZQ0

B4

ZQ1

H4

VREFCA
VREFDQ

A1
A2

B1

T1

NU

U1
U2

MEM_A_CAA<0>

24 70 76

IN

MEM_A_CAA<1>

24 70 76

IN

MEM_A_CAA<2>

24 70 76

IN

MEM_A_CAA<3>

24 70 76

IN

MEM_A_CAA<4>

24 70 76

IN

MEM_A_CAA<5>

24 70 76

IN

MEM_A_CAA<6>

24 70 76

IN

MEM_A_CAA<7>

24 70 76

IN

MEM_A_CAA<8>

24 70 76

IN

MEM_A_CAA<9>

24 70 76

IN

MEM_A_CKE<0>

7

24 76

IN

MEM_A_CKE<1>

7

24 76

IN

MEM_A_CLK_P<0>

7

24 76

IN

MEM_A_CLK_N<0>

7

24 76

C

R2300

243

1/20W

201 201

1

1%
MF

2

R2301

243

1/20W

1

1%
MF

2

C2340

0.047UF

6.3V

10%
X5R

201

1

1

C2341

0.047UF

10%

6.3V

2

2

X5R
201

IN

MEM_A_CS_L<0>

7

21 24 76

IN

MEM_A_CS_L<1>

7

21 24 76

IN

MEM_A_ODT<0>

21 24 70 76

IN

MEM_A_ZQ<0>
MEM_A_ZQ<1>

PP0V6_S3_MEM_VREFCA_A

21 68 76

PP0V6_S3_MEM_VREFDQ_A

21 68 76

B

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

A10

U10

H12

K12

A11
C12

E12
G12

H11

J10

K11
L12

N12
R12
U11

A3
A4
A5
A6

U3
U4
U5
U6

A8
A9
D4
D5
D6
G5
H5
H6

J5
J6
K5
K6

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

E8

H8
H9

J9

K8

N8

U2300

LPDDR3-1600-32GB

EDFB232A1MA

FBGA

SYM 2 OF 2

VDD1

OMIT_TABLE

CRITICAL

VDD2

VDDCA

VDDQ

VSSCA

VSSQ

VSS

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

D

C

B

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

1

C2310

1UF

A

=PP1V8_S3_MEM

20 21 22 23 68

10%
10V

2

X5R
402

1

C2330

1UF

10%
10V

2

X5R
402

1

C2311

1UF

10%
10V

2

X5R
402

1

C2331

1UF

10%
10V

2

X5R
402

1

C2312

10UF

20%
25V

2

X5R-CERM
0603

1

C2332

10UF

20%
25V

2

X5R-CERM
0603

1

C2333

10UF

20%
25V

2

X5R-CERM
0603

6 3

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

CRITICAL

1

C2338

12PF

2%
50V

2

C0G-CERM
0402

CRITICAL

1

C2339

12PF

2%
50V

2

C0G-CERM
0402

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel A (00-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

23 OF 120

SHEET

20 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL A (32-63)

U2400

LPDDR3-1600-32GB

EDFB232A1MA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

1

C2401

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2421

1UF

10%
10V

2

X5R
402

FBGA

1

C2402

1UF

10%
10V

2

X5R
402

1

C2422

1UF

10%
10V

2

X5R
402

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2403

1UF

10%
10V

2

X5R
402

1

C2423

10UF

20%
25V

2

X5R-CERM
0603

=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<36>
=MEM_A_DQ<37>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DQ<42>
=MEM_A_DQ<43>
=MEM_A_DQ<44>
=MEM_A_DQ<45>
=MEM_A_DQ<46>
=MEM_A_DQ<47>
=MEM_A_DQ<48>
=MEM_A_DQ<49>
=MEM_A_DQ<50>
=MEM_A_DQ<51>
=MEM_A_DQ<52>
=MEM_A_DQ<53>
=MEM_A_DQ<54>
=MEM_A_DQ<55>
=MEM_A_DQ<56>
=MEM_A_DQ<57>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
=MEM_A_DQ<60>
=MEM_A_DQ<61>
=MEM_A_DQ<62>
=MEM_A_DQ<63>

=MEM_A_DQS_N<4>
=MEM_A_DQS_N<5>
=MEM_A_DQS_N<6>
=MEM_A_DQS_N<7>

=MEM_A_DQS_P<4>
=MEM_A_DQS_P<5>
=MEM_A_DQS_P<6>
=MEM_A_DQS_P<7>

1

C2404

1UF

10%
10V

2

X5R
402

1

C2424

10UF

20%
25V

2

X5R-CERM
0603

1

C2405

1UF

10%
10V

2

X5R
402

CRITICAL

1

C2434

12PF

2%
50V

2

C0G-CERM
0402

A10

U10

H12

K12

A11
C12

E12
G12

H11

J10

K11
L12

N12
R12
U11

A3
A4
A5
A6

U3
U4
U5
U6

A8
A9
D4
D5
D6
G5
H5
H6

J5
J6
K5
K6

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

E8

H8
H9

J9

K8

N8

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

1

C2406

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2435

12PF

2%
50V

2

C0G-CERM
0402

1

C2407

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2436

12PF

2%
50V

2

C0G-CERM
0402

=PP1V8_S3_MEM

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2400

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2420

1UF

10%
10V

2

X5R
402

J11

A12
A13

B13

T13

U12
U13

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

K3

CKE0

K4

CKE1

J3

CK_T

J2

CK_C

L3

CS0*

L4

CS1*

L8

DM0

G8

DM1

P8

DM2

D8

DM3

J8

ODT

B3

ZQ0

B4

ZQ1

H4

VREFCA
VREFDQ

A1
A2

B1

T1

NU

U1
U2

MEM_A_CAB<0>

24 70 76

IN

MEM_A_CAB<1>

24 70 76

IN

MEM_A_CAB<2>

24 70 76

IN

MEM_A_CAB<3>

24 70 76

IN

MEM_A_CAB<4>

24 70 76

IN

MEM_A_CAB<5>

24 70 76

IN

MEM_A_CAB<6>

24 70 76

IN

MEM_A_CAB<7>

24 70 76

IN

MEM_A_CAB<8>

24 70 76

IN

MEM_A_CAB<9>

24 70 76

IN

MEM_A_CKE<2>

7

24 76

IN

MEM_A_CKE<3>

7

24 76

IN

MEM_A_CLK_P<1>

7

24 76

IN

MEM_A_CLK_N<1>

7

24 76

C

R2400

243

1/20W

1

1%
MF

201

2

R2401

243

1/20W

1

1%
MF

201

2

0.047UF

C2440

6.3V

1

1

C2441

10%
X5R

201

0.047UF

10%

6.3V

2

2

X5R
201

IN

MEM_A_CS_L<0>

7

20 24 76

IN

MEM_A_CS_L<1>

7

20 24 76

IN

MEM_A_ODT<0>

20 24 70 76

IN

MEM_A_ZQ<2>
MEM_A_ZQ<3>

PP0V6_S3_MEM_VREFCA_A

20 68 76

PP0V6_S3_MEM_VREFDQ_A

20 68 76

B

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

U2400

LPDDR3-1600-32GB

EDFB232A1MA

FBGA

SYM 2 OF 2

VDD1

OMIT_TABLE

CRITICAL

VDD2

VDDCA

VDDQ

VSSCA

VSSQ

VSS

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

D

C

B

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

1

C2410

1UF

A

=PP1V8_S3_MEM

20 21 22 23 68

10%
10V

2

X5R
402

1

C2430

1UF

10%
10V

2

X5R
402

1

C2411

1UF

10%
10V

2

X5R
402

1

C2431

1UF

10%
10V

2

X5R
402

1

C2412

10UF

20%
25V

2

X5R-CERM
0603

1

C2432

10UF

20%
25V

2

X5R-CERM
0603

1

C2433

10UF

20%
25V

2

X5R-CERM
0603

6 3

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

CRITICAL

1

C2437

12PF

2%
50V

2

C0G-CERM
0402

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

24 OF 120

SHEET

21 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL B (0-31)

U2500

LPDDR3-1600-32GB

EDFB232A1MA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

1

C2501

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2521

1UF

10%
10V

2

X5R
402

FBGA

1

C2502

1UF

10%
10V

2

X5R
402

1

C2522

1UF

10%
10V

2

X5R
402

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2503

1UF

10%
10V

2

X5R
402

1

C2523

10UF

20%
25V

2

X5R-CERM
0603

=MEM_B_DQ<0>
=MEM_B_DQ<1>
=MEM_B_DQ<2>
=MEM_B_DQ<3>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQ<6>
=MEM_B_DQ<7>
=MEM_B_DQ<8>
=MEM_B_DQ<9>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_B_DQ<12>
=MEM_B_DQ<13>
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQ<18>
=MEM_B_DQ<19>
=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DQ<22>
=MEM_B_DQ<23>
=MEM_B_DQ<24>
=MEM_B_DQ<25>
=MEM_B_DQ<26>
=MEM_B_DQ<27>
=MEM_B_DQ<28>
=MEM_B_DQ<29>
=MEM_B_DQ<30>
=MEM_B_DQ<31>

=MEM_B_DQS_N<0>
=MEM_B_DQS_N<1>
=MEM_B_DQS_N<2>
=MEM_B_DQS_N<3>

=MEM_B_DQS_P<0>
=MEM_B_DQS_P<1>
=MEM_B_DQS_P<2>
=MEM_B_DQS_P<3>

1

C2504

1UF

10%
10V

2

X5R
402

1

C2524

10UF

20%
25V

2

X5R-CERM
0603

1

C2505

1UF

10%
10V

2

X5R
402

CRITICAL

1

C2534

12PF

2%
50V

2

C0G-CERM
0402

A10

U10

H12

K12

A11
C12

E12
G12

H11

J10

K11
L12

N12
R12
U11

A3
A4
A5
A6

U3
U4
U5
U6

A8
A9
D4
D5
D6
G5
H5
H6

J5
J6
K5
K6

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

E8

H8
H9

J9

K8

N8

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

1

C2506

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2535

12PF

2%
50V

2

C0G-CERM
0402

1

C2507

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2536

12PF

2%
50V

2

C0G-CERM
0402

=PP1V8_S3_MEM

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2500

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2520

1UF

10%
10V

2

X5R
402

J11

A12
A13

B13

T13

U12
U13

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

K3

CKE0

K4

CKE1

J3

CK_T

J2

CK_C

L3

CS0*

L4

CS1*

L8

DM0

G8

DM1

P8

DM2

D8

DM3

J8

ODT

B3

ZQ0

B4

ZQ1

H4

VREFCA
VREFDQ

A1
A2

B1

T1

NU

U1
U2

MEM_B_CAA<0>

24 70 76

IN

MEM_B_CAA<1>

24 70 76

IN

MEM_B_CAA<2>

24 70 76

IN

MEM_B_CAA<3>

24 70 76

IN

MEM_B_CAA<4>

24 70 76

IN

MEM_B_CAA<5>

24 70 76

IN

MEM_B_CAA<6>

24 70 76

IN

MEM_B_CAA<7>

24 70 76

IN

MEM_B_CAA<8>

24 70 76

IN

MEM_B_CAA<9>

24 70 76

IN

MEM_B_CKE<0>

7

24 76

IN

MEM_B_CKE<1>

7

24 76

IN

MEM_B_CLK_P<0>

7

24 76

IN

MEM_B_CLK_N<0>

7

24 76

C

R2500

243

1/20W

1

1%
MF

201

2

R2501

243

1/20W

1

1%
MF

201

2

0.047UF

C2540

6.3V

1

1

C2541

10%
X5R

201

0.047UF

10%

6.3V

2

2

X5R
201

IN

MEM_B_CS_L<0>

7

23 24 76

IN

MEM_B_CS_L<1>

7

23 24 76

IN

MEM_B_ODT<0>

23 24 70 76

IN

MEM_B_ZQ<0>
MEM_B_ZQ<1>

PP0V6_S3_MEM_VREFCA_B

23 68 76

PP0V6_S3_MEM_VREFDQ_B

23 68 76

B

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

U2500

LPDDR3-1600-32GB

EDFB232A1MA

FBGA

SYM 2 OF 2

VDD1

OMIT_TABLE

CRITICAL

VDD2

VDDCA

VDDQ

VSSCA

VSSQ

VSS

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

D

C

B

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

1

C2510

1UF

A

=PP1V8_S3_MEM

20 21 22 23 68

10%
10V

2

X5R
402

1

C2530

1UF

10%
10V

2

X5R
402

1

C2511

1UF

10%
10V

2

X5R
402

1

C2531

1UF

10%
10V

2

X5R
402

1

C2512

10UF

20%
25V

2

X5R-CERM
0603

1

C2532

10UF

20%
25V

2

X5R-CERM
0603

1

C2533

10UF

20%
25V

2

X5R-CERM
0603

6 3

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

CRITICAL

1

C2537

12PF

2%
50V

2

C0G-CERM
0402

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel B (00-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

25 OF 120

SHEET

22 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL B (32-63)

U2600

LPDDR3-1600-32GB

EDFB232A1MA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

1

C2601

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2621

1UF

10%
10V

2

X5R
402

FBGA

1

C2602

1UF

10%
10V

2

X5R
402

1

C2622

1UF

10%
10V

2

X5R
402

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0_C
DQS1_C
DQS2_C
DQS3_C

DQS0_T
DQS1_T
DQS2_T
DQS3_T

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

L11
G11
P11
D11

L10
G10
P10
D10

C4
K9
R3

NC
NC
NC

1

C2603

1UF

10%
10V

2

X5R
402

1

C2623

10UF

20%
25V

2

X5R-CERM
0603

=MEM_B_DQ<32>
=MEM_B_DQ<33>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<36>
=MEM_B_DQ<37>
=MEM_B_DQ<38>
=MEM_B_DQ<39>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DQ<44>
=MEM_B_DQ<45>
=MEM_B_DQ<46>
=MEM_B_DQ<47>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<52>
=MEM_B_DQ<53>
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<56>
=MEM_B_DQ<57>
=MEM_B_DQ<58>
=MEM_B_DQ<59>
=MEM_B_DQ<60>
=MEM_B_DQ<61>
=MEM_B_DQ<62>
=MEM_B_DQ<63>

=MEM_B_DQS_N<4>
=MEM_B_DQS_N<5>
=MEM_B_DQS_N<6>
=MEM_B_DQS_N<7>

=MEM_B_DQS_P<4>
=MEM_B_DQS_P<5>
=MEM_B_DQS_P<6>
=MEM_B_DQS_P<7>

1

C2604

1UF

10%
10V

2

X5R
402

1

C2624

10UF

20%
25V

2

X5R-CERM
0603

1

C2605

1UF

10%
10V

2

X5R
402

CRITICAL

1

C2634

12PF

2%
50V

2

C0G-CERM
0402

A10

U10

H12

K12

A11
C12

E12
G12

H11

J10

K11
L12

N12
R12
U11

A3
A4
A5
A6

U3
U4
U5
U6

A8
A9
D4
D5
D6
G5
H5
H6

J5
J6
K5
K6

L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

E8

H8
H9

J9

K8

N8

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

70

BI

1

C2606

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2635

12PF

2%
50V

2

C0G-CERM
0402

1

C2607

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1

C2636

12PF

2%
50V

2

C0G-CERM
0402

=PP1V8_S3_MEM

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

C2600

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2620

1UF

10%
10V

2

X5R
402

J11

A12
A13

B13

T13

U12
U13

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

K3

CKE0

K4

CKE1

J3

CK_T

J2

CK_C

L3

CS0*

L4

CS1*

L8

DM0

G8

DM1

P8

DM2

D8

DM3

J8

ODT

B3

ZQ0

B4

ZQ1

H4

VREFCA
VREFDQ

A1
A2

B1

T1

NU

U1
U2

MEM_B_CAB<0>

24 70 76

IN

MEM_B_CAB<1>

24 70 76

IN

MEM_B_CAB<2>

24 70 76

IN

MEM_B_CAB<3>

24 70 76

IN

MEM_B_CAB<4>

24 70 76

IN

MEM_B_CAB<5>

24 70 76

IN

MEM_B_CAB<6>

24 70 76

IN

MEM_B_CAB<7>

24 70 76

IN

MEM_B_CAB<8>

24 70 76

IN

MEM_B_CAB<9>

24 70 76

IN

MEM_B_CKE<2>

7

24 76

IN

MEM_B_CKE<3>

7

24 76

IN

MEM_B_CLK_P<1>

7

24 76

IN

MEM_B_CLK_N<1>

7

24 76

C

R2600

243

1/20W

1

1%
MF

201

2

R2601

243

1/20W

1

1%
MF

201

2

0.047UF

C2640

6.3V

1

1

C2641

10%
X5R

201

0.047UF

10%

6.3V

2

2

X5R
201

IN

MEM_B_CS_L<0>

7

22 24 76

IN

MEM_B_CS_L<1>

7

22 24 76

IN

MEM_B_ODT<0>

22 24 70 76

IN

MEM_B_ZQ<2>
MEM_B_ZQ<3>

PP0V6_S3_MEM_VREFCA_B

22 68 76

PP0V6_S3_MEM_VREFDQ_B

22 68 76

B

=PP1V2_S3_MEM_VDDQ

20 21 22 23 68

=PP1V2_S3_MEM_VDD2

20 21 22 23 68

U2600

LPDDR3-1600-32GB

EDFB232A1MA

FBGA

SYM 2 OF 2

VDD1

OMIT_TABLE

CRITICAL

VDD2

VDDCA

VDDQ

VSSCA

VSSQ

VSS

B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2

C3
D3
F4
G3
G4
P3
M4
J4

B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12

D

C

B

=PP1V2_S3_MEM_VDDCA

20 21 22 23 68

1

C2610

1UF

A

=PP1V8_S3_MEM

20 21 22 23 68

10%
10V

2

X5R
402

1

C2630

1UF

10%
10V

2

X5R
402

1

C2611

1UF

10%
10V

2

X5R
402

1

C2631

1UF

10%
10V

2

X5R
402

1

C2612

10UF

20%
25V

2

X5R-CERM
0603

1

C2632

10UF

20%
25V

2

X5R-CERM
0603

1

C2633

10UF

20%
25V

2

X5R-CERM
0603

6 3

PLACEMENT_NOTE:

10uF caps are shared between DRAM.
Distribute evenly.

CRITICAL

1

C2637

12PF

2%
50V

2

C0G-CERM
0402

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

26 OF 120

SHEET

23 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

Intel recommends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

=PP0V6_S0_MEM_VTT_A

68 68

MEM_A_CAA<9>

20 70 76

IN

MEM_A_CAA<8>

20 70 76

IN

MEM_A_CAA<6>

20 70 76

IN

MEM_A_CAA<7>

20 70 76

IN

MEM_A_CAA<5>

20 70 76

IN

MEM_A_CLK_P<0>

7

20 76

IN

MEM_A_CLK_N<0>

7

20 76

IN

MEM_A_CKE<1>

7

20 76

IN

MEM_A_CKE<0>

7

20 76

IN

MEM_A_CAA<4>

20 70 76

IN

MEM_A_CAA<3>

20 70 76

IN

MEM_A_CAA<2>

20 70 76

IN

MEM_A_CAA<1> MEM_B_CAA<1>

20 70 76

IN

MEM_A_CAA<0>

20 70 76

IN

MEM_A_CAB<9>

21 70 76

IN

MEM_A_CAB<8>

21 70 76

IN

MEM_A_CAB<6>

21 70 76

IN

MEM_A_CAB<7>

21 70 76

IN

MEM_A_CAB<5>

21 70 76

IN

MEM_A_CLK_P<1>

7

21 76

IN

MEM_A_CLK_N<1>

7

21 76

IN

MEM_A_CKE<2>

7

21 76

IN

MEM_A_CKE<3>

7

21 76

IN

MEM_A_CAB<4>

21 70 76

IN

MEM_A_CAB<2>

21 70 76

IN

MEM_A_CAB<3>

21 70 76

IN

MEM_A_CAB<1>

21 70 76

IN

MEM_A_CAB<0>

21 70 76

IN

MEM_A_CS_L<0>

7

20 21 76

IN

MEM_A_CS_L<1>

7

20 21 76

IN

MEM_A_ODT<0>

20 21 70 76

IN

R2700
R2701
R2702
R2703
R2704
R2705
R2706
R2707
R2708
R2709
R2710
R2711
R2712
R2713
R2714
R2715
R2716
R2717
R2718
R2719
R2720
R2721
R2722
R2723
R2724
R2725
R2726
R2727
R2728
R2729
R2730

56
56
56
56
56
39
39
82
82
56
56
56
56
56
56
56
56

82

56

56

82
82

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1/20W

201 MF1%

1/20W
1/20W

1%
1%

1/20W

201 MF1%

1/20W

1%

1/20W
1/20W

201

1/20W

201

1%

1/20W

201 MF
201 MF

1%

1/20W

201 MF

1%

1/20W
1/20W

1%

1/20W

201

1/20W

201

1/20W
1/20W

2011%
201

1/20W

1%

201

1/20W56MF1%
1/20W
1/20W39201 MF1%
1/20W392011%

1% 201

1/20W

1% 201

1/20W82MF

20156MF

1/20W

1%
1%561/20W

201 MF

1%

201

1/20W
1%561/20W
1% 201 MF

1/20W
1% 20182MF

1/20W
1% MF201

1/20W
1% 201 MF

1/20W

MF2011%

MF201
MF201

MF201
MF1%
MF1%

MF201
MF2011%
MF1%
MF1%
MF
MF

MF562011%

MF
MF

MF
MF201

1

C2700

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2701

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2703

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2705

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2707

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2709

0.47UF

20%
4V

2

CERM-X5R-1
201

CRITICAL

1

C2720

22UF

20%

6.3V

2

X5R-CERM-1
603

1

C2730

12PF

5%
25V

2

NP0-C0G
0201

1

C2702

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2704

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2706

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2708

0.47UF

20%
4V

2

CERM-X5R-1
201

=PP0V6_S0_MEM_VTT_B

MEM_B_CAA<9>

22 70 76

IN

MEM_B_CAA<8>

22 70 76

IN

MEM_B_CAA<7>

22 70 76

IN

MEM_B_CAA<6>

22 70 76

IN

MEM_B_CAA<5>

22 70 76

IN

MEM_B_CLK_P<0>

7

22 76

IN

MEM_B_CLK_N<0>

7

22 76

IN

MEM_B_CKE<1>

7

22 76

IN

MEM_B_CKE<0>

7

22 76

IN

MEM_B_CAA<4>

22 70 76

IN

MEM_B_CAA<2>

22 70 76

IN

MEM_B_CAA<3>

22 70 76

IN

22 70 76

IN

MEM_B_CAA<0>

22 70 76

IN

MEM_B_CAB<9>

23 70 76

IN

MEM_B_CAB<8>

23 70 76

IN

MEM_B_CAB<7>

23 70 76

IN

MEM_B_CAB<6>

23 70 76

IN

MEM_B_CAB<5>

23 70 76

IN

MEM_B_CLK_N<1>

7

23 76

IN

MEM_B_CLK_P<1>

7

23 76

IN

MEM_B_CKE<2>

7

23 76

IN

MEM_B_CKE<3>

7

23 76

IN

MEM_B_CAB<4>

23 70 76

IN

MEM_B_CAB<2>

23 70 76

IN

MEM_B_CAB<3>

23 70 76

IN

MEM_B_CAB<1>

23 70 76

IN

MEM_B_CAB<0>

23 70 76

IN

MEM_B_CS_L<0>

7

22 23 76

IN

MEM_B_CS_L<1>

7

22 23 76

IN

MEM_B_ODT<0>

22 23 70 76

IN

R2740
R2741
R2742
R2743
R2744
R2745
R2746
R2747
R2748
R2749
R2750
R2751
R2752
R2753
R2754
R2755
R2756
R2757
R2758
R2759
R2760
R2761
R2762
R2763
R2764
R2765
R2766
R2767
R2768
R2769
R2770

56
56
56
56
56
39
39

82
56
56
56
56
56
56
56
56
56

39
39
82
82
56
56
56
56
56

82

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1%

1/20W

201

1% MF

1/20W

201

1/20W

1% MF201

1/20W

1% MF201
1% 201 MF

1/20W

1% 201 MF

1/20W

1% 201 MF

1/20W
1/20W

1% 20182MF

2011%

1/20W
1/20W

1% MF201

1/20W

201

1/20W

201

1/20W

1% 201 MF

1/20W

1%

201 MF

1/20W

201 MF1%

1/20W

201 MF1%

1/20W

201 MF1%

1/20W

201 MF1%561/20W

1/20W

2011%
1/20W
1/20W

2011%
1/20W

1% MF

1/20W

201

1%

201

1/20W

201

1/20W

1%
1%

201 MF

1/20W

1%

201 MF

1/20W

2011%

1/20W82MF

1% 201

1/20W

1% 20182MF

1/20W

MF

MF

MF2011%
MF1%
MF1%

MF
MF2011%
MF
MF2011%

MF
MF

MF

1

C2710

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2711

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2713

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2715

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2717

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2719

0.47UF

20%
4V

2

CERM-X5R-1
201

CRITICAL

1

C2740

22UF

20%

6.3V

2

X5R-CERM-1
603

1

C2731

12PF

5%
25V

2

NP0-C0G
0201

1

C2712

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2714

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2716

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C2718

0.47UF

20%
4V

2

CERM-X5R-1
201

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Termination

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=02/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

27 OF 120

SHEET

24 OF 82

124578

8 7 6 5 4 3

CRITICAL

OMIT_TABLE

U2800

FALCON RIDGE

FCBGA

SYM 1 OF 2

PCIE GEN2

RSVD_GND

GPIO_16/DEVICE_PCIE_RST_N

MISC

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P
REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMU_CLK_OUT

DPSRC_3_P
DPSRC_3_N

DPSRC_2_P
DPSRC_2_N

DPSRC_1_P
DPSRC_1_N

DPSRC_0_P
DPSRC_0_N

DISPLAY PORT

GPIO_2/TMU_CLK_IN/AC_PRESENT

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

GPIO_8/EN_CIO_PWR_N_OD

PB_CIO2_TX_P/DPSRC_0_P
PB_CIO2_TX_N/DPSRC_0_N

PB_CONFIG1/CIO_2_LSEO
PB_CONFIG2/CIO_2_LSOE

PB_CIO3_TX_P/DPSRC_2_P
PB_CIO3_TX_N/DPSRC_2_N

PORTS

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

DPSRC_AUX_P
DPSRC_AUX_N

DPSRC_HPD_OD

GPIO_3/FORCE_PWR
GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD
GPIO_7_OD/CIO_SCL_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_RX_P
PB_CIO2_RX_N

PB_CIO3_RX_P
PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO
PB_LSRX/CIO_3_LSOE

PB_DPSRC_1_P
PB_DPSRC_1_N

PB_DPSRC_3_P
PB_DPSRC_3_N

PB_DPSRC_HPD

GPIO_1/PB_HV_EN/BYP0

PETP_0
PETN_0

PETP_1
PETN_1

PETP_2
PETN_2

PETP_3
PETN_3

RSENSE

RBIAS

GPIO_17
GPIO_18
GPIO_19

GPIO_14
GPIO_15

PB_AUX_P
PB_AUX_N

AD5

PCIE_TBT_D2R_C_P<0>

81

AD7

PCIE_TBT_D2R_C_N<0>

81

AD9

PCIE_TBT_D2R_C_P<1>

71 81
81

AD11

PCIE_TBT_D2R_C_N<1>

71

81

AD13

PCIE_TBT_D2R_C_P<2>

71
81

AD15

PCIE_TBT_D2R_C_N<2>

71

81

AD17

PCIE_TBT_D2R_C_P<3>

71
81

AD19

PCIE_TBT_D2R_C_N<3>

71

U20

TBT_RSENSE

W20

TBT_RBIAS

AD1
L8

Used for straps in host mode

W6

TP_TBT_PCIE_RESET0_L

AB3

TBT_DFT_STRAP_1

AD3

TBT_ROM_SECURITY_XOR

V1

TBT_DFT_STRAP_3

V3

TBT_CLKREQ_L

AB21

PCIE_CLK100M_TBT_P

AD21

PCIE_CLK100M_TBT_N

AA24

SYSCLK_CLK25M_TBT_R

74

AB23

TP_TBT_XTAL25OUT

AA4

TBT_TMU_CLK_OUT

A14

TP_DP_TBTSRC_ML_CP<3>

B15

TP_DP_TBTSRC_ML_CN<3>

A12

TP_DP_TBTSRC_ML_CP<2>

B13

TP_DP_TBTSRC_ML_CN<2>

A10

TP_DP_TBTSRC_ML_CP<1>

B11

TP_DP_TBTSRC_ML_CN<1>

A8

TP_DP_TBTSRC_ML_CP<0>

B9

TP_DP_TBTSRC_ML_CN<0>

J4

TP_DP_TBTSRC_AUXCH_CP

J2

TP_DP_TBTSRC_AUXCH_CN

AC2

DP_TBTSRC_HPD

U2

TBT_GPIO2

L6

TBT_PWR_EN

H5

=TBT_WAKE_L

Y7

TBT_CIO_PLUG_EVENT_L

Y1

HDMITBTMUX_SEL_TBT

T7

TBT_GPIO7

V7

TBT_EN_CIO_PWR_L

M7

=TBT_BATLOW_L

T1

TBTDP_AUXIO_EN

T3

TBT_DDC_XBAR_EN_L

R24

TBT_B_R2D_C_P<0>

N24

TBT_B_R2D_C_N<0>

R22

TBT_B_D2R_P<0>

N22

TBT_B_D2R_N<0>

D3

TBT_B_CONFIG1_BUF

M1

TBT_B_CONFIG2_RC

W24

TBT_B_R2D_C_P<1>

U24

TBT_B_R2D_C_N<1>

W22

TBT_B_D2R_P<1>

U22

TBT_B_D2R_N<1>

M5

TBT_B_LSTX

P7

TBT_B_LSRX

A20

DP_TBTPB_ML_C_P<1>

B21

DP_TBTPB_ML_C_N<1>

A22

DP_TBTPB_ML_C_P<3>

B23

DP_TBTPB_ML_C_N<3>

K3

DP_TBTPB_AUXCH_C_P

K1

DP_TBTPB_AUXCH_C_N

N6

DP_TBTPB_HPD

F1

TBT_B_HV_EN
TBT_B_CIO_SEL
TBT_B_DP_PWRDN

C2840
C2841

C2842
C2843

C2844
C2845

C2846
C2847

1

R2855

1K

1%
1/20W
MF
201

2

69

12

OUT

12 71 81

IN

12 71 81

IN

69

69

69

69

69

69

69

69

69

69

69

25

15

IN

39

OUT

18 75

OUT

25 69

IN

25 26

OUT

25 27

IN

25 28 29

OUT

25 30

OUT

29 71 77

OUT

29 71 77

OUT

29 71 77

IN

29 71 77

IN

29

IN

29

IN

29 71 77

OUT

29 71 77

OUT

29 71 77

IN

29 71 77

IN

29

OUT

29

IN

29 77

OUT

29 77

OUT

29 77

OUT

29 77

OUT

BI
BI

29

IN

25 29 30

OUT

29

OUT

25 29

OUT

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

29 77

29 77

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

PCIE_TBT_D2R_P<0>

X5R-CERM

10% 16V

PCIE_TBT_D2R_N<0>

10% 16V

X5R-CERM

PCIE_TBT_D2R_P<1>

X5R-CERM

10% 16V

PCIE_TBT_D2R_N<1>

X5R-CERM

10% 16V

PCIE_TBT_D2R_P<2>

X5R-CERM

10% 16V

PCIE_TBT_D2R_N<2>

10% 16V

X5R-CERM

PCIE_TBT_D2R_P<3>

X5R-CERM

10% 16V

PCIE_TBT_D2R_N<3>

X5R-CERM

16V10%

Security strap setting is XORed with
bit in the flash, so the active-level
depends on the code in the flash.

0201

0201

0201

0201

0201

0201

0201

0201

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

14 71 81

OUT

If strap != bit then security is enabled?

Divides 3.3V to 1.8V

R2895

806

NO STUFF

R2899

10K

5%

1/20W

MF

201

R2878

100K 100K

5%

1/20W

MF

201

1 2

1

1

R2896

1K

5%
1/20W
MF
201

2

2

PP3V3_TBTLC

1

1

R2879

5%
1/20W
MF
201

2

2

NOTE: The following pins require testpoints:
0 - GPIO_13
1 - GPIO_1
2 - GPIO_2
3 - GPIO_3
4 - GPIO_5
5 - PCIE_RST_1_N
6 - PCIE_RST_2_N
7 - PCIE_RST_3_N

SYSCLK_CLK25M_TBT

1%

1/20W

MF

201

25 26

25 30

25 69

25 28 29

25

SYNC_MASTER=T29_RR

PAGE TITLE

TBT_EN_CIO_PWR_L
TBT_DDC_XBAR_EN_L
HDMITBTMUX_SEL_TBT
TBTDP_AUXIO_EN
DP_TBTSRC_HPD

18 25 26 68

25 27

25 28

25 29

25 27 28

25 29 30

Thunderbolt Host (1 of 2)

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=TBT

IV ALL RIGHTS RESERVED

PP3V3_TBTLC

18 25 26 68

PP3V3_TBTLC

18 25 26 68

=PP3V3_S4_TBT

25 26 27 68

=PP3V3_S4_TBT

25 26 27 68

=TBT_BATLOW_L
TBT_A_DP_PWRDN
TBT_B_DP_PWRDN
TBT_A_HV_EN
TBT_B_HV_EN

8 - GPIO_15
9 - GPIO_11
10 - GPIO_14
11 - GPIO_0
12 - GPIO_12
13 - GPIO_10
14 - PB_LSTX
15 - PB_LSRX

Apple Inc.

R

1

R2861

10K

5% 5%
1/20W
MF
201

2

17 74

IN

1

R2881

100K

5%

1/20W

MF

201

2

1

R2884

100K

5%

1/20W

MF

201

2

10K

1/20W

201

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1

5%
MF

2

1 2

10%

1 2

10%

1 2

10%

1 2

10%

1 2

10%

1 2

10%

1 2

10%

1 2

10%

R2815

NOSTUFF

1

R2825

100

5%
1/20W
MF
201

2

13

OUT

R2830

100K

1/20W

67

OUT

R2831

100K

1/20W

201

201

OMIT

NONE
NONE
NONE
0201

5%
MF

5%
MF

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

16V
X5R-CERM

1

2

1

2

1

2

81

PCIE_TBT_R2D_P<0>

71

0201

PCIE_TBT_R2D_N<0>

71 81

0201

81

PCIE_TBT_R2D_P<1>

71

0201

PCIE_TBT_R2D_N<1>

71 81

0201

81

PCIE_TBT_R2D_P<2>

71

0201

PCIE_TBT_R2D_N<2>

71 81

0201

81

PCIE_TBT_R2D_P<3>

71

0201

PCIE_TBT_R2D_N<3>

71 81

0201

TBT_PCIE_RESET_L

18

IN

TBT_PWR_ON_POC_RST_L

26

IN

TP_TBT_MONDC0

69

TP_TBT_MONDC1

69

DEBUG: For monitoring current/voltage

TBT_MONOBSP
TBT_MONOBSN

DEBUG: For monitoring clock

TP_TBT_THERM_DP

45

Use AA8 GND ball for THERM_DN

TBT_SPI_MOSI

77

TBT_SPI_MISO

77

TBT_SPI_CS_L

77

TBT_SPI_CLK

77

JTAG_TBT_TDI

18

IN

JTAG_TBT_TMS

18

IN

JTAG_TBT_TCK

18

IN

JTAG_TBT_TDO

18

OUT

TBT_TEST_EN
TBT_TEST_PWR_GOOD

DP_TBTSNK0_ML_P<3>

25 77

DP_TBTSNK0_ML_N<3>

25 77

DP_TBTSNK0_ML_P<2>

25 77

DP_TBTSNK0_ML_N<2>

25 77

DP_TBTSNK0_ML_P<1>

25 77

DP_TBTSNK0_ML_N<1>

25 77

DP_TBTSNK0_ML_P<0>

25 77

DP_TBTSNK0_ML_N<0>

25 77

DP_TBTSNK0_AUXCH_P

25 77

DP_TBTSNK0_AUXCH_N

25 77

DP_TBTSNK0_HPD

DP_TBTSNK1_ML_P<3>

25 77

DP_TBTSNK1_ML_N<3>

25 77

DP_TBTSNK1_ML_P<2>

25 77

DP_TBTSNK1_ML_N<2>

25 77

DP_TBTSNK1_ML_P<1>

25 77

DP_TBTSNK1_ML_N<1>

25 77

DP_TBTSNK1_ML_P<0>

25 77

DP_TBTSNK1_ML_N<0>

25 77

DP_TBTSNK1_AUXCH_P

25 77

DP_TBTSNK1_AUXCH_N

25 77

DP_TBTSNK1_HPD

TBT_A_R2D_C_P<0>

28 71 77

OUT

TBT_A_R2D_C_N<0>

28 71 77

OUT

TBT_A_D2R_P<0>

28 71 77

IN

TBT_A_D2R_N<0>

28 71 77

IN

TBT_A_CONFIG1_BUF

28

IN

TBT_A_CONFIG2_RC

28

IN

TBT_A_R2D_C_P<1>

28 71 77

OUT

TBT_A_R2D_C_N<1>

28 71 77

OUT

TBT_A_D2R_P<1>

28 71 77

IN

TBT_A_D2R_N<1>

28 71 77

IN

TBT_A_LSTX

28

OUT

TBT_A_LSRX

28

IN

DP_TBTPA_ML_C_P<1>

28 77

OUT

DP_TBTPA_ML_C_N<1>

28 77

OUT

DP_TBTPA_ML_C_P<3>

28 77

OUT

DP_TBTPA_ML_C_N<3>

28 77

OUT

DP_TBTPA_AUXCH_C_P

28 77

BI

DP_TBTPA_AUXCH_C_N

28 77

BI

DP_TBTPA_HPD

28

IN

TBT_A_HV_EN

25 27 28

OUT

TBT_A_CIO_SEL

28

OUT

TBT_A_DP_PWRDN

25 28

OUT

AB9

PERP_0

AA10

PERN_0

AA12

PERP_1

AB13

PERN_1

AB15

PERP_2

AA16

PERN_2

AA18

PERP_3

AB19

PERN_3

P5

PERST_OD_N

R4

PWR_ON_POC_RSTN

AD23

MONDC0

AC24

MONDC1

W18

MONOBSP

W16

MONOBSN

AB7

THERMDA

AA2

EE_DI

Y3

EE_DO

T5

EE_CS_N

U8

EE_CLK

W2

TDI

AB1

TMS

AA6

TCK

U6

TDO

R6

TEST_EN

W8

TEST_PWR_GOOD

E14

DPSNK0_3_P

D13

DPSNK0_3_N

E16

DPSNK0_2_P

D15

DPSNK0_2_N

E18

DPSNK0_1_P

D17

DPSNK0_1_N

E20

DPSNK0_0_P

D19

DPSNK0_0_N

G4

DPSNK0_AUX_P

G2

DPSNK0_AUX_N

AB5

DPSNK0_HPD

E6

DPSNK1_3_P

D5

DPSNK1_3_N

E8

DPSNK1_2_P

D7

DPSNK1_2_N

E10

DPSNK1_1_P

D9

DPSNK1_1_N

E12

DPSNK1_0_P

D11

DPSNK1_0_N

H3

DPSNK1_AUX_P

H1

DPSNK1_AUX_N

U4

DPSNK1_HPD

G24

PA_CIO0_TX_P/DPSRC_0_P

E24

PA_CIO0_TX_N/DPSRC_0_N

G22

PA_CIO0_RX_P

E22

PA_CIO0_RX_N

P1

PA_CONFIG1/CIO_0_LSEO

K5

PA_CONFIG2/CIO_0_LSOE

L24

PA_CIO1_TX_P/DPSRC_2_P

J24

PA_CIO1_TX_N/DPSRC_2_N

L22

PA_CIO1_RX_P

J22

PA_CIO1_RX_N

N8

PA_LSTX/CIO_1_LSEO

J6

PA_LSRX/CIO_1_LSOE

A16

PA_DPSRC_1_P

B17

PA_DPSRC_1_N

A18

PA_DPSRC_3_P

B19

PA_DPSRC_3_N

L4

PA_AUX_P

L2

PA_AUX_N

M3

PA_DPSRC_HPD

R8

GPIO_0/PA_HV_EN/BYP0

N2 R2

GPIO_10/PA_CIO_SEL/BYP1

P3 F3

GPIO_12/PA_DP_PWRDN/BYP2

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

PCIE_TBT_R2D_C_P<0>

14 71 81

IN

PCIE_TBT_R2D_C_N<0>

14 71 81

IN

PCIE_TBT_R2D_C_P<1>

14 71 81

IN

PCIE_TBT_R2D_C_N<1>

14 71 81

IN

PCIE_TBT_R2D_C_P<2>

14 71 81

D

BYPASS=U2890::2mm

1

201

1

R2891

3.3K

5%

5%
1/20W

MF

MF
201

2

2

R2890

3.3K

1/20W

(TBT_SPI_CLK)
(TBT_SPI_CS_L)

TBTROM_WP_L

C

TBTROM_HOLD_L

C2890

1UF

10%

6.3V
CERM

402

1

2

5 2

6

1

3

DI/IO0

U2890

CLK

4MBIT

W25X40CLXIG

CS*

WP*

HOLD*

GND

479

8

VCC

DO/IO1

USON

THRM_PAD

CRITICAL
OMIT_TABLE

IN

PCIE_TBT_R2D_C_N<2>

14 71 81

IN

PCIE_TBT_R2D_C_P<3>

14 71 81

IN

PCIE_TBT_R2D_C_N<3>

14 71 81

IN

(TBT_SPI_MISO)(TBT_SPI_MOSI)

R2892

3.3K

1/20W

201

18 25 26 68

1

5%
MF

2

C2800
C2801

C2802
C2803

C2804
C2805

C2806
C2807

PP3V3_TBTLC

1

R2893

3.3K

5%
1/20W
MF
201

2

R2829

SNK0 AC Coupling

DP_TBTSNK0_ML_C_P<0>

5

77

IN

DP_TBTSNK0_ML_C_N<0>

5

77

IN

DP_TBTSNK0_ML_C_P<1>

5

77

IN

DP_TBTSNK0_ML_C_N<1>

5

77

IN

B

DP_TBTSNK0_ML_C_P<2>

5

77

IN

DP_TBTSNK0_ML_C_N<2>

5

77

IN

DP_TBTSNK0_ML_C_P<3>

5

77

IN

DP_TBTSNK0_ML_C_N<3>

5

77

IN

DP_TBTSNK0_AUXCH_C_P

13 77

BI

DP_TBTSNK0_AUXCH_C_N

13 77

BI

C2820
C2821

C2822
C2823

C2824
C2825

C2826
C2827

C2828
C2829

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

DP_TBTSNK0_ML_P<0>

10% 16V

0201

X5R-CERM

DP_TBTSNK0_ML_N<0>

10% 16V

0201

X5R-CERM

DP_TBTSNK0_ML_P<1>

16V10%

0201

X5R-CERM

DP_TBTSNK0_ML_N<1>

10% 16V

0201

X5R-CERM

DP_TBTSNK0_ML_P<2>

16V10%

0201

X5R-CERM

DP_TBTSNK0_ML_N<2>

10% 16V

0201

X5R-CERM

DP_TBTSNK0_ML_P<3>

16V10%

0201

X5R-CERM

DP_TBTSNK0_ML_N<3>

10% 16V

0201

X5R-CERM

DP_TBTSNK0_AUXCH_P

16V10%

0201

X5R-CERM

DP_TBTSNK0_AUXCH_N

10% 16V

0201

X5R-CERM

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

SNK1 AC Coupling

DP_TBTSNK1_ML_C_P<0>

67 77

IN

DP_TBTSNK1_ML_C_N<0>

67 77

IN

DP_TBTSNK1_ML_C_P<1>

67 77

IN

DP_TBTSNK1_ML_C_N<1>

67 77

IN

DP_TBTSNK1_ML_C_P<2>

67 77

A

IN

DP_TBTSNK1_ML_C_N<2>

67 77

IN

DP_TBTSNK1_ML_C_P<3>

67 77

IN

DP_TBTSNK1_ML_C_N<3>

67 77

IN

DP_TBTSNK1_AUXCH_C_P

67 77

BI

DP_TBTSNK1_AUXCH_C_N

67 77

BI

C2830
C2831

C2832
C2833

C2834
C2835

C2836
C2837

C2838
C2839

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

DP_TBTSNK1_ML_P<0>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_N<0>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_P<1>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_N<1>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_P<2>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_N<2>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_P<3>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_ML_N<3>

10% 16V

0201

X5R-CERM

DP_TBTSNK1_AUXCH_P

10% 16V

0201

X5R-CERM

DP_TBTSNK1_AUXCH_N

10% 16V

0201

X5R-CERM

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

25 77

6 3

12

NO STUFF

1

R2867

10K

5%
1/20W
MF
201

2

1

5%
MF

201

2

1

5%
MF

201

2

1

10K

5%
MF

201

2

1

10K

5% 5%
MF

201

2

1

R2863

10K

2

1

R2882

100K

2

1

R2883

100K

2

NO STUFF

1

R2886

10K

2

1

R2887

10K

2

1

R2862

10K

5%
1/20W
MF
201

2

R2880

100K

1/20W

R2832

100K

1/20W

NO STUFF

R2885

1/20W

R2888

1/20W

SYNC_DATE=01/19/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

28 OF 120

SHEET

25 OF 82

124578

1/20W
MF
201

5%
1/20W
MF
201

5%
1/20W
MF
201

5%
1/20W
MF
201

1/20W
MF
201

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

1

C290A

12PF

5%
25V

2

NP0-C0G
0201

1

C290B

3.0PF

+/-0.1PF
25V

2

NP0-C0G
0201

1

C290C

1.0UF

20%

6.3V

2

X5R
0201-1

1

C290D

12PF

5%
25V

2

NP0-C0G
0201

D

1

C2900

1.0UF

20%

6.3V
2

X5R

0201-1

PP1V05_TBT

26

MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=1.05V

C2901

3.0PF

+/-0.1PF

25V

NP0-C0G

0201

1

2

C2902

1.0UF

20%

6.3V
X5R

0201-1

1

2

C2903

1.0UF

20%

6.3V
X5R

0201-1

1

2

C

1900 mA EDP

C2923

10UF

20%

6.3V

CERM-X5R

0402-1

OMIT_TABLE

1

2

OMIT_TABLE

C2922

10UF

20%

6.3V

CERM-X5R

0402-1

1

C2921

10UF

2

CERM-X5R

0402-1

OMIT_TABLE

20%

6.3V

C2904

1.0UF

20%

6.3V
X5R

0201-1

1

C2920

2

CERM-X5R

OMIT_TABLE

1

2

C291A

10UF

20%

6.3V

0402-1

C2905

12PF

NP0-C0G

0201

1

20%

6.3V
2

X5R

1

C291B

12PF

2

NP0-C0G

CRITICAL

L2920

1 2

CRITICAL

C2906

5%

25V

0201

SM

D2920

1.0UF

0201-1

5%

25V

680NH-30%-3.6A-35MOHM

1

2

NSR1020MW2T1G

B

A

PART NUMBER

QTY

8

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

DESCRIPTION

CAP,CER,10UF,20%,6.3V,HRZTL,0402

REFERENCE DES

CRITICAL

CRITICAL138S0801

1.0UF

20%

6.3V
X5R

0201-1

1

2

SOD-323

U2950

Part

Type

R(on)
@ 1.05V

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

1

1200 mA EDP

2

18 25 26 68

1

C2981

1.0UF

20%

6.3V

2

X5R
0201-1

R2995

100K

1/20W

TPS22920

Load Switch

8 mOhm Typ

11.5 mOhm Max

1

5%
MF

201

2

PP1V05_TBTRDV

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=1.05V

1

700 mA EDP

2

1

C2910

1.0UF

0201-1

K

A

C2911

20%

6.3V
2

X5R

P1V05TBT_SW

MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM

DIDT=TRUE
SWITCH_NODE=TRUE

1.0UF

6.3V

0201-1

20%
X5R

CRITICAL

G10
G12
G14
G16
G18
H19

H9
J18
K15
K17
K19

K7

VCC1P0_RDV_DECAP

L16
M19
P19
T19
U18
V15
V17
W12
W14

J8

1

2

K9
L14
M15

SVR_VCC1P0

M17
P17
V19

A4

A6

SVR_IND

B3

B5

SVR_AMON

NC

A2
A24

AA14
AA20
AA22

AA8 J14

AB11
AB17
AC10
AC12
AC14
AC16
AC18
AC20
AC22

AC4
AC6
AC8

B1

B7

VSS

C10
C12
C14
C16
C18

C2
C20
C22
C24

C4

C6

C8
D21
D23

E4
F11
F13
F15
F17
F19
F21
F23

F5

F7

F9

OMIT_TABLE

U2800

FALCON RIDGE

FCBGA

SYM 2 OF 2

VCC

VCC3P3_RDV_DECAP

GND

1

0201

VSS

25V

2

J10
J12
K11
L10
M11
N10
N14
P11
P15
R10
R14
T11
T15
U10
U14
V11

D1
E2
H11
N4
V5
W4

Y5

H13
H15
H17
H7
L18
N18
R18
W10

G20
G6
G8
H21
H23

J16
J20
K13
K21
K23
L12
L20
M13
M21
M23
M9
N12
N16
N20
P13
P21
P23
P9
R12
R16
R20
T13
T17
T21
T23
T9
U12
U16
V13
V21
V23
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y9

C291D

C291C

3.0PF

+/-0.1PF

NP0-C0G NP0-C0G

VCC1P0_CIO

VCC3P3

VCC3P3_LC

1

12PF

5%

25V

2

NP0-C0G

0201

C2930

1.0UF

20%

6.3V
X5R

0201-1

SVR input to RR - 1100 mA EDP

POC input to RR - 150 mA EDP

Isolated to reduce noise from SVR

C2970

1.0UF

20%

6.3V
X5R

0201-1

PP3V3_TBTRDV

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

25 mA EDP

C291E

1

12PF

5%

25V

2

0201

1

C2931

1.0UF

20%

6.3V

2

X5R

0201-1

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

100 mA EDP

1

2

17 27 38 39 75

12 13 15 18 26 65 68

15

Max Current = 4A (85C)

1

C2932

1.0UF

20%

6.3V

2

X5R

0201-1

1

C2980

1.0UF

20%

6.3V

2

X5R
0201-1

SMC_DELAYED_PWRGD

IN

=PP3V3_S0_PCH_GPIO

TBT_POC_RESET_L

IN

BOM OPTION

C2920,C2921,C2922,C2923,C2950,C2951,C2952,C2953

6 3

C2950

10UF

CERM-X5R

0402-1

OMIT_TABLE

C2960

1.0UF

0201-1

=PP3V3_S4_TBT

25 26 27 68

Q2995

DMN32D2LFB4

DFN1006H4-3

1

S G

2

1.05V TBT "CIO" Switch

Internal switch not functional on RR.

U2940

TPS22920

CSP

A2
B2

VIN

C2

D2

ON

GND

D1

=PP3V3_S0_PCH_GPIO

TBT_PWR_REQ_L

13

OUT

Pull-up (S0) on PCH page

1

C2952

2

10UF

CERM-X5R

0402-1

20%

6.3V

OMIT_TABLE

PP3V3_S4_TBT_F

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

1

20%

6.3V
2

X5R

20%

6.3V

20%

6.3V
X5R

A1
B1

VOUT

C1

CRITICAL

12 13 15 18 26 65 68

1

C2951

10UF

2

CERM-X5R

0402-1

OMIT_TABLE

1

C2961

1.0UF

2

0201-1

TBT "POC" Power-up Reset

1

R2990

100K

5%

SYM_VER_3

C2995

330PF

10%
16V
X7R

0201

3

2

D

1

R2991

1

24.9K

2

2

Vth = 2.508V nominal

1/20W
MF
201

TBTPOCRST_MR_L
TBTPOCRST_SENSE

1%
1/20W
MF
201

BOM_COST_GROUP=TBT

PP1V05_TBT

TBT_EN_CIO_PWR

1

C2940

1.0UF

20%

6.3V

2

X5R
0201-1

1

C2953

20%

6.3V

2

CERM-X5R

0402-1

OMIT_TABLE

1

R2992

100K

5%

1/20W

MF

201

2

26

PP3V3_TBTLC

1

R2945

100K

5%
1/20W
MF
201

2

Q2945

6

D

DMN5L06VK-7

SOT563

VER 3

2

S G

1

5

VER 3

SOT563

S G

4

1

10UF

20%

6.3V

2

C292A

3.0PF

+/-0.1PF

NP0-C0G

CRITICAL

1

ENABLE SENSE_OUT

3

SENSE

D

3

Q2945

DMN5L06VK-7

=PP3V3_S4_TBT

3.1 W (Dual-Port)

2.4 W (Single-Port)
EDP: 1.25 A

PLACE_NEAR=C2953.1:1mm

2

XW2960

SM

1

1

25V

2

0201

6

VCC

U2990

TPS3895ADRY

USON

GND

2

SYNC_MASTER=T29_RR

PAGE TITLE

TBT_EN_CIO_PWR_L

C292B

12PF

5%

25V

NP0-C0G

0201

4

5

CT

Thunderbolt Host (2 of 2)

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

18 25 26 68

25 26 27 68

=PP3V3_S4_TBT

1

2

1

C2990

0.1UF

10%
25V

2

X5R
402

Push-pull output

TBT_PWR_ON_POC_RST_L
TBTPOCRST_CT

Delay = 4.04ms nominal

Apple Inc.

IN

0.001UF

25

25 26 27 68

C2991

X7R-CERM

0402

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

10%
50V

051-1573

25

OUT

1

2

SYNC_DATE=12/17/2012

8.0.0
dvt1

29 OF 120

26 OF 82

SIZE

D

C

B

A

D

8 7 6 5 4 3

Page Notes

Power aliases required by this page:

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP15V_TBT_REG (15V Boost Output)

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
(NONE)

12

D

=PPVIN_SW_TBTBST

27 68

1

C3000

12PF

5%
25V

2

NP0-C0G
0201

CRITICAL

Q3080

=PPVIN_SW_TBTBST

27 68

8-13V Input
Changes required
for 2S.

C

1

R3080

470K

1/16W
MF-LF

R3081

330K

1/16W
MF-LF

5%

402

2

1

5%

402

2

TBTBST_PWREN_L

30

1

2

DMN32D2LFB4

TBT_A_HV_EN

25 28

IN

Second FET needed for
dual-port designs.

C3080

0.1UF

10%
25V
X5R
402

TBTBST_PWREN_DIV_L

1

D

G S

Q3005

DFN1006H4-3

SYM_VER_2

SI8409DB

SGD

4

1

3

C3085

2.2UF

X5R-CERM

2

1

R3092

73.2K

1%
1/16W
MF-LF
402

2

<R2>

UVLO(falling) = 1.22 * (R1 + R2) / R2
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)

B

SI8409DB:
Vds(max): -30V
Vgs(max): +/-12V
Vgs(th): -1.4V
Rds(on): 46mOhm @ 4.5V Vgs
Id(max): 3.7A @ 70C

BGA

2 3

1

1

20%
10V

2

402

2

PPVIN_SW_TBTBST

68

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

Voltage not specified here,
add property on another page.

20%
10V

402

1

2

1

2

C3086

2.2UF

20%
10V
X5R-CERM
402

C3092

2.2UF

X5R-CERM

C3087

68PF

5%
50V
CERM
0402

TBTBST_VC_RC

1

C3093

0.0033UF

10%
50V

2

X7R-CERM
0402

R3091

R3093

49.9K

1/16W
MF-LF

402

R3094

26.7K

200K

1/16W
MF-LF

402

<R1>

1

1%

2

1/16W
MF-LF

402

Thunderbolt 15V Boost Regulator

CRITICAL

L3095

3.3UH-6.5A

1 2

1

C3090

10UF

20%
25V

2

X5R-CERM

1

1%

2

0603

TBTBST_EN_UVLO

TBTBST_INTVCC

TBTBST_VC

TBTBST_RT

TBTBST_SS

1

1

C3094

1%

2

0.33UF

10%

6.3V

2

CERM-X5R
402

GND_TBTBST_SGND

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

Q3088

6

D

DMN5L06VK-7

SOT563

VER 3

Max Vgs: 10V

2

S G

1

TBTBST_SHDN_DIV

1

R3087

330K

5%
1/16W
MF-LF
402

2

C3091

10UF

X5R-CERM

0603

20%
25V

1

2

25

EN/UVLO

28

INTVCC

30

VC

33

RT

32

SS

34

SYNC

1

R3088

330K

5%
1/16W
MF-LF
402

2

Q3088

3

D

DMN5L06VK-7

SOT563

VER 3

S G

4

PIMB063T-SM

CRITICAL

U3090

LT3957

QFN

1213141516

37

8

27

VIN

SGND

42324

SGND shorted to
GND inside package,
no XW necessary.

5

SMC_DELAYED_PWRGD

TBTBST_BOOST

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE
DIDT=TRUE

9

202138

SW

SNS1

SNS2

NC

FBX

GND

17

TBTBST_SNS1

R3089

5%

1/20W

MF

6

3

1
2
10

NC

35
36

31

TBTBST_SNS2

TBTBST_VSNS

1

C3088

10PF

5%
50V

2

CERM
0402

TBTBST_FBX

NO STUFF

1

C3089

100PF

5%
50V

2

CERM
402

Vout = 1.6V * (1 + Ra / Rb)

17 26 38 39 75

IN

0201

XW3095

R3095

R3096

15.8K

1

0

2

137K

1/16W
MF-LF

<Ra>

1/16W
MF-LF

<Rb>

SM

1%

402

1%

402

1

3

12

PLACE_NEAR=C3095.1:2 mm

1

2

1

2

1

2

2

CRITICAL

D3095

PDS540XF

PWRDI5

C3095

33UF-0.06OHM

20%
25V
POLY-TANT
CASE-D3L

C3096

10UF

1206-2

=PP15V_TBT_REG

Vout = 15.47V
Max Current = 2A?
FREQ = 480KHZ

1

1

10%
25V

2

X5R

2

NO STUFF

C3097

10UF

10%
25V
X5R
805

68

1

C3099

0.001UF

10%
50V

2

X7R-CERM
0402

1

C3001

12PF

5%
25V

2

NP0-C0G
0201

1

C3002

12PF

5%
25V

2

NP0-C0G
0201

D

C

B

BATLOW# Isolation

Q3000

A

13 38

IN

DMN32D2LFB4

PM_BATLOW_L

DFN1006H4-3

SYM_VER_3

D

3

=PP3V3_S4_TBT

1

S G

2

Pull-up on RR page

=TBT_BATLOW_L
TBT_BATLOW_L

MAKE_BASE=TRUE

6 3

25 26 68

SIZE

A

D

SYNC_MASTER=T29_RR

PAGE TITLE

25

OUT

BOM_COST_GROUP=TBT

Thunderbolt Mobile Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/19/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

30 OF 120

SHEET

27 OF 82

124578

8 7 6 5 4 3

V3P3 must be S4 to support
wake from Thunderbolt devices.

=PP3V3_S4_TBTAPWRSW

68

CRITICAL

POLY-TANT

D

C

CASE-B2-SM

For 12V systems:

PART NUMBER

Nominal Min Max
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

B

1

C3287

100UF

68

15.75V Max

C3280

20%

6.3V

2

X5R-CERM-1

=PPHV_S4SW_TBTAPWRSW

C3215

4.7UF

10%
25V

X5R-CERM

0603

64

25 27

29 64

118S0145
118S0145

25 71 77

OUT

25 71 77

OUT

25 77

IN

25 77

IN

22UF

IN

IN

IN

QTY

2
2

TBT_A_D2R_P<0>
TBT_A_D2R_N<0>

DP_TBTPA_ML_C_P<3>
DP_TBTPA_ML_C_N<3>

A

3.3V/HV Power MUX

1

1

C3281

0.1UF

20%

6.3V
603

1

2

=TBTAPWRSW_EN
TBT_A_HV_EN
=TBT_S0_EN

10%
16V

2

2

X5R-CERM
0201

1

C3210

0.1UF

10%
25V

2

X5R
402

DESCRIPTION

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

Nominal Min Max
IV3P3 1100mA 1030mA 1200mA
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19

V3P3

20

6

VHV

7

CRITICAL

U3210

CD3211A1RGP

16 4

11 10

17

QFN

ENHVU

5

EN

HV_EN

S0

123

ISET_V3P3

GND

13

TBTHV:P15V

R3213

22.6K

1/20W

18

V3P3OUT

12

OUT

14

C3285

X5R-CERM

FAULTZ

8

ISET_S0

9

ISET_S3

THRM

PAD

21

15

71

TBTHV:P15V

1

1

R3214

22.6K

1%

1%

1/20W
MF

MF

201

201

2

2

<RHVS0><RHVS3>

REFERENCE DES

1

1

C3286

0.1UF

10%
16V

0201

TBTAPWRSW_ISET_V3P3

71

TBTAPWRSW_ISET_S0

71

TBTAPWRSW_ISET_S3

71

12V: See
below

TBTAPWRSW_ISET_S3_R
TBTAPWRSW_ISET_S0_R

10UF

20%

6.3V

2

2

CERM-X5R
0402

Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.

ILIM = 40000 / RISET

CRITICAL

R3210

22.6K

1/20W

201

1

2

1%
MF

R3210,R3213
R3211,R3214

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3274
C3275

C3278
C3279

1 2

0.47UF

1 2

0.47UF

1 2

0.22UF

1 2

0.22UF

TBT_A_HPD

28

TBT_A_CONFIG1_RC

28

TBT_A_CONFIG2_RC

25

OUT

CERM-X5R-1

CERM-X5R-1

20%

6.3V

X5R

0201

20%

6.3V

X5R

0201

20120% 4V

20120% 4V

R3252

1/20W

201

71 77

71 77

77

77

1

1M

5%
MF

2

TBT_A_D2R_C_P<0>
TBT_A_D2R_C_N<0>

DP_TBTPA_ML_P<3>
DP_TBTPA_ML_N<3>

1

R3251

1M

5%
1/20W
MF
201

2

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

C3294

PP3V3_S4_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

PP3V3RHV_S4_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

C3211

0.1UF

10%
25V
X5R
402

TBTHV:P15VTBTHV:P15V

1

1

R3211

22.6K

1%
1/20W
MF
201

2

2

28

1

R3212

36.5K

1%
1/20W
MF
201

2

<RV3P3>

TBT_A_D2R_N<1>

25 71 77

OUT

TBT_A_D2R_P<1>

25 71 77

OUT

DP_TBTPA_AUXCH_C_N

25 77

BI

DP_TBTPA_AUXCH_C_P

25 77

BI

DP_TBTPA_ML_C_P<1>

25 77

IN

DP_TBTPA_ML_C_N<1>

25 77

IN

C3277

0.47UF

C3276

0.47UF

C3230

0.1UF

C3231

0.1UF

C3232

0.22UF

C3233

0.22UF

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

1 2

1 2

1 2

1 2

1 2

1 2

CERM-X5R-1

CERM-X5R-1

10% 16V
X5R-CERM

0201

10% 16V
X5R-CERM

0201

20%

6.3V

X5R

0201

20%

6.3V

X5R

0201

20120% 4V

20120% 4V

30

30

25

77

77

25

25

25

BOM OPTION

TBTHV:P12V
TBTHV:P12V

R3294

1K

5%

1/20W

MF

201

330PF

10%
16V
X7R

0201

C3260

NP0-C0G

1

2

1

2

1

12PF

5%

25V

2

0201

GND_VOID=TRUE

1

R3295

1K

5%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

1

R3279

470K

5%

1/20W

MF

201

2

28 77

28 77

1

C3295

330PF

10%
16V

2

X7R
0201

C3200

0.01UF

10%
50V

X7R-CERM

0402

1

R3278

470K

5%
1/20W
MF
201

2

TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N

1

R3241

100K

5%
1/20W
MF
201

2

CRITICAL

L3200

FERR-120-OHM-3A

1 2

1

C3201

0.01UF

10%
50V

2

X7R-CERM
0402

1

C3202

0.01UF

10%
16V

2

X5R-CERM
0201

0603

1

2

PP3V3RHV_S4_TBTAPWR_F

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

TBTACONN_20_RC

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

TBT Dir

TBT: RX_0

TBT: Unused

TBT: RX_1

DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).

Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V

DP Dir

Thunderbolt Connector A

R3201

12

1 2

5%

1/20W

MF

201

B10
B12

B16
B18
B20

B2
B4
B6

CRITICAL

SHIELD PINS

J3200

MDP-J44

HPD
CONFIG1
CONFIG2
GND2
ML_LANE3P
ML_LANE3N
GND4
AUX_CHP
AUX_CHN
DP_PWR

PORT B

SHIELD PINS

S22

S24

514-0876

S15

S16

F-RT-TH

S20

S21

S12

S13

S14

GND0
ML_LANE0P
ML_LANE0N

GND1
ML_LANE1P
ML_LANE1N

GND3
ML_LANE2P
ML_LANE2N

RETURN

S17

S18

S19

B1
B3
B5
B7B8
B9
B11
B13B14
B15
B17
B19

6 3

PP3V3_S4_TBTAPWR

28

TBT_A_D2R_C_N<1>

71 77

TBT_A_D2R_C_P<1>

71 77

DP_TBTPA_AUXCH_N

77

DP_TBTPA_AUXCH_P

77

DP_TBTPA_DDC_DATA

BI

DP_TBTPA_DDC_CLK

IN

TBT_A_CONFIG1_BUF

OUT

DP_TBTPA_ML_P<1>
DP_TBTPA_ML_N<1>

TBT_A_LSTX

IN

TBT_A_LSRX

OUT

DP_TBTPA_HPD

OUT

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

DP Dir

TBTACONN_7_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

TBT Dir

TBT: TX_0

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

C3220

0.1UF

10%
16V

X5R-CERM

0201

(0-18.9V)

TBT_A_R2D_P<0>

71 77

TBT_A_R2D_N<0>

71 77

(0-18.9V)

TBT_A_R2D_P<1>

71 77

TBT_A_R2D_N<1>

71 77

BOM_COST_GROUP=TBT

1

2

GND_VOID=TRUE

GND_VOID=TRUE

TB-

8

TB+

1

AUX-

2

AUX+

4

DDC_DAT

5

DDC_CLK

CA_DETOUT

11

DP+

10

DP-

14

LSTX

13

LSRX

HPDOUT

C3205

0.01UF

10%
25V

X5R-CERM

0201

C3206

0.01UF

10%
25V

X5R-CERM

0201

3

SIGNAL_MODEL=TBT_MUX

VDD

CRITICAL

U3220

CBTL05024

HVQFN24-COMBO

AUXIO_EN

(IPU)

(IPD)

(IPU)
(IPD)

THMPAD

GND

9

21

1

2

1

2

157

TB_ENA

DP_PD

AUXIO­AUXIO+

CA_DET

DPMLO+
DPMLO-

25

GND_VOID=TRUE

1

R3270

2

GND_VOID=TRUE

1

R3272

2

470k R’s for ESD protection
on AC-coupled signals.

SYNC_MASTER=T29_RR

PAGE TITLE

TBT_A_CIO_SEL

24

TBTDP_AUXIO_EN

6

TBT_A_DP_PWRDN

23

TBT_A_D2R1_AUXDDC_N

22

TBT_A_D2R1_AUXDDC_P

TBT: RX_1

1816

TBT_A_CONFIG1_RC

19

DP_A_LSX_ML_P<1>

20

DP_A_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

1712

TBT_A_HPD

HPD

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3270

0.22UF

C3271

0.22UF

470K

5%
1/20W
MF
201

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3272

0.22UF

C3273

0.22UF

470K

5%
1/20W
MF
201

1 2

1 2

GND_VOID=TRUE

1

R3271

470K

5%
1/20W
MF
201

2

1 2

1 2

GND_VOID=TRUE

1

R3273

470K

5%
1/20W
MF
201

2

20%
X5R

20%
X5R

20%
X5R

20%
X5R

TBT_A_R2D_C_P<0>

6.3V
0201

TBT_A_R2D_C_N<0>

6.3V
0201

DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

TBT_A_R2D_C_P<1>

6.3V
0201

TBT_A_R2D_C_N<1>

6.3V
0201

Thunderbolt Connector A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

28 77

28 77

28

28 77

28 77

28

IN
IN
IN

12

25

25 29

25

SYNC_DATE=10/26/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

PAGE

32 OF 120

SHEET

28 OF 82

124578

IN
IN

28 77

28 77

IN
IN

dvt1

25 71 77

25 71 77

25 71 77

25 71 77

SIZE

D

C

B

A

D

8 7 6 5 4 3

V3P3 must be S4 to support
wake from Thunderbolt devices.

=PP3V3_S4_TBTBPWRSW

68

CRITICAL

POLY-TANT

D

C

CASE-B2-SM

For 12V systems:

PART NUMBER

Nominal Min Max
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

B

1

C3387

100UF

68

15.75V Max

C3380

20%

6.3V

2

X5R-CERM-1

=PPHV_S4SW_TBTBPWRSW

C3315

4.7UF

10%
25V

X5R-CERM

0603

64

25 30

28 64

118S0145
118S0145

25 71 77

OUT

25 71 77

OUT

25 77

IN

25 77

IN

22UF

IN

IN

IN

QTY

2
2

TBT_B_D2R_P<0>
TBT_B_D2R_N<0>

DP_TBTPB_ML_C_P<3>
DP_TBTPB_ML_C_N<3>

A

3.3V/HV Power MUX

1

1

C3381

0.1UF

20%

6.3V
603

1

2

=TBTBPWRSW_EN
TBT_B_HV_EN
=TBT_S0_EN

10%
16V

2

2

X5R-CERM
0201

1

C3310

0.1UF

10%
25V

2

X5R
402

DESCRIPTION

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

Nominal Min Max
IV3P3 1100mA 1030mA 1200mA
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19

V3P3

20

6

VHV

7

CRITICAL

U3310

CD3211A1RGP

16 4

11 10

17

QFN

ENHVU

5

EN

HV_EN

S0

123

ISET_V3P3

GND

13

TBTHV:P15V

R3313

22.6K

1/20W

<RHVS3> <RHVS0>

18

V3P3OUT

12

OUT

14

C3385

X5R-CERM

FAULTZ

8

ISET_S0

9

ISET_S3

THRM

PAD

21

15

71

TBTHV:P15V

1

1

R3314

22.6K

1%

1%

1/20W
MF

MF

201

201

2

2

REFERENCE DES

1

1

C3386

0.1UF

10%
16V

0201

TBTBPWRSW_ISET_V3P3

71

10UF

20%

6.3V

2

2

CERM-X5R
0402

TBTBPWRSW_ISET_S0
TBTBPWRSW_ISET_S3

71

12V: See
below

TBTBPWRSW_ISET_S3_R
TBTBPWRSW_ISET_S0_R

TBTHV:P15V

Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.

ILIM = 40000 / RISET

CRITICAL

R3310

22.6K

1/20W

201

1

2

1%
MF

R3310,R3313
R3311,R3314

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3374
C3375

C3378
C3379

1 2

0.47UF

1 2

0.47UF

1 2

0.22UF

1 2

0.22UF

TBT_B_HPD

29

TBT_B_CONFIG1_RC

29

TBT_B_CONFIG2_RC

25

OUT

4V20% 201

CERM-X5R-1

4V20% 201

CERM-X5R-1

6.3V

20%

0201

X5R

6.3V

20%

0201

X5R

R3352

1/20W

201

TBT_B_D2R_C_P<0>

71 77

TBT_B_D2R_C_N<0>

71 77

DP_TBTPB_ML_P<3>

77

DP_TBTPB_ML_N<3>

77

1

1

R3351

1M

1M

5%

5%
1/20W

MF

MF
201

2

2

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

C3394

PP3V3_S4_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

PP3V3RHV_S4_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

C3311

0.1UF

10%
25V
X5R
402

TBTHV:P15V

1

1

R3311

22.6K

1%
1/20W
MF
201

2

2

29

1

R3312

36.5K

1%
1/20W
MF
201

2

<RV3P3>

TBT_B_D2R_N<1>

25 71 77

OUT

TBT_B_D2R_P<1>

25 71 77

OUT

DP_TBTPB_AUXCH_C_N

25 77

BI

DP_TBTPB_AUXCH_C_P

25 77

BI

DP_TBTPB_ML_C_P<1>

25 77

IN

DP_TBTPB_ML_C_N<1>

25 77

IN

C3377

0.47UF

C3376

0.47UF

C3330

0.1UF

C3331

0.1UF

C3332

0.22UF

C3333

0.22UF

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

1 2

1 2

1 2

1 2

1 2

1 2

4V20% 201

CERM-X5R-1

4V20% 201

CERM-X5R-1

16V10%

X5R-CERM

0201
16V10%

X5R-CERM

0201

6.3V

20%

0201

X5R

6.3V

20%

0201

X5R

30

30

25

77

77

25

25

25

BOM OPTION

TBTHV:P12V
TBTHV:P12V

R3394

1K

5%

1/20W

MF

201

330PF

10%
16V
X7R

0201

C3360

NP0-C0G

1

2

1

2

1

12PF

5%

25V

2

0201

GND_VOID=TRUE

1

R3395

1K

5%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

1

R3379

470K

5%

1/20W

MF

201

2

29 77

29 77

1

C3395

330PF

10%
16V

2

X7R
0201

C3300

0.01UF

10%
50V

X7R-CERM

0402

1

R3378

470K

5%
1/20W
MF
201

2

TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N

1

R3341

100K

5%
1/20W
MF
201

2

CRITICAL

L3300

FERR-120-OHM-3A

1 2

1

C3301

0.01UF

10%
50V

2

X7R-CERM
0402

1

C3302

0.01UF

10%
16V

2

X5R-CERM
0201

0603

1

2

PP3V3RHV_S4_TBTBPWR_F

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

TBTBCONN_20_RC

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

TBT Dir

TBT: RX_0

TBT: Unused

TBT: RX_1

DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).

Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V

DP Dir

Thunderbolt Connector B

R3301

12

1 2

5%

1/20W

MF

201

A10
A12

A16
A18
A20

A2
A4
A6

SHIELD PINS

J3200

MDP-J44

HPD
CONFIG1
CONFIG2
GND2
ML_LANE3P
ML_LANE3N
GND4
AUX_CHP
AUX_CHN
DP_PWR

PORT A

SHIELD PINS

S11S2S23

514-0876

CRITICAL

S4

S5

F-RT-TH

S9

S10

S1

S3

GND0
ML_LANE0P
ML_LANE0N

GND1
ML_LANE1P
ML_LANE1N

GND3
ML_LANE2P
ML_LANE2N

RETURN

S6S7S8

A1
A3
A5
A7A8
A9
A11
A13A14
A15
A17
A19

6 3

PP3V3_S4_TBTBPWR

29

TBT_B_D2R_C_N<1>

71 77

TBT_B_D2R_C_P<1>

71 77

DP_TBTPB_AUXCH_N

77

DP_TBTPB_AUXCH_P

77

DP_TBTPB_DDC_DATA

BI

DP_TBTPB_DDC_CLK

IN

TBT_B_CONFIG1_BUF

OUT

DP_TBTPB_ML_P<1>
DP_TBTPB_ML_N<1>

TBT_B_LSTX

IN

TBT_B_LSRX

OUT

DP_TBTPB_HPD

OUT

TBTBCONN_1_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

DP Dir

TBTBCONN_7_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

TBT Dir

TBT: TX_0

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

C3320

0.1UF

10%
16V

X5R-CERM

0201

(0-18.9V)

TBT_B_R2D_P<0>

71 77

TBT_B_R2D_N<0>

71 77

(0-18.9V)

TBT_B_R2D_P<1>

71 77

TBT_B_R2D_N<1>

71 77

BOM_COST_GROUP=TBT

1

2

GND_VOID=TRUE

GND_VOID=TRUE

TB-

8

TB+

1

AUX-

2

AUX+

4

DDC_DAT

5

DDC_CLK

CA_DETOUT

11

DP+

10

DP-

14

LSTX

13

LSRX

HPDOUT

C3305

0.01UF

10%
25V

X5R-CERM

0201

C3306

0.01UF

10%
25V

X5R-CERM

0201

3

SIGNAL_MODEL=TBT_MUX

VDD

CRITICAL

U3320

CBTL05024

HVQFN24-COMBO

AUXIO_EN

(IPU)

(IPD)

(IPU)
(IPD)

THMPAD

GND
9

21

1

2

1

2

157

TB_ENA

DP_PD

AUXIO­AUXIO+

CA_DET

DPMLO+
DPMLO-

25

GND_VOID=TRUE

1

R3370

2

GND_VOID=TRUE

1

R3372

2

470k R’s for ESD protection
on AC-coupled signals.

SYNC_MASTER=T29_RR

PAGE TITLE

TBT_B_CIO_SEL

TBTDP_AUXIO_EN

24
6

TBT_B_DP_PWRDN

23

TBT_B_D2R1_AUXDDC_N

22

TBT_B_D2R1_AUXDDC_P

TBT: RX_1

1816

TBT_B_CONFIG1_RC

19

DP_B_LSX_ML_P<1>

20

DP_B_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

1712

TBT_B_HPD

HPD

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3370

0.22UF

C3371

0.22UF

470K

5%
1/20W
MF
201

GND_VOID=TRUE

GND_VOID=TRUE

(Both C’s)

C3372

0.22UF

C3373

0.22UF

470K

5%
1/20W
MF
201

1 2

1 2

GND_VOID=TRUE

1

R3371

470K

5%
1/20W
MF
201

2

1 2

1 2

GND_VOID=TRUE

1

R3373

470K

5%
1/20W
MF
201

2

20%
X5R

20%
X5R

20%
X5R

20%
X5R

TBT_B_R2D_C_P<0>

6.3V
0201

TBT_B_R2D_C_N<0>

6.3V
0201

DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>

TBT_B_R2D_C_P<1>

6.3V
0201

TBT_B_R2D_C_N<1>

6.3V
0201

Thunderbolt Connector B

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

29 77

29 77

29

29 77

29 77

29

IN
IN
IN

12

25

25 28

25

SYNC_DATE=10/26/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

PAGE

33 OF 120

SHEET

29 OF 82

124578

IN
IN

29 77

29 77

IN
IN

dvt1

25 71 77

25 71 77

25 71 77

25 71 77

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

DDC Pull-Ups

2.2k pull-ups are required by PCH
to indicate active display interface.

DP++ spec violation, should remove!

NOTE: Only DDC_DATA is sensed, so DDC_CLK

D

=PP3V3_S0_DDCMUX

68

pull-ups are unstuffed.

D

R3451

DDC Crossbar

On single-port hosts alias TBTPA_DDC to TBTSNK0_DDC.

R3485

DP_TBTPA_DDC_CLK

28

C

TBT_DDC_XBAR_EN_L

25

IN

OUT

DP_TBTPA_DDC_DATA

28

BI

DP_TBTPB_DDC_CLK

29

OUT

DP_TBTPB_DDC_DATA

29

BI

Q3485

DMN5L06VK-7

SOT563

VER 3

TBT_DDC_XBAR_EN

3

D

5

SG

4

SAI/SBI = 1: INA == OUTA0, INB == OUTB0
SAI/SBI = 0: INA == OUTB0, INB == OUTA0

Only necessary on dual-port hosts.

NEVER SEND AUXCH THROUGH CROSSBAR!

1

100K

5%

1/20W

201

MF

2

16

14

10

12 11

1
2

3
4

SBI

TS3DS10224

ENA

INA+
INA-

SAI

ENB

INB+
INB-

U3400

CRITICAL

QFN

SAO

SBO

1

C3480

0.1UF

20%
10V

2

CERM
402

20
19

18
17

15

6
7

8
9

13

VCC

OUTA1+
OUTA1-

OUTA0+
OUTA0-

OUTB1+
OUTB1-

OUTB0+
OUTB0-

PAD

THRM

GND

5

21

1

2.2K

1%
1/20W
MF
201

2

R3452

1

2.2K

1%
1/20W
MF
201

2

R3453

1

2.2K

1%
1/20W
MF
201

2

R3454

1

2.2K

1%
1/20W
MF
201

2

DP_TBTSNK1_DDC_CLK
DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA

C

67

IN

67

BI

13

IN

13

BI

SIZE

B

A

D

B

Second FET needed for
dual-port designs.
CONNECTS TO TBTBTS_PWREN_L ON PAGE 30.

TBTBST_PWREN_L

6

D

SG

1

25 29

TBT_B_HV_EN

IN

Q3485

DMN5L06VK-7

SOT563

VER 3

2

A

6 3

27

OUT

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

34 OF 120

SHEET

30 OF 82

BOM_COST_GROUP=TBT

SYNC_MASTER=J14

PAGE TITLE

DDC Crossbar

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

124578

8 7 6 5 4 3

12

D

C

D

C

=PP3V3_S4_BT

31 68

BYPASS=U3520::5 mm

1

C3520

0.1UF

10%
10V

2

6

08

3

5

NC

0

1 2

5%

1/20W

MF

0201

X5R-CERM
0201

2

1

NC

PM_SLP_S4_L

40

OUT

SYNC_MASTER=J41

PAGE TITLE

Wireless Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

13 18 37 38 64 66

IN

SYNC_DATE=11/01/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

35 OF 120

SHEET

31 OF 82

124578

SIZE

B

A

D

PCIe Wake Muxing

B

=PP3V3_S5_WLAN

68

1

R3561

100K

5%
1/20W
MF
201

2

AP_PCIE_WAKE_L

66 75

C3560

0.1UF

10%

6.3V

CERM-X5R

0201

1

2

4

VCC

CRITICAL

U3560

NC7SB3157P6XG

SC70
VER-3

A

GND

5

2

A

SEL OUTPUT

L PCIE_WAKE_L (B0)
H AP_S0IX_WAKE_L (B1)

6

AP_S0IX_WAKE_SEL

S

3

PCIE_WAKE_L

B0

1

AP_S0IX_WAKE_L

B1

NOSTUFF

R3560

0

1 2

5%

1/20W

MF

0201

15

IN

13 33 75

OUT

15

OUT

BLUETOOTH

=PP3V3_S4_BT

31 68

1

5

VDD

U3510

USB3740

DFN

GND

DP_2

DM_2

DP_1

DM_1

OE*

S

8

CRITICAL

66 74

66 74

USB_BT_CONN_P
USB_BT_CONN_N

SIGNAL_MODEL=BT_MUX

10

DP

9

DM

C3510

0.1UF

10%

6.3V

2

CERM-X5R
0201

6

USB_BT_P

7

USB_BT_N

2

NC

1

BT_WAKE

3

4

SEL OUTPUT

L BT_WAKE (1)
H USB_BT (2)

14 74

BI

14 74

BI

PM_SLP_S4_BTMUX_L

NO_XNET_CONNECTION=TRUE

Q3510

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

1

G S

1

2

R3512

15K

1%
1/20W
MF
201

BT_WAKE_L

3

D

2

CRITICAL

74LVC1G08

SOT891

4

U3520

NOSTUFF

R3520

BOM_COST_GROUP=WIRELESS

6 3

8 7 6 5 4 3

12

D

PLACE_NEAR=J3700.1:3mm

CRITICAL

L3700

FERR-26-OHM-6A

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1 2

0603

1

C3701

0.1UF

10%
10V

2

X5R-CERM
0201

1 2

GND_VOID=TRUE

10%

1 2

GND_VOID=TRUE

1 2

GND_VOID=TRUE

1 2

GND_VOID=TRUE

1 2

GND_VOID=TRUE

1 2

GND_VOID=TRUE

1 2

GND_VOID=TRUE

1 2

GND_VOID=TRUE

16V

X5R-CERM

16V10%

16V10%

16V10%

X5R-CERM

16V10%

X5R-CERM 0201

16V10%

X5R-CERM

16V10%

X5R-CERM

16V10%

1

C3702

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=L3700.1:1mm

15

IN

R3701

1 2

0201

0201X5R-CERM

0201X5R-CERM

0201

0201

0201

0201X5R-CERM

=PP3V3_S0SW_SSD

32 68

PLACE_NEAR=L3700.1:1mm

C

SSD_BOOT

13

IN

PCIE_SSD_R2D_C_N<3>

12 71 81

IN

PCIE_SSD_R2D_C_P<3>

12 71 81

IN

PCIE_SSD_R2D_C_N<2>

12 71 81

IN

PCIE_SSD_R2D_C_P<2>

12 71 81

IN

PCIE_SSD_R2D_C_N<1>

12 71 81

IN

PCIE_SSD_R2D_C_P<1>

12 71 81

IN

PCIE_SSD_R2D_C_N<0>

12 71 81

IN

PCIE_SSD_R2D_C_P<0>

12 71 81

IN

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

C3710
C3711
C3712
C3713

C3714
C3715
C3716
C3717

1

C3722

12PF

5%
25V

2

NP0-C0G
0201

PP3V3_S0SW_SSD_FLT

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.15mm
VOLTAGE=3.3V

SSD_SR_EN_L
SSD_RESET_CONN_L

MF

0

SSD_BOOT_R

5%

0201

1/20W

NOSTUFF

71 81

PCIE_SSD_R2D_P<3>

71 81

PCIE_SSD_R2D_N<2>

71 81

PCIE_SSD_R2D_P<2>

71 81

PCIE_SSD_R2D_N<1>

71 81

PCIE_SSD_R2D_P<1>

71 81

71 81

PCIE_SSD_R2D_P<0>

71 81

SSD_CLKREQ_CONN_L

1

C3723

12PF

5%
25V

2

NP0-C0G
0201

TRUE TRUE

TRUE
TRUE

TRUE

TRUE

TRUE TRUE

TRUE

1

C3724

12PF

5%
25V

2

NP0-C0G NP0-C0G
0201

514S0449

CRITICAL

J3700

SSD-GS3

F-RT-SM
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

17
18
19
20
21
22
23
24
25
26
27
28

53
52
51

50
49
48
47

46
45
44
43
42
41
40

39
38
37
36
35
34
33

32
31
30
29

1

2

GND_VOIDGND_VOID

TRUETRUE

TRUE
TRUE

TRUE

TRUE

TRUE

C3725

12PF

5%
25V
NP0-C0G
0201

NC
NC

81

81

NOSTUFF

1

C3726

12PF

5%
25V

2

0201

R3700

100K

1/20W

NOSTUFF

SMC_OOB1_R2D_CONN_L
SMC_OOB1_D2R_CONN_L

SSD_PWR_EN

PCIE_SSD_D2R_N<3>PCIE_SSD_R2D_N<3>
PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<0>PCIE_SSD_R2D_N<0>
PCIE_SSD_D2R_P<0>

PCIE_CLK100M_SSD_RC2_N
PCIE_CLK100M_SSD_RC2_P

201

1

1%
MF

2

15 32 64

IN

12 71 81

OUT

12 71 81

OUT

12 71 81

OUT

12 71 81

OUT

12 71 81

OUT

12 71 81

OUT

12 71 81

OUT

12 71 81

OUT

=PP3V3_S0_OOB1_PWRDN

68

R3703

OOB Isolation

=PP3V3_S0SW_SSD

32 68

CRITICAL

74LVC1G08

BYPASS=U3711::5 mm

C3719

0.1UF

X5R-CERM

1

100K

1%

1/20W

MF

201

2

SOT891

10%
10V

0201

4

U3710

1

2

2

U3711

1

NC

5

NC

6

08

3

6

08

3

5

NC

CRITICAL

NC

74LVC1G08

BYPASS=U3710::5 mm

1

C3718

0.1UF

10%
10V

2

X5R-CERM
0201

2

SMC_OOB1_R2D_L

1

SOT891

4

SMC_OOB1_D2R_L

38

IN

38

OUT

D

C

54
55

B

1

2

=PP3V3_S0SW_SSD

1

R3741

232K

1%
1/20W
MF
201

2

1

R3742

100K

1%
1/20W
MF
201

2

SSD_CLKREQ:UNI

R3740

100K

5%

1/20W

MF

201

Supervisor & CLKREQ# Isolation

Delay = 55ms

32 68

2

4

7

SENSE

0.7V

RESET*

IN

P3V3SSD_VMON

SSD_CLKREQ_CONN_R_L

R3744

1 2

1/20W

SSD_CLKREQ:UNI

0201

0

5%
MF

1

CRITICAL

VDD

U3740

SLG4AP016V

TDFN
+

-

DLY

THRM

GND

PAD

9

=PP3V42_G3H_SSDSAK

1

C3740

0.1UF

10%

6.3V

2

CERM-X5R
0201

3

MR*

OUT

(OD)

5

6

EN

8

SSD_RESET_L

SSD_PWR_EN
SSD_CLKREQ_R_L

68

15

IN

R3745

15

IN

32 64

SSD_CLKREQ:UNI

0

1 2

5%

1/20W

MF

0201

SSD_CLKREQ_L

Gumstick3 Connector

12

OUT

56
57
58

A

R3743

0

5%

1/20W

1 2

MF

0201

SSD_CLKREQ:BI

6 3

59
60
61
62
63

R3702

0

1 2

5%

1/20W

MF

0201

12 71 81

IN

IN

SSD Connector

Apple Inc.

12 71 81

SYNC_DATE=12/18/2012

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

37 OF 120

SHEET

32 OF 82

8.0.0
dvt1

PLACE_NEAR=R3704.1:1mm

PLACE_NEAR=R3706.1:1mm

C3720

47PF

0201

NOSTUFF

25V
C0G

1

5%

2

R3704

0

5%

1/20W

1 2

PLACE_NEAR=C3721.1:1mm

PLACE_NEAR=C3721.2:1mm

R3706

1 2

0201

1/20W

0201

81

MF

0

5%

81

MF

PCIE_CLK100M_SSD_RC1_N

PCIE_CLK100M_SSD_RC1_P

BOM_COST_GROUP=SSD

16

OUT

C3721

47PF

25V
C0G

0201

NOSTUFF

SSD_PCIE_SEL_L

R3705

1 2

1

5%

2

R3707

1 2

0

5%

1/20W

PLACE_NEAR=C3721.1:1mm

PLACE_NEAR=C3721.2:1mm

1/20W

PCIE_CLK100M_SSD_N

MF

0201

0

5%

PCIE_CLK100M_SSD_P

MF

0201

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

B

A

D

124578

D

33

33

C

B

A

8 7 6 5 4 3

PART NUMBER

138S0801 CRITICAL

GND_CAM_PVSSC

GND_CAM_PVSSD

QTY

CAM_UARTCTS

33

CAM_UARTRXD

33

2

N7
N8
N6

C10

C7

G14
M12

N13
P14
P15
R15

K15
L12
L13
L14
L15

A1
A6
B6
D1
D5
E5
G1
G6
G7
G8
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
J9
K1
K5
K6
K7
K8
K9

A14

M9
N1
P5
R1
R5

E9

B12

DESCRIPTION

CAP,CER,10UF,20%,6.3V,HRZTL,0402

U3900

BCM15700

FBGA

SYM 3 OF 3

CRITICAL

MIPI_AGND

OMIT_TABLE

PCIE_GND

PMU_AVSS

SR_PVSSC

SR_PVSSD

VSSC

XTAL_AVSS

SR_VDD_3P3C

SR_VDD_3P3D

L3901:1
L3902:1

1

R3975

51K

5%
1/20W
MF
201

2

DDR_VDDIO

DDR_VDDIO_CK

DDR_VREF

PCIE_VDD1P2

PCIE_PVDD1P2

DDR_AVDD1P8

MIPI_AVDD1P8

PLL_VDD1P8

OTP_VDD3P3

SR_VLXC_O

SR_VLXD_O

VDD_1P35A

VDD_3P3A

VDD1P2_O

VDD1P8_O

VSENSE_C
VSENSE_D

XTAL_AVDD1P2

VDDC

VDDO18

1

R3976

51K

5%
1/20W
MF
201

2

REFERENCE DES

C3931,C3933

PP1V35_CAM

33 34 78

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.35V

PP1V35_DDR_CLK

A4
D4
G4
K4
N4

G5

N5

C8

D9

J1

L7

D6

(=PP3V3_S3RS0_CAMERA)

D7

M14
M15
N15

H14
H15
J13
J14
J15

M13
N14

K13
K14

F14

J11

F15

G15

F6
F7
F8
F9
L6
L5
L8
L9

B15

R11

M11
K12

B13

1

C3977

12PF

5%

25V

2

NP0-C0G

0201

(=PP3V3_S3RS0_CAMERA)

P1V35_CAM_SRVLXD_PHASE

PP1V35_CAM

PP1V8_CAM

PP1V2_CAM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PP1V2_CAM

PP1V35_CAM

PP1V2_CAM_XTALPCIEVDD

1

2

CRITICAL

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.35V

PP0V675_CAM_VREF

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=0.675V

PP1V2_CAM_PCIE_VDD_FLT

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PP1V2_CAM_PCIE_PVDD_FLT

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PP1V8_CAM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

1

C3928

4.7UF

20%

6.3V

2

X5R
402

GND_CAM_PVSSC

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.175MM

VOLTAGE=0V

P1V2_CAM_SRVLXC_PHASE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

33 34 78

PP1V2_CAM_XTALPCIEVDD

33

33

33 34 78

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

MAKE_BASE=TRUE

=PPVDDIO_S3RS0_CAMCLK

C3960

0.1UF

10%

6.3V
CERM-X5R
0201

R3912

1 2

1 2

1

C3900

0.1UF

10%

6.3V

2

CERM-X5R
0201

34 78

1

C3927

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900.D7::2.54MM

33

33

33

240

1%

1/20W

MF

201

BOM OPTION

L3902

1.0UH-1.6A-55MOHM

1 2

1

C3976

12PF

5%
25V

2

NP0-C0G
0201

33

1

C3970

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900.F6::2.54MM

1

2

1

C3971

1000PF

10%
16V

2

X7R-1
0201

BYPASS=U3900.F6::2.54MM

BYPASS=U3900.F9::2.54MM

1

C3978

12PF

5%
25V

2

NP0-C0G
0201

33 44

PP1V8_CAM

33 34

R3913

33 44

C3937

0.1UF

10%

6.3V
CERM-X5R
0201

PCIE_WAKE_L

13 31 75

OUT

PP1V8_CAM

33 34

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

BI

34 78

OUT

34 78

OUT

34 78

OUT

34

OUT

PLACE_NEAR=U3900.R9:5MM

P1V35_CAM_SRVLXD_PHASE

1008

PLACE_NEAR=U3900.K13:4MM

PP1V8_CAM

1

R3920

100K

5%
1/20W
MF
201

2

1

C3972

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900.F9::2.54MM

BYPASS=U3900.L9::2.54MM

1

R3914

33 34 71

33 34 71

1/20W

OUT

BI

201

1K

5%
MF

1K

5%

1/20W

MF

201

2

NOSTUFF

R3991

0

1 2

5%

1/20W

MF

0201

1

R3990

100K

5%
1/20W
MF
201

2

NOSTUFF

1

C3990

0.1UF

10%

6.3V

2

CERM-X5R
0201

CAM_XTAL_FREQ

33

PU = 25MHz

I2C_CAM_SCK

33 34 71

I2C_CAM_SDA

33 34 71

1

2

34 71 78

34 71 78

34 71 78

34 71 78

34 81

34 81

34 81

34 81

34 81

34 81

1

2

PU on PCH page

PLACE_NEAR=U3900.R10:5MM

L3906

22NH

0402

1

C3938

1000PF

10%
16V

2

X7R-1
0201

XW3900

SM

1 2

PLACE_NEAR=U3900.M14:2.54MM

1

C3926

4.7UF

20%

6.3V

2

X5R
402

MIN_NECK_WIDTH=0.175MM

1

C3941

2.2UF

20%

6.3V

2

CERM

1

C3939

1UF

10%

10V

2

X5R
402

BYPASS=U3900.G15::2.54MM

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

17

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

34 78

OUT

402-LF

BYPASS=U3900.F15::2.54MM

MEM_CAM_A<0>
MEM_CAM_A<1>
MEM_CAM_A<2>
MEM_CAM_A<3>
MEM_CAM_A<4>
MEM_CAM_A<5>
MEM_CAM_A<6>
MEM_CAM_A<7>
MEM_CAM_A<8>
MEM_CAM_A<9>
MEM_CAM_A<10>
MEM_CAM_A<11>
MEM_CAM_A<12>
MEM_CAM_A<13>
MEM_CAM_A<14>

MEM_CAM_BA<0>
MEM_CAM_BA<1>
MEM_CAM_BA<2>

MEM_CAM_CLK_P
MEM_CAM_CLK_N

MEM_CAM_DM<0>
MEM_CAM_DM<1>

MEM_CAM_ZQ_S2
MEM_CAM_CKE
MEM_CAM_CS_L

1

C3921

1.0UF

20%

6.3V

2

X5R
0201-1

1

2

OMIT_TABLE

1

C3930

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3932

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3919

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900.J1::2.54MM

GND_CAM_PVSSD

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

1

2

1

2

1

2

BYPASS=U3900.J1::2.54MM

1

C3942

4.7UF

20%

6.3V

2

X5R
402

BYPASS=U3900::7mm

L3

DDR_AD00

M4

DDR_AD01

N3

DDR_AD02

M3

DDR_AD03

M1

DDR_AD04

M2

DDR_AD05

P4

DDR_AD06

N2

DDR_AD07

P3

DDR_AD08

P2

DDR_AD09

J4

DDR_AD10

R2

DDR_AD11

L1

DDR_AD12

P1

DDR_AD13

R4

DDR_AD14

K3

DDR_BA0

L2

DDR_BA1

K2

DDR_BA2

H2

DDR_CK_P0

G2

DDR_CK_N0

C1

DDR_DM0

C4

DDR_DM1

G3

DDR_ZQ

J3

DDR_CKE

L4

DDR_CS*

1

C3922

0.1UF

10%

6.3V
CERM-X5R
0201

C3931

10UF

20%

6.3V
CERM-X5R
0402-1

C3933

10UF

20%

6.3V
CERM-X5R
0402-1

OMIT_TABLE

C3918

1000PF

10%
16V
X7R-1
0201

BYPASS=U3900.L7::2.54MM

XW3901

1 2

BYPASS=U3900::5mm

C3923

1.0UF

20%

6.3V

2

X5R
0201-1

L3903

220-OHM-1.4A

1 2

0603

L3904

220-OHM-1.4A

1 2

0603

1

C3916

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900.L7::2.54MM

SM

1

C3940

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900::3mm

OMIT_TABLE

1

2

GND_CAM_PVSSD

33

1

2

BYPASS=U3900.D6::2.54MM

1

C3934

1000PF

10%
16V

2

X7R-1
0201

BYPASS=U3900::5mm

U3900

BCM15700

FBGA

SYM 2 OF 3

CRITICAL

BYPASS=U3900.K13::2.54MM

C3924

0.1UF

10%

6.3V
CERM-X5R
0201

1

C3912

4.7UF

20%

6.3V

2

X5R
402

PP1V2_CAM_XTALPCIEVDD

1

C3917

1000PF

10%
16V
X7R-1
0201

C3910

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U3900.D6::2.54MM

=PP3V3_S3RS0_CAMERA

1

C3980

12PF

5%
25V

2

NP0-C0G
0201

1

C3981

12PF

5%
25V

2

NP0-C0G
0201

=PP3V3_S3RS0_CAMERA

1

C3935

0.1UF0.1UF

10%

6.3V

2

CERM-X5R
0201

DDR_DQ00
DDR_DQ01
DDR_DQ02
DDR_DQ03
DDR_DQ04
DDR_DQ05
DDR_DQ06
DDR_DQ07
DDR_DQ08
DDR_DQ09
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15

DDR_DQS_P0
DDR_DQS_N0

DDR_DQS_P1
DDR_DQS_N1

DDR_RAS*

DDR_WE*

DDR_CAS*

DDR_RESET*

1

2

BYPASS=U3900::3mm

C2
E3
E4
D3
F3
F1
F4
F2
B5
C3
B1
B4
A5
C5
B2
B3

E2
D2

A2
A3

H3
J2
H4
R3

1

C3913

4.7UF

20%

6.3V

2

X5R
402

PP1V2_CAM

33

1

C3951

0.1UF

10%

6.3V

2

CERM-X5R
0201

C3936

1000PF

10%
16V
X7R-1
0201

BYPASS=U3900::5mm

MEM_CAM_DQ<0>
MEM_CAM_DQ<1>
MEM_CAM_DQ<2>
MEM_CAM_DQ<3>
MEM_CAM_DQ<4>
MEM_CAM_DQ<5>
MEM_CAM_DQ<6>
MEM_CAM_DQ<7>
MEM_CAM_DQ<8>
MEM_CAM_DQ<9>
MEM_CAM_DQ<10>
MEM_CAM_DQ<11>
MEM_CAM_DQ<12>
MEM_CAM_DQ<13>
MEM_CAM_DQ<14>
MEM_CAM_DQ<15>

MEM_CAM_DQS_P<0>
MEM_CAM_DQS_N<0>

MEM_CAM_DQS_P<1>
MEM_CAM_DQS_N<1>

MEM_CAM_RAS_L
MEM_CAM_WE_L
MEM_CAM_CAS_L
MEM_CAM_RESET_L

6 3

33

1

R3921

100K

5%
1/20W
MF
201

2

I2C_CAM_SMBDBG_CLK
I2C_CAM_SMBDBG_DAT

1

C3973

1000PF

10%
16V
X7R-1
0201

BYPASS=U3900.L9::2.54MM

IN
IN

IN
IN

IN
IN

IN
IN

OUT
OUT

34 74

34 74

12

15 18

34

18

1

C3982

12PF

2

C3974

0.1UF

10%

6.3V

2

CERM-X5R
0201

MIPI_CLK_P
MIPI_CLK_N

MIPI_DATA_P
MIPI_DATA_N

PCIE_CAMERA_R2D_P
PCIE_CAMERA_R2D_N

PCIE_CLK100M_CAMERA_C_P
PCIE_CLK100M_CAMERA_C_N

PCIE_CAMERA_D2R_C_P
PCIE_CAMERA_D2R_C_N

CLK25M_CAM_CLKP

OUT

CLK25M_CAM_CLKN

IN

I2C_CAM_SMBDBG_CLK

33

I2C_CAM_SCK
I2C_CAM_SMBDBG_DAT

33

I2C_CAM_SDA

TP_CAM_JTAG_TCK
TP_CAM_JTAG_TDI
TP_CAM_JTAG_TDO
TP_CAM_JTAG_TMS
TP_CAM_JTAG_TRST_L
CAM_JTAG_SRST_L

33

CAMERA_CLKREQ_L

OUT

CAM_PCIE_RESET_L

IN

CAM_PCIE_WAKE_L

75

CAM_PWR_SEL
CAM_DEBUG_RESET_L

1

R3901

100K

PD = 1.35V

5%
1/20W
MF
201

2

CAM_SENSOR_WAKE_L

IN

CAMERA_PWR_EN

IN

1

R3904

100K

5%
1/20W
MF
201

2

1

C3983

12PF

5%
25V
NP0-C0G
0201

5%
25V

2

NP0-C0G
0201

PP1V8_CAM

NOSTUFF

1

R3930

100K

5%
1/20W
MF
201

2

1

R3931

330K

5%
1/20W
MF
201

2

33

33

1

C3975

0.1UF

10%

6.3V

2

CERM-X5R
0201

PP1V8_CAM

CAM_XTAL:YES

1

R3906

100K

5%
1/20W
MF
201

2

CAM_XTAL:NO

1

R3907

100K

5%
1/20W
MF
201

2

1

C3979

12PF

5%
25V

2

NP0-C0G
0201

GND_CAM_PVSSC

33

P7
R7

P8
R8

P6

NC

R6

NC

B7
A7

B10
A10

A8
B8

B9

NC

C9

NC

A13
A12

D15
R10
C15

R9

F13
E12
F12
D12
D11
C11

P13
R14
N12

G12
E15
R13
H12

CAM_XTAL_SEL

MIPI_CP_CLK
MIPI_CM_CLK

MIPI_DP0
MIPI_DM0

MIPI_DP1
MIPI_DM1

PCIE_RDP0
PCIE_RDN0

PCIE_REFCLKP
PCIE_REFCLKN

PCIE_TDP0
PCIE_TDN0

PCIE_TESTP
PCIE_TESTN

XTAL_P
XTAL_N

I2C_CLK_DBG
I2C_CLK_SENSOR
I2C_DATA_DBG
I2C_DATA_SENSOR

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
JTAG_SRST*

PCIE_CLKREQ*
PCIE_RST*
PCIE_WAKE*

PWR_MODE
RESET*
SENSOR_WAKE*
SHUTDOWN*

33 34

BOM_COST_GROUP=CAMERA

PP1V8_CAM

33 34

33

33 34

NOSTUFF

1

R3932

100K

5%
1/20W
MF
201

2

1

R3933

330K

5%
1/20W
MF
201

2

1

C3914

4.7UF

20%

6.3V

2

X5R
402

BCM15700

SYM 1 OF 3

OMIT_TABLE

NOSTUFF

1

R3934

100K

5%
1/20W
MF
201

2

CAM_RAMCFG2
CAM_RAMCFG1
CAM_RAMCFG0

1

R3935

330K

5%
1/20W
MF
201

2

1.0UH-1.6A-55MOHM

1

C3915

4.7UF

20%

6.3V

2

X5R
402

U3900

FBGA

CRITICAL

STRAP_XTAL_FREQ

CAM_A1

1

R3915

100K

5%
1/20W
MF
201

2

CAM_JTAG_SRST_L

L3901

1 2

1008

PLACE_NEAR=U3900.M13:2.54MM

DEBUG_00
DEBUG_01
DEBUG_02
DEBUG_03
DEBUG_04
DEBUG_05
DEBUG_06
DEBUG_07
DEBUG_08
DEBUG_09
DEBUG_10
DEBUG_11
DEBUG_12
DEBUG_13
DEBUG_14
DEBUG_15
DEBUG_16

GPIO_00
GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06
GPIO_07

UARTCTS
UARTRTS

UARTRXD
UARTTXD

TEST_OUT

TEST_MODE

STRAP_XTAL_SEL

CAM_TEST_OUT

33

A1 SILICON BUG

SYNC_MASTER=J45

PAGE TITLE

Camera (1 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

33

33

33

P1V2_CAM_SRVLXC_PHASE

PLACE_NEAR=U3900.M13:4MM

B11

TP_CAM_TEST_MODE0

C14

TP_CAM_TEST_MODE1

B14

TP_CAM_TEST_MODE2

A15

TP_CAM_LV_JTAG_TCK

E11

TP_CAM_LV_JTAG_TDI

E10

TP_CAM_LV_JTAG_TDO

F11

TP_CAM_LV_JTAG_TMS

F10

TP_CAM_LV_JTAG_TRSTN

G11

NC

G10

NC

H11

NC

H10

NC

J10

NC

K11

NC

K10

NC

L11

NC

L10

NC

R12

CAM_RAMCFG0

P12

CAM_RAMCFG1

P11

CAM_RAMCFG2

P10

CAM_GPIO3

P9

NC

N11

NC

N10

NC

N9

NC

D13

CAM_UARTCTS

D14

TP_CAM_UARTRTS

E13

CAM_UARTRXD

E14

TP_CAM_UARTTXD

J12

CAM_TEST_OUT

M10

CAM_TEST_MODE

C13

CAM_XTAL_FREQ

C12

CAM_XTAL_SEL

CAM_TEST_MODE

33

33

NO STUFF

1

R3910

100K

5%
1/20W
MF
201

2

PP1V8_CAM

33 34

SYNC_DATE=01/24/2013

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

39 OF 120

SHEET

33 OF 82

124578

NOSTUFF

R3936

100K

1/20W

33

33

33

NOSTUFF

R3937

100K

1/20W

33

33

33

33

33

33

1

R3911

100K

5%
1/20W
MF
201

2

8.0.0
dvt1

201

201

D

33

C

1

5%
MF

2

1

5%
MF

2

B

A

SIZE

D

8 7 6 5 4 3

12

PP1V35_CAM

33 78

1

C4019

12PF

5%
25V

2

0201

1

1

C4011

0.1UF

10%

6.3V

2

2

CERM-X5R
0201

MEM_CAM_A<0>
MEM_CAM_A<1>
MEM_CAM_A<2>
MEM_CAM_A<3>
MEM_CAM_A<4>
MEM_CAM_A<5>
MEM_CAM_A<6>
MEM_CAM_A<7>
MEM_CAM_A<8>
MEM_CAM_A<9>
MEM_CAM_A<10>
MEM_CAM_A<11>
MEM_CAM_A<12>
MEM_CAM_A<13>
MEM_CAM_A<14>

MEM_CAM_BA<0>
MEM_CAM_BA<1>
MEM_CAM_BA<2>

MEM_CAM_RAS_L
MEM_CAM_CAS_L
MEM_CAM_WE_L

MEM_CAM_CLK_P
MEM_CAM_CLK_N

MEM_CAM_CKE
MEM_CAM_CS_L

MEM_CAM_ODT

78

MEM_CAM_ZQ_DDR

MEM_CAM_RESET_L

C4010

0.1UF

6.3V

CERM-X5R

0201

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33 78

IN

33

IN

1

C4018

12PF

5%
25V

2

NP0-C0G
0201

10%

1

C4017

12PF

5%
25V

2

NP0-C0G

R4000

D

PP0V675_CAM_VREF

33 78

R4022

1/20W

201

R4023

1/20W

201

1

1K

1%
MF

2

1

1K

1%
MF

2

1 2

0201

5%

1/20W

0

MF

R4002

1/20W

NOSTUFF

R4003

1/20W

201

201

78

78

1

1K

5%
MF

2

1

1K

5%
MF

2

0201

PP0V675_MEM_CAM_VREFDQ

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.675V

PP0V675_MEM_CAM_VREFCA

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.675V

C

33 78

IN

1

R4020

84.5

1%
1/20W
MF
201

33 78

IN

33 78

IN

MEM_CAM_CKE_R

NO STUFF

1

R4006

100PF

5%
25V

2

C0G
0201

B

2

NO STUFF

1

R4021

82

1%
1/20W
MF
201

2

1

R4004

240

1%
1/20W
MF
201

2

BYPASS=U4000.A1::4mm

1

C4020

12PF

5%
25V

2

NP0-C0GNP0-C0G

0201

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

M2
N8
M3

J3
K3
L3

J7
K7

K9
L2

K1

L8

T2

OMIT_TABLE

1

C4002

10UF

20%

6.3V

2

CERM-X5R
0402-1

A1A8C1C9D2E9F1H2H9

VDDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14

BA0
BA1
BA2

RAS*
CAS*
WE*

CK
CK*

CKE
CS*

ODT

ZQ

RESET*

VSSQ

B1B9D1D8E2E8F9G1G9

OMIT_TABLE

BYPASS=U4000.B2::4mm

1

C4003

10UF

20%

6.3V

2

CERM-X5R
0402-1

B2D9G7K2K8N1N9R1R9

U4000

4GB-DDR3-256MX16

FBGA

K4B4G1646B-HYK0

1

2

BYPASS=U4000.H9::4mm

VDD

CRITICAL

OMIT_TABLE

VSS

A9

B3

E1G8J2J8M1M9P1

C4004

0.47UF

20%
4V
CERM-X5R-1
201

P9

1

C4005

0.1UF

10%

6.3V

2

CERM-X5R
0201

M8

VREFCA

NC

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQSL

DQSL*

DQSU

DQSU*

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

T1

T9

BYPASS=U4000.D2::4mm

H1

J1

VREFDQ

NC

J9

NC

L1

NC

L9

NC

M7

NC

E3
F7
F2
F8
H3
H8
G2
H7

F3

MEM_CAM_DQS_P<0>

G3

MEM_CAM_DQS_N<0>

C7

MEM_CAM_DQS_P<1>

B7

MEM_CAM_DQS_N<1>

D7
C3
C8
C2
A7
A2
B8
A3

E7

DML

D3

DMU

1

C4006

2.2UF

20%
10V

2

X5R-CERM
402

MEM_CAM_DQ<0>
MEM_CAM_DQ<1>
MEM_CAM_DQ<2>
MEM_CAM_DQ<3>
MEM_CAM_DQ<4>
MEM_CAM_DQ<5>
MEM_CAM_DQ<6>
MEM_CAM_DQ<7>

MEM_CAM_DQ<8>
MEM_CAM_DQ<9>
MEM_CAM_DQ<10>
MEM_CAM_DQ<11>
MEM_CAM_DQ<12>
MEM_CAM_DQ<13>
MEM_CAM_DQ<14>
MEM_CAM_DQ<15>

MEM_CAM_DM<0>
MEM_CAM_DM<1>

1

C4007

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U4000.R9::4mm

BYPASS=U4000.K2::4mm

1

C4008

2.2UF

20%
10V

2

X5R-CERM
402

CAM_XTAL:YES

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

BI

33 78

IN

33 78

IN

1

C4009

0.1UF

10%

6.3V

2

CERM-X5R
0201

C4015

12PF

1 2

25V

C4014

12PF

1 2

25V
CERM
0201

CLK25M_CAM_XTALP

74

5%

0201

CERM

NC
NC

CAM_XTAL:YES

5%

CRITICAL

1 3

Y4000

2 4

SM-3.2X2.5MM

25.000MHZ-12PF-20PPM
CAM_XTAL:YES

CAM_SENSOR_WAKE_L_CONN

34 71

CAM_WAKE:NO

R4031

14 81

14 81

33 81

33 81

12 71 81

12 71 81

SYSCLK_CLK25M_CAMERA

17 74

IN

NOTE: TBD PPM crystal required

1

0

5%

1/20W

MF

0201

2

PCIE_CAMERA_R2D_C_P

IN

PCIE_CAMERA_R2D_C_N

IN

PCIE_CAMERA_D2R_C_P

IN

PCIE_CAMERA_D2R_C_N

IN

PCIE_CLK100M_CAMERA_P

IN

PCIE_CLK100M_CAMERA_N

IN

CAM_XTAL:YES

R4007

0

1 2

5%

0201

1/20W

MF

CAM_WAKE:YES

R4030

0

1 2

5%

0201

1/20W

MF

CLK25M_CAM_XTALP_R

74

NOSTUFF

1

R4012

1M

1%
1/20W
MF
201

2

CLK25M_CAM_XTALN

74

CAM_SENSOR_WAKE_L

33

C4033

0.1UF

C4032

0.1UF

C4031

0.1UF

C4030

0.1UF

C4061

0.1UF

C4062

0.1UF

CAM_XTAL:NO

1 2

PCIE_CAMERA_R2D_P

16V

X5R-CERM

10%

1 2

PCIE_CAMERA_R2D_N

16V

X5R-CERM

10%

1 2

PCIE_CAMERA_D2R_P

16V

10%

1 2

PCIE_CAMERA_D2R_N

16V

10%

1 2

PCIE_CLK100M_CAMERA_C_P

16V

X5R-CERM

10%

1 2

PCIE_CLK100M_CAMERA_C_N

16V

X5R-CERM

10%

R4008

0

1 2

5%

0201

MF

1/20W

R4009

0

1 2

5%

CAM_XTAL:YES

1/20W

MF

0201

R4010

0

1 2

5%

CAM_XTAL:YES

1/20W

MF

0201

PP1V8_CAM

1

R4005

100K

5%
1/20W
MF
201

2

0201

0201

0201X5R-CERM

0201X5R-CERM

0201

0201

CLK25M_CAM_CLKP

CLK25M_CAM_CLKN

CAM_XTAL:NO

1

C4016

100PF

2

33

5%
25V
C0G
0201

33 81

OUT

33 81

OUT

14 71 81

OUT

14 71 81

OUT

33 81

OUT

33 81

OUT

33 74

IN

33 74

OUT

D

C

B

CRITICAL

L4009

CAMERA SENSOR

CRITICAL

J4002

CCR20-AK7100-1

F-RT-SM

14

1
2

MIPI_CLK_CONN_N

71 78

3

MIPI_CLK_CONN_P

71 78

4

CAM_SENSOR_WAKE_L_CONN

5

MIPI_DATA_CONN_N

71 78

6

MIPI_DATA_CONN_P

71 78

7
8

=I2C_ALS_SDA

9

A

ALS

=I2C_ALS_SCL

10

I2C_CAM_SCK

11

I2C_CAM_SDA

12

PP5V_S3RS0_ALSCAM_F

71

13

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

BI
IN
IN
BI

518S0892

41

41

33 71

33 71

34 71

C4013

0.1uF

20%
10V

CERM

402

FERR-120-OHM-1.5A

1

2

FERR-120-OHM-1.5A

3.25-OHM-0.1A-2.4GHZ

PLACE_NEAR=J4002.2:2.54MM

3.25-OHM-0.1A-2.4GHZ

PLACE_NEAR=J4002.5:2.54MM

L4010

12

0402-LF

NOSTUFF

L4011

0402-LF

TAM0605-4SM

SYM_VER-1

1

2 3

CRITICAL

L4007

TAM0605-4SM

1

2 3

12

4

MIPI_CLK_N

MIPI_CLK_P

SYM_VER-1

4

MIPI_DATA_N

MIPI_DATA_P

=PP5V_S0_ALSCAM

=PP5V_S3_ALSCAM

77.2 mA nominal max

96.2 mA peak

33 71 78

IN

33 71 78

IN

33 71 78

BI

33 71 78

BI

68

68

PART NUMBER

138S0801 CRITICAL

QTY

2

DESCRIPTION

CAP,CER,10UF,20%,6.3V,HRZTL,0402

REFERENCE DES

C4002,C4003

6 3

CRITICAL

BOM OPTION

BOM_COST_GROUP=CAMERA

SYNC_MASTER=J41

PAGE TITLE

Camera (2 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/21/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

40 OF 120

SHEET

34 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

RIGHT USB PORT A

12

D

=PP5V_S3_LTUSB

68

USB_EXTA_OC_L

16

OUT

=USB_PWR_EN

64

1

C4690

10UF

20%

6.3V

2

CERM-X5R

0402-2

Current limit per port (R4600+R4601): 2.19A min / 2.76A max

C

Mojo SMC Debug Mux

THE PI3USB102E CAN CLAMP VOLTAGE IN THE INTERNAL USB PINS

=PP3V42_G3H_SMCUSBMUX

68

BYPASS=U4650.9:3:5mm

SMC_DEBUGPRT_RX_L

38 39 74

IN

SMC_DEBUGPRT_TX_L

38 39 74

OUT

USB_EXTA_P

14 74

BI

USB_EXTA_N

14 74

BI

SIGNAL_MODEL=MOJO_MUX_SMSC

B

USB Port Power Switch

CRITICAL

U4600

TPS2557DRB

2

IN_0

3

IN_1

8

FAULT*

4

EN

1

C4691

0.1UF

10%
16V

2

X5R-CERM
0201

C4650

0.1UF

X5R-CERM

0201

CRITICAL

1

C4696

220UF-35MOHM

20%

6.3V

2

POLY-TANT
CASE-B2-SM1

1

10%
10V

2

8

5
4

7
6

GND

1

9

VCC

M+
M-

U4650

PI3USB102EZLE

TQFN

D+

CRITICAL

D-

GND

3

SON

THRM

PAD

9

SELOE*

OUT1
OUT2

ILIM

Y+
Y-

6
7

5

USB_ILIM

R4600

22.1K

1/20W

USB_ILIM_L

1

R4601

22.1K

1%
1/20W
MF
201

2

1

R4650

100K

5%
1/20W
MF
201

2
1
2

10

SMC_DEBUGPRT_EN_L

SEL OUTPUT

L SMC (M)
H USB (D)

201

CRITICAL

L4605

FERR-120-OHM-3A

1

2

1 2

0603

CRITICAL

L4600

90-OHM

DLP0NS

SYM_VER-1

1 2

5.5V-0.28PF

0201-THICKSTNCL

GND_VOID=TRUE

5.5V-0.28PF

0201-THICKSTNCL

PP5V_S3_LTUSB_A_F

71

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

34

CRITICAL

D4601

GND_VOID=TRUE

CRITICAL

D4621

5.5V-0.28PF

0201-THICKSTNCL

CRITICAL

D4611

2

1

2

1

USB2_EXTA_MUXED_F_N

74

USB2_EXTA_MUXED_F_P

74

CRITICAL

2

D4600

5.5V-0.28PF

0201-THICKSTNCL

1

GND_VOID=TRUE

CRITICAL

2

2

1

1

GND_VOID=TRUE

CRITICAL

2

D4610

5.5V-0.28PF

0201-THICKSTNCL

1

D4620

5.5V-0.28PF

0201-THICKSTNCL

CRITICAL

J4600

USB3.0-J44-ALT

F-RT-TH

1

VBUS

2

SSTX+

3

SSTX-

4

GND

5

D-

6

D+

7

GND

8

SXRX+

9

SSRX-

10

GND

11
12
13
14
15
16
17
18
19
20
21
22
23

PP5V_S3_LTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=5V

1

1%
MF

2

C4695

10UF

20%

6.3V

CERM-X5R

0402-2

1

2

38

IN

USB3_EXTA_R2D_C_N

14 71 74

IN

USB3_EXTA_R2D_C_P

14 71 74

IN

GND_VOID=TRUE

C4620

0.1UF

1 2

10%

CERM-X5R0201

USB2_EXTA_MUXED_N

74

USB2_EXTA_MUXED_P

74

14 71 74

14 71 74

C4621

6.3V

0.1UF

1 2

10%

CERM-X5R0201

GND_VOID=TRUE

USB3_EXTA_D2R_N

OUT

USB3_EXTA_D2R_P

OUT

6.3V

1

C4606

12PF

5%

25V

2

NP0-C0G

0201

USB3_EXTA_R2D_N

71 74

USB3_EXTA_R2D_P

74

C4605

0.01UF

X5R-CERM

0201

10%
16V

D

C

B

A

BOM_COST_GROUP=IO PORTS

6 3

SYNC_MASTER=J41

PAGE TITLE

External A USB3 Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

46 OF 120

SHEET

35 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

L4803

PP5V_S4_TPAD_F

36 71

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

C4803

0.1uF

PLACE_NEAR=J4802:3MM

FERR-120-OHM-1.5A

PLACE_NEAR=J4802:3MM

1

20%
10V

2

CERM

402

0402-LF

12

=PP5V_S4_TPAD

68

=PPVIN_S4_TPAD

68 71

D

SMC Manual Reset & Isolation

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

C

Keys ANDed with PSoC power to isolate when PSoC is not powered.

No IPD on OE input pin PP3V3_S4 (symbol error).

=PP3V3_S4_TPAD

36 37 68 71

WS_LEFT_SHIFT_KBD

36 71

WS_LEFT_OPTION_KBD

36 71

WS_CONTROL_KBD

36 71

=PP3V42_G3H_TPAD

36 68

4

OE

(IPD)

1

IN_1

(IPD)

2

IN_2

(IPD)

3

IN_3

(IPD)

10

VDD

U4850

SLG4AP4103

TQFN

THRM

GND

5

OUT_ALL#

PAD

11

OUT_1

OUT_2

OUT_3

C4850

0.1UF

10%
16V

X7R-CERM

0402

9

WS_LEFT_SHIFT_KEY

8

WS_LEFT_OPTION_KEY

7

WS_CONTROL_KEY

Pull-up in U5110.

6

SMC_TPAD_RST_L

B

=PP3V3_S4_TPAD

36 37 68 71

1

1

R4820

100K

5%
1/20W
MF

2

201

2

IOXP1_INT_L

I2C_IOXP_SCL

36 71

I2C_IOXP_SDA

36 71

R4822

2.0K

1/20W

201

5%
MF

1

R4823

2

2.0K

1/20W

201

R4821

10K

5%

1/20W

MF

1

5%
MF

2

201

IOXP1_RESET_L

NOSTUFF

A

C4824

0.01UF

10%
10V

X5R-CERM

0201

1

2

BYPASS=U4820.B4:E2:5MM

1

C4820

1UF

10%

6.3V

2

CERM
402

B3

VCCI

U4820

PCAL6416A

A3 A1

INT*

ADDR

SCL
SDA

RESET*

VFBGA

E2

B5

A5
A4

A2

CRITICAL

F4800

2.5A-16V-0.1OHM

1 2

1812

BYPASS=U4850.10:5:5 mm

1

2

PPVIN_S4_TPAD_FUSE

42

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V

=PP3V3_S4_TPAD

36
37 68 71

PP5V_S4_TPAD_F

36 71

IO Expander / Keyboard Interface

36

36

36

39

OUT

BYPASS=U4820.B3:E2:2MM

1

C4821

0.1UF

P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7

P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7

C3
B1
C1
C2
D1
E1
D2

E3
E4
D3
E5
D4
D5
C5
C4

10%

6.3V

2

CERM-X5R
0201

WS_KBD23
WS_KBD2
WS_KBD1
WS_KBD3
WS_KBD4
WS_KBD20
WS_KBD22
WS_KBD21

TP_IOXP1_0
TP_IOXP1_1
TP_IOXP1_2
TP_IOXP1_3
TP_IOXP1_4
TP_IOXP1_DEBUG
WS_KBD16N
IOXP1_LED_DRV

B4

VCCP

GND

311S0597

(Write: 0x40 Read: 0x41)

BYPASS=U4820.B4:E2:2MM

1

C4822

0.1UF

10%

6.3V

2

CERM-X5R
0201

36 71

36 71

36 71

36 71

36 71

36 71

36 71

36 71

36

6 3

GND_ACTUATOR

36 71

TPAD_ACTUATOR_EN_L

40 42 71

OUT

=I2C_TPAD_SDA

41 71

IN

=I2C_TPAD_SCL

41 71

BI

PP5V_S4_TPAD_F

36 71

=PP3V3_S4_TPAD

36 37 68 71

USB_TPAD_P

14 71 74

BI

USB_TPAD_N

14 71 74

BI

I2C_IOXP_SCL

36 71

OUT

IOXP2_INT_L

36 71

OUT

I2C_IOXP_SDA

36 71

BI

1

2

Q4840

DMN32D2LFB4

DFN1006H4-3

R4840

100K

1/16W
MF-LF

PLACE_NEAR=J4802.1:8MM

C4864

12PF

5%
25V
NP0-C0G
0201

=PP3V3_S4_TPAD

36 37 68 71

SYM_VER_2

1

G S

1

1%

402

2

1

C4862

0.1UF

10%
25V

2

X5R
402

1

C4863

12PF

5%
25V

2

NP0-C0G
0201

R4831

NOSTUFF

C4834

0.01UF

X5R-CERM

WS_KBD15_C

3

D

2

IPD Interface

J4802

DF40BG-48DP-0.4V

M-ST-SM

49

50

1

2

3

4

5

6

7 8

10

9
11 12
13 14
15 16
17 18
19

20
21 22
23 24
25 26
27 28
29

30
31 32
33 34
35 36
37 38
39

40
41 42
43 44
45 46
47 48

51 52

CRITICAL

516S1037

NOTE: Mates with 516S1035 on IPD Flex

BYPASS=U4830.B4:E2:5MM

10K

1/20W

201

10%
10V

0201

1

5%
MF

2

1

2

1

R4830

2

36 71

36 71

36

100K

5%
1/20W
MF
201

IOXP2_INT_L

I2C_IOXP_SCL
I2C_IOXP_SDA

IOXP2_RESET_L

1

C4830

1UF

10%

6.3V

2

CERM
402

A3 A1

B5

A5
A4

A2

GND_ACTUATOR

36 71

TPAD_VBUS_EN
TPAD_ACTUATOR_THRMTRIP_L

=TPAD_WAKE_L
SMC_LID

TPAD_SPI_INT_L
=TPAD_SPI_BUS_EN

=TPAD_SPI_SCLK
=TPAD_SPI_MISO
=TPAD_SPI_CS_L
=TPAD_SPI_MOSI

B3

VCCI

U4830

PCAL6416A

INT*

VFBGA

ADDR

SCL
SDA

RESET*

GND

E2

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

XW4801

SM

1 2

PLACE_NEAR=J4802:3MM

37 71

IN

62 71

OUT

40 71

OUT

38 39 40 71

IN

15 71

OUT

37 71

IN

37 71

IN

37 71

OUT

37 71

IN

37 71

IN

38 39 71

PLACE_NEAR=J4813.5:5MM

B4

VCCP

BYPASS=U4830.B3:E2:2MM

1

C4831

2

WS_KBD5

36 71 36 71

P0_0

C3

WS_KBD6

36 71

P0_1

B1

WS_KBD7

36 71

P0_2

C1

WS_KBD9

36 71

P0_3

C2

WS_KBD12

36 71

P0_4

D1

WS_KBD8

36 71

P0_5

E1

WS_KBD17

36 71

P0_6

D2

WS_KBD18

36 71

P0_7

E3

WS_KBD19

36 71

P1_0

E4

WS_KBD10

36 71

P1_1

D3

WS_KBD14

36 71

P1_2

E5

WS_KBD13

36 71

P1_3

D4

WS_KBD11

36 71

P1_4

D5

WS_CONTROL_KEY

P1_5

C5

WS_LEFT_OPTION_KEY

P1_6

C4

WS_LEFT_SHIFT_KEY

P1_7

BYPASS=U4830.B4:E2:2MM

1

0.1UF

10%

6.3V
CERM-X5R
0201

C4832

0.1UF

10%

6.3V

2

CERM-X5R
0201

36

36

36

311S0597

(Write: 0x42 Read: 0x43)

BOM_COST_GROUP=TRACKPAD

36

36

SMC_ONOFF_L

OUT

1

R4850

10K

5%
1/20W
MF
201

2

Keyboard Connector

=PP3V3_S4_TPAD

36 37 68 71

=PP3V42_G3H_TPAD

36 68

WS_KBD1

36 71

WS_KBD2

36 71

WS_KBD3

36 71

WS_KBD4

36 71

WS_KBD5

36 71

WS_KBD6

36 71

WS_KBD7

36 71

WS_KBD8

36 71

WS_KBD9

36 71

WS_KBD10

36 71

WS_KBD11

36 71

WS_KBD12

36 71

WS_KBD13

36 71

WS_KBD14

36 71

WS_KBD15_CAP

71

WS_KBD16_NUM

71

WS_KBD17

36 71

WS_KBD18

36 71

WS_KBD19

36 71

WS_KBD20

36 71

WS_KBD21

36 71

WS_KBD22

36 71

WS_KBD23

36 71

WS_KBD_ONOFF_L

71

WS_LEFT_SHIFT_KBD

36 71

WS_LEFT_OPTION_KBD

36 71

WS_CONTROL_KBD

36 71

1

R4853

10K

5%
1/20W
MF
201

2

1

R4854

10K

2

=PP3V3_S4_TPAD

1

R4858

10K

5%
1/20W
MF
201

2

R

1

R4859

10K

2

Apple Inc.

FF14A-30C-R11DL-B-3H

1

R4855

5%
1/20W
MF
201

5%
1/20W
MF
201

10K

5%
1/20W
MF
201

2

1

R4860

10K

5%
1/20W
MF
201

2

WS_KBD15_C

WS_KBD16N

1

C4810

0.1UF

20%
10V

2

CERM

402

=PP3V3_S4_TPAD

1

R4851

10K

5%
1/20W
MF
201

2

TBT

R4814

113

1 2

1%
1/16W
MF-LF

402

R4815

0

1 2

5%
1/16W
MF-LF

402

R4810

1K

1 2

5%
1/16W
MF-LF

402

36 37 68 71

1

R4852

10K

5%
1/20W
MF
201

2

SYNC_MASTER=JACK_J52 SYNC_DATE=01/28/2014

PAGE TITLE

Keyboard & Trackpad (1 of 2)

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

518S0752

CRITICAL

J4813

32

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

31

F-RT-SM

1

R4856

10K

5%
1/20W
MF
201

2

36 37 68 71

1

R4861

10K

5% 5%
1/20W
MF
201

2

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

48 OF 120

SHEET

36 OF 82

124578

8.0.0
dvt1

1

R4857

10K

5%
1/20W
MF
201

2

1

R4862

10K

1/20W
MF
201

2

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Keyboard Backlight Connector

516S0899

CRITICAL

J4915

AA07A-S010-VA1

F-ST-SM

12

D

KBDLED_CATHODE2

60 71

PPVOUT_S0_KBDBKLT

37 60 71

TP_KBKLT_NC

PIN 6 WAS USED KEYBOARD BKLT DETECTION

NOT USED ANYMORE

11

1

2

34
56
78

10

9

13
14

KBDLED_CATHODE1
PPVOUT_S0_KBDBKLT

J4915 PIN 5 IS GROUNDED

ON KEYBOARD BACKLIGHT FLEX

60 71

37 60 71

TPAD SPI WITH SRC TERMINATION

D

=TPAD_SPI_BUS_EN

36 71

=TPAD_SPI_CS_L

36 71

=TPAD_SPI_MISO

36 71

=TPAD_SPI_MOSI

36 71

=TPAD_SPI_SCLK

36 71

C

=PP3V3_S4_TPAD

13 18 31 37 38 64 66

IN

15

IN

From PCH

13 18 31 37 38 64 66

IN

15

IN

From PCH

36 37 68 71

BYPASS=U4810::3mm

PM_SLP_S4_L

TPAD_USB_IF_EN

NOSTUFF

1

R4910

100K

5%
1/20W
MF
201

2

PM_SLP_S4_L

TPAD_SPI_IF_EN

C4941

0.1UF

6.3V

CERM-X5R

0201

10%

1

2

CRITICAL

74LVC2G08GT/S505

8

1

A

U4910

2

08

B

4

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT/S505

8

5

A

U4910

6

08

B

4

CKPLUS_WAIVE=UNCONNECTED_PINS

B

TPAD_SPI_IF_EN_CONN

TRUE

TPAD_SPI_CS_CONN_L

TRUE

TPAD_SPI_MISO_R

TRUE

TPAD_SPI_MOSI_R

TRUE

TPAD_SPI_CLK_R

TRUE

SOT833

7

TPAD_VBUS_EN_R

Y

SOT833

3

TPAD_SPI_IF_EN_R

Y

=PP3V3_S0_TPAD

68

TPAD_SPI_CS_L

15 75

IN

From PCH

R4902

1 2

02010MF 5%

1 2

D

3

5%

MF15201

1/20W

1/20W

1

C4942

100PF

5%
25V

2

C0G
0201

1

C4943

100PF

5%
25V

2

C0G
0201

R4904

R4911

33 33

1 2

R4913

1 2

5%

1/20W

MF

201

33

TPAD_SPI_IF_EN_R_C

5%

1/20W

MF

201

=PP3V3_S4_TPAD

36 37 68 71

Q4960

1

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

S G

2

TPAD_VBUS_EN_R_C

SIGNAL_MODEL=TPAD_SPI_ISOL

R4903

1 2

2015%1/20W

MF

R4912

1 2

5%

1/20W

MF

201

R4914

33

1 2

1/20W

201

1

R4960

100K

5%
1/20W
MF
201

2

(TPAD_SPI_CS_CONN_L)

(TPAD_SPI_IF_EN_CONN)

5%
MF

TPAD_SPI_MISO
TPAD_SPI_MOSI

15

TPAD_SPI_CLK

TPAD_VBUS_EN

36 71

15 75

15 75

15 75

C

B

A

BOM_COST_GROUP=TRACKPAD

6 3

SYNC_MASTER=JACK_J52SYNC_DATE=01/31/2014

PAGE TITLE

Keyboard & Trackpad (2 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

.

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

49 OF 120

SHEET

37 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

U5000

LM4FSXAH5BB

LPC_AD<0>

14 71 75

BI

LPC_AD<1>

14 71 75

BI

LPC_AD<2>

14 71 75

BI

LPC_AD<3>

14 71 75

BI

LPC_CLK_SMC

17

IN

LPC_FRAME_L

14 71 75

IN

SMC_LRESET_L

18

IN

LPC_SERIRQ

15 71

BI

PM_CLKRUN_L

13 71

OUT

LPC_PWRDWN_L

13 71

IN

SMC_RUNTIME_SCI_L

13

OUT

SMC_WAKE_SCI_L

15

OUT

SMBUS_SMC_0_S0_SCL

41 79

BI

SMBUS_SMC_0_S0_SDA

41 79

BI

SMBUS_SMC_1_S0_SCL

41 71 79

BI

SMBUS_SMC_1_S0_SDA

41 71 79

BI

SMBUS_SMC_2_S3_SCL

41 71 79

BI

SMBUS_SMC_2_S3_SDA

41 71 79

BI

SMBUS_SMC_3_SCL

41 79

BI

SMBUS_SMC_3_SDA

41 79

C

B

BI

SMBUS_SMC_4_ASF_SCL

40

BI

SMBUS_SMC_4_ASF_SDA

40

BI

SMBUS_SMC_5_G3_SCL

41 71 79

BI

SMBUS_SMC_5_G3_SDA

41 71 79

BI

SMC_FAN_0_CTL

46

OUT

SMC_FAN_0_TACH

46

IN

SMC_FAN_1_CTL

40

OUT

SMC_FAN_1_TACH

40

IN

SMC_TOPBLK_SWP_L

40

OUT

SMC_SENSOR_PWR_EN

40

OUT

SMC_SYS_KBDLED

60

OUT

SMC_ACTUATOR_DISABLE_L

62

BI

SMC_5VSW_PWR_EN

40

OUT

SYS_ONEWIRE

53

IN

SMC_FAN_5_CTL

40

OUT

SMC_PCH_SUSACK_L

40

OUT

CPU_PECI_R

39 73

BI

SMC_PECI_L

39 73

OUT

SMC_BIL_BUTTON_L

40

IN

SMC_DP_HPD_L

39

IN

SMC_PME_S4_WAKE_L

40

IN

SMC_PME_S4_DARK_L

18 39

IN

SMC_S4_WAKESRC_EN

39 64

OUT

SMC_SENSOR_ALERT_L

39 40

IN

SMC_ACTUATOR_EN_L

40

IN

SMC_LID

36 39 40 71

IN

SMC_PCH_SUSWARN_L

40

OUT

SMS_INT_L

39

IN

SMC_BC_ACOK

39 53

IN

PM_SLP_S0_L

13 18

IN

PM_SLP_S3_L

13 17 18 64 66 71

IN

PM_SLP_S4_L

13 18 31 37 64 66

IN

PM_SLP_S5_L

13 64

IN

SMC_ONOFF_L

36 39 71

IN

SMC_RX_L

39 71

IN

SMC_TX_L

39 71

OUT

SMC_PWRFAIL_WARN_L

40

OUT

SMC_WIFI_PWR_EN

40

OUT

(OD)
(OD)

(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)

(OD)

(OD)

(OD)

(OD)

B13

LPC0AD0

A13

LPC0AD1

C12

LPC0AD2

D11

LPC0AD3

H12

LPC0CLK

D12

LPC0FRAME*

C13

LPC0RESET*

H13

LPC0SERIRQ

G11

LPC0CLKRUN*

F13

LPC0PD*

F12

LPC0SCI*

B12

PK5

E10

I2C0SCL

D13

I2C0SDA

M4

I2C1SCL

N2

I2C1SDA

N8

I2C2SCL

M8

I2C2SDA

L8

I2C3SCL

K8

I2C3SDA

N7

I2C4SCL

M7

I2C4SDA

N4

I2C5SCL

N3

I2C5SDA

H11

PM6/FAN0PWM0

L13

PM7/FAN0TACH0

C11

PK6/FAN0PWM1

A12

PK7/FAN0TACH1

G3

PN2/FAN0PWM2

D10

PN3/FAN0TACH2

L11

PN4/FAN0PWM3

N12

PN5/FAN0TACH3

N11

PN6/FAN0PWM4

M11

PN7/FAN0TACH4

J4

PH2/FAN0PWM5

J2

PH3/FAN0TACH5

C4

PECI0RX

C6

PECI0TX

M13

PP0/IRQ116

L12

PP1/IRQ117

M5

PP2/IRQ118

J12

PP3/IRQ119

J13

PP4/IRQ120

L5

PP5/IRQ121

D8

PP6/IRQ122

K6

PP7/IRQ123

D4

PQ0/IRQ124

E4

PQ1/IRQ125

F5

PQ2/IRQ126

N5

PQ3/IRQ127

N6

PQ4/IRQ128

K5

PQ5/IRQ129

M6

PQ6/IRQ130

L6

PQ7/IRQ131

L3

U0RX

M1

U0TX

E13

USB0DM

E12

USB0DP

(1 OF 2)

OMIT_TABLE

(PL7)
(PL6)

BGA

T3CCP1/PJ5/C2­T3CCP0/PJ4/C2+

SSI0CLK/PA2
SSI0FSS/PA3

SSI0RX/PA4
SSI0TX/PA5

U1TX/PB1
T0CCP0/PB6
T0CCP1/PB7

SSI1RX/PF0
SSI1TX/PF1

SSI1CLK/PF2
SSI1FSS/PF3

WT0CCP0/PG4
WT0CCP1/PG5

WT2CCP0/PH0
WT2CCP1/PH1

WT3CCP0/PH4
WT3CCP1/PH5
WT4CCP0/PH6
WT4CCP1/PH7

T1CCP0/PJ0
T1CCP1/PJ1
T2CCP0/PJ2
T2CCP1/PJ3

WT5CCP1/PM3

AIN00
AIN01
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN09
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
AIN17
AIN18
AIN19
AIN20
AIN21
AIN22
AIN23

PC5/C1+

U1RX/B0

C0­C0+
C1-

PF4
PF5

E2

SMC_ADC0

E1

SMC_ADC1

F2

SMC_ADC2

F1

SMC_ADC3

B3

SMC_ADC4

A3

SMC_ADC5

B4

SMC_ADC6

A4

SMC_ADC7

B5

SMC_ADC8

A5

SMC_ADC9

B6

SMC_ADC10

A6

SMC_ADC11

C1

SMC_ADC12

C2

SMC_ADC13

B1

SMC_ADC14

B2

SMC_ADC15

G2

SMC_ADC16

G1

SMC_ADC17

H1

SMC_ADC18

H2

SMC_ADC19

B7

SMC_ADC20

A7

SMC_ADC21

B8

SMC_ADC22

A8

SMC_ADC23

K2

CPU_PROCHOT_L

K1

SMC_VCCIO_CPU_DIV2

L2

SMC_S5_PWRGD_VIN

L1

SPI_DESCRIPTOR_OVERRIDE_L

C5

CPU_CATERR_L

D5

CPU_THRMTRIP_3V3

M2

SMC_PM_G2_EN

M3

PM_DSW_PWRGD

L4

SMC_DELAYED_PWRGD

N1

SMC_PROCHOT

F11

SMC_DEBUGPRT_RX_L

E11

SMC_DEBUGPRT_TX_L

F4

SMC_SYS_LED

F3

SMC_GFX_THROTTLE_L

M9

SPI_SMC_MISO

N9

SPI_SMC_MOSI

L10

SPI_SMC_CLK

K10

SPI_SMC_CS_L

L9

S5_PWRGD

K9

PM_PCH_SYS_PWROK

K7

SMC_DEBUGPRT_EN_L

L7

SMC_GFX_OVERTEMP

K3

ALL_SYS_PWRGD

K4

SMC_THRMTRIP

J3

PM_PWRBTN_L

H4

PM_SYSRST_L

H3

MEM_EVENT_L

G4

SMC_ADAPTER_EN

C9

SMC_OOB1_D2R_L

B9

SMC_OOB1_R2D_L

A9

SMC_CPU_DBGPWR_RD_L

C8

BDV_BKL_PWM

H10

PM_BATLOW_L

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

6

39 55 73

IN

39

IN

39

IN

17

OUT

6

73

IN

39

IN

39 64

OUT

13 75

OUT

17 26 27 39 75

OUT

39

OUT

35 39 74

IN

35 39 74

OUT

40

OUT

40

BI

47 75

IN

47 75

OUT

47 75

OUT

47 75

OUT

64

IN

13 16 17 75

IN

35

OUT

40

IN

16 17 64

IN

39

OUT

13 16 75

OUT

13 17 71 75

(OD)

OUT

40

BI

13 39

OUT

32

IN

32

OUT

40

OUT

40

OUT

13 27

OUT

=PP3V3_S5_SMC

1

C5002

1UF

20%

6.3V

2

X5R
0201

1

C5003

0.1UF

10%
10V

2

X5R-CERM
0201

1

C5007

0.1UF

10%
10V

2

X5R-CERM
0201

39 40 68

1

C5004

0.1UF

10%
10V

2

X5R-CERM
0201

1

C5008

0.1UF

10%
10V

2

X5R-CERM

1

C5005

0.1UF

10%
10V

2

X5R-CERM
0201

1

C5009

0.1UF

10%
10V

2

X5R-CERM
02010201

1

C5024

12PF

5%
25V

2

NP0-C0G
0201

1

C5006

0.1UF

10%
10V

2

X5R-CERM
0201

1

C5025

12PF

5%
25V

2

NP0-C0G
0201

L5001

30-OHM-1.7A

1 2

1

R5002

1M

5%
1/20W
MF
201

2

SMC_RESET_L

39 40 47

IN

54 71

WIFI_EVENT_L

66

BI

SMC_WAKE_L
NC_SMC_HIB_L

71

SMC_CLK32K

39

IN

NC_SMC_XOSC1

71

SMC_EXTAL

39

SMC_XTAL

39 39 71

PP1V2_S5_SMC_VDDC

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=1.2V

PLACE_NEAR=U5000.D6:5MM

1

C5010

1.0UF

20%

6.3V

2

X5R
0201-1

1

C5017

1.0UF

20%

6.3V

2

X5R
0201-1

0402

G10 C10

B11

(OD)

N13
M12

M10

N10

G12

G13

K12

D7
E6
E8
E9

F10

J7
J9

J10

J1
J6

K13

D6

PLACE_NEAR=U5000.K13:5MM

1

C5015

0.1UF

10%
10V

2

X5R-CERM
0201

PP3V3_S5_SMC_VDDA

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V

U5000

LM4FSXAH5BB

BGA

(2 OF 2)

RST*

PK4/RTCCLK
WAKE*
HIB*

XOSC0
XOSC1

OSC0
OSC1

VBAT

SWCLK/TCK
SWDIO/TMS

SWO/TDO

VDDA

VREFA+
VREFA-

GNDA

TDI

OMIT_TABLE

VDD

GND

VDDC

PLACE_NEAR=U5000.K13:5MM

1

C5016

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=U5000.J6:5MM

1

C5014

1.0UF

20%

6.3V

2

X5R
0201-1

SMC_TCK

A10

SMC_TMS

A11

SMC_TDO

B10

SMC_TDI

A2

NC

NC

D3

D2

PP3V3_S5_AVREF_SMC

D1

44
42 43
40

C3

GND_SMC_AVSS

39

E3

A1
C7
D9
E5
F9
H5
H9
J5
J8
J11

K11

PLACE_NEAR=U5000.J6:5MM

1

C5012

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=U5000.J1:5MMPLACE_NEAR=U5000.D6:5MM

1

C5013

0.1UF

10%
10V

2

X5R-CERM
0201

1

C5001

0.1UF

10%
10V

2

X5R-CERM
0201

39 47 71

39 47 71

39 71

39 71

PLACE_NEAR=U5000.A1:4MM

1

C5020

0.01UF

10%
10V

2

X5R-CERM
0201

BYPASS=U5000.D2:D1:1MM

PLACE_NEAR=U5000.J1:5MM

1

C5011

0.1UF

10%
10V

2

X5R-CERM
0201

XW5000

SM

BYPASS=U5000.D2:D1:1MM

12

1

C5021

1UF

20%

6.3V

2

X5R
0201

D

C

B

NOTE:
SMS INTERRUPT IS NOT USED, PULL UP TO SMC RAIL.

A

NOTE:
Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

6 3

BOM_COST_GROUP=SMC

SYNC_MASTER=JACK_J52 SYNC_DATE=11/07/2013

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SMC

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

50 OF 120

SHEET

38 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

SMC Reset "Button", Supervisor & AVREF Supply

CPU_PROCHOT_L

6

38 55 73

38 39 53

BI

PLACE_NEAR=Q5159.6:5MM

PM_THRMTRIP_L

15 39 75

OUT

38 39

OUT

1

C5131

47PF

5%

25V

2

C0G

0201

CPU_THRMTRIP_3V3

CRITICAL

Q5158

MMBT3904LP-7

DFN1006-3

R5127

0

=PP3V3_S5_SMC

38 39 40
68

D

Desktops: 5V
Mobiles: 3.42V

SMC_TPAD_RST_L

36

IN

SMC_ONOFF_L

36 38 39 71

IN

SMC_MANUAL_RST_L

OMIT

1

R5101

0

5%
1/10W
MF-LF
603

2

SILK_PART=SMC_RST

PLACE_SIDE=BOTTOM

MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
NOTE: Internal pull-ups are to VIN, not V+.

Debug Power "Buttons"

R5116

PLACE_SIDE=BOTTOM

C

SILK_PART=PWR_BTN

1 2

5%
1/16W
MF-LF

402

GND_SMC_AVSS

38 39 40 42 43 44

=PPVIN_S5_SMCVREF

68

OMIT

1

0

5%
1/10W
MF-LF

603

2

1

2

C5120

0.47UF

CERM-X5R

C5101

0.01UF

10%
10V

X5R-CERM

0201

SMC_ONOFF_L

OMIT

1

R5115

0

PLACE_SIDE=TOP

5%
1/10W
MF-LF
603

2

SILK_PART=PWR_BTN

PP3V42_G3H_SMC_SPVSR

4.7UF

20%

6.3V
X5R
402

10%

402

1

2

1

2

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.42V

1

V+

VREF-3.3V-VDET-3.0V

6

MR1*

(IPU)

7

MR2*

(IPU)

4

DELAY

GND

2

36 38 39 71

OUT

NOSTUFF

C5127

6.3V

U5110

DFN

SN0903049

CRITICAL

3

VIN

RESET*

REFOUT

THRM

PAD

9

5

8

C5125

10UF

20%
10V

X5R-CERM

0402-1

1

R5100

100K

5%
1/20W
MF
201

2

SMC_RESET_L
PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V

1

1

C5126

0.01UF

10%
10V

2

2

X5R-CERM
0201

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V

OUT

38 71

38 39 40 42 43 44

38 40 47 54 71

=CHGR_ACOK

54

SMC_BC_ACOK

MAKE_BASE=TRUE

SIGNAL_MODEL=DMN5L06VK_7

Q5159

6

D

DMN5L06VK-7

SOT563

VER 3

2

S G

1

SMC_PROCHOT

SIGNAL_MODEL=DMN5L06VK_7

Q5159

3

D

DMN5L06VK-7

SOT563

VER 3

5

S G

4

SMC_THRMTRIP

3

1

2

PM_THRMTRIP_R_L

75

38

IN

38 39

IN

R5158

3.3K

1 2

5%

1/20W

MF

201

SMC_PECI_L

38 73

IN

From SMC

PM_THRMTRIP_L

SMC12 PECI Support

SIGNAL_MODEL=CPU_PECI_FET

R5152

0

1 2

5%

1/20W

MF

0201

38 73

To SMC

15 39 75

IN

CRITICAL

Q5150

DMN32D2LFB4

DFN1006H4-3

SMC_PECI_L_R

CPU_PECI_R

OUT

SYM_VER_2

NOSTUFF

1

R5153

1.6K

5%
1/20W
MF
201

2

1

2

=PP1V05_S0_SMC

3

D

1

G S

2

1

R5151

330

5%
1/20W
MF
201

2

R5134

1 2

NOSTUFF

C5134

47PF

5%
25V
C0G
0201

PLACE_NEAR=Q5150.2:5MM

1/20W

201

39 68

D

43

CPU_PECI

5%
MF

From/To CPU/PCH

6

BI

73

C

=PP3V3_S5_SMC

38 39 40 68

SMC Crystal Circuit

SMC USB Clock require these crystal
values:5,6,8,10,12,16,18,20,24,25 MHz

SMC_PME_S4_DARK_L

18 38 39

R5110

2.49K

SMC_XTAL

38

SMC_EXTAL

38

1 2

1%

1/20W

MF

201

1

2

B

SMC_XTAL_R

CRITICAL

Y5110

12.000MHZ-30PPM-10PF-85C

C5110

12PF

5%
25V
CERM
0201

3.2X2.5MM-SM

1 3

2 4

NCNC

1

C5111

12PF

5%
25V

2

CERM
0201

SMC_PME_S4_DARK_L

18 38 39

MAKE_BASE=TRUE

PM_CLK32K_SUSCLK_R

13

IN

PLACE_NEAR=U0500.AE6:5.1mm

R5112

22

1 2

=TBT_WAKE_L

SMC_CLK32K

1/20W

25

IN

=PP1V05_S0_SMC

39 68

38

MF 2015%

OUT

SMC_VCCIO_CPU_DIV2

38

SMC_DP_HD_L IS NOT USED ANY MORE

1

R5197

100K

1%
1/20W
MF
201

2

1

R5196

100K

1%
1/20W
MF
201

2

SMC_DP_HPD_L

38

SMC_ONOFF_L

36 38 39 71

SMC_SENSOR_ALERT_L

38 40

SMC_LID

36 38 40 71

SMC_TX_L

38 71

SMC_RX_L

38 71

SMC_DEBUGPRT_TX_L

35 38 74

SMC_DEBUGPRT_RX_L

35 38 74

SMC_TMS

38 47 71

SMC_TDO

38 71

SMC_TDI

38 71

SMC_TCK

38 47 71

SMC_BC_ACOK

38 39 53

SMC_S5_PWRGD_VIN

38

SMS_INT_L

38

CPU_THRMTRIP_3V3

38 39

SMC_PM_G2_EN

38 64

SMC_ADAPTER_EN

13 38

SMC_THRMTRIP

38 39

SMC_DELAYED_PWRGD

17 26 27 38 75

SMC_S4_WAKESRC_EN

38 64

R5167
R5168

R5170
R5172
R5171
R5173
R5174
R5175
R5176
R5177
R5178
R5179
R5180

R5187

R5192

R5193

R5117

R5198
R5185
R5186

R5191
R5190

=PP3V3_S4_SMC

18 40 68

=PP3V3_S0_SMC

68

100K

1 2

100K

1 2

10K

1 2

10K

1 2

100K

1 2

10K

1 2

100K

1 2

20K

1 2

20K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

100K

1 2

100K

1 2

10K

1 2

100K

1 2

100K

1 2

10K

1 2

10K

1 2

100K

1 2

100K

1 2

1/20W
1/20W

1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W

1/20W
1/20W
1/20W

1/20W

1/20W
1/20W
1/20W

1/20W

1/20W

MF 2015%
MF 2015%

MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%

MF 2015%
MF 2015%
MF 2015%

MF 2015%

MF 2015%
MF 2015%
MF 2015%

MF 2015%

MF 2015%

B

A

SYNC_MASTER=JACK_J52

PAGE TITLE

SMC Shared Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SMC

IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=10/24/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

51 OF 120

SHEET

39 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

SMC12 ADC Assignments

SMC_ADC0

38

OUT

SMC_ADC1

38

OUT

SMC_ADC2

38

OUT

SMC_ADC3

38

OUT

SMC_ADC4

38

OUT

SMC_ADC5

38

D

C

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SMC_ADC6
SMC_ADC7
SMC_ADC8
SMC_ADC9
SMC_ADC10
SMC_ADC11
SMC_ADC12
SMC_ADC13
SMC_ADC14
SMC_ADC15
SMC_ADC16
SMC_ADC17
SMC_ADC18
SMC_ADC19
SMC_ADC20
SMC_ADC21
SMC_ADC22
SMC_ADC23

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_BMON_DISCRETE_ISENSE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_OTHER5V_HI_ISENSE

MAKE_BASE=TRUE

SMC_OTHER3V3_HI_ISENSE

MAKE_BASE=TRUE

SMC_DDR_ISENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_TPAD_ISENSE

MAKE_BASE=TRUE

SMC_DDR1V8_ISENSE

MAKE_BASE=TRUE

SMC_SSD_ISENSE

MAKE_BASE=TRUE

SMC_PP3V3S0_ISENSE

MAKE_BASE=TRUE

SMC_CAMERA_ISENSE

MAKE_BASE=TRUE

SMC_TPAD_VSENSE

MAKE_BASE=TRUE

SMC_PP5VS0_ISENSE

MAKE_BASE=TRUE

SMC_CPUDDR_ISENSE

MAKE_BASE=TRUE

SMC_PCH_ISENSE

MAKE_BASE=TRUE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_LCDPANEL_ISENSE

MAKE_BASE=TRUE

SMC_CPU_IMON_ISENSE

MAKE_BASE=TRUE

SMC_TBT_ISENSE

MAKE_BASE=TRUE

42

IN

42

IN

42

IN

42

IN

42

IN

44

IN

43

IN

42

IN

42

IN

43

IN

42

IN

42

IN

43

IN

43

IN

43

IN

44

IN

42

IN

43

IN

43

IN

43

IN

44

IN

44

IN

44

IN

44

IN

PCH_SML1ALERT_L

14

IN

SMC_CPUHI_COMP_ALERT_L

43

IN

SMC_BMON_COMP_ALERT_L

44

IN

CPUTHMSNS_THM_L

45

IN

CPUTHMSNS_ALERT_L

45

IN

TBTTHMSNS_THM_L

45

IN

TBTTHMSNS_ALERT_L

45

IN

SMC12 Pin Assignments

SMBUS_SMC_4_ASF_SCL

38

SMBUS_SMC_4_ASF_SDA

38

BDV_BKL_PWM

38

SMC_SYS_LED

38

SMC_GFX_THROTTLE_L

38

SMC_GFX_OVERTEMP

38

SMC_FAN_1_CTL

38

SMC_FAN_1_TACH

38

SMC_5VSW_PWR_EN

38

SMC_FAN_5_CTL

38

SMC_BIL_BUTTON_L

38

MEM_EVENT_L

38

SMC_PWRFAIL_WARN_L

38

B

SMC_PCH_SUSWARN_L

38

IN

MAKE_BASE=TRUE

SMC_PCH_SUSACK_L

38

OUT

MAKE_BASE=TRUE

SMC_SENSOR_PWR_EN

38 40

MAKE_BASE=TRUE

SMC_WIFI_PWR_EN

38 40

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NC_SMC_TPAD_BOOST_DISABLE_L

MAKE_BASE=TRUE

NC_SMC_SYS_LED

MAKE_BASE=TRUE

NC_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

NC_SMC_GFX_OVERTEMP

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

MAKE_BASE=TRUE

NC_SMC_5VSW_PWR_EN

MAKE_BASE=TRUE

NC_SMC_FAN_5_CTL

MAKE_BASE=TRUE

NC_SMC_BIL_BUTTON_L

MAKE_BASE=TRUE

NC_MEM_EVENT_L

MAKE_BASE=TRUE

NC_SMC_PWRFAIL_WARN_L

MAKE_BASE=TRUE

R5230

0

1 2

1/20W

R5231

1 2

1/20W

PCH_SUSWARN_L

5%
MF

0201

0

PCH_SUSACK_L

5%
MF

0201

P3V3S4SW_SNS_EN
PBUSVSENSE_EN

PM_WLAN_EN

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

SMC_CPU_DBGPWR_RD_L

38

13

OUT

36 71

IN

13

IN

63

42

66

31

IN

Thermal Alerts

NOSTUFF

R5215

100

1 2

5%

1/20W

MF

201

CPUHYS

R5217

100

1 2

5%

1/20W

MF

201

BMONHYS

R5213

100

1 2

5%

1/20W

MF

201

R5216

100

1 2

5%

1/20W

MF

R5214

201

100

1 2

5%

1/20W

100

5%
MF

201

MF

201

R5210

100

1 2

5%

1/20W

MF

201

=PP3V3_S5_SMC

38 39 68

R5220

1 2

1/20W

SMC_BOARDID

MAKE_BASE=TRUE

S4 SMC Wake Sources

=TPAD_WAKE_L

BT_WAKE_L

CPUTHRM_THRM:SMC

CPUTHRM_ALRT:SMC

TBTTHRM_THRM:SMC

TBTTHRM_ALRT:SMC

SMC_SENSOR_ALERT_L

1

R5232

10K

5%
1/20W
MF
201

2

SMCBOARDID:16

1

R5233

10K

5%
1/20W
MF
201

2

SMCBOARDID:8

38 39

OUT

=PP3V3_S4_SMC

1

R5282

100K

5%
1/20W
MF
201

2

SMC_PME_S4_WAKE_L

Hall Effect Pads

APN: 998-00296

OMIT_TABLE

J5250

HALL-EFFECT-MLB-J44

PART NUMBER

677-01216

QTY

1

639-00525 (PCBA,HALL EFFECT,X304) REPORTS TO 677-01216

Specify one of these BOM GROUPs.

BOM GROUP

CPUTHRM:BOTH
CPUTHRM:THRM
CPUTHRM:ALRT
CPUTHRM:NONE

Specify one of these BOM GROUPs.

BOM GROUP

TBTTHRM:BOTH
TBTTHRM:THRM
TBTTHRM:ALRT
TBTTHRM:NONE

Requires EMC1412-1 or EMC1412-2 instead of EMC1412-A, new APN needs to be created.

18 39 40 68

38

MAKE_BASE=TRUE

OUT

SM

1
2
3
4 5

8
7
6

NC

NC

DESCRIPTION

SUBASSY,PCBA,HALL EFFECT,X304

SMC_WIFI_PWR_EN

38 40

SMC_SENSOR_PWR_EN

38 40

NC

NC

=PP3V42_G3H_HALL

SMC_LID_R

R5250

1 2

1/16W
MF-LF

402

68

0

5%

SMC_LID

1

C5250

0.001UF

10%
50V

2

X7R-CERM
0402

REFERENCE DES

J5250

BOM OPTIONS

CPUTHRM_THRM:SMC,CPUTHRM_ALRT:SMC

CPUTHRM_THRM:SMC,CPUTHRM_ALRT:PU
CPUTHRM_THRM:PU,CPUTHRM_ALRT:SMC

CPUTHRM_THRM:PU,CPUTHRM_ALRT:PU

BOM OPTIONS

TBTTHRM_THRM:SMC,TBTTHRM_ALRT:SMC

TBTTHRM_THRM:SMC,TBTTHRM_ALRT:PU
TBTTHRM_THRM:PU,TBTTHRM_ALRT:SMC

TBTTHRM_THRM:PU,TBTTHRM_ALRT:PU

R5295
R5294

10K

10K

CRITICAL

CRITICAL

18 39 40 68

1 2

NOSTUFF

1 2

NOSTUFF

36 38 39 71

=PP3V3_S4_SMC

5%

5%

BOM OPTION

MF 201

1/20W

MF 201

1/20W

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

D

C

B

MF

1 2

201

100

TPAD_ACTUATOR_EN_RC_L

1%

MAKE_BASE=TRUE

1/20W

1

C5271

220PF

10%
25V

2

X7R-CERM
201

SMC_ACTUATOR_EN_L

38

NOSTUFF

C5270

1000PF

X7R-1

10%
16V

0201

SMC_RESET_L

1

2

GND_SMC_AVSS

38 39 47 54 71

38 39 42 43 44

BOM_COST_GROUP=SMC

PAGE TITLE

SMC Project Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

52 OF 120

SHEET

40 OF 82

SIZE

A

D

124578

A

Top Block Swap

SMC_TOPBLK_SWP_L

38

IN

R5296

1/20W

201

=PP3V3R1V8_S0_PCH_VCCSDIO

1

1K

5%
MF

R5283

2

1K

1 2

PCH_STRP_TOPBLK_SWP_L

5%

1/20W

MF

201

8

11 68

15

OUT

TPAD_ACTUATOR_EN_L

36 42 71

IN

R5297

RC Placeholder to filter noise
on this signal towards SMC IO.

6 3

8 7 6 5 4 3

12

WILDCAT POINT LP S0 "SMBus 0" Connections

=PP3V3_S0_SMBUS_PCH

41 68

1

1

201

R5301

1K

1K

5%5%
1/20W
MF

MF

201

2

2

HDMI Redriver (on RIO)

(WRITE: 0xCC READ: 0xCD)

J9510

=I2C_HDMIRDRV_SCL
=I2C_HDMIRDRV_SDA

(MASTER)

66

66

SMBUS_SMC_0_S0_SCL

38 79

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

38 79

MAKE_BASE=TRUE

WILDCAT POINT LP

U0500

(MASTER)

SMBUS_PCH_CLK

14 71 75 38 71 79

D

MAKE_BASE=TRUE

SMBUS_PCH_DATA

14 71 75 38 71 79

MAKE_BASE=TRUE

R5300

1/20W

SMC SMBus "0" S0 Connections

PP3V3_S0_EDP_SW

15 65

1

1

SMC

U5000

R5350

2.0K

1/20W

201

R5351

2.0K

5%
MF

5%
1/20W
MF
201

2

2

Internal DP

J8300

(See Table)

=I2C_TCON_SCL
=I2C_TCON_SDA

65 71

65 71

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

MAKE_BASE=TRUE

SMC SMBus "5" G3H Connections

=PP3V42_G3H_SMBUS_SMC_5

68

1

SMC

U5000

(MASTER)

R5380

2.0K

1/20W

201

5%
MF

2

1

R5381

2.0K

5%
1/20W
MF
201

2

Battery Charger

ISL6259 - U7100

(Write: 0x12 Read: 0x13)

=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA

54

54

D

Battery

Battery
Battery Manager - (Write: 0x16 Read: 0x17)

J7050

(See Table)

=SMBUS_BATT_SCL
=SMBUS_BATT_SDA

53

53

SMC SMBus "3" S0 Connections

=PP3V3_S0_SMBUS_SMC_3

68

Internal DP

Parade T-con - (0x10-0x2F or 0x30-0x4F) Y Y

XDP Connectors

C

J1800

(MASTER)

=SMBUS_XDP_SCL

16

=SMBUS_XDP_SDA

16

SMC SMBus "2" S3 Connections

=PP3V3_S4_SMBUS_SMC_2

68

SMC

U5000

(MASTER)

SMBUS_SMC_2_S3_SCL

38 71 79

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

38 71 79

MAKE_BASE=TRUE

J44

Samsung LGD

1

1K 1K

5%
MF

201

2

1

R5371

5%
1/20W
MF
201

2

R5370

1/20W

Trackpad

(Write: 0x98 Read: 0x99)

J4802

=I2C_TPAD_SCL
=I2C_TPAD_SDA

36 71

36 71

SMC

U5000

(MASTER)

SMBUS_SMC_3_SCL

38 79

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

MAKE_BASE=TRUE

R5390

2.0K

1/20W

201

1

1

R5391

2.0K

5%

5%

1/20W
MF

MF

201

2

2

C

X29 Temp (on RIO)

TMP105: J9510

(Write: 0x92 Read: 0x93)

=I2C_X29THMSNS_SCL
=I2C_X29THMSNS_SDA

TBT & MLB Prox

EMC1412: U5850

(Write: 0xD8 Read: 0xD9)

=I2C_TBTTHMSNS_SCL
=I2C_TBTTHMSNS_SDA

66

66

45

45

B

WILDCAT POINT LP S0 "SMLink 0" Connections

WILDCAT POINT LP

(MASTER)

SML_PCH_0_CLK

14 75

MAKE_BASE=TRUE

SML_PCH_0_DATA

14 75

MAKE_BASE=TRUE

WILDCAT POINT LP S0 "SMLink 1" Connections

WILDCAT POINT LP

A

(Write: 0x88 Read: 0x89)

SML_PCH_1_CLK

14 75

SML_PCH_1_DATA

14 75

SMLink 1 is slave port to
access PCH.

U0500

U0500

=PP3V3_S0_SMBUS_PCH

41 68

R5310

8.2K

1/20W

201

B

SMC SMBus "1" S0 Connections

1

1

R5311

8.2K

5%

5%
1/20W

MF

MF
201

2

2

SMC

U5000

(MASTER)

SMBUS_SMC_1_S0_SCL

38 71 79

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

38 71 79

MAKE_BASE=TRUE

6 3

=PP3V3_S0_SMBUS_SMC_1

68

R5360

2.0K

1/20W

201

1

1

R5361

2.0K

5%
MF

5%
1/20W
MF
201

2

2

CPU, Mem, Airflow,

Fixstack Prox

EMC1704-02: U5870

(Write: 0x98 Read: 0x99)

=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA

45

45

ALS

(Write: 0x72 Read 0x73)

J4002

=I2C_ALS_SCL
=I2C_ALS_SDA

34

34

SIZE

A

D

BOM_COST_GROUP=SMC

SYNC_MASTER=GKOO_J52 SYNC_DATE=12/06/2013

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SMBus Connections

Apple Inc.

R

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

53 OF 120

SHEET

8.0.0
dvt1

41 OF 82

124578

8 7 6 5 4 3

PBUS Voltage Sense & Enable (VP0R)

Gain: 0.167x

CPU High Side Current Sense (IC0R)

Gain: 100x, EDP: 10.5 A
Rsense: 0.003 (R5400)
Vsense: 31.5 mV, Range: 11 A
SMC ADC: 00

=PPVIN_S5_HS_COMPUTING_ISNS

68

D

=PPVIN_S5_HS_COMPUTING_ISNS_R

68

OTHER 5V High Side Current Sense (IO5R)

Gain: 100x, EDP: 6 A
Rsense: 0.005 (R5410) or Rsense SHORT
Vsense: 30 mV, Range: 6.6 A
SMC ADC: 07

=PPVIN_S5_HS_OTHER5V_ISNS

58 68

R5400

0.003

CRITICAL

R5410

Short Rsense

OMIT

0612-SHORT

=PPVIN_S5_HS_OTHER5V_ISNS_R

68

CRITICAL

PLACE_NEAR=U5400.5:10MM

80

123

ISNS_HS_COMPUTING_N

44

1%

80

1W

ISNS_HS_COMPUTING_P

44

CYN

0612

4

PLACE_NEAR=U5400.4:10MM

PLACE_NEAR=U5410.5:10MM

123

ISNS_HS_OTHER5V_N

80

0

0

1 W

MF

ISNS_HS_OTHER5V_P

80

4

PLACE_NEAR=U5410.4:10MM

C

OTHER 3.3V High Side Current Sense (IO3R)

Gain: 200x, EDP: 5 A
Rsense: 0.003 (R5440) or Rsense SHORT
Vsense: 15 mV, Range: 5.5 A
SMC ADC: 08

=PPVIN_S5_HS_OTHER3V3_ISNS

58 68

R5440

Short Rsense

OMIT

=PPVIN_S5_HS_OTHER3V3_ISNS_R

68

LCD Backlight Current Sense (IBLC)

Gain: 100x. EDP: 0.9 A
Rsense: 0.025 (R7700)

B

Vsense: 22.5 mV, Range: 1.32 A
SMC AD: 10

0.003

0612-SHORT

CRITICAL

PLACE_NEAR=U5440.5:10MM

123

ISNS_HS_OTHER3V3_N

80

1%
1W
MF

ISNS_HS_OTHER3V3_P

80

4

PLACE_NEAR=U5440.4:10MM

PLACE_NEAR=U7700.2:10MM

ISNS_LCDBKLT_N

60 80

IN

ISNS_LCDBKLT_P

60 80

IN

PLACE_NEAR=U7700.1:10MM

Trackpad Actuator X239 Current Sense (ITPC)

Gain: 4.99x, EDP: 2.61 A (Transient)
Rsense: 0.02 (R5460)
Vsense: 261 mV, Range: 5 A
SMC ADC: 11

=PPVIN_X239_PBUS_ISNS_R

68

IN

ISNS_TPAD_P

80

A

=PP3V3_S4_ISNS

42 43 44 68

C5460

TPADISNS

BYPASS=U5460.5::5MM

0.1UF

CERM

20%
10V

402

1

2

=PP3V3_S0_HS_COMPUTING_ISNS

43 68

3

V+

U5400

INA214

5

SC70

IN-

100x

4

IN+ REF

GND

2

CRITICAL

=PP3V3_S4_HS_OTHER_ISNS

42 68

3

V+

U5410

INA214

5

SC70

IN-

100x

4

IN+ REF

GND

OTHERISNS
CRITICAL

=PP3V3_S4_HS_OTHER_ISNS

42 68

5

4

OTHERISNS
CRITICAL

=PP3V3_S4_ISNS

42 43 44 68

LOADISNS
CRITICAL

CRITICAL

R5460

0612-SHORT

1 2
3 4

VIN+ VIN-

U5460

INA139

V+

TPADISNS
CRITICAL

0.001

1%
1W
MF

3 4

SOT23-5

GND

2

Short Rsense

OMIT

=PPVIN_X239_PBUS_ISNS

PLACE_NEAR=U5460.4:3MMPLACE_NEAR=U5460.3:3MM

ISNS_TPAD_N

80

OUT

2

3

V+

U5440

INA210

SC70

IN-

200x

GND

2

U5450

INA214

5

SC70

IN-

100x

4

IN+ REF

GND

15

ISNS_X239_IOUT_BUF

1

R5461

24.9K

1%
1/16W
MF-LF
402

2

TPADISNS

Gain: 200uA/V * 24.9KOhm = 4980

43

(to CPU High Side Threshold
Alert circuit)

PLACE_NEAR=U5000.E2:5MM

R5409

4.53K

1 2

1/20W

SMC_CPU_HI_ISENSE

1%

1

MF

201

2

C5409

0.22UF

20%

6.3V
X5R
0201

PLACE_NEAR=U5000.E2:5MM

OUT

1

C5401

0.1UF

20%
10V

2

CERM
402

BYPASS=U5400.3:2:5MM

6

CPUHI_IOUT

1

1

R5405

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U5400.6:5MM

GND_SMC_AVSS

OTHERISNS
BYPASS=U5410.3:2:5MM

1

C5411

0.1UF

OUT

6

1

20%
10V

2

CERM
402

HS_OTHER5V_IOUT

1

R5415

15K

1%
1/20W
MF
201

2

OTHERISNS
PLACE_NEAR=U5410.6:5MM

OTHERRC:YES
PLACE_NEAR=U5000.A4:5MM

R5419

4.53K

1 2

1/20W

SMC_OTHER5V_HI_ISENSE

1%

1

201

MF

C5419

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U5000.A4:5MM

OTHERRC:YES

GND_SMC_AVSS

OTHERISNS
BYPASS=U5440.3:2:5MM

1

C5441

0.1UF

20%
10V

2

CERM
402

6

HS_OTHER3V3_IOUT

OUT

1

1

REFIN+

R5445

15K

1%
1/20W
MF
201

2

OTHERISNS
PLACE_NEAR=U5440.6:5MM

PART NUMBER

LOADISNS

1

C5450

3

V+

OUT

2

0.1UF

20%
10V

2

CERM
402

BYPASS=U5450.3:2:5MM

6

ISNS_LCDBKLT_IOUT

1

1

R5455

6.04K

1%
1/20W
MF
201

2

LOADISNS
PLACE_NEAR=U5450.6:5MM

OTHERRC:YES
PLACE_NEAR=U5000.B5:5MM

R5449

4.53K

1 2

1%

1/20W

MF

201

QTY

117S0008
117S0008
117S0008

LOADRC:YES

R5459

4.53K

1 2

1%

1/20W

MF

201

SMC_OTHER3V3_HI_ISENSE

1

C5449

0.22UF

20%

6.3V

2

X5R
0201

OTHERRC:YES
PLACE_NEAR=U5000.B5:5MM

GND_SMC_AVSS

DESCRIPTION

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

2
1

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

1

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

PLACE_NEAR=U5000.B6:5MM

SMC_LCDBKLT_ISENSE

1

C5459

0.22UF

20%

6.3V

2

X5R
0201

LOADRC:YES
PLACE_NEAR=U5000.B6:5MM

GND_SMC_AVSS

OUT

R5464

1 2

1/16W
MF-LF

402

TPADISNS

=PP3V3_S4_ISNS

42 43 44 68

C5461

0.1UF

NOSTUFF

BYPASS=U5461.5::5MM

68

0

5%

20%
10V

CERM

402

ISNS_X239_IOUT_D

3

+

4

-

1

2

5

V+

V-

2

NOSTUFF
CRITICAL

U5461

OPA340NA

SOT-23

1

CRITICAL

BAT54DW-X-G

NOSTUFF

OUT

40

OUT

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

NOSTUFF

C5463

2200PF

1 2

ISNS_X239_PEAK_CAP

NOSTUFF

D5461

SOT-363
1 6

NC NC

5 2

CRITICAL

D5461

BAT54DW-X-G

42 43 44 68

68

REFERENCE DES

C5419,C5449

C5459
C5469

ISNS_X239_PEAK_R

NOSTUFF

R5463

1/16W
MF-LF

1

39

5%

402

2

PLACE_NEAR=U5462:5MM

5%

10V

ISNS_X239_PEAK_FBK

CERM
0402

SOT-363

4 3

NCNC

=PP3V3_S4_ISNS

C5462

0.1UF

20%
10V

CERM

TPADISNS

BYPASS=U5462.5::5MM

402

=PPBUS_S0_VSENSE

64

IN

68

Charger (BMON) Current Sense (IPBR)

Charger Gain: 36x, EDP: 8 A
Rsense: 0.005 (R7150)
SMC ADC: 02

54

IN

CHGR_BMON

CRITICAL

3

D

Q5460

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

NOSTUFF

1

GS

2

TPAD_ACTUATOR_EN_L

NOSTUFF

R5462

100

1 2

1%
1/16W
MF-LF

402

ISNS_X239_IOUT

CRITICAL

5

3

+

V+

V-

4

-

2

TPADISNS

1

2

Vnominal: 12.6 V, Range: 19.7 V
SMC ADC: 01

Enables PBUS VSense
divider when in S0.

PBUSVSENSE_EN

40

IN

XW5480

SM

1 2

PLACE_NEAR=R5400.1:10 MM

PBUS_S0_VSENSE_IN

1

R5481

100K

1%
1/16W
MF-LF

402

2

DC In Voltage Sense & Enable (VD0R)

Gain: 0.148x
Vnominal: 16.5 V, Range: 22.29 V
SMC ADC: 04

Enables DC-In VSense
divider when AC present.

DCINVSENSE_EN

=PPDCIN_S5_VSENSE

1

R5491

69.8K

1%
1/16W
MF-LF

402

2

PLACE_NEAR=U5000.F2:5MM

R5429

300K

1 2

1/20W

BOM OPTION

OTHERRC:NO

LOADRC:NO
TPADRC:NO

SMC_BMON_ISENSE

1%
MF

1

201

C5429

3300PF

10%
10V

2

GND_SMC_AVSS

Trackpad Actuator X239 Voltage Sense (VTPC)

Gain: 0.10771
Vnominal: 28 V, Range: 30.64 V
SMC ADC: 16

PLACE_NEAR=U5000.F2:5MM

X7R-CERM
0201

PPVIN_S4_TPAD_FUSE

36

Final Filter RC TBD

=PP3V3_S4_ISNS

42 43 44 68

10K

ISNS_X239_INT_NI

1%
MF

201

NOSTUFF

D

Q5461

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

1

GS

TPAD_ACTUATOR_EN_L

0

ISNS_X239_IOUT_INT

5%
1/16W
MF-LF

402

NOSTUFF

1

R5470

47

5%
1/20W
MF
201

2

NOSTUFF

1

C5464

0.15UF

10%

6.3V

2

X5R
0201

TPADRC:YES

R5468

10K

1 2

1%

1/20W

MF

201

PLACE_NEAR=U5000.A6:5MM

TPADRC:YES

IN

ISNS_X239_INT_DIS

U5462

OPA340NA

SOT-23

1

TPADRC:YES

R5465

1 2

1/20W

42
36
40
71

3

2

R5471

1 2

NOSTUFF

CRITICAL

Q5480

NTUD3169CZ

N-CHANNEL

2

1

5

4

P-CHANNEL

CRITICAL

Q5490

NTUD3169CZ

SOT-963

N-CHANNEL

G

2

1

G

5

4

P-CHANNEL

PDCINVSENS_EN_L_DIV

OUT

NOSTUFF

R5466

10K

1 2

1/20W

201

TPADRC:YES

5

3

+

V+

V-

4

-

2

TPADRC:YES

R5467

10K

1 2

1/20W

201

ISNS_X239_INT_I

36 40 42 71

R5469

4.53K

1 2

1%

1/20W

MF

201

SOT-963

G

G

6

D

S

D

S

PBUSVSENS_EN_L

3

PBUS_S0_VSENSE

PBUSVSENS_EN_L_DIV

6

D

S

D

S

40

38 39 40 42 43 44

1%
MF

DCINVSENS_EN_L

3

DCIN_S5_VSENSE

DC-IN (AMON) Current Sense (ID0R)

Charger Gain: 20x, EDP: 4.6 A
Rsense: 0.020 (R7120)
SMC ADC: 03

54

IN

XW5470

SM

1 2

VOUT_X239_DIV

CRITICAL

U5463

OPA340NA

SOT-23

1

1%
MF

ISNS_X239_IOUT_INT

SMC_TPAD_ISENSE

1

C5469

0.22UF

20%

6.3V

2

X5R
0201

TPADRC:YES

PLACE_NEAR=U5000.A6:5MM

GND_SMC_AVSS

38 39 40
42 43 44

BOM_COST_GROUP=SENSORS

1

R5482

100K

1%
1/16W
MF-LF

402

2

PLACE_NEAR=U5000.E1:5MM

R5488

27.4K

1%
1/16W
MF-LF

402

R5489

5.49K

1%
1/16W
MF-LF

402

1

R5492

200K

1%
1/16W
MF-LF

PLACE_NEAR=U5000.B3:5MM

402

2

1

R5498

31.6K

1%
1/16W
MF-LF

402

2

1

R5499

5.49K

1%
1/16W
MF-LF

402

2

PLACE_NEAR=U5000.F1:5MM

R5439

45.3K

CHGR_AMON

1 2

1%

1/20W

MF

201

VOUT_X239_XW

1

R5477

84.5K

1%

PLACE_NEAR=U5000.G2:5MM

1/20W
MF
201

2

R5479

4.53K

1 2

10.2K

1%
1/20W
MF
201

1/20W

1

R5478

2

42

PLACE_NEAR=U5000.G2:5MM

SYNC_MASTER=JACK_J52

PAGE TITLE

40

OUT

Power Sensors: High Side

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

Rthevenin = 4573 Ohms

2

SMC_PBUS_VSENSE

1

1

C5489

0.22UF

20%

PLACE_NEAR=U5000.E1:5MM

6.3V

2

X5R
0201

2

Rthevenin = 4573 Ohms

PLACE_NEAR=U5000.E1:5MM

GND_SMC_AVSS

SMC_DCIN_VSENSE

1

C5499

0.22UF

20%

6.3V

PLACE_NEAR=U5000.B3:5MM

2

X5R
0201

PLACE_NEAR=U5000.B3:5MM

GND_SMC_AVSS

SMC_DCIN_ISENSE

1

C5439

2200PF

10%

PLACE_NEAR=U5000.F1:5MM

10V

2

X7R-CERM
0201

GND_SMC_AVSS

SMC_TPAD_VSENSE

1%

1

201

MF

C5479

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

6 3

12

40

OUT

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

SYNC_DATE=12/15/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

54 OF 120

SHEET

42 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

CPU Fixed Current Sense (IC0C)

PCH 1.05V Current Sense (IC1C)

Gain: 200x, EDP: 5.2 A
Rsense: 0.003 (R7640) or Rsense SHORT
Vsense: 15.6 mV, Range: 5.5 A
SMC ADC: 19

59 80

D

DDR 1.2V S3 (CPU & Memory) Current Sense (IM0C)

Gain: 200x, EDP: 9.5 A
Rsense: 0.002 (R7450) or XW7450
Vsense: 19 mV, Range: 8.25 A
SMC ADC: 09

IN

59 80

IN

57 68

IN

57

IN

C

CPU DDR 1.2V S3 (CPU Only) Current Sense (IM1C)

Gain: 500x, EDP: 1.1 A
Rsense: 0.005 (R5510) or Rsense SHORT
Vsense: 5.5 mV, Range: 1.32 A
SMC ADC: 18

=PP1V2_S3_CPUDDR_ISNS

68

R5510

Short Rsense

=PP1V2_S3_CPUDDR_ISNS_R

68

3.3V S0 Rail Current Sense (IR3C)

Gain: 500x, EDP: 1.1 A

B

Rsense: 0.005 (R5520) or Rsense SHORT
Vsense: 5.5 mV, Range: 1.32 A
SMC ADC: 14

=PP3V3_S0_ISNS

68

Short Rsense

=PP3V3_S0_ISNS_R

68

5V S0 Rail Current Sense (IR5C)

Gain: 500x, EDP: 1.0 A
Rsense: 0.005 (R5530) or Rsense SHORT
Vsense: 5 mV, Range: 1.32 A
SMC ADC: 17

=PP5V_S0_ISNS

68

A

Short Rsense

=PP5V_S0_ISNS_R

68

OMIT

CRITICAL

OMIT

CRITICAL

OMIT

CRITICAL

0612-SHORT

R5520

0612-SHORT

R5530

0612-SHORT

PLACE_NEAR=U5510.5:10MM

123

80

0

0

1 W

MF

80

4

PLACE_NEAR=U5510.4:10MM

PLACE_NEAR=U5520.5:10MM

123

80

0

0

1 W

MF

80

4

PLACE_NEAR=U5520.4:10MM

PLACE_NEAR=U5530.5:10MM

123

80

0

0

1 W

MF

80

4

PLACE_NEAR=U5530.4:10MM

44

=PP3V3_S4_ISNS

42
43
68

ISNS_1V05_S0_N

ISNS_1V05_S0_P

LOADISNS
CRITICAL

=PP3V3_S4_ISNS

42 43
44 68

=PPDDR_S3_REG

PPDDR_S3_REG_R

DDRISNS
CRITICAL

=PP3V3_S4_ISNS

ISNS_CPUDDR_N

ISNS_CPUDDR_P

42 43
44 68

ISNS_PP3V3S0_N

ISNS_PP3V3S0_P

42 43 44 68

ISNS_PP5VS0_N

ISNS_PP5VS0_P

5

IN-

4

5

IN-

4

5

IN-

4

CRITICAL
LOADISNS

=PP3V3_S4_ISNS

5

IN-

4

CRITICAL
LOADISNS

=PP3V3_S4_ISNS

5

IN-

4

CRITICAL
LOADISNS

3

V+

U5560

INA210

SC70

200x

GND

2

3

V+

U5570

INA210

SC70

200x

GND

2

3

V+

U5510

INA211

SC70

500x

GND

2

3

V+

U5520

INA211

SC70

500x

GND

2

3

V+

U5530

INA211

SC70

500x

GND

2

OUT

REFIN+

OUT

REFIN+

OUT

REFIN+

OUT

REFIN+

OUT

REFIN+

LOADISNS
BYPASS=U5560.3:2:5MM

1

C5560

0.1uF

20%
10V

2

CERM
402

6

P1V05S0_IOUT

1

1

R5565

20K

5%
1/20W
MF
201

2

NOSTUFF
PLACE_NEAR=U5560.6:5MM

DDRISNS
BYPASS=U5570.3:2:5MM

1

C5570

0.1UF

20%
10V

2

CERM
402

6

ISNS_DDR_IOUT

1

1

R5575

20K

5%
1/20W
MF
201

2

NOSTUFF
PLACE_NEAR=U5570.6:5MM

LOADISNS
BYPASS=U5510.3:2:5MM

1

C5510

0.1UF

20%
10V

2

CERM
402

6

ISNS_CPUDDR_IOUT

1

1

R5515

20K

5%
1/20W
MF
201

2

NOSTUFF
PLACE_NEAR=U5510.6:5MM

LOADISNS
BYPASS=U5520.3:2:5MM

1

C5520

0.1UF

20%
10V

2

CERM
402

6

ISNS_PP3V3S0_IOUT

1

1

R5525

20K

5%
1/20W
MF
201

2

NOSTUFF
PLACE_NEAR=U5520.6:5MM

LOADISNS
BYPASS=U5530.3:2:5MM

1

C5530

0.1UF

20%
10V

2

CERM
402

6

ISNS_PP5VS0_IOUT

1

1

R5535

51K

5%
1/20W
MF
201

2

LOADISNS
PLACE_NEAR=U5530.6:5MM

LOADRC:YES
PLACE_NEAR=U5000.H2:5MM

R5569

4.53K

1 2

1%

1/20W

MF

201

SMC_PCH_ISENSE

1

C5569

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U5000.H2:5MM
LOADRC:YES

GND_SMC_AVSS

DDRRC:YES
PLACE_NEAR=U5000.A5:5MM

R5579

4.53K

1 2

1%

1/20W

MF

201

SMC_DDR_ISENSE

1

C5579

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U5000.A5:5MM
DDRRC:YES

GND_SMC_AVSS

LOADRC:YES
PLACE_NEAR=U5000.H1:5MM

R5519

4.53K

1 2

1%

1/20W

MF

201

SMC_CPUDDR_ISENSE

1

C5519

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U5000.H1:5MM
LOADRC:YES

GND_SMC_AVSS

LOADRC:YES
PLACE_NEAR=U5000.B1:5MM

R5529

4.53K

1 2

1%

1/20W

MF

201

1

2

SMC_PP3V3S0_ISENSE

C5529

0.22UF

20%

6.3V
X5R
0201

PLACE_NEAR=U5000.B1:5MM
LOADRC:YES

GND_SMC_AVSS

LOADRC:YES
PLACE_NEAR=U5000.G1:5MM

R5539

4.53K

1 2

1%

1/20W

MF

201

SMC_PP5VS0_ISENSE

1

C5539

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U5000.G1:5MM
LOADRC:YES

GND_SMC_AVSS

DIFFERENTIAL_PAIR=CPUVR_ISEN1

DIFFERENTIAL_PAIR=CPUVR_ISEN2

40

OUT

DIFFERENTIAL_PAIR=CPUVR_ISEN1

DIFFERENTIAL_PAIR=CPUVR_ISEN2

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

Gain: 219.33x, EDP: 40 A
Rsense: 2x of 0.00075 (R7310, R7320), Rsum: 0.000375
Vsense: 15 mV, Range: 40.12 A
SMC ADC: 06

CPUVR_ISNS1_P

56 80

IN

PLACE_NEAR=R7310.4:5MM
NO_XNET_CONNECTION=TRUE

LOADISNS

CPUVR_ISNS2_P

56 80

IN

PLACE_NEAR=R7320.3:5MM
NO_XNET_CONNECTION=TRUE

LOADISNS

CPUVR_ISNS1_N

56 80

IN

PLACE_NEAR=R7310.3:5MM

NO_XNET_CONNECTION=TRUE

LOADISNS

CPUVR_ISNS2_N

56 80

IN

PLACE_NEAR=R7320.4:5MM

NO_XNET_CONNECTION=TRUE

LOADISNS

SSD Current Sense (ISDC)

Gain: 200x, EDP: 2.5 A (8.2 W)
Rsense: 0.005 (R5580)
Vsense: 12.5 mV, Range: 3.3 A
SMC ADC: 13

=PP3V3_S0SW_SSD_ISNS

68

107S00030

=PP3V3_S0SW_SSD_ISNS_R

68

CPU High Side Current (IC0R) Threshold Alert

Gain: 100x
Rsense: 0.003 (R5400)

Trip Target on CPU High current: 2.5 A
Hysteresis Circuit:
Vref = 0.737 V
Vth = 0.616 V -> 2.054 A on CPU High current
Vtl = 0.771 V -> 2.571 A on CPU High current
Hysteresis Margin = 0.518 A

DDR 1.8V Current Sense (IM2C)

Gain: 500x, EDP: 0.45 A
Rsense: 0.005 (R7829) or Rsense SHORT
Vsense: 2.25 mV, Range: 1.32 A
SMC ADC: 12

PART NUMBER

117S0008
117S0008

QTY

3
3
1

R5545

4.42K

1 2

0.1%

1/16W

MF

0402

R5546

4.42K

1 2

1/16W

R5547

4.42K

1 2

1/16W

R5548

4.42K

1 2

1/16W

CPUVR_ISNS_P

80 80

0.1%
MF

0402

CPUVR_ISNS_N

80

0.1%
MF

0402

0.1%
MF

0402

PLACE_NEAR=U5580.5:10MM

123

ISNS_SSD_N

R5580

0.005

CRITICAL

42 68

0612-6

=PP3V3_S0_HS_COMPUTING_ISNS

61 80

IN

61 80

IN

80

1%
1W
MF

ISNS_SSD_P

80

4

PLACE_NEAR=U5580.4:10MM

ISNS_1V8_S3_N

PLACE_NEAR=R7829.4:5MM

ISNS_1V8_S3_P

PLACE_NEAR=R7829.3:5MM

DESCRIPTION

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

LOADISNS

R5542

1.05K

1 2

1%

1/20W

MF

201

R5543

1.05K

1 2

1%

1/20W

MF

LOADISNS

201

=PP3V3_S4_ISNS

42 43 44 68

CRITICAL

RB521ZS-30

=PP3V3_S4_ISNS

5

4

CRITICAL
LOADISNS

REFERENCE DES

C5569,C5519,C5599
C5529,C5539,C5549

C5579

1

2

1

2

IN-

80

5

4

CPUHYS

R5554

294K

1%
1/20W
MF
201

CPUHYS

R5555

84.5K

1%
1/20W
MF
201

NOSTUFF

D5557

SM-201

U5590

INA211

SC70

500x

GND

=PP3V3_S0_VRISNS

68

CPUVR_ISNS_R_P

CPUVR_ISNS_R_N

1

R5544

715K

0.1%
1/16W
MF
402

2

LOADISNS

NO_XNET_CONNECTION=TRUE

3
V+

U5580

INA210

SC70

IN-

200x

GND

2

OUT

REFIN+

CPUHI_COMP_VREF

NOSTUFF

1

R5557

0

5%
1/20W
MF
0201

2

BMON_IOUT_D

44

A

K

OUT

REFIN+

1

2

6

P1V8S3_IOUT

1

3

V+

2

CRITICAL

BOM_COST_GROUP=SENSORS

LOADISNS
CRITICAL

U5540

5

ISL28133

1

3

SC70-5

V+

V-

2

R5541

715K

1 2

0.1%

1/16W

MF

LOADISNS

402

NO_XNET_CONNECTION=TRUE

4

BYPASS=U5580.3:2:5MM

1

C5580

0.1uF

20%
10V

2

CERM
402

6

ISNS_S0_SSD_IOUT

1

1

R5585

20K

5%
1/20W
MF
201

2

NOSTUFF
PLACE_NEAR=U5580.6:5MM

BYPASS=U5551.5:2:3MM

CPUHYS

1

C5551

0.1UF

10%

6.3V

2

CERM-X5R
0201

CPUHYS

R5556

12K

1 2

1%

1/20W

MF

201

CPUHI_IOUT_R

CPUHYS

1

R5552

0

5%
1/20W
MF
0201

2

CPUHI_IOUT

LOADISNS
BYPASS=U5590.3:2:5MM

C5590

0.1uF

20%
10V
CERM
402

1

R5595

20K

5%
1/20W
MF
201

2

NOSTUFF
PLACE_NEAR=U5590.6:5MM

BOM OPTION

LOADRC:NO
LOADRC:NO

DDRRC:NO117S0008

LOADISNS

BYPASS=U5540.5:2:3MM

1

C5540

0.1UF

20%
10V

2

CERM
402

CPUVR_ISUM_IOUT

1

R5540

20K

5%
1/20W
MF
201

2

NOSTUFF
PLACE_NEAR=U5540.4:5MM

LOADRC:YES

PLACE_NEAR=U5000.B4:5MM

R5549

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_ISENSE

1

C5549

0.22UF

20%

6.3V

2

X5R
0201

LOADRC:YES
PLACE_NEAR=U5000.B4:5MM

GND_SMC_AVSS

PLACE_NEAR=U5000.C2:5MM

R5589

4.53K

1 2

1%

1/20W

MF

201

SMC_SSD_ISENSE

1

C5589

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U5000.C2:5MM

GND_SMC_AVSS

CPUHI_COMP_FB
CPUHYS

U5551

5

3

4

NOSTUFF

1

C5552

0.1UF

10%
25V

2

X5R
402

LOADRC:YES
PLACE_NEAR=U5000.G2:5MM

R5599

4.53K

1 2

1%

1/20W

MF

201

MCP6541T

SC70-5

1

CPUHI_COMP_OUT

2

SMC_CPUHI_COMP_ALERT_L

U5552

DFN1006H4-3

SYM_VER_2

1

G S

42

IN

CPUHYS

DMN32D2LFB4

SMC_DDR1V8_ISENSE

1

C5599

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U5000.G2:5MM

LOADRC:YES

GND_SMC_AVSS

PAGE TITLE

Power Sensors: Load Side

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NOSTUFF

C5553

0.22UF

1 2

R5553

255K

1 2

1/16W
MF-LF

CPUHYS

3

D

OUT

20%

6.3V
X5R

0201

1%

402

2

40

38 39 40 42 43 44

6 3

40

OUT

38 39 40 42 43 44

SYNC_DATE=12/06/2013SYNC_MASTER=JACK_J52

12

40

OUT

38 39 40 42 43 44

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

55 OF 120

SHEET

43 OF 82

124578

D

C

40

OUT

B

A

SIZE

D

8 7 6 5 4 3

D

Thunderbolt TBT Current/Voltage Sense (IHSC/VHSC)

Gain: 200x. EDP: 2.8 A
Rsense: 0.005 (R5640) or Rsense SHORT
Vsense: 14 mV, Range: 3.3 A
SMC AD: 23

=PP3V3_S4_TBT_ISNS

68

Short Rsense

CRITICAL

=PP3V3_S4_TBT_ISNS_R

68

OMIT

R5640

0612-SHORT

PLACE_NEAR=U5640.5:10MM

123

ISNS_TBT_N

80

0

0

1 W

ISNS_TBT_P

80

MF

4

PLACE_NEAR=U5640.4:10MM

C

LCD Panel Current Sense (ILDC)

Gain: 500x. EDP: 1 A
RSENSE: 0.005 (R8320) or Rsense SHORT
Vsense: 5 mV, Range: 1.32 A
SMC AD: 21

ISNS_LCDPANEL_N

65 80 40

IN

ISNS_LCDPANEL_P

65 80

IN

B

A

Camera (S2 Controller) Current Sense (ICMC)

Gain: 500x. EDP: 0.82 A
Rsense: 0.005 (R5610) or XW5610
Vsense: 4.1 mV, Range: 1.32 A
SMC AD: 15

=PP3V3_S3RS0_CAMPWREN

15 18

PP3V3_S3RS0_CAMERA

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.175MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S3RS0_CAMERA

33 44

PP3V3_S3RS0_CAMERA_R

44

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V

=PP3V3_S0_CAMERA_R

68

=PP3V3_S3_CAMERA_R

68

PART NUMBER

117S0008
117S0008
117S0008

XW5610

QTY

2
1
1

R5611

1 2

R5612

1 2

1

SM

2

0

CAMERA_3V3:S0

5%
1/16W
MF-LF

402

0

CAMERA_3V3:S3

5%
1/16W
MF-LF

402

DESCRIPTION

RES,MTL FILM,100K,1/16W,0201,SMD,LF

RES,MTL FILM,100K,1/16W,0201,SMD,LF

RES,MTL FILM,100K,1/16W,0201,SMD,LF

XW5640

SM

1 2

PLACE_NEAR=R5640.1:10 MM

=PP3V3_S4_ISNS

42 43 44 68

TBTISNS

=PP3V3_S4_ISNS

42 43 44 68

LOADISNS

=PP3V3_S4_ISNS

42 43 44 68

=PP3V3_S3RS0_CAMERA

33 44

PP3V3_S3RS0_CAMERA_R

44

LOADISNS

ISNS_TBT_IVIN

3

V+

U5640

INA210

5

SC70

IN-

200x

4

GND

2

3

V+

U5620

INA211

5

SC70

IN-

500x

4

GND

2

3

V+

U5610

INA211

5

SC70

IN-

500x

4

GND

2

REFERENCE DES

C5619,C5629

C5679
C5649

OUT

OUT

OUT

R5648

0

1 2

5%

1/20W

MF

0201

1

C5640

0.1UF

2

6

1

REFIN+

LOADISNS

BYPASS=U5620.3:2:5MM

1

C5620

0.1UF

2

6

ISNS_LCDPANEL_IOUT

1

REFIN+

LOADISNS

BYPASS=U5630.3:2:5MM

1

C5610

0.1UF

2

6

ISNS_CAMERA_IOUT

1

REFIN+

CRITICAL

TBTISNS

BYPASS=U5640.3:2:5MM

20%
10V
CERM
402

ISNS_TBT_IOUT

1

R5645

20K

5%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=U5640.6:5MM

20%
10V
CERM
402

1

R5625

51K

5%
1/20W
MF
201

2

LOADISNS

PLACE_NEAR=U5620.6:5MM

20%
10V
CERM
402

1

R5615

20K

5%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=U5610.6:5MM

NOSTUFF

PLACE_NEAR=XW5640.2:10MM

ISNS_TBT_IVOUT

PLACE_NEAR=XW5640.2:10MM

TBTISNS

R5647

1 2

LOADRC:YES

PLACE_NEAR=U5000.A7:5MM

R5629

1 2

LOADRC:YES

PLACE_NEAR=U5000.B2:5MM

R5619

1 2

BOM OPTION

LOADRC:NO
BMONRC:NO

TBTRC:NO

6 3

0

5%

1/20W

MF

0201

4.53K

1%

1/20W

MF

201

4.53K

1%

1/20W

MF

201

TBTRC:YES

PLACE_NEAR=U5000.A8:5MM

R5649

4.53K

1 2

1%

1/20W

MF

201

SMC_LCDPANEL_ISENSE

1

C5629

0.22UF

20%

6.3V

2

X5R
0201

LOADRC:YES

PLACE_NEAR=U5000.A7:5MM

GND_SMC_AVSS

SMC_CAMERA_ISENSE

1

C5619

0.22UF

20%

6.3V

2

X5R
0201

LOADRC:YES

PLACE_NEAR=U5000.B2:5MM

GND_SMC_AVSS

SMC_TBT_ISENSE

1

C5649

0.22UF

20%

6.3V

2

X5R
0201

TBTRC:YES

PLACE_NEAR=U5000.A8:5MM

GND_SMC_AVSS

OUT

38 39 40 42 43 44

40

OUT

38 39 40 42 43 44

CPU High Side (IC0R) Peak Detection Support

R5660

47

=PP3V3_S0_CPUTHMSNS

45 68

PLACE_NEAR=R5400:10MM

CKPLUS_WAIVE=NdifPr_badTerm

ISNS_HS_COMPUTING_P

42 44 80

IN

ISNS_HS_COMPUTING_N

42 44 80

IN

CKPLUS_WAIVE=NdifPr_badTerm

40

OUT

38 39 40 42 43 44

CHGR_CSO_R_P/N are swapped on purpose
to measure Battery discharge power
into system.

Trip Target on Battery current: 3.5 A
Hysteresis Circuit:
Vref = 0.854 V
Vth = 0.758 V -> 3.031 A on Battery current
Vtl = 0.887 V -> 3.549 A on Battery current
Hysteresis Margin = 0.518 A

CKPLUS_WAIVE=NdifPr_badTerm

54 80

IN

54 80

IN

CKPLUS_WAIVE=NdifPr_badTerm

CPU Core Voltage Sense (VC0C)

SMC ADC: 20

=PPVCC_S0_CPU

8

10 68

CPU Core IMON Current Sense (IC2C)

Gain: 1 A / 28.273 mV, Range: 40 A.
SMC ADC: 22

CPUVR_IMON

55

With R7210 (Ri) set to 316 Ohm,
R7310 (Rsen) set to 0.75 mOhm,
R7230 set to 95.3 kOhm,
Num Phases (N) is 2, and Io (ICCmax) is 40A,
then 1A of Io gives 28.273mV at the Vimon.

1 2

5%

1/20W

MF

201

3

V+

U5660

INA210

5

SC70

IN-

CRITICAL

4

200x

GND

2

Battery BMON Discrete Current Sense (IP0R) & Threshold Alert

Gain: 50x. EDP: 8 A
Rsense: 0.005 (R7150)
Vsense: 50 mV, Range: 13.2 A
SMC AD: 05

=PP3V3_S0_SNS_BMON

68

BMONISNS

C5670

0.1UF

6.3V

CERM-X5R

BYPASS=U5670.3:2:3MM

0201

CHGR_CSO_R_P

CHGR_CSO_R_N

BMONISNS

XW5680

SM

1 2

PLACE_NEAR=R7310.2:5 MM

CPUVSENSE_IN

6

OUT

1

REFIN+

1

10%

2

3

V+

U5670

INA213

5

SC70

IN-

CRITICAL

4

50x

GND

2

PLACE_NEAR=U5000.B7:5MM

PLACE_NEAR=U5000.B8:5MM

1

C5660

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U5660.3:2:5MM

ISNS_CPUHIGAIN_OUT

1

R5664

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U5660.6:5MM

NOSTUFF

D5677

SM-201

RB521ZS-30

6

OUT

1

1

REFIN+

R5689

4.53K

1 2

1%

1/20W

MF

201

R5671

15K

5%
1/20W
MF
201

2

NOSTUFF

PLACE_NEAR=U5670.6:5MM

SMC_CPU_VSENSE

1

C5689

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

R5699

0

1 2

5%

1/20W

MF

0201

SMC_CPU_IMON_ISENSE

1

C5699

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

R5665

0

1 2

ISNS_CPUHIGAIN_OUT_R

5%

1/20W

1

MF

0201

C5665

0.22UF

20%

6.3V

2

X5R
0201

NOSTUFF

BMONHYS

1

R5674

200K

1%
1/20W
MF
201

2

BMON_COMP_VREF

BMONHYS

1

R5675

69.8K

1%
1/20W
MF
201

2

NOSTUFF

1

R5677

0

5%
1/20W
MF
0201

2

BMON_IOUT_D

43

A

K

BMON_IOUT

OUT

PLACE_NEAR=U5000.B7:5MM

OUT

NOSTUFF

PLACE_NEAR=U5000.B8:5MM

BOM_COST_GROUP=SENSORS

R5666

0

ISNS_CPUHIGAIN_R_P

80

PLACE_NEAR=U5660.6:10MM

1

R5662

1K

1%
1/20W
MF
201

2

ISNS_CPUHIGAIN_R_N

80

1

R5661

16K

1%
1/20W
MF
201

2

In battery discharge scenario negative voltage will be
present on IN+/- pins with INA output voltage decreasing
from 3.3V with increasing discharge current.

SENSE+ pins of EMC1704 sink 10-20uA current.
This deviation has been designed in our Peak Detection circuit.
With 10uA sink: 0.125A - 2.1A -> 13mV - 83 mV
With 20uA sink: 0.125A - 2.1A -> 23mV - 92 mV

BMONHYS

1

C5671

0.1UF

10%

6.3V

2

CERM-X5R
0201

BYPASS=U5671.5:2:3MM

BMONHYS

R5676

10K

1 2

1%

1/20W

MF

201

BMON_IOUT_R

BMONHYS

1

R5672

0

5%
1/20W
MF
0201

2

PLACE_NEAR=U5000.A3:5MM

42 44 80

IN

PLACE_NEAR=U5660.6:10MM

42 44 80

IN

BMON_COMP_FB

BMONHYS

3

4

NOSTUFF

1

C5672

0.1UF

10%
25V

2

X5R
402

U5671

5

MCP6541T

SC70-5

2

BMONRC:YES

R5679

4.53K

1 2

1%

1/20W

MF

201

1 2

5%

1/20W

MF

0201

ISNS_HS_COMPUTING_P

PLACE_NEAR=U5660.6:10MM

R5668

0

1 2

5%

1/20W

MF

0201

ISNS_HS_COMPUTING_N

PLACE_NEAR=U5660.6:10MM

1

BMONHYS

DMN32D2LFB4

BMONHYS

BMON_COMP_OUT

SMC_BMON_COMP_ALERT_L

U5672

DFN1006H4-3

SYM_VER_2

1

G S

SMC_BMON_DISCRETE_ISENSE

BMONRC:YES

1

C5679

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U5000.A3:5MM

ISNS_CPUHIGAIN_P

ISNS_CPUHIGAIN_N

NOSTUFF

C5673

0.22UF

1 2

20%

6.3V
X5R

0201

R5673

255K

1 2

1%
1/16W
MF-LF

402

3

D

2

GND_SMC_AVSS

40

38 39 40 42 43 44

SYNC_MASTER=JACK_J52 SYNC_DATE=10/26/2013

PAGE TITLE

Power Sensors: Extended

40

38 39 40 42 43 44

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

R

12

NOSTUFF

R5667

0

1 2

5%

1/20W

MF

0201

NOSTUFF

R5669

0

1 2

5%

1/20W

MF

0201

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

OUT

38 39 40 42 43 44

051-1573

8.0.0
dvt1

56 OF 120

44 OF 82

45 80

OUT

45 80

OUT

D

C

40

OUT

B

40

A

SIZE

D

8 7 6 5 4 3

12

Thermal Sensor A:
Thunderbolt Die, MLB Proximity

I2C Write: 0xD8, I2C Read: 0xD9

R5850

47

=PP3V3_S0_TBTTHMSNS

68

D

TP_TBT_THERM_DP

25

BI

Thermal Diode: TBT Die (THSP)

Placement Note:
The P leg connects to THERMDA pin of the TBT
chip, the N leg connect to pin AA8.

1 2

XW5851

Note: Use GND pin AA8 on U2800 for N leg.

PLACE_NEAR=U2800.AA8:2MM

SM

TBTTHMSNS_D1_P

80

MAKE_BASE=TRUE

TBTTHMSNS_D1_N

80

PLACE_NEAR=U5850.2:5MM

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5850.3:5MM

41

41

1 2

1/16W
MF-LF

402

0.0022uF

TBTTHRM_SNS

=I2C_TBTTHMSNS_SDA

BI

=I2C_TBTTHMSNS_SCL

BI

PP3V3_S0_TBTTHMSNS_R

MIN_LINE_WIDTH=0.38 mm

5%

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C5851

10%
50V

2

CERM

402

TBTTHRM_SNS

2
3

7
8

DP
DN

SMDATA
SMCLK

1

VDD

U5850

EMC1412-A

TQFN

THERM*/ADDR

GND

5

1

C5850

0.1uF

20%
10V

2

CERM
402

TBTTHRM_SNS

1

R5851

15K

1%
1/20W
MF
201

2

1

R5852

100K

1%
1/20W
MF
201

2

TBTTHRM_THRM:PU TBTTHRM_ALRT:PU

4

ALERT*

THRM

PAD

TBTTHMSNS_THM_L

6

TBTTHMSNS_ALERT_L

9

40

OUT

40

OUT

Thermal Diode: MLB Proximity (TMLB)

Placement Note:
Place U5850 on the TOP side, on the left portion
of the board, 1" to the right of USB connector.

U5850 I2C Address:
By setting R5851 to 15k, I2C address
for U5850 is 0xD8/0xD9.

D

C

C

Thermal Sensor B & CPU High Peak Detection:
CPU Proximity, Memory Proximity, Airflow, Fin Stack Proximity

I2C Write: 0x98, I2C Read: 0x99

R5870

47

=PP3V3_S0_CPUTHMSNS

44 68

CPUTHMSNS_D1_P

Thermal Diode: Airflow (TA0P)

Placement Note:
Place Q5871, Airflow thermal indicator, above
the SSD, on the BOTTOM side.

CPUTHMSNS_D2_P

Q5872

BC846BLP

DFN1006H4-3

B

2

1

3

CRITICAL

80

CPUTHMSNS_D2_N

80

Thermal Diode: Memory Proximity (TM0P)

Placement Note:
Place Q5872 between two rows of Memory devices,
between channel A and B, on the BOTTOM side.

Q5871

BC846BLP

DFN1006H4-3

Q5873

BC846BLP

DFN1006H4-3

Thermal Diode: CPU Proximity (TC0P)

Placement Note:
Place Q5873 under the CPU,
on the BOTTOM side.

80

3

1

CRITICAL

2

CPUTHMSNS_D1_N

80

3

1

CRITICAL

2

44 80

IN

44 80

IN

PLACE_NEAR=U5870.2:5MM

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5870.3:5MM

PLACE_NEAR=U5870.4:5MM

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5870.5:5MM

1 2

1/16W
MF-LF

402

0.0022uF

0.0022uF

ISNS_CPUHIGAIN_P
ISNS_CPUHIGAIN_N

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm

5%

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C5871

10%
50V

2

CERM

402

1

C5872

10%
50V

2

CERM

402

2

4

5

16
15

13
14

EMC1704-2

DP1

DN1

DP2/DN3

DN2/DP3

SENSE+
SENSE-

DUR_SEL
TH_SEL

GND

8

1

CRITICAL

VDD

U5870

QFN

THRM_PAD

1

C5870

0.1uF

20%
10V

2

CERM
402

1

2

CPUTHRM_THRM:PU

9

THERM*

ALERT*

SMDATA

SMCLK

ADDR_SEL

17

CPUTHMSNS_THM_L

103

CPUTHMSNS_ALERT_L

11

=I2C_CPUTHMSNS_SDA

12

=I2C_CPUTHMSNS_SCL

6

CPUTHMSNS_ADDR_SEL

7

GPIO

NC

Thermal Sensor: Fin Stack Proximity (Th1H)

Placement Note:
Place U5870 at corner near Fan,
on the TOP side.

R5871

100K

1%
1/20W
MF
201

1

R5875

0

5%
1/20W
MF
0201

2

1

R5872

100K

1%
1/20W
MF
201

2

CPUTHRM_ALRT:PU

40

OUT

40

OUT

41

BI

41

BI

B

Placement Note: Place C5800 and C5801 near Q5871.

NC NC

1

C5800

NC

0.0022UF

10%
50V

2

CERM-X7R
0603

A

NC

1

C5801

0.0022UF

10%
50V

2

CERM-X7R
0603

6 3

CPUTHMSNS_DUR_SEL

1

R5874

10K

5%
1/20W
MF
201

2

NOSTUFF

CPUTHMSNS_TH_SEL

1

R5873

10K

5%
1/20W
MF
201

2

NOSTUFF

BOM_COST_GROUP=SENSORS

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

Thermal Sensors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/07/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

58 OF 120

SHEET

45 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

FAN CONNECTOR

D

KEEP THE 5 PIN CONNECTOR FROM D1

12PF

NP0-C0G

0201

=PP3V3_S0_FAN

1

5%

25V

2

=PP3V3_S0_FAN

=PP5V_S0_FAN

46 68

46 68

C6000

C

=PP5V_S0_FAN

CRITICAL

J6050

FF14A-5C-R11DL-B-3H

F-RT-SM

6

NC

1

5V DC

2

MOTOR CONTROL

3

GND

4

TACH

5

NC

7

NC

518S0769

47K

1/20W

201

1

5%
MF

2

R6060

R6065

47K

SMC_FAN_0_TACH

38

OUT

R6061

100K

5%

1/20W

MF

201

SMC_FAN_0_CTL

38

B

IN

1 2

1/20W

1

1

2

S G

2

5%
MF

201

Q6060

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

3

FAN_RT_TACH

FAN_RT_PWM

C6001

12PF

NP0-C0G

0201

25V

1

5%

2

46 68

C

46 68

B

Placement Note: Place C6002 and C6003 near Q6060

NC

1

C6002

0.0022UF

10%
50V

2

CERM-X7R
0603

NC

A

6 3

NC

NC

1

C6003

0.0022UF

10%
50V

2

CERM-X7R
0603

BOM_COST_GROUP=FAN

SYNC_MASTER=J41

PAGE TITLE

Fan

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

60 OF 120

SHEET

46 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

SPI ROM

Quad-IO Mode (Mode 0 & 3) supported.
SPI Frequency: 50MHz for CPU, 20MHz for SMC.

=PP3V3_SUS_ROM

68

BYPASS=U6101::3mm

OE*

1

2

7

1

C6101

0.1UF

10%
16V
X5R-CERM
0201

SPI_MLBROM_CS_L

PLACE_NEAR=U6100.1:12MM

BYPASS=U6100::3mm

SPI_MLB_CLK

47 75

SPI_MLB_IO2_WP_L

47 75

SPI_MLB_IO3_HOLD_L

47 75

C6100

0.1UF

10%
16V

X5R-CERM

0201

1

2

6

1

3

8

CRITICAL

VCC

U6100

W25Q64FVZPIG

64MBIT

WSON

CLK

OMIT_TABLE

CS*

IO2

WP*(IO2)
HOLD*(IO3)

GND

479

IO3

THRM_PAD

DI(IO0)

DO(IO1)

IO0

5

IO1

2

SPI_MLB_IO0_MOSI

SPI_MLB_IO1_MISO

47 75

47 75

68

47 75

47 75

47 75

47 75

38 39 40 54 71

D

8

VCC

U6101

74LVC1G99

2

SOT833

A Y

SPI_MLB_CS_L

47 75

SPIROM_USE_MLB

15 47 71

Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)
in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

3

B

CRITICAL

5

C

6

D

GND

4

NOTE: If HOLD* is asserted
ROM will ignore SPI cycles
in normal and Dual-IO modes.

SPI+SWD SAM Connector

SAMCONN

CRITICAL

J6100

DF40PC-12DP-0.4V-51

M-ST-SM

=PP3V3_G3H_T112

SPI_ALT_IO0_MOSI
SPI_ALT_IO1_MISO
SPI_ALT_IO2_WP_L
SPI_ALT_IO3_HOLD_L

SMC_RESET_L

2

10

16

1314

1
34
56
78
9
1112

15

SPI_ALT_CLK
SPI_ALT_CS_L

SPIROM_USE_MLB
SMC_TMS
SMC_TCK

(SWDIO)
(SWCLK)

47 75

47 75

OUTOUT

15 47 71

BI

38 39 71

BI

38 39 71

12

D

C

C

SPI Bus Series Termination

PLACE_NEAR=J6100.10:5MM

SAMCONN

1

R6133

0

5%
1/20W
MF
0201

2

R6110

22

201

201

201

1 2

1/20W

22

5%
MF

R6112

1 2

1/20W

22

5%
MF

SPI_IO2_R

75

22

75

5%
MF

SPI_CS0_R_L

14 75

IN

SPI_CLK_R

14 75

IN

B

CPU Master

14 75

14 75

14 75

BI

14 75

BI

PLACE_NEAR=U0500.AA3:50MM

SPI_MOSI_R

(SPI_IO<0>)

SPI_MISO

PLACE_NEAR=U0500.AA2:50MM

(SPI_IO<1>)

SPI_IO<2>

PLACE_NEAR=U0500.Y6:50MM

SPI_IO<3> SPI_IO3_R

PLACE_NEAR=U0500.AF1:50MM

PLACE_NEAR=U0500.Y7:50MM

R6111

1 2

1/20W

PLACE_NEAR=U0500.AA2:50MM

R6113

1 2

R6118

22

1 2

1/20W

201

1/20W

5%
MF

R6119

1 2

1/20W

201

22

201

5%
MF

5%
MF

SPI_CS0_L

75

SPI_CLK

75

SPI_MOSI

75

SPI_MISO_R

75

R6121

1 2

R6123

1 2

R6120

1 2

1/20W

22

PLACE_NEAR=U6100.6:12MM

5%

1/20W

MF

R6122

201

1 2

1/20W

22

PLACE_NEAR=U6100.2:12MM

5%

1/20W

MF

201

R6131

22

1 2

5%

1/20W

MF

201

22

PLACE_NEAR=U6100.1:12MM

5%
MF

201

22

PLACE_NEAR=U6100.5:12MM

5%
MF

201

R6130

22

1 2

1/20W

PLACE_NEAR=U6100.7:12MM

PLACE_NEAR=U6100.3:12MM

5%
MF

201

PLACE_NEAR=J6100.8:5MM

SAMCONN

1

R6132

0

5%
1/20W
MF
0201

2

PLACE_NEAR=J6100.6:5MM

SAMCONN

1

R6128

0

5%
1/20W
MF
0201

2

PLACE_NEAR=J6100.4:5MM

SAMCONN

1

R6127

0

5%
1/20W
MF
0201

2

PLACE_NEAR=J6100.3:5MM

SAMCONN

1

R6126

0

5%
1/20W
MF
0201

2

PLACE_NEAR=J6100.5:5MM

SAMCONN

1

R6125

0

5%
1/20W
MF
0201

2

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_IO0_MOSI

SPI_MLB_IO1_MISO

SPI_MLB_IO2_WP_L

SPI_MLB_IO3_HOLD_L

SPI_ALT_IO3_HOLD_L
SPI_ALT_IO2_WP_L
SPI_ALT_IO1_MISO
SPI_ALT_IO0_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L

47 75

47 75

47 75

Sam Card ROM Slave

47 75

47 75

47 75

47 75

OUT

47 75

OUT

47 75

BIBI

B

SPI ROM Slave

47 75

BIBI

47 75

BI

47 75

BI

R6114

22

SPI_SMC_MISO

38 75

OUT

SPI_SMC_MOSI

38 75

IN

A

SMC12 Master

38 75

IN

38 75

IN

SPI_SMC_CLK

SPI_SMC_CS_L

1 2

PLACE_NEAR=U5000.M9:12MM

5%

1/20W

MF

201

R6115

22

1 2

PLACE_NEAR=U5000.N9:12MM

5%

1/20W

MF

201

R6116

22

1 2

PLACE_NEAR=U5000.L10:12MM

5%

1/20W

MF

R6117

201

22

1 2

PLACE_NEAR=U5000.K10:12MM

5%

1/20W

MF

201

6 3

BOM_COST_GROUP=CPU SUPPORT

PAGE TITLE

SPI Debug Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/09/2013SYNC_MASTER=YHARTANTO_J44

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

SHEET

124578

8.0.0
dvt1

61 OF 120

47 OF 82

SIZE

A

D

8 7 6 5 4 3

AUDIO CODEC, ANALOG BLOCKS

APPLE P/N 353S4080

PP3V3_S0_AUDIO_ANALOG

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V

D

BYPASS=U6201.H12:L10:5 mm

CRITICAL

C6219

15UF

1 2

20%

4V

X5R

0402

CODEC_FLYP

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.07MM

CODEC_FLYN

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.07MM

GND_AUDIO_CODEC

48 52

TP_AUD_CODEC_MICBIAS1_L

69

TP_AUD_CODEC_MICBIAS1_R

69

TP_AUD_CODEC_MICBIAS2_L

69

TP_AUD_CODEC_MICBIAS2_R

69

BYPASS=U6201.A8:B10:5 mm

48 52

CRITICAL

C6222

15UF

20%

4V

X5R

0402

GND_AUDIO_CODEC

1

2

C

GND_AUDIO_CODEC

48 52

GND_AUDIO_CODEC

48 52

R6206

2.21K

1 2

1%

1/20W

MF

201

C6220

1UF

1 2

10%
25V
X5R
402

B

CRITICAL

C6215

10UF

20%
16V

TANT-POLY

0805-LLP-1

BYPASS=U6201.H12:H13:5 mm

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.07MM

C6226

0.1UF

10%
16V
X5R-CERM
0201

1 2

AUD_HSBIAS_IN
AUD_HSBIAS

AUD_HSBIAS_REF

1

C6221

4.7UF

20%
10V

2

X5R-CERM
0402

1

2

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.07MM

VREF_DAC
VHP_FILTN

CODEC_MICIN2

AUD_HSBIAS_FILT

H13

A11

B10
B11

N10
M10

L12
L13
M13
N11

A8

N9
M9

L8
L7

L5
L4

N8
M8

N7
M7

N5
M5

N4
M4

VREF_DAC

VHP_FILT-

FLYP
FLYN
FLYN

LINEIN_L+
LINEIN_L-

LINEIN_R+
LINEIN_R-

MICBIAS1_L
MICBIAS1_R

MICBIAS2_L
MICBIAS2_R

MICIN1_L+
MICIN1_L-

MICIN1_R+
MICIN1_R-

MICIN2_L+
MICIN2_L-

MICIN2_R+
MICIN2_R-

HSBIAS_IN
HSBIAS
HSBIAS_REF
HSBIAS_FILT

H12

VA_REF

U6201

CS4208-CRZR

VFBGA

ANALOG

SYM 1 OF 2

AGND

AGND

AGND

AGND

L6

L9

M11

L10

N13A9A1

VA

VA_HP

HPGND

HPGND

A10C8C10

VA_PLL

HPGND

C6218

0.1UF

X7R-CERM

0402

LINEOUT1_L+
LINEOUT1_L-

LINEOUT1_R+
LINEOUT1_R-

LINEOUT2_L+
LINEOUT2_L-

LINEOUT2_R+
LINEOUT2_R-

LINEOUT3_L+
LINEOUT3_L-

LINEOUT3_R+
LINEOUT3_R-

LINEOUT4_L+
LINEOUT4_L-

LINEOUT4_R+
LINEOUT4_R-

PLLGND

HSGND

A2

D13

10%
16V

1

2

HPOUT_L
HPOUT_R

SENSE_A1
SENSE_A2

HS3_REF
HS4_REF

HSIN+
HSIN-

SENSE_B1
SENSE_B2

SENSE_C
SENSE_D

VCOM

VREF_ADC

HS3
HS4

C6216

0.1UF

X7R-CERM

BYPASS=U6201.N13:M11:5 mm

A12
A13

C11
D12

C13
C12
B13
B12
N6

CODEC_HS_MIC_P

80

M6

CODEC_HS_MIC_N

80

E11
D11
M3
L3

E12
E13

F11
F12

F13
G11

G12
G13

H11
J11

J12
J13

K11
K12

K13
L11

M12

CODEC_VCOM

N12

CODEC_VREF_ADC

CRITICAL

C6210

1UF-10OHM

0603-LLP

10%
16V

0402

MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM

MIN_LINE_WIDTH=0.5MM
MIN_LINE_WIDTH=0.5MM

20%
25V

TANT

PP4V5_AUDIO_ANALOG

1

1

2

1

2

C6217

10UF

20%
16V

2

TANT-POLY
0805-LLP-1

MIN_LINE_WIDTH=0.4MM
MIN_LINE_WIDTH=0.4MM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.06MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.06MM

CRITICAL

1

C6211

10UF

20%
16V

2

TANT-POLY
0805-LLP-1

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.07MM

MIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.07MM

GND_AUDIO_CODEC

48

48 52

MIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.07MM

C6224

1UF

1 2

10%
X5R

C6214

C6212

0.1UF

X7R-CERM

MAX_LINE_WIDTH=0.5MM
MAX_LINE_WIDTH=0.5MM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.07MM

C6225

40225V

1 2

48
52

GND_AUDIO_CODEC

1

0.1UF

10%
16V

2

X7R-CERM

0402

1

10%
16V

2

0402

1UF

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.07MM

10%
25V
X5R
402

BYPASS=U6201.A1:A2:5 MM

AUD_HP_PORT_REFUS
AUD_HP_PORT_REFCH

48 52

CRITICAL

L6201

120-OHM-25%-1.3A

1 2

0402

CRITICAL

1

C6213

10UF

20%
10V

2

X5R-CERM
0402-1

AUD_HP_PORT_L
AUD_HP_PORT_R

AUD_TIPDET_1
AUD_TIPDET_2

AUD_US_HS_GND
AUD_CH_HS_GND

HS_MIC_P

HS_MIC_N

AUD_TYPEDET
NC_AUD_LO1_LP
NC_AUD_LO1_LN

NC_AUD_LO1_RP
NC_AUD_LO1_RN

AUD_LO2_L_P
AUD_LO2_L_N

AUD_LO2_R_P

AUD_LO2_R_N
AUD_LO3_L_P

AUD_LO3_L_N
AUD_LO3_R_P

AUD_LO3_R_N
NC_AUD_LO4_LP

NC_AUD_LO4_LN
NC_AUD_LO4_RP

NC_AUD_LO4_RN

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

GND_AUDIO_CODEC

52

OUT

52

OUT

52

IN

52

IN

52 80

IN

52 80

IN

52 80

IN

52 80

IN

51 80

IN

51 80

IN

52

OUT

71

71

71

71

50 80

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

71

71

71

71

LFT. SPKR AMP. SIG. SOURCE

50 80

50 80

RT. SPKR AMP. SIG. SOURCE

50 80

50 80

LFT SUBWOOFER AMP. SIG. SOURCE

50 80

50 80

RT. SUBWOOFER AMP. SIG. SOURCE

50 80

48 52

12

68

D

48 52

C

B

4.5V POWER SUPPLY FOR CODEC

APPLE P/N 353S2456

PLACE XW6201 NEAR 5V SOURCE

XW6201

SM

1 2

2.2K

5%

1/20W

MF

201

PP5V_S3_AUDIO_XW

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V

R6207

=PP5V_S3_AUDIO

68

R6200

=PP3V3_S0_AUDIO_DIG

49 52 68

A

PM_SLP_S3_BUF_L

64

NO STUFF

1 2

FERR-22-OHM-1A-0.055OHM

22K

12

5%
1/16W
MF-LF

402

L6200

1 2

0201

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V

4V5_REG_IN

4V5_REG_EN

1

C6200

0.1UF

20%
10V

2

X7R-CERM
0402

1

C6201

1UF

10%
10V

2

X5R
402

TPS71745

6

IN

4

EN

U6200

SON

CRITICAL

NR/FB

GND

2

1

OUT

3

4V5_NR

5

NC

XW6200

SM

1 2

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

6 3

CRITICAL

C6202

0.01UF

X5R-CERM

0201

10%
25V

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

CRITICAL

1

1

C6203

1.0UF

20%
10V

2

2

X5R-CERM
0201-1

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=0V

48

48 52

BOM_COST_GROUP=AUDIO

SYNC_MASTER=JCURCIO_J44

PAGE TITLE

Audio: Codec,Analog

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/13/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

62 OF 120

SHEET

48 OF 82

SIZE

A

D

124578

8 7 6 5 4 3

12

AUDIO CODEC, DIGITAL BLOCKS

APPLE P/N 353S4080

H3
H2
H1
C4
C5
C7

C9
B9

F2
E2
D1
C1
D2
C2
C3
B1
D3

A5
B2
B4
A3
B3

A6
B6
B5
B8
A4

C6
B7

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5

GPO0
GPO1

BCLK
SYNC
SDI0
SDI1
SDO0
SDO1
SDO2
SDO3
RST*

MCLK_A
SCLK_A
LRCK_A
SDOUT_A
SDIN_A

MCLK_B
SCLK_B
LRCK_B
SDOUT_B
SDIN_B

SDA
SCL

J2K1E1G1A7

VD

VL_HD

VL_SP

U6201

CS4208-CRZR

VFBGA

DIGITAL

SYM 2 OF 2

DGND

LGND

LGND

LGND

J1

F1E3F3J3K3

BYPASS=U6201.G1:F1:5 mm

VL_IF

VL_DM

LGND

LGND

SPDIF_IN

SPDIF_OUT

DMIC_SDA0
DMIC_SCL0

DMIC_SDA1
DMIC_SCL1

DMIC_SDA2
DMIC_SCL2

DMIC_SDA3
DMIC_SCL3

1

C6303

0.1UF

10%

6.3V

2

CERM-X5R
0201

NC
NC
NC
NC
NC
NC
NC
NC
NC

G3
G2

N3
N2

N1
M1

M2
L1

K2
L2

F6
F7
F8
G6
G7
G8
H6
H7
H8

BYPASS=U6201.K1:K3:5 mm

1

C6304

0.1UF

10%

6.3V

2

CERM-X5R
0201

CS4208_SPDIF_IN

CS4208_SPDIF_OUT

DMIC_CLK3_R

C6305

10UF

20%
10V
X5R-CERM
0402-1

OMIT

R6302

SHORT

1 2

402

=PP3V3_S0_AUDIO_DIG

1

2

C6306

10UF

20%
10V
X5R-CERM
0402-1

1

2

48 49 52 68

=PP3V3_S0_AUDIO_DIG

BYPASS=U6201.A7:E3:5 mm

1

C6307

0.1UF

10%

6.3V

2

CERM-X5R
0201

R6330

33

1 2

5%
1/16W
MF-LF

402

NC_DMIC_CLK0

NC_DMIC_CLK1

NC_DMIC_CLK2

R6332

75

1 2

1%
1/16W
MF-LF

402

DMIC_SDA3

49 52 71

SPDIF_OUT_JACK

71

DMIC_SDA3

DMIC_CLK3

48 49 52 68

52

OUT

71

71

49 52 71

IN

52 71

OUT

PP6301

P3MM

SM

1

PP

PLACE_NEAR=U6201.N3:5 mm

D

C

5%
MF

L6300

1 2

0201

=PP3V3_S0_AUDIO_DIG

48 49 52 68

50

OUT

52 71

IN

52 71

IN

51

OUT

12 75

IN

12 75

IN

12 71 75

OUT

12 49 75

IN

12 75

IN

71

71

71

71

71

71

71

71

1

C6300

4.7UF

20%
4V
X5R-1
402

GPIO0_SPKR_SHUTDOWN

PD_CS4208_GPIO1

SPKRCONN_L_ID
SPKRCONN_R_ID

HDA_BIT_CLK
HDA_SYNC

1

C6301

0.1UF

2

2

DFET_OPENUS
DFET_OPENCH

HDA_SDIN0

HDA_SDOUT
HDA_RST_L

NC_CS4208_MCLKA
NC_CS4208_SCLKA
NC_CS4208_LRCLKA
NC_CS4208_SDOUTA

NC_CS4208_MCLKB
NC_CS4208_SCLKB
NC_CS4208_LRCLKB
NC_CS4208_SDOUTB

PP1V5_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.07MM

VOLTAGE=1.5V

10%
16V
X7R-CERM
0402

BYPASS=U6201.J2:J1:5 mm

R6331

22

1 2

5%

1/20W

MF

201

1

R6324

100K

5%
1/20W
MF
201

2

71

71

1

R6325

100K

5%
1/20W
MF
201

2

NC_CS4208_GPO0
NC_CS4208_GPO1

CS4208_HDA_SDOUT0_R

75

TP_CS4208_HDA_SDOUT1

BYPASS=U6201.E1:F1:5 mm

1

C6302

0.1UF

10%
16V

2

X7R-CERM
0402

=PP1V5_S0_AUDIO

68

D

FERR-22-OHM-1A-0.055OHM

R6323

100K

1 2

NOSTUFF

R6322

100K

1 2

5%

1/20W

MF

201

51

1/20W

201

OUT

C

SIZE

B

A

D

B

PP6304

P3MM

SM

HDA_SDOUT

12 49 75

A

BOM_COST_GROUP=AUDIO

6 3

1

PP

PLACE_NEAR=U6201.D2:5 mm

SYNC_MASTER=JCURCIO_J44

PAGE TITLE

Audio: Codec,Digital

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/25/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

63 OF 120

SHEET

49 OF 82

124578

8 7 6 5 4 3

PP5V_S0_AUDIO_AMP_L

50 69

CRITICAL

1

NO_TEST=TRUE

SPKRAMP_LIN_P

80

SPKRAMP_LIN_N

NO_TEST=TRUE

80

SPKRAMP_RIN_N

80

NO_TEST=TRUE

C6412

47UF

20%

6.3V

TANT-POLY

R6400

2

CASE-A4

1

100K

5%
1/16W
MF-LF

402

2

CRITICAL

C6422

47UF

20%

6.3V

TANT-POLY

CASE-A4

NO_TEST=TRUE

SPKRAMP_RIN_P

A1

CRITICAL

PVDD

U6410

MAX98300

WLP

A3

IN+

B3

IN-

C2

B2

NC

PGND

1

2

U6420

MAX98300

A3

IN+

B3

IN-

C2

B2

NC

A2

A1

CRITICAL

PVDD

WLP

PGND

A2

OUT+
OUT-

GAINSHDN*

OUT+
OUT-

GAINSHDN*

B1
C1

C3

CRITICAL

L6410

FERR-1000-OHM

48 80

AUD_LO2_L_P

IN

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

APN: 353S2888 & 353S2958

D

GAIN = +3 DB
1ST ORDER FC (L&R) = NOM 569 HZ
1ST ORDER FC (SUB) = NOM 9 HZ

48 80

IN

AUD_LO2_L_N

SPKR_SHUTDOWN

50

48 80

C

48 80

IN

PP5V_S0_AUDIO_AMP_R

50 69

48 80

IN

AUD_LO3_R_P

48 80

IN

AUD_LO3_R_N

CRITICAL

L6430

FERR-1000-OHM

1 2

0402

CRITICAL

L6431

FERR-1000-OHM

1 2

80

0402

AUD_SPKRAMP_RSUBIN_P

80

NO_TEST=TRUE

AUD_SPKRAMP_RSUBIN_N

NO_TEST=TRUE

CRITICAL

C6433

0.22UF

1 2

10%
16V

CERM

402

CRITICAL

C6434

0.22UF

1 2

10%
16V

CERM

402

RSUBIN_P

NO_TEST=TRUE

RSUBIN_N

NO_TEST=TRUE

SPKR_SHUTDOWN

50

CRITICAL

C6432

100UF

20%

6.3V
TANT

CASE-AL1

1

2

B1
A1

A2

SSM2375

IN+
IN-

SD*

GND

C2

VDD

U6430

WLCSP

C1

CRITICAL

C3

OUT+

B3

OUT-

A3

GAIN

B2

EDGE

1 2

FERR-1000-OHM

1 2

CRITICAL

AUD_LO2_R_P

IN

AUD_LO2_R_N

RSUB_GAIN

80

0402

L6411

80

0402

49

IN

FERR-1000-OHM

1 2

L6421

FERR-1000-OHM

1 2

0402

CRITICAL

BYPASS=U6430.C2:C1:5 mm

1

C6431

0.1UF

10%
16V

2

X5R-CERM
0201

1

C6436

4700PF

10%
50V

2

X7R-CERM
0402

AUD_SPKRAMP_LIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LIN_N

NO_TEST=TRUE

GPIO0_SPKR_SHUTDOWN

CRITICAL

L6420

AUD_SPKRAMP_RIN_P

80

0402

80

NO_TEST=TRUE

AUD_SPKRAMP_RIN_N

NO_TEST=TRUE

CRITICAL

C6414

0.01UF

1 2

10%
50V

X7R-CERM

0402

CRITICAL

C6424

CRITICAL

C6413

0.01UF

1 2

10%
50V

X7R-CERM

0402

80

L6401

FERR-1000-OHM

1 2

0402

CRITICAL

PP5V_S0_AUDIO_AMP_R

50 69

CRITICAL

C6423

0.01UF

1 2

10%
50V

X7R-CERM

0402

0.01UF

1 2

10%
50V

X7R-CERM

SPKR_SHUTDOWN

50

0402

SPKRCONN_SR_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

MAX_LINE_WIDTH=0.40 MM

SPKRCONN_SR_OUT_N

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

MAX_LINE_WIDTH=0.40 MM

BYPASS=U6410.A1:A2:5 mm

1

C6411

0.1UF

10%
16V

2

X5R-CERM
0201

SPKR_L_GAIN

1

R6410

100K

5%
1/16W
MF-LF

402

2

B1
C1

C3

SPKR_R_GAIN

1

R6420

100K

5%
1/16W
MF-LF

402

2

BYPASS=U6420.A1:A2:5 mm

1

C6421

0.1UF

10%
16V

2

X5R-CERM
0201

52 71 80

OUT

52 71 80

OUT

SPKRCONN_L_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_N

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

B

12

SPKRCONN_L_OUT_N

OUT

OUT

OUT

OUT

52 71 80

52 71 80

52 71 80

52 71 80

D

C

B

50 69

48 80

IN

48 80

IN

AUD_LO3_L_P

AUD_LO3_L_N

CRITICAL

L6440

FERR-1000-OHM

1 2

80

0402

CRITICAL

L6441

FERR-1000-OHM

1 2

80 50

0402

AUD_SPKRAMP_LSUBIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LSUBIN_N

NO_TEST=TRUE

CRITICAL

C6443

0.22UF

1 2

10%
16V

CERM

402

CRITICAL

C6444

0.22UF

1 2

10%
16V

CERM

402

LSUBIN_P

NO_TEST=TRUE

LSUBIN_N

NO_TEST=TRUE

A

Placement Note: Place C6448 and C6449 near U6430Placement Note: Place C6447 and C6452 near U6420

NC

NC

1

C6447

0.0022UF

10%
50V

2

CERM-X7R
0603

NC

NC

1

C6452

0.0022UF

10%
50V

2

CERM-X7R
0603

NC

1

C6448

0.0022UF

10%
50V

2

CERM-X7R
0603 0603

NC

NC

1

C6449

0.0022UF

10%
50V 50V

2

CERM-X7R

NC

6 3

PP5V_S0_AUDIO_AMP_L

CRITICAL

C6442

100UF

20%

6.3V
TANT

CASE-AL1

1

2

SPKR_SHUTDOWN

B1
A1

A2

SSM2375

IN+
IN-

SD*

GND

C2

VDD

U6440

WLCSP

C1

CRITICAL

OUT+
OUT-

GAIN

EDGE

NC

NC

C3
B3

A3

B2

1

2

LSUB_GAIN

C6450

0.0022UF

10%
50V
CERM-X7R

1

C6446

4700PF

10%
50V

2

X7R-CERM
0402

BYPASS=U6440.C2:C1:5 mm

1

C6441

0.1UF

10%
16V

2

X5R-CERM
0201

Placement Note: Place C6451 near U6440Placement Note: Place C6450 near U6410

SPKRCONN_SL_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

MAX_LINE_WIDTH=0.40 MM

NC

NC

SPKRCONN_SL_OUT_N

1

C6451

0.0022UF

10%

2

CERM-X7R
06030603

BOM_COST_GROUP=AUDIO

52 71 80

OUT

52 71 80

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

MAX_LINE_WIDTH=0.40 MM

SYNC_MASTER=DIRK_J44

PAGE TITLE

OUT

Audio: Speaker Amps

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/09/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

64 OF 120

SHEET

50 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

R6550

HS_MIC_P

48 80

OUT

R6556

100K

5%

1/20W

MF

HS_MIC_N

48 80

OUT

IN

DFET_OPENCH

1

R6520

10K

5%
1/16W
MF-LF
402

2

C

49

201

R/C6550 FILTER TO ADDRESS OUT-OF-BAND
NOISE ISSUE SEEN ON EARLY HEADSETS
(SEE RADAR # 6210118)

1

C6560

1.0UF

10%
35V

2

CERM-X5R
0402

CRITICAL

1

1

C6550

3300PF

10%
10V

2

X7R-CERM
0201

2

BYPASS=U6500.B2:B1:3MM

1

C6562

0.1UF

10%
16V

2

X5R-CERM
0201

2.2K

1 2

5%
1/16W
MF-LF

402

R6559

2.2K

1 2

5%
1/16W
MF-LF

402

BYPASS=U6500.B2:B1:3MM

1

C6563

0.01UF

10%
10V

2

X5R-CERM
0201

MIN_NECK_WIDTH=0.06MM
MIN_LINE_WIDTH=0.2MM

AUD_HS_MIC_P

CRITICAL

1

C6558

27PF

5%
25V

2

C0G
0201

AUD_HS_MIC_N

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.06MM

DFET_CPO1

1

C6501

1000PF

5%
25V

2

NP0-C0G
0402

TAIC3027A0YFFR

C2

PSEL

C1

CP

IN

IN

B2

VDD

U6500

WCSP

GND

B1

52 80

52 80

OUT1
OUT2

A1

AUD_CONN_SLEEVE_XW

A2

AUD_CONN_SLEEVE_XW

51 52 80

OUT

51 52 80

OUT

D

C

IN

DFET_OPENUS

1

R6521

10K

5%
1/16W
MF-LF
402

2

1

C6530

1.0UF

10%
35V

2

CERM-X5R
0402

49

B

A

BYPASS=U6501.B2:B1:3MM

BYPASS=U6501.B2:B1:3MM

1

C6542

0.1UF

10%
16V

2

X5R-CERM
0201

1

C6543

0.01UF

10%
10V

2

X5R-CERM
0201

DFET_CPO2

1

C6502

1000PF

5%
25V

2

NP0-C0G
0402

TAIC3027A0YFFR

C2

PSEL

C1

CP

B2

VDD

U6501

WCSP

GND

B1

OUT1
OUT2

A1

AUD_CONN_RING2_XW

A2

AUD_CONN_RING2_XW

51 52 80

OUT

51 52 80

OUT

6 3

BOM_COST_GROUP=AUDIO

SYNC_MASTER=JCURCIO_J44

PAGE TITLE

Audio: Jack Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/25/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

65 OF 120

SHEET

51 OF 82

124578

SIZE

B

A

D

8 7 6 5 4 3

12

D

C

GND_AUDIO_CODEC

B

CODEC OUTPUT SIGNAL PATHS

FUNCTION
HP/HS OUT
TWEETERS
SUB
SPDIF OUT 0X0E (14) 0X21 (33) N/A

0X02 (2)
0X03 (3)
0X04 (4)
N/A

CONVERTERVOLUME
0X02 (2)
0X03 (3)
0X04 (4)

PIN COMPLEX
0X10 (16)
0X12 (18)
0X13 (19)

CODEC INPUT SIGNAL PATHS

FUNCTION
DMIC 1
DMIC 2

HEADSET MIC

CONVERTER
0X09 (9)
0X09 (9)

0X07 (7)

PIN COMPLEX
0X1C (28)
0X1C (28)

0X18 (24)

OTHER CODEC GPIO LINES

LEFT SPEAKER ID
RIGHT SPEAKER ID
DFET CONTROL

48 80

48 80

48

IN

R6602

R6603

48

IN

AUD_HP_PORT_REFCH

OUT

OUT

AUD_HP_PORT_REFUS

48 80

OUT

AUD_HP_PORT_L

1

2.2K

5%
1/16W
MF-LF

402

2

1

2.2K

5%
1/16W
MF-LF

402

2

AUD_HP_PORT_R

49

48 49 52 68

51 80

OUT

AUD_US_HS_GND

51 80

OUT

48

OUT

48

OUT

48

OUT

SPDIF_OUT_JACK

IN

=PP3V3_S0_AUDIO_DIG

GPIO2
GPIO3
GPIO4

120-OHM-25%-1.3A

1 2

AUD_HS_MIC_P

120-OHM-25%-1.3A

1 2

AUD_HS_MIC_N

120-OHM-25%-1.3A

AUD_TIPDET_2

AUD_TIPDET_1

120-OHM-25%-1.3A

AUD_TYPEDET

INPUT
INPUT
OUTPUT

CRITICAL

L6611

0402

AUD_CH_HS_GND

48 80

OUT

CRITICAL

L6613

0402

CRITICAL

L6604

1 2

0402

CRITICAL

L6608

FERR-470-OHM

1 2

0201

CRITICAL

L6605

1 2

0402

L6606

FERR-470-OHM

1 2

HIGH = FG, LOW = MERRY
HIGH = FG, LOW = MERRY
HIGH = DFETs OPEN

AUD_CONN_SLEEVE

80

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM

XW6601

1 2

AUD_CONN_RING2

80

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM

XW6603

1 2

AUD_CONN_HP_LEFT

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.06MM

CRITICAL

L6607

FERR-470-OHM

1 2

0201

AUD_CONN_HP_RIGHT

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.06MM

CRITICAL

0201

AUD_CONN_TYPEDET

SM

SM

AUD_CONN_TIPDET_2

AUD_CONN_TIPDET_1

MUTE CONTROL

N/A
CODEC GPIO0
CODEC GPIO0

VREF

3.3V

3.3V

2.7V

CRITICAL

L6612

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6614

120-OHM-25%-1.3A

1 2

0402

=PP3V3_S0_AUDIO_DIG

48 49 52 68

49 71

OUT

49 71

OUT

PLACE_NEAR=J6600.5:5mm

XW6600

SM

1 2

AUD_CONN_SLEEVE_XW

51 80

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.1MM

PLACE_NEAR=J6600.6:5mm

XW6602

SM

1 2

AUD_CONN_RING2_XW

51 80

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.1MM

DMIC_SDA3

DMIC_CLK3

OMIT

R6680

SHORT

1 2

402

DMIC_SDA2

71

2-MIC CONNECTOR

APN: 518S0818

CRITICAL

J6601

FF14A-6C-R11DL-B-3H

F-RT-SM
7

1
2
3
4
5
6

8

SPKRCONN_L_OUT_P

50 71 80

IN

SPKRCONN_L_OUT_N

50 71 80

IN

SPKRCONN_L_ID

49 71

IN

SPKRCONN_SL_OUT_P

50 71 80

IN

SPKRCONN_SL_OUT_N

50 71 80

IN

SPKRCONN_R_OUT_P

50 71 80

IN

SPKRCONN_R_OUT_N

50 71 80

IN

SPKRCONN_R_ID

49 71

IN

SPKRCONN_SR_OUT_P

50 71 80

IN

SPKRCONN_SR_OUT_N

50 71 80

IN

SPEAKER CONNECTOR

HP=80HZ

APN: 518S0672

NC

1

C6600

1UF

10%
10V
X5R
402

1

C6601

0.1UF

10%

2

6.3V

2

CERM-X5R
0201

CRITICAL

J6602

78171-6006

M-RT-SM

7

1
2
3
4
5
6

8

CRITICAL

J6603

78171-6006

M-RT-SM

7

1
2
3
4
5
6

8

APN: 514-0875

J6600

AUDIO-SPDIF-J44

F-RT-TH

5

MIC

6

AUDIO GND

2

2RTN

1

DET2

8

DET1

7

1RTN

3

R.AUDIO

4

AUDIO GND

AUDIO

9

VIN

10

VDD

11

GND

OPERATING VOLTAGE 3.3

POF
12
13

SHELL

14

PINS

15

D

C

B

CRITICAL

2

1

2

DZ6603

ESDALC5-1BM2 ESDALC5-1BM2

SOD882

1

C6606

100PF

5%
25V
C0G

0201

1

R6601

10K

5%
1/16W
MF-LF
402

2

C6602

100PF

0201

CRITICAL

2

DZ6607

ESDALC5-1BM2

SOD882

1

1

5%

25V

2

C0G

CRITICAL

DZ6601

ESDALC5-1BM2

SOD882

1

C6603

100PF

5%
25V

2

C0G
0201

2

1

C6604

100PF

0201

1

5%

25V

2

C0G

C6605

100PF

CRITICAL

2

DZ6602

ESDALC5-1BM2

SOD882

1

0201

5%
25V
C0G

A

6 3

1

2

CRITICAL

2

DZ6606

SOD882

1

CRITICAL

DZ6605

ESDALC5-1BM2

SOD882

1

C6607

100PF

5%
25V

2

C0G
0201

2

C6608

100PF

5%
25V
C0G

1

0201

CRITICAL

2

1

2

DZ6604

ESDALC5-1BM2

SOD882

1

BOM_COST_GROUP=AUDIO

SYNC_MASTER=JCURCIO_J44

PAGE TITLE

Audio: Jack Translators

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=05/13/2013

051-1573

8.0.0
dvt1

66 OF 120

52 OF 82

SIZE

A

D

124578

8 7 6 5 4 3

MagSafe DC Power Jack

PP18V5_DCIN_FUSE

CRITICAL

J7000

D

WTB-PWR-M82

M-RT-SM

1
2
3
4
5
6

518S0508

The chassis ground will otherwise float and can
send transients onto ADAPTER_SENSE when AC is
connected.

71

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V

TP_TDM_ONEWIRE_MPM

ADAPTER_SENSE

71

69

1-Wire OverVoltage Protection

NO STUFF

1

C7005

0.1UF

10%
50V

2

X7R
603-1

C7000

0.1UF

20%
10V

CERM

402

C

CRITICAL

F7005

6AMP-32V-0.0095OHM

1 2

0603

SMC_BC_ACOK_VCC

1

1

2

VCC

U7000

MAX9940

SC70-5

5

EXT INT

CRITICAL

NC GND

2

3

NC

CRITICAL

U7001

TC7SZ08FEAPE

SOT665

4

1

2

4

=PP3V42_G3H_ONEWIREPROT

1

C7008

0.1UF

20%
10V

2

CERM
402

2

A

1

B

PLACE_NEAR=U7001.5:1MM

68

5

Y

3

R7029

2.0K

5%
1/16W
MF-LF
402

SYS_ONEWIRE

DCIN_ISOL_BLEEDER_R

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

SMC_BC_ACOK

=PP18V5_DCIN_ISOL

38

BI

3

Q7030

2N7002

SOT23-HF1

2

68

38 39

IN

BLEEDER

1

R7030

1K

5%
1/16W
MF-LF
402

2

BLEEDER

D

1

G

S

DCIN_ISOL_BLEEDER_NGATE

BLEEDER

CRITICAL

D7020

SBR0330CW

SOT-323
1

3

DCIN_ISOL_BLEEDER_PSRC

2

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

1

C7020

0.1UF

10%

BLEEDER

50V

2

X7R
603-1

2

BLEEDER

S

1

G

D

3

BLEEDER

1

R7021

10K

5%
1/16W
MF-LF
402

2

Q7020

AO3407A

SOT23

SI5419DU

1

DCIN_ISOL_GATE_R

Q7010

POWERPAK

D

G

C7012

4

0.047UF

5A

S

=PP18V5_DCIN_CONN

5

1

10%
25V

2

X7R

0402

6.8V Zener

R7011

10K

1 2

1%

1/20W

MF

201

68

1

R7012

68K

1%
1/20W
MF
201

2

1

R7010

100K

5%
1/20W
MF
201

2

DCIN_ISOL_GATE

K

D7010

GDZT2R6.8

GDZ-0201

A

Input impedance of 68K meets
sparkitecture requirements
for both MPM4 and MPM5.

When input voltage is 2V the FET will be off
blocking the leakage path and 22.1K can be
properly detected.

When input voltage is at 16V+, FET will
conduct and power charger and 3.42V reg

12

D

C

R7020

47

1 2

1%

1/3W

MF

805

R7005

10

=PPBUS_G3H

54 68

B

518-0394

CRITICAL

J7050

BAT-J44

F-ST-TH

PWR

1 10

PWR

2 11

PWR

3 12
4 13

NC

5 14

NC

6 15
7 16
8 17
9 18

SMBUSSCL
SMBUSSDA

SYSDETL

GND
GND
GND

PPVBAT_G3H_CONN

1

C7050

0.1UF

10%
25V

2

X5R
402

C7060

1UF

10%
25V
X5R

603-1

54 71

=SMBUS_BATT_SCL
=SMBUS_BATT_SDA

SYS_DETECT_L

CRITICAL

D7050

RCLAMP2402B

1

2

SC-75

1

2

3

1 2

5%

1/8W

MF-LF

805

BI
BI

1

R7050

10K

5%
1/16W
MF-LF
402

2

PP18V5_DCIN_CONN_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V

PPBUS_G3H_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V

41

41

71

A

6 3

CRITICAL

D7005

SBR0330CW

SOT-323
1

2

3

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

C7092

4.7UF

10%
25V

X6S-CERM

0603

1

2

C7091

4.7UF

X6S-CERM

0603

10%
25V

1

2

C7090

4.7UF

X6S-CERM

0603

10%
25V

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

6

U7090

DFN

GND

5

1

5%

2

BOOST

THRM

3

BIAS

PAD

SW

FB

9

1

2

1

R7080

0

5%
1/20W
MF
0201

2

NO STUFF

1

R7081

49.9K

1%
1/20W
MF
201

2

VIN

LT3470AED

8 4

SHDN*

CRITICAL

7

NC

NC

P3V42G3H_SHDN_L

NO STUFF

C7080

1000PF

25V
CERM
0402

BOM_COST_GROUP=POWER

P3V42G3H_BOOST

DIDT=TRUE

NO_TEST=TRUE

SWITCH_NODE=TRUE

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm

2

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE
DIDT=TRUE

1

P3V42G3H_FB

C7094

Vout = 1.25V * (1 + Ra / Rb)

=PP3V42_G3H_REG

C7010

1

0.22UF

CERM

10%
10V

402

CRITICAL

L7095

2

10UH-20%-0.85A-0.46OHM

1 2

2520

Vout = 3.425V
300MA MAX OUTPUT

1

C7095

22PF

5%
50V

2

C0G
0201

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

R7095

348K

1/20W

R7096

200K

1/20W

<Ra>

201

<Rb>

201

1

1%
MF

2

1

1%
MF

2

(Switcher limit)

CRITICAL

1

C7099

22UF

20%

6.3V

2

X5R
0603

DC-In & Battery Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NP0-C0G

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

1

12PF

5%

25V

2

0201

SYNC_DATE=01/09/2013

051-1573

8.0.0
dvt1

70 OF 120

53 OF 82

68

B

A

SIZE

D

8 7 6 5 4 3

12

Reverse-Current Protection

R7192

0

CHGR_DCIN_D_R

54

Inrush Limiter

NC

D

CRITICAL

1UF

10%
10V
X5R
402

NCNCNC

879

10

D

1

2

NO_XNET_CONNECTION=TRUE

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE
DIDT=TRUE

OUT
OUT
OUT

C7126

0.001UF

415

C7180

4.7UF

X6S-CERM

S

NOSTUFF

G

6

1

C7120

0.047UF

10%
10V

2

X5R-CERM
0402

C7122

0.1UF

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

42

42

39

1

10%
50V

2

X7R-CERM

0402

1

10%
25V

2

0603

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

(CHGR_SGATE)

R7121

10

1 2

1/16W
MF-LF

402

R7122

10

1 2

1/16W
MF-LF

1

10%
25V

2

X5R
402

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

DIDT=TRUE

402

1

C7121

0.1UF

10%
25V

2

X5R
402

NO_XNET_CONNECTION=TRUE

1

C7125

0.22UF

10%
10V

2

CERM
402

PLACE_NEAR=U7100.23:2MM

5%

5%

FROM ADAPTER

=PPDCIN_S5_CHGR

68

D

1

2

=PPDCIN_S5_CHGR_ISOL

68

CRITICAL

D7105

SBR0330CW

SOT-323
1

ACIN pin threshold is 3.2V, +/- 50mV
Divider sets ACIN threshold at 13.55V
Input impedance of ~90K meets

sparkitecture requirements

=PP3V42_G3H_CHGR

68

C

1

2

R7112

1/16W
MF-LF

R7110

68.1K

1%
1/16W
MF-LF
402

402

1

1K

1%

2

71
40

SMC_RESET_L

38

IN

39
47

C7102

1UF

10%
10V
X5R
402

1

2

GND_CHGR_AGND

R7100

0

1 2

5%

41

1/16W
MF-LF

41

402

64

54

IN

BI

IN

Float CELL for 1S

1

R7111

21.5K

1%
1/16W
MF-LF
402

2

B

1

R7115

100K

1%
1/16W
MF-LF
402

2

CHGR_VCOMP_R

1

R7142

1K

1%
1/16W
MF-LF
402

2

CHGR_VNEG_R

1

C7116

470PF

10%
50V

2

CERM
0402

CHGR_ICOMP_RC

1

C7142

0.068UF

10%
10V

2

X5R-CERM
0402

1

C7115

330PF

5%
50V

2

COG
402

R7116

3.01K

1/16W
MF-LF

402

80

80

1

1%

2

2

30mA max load

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

NO STUFF

1

R7102

100K

5%
1/16W
MF-LF
402

2

CHGR_RST_L
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
CHGR_VFRQ
CHGR_CELL

CHGR_ACIN
CHGR_ICOMP

CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N

1

C7150

1UF

10%
16V

2

X5R
402

C7111

0.01UF

X7R-CERM

C7185

0.1UF

10%
25V
X5R
402

R7186

10%
16V

0402

1

R7185

470K

1/16W
MF-LF

402

2

332K

1%
1/16W
MF-LF

402

3

CHGR_DCIN_D_R

54

1

2

1%

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

1

2

R7101

4.7

1 2

5%
1/16W
MF-LF

402

19

VDD

12

VHST

CRITICAL

13

SMB_RST_N

11

SCL

U7100

10

SDA

4

VFRQ

6

CELL

3

ACIN

5

ICOMP

7

VCOMP

8

VNEG

18

CSOP

17

CSON

(AGND)

29

1

C7100

1UF

10%
10V

2

X5R
402

Q7180

IRF9395TRPBF

DIRECTFET-MC

(CHGR_AGATE)

R7105

20

1 2

5%
1/16W
MF-LF

402

54

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

20

VDDP

DCIN

SGATE
AGATE

TQFN

CSIP

CSIN

BOOT

UGATE

ISL6259

PHASE

LGATE

BGATE

AMON

20V/V

BMON

36V/V

ACOK

(OD)

THRM_PAD

PGND

353S2929

22

PLACE_NEAR=U7100.29:1MM

XW7100

SM

1 2

PLACE_NEAR=U7100.22:1MM

C7105

0.22UF

X5R-CERM

0603-1

2

S

G

3

(CHGR_DCIN)

PP5V1_CHGR_VDDP

C7101

2

CHGR_DCIN

54

26

CHGR_SGATE

1

CHGR_AGATE

28

CHGR_CSI_P

80

27

CHGR_CSI_N

80

25

CHGR_BOOT

24

CHGR_UGATE

23

21

CHGR_LGATE

16

CHGR_BGATE

9

CHGR_AMON

15

CHGR_BMON

14

=CHGR_ACOK

(GND)

(CHGR_CSO_P)
(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

1

10%
50V

2

GND_CHGR_AGND

54

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.116 mm
MIN_NECK_WIDTH=0.116 mm
VOLTAGE=18.5V

1

R7180

100K

5%
1/16W
MF-LF
402

2

1

R7181

62K

5%
1/16W
MF-LF
402

2

CHGR_CSI_R_P

80

CHGR_CSI_R_N

80

2 3 4 9

1

8

5 6 7

R7151
R7152

2.2
0

CRITICAL

10

1 2

1 2

Q7130

NTMFD4902NF

DFN

5%

5%

1 2

5% 402

MF-LF

1/16W

OMIT_TABLE
CRITICAL

123

R7120

0.02

0.5%
1W
MF
RL1632W

4

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

Max Current = 8.5A

CHGR_PHASE

CHGR_CSO_R_P

44 80

1/16W

CHGR_CSO_R_N

44 80

1/16W

(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)

MF-LF

MF-LF

402

402

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

P5V1_VIN

1

C7190

4.7UF

10%
25V

2

X6S-CERM

0603

8 4

SHDN*

7

NC

NC

1

2

(L7130 limit)
f = 400 kHz

CRITICAL

4.7UH-20%-8.5A-18.3MOHM

L7130

1 2

PIME103T-4R7MS

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V

CRITICAL

R7150

0.005

1%
1W
MF

0612-6

6

VIN

U7190

LT3470A

CRITICAL

CRITICAL CRITICAL

C7130

22UF

20%
25V
POLY-TANT
CASE-D2-SM

12

MIN_LINE_WIDTH=0.6 mm

34

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V

For Erp Lot6 spec

P5V1_BOOST

DIDT=TRUE

NO_TEST=TRUE

SWITCH_NODE=TRUE

3

BOOST

DFN

SW

2

BIAS

1

FB

THRM

GND

PAD

5

9

Vout = 1.25V * (1 + Ra / Rb)

1

C7131

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

1

C7148

12PF

5%
25V

2

NP0-C0G
0201

PPVBAT_G3H_CHGR_R

C7155

1

C7194

0.22UF

10%
10V

2

CERM

402

33UH-20%-0.39A-0.435OHM

P5V1_SW

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE
DIDT=TRUE

1

2

P5V1_FB

CRITICAL

1

C7132

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

CRITICAL

1

C7140

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

C7156

1UF

10%
25V
X5R
402

0.1UF

10%
25V

2

X5R
402

CRITICAL

L7195

1 2

DP418C-SM

P5V1_BIAS

C7195

22PF

5%
50V
C0G
0201

1

C7135

1.0UF

10%
50V

2

X5R
0603

1

C7145

0.001UF

2

1

C7157

0.01UF

2

X7R-CERM

R7195

681K

R7196

200K

1

2

PLACE_NEAR=Q7130.2:1MM

CRITICAL

F7140

12AMP-32V

1 2

10%
50V
X7R-CERM
0402

1

10%
50V

2

0402

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

<Ra>

1/20W

<Rb>

1/20W

C7136

1.0UF

10%
50V
X5R
0603

1206

201

201

1%
MF

1%
MF

1

2

1

2

CRITICAL

SI7137DP

S

3
2
1

CRITICAL

1

C7198

10UF

20%
25V

2

X5R-CERM
0603

1

C7137

0.001UF

20%
50V

2

CERM
0402

Q7155

SO-8

SYM-VER-2

G

4

PLACE_NEAR=C7136.1:3mm

D

(P5V1_BIAS)

CRITICAL

1

C7199

10UF

20%
25V

2

X5R-CERM
0603

5

NOSTUFF

R7190

0

1 2

CHGR_DCIN

5% 402

MF-LF

1/16W

R7191

0

1 2

MF-LF

PP5V1_CHGR_VDDP

5% 402

1/16W

Vout = 5.50V
250MA MAX OUTPUT
(Switcher limit)

1

C7146

12PF

5%
25V

2

NP0-C0G
0201

TO SYSTEM

=PPBUS_G3H

TO/FROM BATTERY

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V

1

C7147

12PF

5%
25V

2

NP0-C0G
0201

53 68

53 71

54

54

D

C

B

A

PART NUMBER

107S0387

QTY

1

RES,MTL FILM,1W,20MOHM,0.5%,0612,LF,BLK

DESCRIPTION

REFERENCE DES

R7120

CRITICAL

CRITICAL

BOM OPTION

BOM_COST_GROUP=POWER

6 3

SYNC_MASTER=AHARTMAN_J52

PAGE TITLE

PBus Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

71 OF 120

SHEET

54 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

PART NUMBER

353S00036

D

=PP5V_S0_CPUVR

56 68 56 68

R7235

10K

CPUVR_NTC_R

1%

1/20W

MF

201

845

0.01UF

10%
10V
X7R-CERM
0201

0

5%

1/20W

MF

0201

MF

PLACE_NEAR=Q7310.3:3MM

1

2

1

2

CPUVR_ISUMN_RC

R7210

316

1 2

1/20W

1

C7211

0.01UF

10%
10V

2

X7R-CERM
0201

CPU_VCCSENSE_P_R

NO_XNET_CONNECTION=TRUE

R7237

100KOHM

0201

1%
MF

201

C7242

100PF

5%
25V
C0G

0201

PLACE_NEAR=L7310.1:3MM

R7236

95.3K

=PP1V05_S0_CPU_VCCST

6 8

15 16 17 68

1

2

C7214

220PF

10%
25V

X7R-CERM

201

C7213

0.1UF

1

R7280

130

1%
1/20W
MF
201

2

PLACE_NEAR=U7200.30:2mm

1

2

1

10%

6.3V

2

X6S

0201

NO_XNET_CONNECTION=TRUE

R7215

1 2

1% 201

1/20W

1

C7210

2

R7243

1 2

C7278

PLACE_NEAR=R7279.1:3mm

8

73

C

BI

8

73

OUT

8

73

IN

56

IN

56

IN

56

IN

56

IN

1

0.1UF

6.3V
0201

CPU_VIDSOUT
CPU_VIDALERT_L
CPU_VIDSCLK

R7279

10%

2

X6S

PLACE_NEAR=U7200.32:2mm

CPUVR_ISUMP

NO_XNET_CONNECTION=TRUE

CPUVR_ISUMN

CPUVR_ISEN1
CPUVR_ISEN2

54.9

1/20W

201

1%
MF

B

CPU_VCCSENSE_P

8

73

IN

CPU_VCCSENSE_N

9

73

IN

1 2

1%

1/20W

MF

201

C7215

820PF

1 2

10%
25V

CPUVR_COMP_RC

NO_XNET_CONNECTION=TRUE

12

CPU_VCCSENSE_P_RC

XW7261

SM

1 2

NO_XNET_CONNECTION=TRUE

(GND)

1

R7223

16.9KMF9.31K

1%
1/20W
MF
201

2

X7R-CERM

0201

C7240

R7241

1.69K

1 2

1%

1/20W

MF

201

1

R7222

1%
1/20W

201

2

1.2NF

+/-10%

10V

CERM

0201-1

R7240

75K

1/20W

201

1%
MF

1

2

1

2

R7242

1

R7221

34K

1/20W
MF
201

2

C7216

22PF

1 2

5%

25V

C7241

39PF

NP0-C0G

0201

1K

1%

1/20W

MF

201

0201

C0G

1

5%

25V

2

NO_XNET_CONNECTION=TRUE

12

1

R7220

6.04K

1%1%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

R7201

1

1 2

5%
1/16W
MF-LF

402

PLACE_NEAR=U7200.16:2mm

CPUVR_NTC
CPU_PROCHOT_L

6

38 39 73

OUT

CPUVR_SLOPE
CPUVR_PROG1

CPUVR_PROG2
CPUVR_PROG3

CPU_VR_EN

8

17

IN

CPUVR_COMP
CPU_RTN
CPUVR_FB

CPUVR_FB2

(CPUVR_ISUMP)

CPUVR_ISUMN_R
CPUVR_IMON

44

OUT

NOSTUFF

R7250

2K

1 2

1%

1/20W

MF

201

QTY

1

IC,ISL95826AS2378,PWM,PG,VR12.5/6,QFN-32

PP5V_S0_CPUVR_VDD

C7230

1500PF

0201

10%
10V
X7R

1

C7201

1UF

10%
10V

2

X6S-CERM
0402

1

2

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

CPUVR_FB_RC

DESCRIPTION

PPVIN_S0_CPUVR_VIN

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.9V

16

17

VINVDD

U7200

ISL95826

5

4

29

28
27
26 20

1

30
31
32

6

13

7
8

15
14

3

12
11
10

1

R7230

95.3K

1%
1/20W
MF
201

2

NTC

OMIT_TABLE

VR_HOT*

SLOPE

PROG1
PROG2
PROG3

VR_ON

SDA
ALERT*
SCLK

CRITICAL

COMP

RTN

FB
FB2

ISUMP
ISUMN

IMON

ISEN1
ISEN2
ISEN3

NOSTUFF

1

C7250

330PF

10%
16V

2

X7R
0201

LLP

THRM

33

PAD

FCCM

PWM3
PWM2
PWM1

DRSEL

PGOOD

NC
NC
NC
NC

REFERENCE DES

U7200

C7202

0.22UF

0402

FCCM = 1: Forced CCM
FCCM = 0: DCM
FCCM = FLOATING: PS4

18

CPUVR_FCCM

23

NC

22

CPUVR_PWM2
CPUVR_PWM1

25

CPUVR_DRSEL

2

CPUVR_PGOOD

9

NC

19

NC

21

NC

24

NC

10%
25V
X7R

1

2

CRITICAL

CRITICAL

R7202

10

1 2

5%
1/16W
MF-LF

402

PLACE_NEAR=U7200.17:2mm

56

OUT

56

OUT

56

OUT

17

OUT

BOM OPTION

=PPVIN_S0_CPUVR

NOSTUFF

1

R7225

0

5%
1/20W
MF
0201

2

R7224

0

1 2

5%

1/20W

MF

0201

D

C

B

1

C7260

330PF

10%
16V

2

X7R
0201

A

1

C7261

330PF

10%
16V

2

X7R
0201

6 3

BOM_COST_GROUP=POWER

SYNC_MASTER=J41

PAGE TITLE

CPU VR12.6 VCC Regulator IC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

72 OF 120

SHEET

124578

8.0.0

dvt1

55 OF 82

SIZE

A

D

8 7 6 5 4 3

=PPVIN_S0_CPUVR

55 68

CRITICAL

1

C7313

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

=PP5V_S0_CPUVR

55 56 68

G

4

R7311

2.2

5%
1/16W
MF-LF

402

G

4

R7321

2.2

5%
1/16W
MF-LF

402

5

OMIT_TABLE

CRITICAL

D

Q7310

SISA18DN

PWRPAK-SM

S

1 2 3

4

21

CPUVR_BOOT1_RC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE

5

OMIT_TABLE

CRITICAL

D

Q7320

SISA18DN

PWRPAK-SM

S

1 2 3

12

CPUVR_BOOT2_RC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE

CPUVR_PHASE1

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
SWITCH_NODE=TRUE

5

OMIT_TABLE

CRITICAL

D

S

1 2 3

Q7311

SISA12DN

PWRPAK-SM

G

NOSTUFF

R7312

1/10W
MF-LF

CPUVR_PHASE2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
SWITCH_NODE=TRUE

2.2

603

5%

R7322

5

OMIT_TABLE

CRITICAL

D

S

1 2 3

Q7321

SISA12DN

PWRPAK-SM

G

4

1

C7310

1UF

10%
16V

2

PWM

FCCM

GND

PWM

FCCM

GND

X6S-CERM

6

VCC

U7310

ISL6208D

DFN

CRITICAL

THRM

PAD

4

9

C7320

X6S-CERM

6

VCC

U7320

ISL6208D

DFN

CRITICAL

THRM

PAD

4

9

0402

BOOT

UGATE

PHASE

LGATE

1UF

10%
16V

0402

BOOT

UGATE

PHASE

LGATE

1

2

CPUVR_UGATE1

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE

GATE_NODE=TRUE

2

1

8

5

CPUVR_BOOT1

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE

CPUVR_UGATE2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE

GATE_NODE=TRUE

2

1

8

5

CPUVR_LGATE2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE

GATE_NODE=TRUE

CPUVR_BOOT2

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE

CPUVR_LGATE1

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE

GATE_NODE=TRUE

C7311

0.22UF

1 2

10%
16V

CERM

402

C7321

0.22UF

1 2

10%
16V

CERM

402

D

PHASE 1

CPUVR_PWM1

55

IN

CPUVR_FCCM

55 56

IN

C

=PP5V_S0_CPUVR

55 56 68

3

7

353S3942

PHASE 2

55

55 56

CPUVR_PWM2

IN

CPUVR_FCCM

IN

3

7

353S3942

B

L7310

0.4UH-20%-23A

1 2

PILE063T-SM

152S1821

1

2

NOSTUFF

1

2.2

5%
1/10W
MF-LF

603

2

CRITICAL

CPUVR_PH1_SNUB

DIDT=TRUE

NOSTUFF

1

C7312

0.001UF

10%
50V

2

X7R-CERM
0402

CRITICAL

L7320

0.4UH-20%-23A

1 2

PILE063T-SM

152S1821

CPUVR_PH2_SNUB

CRITICAL

1

C7314

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

PPVCC_S0_CPU_PH1

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V

CPUVR_ISNS1_P

CRITICAL

1

C7323

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

PPVCC_S0_CPU_PH2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V

DIDT=TRUE

NOSTUFF

1

C7322

0.001UF

10%
50V

2

X7R-CERM
0402

NOSTUFF

CRITICAL

1

C7315

10UF

20%
16V

2

0603

R7315

1K

1%

1/20W

MF

201

CRITICAL

1

C7324

33UF

20%
16V

2

POLY-TANT
CASED12-SM

CPUVR_ISNS2_P

R7325

0.00075

1

2

NOSTUFF

CRITICAL

1

C7325

10UF

20%
16V

2

X6S-CERM
0603

1K

1/20W

201

NOSTUFF

CRITICAL

1

C7316

10UF

20%
16V

2

X6S-CERMX6S-CERM
0603

CRITICAL

R7310

1%
1W
MF

0612-1

12
34

CPUVR_ISNS1_N

1

R7314

2

NO_XNET_CONNECTION=TRUE

1

R7316

200K

1%
1/20W
MF
201

2

CRITICAL

R7320

0.00075

0612-1

1 2
3 4

1

1%
MF

2

1

2

1.00

1%
1/20W
MF-LF
0201

CPUVR_ISUMN

CPUVR_ISEN1
CPUVR_ISUMP

NOSTUFF

CRITICAL

1

C7326

10UF

20%
16V

2

X6S-CERM
0603

1%
1W
MF

CPUVR_ISNS2_N

1

R7324

1.00

1%
1/20W
MF-LF
0201

2

NO_XNET_CONNECTION=TRUE

1

R7326

200K

1%
1/20W
MF
201

2

C7317

1UF

20%
35V
CER-X6S
0402

1

C7327

1UF

20%
35V

2

CER-X6S
0402

CPUVR_ISUMN

CPUVR_ISEN2
CPUVR_ISUMP

THESE TWO CAPS ARE FOR EMC

1

2

1

C7318

0.001UF

10%
50V
X7R-CERM
0402

C7319

0.001UF

10%
50V

2

X7R-CERM
0402

43 56 80 43 80

OUTOUT

OUT

OUT

OUT

THESE TWO CAPS ARE FOR EMC

1

C7328

0.001UF

10%
50V

2

X7R-CERM
0402

43 56 80 43 80

OUTOUT

1

2

55 56

55

55 56

C7329

0.001UF

10%
50V
X7R-CERM
0402

55 56

OUT

55

OUT

55 56

OUT

OMIT

R7317

NOSTUFF

1 2

NONE
NONE
NONE
0201

NOSTUFF

CPUVR_ISNS2_N

NO_XNET_CONNECTION=TRUE

OMIT

R7327

1 2

NONE
NONE
NONE
0201

CPUVR_ISNS1_N

NO_XNET_CONNECTION=TRUE

Additonal Input Bulk Caps

CRITICAL

1

C7371

33UF

20%
16V

2

POLY-TANT
CASED12-SM

Note: C7377, C7379 were removed. Area
where the pads used to reside was preserved.

43 56 80

1

2

43 56 80

CRITICAL

C7370

33UF

20%
16V

POLY-TANT
CASED12-SM

CRITICAL

1

C7376

33UF

20%
16V

2

POLY-TANT
CASED12-SM

1

2

CRITICAL

1

C7374

33UF

20%
16V

2

POLY-TANT
CASED12-SM

NOSTUFF

CRITICAL

C7381

33UF

20%
16V

POLY-TANT
CASED12-SM

CRITICAL

1

C7372

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7378

33UF

20%
16V

2

POLY-TANT
CASED12-SM

CRITICAL

1

C7373

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

=PPVCC_S0_CPU_REG

Vout = 1.85V max
40A MAX OUTPUT
F = 800KHZ

CRITICAL

1

C7380

33UF

20%
16V

2

POLY-TANT
CASED12-SM

CRITICAL

1

C7375

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

12

NOSTUFF

CRITICAL

1

C7382

33UF

20%
16V

2

POLY-TANT
CASED12-SM

D

C

68

B

A

SYNC_MASTER=J41

PAGE TITLE

CPU VR12.6 VCC Power Stage

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=POWER

6 3

IV ALL RIGHTS RESERVED

.

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

73 OF 120

SHEET

56 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

1.2V S3 Regulator

=PPVIN_S3_DDRREG

68

CRITICAL

1

C7431
68UF

20%
16V

2

POLY-TANT

R7425

402

5%

0

1 2

64

XW7460

SM

1 2

PLACE_NEAR=C7461.1:3mm

CRITICAL

C7460

10UF

X5R-CERM

0603

PLACE_NEAR=C7461.1:4mm

CASE-D2E-SM

MF-LF

1/16W

1

20%
25V

2

=PPVIN_S0_DDRREG_LDO

68

VTT Enable

1

R7418

51.1K

1%
1/16W
MF-LF
402

2

CRITICAL

1

C7401

10UF

20%
10V

2

X5R-CERM

0402-1

PLACE_NEAR=U7400.2:1MM

2

VLDOIN

12 15

V5IN

S3
S5

VREF

REFIN

MODE
TRIP

TPS51916

CRITICAL

PGND

10

U7400

QFN

GND

7

VTT

4

VDDQSNS

THRM

PADGND

17
16

6

8

19
18

VBST
DRVH

DRVL

PGOOD

VTTSNS

VTTREF

21

DDRREG_VBST

DDRREG_DRVH

14

DDRREG_LL

13

SW

SWITCH_NODE=TRUE

DIDT=TRUE

DDRREG_DRVL

11

DDRREG_PGOOD

20

DDRREG_VDDQSNS

9

=PPVTT_S0_DDR_LDO

68

3

VTT

1

DDRREG_VTTSNS
=PPVTT_S3_DDR_BUF

68

5

10mA max load

2

XW7400

SM

1

PLACE_NEAR=U7400.21:1MM

MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

DIDT=TRUE

C7450

0.22UF

CERM

NO_TEST=TRUE

GATE_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

C7460, C7461 close to memory

1

10%
10V

2

402

OUT

=PP5V_S3_DDRREG

68

CRITICAL

1

C7400

10UF

20%
10V

2

X5R-CERM

0402-1

PLACE_NEAR=U7400.12:1MM

=DDRVTT_EN

17

C

64

IN
IN

=DDRREG_EN

VDDQ/VTTREF Enable

DDRREG_1V8_VREF

C7415

0.1UF

X7R-CERM

0402

PLACE_NEAR=U7400.6:1MM

1

10%
16V

2

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0V

1

R7415

28.7K

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U7400.8:5mm

PLACE_NEAR=U7400.8:5mm

1

R7416

57.6K

1%
1/16W
MF-LF
402

2

1

C7416

0.01UF

10%
16V

2

X7R-CERM
0402

PLACE_NEAR=U7400.8:1MM

PLACE_NEAR=U7400.19:3MM

1

R7417
200K

1%
1/16W
MF-LF
402

2

DDRREG_FB
DDRREG_MODE

DDRREG_TRIP

PLACE_NEAR=U7400.18:3MM

CRITICAL

1

C7434
68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST_RC

MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

DIDT=TRUE

1

2

CRITICAL

C7461

10UF

20%
25V
X5R-CERM
0603

PLACE_NEAR=C7460.1:4mm

(DDRREG_LL)

1

C7432

1.0UF

10%
35V

2

CERM-X6S
0402

PLACE_NEAR=Q7430.5:3mm PLACE_NEAR=Q7430.5:3MM

(DDRREG_DRVH)

C7425

0.1UF

1 2

10%
25V
X5R
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

(DDRREG_DRVL)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

(DDRREG_VDDQSNS)

PLACE_NEAR=Q7430.2:1MM

1

C7435

1.0UF

10%
35V

2

CERM-X6S
0402

1

6

1

C7433

0.001UF

20%
50V

2

CERM
0402

PLACE_NEAR=C7435.1:3MM

2

PHASE

3 4 5

1

C7420

12PF

5%
25V

2

NP0-C0G
0201

CRITICAL
Q7430
FDMS3602S

POWER56

1.0UH-20%-15A-0.0066OHM

7

CRITICAL

L7430

1 2

PIME063T-SM

152S1822

43 57

43 57 68

PPDDR_S3_REG_R

43
57

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM

PPDDR_S3_REG_R

OUT

=PPDDR_S3_REG

OUT

XW7450

1 2

SM

CRITICAL

1

C7442
330UF

20%

2.0V

2

POLY-TANT
CASE-B2-SM1

CRITICAL

1

C7440
330UF

20%

2.0V

2

POLY-TANT
CASE-B2-SM1

CRITICAL

C7441

330UF

2.0V

POLY-TANT

CASE-B2-SM1

1

1

20%

2

2

PLACE_NEAR=C7442.1:2MM

C7445

10UF

20%
25V
X5R-CERM
0603

=PPDDR_S3_REG

1

C7446

0.001UF

10%
50V

2

X7R-CERM
0402

VOUT = 1.2V
9A MAX OUTPUT

f = 400 kHz

2

XW7401

SM

1

43 57 68

D

C

SIZE

B

A

D

B

R7401

10

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm

1 2

5%

1/20W

MF

201

A

6 3

DDRREG_VDDQSNS_R

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm

BOM_COST_GROUP=POWER

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/21/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

74 OF 120

SHEET

57 OF 82

124578

8 7 6 5 4 3

12

D

CRITICAL CRITICAL

CASE-D2E-SM

VOUT = 5.0V

10.8A MAX OUTPUT
F = 600 KHZ

CRITICAL

1

C7553

C

330UF

20%

6.3V

2

POLY-TANT
CASE-D3L-SM

CRITICAL

C7552

330UF

POLY-TANT

CASE-D3L-SM

B

=PPVIN_S5_HS_OTHER5V_ISNS

42 68

CRITICAL

1

2

1

2

CRITICAL

C7550

X5R-CERM

C7540

POLY-TANT

CASE-D2E-SM

C7571

0.001UF

10%
50V
X7R-CERM
0402

10UF

20%
25V

0603

68UF

1

2

C7543

68UF

20%
16V

POLY-TANT

=PP5V_S3_REG

58 68

1

20%

6.3V

2

XW7522

P5VS3_VFB1_R

1

R7522

10

5%
1/16W
MF-LF
402

2

5VS3_VFB1_RR

1

R7520

41.2K

1%
1/16W
MF-LF
402

2

1

R7521

10.0K

0.5%
1/16W
MF
402

2

XW7520

1

20%
16V

2

PLACE_NEAR=C7553.1:3MM

2

SM

1

2

SM

1

CRITICAL

C7542

68UF

20%
16V

POLY-TANT

CASE-D2E-SM

1

CRITICAL

L7520

1.0UH-21A-0.006OHM

PCMB103T-1R0MS

2

P5VS3_VSW

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

PLACE_NEAR=L7520.1:3MM

PLACE_NEAR=L7520.2:3MM

2

XW7521

SM

1

P5VS3_CSP1_R

1

1

C7541

4.7UF

10%
25V

2

2

X6S-CERM
0603

NO STUFF

1

R7599

1

5%
1/10W
MF-LF
603

2

P5VS3_SNUBR

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCH_NODE=TRUE

NO STUFF

0.0033UF

DIDT=TRUE

C7599

1

C7570

0.001UF

20%
50V

2

CERM
0402

CRITICAL

CSD58872Q5D

VIN

1

VSW

6
7
8

PGND

1

10%
50V

2

CERM

402

Q7520

SON5X6

9

1

C7520

12PF

5%
25V

2

NP0-C0G
0201

TG

TGR

BG

R7556

3.01K

1/16W
MF-LF

42 68

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1

C7524

0.1UF

10%
50V

2

X7R
603-1

3

P5VS3_TG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE
DIDT=TRUE

4

5

402

C7518

0.1UF

X7R-CERM

R7547

2.49K

1 2

1

1%

2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1 2

10%
16V

0402

1%
1/16W
MF-LF

402

=PPVIN_S5_HS_OTHER3V3_ISNS

C7500

603-1

SKIP_5V3V3:INAUDIBLE

SKIP_5V3V3:AUDIBLE

1

R7544

1

5%
1/16W
MF-LF

402

2

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

1

C7537

150PF

5%

50V

2

CERM

402

1

1UF

10%
25V

2

X5R

R7500

1/20W

0201

64

64

1

R7537

10K

1%
1/16W
MF-LF
402

2

1

2

(P5VP3V3_VREF2)

58 68

R7501

1

0

5%
MF

2

IN
OUT

0

5%

1/20W

MF

0201

P5VP3V3_SKIPSEL

P5VS3_VBST

DIDT=TRUE

P5VS3_DRVH

DIDT=TRUE

P5VS3_LL

DIDT=TRUE

P5VS3_DRVL

DIDT=TRUE

P5VS3_CSP1
P5VS3_CSN1

P5VS3_VFB1
P5VS3_COMP1

P5VS3_EN
P5VS3_PGOOD

R7536

12.1K

P5VS3_COMP1_R

C7536

4700PF

10%
100V
CERM
402

GND_5V3V3_AGND

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

=PP5V_S3_REG

1

2

SWITCH_NODE=TRUE

1

1%
1/16W
MF-LF

402

2

2

23

29

VIN

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

OCSEL

31

1

32

30

DRVL1

7

CSP1

8

11

MODE

9

VFB1 VFB2

10

4
5

XW7500

PLACE_NEAR=U7501.28:1MM

CRITICAL

U7501

GND

28

SM

VREG5

QFN

TPS51980

THRM_PAD

2

1

22

VREG3

33

VBST2VBST1

DRVH2DRVH1

DRVL2

COMP2COMP1

PGOOD2PGOOD1

CSP2
CSN2CSN1

P5VP3V3_VREG3
P5VP3V3_VREF2

13

VREF2

12

EN

26

DIDT=TRUE

24

DIDT=TRUE

25

SW2SW1

EN2EN1

DIDT=TRUE

27

DIDT=TRUE

18
17

3

RF

16
15

21
20

1

C7501

0.22UF

10%
10V

2

CERM

402

P5VS5_EN

P3V3S5_VBST

SWITCH_NODE=TRUE

P3V3S5_DRVH
P3V3S5_LL
P3V3S5_DRVL
P3V3S5_CSP2

P3V3S5_CSN2
P3V3S5_RF

P3V3S5_VFB2
P3V3S5_COMP2

P3V3S5_EN
P3V3S5_PGOOD

1

R7538

12.1K

1%
1/16W
MF-LF
402

2

P3V3S5_COMP2_R

(P5VP3V3_VREF2)

1

C7503

2.2UF

20%
10V

2

X5R-CERM
402

IN

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

IN

OUT

R7539

C7538

4700PF

10%
100V
CERM

402

1

2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

64

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

64

64

1

10K

1%
1/16W
MF-LF

402

2

1

2

=PP5V_S5_LDO

VOUT = 5V
100MA MAX OUTPUT

CRITICAL

C7505

10UF

20%

6.3V
X5R
603

R7563

0

1 2

5%
1/16W
MF-LF

402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

R7506

165K

1/16W
MF-LF

1

C7539

47PF

5%
50V

2

CER
0402

P3V3S5_TG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE
GATE_NODE=TRUE

1

1%

402

2

68

C7564

0.1UF

603-1

C7588

0.1UF

1 2

10%
16V

X7R-CERM

0402

R7546

1.82K

1 2

1%
1/16W
MF-LF

402

10%
50V
X7R

C7521

NP0-C0G

1

2

1

12PF

5%

25V

2

0201

2

1

6

3 4 5

1

R7516

5.23K

1%
1/16W
MF-LF
402

2

P3V3S5_CSP2_R

C7584

68UF

POLY-TANT

CASE-D2E-SM

376S0958

CRITICAL

Q7560

FDMS3602S

POWER56

7

PHASE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCH_NODE=TRUE

1

2

DIDT=TRUE

CRITICAL

1

2

CASE-D2E-SM

C7580

POLY-TANT

20%
16V

NO STUFF

P3V3S5_SNUBR

NO STUFF

C7598

0.001UF

10%
50V
X7R-CERM
0402

68UF

20%
16V

152S0754152S0688

CRITICAL

1.0UH-22A

PCMC063T-SM

R7598

1/10W
MF-LF

CRITICAL

1

2

CASE-D2E-SM

L7560

1

10

5%

603

2

XW7560

C7582

68UF

POLY-TANT

SM

1

20%
16V

2

12

PLACE_NEAR=C7592.1:3MM

PLACE_NEAR=L7560.2:3MM

PLACE_NEAR=L7560.1:3MM

2

2

XW7561

SM

1

1

1

C7581

4.7UF

10%
25V

2

X6S-CERM
0603

=PP3V3_S5_REG

VOUT = 3.3V

10.5A MAX OUTPUT
F = 600 KHZ

C7572

0.001UF

10%
50V

X7R-CERM

0402

CRITICAL

1

C7590

10UF

20%
25V

2

X5R-CERM
0603

2

XW7562

SM

1

P3V3S5_VFB2_R

P3V3S5_VFB2_RR

R7560

R7561

1

C7583

0.001UF

20%
50V

2

CERM
0402

1

2

23.2K

0.5%
1/16W
MF-LF

0402

10.0K

0.5%
1/16W

402

CRITICAL

1

C7592

330UF

20%

6.3V

2

POLY-TANT
CASE-D3L-SM

1

2

1

MF

2

58 68

1

R7562

10

5%
1/16W
MF-LF
402

2

D

C

B

=PP5V_S3_REG

58 68

1

C7522

12PF

5%
25V

2

NP0-C0G
0201

A

6 3

=PP3V3_S5_REG

58 68

1

C7523

12PF

5%
25V

2

NP0-C0G
0201

BOM_COST_GROUP=POWER

SYNC_MASTER=J14

PAGE TITLE

5V & 3.3V Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

75 OF 120

SHEET

58 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

D

D

1.05V S0 Regulator

=PPVIN_S0_1V05S0

68

1

C7622

=PPVIN_S0_1V05S0_LDO

68

1UF

X6S-CERM

0402

10%
10V

P1V05S0_BOOT_RC

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

1

R7630

2.2

5%
1/10W
MF-LF

603

2

P1V05S0_VBST

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P1V05S0_DRVH

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

P1V05S0_LL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE
DIDT=TRUE

P1V05S0_DRVL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

P1V05S0_PGOOD

1

2

R7631

0

1 2

5%
1/16W
MF-LF

402

OUT

1

C7630

0.1UF

10%
16V

2

X7R-CERM
0402

P1V05S0_DRVH_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

64

V+

8

V+

9

LSG

7

CRITICAL

Q7630

FDPC1012S

LLP

GND

GND

GND

5

6

10

HSG

SW

P1V05S3_EN
=P1V05S0_EN

64

P1V05S0_FB
P1V05S0_MODE

P1V05S0_TRIP

PLACE_NEAR=U7600.19:3mm

BYPASS=U7600.2::1mm

C7601

X6S-CERM

1

R7614

14.7K

1%
1/20W
MF
201

2

PLACE_NEAR=U7600.18:3mm

1

10UF

20%
10V

2

0603

2

VLDOIN

12 15

V5IN

S3
S5

VREF

REFIN

MODE
TRIP

TPS51916

CRITICAL

PGND

10

U7600

GND

7

17
16

6

8

19
18

QFN

VTT

4

VBST
DRVH

DRVL

PGOOD

VDDQSNS

VTTSNS

VTTREF

THRM

PADGND

21

SW

VTT

XW7600

14
13

11
20
9

P1V05S0_VTT

3
1

5

P1V05S0_VTTREF

C7650

2

SM

1

=PP5V_S0_1V05S0

68

BYPASS=U7600.12::1mm

C

C7600

Scrub S3 & S5 pins connections!

P1V05_S0_VREF

C7615

0.1UF

X7R-CERM

BYPASS=U7600.6::1mm

0402

10%
16V

1

2

1

R7611

35.7K

1%
1/20W
MF
201

2

PLACE_NEAR=U7600.8:5mm

1

R7612

49.9K

1%
1/20W
MF
201

2

PLACE_NEAR=U7600.8:5mm

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

1

C7616

0.01UF

10%
16V

2

X7R-CERM
0402

BYPASS=U7600.8::1mm

1

10UF

20%
10V

2

X6S-CERM

0603

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

1

R7610

1K

1%
1/20W
MF
201

2

1

R7613

47.5K

1%
1/20W
MF
201

2

B

1000PF

5%

25V
CERM
0402

1

2
3
4

1

2

P1V05S0_LL_SNUB

1

2

2

PLACE_NEAR=Q7630.8:1.5mm

1.0UH-13A-7.8MOHM

NOSTUFF

R7632

2.2

5%
1/10W
MF-LF
603

DIDT=TRUE

C7619

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

L7630

1 2

SPM6530T-SM

CRITICAL

NOSTUFF

C7632

0.001UF

10%
50V

X7R-CERM

0402

1

C7624

1UF

20%
35V

2

CER-X6S
0402

PP1V05_S0_REG_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

43 80

43 80

1

2

1

C7620

12PF

5%
25V

2

NP0-C0G
0201

ISNS_1V05_S0_P

OUT

ISNS_1V05_S0_N

OUT

Short Rsense

OMIT

R7640

0.003

1%
1W
MF

0612-SHORT

1 2
3 4

PLACE_NEAR=L7630.2:1.5mm

C7623

1000PF

25V
CERM
0402

C

=PP1V05_S0_REG

20%

2.0V

Vout = 1.05V

5A MAX OUTPUT

1

F = 400 KHZ

2

PLACE_NEAR=C7648.1:1mm

XW7610

SM

CRITICAL

C7649

1

5%

2

330UF

POLY-TANT

CASE-B2-SM1

CRITICAL

1

C7648

330UF

20%

2.0V

2

POLY-TANT
CASE-B2-SM1

59 68

2

1

B

P1V05S0_AGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

A

6 3

PLACE_NEAR=U7600.21:1mm

P1V05S0_VDDQSNS

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm

R7641

10

1 2

5%

1/20W

MF

201

P1V05S0_VDDQSNS_R

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm

BOM_COST_GROUP=POWER

=PP1V05_S0_REG

59 68

SYNC_MASTER=AHARTMAN_J52

PAGE TITLE

1.05V Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

C7621

12PF

5%
25V

2

NP0-C0G
0201

SYNC_DATE=10/29/2013

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

76 OF 120

SHEET

59 OF 82

124578

8.0.0
dvt1

SIZE

A

D

8 7 6 5 4 3

12

Page Notes

Power aliases required by this page:

- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)

- =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT)

- =PP5V_S0SW_KBDLED (5V KEYBOARD BACKLIGHT INPUT)

BOM options provided by this page:

BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds
BKLT:PROD - Stuffs 0 ohm series R for production

D

=PPVIN_S0SW_LCDBKLTFET

68

C

PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW

B

740S0159

CRITICAL

F7700

3AMP-32V

1 2

0603

42 80

OUT

42 80

OUT

PART NUMBER

107S0386 CRITICAL

SENSOR ON PAGE 54 USES R7700 TO MEASURE THE

POWER GOING TO LCD BACKLIGHT

R7700

0.025

1%
1W

MTL

0612

PPVIN_S0SW_LCDBKLT_F

60

1 2
3 4

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

EDP_BKLT_PSR_EN

65

IN

SMC_SYS_KBDLED

38

IN

=PP5V_S0_BKLT

60 68

=I2C_BKLT_SCL

69

IN

=I2C_BKLT_SDA

69

BI

I2C ID DEDICATED.ONLY CONNECTS TO JERRY

OMIT_TABLE

60

1

2

QTY

RES,MTL FILM,1W,25MOHM,1%,4TERM,0612,BLK

1

DESCRIPTION

CRITICAL

Q7700

FDC638APZ_SBMS001

PPVIN_S0SW_LCDBKLT_R

C7700

1000PF

10%
16V
X7R-1
0201

1

R7701

80.6K

1%
1/16W
MF-LF
402

2

SSOT6-HF

4

3

6
5
2
1

LCDBKLT_EN_L

1

R7702

63.4K

1%
1/16W
MF-LF
402

2

1

R7740

1M

5%
1/20W
MF
201

2

=PP5V_S0_BKLT

60 68

PLACE_NEAR=U7700.5:5MM

GND_BKLT_SGND

60

BKLT_SD

R7744

1/16W
MF-LF

C7740

1UF

10%
10V
X5R
402

5%

402

BKLT_SENSE_OUT

R7742

0

GND_BKLT_SGND

60

R7747

GND_BKLT_SGND

60

1

R7752

2.4K

5%
1/20W
MF
201

2

1 2

5%

1/20W

MF

0201

0

1 2

5%

1/20W

MF

0201

1

R7753

2.4K

5%
1/20W
MF
201

2

PLACE_NEAR=U7700.16:10MM

PLACE_NEAR=U7700.15:10MM

R7751

0

1 2

5%

1/20W

MF

0201

BKLT_EN_R

NO STUFF

1

C7742

33PF

5%
25V

2

NPO-C0G
0201

BKLT_PWM_KEYB

NO STUFF

1

C7747

33PF

5%
25V

2

NPO-C0G
0201

R7750

0

1 2

5%

1/20W

MF

0201

BKLT_SCL

BKLT_SDA

REFERENCE DES

NOSTUFF

1

C7701

0.001UF

10%
50V

2

CERM
402

1

1

0

2

2

PP5V_S0_BKLT_A

60

PP5V_S0_BKLT_D

60

1

1

2

2

R7700

PPVIN_S0SW_LCDBKLT

60

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=12.9V
MAKE_BASE=TRUE

R7745

0

5%
1/16W
MF-LF
402

C7741

PLACE_NEAR=U7700.18:5MM

1UF

10%
10V
X5R
402

LP8548B1SQ_-04

11

10

19

17
12

15
16

SD

9

VSENSE_N
VSENSE_P

SENSE_OUT

EN
PWM_KEYB

SCL
SDA

5

VDDD

U7700

LLP

ISET_KEYB

(IPU)
(IPU)

CRITICAL

353S4160

GND_SW2

GNDD

GND_SW

GND_SW

7

3

232422

XW7700

SM

1 2

68

CRITICAL

PLACE_NEAR=L7710.1:5MM

18

VDDA

2

LCDBKLT_SW

60

SW

1

SW

21

LCDBKLT_FB

FB

4

LCDBKLT_FET_DRV

60

GD

20

BKLT_ISET_KEYB

13

BKLT_KEYB1

KEYB1

14

BKLT_KEYB2

KEYB2

6

SW2

8

FB2

THRM

GNDA

PAD

25

GND_BKLT_SGND

60

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

=PP5V_S0SW_KBDLED

PLACE_NEAR=L7720.1:5MM

BOM OPTION

1

C7710

4.7UF

10%
25V

2

X6S-CERM
0603

PLACE_NEAR=L7710.1:5MM

1

2

PLACEMENT_NOTE:

SANDWICH C7720 AND C7721

SANDWICH C7720 AND C7721

1

2

PLACEMENT_NOTE:

SANDWICH C7710 AND C7711

SANDWICH C7710 AND C7711

PLACE_NEAR=L7710.1:5MM

C7720

2.2UF

10%
25V
X5R-CERM
603

PLACE_NEAR=L7720.1:5MM

PLACE_NEAR=Q7701.5:3MM

152S1527

CRITICAL

22UH-20%-2.4A-0.105OHM

C7711

4.7UF

10%
25V
X6S-CERM
0603

LCDBKLT_FET_DRV_R

60

R7720

1 2

1

R7741

31.6K

1%
1/20W
MF
201

2

PLACE_NEAR=U7700.20:5MM

60

60

1

C7721

2.2UF

10%
25V

2

X5R-CERM
603

L7710

1 2

DEM8030C-SM

1

C7712

0.1UF

10%
25V

2

X5R
402

1

R7733

0

5%
1/16W
MF-LF
402

2

BKLT:ENG

PLACE_NEAR=U7700.13:10MM

10.2

0.1%

1/16W

TF

402

R7721

1 2

PPVOUT_BKLT_FB2
PP5V_S0_KBDBKLT_SW

1

C7722

0.1UF

10%
16V

2

X5R-CERM
0201

PLACE_NEAR=L7720.1:5MM

PLACE_NEAR=L7710.2:3MM

D7710

POWERDI-123

DFLS2100

PLACE_NEAR=D7710.K:2MM

PPVIN_SW_LCDBKLT_SW

60

5

CRITICAL

Q7701

1 2 3

SI7812DN

PWRPK-1212-8

4

PLACE_NEAR=U7700.1:3MM

BKLT:ENG

PLACE_NEAR=U7700.14:10MM

10.2

0.1%

1/16W

TF

402

PLACE_NEAR=U7700.6:5MM

152S1701

CRITICAL

10UH-20%-1.4A-0.17OHM

L7720

1 2

PST041H-SM

371S0704

CRITICAL

A K

XW7710

PART NUMBER

116S0004

2

SM

1

1

R7731

LCDBKLT_TB_XWR

13.3K

1%
1/16W
MF-LF
402

2

1

R7732

150K

1%
1/16W
MF-LF
402

2

XW7720

371S0572

CRITICAL

D7720

SOD-123

A K

RB160M-60G

PLACE_NEAR=L7720.2:5MM

PLACE_NEAR=D7710.K:5MM

1

C7760

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=D7710.K:5MM

1

C7765

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=D7710.K:5MM

1

C7770

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=D7710.K:5MM

1

2

PLACE_NEAR=D7710.K:5MM

1

2

PLACE_NEAR=D7710.K:5MM

1

2

QTY

RES,MTL FILM,0 OHM,1A MAX,0402,SMD

1

KBDLED_CATHODE1

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

KBDLED_CATHODE2

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

2

SM

PLACE_NEAR=D7720.K:2MM

1

1

C7723

1.0UF

10%
50V

2

X7R
0805

PLACEMENT_NOTE:

SANDWICH C7723 AND C7724

SANDWICH C7723 AND C7724

PLACE_NEAR=D7720.K:5MM

PLACE_NEAR=D7710.K:5MM

C7761

2.2UF

10%
100V
X5R
1206

PLACE_NEAR=D7710.K:5MM

C7766

2.2UF

10%
100V
X5R
1206

PLACE_NEAR=D7710.K:5MM

C7771

2.2UF

10%
100V
X5R

1206

DESCRIPTION

37 71

37 71

1

C7724

1.0UF

10%
50V

2

X7R
0805

PLACE_NEAR=D7720.K:5MM

1

C7762

2.2UF

10%
100V

2

X5R
1206

1

C7767

2.2UF

10%
100V

2

X5R
1206

1

C7772

2.2UF

10%
100V

2

X5R
1206

1

C7725

0.001UF

10%
50V

2

X7R-CERM
0402

PLACE_NEAR=D7710.K:5MM

1

C7763

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=D7710.K:5MM

1

C7768

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=D7710.K:5MM

1

C7773

2.2UF

10%
100V

2

X5R
1206

REFERENCE DES

R7720,R7721

PPVOUT_S0_KBDBKLT

1

2

PLACE_NEAR=D7720.K:9MM

PLACE_NEAR=D7720.K:5MM

PLACE_NEAR=D7710.K:5MM

1

C7764

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=D7710.K:5MM

1

C7769

2.2UF

10%
100V

2

X5R
1206

PLACE_NEAR=D7710.K:5MM

1

C7717

1000PF

10%
100V

2

X7R-CERM
0603

1

C7774

12PF

5%
100V

2

CERM
0402

1

C7775

12PF

5%
100V

2

CERM
0402

1

C7776

12PF

5%
100V

2

CERM
0402

CRITICAL

CRITICAL

C7726

1.0UF

10%
50V
X7R
0805

T-BONE C7726 AND C7727

1

C7727

1.0UF

10%
50V

2

X7R
0805

PLACE_NEAR=D7720.K:9MM

PPVOUT_S0_LCDBKLT

BOM OPTION

BKLT:PROD

1

C7777

12PF

5%
100V

2

CERM
0402

1

C7778

12PF

5%
100V

2

CERM
0402

60 65 71

D

C

B

37 60 71

PBUS LINE WIDTHS

A

PP5V_S0_BKLT_A

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V

PP5V_S0_BKLT_D

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V

60

60

PPVIN_S0SW_LCDBKLT_F

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT_R

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT_FET

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=12.9V

60

60

60

LCDBKLT_FET_DRV_R

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V

GATE_NODE=TRUE

LCDBKLT_FET_DRV

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V

GATE_NODE=TRUE

6 3

LCD BKLT LINE WIDTHS

DIDT=TRUE

DIDT=TRUE

LCDBKLT_SW

60

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=53V

SWITCH_NODE=TRUE

PPVIN_SW_LCDBKLT_SW

60

MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=53V

SWITCH_NODE=TRUE

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=53V

PPVOUT_BKLT_FB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=53V

DIDT=TRUE

DIDT=TRUE

KBD BKLT LINE WIDTHS

60

60

60 65 71

PP5V_S0_KBDBKLT_SW

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=40V

SWITCH_NODE=TRUE

PPVOUT_S0_KBDBKLT

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=40V

PPVOUT_BKLT_FB2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=40V

DIDT=TRUE

BOM_COST_GROUP=DISPLAY

60

37 60 71

60

SYNC_MASTER=SHART_J44

PAGE TITLE

LCD & KBD Backlight Driver

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=11/20/2012

8.0.0
dvt1

77 OF 120

60 OF 82

SIZE

A

D

8 7 6 5 4 3

12

1.05V SUS LDO

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).

=PP3V3_S3_P1V8S3

68

D

C7824

1000PF

X7R-1

1

10%
16V

2

0201

CRITICAL

1

C7820

2

64

IN

64

OUT

10UF

20%
10V
X5R

0603-1

1

2

=P1V8S3_EN

P1V8S3_PGOOD

CRITICAL

C7827

10UF

20%
10V
X5R
0603-1

2

3

EN

POR

SKIP

1

VIN

U7820

ISL8009B

DFN

CRITICAL

GND

THRM_PAD

7

8

6

54

P1V8S3_SW

SWITCH_NODE=TRUE
DIDT=TRUE

LX

VFB

RSI

9

C

1.8V S3 REGULATOR

152S1870

L7820

2.2UH-20%-2.0A-0.108OHM

2520-SM

1 2

P1V8S3_FB

Vout = 0.8V * (1 + Ra / Rb)

CRITICAL

<Ra>

<Rb>

R7822

10

1/16W
MF-LF

402

R7820

113K

1/20W

R7821

90.9K

1/20W

5%

201

201

PP1V8_S3_REG_R

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V

1

2

P1V8S3_FB_R

1

1%

MF

2

1

1%
MF

2

1

C7823

2

47PF

5%
25V
C0G
0201

CRITICAL

1

C7821

22UF

20%

6.3V

2

X5R-CERM-1
603

CRITICAL

C7822

X5R-CERM-1

22UF

Short Rsense

OMIT

R7829

0.002

1%
1W
MF

0612-SHORT

CRITICAL

C7825

22UF

X5R-CERM-1

1 2
3 4

1

20%

6.3V

2

603

=PP1V8_S3_REG

Vout = 1.794V
Max Current = 1.8A
Freq = 1 MHz

ISNS_1V8_S3_N
ISNS_1V8_S3_P

1

20%

6.3V
2

603

CRITICAL

C7826

22UF

X5R-CERM-1

1

20%

6.3V

2

603

1

C7800

12PF

5%
25V

2

NP0-C0G
0201

70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

CRITICAL
XDP_CONN

U7840

TPS720105

SON

4

BIAS

6

IN

3

EN

1

2

OUT

NC

THRM

PADGND

5

7

61 68

43 80

OUT

43 80

OUT

=PP1V8_S3_REG

=PP3V3_SUS_P1V05SUSLDO

68

61 68

XDP

C7840

1UF

10%

6.3V
CERM

402

1

2

NC

1

2

=PP1V05_SUS_LDO

Vout = 1.05V
Max Current = 0.35A

XDP

C7841

2.2UF

10%

6.3V
X5R
402

D

68

C

=PP3V3_S0_P1V5S0

1.5V S0 Switcher

68

CRITICAL

1

C7870

22UF

20%

6.3V

2

X5R
0603

8

6

54

152S1051

CRITICAL

L7870

2.2UH-2A-0.155-OHM

P1V5_S0_SW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE
DIDT=TRUE

1 2

2512

P1V5_S0_FB_R

C7876

10PF

P1V5_S0_FB

Vout = 0.8V * (1 + Ra / Rb)

6 3

50V
CERM
0402

B

=PP1V5_S0_REG

1

R7882

10

5%
1/16W
MF-LF
402

2

CRITICAL

1

C7873

1

R7880

1

100K

1%

5%

1/16W
MF-LF

2

402

2

<Ra>

1

R7881

113K

1%
1/16W
MF-LF
402

2

<Rb>

2

22UF

20%

6.3V
X5R
0603

Vout = 1.508V
MAX CURRENT = 0.6A
Freq = 1.6MHZ

CRITICAL

1

C7874

22UF

20%

6.3V

2

X5R
0603

1

C7801

12PF

5%
25V

2

NP0-C0G
0201

68

SIZE

A

D

BOM_COST_GROUP=POWER

SYNC_MASTER=AHARTMAN_J52

PAGE TITLE

Misc Power Supplies

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

78 OF 120

SHEET

61 OF 82

124578

2

EN

3

POR

SKIP

1

VIN

U7870

ISL8009B

DFN

CRITICAL

GND

THRM_PAD

7

LX

VFB

RSI

9

B

=P1V5S0_EN

64

IN

P1V5S0_PGOOD

64

OUT

353S2535

A

8 7 6 5 4 3

12

D

CRITICAL

Q7979

SI7121DN

=PPVIN_X239

RC Value not Final

68

C

=PP3V3_S4_X239

68

R7922

0

5%
1/16W
MF-LF
402

R7926

0

5%
1/16W
MF-LF
402

12

12

SMC_ACTUATOR_DISABLE_L

38

BI

(Open-Drain)

TPAD_ACTUATOR_THRMTRIP_L

36 71

IN

B

(Open-Drain)

C7900

10UF

20%
25V

X5R-CERM

0603

1

2

C7901

10UF

X5R-CERM

0603

20%
25V

1

2

1

2

R7976

100K

5%
1/20W
MF
201

CRITICAL

DMN32D2LFB4

DFN1006H4-3

PVIN_S4_TPAD_EN

Q7972

SYM_VER_2

1

PVIN_S4_TPAD_EN_L

3

D

G S

2

R7972

47K

1/16W
MF-LF

402

1

5%

2

0.033UF

R7970

33K

5%
1/16W
MF-LF

402

C7971

10%
16V
X5R
402

12

1

2

PVIN_S4_TPAD_SS

PWRPK-1212-8

S

1 2 3

D

5

G

4

C7970

0.01UF

X7R-CERM

0402

10%
16V

1

2

=PPBUS_X239_REG

68

D

C

B

A

BOM_COST_GROUP=TRACKPAD

6 3

SYNC_MASTER=AHARTMAN_J52

PAGE TITLE

X239 Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

79 OF 120

SHEET

62 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

1.5V S0 Audio Switch (BYPASSED)

=PP1V5_S0SW_P1V5S0SWAUDIOFET

68

D

P1V5S0SW_AUDIO_EN

64

IN

=PP3V3_S4_P3V3S4FET

68

=P3V3S4_EN

64

IN

C

=PP3V3_S3_P3V3S3FET

68 68

=P3V3S3_EN

64

IN

B

=PP3V3_S0_P3V3S0FET

68

=P3V3S0_EN

63 64

IN

3.3V Sensor Switch

=PP3V3_S4SW_P3V3S4SWSNSFET

68

A

P3V3S4SW_SNS_EN

40

IN

R8042

0

1 2

5%

1/20W

MF

A2
B2

C2

0201

U8040

TPS22924

CSP

NOSTUFF

VIN

CRITICAL

ON

GND

C1

VOUT

NOSTUFF

R8040

10K

1/20W

C8040

1

5%
MF

201

2

NOSTUFF

1.0UF

20%

6.3V
X5R

0201-1

1

2

3.3V S4 Switch

U8000

TPS22920

CSP

A2

C8000

1.0UF

6.3V

0201-1

20%
X5R

B2
C2

D2

1

2

VIN

CRITICAL

ON

GND

D1

VOUT

3.3V S3 Switch

U8010

TPS22924

CSP

C8010

1.0UF

6.3V

0201-1

20%
X5R

A2
B2

C2

1

2

VIN

CRITICAL

ON

GND

C1

VOUT

3.3V S0 Switch

U8030

TPS22924

CSP

C8030

1.0UF

6.3V

0201-1

C8050

1.0UF

6.3V

0201-1

20%
X5R

20%
X5R

A2
B2

C2

1

2

A2

B2

1

2

VIN

CRITICAL

ON

GND

C1

U8050

TPS22934

DSBGA

VIN

ON

CRITICAL

GND

B1

VOUT

VOUT

A1
B1

Part Part

Type

R(on)
@ 1.8V

Current

A1

PP3V3_S4_FET_R

VOLTAGE=3.3V

B1

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

C1

Part

Type

R(on)
@ 3.6V

Current

PP3V3_S3_FET_R

VOLTAGE=3.3V

A1

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

B1

Part

Type

R(on)
@ 2.5V

Current

Sense R on sensor page

=PP3V3_S0_FET

A1
B1

Part

Type

R(on)
@ 2.5V

Current

PP3V3_S4SW_SNS_FET_R

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm

A1

MIN_NECK_WIDTH=0.2mm

U8050

Part

Type

R(on)
@ 3.6V

Current

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

PP1V5_S0SW_AUDIO_HDA

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

EDP: 0.5A

U8040

TPS22924C

Load Switch

19.6 mOhm Typ

21.8 mOhm Max

2A Max

OMIT

R8000

0.002

1%
1W
MF

0612-SHORT

1 2
3 4

NC NC

=PP3V3_S4_FET

EDP: 2.4A

U8000

TPS22920

Load Switch

5.5 MOHM TYP

8.8 MOHM MAX

4A MAX

OMIT

R8011

0.002

1%
1W
MF

0612-SHORT

1 2
3 4

NC NC

=PP3V3_S3_FET

EDP: 1.02A

U8010

TPS22924C

Load Switch

18.5 mOhm Typ

25.8 mOhm Max

2A Max

68

EDP: 1A

U8030

TPS22924C

Load Switch

18.5 mOhm Typ

25.8 mOhm Max

2A Max

R8050

0

1 2

=PP3V3_S4SW_SNS_FET

5%

EDP: 50mA
1/16W
MF-LF

402

TPS22934

Load Switch

63 mOhm Typ
77 mOhm Max

1A Max

Loading specs per J41/43_PowerBudget_Riviera_rev0.99e

8

11 17

=PP3V3_SUS_P3V3SUSFET

68

64

IN

63 68

P3V3S0SW_SSD_FET_RAMP

64

4700PF

63 64

C8061

4700PF

10%
10V
X7R
201

IN

1

2

=P3V3S0_EN

1

10%
10V

2

X7R
201

C8071

3.3V SUS Switch

U8020

TPS22934

DSBGA

A2

VIN

6.3V

20%
X5R

B2

ON

CRITICAL

GND

1

2

=P3V3SUS_EN

C8020

1.0UF

0201-1

3.3V SSD Switch

=PP3V3_S0SW_P3V3S0SWSSDFET

68

SLG5AP1453V

7 3

CAP

P3V3S0SW_SSD_EN

IN

2 5

NOSTUFF

R8070

0

1 2

5%

1/20W

MF

0201

5V S4 Switch

=PP5V_S5_P5VS5FET

68

P5VS5_FET_RAMP

=P5VS4_EN

64

IN

7 3

CAP

2 5

A1

VOUT

B1

1

VDD

U8070

TDFN

CRITICAL

GND

8

1

VDD

U8060

SLG5AP1443V

TDFN

CRITICAL

GND

8

PP3V3_SUS_FET_R

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

U8020

Type

R(on)
@ 3.6V

Current

1

C8070

0.1UF

10%

6.3V

2

CERM-X5R
0201

D

PP3V3_S0SW_SSD_FET_R

SON

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM

U8070

Part
Type
R(on)

@ 25C
Current

1

C8060

0.1UF

10%
16V

2

X5R-CERM
0201

D

SON

OMIT

R8020

0.002

0612-SHORT

1 2
3 4

TPS22934

Load Switch

63 mOhm Typ
77 mOhm Max

1A Max

SLG5AP1453V
Load Switch

7.8 mOhm Typ

8.5 mOhm Max

5.3A Max

1%
1W
MF

=PP3V3_SUS_FET

EDP: 167mA

NCNC

68

Sense R on sensor page

=PP5V_S5_FET

EDP: 16mA

Part

Type

R(on)

Current

68

68

68

15

EDP: 5A

REMOVED THE ANALOG POWER GATE AS SLG5AP1471 SHOULD BE AVAILABLE BY THEN

CAPACITORS ADDED FOR NOISE FLOOR REASONS:

=PP3V3_S4_FET

63 68

68

U8060

SLG5AP1443V

Load Switch

17 mOhm Typ
19 mOhm Max

2.5A

5V S0 Switch

=PP5V_S0_P5VS0FET

68

1

63 68

C8081

4700PF

10%
10V
X7R
201

1

2

P5VS0_FET_RAMP

=P5VS0_EN

64

IN

1

VDD

U8080

SLG5AP1443V

TDFN

7 3

CAP

CRITICAL

2 5

GND

D

SON

8

C8080

0.1UF

10%
16V

2

X5R-CERM
0201

=PP5V_S0_FET

EDP: 1.1A

Part

Type

R(on)

Current

U8080

=PP3V3_S4SW_SNS_FET

63 68

68

SLG5AP1443V

Load Switch

17 mOhm Typ
19 mOhm Max

2.5A

6 3

1.05V PCH HSIO Switch

=PP5V_S0_HSIOFET

=PP1V05_S0_PCHHSIOFET

1

VDD

U8005

SLG5AP1471V

TDFN

PCH_HSIO_PWR_EN

IN

1

C8082

12PF

5%
25V

2

NP0-C0G
0201

1

C8085

12PF

5%
25V

2

NP0-C0G
0201

C8005

1UF

10%
10V
X5R
402

1

C8093

12PF

5%
25V

2

NP0-C0G
0201

Placement Note: Place C8090, C8091 and C8092 near U8000

1

C8083

12PF

5%
25V

2

NP0-C0G
0201

1

C8086

12PF

5%
25V

2

NP0-C0G
0201

BOM_COST_GROUP=POWER

9 5

ON S

CRITICAL

1

2

1

C8094

12PF

5%
25V

2

NP0-C0G
0201

NC

1

C8090

0.0022UF

10%
50V

2

CERM-X7R
0603

NC

1

C8084

12PF

5%
25V

2

NP0-C0G
0201

GND

8

1

2

SYNC_MASTER=J41

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

D

3

D

=PP1V05_S0SW_PCH_HSIO_FET

7

S

EDP: 1.84A

U8005

Part
Type
R(on)

@ 4V Vgs
Current

C8095

12PF

5% 5%
25V
NP0-C0G
0201

1

C8096

12PF

25V

2

NP0-C0G
0201

NC NC

1

C8091

0.0022UF

10%
50V

2

CERM-X7R
0603

NC

NC

1

C8092

0.0022UF

10%
50V

2

CERM-X7R
0603

Power FETs

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

SLG5AP1417V
Load Switch

9.8 mOhm Typ
TBD mOhm Max

6A Max

DRAWING NUMBER

051-1573

REVISION

BRANCH

PAGE

SHEET

124578

68

SYNC_DATE=10/23/2012

8.0.0
dvt1

80 OF 120

63 OF 82

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

C

B

A

5V Divider:

3.19V @ 4.5Vmin

1.5V Divider:

0.718V @ 1.45Vmin

1.05V Divider:

0.723V @ 1.02Vmin

P5VS5_EN

58

OUT

SMC_PM_G2_EN

38 39

IN

MAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

64 68

PLACE_NEAR=U7501.20:7mm

P3V3S5_PGOOD

58

SSD_PWR_EN

IN

MAKE_BASE=TRUE

=PP5V_S0_VMON

1

R8151

54.9K

1%
1/20W
MF
201

2

5.0V Divider: 1.07V

1

R8152

15K

1%
1/20W
MF
201

2

=PP3V3_S0_VMON

1

R8158

15K

1%
1/20W
MF
201

2

VMON_3V3_DIV

3.3V Divider: 1.07V

1

R8159

7.15K

1%
1/20W
MF
201

2

Thresholds:
VDD: 2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V

=PP1V5_S0_VMON

64 68

=PP5V_S0_VMON

64 68

S5 Enables

PLACE_NEAR=U7501.21:7mm

S5 Power Good

R8141

100K

5%

1/20W

MF

201

SSD Enable

64 68

VMON_5V_DIV

C8159

1UF

10%
10V
X5R
402

64 68

=PP1V5_S0_VMON

64 68

=PP1V05_S0_VMON

68

S0PGOOD_ISL

1

R8160

6.04K

1%
1/20W
MF
201

2

S0PGOOD_ISL

1

R8161

15K

1%
1/20W
MF
201

2

R8140

100

1 2

5%

1/20W

MF

201

1

S5_PWRGD-->SMC

SMC-->PM_DSW_PWRGD

2

S5_PWRGD

MAKE_BASE=TRUE

P3V3S0SW_SSD_EN

R8153

1K

1 2

5%

1

2

1/20W

9ms RC delay

R8154

1 2

1/20W

201

1K

201

MF

5%
MF

S0 Rail PGOOD Circuitry

(ISL version used for development)

S0PGOOD_ISL

1

R8170

15K

1%
1/20W
MF
201

2

S0PGOOD_ISL

1

R8171

15K

1%
1/20W
MF
201

2

S5_PWR_EN

MAKE_BASE=TRUE

NOSTUFF

1

C8142

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACE_NEAR=U7501.21:7mm

P3V3S5_EN

38

OUT

63 15 32

OUT

S0 Rail PGOOD (BJT Version)

=PP3V3_S5_VMON

68

VMON_Q2_BASE

VMON_Q3_BASE

R8155

1K

1 2

VMON_Q4_BASE

5%

1/20W

MF

201

64 68

S0PGOOD_ISL

1

R8172

6.04K

1%
1/20W
MF
201

2

P5V_DIV_VMON
P1V5_DIV_VMON
P1V05_DIV_VMON

S0PGOOD_ISL

1

R8173

15K

1%
1/20W
MF
201

2

1

R8156

150K

1%

1/20W

MF

201

2

S0PGD_C

5

8

NC

7

2

NC

1

Vbe 0.7V max @ 2mA
Vce(sat) 0.1V max @ 1mA
Q1 Vth 0.7~1V @Id 250uA

=PP3V3_S0_VMON

ISL88042IRTEZ

3

V2MON

5

V3MON

6

GND

58

OUT

6

Q2

Q3

Q4

3

S0PGD_BJT_GND_R

R8157

S0PGOOD_ISL

C8160

CERM-X5R

2

7

VDD

S0PGOOD_ISL

U8160

TDFN

(IPU)

MR*

CRITICAL

RST*V4MON

THRM_PAD

4

9

=PP3V3_S5_PWRCTL

64 68

BYPASS=U8170.6::2.3mm

PM_SLP_S5_L

13 38

IN

SMC_S4_WAKESRC_EN

38 39

IN

PM_SLP_S4_L

13 18 31 37 38 64 66

5V needs to be held up

so 1.05V can fall after 1.5V

P5VS3_EN_D

ALL_SYS_PWRGD

4

CRITICAL

Q8150

Q1

ASMCC0179

DFN2015H4-8

376S0854

MIN_NECK_WIDTH=0.116 mm
MIN_LINE_WIDTH=0.116 mm

1

MAX_LINE_WIDTH=0.116 mm

100

5%

1/20W

MF

201

2

0.1UF

10%

6.3V
0201

353S2310

1

NC

8

ALL_SYS_PWRGD_R

61

IN

IN

58

1

2

IN

59

IN

57

IN

13 18 31 37 38 64 66

NOSTUFF

C8170

0.1UF

10%

6.3V

CERM-X5R

0201

1

2

2

1

NC

Standby Enables

NOSTUFF

U8170

6

74LVC1G32

SOT891

S4_PWR_EN

4

18

3

MAKE_BASE=TRUE

R8115

1 2

5%

1/20W

MF

0201

NC

5

1

=TBTBPWRSW_EN
=TBTAPWRSW_EN
=P3V3S4_EN

0

29

OUT

28

OUT

63

OUT

USB_PWR_EN

MAKE_BASE=TRUE

NO STUFF

1

C8114

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACE_NEAR=U4600.4:6mm

R8117

100

5%
1/20W
MF
201

2

PLACE_NEAR=U4600.4:6mm

=USB_PWR_EN

5V S3 Enables

R8179

0

1 2

5%

1/20W

MF

0201

16 17 38 64

P1V8S3_PGOOD

P1V5S0_PGOOD

P5VS3_PGOOD

P1V05S0_PGOOD

DDRREG_PGOOD

S0PGOOD_ISL

P5VS3_EN_RC

PLACE_NEAR=U7501.4:15mm

NO STUFF

A

D8175

SM-201

RB521ZS-30

K

NO STUFF

R8176

240

1 2

5%

1/20W

MF

201

PLACE_NEAR=U7501.4:15mm

PM_SLP_S3_L

13 17 18 38 66 71

IN

1.5V Codec Enable(BYPASSED NOW)

13

R8162

330

1 2

5%

1/20W

MF

201

AUD_PWR_EN

IN

NOSTUFF

D8146

SM-201

RB521ZS-30

PLACE_NEAR=U8040.C2:7mm

PM_SLP_S3_BUF_L

48 64

R8166

1 2

R8169

100

1 2

5%

1/20W

MF

201

R8165

1 2

R8168

1 2

ALL_SYS_PWRGD

100

5%

1/20W

MF

201

100

5%

1/20W

MF

201

100

5%

1/20W

MF

201

1

R8175

0

5%
1/20W
MF
0201

2

PLACE_NEAR=U7501.4:15mm

P5VS3_EN

NO STUFF

1

C8175

2.2UF

10%

6.3V

2

X5R
402

PLACE_NEAR=U7501.4:15mm

R8178

100

1 2

1/20W

201

PLACE_NEAR=U8040.C2:7mm

R8145

1 2

AK

P1V5CODEC_EN_D

R8164

100

1 2

5%

1/20W

MF

201

5%
MF

NOSTUFF

100K

1%

1/20W

MF

201

1

R8167

10K

5%
1/20W
MF
201

2

OUT

PM_SLP_S3_R_L

R8146

1 2

16 17 38 64

OUT

=PP3V3_S5_PWRCTL

64 68

P1V5S0SW_AUDIO_EN

NOSTUFF

1K

1%

1/20W

MF

201

PLACE_NEAR=U8060.2:6mm

1

R8191

330

5%
1/20W
MF
201

2

P5VS4_EN_D

58

NOSTUFF

1

C8146

0.1UF

10%
25V

2

X5R
402

PLACE_NEAR=U8040.C2:7mm

D8191

SM-201

A K

RB521ZS-30

PLACE_NEAR=U8060.2:6mm

5

MC74VHC1G08

1

2

64 68

SC70-HF

4

U8180

3

63

OUT

=PP3V3_SUS_PWRCTL

SUS_PGOOD_CT

NO STUFF

1

C8131

1000PF

10%
16V

2

X7R-1
0201

1

R8192

120K

1%
1/20W
MF
201

2

PLACE_NEAR=U8060.2:6mm

P5VS4_EN

MAKE_BASE=TRUE

1

C8192

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACE_NEAR=U8060.2:6mm

BYPASS=U8180.6::3mm

1

C8180

0.1UF

10%

6.3V

2

CERM-X5R
0201

PM_SLP_S3_BUF_L

48 64

NOSTUFF

1

R8180

330K

2

5%
1/20W
MF
201

MAKE_BASE=TRUE

P1V05_EN_D

3.3V SUS Detect

=PP3V3_S5_PWRCTL

64 68

No stuff C8131, 12ms
Min delay time

U8130 Sense input
threhold is 3.07V

CRITICAL

3

PM_SLP_SUS_L

13

IN

MAKE_BASE=TRUE

=P5VS4_EN

NO STUFF

A

D8185

SM-201

RB521ZS-30

PLACE_NEAR=U7600.16:6mm

K

NO STUFF

R8138

1 2

1/20W

PLACE_NEAR=U7600.16:6mm

1

VDD

SENSE

U8130

TPS3808G33

QFN

CT

GND

5

SUS Enables

PLACE_NEAR=U7600.16:6mm

820

5%
MF

201

BYPASS=U8130.6::2.3mm

C8130

CERM-X5R

RESET*

MR*

THRM

PAD

7

1

R8190

0

5%
1/20W
MF
0201

2

P3V3SUS_EN

MAKE_BASE=TRUE

NO STUFF

1

C8190

0.1UF

10%
25V

2

X5R
402

63

OUT

1

1

R8185

R8184

0

330

5%
1/20W
MF
0201

2

2

PLACE_NEAR=U8030.C2:6mm

P3V3S0_EN_D

NO STUFF

1

C8185

0.22UF

10%
10V

2

CERM
402

PLACE_NEAR=U7600.16:6mm

1

0.1UF

10%

6.3V
2

0201

62

PM_RSMRST_L

4

TP_SUS_PGOOD_MR_L

5%
1/20W
MF
201

6 3

PM_SLP_S4_L

IN

35

OUT

State

Run (S0)

Sleep (S3AC)

Sleep (S3)

Deep Sleep (S4AC)

Deep Sleep (S4)

Deep Sleep (S5AC)

Deep Sleep (S5)

Battery Off (G3HotAC)

Battery Off (G3Hot)

S0 Enables

D8184

SM-201

AK

RB521ZS-30

PLACE_NEAR=U8030.C2:6mm

P1V05S0_EN

MAKE_BASE=TRUE

=PP3V3_SUS_PWRCTL

1

R8133

100K

5%
1/20W
MF
201

2

13 75

OUT

69

DCINVSENSE_EN

=P3V3SUS_EN

BOM_COST_GROUP=CPU SUPPORT

1

R8111

20K

5%
1/20W
MF
201

2

PLACE_NEAR=U7400.16:6mm

PLACE_NEAR=U7400.16:6mm PLACE_NEAR=U8010.C2:6mm

1

2

1

R8186

39K

5%
1/20W
MF
201

2

PLACE_NEAR=U8030.C2:6mm

P3V3S0_EN

MAKE_BASE=TRUE

1

C8186

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=U8030.C2:6mm

OUT

OUT

C8111

0.1UF

20%
10V
CERM
402

SMC_ADAPTER_EN

toggle 3Hz

1

2

P5VS0_EN_D

PLACE_NEAR=U8080.2:6mm

42

63

1

R8110

0

5%
1/20W
MF
0201

2

PLACE_NEAR=U7820.2:6mm

NO STUFF

1

C8110

0.47UF

10%

6.3V

2

CERM-X5R
402

Mobile System Power State Table

X

0

1

0

1

0

1

R8189

330

5%
1/20W
MF
201

PLACE_NEAR=U8080.2:6mm

D8189

RB521ZS-30

64 68

S3 Enables

1

R8112

0

5%
1/20W
MF
0201

2

PLACE_NEAR=U8010.C2:6mm

MAKE_BASE=TRUE

NO STUFF

1

C8112

0.47UF

10%

6.3V

2

CERM-X5R
402

SMC_PM_G2_ENABLE

1

11 1

1

1

1

1

1

0

0

1

R8187

47K

5%
1/20W
MF
201

2

SM-201

PLACE_NEAR=U8080.2:6mm

AK

P5VS0_EN

MAKE_BASE=TRUE

1

C8187

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=U8080.2:6mm

SYNC_MASTER=AHARTMAN_J52

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

MAKE_BASE=TRUE

P3V3S3_EN
P1V8S3_EN

DDRREG_EN

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

1

1

1

1

0

0

0

1

R8183

330

5%
1/20W
MF
201

2

PLACE_NEAR=U7870.2:6mm

P1V5S0_EN_D

=P3V3S3_EN
=P1V8S3_EN

=DDRREG_EN

PM_SUS_EN

1 1

1

1

0

0

0

0

0

0

D8183

SM-201

RB521ZS-30

PLACE_NEAR=U7870.2:6mm

AK

1

1

0

0

0

0

0

1

R8188

68K

5%
1/20W
MF
201

2

PLACE_NEAR=U7870.2:6mm

P1V5S0_EN

MAKE_BASE=TRUE

1

C8188

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=U7870.2:6mm

CHGR VFRQ Generation

=PP3V42_G3H_PWRCTL

64 68

VFRQ Low: Fix Frequency

VFRQ High: Variable Frequency

DMN32D2LFB4

DFN1006H4-3

PM_SLP_S3_R_L

64

Q8131

SYM_VER_2

R8131

330K

1/20W

1

G S

201

1

5%
MF

2

D

Power Control

Apple Inc.

R

63

OUT

61

OUT

57

OUT

PM_SLP_S4_LPM_SLP_S5_L

1

1

1

00

0

0

0

0

=TBT_S0_EN

=P1V5S0_EN
=P5VS0_EN
=P3V3S0_EN

=P1V05S0_EN

CHGR_VFRQ

3

2

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

PM_SLP_S3_L

1

0

0

0

0

0

0

00

00

28 29

OUT

61

OUT

63

OUT

63

OUT

59

OUT

54

OUT

SYNC_DATE=11/06/2013

051-1573

8.0.0

dvt1

81 OF 120

64 OF 82

SIZE

D

C

B

A

D

D

C

65 71

B

A

EDP_PANEL_PWR_OR_PSR_EN

65 71

1

R8322

4.32K

1%
1/20W
MF
201

2

PLACE_NEAR=D8322.K:2mm

EDP_PANEL_PWR_OR_PSR_EN_D1

EDP_PANEL_PWR_OR_PSR_EN

1

R8323

3.01K

1%
1/20W
MF
201

2

PLACE_NEAR=D8323.A:2mm

EDP_PANEL_PWR_OR_PSR_EN_D2

PANEL COMPATIBILITY

PART NUMBER

8 7 6 5 4 3

LCD PANEL INTERFACE (eDP)

LCD_HPD_CONN IS A 2.5V SIGNAL
NEEDS TO BE LEVEL SHIFTED TO 3.3V

PANEL:OLD

U8340

74AUP1T97

SOT891

Y = B

PANEL:OLD

1

C8340

0.1UF

10%
16V

2

X5R-CERM
0201

BYPASS=U8340.5::3MM

PANEL:NEW

R8341

PP3V3_S0_EDP_SW

15 41 65

OMIT_TABLE

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

0201
10% 16V
X5R-CERM

0201
10%

16V

X5R-CERM

16V
10%
X5R-CERM

16V
10%
X5R-CERM

16V
10%
X5R-CERM

16V
10%
X5R-CERM

16V
10%
X5R-CERM

16V
10%
X5R-CERM

16V
10%
X5R-CERM

16V
10%
X5R-CERM

0201

0201

0201

0201

0201

0201

0201

0201

5

4

Y A

2

1 2

VCC

3

1

B

6

C

GND

0

5%

1/20W

R8342

10K

1 2

5%

1/20W

MF

201

BYPASS=J8300.5::5MM

DP_INT_ML_F_P<0>

77

DP_INT_ML_F_N<0>

77

DP_INT_ML_F_P<1>

77

DP_INT_ML_F_N<1>

77

DP_INT_ML_F_P<2>

77

DP_INT_ML_F_N<2>

77

DP_INT_ML_F_P<3>

77

DP_INT_ML_F_N<3>

77

OMIT

R8320

0

Short Rsense

0

1 W

MF

0612-SHORT

1 2
3 4

ISNS_LCDPANEL_N
ISNS_LCDPANEL_P

DP_INT_ML_P<0>

65 71 77

DP_INT_ML_N<0>

65 71 77

DP_INT_ML_P<1>

65 71 77

DP_INT_ML_N<1>

65 71 77

DP_INT_ML_P<2>

65 71 77

DP_INT_ML_N<2>

65 71 77

DP_INT_ML_P<3>

65 71 77

DP_INT_ML_N<3>

65 71 77

MF

0201

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

1

C8304

0.1UF

10%

6.3V

2

CERM-X5R
0201

3.25-OHM-0.1A-2.4GHZ

TAM0605-4SM

SYM_VER-2

1

2 3

3.25-OHM-0.1A-2.4GHZ

TAM0605-4SM

SYM_VER-2

1

2 3

3.25-OHM-0.1A-2.4GHZ

TAM0605-4SM

SYM_VER-2

1

2 3

3.25-OHM-0.1A-2.4GHZ

TAM0605-4SM

SYM_VER-2

1

2 3

PP5VR3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

EDP_LS_CAP

1

C8350

12PF

5%
NP0-C0G

2

0201
25V

4

4

4

4

C8301

0.1UF

X5R-CERM

44 80

OUT

44 80

OUT

R8311

1M

1 2

5%

1/20W

MF

201

R8313

1 2

1/20W

201

R8315

1 2

R8317

1 2

1/20W

201

EDP_LS_CAP

1

C8351

12PF

5%
NP0-C0G

2

0201
25V

GND_VOID=TRUE

65 71 77

FL8300

65 71 77

GND_VOID=TRUE

65 71 77

FL8301

65 71 77

GND_VOID=TRUE

65 71 77

FL8302

65 71 77

GND_VOID=TRUE

65 71 77

FL8303

65 71 77

CRITICAL

FERR-220-OHM

1 2

1

10%
16V

2

0201

NOSTUFF

NO_XNET_CONNECTION=TRUE

R8312

1M

1 2

5%

1/20W

MF

1M

1/20W

1M

201

NOSTUFF

5%

NO_XNET_CONNECTION=TRUE

MF

R8314

1M

1 2

5%

1/20W

MF

1M

201

201

NOSTUFF

5%

NO_XNET_CONNECTION=TRUE

MF

R8316

1M

1 2

5%

1/20W

MF

201

NOSTUFF

5%
MF

TRUE

R8318

1M

1 2

5%

1/20W

MF

201

13

15

13

PANEL USES EDP_PANEL_PWR_PSR_EN TO DISCHARGE THE LCD BEFORE POWER GOES AWAY

EDP_BKLT_EN

LCD_PSR_EN

EDP_PANEL_PWR

3.3V TCON Switch

=PP3V3_S0_EDP

R8321

1 2

=PP5V_S0_LCD

68

R8319

1 2

1/20W

68

24.9K

1%

1/20W

MF

201

D8322

RB521ZS-30

PLACE_NEAR=U8310.B1:6mm

11K

1%
MF

201

D8323

SM-201

A K

RB521ZS-30

PLACE_NEAR=U8300.2:6mm

EDP_TCON_PWR_EN_RC

SM-201

AK

1

2

PP5V_S0_LCD_FETCAP

EDP_PANEL_PWR_EN_RC

C8310

4700PF

1

C8319

1UF

10%

6.3V

2

CERM
402

C8308

1.0UF

6.3V

0201-1

C8318

1UF

10%

6.3V
CERM
402

1

10%
10V

2

X7R
201

20%
X5R

U8310

TPS22904

A1

VIN

CRITICAL

B1

ON

1

2

U8300

SLG5AP1443V

7 3

CAP

CRITICAL

2 5

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=5V

U8300

Part

Type

R(on)

Current

LCD Panel AUX strapping

S0 Enables

DESCRIPTION

RES,MF,1/20W,10K OHM,5,0201,SMD

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

117S0201

QTY

1
1

R8330
R8331

CSP

VOUT

GND

B2

1

VDD

TDFN

GND

8

SLG5AP1443V

Load Switch

17 mOhm Typ
19 mOhm Max

2.5A

12 13 15 18 26 68

0

1 2

0

1 2

PP3V3_S0_EDP_SW

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

A2

Part

Type

R(on)
@ 2.5V

Current

C8309

0.1UF

10%
16V

X7R-CERM

0402

D

SON

REFERENCE DES

R8342
R8342

U8330

SOT833

1
2

74LVC2G32GT

5
6

NO STUFF

1/20W

NO STUFF

5%

1/20W

U8310

1

2

=PP3V3_S0_LCD

68

DP_INT_AUX_N

65 71 77

DP_INT_AUX_P

65 71 77

CRITICAL

VCC

A

Y

B

A

Y

B

GND

4 8

MF5%

MF

TPS22904

Load Switch

75 mOhm Typ
95 mOhm Max

0.5A Max

1

C8311

0.1UF

10%
16V

2

X7R-CERM
0402

CRITICAL117S0007
CRITICAL

BYPASS=U8330.8::3MM

NOSTUFF

EDP_BKLT_PSR_EN

7

3

EDP_PANEL_PWR_OR_PSR_EN

0201

0201

15 41 65

EDP: 1.02A

EDP: 1 A

NOSTUFF

NO_XNET_CONNECTION=TRUE

1

R8303

1M

5%
1/20W
MF
201

2

NOSTUFF

NO_XNET_CONNECTION=TRUE

1

R8302

1M

5%
1/20W
MF
201

2

BOM OPTION

PANEL:OLD
PANEL:NEW

C8330

0.1UF

6.3V

CERM-X5R

0201

R8310

100K

1/16W
MF-LF

402

1

C8312

10UF

20%

6.3V

2

X5R
603

=PP3V3_S0_PCH_GPIO

1

10%

2

1

R8309

5%

2

13

OUT

LCD_IRQ_L

15 71

5

77

BI

5

77

BI

5

77

IN

5

77

IN

5

77

IN

5

77

IN

5

77

IN

5

77

IN

5

77

IN

5

77

IN

60

65 71

1

100K

5%
1/16W
MF-LF

402

2

DP_INT_HPD

DP_INT_AUXCH_C_P

DP_INT_AUXCH_C_N

DP_INT_ML_C_P<0>

DP_INT_ML_C_N<0>

DP_INT_ML_C_P<1>

DP_INT_ML_C_N<1>

DP_INT_ML_C_P<2>

DP_INT_ML_C_N<2>

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<3>

1

R8340

100K

5%
1/16W
MF-LF

402

2

C8328
C8329

GND_VOID=TRUE

C8320

GND_VOID=TRUE

C8321

GND_VOID=TRUE

C8322

GND_VOID=TRUE

C8323

GND_VOID=TRUE

C8324

GND_VOID=TRUE

C8325

GND_VOID=TRUE

C8326

GND_VOID=TRUE

C8327

PP5VR3V3_SW_LCD_ISNS

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

6 3

EDP_LS_CAP

1

C8352

12PF

5%
NP0-C0G

2

0201
25V

PPVOUT_S0_LCDBKLT

60 71

I2C_BKLT_SCL

69 71

I2C_BKLT_SDA

69 71

PP3V3_S0_EDP_R

=I2C_TCON_SCL

41 71

=I2C_TCON_SDA

41 71

EDP_BKLT_PWM

13 71

LCD_HPD_CONN

71

DP_INT_AUX_P

65 71 77

DP_INT_AUX_N

65 71 77

DP_INT_ML_P<0>

DP_INT_ML_N<0>

DP_INT_ML_P<1>

DP_INT_ML_N<1>

DP_INT_ML_P<2>

DP_INT_ML_N<2>

DP_INT_ML_P<3>

DP_INT_ML_N<3>

L8300

0805

1

C8302

0.1UF

10%
16V

2

X5R-CERM

0201

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

1

2

EDP_LS_CAP

1

C8354

2

C8303

1000PF

10%

100V

X7R-CERM

0603

12PF

5%
NP0-C0G
0201
25V

1

2

EDP_LS_CAP

1

C8353

12PF

5%
NP0-C0G

2

0201
25V

PP5VR3V3_SW_LCD

65 71

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

C8305

12PF

5%
100V
CERM
0402

PLACE_NEAR=J8300.1:5mm

BOM_COST_GROUP=DISPLAY

EDP_LS_CAP

1

C8355

12PF

5%
NP0-C0G

2

0201
25V

EDP_LS_CAP

1

C8356

12PF

5%
NP0-C0G

2

0201
25V

EDP_LS_CAP

1

C8357

12PF

5%
NP0-C0G

2

0201
25V

CRITICAL

J8300

20525-130E-01

F-RT-SM

31

1

10
11
12
13
14

TRUE

15

TRUE

16
17

TRUE

18

TRUE

19
20

TRUE

21

TRUE

22
23

TRUE

24

TRUE

25
26
27
28
29
30

33
34
35
36
37
38
39
40
41

32

518S0829

1

C8306

12PF

5%
NP0-C0G

2

0201
25V

PLACE_NEAR=J8300.28:5mm

2
3
4
5
6
7
8
9

NC

1

C8300

1000PF

10%

100V

2

X7R-CERM

0603

PP5VR3V3_SW_LCD

65 71

SYNC_MASTER=GKOO_J52

PAGE TITLE

eDP Display Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

EDP_LS_CAP

1

C8358

12PF 12PF

5%
NP0-C0G

2

0201
25V

1

C8307

12PF

5%
NP0-C0G

2

0201
25V

PLACE_NEAR=J8300.29:5mm

12

EDP_LS_CAP

1

C8359

5%
NP0-C0G

2

0201
25V

1

C8313

12PF

5%
NP0-C0G

2

0201
25V

PLACE_NEAR=J8300.30:5mm

SYNC_DATE=05/04/2014

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

83 OF 120

SHEET

65 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

PLACE_NEAR=J9510.2:2.54MM

PCIE_AP_R2D_P

66 71 81

OUT

C9533

0.1UF

GND_VOID=True

1 2

10% 16V

PCIE_AP_R2D_C_P

X5R-CERM

0201

IN

14 71 81

PLACE_NEAR=J9510.4:2.54MM

PCIE_AP_R2D_N

66 71 81

D

OUT

PCIE_AP_D2R_P

14 66 71 81

14 66 71 81

IN

PCIE_AP_D2R_N

14 66 71 81

14 66 71 81

IN

PCIE_CLK100M_AP_CONN_P

66 81

OUT

PCIE_CLK100M_AP_CONN_N

66 81

OUT

3.25-OHM-0.1A-2.4GHZ

1

2 3

CRITICAL

L9501

TAM0605-4SM

SYM_VER-1

C9532

GND_VOID=True

PLACE_NEAR=J9510.1:2.54MM

C

66

66

66

66

66

66

B

66

66

66

66

14 71 74

14 71 74

66 67

14 71 74

14 71 74

14 74

14 74

14 66 71 81

14 66 71 81

66

66

=HDMI_CLK_C_LS_N

OUT

=HDMI_CLK_C_LS_P

OUT

=HDMI_DATA_C_N<0>

OUT

=HDMI_DATA_C_P<0>

OUT

=HDMI_DATA_C_N<1>

OUT

=HDMI_DATA_C_P<1>

OUT

=HDMI_DATA_C_N<2>

OUT

=HDMI_DATA_C_P<2>

OUT

=USB_BT_P

BI

=USB_BT_N

BI

USB3_EXTB_R2D_C_P

OUT

USB3_EXTB_R2D_C_N

OUT

(USB3_EXTB_R2D caps on RIO)

HDMI_HPD

IN

USB3_EXTB_D2R_P

IN

USB3_EXTB_D2R_N

IN

USB_EXTB_N

BI

USB_EXTB_P

BI

PCIE_AP_D2R_N

IN

PCIE_AP_D2R_P

IN

=PCIE_CLK100M_AP_P

OUT

=PCIE_CLK100M_AP_N

OUT

A

RIO FLEX CONNECTOR

J9510

DF40BG-70DP-0.4V

M-ST-SM

516S1059

CRITICAL

73 74

69
67 68
65 66

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

63 64
61 62
59
57 58
55 56
53 54
51 52
49
47 48
45 46
43 44
41 42
39
37 38
35 36
33 34
31 32
29
27 28
25 26
23 24
21 22
19
17 18
15 16
13 14
11 12

9
7
5
3
1

71

70

60

50

40

30

20

10

8
6
4
2

72

PM_SLP_S3_L
PM_SLP_S4_L
USB_EXTB_OC_L
AP_RESET_L
SD_RESET_L

I2C_HDMIRDRV_SCL_CONN
I2C_HDMIRDRV_SDA_CONN
PM_WLAN_EN
HDMI_DDC_LS_CLK
HDMI_DDC_LS_DATA

=PP1V5_S0_CONN

I2C_X29THMSNS_SCL_CONN
I2C_X29THMSNS_SDA_CONN
WIFI_EVENT_L
SD_PWR_EN
SDCONN_STATE_CHANGE_SAK_L

=PCIE_WAKE_L
AP_CLKREQ_L

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

NOTE: This connector is shielded 70P Hirose Plug APN 516S1059, mates with APN 516S1058.

1 2

0.1UF

4

10% 16V

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

USB3_SD_D2R_N
USB3_SD_D2R_P

USB3_SD_R2D_C_N
USB3_SD_R2D_C_P

PCIE_AP_R2D_N
PCIE_AP_R2D_P

PCIE_AP_R2D_C_N

X5R-CERM

0201

OUT
OUT

OUT
OUT

IN
OUT
OUT

66

66

OUT

66

66

66

66

66

OUT
OUT

66

IN

IN

66

66

66

66

OUT
OUT

IN

IN

=PP1V5_S0_CONN

1

C9504

12PF

5%
25V

2

NP0-C0G
0201

13 17 18 38 64 71

13 18 31 37 38 64

16

15

15

40

38

15

66

12

66 71 81

66 71 81

12 71 81

12 71 81

IN

14 71 81

=PP3V3_S4_RIO

66 68

PLACE_NEAR=J9500:2.5MM

=PP5V_S3_RIO

66 68

66

PLACE_NEAR=J9500:2.5MM

=PP3V3_S4_RIO

66 68

=PP5V_S3_RIO

66 68

1

C9500

12PF

5%
25V

2

NP0-C0G
0201

1

C9502

12PF

5%
25V

2

NP0-C0G
0201

1

2

1

C9501

12PF

5%
25V

2

NP0-C0G
0201

PLACE_NEAR=J9500:2.5MM

1

C9503

12PF

5%
25V

2

NP0-C0G
0201

PLACE_NEAR=J9500:2.5MM

PLACE_NEAR=J9500.2:2.5MM

C9591

0.1UF

10%
16V
X5R-CERM
0201

66 67

MAKE BASE

TRUE

66

66

66

66

66

66

66

66

66

66

66

66

66 31 75

=HDMI_DATA_C_P<2>

OUT

=HDMI_DATA_C_N<2>

OUT

=HDMI_DATA_C_P<1>

OUT

=HDMI_DATA_C_N<1>

OUT

=HDMI_DATA_C_P<0>

OUT

=HDMI_DATA_C_N<0>

OUT

=HDMI_CLK_C_LS_P

OUT

=HDMI_CLK_C_LS_N

OUT

=USB_BT_P

BI

=USB_BT_N

BI

=PCIE_CLK100M_AP_P

OUT

=PCIE_CLK100M_AP_N

OUT

I2C_HDMIRDRV_SCL_CONN

66

I2C_HDMIRDRV_SDA_CONN

66

HDMI_DDC_LS_CLK

66

HDMI_DDC_LS_DATA

66

I2C_X29THMSNS_SCL_CONN

66

I2C_X29THMSNS_SDA_CONN

66

SDCONN_STATE_CHANGE_SAK_L

66

USB3_SD_D2R_N

66

USB3_SD_D2R_P

66

USB3_SD_R2D_C_N

66

USB3_SD_R2D_C_P

=PCIE_WAKE_L

IN

HDMI_IG_DATA_C_P<2>

TRUE

HDMI_IG_DATA_C_N<2>

TRUE

HDMI_IG_DATA_C_P<1>

TRUE

HDMI_IG_DATA_C_N<1>

TRUE

HDMI_IG_DATA_C_P<0>

TRUE

HDMI_IG_DATA_C_N<0>

TRUE

HDMI_IG_CLK_C_P

TRUE

HDMI_IG_CLK_C_N

TRUE

USB_BT_CONN_P

TRUE

USB_BT_CONN_N

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

PCIE_CLK100M_AP_CONN_N
=I2C_HDMIRDRV_SCL

=I2C_HDMIRDRV_SDA

TRUE

HDMI_IG_DDC_CLK

TRUE

HDMI_IG_DDC_DATA
=I2C_X29THMSNS_SCL

=I2C_X29THMSNS_SDA

TRUE

SDCONN_STATE_CHANGE_RIO

TRUE

USB3RPCIE_SD_D2R_P

TRUE

USB3RPCIE_SD_D2R_N

TRUE

USB3RPCIE_SD_R2D_C_P

TRUE

USB3RPCIE_SD_R2D_C_N

TRUE

AP_PCIE_WAKE_L

1

C9592

0.1UF

10%
16V

2

X5R-CERM
0201

PLACE_NEAR=J9500.1:2.5MM

HDMI_HPD

IN

=PP1V5_S0_CONN

66

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

BP9500
BP9501
BP9502
BP9503
BP9504
BP9505
BP9506
BP9507

67 71 77

IN

67 71 77

IN

67 71 77

IN

67 71 77

IN

67 71 77

IN

67 71 77

IN

67 71 77

IN

67 71 77

IN

31 74

BI

31 74

BI

66 81

IN

66 81

IN

41

IN

MAKE BASE FOR I2C IS ON I2C PAGE

41

BI

67

IN

67

BI

41

IN

MAKE BASE FOR I2C IS ON I2C PAGE

41

BI

18

OUT

14 71 74

OUT

14 71 74

OUT

14 74

IN

14 74

IN

OUT

BOM_COST_GROUP=IO PORTS

6 3

RIO Power Connector

518S0882

J9500

504050-0491

M-RT-SM

5

1
2
3
4

6

1

2

=PP1V5_S0_RDRVR

68

PLACE_NEAR=J9510.39:2.54MM

1

2

BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE

SM
SM
SM
SM
SM
SM
SM
SM

SYNC_MASTER=GKOO_J52 SYNC_DATE=05/01/2014

PAGE TITLE

RIO Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R9530

300K

5%
1/20W
MF
201

C9593

0.1UF

10%
16V
X5R-CERM
0201

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

95 OF 120

SHEET

66 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

DISPLAY MUX: DP OR HDMI

12

=PP3V3_S0_DPMUX

D

TOWARDS PORTS

C

=PP3V3_S0_DPMUX

67 68

100K

1/20W

1

5%
MF

201

G S

1

2

3

D

2

R9753

Q9700

DMN32D2LFB4

DFN1006H4-3

B

SYM_VER_2

67 68

1

C9750

DP 1:2 ANALOG DEMUX

A2

25 77

OUT

25 77

OUT

25 77

OUT

25 77

OUT

25 77

OUT

25 77

OUT

25 77

OUT

25 77

OUT

25 77

BI

25 77

BI

66 71 77

OUT

66 71 77

OUT

66 71 77

OUT

66 71 77

OUT

66 71 77

OUT

66 71 77

OUT

66 71 77

OUT

66 71 77

OUT

DP_TBTSNK1_ML_C_P<0>
DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<1>
DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<2>
DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<3>
DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_DDC_CLK

30 67

OUT

DP_TBTSNK1_DDC_DATA

30 67

BI

25 67

66 67

OUT

66 67

BI

66 67

DP_TBTSNK1_HPD

IN

HDMI_IG_DATA_C_P<2>
HDMI_IG_DATA_C_N<2>

HDMI_IG_DATA_C_P<1>
HDMI_IG_DATA_C_N<1>

HDMI_IG_DATA_C_P<0>
HDMI_IG_DATA_C_N<0>

HDMI_IG_CLK_C_P
HDMI_IG_CLK_C_N

HDMI_IG_DDC_CLK
HDMI_IG_DDC_DATA

IN

HDMI_HPD

DISP_MUX_SEL_L

67

DISP_MUX_EN

DISP MUX SEL_L

SEL_L 0 = DP
SEL_L 1 = HDMI

B4

DA0(P)

A4

DA0(N)

B5

DA1(P)

A5

DA1(N)

B6

DA2(P)

A6

DA2(N)

A8

DA3(P)

A9

DA3(N)

H9

AUXA(P)

J9

AUXA(N)

H8

DDCCLK_A

J8

DDCDAT_A

J2

HPDA

B8

DB0(P)

B9

DB0(N)

D8

DB1(P)

D9

DB1(N)

E8

DB2(P)

E9

DB2(N)

F8

DB3(P)

F9

DB3(N)

H6
J6

H5
J5

H3

A1

B7

AUXB(P)
AUXB(N)

DDCCLK_B
DDCDAT_B

HPDB

DX_SEL

NC
NC

J4

VDDOEVDD

U9750

HD3SS213ZQE

BGA

CRITICAL

DDCCLK_C
DDCDAT_C

GND

GND

GND

GND

GND

B3C8G8H4H7

DC0(P)
DC0(N)

DC1(P)
DC1(N)

DC2(P)
DC2(N)

DC3(P)
DC3(N)

AUXC(P)
AUXC(N)

HPDC

AUX_SEL

GND

G2

0.1UF

20%
10V

2

X7R-CERM
0402

B2

DP_HDMI_TBT_ML_P<0>

B1

DP_HDMI_TBT_ML_N<0>

D2

DP_HDMI_TBT_ML_P<1>

D1

DP_HDMI_TBT_ML_N<1>

E2

DP_HDMI_TBT_ML_P<2>

E1

DP_HDMI_TBT_ML_N<2>

F2

DP_HDMI_TBT_ML_P<3>

F1

DP_HDMI_TBT_ML_N<3>

H2

DP_HDMI_TBT_AUX_P

H1

DP_HDMI_TBT_AUX_N

J1

J3
J7
C2

1

C9751

0.1UF

20%
10V

2

X7R-CERM
0402

DPMUX_HPD_OUT

DP_HDMI_TBT_DDC_CLK
DP_HDMI_TBT_DDC_DATA
DPMUX_AUX_DDC_SEL

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

69 77

69 77

69 77

69 77

69 77

69 77

69 77

69 77

69 77

69 77

67

IN

BI

TOWARDS CPU

67 69

67 69

1

2

=PP3V3_S0_DPMUX

67 68

DISP_MUX_EN

67

OUT

R9752

100K

5%
1/20W
MF
201

NO STUFF

R9755

NO STUFF

Q9701

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

69

100K

1/20W

1

5%
MF

201

G S

1

2

3

D

2

NOTE: HDMI ML SWIZZLED INTENTIONALLY AS PER TABLE 9-1 HASWELL-ULT PDG

=PP3V3_S0_DPMUX

67 68

TOWARDS PORTS

HDMI_IG_DDC_CLK

66 67

BI

HDMI_IG_DDC_DATA

66 67

BI

DP_TBTSNK1_DDC_CLK

30 67

BI

DP_TBTSNK1_DDC_DATA

30 67

BI

C9725

0.1UF

X6S-CERM

DISP_MUX_EN_L

=PP3V3_S0_DPMUX

67 68

C9700

0.1UF

CERM-X5R

DP_TBTSNK1_HPD

25 67

HDMI_HPD

66 67

HDMITBTMUX_LATCH

67 69

20%
16V

0201

6.3V
0201

10%

1

2

9

VCC

NO STUFF

5

M+

4

M-

U9725

PI3USB102ZLE

7

D+

CRITICAL

6

D-

8

TQFN

GND

3

1

Y+

2

Y-

10

SELOE*

SIGNAL_MODEL=MOJO_MUX

NO STUFF

1

R9725

10K

5%
1/20W
MF
201

2

DISP_MUX_SEL

1

R9726

10K

5%
1/20W
MF
201

2

DP_HDMI_TBT_DDC_CLK
DP_HDMI_TBT_DDC_DATA

DISP MUX SEL
SEL 0 = HDMI
SEL 1 = DP

1

R9727

10K

5%
1/20W
MF
201

2

67 69

67 69

BI
BI

67 69

TOWARDS CPU

D

C

1

2

OMIT_TABLE

U9700

SLG4APXXX

TDFN

1

VDD

2

IO_2

3

IO_3

4

IO_4

THRM

PAD

9

IO_8

IO_7

IO_6

GND

8

7

6

5

DISP_MUX_EN

DISP_MUX_SEL

HDMITBTMUX_FLAG_L

67

67 69

15 67

B

DISP_MUX_SEL

67 69

PART NUMBER

343S0666

=PP3V3_S4_DPMUX

68

=PP3V3_S0_DPMUX

67 68

NOSTUFF

R9701

A

R9702

PRIORITY 0 = HDMI WINS OVER DP

PRIORITY 1 = DP WINS OVER HDMI

100K

1/20W

201

100K

1/20W

201

5%
MF

5%
MF

1

2

DISP_MUX_PRIORITY

1

2

=PP3V3_S0_DPMUX

67 68

R9703

510K

5%

1/20W

MF

201

67

R9704

510K

5%

1/20W

MF

201

1

2

DPMUX_AUX_DDC_SEL

1

2

AUX_SEL 0 = AUX ONLY
AUX_SEL 1 = DDC ONLY
AUX_SEL Vdd/2 = AUX & DDC

67

HDMI_HPD

66 67

DP_TBTSNK1_HPD

25 67

DISP_MUX_PRIORITY

67

HDMITBTMUX_LATCH

67 69

C9775

0.1UF

10%

6.3V

CERM-X5R

0201

1

2

NOSTUFF

CRITICAL

SLG46400V

1

VDD

2

GPI(2)

3

GPIO(3)

4

GPIO(4)

5

NC

6

GPIO(5)
GPIO(6)

U9775

TDFN

GPIO(12)
GPIO(11)
GPIO(10)

THRM_PAD

13

67 68

GPIO(9)
GPIO(8)

=PP3V3_S0_DPMUX

R9754

100K

1/20W

201

12
11
10
9
8
7

GND

1

5%
MF

2

NC
NC

HDMITBTMUX_FLAG_L

DISP_MUX_EN
DISP_MUX_SEL

67

67 69

15 67

DISP MUX SEL
SEL 0 = HDMI
SEL 1 = DP

QTY

1

6 3

DESCRIPTION

IC, SAK,AP4179,DP MUX CTRLR,TDFN-8

BOM_COST_GROUP=TBT

REFERENCE DES

U9700

SYNC_MASTER=SRAMAN_J44

PAGE TITLE

CRITICAL

CRITICAL

BOM OPTION

Display Mux: HDMI vs DP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/29/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

97 OF 120

SHEET

67 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

"G3Hot" (Always-Present) Rails

=PPBUS_G3H

53 54

=PPVIN_S5_HS_COMPUTING_ISNS

42

D

=PPVIN_S5_HS_OTHER5V_ISNS

42 58

=PPVIN_S5_HS_OTHER3V3_ISNS

42 58

=PPBUS_X239_REG

62

=PPVIN_X239_PBUS_ISNS

42

=PP18V5_DCIN_ISOL

53

C

=PP18V5_DCIN_CONN

53

=PP3V42_G3H_REG

53

=PPVRTC_G3_OUT

17

B

5V Rails

=PP5V_S5_LDO

58

=PP5V_S5_FET

63

=PP5V_S3_REG

58

=PP5V_S3_AUDIO

48

A

=PP5V_S0_ISNS

PPBUS_G3H

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=8.6V
MAKE_BASE=TRUE

=PPVIN_S0SW_LCDBKLTFET
=PPBUS_S0_VSENSE
=PPVIN_SW_TBTBST

=PPVIN_S5_HS_COMPUTING_ISNS_R
=PPVIN_S5_HS_OTHER5V_ISNS_R
=PPVIN_S5_HS_OTHER3V3_ISNS_R
=PPVIN_X239

PPBUS_S5_HS_COMPUTING

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V
MAKE_BASE=TRUE

=PPVIN_S0_CPUVR
=PPVIN_S3_DDRREG
=PPVIN_S0_1V05S0

PPBUS_S5_HS_OTHER5V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V

PPBUS_S5_HS_OTHER3V3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V

PPBUS_S4_X239

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.9V

=PPVIN_X239_PBUS_ISNS_R

PPVIN_S4_TPAD

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V

=PPVIN_S4_TPAD

PPDCIN_G3H_ISOL

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=18.5V

=PPDCIN_S5_CHGR_ISOL
=PPDCIN_S5_VSENSE

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

PP3V42_G3H

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE

=PP3V3_G3H_T112
=PP3V3_S5_SMC
=PP3V42_G3H_HALL
=PP3V42_G3H_CHGR
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_5
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3H_SYSCLK
=PP3V42_G3H_ONEWIREPROT
=PP3V42_G3H_SSDSAK
=PP3V42_G3H_CSPWRGD
=PP3V42_G3H_X239_COFET_EN

PPVRTC_G3H

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MAKE_BASE=TRUE

=PPVRTC_G3_PCH

PP5V_S5

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S5_P5VS5FET
PP5V_S4

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S4_TPAD

PP5V_S3

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.175 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S3_ALSCAM
=PP5V_S3_LTUSB
=PP5V_S3_RIO

=PP5V_S0_P5VS0FET
=PP5V_S0_1V05S0
=PP5V_S0_AUDIO_AMP
=PP5V_S0_LCD =PP5V_S0_FET
=PP5V_S3_DDRREG

PP5V_S0

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_LPCPLUS

=PP5V_S0_CPUVR

=PP5V_S0_VMON

=PP5V_S0_PCH_STRAP

=PP5V_S0_XDPJTAGISOL
=PP5V_S0_FAN
=PP5V_S0_BKLT

=PP5V_S0SW_KBDLED
=PP5V_S0_ALSCAM
=PP5V_S0_HSIOFET

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

71

60

42

27

42

42

42

62

55 56

57

59

42

36 71

54

42

71

54

71

47

38 39 40

40

54

64

41

35

36

39

17

53

32

17

8

12 13

71

63

36

71

34

35

66

63

59

69

65 63

57

71 43

55 56

64

17

16

46

60

60

34

63

=PP3V3_S5_REG

58

=PP3V3_S4_FET

63

=PP3V3_SUS_FET

63

=PP3V3_S3_FET

63

=PP3V3_S0_ISNS

43

=PP3V3_S0_AUDIO

48

=PP3V3_S0_AUDIO_DIG

48 49 52

=PP3V3_S0_DDCMUX

30

=PP3V3_S0_DPMUX

67

=PP3V3_S0_EDP

65

=PP3V3_S0_FET

63

PPVREF_S3_MEM_VREFDQ_A

19

PPVREF_S3_MEM_VREFCA

19 68

PPVREF_S3_MEM_VREFDQ_B

19

PPVREF_S3_MEM_VREFCA

19 68

3.3V Rails

PP3V3_S5

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE

=PP3V3_S0SW_P3V3S0SWSSDFET

=PP3V3_S4_TBTBPWRSW

=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET
=PP3V3_S4_P3V3S4FET
=PP3V3_S5_DBGLEDS
=PP3V3_SUS_P3V3SUSFET
=PP3V3_S5_CSPWRGD
=PP3V3_S5_PCH_VCCDSW
=PP3V3_S5_PWRCTL
=PP3V3_S5_SYSCLK
=PP3V3_S5_VMON
=PP3V3_S5_PCH_GPIO
=PP3V3_S4_TBTAPWRSW
=PP3V3_S4SW_P3V3S4SWSNSFET
=PP3V3_S5_XDPJTAGISOL
=PP3V3_S0_P1V5S0

=PP3V3_S5_WLAN
=PP3V3_S5_CAMPWREN
=PP3V3_S3_P1V8S3

PP3V3_S4

MIN_LINE_WIDTH=0.20MM

=PP3V3_S4_SMC
=PP3V3_S4_TPAD
=PP3V3_S4_BT

=PP3V3_S4_TBT_ISNS_R

=PP3V3_S4_DPMUX

=PP3V3_S4_RIO
=PP3V3_S4_X239
=PP3V3_S4_SMBUS_SMC_2
=PP3V3_S4_CAMPWREN

PP3V3_SUS

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_SUS_ROM

=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_SUS_PCH_VCCSUS_ICC

=PP3V3_SUS_PCH_VCC_SPI
=PP3V3_SUS_PWRCTL
=PP3V3_SUS_P1V05SUSLDO
=PP3V3_SUS_PCH_GPIO
=PP3V3_SUS_PCH_VCCSUS_RTC

PP3V3_S3

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S3SW_SD_RESET

=PP3V3_S3_PCH_GPIO
=PP3V3_S3_SDBUF
=PP3V3_S3RS4_PCH_GPIO
=PP3V3_S3_SYSCLKGEN
=PP3V3_S3_CAMERA_R
=PP3V3_S3_TPAD

PP3V3_S0

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S0_FAN
=PP3V3_S0_SMBUS_SMC_0

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_TBTTHMSNS
=PP3V3_S0_PCH_VCCTS
=PP3V3_S0_RSTBUF
=PP3V3_S0_SB_PM
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_LCD
=PP3V3_S0_SMBUS_SMC_1
=PP3V3_S0_SMC
=PP3V3R1V8_S0_PCH_VCCSDIO

=PP3V3_S0_VMON

=PP3V3_S0RTBTLC_PCH_GPIO

=PP3V3_S0_SYSCLKGEN
=PP3V3_S0_OOB1_PWRDN
=PP3V3_S0_MEM_VTTPWRCTL
=PP3V3_S0_SNS_BMON

=PP3V3_S0_HS_COMPUTING_ISNS

=PP3V3_S0_VRISNS
=PP3V3_S0_CAMERA_R
=PP3V3_S0_SMBUS_SMC_3
=PP3V3_S0_TPAD

PP5V_S0_FET

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_ISNS_R
PP3V3_S0_FET

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S0_ISNS_R

PP0V6_S3_MEM_VREFDQ_A

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFCA_A

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_B

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFCA_B

MAKE_BASE=TRUE

VOLTAGE=3.3V

VOLTAGE=3.3V
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=0.6V

VOLTAGE=0.6V

VOLTAGE=0.6V

VOLTAGE=0.6V

71 80

63

29

63

63

63

18

63

17

8

11

64

17 18

64

13 15

28

63

16

61

31

61

71

18 39 40

36 37 71

31

44

67

66

62

41

18

47

8

11

8

8

11 14

64

61

14

8

11

71

15

15

18

15

18

44

71 80

46

8

11

12 13 15 18 26 65

44 45

45

8

11

18

17

41

65

41

39

8

11 40

64

15

18

32

17

44

42 43

43

44

41

37

43

43

20 21 76

20 21 76

22 23 76

22 23 76

=PP3V3_S4SW_SNS_FET

63

PP3V3_S0SW_SSD_FET_R

63

PP3V3_S4SW_SNS

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S4_HS_OTHER_ISNS
=PP3V3_S4_ISNS

PP3V3_S0SW_SSD_FET

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE

=PP3V3_S0SW_SSD_ISNS_R

=PP3V3_S0SW_SSD_ISNS

43

PP3V3_S0SW_SSD

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S0SW_SSD

=PP3V3_S4_TBT_ISNS

44

PP3V3_S4_TBT

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S4_TBT

1.5V/1.2V/1.8V/1.05V RAILS

=PP1V2_S3_CPUDDR_ISNS

43

=PPDDR_S3_REG

43 57

=PP1V8_S3_REG

61

=PPVTT_S0_DDR_LDO

57

=PPVTT_S3_DDR_BUF

57

=PP1V05_SUS_LDO

61

=PP1V5_S0_REG

61

=PP1V05_S0_REG

59

? mA

=PP1V05_S0SW_PCH_HSIO_FET

63

1.84A

PP1V2_S3_CPUDDR

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PPVMEMIO_S0_CPU

PP1V2_S3

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PP1V2_S3_MEM_VDDQ

=PPVIN_S0_DDRREG_LDO
=PP1V2_S3_CPUDDR_ISNS_R
=PP1V2_S3_MEM_VTTPWRCTL

=PPDDR_S3_MEMVREF
=PP1V2_S3_MEM_VDDCA
=PP1V2_S3_MEM_VDD2

PP1V8_S3

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_S3_MEM

PP0V6_S0_DDRVTT

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.6V
MAKE_BASE=TRUE

=PP0V6_S0_MEM_VTT_A
=PP0V6_S0_MEM_VTT_B

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.675V
MAKE_BASE=TRUE

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_SUS_PCH_JTAG

PP1V5_S0

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0SW_P1V5S0SWAUDIOFET

=PP1V5_S0_PCH_VCCTS

=PP1V5_S0_AUDIO
=PP1V5_S0_VMON
=PP1V5_S0_RDRVR

PP1V05_S0

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0M_PCH_VCCASW
=PP1V05_S0_PCH_VCC
=PP1V05_S0_PCHHSIOFET
=PP1V05_S0_PCH_PLLFILTERS
=PP1V05_S0_VMON
=PP1V05_S0_PCH_VCCIO_USB2
=PP1V05_S0_PCH_VCCCLK
=PP1V05_S0_CPU_VCCST
=PP1V05_S0_PCH_VCCIO_HSIO
=PPVIN_S0_1V05S0_LDO
=PP1V05_S0_SMC
=PP1V05_S0_XDP

PP1V05_S0SW_PCH_HSIO

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0SW_PCH_VCCHSIO
=PP1V05_S0SW_PCH_VCCPLL_HSIO

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V

VOLTAGE=3.3V

MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

42

42 43 44

43

32

25 26 27

76

8

10

76

20 21 22 23

57

43

17

19

20 21 22 23

20 21 22 23

20 21 22 23

71 76

24

24

71 76

16

71

63

8

49

64

66

71

8

11

8

11

63

11

64

8

8

11

6 8

15 16 17 55

8

59

39

16

8

11

TBT RAILS (OFF WHEN NO CABLE)

PPVIN_SW_TBTBST

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V

=PP15V_TBT_REG

27

PP15V_TBT

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=15V
MAKE_BASE=TRUE

=PPHV_S4SW_TBTAPWRSW
=PPHV_S4SW_TBTBPWRSW

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PPVDDIO_TBTLC_CLK

CPU "VCORE" RAILS

=PPVCC_S0_CPU_REG

56

PPVCC_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PPVCC_S0_CPU

Digital Ground

GND

VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM

11

SYNC_MASTER=SHART_J44

PAGE TITLE

Power Aliases

Apple Inc.

11

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R

6 3

12

27

28

29

18 25 26

17

SYNC_DATE=01/14/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

100 OF 120

SHEET

68 OF 82

124578

71

8

10 44

SIZE

D

C

B

A

D

8 7 6 5 4 3

HDMI VS TBT

12

=DP_TBTSNK1_ML_C_P<0>

5

=DP_TBTSNK1_ML_C_N<0>

5

=DP_TBTSNK1_ML_C_P<1>

5

=DP_TBTSNK1_ML_C_N<1>

5

=DP_TBTSNK1_ML_C_P<2>

5

=DP_TBTSNK1_ML_C_N<2>

5

=DP_TBTSNK1_ML_C_P<3>

D

5

=DP_TBTSNK1_ML_C_N<3>

5

=DP_TBTSNK1_AUXCH_C_P

13

=DP_TBTSNK1_AUXCH_C_N

13

=DP_TBTSNK1_DDC_CLK

13

=DP_TBTSNK1_DDC_DATA

13

=DP_TBTSNK1_HPD

13

HDMITBTMUX_SEL_TBT

25

MAKE_BASE=TRUE

DP_AUXCH_ISOL_L

13

EPD PANEL

=I2C_BKLT_SCL

60 65 71

=I2C_BKLT_SDA

60

MAKE_BASE

DP_HDMI_TBT_ML_P<0>

TRUE

DP_HDMI_TBT_ML_N<0>

TRUE

DP_HDMI_TBT_ML_P<1>

TRUE

DP_HDMI_TBT_ML_N<1>

TRUE

DP_HDMI_TBT_ML_P<2>

TRUE

DP_HDMI_TBT_ML_N<2>

TRUE

DP_HDMI_TBT_ML_P<3>

TRUE

DP_HDMI_TBT_ML_N<3>

TRUE

DP_HDMI_TBT_AUX_P

TRUE

DP_HDMI_TBT_AUX_N

TRUE

DP_HDMI_TBT_DDC_CLK

TRUE

DP_HDMI_TBT_DDC_DATA

TRUE

DPMUX_HPD_OUT

TRUE

=TBT_GO2SX_BIDIR

HDMITBTMUX_LATCH

MAKE_BASE=TRUE

MAKE_BASE

I2C_BKLT_SCL

TRUE

I2C_BKLT_SDA

TRUE

DISP_MUX_SEL

67

65 71

67 77

67 77

15

67

67 77

67 77

67 77

67 77

67 77

67 77

67 77

67 77

67

67

D

67

UNUSED SIGNALS

C

TP_PCIE_CLK100M_FWP

12

TP_PCIE_CLK100M_FWN

12

TP_PCIE_FW_D2RP

14

TP_PCIE_FW_D2RN

14

TP_PCIE_FW_R2D_CP

14

TP_PCIE_FW_R2D_CN

14

TP_PCIE_CLK100M_ENETSDP

12

TP_PCIE_CLK100M_ENETSDN

12

USB_IR_P

14

USB_IR_N

14

TP_USB_CAMERAP

14

TP_USB_CAMERAN

14

TP_USB_SDP

14

TP_USB_SDN

14

TP_HDA_SDIN1

12

TP_PCI_PME_L

13

TP_CLINK_CLK

14

TP_CLINK_DATA

14

TP_CLINK_RESET_L

14

TP_ITPXDP_CLK100MN

12

TP_ITPXDP_CLK100MP

12

TP_PCH_I2S1_TXD

12

B

TP_PCH_I2S1_SFRM

12

TP_PCH_I2S1_SCLK

12

TP_PCH_SLP_WLAN_L

13

TP_PCH_SLP_LAN_L

13

TP_SPI_CS1_L

14

TP_SPI_CS2_L

14

TP_USB_5N

14

TP_USB_5P

14

MAKE_BASE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

TRUE

NO_TEST=TRUE
TRUE NO_TEST=TRUE
TRUE

NO_TEST=TRUE

NO_TEST=TRUE

TRUE
TRUE

NO_TEST=TRUE

NO_TEST=TRUE

TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_FWP
NC_PCIE_CLK100M_FWN
NC_PCIE_FW_D2RP
NC_PCIE_FW_D2RN

NC_PCIE_FW_R2D_CP
NC_PCIE_FW_R2D_CN

NC_PCIE_CLK100M_ENETSDP
NC_PCIE_CLK100M_ENETSDN
NC_USB_IRP
NC_USB_IRN
NC_USB_CAMERAP
NC_USB_CAMERAN
NC_USB_SDP
NC_USB_SDN

NC_HDA_SDIN1
NC_PCI_PME_L
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L

NC_ITPXDP_CLK100MN
NC_ITPXDP_CLK100MP
NC_PCH_I2S1_TXD
NC_PCH_I2S1_SFRM
NC_PCH_I2S1_SCLK
NC_PCH_SLP_WLAN_L

NC_PCH_SLP_LAN_L
NC_SPI_CS1_L
NC_SPI_CS2_L
NC_USB_5N
NC_USB_5P

TP_TBT_MONDC0

25

TP_TBT_MONDC1

25

TP_TBT_PCIE_RESET0_L

25

TP_TBT_XTAL25OUT

25

TP_DP_TBTSRC_ML_CP<3>

25

TP_DP_TBTSRC_ML_CN<3>

25

TP_DP_TBTSRC_ML_CP<2>

74

74

74

74

74

74

74

74

25

TP_DP_TBTSRC_ML_CN<2>

25

TP_DP_TBTSRC_ML_CP<1>

25

TP_DP_TBTSRC_ML_CN<1>

25

TP_DP_TBTSRC_ML_CP<0>

25

TP_DP_TBTSRC_ML_CN<0>

25

TP_DP_TBTSRC_AUXCH_CP

25

TP_DP_TBTSRC_AUXCH_CN

25

TBT UNUSED NETS

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_TBT_PCIE_RESET0_L

TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CP<3>

TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CN<3>

TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CP<2>

TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CN<2>

TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CP<1>

TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CN<1>

TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CP<0>

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_AUXCH_CP

TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_AUXCH_CN

TRUE
MAKE_BASE=TRUE

NC_TBT_MONDC0
NC_TBT_MONDC1

NC_TBT_XTAL25OUT

NC_DP_TBTSRC_ML_CN<0>

C

B

TP_AUD_CODEC_MICBIAS1_L

48

TP_AUD_CODEC_MICBIAS1_R

48

TP_AUD_CODEC_MICBIAS2_L

48

TP_AUD_CODEC_MICBIAS2_R

48

TP_SUS_PGOOD_MR_L

64

TP_SMC_TRST_L
TP_SMC_MD1
TP_TDM_ONEWIRE_MPM

A

53

GND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

TRUE NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE NO_TEST=TRUE

TRUE

NO_TEST=TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

NO_TEST=TRUE

TRUE

=PP5V_S0_AUDIO_AMP

68

Digital Ground

6 3

NC_AUD_CODEC_MICBIAS1_L
NC_AUD_CODEC_MICBIAS1_R
NC_AUD_CODEC_MICBIAS2_L
NC_AUD_CODEC_MICBIAS2_R

NC_SUS_PGOOD_MR_L

NC_SMC_TRST_L

NC_SMC_MD1

NC_TDM_ONEWIRE_MPM

XWA202

SM

1 2

XWA203

SM

1 2

PP5V_S0_AUDIO_AMP_L

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

PP5V_S0_AUDIO_AMP_R

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

SIZE

A

D

SYNC_MASTER=SHART_J44

PAGE TITLE

Signal Aliases

Apple Inc.

50

50

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R

SYNC_DATE=11/19/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

102 OF 120

SHEET

69 OF 82

124578

8 7 6 5 4 3

12

LPDDR3 COMMAND/ADDRESS

=MEM_A_A<5>

7

=MEM_A_A<9>

D

C

B

7

=MEM_A_A<6>

7

=MEM_A_A<8>

7

=MEM_A_A<7>

7

=MEM_A_BA<2>

7

=MEM_A_A<12>

7

=MEM_A_A<11>

7

=MEM_A_A<15>

7

=MEM_A_A<14>

7

=MEM_A_A<13>

7

=MEM_A_CAS_L

7

=MEM_A_WE_L

7

=MEM_A_RAS_L

7

=MEM_A_BA<0>

7

=MEM_A_A<2>

7

=MEM_A_BA<1>

7

=MEM_A_A<10>

7

=MEM_A_A<1>

7

=MEM_A_A<0>

7

=MEM_A_ODT<0>

7

=MEM_A_A<3>

7

=MEM_A_A<4>

7

=MEM_B_A<5>

7

=MEM_B_A<9>

7

=MEM_B_A<6>

7

=MEM_B_A<8>

7

=MEM_B_A<7>

7

=MEM_B_BA<2>

7

=MEM_B_A<12>

7

=MEM_B_A<11>

7

=MEM_B_A<15>

7

=MEM_B_A<14>

7

=MEM_B_A<13>

7

=MEM_B_CAS_L

7

=MEM_B_WE_L

7

=MEM_B_RAS_L

7

=MEM_B_BA<0>

7

=MEM_B_A<2>

7

=MEM_B_BA<1>

7

=MEM_B_A<10>

7

=MEM_B_A<1>

7

=MEM_B_A<0>

7

=MEM_B_ODT<0>

7

=MEM_B_A<3>

7

=MEM_B_A<4>

7

UNUSED MEMORY SIGNALS

6

MAKE_BASE

MAKE_BASE

TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TP_CPU_MEM_RESET_L=MEM_RESET_L

MEM_A_CAA<0>
MEM_A_CAA<1>
MEM_A_CAA<2>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_CAA<5>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_CAA<8>
MEM_A_CAA<9>

MEM_A_CAB<0>
MEM_A_CAB<1>
MEM_A_CAB<2>
MEM_A_CAB<3>
MEM_A_CAB<4>
MEM_A_CAB<5>
MEM_A_CAB<6>
MEM_A_CAB<7>
MEM_A_CAB<8>
MEM_A_CAB<9>
MEM_A_ODT<0>
TP_LPDDR3_RSVD1
TP_LPDDR3_RSVD2

MEM_B_CAA<0>
MEM_B_CAA<1>
MEM_B_CAA<2>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAA<7>
MEM_B_CAA<8>
MEM_B_CAA<9>

MEM_B_CAB<0>
MEM_B_CAB<1>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<4>
MEM_B_CAB<5>
MEM_B_CAB<6>
MEM_B_CAB<7>
MEM_B_CAB<8>
MEM_B_CAB<9>
MEM_B_ODT<0>
TP_LPDDR3_RSVD3
TP_LPDDR3_RSVD4

20 24 76

20 24 76

20 24 76

20 24 76

20 24 76

20 24 76

20 24 76

20 24 76

20 24 76

20 24 76

21 24 76

21 24 76

21 24 76

21 24 76

21 24 76

21 24 76

21 24 76

21 24 76

21 24 76

21 24 76

20 21 24 76

22 24 76

22 24 76

22 24 76

22 24 76

22 24 76

22 24 76

22 24 76

22 24 76

22 24 76

22 24 76

23 24 76

23 24 76

23 24 76

23 24 76

23 24 76

23 24 76

23 24 76

23 24 76

23 24 76

23 24 76

22 23 24 76

MEM_A_DQ<0>

7

71 76

MEM_A_DQ<1>

7

71 76

MEM_A_DQ<2>

7

71 76

MEM_A_DQ<3>

7

71 76

MEM_A_DQ<4>

7

71 76

MEM_A_DQ<5>

7

71 76

MEM_A_DQ<6>

7

71 76

MEM_A_DQ<7>

7

71 76

MEM_A_DQ<8>

7

71 76

MEM_A_DQ<9>

7

71 76

7

71 76

7

71 76

MEM_A_DQ<12>

7

71 76

MEM_A_DQ<13>

7

71 76

MEM_A_DQ<14>

7

71 76

MEM_A_DQ<15>

7

71 76 20

MEM_A_DQ<16>

7

71 76

MEM_A_DQ<17>

7

71 76

MEM_A_DQ<18>

7

71 76

MEM_A_DQ<19>

7

71 76

MEM_A_DQ<20>

7

71 76

MEM_A_DQ<21>

7

71 76

MEM_A_DQ<22>

7

71 76

MEM_A_DQ<23>

7

71 76

MEM_A_DQ<24>

7

71 76

MEM_A_DQ<25>

7

71 76

MEM_A_DQ<26>

7

71 76

MEM_A_DQ<27>

7

71 76

MEM_A_DQ<28>

7

71 76

MEM_A_DQ<29>

7

71 76

MEM_A_DQ<30>

7

71 76

MEM_A_DQ<31>

7

71 76

MEM_A_DQ<32>

7

71 76

MEM_A_DQ<33>

7

71 76

MEM_A_DQ<34>

7

71 76

MEM_A_DQ<35>

7

71 76

MEM_A_DQ<36>

7

71 76

MEM_A_DQ<37>

7

71 76

MEM_A_DQ<38>

7

71 76

MEM_A_DQ<39>

7

71 76

MEM_A_DQ<40>

7

71 76

MEM_A_DQ<41>

7

71 76

MEM_A_DQ<42>

7

71 76

MEM_A_DQ<43>

7

71 76

MEM_A_DQ<44>

7

71 76

MEM_A_DQ<45>

7

71 76

MEM_A_DQ<46>

7

71 76

MEM_A_DQ<47>

7

71 76

MEM_A_DQ<48>

7

71 76

MEM_A_DQ<49>

7

71 76

MEM_A_DQ<50>

7

71 76

MEM_A_DQ<51>

7

71 76

MEM_A_DQ<52>

7

71 76

MEM_A_DQ<53>

7

71 76

MEM_A_DQ<54>

7

71 76

MEM_A_DQ<55>

7

71 76

MEM_A_DQ<56>

7

71 76

MEM_A_DQ<57>

7

71 76

MEM_A_DQ<58>

7

71 76

MEM_A_DQ<59>

7

71 76

MEM_A_DQ<60>

7

71 76

MEM_A_DQ<61>

7

71 76

MEM_A_DQ<62>

7

71 76

MEM_A_DQ<63>

7

71 76

Memory Bit/Byte Swizzle

TRUETRUE
=MEM_A_DQ<7>
=MEM_A_DQ<6>
=MEM_A_DQ<5>
=MEM_A_DQ<1>
=MEM_A_DQ<3>
=MEM_A_DQ<2>
=MEM_A_DQ<0>
=MEM_A_DQ<4>

=MEM_A_DQ<10>
=MEM_A_DQ<14>
=MEM_A_DQ<8>MEM_A_DQ<10>
=MEM_A_DQ<9>MEM_A_DQ<11>
=MEM_A_DQ<15>
=MEM_A_DQ<11>
=MEM_A_DQ<12>
=MEM_A_DQ<13>

=MEM_A_DQ<21>
=MEM_A_DQ<16>
=MEM_A_DQ<23>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<22>
=MEM_A_DQ<17>
=MEM_A_DQ<20>

=MEM_A_DQ<27>
=MEM_A_DQ<26>
=MEM_A_DQ<25>
=MEM_A_DQ<29>
=MEM_A_DQ<30>
=MEM_A_DQ<31>
=MEM_A_DQ<24>
=MEM_A_DQ<28>

=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<37>
=MEM_A_DQ<33>
=MEM_A_DQ<35>
=MEM_A_DQ<34>
=MEM_A_DQ<32>
=MEM_A_DQ<36>

=MEM_A_DQ<42>
=MEM_A_DQ<46>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DQ<47>
=MEM_A_DQ<43>
=MEM_A_DQ<44>
=MEM_A_DQ<45>

=MEM_A_DQ<61>
=MEM_A_DQ<60>
=MEM_A_DQ<58>
=MEM_A_DQ<62>
=MEM_A_DQ<63>
=MEM_A_DQ<59>
=MEM_A_DQ<57>
=MEM_A_DQ<56>

=MEM_A_DQ<48>
=MEM_A_DQ<49>
=MEM_A_DQ<55>
=MEM_A_DQ<51>
=MEM_A_DQ<53>
=MEM_A_DQ<52>
=MEM_A_DQ<54>
=MEM_A_DQ<50>

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

MEM_B_DQ<0>

7

71 76

MEM_B_DQ<1>

7

71 76

MEM_B_DQ<2>

7

71 76

MEM_B_DQ<3>

7

71 76

MEM_B_DQ<4>

7

71 76

MEM_B_DQ<5>

7

71 76

MEM_B_DQ<6>

7

71 76

MEM_B_DQ<7>

7

71 76

MEM_B_DQ<8>

7

71 76

MEM_B_DQ<9>

7

71 76

7

71 76

7

71 76

MEM_B_DQ<12>

7

71 76

MEM_B_DQ<13>

7

71 76

MEM_B_DQ<14>

7

71 76

MEM_B_DQ<15>

7

71 76

MEM_B_DQ<16>

7

71 76

MEM_B_DQ<17>

7

71 76

MEM_B_DQ<18>

7

71 76

MEM_B_DQ<19>

7

71 76

MEM_B_DQ<20>

7

71 76

MEM_B_DQ<21>

7

71 76

MEM_B_DQ<22>

7

71 76

MEM_B_DQ<23>

7

71 76

MEM_B_DQ<24>

7

71 76

MEM_B_DQ<25>

7

71 76

MEM_B_DQ<26>

7

71 76

MEM_B_DQ<27>

7

71 76

MEM_B_DQ<28>

7

71 76

MEM_B_DQ<29>

7

71 76

MEM_B_DQ<30>

7

71 76

MEM_B_DQ<31>

7

71 76

MEM_B_DQ<32>

7

71 76

MEM_B_DQ<33>

7

71 76

MEM_B_DQ<34>

7

71 76

MEM_B_DQ<35>

7

71 76

MEM_B_DQ<36>

7

71 76

MEM_B_DQ<37>

7

71 76

MEM_B_DQ<38>

7

71 76

MEM_B_DQ<39>

7

71 76

MEM_B_DQ<40>

7

71 76

MEM_B_DQ<41>

7

71 76

MEM_B_DQ<42>

7

71 76

MEM_B_DQ<43>

7

71 76

MEM_B_DQ<44>

7

71 76

MEM_B_DQ<45>

7

71 76

MEM_B_DQ<46>

7

71 76

MEM_B_DQ<47>

7

71 76

MEM_B_DQ<48>

7

71 76

MEM_B_DQ<49>

7

71 76

MEM_B_DQ<50>

7

71 76

MEM_B_DQ<51>

7

71 76

MEM_B_DQ<52>

7

71 76

MEM_B_DQ<53>

7

71 76

MEM_B_DQ<54>

7

71 76

MEM_B_DQ<55>

7

71 76

MEM_B_DQ<56>

7

71 76

MEM_B_DQ<57>

7

71 76

MEM_B_DQ<58>

7

71 76

MEM_B_DQ<59>

7

71 76

MEM_B_DQ<60>

7

71 76

MEM_B_DQ<61>

7

71 76

MEM_B_DQ<62>

7

71 76

MEM_B_DQ<63>

7

71 76

=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<5>
=MEM_B_DQ<1>
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=MEM_B_DQ<0>
=MEM_B_DQ<4>

=MEM_B_DQ<10>
=MEM_B_DQ<14>
=MEM_B_DQ<8>MEM_B_DQ<10>
=MEM_B_DQ<9>MEM_B_DQ<11>
=MEM_B_DQ<15>
=MEM_B_DQ<11>
=MEM_B_DQ<12>
=MEM_B_DQ<13>

=MEM_B_DQ<22>
=MEM_B_DQ<18>
=MEM_B_DQ<17>
=MEM_B_DQ<16>
=MEM_B_DQ<23>
=MEM_B_DQ<19>
=MEM_B_DQ<20>
=MEM_B_DQ<21>

=MEM_B_DQ<27>
=MEM_B_DQ<26>
=MEM_B_DQ<24>
=MEM_B_DQ<28>
=MEM_B_DQ<31>
=MEM_B_DQ<30>
=MEM_B_DQ<29>
=MEM_B_DQ<25>

=MEM_B_DQ<39>
=MEM_B_DQ<38>
=MEM_B_DQ<37>
=MEM_B_DQ<33>
=MEM_B_DQ<35>
=MEM_B_DQ<34>
=MEM_B_DQ<32>
=MEM_B_DQ<36>

=MEM_B_DQ<42>
=MEM_B_DQ<46>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
=MEM_B_DQ<47>
=MEM_B_DQ<43>
=MEM_B_DQ<44>
=MEM_B_DQ<45>

=MEM_B_DQ<53>
=MEM_B_DQ<55>
=MEM_B_DQ<49>
=MEM_B_DQ<54>
=MEM_B_DQ<51>
=MEM_B_DQ<52>
=MEM_B_DQ<48>
=MEM_B_DQ<50>

=MEM_B_DQ<62>
=MEM_B_DQ<63>
=MEM_B_DQ<57>
=MEM_B_DQ<60>
=MEM_B_DQ<61>
=MEM_B_DQ<56>
=MEM_B_DQ<58>
=MEM_B_DQ<59>

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

D

C

B

=MEM_A_DQS_P<0>

20

=MEM_A_DQS_N<0>

20

=MEM_A_DQS_P<1>

20

=MEM_A_DQS_N<1>

20

=MEM_A_DQS_P<2>

20

=MEM_A_DQS_N<2>

20

=MEM_A_DQS_P<3>

A

20

=MEM_A_DQS_N<3>

20

=MEM_A_DQS_P<4>

21

=MEM_A_DQS_N<4>

21

=MEM_A_DQS_P<5>

21

=MEM_A_DQS_N<5>

21

=MEM_A_DQS_P<6>

21

=MEM_A_DQS_N<6>

21

=MEM_A_DQS_P<7>

21

=MEM_A_DQS_N<7>

21

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

=MEM_B_DQS_P<0>

22

=MEM_B_DQS_N<0>

22

=MEM_B_DQS_P<1>

22

=MEM_B_DQS_N<1>

22

=MEM_B_DQS_P<2>

22

=MEM_B_DQS_N<2>

22

=MEM_B_DQS_P<3>

22

=MEM_B_DQS_N<3>

22

=MEM_B_DQS_P<4>

23

=MEM_B_DQS_N<4>

23

=MEM_B_DQS_P<5>

23

=MEM_B_DQS_N<5>

23

=MEM_B_DQS_P<6>

23

=MEM_B_DQS_N<6>

23

=MEM_B_DQS_P<7>

23

=MEM_B_DQS_N<7>

23

6 3

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

7

76

SYNC_MASTER=AHARTMAN_J52

PAGE TITLE

Memory Bit & Byte Swizzle

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/29/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

103 OF 120

SHEET

70 OF 82

SIZE

A

D

124578

8 7 6 5 4 3

Functional Test Points

J6050 (LEFT FAN CONN)

FUNC_TEST

TRUE

TRUE

TRUE

PP5V_S0
FAN_LT_PWM

FAN_LT_TACH

68
71

3 TPs
per Fan

D

J4002 (ALS/CAMERA CONN)

SMBUS_SMC_1_S0_SCL

TRUE

SMBUS_SMC_1_S0_SDA

TRUE

PP5V_S3RS0_ALSCAM_F

TRUE

MIPI_CLK_CONN_N

TRUE

MIPI_CLK_CONN_P

TRUE

CAM_SENSOR_WAKE_L_CONN

TRUE

MIPI_DATA_CONN_N

TRUE

MIPI_DATA_CONN_P

TRUE

I2C_CAM_SCK

TRUE

I2C_CAM_SDA

TRUE

J9500 (RIO POWER PINS)

PP3V3_S4

TRUE

PP5V_S3

TRUE

PP1V5_S0

TRUE

TRUE

GND

38 41 79

38 41 79

34 78

34 78

34 78

34 78

33 34

33 34

68 71

68 71

68

34

34

14 25 81

14 25 81

14 34 81

14 34 81

12 32 71 81

12 32 71 81

14 66 71 81

14 66 71 81

14 66 74

14 66 74

12 49 75

U0500 CHARZ TPS

PCIE_TBT_D2R_P<0>
PCIE_TBT_D2R_N<0>

25 71 81

PCIE_CLK100M_TBT_P

12

PCIE_CLK100M_TBT_N

PCIE_CAMERA_D2R_P
PCIE_CAMERA_D2R_N

PCIE_SSD_D2R_P<0>
PCIE_SSD_D2R_N<0>

PCIE_AP_D2R_P
PCIE_AP_D2R_N

USB3RPCIE_SD_D2R_P
USB3RPCIE_SD_D2R_N

HDA_SDIN0

34 78

MIPI_CLK_N

33

MIPI_CLK_P

34 78
33

MIPI_DATA_N
MIPI_DATA_P

U5000 CHARZ TPS

75

LPC_CLK24M_SMC

17

P2MM

SM

1

P2MM

PP

SM

PPA400

1

PP

PPA401

P2MM

SM

1

P2MM

PP

SM

PPA423

1

PP

PPA424

P2MM

SM

1

P2MM

PP

SM

PPA402

1

PP

PPA403

P2MM

SM

1

P2MM

PP

SM

PPA404

1

PP

PPA405

P2MM

SM

1

P2MM

PP

SM

PPA410

1

PP

PPA411

P2MM

SM

1

P2MM

PP

SM

PPA420

1

PP

PPA421

P2MM

SM

1

PP

PPA408

PLACE_NEAR=U0500.AY10:6MM

SM

1

P2MMSMP2MM

PP

PPA441

1

PP

P2MM

PPA442

SM

1

P2MM

PP

SM

PPA443

1

PP

PPA444

P2MM

SM

1

PP

PPA419

C

J6601 (AUDIO 2-MIKE CONN)

DMIC_SDA3

SMBUS_PCH_CLK

TRUE

SMBUS_PCH_DATA

TRUE

14 41 75

14 41 75

TRUE
TRUE

TRUE

DMIC_SDA2

DMIC_CLK3

J6602 (AUDIO LEFT SPEAKER CONN)

SPKRCONN_L_OUT_P

TRUE

SPKRCONN_L_OUT_N

TRUE

J7715 (KBD BACKLIGHT CONN)

PPVOUT_S0_KBDBKLT

TRUE

KBDLED_CATHODE1

TRUE

KBDLED_CATHODE2

TRUE

37 60

37 60

37 60

SPKRCONN_L_ID

TRUE

SPKRCONN_SL_OUT_P

TRUE

SPKRCONN_SL_OUT_N

TRUE

J6603 (AUDIO RIGHT SPEAKER CONN)

SPKRCONN_R_OUT_P

TRUE

B

J7050 (MAIN BATT CONN)

PPVBAT_G3H_CONN

TRUE

SMBUS_SMC_5_G3_SCL

TRUE

SMBUS_SMC_5_G3_SDA

TRUE

SYS_DETECT_L

TRUE

J6601 (2 MIC CONN)

CON_DMIC_PWR

TRUE

CON_DMIC_SDA1

TRUE

CON_DMIC_CLK

TRUE

PCH_VSS_NCTF<19>

A

TRUE

PCH_VSS_NCTF<19>

TRUE

J4600 (LEFT USB CONN)

PP5V_S3_LTUSB_A_F

TRUE

USB_LT1_N

TRUE

USB_LT1_P

TRUE

FUNC_TEST

TRUE

TRUE

GND

GND

6 TPs

TRUE

53 54

38 41 79

38 41 79

53

71

71

35

74

74

GND

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_ID

TRUE

SPKRCONN_SR_OUT_P

TRUE

SPKRCONN_SR_OUT_N

TRUE

GND

TRUE

J8300 (EDP CONN)

PP5VR3V3_SW_LCD

TRUE

PPVOUT_S0_LCDBKLT

TRUE

I2C_BKLT_SCL

TRUE

I2C_BKLT_SDA

TRUE

LCD_HPD_CONN

TRUE

LCD_IRQ_L

TRUE

EDP_BKLT_PWM

TRUE

=I2C_TCON_SCL

TRUE

=I2C_TCON_SDA

TRUE

EDP_PANEL_PWR_OR_PSR_EN

TRUE

DP_INT_AUX_P

TRUE

DP_INT_AUX_N

TRUE

DP_INT_ML_P<0>

TRUE

DP_INT_ML_N<0>

TRUE

DP_INT_ML_P<1>

TRUE

DP_INT_ML_N<1>

TRUE

DP_INT_ML_P<2>

TRUE

DP_INT_ML_N<2>

TRUE

DP_INT_ML_P<3>

TRUE

DP_INT_ML_N<3>

TRUE

49 52

52

49 52

50 52 80

50 52 80

49 52

50 52 80

50 52 80

50 52 80

50 52 80

49 52

50 52 80

50 52 80

65

60 65

65 69

65 69

65

15 65

13 65

41 65

41 65

65 77

65 77

65 77

65 77

65 77

65 77

65 77

65 77

65 77

65 77

2 TP needed

65

J4813 (KEY BOARD CONN)

PP3V3_S4

TRUE

PP3V42_G3H

TRUE

WS_KBD1

TRUE

WS_KBD2

TRUE

WS_KBD3

TRUE

WS_KBD4

TRUE

WS_KBD5

TRUE

WS_KBD6

TRUE

WS_KBD7

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD10

TRUE

WS_KBD11

TRUE

WS_KBD12

TRUE

WS_KBD13

TRUE

WS_KBD14

TRUE

WS_KBD15_CAP

TRUE

WS_KBD16_NUM

TRUE

WS_KBD17

TRUE

WS_KBD18

TRUE

WS_KBD19

TRUE

WS_KBD20

TRUE

WS_KBD21

TRUE

WS_KBD22

TRUE

WS_KBD23

TRUE

WS_KBD_ONOFF_L

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_CONTROL_KBD

TRUE

J4802 (TPAD CONN)

SMBUS_SMC_2_S3_SDA

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

=PPVIN_S4_TPAD

TRUE

TPAD_ACTUATOR_EN_L

TRUE

TPAD_ACTUATOR_THRMTRIP_L

TRUE

TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE
TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

=TPAD_WAKE_L
SMC_LID
=PP3V3_S4_TPAD
I2C_IOXP_SDA
I2C_IOXP_SCL
TPAD_SPI_INT_L
=TPAD_SPI_SCLK
=TPAD_SPI_MISO
=TPAD_SPI_MOSI
TPAD_VBUS_EN
PP5V_S4_TPAD_F
IOXP2_INT_L
=TPAD_SPI_BUS_EN
=TPAD_SPI_CS_L
GND_ACTUATOR
USB_TPAD_P
USB_TPAD_N
=I2C_TPAD_SCL
=I2C_TPAD_SDA

I2160

I2161
I2163

I2162

I2164
I2165

I2166

I2167

TRUE

TRUE
TRUE

TRUE

J7000 (DC POWER CONN)

TDM_ONEWIRE_MPM

TRUE

ADAPTER_SENSE

TRUE

PP18V5_DCIN_FUSE

TRUE

TRUE

TRUE

TRUE

TRUE

GND

PM_CLKRUN_L
PM_SYSRST_L

SMC_ONOFF_L

J6100 (LPC + SPI CONN)

PP3V42_G3H

TRUE

PP5V_S0

TRUE

LPC_AD<0>

TRUE

LPC_AD<2>

TRUE

LPC_AD<1>

TRUE

LPC_AD<3>

TRUE

LPCPLUS_GPIO

TRUE

LPCPLUS_RESET_L

TRUE

SMC_TDO

TRUE

SMC_TX_L

TRUE

LPC_FRAME_L

TRUE

SPIROM_USE_MLB

TRUE

PM_CLKRUN_L

TRUE

LPC_SERIRQ

TRUE

LPC_PWRDWN_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

SMC_RESET_L

TRUE

SMC_ROMBOOT

TRUE

SMC_RX_L

TRUE

SMC_TMS

TRUE

36 68

36 40

36 38 39 40

36 37 68

36

36

15 36

36 37

36 37

36 37

36 37

36

36

36 37

36

14 36 74

14 36 74

36 41

36 41

53

53

13 38 71

13 17 38 75

36 38 39

68 71

68 71

14 38 75

14 38 75

14 38 75

14 38 75

16

38 39

38 39

14 38 75

15 47

13 38 71

15 38

13 38

38 39

38 39 47

38 39 40 47 54

38 39

38 39 47

68 71

68 71

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

38 41 79

38 41 79

36 37

36 40 42

36 62

POWER RAILS

FUNC_TEST

PM_SLP_S3_L

TRUE

PP0V6_S0_DDRVTT

TRUE

PP1V05_S0

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE

GND

PP3V3_S0

PP3V3_S3
PP3V3_S5

PP3V3_S5_AVREF_SMC
PP3V42_G3H
PP5V_S0
PP5V_S3
PP5V_S5
PPBUS_G3H
PPDCIN_G3H

PPVCC_S0_CPU

PPVTTDDR_S3

TBTBPWRSW_ISET_V3P3

TBTBPWRSW_ISET_S0_R
TBTBPWRSW_ISET_S3

TBTAPWRSW_ISET_V3P3
TBTAPWRSW_ISET_S0

TBTAPWRSW_ISET_S3

TBTAPWRSW_ISET_S3_R

TBT_A_R2D_C_P<1..0>
TBT_A_R2D_C_N<1..0>
TBT_A_R2D_P<1..0>
TBT_A_R2D_N<1..0>

TBT_A_D2R_C_P<1>
TBT_A_D2R_C_N<1>
TBT_A_D2R_C_P<0>
TBT_A_D2R_C_N<0>

TBT_A_D2R_P<1>
TBT_A_D2R_N<1>
TBT_A_D2R_P<0>
TBT_A_D2R_N<0>

TBT_B_R2D_C_P<1..0>
TBT_B_R2D_C_N<1..0>
TBT_B_R2D_P<1..0>
TBT_B_R2D_N<1..0>
TBT_B_D2R_C_P<0>
TBT_B_D2R_C_N<0>
TBT_B_D2R_C_P<1>
TBT_B_D2R_C_N<1>

TBT_B_D2R_P<0>
TBT_B_D2R_N<0>
TBT_B_D2R_P<1>
TBT_B_D2R_N<1>

PCIE_AP_D2R_P

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_AP_R2D_N

TRUE

ICT Test Points

13 17 18 38 64 66

68 76

68

NC_AUD_LO1_LN
NC_AUD_LO1_LP
NC_AUD_LO1_RN
NC_AUD_LO1_RP
NC_AUD_LO4_LN
NC_AUD_LO4_LP
NC_AUD_LO4_RN

4 TPs

68 80 49

68

68 80

38 39

68 71

68 71

68 71

68

68

68

68

68 71 76

TP_PM_SLP_A_L

13

TRUE

MAKE_BASE=TRUE

NC_PM_SLP_A_L

NC_AUD_LO4_RP
NC_CS4208_GPO0
NC_CS4208_GPO1
NC_CS4208_LRCLKA
NC_CS4208_LRCLKB
NC_CS4208_MCLKA
NC_CS4208_MCLKB
NC_CS4208_SCLKA
NC_CS4208_SCLKB
NC_CS4208_SDOUTA
NC_CS4208_SDOUTB
NC_DMIC_CLK0
NC_DMIC_CLK1
NC_DMIC_CLK2

NO_TESTs

NC_SMC_HIB_L
NC_SMC_XOSC1

29

TRUE

29

TRUE

29

TRUE

28

TRUE

28

TRUE

28

TRUE

28

TRUE

25 28 77

TRUE

25 28 77

TRUE

28 77

TRUE

28 77

TRUE

28 77

TRUE

28 77

TRUE

28 77

TRUE

28 77

TRUE

25 28 77

TRUE

25 28 77

TRUE

25 28 77

TRUE

25 28 77

TRUE

25 29 77

TRUE

25 29 77

TRUE

29 77

TRUE

29 77

TRUE

29 77

TRUE

29 77

TRUE

29 77

TRUE

29 77

TRUE

25 29 77

TRUE

25 29 77

TRUE

25 29 77

TRUE

25 29 77

TRUE

14 66 71 81

14 66 71 81

66 81

66 81

TP_1V05_S0_PCH_VCCAPLLEXP

TP_AUD_CODEC_MICBIAS
TP_AUD_MIC_INRP

TP_AUD_MIC_INRN

MEM_A_DQ<63..0>

PPVTTDDR_S3

MEM_B_DQ<63..0>

HDMI_IG_CLK_C_P
HDMI_IG_CLK_C_N

HDMI_IG_DATA_C_P<2..0>
HDMI_IG_DATA_C_N<2..0>

TP_XDP_PCH_HOOK4

TP_XDP_PCH_HOOK5
TP_XDP_PCH_OBSFN_B<0>
TP_XDP_PCH_OBSFN_B<1>
TP_XDP_PCH_OBSFN_A<0>
TP_XDP_PCH_OBSFN_A<1>
TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>
TP_XDP_PCH_TRST_L

7

70 76

TRUE

68 71 76

TRUE

7

70 76

TRUE

66 67 77

TRUE

66 67 77

TRUE

66 67 77

TRUE

66 67 77

TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_1V05_S0_PCH_VCCAPLLEXP

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_XDP_PCH_HOOK4
NC_XDP_PCH_HOOK5
NC_XDP_PCH_OBSFN_B<0>
NC_XDP_PCH_OBSFN_B<1>
NC_XDP_PCH_OBSFN_A<0>
NC_XDP_PCH_OBSFN_A<1>
NC_XDP_PCH_OBSFN_D<0>
NC_XDP_PCH_OBSFN_D<1>
NC_XDP_PCH_TRST_L

NC_AUD_CODEC_MICBIAS

NC_AUD_MIC_INRP
NC_AUD_MIC_INRN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE

NC NO_TEST

48

48

48

48

48

48

48

48

49

49

49

49

49

49

49

49

49

49

49

49

38

38

High Speed NO_TEST

PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N

PCIE_SSD_R2D_C_P<3..0>
PCIE_SSD_R2D_C_N<3..0>

PCIE_SSD_R2D_P<3..0>
PCIE_SSD_R2D_N<3..0>

PCIE_SSD_D2R_P<3..0>
PCIE_SSD_D2R_N<3..0>

PCIE_TBT_R2D_C_P<3..0>
PCIE_TBT_R2D_C_N<3..0>
PCIE_TBT_R2D_P<3..0>
PCIE_TBT_R2D_N<3..0>
PCIE_TBT_D2R_P<3..1>
PCIE_TBT_D2R_N<3..1>
PCIE_TBT_D2R_C_P<3..1>
PCIE_TBT_D2R_C_N<3..1>

USB3_EXTA_D2R_P
USB3_EXTA_D2R_N

USB3_EXTA_R2D_C_P

USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_N

USB3_EXTA_R2D_N

USB3_EXTB_D2R_P
USB3_EXTB_D2R_N

USB3_EXTB_R2D_C_P
USB3_EXTB_R2D_C_N

PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N

PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N

PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_CAMERA_P
PCIE_CLK100M_CAMERA_N

Unused nets with offpage

(Nets with offpages not used on this project)

PAGE TITLE

Functional & ICT Test

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

HDD_PWR_EN
WOL_EN
BT_PWRRST_L

ENET_MEDIA_SENSE

ODD_PWR_EN_L
ENET_LOW_PWR
AUD_IP_PERIPHERAL_DET

AUD_IPHS_SWITCH_EN
ENETSD_CLKREQ_L

6 3

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE
TRUE
TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

12

14 66 81

14 66 81

14 66 71 81

14 66 71 81

12 32 81

12 32 81

32 81

32 81

12 32 71 81

12 32 71 81

14 25 81

TRUE

14 25 81

TRUE

25 81

TRUE

25 81

TRUE

14 25 81

TRUE

14 25 81

TRUE

25 81

TRUE

25 81

TRUE

14 35 74

14 35 74

14 35 74

14 35 74

35 71 74

35 71 74

14 66 74

14 66 74

14 66 74

14 66 74

12 32 81

12 32 81

12 25 71 81

12 25 71 81

12 66 81

12 66 81

12 34 81

12 34 81

15

14

15

15

13

13

13

13

12

SYNC_DATE=12/06/2013SYNC_MASTER=GKOO_J52

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

104 OF 120

SHEET

71 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

X304 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT

ALLOW ROUTE
ON LAYER?

*

STANDARD =DEFAULT =DEFAULT

D

50_OHM_SE

LAYER

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

*

LAYER

45_OHM_SE

TOP,BOTTOM

45_OHM_SE =STANDARD =STANDARD=STANDARD

LAYER

40_OHM_SE

TOP,BOTTOM

40_OHM_SE

LAYER

37_OHM_SE

TOP,BOTTOM

37_OHM_SE =STANDARD

LAYER

27P4_OHM_SE

TOP,BOTTOM

27P4_OHM_SE

C

LAYER

72_OHM_DIFF
72_OHM_DIFF
72_OHM_DIFF
72_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

* Y

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

80_OHM_DIFF
80_OHM_DIFF
80_OHM_DIFF
80_OHM_DIFF

85_OHM_DIFF
85_OHM_DIFF
85_OHM_DIFF
85_OHM_DIFF

B

90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

*

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

*

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

70_OHM_DIFF
70_OHM_DIFF
70_OHM_DIFF
70_OHM_DIFF

73_OHM_DIFF
73_OHM_DIFF
73_OHM_DIFF
73_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

* N

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

=45_OHM_SE =45_OHM_SE

Y
Y*

MINIMUM LINE WIDTH

Y
Y

Y
Y

0.066 MM

MINIMUM LINE WIDTH

0.116 MM

0.083 MM

MINIMUM LINE WIDTH

Y
Y

MINIMUM LINE WIDTH

Y

0.165 MM

0.118 MM

MINIMUM LINE WIDTH

Y
Y

N
Y
Y

0.265 MM 0.095 MM

0.190 MM

MINIMUM LINE WIDTH

=STANDARD

0.105 MM

0.105 MM 0.105 MM

Y

MINIMUM LINE WIDTH

N*
Y
Y
Y

=STANDARD =STANDARD =STANDARD=STANDARD

0.092 MM

0.092 MM 0.120 MM 0.120 MM

0.125 MM

MINIMUM LINE WIDTH

N
Y
Y

0.080 MM 0.080 MM

Y

MINIMUM LINE WIDTH

N

=STANDARD
Y
Y
Y

N*

0.101 MM 0.101 MM

MINIMUM LINE WIDTH

=STANDARD =STANDARD
Y
Y
Y

0.155 MM

MINIMUM LINE WIDTH

Y
Y
Y

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

=STANDARD

MINIMUM NECK WIDTH

=STANDARD

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

=STANDARD =STANDARD

MINIMUM NECK WIDTH

=STANDARD =STANDARD =STANDARD

MINIMUM NECK WIDTH

=STANDARD=STANDARD =STANDARD

NO_TYPE,BGA,P65BGA,BGA_MEM

0.095 MM0.095 MM

0.066 MM

0.116 MM

0.083 MM

0.095 MM0.145 MM

0.090 MM0.102 MM

0.095 MM

0.090 MM

0.090 MM

0.105 MM

0.092 MM

0.092 MM

0.125 MM 0.155 MM 0.155 MM

0.080 MM0.080 MM

0.105 MM 0.125 MM0.105 MM

0.078 MM0.078 MM

0.120 MM0.120 MM 0.125 MM

0.110 MM

BOARD AREAS

MAXIMUM NECK LENGTH

10 MM
10 MM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD =STANDARD

MAXIMUM NECK LENGTH

=STANDARD =STANDARD=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

A

1TO1_DIFFPAIR

LAYER

* Y

LAYER

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

Y*

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.071MM 0.071MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

BOARD UNITS
(MIL or MM)

MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0 MM

=DEFAULT=DEFAULT

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD=STANDARD50_OHM_SE

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD

0.120 MM 0.120 MM

0.120 MM

0.120 MM

DIFFPAIR PRIMARY GAP

0.120 MM

0.120 MM0.146 MM 0.146 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.120 MM0.120 MM

DIFFPAIR PRIMARY GAP

=STANDARD

0.120 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

0.120 MM

0.120 MM 0.120 MM

0.125 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

0.200 MM

0.200 MM0.078 MM0.078 MM

0.180 MM

DIFFPAIR PRIMARY GAP

0.200 MM

0.200 MM

0.180 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.125 MM

0.125 MM0.120 MM 0.120 MM

0.125 MM

0.125 MM0.155 MM 0.125 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

0.120 MM

0.120 MM

0.120 MM0.110 MM0.110 MM

0.120 MM0.110 MM

0.120 MM0.141 MM0.141 MM 0.120 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.075MM 0.126MMP65_BGA

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.1 MM=STANDARD=STANDARD=STANDARD

6 3

0 MM

0.1 MM

ALLEGRO
VERSION

16.5

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

D

P072_SPACE
P075_SPACE

WEIGHT

?*
?*
?*

WEIGHT

?

WEIGHT

?
?
?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

PCB Rule Definitions

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/14/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

110 OF 120

SHEET

72 OF 82

SIZE

C

B

A

D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

*
*

SPACING_RULE_SET

*
*

LAYER

DEFAULT

STANDARD
P072_SPACE
P075_SPACE

* ?

AREA_TYPE

BGA

P65BGA

LINE-TO-LINE SPACING

0.1 MM

=DEFAULT

0.071 MM

0.075 MM

Stackup-Defined Spacing Rules

Note: Outer dielectric is 0.058 mm nominal,
Inner dielectric is 0.053 mm nominal.

LINE-TO-LINE SPACING

SPACING_RULE_SET

1:1_SPACING

SPACING_RULE_SET

1x_DIELECTRIC
1x_DIELECTRIC
1X_DIELECTRIC

NET_PHYSICAL_TYPE

*

LAYER

*

LAYER

TOP,BOTTOM

ISL3,ISL4,ISL9,ISL10

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

AREA_TYPE

P65BGA

0.1 MM

LINE-TO-LINE SPACING

0.058 MM

0.053 MM

0.101 MM

P65_BGA

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

SPACING_RULE_SET

124578

8 7 6 5 4 3

12

CPU Signal Constraints

*
*

*

ALLOW ROUTE
ON LAYER?

=45_OHM_SE

=27P4_OHM_SE

LINE-TO-LINE SPACING

D

CPU_45S

CPU_27P4S

SPACING_RULE_SET

CPU_VCCSENSE

LAYER

LAYER

C

25 MIL

MINIMUM LINE WIDTH

=45_OHM_SE

=27P4_OHM_SE

WEIGHT

?

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD

=27P4_OHM_SE=27P4_OHM_SE

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

CPU_08MIL

LAYER

CPU_12MIL
CPU_18MIL
CPU_25MIL

LINE-TO-LINE SPACING

0.203 MM
* ?
* ?
* ?

0.305 MM

0.457 MM

0.635 MM

WEIGHT

TABLE_SPACING_RULE_HEAD

?*

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

CPU Signal Properties

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

7 MIL7 MIL

ELECTRICAL CONST SET

XDP_TCK0
XDP_TCK0
XDP_TCK1
XDP_TDO
XDP_TDO
XDP_TDI
XDP_TDI
XDP_TMS CPU_45S
XDP_TMS
XDP_TRST_L
XDP_TRST_L
XDP_PRDY_L
XDP_PREQ_L

CPU_VCCST_PWRGD
CPU_VCCST_PWRGD

CPU_BPM_TP

CPU_RCOMP_SM
CPU_RCOMP_EDP
CPU_RCOMP_OPI

CPU_PROCHOT
CPU_PROCHOT
CPU_CATERR

CPU_VIDALERT
CPU_VIDALERT
CPU_VIDSCLK
CPU_VIDSCLK
CPU_VIDSOUT
CPU_VIDSOUT
CPU_PECI
CPU_PECI
CPU_PECI
CPU_PECI

PHYSICAL

CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S

CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S

CPU_45S
CPU_45S
CPU_45SCPU_BPM
CPU_45S

CPU_27P4S
CPU_27P4S
CPU_27P4S

CPU_45S
CPU_45S
CPU_45S

CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S

NET TYPE

SPACING

CPU_18MIL
CPU_18MIL
CPU_18MIL

CPU_08MIL
CPU_08MIL
CPU_08MIL

CPU_25MIL
CPU_25MIL
CPU_12MIL

CPU_08MIL
CPU_08MIL
CPU_08MIL

CPU_18MIL
CPU_18MIL
CPU_18MIL
CPU_18MIL
CPU_18MIL
CPU_18MIL
CPU_18MIL
CPU_18MIL
CPU_18MIL
CPU_18MIL

XDP_CPU_TCK
PCH_JTAGX
XDP_PCH_TCK
XDP_CPU_TDO
XDP_PCH_TDO
XDP_CPU_TDI
XDP_PCH_TDI
XDP_CPU_TMS
XDP_PCH_TMS
XDP_TRST_L
XDP_CPUPCH_TRST_L
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

CPU_VCCST_PWRGD
XDP_CPU_VCCST_PWRGD
XDP_BPM_L<1..0>
XDP_BPM_L<7..2>

CPU_SM_RCOMP<2..0>
MCP_EDP_RCOMP
CPU_OPI_RCOMP

CPU_PROCHOT_L
CPU_PROCHOT_R_L
CPU_CATERR_L

CPU_VIDALERT_L
CPU_VIDALERT_R_L
CPU_VIDSCLK
CPU_VIDSCLK_R
CPU_VIDSOUT
CPU_VIDSOUT_R
CPU_PECI
CPU_PECI_R
SMC_PECI_L
SMC_PECI_L_R

6

16

12 16

12 16

6

16

12 16

6

16

12 16

6

16

12 16

16

16

6

16

6

16

8

16 17

16

6

16

6

16

6

5

6

6

38 39 55

6

6

38

8

55

8

8

55

8

8

55

8

6

39

38 39

38 39

39

D

C

CPU_CFG_PD
CPU_CFG CPU_45S
CPU_CFG_PD
CPU_CFG_3
CPU_CFG CPU_45S
CPU_CFG_PD

B

CPU_MEM_RESET

CPU_VCCSENSE CPU_VCCSENSE
CPU_VCCSENSE

CPU_45SCPU_CFG
CPU_45S

CPU_45S
CPU_45S

CPU_45S

CPU_45S

CPU_27P4S
CPU_27P4S

CPU_08MIL

CPU_VCCSENSE

A

6 3

CPU_CFG<19..11>
CPU_CFG<10..8>
CPU_CFG<7..5>
CPU_CFG<4>
CPU_CFG<3>
CPU_CFG<2>
CPU_CFG<1..0>

MEM_RESET_L

CPU_VCCSENSE_P
CPU_VCCSENSE_N

6

16

6

16

6

16

6

16

6

16

6

16

6

16

B

8

55

9

55

SIZE

A

D

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

CPU Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/13/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

111 OF 120

SHEET

73 OF 82

124578

8 7 6 5 4 3

12

USB 2 Interface Constraints

D

PCH_USB_RBIAS

USB_85D

SPACING_RULE_SET

USB

USB_RBIAS

LAYER

LAYER

ALLOW ROUTE
ON LAYER?

*

=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD=STANDARD

*

=85_OHM_DIFF

LINE-TO-LINE SPACING

=4X_DIELECTRIC

*

=6X_DIELECTRIC

*

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

USB 3 Interface Constraints

USB3_85D

SPACING_RULE_SET

USB3_2SAME

USB3_TXRX

USB3_2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

USB3_*

C

USB3_*
USB3_TX
USB3_RX

*

*
*
*

ALLOW ROUTE
ON LAYER?

=85_OHM_DIFF

LINE-TO-LINE SPACING

=3X_DIELECTRIC
=6X_DIELECTRIC
=4X_DIELECTRIC

LAYER

LAYER

=SAME USB3_2SAME

*_RX
*_TX

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

AREA_TYPE

**
*
*
*

System Clock Signal Constraints

CLK_25M_45S

SPACING_RULE_SET

CLK_25M

LAYER

LAYER

*

*

ALLOW ROUTE
ON LAYER?

=45_OHM_SE

LINE-TO-LINE SPACING

=5x_DIELECTRIC

MINIMUM LINE WIDTH

=45_OHM_SE

B

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_TXRX

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_TXRX

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

SPACING_RULE_SET

USB

MAXIMUM NECK LENGTH

TOP,BOTTOM

USB_RBIAS

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=85_OHM_DIFF

SPACING_RULE_SET

USB3_2SAME TOP,BOTTOM

USB3_TXRX

USB3_2OTHER

MINIMUM NECK WIDTH

TOP,BOTTOM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

LAYER

=6X_DIELECTRIC

=10X_DIELECTRICTOP,BOTTOM

DIFFPAIR PRIMARY GAP

LAYER

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=10X_DIELECTRICTOP,BOTTOM

=6X_DIELECTRIC

DIFFPAIR PRIMARY GAP

=45_OHM_SE=45_OHM_SE

=STANDARD

WEIGHT

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL CONST SET

USB_BT
USB_BT
USB_BT
USB_BT

USB_EXTA
USB_EXTA

USB_EXTA
USB_EXTA
USB_EXTA
USB_EXTA
USB_EXTA
USB_EXTA
USB_EXTB
USB_EXTB
USB_TPAD

I331

USB_TPAD

I330

USB3_EXTA_D2R
USB3_EXTA_D2R
USB3_EXTA_R2D
USB3_EXTA_R2D
USB3_EXTA_R2D
USB3_EXTA_R2D
USB3_EXTB_D2R
USB3_EXTB_D2R
USB3_EXTB_R2D
USB3_EXTB_R2D

USB3_SD_D2R
USB3_SD_D2R
USB3_SD_R2D
USB3_SD_R2D

USB_NC
USB_NC
USB_NC
USB_NC
USB_NC
USB_NC
USB_NC
USB_NC

NET TYPE

PHYSICAL

USB_85D
USB_85D
USB_85D
USB_85D

USB_85D
USB_85D

USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D

USB_85D USB3_RX

USB_85D USB3_RX
USB_85D USB3_RX
USB_85D
USB_85D

USB3_85D
USB3_85D
USB3_85D
USB3_85D

USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D

SPACING

USB
USB
USB
USB

USB
USB
DEFAULTDEFAULT
DEFAULTDEFAULT
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB

USB3_RXUSB_85D

USB3_TXUSB_85D
USB3_TXUSB_85D
USB3_TXUSB_85D
USB3_TXUSB_85D

USB3_TX
USB3_TX

USB3_RX
USB3_RX
USB3_TX
USB3_TX

USB
USB
USB
USB
USB
USB
USB
USB

USB_BT_P
USB_BT_N
USB_BT_CONN_P
USB_BT_CONN_N

USB_EXTA_P
USB_EXTA_N
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N
USB2_EXTA_MUXED_F_P
USB2_EXTA_MUXED_F_N
USB_LT1_P
USB_LT1_N
USB_EXTB_P
USB_EXTB_N
USB_TPAD_P
USB_TPAD_N

USB3_EXTA_D2R_P
USB3_EXTA_D2R_N
USB3_EXTA_R2D_P
USB3_EXTA_R2D_N
USB3_EXTA_R2D_C_P
USB3_EXTA_R2D_C_N
USB3_EXTB_D2R_P
USB3_EXTB_D2R_N
USB3_EXTB_R2D_C_P
USB3_EXTB_R2D_C_N

USB3RPCIE_SD_D2R_P
USB3RPCIE_SD_D2R_N
USB3RPCIE_SD_R2D_C_P
USB3RPCIE_SD_R2D_C_N

NC_USB_IRP
NC_USB_IRN
NC_USB_5P
NC_USB_5N
NC_USB_SDP
NC_USB_SDN
NC_USB_CAMERAP
NC_USB_CAMERAN

14 31

14 31

31 66

31 66

14 35

14 35

35 38 39

35 38 39

35

35

35

35

71

71

14 66

14 66

14 36 71

14 36 71

14 35 71

14 35 71

35

35 71

14 35 71

14 35 71

14 66 71

14 66 71

14 66 71

14 66 71

14 66 71

14 66 71

14 66

14 66

69

69

69

69

69

69

69

69

D

C

B

USB Constraints

SATA Interface Constraints (Not Used)

SATA_85D

SATA_45SE

SPACING_RULE_SET

SATA_2SAME

SATA_TXRX

SATA_2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

SATA_*

A

SATA_*
SATA_TX
SATA_RX

LAYER

LAYER

ALLOW ROUTE
ON LAYER?

*

=85_OHM_DIFF

*

=45_OHM_SE

LINE-TO-LINE SPACING

* ?

=3X_DIELECTRIC

* ?

=6X_DIELECTRIC

* ?

=4X_DIELECTRIC

=SAME

*_RX
*_TX

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=45_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

**
*
*
*

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SATA_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

SATA_2SAME

TABLE_SPACING_ASSIGNMENT_ITEM

SATA_TXRX

TABLE_SPACING_ASSIGNMENT_ITEM

SATA_TXRX

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE

SPACING_RULE_SET

LAYER

SATA_2SAME TOP,BOTTOM

SATA_TXRX

SATA_2OTHER

TOP,BOTTOM=10X_DIELECTRIC
TOP,BOTTOM

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=6X_DIELECTRIC

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

6 3

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PCH_USB_RBIAS

SYSCLK_CLK25M
SYSCLK_CLK25M
SYSCLK_CLK25M

SYSCLK_CLK25M_CAM
SYSCLK_CLK25M_CAM
SYSCLK_CLK25M_CAM
SYSCLK_CLK25M_CAM
SYSCLK_CLK25M_CAM
SYSCLK_CLK25M_CAM

SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_TBT

PCH_USB_RBIAS

SATA_85D
SATA_85D
SATA_85D
SATA_85D

CLK_25M_45S
CLK_25M_45S
CLK_25M_45S

CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S

CLK_25M_45S
CLK_25M_45S

USB_RBIAS

SATA_RX
SATA_RX
SATA_TX
SATA_TX

CLK_25M
CLK_25M
CLK_25M

CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M

CLK_25M
CLK_25M

PCH_USB_RBIAS

DUMMY_SATA_D2R_P
DUMMY_SATA_D2R_N
DUMMY_SATA_R2D_P
DUMMY_SATA_R2D_N

SYSCLK_CLK25M_X1
SYSCLK_CLK25M_X2
SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_CAMERA
CLK25M_CAM_CLKP
CLK25M_CAM_XTALP_R
CLK25M_CAM_XTALP
CLK25M_CAM_XTALN
CLK25M_CAM_CLKN

SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_TBT_R

14

17

17

17

17 34

33 34

34

34

34

33 34

17 25

25

Notes:
This is here to keep the SATA rules.

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

USB Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/07/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

112 OF 120

SHEET

74 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

LPC Bus Constraints

LAYER

LPC_45S

CLK_LPC_45S

SPACING_RULE_SET

LAYER

LPC

CLK_LPC

D

SMBus Interface Constraints

LAYER

SMB_45S

SPACING_RULE_SET

LAYER

SMB

HD Audio Interface Constraints

LAYER

HDA_45S

SPACING_RULE_SET

LAYER

HDA

SPI Interface Constraints

LAYER

SPI_45S

C

SPACING_RULE_SET

LAYER

SPI

PCH Single Net Constraints

LAYER

PCH_45S

PCH_27P4S

SPACING_RULE_SET

PCH_12MIL
PCH_15MIL
PCH_18MIL
PCH_20MIL

LAYER

*
*

*
*

*

ALLOW ROUTE
ON LAYER?

=45_OHM_SE
=45_OHM_SE

LINE-TO-LINE SPACING

ALLOW ROUTE
ON LAYER?

=45_OHM_SE

LINE-TO-LINE SPACING

MINIMUM LINE WIDTH

=45_OHM_SE =45_OHM_SE

6 MIL
8 MIL

MINIMUM LINE WIDTH

=45_OHM_SE =45_OHM_SE

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

*

=45_OHM_SE

LINE-TO-LINE SPACING

*

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

*

=45_OHM_SE

LINE-TO-LINE SPACING

* ?

ALLOW ROUTE
ON LAYER?

*

=45_OHM_SE

*

=27P4_OHM_SE

LINE-TO-LINE SPACING

* ?

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

=45_OHM_SE

8 MIL

MINIMUM LINE WIDTH

=45_OHM_SE =45_OHM_SE

=27P4_OHM_SE

0.305 MM

0.381 MM

0.457 MM

* ?

0.508 MM

B

A

WEIGHT

?
?

WEIGHT

?*

WEIGHT

WEIGHT

WEIGHT

?*
?*

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=45_OHM_SE
=45_OHM_SE

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

=45_OHM_SE=45_OHM_SE

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

=27P4_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE=45_OHM_SE

MAXIMUM NECK LENGTH

=45_OHM_SE

=27P4_OHM_SE

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD
=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

7 MIL

6 3

7 MIL

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PCH Net Properties

ELECTRICAL CONST SET

LPC_AD
LPC_AD
LPC_CLK24M_SMC CLK_LPC

SMBUS_PCH
SMBUS_PCH
SML_PCH_0
SML_PCH_0

HDA_BIT_CLK
HDA_BIT_CLK
HDA_SYNC
HDA_SYNC
HDA_RST
HDA_RST
HDA_SDIN
HDA_SDIN
HDA_SDOUT
HDA_SDOUT

SPI_MLB
SPI_MLB SPI_45S
SPI_MLB
SPI_MLB SPI_45S

SPI_MLB
SPI_MLB
SPI_MLB
SPI_MLB
SPI_MLB

SPI_MLB

SPI_MLB
SPI_MLB SPI_45S

SPI_MLB SPI_45S

SPI_MLB
SPI_MLB

SPI_MLB_IO2
SPI_MLB_IO2

I387

SPI_MLB_IO2
SPI_MLB_IO2

I381

SPI_MLB_IO3
SPI_MLB_IO3

I388

SPI_MLB_IO3
SPI_MLB_IO3

I382

SPI_TPAD

I386

SPI_TPAD_CS

I385

SPI_TPAD

I384

SPI_TPAD

I383

PCH_RTCX
PCH_SRTCRST
PCH_RTCRST

PCH_THRMTRIP
PCH_THRMTRIP

PCH_CLK24M_XTAL
PCH_CLK24M_XTAL
PCH_CLK24M_XTAL

PCH_RCOMP_PCIE
PCH_RCOMP_OPI
PCH_RCOMP_SATA

PHYSICAL

LPC_45S
LPC_45S
CLK_LPC_45S
CLK_LPC_45S

SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S

HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S

SPI_45S

SPI_45S

SPI_45SSPI_MLB

SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S

SPI_45S
SPI_45SSPI_MLB
SPI_45S

SPI_45SSPI_MLB

SPI_45SSPI_MLB

SPI_45SSPI_MLB
SPI_45S
SPI_45S

SPI_45S
SPI_45S
SPI_45S
SPI_45S

SPI_45S
SPI_45S
SPI_45S
SPI_45S

SPI_45S
SPI_45S
SPI_45S
SPI_45S

PCH_45S
PCH_45S
PCH_45S

PCH_45S
PCH_45S

PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S

PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S

PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_45S

PCH_45S
PCH_45S
PCH_45S

NET TYPE

SPACING

LPC
LPC

CLK_LPCLPC_CLK24M_SMC

SMB
SMB
SMB
SMB
SMB
SMB

HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA

SPI
SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI

PCH_15MIL
PCH_15MIL
PCH_15MIL

PCH_18MIL
PCH_18MIL

PCH_15MIL
PCH_15MIL
PCH_15MIL
PCH_15MIL
PCH_15MIL
PCH_15MIL

PCH_15MIL
PCH_15MIL
PCH_15MIL
PCH_15MIL
PCH_15MIL
PCH_15MIL
PCH_15MIL

PCH_15MIL
PCH_15MIL
PCH_15MIL
PCH_15MIL
PCH_15MIL
PCH_15MIL

PCH_20MIL
PCH_20MIL
PCH_20MIL

PCH_12MILPCH_27P4S
PCH_12MILPCH_27P4S
PCH_12MILPCH_27P4S

LPC_AD<3..0>
LPC_FRAME_L
LPC_CLK24M_SMC_R
LPC_CLK24M_SMC

SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA

HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
CS4208_HDA_SDOUT0_R
HDA_SDOUT
HDA_SDOUT_R

SPI_ALT_CLK
SPI_CLK
SPI_CLK_R
SPI_MLB_CLK
SPI_SMC_CLK

SPI_ALT_CS_L
SPI_CS0_L
SPI_CS0_R_L
SPI_MLB_CS_L
SPI_SMC_CS_L

SPI_ALT_IO1_MISO
SPI_MISO
SPI_MISO_R
SPI_MLB_IO1_MISO
SPI_SMC_MISO

SPI_ALT_IO0_MOSI
SPI_MOSI
SPI_MOSI_R
SPI_MLB_IO0_MOSI
SPI_SMC_MOSI

SPI_IO<2>
SPI_IO2_R
SPI_MLB_IO2_WP_L
SPI_ALT_IO2_WP_L

SPI_IO<3>
SPI_IO3_R
SPI_MLB_IO3_HOLD_L
SPI_ALT_IO3_HOLD_L

TPAD_SPI_CLK
TPAD_SPI_CS_L
TPAD_SPI_MISO
TPAD_SPI_MOSI

PCH_CLK32K_RTCX1
PCH_SRTCRST_L
RTC_RESET_L

PM_THRMTRIP_L
PM_THRMTRIP_R_L

PCH_INTRUDER_L
PCH_INTVRMEN
PCH_DSWVRMEN
PM_RSMRST_L
PM_SYSRST_L
XDP_DBRESET_L

PM_PCH_SYS_PWROK
XDP_SYS_PWROK
SYS_PWROK_R
PM_PCH_PWROK
PM_S0_PGOOD
SMC_DELAYED_PWRGD
PM_DSW_PWRGD

PM_PWRBTN_L
XDP_CPU_PWRBTN_L
PCIE_WAKE_L
AP_PCIE_WAKE_L
CAM_PCIE_WAKE_L
TBT_CIO_PLUG_EVENT_L

PCH_CLK24M_XTALIN
PCH_CLK24M_XTALOUT
PCH_CLK24M_XTALOUT_R

PCH_PCIE_RCOMP
PCH_OPI_COMP
PCH_SATA_RCOMP

14 38 71

14 38 71

12 17

17 71

14 41 71

14 41 71

14 41

14 41

14 41

14 41

12 49

12

12 49

12

12

12 49

12 49 71

49

12 49

12 17

47

47

14 47

47

38 47

47

47

14 47

47

38 47

47

14 47

47

47

38 47

47

47

14 47

47

38 47

14 47

47

47

47

14 47

47

47

47

15 37

15 37

15 37

15 37

12 17

12

12

15 39

39

12

12

13

13 64

13 17 38 71

16 17

13 16 17 38

16

17

13 17

17

17 26 27 38 39

13 38

13 16 38

16

13 31 33

31 66

33

18 25

12 17

12 17

17

14

15

12

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

PCH Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

SYNC_DATE=01/08/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

113 OF 120

SHEET

75 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Memory Bus Constraints

LAYER

MEM_40S
MEM_50S
MEM_70D
MEM_73D

ALLOW ROUTE
ON LAYER?

=40_OHM_SE

*

=50_OHM_SE

*

=70_OHM_DIFF

*
*

=73_OHM_DIFF

Spacing Rule Sets

D

SPACING_RULE_SET

LAYER

MEM_DATA2SELF

MEM_DQS2OWNDATA

MEM_CMD2CMD
MEM_CMD2CTL
MEM_CTL2CTL
MEM_CLK2CLK

MEM_DATA2OTHERMEM

MEM_2OTHERMEM

MEM_2PWR
MEM_2GND

MEM_2OTHER

MEM_CTL2CTL_BM

MEM_12MIL

C

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DQBYTE_*

MEM_*_DQS_*

MEM_CMD
MEM_CTL
MEM_CLK

MEM_*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DQBYTE_*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DQBYTE_*

NET_SPACING_TYPE1 NET_SPACING_TYPE2

B

MEM_CLK MEM_CLK

LINE-TO-LINE SPACING

=2x_DIELECTRIC
=3x_DIELECTRIC

*
* ?

=3x_DIELECTRIC
=3x_DIELECTRIC

* ?

=3x_DIELECTRIC

*

=6x_DIELECTRIC

* ?
* ?

=8x_DIELECTRIC
=4x_DIELECTRIC

*
* ?

=2x_DIELECTRIC
=2x_DIELECTRIC

* ?

=6x_DIELECTRIC

* ?

=3x_DIELECTRICMEM_CMD2CMD_BM
=3x_DIELECTRICMEM_CMD2CTL_BM

* ?

=3x_DIELECTRIC

*

MEM_*

=SAME

MEM_*

MEM_CMDMEM_CMD
MEM_CTLMEM_CMD
MEM_CTLMEM_CTL

MEM_CMD BGA_MEMMEM_CMD MEM_CMD2CMD_BM

MINIMUM LINE WIDTH

=70_OHM_DIFF

WEIGHT

0.305 MM

AREA_TYPE

AREA_TYPE

AREA_TYPE

AREA_TYPE

**
**
**
**
**
*

*

*

*
*
*
*

SPACING_RULE_SET

MEM_2OTHER
MEM_2OTHER
MEM_2OTHER
MEM_2OTHER
MEM_2OTHER

MEM_2OTHERMEM

SPACING_RULE_SET

MEM_DATA2SELF

SPACING_RULE_SET

MEM_DATA2OTHERMEM

SPACING_RULE_SET

MEM_CMD2CMD
MEM_CMD2CTL
MEM_CTL2CTL
MEM_CLK2CLK

MEM_CMD2CTL_BMBGA_MEMMEM_CTLMEM_CMD

BGA_MEMMEM_CTLMEM_CTL MEM_CTL2CTL_BM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=40_OHM_SE
=50_OHM_SE=50_OHM_SE=50_OHM_SE

=70_OHM_DIFF

0.066 MM

SPACING_RULE_SET

MEM_DATA2SELF

MEM_DQS2OWNDATA

MEM_CMD2CMD
MEM_CMD2CTL
MEM_CTL2CTL
MEM_CLK2CLK

MEM_2OTHERMEM

MEM_2PWR
MEM_2GND

MEM_2OTHER TOP,BOTTOM

MEM_CMD2CTL_BM =3x_DIELECTRIC
MEM_CTL2CTL_BM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_A_DQS_0
MEM_A_DQS_1
MEM_A_DQS_2
MEM_A_DQS_3
MEM_A_DQS_4
MEM_A_DQS_5
MEM_A_DQS_6
MEM_A_DQS_7
MEM_B_DQS_0
MEM_B_DQS_1
MEM_B_DQS_2*MEM_B_DQBYTE_2
MEM_B_DQS_3
MEM_B_DQS_4*MEM_B_DQBYTE_4
MEM_B_DQS_5
MEM_B_DQS_6
MEM_B_DQS_7

=70_OHM_DIFF
=73_OHM_DIFF=73_OHM_DIFF

LINE-TO-LINE SPACING

LAYER

TOP,BOTTOM?=5x_DIELECTRIC
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM

TOP,BOTTOM
TOP,BOTTOM

MEM_A_DQBYTE_0
MEM_A_DQBYTE_1
MEM_A_DQBYTE_2
MEM_A_DQBYTE_3
MEM_A_DQBYTE_4
MEM_A_DQBYTE_5
MEM_A_DQBYTE_6
MEM_A_DQBYTE_7
MEM_B_DQBYTE_0
MEM_B_DQBYTE_1

MEM_B_DQBYTE_3

MEM_B_DQBYTE_5
MEM_B_DQBYTE_6
MEM_B_DQBYTE_7

=5x_DIELECTRIC
=5x_DIELECTRIC
=5x_DIELECTRIC
=5x_DIELECTRIC
=8x_DIELECTRIC
=8x_DIELECTRIC
=4x_DIELECTRIC
=4x_DIELECTRIC

=10x_DIELECTRIC

=3x_DIELECTRICMEM_CMD2CMD_BM?TOP,BOTTOM

=3x_DIELECTRIC

Broadwell ULT Memory Down LPDDR3 1x4 Length Matching

LPDDR3 Signal Group Unit Min Length Max Length

CTL/CKEmax - CTL/CKEmin mils 0 50
CTL/CKE to CLK mils CLK - 100 0
(CMDmax - CMDmin) mils 0 50
CMD to CLK mils CLK - 250 CLK + 250
DQmax - DQmin per byte mils 0 125
DQmax to DQs per byte mils DQS - 200 DQS + 50
DQS to DQS# mils -2.5 2.5
DQS to CLK (Rule 1) mils CLK - 750 CLK + 1250
CLK to CLK# mils -2.5 2.5

Memory to Power Spacing

A

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_PWR
MEM_PWR

MEM_*

*

AREA_TYPE

*
*

SPACING_RULE_SET

MEM_2PWR

DEFAULT

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

NET_PHYSICAL_TYPE

AREA_TYPE

BGA_MEM
BGA_MEM

Memory to GND Spacing

MEM_2GND

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GND

MEM_*

AREA_TYPE

*

SPACING_RULE_SET

Memory Net Properties

AREA_TYPE

*
*
*
*
*
*
*
*
*
*

*

*
*
*

PHYSICAL_RULE_SET

MEM_73DMEM_70D
MEM_50SMEM_40S

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE

=50_OHM_SE=50_OHM_SE
=70_OHM_DIFF=70_OHM_DIFF
=73_OHM_DIFF=73_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

SPACING_RULE_SET

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL CONST SET

MEM_A_CLK0
MEM_A_CLK0
MEM_A_CLK1
MEM_A_CLK1
MEM_A_CTL
MEM_A_CTL
MEM_A_CKE0
MEM_A_CKE1
MEM_A_CMD0
MEM_A_CMD1
MEM_A_DQBYTE0
MEM_A_DQBYTE1
MEM_A_DQBYTE2
MEM_A_DQBYTE3
MEM_A_DQBYTE4
MEM_A_DQBYTE5
MEM_A_DQBYTE6
MEM_A_DQBYTE7
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7

MEM_B_CLK0
MEM_B_CLK0
MEM_B_CLK1
MEM_B_CLK1
MEM_B_CTL
MEM_B_CTL
MEM_B_CKE0
MEM_B_CKE1
MEM_B_CMD0
MEM_B_CMD1
MEM_B_DQBYTE0
MEM_B_DQBYTE1
MEM_B_DQBYTE2
MEM_B_DQBYTE3
MEM_B_DQBYTE4
MEM_B_DQBYTE5
MEM_B_DQBYTE6
MEM_B_DQBYTE7
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7

NET TYPE

PHYSICAL

MEM_70D MEM_CLK

MEM_40S MEM_A_DQBYTE_1
MEM_40S MEM_A_DQBYTE_2
MEM_40S MEM_A_DQBYTE_3

MEM_40S MEM_A_DQBYTE_7
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D

MEM_70D
MEM_70D
MEM_70D MEM_CLK

MEM_40S MEM_CTL
MEM_40S MEM_CTL
MEM_40S MEM_CMD
MEM_40S

MEM_40S MEM_CMD
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D

SPACING

MEM_CLKMEM_70D
MEM_CLKMEM_70D
MEM_CLKMEM_70D
MEM_CTLMEM_40S
MEM_CTLMEM_40S
MEM_CMDMEM_40S
MEM_CMDMEM_40S
MEM_CMDMEM_40S
MEM_CMDMEM_40S
MEM_A_DQBYTE_0MEM_40S

MEM_A_DQBYTE_4MEM_40S
MEM_A_DQBYTE_5MEM_40S
MEM_A_DQBYTE_6MEM_40S

MEM_A_DQS_0
MEM_A_DQS_0
MEM_A_DQS_1
MEM_A_DQS_1
MEM_A_DQS_2
MEM_A_DQS_2
MEM_A_DQS_3
MEM_A_DQS_3
MEM_A_DQS_4
MEM_A_DQS_4
MEM_A_DQS_5
MEM_A_DQS_5
MEM_A_DQS_6
MEM_A_DQS_6
MEM_A_DQS_7
MEM_A_DQS_7

MEM_CLK
MEM_CLK

MEM_CLKMEM_70D

MEM_CMD
MEM_CMDMEM_40S

MEM_B_DQBYTE_0
MEM_B_DQBYTE_1
MEM_B_DQBYTE_2
MEM_B_DQBYTE_3
MEM_B_DQBYTE_4
MEM_B_DQBYTE_5
MEM_B_DQBYTE_6
MEM_B_DQBYTE_7
MEM_B_DQS_0
MEM_B_DQS_0
MEM_B_DQS_1
MEM_B_DQS_1
MEM_B_DQS_2
MEM_B_DQS_2
MEM_B_DQS_3
MEM_B_DQS_3
MEM_B_DQS_4
MEM_B_DQS_4
MEM_B_DQS_5
MEM_B_DQS_5
MEM_B_DQS_6
MEM_B_DQS_6
MEM_B_DQS_7
MEM_B_DQS_7

MEM_PWR
MEM_PWR
MEM_PWR
MEM_PWR

MEM_12MIL

MEM_12MIL

MEM_12MIL

MEM_12MIL
MEM_12MIL
MEM_12MIL
MEM_12MIL

6 3

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CS_L<1..0>
MEM_A_ODT<0>
MEM_A_CKE<1..0>
MEM_A_CKE<3..2>
MEM_A_CAA<9..0>
MEM_A_CAB<9..0>
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CS_L<1..0>
MEM_B_ODT<0>
MEM_B_CKE<1..0>
MEM_B_CKE<3..2>
MEM_B_CAA<9..0>
MEM_B_CAB<9..0>
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

PP1V2_S3
PP1V2_S3_CPUDDR
PP0V6_S0_DDRVTT
PPVTTDDR_S3

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

PP0V6_S3_MEM_VREFDQ_A
PP0V6_S3_MEM_VREFDQ_B
PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFCA_B

68

68

68 71

68 71

7

19

7

19

7
19

20 21 68

22 23 68

20 21 68

22 23 68

7

20 24

7

20 24

7

21 24

7

21 24

7

20 21 24

20 21 24 70

7

20 24

7

21 24

20 24 70

21 24 70

7

70 71

7

70 71

7

70 71

7

70 71

7

70 71

7

70 71

7

70 71

7

70 71

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

22 24

7

22 24

7

23 24

7

23 24

7

22 23 24

22 23 24 70

7

22 24

7

23 24

22 24 70

23 24 70

7

70 71

7

70 71

7

70 71

7

70 71

7

70 71

7

70 71

7

70 71

7

70 71

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

7

70

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

Memory Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/02/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

114 OF 120

SHEET

76 OF 82

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

Thunderbolt, DP, HDMI Constraints
Thunderbolt SPI Signal Constraints

LAYER

TBT_SPI_45S

SPACING_RULE_SET

D

TBT_SPI

LAYER

ALLOW ROUTE
ON LAYER?

=45_OHM_SE*=45_OHM_SE =45_OHM_SE =45_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*

Thunderbolt & DisplayPort Constraints

LAYER

TBTDP_85D =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

SPACING_RULE_SET

LAYER

TBTDP_2SAME

TBTDP_TXRX

TBTDP_2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TBTDP_*

TBTDP_*
TBTDP_TX
TBTDP_RX

ALLOW ROUTE
ON LAYER?

*

=85_OHM_DIFF

LINE-TO-LINE SPACING

=3X_DIELECTRIC

*

=6X_DIELECTRIC

*

=4X_DIELECTRIC

*

* *

=SAME

*_RX
*_TX

DisplayPort & HDMI Constraints

C

B

LAYER

DP_85D

HDMI_85D

SPACING_RULE_SET

LAYER

DP_2SAME

DP_2OTHER

HDMICLK_2OTHER

HDMICLK_2DPHDMI

HDMIDATA_2SAME

HDMIDATA_2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

HDMI_DATA
HDMI_DATA
HDMI_DATA
HDMI_DATA

HDMI_CLK
HDMI_CLK
HDMI_CLK

DISPLAYPORT

HDMI_CLK TBTDP_TX

ALLOW ROUTE
ON LAYER?

*

=85_OHM_DIFF

*

=85_OHM_DIFF

LINE-TO-LINE SPACING

*

=3x_DIELECTRIC

*

=4x_DIELECTRIC

*

=7x_DIELECTRIC

* ?

=4x_DIELECTRIC

*

=3x_DIELECTRIC

*

=4x_DIELECTRIC

* *

=SAME
TBTDP_TX
TBTDP_RX

* *

HDMI_DATA

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM LINE WIDTH

WEIGHT

?
?
?

AREA_TYPE

SPACING_RULE_SET

TBTDP_2OTHER

*

TBTDP_2SAME

*

TBTDP_TXRX

*

TBTDP_TXRX

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

WEIGHT

?
?
?

?
?

AREA_TYPE

*
*
*

*
*
*

SPACING_RULE_SET

HDMIDATA_2OTHER

HDMIDATA_2SAME

HDMIDATA_2SAME

TBTDP_TXRX

HDMICLK_2OTHER

HDMICLK_2DPHDMI

HDMICLK_2DPHDMI

HDMICLK_2DPHDMI

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

SPACING_RULE_SET

TBTDP_2SAME

LAYER

TOP,BOTTOM
TOP,BOTTOMTBTDP_TXRX

TBTDP_2OTHER

SPACING_RULE_SET

DP_2SAME

DP_2OTHER

HDMICLK_2OTHER

HDMICLK_2DPHDMI

HDMIDATA_2SAME

HDMIDATA_2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TOP,BOTTOM

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

=SAME

HDMI_DATA

TBTDP_TX
TBTDP_RX

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC

=10X_DIELECTRIC

=6X_DIELECTRIC

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC
=6x_DIELECTRIC

=10x_DIELECTRIC

=6x_DIELECTRIC
=4x_DIELECTRIC
=6x_DIELECTRIC

AREA_TYPE

* *

*
*
*
*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=85_OHM_DIFF
=85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DP_2OTHER

DP_2SAME
DP_2SAME
DP_2SAME

TBTDP_TXRX

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Thunderbolt, DP, HDMI Net Properties

ELECTRICAL CONST SET

TBT_A_R2D
TBT_A_R2D
TBT_A_R2D

DP_A_LSX_ML
DP_A_LSX_ML
DP_A_LSX_ML

DP_A_LSX_ML
DP_A_LSX_ML
DP_TBTPA_ML DISPLAYPORT

I355

DP_TBTPA_ML

I354

DP_TBTPA_ML DISPLAYPORT

I353

DP_TBTPA_ML DISPLAYPORT

I352

TBT_A_D2R_0
TBT_A_D2R_0
TBT_A_D2R_0
TBT_A_D2R_0
TBT_A_D2R_1

I343

TBT_A_D2R_1

I342

TBT_A_D2R_1

I341

TBT_A_D2R_1

I340

TBT_A_D2R_1
TBT_A_D2R_1

DP_TBTPA_AUXCH
DP_TBTPA_AUXCH
DP_TBTPA_AUXCH
DP_TBTPA_AUXCH

TBT_B_R2D
TBT_B_R2D
TBT_B_R2D
TBT_B_R2D TBTDP_85D

DP_B_LSX_ML
DP_B_LSX_ML
DP_B_LSX_ML
DP_B_LSX_ML
DP_B_LSX_ML
DP_B_LSX_ML
DP_TBTPB_ML

I351

DP_TBTPB_ML DISPLAYPORT

I350

DP_TBTPB_ML DISPLAYPORT

I348

DP_TBTPB_ML

I349

TBT_B_D2R_0
TBT_B_D2R_0
TBT_B_D2R_0
TBT_B_D2R_0
TBT_B_D2R_1

I347

TBT_B_D2R_1

I346

TBT_B_D2R_1

I344

TBT_B_D2R_1

I345

TBT_B_D2R_1
TBT_B_D2R_1

DP_TBTPB_AUXCH
DP_TBTPB_AUXCH
DP_TBTPB_AUXCH
DP_TBTPB_AUXCH

PHYSICAL

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85DTBT_A_R2D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D

DP_85D
DP_85D
DP_85D
DP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D

DP_85D
DP_85D
DP_85D
DP_85D

NET TYPE

SPACING

TBTDP_TX
TBTDP_TX
TBTDP_TX
TBTDP_TX

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORTDP_A_LSX_ML
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT

TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX

TBTDP_TX
TBTDP_TX
TBTDP_TX
TBTDP_TX

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT

TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX

TBT_A_R2D_C_P<1..0>
TBT_A_R2D_C_N<1..0>
TBT_A_R2D_P<1..0>
TBT_A_R2D_N<1..0>

DP_TBTPA_ML_C_P<1>
DP_TBTPA_ML_C_N<1>
DP_TBTPA_ML_P<1>
DP_TBTPA_ML_N<1>
DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>
DP_TBTPA_ML_C_P<3>
DP_TBTPA_ML_C_N<3>
DP_TBTPA_ML_P<3>
DP_TBTPA_ML_N<3>

TBT_A_D2R_C_P<0>
TBT_A_D2R_C_N<0>
TBT_A_D2R_P<0>
TBT_A_D2R_N<0>
TBT_A_D2R_C_P<1>
TBT_A_D2R_C_N<1>
TBT_A_D2R_P<1>
TBT_A_D2R_N<1>
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N

DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_P
DP_TBTPA_AUXCH_N

TBT_B_R2D_C_P<1..0>
TBT_B_R2D_C_N<1..0>
TBT_B_R2D_P<1..0>
TBT_B_R2D_N<1..0>

DP_TBTPB_ML_C_P<1>
DP_TBTPB_ML_C_N<1>
DP_TBTPB_ML_P<1>
DP_TBTPB_ML_N<1>
DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>
DP_TBTPB_ML_C_P<3>
DP_TBTPB_ML_C_N<3>
DP_TBTPB_ML_P<3>
DP_TBTPB_ML_N<3>

TBT_B_D2R_C_P<0>
TBT_B_D2R_C_N<0>
TBT_B_D2R_P<0>
TBT_B_D2R_N<0>
TBT_B_D2R_C_P<1>
TBT_B_D2R_C_N<1>
TBT_B_D2R_P<1>
TBT_B_D2R_N<1>
TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N

DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N
DP_TBTPB_AUXCH_P
DP_TBTPB_AUXCH_N

25 28 71

25 28 71

28 71

28 71

25 28

25 28

28

28

28

28

25 28

25 28

28

28

28 71

28 71

25 28 71

25 28 71

28 71

28 71

25 28 71

25 28 71

28

28

25 28

25 28

28

28

25 29 71

25 29 71

29 71

29 71

25 29

25 29

29

29

29

29

25 29

25 29

29

29

29 71

29 71

25 29 71

25 29 71

29 71

29 71

25 29 71

25 29 71

29

29

25 29

25 29

29

29

Notes:
AUX and DDC was removed from DISPLAYPORT or
TBTDP_RX/TX because it’s not high speed, and
to save routing space.

Only used on dual-port hosts.

12

D

C

B

DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.
DisplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.
SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.
MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.

ELECTRICAL CONST SET

SPI_TBT_CLK
SPI_TBT_MOSI
SPI_TBT_MISO
SPI_TBT_CS_L

DP_HDMI_TBT_ML

I315

DP_HDMI_TBT_ML

A

I314

DP_HDMI_TBT_AUX

I313

DP_HDMI_TBT_AUX

I312

HDMI_CLOCK

I309

HDMI_CLOCK

I308

HDMI_DATA HDMI_DATA

I311

HDMI_DATA HDMI_DATA

I310

PHYSICAL

DP_85D
DP_85D
DP_85D
DP_85D

TBT_SPI_45S
TBT_SPI_45S
TBT_SPI_45S
TBT_SPI_45S

DP_85D
DP_85D
DP_85D
DP_85D

HDMI_85D
HDMI_85D

NET TYPE

SPACING

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

TBT_SPI
TBT_SPI
TBT_SPI
TBT_SPI

DISPLAYPORT
DISPLAYPORT

HDMI_CLKHDMI_85D
HDMI_CLKHDMI_85D

DP_TBTSRC_ML_C_P<3..0>
DP_TBTSRC_ML_C_N<3..0>
DP_TBTSRC_AUXCH_C_P
DP_TBTSRC_AUXCH_C_N

TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L

DP_HDMI_TBT_ML_P<3..0>
DP_HDMI_TBT_ML_N<3..0>
DP_HDMI_TBT_AUX_P
DP_HDMI_TBT_AUX_N

HDMI_IG_CLK_C_P
HDMI_IG_CLK_C_N
HDMI_IG_DATA_C_P<2..0>
HDMI_IG_DATA_C_N<2..0>

Only used on hosts supporting Thunderbolt video-in

25

25

25

25

67 69

67 69

67 69

67 69

66 67 71

66 67 71

66 67 71

66 67 71

DP_TBTSNK0_ML

I338

DP_TBTSNK0_ML

I339

DP_TBTSNK0_ML

I336

DP_TBTSNK0_ML

I337

DP_TBTSNK_AUXCH

I335

DP_TBTSNK_AUXCH

I334

DP_TBTSNK_AUXCH

I324

DP_TBTSNK_AUXCH

I333

DP_TBTSNK1_ML

I332

DP_TBTSNK1_ML

I330

DP_TBTSNK1_ML

I331

DP_TBTSNK1_ML

I328

DP_TBTSNK_AUXCH

I329

DP_TBTSNK_AUXCH

I327

DP_TBTSNK_AUXCH

I325

DP_TBTSNK_AUXCH

I326

DP_INT_ML

I359

DP_INT_ML

I360

DP_INT_ML

I316

DP_INT_ML

I358

DP_INT_ML

I357

DP_INT_ML

I356

DP_INT_AUXCH

I320

DP_INT_AUXCH

I321

DP_INT_AUXCH

I322

DP_INT_AUXCH

I323

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DP_TBTSNK0_ML_C_P<3..0>
DP_TBTSNK0_ML_C_N<3..0>
DP_TBTSNK0_ML_P<3..0>
DP_TBTSNK0_ML_N<3..0>
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N

DP_TBTSNK1_ML_C_P<3..0>
DP_TBTSNK1_ML_C_N<3..0>
DP_TBTSNK1_ML_P<3..0>
DP_TBTSNK1_ML_N<3..0>
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N

DP_INT_ML_F_P<3..0>
DP_INT_ML_F_N<3..0>
DP_INT_ML_C_P<3..0>
DP_INT_ML_C_N<3..0>
DP_INT_ML_P<3..0>
DP_INT_ML_N<3..0>
DP_INT_AUXCH_C_P
DP_INT_AUXCH_C_N
DP_INT_AUX_P
DP_INT_AUX_N

6 3

5

5

25

25

13 25

13 25

25

25

25 67

25 67

25

25

25 67

25 67

25

25

65

65

5

5

65 71

65 71

5

5

65 71

65 71

25

25

SIZE

A

D

SYNC_MASTER=GKOO_J52

65

65

65

65

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

TBT,DP,HDMI Constraints

Apple Inc.

R

SYNC_DATE=12/06/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

115 OF 120

SHEET

77 OF 82

124578

8 7 6 5 4 3

Camera Net Properties

ELECTRICAL CONST SET

PHYSICAL

NET TYPE

SPACING

12

MIPI Interface Constraints

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

*

=85_OHM_DIFF

* *

CLK_MIPI

* *

ALLOW ROUTE
ON LAYER?

LINE-TO-LINE SPACING

=4X_DIELECTRIC
=6X_DIELECTRIC
=7X_DIELECTRIC

LAYER

D

MIPI_85D

SPACING_RULE_SET

LAYER

MIPI_2OTHER

MIPI_2CLK

MIPICLK_2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MIPI_DATA
MIPI_DATA

CLK_MIPI

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

WEIGHT

AREA_TYPE

SPACING_RULE_SET

MIPI_2OTHER

*

MIPI_2CLK

MIPICLK_2OTHER

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

MIPI_2OTHER

MIPI_2CLK

MIPICLK_2OTHER

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM
TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF

LINE-TO-LINE SPACING

=6X_DIELECTRIC
=8X_DIELECTRIC

=10X_DIELECTRICTOP,BOTTOM

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

Memory Bus Constraints

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

S2_MEM_45S
S2_MEM_85D

LAYER

*
*

ALLOW ROUTE
ON LAYER?

=45_OHM_SE

=85_OHM_DIFF

MINIMUM LINE WIDTH

=45_OHM_SE =45_OHM_SE =45_OHM_SE

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

Spacing Rule Sets

C

SPACING_RULE_SET

LAYER

S2_DATA2SELF

S2_DQS2OWNDATA

S2_CMD2CMD

S2_CMD2CTRL
S2_CTRL2CTRL
S2_2OTHERMEM

S2MEM_2PWR
S2MEM_2GND

S2MEM_2OTHER

*
*
*
*
*
*
*
*
*

LINE-TO-LINE SPACING

=2x_DIELECTRIC
=2x_DIELECTRIC
=2x_DIELECTRIC
=2x_DIELECTRIC
=2x_DIELECTRIC
=4x_DIELECTRIC
=2x_DIELECTRIC
=2x_DIELECTRIC
=6x_DIELECTRIC

WEIGHT

?
?
?
?
?
?
?
?
?

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

S2_DATA2SELF

TABLE_SPACING_RULE_ITEM

S2_DQS2OWNDATA

TABLE_SPACING_RULE_ITEM

S2_CMD2CMD TOP,BOTTOM

TABLE_SPACING_RULE_ITEM

S2_CMD2CTRL

TABLE_SPACING_RULE_ITEM

S2_CTRL2CTRL
S2_2OTHERMEM

TABLE_SPACING_RULE_ITEM

S2MEM_2PWR TOP,BOTTOM

TABLE_SPACING_RULE_ITEM

S2MEM_2GND TOP,BOTTOM

TABLE_SPACING_RULE_ITEM

S2MEM_2OTHER

LAYER

TOP,BOTTOM
TOP,BOTTOM

LINE-TO-LINE SPACING

=4x_DIELECTRIC
=4x_DIELECTRIC

=4x_DIELECTRIC
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM

=4x_DIELECTRIC

=4x_DIELECTRIC

=6x_DIELECTRIC

=4x_DIELECTRIC

=4x_DIELECTRIC
TOP,BOTTOM=10x_DIELECTRIC

WEIGHT

?
?
?
?
?
?
?
?
?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

S2_MEM_CLK S2_MEM_CLKS2_MEM_85D
S2_MEM_CLK S2_MEM_CLKS2_MEM_85D

S2_MEM_45SS2_MEM_CKE

S2_MEM_CS

S2_MEM_CMD
S2_MEM_CMD
S2_MEM_CMD S2_MEM_CMDS2_MEM_45S
S2_MEM_CMD S2_MEM_CMDS2_MEM_45S
S2_MEM_CMD S2_MEM_CMDS2_MEM_45S
S2_MEM_CMD S2_MEM_CMDS2_MEM_45S
S2_MEM_DQS0
S2_MEM_DQS0 S2_MEM_DQS0
S2_MEM_DQS1 S2_MEM_DQS1
S2_MEM_DQS1 S2_MEM_DQS1
S2_MEM_DATA_0
S2_MEM_DATA_1
S2_MEM_A

S2_MEM_DATA_0
S2_MEM_DATA_1

MIPI_DATA_S2 MIPI_85D
MIPI_DATA_S2

MIPI_CLK_S2
MIPI_CLK_S2
MIPI_CLK_S2
MIPI_CLK_S2

I149

S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S

S2_MEM_85D
S2_MEM_85D
S2_MEM_85D
S2_MEM_85D
S2_MEM_45S
S2_MEM_45S

S2_MEM_45S
S2_MEM_45S

MIPI_85DMIPI_DATA_S2

MIPI_85D
MIPI_85DMIPI_DATA_S2

S2_MEM_CTRL
S2_MEM_CTRL
S2_MEM_CTRL
S2_MEM_CTRL
S2_MEM_CTRL

S2_MEM_DQS0

S2_MEM_DATA0
S2_MEM_DATA1
S2_MEM_CMDS2_MEM_45S

S2_MEM_DATA0
S2_MEM_DATA1

MIPI_DATA
MIPI_DATA
MIPI_DATA
MIPI_DATA

CLK_MIPIMIPI_85D
CLK_MIPIMIPI_85D
CLK_MIPIMIPI_85D
CLK_MIPIMIPI_85D

S2_MEM_PWR
S2_MEM_PWR
S2_MEM_PWR
S2_MEM_PWR

MEM_CAM_CLK_P
MEM_CAM_CLK_N

MEM_CAM_CKE
MEM_CAM_CS_L
MEM_CAM_ODT
MEM_CAM_CAS_L
MEM_CAM_RAS_L
MEM_CAM_WE_L
MEM_CAM_BA<0>
MEM_CAM_BA<1>
MEM_CAM_BA<2>
MEM_CAM_DQS_P<0>
MEM_CAM_DQS_N<0>
MEM_CAM_DQS_P<1>
MEM_CAM_DQS_N<1>
MEM_CAM_DM<0>
MEM_CAM_DM<1>
MEM_CAM_A<14..0>

MEM_CAM_DQ<7..0>
MEM_CAM_DQ<15..8>

MIPI_DATA_P
MIPI_DATA_N
MIPI_DATA_CONN_P
MIPI_DATA_CONN_N

MIPI_CLK_P
MIPI_CLK_N
MIPI_CLK_CONN_P
MIPI_CLK_CONN_N

PP1V35_CAM
PP0V675_CAM_VREF

PP0V675_MEM_CAM_VREFCA
PP0V675_MEM_CAM_VREFDQ

33 34

33 34

33 34

33 34

34

33 34

33 34

33 34

33 34

33 34

33 34

33 34

33 34

33 34

33 34

33 34

33 34

33 34

33 34

33 34

33 34 71

33 34 71

34 71

34 71

33 34 71

33 34 71

34 71

34 71

33 34

33 34

34

34

D

C

Memory Bus Spacing Group Assignments

S2MEM_2PWR

DEFAULT

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

B

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

S2_CMD2CMD

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

S2_MEM_DATA*

S2_MEM_DQS*

S2_MEM_CMD

B

S2_MEM_CTRL

S2_MEM_CLK

S2_MEM_DATA*

S2_MEM_CMD
S2_MEM_CMD

* *
* *
* *
* *
* *

=SAME

S2_MEM_CMD

S2_MEM_CTRL

AREA_TYPE

S2_MEM_CTRL S2_MEM_CTRL

S2_MEM_* S2_MEM_*

*
*
*
*
*

SPACING_RULE_SET

S2MEM_2OTHER
S2MEM_2OTHER
S2MEM_2OTHER
S2MEM_2OTHER
S2MEM_2OTHER
S2_DATA2SELF

S2_CMD2CTRL
S2_CTRL2CTRL
S2_2OTHERMEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

S2_MEM_DQS1
S2_MEM_DQS0

S2_MEM_DATA1
S2_MEM_DATA0

Memory to Power Spacing

NET_SPACING_TYPE1 NET_SPACING_TYPE2

S2_MEM_PWR
S2_MEM_PWR

S2_MEM_*

* *

AREA_TYPE

*
*

AREA_TYPE

*

SPACING_RULE_SET

S2_DQS2OWNDATA
S2_DQS2OWNDATA

SPACING_RULE_SET

Memory to GND Spacing

S2MEM_2GND

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

Camera Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/09/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

116 OF 120

SHEET

78 OF 82

124578

SIZE

A

D

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GND

S2_MEM_*

AREA_TYPE

SPACING_RULE_SET

*

A

6 3

8 7 6 5 4 3

12

SMC SMBus & Charger Net Properties

ELECTRICAL CONST SET

SMBUS_SMC_2
SMBUS_SMC_2
SMBUS_SMC_1
SMBUS_SMC_1
SMBUS_SMC_0

D

SMBUS_SMC_0
SMBUS_SMC_5
SMBUS_SMC_5
SMBUS_SMC_3
SMBUS_SMC_3

PHYSICAL

SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S
SMB_45S

NET TYPE

SPACING

SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB

SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA

38 41 71

38 41 71

38 41 71

38 41 71

38 41

38 41

38 41 71

38 41 71

38 41

38 41

D

C

B

C

B

A

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

SMC Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=01/02/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

117 OF 120

SHEET

79 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

SENSE_45S
THERM_45S
DIG_AUDIO
ANL_AUDIO

ANL_AUDIO_WIDE

D

SPACING_RULE_SET

SENSE
THERM
AUDIO

SPACING_RULE_SET

GND

SPACING_RULE_SET

GND_P2MM
PWR_P2MM

MEM_45S

C

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_40S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_72D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_85D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

PCIE_85D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

USB_85D

CPU_27P4S BOTTOM

USB3_85D
USB3_85D

DP_85D

PCIE_85D

B

LAYER

*
*
*
*
*

LAYER

LAYER

LAYER

LAYER

*

*

*

*

*

TOP

TOP

ISL10

ISL9

ISL10

*

*

*

*

*
*

ALLOW ROUTE
ON LAYER?

=1TO1_DIFFPAIR

=1TO1_DIFFPAIR

=1TO1_DIFFPAIR

=1TO1_DIFFPAIR

=1TO1_DIFFPAIR

LINE-TO-LINE SPACING

MINIMUM LINE WIDTH

=1TO1_DIFFPAIR =1TO1_DIFFPAIR =1TO1_DIFFPAIR

=2X_DIELECTRIC
=2X_DIELECTRIC
=2X_DIELECTRIC

LINE-TO-LINE SPACING

=STANDARD

LINE-TO-LINE SPACING

0.20 MM

0.20 MM

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=45_OHM_SE =45_OHM_SE =45_OHM_SE
=45_OHM_SE =45_OHM_SE =45_OHM_SE

0.1 MM 0.1 MM

0.3 MM 0.3 MM

TABLE_SPACING_RULE_HEAD

WEIGHT

WEIGHT

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

CPU_VCCSENSE

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

CLK_PCIE

GND PCIE_*

10 MM
10 MM

GND

GND

GND SATA_*

WEIGHT

1000
1000

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

USB
CLK_PCIE SB_POWER
SB_POWER

USB

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

0.070 MM

0.090 MM

0.090 MM

0.090 MM

0.090 MM

0.100 MM

0.230 MM

0.100 MM

GND *

SATA_*

SB_POWER

100 MIL

100 MIL

100 MIL

100 MIL

10 MM

500 MIL
100 MIL
500 MIL

0.075 MM 0.090 MM

0.075 MM 0.090 MM

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM

0.1 MM 0.1 MM

0.1 MM 0.1 MM

0.1 MM 0.1 MM

0.1 MM 0.1 MM

AREA_TYPE

AREA_TYPE

*

*
*
*

SPACING_RULE_SET

GND_P2MM

SPACING_RULE_SET

GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM

*

PWR_P2MM

*

PWR_P2MM

*

PWR_P2MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

0.090 MM0.075 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

X304 Specific Net Properties

ELECTRICAL CONST SET

THERM_DP_TBT_D1
THERM_DP_TBT_D1
THERM_DP_CPU_D1
THERM_DP_CPU_D1
THERM_DP_CPU_D2
THERM_DP_CPU_D2

SENSE_DP
SENSE_DP

SENSE_DP_LCDBKLT
SENSE_DP_LCDBKLT
SENSE_DP_TBT
SENSE_DP_TBT
SENSE_DP
SENSE_DP

SENSE_DP
SENSE_DP
SENSE_DP
SENSE_DP

SENSE_DP_CPUVR
SENSE_DP_CPUVR
SENSE_DP_CPUVR
SENSE_DP_CPUVR

SENSE_DP
SENSE_DP
SENSE_DP
SENSE_DP
SENSE_DP
SENSE_DP

SENSE_DP
SENSE_DP

SENSE_DP
SENSE_DP
SENSE_DP
SENSE_DP

SENSE_DP_CPUHIGN
SENSE_DP_CPUHIGN
SENSE_DP_CPUHIGN
SENSE_DP_CPUHIGN

PHYSICAL

THERM_45S
THERM_45S
THERM_45S
THERM_45S
THERM_45S
THERM_45S

SENSE_45S
SENSE_45S

SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S

SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S

SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S

SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S

SENSE_45S
SENSE_45S

SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S

SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S

NET TYPE

SPACING

THERM
THERM
THERM
THERM
THERM
THERM

SENSE
SENSE

SENSE
SENSE
SENSE
SENSE
SENSE
SENSE

SENSE
SENSE
SENSE
SENSE
SENSE
SENSE

SENSE
SENSE
SENSE
SENSE

SENSE
SENSE
SENSE
SENSE
SENSE
SENSE

SENSE
SENSE

SENSE
SENSE
SENSE
SENSE

SENSE
SENSE
SENSE
SENSE

TBTTHMSNS_D1_P
TBTTHMSNS_D1_N
CPUTHMSNS_D1_P

CPUTHMSNS_D1_N
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N

ISNS_CPUDDR_P

ISNS_CPUDDR_N

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

ISNS_TBT_P

ISNS_TBT_N

ISNS_LCDPANEL_P

ISNS_LCDPANEL_N

ISNS_HS_COMPUTING_P
ISNS_HS_COMPUTING_N
ISNS_HS_OTHER5V_P
ISNS_HS_OTHER5V_N
ISNS_HS_OTHER3V3_P
ISNS_HS_OTHER3V3_N

CPUVR_ISNS_P
CPUVR_ISNS_N
CPUVR_ISNS_R_P
CPUVR_ISNS_R_N

ISNS_1V05_S0_P
ISNS_1V05_S0_N
ISNS_SSD_P
ISNS_SSD_N
ISNS_TPAD_P
ISNS_TPAD_N

ISNS_1V8_S3_P
ISNS_1V8_S3_N

ISNS_PP3V3S0_P
ISNS_PP3V3S0_N
ISNS_PP5VS0_P
ISNS_PP5VS0_N

ISNS_CPUHIGAIN_P
ISNS_CPUHIGAIN_N
ISNS_CPUHIGAIN_R_P
ISNS_CPUHIGAIN_R_N

45

45

45

45

45

45

43

43

42 60

42 60

44

44

44 65

44 65

42 44

42 44

42

42

42

42

43

43

43

43

43 59

43 59

43

43

42

42

43 61

43 61

43

43

43

43

44 45

44 45

44

44

X304 Specific Net Properties

ELECTRICAL CONST SET

AUDIO_DP_AMPTWT
AUDIO_DP_AMPTWT
AUDIO_DP_AMPTWT
AUDIO_DP_AMPTWT
AUDIO_DP_AMPTWT
AUDIO_DP_AMPTWT

AUDIO_DP_AMPTWT
AUDIO_DP_AMPTWT
AUDIO_DP_AMPTWT
AUDIO_DP_AMPTWT
AUDIO_DP_AMPTWT
AUDIO_DP_AMPTWT

AUDIO_DP_AMPSUB
AUDIO_DP_AMPSUB
AUDIO_DP_AMPSUB
AUDIO_DP_AMPSUB
AUDIO_DP_AMPSUB
AUDIO_DP_AMPSUB

AUDIO_DP_AMPSUB
AUDIO_DP_AMPSUB
AUDIO_DP_AMPSUB
AUDIO_DP_AMPSUB
AUDIO_DP_AMPSUB
AUDIO_DP_AMPSUB

AUDIO_DP_SPKSUB
AUDIO_DP_SPKSUB
AUDIO_DP_SPKSUB
AUDIO_DP_SPKSUB
AUDIO_DP_SPKTWT
AUDIO_DP_SPKTWT
AUDIO_DP_SPKTWT
AUDIO_DP_SPKTWT

AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC

AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC
AUDIO_DP_MIC

NET TYPE

PHYSICAL

ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO

ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO

ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO

ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO
ANL_AUDIO

DIG_AUDIO
DIG_AUDIO
DIG_AUDIO
DIG_AUDIO
DIG_AUDIO
DIG_AUDIO
DIG_AUDIO
DIG_AUDIO

ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE

ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
ANL_AUDIO_WIDE

SPACING

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

SB_POWER
SB_POWER

AUD_LO2_L_P
AUD_LO2_L_N
AUD_SPKRAMP_LIN_P
AUD_SPKRAMP_LIN_N
SPKRAMP_LIN_P
SPKRAMP_LIN_N

AUD_LO2_R_P
AUD_LO2_R_N
AUD_SPKRAMP_RIN_P
AUD_SPKRAMP_RIN_N
SPKRAMP_RIN_P
SPKRAMP_RIN_N

AUD_LO3_L_P

AUD_LO3_L_N
AUD_SPKRAMP_LSUBIN_P
AUD_SPKRAMP_LSUBIN_N

LSUBIN_P
LSUBIN_N

AUD_LO3_R_P

AUD_LO3_R_N
AUD_SPKRAMP_RSUBIN_P
AUD_SPKRAMP_RSUBIN_N

RSUBIN_P
RSUBIN_N

SPKRCONN_SL_OUT_P

SPKRCONN_SL_OUT_N

SPKRCONN_SR_OUT_P

SPKRCONN_SR_OUT_N

SPKRCONN_L_OUT_P

SPKRCONN_L_OUT_N

SPKRCONN_R_OUT_P

SPKRCONN_R_OUT_N

AUD_CH_HS_GND

AUD_CONN_HS_MIC_P

AUD_CONN_SLEEVE

AUD_CONN_SLEEVE_XW

AUD_HP_PORT_REFCH

AUD_HS_MIC_P

CODEC_HS_MIC_P

HS_MIC_P

AUD_CONN_HS_MIC_N

AUD_CONN_RING2

AUD_CONN_RING2_XW

AUD_HP_PORT_REFUS

AUD_HS_MIC_N

AUD_US_HS_GND

HS_MIC_N

CODEC_HS_MIC_N

PP3V3_S5

PP3V3_S0

48 50

48 50

50

50

50

50

48 50

48 50

50

50

50

50

48 50

48 50

50

50

50

50

48 50

48 50

50

50

50

50

50 52 71

50 52 71

50 52 71

50 52 71

50 52 71

50 52 71

50 52 71

50 52 71

48 52

52

51 52

48 52

51 52

48

48 51

52

51 52

48 52

51 52

48 52

48 51

48

68 71

68 71

D

C

B

DP, SATA, HDMI, PCIE CONSTRAINT RELAXATIONS

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

NET_PHYSICAL_TYPE

AREA_TYPE

PHYSICAL_RULE_SET

BGADP_85D

PCIE_85D

CLK_PCIE_85D

HDMI_85D

BGA
BGA
BGA

A

P65_BGA
P65_BGA
P65_BGA
P65_BGA

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_PHYSICAL_TYPE

DIG_AUDIO
ANL_AUDIO

AREA_TYPE

*
*
*
*

SENSE_45SSENSE_45S
THERM_45STHERM_45S
DIG_AUDIO
ANL_AUDIO

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

CHGR_CSI_P

SENSE_DP_CHGR_CSI
SENSE_DP_CHGR_CSI
SENSE_DP_CHGR_CSI
SENSE_DP_CHGR_CSI
SENSE_DP_CHGR_CSO
SENSE_DP_CHGR_CSO
SENSE_DP_CHGR_CSO
SENSE_DP_CHGR_CSO

SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S

SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE

CHGR_CSI_N
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_P
CHGR_CSO_N
CHGR_CSO_R_P
CHGR_CSO_R_N

54

54

54

54

54

54

44 54

44 54

The signals below have no topologies assigned.

DP_NO_TOPOLOGY
DP_NO_TOPOLOGY
DP_NO_TOPOLOGY
DP_NO_TOPOLOGY

SENSE_45S
SENSE_45S
SENSE_45S
SENSE_45S

SENSE
SENSE
SENSE
SENSE

CPUVR_ISNS1_P
CPUVR_ISNS1_N
CPUVR_ISNS2_P
CPUVR_ISNS2_N

43 56

43 56

43 56

43 56

6 3

GND

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

Project Specific Constraints

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

GND

Apple Inc.

R

SYNC_DATE=01/04/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

118 OF 120

SHEET

80 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

12

PCI Express Constraints

LAYER

PCIE_85D

D

SPACING_RULE_SET

PCIE_2SAME

LAYER

PCIE_TXRX

PCIE_2OTHER

PCIE_2CLK

PCIECLK_2OTHER

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PCIE_*
PCIE_*
PCIE_*

CLK_PCIE

PCIE_TX
PCIE_RX

ALLOW ROUTE
ON LAYER?

=85_OHM_DIFF

*
*

=85_OHM_DIFF

LINE-TO-LINE SPACING

* ?

=3X_DIELECTRIC

* ?

=6X_DIELECTRIC

* ?

=4X_DIELECTRIC

* ?

=7X_DIELECTRIC

* ?

=7X_DIELECTRIC

*
=SAME
CLK_*

* *

*_RX
*_TX

AREA_TYPE

*
*
*

*
*

MINIMUM LINE WIDTH

=85_OHM_DIFF
=85_OHM_DIFFCLK_PCIE_85D

WEIGHT

SPACING_RULE_SET

PCIE_2OTHER

PCIE_2SAME

PCIE_2CLK

PCIECLK_2OTHER

PCIE_TXRX
PCIE_TXRX

MINIMUM NECK WIDTH

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

PCIE_TXRX

PCIE_2OTHER

PCIE_2CLK

PCIECLK_2OTHER

LAYER

TOP,BOTTOMPCIE_2SAME
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM

LINE-TO-LINE SPACING

=4X_DIELECTRIC

=10X_DIELECTRIC

=6X_DIELECTRIC
=10X_DIELECTRIC
=10X_DIELECTRIC

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

C

PCI Express Properties

ELECTRICAL CONST SET

PCIE_SSD_D2R
PCIE_SSD_D2R
PCIE_SSD_D2R_PP
PCIE_SSD_D2R_PP

PCIE_SSD_R2D

PCIE_TBT_D2R_0
PCIE_TBT_D2R_0
PCIE_TBT_D2R_0 PCIE_RX

PCIE_TBT_D2R PCIE_85D
PCIE_TBT_D2R PCIE_85D
PCIE_TBT_D2R
PCIE_TBT_D2R PCIE_85D
PCIE_TBT_R2D PCIE_85D
PCIE_TBT_R2D
PCIE_TBT_R2D
PCIE_TBT_R2D PCIE_85D

PCIE_AP_R2D
PCIE_AP_R2D
PCIE_AP_R2D
PCIE_AP_R2D

PHYSICAL

PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D

PCIE_85DPCIE_SSD_R2D
PCIE_85DPCIE_SSD_R2D
PCIE_85DPCIE_SSD_R2D
PCIE_85D

PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D

PCIE_85D

PCIE_85D
PCIE_85D

PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D

NET TYPE

SPACING

PCIE_RX
PCIE_RX
PCIE_RX
PCIE_RX

PCIE_TX
PCIE_TX
PCIE_TX
PCIE_TX

PCIE_RX
PCIE_RX

PCIE_RXPCIE_TBT_D2R_0
PCIE_RX
PCIE_RX
PCIE_RX
PCIE_RX
PCIE_TX
PCIE_TX
PCIE_TX
PCIE_TX

PCIE_TX
PCIE_TX
PCIE_TX
PCIE_TX

PCIE_SSD_D2R_P<3..1>
PCIE_SSD_D2R_N<3..1>
PCIE_SSD_D2R_P<0>
PCIE_SSD_D2R_N<0>

PCIE_SSD_R2D_C_P<3..0>
PCIE_SSD_R2D_C_N<3..0>
PCIE_SSD_R2D_P<3..0>
PCIE_SSD_R2D_N<3..0>

PCIE_TBT_D2R_P<0>
PCIE_TBT_D2R_N<0>
PCIE_TBT_D2R_C_P<0>
PCIE_TBT_D2R_C_N<0>
PCIE_TBT_D2R_P<3..1>
PCIE_TBT_D2R_N<3..1>
PCIE_TBT_D2R_C_P<3..1>
PCIE_TBT_D2R_C_N<3..1>
PCIE_TBT_R2D_P<3..0>
PCIE_TBT_R2D_N<3..0>
PCIE_TBT_R2D_C_P<3..0>
PCIE_TBT_R2D_C_N<3..0>

PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N

12 32 71

12 32 71

12 32 71

12 32 71

12 32 71

12 32 71

32 71

32 71

14 25 71

14 25 71

25

25

14 25 71

14 25 71

25 71

25 71

25 71

25 71

14 25 71

14 25 71

66 71

66 71

14 66 71

14 66 71

D

C

PCIE_AP_D2R
PCIE_AP_D2R
PCIE_CLK100M_AP
PCIE_CLK100M_AP
PCIE_CLK100M_AP
PCIE_CLK100M_AP
PCIE_CLK100M_CAM
PCIE_CLK100M_CAM
PCIE_CLK100M_CAM
PCIE_CLK100M_CAM
PCIE_CLK100M_SSD
PCIE_CLK100M_SSD
PCIE_CLK100M_SSD

I303

PCIE_CLK100M_SSD

I302

PCIE_CLK100M_SSD

I304

PCIE_CLK100M_SSD

I305

PCIE_CLK100M_TBT

B

PCIE_CLK100M_TBT
PCIE_CAMERA_D2R
PCIE_CAMERA_D2R
PCIE_CAMERA_D2R
PCIE_CAMERA_D2R
PCIE_CAMERA_R2D
PCIE_CAMERA_R2D
PCIE_CAMERA_R2D
PCIE_CAMERA_R2D

PCIE_85D
PCIE_85D

CLK_PCIE_85D

CLK_PCIE_85D CLK_PCIE

CLK_PCIE_85D

CLK_PCIE_85D
CLK_PCIE_85D CLK_PCIE
CLK_PCIE_85D
CLK_PCIE_85D
CLK_PCIE_85D

CLK_PCIE_85D CLK_PCIE

PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D

PCIE_RX
PCIE_RX
CLK_PCIE
CLK_PCIECLK_PCIE_85D

CLK_PCIECLK_PCIE_85D
CLK_PCIECLK_PCIE_85D
CLK_PCIE
CLK_PCIECLK_PCIE_85D
CLK_PCIE

CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIECLK_PCIE_85D

CLK_PCIECLK_PCIE_85D
CLK_PCIECLK_PCIE_85D
PCIE_RX
PCIE_RX
PCIE_RX
PCIE_RX
PCIE_TX
PCIE_TX
PCIE_TX
PCIE_TX

PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_CAMERA_P
PCIE_CLK100M_CAMERA_N
PCIE_CLK100M_CAMERA_C_P
PCIE_CLK100M_CAMERA_C_N
PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_RC1_P
PCIE_CLK100M_SSD_RC1_N
PCIE_CLK100M_SSD_RC2_P
PCIE_CLK100M_SSD_RC2_N
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
PCIE_CAMERA_D2R_P
PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_C_P
PCIE_CAMERA_D2R_C_N
PCIE_CAMERA_R2D_P
PCIE_CAMERA_R2D_N
PCIE_CAMERA_R2D_C_P
PCIE_CAMERA_R2D_C_N

14 66 71

14 66 71

66

66

12 66 71

12 66 71

12 34 71

12 34 71

33 34

33 34

12 32 71

12 32 71

32

32

32

32

12 25 71

12 25 71

14 34 71

14 34 71

33 34

33 34

33 34

33 34

14 34

14 34

B

A

6 3

SYNC_MASTER=YHARTANTO_J44

PAGE TITLE

PCIe Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/13/2013

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

119 OF 120

SHEET

81 OF 82

124578

SIZE

A

D

8 7 6 5 4 3

Change List:

<RDAR://COMPONENT/XXXXXX> X304 HW EE SCHEMATIC | PROTO 0

12

D

Kismet:

D

AFP://KISMET.APPLE.COM/KISMET-PROJECTS/X304

Useful Wiki Links:

Schematic Conventions - https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions
Schematic Design Wiki - https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design

MobileMac HW Radar:

<rdar://component/497591> MobileMac HW | Task
<rdar://component/497587> MobileMac HW | Schematic
<rdar://component/497585> MobileMac HW | New Bugs
<rdar://component/497588> MobileMac HW | Layout
<rdar://component/497590> MobileMac HW | Investigation

C

<rdar://component/497589> MobileMac HW | Architecture

C

Other Info:

Page Allocations - <rdar://problem/11791318> 2012 Schematic Page Allocations

SIZE

B

A

D

B

A

SYNC_MASTER=J14

PAGE TITLE

Reference

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=10/23/2012

DRAWING NUMBER

051-1573

REVISION

8.0.0

BRANCH

dvt1

PAGE

120 OF 120

SHEET

82 OF 82

124578