Apple MacBook Pro A1398 Schematics

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

SCHEM,MLB,J45

Schematic / PCB #’s

DVT 8/6/2013

ALIASES RESOLVED

1 OF 81

<PART_DESCRIPTION>

<SCH_NUM>

<ECO_DESCRIPTION>

1 OF 118

03/15/2013

SMC

50

CHANG_J45

41

03/15/2013

KEYBOARD/TRACKPAD (2 OF 2)

49

CHANG_J45

40

03/15/2013

KEYBOARD/TRACKPAD (1 OF 2)

48

CHANG_J45

39

10/31/2012

USB 3.0 CONNECTORS

46

J15_MLB

38

06/13/2013

Camera 2 of 2

40

CLEAN_MLB_KEPLER

37

06/13/2013

Camera 1 of 2

39

CLEAN_MLB_KEPLER

36

06/08/2013

SSD Connector

37

CLEAN_MLB_KEPLER

35

10/31/2012

X29C CONNECTOR

35

J15_MLB

34

11/16/2012

DDC Crossbar

34

J15_REFERENCE

33

12/18/2012

Thunderbolt Connector B

33

J15_REFERENCE

32

12/18/2012

Thunderbolt Connector A

32

J15_REFERENCE

31

01/14/2013

Thunderbolt Mobile Support

30

T29_RR

30

01/14/2013

Thunderbolt Host (2 of 2)

29

T29_RR

29

01/14/2013

Thunderbolt Host (1 of 2)

28

T29_RR

28

10/31/2012

DDR3 Termination

27

J15_MLB

27

10/31/2012

DDR3 SDRAM Bank B (2 OF 2)

26

J15_MLB

26

10/31/2012

DDR3 SDRAM Bank B (1 OF 2)

25

J15_MLB

25

10/31/2012

DDR3 SDRAM Bank A (2 OF 2)

24

J15_MLB

24

10/31/2012

DDR3 SDRAM Bank A (1 OF 2)

23

J15_MLB

23

10/31/2012

DDR3 VREF MARGINING

22

J15_MLB

22

12/18/2012

CPU Memory S3 Support

21

J15_REFERENCE

21

01/14/2013

Project Chipset Support

20

J15_REFERENCE

20

12/18/2012

Chipset Support

19

J15_REFERENCE

19

10/31/2012

CPU & PCH XDP

18

J15_MLB

18

12/18/2012

PCH DECOUPLING

17

J15_REFERENCE

17

12/18/2012

PCH Grounds

16

J15_REFERENCE

16

12/18/2012

PCH Power

15

J15_REFERENCE

15

12/18/2012

PCH GPIO/MISC/NCTF

14

J15_REFERENCE

14

12/18/2012

PCH PCI-E/USB

13

J15_REFERENCE

13

12/18/2012

PCH DMI/FDI/PM/GFX/PCI

12

J15_REFERENCE

12

12/18/2012

PCH RTC/HDA/JTAG/SATA/CLK

11

J15_REFERENCE

11

12/18/2012

CPU Decoupling

10

J15_REFERENCE

10

12/18/2012

CPU Ground

9

J15_REFERENCE

9

12/18/2012

CPU Power

8

J15_REFERENCE

8

12/18/2012

CPU DDR3 Interfaces

7

J15_REFERENCE

7

12/18/2012

CPU Clock/Misc/JTAG/CFG

6

J15_REFERENCE

6

12/18/2012

CPU DMI/PEG/FDI/RSVD

5

J15_REFERENCE

5

10/31/2012

PD Parts

4

J15_MLB

4

10/31/2012

BOM Configuration

3

J15_MLB

3

10/25/2012

BOM Configuration

2

J15_MLB

2

118

SIDLE_J45

12/10/2012

Project Specific Constraints

81

117

SIDLE_J45

12/10/2012

SMC Constraints

80

116

SIDLE_J45

12/10/2012

Camera Constraints

79

115

SIDLE_J45

12/10/2012

Thunderbolt Constraints

78

114

SIDLE_J45

12/10/2012

Memory Constraints

77

113

SIDLE_J45

12/10/2012

PCH Constraints 2

76

112

SIDLE_J45

12/10/2012

PCH Constraints 1

75

111

SIDLE_J45

12/10/2012

CPU Constraints

74

110

SIDLE_J45

12/10/2012

PCB Rule Definitions

73

105

J15_MLB

10/31/2012

NC & No Test

72

104

J15_MLB

10/31/2012

Functional Test Points

71

102

J15_MLB

10/31/2012

Signal Aliases

70

100

J15_MLB

10/31/2012

Power Aliases

69

95

J15_MLB

10/31/2012

RIO Connectors

68

83

J15_MLB

10/31/2012

eDP Display Connector

67

81

CHANG_J45

03/15/2013

Power Control 1/ENABLE

66

80

J15_MLB

10/31/2012

Power FETs

65

78

J15_MLB

10/31/2012

Misc Power Supplies

64

77

CLEAN_MLB_KEPLER

06/13/2013

LCD/KBD Backlight Driver

63

76

J15_MLB

10/31/2012

1V05V POWER SUPPLY

62

75

J15_MLB

10/31/2012

5V / 3.3V Power Supply

61

74

J15_MLB

10/31/2012

1.35V DDR3L SUPPLY

60

73

J15_MLB

10/31/2012

CPU VR12.5 VCC Power Stage

59

72

J15_MLB

10/31/2012

CPU VR12.5 VCC Regulator IC

58

71

J15_MLB

10/31/2012

PBus Supply & Battery Charger

57

70

J15_MLB

10/31/2012

DC-In & Battery Connectors

56

66

JOE_J45

07/30/2013

AUDIO: JACK TRANSLATORS

55

65

JOE_J45

07/30/2013

AUDIO: JACK

54

64

JOE_J45

07/30/2013

AUDIO: SPEAKER AMP

53

63

JOE_J45

07/30/2013

AUDIO:CODEC, DIGITAL

52

62

JOE_J45

07/30/2013

AUDIO:CODEC, ANALOG

51

61

J15_MLB

10/31/2012

SPI ROM / LPC+SPI Conn.

50

60

J15_MLB

10/31/2012

Fan Connectors

49

58

CHANG_J45

11/26/2012

Thermal Sensors

48

56

CHANG_J45

12/21/2012

Debug Sensors

47

55

CHANG_J45

03/15/2013

Load Side Voltage and Current Sensing

46

54

CHANG_J45

12/21/2012

High Side Voltage and Current Sensing

45

53

CHANG_J45

11/26/2012

SMBus Connections

44

52

CHANG_J45

03/15/2013

SMC Project Support

43

Date

Sync

(.csa)

Contents

Page

MASTER

Table of Contents

1

MASTER

1

051-0456

1 SCH

SCHEM,MLB,J45

CRITICAL

ABBREV=ABBREV

TITLE=MLB

LAST_MODIFIED=Tue Aug 6 17:09:28 2013

CRITICAL820-3662

1

PCBF,MLB,J45

PCB

51

CHANG_J45

11/12/2012

SMC Shared Support

42

(.csa)

Contents

Date

SyncPage

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

COMMON/DEVEL BOM

DRAM SPD Straps

J45 BOM Groups

BOM Variants

Module Parts

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:ELPIDA_1600

PCBA,MLB,BETTER,16G ELP,J45

639-4829

PCBA,MLB,BETTER,8G ELP,J45

639-4828

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:ELPIDA_1600_S

PCBA,MLB,BETTER,8G MIC,J45

639-4834

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:MICRON_1600_S

PCBA,MLB,BETTER,16G MIC,J45

639-4835

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:MICRON_1600

PCBA,MLB,BEST,8G MIC,J45

639-4852

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:MICRON_1600_S

639-4853

PCBA,MLB,BEST,16G MIC,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:MICRON_1600

337S4599

CRW,SR18J,,PRQ,C0,2.0,47W,4+3E,6M,BGA

CPU_CRW:BETTER

1

U0500

CRITICAL CRITICAL

CPU_CRW:BEST

U0500

1

CRW,SR18H,PRQ,C0,2.3,47W,4+3E,6M,BGA

337S4600

U2800

CRITICAL

1

338S1247

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

PCBA,MLB,CTO,16G MIC,J45

639-4871

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:MICRON_1600

PCBA,MLB,CTO,16G ELP,J45

639-4865

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:ELPIDA_1600

639-4841

PCBA,MLB,BEST,16G HYN,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:HYNIX_1600

PCBA,MLB,BEST,8G HYN,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:HYNIX_1600_S

639-4840

PCBA,MLB,BEST,8G ELP,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:ELPIDA_1600_S

639-4846

PCBA,MLB,BEST,16G ELP,J45

639-4847

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:ELPIDA_1600

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

333S0660

MICRON_1600

32

IC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA

CRITICAL

ELPIDA_1600

32

333S0703

IC,SDRAM,4GBIT,DDR3L-1600,F DIE,RS,78P

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

639-4822

PCBA,MLB,BETTER,8G HYN,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:HYNIX_1600_S

PCBA,MLB,CTO,8G HYN,J45

639-4858

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:HYNIX_1600_S

PCBA,MLB,CTO,8G ELP,J45

639-4864

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:ELPIDA_1600_S

PCBA,MLB,CTO,8G MIC,J45

639-4870

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:MICRON_1600_S

PCBA,MLB,CTO,16G HYN,J45

639-4859

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:HYNIX_1600

J45_COMMON2

EDP:YES,LPCPLUS_CONN:YES,LPCPLUS_R:YES,XDP,RIO_PWR:1V5,SPI:DUAL_IO,SSD_PWR_EN:GPIO,CAM_WAKE:NO

639-4823

PCBA,MLB,BETTER,16G HYN,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:HYNIX_1600

985-0045

DEV BOM,MLB,J45

J45_DEVEL:ENG

685-0067

COMMON PARTS,MLB,J45

J45_COMMON

XDP_CONN,XDP_PCH

XDP_DEBUG

CRITICAL

U3900

1

IC,BCM15700A2,S2 PCIE CMRA,8X8,208FCBGA

338S1186

32

HYNIX_1600

CRITICAL

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

333S0667

IC,SDRAM,4GBIT,DDR3L-1600,HUMA,78P FBGA

1

CRITICAL

IC,SDRAM,4GBIT,DDR3L-1600,GEMMA,96B FBGA

U4000

333S0700

CRITICAL

U1100

1

337S4542

IC,QEWV,LPT-M,HM87,C2,SR199,PRQ,FCBGA

337S4624

CPU_CRW:CTO

CRITICAL

1

U0500

CRW,SR1BS,PRQ,C0,2.6,47W,4+3E,6M,BGA

ELPIDA_1600_S

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

16

CRITICAL333S0703

IC,SDRAM,4GBIT,DDR3L-1600,F DIE,RS,78P

333S0624

SAMSUNG_1600

32

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

CRITICAL

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

RAM:ELPIDA_1600

ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

J45 MLB BASE BOM

BASE_BOM

CRITICAL

1

BASE685-0067

1

DEVEL_BOM

CRITICAL

DEVEL

J45 MLB DEVEL BOM

985-0045

ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAM:ELPIDA_1600_S

RAM:HYNIX_1600

HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

SAMSUNG_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM:SAMSUNG_1600_S

SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

RAM:SAMSUNG_1600

RAM:MICRON_1600

MICRON_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

MICRON_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAM:MICRON_1600_S

HYNIX_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM:HYNIX_1600_S

SAMSUNG_1600_S

16

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

CRITICAL333S0624

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

IC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA

MICRON_1600_S

CRITICAL

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

16

333S0660

333S0667

16

HYNIX_1600_S

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

CRITICAL

IC,SDRAM,4GBIT,DDR3L-1600,HUMA,78P FBGA

J45_COMMON

ALTERNATE,COMMON,J45_COMMON1,J45_COMMON2,J45_PROGPARTS

J45_DEVEL:FSB

ALTERNATE,XDP_DEBUG,BKLT:PROD,SENSOR_NONPROD:N,SENSOR_NONPROD_R

J45_DEVEL:ENG

ALTERNATE,XDP_DEBUG,S0PGOOD_ISL,DDRVREF_DAC,SENSOR_NONPROD:Y,SENSOR_NONPROD_R,BKLT:ENG,DBGLED,CAM_XTAL:YES

J45_PROGPARTS

SMC_PROG:EVT,BOOTROM_PROG:DVT,TBTROM:PROG,TPAD_PSOC:PROG

J45_PVB

BKLT:PROD,SENSOR_NONPROD:N

J45_COMMON1

CPUMEM:S0,TBTHV:P15V,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,CPUPEG:X16,S2_PWR:S0

BOM Configuration

SYNC_MASTER=J15_MLB

SYNC_DATE=10/25/2012

<SCH_NUM>

2 OF 118

2 OF 81

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Programmables - All builds

EFI ROM

Bar Code Labels / EEEE #’s

SMC

Alternate Parts

CRITICAL

U6100

1

335S0812

BOOTROM_BLANK:NUMONYX

IC,SPI SRL 50MHZ,FLASH,64MBIT,SOIC8

335S0807

1

U6100

CRITICAL

BOOTROM_BLANK:MACRONIX

IC,SPI SRL 50MHZ FLASH,64MBIT,8SOP,FUSE=1

341S3811

1

U6100

CRITICAL

BOOTROM_PROG:PROTO2

IC,EFI ROM(V00xx)PROTO 2,J45

371S0558

DDS alt to STALL

371S0713

Cyntec alt to Vishay

ALL

152S1645152S0461

376S1080

Diodes alt to On Semi

ALL

376S0820

Panasonic alt to TDK

ALL

155S0583155S0667

ALL

Rohm alt to Vishay

138S0732 138S0715

ALL

128S0264

Kemet alt to Sanyo

128S0364

ALL

333S0704 333S0700

ELPIDA to HYNIX U4000

ALL

311S0649 311S0541

ON alt to Toshiba (U2030, U7001)

127S0164

ALL

127S0162

Rohm alt to Vishay

138S0843 138S0674

Samsung alt to Murata

ALL

138S0811138S0846

Samsung alt to Murata

ALL

138S0803 138S0639

ALL

Samsung alt to Murata

138S0681 138S0638

ALL

Taiyo Yuden alt to Samsung

ALL

Kemet alt to Sanyo

128S0371 128S0376

333S0703333S0629

ALL

Elpida F die alt

376S1128376S1089

NXP alt to Diodes

ALL

376S1129 376S0855

ALL

NXP alt to Diodes

376S1032

ALL

Toshiba alt to Diodes

376S0855

107S0232

Cyntec alt to TFT

107S0241

ALL

197S0478 197S0479

NDK Alt to Epson

ALL

376S0604

Diodes alt to Fairchild

ALL

376S1053

NEC alt to Sanyo

ALL

128S0329128S0311 138S0706

ALL

138S0739

Samsung alt to Murata

197S0481

ALL

197S0480

Epson Alt to NDK

CRITICAL

MBP BARCODE LABEL

1

825-7845

LABEL

U5000

SMC_PROG:EVT

1

CRITICAL

IC,SMC-B1,EXT,V2.12A54,EVT,J45

341S3902

U5000

SMC_PROG:PVT

CRITICAL

1

341S3741

IC,SMC-A3,SCPL,EXT,VXXXX,PVT,J15

1

U6100

CRITICAL

BOOTROM_PROG:PRE-PROTO1

IC,EFI ROM(V0035)PRE-PROTO 1,J45

341S3780

BOOTROM_PROG:PROTO0

1

CRITICAL

U6100

341S3763

IC,EFI ROM(VXXXX)PROTO 0,J45

BOOTROM_PROG:EVT

341S3890

1

CRITICAL

U6100

IC,EFI ROM(V0100)PROTO3-J45 &EVT-J45

U6100

CRITICAL

1

341S3929

IC,EFI ROM(Vxxxx)DVT-J45 BOOTROM_PROG:DVT

U6100

IC,EFI ROM(V0041)PROTO 1,J45

341S3793

1

CRITICAL

BOOTROM_PROG:PROTO1

338S1214

1

SMC_PROG:BASE

IC,SMC-B1,40MHZ/50DMIPS,SCPL FW,157BGA

U5000

CRITICAL

TPAD_PSOC:PROG

341S3856

U4801

CRITICAL

1

IC,TRKPD/KYBD,PSOC(V225)

337S4587

TPAD_PSOC:BLANK

1

CRITICAL

U4801

IC,TP PSOC, QFN,BLANK

U2890

CRITICAL

1

TBTROM:PROG

341S3919

IC,EPROM,Falcon RIDGE(V13.9)J44/45

U2890

CRITICAL

1

TBTROM:BLANK

IC,SERIAL SPI FLASH ROM,4MBIT,50MHZ,USON

335S0915

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

BOM Configuration

<SCH_NUM>

3 OF 118

3 OF 81

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

-----------------------

817-0688

860-1687

806-6194806-6192806-6170

817-0741

-----------------------

SMT GND TEST PONTS

|

-----------------------

|

J45 POGO PINS

APN 806-2247

||

|

J45 THERMAL MODULE STANDOFF

|

-----------------------

|

| |

|

| |

|

Frame Holes

| | |

| |

|

| |

860-1328

|

860-1327

|

| |

| | |

|

| |

| | |

| |

|

860-1448

J45 StAND OFF

STDOFF-4.5OD1.8H-SM

SH0425

1

STDOFF-4.5OD1.9H-SM

SH0424

1

2.8R2.3

ZT0415

1

STDOFF-4.5OD1.8H-SM

SH0423

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0431

1

TH-NSP

SL-1.1X0.45-1.4x0.75

ZT0470

1

SHLD-J44-MLB

SM

OMIT_TABLE

SH0450

1

SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0432

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0433

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0435

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0436

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0434

1

TH-NSP

SL-1.1X0.45-1.4x0.75

ZT0471

1

TH-NSP

SL-1.1X0.45-1.4x0.75

ZT0472

1

SL-1.1X0.45-1.4x0.75

TH-NSP

ZT0474

1

TH-NSP

SL-1.1X0.45-1.4x0.75

ZT0475

1

TH-NSP

SL-1.1X0.45-1.4x0.75

ZT0473

1

SL-2.3X3.9-2.9X4.5

TH-NSP

ZT0450

1

2.9OD1.2ID-1.35H-SM

SH0440

1

2

2.9OD1.2ID-1.35H-SM

SH0442

1

2

2.9OD1.2ID-1.35H-SM

SH0441

1

2

2.9OD1.2ID-1.35H-SM

SH0443

1

2

2.9OD1.2ID-1.35H-SM

SH0444

1

2

SMT-PAD-NSP

2.1SM2.0MM-CIR

ZT0490

1

SMT-PAD-NSP

2.1SM2.0MM-CIR

ZT0491

1

2.1SM2.0MM-CIR

SMT-PAD-NSP

ZT0492

1

TH

MLB-MTG-BRKT-J5

BR0401

1

SM

SHLD-J45-CAN-FENCE2-MDP

SH0451

1

SM

SHLD-J45-CAN-FENCE1-MDP

SH0452

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0437

1

STDOFF-4.9OD2.38H-SM-2

SH0446

1

STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2

SH0445

1

2.9OD1.2ID-1.35H-SM

SH0460

1

2

2.9OD1.2ID-1.35H-SM

SH0461

1

2

5.0OD1.85ID-2.9H

SH0427

1

2.9OD1.2ID-1.35H-SM

SH0462

1

2

2.9OD1.2ID-1.35H-SM

SH0463

1

2

2.9OD1.2ID-1.35H-SM

SH0464

1

2

2.9OD1.2ID-1.35H-SM

SH0467

1

2

2.9OD1.2ID-1.35H-SM

SH0466

1

2

2.9OD1.2ID-1.35H-SM

SH0465

1

2

5.0OD1.85ID-2.9H

SH0426

1

5.0OD1.85ID-2.9H

SH0429

1

5.0OD1.85ID-2.9H

SH0428

1

946-3819

EDGE_BOND

1

CRITICAL

D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC

CAN_COVER1, CAN_COVER2

2

806-6193 CRITICAL

CAN COVER,mDP

CRITICAL806-9391

1

SHIELD CAN, USB,J45

SH0450

825-7841

CONFIG_LABEL

CRITICAL

1

LBL,PART CONFIG,BOARDS,D2

CRITICAL

1

725-1787

PCH_INSULATOR

INSULATOR,PCH,J15

CPU_INSULATOR

CRITICAL

1

725-1877

INSULATOR,CPU,J45

CRITICAL

REAR_INSULATOR

1

725-1807

INSULATOR,REAR,MLB,J45

PD Parts

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

GND

<SCH_NUM>

4 OF 118

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IN IN IN

IN

IN IN IN IN IN

OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

SYM 10 OF 12

EDP

DIGITAL DISPLAY INTERFACES

FDI

EDP_TXN0

DDIC_TXP2

FDI_TXP1

FDI_TXN1

FDI_TXP0

FDI_TXN0

EDP_DISP_UTIL

EDP_RCOMP

DDIB_TXN0

DDIC_TXN1

DDIC_TXP0

DDIC_TXN0

DDIB_TXN3

DDIB_TXP2

EDP_TXP1

EDP_TXP0

EDP_TXN1

EDP_AUXP

EDP_HPD

EDP_AUXN

DDID_TXP1

DDID_TXN1

DDID_TXP0

DDID_TXN0

DDID_TXP3

DDID_TXN3

DDID_TXP2

DDID_TXN2

DDIC_TXP1 DDIC_TXN2

DDIC_TXN3 DDIC_TXP3

DDIB_TXP0 DDIB_TXN1 DDIB_TXP1 DDIB_TXN2

DDIB_TXP3

RESERVED

SYM 12 OF 12

DAISY_CHAIN_NCTF

RSVD132 RSVD133 RSVD134 RSVD135 RSVD136 RSVD137 RSVD138 RSVD139

DAISY_CHAIN_NCTF

TP

NC NC NC NC NC NC NC NC

IN IN IN IN

IN

OUT

IN

SYM 1 OF 12

FDI

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_RCOMP

DISP_INT

FDI_CSYNC

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

DMI_RX0* DMI_RX1* DMI_RX2* DMI_RX3*

DMI_RX0

DMI_RX2 DMI_RX3

DMI_TX0* DMI_TX1* DMI_TX2* DMI_TX3*

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

DMI_RX1

IN IN IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU Daisy-Chain Strategy:

NO_TESTNO_TEST

Port D pins out of order to match Intel symbol.

Other corner test signals connected in

Each corner of CPU has two testpoints.

daisy-chain fashion. Continuity should exist between both TP’s on each corner.

28 70 74

70

28 70 74

70

28 70 74

70

BGA

OMIT_TABLE

HASWELL

U0500

C25

A25

C24

A24

D25

B25

D24

B24

C21

A21

C20

A20

D21

B21

D20

B20

C17

A17

C16

A16

D17

B17

D16

B16

F15 F14

E12

E14

AG6

C14 A12

D14 B12

C12

A14

D12

B14

24.9

402

MF-LF

1/16W

1%

R0530

1

2

402

MF-LF

1/16W

5%

10k

R0531

1

2

BGA

OMIT_TABLE

HASWELL

U0500

A3 A4

A51 A52 A53

B2 B3

B52 B53 B54

BC1

BC54

BD1

BD54

BE1 BE2

BE3 BE52 BE53 BE54

BF2

BF3

BF4

BF51 BF52 BF53

C1 C2 C3

C54 D1

D54

AD45

AE9

AF9

AG45

AN35 AN37

G14 G17

TP-P6

TP0500

1

TP-P6

TP0501

1

TP-P6

TP0511

1

TP-P6

TP0531

1

TP-P6

TP0510

1

TP-P6

TP0520

1

TP-P6

TP0530

1

TP-P6

TP0521

1

12 74

12 72 74

12 74

12 72 74

12 74

12 72 74

24.9

1% MF-LF

1/16W 402

R0510

1

2

12 74

BGA

HASWELL

OMIT_TABLE

U0500

F12

AB2 AB3 AC3 AC1

AB1 AB4 AC4 AC2

AF2 AF4 AG4 AG2

AF1 AF3 AG3 AG1

F11

AH6

E10 C10

M2 V5 V4 V1 Y3 Y2

B10 E9 D9 B9 L5 L2 M4 L4

F10 D10

M1 Y5 V3 V2 Y4 Y1

A10 F9 C9 A9 M5 L1 M3 L3

B6 C5

T6 R6 R2 R4 T4 T1

E6 D4 G4 E3 J5 G3 J3 J2

C6 B5

T5 R5 R1 R3 T3 T2

D6 E4 G5 E2 J6 G2 J4 J1

28 70 74

70

28 70 74

70

28 70 74

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

CPU DMI/PEG/FDI/RSVD

DMI_S2N_N<2>

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<3>

DP_INT_ML_C_P<2>

DP_INT_ML_C_N<2>

PCIE_TBT_D2R_N<2>

TRUE

CPU_DC_BE53_BF53

CPU_DC_A3_B3

TRUE

CPU_DC_A4

DP_TBTSNK0_ML_C_P<0>

PPVCOMP_S0_CPU

DP_INT_ML_C_P<1>

CPU_DC_BC54

TRUE

CPU_DC_A3_B3

CPU_DC_BF51

CPU_DC_B54_C54

TRUE

DMI_S2N_N<0>

TP_PEG_D2RN<13>

TP_PEG_D2RN<7>

CPU_EDP_RCOMP

HDMI_CLK_P

PPVCCIO_S0_CPU

DP_INT_AUXCH_C_N

PPVCOMP_S0_CPU

TP_PEG_D2RN<6>

TP_PEG_D2RN<5>

TP_PEG_R2D_CP<9>

CPU_PEG_RCOMP

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_N<0>

DMI_N2S_N<2>

DMI_N2S_P<1>

DMI_N2S_N<3>

DMI_N2S_N<0> DMI_N2S_N<1>

DMI_N2S_P<3>

DMI_S2N_P<2>

PCIE_TBT_D2R_N<0>

TP_PEG_D2RN<9>

FDI_INT

FDI_CSYNC

TP_PEG_R2D_CP<15>

TP_PEG_R2D_CP<14>

TP_PEG_R2D_CP<13>

TP_PEG_R2D_CP<12>

TP_PEG_R2D_CP<11>

TP_PEG_R2D_CP<10>

TP_PEG_R2D_CP<8>

TP_PEG_R2D_CP<7>

TP_PEG_R2D_CP<6>

TP_PEG_R2D_CP<4>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_P<1> PCIE_TBT_R2D_C_P<2>

TP_PEG_R2D_CN<15>

TP_PEG_R2D_CN<14>

TP_PEG_R2D_CN<13>

TP_PEG_R2D_CN<11>

TP_PEG_R2D_CN<10>

TP_PEG_R2D_CN<8> TP_PEG_R2D_CN<9>

TP_PEG_R2D_CN<7>

TP_PEG_R2D_CN<6>

TP_PEG_R2D_CN<5>

TP_PEG_R2D_CN<4>

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<1>

TP_PEG_D2RP<14> TP_PEG_D2RP<15>

TP_PEG_D2RP<12>

TP_PEG_D2RP<11>

TP_PEG_D2RP<9> TP_PEG_D2RP<10>

TP_PEG_D2RP<7>

TP_PEG_D2RP<6>

TP_PEG_D2RP<4>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_P<0>

TP_PEG_D2RN<15>

TP_PEG_D2RN<14>

TP_PEG_D2RN<12>

TP_PEG_D2RN<10> TP_PEG_D2RN<11>

TP_PEG_D2RN<8>

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_N<1>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_P<3>

TP_PEG_R2D_CP<5>

PCIE_TBT_D2R_P<1>

DMI_N2S_P<0>

DMI_N2S_P<2>

TP_PEG_D2RN<4>

DP_INT_ML_C_N<0>

DP_TBTSNK1_ML_C_P<2>

TP_EDP_DISP_UTIL

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_P<2>

DP_INT_ML_C_P<0>

DP_INT_ML_C_N<1>

TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLP<0>

HDMI_CLK_N

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLN<2>

DP_TBTSNK1_ML_C_P<1> DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_N<3> DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK0_ML_C_N<1> DP_TBTSNK0_ML_C_P<1> DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DP_INT_AUXCH_C_P

PCIE_TBT_D2R_P<3>

TP_PEG_D2RP<5>

TP_PEG_D2RP<8>

TP_PEG_D2RP<13>

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<0>

TP_PEG_R2D_CN<12>

DP_IG_A_HPD_L

CPU_DC_A53_B53

TRUE

CPU_DC_A52_B52

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_A53_B53

TRUE

CPU_DC_A52_B52

TRUE

CPU_DC_BE3_BF3

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_B54_C54

CPU_DC_BE52_BF52

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_BE52_BF52

TRUE

CPU_DC_BE3_BF3

CPU_DC_D1

CPU_DC_D54

CPU_DC_A51

CPU_DC_BF4

CPU_DC_BC1

TRUE

CPU_DC_BE53_BF53

5 OF 81

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<SCH_NUM>

67 70 74

5

28 70 74

5 8

67 70 74

5 5

74

68 70 71 74

6 8

10 18 58

67 70 74

5 8

74

67 70 74

28 70 74

67 70 74

70

68 70 71 74

70

28 70 74

67 70 74

70

20

5

w w w . c h i n a f i x . c o m

BI BI BI BI BI

IN

OUT

BI

NC

OUT

BI

SYM 2 OF 12

CLOCK

JTAG

PWR

DDR3

THERMAL

THERMTRIP*

PM_SYNC

PWRGOOD

SM_DRAMPWROK

PLTRSTIN*

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

SM_DRAMRST*

PRDY* PREQ*

TCK TMS

TRST*

TDI TDO

DBR*

BPM0* BPM1*

BPM3*

BPM2*

BPM4* BPM5* BPM6* BPM7*

PECI

PROC_DETECT*

PROCHOT*

CATERR*

DPLL_REF_CLKN DPLL_REF_CLKP

BCLKN BCLKP

SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP

OUT

IN IN

SYM 11 OF 12

RESERVED

RSVD_TP28

RSVD_TP27

RSVD_TP39

RSVD_TP38

RSVD11

RSVD_TP1 RSVD_TP2

RSVD51 RSVD52

RSVD50

RSVD16

RSVD42

RSVD41

RSVD10

RSVD9

RSVD95

RSVD94

RSVD93

RSVD92

CFG_RCOMP

CFG16

CFG19

CFG18 CFG17

VSS_H54

VSS_H52

VSS_H51

VSS_H53

VCC_F22

VSS_G19

VSS_F52

VSS_F51

TESTLO_F21

CFG0 CFG1

CFG6

CFG5

CFG2 CFG3 CFG4

TESTLO_F20

CFG11

CFG10

CFG9

CFG8

CFG7

CFG12

CFG14

CFG13

CFG15

RSVD_TP17 RSVD_TP18

RSVD_TP37

RSVD_TP36

RSVD_TP35

RSVD_TP23

RSVD_TP3 RSVD_TP4

RSVD47 RSVD48 RSVD49

RSVD_TP26

RSVD_TP25

RSVD_TP24

NC

IN

OUT

IN IN

IN

OUT

IN

OUT

BI BI BI

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

These can be placed close to

J1800 and only for debug access

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU) (IPU) (IPU)

(IPD)

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

18 74

PLACE_NEAR=U0500.F50:157mm

402

MF-LF

1/16W

5%

10K

R0611

1

2

12 21 74

14 18 74

14 42 74

PLACE_NEAR=U0500.BB52:12.7mm

100

1% 1/16W MF-LF 402

R0614

1

2

75

1% 1/16W MF-LF 402

PLACE_NEAR=U0500.BB53:12.7mm

R0613

1

2

100

1% 1/16W MF-LF 402

PLACE_NEAR=U0500.BB51:12.7mm

R0612

1

2

41 74

5% 1/16W MF-LF

402

62

R0601

1

2

402

MF-LF

5%

56

1/16W

R0603

12

41 42 58 74

BGA

HASWELL

OMIT_TABLE

U0500

AB6 AA6

R51 R50 P49 N50 R49 P53 U51 P51

G50

F53

AC6 AE6

G51

L54

D52

N53 N52

C51

E50

F50

AP48

BE51

BB51 BB53 BB52

V6 Y6

N54

N49 M49

D53

M51 M53

21

11 74

HASWELL

OMIT_TABLE

BGA

U0500

AG49 AD49

Y53 W53 U53 V54 R53 R52

Y52

Y51

V53

V52

AC49 AE49

Y50

AB49

V51 W51 Y49 Y54

R54

AH49

AL6

AM48

AU26

AU27

B50

BC4

BD4

E5

F16

F8

G53 H50

L49

L50 N51

A5 A6

BD3

BE4

E1

F1

F24 F25

F6

G10

G12

G21 G24

G6

L51

L52 L53

F20

F21

F22

F51 F52

G19

H51 H52

H53

H54

MF-LF 402

1/16W

1%

49.9

R0690

1

2

49.9

1% 1/16W MF-LF

402

R0680

1

2

49.9

1% 1/16W MF-LF

402

R0685

1

2

402

MF-LF

5%

1K

1/16W

NOSTUFF

R0649

1

2

MF-LF 402

1/16W

5%

NOSTUFF

1K

R0643

1

2

NOSTUFF

1K

5% 1/16W MF-LF

402

R0641

1

2

NOSTUFF

1K

5% 1/16W MF-LF 402

R0640

1

2

NOSTUFF

1K

5% 1/16W MF-LF

402

R0647

1

2

1K

5% 1/16W MF-LF

402

CPUCFG6_PD

R0646

1

2

1K

5% 1/16W MF-LF 402

CPUCFG5_PD

R0645

1

2

402

MF-LF

1/16W

5%

EDP:YES

1K

R0644

1

2

402

MF-LF

1/16W

5%

1K

NOSTUFF

R0642

1

2

3.32K

402

MF-LF

1/16W

1%

PLACE_NEAR=U0500.AP48:51.562mm

R0621

1

2

402

MF-LF

1/16W

5%

1K

NOSTUFF

R0648

1

2

18 71 74

1.82K

PLACE_NEAR=R0621.2:1mm

1% 1/16W MF-LF

402

R0620

1

2

12 74

14

18 19 74

18 74

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

CPU Clock/Misc/JTAG/CFG

CPUPEG:X16

CPUPEG:X8X8

CPUCFG5_PD

CPUPEG:X8X4X4

CPUCFG6_PD,CPUCFG5_PD

PP1V35_S3RS0_CPUDDR

PPVCCIO_S0_CPU

CPU_PROCHOT_L

CPU_CFG<9> CPU_CFG<3>

CPU_CFG<16>

CPU_CFG<1> CPU_CFG<0>

CPU_CFG<7> CPU_CFG<6>

CPU_RESET_L

CPU_PWRGD

CPU_CLK135M_DPLLREF_N

PM_THRMTRIP_L

TP_CPU_RSVD_TP17

CPU_CFG<18>

TP_CPU_RSVD_TP39

TP_CPU_RSVD_TP38

TP_CPU_RSVD_TP25 TP_CPU_RSVD_TP26

TP_CPU_RSVD_TP28

TP_CPU_RSVD_TP27

CPU_CFG<19>

CPU_TESTLO_F20

CPU_CFG<0>

TP_CPU_RSVD_TP18

CPU_TESTLO_F21

TP_CPU_RSVD_TP47

TP_CPU_RSVD_TP23

TP_CPU_RSVD_TP3

CPU_CFG_RCOMP

CPU_CFG<5> CPU_CFG<4>

CPU_CFG<9> CPU_CFG<10>

CPU_CFG<2>

CPU_CFG<16>

CPU_CFG<17>

CPU_CFG<3>

XDP_CPU_PRDY_L

XDP_CPU_TMS

XDP_DBRESET_L

XDP_BPM_L<0> XDP_BPM_L<1>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6>

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPUPCH_TRST_L

TP_CPU_RSVD_TP24

TP_CPU_RSVD_TP35

CPU_CFG<4>

CPU_CFG<1> CPU_CFG<2>

CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8>

CPU_CFG<11> CPU_CFG<12>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<15>

TP_CPU_RSVD_TP36

TP_CPU_RSVD_TP4

TP_CPU_RSVD_TP1

TP_CPU_RSVD_TP48 TP_CPU_RSVD_TP49

TP_CPU_RSVD_TP37

PPVCC_S0_CPU

CPU_SM_RCOMP<1>

CPU_SM_RCOMP<0>

PM_SYNC

CPU_CLK135M_DPLLREF_P

CPU_CLK135M_DPLLSS_N CPU_CLK135M_DPLLSS_P

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

CPU_PECI

TP_CPU_RSVD_TP2

CPU_CATERR_L

CPU_PROCHOT_R_L

XDP_CPU_TCK

XDP_CPU_PREQ_L

CPU_MEM_RESET_L

CPU_SM_RCOMP<2>

XDP_BPM_L<7>

PM_MEM_PWRGD

<SCH_NUM>

6 OF 118

6 OF 81

8

10 21 65 66 69 81

5 8

10 18 58

6

18 74

6

18 71 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 71 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

8

10 46 59 69 71

74

w w w . c h i n a f i x . c o m

OUT

NC

NC NC

NC

NC NC NC

NC

NCNC

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SYM 3 OF 12

MEMORY CHANNEL A

SA_DQ12

SA_DQ11

SA_DQ8

SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24

SA_CKP3

SA_CKN3

SA_CKP2

SA_CKP1

SA_CKN1

SA_CKP0

SA_CKN0

SA_CKE1

SA_CS1*

SA_DQ20

SM_VREF

SA_DQSN7

SA_DQSN6

SA_DQSN5

SA_DQSN4

SA_DQSN3

SA_DQSN2

SA_DQSN1

SA_DQSN0

SA_DQS7

SA_DQS6

SA_DQS4 SA_DQS5

SA_DQS3

SA_DQS2

SA_DQS1

SA_DQS0

SA_MA13

SA_MA12

SA_MA11

SA_MA9

SA_MA8

SA_MA7

SA_MA5 SA_MA6

SA_MA4

SA_MA2 SA_MA3

SA_MA0 SA_MA1

SA_CAS*

SA_WE*

VSS_BC21

SA_RAS*

SA_BS1 SA_BS2

SA_ODT3

SA_BS0

SA_ODT2

SA_ODT1

SA_ODT0

SA_CS3*

SA_CS2*

SA_CS0*

SA_CKE3

SA_CKE2

SA_CKE0

SA_DQ30

SA_DQ0 SA_DQ1 SA_DQ2

SA_DQ9

SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19

SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58

SA_DQ61 SA_DQ62 SA_DQ63

SA_DQ4

SA_DQ3

SA_DQ10

SA_DQ7

SA_DQ5 SA_DQ6

SA_DQ47

SA_DQ46

SA_DQ45

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

RSVD25

RSVD162

RSVD165

RSVD168

SA_CKN2

SA_MA10

SA_MA14 SA_MA15

RSVD170

RSVD169

RSVD167

RSVD166

RSVD164

RSVD163

SA_DQ59 SA_DQ60

RSVD161

RSVD160

SYM 4 OF 12

MEMORY CHANNEL B

SB_DQ29

SB_DQ28

RSVD171

SB_CKN0

SB_CKE0

RSVD181

RSVD180

RSVD179

RSVD178

RSVD177

RSVD176

RSVD175

RSVD174

RSVD173

RSVD172

SB_DQSN3

SB_DQSN6

SB_DQS0 SB_DQS1

SB_DQS5

SB_DQS3 SB_DQS4

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7

SB_CKE1 SB_DQ8 SB_DQ9 SB_DQ10

SB_CKE2 SB_DQ11

SB_DQ12 SB_DQ13 SB_DQ14 SB_CKE3 SB_DQ15 SB_DQ16 SB_CS0* SB_DQ17 SB_CS1* SB_DQ18 SB_CS2* SB_DQ19 SB_CS3* SB_DQ20

SB_ODT0 SB_DQ21

SB_ODT1 SB_DQ22

SB_ODT2 SB_DQ23

SB_ODT3 SB_DQ24

SB_DQ25

SB_BS0

SB_DQ26

SB_BS1

SB_DQ27

SB_DQ30

SB_RAS*

SB_WE*

SB_CAS*

SB_MA0 SB_MA1

SB_DQ36

SB_MA2

SB_DQ37

SB_MA3

SB_DQ38

SB_MA4

SB_DQ39

SB_MA5

SB_DQ40

SB_MA6

SB_DQ41

SB_MA7

SB_DQ42

SB_MA8

SB_DQ43

SB_MA9

SB_DQ44

SB_MA10 SB_DQ45

SB_MA11 SB_DQ46

SB_MA12 SB_DQ47

SB_MA13 SB_DQ48

SB_MA14 SB_DQ49

SB_MA15 SB_DQ50

SB_DQ51

SB_DQSN0

SB_DQ52

SB_DQSN1

SB_DQ53

SB_DQSN2

SB_DQ54 SB_DQ55

SB_DQSN4

SB_DQ56

SB_DQSN5

SB_DQ57 SB_DQ58

SB_DQSN7

SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_DQS2

SB_DQS6

SB_DQS7

SB_CKP0

SB_CKN1

SB_CKP1

SB_CKN2

SB_CKP2

SB_CKN3

SB_CKP3

SB_BS2

VSS_AU30

BI

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI

BI

BI BI

NC

NC NC

NC NC NC

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

22 74

22

23 24 77

25 26 77

23 27 77

24 27 77

23 24 27 77

BGA

HASWELL

OMIT_TABLE

U0500

AU39

AU40 AV39

AV40

AW39

AW40

AY39

AY40 BA39

BA40

BC53

BD31

BC20 BD21 BD32

BE21

BE34

BF34

BC34

BD34

BE25

BD25

BE23

BD23

BF25

BC25

BF23

BC23

BE16 BC17 BE17 BD16

AR6

AH54 AH52

AR51 AR53 AN53 AN51 AR52 AR54 AV52 AV53 AY52 AY51

AK51

AV51 AV54 AY54 AY53 AY47 AY49 BA47 BA45 AY45 AY43

AK54

BA49 BA43 BF14 BC14 BC11 BF11 BE14 BD14 BD11 BE11

AH53

BC9 BE9 BE6 BC6 BD9 BF9 BE5 BD6 BB4 BC2

AH51

AW3 AW2 BB3 BB2 AW4 AW1 AU3 AU1 AR1 AR4

AK52

AU2 AU4 AR2 AR3

AK53 AN54 AN52

AJ53 AP52 AW53 BA46 BE12 BD7 BA2 AT3

AJ52 AP53 AW52 AY46 BD12 BE7 BA3 AT2

BD28 BD27

BD20 BF31 BC31 BE20 BE32 BE31

BF28 BE28 BF32 BC27 BF27 BC28 BE27 BC32

BC16 BF16 BF17 BD17

BF20 BF21

AN6

AM6

BC21

BGA

HASWELL

OMIT_TABLE

U0500

AY36

BC37

BC39

BD37

BD38

BD39

BE37

BE38

BE39 BF37

BF39

AY23 BA23 BA36

AV20

AU36

AU35

AV35

AV36

AW27

AW26

BA26

BA27

AV27

AV26

AY26

AY27

BA20 AY19 AU19 AW20

AC54 AC52

AV43 AV45 AU43 AU45 AV47 AV49 BC49 BE49 BD47 BC47

AE51

BD49 BD50 BE47 BF47 BE44 BD44 BC42 BF42 BF44 BC44

AE54

BD42 BE42 BA16 AU16 BA15 AV15 AY16 AV16 AY15 AU15

AC53

AU12 AY12 BA10 AU10 AV12 BA12 AY10 AV10

AU8 BA8

AC51

AV6 BA6 AV8 AY8 AU6 AY6 AM2 AM3 AK1 AK4

AE52

AM1 AM4 AK2 AK3

AE53 AU47 AU49

AD53 AV46 BE48 BE43 AW15 AW12 AW6 AL3

AD52 AU46 BD48 BD43 AW16 AW10 AW8 AL2

BA30 AW30

AU23 AY35 AW35 AU20 AW36 BA35

AY30 AV30 AW32 AY32 AT30 AV32 BA32 AU32

AY20 BA19 AV19 AW19

AV23 AW23

AU30

23 24 77

24 27 77

23 27 77

24 27 77

23 27 77

23 24 27 77

25 27 77

26 27 77

25 27 77

25 26 27 77

26 27 77

25 27 77

26 27 77

25 26 27 77

25 26 77

CPU DDR3 Interfaces

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

MEM_A_DQ<2> MEM_A_DQ<3>

MEM_A_CS_L<1>

MEM_A_DQ<45>

MEM_A_DQ<54>

MEM_A_DQ<51>

MEM_A_DQ<53>

MEM_A_DQ<0> MEM_A_DQ<1>

MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13>

MEM_A_DQ<15> MEM_A_DQ<16>

MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44>

MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50>

MEM_A_DQ<52>

MEM_A_DQ<55> MEM_A_DQ<56>

MEM_A_DQ<61>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<19>

MEM_B_DQ<17>

MEM_B_DQ<15>

MEM_B_DQ<20>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<25>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<51>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<61>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_A_DQ<60>

MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CKE<0>

MEM_B_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CKE<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_RAS_L MEM_B_WE_L MEM_B_CAS_L

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>

MEM_A_CLK_N<0> MEM_A_CLK_P<0> MEM_A_CKE<0>

MEM_A_CLK_N<1> MEM_A_CLK_P<1> MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_ODT<0> MEM_A_ODT<1>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_WE_L MEM_A_CAS_L

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<5> MEM_A_DQS_N<6>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQ<17>

MEM_A_DQ<14>

CPU_DIMMB_VREFDQ

CPU_DIMMA_VREFDQ

MEM_B_DQ<52>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

CPU_DIMM_VREFCA

MEM_B_DQ<16>

MEM_B_DQ<18>

<SCH_NUM>

7 OF 118

7 OF 817 OF 81

7 OF 118

<SCH_NUM>

w w w . c h i n a f i x . c o m

BI

OUT

IN

SYM 5 OF 12

RSVD68

VIDSOUT

VIDSCLK

VIDALERT*

RSVD79(VSS)

RSVD78 VSS_V50(RSVD)

VSS_AP50(RSVD)

VSS_AP49(RSVD)

VSS_AN49(RSVD)

VSS_AM50(RSVD)

IVR_ERROR

VSS_AK49(RSVD)

VSS_AJ49(RSVD)

VSS_AJ50(RSVD)

VSS_AG50(RSVD)

VSS_AD50(RSVD)

VSS_AB50(RSVD)

FC_F17

RSVD65

RSVD69

RSVD67

RSVD66

RSVD74

RSVD73

RSVD72

RSVD71

RSVD70

VCC_L6 VCC_M6

VCOMP_OUT

VCC_SENSE

VSS_B51

FC_D5 FC_D3

VDDQ

VCC

VCCIO_OUT

RSVD76

RSVD75

VSS_E52

PWR_DEBUG

RSVD64

SYM 6 OF 12

POWER

VCC VCC

IN

OUT

NC NC NC NC

NC NC

NC NC NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Max load: 300mA

Connections would be required for 2014 CPU support.

R0802.2:

R0800.2:

R0810.2:

Max load: 300mA

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

0

5% 1/16W MF-LF

402

R0812

1 2

58 74

110

PLACE_NEAR=U0500.J50:2.54mm

402

1/16W

1% MF-LF

R0802

1

2

0

402

5%

MF-LF

1/16W

R0811

1 2

58 74

PLACE_NEAR=U0500.J53:38mm

5%

402

MF-LF

1/16W

43

R0810

1 2

58 74

PLACE_NEAR=R0810.1:2.54mm

75

1% 1/16W MF-LF

402

R0800

1

2

OMIT_TABLE

HASWELL

BGA

U0500

D3

D5

F17

AM49

F19

AH9

AN18

AN22

AN31

AN33

AR49

J12

J17 J21 J26 J31

U49

V49

W49

W9

A36 A38 A39 A42 A43 A45 A46

A48 AA46 AA47

AA8

AA9

B43 B45 B46 B48 C27 C28 C31 C32 C34 C36 C38 C39 C42 C43 C45 C46 C48 D27 D28 D31 D32 D34 D36 D38 D39 D42 D43 D45 D46 D48 E27 E28 E31 E32 E34 E36 E38 E39 E42 E43 E45 E46 E48 F27 F28 F31 F32 F34 F36 F38 F39 F42 F43 F45 F46 F48 G27 G29 G31 G32 G34 G36 G38 G39 G42 G43 G45 G46 G48 H11 H12 H13 H14 H16 H17 H18 H19 H20 H21 H23 H24 H25 H26 H27 H29

L6 M6

C50

D51

AK6

AR29 AR31 AR33 AT13 AT19 AT23 AT27 AT32 AT36 AV37 AW22 AW25 AW29 AW33 AY18 BB21 BB22 BB26 BB27 BB30 BB31 BB34 BB36 BD22 BD26 BD30 BD33 BE18 BE22 BE26 BE30 BE33

J53

J52

J50

AB50

AD50

AG50

AJ49

AJ50

AK49

AM50

AN49

AP49

AP50

B51

E52

V50

OMIT_TABLE

HASWELL

BGA

U0500

A27

A28

A31

A32

A34

AB45

AB46

AB8

AC46

AC47

AC8

AC9

AD46

AD8

AE46

AE47

AE8

AF8

AG46

AG8

AH46

AH47

AH8

AJ45

AJ46

AK46

AK47

AK8

AL45

AL46

AL8

AL9

AM46

AM47

AM8

AM9

AN10

AN12

AN13

AN14

AN15

AN16

AN17

AN19

AN20

AN21

AN23

AN24

AN25

AN26

AN27

AN29

AN30

AN32

AN34

AN36

AN38

AN39

AN40

AN41

AN42

AN43

AN44

AN45

AN46

AN8

AN9

AP10

AP12

AP13

AP14

AP15

AP16

AP17

AP18

AP19

AP20

AP21

AP22

AP23

AP24

AP25

AP26

AP27

AP29

AP30

AP31

AP32

AP33

AP34

AP35

AP36

AP37

AP38

AP39

AP40

AP41

AP42

AP43

AP44

AP46

AP47

AP8

AP9

AR35

AR37

AR39

AR41

AR43

AR45

AR46

B27

B28

B31

B32

B34

B36

B38

B39

B42

H30

H31

H32

H33

H34

H36

H37

H38

H39

H40

H42

H43

H45

H46

H48H8H9

J10

J14

J19

J24

J29

J33

J36

J37

J38

J39

J40

J42

J43

J45

J46

J48J8J9

K38

K40

K43

K44

K45

K46

K48K8K9

L37

L38

L39

L40

L42

L43

L44

L46

L47L8M37

M38

M39

M40

M42

M43

M44

M45

M46M8M9

N37

N38

N39

N40

N42

N43

N44

N46

N47N8N9

P45

P46P8R46

R47R8R9

T45

T46

U46

U47U8U9

V45

V46V8W46

W47W8Y45

Y46

Y8

18

PLACE_NEAR=U0500.C50:50.8mm

PLACE_SIDE=BOTTOM

100

1/16W MF-LF

402

5%

R0860

1

2

58 74

CPU Power

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

CPU_VIDSCLK

CPU_VIDSCLK_R

PPVCC_S0_CPU

CPU_VCCSENSE_P

TP_CPU_RSVD_TP78

TP_CPU_RSVD_TP76

TP_CPU_RSVD_TP75

PPVCC_S0_CPU

PP1V35_S3RS0_CPUDDR

CPU_PWR_DEBUG

CPU_VIDSOUT

TP_CPU_FC_VCCST_PWRGD

TP_CPU_FC_VCCST

CPU_VIDALERT_L

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVCOMP_S0_CPU

TP_CPU_IVR_ERROR

CPU_VIDALERT_R_L

CPU_VIDSOUT_R

PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

<SCH_NUM>

8 OF 81

8 OF 118

6 8

10 46 59 69 71

6 8

10 46 59 69 71

6

10 21 65 66 69 81

5

5 6

10 18 58

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

SYM 7 OF 12

GROUND

VSS VSS

SYM 8 OF 12

GROUND

VSSVSS

SYM 9 OF 12

VSS_P9(RSVD)

VSS_G18(RSVD)

VSS_AR22(RSVD)

VSS_AB48(RSVD)

VSS_NCTF

VSS_SENSE

VSS

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BGA

OMIT_TABLE

HASWELL

U0500

A11 A15 A19 A22 A26 A30 A33 A37 A40 A44 AA1 AA2 AA3 AA4

AA48

AA5 AA7

AB5 AB51 AB52 AB53 AB54

AB7

AB9 AC48

AC5 AC50

AC7 AD48 AD51 AD54

AD7

AD9

AE1

AE2

AE3

AE4 AE48

AE5 AE50

AE7

AF5

AF6

AF7 AG48

AG5 AG51 AG52 AG53 AG54

AG7

AG9

AH1

AH2

AH3

AH4 AH48

AH5 AH50

AH7

AJ48 AJ51 AJ54 AK48 AK5 AK50 AK7 AK9 AL1 AL4 AL48 AL5 AL7 AM5 AM51 AM52 AM53 AM54 AM7 AN1 AN2 AN3 AN4 AN48 AN5 AN50 AN7 AP51 AP54 AP7 AR12 AR14 AR16 AR18 AR20 AR24 AR26 AR48 AR5 AR50 AR7 AR8 AR9 AT1 AT10 AT12 AT15 AT16 AT18 AT20 AT22 AT25 AT26 AT29 AT33 AT35 AT37 AT39 AT4

BGA

OMIT_TABLE

HASWELL

U0500

AT40 AT42 AT43 AT45 AT46 AT47 AT49

AT5 AT50 AT51 AT52 AT53 AT54

AT6

AT8

AT9 AU13 AU18 AU22 AU25 AU29 AU33 AU37 AU42

AU5

AU9

AV1 AV13 AV18

AV2 AV22 AV25 AV29

AV3 AV33

AV4 AV42

AV5 AV50

AV9 AW13 AW18 AW37 AW42 AW43 AW45 AW46 AW47 AW49

AW5 AW50 AW51 AW54

AW9 AY13 AY22 AY25 AY29 AY33 AY37 AY42

AY50 AY9 B11 B15 B19 B22 B26 B30 B33 B37 B40 B44 B49 B8 BA13 BA18 BA22 BA25 BA29 BA33 BA37 BA4 BA42 BA5 BA50 BA51 BA52 BA53 BA9 BB10 BB11 BB12 BB14 BB15 BB16 BB17 BB18 BB20 BB23 BB25 BB28 BB32 BB33 BB37 BB38 BB39 BB41 BB42 BB43 BB44 BB46 BB47 BB48 BB49 BB5 BB6 BB7 BB9

BGA

OMIT_TABLE

HASWELL

U0500

AB48

AR22

BC10

BC12

BC15

BC18

BC22

BC26

BC3

BC30

BC33

BC36

BC38

BC41

BC43

BC46

BC48

BC5

BC50

BC52

BC7

BD10

BD15

BD18

BD36

BD41

BD46

BD5

BD51

BE10

BE15

BE36

BE41

BE46

BF10

BF12

BF15

BF18

BF22

BF26

BF30

BF33

BF36

BF38

BF41

BF43

BF46

BF48

BF7

C11

C15

C19

C22

C26

C30

C33

C37C4C40

C44

C49

C52C8D11

D15

D19

D22

D26

D30

D33

D37

D40

D44

D49D8E11

E15

E16

E17

E19

E20

E21

E22

E24

E25

E26

E30

E33

E37

E40

E44

E49

E51

E53

E8

F2

F26F3F30

F33

F37F4F40

F44

F49F5G11

G13

G16

G18

G20

G23

G25

G26

G30

G33

G37

G40

G44

G49

G52

G54G7G8G9H44

H49H7J44

J49

J51

J54J7K1K2K3K4K5K6K7

L48L7L9

M48

M50

M52

M54M7N48

N7

A49

A50A8B4

BA1

BA54

BB1

BB54

BD2

BD53

BF49

BF5

BF50

BF6

C53D2E54

F54

G1

P1P2P3P4P48P5P50

P52

P54P6P7P9R48

R7

D50

T48U1U2U3U4

U48U5U50

U52

U54U6U7

V48V7V9

W48

W50

W52

W54W7Y48Y7Y9

58 74

100

5% 1/16W MF-LF 402

PLACE_SIDE=BOTTOM

PLACE_NEAR=U0500.D50:50.8mm

R0960

1

2

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

CPU Ground

CPU_VCCSENSE_N

<SCH_NUM>

9 OF 118

9 OF 81

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Apple Implementation: 8x 210uF(2x nostuff) 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402

PLACEMENT_NOTE (C1024-C1045):

PLACEMENT_NOTE (C1020-C1023):

PLACEMENT_NOTE (C1000-C1019):

Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU)

CPU VCORE Decoupling

CAPs for Acoustic control (C109A-C102D)

PLACEMENT_NOTE (C1046-C1067):

CPU VDDQ Decoupling

Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups) Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)

PLACEMENT_NOTE (C1098-C1099):

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

CPU VCCIO Decoupling

PLACEMENT_NOTE (C1090-C1097):

PLACEMENT_NOTE (C1080-C1089):

CAPs for Acoustic control (C102E-C103F)

Apple Implementation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.

PLACEMENT_NOTE (C1068-C1076:

0402

1UF

X6S-CERM

10V

10%

Place on bottom side of U0500

C1009

1

2

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1008

1

2

0402

Place on bottom side of U0500

10%

1UF

10V X6S-CERM

C1007

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1031

1

2

10% 10V X6S-CERM

Place on bottom side of U0500

1UF

0402

C1006

1

2

Place on bottom side of U0500

1UF

10%

0402

X6S-CERM

10V

C1005

1

2

1UF

10% 10V X6S-CERM

Place on bottom side of U0500

0402

C1004

1

2

0402

Place on bottom side of U0500

1UF

10V

10% X6S-CERM

C1003

1

2

Place on bottom side of U0500

10V

10%

1UF

0402

X6S-CERM

C1002

1

2

0402

Place on bottom side of U0500

10V

10%

1UF

X6S-CERM

C1001

1

2

0402

Place on bottom side of U0500

1UF

10V

10% X6S-CERM

C1000

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1030

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1029

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1027

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1026

1

2

20%

NO STUFF

Place near U0500 on bottom side

20UF

X5R-CERM

4V 0402-2

C1020

1

2

NO STUFF

20%

Place near U0500 on bottom side

20UF

X5R-CERM

4V 0402-2

C1021

1

2

NO STUFF

20%

Place near U0500 on bottom side

20UF

X5R-CERM

4V 0402-2

C1022

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C109A

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1025

1

2

NO STUFF

CRITICAL

20%

20UF

X5R-CERM

4V 0402-2

C1024

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL 20UF

X5R-CERM

4V 0402-2

C1028

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1032

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1033

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1039

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1038

1

2

NO STUFF

CRITICAL

20%

Place near inductors on bottom side.

20UF

X5R-CERM

4V 0402-2

C1037

1

2

NO STUFF

Place near inductors on bottom side.

20%

CRITICAL 20UF

X5R-CERM

4V 0402-2

C1036

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1035

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1034

1

2

X7R-CERM 0402

16V

0.01UF

10%

C1079

1

2

X6S-CERM 0402

10% 10V

1UF

Place on bottom side of U0500

C1089

1

2

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1088

1

2

X6S-CERM 0402

10%

Place on bottom side of U0500

10V

1UF

C1087

1

2

1UF

10V 0402

Place on bottom side of U0500

10% X6S-CERM

C1086

1

2

X6S-CERM

1UF

0402

Place on bottom side of U0500

10% 10V

C1085

1

2

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

C1084

1

2

10V 0402

Place on bottom side of U0500

1UF

X6S-CERM

10%

C1083

1

2

1UF

X6S-CERM 0402

Place on bottom side of U0500

10V

10%

C1082

1

2

0402

Place on bottom side of U100.

1UF

X6S-CERM

10V

10%

C1081

1

2

X6S-CERM 0402

Place on bottom side of U0500

10%

1UF

10V

C1080

1

2

Place near U0500 on bottom side

20%

10UF

0603

X6S-CERM

4V

C1093

1

2

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1092

1

2

10UF

20% 4V

0603

Place near U0500 on bottom side

X6S-CERM

C1091

1

2

20%

Place near U0500 on bottom side

10UF

0603

4V X6S-CERM

C1090

1

2

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1097

1

2

20%

Place near U0500 on bottom side

10UF

4V 0603

X6S-CERM

C1096

1

2

0603

20%

Place near U0500 on bottom side

10UF

X6S-CERM

4V

C1095

1

2

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1094

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL 20UF

X5R-CERM

4V 0402-2

C1043

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL 20UF

X5R-CERM

4V 0402-2

C1042

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1041

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1040

1

2

20%

CRITICAL

330UF-6MOHM

2.0V D15T-ECGLT-COMBO

POLY-TANT

C1098

1

23

D15T-ECGLT-COMBO

CRITICAL

2.0V

20%

330UF-6MOHM

POLY-TANT

C1099

1

23

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1019

1

2

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1018

1

2

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1017

1

2

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1016

1

2

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1015

1

2

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

C1014

1

2

0402

Place on bottom side of U0500

X6S-CERM

10% 10V

1UF

C1013

1

2

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1012

1

2

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1011

1

2

0402

10% 10V

Place on bottom side of U0500

X6S-CERM

1UF

C1010

1

2

Place near inductors on bottom side.

CRITICAL

X5R-CERM 0402-2

4V

20UF

20%

C1065

1

2

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

CRITICAL

C1064

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1063

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1062

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1061

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1060

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1059

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1058

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1057

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1056

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1055

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1054

1

2

Place near inductors on bottom side.

CRITICAL

X5R-CERM 0402-2

4V

20UF

20%

C1053

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1052

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1051

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1050

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1049

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1048

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1047

1

2

CRITICAL

X5R-CERM 0402-2

4V

20UF

20%

C1046

1

2

CRITICAL

Place near inductors on bottom side.

20% 4V X5R-CERM 0402-2

20UF

C1045

1

2

CRITICAL

Place near inductors on bottom side.

20% 4V X5R-CERM 0402-2

20UF

C1044

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1067

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1066

1

2

POLY-TANT

2.5V

20%

210UF

CASE-B2S

CRITICAL

C1068

1

2

POLY-TANT CASE-B2S

20%

210UF

CRITICAL

2.5V

C1069

1

2

CASE-B2S

2.5V

20%

210UF

CRITICAL

POLY-TANT

C1070

1

2

20%

2.5V CASE-B2S

CRITICAL 210UF

POLY-TANT

NO STUFF

C1071

1

2

POLY-TANT

2.5V

210UF

CRITICAL

20%

CASE-B2S

C1072

1

2

POLY-TANT CASE-B2S

210UF

CRITICAL

2.5V

20%

NO STUFF

C1073

1

2

CRITICAL

CASE-B2S

2.5V

210UF

POLY-TANT

20%

C1074

1

2

20%

210UF

2.5V CASE-B2S

POLY-TANT

CRITICAL

C1075

1

2

CASE-B2S

2.5V

20%

210UF

POLY-TANT

CRITICAL

C1076

1

2

20%

2.5V CASE-B2S

210UF

CRITICAL

POLY-TANT

C1077

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C109B

1

2

NO STUFF

20%

20UF

X5R-CERM

4V 0402-2

C109C

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C109D

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C109E

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C109F

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101A

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101B

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101C

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101D

1

2

Place near U0500 on bottom side

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C1023

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101E

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101F

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102A

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102B

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102C

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102D

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103F

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103E

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103D

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103C

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103B

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103A

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102F

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102E

1

2

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

CPU Decoupling

PPVCC_S0_CPU

PP1V35_S3RS0_CPUDDR

PPVCCIO_S0_CPU

10 OF 81

10 OF 118

<SCH_NUM>

6 8

46 59 69 71

6 8

21 65 66

69 81

5 6 8

18 58

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN

OUT

IN

OUT OUT

OUT

IN

OUT

IN

OUT OUT

IN

OUT OUT

OUT

NC

HDA_SDI1 HDA_SDI2

TP25 TP22

HDA_DOCK_RST*/GPIO13

SATA_RXP0

SATA_RXP5/PERP2

SATA_RXN5/PERN2

TP8

SRTCRST*

RTCX1 RTCX2

HDA_BCLK

DOCKEN*/GPIO33

SATA_RCOMP

SATA_TXN0

SATA_TXP4/PETP1

SATA_TXP1

SATA_TXN4/PETN1

SATA_TXN1

SATA0GP/GPIO21

SATALED*

SPKR

JTAG_TDI

JTAG_TDO

JTAG_TMS

TP20

JTAG_TCK

INTRUDER*

HDA_SYNC

HDA_SDI3

HDA_SDO

SATA_RXP2

SATA_RXN2

SATA_TXN2 SATA_TXP2

SATA_RXN3 SATA_RXP3 SATA_TXN3

TP9

SATA_IREF

SATA1GP/GPIO19

SATA_TXP0

SATA_RXN1 SATA_RXP1

RTCRST*

INTVRMEN

SATA_RXN0

SATA_RXP4/PERP1

SATA_RXN4/PERN1

SATA_TXP3

SATA_TXP5/PETP2

SATA_TXN5/PETN2

HDA_SDI0

HDA_RST*

JTAG

(1 OF 11)

RTC

AZALIA

SATA

CLOCKS

(2 OF 11)

PCIECLKRQ2*/GPIO20/SMI*

CLKOUT_33MHZ4

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

PCIECLKRQ0*/GPIO73

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_PCIE_P6

CLKOUT_PCIE_N6

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

TP18

TP19

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE_P5

CLKOUT_PCIE_N5

PCIECLKRQ1*/GPIO18

CLKOUT_DPNS_N CLKOUT_DPNS_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

PEG_A_CLKRQ*/GPIO47

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_DP_P

CLKOUT_DP_N

CLKOUT_PCIE_P7

CLKOUT_PCIE_N7

XTAL25_OUT

XTAL25_IN

ICLK_IREF

DIFFCLK_BIASREF

CLKIN_GND_N CLKIN_GND_P

CLKIN_DMI_P

CLKIN_DMI_N

CLKOUT_33MHZ2

CLKIN_SATA_P

CLKIN_SATA_N

CLKOUTFLEX0/GPIO64

CLKIN_33MHZLOOPBACK

CLKOUT_33MHZ0 CLKOUT_33MHZ1

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX3/GPIO67

CLKOUT_33MHZ3

REFCLK14IN

CLKIN_DOT96_P

CLKIN_DOT96_N

PCIECLKRQ3*/GPIO25

PEG_B_CLKRQ*/GPIO56

PCIECLKRQ4*/GPIO26

PCIECLKRQ7*/GPIO46

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

OUT OUT

OUT

IN

IN OUT OUT

OUT OUT

IN

NC NC

NC

OUT

IN

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks. PEG-attached (CPU) PCIe devices must use one set, while PCH-attached PCIe devices use the other set. If 2 or less devices are attached to PEG the CLKOUT_PEG outputs can be used for those devices.

(IPD-DOCKEN#?)

(IPD)

NOTE: ENET pair only used if SD Card Reader is USB3.

Secondary HDD/SSD (SATA only)

Primary HDD/SSD (SATA only)

Reserved: ODD

Unused

PCIe:

SATA Port assignments:

Reserved: Ethernet (if not combo w/SD Card)

Unused

(IPD)

(IPU)

(IPD-boot)

Unused clock terminations for FCIM Mode

(IPD) (IPD)

(IPU-PLTRST#)

Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

(IPD-PWROK)

(IPU-RSMRST#)

(IPD-PWROK)

(IPD-PWROK) (IPD-PWROK)

(IPD-PWROK)

1.5V -> 1.1V

(IPU)

(IPD-PLTRST#)

(IPD)

If HDA = S0, must also ensure that signal cannot be high in S3.

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

19 75

52 76

330K

1/20W

5%

201

MF

R1100

1

2

1/20W

5%

201

MF

1M

R1101

1

2

1/20W

5%

201

MF

20K

R1102

1

2

1/20W

5%

201

MF

20K

R1103

1

2

10V

10% 402

X5R

1UF

C1103

1

2

10V

10% 402

X5R

1UF

C1102

1

2

1/20W

1%

201

MF

7.5K

PLACE_NEAR=U1100.AY5:2.54mm

R1130

1

2

11 70

18 71

340

MF-LF

402

1%

1/16W

R1172

1 2

1K

1/20W

1%

201

MF

R1173

1

2

19 75

18

11 18

34 76

37 76

18

37 76

11 35

11 36

11 28

6

74

6

74

6

74

6

74

19 76

11 70

28 76

MF

1/20W

5% 201

4.7K

R1177

1 2

4.7K

201

1/20W

5% MF

R1178

1 2

10K

MF 2015%

1/20W

R1134

1 2

10K

MF 2015%

1/20W

R1142

1 2

10K

MF 2015%

1/20W

R1169

1 2

10K

MF 2015%

1/20W

R1144

1 2

10K

MF 2015%

1/20W

R1145

1 2

10K

MF 2015%

1/20W

R1147

1 2

10K

MF 2015%

1/20W

R1114

2 1

10K

MF 201

1/20W

5%

R1115

1 2

1/20W

5% 201MF

10K

R1143

1 2

1/20W

5% 201MF

10K

R1133

1 2

1/20W

10K

MF 2015%

R1179

1 2

1/20W

5% 201MF

10K

R1146

1 2

1/20W

5% 201MF

10K

R1148

1 2

52 76

10K

MF 2015%

1/20W

R1191

1 2

10K

MF 2015%

1/20W

R1192

1 2

10K

MF5%

1/20W

201

R1193

1 2

10K

MF 2015%

1/20W

R1194

1 2

10K

MF 2015%

1/20W

R1195

1 2

10K

MF 2015%

1/20W

R1196

1 2

10K

MF 2015%

1/20W

R1197

1 2

5% 201MF

10K

1/20W

R1170

1 2

10K

MF 2015%

1/20W

R1171

1 2

OMIT_TABLE

LYNXPOINT

MOBILE

FCBGA

U1100

B17

B25

C22

C24

L22 K22 G22 F22

A24

A22

A8

G10

AB3

AE2

AD3

AD1

D9

B5 B4

AT1 AU2

BD4

AY5

BC8

BC10

BB9

BC12

BD13

BC14

BE8

BE10

BD9

BE12

BB13

BE14

AW8

AV10

AY13

AR13

AV15

AP15

AY8

AW10

AW13

AT13

AW15

AR15

AP3

AL10

B9

AB6

C26

F8

BB2

BA2

MOBILE

LYNXPOINT

OMIT_TABLE

FCBGA

U1100

D17

AY24 AW24

H33 G33

AR24 AT24

BE6 BC6

D44 E44 B42 F41 A40

AF39 AF40

AJ40 AJ39

AF35 AF36

AH43 AH45

Y43

AA44

AB43

AD43

AF43

AE44

AB40

AJ44

Y45

AA42

AB45

AD45

AF45

AE42

AB39

AJ42

AB35 AB36

Y39 Y38

C40 F38 F36 F39

AN44

AM45

AB1

AF1

AF3

T3

V3

AA2

AE4

Y3

AF6

U4

F45

AD38

AD39

AM43 AL44

6

74

6

74

72 74

PLACE_NEAR=U1100.B25:1.27mm

MF 2015%

1/20W

33

R1110

1 2

PLACE_NEAR=U1100.A24:1.27mm

2015%

1/20W33MF

R1113

1 2

1/20W

5% 201MF

33

PLACE_NEAR=U1100.A22:1.27mm

R1111

1 2

PLACE_NEAR=U1100.C24:1.27mm

33

MF 2015%

1/20W

R1112

1 2

19 76

72 75

72

11 18

1/20W

MF

1%

PLACE_NEAR=U1100.AN44:2.54mm

201

7.5K

R1190

2 1

11 70

10K

MF 2015%

1/20W

R1176

1 2

35 76

11 70

72 75

PCH RTC/HDA/JTAG/SATA/CLK

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

ENET_CLKREQ_L

NC_PCIE_CLK100M_PEGBN

PCH_PEGCLKRQB_L_GPIO56 ENET_MEDIA_SENSE_RDIV

XDP_PCH_TCK

ENET_MEDIA_SENSE_RDIV

DP_TBT_SEL

HDA_SDOUT

HDA_SDIN0

PCH_CLK96M_DOT_N

PCH_SPKR DP_TBT_SEL

PCH_SRTCRST_L PCH_INTRUDER_L

HDA_SYNC_R

PP1V5_S0

PCH_INTRUDER_L PCH_INTVRMEN_L

PCH_SRTCRST_L

RTC_RESET_L

PPVRTC_G3H

SYSCLK_CLK25M_SB

NC_HDA_SDIN3

NC_HDA_SDIN1

PCH_DIFFCLK_BIASREF

PCH_CLK14P3M_REFCLK

PCH_CLKIN_GNDN PCH_CLKIN_GNDP

PCH_CLK100M_SATA_P

NC_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO67_CLKOUTFLEX3

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

DMI_CLK100M_CPU_N

NC_PCIE_CLK100M_ENETN

SYSCLK_CLK32K_RTC

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_BIT_CLK

XDP_PCH_TMS

XDP_PCH_TDO

PP1V5_S0

SSD_CLKREQ_L

NC_PCH_GPIO64_CLKOUTFLEX0

PCH_SATALED_L

XDP_DD2_ENETSD_CLKREQ_L AP_CLKREQ_L

PCH_CLKRQ5_L_GPIO44 PEG_CLKREQ_L PCH_CLKRQ7_L_GPIO46

ENET_CLKREQ_L

HDA_SYNC

HDA_RST_L

PCH_INTVRMEN_L RTC_RESET_L

PCH_SPKR

XDP_PCH_TDI

NC_PCH_GPIO65_CLKOUTFLEX1

PCH_CLK33M_PCIIN

SYSCLK_CLK25M_SB_R

PCH_CLK96M_DOT_P

PCH_CLKRQ5_L_GPIO44

NC_PCIE_CLK100M_PE5N

NC_PCI_CLK33M_OUT3

PCH_CLKRQ7_L_GPIO46

NC_PCIE_CLK100M_SWN NC_PCIE_CLK100M_SWP

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_GPUN

NC_PCI_CLK33M_OUT2

NC_PCIE_CLK100M_GPUP

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

XDP_DD3_AP_CLKREQ_L

PCIE_CLK100M_CAMERA_N PCIE_CLK100M_CAMERA_P

CAMERA_CLKREQ_L

TBT_CLKREQ_L

PEG_CLKREQ_L

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

NC_ITPXDP_CLK100MN NC_ITPXDP_CLK100MP

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

XDP_DC1_SATARDRVR_EN

DP_AUXCH_ISOL_L

PP1V5_S0

PCH_CLK100M_SATA_N

CPU_CLK135M_DPLLREF_P

CPU_CLK135M_DPLLREF_N

CPU_CLK135M_DPLLSS_P

CPU_CLK135M_DPLLSS_N

DMI_CLK100M_CPU_P

NC_PCIE_CLK100M_PEGBP PCH_PEGCLKRQB_L_GPIO56

NC_PCIE_CLK100M_ENETP

CAMERA_CLKREQ_L TBT_CLKREQ_L

NC_HDA_SDIN2

HDA_SDOUT_R

TP_PCIE_ENET_R2D_CN TP_PCIE_ENET_R2D_CP

NC_SATA_F_D2RN

TP_PCIE_ENET_D2RP

TP_PCIE_ENET_D2RN

NC_SATA_D_D2RN

NC_SATA_D_R2D_CP

NC_SATA_D_D2RP NC_SATA_D_R2D_CN

NC_SATA_F_R2D_CP

NC_SATA_F_D2RP NC_SATA_F_R2D_CN

XDP_DC0_DP_AUXCH_ISOL_L XDP_DC1_SATARDRVR_EN

NC_SATA_ODD_R2D_CP

NC_SATA_ODD_R2D_CN

NC_SATA_ODD_D2RP

NC_SATA_ODD_D2RN

NC_SATA_A_R2D_CP

NC_SATA_A_R2D_CN

NC_SATA_A_D2RP

NC_SATA_A_D2RN

NC_SATA_B_D2RN NC_SATA_B_D2RP NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP

PCH_SATALED_L

PCH_SATA_RCOMP

SSD_CLKREQ_L

NC_PCIE_CLK100M_ENETSDN NC_PCIE_CLK100M_ENETSDP

XDP_DD2_ENETSD_CLKREQ_L

PP3V3_SUS PP3V3_S0

11 OF 81

11 OF 118

<SCH_NUM>

72

11

11 70

76

11

11 70

11 76

76

11 12 13 15 17 19 52 64 66 68 69 71

11 76

11

12 15 19 69

72

76

72

76

72

76

11 12 13 15 17 19 52 64 66 68 69 71

11 35

72

11

11 18

18 34

11

11 70

11

11 70

11 76

11

72

75

76

11

72

11

72

11 18

18

11 12 13 15 17 19 52 64 66 68 69 71

76

72

11

72

11 36

11 28

72

19 76

72

11

75

12 13 14 15 17 50 64 65 66 69

12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55 65

66 67 69 71 81

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

DAC_IREF VGA_IRTN

VGA_VSYNC

VGA_HSYNC

PIRQH*/GPIO5

PIRQG*/GPIO4

DDPC_AUXN

EDP_BKLTEN

EDP_VDDEN

GPIO54

GPIO51

GPIO55

GPIO53

DDPC_CTRLCLK

DDPB_CTRLDATA

DDPB_CTRLCLK

DDPC_CTRLDATA

EDP_BKLTCTL

PIRQF*/GPIO3

DDPC_HPD

DDPC_AUXP DDPD_AUXP

DDPB_HPD

DDPD_HPD

PIRQE*/GPIO2

DDPD_CTRLDATA

DDPD_CTRLCLK

VGA_RED

PIRQA*

GPIO52

GPIO50

PIRQD*

PIRQC*

PIRQB*

PME*

PLTRST*

DDPB_AUXN

VGA_BLUE VGA_GREEN

DDPB_AUXP

DDPD_AUXN

VGA_DDC_DATA

VGA_DDC_CLK

CRT

PCI

DISPLAY

(5 OF 11)

EDP

OUT

IN

OUT

IN

BI

OUT

IN

SYSTEM POWER

MANAGEMENT

(4 OF 11)

DMI

FDI

SUSACK*

RI*

DPWROK

BATLOW*/GPIO72

PWRBTN*

RSMRST*

DRAMPWROK

SLP_LAN*

SLP_A*

PWROK

SLP_SUS*

ACPRESENT/GPIO31

SLP_WLAN*/GPIO29

DSWVRMEN

SLP_S4*

DMI_TXN1

DMI_TXN3

DMI_TXN2

DMI_TXP1

DMI_TXP0

TP5

PMSYNCH

DMI_RXN0

TP15

TP16

TP13

TP17

DMI_RXN1

SYS_RESET*

FDI_RXP1

FDI_RXN1

FDI_RXP0

FDI_RXN0

APWROK

TP21

SUSWARN*/SUSPWRNACK/GPIO30

DMI_TXN0

FDI_RCOMP

DMI_TXP2 DMI_TXP3

DMI_IREF

TP12

DMI_RCOMP

TP7

WAKE*

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

DMI_RXP0

DMI_RXP3

DMI_RXP2

DMI_RXP1

TP10

SLP_S3*

CLKRUN*

SYS_PWROK

DMI_RXN2

FDI_IREF

FDI_INT

FDI_CSYNC

DMI_RXN3

OUT

IN IN IN

OUT

NC NC NC

NC NC

NC

NC NC

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD-DeepSx)

DG v1.0 (Table 12-18).

(IPD-PLTRST#)

(IPU)

(IPD-PLTRST#)

(OD)

(IPU)

(IPU-PWROK&PCIRST#)

(IPD-DeepSx)

(IPU)

(IPD-PLTRST#)

(IPU-RSMRST#)

Redundant to pull-up on audio page

VGA DAC Disabled per SB

5

74

5

74

201

1/20W

MF

PLACE_NEAR=U1100.AY17:12.7mm

1%

7.5K

R1200

1

2

5

74

5

74

5

74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

FCBGA

MOBILE

LYNXPOINT

OMIT_TABLE

U1100

U40

H45

H43

R40 R39

K40

K43

K45

R35 R36

K38

J42

J44

N40 N38

H39

N36

K36

G36

A12

C10

B13

A10

C12

AL6

H20 L20 K17 M20

G17 F17 L15 M15

Y11

AD10

T45

M43 M45

U44

N42

U39

V45

N44

5%

201

1/20W MF

330K

R1215

1

2

5%

201

1/20W

MF

10K

R1205

1

2

12 45 65 66

5%

201

1/20W MF

100K

R1209

1

2

19 41 71 76

18 19 41 71 76

6

21 74

12 19 71 76

66 71 76

12 18 41 76

41 42

12 30 41 43

12 34 36 71 76

12 41 50 71

20 41 50 71

42

12 41 66

12 21 34 38 41 66 68 71

12 21 41 66 71

6

74

41 71 76

5%

201

1/20W

MF

100K

R1223

2 1

5%

201

1/20W

MF

1K

R1225

1 2

5%

201

1/20W

MF

10K

R1291

1 2

5%

201

1/20W

MF

100K

R1222

2 1

5%

201

1/20W

MF

100K

R1221

2 1

5%

201

1/20W

MF

100K

R1224

2 1

5%

201

1/20W

MF

100K

R1284

2 1

5%

201

1/20W

MF

100K

R1281

2 1

OMIT_TABLE

FCBGA

LYNXPOINT

MOBILE

U1100

E6

AB7

K7

AN7

BE16

AY17

AW22 AR20 AP17 AV20

AY22 AP20 AR17 AW20

BD21 BE20 BD17 BE18

BB21 BC20 BB17 BC18

L13

H3

C8

AL39 AL40

AT45

AR44

AJ35 AL35

AJ36 AL36

AY3

K1

F10

N4

J2

F3

G5

H1

C6

Y7

F1

D2

U7

R6

Y6

J4

AD7

AM1

AW44

AW17

AU44

AV45

AV43

AU42

AB10

AY45

AV17

K3

12 67 70 71

12 63 70 71

63 70

5

74

201

1/20W

MF

PLACE_NEAR=U1100.AR44:12.7mm

7.5K

1%

R1210

1

2

5% 201

1/20W

MF

10K

R1261

1 2

5% 201

1/20W

MF

10K

R1263

1 2

5%

201

1/20W

MF

10K

R1262

1 2

5%

201

1/20W

MF

10K

R1260

1 2

5% 201

1/20W

MF

NO STUFF

10K

R1233

1 2

5% 201

1/20W

MF

10K

R1231

1 2

5% 201

1/20W

MF

NO STUFF

100K

R1214

1 2

5% 201

1/20W

MF

10K

R1230

1 2

5% 201

1/20W

MF

100K

R1217

1 2

5% 201

1/20W

MF

10K

R1218

1 2

12 70

5% 201

1/20W

MF

10K

R1216

1 2

12 70

12 29

12 70

18 20 21 71

MF

1/20W

0201

0

5%

R1286

1

2

12 70

5%

201

1/20W

MF

10K

R1240

2 1

5%

201

1/20W

MF

3.0K

R1239

1 2

43

12 70

PCH DMI/FDI/PM/GFX/PCI

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

PP3V3_S0

PM_SLP_S3_L

PM_SLP_S5_L

PM_SLP_SUS_L PM_SYNC

PP3V3_S5

EDP_IG_PANEL_PWR

EDP_IG_BKL_ON

PM_SLP_SUS_L

PM_SLP_S4_L

PCIE_WAKE_L

AUD_I2C_INT_L

TBT_PWR_REQ_L

AUD_IP_PERIPHERAL_DET

SDCONN_OC_L

BT_PWRRST_L

AUD_IPHS_SWITCH_EN_PCH

ENET_LOW_PWR_PCH

PM_CLKRUN_L

PM_BATLOW_L

PM_PWRBTN_L

PCH_FDI_RCOMP

LPC_PWRDWN_L PM_CLK32K_SUSCLK_R PM_SLP_S5_L

PCH_STRP_TOPBLK_SWP_L

PM_PWRBTN_L SMC_ADAPTER_EN

PP3V3_S0

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_HPD HDMI_HPD

TBT_PWR_REQ_L

DP_TBTSNK1_DDC_DATA

PP3V3_SUS

PM_SYSRST_L

PM_RSMRST_L

PM_MEM_PWRGD

PP1V5_S0

DP_TBTSNK0_AUXCH_C_N

PPVRTC_G3H

PCH_DSWVRMEN PM_DSW_PWRGD

TP_PCH_SLP_S0_L

PCH_RI_L

FDI_CSYNC FDI_INT

PM_SLP_S4_L

TP_PCH_STRP_BBS1

DP_TBTSNK0_DDC_DATA

DP_TBTSNK0_DDC_CLK

DP_TBTSNK1_DDC_CLK

HDMI_DDC_DATA

HDMI_DDC_CLK

DP_TBTSNK1_AUXCH_C_N NC_DP_IG_D_AUXCHN

DP_TBTSNK0_AUXCH_C_P

NC_DP_IG_D_AUXCHP

DP_TBTSNK0_HPD

AUD_IP_PERIPHERAL_DET

DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>

DMI_N2S_P<0>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<3>

DMI_S2N_N<0>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<3> DMI_S2N_P<0>

DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>

PM_PCH_SYS_PWROK

PM_BATLOW_L

EDP_IG_BKL_PWM EDP_IG_BKL_ON EDP_IG_PANEL_PWR

PCI_INTB_L PCI_INTC_L

TP_PCH_SLP_LAN_L

PCIE_WAKE_L PM_CLKRUN_L

TP_PCH_SLP_WLAN_L

PM_SLP_S3_L TP_PM_SLP_A_L

TP_PCH_STRP_ESI_L

AUD_IPHS_SWITCH_EN_PCH

PCI_INTD_L

PCI_INTA_L

ENET_LOW_PWR_PCH

BT_PWRRST_L

PCH_DMI_RCOMP

PM_PCH_PWROK

PLT_RESET_L

NC_PCI_PME_L

AUD_I2C_INT_L

SDCONN_OC_L

PCH_SUSWARN_L

PCH_SUSACK_L

PP1V5_S0

<SCH_NUM>

12 OF 118

12 OF 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

12 21 41 66 71

12 41 66

14 15 17 18 19 21 31 32 34 61

64 65 66 69

70 71 81

12 67 70 71

12 63 70 71

12 45 65 66

12 21 34 38 41 66 68 71

12 34 36 71 76

12 70

12 29

12 70

12 41 50 71

12 30 41 43

12 18 41 76

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

28 70 74

28 70

20 68 70

33 70

11 13 14 15 17 50 64 65 66 69

11 12 13 15 17 19 52 64 66 68 69 71

28 70 74

11 15 19 69

76

33 70

68 70 71

28 70 74

72

28 70 74

72

28 70

72

11 12 13 15 17 19 52 64 66 68 69 71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

BI

BI BI

IN IN

OUT

IN

OUT

IN

BI

IN

OC1*/GPIO40 OC2*/GPIO41

OC5*/GPIO9

OC0*/GPIO59

OC3*/GPIO42

OC6*/GPIO10

OC4*/GPIO43

OC7*/GPIO14

USB2P6

USB2N6

USB2P5

USB2N7

USB2N5

USB2N13

USB2P0

USB2P4

USB2P10

USB2P2

USB2P3

USB2P8

PETN7

PETP6

PETN4

PETN3

PETN1_USB3TN3

PCIE_IREF

USB3TP6

USB3TN5

USB3TN1

PETN8 PETP8

PETN5

PCIE_RCOMP

USB3TN6

USB3TN2

USB3TP1

PETP7

PETN6

PETP1_USB3TP3

TP11

USB3TP5

USB3TP2

PETP5

TP6

USB2N0

USB2N4

USB2N10

PERN6

PERP3

PERP1_USB3RP3

PERP6

PERN5

PERN3

PERN1_USB3RN3

USB3RN5

USB3RN2

PERP5

USB3RP5

USB3RP2

PERN7 PERP7

PERN4

PERN2_USB3RN4

PERP4

PERP2_USB3RP4

USB3RN6

USB3RN1

USB3RP6

USB3RP1

PERP8

PERN8

USB2N1

USB2N2

USB2N3

USB2N9 USB2P9

USB2N8

USB2P7

USB2N11

USB2P13

USB2P1

PETP4

USB2P11

PETP2_USB3TP4

PETN2_USB3TN4

PETP3

USB2N12 USB2P12

TP23

TP24

USBRBIAS*

USBRBIAS

(9 OF 11)

USB

PCI-E

BI

IN

IN OUT OUT

IN

OUT OUT

IN

OUT OUT

IN

OUT OUT

OUT

SML0CLK

SML1ALERT*/PCHHOT*/GPIO74

LDRQ1*/GPIO23

LAD1

TP3

TP4

TP2

TP1

SPI_CS1*

SERIRQ

SPI_CS0*

SPI_IO2

SPI_IO3

SPI_CLK

SPI_CS2*

SPI_MISO

SPI_MOSI

LAD2

SML1DATA/GPIO75

CL_RST*

SML1CLK/GPIO58

LDRQ0*

TD_IREF

CL_CLK

CL_DATA

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

LAD0

SML0DATA

LFRAME*

LAD3

SMBUS

LPC

(3 OF 11)

SPI

C-LINK

IN BI

BI

OUT

BI

OUT

BI

OUT

BI BI BI

BI BI

NC

BI

OUT

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN IN

OUT OUT

IN IN

OUT OUT

IN IN

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ext B (LS/FS/HS)

Ext C (SS)

(IPD)

Trackpad

BT

IR

Ext D (SS)

USB3 Port Assignments:

Ext B (SS)

Ext A (SS)

Reserved: Camera

Ext D (LS/FS/HS)

Unused

Reserved: PSOC (Legacy Trackpad)

USB Port Assignments:

Ext C (LS/FS/HS)

Ext A (LS/FS/HS)

Reserved: WiFi (HS)

Reserved: SD (HS)

(IPU)

(IPU) (IPU)

(IPD)

(IPU)

(IPU-LDRQ1#?)

(IPU)

(IPU/IPD)

AirPort

Camera

Lane 3 (PCIe-only)

Lane 2 (PCIe-only)

SSD (Gumstick)

Or PCIe switch if TBT/SSD

SSD (Gumstick)

(PCIe-only)

Lane 0

Lane 1

Or PCIe switch if TBT/SSD

(PCIe-only)

SSD (Gumstick)

USB3 Port Assignments:

PCIe/USB3 Port Assignments:

SD Card Reader (& Ethernet if combo)

PCIe Port Assignments:

Unused

72 75

1/20W

5% 201MF

10K

R1367

2 1

10K

MF 2015%

1/20W

R1368

1 2

10K

1/20W

MF 2015%

R1361

1 2

10K

MF 2015%

1/20W

R1362

1 2

10K

MF 201

1/20W

5%

R1360

1 2

10K

MF 2015%

1/20W

R1369

1 2

13 18

18

13 18

18

13 18

38 75

13 18

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

U1100

P3 V1 U2 P1 M3 T1 N2 M1

BE30

BD29

AW31

AT31

AW33

AT33

AW36

AY38

AT40

AN38

AY31

AR31

AY33

AR33

AV36

AW38

AT39

AN39

BE32

BD33

BE34

BE36

BD37

BC38

BE40

BD42

BC32

BB33

BC34

BC36

BB37

BE38

BC40

BD41

BC30

L33

M33

BB29

B37

A38

B29

A28

G26

F24

A36

A34

B33

F31

K31

G29

A32

A30

D37

C38

D29

C28

F26

G24

C36

C34

D33

G31

L31

H29

C32

C30

AR26

AW26

AW29

AR29

AP26

AV26

AV29

AP29

BE24

BD25

BE26

BD27

BD23

BC24

BC26

BE28

K26

K24

38 75

68 71 75

68 75

72 75

50 76

MOBILE

LYNXPOINT

OMIT_TABLE

FCBGA

U1100

AF11

AF10

AF7

A20 C20 A18 C18

D21 G20

B21

AL11

N7

R10 U11

N8

U8 R7

H6

K6 N11

AJ11

AJ7

AL7

AJ10

AJ4

AJ2

AH3

AH1

AY43

BA45 BC45

BE44

BE43

44 76

18 22 44 63 68 71 76

PLACE_NEAR=U1100.BD29:12.7mm

1/20W 201

MF

1%

7.5K

R1300

1

2

201MF5%

1/20W

33

R1340

1 2

MF 2015%

1/20W

33

R1341

1 2

2015%331/20W

MF

R1343

1 2

MF 201

33

5%

1/20W

R1342

1 2

5% 201MF

1/20W

33

R1344

1 2

13 20

13 41 50 71

1/20W

5% 201MF

10K

R1350

1 2

41 50 71 76

8.2K

MF

1/20W 201

1%

R1380

1

2

34 75

72 75

39 75

1/20W

5% 201MF

10K

R1355

1 2

1/20W

5% 201MF

10K

R1354

1 2

1/20W

5% 201MF

10K

R1353

1 2

1/20W

5% 201MF

10K

R1320

1 2

1/20W

5% 201MF

10K

R1321

1 2

50 76

13 50

18

10K

MF 2015%

1/20W

R1351

1 2

1/20W

5% 201MF

1K

R1393

1 2

1/20W

5% 201MF

1K

R1392

1 2

68 71 75

20 68 71 76

68 71 75

35 76

34 76

37 76

1% 1/20W

201

MF

22.6

PLACE_NEAR=U1100.K24:11.4mm

R1370

1

2

PCH PCI-E/USB

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

USB3_SD_R2D_C_P

USB3_SD_R2D_C_N

USB3_SD_D2R_P

USB3_SD_D2R_N

NC_USB3_SPARE_R2D_CN NC_USB3_SPARE_R2D_CP

NC_USB3_SPARE_D2RN NC_USB3_SPARE_D2RP

PCIE_CAMERA_D2R_N

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_D2R_P PCIE_CAMERA_R2D_C_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_D2R_P<0> PCIE_SSD_R2D_C_N<0>

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_N<2>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_N<3>

PCIE_SSD_R2D_C_P<2>

PCH_USB_RBIAS

LPC_AD_R<0>

SMBUS_PCH_DATA

SML_PCH_0_CLK SML_PCH_0_DATA

SML_PCH_1_CLK SML_PCH_1_DATA

PCH_SML0ALERT_L

SMBUS_PCH_CLK

PCH_SMBALERT_L

NC_CLINK_DATA

NC_CLINK_CLK

PCH_TD_IREF

NC_CLINK_RESET_L

SPI_MOSI_R SPI_MISO

TP_SPI_CS2_L

SPI_CLK_R

SPI_IO<3>

SPI_IO<2>

SPI_CS0_R_L

LPC_SERIRQ

TP_SPI_CS1_L

TBT_PWR_EN_PCH

PCH_SML1ALERT_L

LPC_AD<0>

LPC_AD<2> LPC_AD<3>

LPC_AD<1>

LPC_FRAME_L

USB_EXTA_N USB_EXTA_P

NC_USB_EXTCN NC_USB_EXTCP

USB_EXTB_N USB_EXTB_P

NC_USB_EXTDN NC_USB_EXTDP

USB_BT_N

NC_USB_IRN

USB_BT_P

USB_TPAD_N

NC_USB_IRP

USB_TPAD_P

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_C_N

USB3_EXTB_D2R_N

USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_P USB3_EXTB_R2D_C_N

NC_USB3_EXTC_D2RP

NC_USB3_EXTC_R2D_CP

NC_USB3_EXTD_R2D_CN

XDP_DA0_USB_EXTA_OC_L XDP_DA1_USB_EXTC_OC_L

XDP_DA3_CAMERA_PWR_EN XDP_DB0_USB_EXTB_OC_L XDP_DB1_USB_EXTD_OC_L

XDP_DB3_SDCONN_STATE_CHANGE_L

NC_USB_7P

NC_USB_WLANN

NC_USB_SDN

TP_USB_CAMERAN

NC_USB_4N

NC_USB_WLANP

NC_USB_SDP

NC_USB_4P NC_USB_PSOCN

NC_USB_7N

NC_USB_PSOCP NC_USB_6N

PP1V5_S0

NC_USB3_EXTD_D2RN NC_USB3_EXTD_D2RP

NC_USB3_EXTD_R2D_CP

XDP_DB2_SD_PWR_EN

PCH_PCIE_RCOMP

NC_LPC_DREQ0_L

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

NC_USB3_EXTC_R2D_CN

TP_USB_CAMERAP

NC_USB_6P

XDP_DA2_SSD_PWR_EN

USB3_EXTB_R2D_C_P NC_USB3_EXTC_D2RN

PCH_SML1ALERT_L

PCH_SML0ALERT_L

SPI_IO<2> SPI_IO<3>

PCH_SMBALERT_L

XDP_DB1_USB_EXTD_OC_L SD_PWR_EN

XDP_DB0_USB_EXTB_OC_L

SSD_PWR_EN

LPC_SERIRQ TBT_PWR_EN_PCH XDP_DA0_USB_EXTA_OC_L

XDP_DA1_USB_EXTC_OC_L

PP3V3_SUS PP3V3_SUS

PP3V3_S0

CAMERA_PWR_EN

XDP_DB3_SDCONN_STATE_CHANGE_L

PP3V3_S3RS0_CAMERA

PP3V3_S3

<SCH_NUM>

13 OF 118

13 OF 81

72

75

13

72

13

72 75

72

72 75

72

72 75

72

72 75

72

72 75

11 12 15 17 19 52 64 66 68 69 71

72

72 75

13

13 50

13

13 18

18 68 71

13 18

18 65

13 41 50 71

13 20

13 18

11 12 13 14 15 17 50 64 65 66 69

11 12 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55 65

66 67 69 71 81

18 36

13 18

36 47 69

20 21 22 44 46 47 65 68 69 71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

OUT

BI

IN

OUT

IN

BI

ININ

OUT

IN

OUT

GPIO24

GPIO57

GPIO27

TACH4/GPIO68

SCLOCK/GPIO22

THRMTRIP*

BMBUSY*/GPIO0

SLOAD/GPIO38

GPIO35/NMI*

GPIO34

SDATAOUT1/GPIO48

SDATAOUT0/GPIO39

SATA5GP/GPIO49

SATA3GP/GPIO37

GPIO28

GPIO15

SATA4GP/GPIO16

TACH0/GPIO17

VSS

GPIO8

PLTRST_PROC*

TP14

LAN_PHY_PWR_CTRL/GPIO12

TACH3/GPIO7

TACH2/GPIO6

TACH1/GPIO1

VSS

TACH7/GPIO71

TACH6/GPIO70

TACH5/GPIO69

PECI

PROCPWRGD

RCIN*

VSS

SATA2GP/GPIO36

CPU/MISC

(6 OF 11)

GPIO

OUT

BI

OUT

IN

OUT

BI

OUT

IN

IN IN

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD-PLTRST#)

Redwood Ridge: TBT_CIO_PLUG_EVENT_L, requires pull-up (S0), no isolation necessary.

(IPD)

(IPU-RSMRST#)

(IPU-DeepSx)

(IPU-Boot/SATA4GP?)

(IPU-Boot?)

(IPU-Boot/SATA5GP?)

Cactus Ridge: TBT_CIO_PLUG_EVENT, requires pull-down & isolation.

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high. Systems with chip-down memory should add pull-downs on another page and set straps per software.

Pull-up/down on chipset support page (depends on TBT controller)

NOTE: GPIO70 pull-up/down on project-specific page

NOTE: GPIO0 pull-up/down on project-specific page

6

18 74

21

14 50 71

14 70

14 20

18

14 20

14 50 71

6

42 74

5%

201

1/20W MF

10K

RAMCFG3:H

R1472

1

2

5%

201

1/20W

MF

RAMCFG2:H

10K

R1473

1

2

5%

201

1/20W MF

10K

RAMCFG1:H

R1474

1

2

5%

201

1/20W

MF

10K

RAMCFG0:H

R1475

1

2

14 41

14 20

14 41

14 70

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

U1100

AT8

AB11

Y10

R11

AD11

AN6

AP1

U12

Y1

K13

AY1

AU4

AV3

AT6

AT3

AK1

AN2

AK3

BB4

AM3

AN4

AT7

C14

F13

A14

G15

C16

D13

G13

H15

AV1

AN10

BE41

BE5 C45

A5

A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4

N10

5% 201

1/20W

MF

20K

R1411

2 1

5% 201

1/20W

MF

100K

R1495

2 1

5% 201

1/20W

MF

10K

R1491

1 2

5% 201

1/20W

MF

10K

R1492

1 2

5% 201

1/20W

MF

100K

R1493

1 2

5% 201

1/20W

MF

10K

R1494

1 2

5% 201

1/20W

MF

10K

R1484

1 2

5% 201

1/20W

MF

100K

R1490

1 2

5% 201

1/20W

MF

10K

R1496

1 2

5%

201

1/20W

MF

10K

R1485

1 2

5% 201

1/20W

MF

10K

R1412

2 1

29

14 18

5% 201

1/20W

MF

10K

R1498

2 1

5% 201

1/20W

MF

10K

R1450

1 2

5% 201

1/20W

MF

10K

R1455

1 2

5%

201

1/20W

MF

NO STUFF

43

R1470

1 2

5%

0

0201

1/20W

MF

R1440

1 2

5%

201

1/20W

MF

390

R1456

1 2

6

42 74

14 70

20 28

18

14 70

6

5% 201

1/20W

MF

10K

R1486

1 2

5% 201

1/20W

MF

10K

R1499

1 2

5%

201

1/20W

MF

10K

R1413

2 1

14 70

5% 201

1/20W

MF

10K

R1489

1 2

18

14 70

14 18

5%

NO STUFF

402

MF-LF

1/16W

1K

R1457

1

2

18 20 20

PCH GPIO/MISC/NCTF

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

JTAG_ISP_TDO

PP3V3_SUS

XDP_DD0_SSD_PCIE_SEL_L

MEM_VDD_SEL_1V5_L

LPCPLUS_GPIO JTAG_TBT_TMS_PCH

XDP_DC2_ODD_PWR_EN_L JTAG_ISP_TCK

JTAG_ISP_TDI

PCH_RCIN_L

PP3V3_S5

PP3V3_S0

SPIROM_USE_MLB

XDP_DD1_MLB_RAMCFG1

SD_SEL_PCIE_L_USB_H

JTAG_ISP_TDO JTAG_ISP_TDI

SPIROM_USE_MLB

FW_PWR_EN_PCH

XDP_DC3_JTAG_ISP_TCK

XDP_DC2_ODD_PWR_EN_L

XDP_FC1_GPU_GOOD

XDP_DD0_SSD_PCIE_SEL_L LPCPLUS_GPIO

MEM_VDD_SEL_1V5_L

XDP_FC0_HDD_PWR_EN

SMC_RUNTIME_SCI_L

DPMUX_UC_IRQ

FW_PME_L

PCH_RCIN_L

PCH_PROCPWRGD

PCH_PECI

PCH_A20GATE

CPU_RESET_L

PM_THRMTRIP_L

CPU_PWRGD

PM_THRMTRIP_L_R

CPU_PECI

MLB_RAMCFG0

MLB_RAMCFG3

PP3V3_S0

PP1V05_S0

PCH_A20GATE

FW_PME_L

SMC_RUNTIME_SCI_L

DPMUX_UC_IRQ

WOL_EN

TBT_GO2SX_BIDIR SMC_WAKE_SCI_L

FW_PWR_EN_PCH

WOL_EN

TBT_CIO_PLUG_EVENT_L

ISOLATE_CPU_MEM_L

MLB_RAMCFG2

JTAG_TBT_TMS_PCH TBT_GO2SX_BIDIR SMC_WAKE_SCI_L

TBT_POC_RESET_L

14 OF 81

14 OF 118

<SCH_NUM>

14 20

11 12 13 15 17 50 64 65 66 69

14 18

14 70

14 50 71

14 20

14 18

18 20

14 20

14 76

12 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

14 50 71

14 76

14

42 76

20

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

15 17 18 42 62 66 69 71

14

14 70

14 41

14 70

14 41

14 70

20

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

DCPSUS1

DCPSUSBYP

VCCADAC1_5

VSS

VCCVRM

VCCIO

VCCASW

VCC3_3

DCPSUS3

VCCSUS3_3

VCCADACBG3_3

VCC

CRT

USB3

CORE

PCIE/DMI

(7 OF 11)

FDI

HVCMOS

SATA

VCCMPHY

DCPSUS2

VCCUSBPLL

VCCSPI

DCPSST

VCCRTC

VSS

VCCVRM

VCCIO

VCCCLK3_3

VCCCLK

VCCASW

VCC3_3

VCC

V_PROC_IO

DCPRTC

VCCSUSHDA

VCCSUS3_3

VCCDSW3_3

VCCSUS3_3

VCCIO

VCCCLK

THERMAL

(8 OF 11)

GPIO/LPC

USB

HDARTCCPUSPI

CLK/MISC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

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8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10mA Max, 1mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VGA DAC Disabled per SB DG v1.0 (Table 12-18).

VCC3_3: 133mA Max, 3mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

15 mA Max, 1mA Idle

VCC3_3: 133mA Max, 3mA Idle

6uA Max (3.0V, room temperature)

VCCASW: 670mA Max, 34mA Idle

22mA Max, 1mA Idle

4mA Max, 2mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCASW: 670mA Max, 34mA Idle

VCC3_3: 133mA Max, 3mA Idle

??mA Max, ??mA Idle

NOTE: Pin name is VCC but really is 3.3V

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

Powered in DeepSx

VCCASW: 670mA Max, 34mA Idle

VCC3_3: 133mA Max, 3mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCCLK3_3: 55mA Max, 11mA Idle

VCC: 1.312 A Max, 130mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCCLK: 306mA Max, 89mA Idle

VCCVRM: 183mA Max, 68mA Idle

??mA Max, ??mA Idle

Current data from LPT EDS (doc #486708, Rev 1.0).

BYPASS=U1100.A6:6.35mm

0.1UF

402

CERM

10V

20%

C1532

1

2

BYPASS=U1100.A6:6.35mm

1UF

402

CERM

6.3V

10%

C1531

1

2

BYPASS=U1100.A6:6.35mm

0.1UF

402

CERM

10V

20%

C1533

1

2

FCBGA

CKPLUS_WAIVE=PwrTerm2Gnd

MOBILE

LYNXPOINT

OMIT_TABLE

U1100

Y12

AJ26 AJ28

U14

AE18 AE20 AE22 AE24 AE26 AG18 AG20 AG22 AG24

Y26

AA24

R30 R32

AA26 AD20 AD22 AD24 AD26 AD28

P45

M31

Y18 Y20 Y22

AA18

U18 U20 U22 U24 V18 V20 V22 V24

AM22

AN34 AN35

AP22 AR22 AT22

AK18

AK20

AK22

AM18 AM20

AJ30 AJ32

AK26 AK28

AN11

BB44

BE22

P43

OMIT_TABLE

LYNXPOINT

FCBGA

MOBILE

U1100

P14 P16

AA14

Y35

AJ12 AJ14

P18 P20

AP45

L24

AE14 AF12 AG14

AK30 AK32

L17

R18

Y32

AA30 AA32

AD34

L26

L29

M26

M29

U32 V32

AD35

AD36

AE30 AE32

AG30 AG32

A16

U30 U36 V28 V30 Y30

A6

AD12

K8

R20 R22

R24 R26 R28 U26

A26

U35

AF34

AW40

M24

10%

6.3V

1UF

PLACE_NEAR=R1550.1:2.54mm

CERM

402

C1550

1

2

1%

MF-LF

1/20W

5.11

201

PLACE_NEAR=U1100.U14:2.54mm

R1550

1 2

402

CERM

10V

20%

0.1UF

BYPASS=U1100.P14:6.35mm

C1590

1

2

0.1UF

402

CERM

20% 10V

BYPASS=U1100.AA14:6.35mm

C1580

1

2

PCH Power

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

PP3V3_SUS

PP1V05_S0

PP3V3_S5

PP1V05_S0

PP1V5_S0

PP3V3_S0

PP1V05_S0_PCH_VCC_CLK_F

PP1V5_S0

PP1V05_S0

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPSST

PP1V05_S0

PP3V3_S0

PP1V05_S0

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVOUT_S0_PCH_DCPRTC

PP3V3_S0

PP3V3_SUS

PP1V05_S0

PP3V3_SUS

PP1V05_S0

PP1V5_S0

PP3V3_SUS

PPVRTC_G3H

PP3V3_S0

PP1V05_S0

PP1V5_S0

PP1V05_S0

<SCH_NUM>

15 OF 118

15 OF 81

11 12 13 14 15 17 50 64 65 66 69

11 12 13 14 15 17 50 64 65 66

69

14 15 17 18 42 62 66 69 71

12 14 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68

69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

17

11 12 13 15 17 19 52 64 66 68 69 71

14 15 17 18 42 62 66 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

14 15 17 18 42 62 66 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 50 64 65 66 69

14 15 17 18 42 62 66 69 71

11 12 13 14 15 17 50 64 65 66

69

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68

69 71

11 12 13 14 15 17 50 64 65 66

69

11 12 19 69

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68

69 71

11 12 13 15 17 19 52 64 66 68

69 71

11 12 13 15 17 19 52 64 66 68

69 71

11 12 13 15 17 19 52 64 66 68 69 71

14 15 17 18 42 62 66 69 71

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w w w . c h i n a f i x . c o m

VSS

(10 OF 11)

VSSVSS

(11 OF 11)

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MOBILE

OMIT_TABLE

LYNXPOINT

FCBGA

U1100

AL34 AL38

AN36 AN40 AN42

AN8 AP13 AP24 AP31 AP43

AR2 AK16

AL8

AT10 AT15 AT17 AT20 AT26 AT29 AT36 AT38

D42 AV13

AM14

AV22 AV24 AV31 AV33 BB25 AV40

AV6

AW2

F43 AY10

AM24

AY15 AY20 AY26 AY29

AY7

B11

B15

K39 L2 L44

AM26

M17 M22 N12 N35 N39 N6 P22 P24 P26 P28

AM28

P30 P32 R12 R14 R16 R2 R34 R38 R44 R8

AM30

T43 U10 U16 U28 U34 U38 U42 U6 V14 V16

AM32

V26 V43 W2 W44 Y14 Y16 Y24 Y28 Y34 Y36

AM16

Y40 Y8

LYNXPOINT

MOBILE

OMIT_TABLE

FCBGA

U1100

AB8

AC2 AC44 AD14 AD16 AD18 AD30 AD32 AD40

AD6

AD8 AE16 AE28 AF38

AF8 AG16

AG2 AG26 AG28 AG44 AJ16 AJ18 AJ20 AJ22 AJ24 AJ34 AJ38

AJ6

AJ8 AK14 AK24 AK43 AK45 AL12

AL2 BC22 BB42

B19 B23 B27 B31 B35 B39 B7 BA40 BD11 BD15 BD19 AY36 AT43 BD31 BD35 BD39 BD7 D25 AV7 F15 F20 F29 F33 BC16 D4 G2 G38 G44 G8 H10 H13 H17 H22 H24 H26 H31 H36 H40 H7 K10 K15 K20 K29 K33 BC28

AA16 AA20 AA22 AA28

AA4 AB12 AB34 AB38

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

PCH Grounds

16 OF 81

16 OF 118

<SCH_NUM>

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(PCH 1.05V CPU I/F PWR)

PCH V_PROC_IO BYPASS

(PCH 1.05V USB2 PWR)

PCH VCC BYPASS

Current data from LPT EDS (doc #486708, Rev 1.0).

183mA Max, 68mA Idle

??mA Max, ??mA Idle

(PCH 1.05V ME CORE PWR)

PCH VCCASW BYPASS

(PCH 1.05V PCIe/DMI/SATA/USB3 PWR)

PCH VCCIO BYPASS

PCH VCCVRM BYPASS

PCH VCCSUS3_3 BYPASS

(PCH 3.3V SPI PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

PCH VCCSPI BYPASS

(PCH 3.3V THERMAL PWR)

(PCH 1.05V DIFFCLK135 PWR)

PCH CLK VCC BYPASS (PCH 1.05V CLK PLL PWR)

PCH VCCCLK BYPASS

(PCH 1.05V DIFFCLK PWR)

PCH VCCCLK BYPASS

(PCH 1.05V SSC100 PWR)

PCH VCCCLK BYPASS

PCH VCCCLK BYPASS (PCH 1.05V SSC PWR)

(PCH 1.05V USB2 PLL PWR)

Not documented in EDS!

PCH VCC BYPASS (PCH 1.05V CORE PWR)

PCH VCCUSBPLL BYPASS

(PCH 1.05V FDI PWR)

PCH VCCIO BYPASS

(PCH 3.3V GPIO/LPC PWR)

(PCH 3.3V HVCMOS PWR)

PCH VCC3_3 BYPASS

PCH VCCCLK3_3 BYPASS (PCH 3.3V CLK PWR)

PCH VCC3_3 BYPASS

PCH VCC3_3 BYPASS (PCH 3.3V USB2 PWR)

PCH VCC3_3 BYPASS

(PCH 1.5V VCCVRM PWR)

PCH VCCSUSHDA BYPASS

PCH VCCDSW3_3 BYPASS

PCH VCCIO BYPASS

(PCH 3.3V DSW PWR)

(PCH 3.3V/1.5V HDA PWR)

670mA Max, 34mA Idle

(PCH 3.3V FUSE PWR)

(PCH 3.3V SUSPEND USB PWR)

(PCH 3.3V SUSPEND RTC PWR)

10%

1UF

402

CERM

6.3V

BYPASS=U1100.AG30:6.35mm

C1777

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AD35:6.35mm

C1778

1

2

6.3V

10%

402

CERM

1UF

BYPASS=U1100.AD34:6.35mm

C1780

1

2

6.3V

10%

402

CERM

1UF

BYPASS=U1100.AA30:6.35mm

C1782

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AM18:6.35mm

C1764

1

2

PLACE_NEAR=U1100.V20:2.54mm

6.3V

10%

402

CERM

1UF

C1752

1

2

PLACE_NEAR=U1100.V20:2.54mm

6.3V

10%

402

CERM

1UF

C1751

1

2

PLACE_NEAR=U1100.V20:2.54mm

X5R-CERM-1

603

20%

22UF

6.3V

C1750

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AE18:6.35mm

C1758

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AK20:6.35mm

C1763

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AD20:6.35mm

C1757

1

2

6.3V

20% 603

X5R

10UF

BYPASS=U1100.AG18:12.7mm

C1755

1

2

6.3V

10%

1UF

402

CERM

BYPASS=U1100.AA24:6.35mm

C1756

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AK22:6.35mm

C1762

1

2

1UF

CERM 402

10%

6.3V

BYPASS=U1100.AK18:6.35mm

C1761

1

2

10UF

X5R 603

20%

6.3V

BYPASS=U1100.AK18:12.7mm

C1760

1

2

10%

1UF

402

CERM

6.3V

BYPASS=U1100.AE30:6.35mm

C1776

1

2

1UF

10%

CERM

402

6.3V

BYPASS=U1100.U35:6.35mm

C1770

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AN34:6.35mm

C1772

1

2

CERM

402

10V

20%

0.1UF

BYPASS=U1100.U30:6.35mm

C1774

1

2

BYPASS=U1100.AJ12:6.35mm

10V 402

20% CERM

0.1UF

C1787

1

2

CERM

10%

1UF

402

6.3V

BYPASS=U1100.AJ12:12.7mm

C1785

1

2

10V CERM 402

20%

0.1UF

BYPASS=U1100.AJ12:6.35mm

C1786

1

2

10%

1UF

6.3V CERM

402

BYPASS=U1100.U32:6.35mm

C1723

1

2

BYPASS=U1100.R30:6.35mm

10V

CERM

402

20%

0.1UF

C1726

1

2

16V

10%

X7R-CERM

0402

0.01UF

BYPASS=U1100.AE14:6.35mm

C1728

1

2

BYPASS=U1100.L24:6.35mm

402

10V

CERM

20%

0.1UF

C1730

1

2

BYPASS=U1100.AK30:6.35mm

CERM

402

10V

20%

0.1UF

C1732

1

2

BYPASS=U1100.P18:6.35mm

6.3V

10%

1UF

CERM

402

C1734

1

2

10V

10%

402

X5R

1UF

BYPASS=U1100.AP45:6.35mm

C1791

1

2

6.3V

20%

603

X5R

10UF

BYPASS=U1100.AP45:12.7mm

NO STUFF

C1790

1

2

0603

4.7UH-170MA-0.321OHM

CRITICAL

OMIT_TABLE

L1790

1 2

1

1/16W

5%

402

MF-LF

R1790

1 2

6.3V

20% 603

X5R

10UF

BYPASS=U1100.AF34:12.7mm

C1740

1

2

402

10%

1UF

6.3V CERM

BYPASS=U1100.M29:6.35mm

C1722

1

2

BYPASS=U1100.L29:6.35mm

10%

1UF

6.3V CERM

402

C1721

1

2

10%

1UF

6.3V CERM

402

BYPASS=U1100.L26:6.35mm

C1720

1

2

BYPASS=U1100.A16:6.35mm

402

0.1UF

CERM

20% 10V

C1700

1

2

CERM

10V 402

BYPASS=U1100.R20:6.35mm

20%

0.1UF

C1704

1

2

BYPASS=U1100.AD12:6.35mm

6.3V

10%

402

CERM

1UF

C1702

1

2

402

CERM

6.3V

1UF

10%

BYPASS=U1100.K8:6.35mm

C1708

1

2

BYPASS=U1100.R26:6.35mm

CERM

402

10V

20%

0.1UF

C1706

1

2

BYPASS=U1100.A26:6.35mm

CERM

402

10V

0.1UF

20%

C1710

1

2

PCH DECOUPLING

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

L1790

RES,FF,0 OHM,(020OHM MAX),2A,0603

1113S0022

PP3V3_SUS

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP1V5_S0

PP3V3_S5

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP3V3_SUS

PP1V05_S0

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_R

PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0

PP1V5_S0

PP1V05_S0

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_F

MIN_NECK_WIDTH=0.075 MM

17 OF 81

17 OF 118

<SCH_NUM>

11 12 13 14 15 17 50 64 65 66 69

14 15 17 18 42 62 66 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68 69 71

12 14 15 18 19 21 31 32 34 61 64 65 66 69 70 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

14 15 17 18 42 62 66 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81 11 12 13 14 15 17 50 64 65 66 69

11 12 13 14 15 17 50 64 65 66 69

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68 69 71

14 15 17 18 42 62 66 69 71

15

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

IN IN

OUT

IN

OUT

IN

OUT

IN

BI

TP

IN

OUT

G

D

S

OUT

G

D

S

NCNC

GND

VCC

NCNC

YA

G

D

SG

D

S

IN

IN IN

IN

IN IN

IN

OUT

IN

OUT

NC NC

BI IN

IN IN

IN

TP

IN

IN IN

OUT

BI IN OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Merged (CPU/PCH) Micro2-XDP

support chipset debug.

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

OBSDATA_C0

OBSFN_D0

OBSDATA_C2

OBSFN_C1

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

TCK0

TDI and TMS are terminated in CPU.

PCH/XDP Signals

(All 10 R’s)

Non-XDP Signals

PCH/XDP Signal Isolation Notes: ’Output’ non-XDP signals require pulls.

signal path needs to split between route from PCH to J1850 and path to non-XDP signal destination (to minimize stub).

Unused PCH/XDP Signals

’Output’ PCH/XDP signals require pulls.

R187x and R189x should be placed where

OBSFN_B1

OBSFN_B0

OBSDATA_A3

OBSDATA_A2

OBSDATA_A1

OBSDATA_A0

OBSDATA_B0

OBSDATA_B3

VCC_OBS_AB

Extra BPM Testpoints

CPU JTAG Isolation

SDA

TCK1

SCL

HOOK2

HOOK1

HOOK3

OBSDATA_B2

PWRGD/HOOK0

518S0847

TDO TRSTn TDI TMS

VCC_OBS_CD RESET#/HOOK6

ITPCLK#/HOOK5

OBSDATA_D3

DBR#/HOOK7

XDP_PRESENT#

OBSDATA_D2

OBSDATA_B1

OBSFN_A0 OBSFN_A1

OBSFN_C0

OBSDATA_C1

OBSDATA_C3

OBSDATA_D0 OBSDATA_D1

OBSFN_D1

ITPCLK/HOOK4

20

11

NONE NONENONE

OMIT

SHORT

201

R1897

1 2

OMIT

NONE NONENONE

SHORT

201

R1896

1 2

SHORT

NONENONE

OMIT

NONE

201

R1872

1 2

13

OMIT

NONENONE

SHORT

NONE

201

R1875

1 2

11 18

11

11 18

NONE NONE NONE

SHORT

OMIT

201

R1890

1 2

13 38

13 68 71

13

14 20

OMIT

NONENONE NONE

SHORT

201

R1893

1 2

13

OMIT

SHORT

NONENONENONE

201

R1894

1 2

13

NONENONENONE

OMIT

SHORT

201

R1879

1 2

11

11 18

14

11 18

11 34

13 65 13

14 18 14 18

OMIT

NONE NONE NONE

SHORT

201

R1895

1 2

14 35

13

14

TP-P6

TP1810

1

TP-P6

TP1811

1

TP-P6

TP1812

1

TP-P6

TP1813

1

6

18 71 74

6

18 71 74

6

71 74

PLACE_NEAR=U1100.AE2:28mm

XDP

51

MF

1/20W

2015%

R1861

2 1

PLACE_NEAR=U1100.AD3:28mm

51

XDP

MF

1/20W

2015%

R1860

2 1

PLACE_NEAR=U1100.AD1:28mm

51

XDP

MF

1/20W

2015%

R1862

2 1

PLACE_NEAR=U1100.AB3:28mm

51

XDP

MF

1/20W

2015%

R1866

2 1

SOT-563

DMN5L06VK-7

XDP

CRITICAL

PLACE_NEAR=J1800.55:28mm

Q1842

3

5

4

6

71 74

CRITICAL

DMN5L06VK-7

SOT-563

XDP

PLACE_NEAR=J1800.57:28mm

Q1842

6

2

1

330K

MF

1/20W 201

5%

R1845

1

2

SOT891

74LVC1G07GF

U1845

2

3

1

5

6

4

PLACE_NEAR=J1800.51:28mm

CRITICAL

DMN5L06VK-7

SOT-563

XDP

Q1840

3

5

4

PLACE_NEAR=J1800.53:28mm

SOT-563

DMN5L06VK-7

XDP

CRITICAL

Q1840

6

2

1

10%

0.1UF

X5R-CERM

0201

16V

C1845

1

2

19 41 58 66 71

PLACE_NEAR=U0500.M49:28mm

XDP

51

MF

1/20W

2015%

R1820

1 2

PLACE_NEAR=U0500.N54:28mm

XDP

51

MF

1/20W

2015%

R1823

2 1

6

74

6

74

6

74

6

74

6

74

6

74

6

74

6

74

6

74

1/16W MF-LF 402

150

5%

R1830

1

2

12 20 21 71

11 18 71

1K

XDP

PLACE_NEAR=U0500.AG7:2.54mm

MF

1/20W

2015%

R1805

1 2

6

74

6

74

6

74

6

19 74

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

C1806

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

C1801

1

2

M-ST-SM1

DF40RC-60DP-0.4V

XDP_CONN

CRITICAL

J1800

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

61

62

6364

78 9

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

C1800

1

2

6

71 74

6

71 74

6

74

6

74

6

74

6

71 74

6

74

6

74

6

74

TP-P6

TP1802

1

TP-P6

TP1803

1

TP-P6

TP1804

1

TP-P6

TP1805

1

TP-P6

TP1806

1

TP-P6

TP1807

1

6

74

6

74

6

74

6

74

6

74

6

74

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

C1804

1

2

1/16W 402

MF-LF

XDP

1K

5%

R1831

1

2

6

74

6

74

6

74

8

13 22 44 63 68 71 76

11 18 71

XDP

1K

PLACE_NEAR=U0500.F50:2.54mm

MF

1/20W

2015%

R1800

1 2

PLACE_NEAR=U5000.J3:2.54mm

XDP

MF

1/20W

0201

0

5%

R1802

1 2

1/16W MF-LF

402

XDP

0

5%

R1804

1 2

6

14 74

12 41 76

12 19 41 71 76

6

18 71 74

PLACE_NEAR=U0500.M53:28mm

XDP

51

MF

1/20W

2015%

R1824

2 1

SHORT

NONE NONE NONE

OMIT

201

R1876

1 2

14 18 20 14 18 20

CPU & PCH XDP

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

XDP_CPU_VCCST_PWRGD XDP_CPU_PWRBTN_L

XDP_SYS_PWROK

SMBUS_PCH_DATA

XDP_CPU_TCK

PP5V_S0

CPU_PWRGD

PP1V05_S0

XDP_PCH_TMS

XDP_CPUPCH_TRST_L

XDP_CPU_TDO

XDP_CPUPCH_TRST_L

XDP_CPU_TDI

XDP_PCH_TMS

XDP_PCH_TDO

XDP_PCH_TCK

XDP_PCH_TDI

XDP_CPU_TMS

XDP_JTAG_CPU_ISOL_L

PP3V3_S5

ALL_SYS_PWRGD

XDP_CPU_PRESENT_L

CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<19>

CPU_PWR_DEBUG

PLT_RESET_L

CPU_CFG<14> CPU_CFG<15>

XDP_DBRESET_L

CPU_CFG<1>

XDP_CPU_PREQ_L

CPU_CFG<0>

XDP_BPM_L<1>

XDP_BPM_L<0>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

XDP_PCH_TCK

CPU_CFG<3>

XDP_BPM_L<2>

XDP_BPM_L<6> XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

PM_PCH_SYS_PWROK

PM_PWRBTN_L

XDP_CPU_TCK

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

AP_CLKREQ_L

XDP_FC0_HDD_PWR_EN

XDP_DA1_USB_EXTC_OC_L XDP_DB1_USB_EXTD_OC_L

XDP_FC1_GPU_GOOD

SMBUS_PCH_CLK

XDP_CPU_PRDY_L

USB_EXTA_OC_L

CAMERA_PWR_EN

SSD_PWR_EN

USB_EXTB_OC_L

SDCONN_STATE_CHANGE_L

SD_PWR_EN

DP_AUXCH_ISOL_L

XDP_DC2_ODD_PWR_EN_L JTAG_ISP_TCK SSD_PCIE_SEL_L

XDP_DA0_USB_EXTA_OC_L

XDP_DA3_CAMERA_PWR_EN

XDP_DA2_SSD_PWR_EN

XDP_DB0_USB_EXTB_OC_L XDP_DB2_SD_PWR_EN XDP_DB3_SDCONN_STATE_CHANGE_L

MAKE_BASE=TRUE

XDP_DC1_SATARDRVR_EN

XDP_DC3_JTAG_ISP_TCK

MAKE_BASE=TRUE

XDP_DC2_ODD_PWR_EN_L

XDP_DD0_SSD_PCIE_SEL_L

XDP_DD2_ENETSD_CLKREQ_L

XDP_DD1_MLB_RAMCFG1

XDP_DC1_SATARDRVR_EN

XDP_DD3_AP_CLKREQ_L

MAKE_BASE=TRUE

XDP_DD1_MLB_RAMCFG1

MAKE_BASE=TRUE

XDP_DD2_ENETSD_CLKREQ_L

XDP_DC0_DP_AUXCH_ISOL_L

PP1V05_SUS

XDP_PCH_TDI

XDP_TRST_L

XDP_PCH_TDO

XDP_CPURST_L

PPVCCIO_S0_CPU

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<16>

CPU_CFG<17>

CPU_CFG<2>

CPU_CFG<8>

CPU_CFG<11>

18 OF 118

18 OF 81

<SCH_NUM>

19 37 49 50 58 59 62 63 65 66 69 70 71

14 15 17 18 42 62 66 69 71

6

18 71 74

6

18 71 74

11 18 71

12 14 15 17 19 21 31 32 34 61 64 65 66 69 70 71 81

6

18 71 74

6

18 71 74

64 69

11 18 71

5 6 8

10 58

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN

OUT

IN

OUT

IN

OUT

NC NC

IN

OUT

S

D

G

SDG

OUT OUT

OUT

IN

Y

A

B

08

Y

A

B

08

IN

32.768K

GND

THRM

VOUT

X2 X1

25M_A 25M_B 25M_C

VIOE_25M_A VIOE_25M_B VIOE_25M_C

VG3HOT

NC

VDD

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

PCH PWROK Generation

PCH 33MHz Clocks

System RTC Power Source & 32kHz / 25MHz Clock Generator

complicates VDD_25M power, forcing at least S4. Both issues to be addressed in upcoming part

WF: Do we need this?

Coin-Cell & No G3Hot: 3.3V S5

available ~3.3V power

create VDD_RTC_OUT. +V3.3A should be first

internally ORed to

VBAT and +V3.3A are

to reduce VBAT draw.

For SB RTC Power

No Coin-Cell: 3.42V G3Hot (no RC)

least 5ms after all rails are valid.

(SLG3NB148C).

NOTE: ALL_SYS_PWRGD must remain low until at

Coin-Cell: VBAT (300-ohm & 10uF RC)

SMC controls strap enable to allow in-field control of strap setting.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

PCH ME Disable Strap

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

No Coin-Cell: 3.3V S5 No bypass necessary

NOTE: 30 PPM crystal required

IPD = 9-50k

Coin-Cell & G3Hot: 3.42V G3Hot

Camera XTAL Power TBT XTAL Power

PCH Reset Button

VDDIO_25M_A: SB power rail for XTAL circuit. VDDIO_25M_B: Camera power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

GreenClk 25MHz Power

SB XTAL Power

NOTE: SLG3NB148A provides slow rising edge on 25MHZ_B when powered from

1.2V VDDIO. Redwood Ridge also

6

18 74

5%

0

MF-LF

1/16W

402

XDP

R1996

1 2

5%

201

1/20W

MF

22

PLACE_NEAR=U1100.E44:6.35mm

R1956

1 2

5%

201

1/20W

22

PLACE_NEAR=U1100.D44:6.35mm

MF

R1955

1 2

11 76

50 71 76

41 76

11 76

5%

201

1/20W

MF

PLACE_NEAR=U1100.A40:6.35mm

22

R1959

1 2

11 76

5%

0

OMIT

1/16W MF-LF 402

SILK_PART=SYS RESET

R1997

1

2

5% 1/16W

402

4.7K

MF-LF

R1995

1

2

12 41 71 76

11 75

28 75

1UF

6.3V

10% CERM

402

C1910

1

2

X5R

10% 10V

402-1

1UF

C1902

1

2

0.1UF

20%

CERM

402

10V

C1920

1

2

20% 10V

CERM

402

0.1UF

C1922

1

2

5%

NO STUFF

1M

MF-LF

1/16W 402

R1906

1

2

402

CERM

10V

20%

0.1UF

C1924

1

2

5%

0

402

MF-LF

1/16W

R1905

1 2

12PF

5%

0402

C0G-CERM

50V

C1905

12

5%

0402

12PF

50V

C0G-CERM

C1906

1 2

41 42

5%

201

1/20W MF

1K

R1921

1

2

5%

201

1/20W MF

100K

R1920

1

2

11 76

37 75

DMN5L06VK-7

SOT-563

Q1920

3

5

4

DMN5L06VK-7

SOT-563

Q1920

6

2

1

5%

0

0201

1/20W MF

NO STUFF

R1948

2

1

12 19 71 76

5%

402

MF-LF

1/16W

1K

R1949

1 2

12 18 41 71 76 58

18 41 58 66 71

74LVC2G08GT/S505

CKPLUS_WAIVE=UNCONNECTED_PINS

PLACE_NEAR=U1100.AD7:7MM

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

U1950

5

6

4

8

3

74LVC2G08GT/S505

SOT833

U1950

1

2

4

8

7

5%

402

MF-LF

2.0K

1/16W

R1950

1

2

BYPASS=U1950:5MM

0.1UF

402

CERM

10V

20%

C1950

1

2

29 30 41 42

5%

0

0201

1/20W

MF

R1947

1

2

SLG3NB148CV

TQFN

CRITICAL

U1900

9 8 15

12

71016217

5

13

11

6

14

1

4

3

3.2X2.5MM-SM

25.000MHZ-20PPM-12PF-85C

CRITICAL

Y1905

2 4

1 3

Chipset Support

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

PM_PCH_PWROK

SYS_PWROK_R

PM_PCH_PWROK

MAKE_BASE=TRUE

PM_S0_PGOOD

CPUVR_PGOOD

PP3V3_S0

PCH_CLK33M_PCIIN

PP5V_S0

HDA_SDOUT_R

PM_SYSRST_L

LPC_CLK33M_LPCPLUS

PCH_CLK33M_PCIOUT

XDP_DBRESET_L

PP1V5_S0

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE_L

LPC_CLK33M_SMC_R

ALL_SYS_PWRGD

PM_PCH_SYS_PWROK

PP3V3_S0

LPC_CLK33M_LPCPLUS_R

PP3V42_G3H

SMC_DELAYED_PWRGD

SYSCLK_CLK32K_RTC

PPVRTC_G3H

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_SB SYSCLK_CLK25M_CAMERA SYSCLK_CLK25M_TBT

PP1V5_S0

PP3V3_TBTLC

PP3V3_S5

PP3V42_G3H

PP1V2_CAM_XTALPCIEVDD

SYSCLK_CLK25M_X1

SYSCLK_CLK25M_X2

LPC_CLK33M_SMC

<SCH_NUM>

19 OF 118

19 OF 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

18 37 49 50 58 59 62 63 65 66 69 70 71

11 12 13 15 17 19 52 64 66 68 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51

52 55 65 66 67 69 71 81

19 35 38 39 41 42 43 44 50 56 57 66 69 71

11 12 15 69

11 12 13 15 17 19 52 64 66 68 69 71

20 28 29 69

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70

71 81

19 35 38 39 41 42 43 44 50 56 57 66 69 71

36

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

OUT

G

D

S

G

D

S

OUT

IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

GND

1Y

VCC

1A

3Y 3A

2A 2Y

Y

B

A

IN

OUT

IN

G

SYM_VER_1

D

S

OUT

IN

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

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C

PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SD Card Reader is always USB3 in this implementaton.

Flexible I/O Configuration Strap

Must pull signal correctly even if always USB or PCIe

Flexible I/O Aliases

From RIO Connector

Redwood Ridge Support

RR output is open-drain, no isolation necessary

To/From PCH

TBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

U2060 supports I/O’s powered when VCC=0V

Redwood Ridge JTAG Isolation

GPIO Glitch Prevention

RAM Configuration Straps

DEVSLP not supported on LPT-H

To/From PCH

(Pull-Up on CPU Page)

Buffered

LCD HPD Inverter

Platform Reset Connections

Unbuffered

RIO SD Card Reader Support

HDMI HPD pull-down

GS3 Connector Support

(Pull-ups on PCH page)

To/From RR

Pull-up values TBD

TBT_PWR_EN must be high for JTAG Programming

18

14

14 18

14

RAMCFG0:L

1K

5%

1/20W

MF

201

R2002

1

2

1/20W MF

5%

1K

RAMCFG1:L

201

R2011

1

2

1K

5%

1/20W

MF

RAMCFG2:L

201

R2012

1

2

RAMCFG3:L

1K

5% MF

1/20W 201

R2013

1

2

DMN5L06VK-7

SOT-563

Q2040

3

5

4

DMN5L06VK-7

SOT-563

Q2040

6

2

1

10K

MF

1/20W

5%

201

R2070

1

2

35

MF

1/20W

5%

470K

201

R2040

1

2

20 28 13

12 41 50 71

10K

5%

1/20W

MF

201

R2075

1

2

14 20 28 14 20 28

14

100K

MF

1/20W

5%

201

R2030

1

2

13 20 68 71 76

13 20 68 71 76 13 20 68 71 76

13 20 68 71 76

14

28

10K

5% 1/20W MF 201

R2063

1

2

28

MF

1/20W

5%

10K

201

R2062

1

2

10K

5%

1/20W

MF

201

R2061

1

2

68 71

0201

16V

X5R-CERM

0.1UF

10%

C2060

1

2

MF

1/20W

5%

100K

201

R2010

1

2

12 68 70

SN74AUP3G07DQER

X2SON

CRITICAL

U2060

1

3

6

4

8

7

5

2

SOT665

TC7SZ08FEAPE

CRITICAL

U2030

2

1

3

5

4

402

20% 10V

CERM

0.1UF

C2080

1

2

5%

402

100K

1/16W MF-LF

R2080

1

2

CRITICAL

SC70-HF

MC74VHC1G08

U2080

3

2

1

4

5

402

1/16W MF-LF

0

5%

R2091

1 2

0

1/16W MF-LF

402

5%

R2087

1 2

MF-LF

1/16W

0

402

5%

R2088

1 2

0

MF-LF

1/16W

402

5%

R2085

1 2

6.3V

CERM-X5R

0201

0.1UF

10%

C2030

1

2

MF

1/20W

5%

470K

201

R2041

1

2

12 18 21 71

402

MF-LF

5%

1/16W

0

R2071

1 2

1/16W MF-LF

33

402

5%

R2081

1 2

33

1/16W MF-LF

402

5%

R2083

1 2

36

28

34

35

22

20 50 71 76

41

20 50 71 76

67

DFN1006H4-3

DMN32D2LFB4

Q2010

3

1

2

5

14 18

20 28

SOT833

CRITICAL

74LVC2G08GT/S505

U2000

1

5

2

6

4

8

7

3

16V 0201

X5R-CERM

0.1UF

10%

C2013

1

2

28

28 41 42 43

Project Chipset Support

SYNC_DATE=01/14/2013

SYNC_MASTER=J15_REFERENCE

TBT_PWR_EN JTAG_ISP_TCK

TBT_CIO_PLUG_EVENT_L

MAKE_BASE=TRUE

HDMI_HPD

PP3V3_TBTLC

LPCPLUS_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

TBT_PCIE_RESET_L

PP3V3_S4

CAM_PCIE_RESET_L

AP_RESET_L

SSD_RESET_L

PP3V3_S0

PLT_RESET_L

MAKE_BASE=TRUE MAKE_BASE=TRUE

LPCPLUS_RESET_L

PCA9557D_RESET_L

SMC_LRESET_L

DP_IG_A_HPD_L

LCD_HPD

SSD_DEVSLP

SD_SEL_PCIE_L_USB_H

USB3_SD_R2D_C_N

USB3_SD_D2R_N

USB3_SD_R2D_C_P

MAKE_BASE=TRUE

USB3_SD_R2D_C_N

MAKE_BASE=TRUE

USB3_SD_D2R_P USB3_SD_D2R_N

MAKE_BASE=TRUE

SMC_PME_SDCONN

MLB_RAMCFG3 MLB_RAMCFG2 XDP_DD1_MLB_RAMCFG1 MLB_RAMCFG0

TBT_PWR_EN

JTAG_TBT_TCK

TBT_PWR_EN_PCH LPC_PWRDWN_L

TBT_CIO_PLUG_EVENT_L

JTAG_TBT_TDIJTAG_ISP_TDI

JTAG_TBT_TDOJTAG_ISP_TDO

JTAG_TBT_TMS_PCH

PP3V3_S0

JTAG_TBT_TMS

USB3_SD_D2R_P

PP3V3_S0

SMC_PME_S4_DARK_L

PP3V3_S0

MAKE_BASE=TRUE

USB3_SD_R2D_C_P

SDCONN_STATE_CHANGE_L

PP3V3_S3

RIO_SDCONN_STATE_CHANGE_L

<SCH_NUM>

20 OF 118

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34 39 42 43 46 47 65 66 68 69 70 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

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49 51 52 55 65 66 67 69

71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51

52 55 65 66 67 69 71 81

13 21 22 44 46 47 65 68 69 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN IN

IN

OUT

IN

G

D

S

OUT

SDG

S

D

G

S

D

G

SDG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

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A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN CPUVDDQ_EN

CPUVDDQ_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

MEM S0 "PGOOD" for CPU

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

6 0 1 1 1 1 1 1 1

5 0 1 1 1 0 (*) 1 1 1

4 0 0 1 1 X 1 0 1

3 0 0 0 1 X 1 0 0

2 0 0 1 1 1 1 0 1

1 0 1 1 1 1 1 1 1

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

75mA max load @ 0.75V

S0

to

S3

to

60mW max power

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

S0

MEMVTT Clamp

Ensures CKE signals are held low in S3

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

14 12 41 66 71

12 18 20 71

CPUMEM:S0

1/16W

5%

MF-LF

100K

402

R2102

1

2

21 60 70

10K

MF-LF 402

1/16W

5%

CPUMEM:S0

R2110

1

2

100K

5% 1/16W MF-LF

402

CPUMEM:S0

R2115

1

2

23 24 25 26

CPUMEM:S0

402

MF-LF

1/16W

5%

1K

R2116

1

2

65

CPUMEM:S0

1/16W

10K

5% MF-LF

402

R2105

1

2

12 34 38 41 66 68 71

CPUMEM:S0

MF-LF

1/16W

402

5%

100K

R2101

1

2

21 60 70

CPUMEM:S0

5%

402

100K

1/16W MF-LF

R2151

1

2

NO STUFF

50V

0.001UF

20%

CERM

402

C2151

1

2

CPUMEM:S0

10

5%

MF-LF

603

1/10W

R2150

1

2

402

0

5% 1/16W MF-LF

CPUMEM:S3

R2117

1 2

6

21

402

43.2K

1/16W

1%

MF-LF

R2121

1

2

1%

MF-LF

1/16W

27.4K

402

R2120

1

2

SOT-563

DMB53D0UV

CRITICAL

Q2120

5

3

4

5%

10K

MF-LF

1/16W 402

R2122

1

2

CRITICAL

SOT-563

DMB53D0UV

Q2120

6

2

1

6

12 74

10V

0.047UF

10%

X5R-CERM

0402

C2120

1

2

0.1UF

CPUMEM:S0

10V CERM 402

20%

C2116

1

2

201

6.3V X5R

0.047UF

10%

NO STUFF

C2117

1

2

SOT-563

DMN5L06VK-7

CPUMEM:S0

CRITICAL

Q2100

3

5

4

DMN5L06VK-7

CPUMEM:S0

CRITICAL

SOT-563

Q2100

6

2

1

SOT-563

CRITICAL

CPUMEM:S0

DMN5L06VK-7

Q2105

6

2

1

SOT-563

CRITICAL CPUMEM:S0

DMN5L06VK-7

Q2105

3

5

4

DMN5L06VK-7

SOT-563

CRITICAL

CPUMEM:S0

Q2110

6

2

1

CRITICAL CPUMEM:S0

DMN5L06VK-7

SOT-563

Q2110

3

5

4

DMN5L06VK-7

SOT-563

CRITICAL

CPUMEM:S0

Q2115

6

2

1

DMN5L06VK-7

CRITICAL

CPUMEM:S0

SOT-563

Q2115

3

5

4

CPUMEM:S0

CRITICAL

DMN5L06VK-7

SOT-563

Q2150

3

5

4

CPUMEM:S0

CRITICAL

DMN5L06VK-7

SOT-563

Q2150

6

2

1

CPU Memory S3 Support

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

MEMPWR_DIV

CPUVDDQ_EN_L

PP3V3_S3

PM_SLP_S3_L

PP5V_S3

VTTCLAMP_EN

VTTCLAMP_L

MEMVTT_EN

MEMRESET_ISOL_LS5V_L

MEM_RESET_L

ISOLATE_CPU_MEM_L

MAKE_BASE=TRUE

CPU_MEM_RESET_L

PLT_RESET_L

MEMVTT_EN_L

MEMVTT_EN

CPUVDDQ_EN

PM_MEM_PWRGD_L

PM_MEM_PWRGD

PP3V3_S5

PM_SLP_S4_L

PP1V35_S3

CPU_MEM_RESET_L

PPVTT_S0_DDR

PP5V_S3

PP1V35_S3RS0_CPUDDR

<SCH_NUM>

21 OF 118

21 OF 81

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21 37 60 65 66 69 71

22

12 14 15 17 18 19 31 32 34 61 64 65 66 69 70 71 81

22 46 60 65 69 71

27 60 69 71

21 37 60 65 66 69 71

6 8

10 65 66 69 81

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

OUT

V-

V+

V-

V+

IN

G

D

SG

D

SG

D

S G

D

S

IN

G

D

SG

D

SG

D

SG

D

S

IN

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

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C

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

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SHEET

R

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REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

a DAC output, cannot enable

R22x6 pin 2:

CPU-Based Margining

VRef current: DAC step size:

Page Notes

Pins B1 & B4:

both at the same time!

Addr=0x98(WR)/0x99(RD)

(OD)

DDR3L (1.35V) 6.99mV per step

DDR3 (1.5V) 7.70mV per step

signals for independent DAC

to remove short due to CPU.

- =PP3V3_S3_VREFMRGN

NOTE: MEMVREG and FRAMEBUF share

FETs for CPU isolation during S3

DAC sets voltage level, PCA9557 & FETs enable outputs

(All 4 R’s)

EN RC’s to avoid drain glitches

BOM options provided by this page:

- =I2C_VREFDACS_SCL

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

- =I2C_VREFDACS_SDA

Signal aliases required by this page:

Power aliases required by this page:

Always used, regardless

VRef Dividers

of margining option.

Q2265 pin 6:

watchdog will disable margining.

soft-resets and sleep/wake cycles.

VREFCA. Split into two

margining support. When DAC margining VREFCA ensure ISOLATE_CPU_MEM_L is low

DAC-Based Margining

and disables margining after platform reset.

NOTE: Margining will be disabled across all

RST* on ’platform reset’ so that system

Addr=0x30(WR)/0x31(RD)

Margined target:

Nominal value

DAC Channel: PCA9557D Pin:

1

A

DDR3 (1.5V)

B 2

C 3

DDR3L (1.35V)

C 4

DDR3L (1.35V)

DAC range: Margined range:

+901uA - -911uA (- = sourced)

0.000V - 1.508V (0x00 - 0x75)

7.68mV / step @ output 7.67mV / step @ output

+811uA - -816uA (- = sourced)

0.269V - 1.083V (+/- 406mV)

0.000V - 1.354V (0x00 - 0x69)

0.300V - 1.200V (+/- 450mV)

0.750V (DAC: 0x3A = 0.747mV)

DDR3 (1.5V)

MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA

MEM VREG

D 5

0.000V - 2.707V (0x00 - 0xD2)

0.675V (DAC: 0x34 = 0.670mV)

0.275V - 1.075V (+/- 400mV)

0.299V - 1.206V (+/- 453mV)

0.000V - 3.004V (0x00 - 0xE9)

- =PPDDR_S3_MEMVREF

- DDRVREF_DAC - Stuffs DAC margining circuit.

DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

1.500V (DAC: 0x74 = 1.495V) 1.343V (DAC: 0x68 = 1.341V)

0.932V - 1.760V (+/- 414mV)

0.950V - 1.750V (+/- 400mV)

+28uA - -29uA (- = sourced)

3.923mV / step @ output

NOTE: CPU DAC output step sizes:

1.200V - 1.800V (+/- 300mV)

1.199V - 1.801V (+/- 301mV) +36uA - -36uA (- = sourced)

2.575mV / step @ output

NOTE: DDR3 assumes TPS51916 supply with 10.0k/49.9k divider

NOTE: CPU has single output for

Q2225 pin 6:

60

10%

0.1UF

0201

CERM-X5R

6.3V

DDRVREF_DAC

C2202

1

2

DDRVREF_DAC

402

MF-LF

1/16W

33.2K

1%

R2214

1 2

201

5%

100K

1/20W

MF

DDRVREF_DAC

R2213

1

2

201

5%

100K

1/20W

MF

DDRVREF_DAC

R2215

1

2

CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

MAX4253

UCSP

CRITICAL DDRVREF_DAC

U2204

A3

A2

A1

A4

B1

B4

UCSP

DDRVREF_DAC

CRITICAL

MAX4253

U2204

C3

C2

C1

C4

B1

B4

SHORT

402

NONE NONE

NONE

OMIT

R2218

1 2

7

74

7

74

21

SOT-563

CRITICAL

DMN5L06VK-7

Q2260

6

2

1

201

5%

1/20W

DDRVREF_DAC

100K

MF

R2202

1

2

SOT-563

CRITICAL

DMN5L06VK-7

Q2220

3

5

4

SOT-563

CRITICAL

DMN5L06VK-7

Q2260

3

5

4

SOT-563

DMN5L06VK-7

CRITICAL

Q2220

6

2

1

7

CRITICAL

DMN5L06VK-7

DDRVREF_DAC

SOT-563

PLACE_NEAR=Q2220.6:2.54mm

Q2225

6

2

1

201

DDRVREF_DAC

100K

5%

1/20W

MF

R2201

1

2

1/16W MF-LF

5%

402

100K

DDRVREF_DAC

R2225

1 2

0.1UF

DDRVREF_DAC

20% 10V

CERM

402

C2225

1

2

PLACE_NEAR=Q2260.6:2.54mm

SOT-563

DDRVREF_DAC

CRITICAL

DMN5L06VK-7

Q2265

6

2

1

0.1UF

402

CERM

10V

20%

DDRVREF_DAC

C2245

1

2

DDRVREF_DAC

1/16W MF-LF

5%

402

100K

R2245

1 2

1/16W MF-LF

5%

402

DDRVREF_DAC

100K

R2265

1 2

SOT-563

DDRVREF_DAC

CRITICAL

DMN5L06VK-7

Q2225

3

5

4

0.1UF

20% 10V

CERM

402

DDRVREF_DAC

C2265

1

2

SOT-563

DDRVREF_DAC

CRITICAL

DMN5L06VK-7

Q2265

3

5

4

0.1UF

402

CERM

10V

20%

DDRVREF_DAC

C2285

1

2

201

100K

5%

1/20W

MF

DDRVREF_DAC

R2207

1

2

1/16W MF-LF

402

DDRVREF_DAC

5%

100K

R2285

1 2

201

100K

5%

1/20W

MF

DDRVREF_DAC

R2208

1

2

PLACE_NEAR=Q2225.1:2.54mm

MF-LF

402

1/16W

DDRVREF_DAC

332

1%

R2226

1 2

PLACE_NEAR=Q2225.4:2.54mm

MF-LF

402

1/16W

DDRVREF_DAC

332

1%

R2246

1 2

PLACE_NEAR=Q2265.1:2.54mm

MF-LF

402

1/16W

DDRVREF_DAC

332

1%

R2266

1 2

PLACE_NEAR=Q2265.4:2.54mm

MF-LF

402

1/16W

DDRVREF_DAC

332

1%

R2286

1 2

5% 1/16W MF-LF 402

DDRVREF_DAC

1M

R2217

1

2

0.022UF

6.3V

10% X5R-CERM

0201

PLACE_NEAR=Q2260.3:2mm

C2280

1

2

0.022UF

PLACE_NEAR=Q2220.3:2mm

6.3V

10% X5R-CERM

0201

C2260

1

2

0.022UF

PLACE_NEAR=Q2260.6:2mm

6.3V

10% X5R-CERM

0201

C2240

1

2

201

PLACE_NEAR=C2280.1:2mm

5%

2

1/20W

MF

R2283

1 2

201

MF

1%

24.9

1/20W

R2280

1 2

PLACE_NEAR=R2281.2:1mm

1% 1/16W MF-LF

402

1K

R2282

1

2

201

PLACE_NEAR=C2260.1:2mm

1/20W

MF

5%

2

R2263

1 2

201

MF

1/20W

1%

24.9

R2260

1 2

PLACE_NEAR=R2283.2:1mm

1K

1%

402

1/16W MF-LF

R2281

1

2

1% 1/16W

402

MF-LF

1K

PLACE_NEAR=R2261.2:1mm

R2262

1

2

201

MF

1/20W

1%

24.9

R2240

1 2

PLACE_NEAR=R2263.2:1mm

402

1/16W MF-LF

1K

1%

R2261

1

2

1K

402

MF-LF

1% 1/16W

PLACE_NEAR=R2241.2:1mm

R2242

1

2

0.022UF

PLACE_NEAR=Q2220.6:2mm

6.3V

10% X5R-CERM

0201

C2220

1

2

201

5%

2

1/20W

MF

PLACE_NEAR=C2240.1:2mm

R2243

1 2

201

PLACE_NEAR=C2220.1:2mm

2

5%

1/20W

MF

R2223

1 2

201

MF

1/20W

1%

24.9

R2220

1 2

PLACE_NEAR=R2243.2:1mm

402

1/16W MF-LF

1K

1%

R2241

1

2

1K

1% 1/16W

402

MF-LF

PLACE_NEAR=R2221.2:1mm

R2222

1

2

PLACE_NEAR=R2223.2:1mm

1K

1%

402

1/16W MF-LF

R2221

1

2

20

QFN

PCA9557

DDRVREF_DAC

CRITICAL

U2201

3 4 5

8

6 7 9 10 11 12 13 14

15

1 2

17

16

13 18 22 44 63 68 71 76

CRITICAL DDRVREF_DAC

DAC5574

MSOP

U2200

9

10

3

6

7

8

1

2

4

5

13 18 22 44 63 68 71 76

10%

0.1UF

0201

CERM-X5R

6.3V

DDRVREF_DAC

C2201

1

2

6.3V

20%

CERM

402-LF

2.2UF

DDRVREF_DAC

C2200

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

DDRVREF_DAC

C2205

1

2

SYNC_DATE=10/31/2012

DDR3 VREF MARGINING

SYNC_MASTER=J15_MLB

CPU_MEM_VREFCA_B_ISOL

VREFMRGN_DQ_A_RDIV

VREFMRGN_CA_B_EN_RC

CPU_MEM_VREFDQ_B_ISOL

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

CPU_MEM_VREFDQ_A_ISOL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

VREFMRGN_MEMVREG_BUF

VREFMRGN_MEMVREG_EN

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_DQ_A_EN

VREFMRGN_CA_AB

VREFMRGN_DQ_B

PCA9557D_RESET_L

VREFMRGN_DQ_B_RDIV

PP1V35_S3

MEM_VREFDQ_A_RC

MEM_VREFDQ_B_RC

CPU_MEM_VREFCA_A_ISOL

MEM_VREFCA_A_RC

MEM_VREFCA_B_RC

VREFMRGN_CA_B_EN

VREFMRGN_DQ_A_EN_RC

VREFMRGN_DQ_B_EN

VREFMRGN_DQ_B_EN_RC

VREFMRGN_CA_A_EN_RC

VREFMRGN_FRAMEBUF_BUF

DDRREG_FB

PP3V3_S3

VREFMRGN_CA_B_RDIV

VREFMRGN_CA_A_RDIV

VREFMRGN_DQ_A

CPU_DIMMA_VREFDQ

MEMRESET_ISOL_LS5V_L

CPU_DIMM_VREFCA

CPU_DIMMB_VREFDQ

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK

VREFMRGN_FRAMEBUF_EN

VREFMRGN_CA_A_EN

PP3V3_S3

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S3_VREFMRGN

MIN_LINE_WIDTH=0.3 mm

22 OF 81

22 OF 118

<SCH_NUM>

25 26 70 74

23 24 70 74 77

21 46 60 65 69 71

13 20 21 22 44 46 47 65 68 69 71

23 24 70 74 77

25 26 70 74

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

X5R-CERM

2.2UF

402

10V

20%

C2340

1

2

X5R-CERM

2.2UF

402

10V

20%

C2341

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2343

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2344

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2345

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2353

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2354

1

2

0.1UF

10%

6.3V CERM-X5R 0201

C2355

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2363

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2364

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2365

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2373

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2374

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2375

1

2

201

240

1% 1/20W MF

R2300

2

1

201

1/20W

1%

240

MF

R2310

2

1

201

240

1% 1/20W MF

R2320

2

1

201

MF

1/20W

240

1%

R2330

2

1

201

0.47UF

20%

4V

CERM-X5R-1

C2307

1

2

10%

201

X5R

6.3V

0.047UF

C2309

1

2

10%

201

X5R

6.3V

0.047UF

C2308

1

2

10%

201

X5R

6.3V

0.047UF

C2319

1

2

10%

201

X5R

6.3V

0.047UF

C2318

1

2

201

CERM-X5R-1

4V

20%

0.47UF

C2317

1

2

10%

201

X5R

6.3V

0.047UF

C2329

1

2

10%

201

X5R

6.3V

0.047UF

C2328

1

2

201

0.47UF

4V

20%

CERM-X5R-1

C2327

1

2

10%

201

X5R

6.3V

0.047UF

C2339

1

2

10%

201

X5R

6.3V

0.047UF

C2338

1

2

201

0.47UF

CERM-X5R-1

4V

20%

C2337

1

2

10%

201

X5R

6.3V

0.047UF

C2379

1

2

10%

201

X5R

6.3V

0.047UF

C2378

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2377

1

2

10%

201

X5R

6.3V

0.047UF

C2369

1

2

10%

201

X5R

6.3V

0.047UF

C2368

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2367

1

2

10%

201

X5R

6.3V

0.047UF

C2359

1

2

10%

201

X5R

6.3V

0.047UF

C2358

1

2

201

240

1% 1/20W MF

R2370

2

1

201

MF

1/20W

1%

240

R2360

2

1

201

20%

4V

CERM-X5R-1

0.47UF

C2357

1

2

10%

201

X5R

6.3V

0.047UF

C2349

1

2

10%

201

X5R

6.3V

0.047UF

C2348

1

2

201

0.47UF

20%

4V

CERM-X5R-1

C2347

1

2

201

240

1% 1/20W MF

R2350

2

1

201

MF

1/20W

1%

240

R2340

2

1

10%

0.1UF

0201

CERM-X5R

6.3V

C2335

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2334

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2333

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2325

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2324

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2323

1

2

CERM-X5R 0201

10%

0.1UF

6.3V

C2315

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2314

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2313

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2305

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2304

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2303

1

2

X5R-CERM

2.2UF

402

10V

20%

C2301

1

2

X5R-CERM

2.2UF

20% 10V

402

C2300

1

2

20% 10V

402

2.2UF

X5R-CERM

C2311

1

2

20% 10V

402

2.2UF

X5R-CERM

C2351

1

2

X5R-CERM

402

10V

20%

2.2UF

C2310

1

2

20% 10V

402

2.2UF

X5R-CERM

C2350

1

2

20% 10V

402

2.2UF

X5R-CERM

C2321

1

2

20% 10V

402

X5R-CERM

2.2UF

C2361

1

2

402

10V

20%

2.2UF

X5R-CERM

C2320

1

2

10V 402

2.2UF

X5R-CERM

20%

C2360

1

2

20% 10V

402

2.2UF

X5R-CERM

C2331

1

2

402

10V

20%

2.2UF

X5R-CERM

C2330

1

2

20% 10V

402

X5R-CERM

2.2UF

C2371

1

2

X5R-CERM

402

20% 10V

2.2UF

C2370

1

2

DDR3-1333

OMIT_TABLE

FBGA

U2300

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

DDR3-1333

FBGA

U2310

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

DDR3-1333

FBGA

U2320

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2330

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

DDR3-1333

FBGA

U2340

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

DDR3-1333

FBGA

U2350

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

OMIT_TABLE

FBGA

U2360

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

FBGA

DDR3-1333

OMIT_TABLE

U2370

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

DDR3 SDRAM Bank A (1 OF 2)

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

PP1V35_S3_MEM

MEM_A_ZQ<5>

MEM_A_A<4>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<6>

MEM_A_A<11>

MEM_A_DQS_N<5>

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<50> MEM_A_DQ<51>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<7>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<62>

MEM_A_DQS_N<7>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<7>

MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_A<2>

MEM_A_A<0>

MEM_A_DQS_P<6>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<6>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<54>

MEM_A_DQS_N<6>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQ<55>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_A<2>

PP1V35_S3_MEM

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<46>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<5>

MEM_A_DQ<47>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_A<2>

MEM_A_DQ<32>

MEM_A_CAS_L

MEM_A_DQ<37>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<4>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<38>

MEM_A_DQS_N<4>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<4>

MEM_A_DQ<39>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_A<2>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_RAS_L

MEM_A_ZQ<3>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<26>

MEM_A_DQS_N<3>

MEM_A_CS_L<0>

MEM_A_DQS_P<3>

MEM_A_DQ<29>

MEM_A_DQ<25>

MEM_A_DQ<30>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<24>

MEM_A_DQ<31>

MEM_A_A<2>

MEM_A_A<3>

PP1V35_S3_MEM

MEM_A_A<2>

MEM_A_A<4>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<2>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<20>

MEM_A_DQS_N<2>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<2>

MEM_A_DQ<19>

MEM_A_DQ<23>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_A<7>

PP1V35_S3_MEM

MEM_A_DQ<14>

MEM_A_CLK_P<0>

MEM_A_A<1>

MEM_A_DQ<9>

MEM_A_A<0>

MEM_A_DQ<7>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_RAS_L

MEM_A_ZQ<1>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<5>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<8>

MEM_A_DQS_N<1>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<1>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<11>

MEM_A_DQ<15>

MEM_A_DQ<10>

MEM_A_A<2>

MEM_A_A<7>

PP1V35_S3_MEM

MEM_A_DQS_P<0>

MEM_A_CKE<0>

MEM_A_DQS_N<0>

MEM_A_A<11> MEM_A_A<12>

MEM_A_A<2>

MEM_A_DQ<0>

MEM_A_DQ<5> MEM_A_DQ<3> MEM_A_DQ<1>

MEM_A_DQ<4>

MEM_A_CS_L<0>

MEM_A_DQ<2>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3> MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<0> MEM_A_A<1>

MEM_A_A<5> MEM_A_A<6>

MEM_A_A<8> MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<0>

MEM_A_RAS_L

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

<SCH_NUM>

23 OF 118

23 OF 81

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7

23 24

27 77

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7

23

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77

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77

7

24 77

22 23 24 70 74 77

7

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7

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22 23 24 70 74 77

7

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77

7

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77

7

23

24 27 77

7

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7

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22 23 24 70 74 77

23 24 25 26 46 69 77

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w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

DDR3-1333

OMIT_TABLE

FBGA

U2440

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2450

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2460

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2470

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

201

1/20W MF

1%

240

R2400

2

1

201

240

1% 1/20W MF

R2410

2

1

201

1/20W

240

MF

1%

R2420

2

1

201

240

1% 1/20W MF

R2430

2

1

201

0.47UF

20%

4V

CERM-X5R-1

C2407

1

2

10%

201

X5R

6.3V

0.047UF

C2409

1

2

10%

201

X5R

6.3V

0.047UF

C2408

1

2

10%

201

X5R

6.3V

0.047UF

C2419

1

2

10%

201

X5R

6.3V

0.047UF

C2418

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2417

1

2

10%

201

X5R

6.3V

0.047UF

C2429

1

2

10%

201

X5R

6.3V

0.047UF

C2428

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2427

1

2

10%

201

X5R

6.3V

0.047UF

C2439

1

2

10%

201

X5R

6.3V

0.047UF

C2438

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2437

1

2

10%

201

X5R

6.3V

0.047UF

C2479

1

2

10%

201

X5R

6.3V

0.047UF

C2478

1

2

201

0.47UF

CERM-X5R-1

4V

20%

C2477

1

2

10%

201

X5R

6.3V

0.047UF

C2469

1

2

10%

201

X5R

6.3V

0.047UF

C2468

1

2

201

4V

20%

0.47UF

CERM-X5R-1

C2467

1

2

10%

201

X5R

6.3V

0.047UF

C2459

1

2

10%

201

X5R

6.3V

0.047UF

C2458

1

2

201

MF

1/20W

1%

240

R2470

2

1

201

240

1% 1/20W MF

R2460

2

1

201

CERM-X5R-1

0.47UF

4V

20%

C2457

1

2

10%

201

X5R

6.3V

0.047UF

C2449

1

2

10%

201

X5R

6.3V

0.047UF

C2448

1

2

201

0.47UF

CERM-X5R-1

4V

20%

C2447

1

2

201

MF

1/20W

1%

240

R2450

2

1

201

240

1% 1/20W MF

R2440

2

1

10V

X5R-CERM

2.2UF

402

20%

C2440

1

2

X5R-CERM

2.2UF

20% 10V

402

C2400

1

2

X5R-CERM

2.2UF

402

10V

20%

C2441

1

2

X5R-CERM

2.2UF

402

10V

20%

C2401

1

2

X5R-CERM

20% 10V

402

2.2UF

C2450

1

2

402

10V

20%

2.2UF

X5R-CERM

C2410

1

2

2.2UF

20% 10V

402

X5R-CERM

C2451

1

2

20% 10V

402

2.2UF

X5R-CERM

C2411

1

2

20% 10V

402

2.2UF

X5R-CERM

C2460

1

2

20% 10V

402

2.2UF

X5R-CERM

C2461

1

2

402

10V

20%

2.2UF

X5R-CERM

C2420

1

2

20% 10V

402

2.2UF

X5R-CERM

C2421

1

2

20% 10V

402

X5R-CERM

2.2UF

C2470

1

2

20% 10V

402

2.2UF

X5R-CERM

C2471

1

2

402

10V

20%

2.2UF

X5R-CERM

C2430

1

2

20% 10V

402

2.2UF

X5R-CERM

C2431

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2443

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2444

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2403

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2404

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2445

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2453

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2405

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2413

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2454

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2414

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2455

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2463

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2415

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2423

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2464

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2465

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2424

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2425

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2473

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2433

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2474

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2434

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2475

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2435

1

2

OMIT_TABLE

FBGA

DDR3-1333

U2400

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

FBGA

DDR3-1333

U2410

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2420

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

DDR3-1333

FBGA

U2430

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

DDR3 SDRAM Bank A (2 OF 2)

MEM_A_A<10>

MEM_A_A<14>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<5>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<15>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<15>

MEM_A_DQ<61>

MEM_A_DQS_N<7>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<7>

MEM_A_DQ<60>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_A<2>

MEM_A_DQ<43>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_DQS_N<5>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<14>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<6>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<13>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<53>

MEM_A_DQS_N<6>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<6>

MEM_A_DQ<52>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_A<2>

MEM_A_CLK_N<1>

MEM_A_DQS_N<4>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_ODT<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1> MEM_A_RAS_L MEM_A_CAS_L

MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<45>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<5>

MEM_A_DQ<44>

MEM_A_DQ<47>

MEM_A_DQ<42>

MEM_A_DQ<40>

MEM_A_A<2>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<12>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<4>

MEM_A_DQ<36>

MEM_A_DQ<39>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_A<2>

MEM_A_WE_L

MEM_A_A<0>

MEM_A_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<11>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<25>

MEM_A_DQS_N<3>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<3>

MEM_A_DQ<30>

MEM_A_DQ<26>

MEM_A_DQ<29>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<31>

MEM_A_DQ<24>

MEM_A_A<2>MEM_A_A<2>

MEM_A_A<6>

MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18> MEM_A_DQS_P<2>

MEM_A_CS_L<1> MEM_A_CKE<1>

MEM_A_DQS_N<2>

MEM_A_DQ<23>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<4> MEM_A_A<3>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<7> MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_WE_L

MEM_A_ZQ<10>

MEM_A_RAS_L

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<10>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<13>

PP1V35_S3_MEM

MEM_A_CS_L<1>

MEM_A_CLK_N<1>

MEM_A_A<15>

MEM_A_DQS_N<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1> MEM_A_RAS_L

MEM_A_ZQ<9>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_DQS_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<1>

MEM_A_DQ<11>

MEM_A_DQ<8>

MEM_A_DQ<12>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<9>

MEM_A_A<2>

PP1V35_S3_MEM

MEM_A_A<15>

MEM_A_A<13>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<8>

MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_DQ<1>

MEM_A_CKE<1>

MEM_A_DQS_P<0>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<0>

MEM_A_DQ<6>

MEM_A_A<2>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<41>

MEM_A_A<4>

MEM_A_A<1>

MEM_A_A<8> MEM_A_A<7>

MEM_A_DQ<46>

MEM_A_BA<0>

MEM_A_WE_L

MEM_A_ZQ<13>

PP1V35_S3_MEM

<SCH_NUM>

24 OF 118

24 OF 81

7

23 24

27 77

7

23 24 27 77

22 23 24 70 74 77

7

23 24

27 77

22 23 24 70 74 77

7

24 27

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7

24 27

77

7

23

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7

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7

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23 24

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21 23 24 25 26

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7

23 24

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7

23 24

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23 24

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7

23 24

27 77

7

23 24 27

77

22 23 24 70 74 77

23 24 25 26 46 69 77

7

23 24 27 77

7

23

24 27 77

7

23

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7

23 24 27 77

7

23 24

27 77

7

23 24

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7

23

24 27 77

7

23 24 27 77

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23 77

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7

24 27

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7

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23 77

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23 77

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7

23 77

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23 77

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7

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7

23

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23 24

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7 23 77

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23 24

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23 24

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22 23 24 70 74 77

23 24 25 26 46 69 77

7

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21 23 24

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23

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23 24 27 77

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23 24 27 77

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23

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23 24 27 77

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23 24 27 77

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23 24 27 77

22 23 24 70 74 77

7 24 27 77

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23 24

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23 24

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23 24

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22 23 24 70 74 77

23 24 25 26 46 69 77

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23 24 27

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22 23 24 70 74 77

23 24 25 26 46 69 77

7

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23 24 25 26 46 69 77

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23

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22 23 24 70 74 77 22 23 24 70 74 77

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23 24 25 26 46 69 77

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7

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7

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23 24 27 77

7

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23 24 27 77

7

23 24

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23 24

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23 24

27 77

7

23 24

27 77 7

23 24

27 77

7

23 24

27 77

7

23 24 27

77

7

23 24 27 77

7

23

24 27

77

7

23 24 27 77

7

23 24 27 77

7

23 24

27 77

7

23 24

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7

23

24 27 77

7

23 24 27 77

7

23

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7

23 24 27 77

23 24 25 26 46 69 77

7

23 24

27 77

7

23 24

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22 23 24 70 74 77

7 24 27

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7

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7

24 27

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23 24

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23 24

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7

23 24

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7

23 24

27 77 7

23 24

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7

23 24

27 77

7

23 24

27 77

7

23 24

27 77

7

23 24

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7

23 24

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7 23 77

7

23 24

27 77

22 23 24 70 74 77 22 23 24 70 74 77

7

23 24 27 77

7

23 24

27 77

7

23 24 27 77

23 24 25 26 46 69 77

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

NC NC

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

OMIT_TABLE

DDR3-1333

FBGA

U2550

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2560

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2570

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

201

MF

1/20W

1%

240

R2500

2

1

201

240

1% 1/20W MF

R2510

2

1

201

MF

1/20W

240

1%

R2520

2

1

201

MF

240

1% 1/20W

R2530

2

1

201

CERM-X5R-1

20%

4V

0.47UF

C2507

1

2

10%

201

X5R

6.3V

0.047UF

C2509

1

2

10%

201

X5R

6.3V

0.047UF

C2508

1

2

10%

201

X5R

6.3V

0.047UF

C2519

1

2

10%

201

X5R

6.3V

0.047UF

C2518

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2517

1

2

10%

201

X5R

6.3V

0.047UF

C2529

1

2

10%

201

X5R

6.3V

0.047UF

C2528

1

2

201

0.47UF

20%

4V

CERM-X5R-1

C2527

1

2

10%

201

X5R

6.3V

0.047UF

C2539

1

2

10%

201

X5R

6.3V

0.047UF

C2538

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2537

1

2

10%

201

X5R

6.3V

0.047UF

C2579

1

2

10%

201

X5R

6.3V

0.047UF

C2578

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2577

1

2

10%

201

X5R

6.3V

0.047UF

C2569

1

2

10%

201

X5R

6.3V

0.047UF

C2568

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2567

1

2

10%

201

X5R

6.3V

0.047UF

C2559

1

2

10%

201

X5R

6.3V

0.047UF

C2558

1

2

201

240

1% 1/20W MF

R2570

2

1

201

MF

240

1/20W

1%

R2560

2

1

201

CERM-X5R-1

20%

4V

0.47UF

C2557

1

2

10%

201

X5R

6.3V

0.047UF

C2549

1

2

10%

201

X5R

6.3V

0.047UF

C2548

1

2

201

CERM-X5R-1

0.47UF

4V

20%

C2547

1

2

201

240

1% 1/20W MF

R2550

2

1

201

MF

1/20W

1%

240

R2540

2

1

X5R-CERM

2.2UF

402

10V

20%

C2540

1

2

2.2UF

X5R-CERM

20% 10V

402

C2500

1

2

X5R-CERM

2.2UF

402

10V

20%

C2541

1

2

20% 10V

402

2.2UF

X5R-CERM

C2550

1

2

X5R-CERM

2.2UF

402

10V

20%

C2501

1

2

402

10V

20%

2.2UF

X5R-CERM

C2510

1

2

20% 10V

402

2.2UF

X5R-CERM

C2551

1

2

20% 10V

402

2.2UF

X5R-CERM

C2511

1

2

20% 10V

402

2.2UF

X5R-CERM

C2560

1

2

20% 10V

402

2.2UF

X5R-CERM

C2561

1

2

402

10V

20%

2.2UF

X5R-CERM

C2520

1

2

20% 10V

402

2.2UF

X5R-CERM

C2521

1

2

20% 10V

402

2.2UF

X5R-CERM

C2570

1

2

20% 10V

402

X5R-CERM

2.2UF

C2571

1

2

402

20%

X5R-CERM

10V

2.2UF

C2530

1

2

20% 10V

402

2.2UF

X5R-CERM

C2531

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2543

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2544

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2503

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2504

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2545

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2553

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2505

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2513

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2554

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2514

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2555

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2563

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2515

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2523

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2564

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2565

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2524

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2525

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2573

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2533

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2534

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2574

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2575

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2535

1

2

DDR3-1333

FBGA

OMIT_TABLE

U2500

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2510

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2520

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2530

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2540

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

DDR3 SDRAM Bank B (1 OF 2)

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_ZQ<6>

MEM_B_ZQ<2>

MEM_B_A<2>

MEM_B_A<6>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<7>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<62>

MEM_B_DQS_N<7>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<7>

MEM_B_DQ<63>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_A<2>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<54>

MEM_B_DQS_N<6>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<5>

MEM_B_DQ<32>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0> MEM_B_RAS_L

MEM_B_ZQ<5>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<46>

MEM_B_DQS_N<5>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_A<2>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<4>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<38>

MEM_B_DQS_N<4>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<4>

MEM_B_DQ<39>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_A<2>

MEM_B_WE_L MEM_B_WE_L

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_ODT<0>

MEM_B_WE_L

MEM_B_DQ<19>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<3>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<31>

MEM_B_DQS_N<3>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<3>

MEM_B_DQ<24>

MEM_B_DQ<28>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<27>

MEM_B_A<2>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_DQ<20>

MEM_B_DQ<17>

MEM_B_A<5>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<6>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<22>

MEM_B_DQS_N<2>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<2>

MEM_B_DQ<21>

MEM_B_DQ<23>

MEM_B_DQ<16>

MEM_B_DQ<18>

MEM_B_A<2>

MEM_B_DQ<11>

MEM_B_DQ<3>

MEM_B_A<12>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0> MEM_B_RAS_L

MEM_B_ZQ<1>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<15>

MEM_B_DQS_N<1>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<1>

MEM_B_DQ<8>

MEM_B_DQ<12>

MEM_B_DQ<10>

MEM_B_DQ<13>

MEM_B_DQ<9>

MEM_B_DQ<14>

MEM_B_A<2>

PP1V35_S3_MEM

MEM_B_DQ<2> MEM_B_DQ<4>

MEM_B_DQ<0>

MEM_B_CKE<0>

MEM_B_DQ<5>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<0>

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<7>

MEM_B_DQS_N<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<0>

MEM_B_DQ<1>

MEM_B_DQ<6>

MEM_B_A<2>

PP1V35_S3_MEM

<SCH_NUM>

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w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

Apple MacBook Pro A1398 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual