Apple MacBook Pro A1398 Schematics

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

SCHEM,MLB,J45

Schematic / PCB #’s

DVT 8/6/2013

ALIASES RESOLVED

1 OF 81

<PART_DESCRIPTION>

<SCH_NUM>

<ECO_DESCRIPTION>

1 OF 118

03/15/2013

SMC

50

CHANG_J45

41

03/15/2013

KEYBOARD/TRACKPAD (2 OF 2)

49

CHANG_J45

40

03/15/2013

KEYBOARD/TRACKPAD (1 OF 2)

48

CHANG_J45

39

10/31/2012

USB 3.0 CONNECTORS

46

J15_MLB

38

06/13/2013

Camera 2 of 2

40

CLEAN_MLB_KEPLER

37

06/13/2013

Camera 1 of 2

39

CLEAN_MLB_KEPLER

36

06/08/2013

SSD Connector

37

CLEAN_MLB_KEPLER

35

10/31/2012

X29C CONNECTOR

35

J15_MLB

34

11/16/2012

DDC Crossbar

34

J15_REFERENCE

33

12/18/2012

Thunderbolt Connector B

33

J15_REFERENCE

32

12/18/2012

Thunderbolt Connector A

32

J15_REFERENCE

31

01/14/2013

Thunderbolt Mobile Support

30

T29_RR

30

01/14/2013

Thunderbolt Host (2 of 2)

29

T29_RR

29

01/14/2013

Thunderbolt Host (1 of 2)

28

T29_RR

28

10/31/2012

DDR3 Termination

27

J15_MLB

27

10/31/2012

DDR3 SDRAM Bank B (2 OF 2)

26

J15_MLB

26

10/31/2012

DDR3 SDRAM Bank B (1 OF 2)

25

J15_MLB

25

10/31/2012

DDR3 SDRAM Bank A (2 OF 2)

24

J15_MLB

24

10/31/2012

DDR3 SDRAM Bank A (1 OF 2)

23

J15_MLB

23

10/31/2012

DDR3 VREF MARGINING

22

J15_MLB

22

12/18/2012

CPU Memory S3 Support

21

J15_REFERENCE

21

01/14/2013

Project Chipset Support

20

J15_REFERENCE

20

12/18/2012

Chipset Support

19

J15_REFERENCE

19

10/31/2012

CPU & PCH XDP

18

J15_MLB

18

12/18/2012

PCH DECOUPLING

17

J15_REFERENCE

17

12/18/2012

PCH Grounds

16

J15_REFERENCE

16

12/18/2012

PCH Power

15

J15_REFERENCE

15

12/18/2012

PCH GPIO/MISC/NCTF

14

J15_REFERENCE

14

12/18/2012

PCH PCI-E/USB

13

J15_REFERENCE

13

12/18/2012

PCH DMI/FDI/PM/GFX/PCI

12

J15_REFERENCE

12

12/18/2012

PCH RTC/HDA/JTAG/SATA/CLK

11

J15_REFERENCE

11

12/18/2012

CPU Decoupling

10

J15_REFERENCE

10

12/18/2012

CPU Ground

9

J15_REFERENCE

9

12/18/2012

CPU Power

8

J15_REFERENCE

8

12/18/2012

CPU DDR3 Interfaces

7

J15_REFERENCE

7

12/18/2012

CPU Clock/Misc/JTAG/CFG

6

J15_REFERENCE

6

12/18/2012

CPU DMI/PEG/FDI/RSVD

5

J15_REFERENCE

5

10/31/2012

PD Parts

4

J15_MLB

4

10/31/2012

BOM Configuration

3

J15_MLB

3

10/25/2012

BOM Configuration

2

J15_MLB

2

118

SIDLE_J45

12/10/2012

Project Specific Constraints

81

117

SIDLE_J45

12/10/2012

SMC Constraints

80

116

SIDLE_J45

12/10/2012

Camera Constraints

79

115

SIDLE_J45

12/10/2012

Thunderbolt Constraints

78

114

SIDLE_J45

12/10/2012

Memory Constraints

77

113

SIDLE_J45

12/10/2012

PCH Constraints 2

76

112

SIDLE_J45

12/10/2012

PCH Constraints 1

75

111

SIDLE_J45

12/10/2012

CPU Constraints

74

110

SIDLE_J45

12/10/2012

PCB Rule Definitions

73

105

J15_MLB

10/31/2012

NC & No Test

72

104

J15_MLB

10/31/2012

Functional Test Points

71

102

J15_MLB

10/31/2012

Signal Aliases

70

100

J15_MLB

10/31/2012

Power Aliases

69

95

J15_MLB

10/31/2012

RIO Connectors

68

83

J15_MLB

10/31/2012

eDP Display Connector

67

81

CHANG_J45

03/15/2013

Power Control 1/ENABLE

66

80

J15_MLB

10/31/2012

Power FETs

65

78

J15_MLB

10/31/2012

Misc Power Supplies

64

77

CLEAN_MLB_KEPLER

06/13/2013

LCD/KBD Backlight Driver

63

76

J15_MLB

10/31/2012

1V05V POWER SUPPLY

62

75

J15_MLB

10/31/2012

5V / 3.3V Power Supply

61

74

J15_MLB

10/31/2012

1.35V DDR3L SUPPLY

60

73

J15_MLB

10/31/2012

CPU VR12.5 VCC Power Stage

59

72

J15_MLB

10/31/2012

CPU VR12.5 VCC Regulator IC

58

71

J15_MLB

10/31/2012

PBus Supply & Battery Charger

57

70

J15_MLB

10/31/2012

DC-In & Battery Connectors

56

66

JOE_J45

07/30/2013

AUDIO: JACK TRANSLATORS

55

65

JOE_J45

07/30/2013

AUDIO: JACK

54

64

JOE_J45

07/30/2013

AUDIO: SPEAKER AMP

53

63

JOE_J45

07/30/2013

AUDIO:CODEC, DIGITAL

52

62

JOE_J45

07/30/2013

AUDIO:CODEC, ANALOG

51

61

J15_MLB

10/31/2012

SPI ROM / LPC+SPI Conn.

50

60

J15_MLB

10/31/2012

Fan Connectors

49

58

CHANG_J45

11/26/2012

Thermal Sensors

48

56

CHANG_J45

12/21/2012

Debug Sensors

47

55

CHANG_J45

03/15/2013

Load Side Voltage and Current Sensing

46

54

CHANG_J45

12/21/2012

High Side Voltage and Current Sensing

45

53

CHANG_J45

11/26/2012

SMBus Connections

44

52

CHANG_J45

03/15/2013

SMC Project Support

43

Date

Sync

(.csa)

Contents

Page

MASTER

Table of Contents

1

MASTER

1

051-0456

1 SCH

SCHEM,MLB,J45

CRITICAL

ABBREV=ABBREV

TITLE=MLB

LAST_MODIFIED=Tue Aug 6 17:09:28 2013

CRITICAL820-3662

1

PCBF,MLB,J45

PCB

51

CHANG_J45

11/12/2012

SMC Shared Support

42

(.csa)

Contents

Date

SyncPage

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

COMMON/DEVEL BOM

DRAM SPD Straps

J45 BOM Groups

BOM Variants

Module Parts

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:ELPIDA_1600

PCBA,MLB,BETTER,16G ELP,J45

639-4829

PCBA,MLB,BETTER,8G ELP,J45

639-4828

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:ELPIDA_1600_S

PCBA,MLB,BETTER,8G MIC,J45

639-4834

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:MICRON_1600_S

PCBA,MLB,BETTER,16G MIC,J45

639-4835

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:MICRON_1600

PCBA,MLB,BEST,8G MIC,J45

639-4852

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:MICRON_1600_S

639-4853

PCBA,MLB,BEST,16G MIC,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:MICRON_1600

337S4599

CRW,SR18J,,PRQ,C0,2.0,47W,4+3E,6M,BGA

CPU_CRW:BETTER

1

U0500

CRITICAL CRITICAL

CPU_CRW:BEST

U0500

1

CRW,SR18H,PRQ,C0,2.3,47W,4+3E,6M,BGA

337S4600

U2800

CRITICAL

1

338S1247

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

PCBA,MLB,CTO,16G MIC,J45

639-4871

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:MICRON_1600

PCBA,MLB,CTO,16G ELP,J45

639-4865

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:ELPIDA_1600

639-4841

PCBA,MLB,BEST,16G HYN,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:HYNIX_1600

PCBA,MLB,BEST,8G HYN,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:HYNIX_1600_S

639-4840

PCBA,MLB,BEST,8G ELP,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:ELPIDA_1600_S

639-4846

PCBA,MLB,BEST,16G ELP,J45

639-4847

BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:ELPIDA_1600

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

333S0660

MICRON_1600

32

IC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA

CRITICAL

ELPIDA_1600

32

333S0703

IC,SDRAM,4GBIT,DDR3L-1600,F DIE,RS,78P

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

639-4822

PCBA,MLB,BETTER,8G HYN,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:HYNIX_1600_S

PCBA,MLB,CTO,8G HYN,J45

639-4858

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:HYNIX_1600_S

PCBA,MLB,CTO,8G ELP,J45

639-4864

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:ELPIDA_1600_S

PCBA,MLB,CTO,8G MIC,J45

639-4870

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:MICRON_1600_S

PCBA,MLB,CTO,16G HYN,J45

639-4859

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:HYNIX_1600

J45_COMMON2

EDP:YES,LPCPLUS_CONN:YES,LPCPLUS_R:YES,XDP,RIO_PWR:1V5,SPI:DUAL_IO,SSD_PWR_EN:GPIO,CAM_WAKE:NO

639-4823

PCBA,MLB,BETTER,16G HYN,J45

BASE_BOM,DEVEL_BOM,CPU_CRW:BETTER,RAM:HYNIX_1600

985-0045

DEV BOM,MLB,J45

J45_DEVEL:ENG

685-0067

COMMON PARTS,MLB,J45

J45_COMMON

XDP_CONN,XDP_PCH

XDP_DEBUG

CRITICAL

U3900

1

IC,BCM15700A2,S2 PCIE CMRA,8X8,208FCBGA

338S1186

32

HYNIX_1600

CRITICAL

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

333S0667

IC,SDRAM,4GBIT,DDR3L-1600,HUMA,78P FBGA

1

CRITICAL

IC,SDRAM,4GBIT,DDR3L-1600,GEMMA,96B FBGA

U4000

333S0700

CRITICAL

U1100

1

337S4542

IC,QEWV,LPT-M,HM87,C2,SR199,PRQ,FCBGA

337S4624

CPU_CRW:CTO

CRITICAL

1

U0500

CRW,SR1BS,PRQ,C0,2.6,47W,4+3E,6M,BGA

ELPIDA_1600_S

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

16

CRITICAL333S0703

IC,SDRAM,4GBIT,DDR3L-1600,F DIE,RS,78P

333S0624

SAMSUNG_1600

32

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

CRITICAL

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670

RAM:ELPIDA_1600

ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

J45 MLB BASE BOM

BASE_BOM

CRITICAL

1

BASE685-0067

1

DEVEL_BOM

CRITICAL

DEVEL

J45 MLB DEVEL BOM

985-0045

ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAM:ELPIDA_1600_S

RAM:HYNIX_1600

HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

SAMSUNG_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM:SAMSUNG_1600_S

SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

RAM:SAMSUNG_1600

RAM:MICRON_1600

MICRON_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

MICRON_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAM:MICRON_1600_S

HYNIX_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM:HYNIX_1600_S

SAMSUNG_1600_S

16

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

CRITICAL333S0624

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

IC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA

MICRON_1600_S

CRITICAL

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

16

333S0660

333S0667

16

HYNIX_1600_S

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

CRITICAL

IC,SDRAM,4GBIT,DDR3L-1600,HUMA,78P FBGA

J45_COMMON

ALTERNATE,COMMON,J45_COMMON1,J45_COMMON2,J45_PROGPARTS

J45_DEVEL:FSB

ALTERNATE,XDP_DEBUG,BKLT:PROD,SENSOR_NONPROD:N,SENSOR_NONPROD_R

J45_DEVEL:ENG

ALTERNATE,XDP_DEBUG,S0PGOOD_ISL,DDRVREF_DAC,SENSOR_NONPROD:Y,SENSOR_NONPROD_R,BKLT:ENG,DBGLED,CAM_XTAL:YES

J45_PROGPARTS

SMC_PROG:EVT,BOOTROM_PROG:DVT,TBTROM:PROG,TPAD_PSOC:PROG

J45_PVB

BKLT:PROD,SENSOR_NONPROD:N

J45_COMMON1

CPUMEM:S0,TBTHV:P15V,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,CPUPEG:X16,S2_PWR:S0

BOM Configuration

SYNC_MASTER=J15_MLB

SYNC_DATE=10/25/2012

<SCH_NUM>

2 OF 118

2 OF 81

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Programmables - All builds

EFI ROM

Bar Code Labels / EEEE #’s

SMC

Alternate Parts

CRITICAL

U6100

1

335S0812

BOOTROM_BLANK:NUMONYX

IC,SPI SRL 50MHZ,FLASH,64MBIT,SOIC8

335S0807

1

U6100

CRITICAL

BOOTROM_BLANK:MACRONIX

IC,SPI SRL 50MHZ FLASH,64MBIT,8SOP,FUSE=1

341S3811

1

U6100

CRITICAL

BOOTROM_PROG:PROTO2

IC,EFI ROM(V00xx)PROTO 2,J45

371S0558

DDS alt to STALL

371S0713

Cyntec alt to Vishay

ALL

152S1645152S0461

376S1080

Diodes alt to On Semi

ALL

376S0820

Panasonic alt to TDK

ALL

155S0583155S0667

ALL

Rohm alt to Vishay

138S0732 138S0715

ALL

128S0264

Kemet alt to Sanyo

128S0364

ALL

333S0704 333S0700

ELPIDA to HYNIX U4000

ALL

311S0649 311S0541

ON alt to Toshiba (U2030, U7001)

127S0164

ALL

127S0162

Rohm alt to Vishay

138S0843 138S0674

Samsung alt to Murata

ALL

138S0811138S0846

Samsung alt to Murata

ALL

138S0803 138S0639

ALL

Samsung alt to Murata

138S0681 138S0638

ALL

Taiyo Yuden alt to Samsung

ALL

Kemet alt to Sanyo

128S0371 128S0376

333S0703333S0629

ALL

Elpida F die alt

376S1128376S1089

NXP alt to Diodes

ALL

376S1129 376S0855

ALL

NXP alt to Diodes

376S1032

ALL

Toshiba alt to Diodes

376S0855

107S0232

Cyntec alt to TFT

107S0241

ALL

197S0478 197S0479

NDK Alt to Epson

ALL

376S0604

Diodes alt to Fairchild

ALL

376S1053

NEC alt to Sanyo

ALL

128S0329128S0311 138S0706

ALL

138S0739

Samsung alt to Murata

197S0481

ALL

197S0480

Epson Alt to NDK

CRITICAL

MBP BARCODE LABEL

1

825-7845

LABEL

U5000

SMC_PROG:EVT

1

CRITICAL

IC,SMC-B1,EXT,V2.12A54,EVT,J45

341S3902

U5000

SMC_PROG:PVT

CRITICAL

1

341S3741

IC,SMC-A3,SCPL,EXT,VXXXX,PVT,J15

1

U6100

CRITICAL

BOOTROM_PROG:PRE-PROTO1

IC,EFI ROM(V0035)PRE-PROTO 1,J45

341S3780

BOOTROM_PROG:PROTO0

1

CRITICAL

U6100

341S3763

IC,EFI ROM(VXXXX)PROTO 0,J45

BOOTROM_PROG:EVT

341S3890

1

CRITICAL

U6100

IC,EFI ROM(V0100)PROTO3-J45 &EVT-J45

U6100

CRITICAL

1

341S3929

IC,EFI ROM(Vxxxx)DVT-J45 BOOTROM_PROG:DVT

U6100

IC,EFI ROM(V0041)PROTO 1,J45

341S3793

1

CRITICAL

BOOTROM_PROG:PROTO1

338S1214

1

SMC_PROG:BASE

IC,SMC-B1,40MHZ/50DMIPS,SCPL FW,157BGA

U5000

CRITICAL

TPAD_PSOC:PROG

341S3856

U4801

CRITICAL

1

IC,TRKPD/KYBD,PSOC(V225)

337S4587

TPAD_PSOC:BLANK

1

CRITICAL

U4801

IC,TP PSOC, QFN,BLANK

U2890

CRITICAL

1

TBTROM:PROG

341S3919

IC,EPROM,Falcon RIDGE(V13.9)J44/45

U2890

CRITICAL

1

TBTROM:BLANK

IC,SERIAL SPI FLASH ROM,4MBIT,50MHZ,USON

335S0915

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

BOM Configuration

<SCH_NUM>

3 OF 118

3 OF 81

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

-----------------------

817-0688

860-1687

806-6194806-6192806-6170

817-0741

-----------------------

SMT GND TEST PONTS

|

-----------------------

|

J45 POGO PINS

APN 806-2247

||

|

J45 THERMAL MODULE STANDOFF

|

-----------------------

|

| |

|

| |

|

Frame Holes

| | |

| |

|

| |

860-1328

|

860-1327

|

| |

| | |

|

| |

| | |

| |

|

860-1448

J45 StAND OFF

STDOFF-4.5OD1.8H-SM

SH0425

1

STDOFF-4.5OD1.9H-SM

SH0424

1

2.8R2.3

ZT0415

1

STDOFF-4.5OD1.8H-SM

SH0423

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0431

1

TH-NSP

SL-1.1X0.45-1.4x0.75

ZT0470

1

SHLD-J44-MLB

SM

OMIT_TABLE

SH0450

1

SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0432

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0433

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0435

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0436

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0434

1

TH-NSP

SL-1.1X0.45-1.4x0.75

ZT0471

1

TH-NSP

SL-1.1X0.45-1.4x0.75

ZT0472

1

SL-1.1X0.45-1.4x0.75

TH-NSP

ZT0474

1

TH-NSP

SL-1.1X0.45-1.4x0.75

ZT0475

1

TH-NSP

SL-1.1X0.45-1.4x0.75

ZT0473

1

SL-2.3X3.9-2.9X4.5

TH-NSP

ZT0450

1

2.9OD1.2ID-1.35H-SM

SH0440

1

2

2.9OD1.2ID-1.35H-SM

SH0442

1

2

2.9OD1.2ID-1.35H-SM

SH0441

1

2

2.9OD1.2ID-1.35H-SM

SH0443

1

2

2.9OD1.2ID-1.35H-SM

SH0444

1

2

SMT-PAD-NSP

2.1SM2.0MM-CIR

ZT0490

1

SMT-PAD-NSP

2.1SM2.0MM-CIR

ZT0491

1

2.1SM2.0MM-CIR

SMT-PAD-NSP

ZT0492

1

TH

MLB-MTG-BRKT-J5

BR0401

1

SM

SHLD-J45-CAN-FENCE2-MDP

SH0451

1

SM

SHLD-J45-CAN-FENCE1-MDP

SH0452

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0437

1

STDOFF-4.9OD2.38H-SM-2

SH0446

1

STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2

SH0445

1

2.9OD1.2ID-1.35H-SM

SH0460

1

2

2.9OD1.2ID-1.35H-SM

SH0461

1

2

5.0OD1.85ID-2.9H

SH0427

1

2.9OD1.2ID-1.35H-SM

SH0462

1

2

2.9OD1.2ID-1.35H-SM

SH0463

1

2

2.9OD1.2ID-1.35H-SM

SH0464

1

2

2.9OD1.2ID-1.35H-SM

SH0467

1

2

2.9OD1.2ID-1.35H-SM

SH0466

1

2

2.9OD1.2ID-1.35H-SM

SH0465

1

2

5.0OD1.85ID-2.9H

SH0426

1

5.0OD1.85ID-2.9H

SH0429

1

5.0OD1.85ID-2.9H

SH0428

1

946-3819

EDGE_BOND

1

CRITICAL

D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC

CAN_COVER1, CAN_COVER2

2

806-6193 CRITICAL

CAN COVER,mDP

CRITICAL806-9391

1

SHIELD CAN, USB,J45

SH0450

825-7841

CONFIG_LABEL

CRITICAL

1

LBL,PART CONFIG,BOARDS,D2

CRITICAL

1

725-1787

PCH_INSULATOR

INSULATOR,PCH,J15

CPU_INSULATOR

CRITICAL

1

725-1877

INSULATOR,CPU,J45

CRITICAL

REAR_INSULATOR

1

725-1807

INSULATOR,REAR,MLB,J45

PD Parts

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

GND

<SCH_NUM>

4 OF 118

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IN IN IN

IN

IN IN IN IN IN

OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

SYM 10 OF 12

EDP

DIGITAL DISPLAY INTERFACES

FDI

EDP_TXN0

DDIC_TXP2

FDI_TXP1

FDI_TXN1

FDI_TXP0

FDI_TXN0

EDP_DISP_UTIL

EDP_RCOMP

DDIB_TXN0

DDIC_TXN1

DDIC_TXP0

DDIC_TXN0

DDIB_TXN3

DDIB_TXP2

EDP_TXP1

EDP_TXP0

EDP_TXN1

EDP_AUXP

EDP_HPD

EDP_AUXN

DDID_TXP1

DDID_TXN1

DDID_TXP0

DDID_TXN0

DDID_TXP3

DDID_TXN3

DDID_TXP2

DDID_TXN2

DDIC_TXP1 DDIC_TXN2

DDIC_TXN3 DDIC_TXP3

DDIB_TXP0 DDIB_TXN1 DDIB_TXP1 DDIB_TXN2

DDIB_TXP3

RESERVED

SYM 12 OF 12

DAISY_CHAIN_NCTF

RSVD132 RSVD133 RSVD134 RSVD135 RSVD136 RSVD137 RSVD138 RSVD139

DAISY_CHAIN_NCTF

TP

NC NC NC NC NC NC NC NC

IN IN IN IN

IN

OUT

IN

SYM 1 OF 12

FDI

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_RCOMP

DISP_INT

FDI_CSYNC

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

DMI_RX0* DMI_RX1* DMI_RX2* DMI_RX3*

DMI_RX0

DMI_RX2 DMI_RX3

DMI_TX0* DMI_TX1* DMI_TX2* DMI_TX3*

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

DMI_RX1

IN IN IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU Daisy-Chain Strategy:

NO_TESTNO_TEST

Port D pins out of order to match Intel symbol.

Other corner test signals connected in

Each corner of CPU has two testpoints.

daisy-chain fashion. Continuity should exist between both TP’s on each corner.

28 70 74

70

28 70 74

70

28 70 74

70

BGA

OMIT_TABLE

HASWELL

U0500

C25

A25

C24

A24

D25

B25

D24

B24

C21

A21

C20

A20

D21

B21

D20

B20

C17

A17

C16

A16

D17

B17

D16

B16

F15 F14

E12

E14

AG6

C14 A12

D14 B12

C12

A14

D12

B14

24.9

402

MF-LF

1/16W

1%

R0530

1

2

402

MF-LF

1/16W

5%

10k

R0531

1

2

BGA

OMIT_TABLE

HASWELL

U0500

A3 A4

A51 A52 A53

B2 B3

B52 B53 B54

BC1

BC54

BD1

BD54

BE1 BE2

BE3 BE52 BE53 BE54

BF2

BF3

BF4

BF51 BF52 BF53

C1 C2 C3

C54 D1

D54

AD45

AE9

AF9

AG45

AN35 AN37

G14 G17

TP-P6

TP0500

1

TP-P6

TP0501

1

TP-P6

TP0511

1

TP-P6

TP0531

1

TP-P6

TP0510

1

TP-P6

TP0520

1

TP-P6

TP0530

1

TP-P6

TP0521

1

12 74

12 72 74

12 74

12 72 74

12 74

12 72 74

24.9

1% MF-LF

1/16W 402

R0510

1

2

12 74

BGA

HASWELL

OMIT_TABLE

U0500

F12

AB2 AB3 AC3 AC1

AB1 AB4 AC4 AC2

AF2 AF4 AG4 AG2

AF1 AF3 AG3 AG1

F11

AH6

E10 C10

M2 V5 V4 V1 Y3 Y2

B10 E9 D9 B9 L5 L2 M4 L4

F10 D10

M1 Y5 V3 V2 Y4 Y1

A10 F9 C9 A9 M5 L1 M3 L3

B6 C5

T6 R6 R2 R4 T4 T1

E6 D4 G4 E3 J5 G3 J3 J2

C6 B5

T5 R5 R1 R3 T3 T2

D6 E4 G5 E2 J6 G2 J4 J1

28 70 74

70

28 70 74

70

28 70 74

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

CPU DMI/PEG/FDI/RSVD

DMI_S2N_N<2>

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<3>

DP_INT_ML_C_P<2>

DP_INT_ML_C_N<2>

PCIE_TBT_D2R_N<2>

TRUE

CPU_DC_BE53_BF53

CPU_DC_A3_B3

TRUE

CPU_DC_A4

DP_TBTSNK0_ML_C_P<0>

PPVCOMP_S0_CPU

DP_INT_ML_C_P<1>

CPU_DC_BC54

TRUE

CPU_DC_A3_B3

CPU_DC_BF51

CPU_DC_B54_C54

TRUE

DMI_S2N_N<0>

TP_PEG_D2RN<13>

TP_PEG_D2RN<7>

CPU_EDP_RCOMP

HDMI_CLK_P

PPVCCIO_S0_CPU

DP_INT_AUXCH_C_N

PPVCOMP_S0_CPU

TP_PEG_D2RN<6>

TP_PEG_D2RN<5>

TP_PEG_R2D_CP<9>

CPU_PEG_RCOMP

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_N<0>

DMI_N2S_N<2>

DMI_N2S_P<1>

DMI_N2S_N<3>

DMI_N2S_N<0> DMI_N2S_N<1>

DMI_N2S_P<3>

DMI_S2N_P<2>

PCIE_TBT_D2R_N<0>

TP_PEG_D2RN<9>

FDI_INT

FDI_CSYNC

TP_PEG_R2D_CP<15>

TP_PEG_R2D_CP<14>

TP_PEG_R2D_CP<13>

TP_PEG_R2D_CP<12>

TP_PEG_R2D_CP<11>

TP_PEG_R2D_CP<10>

TP_PEG_R2D_CP<8>

TP_PEG_R2D_CP<7>

TP_PEG_R2D_CP<6>

TP_PEG_R2D_CP<4>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_P<1> PCIE_TBT_R2D_C_P<2>

TP_PEG_R2D_CN<15>

TP_PEG_R2D_CN<14>

TP_PEG_R2D_CN<13>

TP_PEG_R2D_CN<11>

TP_PEG_R2D_CN<10>

TP_PEG_R2D_CN<8> TP_PEG_R2D_CN<9>

TP_PEG_R2D_CN<7>

TP_PEG_R2D_CN<6>

TP_PEG_R2D_CN<5>

TP_PEG_R2D_CN<4>

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<1>

TP_PEG_D2RP<14> TP_PEG_D2RP<15>

TP_PEG_D2RP<12>

TP_PEG_D2RP<11>

TP_PEG_D2RP<9> TP_PEG_D2RP<10>

TP_PEG_D2RP<7>

TP_PEG_D2RP<6>

TP_PEG_D2RP<4>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_P<0>

TP_PEG_D2RN<15>

TP_PEG_D2RN<14>

TP_PEG_D2RN<12>

TP_PEG_D2RN<10> TP_PEG_D2RN<11>

TP_PEG_D2RN<8>

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_N<1>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_P<3>

TP_PEG_R2D_CP<5>

PCIE_TBT_D2R_P<1>

DMI_N2S_P<0>

DMI_N2S_P<2>

TP_PEG_D2RN<4>

DP_INT_ML_C_N<0>

DP_TBTSNK1_ML_C_P<2>

TP_EDP_DISP_UTIL

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_P<2>

DP_INT_ML_C_P<0>

DP_INT_ML_C_N<1>

TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLP<0>

HDMI_CLK_N

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLN<2>

DP_TBTSNK1_ML_C_P<1> DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_N<3> DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK0_ML_C_N<1> DP_TBTSNK0_ML_C_P<1> DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DP_INT_AUXCH_C_P

PCIE_TBT_D2R_P<3>

TP_PEG_D2RP<5>

TP_PEG_D2RP<8>

TP_PEG_D2RP<13>

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<0>

TP_PEG_R2D_CN<12>

DP_IG_A_HPD_L

CPU_DC_A53_B53

TRUE

CPU_DC_A52_B52

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_A53_B53

TRUE

CPU_DC_A52_B52

TRUE

CPU_DC_BE3_BF3

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BE2_BF2

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_BD54_BE54

TRUE

CPU_DC_BD1_BE1

TRUE

CPU_DC_B54_C54

CPU_DC_BE52_BF52

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_C1_C2

TRUE

CPU_DC_B2_C3

TRUE

CPU_DC_BE52_BF52

TRUE

CPU_DC_BE3_BF3

CPU_DC_D1

CPU_DC_D54

CPU_DC_A51

CPU_DC_BF4

CPU_DC_BC1

TRUE

CPU_DC_BE53_BF53

5 OF 81

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<SCH_NUM>

67 70 74

5

28 70 74

5 8

67 70 74

5 5

74

68 70 71 74

6 8

10 18 58

67 70 74

5 8

74

67 70 74

28 70 74

67 70 74

70

68 70 71 74

70

28 70 74

67 70 74

70

20

5

w w w . c h i n a f i x . c o m

BI BI BI BI BI

IN

OUT

BI

NC

OUT

BI

SYM 2 OF 12

CLOCK

JTAG

PWR

DDR3

THERMAL

THERMTRIP*

PM_SYNC

PWRGOOD

SM_DRAMPWROK

PLTRSTIN*

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

SM_DRAMRST*

PRDY* PREQ*

TCK TMS

TRST*

TDI TDO

DBR*

BPM0* BPM1*

BPM3*

BPM2*

BPM4* BPM5* BPM6* BPM7*

PECI

PROC_DETECT*

PROCHOT*

CATERR*

DPLL_REF_CLKN DPLL_REF_CLKP

BCLKN BCLKP

SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP

OUT

IN IN

SYM 11 OF 12

RESERVED

RSVD_TP28

RSVD_TP27

RSVD_TP39

RSVD_TP38

RSVD11

RSVD_TP1 RSVD_TP2

RSVD51 RSVD52

RSVD50

RSVD16

RSVD42

RSVD41

RSVD10

RSVD9

RSVD95

RSVD94

RSVD93

RSVD92

CFG_RCOMP

CFG16

CFG19

CFG18 CFG17

VSS_H54

VSS_H52

VSS_H51

VSS_H53

VCC_F22

VSS_G19

VSS_F52

VSS_F51

TESTLO_F21

CFG0 CFG1

CFG6

CFG5

CFG2 CFG3 CFG4

TESTLO_F20

CFG11

CFG10

CFG9

CFG8

CFG7

CFG12

CFG14

CFG13

CFG15

RSVD_TP17 RSVD_TP18

RSVD_TP37

RSVD_TP36

RSVD_TP35

RSVD_TP23

RSVD_TP3 RSVD_TP4

RSVD47 RSVD48 RSVD49

RSVD_TP26

RSVD_TP25

RSVD_TP24

NC

IN

OUT

IN IN

IN

OUT

IN

OUT

BI BI BI

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

These can be placed close to

J1800 and only for debug access

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU) (IPU) (IPU)

(IPD)

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

18 74

PLACE_NEAR=U0500.F50:157mm

402

MF-LF

1/16W

5%

10K

R0611

1

2

12 21 74

14 18 74

14 42 74

PLACE_NEAR=U0500.BB52:12.7mm

100

1% 1/16W MF-LF 402

R0614

1

2

75

1% 1/16W MF-LF 402

PLACE_NEAR=U0500.BB53:12.7mm

R0613

1

2

100

1% 1/16W MF-LF 402

PLACE_NEAR=U0500.BB51:12.7mm

R0612

1

2

41 74

5% 1/16W MF-LF

402

62

R0601

1

2

402

MF-LF

5%

56

1/16W

R0603

12

41 42 58 74

BGA

HASWELL

OMIT_TABLE

U0500

AB6 AA6

R51 R50 P49 N50 R49 P53 U51 P51

G50

F53

AC6 AE6

G51

L54

D52

N53 N52

C51

E50

F50

AP48

BE51

BB51 BB53 BB52

V6 Y6

N54

N49 M49

D53

M51 M53

21

11 74

HASWELL

OMIT_TABLE

BGA

U0500

AG49 AD49

Y53 W53 U53 V54 R53 R52

Y52

Y51

V53

V52

AC49 AE49

Y50

AB49

V51 W51 Y49 Y54

R54

AH49

AL6

AM48

AU26

AU27

B50

BC4

BD4

E5

F16

F8

G53 H50

L49

L50 N51

A5 A6

BD3

BE4

E1

F1

F24 F25

F6

G10

G12

G21 G24

G6

L51

L52 L53

F20

F21

F22

F51 F52

G19

H51 H52

H53

H54

MF-LF 402

1/16W

1%

49.9

R0690

1

2

49.9

1% 1/16W MF-LF

402

R0680

1

2

49.9

1% 1/16W MF-LF

402

R0685

1

2

402

MF-LF

5%

1K

1/16W

NOSTUFF

R0649

1

2

MF-LF 402

1/16W

5%

NOSTUFF

1K

R0643

1

2

NOSTUFF

1K

5% 1/16W MF-LF

402

R0641

1

2

NOSTUFF

1K

5% 1/16W MF-LF 402

R0640

1

2

NOSTUFF

1K

5% 1/16W MF-LF

402

R0647

1

2

1K

5% 1/16W MF-LF

402

CPUCFG6_PD

R0646

1

2

1K

5% 1/16W MF-LF 402

CPUCFG5_PD

R0645

1

2

402

MF-LF

1/16W

5%

EDP:YES

1K

R0644

1

2

402

MF-LF

1/16W

5%

1K

NOSTUFF

R0642

1

2

3.32K

402

MF-LF

1/16W

1%

PLACE_NEAR=U0500.AP48:51.562mm

R0621

1

2

402

MF-LF

1/16W

5%

1K

NOSTUFF

R0648

1

2

18 71 74

1.82K

PLACE_NEAR=R0621.2:1mm

1% 1/16W MF-LF

402

R0620

1

2

12 74

14

18 19 74

18 74

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

CPU Clock/Misc/JTAG/CFG

CPUPEG:X16

CPUPEG:X8X8

CPUCFG5_PD

CPUPEG:X8X4X4

CPUCFG6_PD,CPUCFG5_PD

PP1V35_S3RS0_CPUDDR

PPVCCIO_S0_CPU

CPU_PROCHOT_L

CPU_CFG<9> CPU_CFG<3>

CPU_CFG<16>

CPU_CFG<1> CPU_CFG<0>

CPU_CFG<7> CPU_CFG<6>

CPU_RESET_L

CPU_PWRGD

CPU_CLK135M_DPLLREF_N

PM_THRMTRIP_L

TP_CPU_RSVD_TP17

CPU_CFG<18>

TP_CPU_RSVD_TP39

TP_CPU_RSVD_TP38

TP_CPU_RSVD_TP25 TP_CPU_RSVD_TP26

TP_CPU_RSVD_TP28

TP_CPU_RSVD_TP27

CPU_CFG<19>

CPU_TESTLO_F20

CPU_CFG<0>

TP_CPU_RSVD_TP18

CPU_TESTLO_F21

TP_CPU_RSVD_TP47

TP_CPU_RSVD_TP23

TP_CPU_RSVD_TP3

CPU_CFG_RCOMP

CPU_CFG<5> CPU_CFG<4>

CPU_CFG<9> CPU_CFG<10>

CPU_CFG<2>

CPU_CFG<16>

CPU_CFG<17>

CPU_CFG<3>

XDP_CPU_PRDY_L

XDP_CPU_TMS

XDP_DBRESET_L

XDP_BPM_L<0> XDP_BPM_L<1>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6>

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPUPCH_TRST_L

TP_CPU_RSVD_TP24

TP_CPU_RSVD_TP35

CPU_CFG<4>

CPU_CFG<1> CPU_CFG<2>

CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8>

CPU_CFG<11> CPU_CFG<12>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<15>

TP_CPU_RSVD_TP36

TP_CPU_RSVD_TP4

TP_CPU_RSVD_TP1

TP_CPU_RSVD_TP48 TP_CPU_RSVD_TP49

TP_CPU_RSVD_TP37

PPVCC_S0_CPU

CPU_SM_RCOMP<1>

CPU_SM_RCOMP<0>

PM_SYNC

CPU_CLK135M_DPLLREF_P

CPU_CLK135M_DPLLSS_N CPU_CLK135M_DPLLSS_P

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

CPU_PECI

TP_CPU_RSVD_TP2

CPU_CATERR_L

CPU_PROCHOT_R_L

XDP_CPU_TCK

XDP_CPU_PREQ_L

CPU_MEM_RESET_L

CPU_SM_RCOMP<2>

XDP_BPM_L<7>

PM_MEM_PWRGD

<SCH_NUM>

6 OF 118

6 OF 81

8

10 21 65 66 69 81

5 8

10 18 58

6

18 74

6

18 71 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 71 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

6

18 74

8

10 46 59 69 71

74

w w w . c h i n a f i x . c o m

OUT

NC

NC NC

NC

NC NC NC

NC

NCNC

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SYM 3 OF 12

MEMORY CHANNEL A

SA_DQ12

SA_DQ11

SA_DQ8

SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24

SA_CKP3

SA_CKN3

SA_CKP2

SA_CKP1

SA_CKN1

SA_CKP0

SA_CKN0

SA_CKE1

SA_CS1*

SA_DQ20

SM_VREF

SA_DQSN7

SA_DQSN6

SA_DQSN5

SA_DQSN4

SA_DQSN3

SA_DQSN2

SA_DQSN1

SA_DQSN0

SA_DQS7

SA_DQS6

SA_DQS4 SA_DQS5

SA_DQS3

SA_DQS2

SA_DQS1

SA_DQS0

SA_MA13

SA_MA12

SA_MA11

SA_MA9

SA_MA8

SA_MA7

SA_MA5 SA_MA6

SA_MA4

SA_MA2 SA_MA3

SA_MA0 SA_MA1

SA_CAS*

SA_WE*

VSS_BC21

SA_RAS*

SA_BS1 SA_BS2

SA_ODT3

SA_BS0

SA_ODT2

SA_ODT1

SA_ODT0

SA_CS3*

SA_CS2*

SA_CS0*

SA_CKE3

SA_CKE2

SA_CKE0

SA_DQ30

SA_DQ0 SA_DQ1 SA_DQ2

SA_DQ9

SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19

SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58

SA_DQ61 SA_DQ62 SA_DQ63

SA_DQ4

SA_DQ3

SA_DQ10

SA_DQ7

SA_DQ5 SA_DQ6

SA_DQ47

SA_DQ46

SA_DQ45

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

RSVD25

RSVD162

RSVD165

RSVD168

SA_CKN2

SA_MA10

SA_MA14 SA_MA15

RSVD170

RSVD169

RSVD167

RSVD166

RSVD164

RSVD163

SA_DQ59 SA_DQ60

RSVD161

RSVD160

SYM 4 OF 12

MEMORY CHANNEL B

SB_DQ29

SB_DQ28

RSVD171

SB_CKN0

SB_CKE0

RSVD181

RSVD180

RSVD179

RSVD178

RSVD177

RSVD176

RSVD175

RSVD174

RSVD173

RSVD172

SB_DQSN3

SB_DQSN6

SB_DQS0 SB_DQS1

SB_DQS5

SB_DQS3 SB_DQS4

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7

SB_CKE1 SB_DQ8 SB_DQ9 SB_DQ10

SB_CKE2 SB_DQ11

SB_DQ12 SB_DQ13 SB_DQ14 SB_CKE3 SB_DQ15 SB_DQ16 SB_CS0* SB_DQ17 SB_CS1* SB_DQ18 SB_CS2* SB_DQ19 SB_CS3* SB_DQ20

SB_ODT0 SB_DQ21

SB_ODT1 SB_DQ22

SB_ODT2 SB_DQ23

SB_ODT3 SB_DQ24

SB_DQ25

SB_BS0

SB_DQ26

SB_BS1

SB_DQ27

SB_DQ30

SB_RAS*

SB_WE*

SB_CAS*

SB_MA0 SB_MA1

SB_DQ36

SB_MA2

SB_DQ37

SB_MA3

SB_DQ38

SB_MA4

SB_DQ39

SB_MA5

SB_DQ40

SB_MA6

SB_DQ41

SB_MA7

SB_DQ42

SB_MA8

SB_DQ43

SB_MA9

SB_DQ44

SB_MA10 SB_DQ45

SB_MA11 SB_DQ46

SB_MA12 SB_DQ47

SB_MA13 SB_DQ48

SB_MA14 SB_DQ49

SB_MA15 SB_DQ50

SB_DQ51

SB_DQSN0

SB_DQ52

SB_DQSN1

SB_DQ53

SB_DQSN2

SB_DQ54 SB_DQ55

SB_DQSN4

SB_DQ56

SB_DQSN5

SB_DQ57 SB_DQ58

SB_DQSN7

SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_DQS2

SB_DQS6

SB_DQS7

SB_CKP0

SB_CKN1

SB_CKP1

SB_CKN2

SB_CKP2

SB_CKN3

SB_CKP3

SB_BS2

VSS_AU30

BI

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI

BI

BI BI

NC

NC NC

NC NC NC

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

22 74

22

23 24 77

25 26 77

23 27 77

24 27 77

23 24 27 77

BGA

HASWELL

OMIT_TABLE

U0500

AU39

AU40 AV39

AV40

AW39

AW40

AY39

AY40 BA39

BA40

BC53

BD31

BC20 BD21 BD32

BE21

BE34

BF34

BC34

BD34

BE25

BD25

BE23

BD23

BF25

BC25

BF23

BC23

BE16 BC17 BE17 BD16

AR6

AH54 AH52

AR51 AR53 AN53 AN51 AR52 AR54 AV52 AV53 AY52 AY51

AK51

AV51 AV54 AY54 AY53 AY47 AY49 BA47 BA45 AY45 AY43

AK54

BA49 BA43 BF14 BC14 BC11 BF11 BE14 BD14 BD11 BE11

AH53

BC9 BE9 BE6 BC6 BD9 BF9 BE5 BD6 BB4 BC2

AH51

AW3 AW2 BB3 BB2 AW4 AW1 AU3 AU1 AR1 AR4

AK52

AU2 AU4 AR2 AR3

AK53 AN54 AN52

AJ53 AP52 AW53 BA46 BE12 BD7 BA2 AT3

AJ52 AP53 AW52 AY46 BD12 BE7 BA3 AT2

BD28 BD27

BD20 BF31 BC31 BE20 BE32 BE31

BF28 BE28 BF32 BC27 BF27 BC28 BE27 BC32

BC16 BF16 BF17 BD17

BF20 BF21

AN6

AM6

BC21

BGA

HASWELL

OMIT_TABLE

U0500

AY36

BC37

BC39

BD37

BD38

BD39

BE37

BE38

BE39 BF37

BF39

AY23 BA23 BA36

AV20

AU36

AU35

AV35

AV36

AW27

AW26

BA26

BA27

AV27

AV26

AY26

AY27

BA20 AY19 AU19 AW20

AC54 AC52

AV43 AV45 AU43 AU45 AV47 AV49 BC49 BE49 BD47 BC47

AE51

BD49 BD50 BE47 BF47 BE44 BD44 BC42 BF42 BF44 BC44

AE54

BD42 BE42 BA16 AU16 BA15 AV15 AY16 AV16 AY15 AU15

AC53

AU12 AY12 BA10 AU10 AV12 BA12 AY10 AV10

AU8 BA8

AC51

AV6 BA6 AV8 AY8 AU6 AY6 AM2 AM3 AK1 AK4

AE52

AM1 AM4 AK2 AK3

AE53 AU47 AU49

AD53 AV46 BE48 BE43 AW15 AW12 AW6 AL3

AD52 AU46 BD48 BD43 AW16 AW10 AW8 AL2

BA30 AW30

AU23 AY35 AW35 AU20 AW36 BA35

AY30 AV30 AW32 AY32 AT30 AV32 BA32 AU32

AY20 BA19 AV19 AW19

AV23 AW23

AU30

23 24 77

24 27 77

23 27 77

24 27 77

23 27 77

23 24 27 77

25 27 77

26 27 77

25 27 77

25 26 27 77

26 27 77

25 27 77

26 27 77

25 26 27 77

25 26 77

CPU DDR3 Interfaces

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

MEM_A_DQ<2> MEM_A_DQ<3>

MEM_A_CS_L<1>

MEM_A_DQ<45>

MEM_A_DQ<54>

MEM_A_DQ<51>

MEM_A_DQ<53>

MEM_A_DQ<0> MEM_A_DQ<1>

MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13>

MEM_A_DQ<15> MEM_A_DQ<16>

MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44>

MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50>

MEM_A_DQ<52>

MEM_A_DQ<55> MEM_A_DQ<56>

MEM_A_DQ<61>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<19>

MEM_B_DQ<17>

MEM_B_DQ<15>

MEM_B_DQ<20>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<25>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<51>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<61>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_A_DQ<60>

MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CKE<0>

MEM_B_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CKE<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_RAS_L MEM_B_WE_L MEM_B_CAS_L

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>

MEM_A_CLK_N<0> MEM_A_CLK_P<0> MEM_A_CKE<0>

MEM_A_CLK_N<1> MEM_A_CLK_P<1> MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_ODT<0> MEM_A_ODT<1>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_WE_L MEM_A_CAS_L

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<5> MEM_A_DQS_N<6>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQ<17>

MEM_A_DQ<14>

CPU_DIMMB_VREFDQ

CPU_DIMMA_VREFDQ

MEM_B_DQ<52>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

CPU_DIMM_VREFCA

MEM_B_DQ<16>

MEM_B_DQ<18>

<SCH_NUM>

7 OF 118

7 OF 817 OF 81

7 OF 118

<SCH_NUM>

w w w . c h i n a f i x . c o m

BI

OUT

IN

SYM 5 OF 12

RSVD68

VIDSOUT

VIDSCLK

VIDALERT*

RSVD79(VSS)

RSVD78 VSS_V50(RSVD)

VSS_AP50(RSVD)

VSS_AP49(RSVD)

VSS_AN49(RSVD)

VSS_AM50(RSVD)

IVR_ERROR

VSS_AK49(RSVD)

VSS_AJ49(RSVD)

VSS_AJ50(RSVD)

VSS_AG50(RSVD)

VSS_AD50(RSVD)

VSS_AB50(RSVD)

FC_F17

RSVD65

RSVD69

RSVD67

RSVD66

RSVD74

RSVD73

RSVD72

RSVD71

RSVD70

VCC_L6 VCC_M6

VCOMP_OUT

VCC_SENSE

VSS_B51

FC_D5 FC_D3

VDDQ

VCC

VCCIO_OUT

RSVD76

RSVD75

VSS_E52

PWR_DEBUG

RSVD64

SYM 6 OF 12

POWER

VCC VCC

IN

OUT

NC NC NC NC

NC NC

NC NC NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Max load: 300mA

Connections would be required for 2014 CPU support.

R0802.2:

R0800.2:

R0810.2:

Max load: 300mA

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

0

5% 1/16W MF-LF

402

R0812

1 2

58 74

110

PLACE_NEAR=U0500.J50:2.54mm

402

1/16W

1% MF-LF

R0802

1

2

0

402

5%

MF-LF

1/16W

R0811

1 2

58 74

PLACE_NEAR=U0500.J53:38mm

5%

402

MF-LF

1/16W

43

R0810

1 2

58 74

PLACE_NEAR=R0810.1:2.54mm

75

1% 1/16W MF-LF

402

R0800

1

2

OMIT_TABLE

HASWELL

BGA

U0500

D3

D5

F17

AM49

F19

AH9

AN18

AN22

AN31

AN33

AR49

J12

J17 J21 J26 J31

U49

V49

W49

W9

A36 A38 A39 A42 A43 A45 A46

A48 AA46 AA47

AA8

AA9

B43 B45 B46 B48 C27 C28 C31 C32 C34 C36 C38 C39 C42 C43 C45 C46 C48 D27 D28 D31 D32 D34 D36 D38 D39 D42 D43 D45 D46 D48 E27 E28 E31 E32 E34 E36 E38 E39 E42 E43 E45 E46 E48 F27 F28 F31 F32 F34 F36 F38 F39 F42 F43 F45 F46 F48 G27 G29 G31 G32 G34 G36 G38 G39 G42 G43 G45 G46 G48 H11 H12 H13 H14 H16 H17 H18 H19 H20 H21 H23 H24 H25 H26 H27 H29

L6 M6

C50

D51

AK6

AR29 AR31 AR33 AT13 AT19 AT23 AT27 AT32 AT36 AV37 AW22 AW25 AW29 AW33 AY18 BB21 BB22 BB26 BB27 BB30 BB31 BB34 BB36 BD22 BD26 BD30 BD33 BE18 BE22 BE26 BE30 BE33

J53

J52

J50

AB50

AD50

AG50

AJ49

AJ50

AK49

AM50

AN49

AP49

AP50

B51

E52

V50

OMIT_TABLE

HASWELL

BGA

U0500

A27

A28

A31

A32

A34

AB45

AB46

AB8

AC46

AC47

AC8

AC9

AD46

AD8

AE46

AE47

AE8

AF8

AG46

AG8

AH46

AH47

AH8

AJ45

AJ46

AK46

AK47

AK8

AL45

AL46

AL8

AL9

AM46

AM47

AM8

AM9

AN10

AN12

AN13

AN14

AN15

AN16

AN17

AN19

AN20

AN21

AN23

AN24

AN25

AN26

AN27

AN29

AN30

AN32

AN34

AN36

AN38

AN39

AN40

AN41

AN42

AN43

AN44

AN45

AN46

AN8

AN9

AP10

AP12

AP13

AP14

AP15

AP16

AP17

AP18

AP19

AP20

AP21

AP22

AP23

AP24

AP25

AP26

AP27

AP29

AP30

AP31

AP32

AP33

AP34

AP35

AP36

AP37

AP38

AP39

AP40

AP41

AP42

AP43

AP44

AP46

AP47

AP8

AP9

AR35

AR37

AR39

AR41

AR43

AR45

AR46

B27

B28

B31

B32

B34

B36

B38

B39

B42

H30

H31

H32

H33

H34

H36

H37

H38

H39

H40

H42

H43

H45

H46

H48H8H9

J10

J14

J19

J24

J29

J33

J36

J37

J38

J39

J40

J42

J43

J45

J46

J48J8J9

K38

K40

K43

K44

K45

K46

K48K8K9

L37

L38

L39

L40

L42

L43

L44

L46

L47L8M37

M38

M39

M40

M42

M43

M44

M45

M46M8M9

N37

N38

N39

N40

N42

N43

N44

N46

N47N8N9

P45

P46P8R46

R47R8R9

T45

T46

U46

U47U8U9

V45

V46V8W46

W47W8Y45

Y46

Y8

18

PLACE_NEAR=U0500.C50:50.8mm

PLACE_SIDE=BOTTOM

100

1/16W MF-LF

402

5%

R0860

1

2

58 74

CPU Power

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

CPU_VIDSCLK

CPU_VIDSCLK_R

PPVCC_S0_CPU

CPU_VCCSENSE_P

TP_CPU_RSVD_TP78

TP_CPU_RSVD_TP76

TP_CPU_RSVD_TP75

PPVCC_S0_CPU

PP1V35_S3RS0_CPUDDR

CPU_PWR_DEBUG

CPU_VIDSOUT

TP_CPU_FC_VCCST_PWRGD

TP_CPU_FC_VCCST

CPU_VIDALERT_L

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVCOMP_S0_CPU

TP_CPU_IVR_ERROR

CPU_VIDALERT_R_L

CPU_VIDSOUT_R

PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

<SCH_NUM>

8 OF 81

8 OF 118

6 8

10 46 59 69 71

6 8

10 46 59 69 71

6

10 21 65 66 69 81

5

5 6

10 18 58

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

SYM 7 OF 12

GROUND

VSS VSS

SYM 8 OF 12

GROUND

VSSVSS

SYM 9 OF 12

VSS_P9(RSVD)

VSS_G18(RSVD)

VSS_AR22(RSVD)

VSS_AB48(RSVD)

VSS_NCTF

VSS_SENSE

VSS

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BGA

OMIT_TABLE

HASWELL

U0500

A11 A15 A19 A22 A26 A30 A33 A37 A40 A44 AA1 AA2 AA3 AA4

AA48

AA5 AA7

AB5 AB51 AB52 AB53 AB54

AB7

AB9 AC48

AC5 AC50

AC7 AD48 AD51 AD54

AD7

AD9

AE1

AE2

AE3

AE4 AE48

AE5 AE50

AE7

AF5

AF6

AF7 AG48

AG5 AG51 AG52 AG53 AG54

AG7

AG9

AH1

AH2

AH3

AH4 AH48

AH5 AH50

AH7

AJ48 AJ51 AJ54 AK48 AK5 AK50 AK7 AK9 AL1 AL4 AL48 AL5 AL7 AM5 AM51 AM52 AM53 AM54 AM7 AN1 AN2 AN3 AN4 AN48 AN5 AN50 AN7 AP51 AP54 AP7 AR12 AR14 AR16 AR18 AR20 AR24 AR26 AR48 AR5 AR50 AR7 AR8 AR9 AT1 AT10 AT12 AT15 AT16 AT18 AT20 AT22 AT25 AT26 AT29 AT33 AT35 AT37 AT39 AT4

BGA

OMIT_TABLE

HASWELL

U0500

AT40 AT42 AT43 AT45 AT46 AT47 AT49

AT5 AT50 AT51 AT52 AT53 AT54

AT6

AT8

AT9 AU13 AU18 AU22 AU25 AU29 AU33 AU37 AU42

AU5

AU9

AV1 AV13 AV18

AV2 AV22 AV25 AV29

AV3 AV33

AV4 AV42

AV5 AV50

AV9 AW13 AW18 AW37 AW42 AW43 AW45 AW46 AW47 AW49

AW5 AW50 AW51 AW54

AW9 AY13 AY22 AY25 AY29 AY33 AY37 AY42

AY50 AY9 B11 B15 B19 B22 B26 B30 B33 B37 B40 B44 B49 B8 BA13 BA18 BA22 BA25 BA29 BA33 BA37 BA4 BA42 BA5 BA50 BA51 BA52 BA53 BA9 BB10 BB11 BB12 BB14 BB15 BB16 BB17 BB18 BB20 BB23 BB25 BB28 BB32 BB33 BB37 BB38 BB39 BB41 BB42 BB43 BB44 BB46 BB47 BB48 BB49 BB5 BB6 BB7 BB9

BGA

OMIT_TABLE

HASWELL

U0500

AB48

AR22

BC10

BC12

BC15

BC18

BC22

BC26

BC3

BC30

BC33

BC36

BC38

BC41

BC43

BC46

BC48

BC5

BC50

BC52

BC7

BD10

BD15

BD18

BD36

BD41

BD46

BD5

BD51

BE10

BE15

BE36

BE41

BE46

BF10

BF12

BF15

BF18

BF22

BF26

BF30

BF33

BF36

BF38

BF41

BF43

BF46

BF48

BF7

C11

C15

C19

C22

C26

C30

C33

C37C4C40

C44

C49

C52C8D11

D15

D19

D22

D26

D30

D33

D37

D40

D44

D49D8E11

E15

E16

E17

E19

E20

E21

E22

E24

E25

E26

E30

E33

E37

E40

E44

E49

E51

E53

E8

F2

F26F3F30

F33

F37F4F40

F44

F49F5G11

G13

G16

G18

G20

G23

G25

G26

G30

G33

G37

G40

G44

G49

G52

G54G7G8G9H44

H49H7J44

J49

J51

J54J7K1K2K3K4K5K6K7

L48L7L9

M48

M50

M52

M54M7N48

N7

A49

A50A8B4

BA1

BA54

BB1

BB54

BD2

BD53

BF49

BF5

BF50

BF6

C53D2E54

F54

G1

P1P2P3P4P48P5P50

P52

P54P6P7P9R48

R7

D50

T48U1U2U3U4

U48U5U50

U52

U54U6U7

V48V7V9

W48

W50

W52

W54W7Y48Y7Y9

58 74

100

5% 1/16W MF-LF 402

PLACE_SIDE=BOTTOM

PLACE_NEAR=U0500.D50:50.8mm

R0960

1

2

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

CPU Ground

CPU_VCCSENSE_N

<SCH_NUM>

9 OF 118

9 OF 81

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Apple Implementation: 8x 210uF(2x nostuff) 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402

PLACEMENT_NOTE (C1024-C1045):

PLACEMENT_NOTE (C1020-C1023):

PLACEMENT_NOTE (C1000-C1019):

Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU)

CPU VCORE Decoupling

CAPs for Acoustic control (C109A-C102D)

PLACEMENT_NOTE (C1046-C1067):

CPU VDDQ Decoupling

Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups) Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)

PLACEMENT_NOTE (C1098-C1099):

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

CPU VCCIO Decoupling

PLACEMENT_NOTE (C1090-C1097):

PLACEMENT_NOTE (C1080-C1089):

CAPs for Acoustic control (C102E-C103F)

Apple Implementation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402

NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.

PLACEMENT_NOTE (C1068-C1076:

0402

1UF

X6S-CERM

10V

10%

Place on bottom side of U0500

C1009

1

2

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1008

1

2

0402

Place on bottom side of U0500

10%

1UF

10V X6S-CERM

C1007

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1031

1

2

10% 10V X6S-CERM

Place on bottom side of U0500

1UF

0402

C1006

1

2

Place on bottom side of U0500

1UF

10%

0402

X6S-CERM

10V

C1005

1

2

1UF

10% 10V X6S-CERM

Place on bottom side of U0500

0402

C1004

1

2

0402

Place on bottom side of U0500

1UF

10V

10% X6S-CERM

C1003

1

2

Place on bottom side of U0500

10V

10%

1UF

0402

X6S-CERM

C1002

1

2

0402

Place on bottom side of U0500

10V

10%

1UF

X6S-CERM

C1001

1

2

0402

Place on bottom side of U0500

1UF

10V

10% X6S-CERM

C1000

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1030

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1029

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1027

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1026

1

2

20%

NO STUFF

Place near U0500 on bottom side

20UF

X5R-CERM

4V 0402-2

C1020

1

2

NO STUFF

20%

Place near U0500 on bottom side

20UF

X5R-CERM

4V 0402-2

C1021

1

2

NO STUFF

20%

Place near U0500 on bottom side

20UF

X5R-CERM

4V 0402-2

C1022

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C109A

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1025

1

2

NO STUFF

CRITICAL

20%

20UF

X5R-CERM

4V 0402-2

C1024

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL 20UF

X5R-CERM

4V 0402-2

C1028

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1032

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1033

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1039

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1038

1

2

NO STUFF

CRITICAL

20%

Place near inductors on bottom side.

20UF

X5R-CERM

4V 0402-2

C1037

1

2

NO STUFF

Place near inductors on bottom side.

20%

CRITICAL 20UF

X5R-CERM

4V 0402-2

C1036

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1035

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1034

1

2

X7R-CERM 0402

16V

0.01UF

10%

C1079

1

2

X6S-CERM 0402

10% 10V

1UF

Place on bottom side of U0500

C1089

1

2

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1088

1

2

X6S-CERM 0402

10%

Place on bottom side of U0500

10V

1UF

C1087

1

2

1UF

10V 0402

Place on bottom side of U0500

10% X6S-CERM

C1086

1

2

X6S-CERM

1UF

0402

Place on bottom side of U0500

10% 10V

C1085

1

2

X6S-CERM 0402

Place on bottom side of U0500

10% 10V

1UF

C1084

1

2

10V 0402

Place on bottom side of U0500

1UF

X6S-CERM

10%

C1083

1

2

1UF

X6S-CERM 0402

Place on bottom side of U0500

10V

10%

C1082

1

2

0402

Place on bottom side of U100.

1UF

X6S-CERM

10V

10%

C1081

1

2

X6S-CERM 0402

Place on bottom side of U0500

10%

1UF

10V

C1080

1

2

Place near U0500 on bottom side

20%

10UF

0603

X6S-CERM

4V

C1093

1

2

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1092

1

2

10UF

20% 4V

0603

Place near U0500 on bottom side

X6S-CERM

C1091

1

2

20%

Place near U0500 on bottom side

10UF

0603

4V X6S-CERM

C1090

1

2

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1097

1

2

20%

Place near U0500 on bottom side

10UF

4V 0603

X6S-CERM

C1096

1

2

0603

20%

Place near U0500 on bottom side

10UF

X6S-CERM

4V

C1095

1

2

20%

Place near U0500 on bottom side

10UF

0603

X6S-CERM

4V

C1094

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL 20UF

X5R-CERM

4V 0402-2

C1043

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL 20UF

X5R-CERM

4V 0402-2

C1042

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1041

1

2

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM

4V 0402-2

C1040

1

2

20%

CRITICAL

330UF-6MOHM

2.0V D15T-ECGLT-COMBO

POLY-TANT

C1098

1

23

D15T-ECGLT-COMBO

CRITICAL

2.0V

20%

330UF-6MOHM

POLY-TANT

C1099

1

23

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1019

1

2

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1018

1

2

0402

Place on bottom side of U0500

1UF

X6S-CERM

10V

10%

C1017

1

2

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1016

1

2

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1015

1

2

X6S-CERM 0402

Place on bottom side of U0500

1UF

10V

10%

C1014

1

2

0402

Place on bottom side of U0500

X6S-CERM

10% 10V

1UF

C1013

1

2

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1012

1

2

0402

Place on bottom side of U0500

10% 10V X6S-CERM

1UF

C1011

1

2

0402

10% 10V

Place on bottom side of U0500

X6S-CERM

1UF

C1010

1

2

Place near inductors on bottom side.

CRITICAL

X5R-CERM 0402-2

4V

20UF

20%

C1065

1

2

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

CRITICAL

C1064

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1063

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1062

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1061

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1060

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1059

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1058

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1057

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1056

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1055

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1054

1

2

Place near inductors on bottom side.

CRITICAL

X5R-CERM 0402-2

4V

20UF

20%

C1053

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1052

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1051

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1050

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1049

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1048

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1047

1

2

CRITICAL

X5R-CERM 0402-2

4V

20UF

20%

C1046

1

2

CRITICAL

Place near inductors on bottom side.

20% 4V X5R-CERM 0402-2

20UF

C1045

1

2

CRITICAL

Place near inductors on bottom side.

20% 4V X5R-CERM 0402-2

20UF

C1044

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1067

1

2

CRITICAL

Place near inductors on bottom side.

X5R-CERM 0402-2

4V

20UF

20%

C1066

1

2

POLY-TANT

2.5V

20%

210UF

CASE-B2S

CRITICAL

C1068

1

2

POLY-TANT CASE-B2S

20%

210UF

CRITICAL

2.5V

C1069

1

2

CASE-B2S

2.5V

20%

210UF

CRITICAL

POLY-TANT

C1070

1

2

20%

2.5V CASE-B2S

CRITICAL 210UF

POLY-TANT

NO STUFF

C1071

1

2

POLY-TANT

2.5V

210UF

CRITICAL

20%

CASE-B2S

C1072

1

2

POLY-TANT CASE-B2S

210UF

CRITICAL

2.5V

20%

NO STUFF

C1073

1

2

CRITICAL

CASE-B2S

2.5V

210UF

POLY-TANT

20%

C1074

1

2

20%

210UF

2.5V CASE-B2S

POLY-TANT

CRITICAL

C1075

1

2

CASE-B2S

2.5V

20%

210UF

POLY-TANT

CRITICAL

C1076

1

2

20%

2.5V CASE-B2S

210UF

CRITICAL

POLY-TANT

C1077

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C109B

1

2

NO STUFF

20%

20UF

X5R-CERM

4V 0402-2

C109C

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C109D

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C109E

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C109F

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101A

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101B

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101C

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101D

1

2

Place near U0500 on bottom side

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C1023

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101E

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C101F

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102A

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102B

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102C

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102D

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103F

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103E

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103D

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103C

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103B

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C103A

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102F

1

2

20%

NO STUFF

20UF

X5R-CERM

4V 0402-2

C102E

1

2

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

CPU Decoupling

PPVCC_S0_CPU

PP1V35_S3RS0_CPUDDR

PPVCCIO_S0_CPU

10 OF 81

10 OF 118

<SCH_NUM>

6 8

46 59 69 71

6 8

21 65 66

69 81

5 6 8

18 58

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN

OUT

IN

OUT OUT

OUT

IN

OUT

IN

OUT OUT

IN

OUT OUT

OUT

NC

HDA_SDI1 HDA_SDI2

TP25 TP22

HDA_DOCK_RST*/GPIO13

SATA_RXP0

SATA_RXP5/PERP2

SATA_RXN5/PERN2

TP8

SRTCRST*

RTCX1 RTCX2

HDA_BCLK

DOCKEN*/GPIO33

SATA_RCOMP

SATA_TXN0

SATA_TXP4/PETP1

SATA_TXP1

SATA_TXN4/PETN1

SATA_TXN1

SATA0GP/GPIO21

SATALED*

SPKR

JTAG_TDI

JTAG_TDO

JTAG_TMS

TP20

JTAG_TCK

INTRUDER*

HDA_SYNC

HDA_SDI3

HDA_SDO

SATA_RXP2

SATA_RXN2

SATA_TXN2 SATA_TXP2

SATA_RXN3 SATA_RXP3 SATA_TXN3

TP9

SATA_IREF

SATA1GP/GPIO19

SATA_TXP0

SATA_RXN1 SATA_RXP1

RTCRST*

INTVRMEN

SATA_RXN0

SATA_RXP4/PERP1

SATA_RXN4/PERN1

SATA_TXP3

SATA_TXP5/PETP2

SATA_TXN5/PETN2

HDA_SDI0

HDA_RST*

JTAG

(1 OF 11)

RTC

AZALIA

SATA

CLOCKS

(2 OF 11)

PCIECLKRQ2*/GPIO20/SMI*

CLKOUT_33MHZ4

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

PCIECLKRQ0*/GPIO73

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_PCIE_P6

CLKOUT_PCIE_N6

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

TP18

TP19

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE_P5

CLKOUT_PCIE_N5

PCIECLKRQ1*/GPIO18

CLKOUT_DPNS_N CLKOUT_DPNS_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

PEG_A_CLKRQ*/GPIO47

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_DP_P

CLKOUT_DP_N

CLKOUT_PCIE_P7

CLKOUT_PCIE_N7

XTAL25_OUT

XTAL25_IN

ICLK_IREF

DIFFCLK_BIASREF

CLKIN_GND_N CLKIN_GND_P

CLKIN_DMI_P

CLKIN_DMI_N

CLKOUT_33MHZ2

CLKIN_SATA_P

CLKIN_SATA_N

CLKOUTFLEX0/GPIO64

CLKIN_33MHZLOOPBACK

CLKOUT_33MHZ0 CLKOUT_33MHZ1

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX3/GPIO67

CLKOUT_33MHZ3

REFCLK14IN

CLKIN_DOT96_P

CLKIN_DOT96_N

PCIECLKRQ3*/GPIO25

PEG_B_CLKRQ*/GPIO56

PCIECLKRQ4*/GPIO26

PCIECLKRQ7*/GPIO46

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

OUT OUT

OUT

IN

IN OUT OUT

OUT OUT

IN

NC NC

NC

OUT

IN

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks. PEG-attached (CPU) PCIe devices must use one set, while PCH-attached PCIe devices use the other set. If 2 or less devices are attached to PEG the CLKOUT_PEG outputs can be used for those devices.

(IPD-DOCKEN#?)

(IPD)

NOTE: ENET pair only used if SD Card Reader is USB3.

Secondary HDD/SSD (SATA only)

Primary HDD/SSD (SATA only)

Reserved: ODD

Unused

PCIe:

SATA Port assignments:

Reserved: Ethernet (if not combo w/SD Card)

Unused

(IPD)

(IPU)

(IPD-boot)

Unused clock terminations for FCIM Mode

(IPD) (IPD)

(IPU-PLTRST#)

Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

(IPD-PWROK)

(IPU-RSMRST#)

(IPD-PWROK)

(IPD-PWROK) (IPD-PWROK)

(IPD-PWROK)

1.5V -> 1.1V

(IPU)

(IPD-PLTRST#)

(IPD)

If HDA = S0, must also ensure that signal cannot be high in S3.

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

19 75

52 76

330K

1/20W

5%

201

MF

R1100

1

2

1/20W

5%

201

MF

1M

R1101

1

2

1/20W

5%

201

MF

20K

R1102

1

2

1/20W

5%

201

MF

20K

R1103

1

2

10V

10% 402

X5R

1UF

C1103

1

2

10V

10% 402

X5R

1UF

C1102

1

2

1/20W

1%

201

MF

7.5K

PLACE_NEAR=U1100.AY5:2.54mm

R1130

1

2

11 70

18 71

340

MF-LF

402

1%

1/16W

R1172

1 2

1K

1/20W

1%

201

MF

R1173

1

2

19 75

18

11 18

34 76

37 76

18

37 76

11 35

11 36

11 28

6

74

6

74

6

74

6

74

19 76

11 70

28 76

MF

1/20W

5% 201

4.7K

R1177

1 2

4.7K

201

1/20W

5% MF

R1178

1 2

10K

MF 2015%

1/20W

R1134

1 2

10K

MF 2015%

1/20W

R1142

1 2

10K

MF 2015%

1/20W

R1169

1 2

10K

MF 2015%

1/20W

R1144

1 2

10K

MF 2015%

1/20W

R1145

1 2

10K

MF 2015%

1/20W

R1147

1 2

10K

MF 2015%

1/20W

R1114

2 1

10K

MF 201

1/20W

5%

R1115

1 2

1/20W

5% 201MF

10K

R1143

1 2

1/20W

5% 201MF

10K

R1133

1 2

1/20W

10K

MF 2015%

R1179

1 2

1/20W

5% 201MF

10K

R1146

1 2

1/20W

5% 201MF

10K

R1148

1 2

52 76

10K

MF 2015%

1/20W

R1191

1 2

10K

MF 2015%

1/20W

R1192

1 2

10K

MF5%

1/20W

201

R1193

1 2

10K

MF 2015%

1/20W

R1194

1 2

10K

MF 2015%

1/20W

R1195

1 2

10K

MF 2015%

1/20W

R1196

1 2

10K

MF 2015%

1/20W

R1197

1 2

5% 201MF

10K

1/20W

R1170

1 2

10K

MF 2015%

1/20W

R1171

1 2

OMIT_TABLE

LYNXPOINT

MOBILE

FCBGA

U1100

B17

B25

C22

C24

L22 K22 G22 F22

A24

A22

A8

G10

AB3

AE2

AD3

AD1

D9

B5 B4

AT1 AU2

BD4

AY5

BC8

BC10

BB9

BC12

BD13

BC14

BE8

BE10

BD9

BE12

BB13

BE14

AW8

AV10

AY13

AR13

AV15

AP15

AY8

AW10

AW13

AT13

AW15

AR15

AP3

AL10

B9

AB6

C26

F8

BB2

BA2

MOBILE

LYNXPOINT

OMIT_TABLE

FCBGA

U1100

D17

AY24 AW24

H33 G33

AR24 AT24

BE6 BC6

D44 E44 B42 F41 A40

AF39 AF40

AJ40 AJ39

AF35 AF36

AH43 AH45

Y43

AA44

AB43

AD43

AF43

AE44

AB40

AJ44

Y45

AA42

AB45

AD45

AF45

AE42

AB39

AJ42

AB35 AB36

Y39 Y38

C40 F38 F36 F39

AN44

AM45

AB1

AF1

AF3

T3

V3

AA2

AE4

Y3

AF6

U4

F45

AD38

AD39

AM43 AL44

6

74

6

74

72 74

PLACE_NEAR=U1100.B25:1.27mm

MF 2015%

1/20W

33

R1110

1 2

PLACE_NEAR=U1100.A24:1.27mm

2015%

1/20W33MF

R1113

1 2

1/20W

5% 201MF

33

PLACE_NEAR=U1100.A22:1.27mm

R1111

1 2

PLACE_NEAR=U1100.C24:1.27mm

33

MF 2015%

1/20W

R1112

1 2

19 76

72 75

72

11 18

1/20W

MF

1%

PLACE_NEAR=U1100.AN44:2.54mm

201

7.5K

R1190

2 1

11 70

10K

MF 2015%

1/20W

R1176

1 2

35 76

11 70

72 75

PCH RTC/HDA/JTAG/SATA/CLK

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

ENET_CLKREQ_L

NC_PCIE_CLK100M_PEGBN

PCH_PEGCLKRQB_L_GPIO56 ENET_MEDIA_SENSE_RDIV

XDP_PCH_TCK

ENET_MEDIA_SENSE_RDIV

DP_TBT_SEL

HDA_SDOUT

HDA_SDIN0

PCH_CLK96M_DOT_N

PCH_SPKR DP_TBT_SEL

PCH_SRTCRST_L PCH_INTRUDER_L

HDA_SYNC_R

PP1V5_S0

PCH_INTRUDER_L PCH_INTVRMEN_L

PCH_SRTCRST_L

RTC_RESET_L

PPVRTC_G3H

SYSCLK_CLK25M_SB

NC_HDA_SDIN3

NC_HDA_SDIN1

PCH_DIFFCLK_BIASREF

PCH_CLK14P3M_REFCLK

PCH_CLKIN_GNDN PCH_CLKIN_GNDP

PCH_CLK100M_SATA_P

NC_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO67_CLKOUTFLEX3

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

DMI_CLK100M_CPU_N

NC_PCIE_CLK100M_ENETN

SYSCLK_CLK32K_RTC

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_BIT_CLK

XDP_PCH_TMS

XDP_PCH_TDO

PP1V5_S0

SSD_CLKREQ_L

NC_PCH_GPIO64_CLKOUTFLEX0

PCH_SATALED_L

XDP_DD2_ENETSD_CLKREQ_L AP_CLKREQ_L

PCH_CLKRQ5_L_GPIO44 PEG_CLKREQ_L PCH_CLKRQ7_L_GPIO46

ENET_CLKREQ_L

HDA_SYNC

HDA_RST_L

PCH_INTVRMEN_L RTC_RESET_L

PCH_SPKR

XDP_PCH_TDI

NC_PCH_GPIO65_CLKOUTFLEX1

PCH_CLK33M_PCIIN

SYSCLK_CLK25M_SB_R

PCH_CLK96M_DOT_P

PCH_CLKRQ5_L_GPIO44

NC_PCIE_CLK100M_PE5N

NC_PCI_CLK33M_OUT3

PCH_CLKRQ7_L_GPIO46

NC_PCIE_CLK100M_SWN NC_PCIE_CLK100M_SWP

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_GPUN

NC_PCI_CLK33M_OUT2

NC_PCIE_CLK100M_GPUP

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

XDP_DD3_AP_CLKREQ_L

PCIE_CLK100M_CAMERA_N PCIE_CLK100M_CAMERA_P

CAMERA_CLKREQ_L

TBT_CLKREQ_L

PEG_CLKREQ_L

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

NC_ITPXDP_CLK100MN NC_ITPXDP_CLK100MP

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

XDP_DC1_SATARDRVR_EN

DP_AUXCH_ISOL_L

PP1V5_S0

PCH_CLK100M_SATA_N

CPU_CLK135M_DPLLREF_P

CPU_CLK135M_DPLLREF_N

CPU_CLK135M_DPLLSS_P

CPU_CLK135M_DPLLSS_N

DMI_CLK100M_CPU_P

NC_PCIE_CLK100M_PEGBP PCH_PEGCLKRQB_L_GPIO56

NC_PCIE_CLK100M_ENETP

CAMERA_CLKREQ_L TBT_CLKREQ_L

NC_HDA_SDIN2

HDA_SDOUT_R

TP_PCIE_ENET_R2D_CN TP_PCIE_ENET_R2D_CP

NC_SATA_F_D2RN

TP_PCIE_ENET_D2RP

TP_PCIE_ENET_D2RN

NC_SATA_D_D2RN

NC_SATA_D_R2D_CP

NC_SATA_D_D2RP NC_SATA_D_R2D_CN

NC_SATA_F_R2D_CP

NC_SATA_F_D2RP NC_SATA_F_R2D_CN

XDP_DC0_DP_AUXCH_ISOL_L XDP_DC1_SATARDRVR_EN

NC_SATA_ODD_R2D_CP

NC_SATA_ODD_R2D_CN

NC_SATA_ODD_D2RP

NC_SATA_ODD_D2RN

NC_SATA_A_R2D_CP

NC_SATA_A_R2D_CN

NC_SATA_A_D2RP

NC_SATA_A_D2RN

NC_SATA_B_D2RN NC_SATA_B_D2RP NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP

PCH_SATALED_L

PCH_SATA_RCOMP

SSD_CLKREQ_L

NC_PCIE_CLK100M_ENETSDN NC_PCIE_CLK100M_ENETSDP

XDP_DD2_ENETSD_CLKREQ_L

PP3V3_SUS PP3V3_S0

11 OF 81

11 OF 118

<SCH_NUM>

72

11

11 70

76

11

11 70

11 76

76

11 12 13 15 17 19 52 64 66 68 69 71

11 76

11

12 15 19 69

72

76

72

76

72

76

11 12 13 15 17 19 52 64 66 68 69 71

11 35

72

11

11 18

18 34

11

11 70

11

11 70

11 76

11

72

75

76

11

72

11

72

11 18

18

11 12 13 15 17 19 52 64 66 68 69 71

76

72

11

72

11 36

11 28

72

19 76

72

11

75

12 13 14 15 17 50 64 65 66 69

12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55 65

66 67 69 71 81

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

DAC_IREF VGA_IRTN

VGA_VSYNC

VGA_HSYNC

PIRQH*/GPIO5

PIRQG*/GPIO4

DDPC_AUXN

EDP_BKLTEN

EDP_VDDEN

GPIO54

GPIO51

GPIO55

GPIO53

DDPC_CTRLCLK

DDPB_CTRLDATA

DDPB_CTRLCLK

DDPC_CTRLDATA

EDP_BKLTCTL

PIRQF*/GPIO3

DDPC_HPD

DDPC_AUXP DDPD_AUXP

DDPB_HPD

DDPD_HPD

PIRQE*/GPIO2

DDPD_CTRLDATA

DDPD_CTRLCLK

VGA_RED

PIRQA*

GPIO52

GPIO50

PIRQD*

PIRQC*

PIRQB*

PME*

PLTRST*

DDPB_AUXN

VGA_BLUE VGA_GREEN

DDPB_AUXP

DDPD_AUXN

VGA_DDC_DATA

VGA_DDC_CLK

CRT

PCI

DISPLAY

(5 OF 11)

EDP

OUT

IN

OUT

IN

BI

OUT

IN

SYSTEM POWER

MANAGEMENT

(4 OF 11)

DMI

FDI

SUSACK*

RI*

DPWROK

BATLOW*/GPIO72

PWRBTN*

RSMRST*

DRAMPWROK

SLP_LAN*

SLP_A*

PWROK

SLP_SUS*

ACPRESENT/GPIO31

SLP_WLAN*/GPIO29

DSWVRMEN

SLP_S4*

DMI_TXN1

DMI_TXN3

DMI_TXN2

DMI_TXP1

DMI_TXP0

TP5

PMSYNCH

DMI_RXN0

TP15

TP16

TP13

TP17

DMI_RXN1

SYS_RESET*

FDI_RXP1

FDI_RXN1

FDI_RXP0

FDI_RXN0

APWROK

TP21

SUSWARN*/SUSPWRNACK/GPIO30

DMI_TXN0

FDI_RCOMP

DMI_TXP2 DMI_TXP3

DMI_IREF

TP12

DMI_RCOMP

TP7

WAKE*

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

DMI_RXP0

DMI_RXP3

DMI_RXP2

DMI_RXP1

TP10

SLP_S3*

CLKRUN*

SYS_PWROK

DMI_RXN2

FDI_IREF

FDI_INT

FDI_CSYNC

DMI_RXN3

OUT

IN IN IN

OUT

NC NC NC

NC NC

NC

NC NC

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD-DeepSx)

DG v1.0 (Table 12-18).

(IPD-PLTRST#)

(IPU)

(IPD-PLTRST#)

(OD)

(IPU)

(IPU-PWROK&PCIRST#)

(IPD-DeepSx)

(IPU)

(IPD-PLTRST#)

(IPU-RSMRST#)

Redundant to pull-up on audio page

VGA DAC Disabled per SB

5

74

5

74

201

1/20W

MF

PLACE_NEAR=U1100.AY17:12.7mm

1%

7.5K

R1200

1

2

5

74

5

74

5

74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

5

72 74

FCBGA

MOBILE

LYNXPOINT

OMIT_TABLE

U1100

U40

H45

H43

R40 R39

K40

K43

K45

R35 R36

K38

J42

J44

N40 N38

H39

N36

K36

G36

A12

C10

B13

A10

C12

AL6

H20 L20 K17 M20

G17 F17 L15 M15

Y11

AD10

T45

M43 M45

U44

N42

U39

V45

N44

5%

201

1/20W MF

330K

R1215

1

2

5%

201

1/20W

MF

10K

R1205

1

2

12 45 65 66

5%

201

1/20W MF

100K

R1209

1

2

19 41 71 76

18 19 41 71 76

6

21 74

12 19 71 76

66 71 76

12 18 41 76

41 42

12 30 41 43

12 34 36 71 76

12 41 50 71

20 41 50 71

42

12 41 66

12 21 34 38 41 66 68 71

12 21 41 66 71

6

74

41 71 76

5%

201

1/20W

MF

100K

R1223

2 1

5%

201

1/20W

MF

1K

R1225

1 2

5%

201

1/20W

MF

10K

R1291

1 2

5%

201

1/20W

MF

100K

R1222

2 1

5%

201

1/20W

MF

100K

R1221

2 1

5%

201

1/20W

MF

100K

R1224

2 1

5%

201

1/20W

MF

100K

R1284

2 1

5%

201

1/20W

MF

100K

R1281

2 1

OMIT_TABLE

FCBGA

LYNXPOINT

MOBILE

U1100

E6

AB7

K7

AN7

BE16

AY17

AW22 AR20 AP17 AV20

AY22 AP20 AR17 AW20

BD21 BE20 BD17 BE18

BB21 BC20 BB17 BC18

L13

H3

C8

AL39 AL40

AT45

AR44

AJ35 AL35

AJ36 AL36

AY3

K1

F10

N4

J2

F3

G5

H1

C6

Y7

F1

D2

U7

R6

Y6

J4

AD7

AM1

AW44

AW17

AU44

AV45

AV43

AU42

AB10

AY45

AV17

K3

12 67 70 71

12 63 70 71

63 70

5

74

201

1/20W

MF

PLACE_NEAR=U1100.AR44:12.7mm

7.5K

1%

R1210

1

2

5% 201

1/20W

MF

10K

R1261

1 2

5% 201

1/20W

MF

10K

R1263

1 2

5%

201

1/20W

MF

10K

R1262

1 2

5%

201

1/20W

MF

10K

R1260

1 2

5% 201

1/20W

MF

NO STUFF

10K

R1233

1 2

5% 201

1/20W

MF

10K

R1231

1 2

5% 201

1/20W

MF

NO STUFF

100K

R1214

1 2

5% 201

1/20W

MF

10K

R1230

1 2

5% 201

1/20W

MF

100K

R1217

1 2

5% 201

1/20W

MF

10K

R1218

1 2

12 70

5% 201

1/20W

MF

10K

R1216

1 2

12 70

12 29

12 70

18 20 21 71

MF

1/20W

0201

0

5%

R1286

1

2

12 70

5%

201

1/20W

MF

10K

R1240

2 1

5%

201

1/20W

MF

3.0K

R1239

1 2

43

12 70

PCH DMI/FDI/PM/GFX/PCI

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

PP3V3_S0

PM_SLP_S3_L

PM_SLP_S5_L

PM_SLP_SUS_L PM_SYNC

PP3V3_S5

EDP_IG_PANEL_PWR

EDP_IG_BKL_ON

PM_SLP_SUS_L

PM_SLP_S4_L

PCIE_WAKE_L

AUD_I2C_INT_L

TBT_PWR_REQ_L

AUD_IP_PERIPHERAL_DET

SDCONN_OC_L

BT_PWRRST_L

AUD_IPHS_SWITCH_EN_PCH

ENET_LOW_PWR_PCH

PM_CLKRUN_L

PM_BATLOW_L

PM_PWRBTN_L

PCH_FDI_RCOMP

LPC_PWRDWN_L PM_CLK32K_SUSCLK_R PM_SLP_S5_L

PCH_STRP_TOPBLK_SWP_L

PM_PWRBTN_L SMC_ADAPTER_EN

PP3V3_S0

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_HPD HDMI_HPD

TBT_PWR_REQ_L

DP_TBTSNK1_DDC_DATA

PP3V3_SUS

PM_SYSRST_L

PM_RSMRST_L

PM_MEM_PWRGD

PP1V5_S0

DP_TBTSNK0_AUXCH_C_N

PPVRTC_G3H

PCH_DSWVRMEN PM_DSW_PWRGD

TP_PCH_SLP_S0_L

PCH_RI_L

FDI_CSYNC FDI_INT

PM_SLP_S4_L

TP_PCH_STRP_BBS1

DP_TBTSNK0_DDC_DATA

DP_TBTSNK0_DDC_CLK

DP_TBTSNK1_DDC_CLK

HDMI_DDC_DATA

HDMI_DDC_CLK

DP_TBTSNK1_AUXCH_C_N NC_DP_IG_D_AUXCHN

DP_TBTSNK0_AUXCH_C_P

NC_DP_IG_D_AUXCHP

DP_TBTSNK0_HPD

AUD_IP_PERIPHERAL_DET

DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>

DMI_N2S_P<0>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<3>

DMI_S2N_N<0>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<3> DMI_S2N_P<0>

DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>

PM_PCH_SYS_PWROK

PM_BATLOW_L

EDP_IG_BKL_PWM EDP_IG_BKL_ON EDP_IG_PANEL_PWR

PCI_INTB_L PCI_INTC_L

TP_PCH_SLP_LAN_L

PCIE_WAKE_L PM_CLKRUN_L

TP_PCH_SLP_WLAN_L

PM_SLP_S3_L TP_PM_SLP_A_L

TP_PCH_STRP_ESI_L

AUD_IPHS_SWITCH_EN_PCH

PCI_INTD_L

PCI_INTA_L

ENET_LOW_PWR_PCH

BT_PWRRST_L

PCH_DMI_RCOMP

PM_PCH_PWROK

PLT_RESET_L

NC_PCI_PME_L

AUD_I2C_INT_L

SDCONN_OC_L

PCH_SUSWARN_L

PCH_SUSACK_L

PP1V5_S0

<SCH_NUM>

12 OF 118

12 OF 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

12 21 41 66 71

12 41 66

14 15 17 18 19 21 31 32 34 61

64 65 66 69

70 71 81

12 67 70 71

12 63 70 71

12 45 65 66

12 21 34 38 41 66 68 71

12 34 36 71 76

12 70

12 29

12 70

12 41 50 71

12 30 41 43

12 18 41 76

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

28 70 74

28 70

20 68 70

33 70

11 13 14 15 17 50 64 65 66 69

11 12 13 15 17 19 52 64 66 68 69 71

28 70 74

11 15 19 69

76

33 70

68 70 71

28 70 74

72

28 70 74

72

28 70

72

11 12 13 15 17 19 52 64 66 68 69 71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

BI

BI BI

IN IN

OUT

IN

OUT

IN

BI

IN

OC1*/GPIO40 OC2*/GPIO41

OC5*/GPIO9

OC0*/GPIO59

OC3*/GPIO42

OC6*/GPIO10

OC4*/GPIO43

OC7*/GPIO14

USB2P6

USB2N6

USB2P5

USB2N7

USB2N5

USB2N13

USB2P0

USB2P4

USB2P10

USB2P2

USB2P3

USB2P8

PETN7

PETP6

PETN4

PETN3

PETN1_USB3TN3

PCIE_IREF

USB3TP6

USB3TN5

USB3TN1

PETN8 PETP8

PETN5

PCIE_RCOMP

USB3TN6

USB3TN2

USB3TP1

PETP7

PETN6

PETP1_USB3TP3

TP11

USB3TP5

USB3TP2

PETP5

TP6

USB2N0

USB2N4

USB2N10

PERN6

PERP3

PERP1_USB3RP3

PERP6

PERN5

PERN3

PERN1_USB3RN3

USB3RN5

USB3RN2

PERP5

USB3RP5

USB3RP2

PERN7 PERP7

PERN4

PERN2_USB3RN4

PERP4

PERP2_USB3RP4

USB3RN6

USB3RN1

USB3RP6

USB3RP1

PERP8

PERN8

USB2N1

USB2N2

USB2N3

USB2N9 USB2P9

USB2N8

USB2P7

USB2N11

USB2P13

USB2P1

PETP4

USB2P11

PETP2_USB3TP4

PETN2_USB3TN4

PETP3

USB2N12 USB2P12

TP23

TP24

USBRBIAS*

USBRBIAS

(9 OF 11)

USB

PCI-E

BI

IN

IN OUT OUT

IN

OUT OUT

IN

OUT OUT

IN

OUT OUT

OUT

SML0CLK

SML1ALERT*/PCHHOT*/GPIO74

LDRQ1*/GPIO23

LAD1

TP3

TP4

TP2

TP1

SPI_CS1*

SERIRQ

SPI_CS0*

SPI_IO2

SPI_IO3

SPI_CLK

SPI_CS2*

SPI_MISO

SPI_MOSI

LAD2

SML1DATA/GPIO75

CL_RST*

SML1CLK/GPIO58

LDRQ0*

TD_IREF

CL_CLK

CL_DATA

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

LAD0

SML0DATA

LFRAME*

LAD3

SMBUS

LPC

(3 OF 11)

SPI

C-LINK

IN BI

BI

OUT

BI

OUT

BI

OUT

BI BI BI

BI BI

NC

BI

OUT

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN IN

OUT OUT

IN IN

OUT OUT

IN IN

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ext B (LS/FS/HS)

Ext C (SS)

(IPD)

Trackpad

BT

IR

Ext D (SS)

USB3 Port Assignments:

Ext B (SS)

Ext A (SS)

Reserved: Camera

Ext D (LS/FS/HS)

Unused

Reserved: PSOC (Legacy Trackpad)

USB Port Assignments:

Ext C (LS/FS/HS)

Ext A (LS/FS/HS)

Reserved: WiFi (HS)

Reserved: SD (HS)

(IPU)

(IPU) (IPU)

(IPD)

(IPU)

(IPU-LDRQ1#?)

(IPU)

(IPU/IPD)

AirPort

Camera

Lane 3 (PCIe-only)

Lane 2 (PCIe-only)

SSD (Gumstick)

Or PCIe switch if TBT/SSD

SSD (Gumstick)

(PCIe-only)

Lane 0

Lane 1

Or PCIe switch if TBT/SSD

(PCIe-only)

SSD (Gumstick)

USB3 Port Assignments:

PCIe/USB3 Port Assignments:

SD Card Reader (& Ethernet if combo)

PCIe Port Assignments:

Unused

72 75

1/20W

5% 201MF

10K

R1367

2 1

10K

MF 2015%

1/20W

R1368

1 2

10K

1/20W

MF 2015%

R1361

1 2

10K

MF 2015%

1/20W

R1362

1 2

10K

MF 201

1/20W

5%

R1360

1 2

10K

MF 2015%

1/20W

R1369

1 2

13 18

18

13 18

18

13 18

38 75

13 18

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

U1100

P3 V1 U2 P1 M3 T1 N2 M1

BE30

BD29

AW31

AT31

AW33

AT33

AW36

AY38

AT40

AN38

AY31

AR31

AY33

AR33

AV36

AW38

AT39

AN39

BE32

BD33

BE34

BE36

BD37

BC38

BE40

BD42

BC32

BB33

BC34

BC36

BB37

BE38

BC40

BD41

BC30

L33

M33

BB29

B37

A38

B29

A28

G26

F24

A36

A34

B33

F31

K31

G29

A32

A30

D37

C38

D29

C28

F26

G24

C36

C34

D33

G31

L31

H29

C32

C30

AR26

AW26

AW29

AR29

AP26

AV26

AV29

AP29

BE24

BD25

BE26

BD27

BD23

BC24

BC26

BE28

K26

K24

38 75

68 71 75

68 75

72 75

50 76

MOBILE

LYNXPOINT

OMIT_TABLE

FCBGA

U1100

AF11

AF10

AF7

A20 C20 A18 C18

D21 G20

B21

AL11

N7

R10 U11

N8

U8 R7

H6

K6 N11

AJ11

AJ7

AL7

AJ10

AJ4

AJ2

AH3

AH1

AY43

BA45 BC45

BE44

BE43

44 76

18 22 44 63 68 71 76

PLACE_NEAR=U1100.BD29:12.7mm

1/20W 201

MF

1%

7.5K

R1300

1

2

201MF5%

1/20W

33

R1340

1 2

MF 2015%

1/20W

33

R1341

1 2

2015%331/20W

MF

R1343

1 2

MF 201

33

5%

1/20W

R1342

1 2

5% 201MF

1/20W

33

R1344

1 2

13 20

13 41 50 71

1/20W

5% 201MF

10K

R1350

1 2

41 50 71 76

8.2K

MF

1/20W 201

1%

R1380

1

2

34 75

72 75

39 75

1/20W

5% 201MF

10K

R1355

1 2

1/20W

5% 201MF

10K

R1354

1 2

1/20W

5% 201MF

10K

R1353

1 2

1/20W

5% 201MF

10K

R1320

1 2

1/20W

5% 201MF

10K

R1321

1 2

50 76

13 50

18

10K

MF 2015%

1/20W

R1351

1 2

1/20W

5% 201MF

1K

R1393

1 2

1/20W

5% 201MF

1K

R1392

1 2

68 71 75

20 68 71 76

68 71 75

35 76

34 76

37 76

1% 1/20W

201

MF

22.6

PLACE_NEAR=U1100.K24:11.4mm

R1370

1

2

PCH PCI-E/USB

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

USB3_SD_R2D_C_P

USB3_SD_R2D_C_N

USB3_SD_D2R_P

USB3_SD_D2R_N

NC_USB3_SPARE_R2D_CN NC_USB3_SPARE_R2D_CP

NC_USB3_SPARE_D2RN NC_USB3_SPARE_D2RP

PCIE_CAMERA_D2R_N

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_D2R_P PCIE_CAMERA_R2D_C_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_D2R_P<0> PCIE_SSD_R2D_C_N<0>

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_N<2>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_N<3>

PCIE_SSD_R2D_C_P<2>

PCH_USB_RBIAS

LPC_AD_R<0>

SMBUS_PCH_DATA

SML_PCH_0_CLK SML_PCH_0_DATA

SML_PCH_1_CLK SML_PCH_1_DATA

PCH_SML0ALERT_L

SMBUS_PCH_CLK

PCH_SMBALERT_L

NC_CLINK_DATA

NC_CLINK_CLK

PCH_TD_IREF

NC_CLINK_RESET_L

SPI_MOSI_R SPI_MISO

TP_SPI_CS2_L

SPI_CLK_R

SPI_IO<3>

SPI_IO<2>

SPI_CS0_R_L

LPC_SERIRQ

TP_SPI_CS1_L

TBT_PWR_EN_PCH

PCH_SML1ALERT_L

LPC_AD<0>

LPC_AD<2> LPC_AD<3>

LPC_AD<1>

LPC_FRAME_L

USB_EXTA_N USB_EXTA_P

NC_USB_EXTCN NC_USB_EXTCP

USB_EXTB_N USB_EXTB_P

NC_USB_EXTDN NC_USB_EXTDP

USB_BT_N

NC_USB_IRN

USB_BT_P

USB_TPAD_N

NC_USB_IRP

USB_TPAD_P

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_C_N

USB3_EXTB_D2R_N

USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_P USB3_EXTB_R2D_C_N

NC_USB3_EXTC_D2RP

NC_USB3_EXTC_R2D_CP

NC_USB3_EXTD_R2D_CN

XDP_DA0_USB_EXTA_OC_L XDP_DA1_USB_EXTC_OC_L

XDP_DA3_CAMERA_PWR_EN XDP_DB0_USB_EXTB_OC_L XDP_DB1_USB_EXTD_OC_L

XDP_DB3_SDCONN_STATE_CHANGE_L

NC_USB_7P

NC_USB_WLANN

NC_USB_SDN

TP_USB_CAMERAN

NC_USB_4N

NC_USB_WLANP

NC_USB_SDP

NC_USB_4P NC_USB_PSOCN

NC_USB_7N

NC_USB_PSOCP NC_USB_6N

PP1V5_S0

NC_USB3_EXTD_D2RN NC_USB3_EXTD_D2RP

NC_USB3_EXTD_R2D_CP

XDP_DB2_SD_PWR_EN

PCH_PCIE_RCOMP

NC_LPC_DREQ0_L

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

NC_USB3_EXTC_R2D_CN

TP_USB_CAMERAP

NC_USB_6P

XDP_DA2_SSD_PWR_EN

USB3_EXTB_R2D_C_P NC_USB3_EXTC_D2RN

PCH_SML1ALERT_L

PCH_SML0ALERT_L

SPI_IO<2> SPI_IO<3>

PCH_SMBALERT_L

XDP_DB1_USB_EXTD_OC_L SD_PWR_EN

XDP_DB0_USB_EXTB_OC_L

SSD_PWR_EN

LPC_SERIRQ TBT_PWR_EN_PCH XDP_DA0_USB_EXTA_OC_L

XDP_DA1_USB_EXTC_OC_L

PP3V3_SUS PP3V3_SUS

PP3V3_S0

CAMERA_PWR_EN

XDP_DB3_SDCONN_STATE_CHANGE_L

PP3V3_S3RS0_CAMERA

PP3V3_S3

<SCH_NUM>

13 OF 118

13 OF 81

72

75

13

72

13

72 75

72

72 75

72

72 75

72

72 75

72

72 75

11 12 15 17 19 52 64 66 68 69 71

72

72 75

13

13 50

13

13 18

18 68 71

13 18

18 65

13 41 50 71

13 20

13 18

11 12 13 14 15 17 50 64 65 66 69

11 12 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55 65

66 67 69 71 81

18 36

13 18

36 47 69

20 21 22 44 46 47 65 68 69 71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

OUT

BI

IN

OUT

IN

BI

ININ

OUT

IN

OUT

GPIO24

GPIO57

GPIO27

TACH4/GPIO68

SCLOCK/GPIO22

THRMTRIP*

BMBUSY*/GPIO0

SLOAD/GPIO38

GPIO35/NMI*

GPIO34

SDATAOUT1/GPIO48

SDATAOUT0/GPIO39

SATA5GP/GPIO49

SATA3GP/GPIO37

GPIO28

GPIO15

SATA4GP/GPIO16

TACH0/GPIO17

VSS

GPIO8

PLTRST_PROC*

TP14

LAN_PHY_PWR_CTRL/GPIO12

TACH3/GPIO7

TACH2/GPIO6

TACH1/GPIO1

VSS

TACH7/GPIO71

TACH6/GPIO70

TACH5/GPIO69

PECI

PROCPWRGD

RCIN*

VSS

SATA2GP/GPIO36

CPU/MISC

(6 OF 11)

GPIO

OUT

BI

OUT

IN

OUT

BI

OUT

IN

IN IN

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD-PLTRST#)

Redwood Ridge: TBT_CIO_PLUG_EVENT_L, requires pull-up (S0), no isolation necessary.

(IPD)

(IPU-RSMRST#)

(IPU-DeepSx)

(IPU-Boot/SATA4GP?)

(IPU-Boot?)

(IPU-Boot/SATA5GP?)

Cactus Ridge: TBT_CIO_PLUG_EVENT, requires pull-down & isolation.

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high. Systems with chip-down memory should add pull-downs on another page and set straps per software.

Pull-up/down on chipset support page (depends on TBT controller)

NOTE: GPIO70 pull-up/down on project-specific page

NOTE: GPIO0 pull-up/down on project-specific page

6

18 74

21

14 50 71

14 70

14 20

18

14 20

14 50 71

6

42 74

5%

201

1/20W MF

10K

RAMCFG3:H

R1472

1

2

5%

201

1/20W

MF

RAMCFG2:H

10K

R1473

1

2

5%

201

1/20W MF

10K

RAMCFG1:H

R1474

1

2

5%

201

1/20W

MF

10K

RAMCFG0:H

R1475

1

2

14 41

14 20

14 41

14 70

OMIT_TABLE

MOBILE

LYNXPOINT

FCBGA

U1100

AT8

AB11

Y10

R11

AD11

AN6

AP1

U12

Y1

K13

AY1

AU4

AV3

AT6

AT3

AK1

AN2

AK3

BB4

AM3

AN4

AT7

C14

F13

A14

G15

C16

D13

G13

H15

AV1

AN10

BE41

BE5 C45

A5

A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4

N10

5% 201

1/20W

MF

20K

R1411

2 1

5% 201

1/20W

MF

100K

R1495

2 1

5% 201

1/20W

MF

10K

R1491

1 2

5% 201

1/20W

MF

10K

R1492

1 2

5% 201

1/20W

MF

100K

R1493

1 2

5% 201

1/20W

MF

10K

R1494

1 2

5% 201

1/20W

MF

10K

R1484

1 2

5% 201

1/20W

MF

100K

R1490

1 2

5% 201

1/20W

MF

10K

R1496

1 2

5%

201

1/20W

MF

10K

R1485

1 2

5% 201

1/20W

MF

10K

R1412

2 1

29

14 18

5% 201

1/20W

MF

10K

R1498

2 1

5% 201

1/20W

MF

10K

R1450

1 2

5% 201

1/20W

MF

10K

R1455

1 2

5%

201

1/20W

MF

NO STUFF

43

R1470

1 2

5%

0

0201

1/20W

MF

R1440

1 2

5%

201

1/20W

MF

390

R1456

1 2

6

42 74

14 70

20 28

18

14 70

6

5% 201

1/20W

MF

10K

R1486

1 2

5% 201

1/20W

MF

10K

R1499

1 2

5%

201

1/20W

MF

10K

R1413

2 1

14 70

5% 201

1/20W

MF

10K

R1489

1 2

18

14 70

14 18

5%

NO STUFF

402

MF-LF

1/16W

1K

R1457

1

2

18 20 20

PCH GPIO/MISC/NCTF

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

JTAG_ISP_TDO

PP3V3_SUS

XDP_DD0_SSD_PCIE_SEL_L

MEM_VDD_SEL_1V5_L

LPCPLUS_GPIO JTAG_TBT_TMS_PCH

XDP_DC2_ODD_PWR_EN_L JTAG_ISP_TCK

JTAG_ISP_TDI

PCH_RCIN_L

PP3V3_S5

PP3V3_S0

SPIROM_USE_MLB

XDP_DD1_MLB_RAMCFG1

SD_SEL_PCIE_L_USB_H

JTAG_ISP_TDO JTAG_ISP_TDI

SPIROM_USE_MLB

FW_PWR_EN_PCH

XDP_DC3_JTAG_ISP_TCK

XDP_DC2_ODD_PWR_EN_L

XDP_FC1_GPU_GOOD

XDP_DD0_SSD_PCIE_SEL_L LPCPLUS_GPIO

MEM_VDD_SEL_1V5_L

XDP_FC0_HDD_PWR_EN

SMC_RUNTIME_SCI_L

DPMUX_UC_IRQ

FW_PME_L

PCH_RCIN_L

PCH_PROCPWRGD

PCH_PECI

PCH_A20GATE

CPU_RESET_L

PM_THRMTRIP_L

CPU_PWRGD

PM_THRMTRIP_L_R

CPU_PECI

MLB_RAMCFG0

MLB_RAMCFG3

PP3V3_S0

PP1V05_S0

PCH_A20GATE

FW_PME_L

SMC_RUNTIME_SCI_L

DPMUX_UC_IRQ

WOL_EN

TBT_GO2SX_BIDIR SMC_WAKE_SCI_L

FW_PWR_EN_PCH

WOL_EN

TBT_CIO_PLUG_EVENT_L

ISOLATE_CPU_MEM_L

MLB_RAMCFG2

JTAG_TBT_TMS_PCH TBT_GO2SX_BIDIR SMC_WAKE_SCI_L

TBT_POC_RESET_L

14 OF 81

14 OF 118

<SCH_NUM>

14 20

11 12 13 15 17 50 64 65 66 69

14 18

14 70

14 50 71

14 20

14 18

18 20

14 20

14 76

12 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

14 50 71

14 76

14

42 76

20

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

15 17 18 42 62 66 69 71

14

14 70

14 41

14 70

14 41

14 70

20

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

DCPSUS1

DCPSUSBYP

VCCADAC1_5

VSS

VCCVRM

VCCIO

VCCASW

VCC3_3

DCPSUS3

VCCSUS3_3

VCCADACBG3_3

VCC

CRT

USB3

CORE

PCIE/DMI

(7 OF 11)

FDI

HVCMOS

SATA

VCCMPHY

DCPSUS2

VCCUSBPLL

VCCSPI

DCPSST

VCCRTC

VSS

VCCVRM

VCCIO

VCCCLK3_3

VCCCLK

VCCASW

VCC3_3

VCC

V_PROC_IO

DCPRTC

VCCSUSHDA

VCCSUS3_3

VCCDSW3_3

VCCSUS3_3

VCCIO

VCCCLK

THERMAL

(8 OF 11)

GPIO/LPC

USB

HDARTCCPUSPI

CLK/MISC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

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8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10mA Max, 1mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VGA DAC Disabled per SB DG v1.0 (Table 12-18).

VCC3_3: 133mA Max, 3mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

15 mA Max, 1mA Idle

VCC3_3: 133mA Max, 3mA Idle

6uA Max (3.0V, room temperature)

VCCASW: 670mA Max, 34mA Idle

22mA Max, 1mA Idle

4mA Max, 2mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCASW: 670mA Max, 34mA Idle

VCC3_3: 133mA Max, 3mA Idle

??mA Max, ??mA Idle

NOTE: Pin name is VCC but really is 3.3V

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle

Powered in DeepSx

VCCASW: 670mA Max, 34mA Idle

VCC3_3: 133mA Max, 3mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VCCCLK3_3: 55mA Max, 11mA Idle

VCC: 1.312 A Max, 130mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCCLK: 306mA Max, 89mA Idle

VCCVRM: 183mA Max, 68mA Idle

??mA Max, ??mA Idle

Current data from LPT EDS (doc #486708, Rev 1.0).

BYPASS=U1100.A6:6.35mm

0.1UF

402

CERM

10V

20%

C1532

1

2

BYPASS=U1100.A6:6.35mm

1UF

402

CERM

6.3V

10%

C1531

1

2

BYPASS=U1100.A6:6.35mm

0.1UF

402

CERM

10V

20%

C1533

1

2

FCBGA

CKPLUS_WAIVE=PwrTerm2Gnd

MOBILE

LYNXPOINT

OMIT_TABLE

U1100

Y12

AJ26 AJ28

U14

AE18 AE20 AE22 AE24 AE26 AG18 AG20 AG22 AG24

Y26

AA24

R30 R32

AA26 AD20 AD22 AD24 AD26 AD28

P45

M31

Y18 Y20 Y22

AA18

U18 U20 U22 U24 V18 V20 V22 V24

AM22

AN34 AN35

AP22 AR22 AT22

AK18

AK20

AK22

AM18 AM20

AJ30 AJ32

AK26 AK28

AN11

BB44

BE22

P43

OMIT_TABLE

LYNXPOINT

FCBGA

MOBILE

U1100

P14 P16

AA14

Y35

AJ12 AJ14

P18 P20

AP45

L24

AE14 AF12 AG14

AK30 AK32

L17

R18

Y32

AA30 AA32

AD34

L26

L29

M26

M29

U32 V32

AD35

AD36

AE30 AE32

AG30 AG32

A16

U30 U36 V28 V30 Y30

A6

AD12

K8

R20 R22

R24 R26 R28 U26

A26

U35

AF34

AW40

M24

10%

6.3V

1UF

PLACE_NEAR=R1550.1:2.54mm

CERM

402

C1550

1

2

1%

MF-LF

1/20W

5.11

201

PLACE_NEAR=U1100.U14:2.54mm

R1550

1 2

402

CERM

10V

20%

0.1UF

BYPASS=U1100.P14:6.35mm

C1590

1

2

0.1UF

402

CERM

20% 10V

BYPASS=U1100.AA14:6.35mm

C1580

1

2

PCH Power

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

PP3V3_SUS

PP1V05_S0

PP3V3_S5

PP1V05_S0

PP1V5_S0

PP3V3_S0

PP1V05_S0_PCH_VCC_CLK_F

PP1V5_S0

PP1V05_S0

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPSST

PP1V05_S0

PP3V3_S0

PP1V05_S0

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVOUT_S0_PCH_DCPRTC

PP3V3_S0

PP3V3_SUS

PP1V05_S0

PP3V3_SUS

PP1V05_S0

PP1V5_S0

PP3V3_SUS

PPVRTC_G3H

PP3V3_S0

PP1V05_S0

PP1V5_S0

PP1V05_S0

<SCH_NUM>

15 OF 118

15 OF 81

11 12 13 14 15 17 50 64 65 66 69

11 12 13 14 15 17 50 64 65 66

69

14 15 17 18 42 62 66 69 71

12 14 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68

69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

17

11 12 13 15 17 19 52 64 66 68 69 71

14 15 17 18 42 62 66 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

14 15 17 18 42 62 66 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 50 64 65 66 69

14 15 17 18 42 62 66 69 71

11 12 13 14 15 17 50 64 65 66

69

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68

69 71

11 12 13 14 15 17 50 64 65 66

69

11 12 19 69

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68

69 71

11 12 13 15 17 19 52 64 66 68

69 71

11 12 13 15 17 19 52 64 66 68

69 71

11 12 13 15 17 19 52 64 66 68 69 71

14 15 17 18 42 62 66 69 71

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w w w . c h i n a f i x . c o m

VSS

(10 OF 11)

VSSVSS

(11 OF 11)

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MOBILE

OMIT_TABLE

LYNXPOINT

FCBGA

U1100

AL34 AL38

AN36 AN40 AN42

AN8 AP13 AP24 AP31 AP43

AR2 AK16

AL8

AT10 AT15 AT17 AT20 AT26 AT29 AT36 AT38

D42 AV13

AM14

AV22 AV24 AV31 AV33 BB25 AV40

AV6

AW2

F43 AY10

AM24

AY15 AY20 AY26 AY29

AY7

B11

B15

K39 L2 L44

AM26

M17 M22 N12 N35 N39 N6 P22 P24 P26 P28

AM28

P30 P32 R12 R14 R16 R2 R34 R38 R44 R8

AM30

T43 U10 U16 U28 U34 U38 U42 U6 V14 V16

AM32

V26 V43 W2 W44 Y14 Y16 Y24 Y28 Y34 Y36

AM16

Y40 Y8

LYNXPOINT

MOBILE

OMIT_TABLE

FCBGA

U1100

AB8

AC2 AC44 AD14 AD16 AD18 AD30 AD32 AD40

AD6

AD8 AE16 AE28 AF38

AF8 AG16

AG2 AG26 AG28 AG44 AJ16 AJ18 AJ20 AJ22 AJ24 AJ34 AJ38

AJ6

AJ8 AK14 AK24 AK43 AK45 AL12

AL2 BC22 BB42

B19 B23 B27 B31 B35 B39 B7 BA40 BD11 BD15 BD19 AY36 AT43 BD31 BD35 BD39 BD7 D25 AV7 F15 F20 F29 F33 BC16 D4 G2 G38 G44 G8 H10 H13 H17 H22 H24 H26 H31 H36 H40 H7 K10 K15 K20 K29 K33 BC28

AA16 AA20 AA22 AA28

AA4 AB12 AB34 AB38

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

PCH Grounds

16 OF 81

16 OF 118

<SCH_NUM>

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(PCH 1.05V CPU I/F PWR)

PCH V_PROC_IO BYPASS

(PCH 1.05V USB2 PWR)

PCH VCC BYPASS

Current data from LPT EDS (doc #486708, Rev 1.0).

183mA Max, 68mA Idle

??mA Max, ??mA Idle

(PCH 1.05V ME CORE PWR)

PCH VCCASW BYPASS

(PCH 1.05V PCIe/DMI/SATA/USB3 PWR)

PCH VCCIO BYPASS

PCH VCCVRM BYPASS

PCH VCCSUS3_3 BYPASS

(PCH 3.3V SPI PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

PCH VCCSPI BYPASS

(PCH 3.3V THERMAL PWR)

(PCH 1.05V DIFFCLK135 PWR)

PCH CLK VCC BYPASS (PCH 1.05V CLK PLL PWR)

PCH VCCCLK BYPASS

(PCH 1.05V DIFFCLK PWR)

PCH VCCCLK BYPASS

(PCH 1.05V SSC100 PWR)

PCH VCCCLK BYPASS

PCH VCCCLK BYPASS (PCH 1.05V SSC PWR)

(PCH 1.05V USB2 PLL PWR)

Not documented in EDS!

PCH VCC BYPASS (PCH 1.05V CORE PWR)

PCH VCCUSBPLL BYPASS

(PCH 1.05V FDI PWR)

PCH VCCIO BYPASS

(PCH 3.3V GPIO/LPC PWR)

(PCH 3.3V HVCMOS PWR)

PCH VCC3_3 BYPASS

PCH VCCCLK3_3 BYPASS (PCH 3.3V CLK PWR)

PCH VCC3_3 BYPASS

PCH VCC3_3 BYPASS (PCH 3.3V USB2 PWR)

PCH VCC3_3 BYPASS

(PCH 1.5V VCCVRM PWR)

PCH VCCSUSHDA BYPASS

PCH VCCDSW3_3 BYPASS

PCH VCCIO BYPASS

(PCH 3.3V DSW PWR)

(PCH 3.3V/1.5V HDA PWR)

670mA Max, 34mA Idle

(PCH 3.3V FUSE PWR)

(PCH 3.3V SUSPEND USB PWR)

(PCH 3.3V SUSPEND RTC PWR)

10%

1UF

402

CERM

6.3V

BYPASS=U1100.AG30:6.35mm

C1777

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AD35:6.35mm

C1778

1

2

6.3V

10%

402

CERM

1UF

BYPASS=U1100.AD34:6.35mm

C1780

1

2

6.3V

10%

402

CERM

1UF

BYPASS=U1100.AA30:6.35mm

C1782

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AM18:6.35mm

C1764

1

2

PLACE_NEAR=U1100.V20:2.54mm

6.3V

10%

402

CERM

1UF

C1752

1

2

PLACE_NEAR=U1100.V20:2.54mm

6.3V

10%

402

CERM

1UF

C1751

1

2

PLACE_NEAR=U1100.V20:2.54mm

X5R-CERM-1

603

20%

22UF

6.3V

C1750

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AE18:6.35mm

C1758

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AK20:6.35mm

C1763

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AD20:6.35mm

C1757

1

2

6.3V

20% 603

X5R

10UF

BYPASS=U1100.AG18:12.7mm

C1755

1

2

6.3V

10%

1UF

402

CERM

BYPASS=U1100.AA24:6.35mm

C1756

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AK22:6.35mm

C1762

1

2

1UF

CERM 402

10%

6.3V

BYPASS=U1100.AK18:6.35mm

C1761

1

2

10UF

X5R 603

20%

6.3V

BYPASS=U1100.AK18:12.7mm

C1760

1

2

10%

1UF

402

CERM

6.3V

BYPASS=U1100.AE30:6.35mm

C1776

1

2

1UF

10%

CERM

402

6.3V

BYPASS=U1100.U35:6.35mm

C1770

1

2

6.3V

10% 402

CERM

1UF

BYPASS=U1100.AN34:6.35mm

C1772

1

2

CERM

402

10V

20%

0.1UF

BYPASS=U1100.U30:6.35mm

C1774

1

2

BYPASS=U1100.AJ12:6.35mm

10V 402

20% CERM

0.1UF

C1787

1

2

CERM

10%

1UF

402

6.3V

BYPASS=U1100.AJ12:12.7mm

C1785

1

2

10V CERM 402

20%

0.1UF

BYPASS=U1100.AJ12:6.35mm

C1786

1

2

10%

1UF

6.3V CERM

402

BYPASS=U1100.U32:6.35mm

C1723

1

2

BYPASS=U1100.R30:6.35mm

10V

CERM

402

20%

0.1UF

C1726

1

2

16V

10%

X7R-CERM

0402

0.01UF

BYPASS=U1100.AE14:6.35mm

C1728

1

2

BYPASS=U1100.L24:6.35mm

402

10V

CERM

20%

0.1UF

C1730

1

2

BYPASS=U1100.AK30:6.35mm

CERM

402

10V

20%

0.1UF

C1732

1

2

BYPASS=U1100.P18:6.35mm

6.3V

10%

1UF

CERM

402

C1734

1

2

10V

10%

402

X5R

1UF

BYPASS=U1100.AP45:6.35mm

C1791

1

2

6.3V

20%

603

X5R

10UF

BYPASS=U1100.AP45:12.7mm

NO STUFF

C1790

1

2

0603

4.7UH-170MA-0.321OHM

CRITICAL

OMIT_TABLE

L1790

1 2

1

1/16W

5%

402

MF-LF

R1790

1 2

6.3V

20% 603

X5R

10UF

BYPASS=U1100.AF34:12.7mm

C1740

1

2

402

10%

1UF

6.3V CERM

BYPASS=U1100.M29:6.35mm

C1722

1

2

BYPASS=U1100.L29:6.35mm

10%

1UF

6.3V CERM

402

C1721

1

2

10%

1UF

6.3V CERM

402

BYPASS=U1100.L26:6.35mm

C1720

1

2

BYPASS=U1100.A16:6.35mm

402

0.1UF

CERM

20% 10V

C1700

1

2

CERM

10V 402

BYPASS=U1100.R20:6.35mm

20%

0.1UF

C1704

1

2

BYPASS=U1100.AD12:6.35mm

6.3V

10%

402

CERM

1UF

C1702

1

2

402

CERM

6.3V

1UF

10%

BYPASS=U1100.K8:6.35mm

C1708

1

2

BYPASS=U1100.R26:6.35mm

CERM

402

10V

20%

0.1UF

C1706

1

2

BYPASS=U1100.A26:6.35mm

CERM

402

10V

0.1UF

20%

C1710

1

2

PCH DECOUPLING

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

L1790

RES,FF,0 OHM,(020OHM MAX),2A,0603

1113S0022

PP3V3_SUS

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP1V5_S0

PP3V3_S5

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP3V3_SUS

PP1V05_S0

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_R

PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0

PP1V5_S0

PP1V05_S0

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_CLK_F

MIN_NECK_WIDTH=0.075 MM

17 OF 81

17 OF 118

<SCH_NUM>

11 12 13 14 15 17 50 64 65 66 69

14 15 17 18 42 62 66 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68 69 71

12 14 15 18 19 21 31 32 34 61 64 65 66 69 70 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

14 15 17 18 42 62 66 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81 11 12 13 14 15 17 50 64 65 66 69

11 12 13 14 15 17 50 64 65 66 69

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68 69 71

14 15 17 18 42 62 66 69 71

15

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

IN IN

OUT

IN

OUT

IN

OUT

IN

BI

TP

IN

OUT

G

D

S

OUT

G

D

S

NCNC

GND

VCC

NCNC

YA

G

D

SG

D

S

IN

IN IN

IN

IN IN

IN

OUT

IN

OUT

NC NC

BI IN

IN IN

IN

TP

IN

IN IN

OUT

BI IN OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Merged (CPU/PCH) Micro2-XDP

support chipset debug.

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

OBSDATA_C0

OBSFN_D0

OBSDATA_C2

OBSFN_C1

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

TCK0

TDI and TMS are terminated in CPU.

PCH/XDP Signals

(All 10 R’s)

Non-XDP Signals

PCH/XDP Signal Isolation Notes: ’Output’ non-XDP signals require pulls.

signal path needs to split between route from PCH to J1850 and path to non-XDP signal destination (to minimize stub).

Unused PCH/XDP Signals

’Output’ PCH/XDP signals require pulls.

R187x and R189x should be placed where

OBSFN_B1

OBSFN_B0

OBSDATA_A3

OBSDATA_A2

OBSDATA_A1

OBSDATA_A0

OBSDATA_B0

OBSDATA_B3

VCC_OBS_AB

Extra BPM Testpoints

CPU JTAG Isolation

SDA

TCK1

SCL

HOOK2

HOOK1

HOOK3

OBSDATA_B2

PWRGD/HOOK0

518S0847

TDO TRSTn TDI TMS

VCC_OBS_CD RESET#/HOOK6

ITPCLK#/HOOK5

OBSDATA_D3

DBR#/HOOK7

XDP_PRESENT#

OBSDATA_D2

OBSDATA_B1

OBSFN_A0 OBSFN_A1

OBSFN_C0

OBSDATA_C1

OBSDATA_C3

OBSDATA_D0 OBSDATA_D1

OBSFN_D1

ITPCLK/HOOK4

20

11

NONE NONENONE

OMIT

SHORT

201

R1897

1 2

OMIT

NONE NONENONE

SHORT

201

R1896

1 2

SHORT

NONENONE

OMIT

NONE

201

R1872

1 2

13

OMIT

NONENONE

SHORT

NONE

201

R1875

1 2

11 18

11

11 18

NONE NONE NONE

SHORT

OMIT

201

R1890

1 2

13 38

13 68 71

13

14 20

OMIT

NONENONE NONE

SHORT

201

R1893

1 2

13

OMIT

SHORT

NONENONENONE

201

R1894

1 2

13

NONENONENONE

OMIT

SHORT

201

R1879

1 2

11

11 18

14

11 18

11 34

13 65 13

14 18 14 18

OMIT

NONE NONE NONE

SHORT

201

R1895

1 2

14 35

13

14

TP-P6

TP1810

1

TP-P6

TP1811

1

TP-P6

TP1812

1

TP-P6

TP1813

1

6

18 71 74

6

18 71 74

6

71 74

PLACE_NEAR=U1100.AE2:28mm

XDP

51

MF

1/20W

2015%

R1861

2 1

PLACE_NEAR=U1100.AD3:28mm

51

XDP

MF

1/20W

2015%

R1860

2 1

PLACE_NEAR=U1100.AD1:28mm

51

XDP

MF

1/20W

2015%

R1862

2 1

PLACE_NEAR=U1100.AB3:28mm

51

XDP

MF

1/20W

2015%

R1866

2 1

SOT-563

DMN5L06VK-7

XDP

CRITICAL

PLACE_NEAR=J1800.55:28mm

Q1842

3

5

4

6

71 74

CRITICAL

DMN5L06VK-7

SOT-563

XDP

PLACE_NEAR=J1800.57:28mm

Q1842

6

2

1

330K

MF

1/20W 201

5%

R1845

1

2

SOT891

74LVC1G07GF

U1845

2

3

1

5

6

4

PLACE_NEAR=J1800.51:28mm

CRITICAL

DMN5L06VK-7

SOT-563

XDP

Q1840

3

5

4

PLACE_NEAR=J1800.53:28mm

SOT-563

DMN5L06VK-7

XDP

CRITICAL

Q1840

6

2

1

10%

0.1UF

X5R-CERM

0201

16V

C1845

1

2

19 41 58 66 71

PLACE_NEAR=U0500.M49:28mm

XDP

51

MF

1/20W

2015%

R1820

1 2

PLACE_NEAR=U0500.N54:28mm

XDP

51

MF

1/20W

2015%

R1823

2 1

6

74

6

74

6

74

6

74

6

74

6

74

6

74

6

74

6

74

1/16W MF-LF 402

150

5%

R1830

1

2

12 20 21 71

11 18 71

1K

XDP

PLACE_NEAR=U0500.AG7:2.54mm

MF

1/20W

2015%

R1805

1 2

6

74

6

74

6

74

6

19 74

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

C1806

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

C1801

1

2

M-ST-SM1

DF40RC-60DP-0.4V

XDP_CONN

CRITICAL

J1800

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

61

62

6364

78 9

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

C1800

1

2

6

71 74

6

71 74

6

74

6

74

6

74

6

71 74

6

74

6

74

6

74

TP-P6

TP1802

1

TP-P6

TP1803

1

TP-P6

TP1804

1

TP-P6

TP1805

1

TP-P6

TP1806

1

TP-P6

TP1807

1

6

74

6

74

6

74

6

74

6

74

6

74

10%

0.1UF

0201

CERM-X5R

6.3V

XDP

C1804

1

2

1/16W 402

MF-LF

XDP

1K

5%

R1831

1

2

6

74

6

74

6

74

8

13 22 44 63 68 71 76

11 18 71

XDP

1K

PLACE_NEAR=U0500.F50:2.54mm

MF

1/20W

2015%

R1800

1 2

PLACE_NEAR=U5000.J3:2.54mm

XDP

MF

1/20W

0201

0

5%

R1802

1 2

1/16W MF-LF

402

XDP

0

5%

R1804

1 2

6

14 74

12 41 76

12 19 41 71 76

6

18 71 74

PLACE_NEAR=U0500.M53:28mm

XDP

51

MF

1/20W

2015%

R1824

2 1

SHORT

NONE NONE NONE

OMIT

201

R1876

1 2

14 18 20 14 18 20

CPU & PCH XDP

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

XDP_CPU_VCCST_PWRGD XDP_CPU_PWRBTN_L

XDP_SYS_PWROK

SMBUS_PCH_DATA

XDP_CPU_TCK

PP5V_S0

CPU_PWRGD

PP1V05_S0

XDP_PCH_TMS

XDP_CPUPCH_TRST_L

XDP_CPU_TDO

XDP_CPUPCH_TRST_L

XDP_CPU_TDI

XDP_PCH_TMS

XDP_PCH_TDO

XDP_PCH_TCK

XDP_PCH_TDI

XDP_CPU_TMS

XDP_JTAG_CPU_ISOL_L

PP3V3_S5

ALL_SYS_PWRGD

XDP_CPU_PRESENT_L

CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<19>

CPU_PWR_DEBUG

PLT_RESET_L

CPU_CFG<14> CPU_CFG<15>

XDP_DBRESET_L

CPU_CFG<1>

XDP_CPU_PREQ_L

CPU_CFG<0>

XDP_BPM_L<1>

XDP_BPM_L<0>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

XDP_PCH_TCK

CPU_CFG<3>

XDP_BPM_L<2>

XDP_BPM_L<6> XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

PM_PCH_SYS_PWROK

PM_PWRBTN_L

XDP_CPU_TCK

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

AP_CLKREQ_L

XDP_FC0_HDD_PWR_EN

XDP_DA1_USB_EXTC_OC_L XDP_DB1_USB_EXTD_OC_L

XDP_FC1_GPU_GOOD

SMBUS_PCH_CLK

XDP_CPU_PRDY_L

USB_EXTA_OC_L

CAMERA_PWR_EN

SSD_PWR_EN

USB_EXTB_OC_L

SDCONN_STATE_CHANGE_L

SD_PWR_EN

DP_AUXCH_ISOL_L

XDP_DC2_ODD_PWR_EN_L JTAG_ISP_TCK SSD_PCIE_SEL_L

XDP_DA0_USB_EXTA_OC_L

XDP_DA3_CAMERA_PWR_EN

XDP_DA2_SSD_PWR_EN

XDP_DB0_USB_EXTB_OC_L XDP_DB2_SD_PWR_EN XDP_DB3_SDCONN_STATE_CHANGE_L

MAKE_BASE=TRUE

XDP_DC1_SATARDRVR_EN

XDP_DC3_JTAG_ISP_TCK

MAKE_BASE=TRUE

XDP_DC2_ODD_PWR_EN_L

XDP_DD0_SSD_PCIE_SEL_L

XDP_DD2_ENETSD_CLKREQ_L

XDP_DD1_MLB_RAMCFG1

XDP_DC1_SATARDRVR_EN

XDP_DD3_AP_CLKREQ_L

MAKE_BASE=TRUE

XDP_DD1_MLB_RAMCFG1

MAKE_BASE=TRUE

XDP_DD2_ENETSD_CLKREQ_L

XDP_DC0_DP_AUXCH_ISOL_L

PP1V05_SUS

XDP_PCH_TDI

XDP_TRST_L

XDP_PCH_TDO

XDP_CPURST_L

PPVCCIO_S0_CPU

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<16>

CPU_CFG<17>

CPU_CFG<2>

CPU_CFG<8>

CPU_CFG<11>

18 OF 118

18 OF 81

<SCH_NUM>

19 37 49 50 58 59 62 63 65 66 69 70 71

14 15 17 18 42 62 66 69 71

6

18 71 74

6

18 71 74

11 18 71

12 14 15 17 19 21 31 32 34 61 64 65 66 69 70 71 81

6

18 71 74

6

18 71 74

64 69

11 18 71

5 6 8

10 58

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN

OUT

IN

OUT

IN

OUT

NC NC

IN

OUT

S

D

G

SDG

OUT OUT

OUT

IN

Y

A

B

08

Y

A

B

08

IN

32.768K

GND

THRM

VOUT

X2 X1

25M_A 25M_B 25M_C

VIOE_25M_A VIOE_25M_B VIOE_25M_C

VG3HOT

NC

VDD

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

PCH PWROK Generation

PCH 33MHz Clocks

System RTC Power Source & 32kHz / 25MHz Clock Generator

complicates VDD_25M power, forcing at least S4. Both issues to be addressed in upcoming part

WF: Do we need this?

Coin-Cell & No G3Hot: 3.3V S5

available ~3.3V power

create VDD_RTC_OUT. +V3.3A should be first

internally ORed to

VBAT and +V3.3A are

to reduce VBAT draw.

For SB RTC Power

No Coin-Cell: 3.42V G3Hot (no RC)

least 5ms after all rails are valid.

(SLG3NB148C).

NOTE: ALL_SYS_PWRGD must remain low until at

Coin-Cell: VBAT (300-ohm & 10uF RC)

SMC controls strap enable to allow in-field control of strap setting.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

PCH ME Disable Strap

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

No Coin-Cell: 3.3V S5 No bypass necessary

NOTE: 30 PPM crystal required

IPD = 9-50k

Coin-Cell & G3Hot: 3.42V G3Hot

Camera XTAL Power TBT XTAL Power

PCH Reset Button

VDDIO_25M_A: SB power rail for XTAL circuit. VDDIO_25M_B: Camera power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

GreenClk 25MHz Power

SB XTAL Power

NOTE: SLG3NB148A provides slow rising edge on 25MHZ_B when powered from

1.2V VDDIO. Redwood Ridge also

6

18 74

5%

0

MF-LF

1/16W

402

XDP

R1996

1 2

5%

201

1/20W

MF

22

PLACE_NEAR=U1100.E44:6.35mm

R1956

1 2

5%

201

1/20W

22

PLACE_NEAR=U1100.D44:6.35mm

MF

R1955

1 2

11 76

50 71 76

41 76

11 76

5%

201

1/20W

MF

PLACE_NEAR=U1100.A40:6.35mm

22

R1959

1 2

11 76

5%

0

OMIT

1/16W MF-LF 402

SILK_PART=SYS RESET

R1997

1

2

5% 1/16W

402

4.7K

MF-LF

R1995

1

2

12 41 71 76

11 75

28 75

1UF

6.3V

10% CERM

402

C1910

1

2

X5R

10% 10V

402-1

1UF

C1902

1

2

0.1UF

20%

CERM

402

10V

C1920

1

2

20% 10V

CERM

402

0.1UF

C1922

1

2

5%

NO STUFF

1M

MF-LF

1/16W 402

R1906

1

2

402

CERM

10V

20%

0.1UF

C1924

1

2

5%

0

402

MF-LF

1/16W

R1905

1 2

12PF

5%

0402

C0G-CERM

50V

C1905

12

5%

0402

12PF

50V

C0G-CERM

C1906

1 2

41 42

5%

201

1/20W MF

1K

R1921

1

2

5%

201

1/20W MF

100K

R1920

1

2

11 76

37 75

DMN5L06VK-7

SOT-563

Q1920

3

5

4

DMN5L06VK-7

SOT-563

Q1920

6

2

1

5%

0

0201

1/20W MF

NO STUFF

R1948

2

1

12 19 71 76

5%

402

MF-LF

1/16W

1K

R1949

1 2

12 18 41 71 76 58

18 41 58 66 71

74LVC2G08GT/S505

CKPLUS_WAIVE=UNCONNECTED_PINS

PLACE_NEAR=U1100.AD7:7MM

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

U1950

5

6

4

8

3

74LVC2G08GT/S505

SOT833

U1950

1

2

4

8

7

5%

402

MF-LF

2.0K

1/16W

R1950

1

2

BYPASS=U1950:5MM

0.1UF

402

CERM

10V

20%

C1950

1

2

29 30 41 42

5%

0

0201

1/20W

MF

R1947

1

2

SLG3NB148CV

TQFN

CRITICAL

U1900

9 8 15

12

71016217

5

13

11

6

14

1

4

3

3.2X2.5MM-SM

25.000MHZ-20PPM-12PF-85C

CRITICAL

Y1905

2 4

1 3

Chipset Support

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

PM_PCH_PWROK

SYS_PWROK_R

PM_PCH_PWROK

MAKE_BASE=TRUE

PM_S0_PGOOD

CPUVR_PGOOD

PP3V3_S0

PCH_CLK33M_PCIIN

PP5V_S0

HDA_SDOUT_R

PM_SYSRST_L

LPC_CLK33M_LPCPLUS

PCH_CLK33M_PCIOUT

XDP_DBRESET_L

PP1V5_S0

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE_L

LPC_CLK33M_SMC_R

ALL_SYS_PWRGD

PM_PCH_SYS_PWROK

PP3V3_S0

LPC_CLK33M_LPCPLUS_R

PP3V42_G3H

SMC_DELAYED_PWRGD

SYSCLK_CLK32K_RTC

PPVRTC_G3H

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_SB SYSCLK_CLK25M_CAMERA SYSCLK_CLK25M_TBT

PP1V5_S0

PP3V3_TBTLC

PP3V3_S5

PP3V42_G3H

PP1V2_CAM_XTALPCIEVDD

SYSCLK_CLK25M_X1

SYSCLK_CLK25M_X2

LPC_CLK33M_SMC

<SCH_NUM>

19 OF 118

19 OF 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

18 37 49 50 58 59 62 63 65 66 69 70 71

11 12 13 15 17 19 52 64 66 68 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51

52 55 65 66 67 69 71 81

19 35 38 39 41 42 43 44 50 56 57 66 69 71

11 12 15 69

11 12 13 15 17 19 52 64 66 68 69 71

20 28 29 69

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70

71 81

19 35 38 39 41 42 43 44 50 56 57 66 69 71

36

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

OUT

G

D

S

G

D

S

OUT

IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

GND

1Y

VCC

1A

3Y 3A

2A 2Y

Y

B

A

IN

OUT

IN

G

SYM_VER_1

D

S

OUT

IN

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

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C

PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SD Card Reader is always USB3 in this implementaton.

Flexible I/O Configuration Strap

Must pull signal correctly even if always USB or PCIe

Flexible I/O Aliases

From RIO Connector

Redwood Ridge Support

RR output is open-drain, no isolation necessary

To/From PCH

TBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

U2060 supports I/O’s powered when VCC=0V

Redwood Ridge JTAG Isolation

GPIO Glitch Prevention

RAM Configuration Straps

DEVSLP not supported on LPT-H

To/From PCH

(Pull-Up on CPU Page)

Buffered

LCD HPD Inverter

Platform Reset Connections

Unbuffered

RIO SD Card Reader Support

HDMI HPD pull-down

GS3 Connector Support

(Pull-ups on PCH page)

To/From RR

Pull-up values TBD

TBT_PWR_EN must be high for JTAG Programming

18

14

14 18

14

RAMCFG0:L

1K

5%

1/20W

MF

201

R2002

1

2

1/20W MF

5%

1K

RAMCFG1:L

201

R2011

1

2

1K

5%

1/20W

MF

RAMCFG2:L

201

R2012

1

2

RAMCFG3:L

1K

5% MF

1/20W 201

R2013

1

2

DMN5L06VK-7

SOT-563

Q2040

3

5

4

DMN5L06VK-7

SOT-563

Q2040

6

2

1

10K

MF

1/20W

5%

201

R2070

1

2

35

MF

1/20W

5%

470K

201

R2040

1

2

20 28 13

12 41 50 71

10K

5%

1/20W

MF

201

R2075

1

2

14 20 28 14 20 28

14

100K

MF

1/20W

5%

201

R2030

1

2

13 20 68 71 76

13 20 68 71 76 13 20 68 71 76

13 20 68 71 76

14

28

10K

5% 1/20W MF 201

R2063

1

2

28

MF

1/20W

5%

10K

201

R2062

1

2

10K

5%

1/20W

MF

201

R2061

1

2

68 71

0201

16V

X5R-CERM

0.1UF

10%

C2060

1

2

MF

1/20W

5%

100K

201

R2010

1

2

12 68 70

SN74AUP3G07DQER

X2SON

CRITICAL

U2060

1

3

6

4

8

7

5

2

SOT665

TC7SZ08FEAPE

CRITICAL

U2030

2

1

3

5

4

402

20% 10V

CERM

0.1UF

C2080

1

2

5%

402

100K

1/16W MF-LF

R2080

1

2

CRITICAL

SC70-HF

MC74VHC1G08

U2080

3

2

1

4

5

402

1/16W MF-LF

0

5%

R2091

1 2

0

1/16W MF-LF

402

5%

R2087

1 2

MF-LF

1/16W

0

402

5%

R2088

1 2

0

MF-LF

1/16W

402

5%

R2085

1 2

6.3V

CERM-X5R

0201

0.1UF

10%

C2030

1

2

MF

1/20W

5%

470K

201

R2041

1

2

12 18 21 71

402

MF-LF

5%

1/16W

0

R2071

1 2

1/16W MF-LF

33

402

5%

R2081

1 2

33

1/16W MF-LF

402

5%

R2083

1 2

36

28

34

35

22

20 50 71 76

41

20 50 71 76

67

DFN1006H4-3

DMN32D2LFB4

Q2010

3

1

2

5

14 18

20 28

SOT833

CRITICAL

74LVC2G08GT/S505

U2000

1

5

2

6

4

8

7

3

16V 0201

X5R-CERM

0.1UF

10%

C2013

1

2

28

28 41 42 43

Project Chipset Support

SYNC_DATE=01/14/2013

SYNC_MASTER=J15_REFERENCE

TBT_PWR_EN JTAG_ISP_TCK

TBT_CIO_PLUG_EVENT_L

MAKE_BASE=TRUE

HDMI_HPD

PP3V3_TBTLC

LPCPLUS_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

TBT_PCIE_RESET_L

PP3V3_S4

CAM_PCIE_RESET_L

AP_RESET_L

SSD_RESET_L

PP3V3_S0

PLT_RESET_L

MAKE_BASE=TRUE MAKE_BASE=TRUE

LPCPLUS_RESET_L

PCA9557D_RESET_L

SMC_LRESET_L

DP_IG_A_HPD_L

LCD_HPD

SSD_DEVSLP

SD_SEL_PCIE_L_USB_H

USB3_SD_R2D_C_N

USB3_SD_D2R_N

USB3_SD_R2D_C_P

MAKE_BASE=TRUE

USB3_SD_R2D_C_N

MAKE_BASE=TRUE

USB3_SD_D2R_P USB3_SD_D2R_N

MAKE_BASE=TRUE

SMC_PME_SDCONN

MLB_RAMCFG3 MLB_RAMCFG2 XDP_DD1_MLB_RAMCFG1 MLB_RAMCFG0

TBT_PWR_EN

JTAG_TBT_TCK

TBT_PWR_EN_PCH LPC_PWRDWN_L

TBT_CIO_PLUG_EVENT_L

JTAG_TBT_TDIJTAG_ISP_TDI

JTAG_TBT_TDOJTAG_ISP_TDO

JTAG_TBT_TMS_PCH

PP3V3_S0

JTAG_TBT_TMS

USB3_SD_D2R_P

PP3V3_S0

SMC_PME_S4_DARK_L

PP3V3_S0

MAKE_BASE=TRUE

USB3_SD_R2D_C_P

SDCONN_STATE_CHANGE_L

PP3V3_S3

RIO_SDCONN_STATE_CHANGE_L

<SCH_NUM>

20 OF 118

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34 39 42 43 46 47 65 66 68 69 70 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

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49 51 52 55 65 66 67 69

71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51

52 55 65 66 67 69 71 81

13 21 22 44 46 47 65 68 69 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN IN

IN

OUT

IN

G

D

S

OUT

SDG

S

D

G

S

D

G

SDG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

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A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN CPUVDDQ_EN

CPUVDDQ_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

MEM S0 "PGOOD" for CPU

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

6 0 1 1 1 1 1 1 1

5 0 1 1 1 0 (*) 1 1 1

4 0 0 1 1 X 1 0 1

3 0 0 0 1 X 1 0 0

2 0 0 1 1 1 1 0 1

1 0 1 1 1 1 1 1 1

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

75mA max load @ 0.75V

S0

to

S3

to

60mW max power

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

S0

MEMVTT Clamp

Ensures CKE signals are held low in S3

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

14 12 41 66 71

12 18 20 71

CPUMEM:S0

1/16W

5%

MF-LF

100K

402

R2102

1

2

21 60 70

10K

MF-LF 402

1/16W

5%

CPUMEM:S0

R2110

1

2

100K

5% 1/16W MF-LF

402

CPUMEM:S0

R2115

1

2

23 24 25 26

CPUMEM:S0

402

MF-LF

1/16W

5%

1K

R2116

1

2

65

CPUMEM:S0

1/16W

10K

5% MF-LF

402

R2105

1

2

12 34 38 41 66 68 71

CPUMEM:S0

MF-LF

1/16W

402

5%

100K

R2101

1

2

21 60 70

CPUMEM:S0

5%

402

100K

1/16W MF-LF

R2151

1

2

NO STUFF

50V

0.001UF

20%

CERM

402

C2151

1

2

CPUMEM:S0

10

5%

MF-LF

603

1/10W

R2150

1

2

402

0

5% 1/16W MF-LF

CPUMEM:S3

R2117

1 2

6

21

402

43.2K

1/16W

1%

MF-LF

R2121

1

2

1%

MF-LF

1/16W

27.4K

402

R2120

1

2

SOT-563

DMB53D0UV

CRITICAL

Q2120

5

3

4

5%

10K

MF-LF

1/16W 402

R2122

1

2

CRITICAL

SOT-563

DMB53D0UV

Q2120

6

2

1

6

12 74

10V

0.047UF

10%

X5R-CERM

0402

C2120

1

2

0.1UF

CPUMEM:S0

10V CERM 402

20%

C2116

1

2

201

6.3V X5R

0.047UF

10%

NO STUFF

C2117

1

2

SOT-563

DMN5L06VK-7

CPUMEM:S0

CRITICAL

Q2100

3

5

4

DMN5L06VK-7

CPUMEM:S0

CRITICAL

SOT-563

Q2100

6

2

1

SOT-563

CRITICAL

CPUMEM:S0

DMN5L06VK-7

Q2105

6

2

1

SOT-563

CRITICAL CPUMEM:S0

DMN5L06VK-7

Q2105

3

5

4

DMN5L06VK-7

SOT-563

CRITICAL

CPUMEM:S0

Q2110

6

2

1

CRITICAL CPUMEM:S0

DMN5L06VK-7

SOT-563

Q2110

3

5

4

DMN5L06VK-7

SOT-563

CRITICAL

CPUMEM:S0

Q2115

6

2

1

DMN5L06VK-7

CRITICAL

CPUMEM:S0

SOT-563

Q2115

3

5

4

CPUMEM:S0

CRITICAL

DMN5L06VK-7

SOT-563

Q2150

3

5

4

CPUMEM:S0

CRITICAL

DMN5L06VK-7

SOT-563

Q2150

6

2

1

CPU Memory S3 Support

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

MEMPWR_DIV

CPUVDDQ_EN_L

PP3V3_S3

PM_SLP_S3_L

PP5V_S3

VTTCLAMP_EN

VTTCLAMP_L

MEMVTT_EN

MEMRESET_ISOL_LS5V_L

MEM_RESET_L

ISOLATE_CPU_MEM_L

MAKE_BASE=TRUE

CPU_MEM_RESET_L

PLT_RESET_L

MEMVTT_EN_L

MEMVTT_EN

CPUVDDQ_EN

PM_MEM_PWRGD_L

PM_MEM_PWRGD

PP3V3_S5

PM_SLP_S4_L

PP1V35_S3

CPU_MEM_RESET_L

PPVTT_S0_DDR

PP5V_S3

PP1V35_S3RS0_CPUDDR

<SCH_NUM>

21 OF 118

21 OF 81

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21 37 60 65 66 69 71

22

12 14 15 17 18 19 31 32 34 61 64 65 66 69 70 71 81

22 46 60 65 69 71

27 60 69 71

21 37 60 65 66 69 71

6 8

10 65 66 69 81

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

OUT

V-

V+

V-

V+

IN

G

D

SG

D

SG

D

S G

D

S

IN

G

D

SG

D

SG

D

SG

D

S

IN

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

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C

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

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SHEET

R

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REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

a DAC output, cannot enable

R22x6 pin 2:

CPU-Based Margining

VRef current: DAC step size:

Page Notes

Pins B1 & B4:

both at the same time!

Addr=0x98(WR)/0x99(RD)

(OD)

DDR3L (1.35V) 6.99mV per step

DDR3 (1.5V) 7.70mV per step

signals for independent DAC

to remove short due to CPU.

- =PP3V3_S3_VREFMRGN

NOTE: MEMVREG and FRAMEBUF share

FETs for CPU isolation during S3

DAC sets voltage level, PCA9557 & FETs enable outputs

(All 4 R’s)

EN RC’s to avoid drain glitches

BOM options provided by this page:

- =I2C_VREFDACS_SCL

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

- =I2C_VREFDACS_SDA

Signal aliases required by this page:

Power aliases required by this page:

Always used, regardless

VRef Dividers

of margining option.

Q2265 pin 6:

watchdog will disable margining.

soft-resets and sleep/wake cycles.

VREFCA. Split into two

margining support. When DAC margining VREFCA ensure ISOLATE_CPU_MEM_L is low

DAC-Based Margining

and disables margining after platform reset.

NOTE: Margining will be disabled across all

RST* on ’platform reset’ so that system

Addr=0x30(WR)/0x31(RD)

Margined target:

Nominal value

DAC Channel: PCA9557D Pin:

1

A

DDR3 (1.5V)

B 2

C 3

DDR3L (1.35V)

C 4

DDR3L (1.35V)

DAC range: Margined range:

+901uA - -911uA (- = sourced)

0.000V - 1.508V (0x00 - 0x75)

7.68mV / step @ output 7.67mV / step @ output

+811uA - -816uA (- = sourced)

0.269V - 1.083V (+/- 406mV)

0.000V - 1.354V (0x00 - 0x69)

0.300V - 1.200V (+/- 450mV)

0.750V (DAC: 0x3A = 0.747mV)

DDR3 (1.5V)

MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA

MEM VREG

D 5

0.000V - 2.707V (0x00 - 0xD2)

0.675V (DAC: 0x34 = 0.670mV)

0.275V - 1.075V (+/- 400mV)

0.299V - 1.206V (+/- 453mV)

0.000V - 3.004V (0x00 - 0xE9)

- =PPDDR_S3_MEMVREF

- DDRVREF_DAC - Stuffs DAC margining circuit.

DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

1.500V (DAC: 0x74 = 1.495V) 1.343V (DAC: 0x68 = 1.341V)

0.932V - 1.760V (+/- 414mV)

0.950V - 1.750V (+/- 400mV)

+28uA - -29uA (- = sourced)

3.923mV / step @ output

NOTE: CPU DAC output step sizes:

1.200V - 1.800V (+/- 300mV)

1.199V - 1.801V (+/- 301mV) +36uA - -36uA (- = sourced)

2.575mV / step @ output

NOTE: DDR3 assumes TPS51916 supply with 10.0k/49.9k divider

NOTE: CPU has single output for

Q2225 pin 6:

60

10%

0.1UF

0201

CERM-X5R

6.3V

DDRVREF_DAC

C2202

1

2

DDRVREF_DAC

402

MF-LF

1/16W

33.2K

1%

R2214

1 2

201

5%

100K

1/20W

MF

DDRVREF_DAC

R2213

1

2

201

5%

100K

1/20W

MF

DDRVREF_DAC

R2215

1

2

CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

MAX4253

UCSP

CRITICAL DDRVREF_DAC

U2204

A3

A2

A1

A4

B1

B4

UCSP

DDRVREF_DAC

CRITICAL

MAX4253

U2204

C3

C2

C1

C4

B1

B4

SHORT

402

NONE NONE

NONE

OMIT

R2218

1 2

7

74

7

74

21

SOT-563

CRITICAL

DMN5L06VK-7

Q2260

6

2

1

201

5%

1/20W

DDRVREF_DAC

100K

MF

R2202

1

2

SOT-563

CRITICAL

DMN5L06VK-7

Q2220

3

5

4

SOT-563

CRITICAL

DMN5L06VK-7

Q2260

3

5

4

SOT-563

DMN5L06VK-7

CRITICAL

Q2220

6

2

1

7

CRITICAL

DMN5L06VK-7

DDRVREF_DAC

SOT-563

PLACE_NEAR=Q2220.6:2.54mm

Q2225

6

2

1

201

DDRVREF_DAC

100K

5%

1/20W

MF

R2201

1

2

1/16W MF-LF

5%

402

100K

DDRVREF_DAC

R2225

1 2

0.1UF

DDRVREF_DAC

20% 10V

CERM

402

C2225

1

2

PLACE_NEAR=Q2260.6:2.54mm

SOT-563

DDRVREF_DAC

CRITICAL

DMN5L06VK-7

Q2265

6

2

1

0.1UF

402

CERM

10V

20%

DDRVREF_DAC

C2245

1

2

DDRVREF_DAC

1/16W MF-LF

5%

402

100K

R2245

1 2

1/16W MF-LF

5%

402

DDRVREF_DAC

100K

R2265

1 2

SOT-563

DDRVREF_DAC

CRITICAL

DMN5L06VK-7

Q2225

3

5

4

0.1UF

20% 10V

CERM

402

DDRVREF_DAC

C2265

1

2

SOT-563

DDRVREF_DAC

CRITICAL

DMN5L06VK-7

Q2265

3

5

4

0.1UF

402

CERM

10V

20%

DDRVREF_DAC

C2285

1

2

201

100K

5%

1/20W

MF

DDRVREF_DAC

R2207

1

2

1/16W MF-LF

402

DDRVREF_DAC

5%

100K

R2285

1 2

201

100K

5%

1/20W

MF

DDRVREF_DAC

R2208

1

2

PLACE_NEAR=Q2225.1:2.54mm

MF-LF

402

1/16W

DDRVREF_DAC

332

1%

R2226

1 2

PLACE_NEAR=Q2225.4:2.54mm

MF-LF

402

1/16W

DDRVREF_DAC

332

1%

R2246

1 2

PLACE_NEAR=Q2265.1:2.54mm

MF-LF

402

1/16W

DDRVREF_DAC

332

1%

R2266

1 2

PLACE_NEAR=Q2265.4:2.54mm

MF-LF

402

1/16W

DDRVREF_DAC

332

1%

R2286

1 2

5% 1/16W MF-LF 402

DDRVREF_DAC

1M

R2217

1

2

0.022UF

6.3V

10% X5R-CERM

0201

PLACE_NEAR=Q2260.3:2mm

C2280

1

2

0.022UF

PLACE_NEAR=Q2220.3:2mm

6.3V

10% X5R-CERM

0201

C2260

1

2

0.022UF

PLACE_NEAR=Q2260.6:2mm

6.3V

10% X5R-CERM

0201

C2240

1

2

201

PLACE_NEAR=C2280.1:2mm

5%

2

1/20W

MF

R2283

1 2

201

MF

1%

24.9

1/20W

R2280

1 2

PLACE_NEAR=R2281.2:1mm

1% 1/16W MF-LF

402

1K

R2282

1

2

201

PLACE_NEAR=C2260.1:2mm

1/20W

MF

5%

2

R2263

1 2

201

MF

1/20W

1%

24.9

R2260

1 2

PLACE_NEAR=R2283.2:1mm

1K

1%

402

1/16W MF-LF

R2281

1

2

1% 1/16W

402

MF-LF

1K

PLACE_NEAR=R2261.2:1mm

R2262

1

2

201

MF

1/20W

1%

24.9

R2240

1 2

PLACE_NEAR=R2263.2:1mm

402

1/16W MF-LF

1K

1%

R2261

1

2

1K

402

MF-LF

1% 1/16W

PLACE_NEAR=R2241.2:1mm

R2242

1

2

0.022UF

PLACE_NEAR=Q2220.6:2mm

6.3V

10% X5R-CERM

0201

C2220

1

2

201

5%

2

1/20W

MF

PLACE_NEAR=C2240.1:2mm

R2243

1 2

201

PLACE_NEAR=C2220.1:2mm

2

5%

1/20W

MF

R2223

1 2

201

MF

1/20W

1%

24.9

R2220

1 2

PLACE_NEAR=R2243.2:1mm

402

1/16W MF-LF

1K

1%

R2241

1

2

1K

1% 1/16W

402

MF-LF

PLACE_NEAR=R2221.2:1mm

R2222

1

2

PLACE_NEAR=R2223.2:1mm

1K

1%

402

1/16W MF-LF

R2221

1

2

20

QFN

PCA9557

DDRVREF_DAC

CRITICAL

U2201

3 4 5

8

6 7 9 10 11 12 13 14

15

1 2

17

16

13 18 22 44 63 68 71 76

CRITICAL DDRVREF_DAC

DAC5574

MSOP

U2200

9

10

3

6

7

8

1

2

4

5

13 18 22 44 63 68 71 76

10%

0.1UF

0201

CERM-X5R

6.3V

DDRVREF_DAC

C2201

1

2

6.3V

20%

CERM

402-LF

2.2UF

DDRVREF_DAC

C2200

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

DDRVREF_DAC

C2205

1

2

SYNC_DATE=10/31/2012

DDR3 VREF MARGINING

SYNC_MASTER=J15_MLB

CPU_MEM_VREFCA_B_ISOL

VREFMRGN_DQ_A_RDIV

VREFMRGN_CA_B_EN_RC

CPU_MEM_VREFDQ_B_ISOL

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

CPU_MEM_VREFDQ_A_ISOL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

VREFMRGN_MEMVREG_BUF

VREFMRGN_MEMVREG_EN

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_DQ_A_EN

VREFMRGN_CA_AB

VREFMRGN_DQ_B

PCA9557D_RESET_L

VREFMRGN_DQ_B_RDIV

PP1V35_S3

MEM_VREFDQ_A_RC

MEM_VREFDQ_B_RC

CPU_MEM_VREFCA_A_ISOL

MEM_VREFCA_A_RC

MEM_VREFCA_B_RC

VREFMRGN_CA_B_EN

VREFMRGN_DQ_A_EN_RC

VREFMRGN_DQ_B_EN

VREFMRGN_DQ_B_EN_RC

VREFMRGN_CA_A_EN_RC

VREFMRGN_FRAMEBUF_BUF

DDRREG_FB

PP3V3_S3

VREFMRGN_CA_B_RDIV

VREFMRGN_CA_A_RDIV

VREFMRGN_DQ_A

CPU_DIMMA_VREFDQ

MEMRESET_ISOL_LS5V_L

CPU_DIMM_VREFCA

CPU_DIMMB_VREFDQ

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK

VREFMRGN_FRAMEBUF_EN

VREFMRGN_CA_A_EN

PP3V3_S3

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S3_VREFMRGN

MIN_LINE_WIDTH=0.3 mm

22 OF 81

22 OF 118

<SCH_NUM>

25 26 70 74

23 24 70 74 77

21 46 60 65 69 71

13 20 21 22 44 46 47 65 68 69 71

23 24 70 74 77

25 26 70 74

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

X5R-CERM

2.2UF

402

10V

20%

C2340

1

2

X5R-CERM

2.2UF

402

10V

20%

C2341

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2343

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2344

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2345

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2353

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2354

1

2

0.1UF

10%

6.3V CERM-X5R 0201

C2355

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2363

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2364

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2365

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2373

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2374

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2375

1

2

201

240

1% 1/20W MF

R2300

2

1

201

1/20W

1%

240

MF

R2310

2

1

201

240

1% 1/20W MF

R2320

2

1

201

MF

1/20W

240

1%

R2330

2

1

201

0.47UF

20%

4V

CERM-X5R-1

C2307

1

2

10%

201

X5R

6.3V

0.047UF

C2309

1

2

10%

201

X5R

6.3V

0.047UF

C2308

1

2

10%

201

X5R

6.3V

0.047UF

C2319

1

2

10%

201

X5R

6.3V

0.047UF

C2318

1

2

201

CERM-X5R-1

4V

20%

0.47UF

C2317

1

2

10%

201

X5R

6.3V

0.047UF

C2329

1

2

10%

201

X5R

6.3V

0.047UF

C2328

1

2

201

0.47UF

4V

20%

CERM-X5R-1

C2327

1

2

10%

201

X5R

6.3V

0.047UF

C2339

1

2

10%

201

X5R

6.3V

0.047UF

C2338

1

2

201

0.47UF

CERM-X5R-1

4V

20%

C2337

1

2

10%

201

X5R

6.3V

0.047UF

C2379

1

2

10%

201

X5R

6.3V

0.047UF

C2378

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2377

1

2

10%

201

X5R

6.3V

0.047UF

C2369

1

2

10%

201

X5R

6.3V

0.047UF

C2368

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2367

1

2

10%

201

X5R

6.3V

0.047UF

C2359

1

2

10%

201

X5R

6.3V

0.047UF

C2358

1

2

201

240

1% 1/20W MF

R2370

2

1

201

MF

1/20W

1%

240

R2360

2

1

201

20%

4V

CERM-X5R-1

0.47UF

C2357

1

2

10%

201

X5R

6.3V

0.047UF

C2349

1

2

10%

201

X5R

6.3V

0.047UF

C2348

1

2

201

0.47UF

20%

4V

CERM-X5R-1

C2347

1

2

201

240

1% 1/20W MF

R2350

2

1

201

MF

1/20W

1%

240

R2340

2

1

10%

0.1UF

0201

CERM-X5R

6.3V

C2335

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2334

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2333

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2325

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2324

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2323

1

2

CERM-X5R 0201

10%

0.1UF

6.3V

C2315

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2314

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2313

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2305

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2304

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2303

1

2

X5R-CERM

2.2UF

402

10V

20%

C2301

1

2

X5R-CERM

2.2UF

20% 10V

402

C2300

1

2

20% 10V

402

2.2UF

X5R-CERM

C2311

1

2

20% 10V

402

2.2UF

X5R-CERM

C2351

1

2

X5R-CERM

402

10V

20%

2.2UF

C2310

1

2

20% 10V

402

2.2UF

X5R-CERM

C2350

1

2

20% 10V

402

2.2UF

X5R-CERM

C2321

1

2

20% 10V

402

X5R-CERM

2.2UF

C2361

1

2

402

10V

20%

2.2UF

X5R-CERM

C2320

1

2

10V 402

2.2UF

X5R-CERM

20%

C2360

1

2

20% 10V

402

2.2UF

X5R-CERM

C2331

1

2

402

10V

20%

2.2UF

X5R-CERM

C2330

1

2

20% 10V

402

X5R-CERM

2.2UF

C2371

1

2

X5R-CERM

402

20% 10V

2.2UF

C2370

1

2

DDR3-1333

OMIT_TABLE

FBGA

U2300

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

DDR3-1333

FBGA

U2310

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

DDR3-1333

FBGA

U2320

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2330

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

DDR3-1333

FBGA

U2340

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

DDR3-1333

FBGA

U2350

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

OMIT_TABLE

FBGA

U2360

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

FBGA

DDR3-1333

OMIT_TABLE

U2370

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

DDR3 SDRAM Bank A (1 OF 2)

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

PP1V35_S3_MEM

MEM_A_ZQ<5>

MEM_A_A<4>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<6>

MEM_A_A<11>

MEM_A_DQS_N<5>

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<50> MEM_A_DQ<51>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<7>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<62>

MEM_A_DQS_N<7>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<7>

MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_A<2>

MEM_A_A<0>

MEM_A_DQS_P<6>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<6>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<54>

MEM_A_DQS_N<6>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQ<55>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_A<2>

PP1V35_S3_MEM

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<46>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<5>

MEM_A_DQ<47>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_A<2>

MEM_A_DQ<32>

MEM_A_CAS_L

MEM_A_DQ<37>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<4>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<38>

MEM_A_DQS_N<4>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<4>

MEM_A_DQ<39>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_A<2>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_RAS_L

MEM_A_ZQ<3>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<26>

MEM_A_DQS_N<3>

MEM_A_CS_L<0>

MEM_A_DQS_P<3>

MEM_A_DQ<29>

MEM_A_DQ<25>

MEM_A_DQ<30>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<24>

MEM_A_DQ<31>

MEM_A_A<2>

MEM_A_A<3>

PP1V35_S3_MEM

MEM_A_A<2>

MEM_A_A<4>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<2>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6> MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<20>

MEM_A_DQS_N<2>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<2>

MEM_A_DQ<19>

MEM_A_DQ<23>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_A<7>

PP1V35_S3_MEM

MEM_A_DQ<14>

MEM_A_CLK_P<0>

MEM_A_A<1>

MEM_A_DQ<9>

MEM_A_A<0>

MEM_A_DQ<7>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>

MEM_A_RAS_L

MEM_A_ZQ<1>

MEM_A_WE_L MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<5>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<8>

MEM_A_DQS_N<1>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_DQS_P<1>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<11>

MEM_A_DQ<15>

MEM_A_DQ<10>

MEM_A_A<2>

MEM_A_A<7>

PP1V35_S3_MEM

MEM_A_DQS_P<0>

MEM_A_CKE<0>

MEM_A_DQS_N<0>

MEM_A_A<11> MEM_A_A<12>

MEM_A_A<2>

MEM_A_DQ<0>

MEM_A_DQ<5> MEM_A_DQ<3> MEM_A_DQ<1>

MEM_A_DQ<4>

MEM_A_CS_L<0>

MEM_A_DQ<2>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<3> MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<0> MEM_A_A<1>

MEM_A_A<5> MEM_A_A<6>

MEM_A_A<8> MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<0>

MEM_A_RAS_L

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

<SCH_NUM>

23 OF 118

23 OF 81

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7

23 24

27 77

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7

23

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77

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77

7

24 77

22 23 24 70 74 77

7

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7

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22 23 24 70 74 77

7

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77

7

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77

7

23

24 27 77

7

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7

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22 23 24 70 74 77

23 24 25 26 46 69 77

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w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

DDR3-1333

OMIT_TABLE

FBGA

U2440

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2450

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2460

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2470

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

201

1/20W MF

1%

240

R2400

2

1

201

240

1% 1/20W MF

R2410

2

1

201

1/20W

240

MF

1%

R2420

2

1

201

240

1% 1/20W MF

R2430

2

1

201

0.47UF

20%

4V

CERM-X5R-1

C2407

1

2

10%

201

X5R

6.3V

0.047UF

C2409

1

2

10%

201

X5R

6.3V

0.047UF

C2408

1

2

10%

201

X5R

6.3V

0.047UF

C2419

1

2

10%

201

X5R

6.3V

0.047UF

C2418

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2417

1

2

10%

201

X5R

6.3V

0.047UF

C2429

1

2

10%

201

X5R

6.3V

0.047UF

C2428

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2427

1

2

10%

201

X5R

6.3V

0.047UF

C2439

1

2

10%

201

X5R

6.3V

0.047UF

C2438

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2437

1

2

10%

201

X5R

6.3V

0.047UF

C2479

1

2

10%

201

X5R

6.3V

0.047UF

C2478

1

2

201

0.47UF

CERM-X5R-1

4V

20%

C2477

1

2

10%

201

X5R

6.3V

0.047UF

C2469

1

2

10%

201

X5R

6.3V

0.047UF

C2468

1

2

201

4V

20%

0.47UF

CERM-X5R-1

C2467

1

2

10%

201

X5R

6.3V

0.047UF

C2459

1

2

10%

201

X5R

6.3V

0.047UF

C2458

1

2

201

MF

1/20W

1%

240

R2470

2

1

201

240

1% 1/20W MF

R2460

2

1

201

CERM-X5R-1

0.47UF

4V

20%

C2457

1

2

10%

201

X5R

6.3V

0.047UF

C2449

1

2

10%

201

X5R

6.3V

0.047UF

C2448

1

2

201

0.47UF

CERM-X5R-1

4V

20%

C2447

1

2

201

MF

1/20W

1%

240

R2450

2

1

201

240

1% 1/20W MF

R2440

2

1

10V

X5R-CERM

2.2UF

402

20%

C2440

1

2

X5R-CERM

2.2UF

20% 10V

402

C2400

1

2

X5R-CERM

2.2UF

402

10V

20%

C2441

1

2

X5R-CERM

2.2UF

402

10V

20%

C2401

1

2

X5R-CERM

20% 10V

402

2.2UF

C2450

1

2

402

10V

20%

2.2UF

X5R-CERM

C2410

1

2

2.2UF

20% 10V

402

X5R-CERM

C2451

1

2

20% 10V

402

2.2UF

X5R-CERM

C2411

1

2

20% 10V

402

2.2UF

X5R-CERM

C2460

1

2

20% 10V

402

2.2UF

X5R-CERM

C2461

1

2

402

10V

20%

2.2UF

X5R-CERM

C2420

1

2

20% 10V

402

2.2UF

X5R-CERM

C2421

1

2

20% 10V

402

X5R-CERM

2.2UF

C2470

1

2

20% 10V

402

2.2UF

X5R-CERM

C2471

1

2

402

10V

20%

2.2UF

X5R-CERM

C2430

1

2

20% 10V

402

2.2UF

X5R-CERM

C2431

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2443

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2444

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2403

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2404

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2445

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2453

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2405

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2413

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2454

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2414

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2455

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2463

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2415

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2423

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2464

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2465

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2424

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2425

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2473

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2433

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2474

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2434

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2475

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2435

1

2

OMIT_TABLE

FBGA

DDR3-1333

U2400

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

FBGA

DDR3-1333

U2410

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2420

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

OMIT_TABLE

DDR3-1333

FBGA

U2430

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

DDR3 SDRAM Bank A (2 OF 2)

MEM_A_A<10>

MEM_A_A<14>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<5>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<15>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<15>

MEM_A_DQ<61>

MEM_A_DQS_N<7>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<7>

MEM_A_DQ<60>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_A<2>

MEM_A_DQ<43>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_DQS_N<5>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<14>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<6>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<13>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<53>

MEM_A_DQS_N<6>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<6>

MEM_A_DQ<52>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_A<2>

MEM_A_CLK_N<1>

MEM_A_DQS_N<4>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_ODT<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1> MEM_A_RAS_L MEM_A_CAS_L

MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<45>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<5>

MEM_A_DQ<44>

MEM_A_DQ<47>

MEM_A_DQ<42>

MEM_A_DQ<40>

MEM_A_A<2>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<12>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<4>

MEM_A_DQ<36>

MEM_A_DQ<39>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_A<2>

MEM_A_WE_L

MEM_A_A<0>

MEM_A_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<11>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14> MEM_A_A<15>

MEM_A_DQ<25>

MEM_A_DQS_N<3>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<3>

MEM_A_DQ<30>

MEM_A_DQ<26>

MEM_A_DQ<29>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<31>

MEM_A_DQ<24>

MEM_A_A<2>MEM_A_A<2>

MEM_A_A<6>

MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18> MEM_A_DQS_P<2>

MEM_A_CS_L<1> MEM_A_CKE<1>

MEM_A_DQS_N<2>

MEM_A_DQ<23>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_BA<2>

MEM_A_A<4> MEM_A_A<3>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<1>

MEM_A_A<8>

MEM_A_A<5>

MEM_A_A<7> MEM_A_A<9>

MEM_RESET_L

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_WE_L

MEM_A_ZQ<10>

MEM_A_RAS_L

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<10>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<13>

PP1V35_S3_MEM

MEM_A_CS_L<1>

MEM_A_CLK_N<1>

MEM_A_A<15>

MEM_A_DQS_N<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1> MEM_A_RAS_L

MEM_A_ZQ<9>

MEM_A_WE_L MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_DQS_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_DQS_P<1>

MEM_A_DQ<11>

MEM_A_DQ<8>

MEM_A_DQ<12>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<9>

MEM_A_A<2>

PP1V35_S3_MEM

MEM_A_A<15>

MEM_A_A<13>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_P<1>

MEM_A_RAS_L

MEM_A_ZQ<8>

MEM_A_ODT<1>

MEM_A_CAS_L

MEM_A_BA<1> MEM_A_BA<0>

MEM_RESET_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<0>

MEM_A_A<11> MEM_A_A<12>

MEM_A_A<10>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<14>

MEM_A_DQ<1>

MEM_A_CKE<1>

MEM_A_DQS_P<0>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<0>

MEM_A_DQ<6>

MEM_A_A<2>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<41>

MEM_A_A<4>

MEM_A_A<1>

MEM_A_A<8> MEM_A_A<7>

MEM_A_DQ<46>

MEM_A_BA<0>

MEM_A_WE_L

MEM_A_ZQ<13>

PP1V35_S3_MEM

<SCH_NUM>

24 OF 118

24 OF 81

7

23 24

27 77

7

23 24 27 77

22 23 24 70 74 77

7

23 24

27 77

22 23 24 70 74 77

7

24 27

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7

24 27

77

7

23

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7

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7

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23 24

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21 23 24 25 26

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7

23 24

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7

23 24

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23 24

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7

23 24

27 77

7

23 24 27

77

22 23 24 70 74 77

23 24 25 26 46 69 77

7

23 24 27 77

7

23

24 27 77

7

23

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7

23 24 27 77

7

23 24

27 77

7

23 24

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7

23

24 27 77

7

23 24 27 77

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23 77

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7

24 27

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7

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23 77

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23 77

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7

23 77

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23 77

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7

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7

23

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23 24

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7 23 77

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23 24

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23 24

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22 23 24 70 74 77

23 24 25 26 46 69 77

7

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21 23 24

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23

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23 24 27 77

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23 24 27 77

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23

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23 24 27 77

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23 24 27 77

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23 24 27 77

22 23 24 70 74 77

7 24 27 77

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23 24

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23 24

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23 24

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22 23 24 70 74 77

23 24 25 26 46 69 77

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23 24 27

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22 23 24 70 74 77

23 24 25 26 46 69 77

7

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23 24 25 26 46 69 77

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23

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22 23 24 70 74 77 22 23 24 70 74 77

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23 24 25 26 46 69 77

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7

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7

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23 24 27 77

7

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23 24 27 77

7

23 24

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23 24

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23 24

27 77

7

23 24

27 77 7

23 24

27 77

7

23 24

27 77

7

23 24 27

77

7

23 24 27 77

7

23

24 27

77

7

23 24 27 77

7

23 24 27 77

7

23 24

27 77

7

23 24

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7

23

24 27 77

7

23 24 27 77

7

23

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7

23 24 27 77

23 24 25 26 46 69 77

7

23 24

27 77

7

23 24

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22 23 24 70 74 77

7 24 27

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7

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7

24 27

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23 24

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23 24

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7

23 24

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7

23 24

27 77 7

23 24

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7

23 24

27 77

7

23 24

27 77

7

23 24

27 77

7

23 24

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7

23 24

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7 23 77

7

23 24

27 77

22 23 24 70 74 77 22 23 24 70 74 77

7

23 24 27 77

7

23 24

27 77

7

23 24 27 77

23 24 25 26 46 69 77

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

NC NC

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

OMIT_TABLE

DDR3-1333

FBGA

U2550

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2560

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2570

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

201

MF

1/20W

1%

240

R2500

2

1

201

240

1% 1/20W MF

R2510

2

1

201

MF

1/20W

240

1%

R2520

2

1

201

MF

240

1% 1/20W

R2530

2

1

201

CERM-X5R-1

20%

4V

0.47UF

C2507

1

2

10%

201

X5R

6.3V

0.047UF

C2509

1

2

10%

201

X5R

6.3V

0.047UF

C2508

1

2

10%

201

X5R

6.3V

0.047UF

C2519

1

2

10%

201

X5R

6.3V

0.047UF

C2518

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2517

1

2

10%

201

X5R

6.3V

0.047UF

C2529

1

2

10%

201

X5R

6.3V

0.047UF

C2528

1

2

201

0.47UF

20%

4V

CERM-X5R-1

C2527

1

2

10%

201

X5R

6.3V

0.047UF

C2539

1

2

10%

201

X5R

6.3V

0.047UF

C2538

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2537

1

2

10%

201

X5R

6.3V

0.047UF

C2579

1

2

10%

201

X5R

6.3V

0.047UF

C2578

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2577

1

2

10%

201

X5R

6.3V

0.047UF

C2569

1

2

10%

201

X5R

6.3V

0.047UF

C2568

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2567

1

2

10%

201

X5R

6.3V

0.047UF

C2559

1

2

10%

201

X5R

6.3V

0.047UF

C2558

1

2

201

240

1% 1/20W MF

R2570

2

1

201

MF

240

1/20W

1%

R2560

2

1

201

CERM-X5R-1

20%

4V

0.47UF

C2557

1

2

10%

201

X5R

6.3V

0.047UF

C2549

1

2

10%

201

X5R

6.3V

0.047UF

C2548

1

2

201

CERM-X5R-1

0.47UF

4V

20%

C2547

1

2

201

240

1% 1/20W MF

R2550

2

1

201

MF

1/20W

1%

240

R2540

2

1

X5R-CERM

2.2UF

402

10V

20%

C2540

1

2

2.2UF

X5R-CERM

20% 10V

402

C2500

1

2

X5R-CERM

2.2UF

402

10V

20%

C2541

1

2

20% 10V

402

2.2UF

X5R-CERM

C2550

1

2

X5R-CERM

2.2UF

402

10V

20%

C2501

1

2

402

10V

20%

2.2UF

X5R-CERM

C2510

1

2

20% 10V

402

2.2UF

X5R-CERM

C2551

1

2

20% 10V

402

2.2UF

X5R-CERM

C2511

1

2

20% 10V

402

2.2UF

X5R-CERM

C2560

1

2

20% 10V

402

2.2UF

X5R-CERM

C2561

1

2

402

10V

20%

2.2UF

X5R-CERM

C2520

1

2

20% 10V

402

2.2UF

X5R-CERM

C2521

1

2

20% 10V

402

2.2UF

X5R-CERM

C2570

1

2

20% 10V

402

X5R-CERM

2.2UF

C2571

1

2

402

20%

X5R-CERM

10V

2.2UF

C2530

1

2

20% 10V

402

2.2UF

X5R-CERM

C2531

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2543

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2544

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2503

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2504

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2545

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2553

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2505

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2513

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2554

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2514

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2555

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2563

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2515

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2523

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2564

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2565

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2524

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2525

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2573

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2533

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2534

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2574

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2575

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2535

1

2

DDR3-1333

FBGA

OMIT_TABLE

U2500

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2510

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2520

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2530

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2540

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

DDR3 SDRAM Bank B (1 OF 2)

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_ZQ<6>

MEM_B_ZQ<2>

MEM_B_A<2>

MEM_B_A<6>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<7>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<62>

MEM_B_DQS_N<7>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<7>

MEM_B_DQ<63>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_A<2>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<54>

MEM_B_DQS_N<6>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<5>

MEM_B_DQ<32>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0> MEM_B_RAS_L

MEM_B_ZQ<5>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<46>

MEM_B_DQS_N<5>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_A<2>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<4>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<38>

MEM_B_DQS_N<4>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<4>

MEM_B_DQ<39>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_A<2>

MEM_B_WE_L MEM_B_WE_L

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_ODT<0>

MEM_B_WE_L

MEM_B_DQ<19>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<3>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<31>

MEM_B_DQS_N<3>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<3>

MEM_B_DQ<24>

MEM_B_DQ<28>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<27>

MEM_B_A<2>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_DQ<20>

MEM_B_DQ<17>

MEM_B_A<5>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<6>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<22>

MEM_B_DQS_N<2>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<2>

MEM_B_DQ<21>

MEM_B_DQ<23>

MEM_B_DQ<16>

MEM_B_DQ<18>

MEM_B_A<2>

MEM_B_DQ<11>

MEM_B_DQ<3>

MEM_B_A<12>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0> MEM_B_RAS_L

MEM_B_ZQ<1>

MEM_B_WE_L MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<15>

MEM_B_DQS_N<1>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<1>

MEM_B_DQ<8>

MEM_B_DQ<12>

MEM_B_DQ<10>

MEM_B_DQ<13>

MEM_B_DQ<9>

MEM_B_DQ<14>

MEM_B_A<2>

PP1V35_S3_MEM

MEM_B_DQ<2> MEM_B_DQ<4>

MEM_B_DQ<0>

MEM_B_CKE<0>

MEM_B_DQ<5>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<0>

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6> MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<7>

MEM_B_DQS_N<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<0>

MEM_B_DQ<1>

MEM_B_DQ<6>

MEM_B_A<2>

PP1V35_S3_MEM

<SCH_NUM>

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25 26

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25 26 27 77

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22 25 26 70 74

7

25 27

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25

26 27 77

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23 24 25 26 46 69 77

7

25 26 27 77

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25

26 27

77

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7

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25

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23 24 25 26 46 69 77

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77

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26 77

22 25 26 70 74

7

25 27

77

7

25 27

77

7

25 26 27 77

7

25 26

27 77 7

25 26

27 77

21 23 24 25 26

7

25 26

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7

25 26

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7

25 26

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25 26

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7

25 26 27

77

22 25 26 70 74

23 24 25 26 46 69 77

7

25 26 27 77

7

25

26 27

77

7

25

26 27 77

7

25 26 27 77

7

25 26 27 77

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25 26

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7

25 26

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7

25 26 27 77

7

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7

26 77

7

26 77

7

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77

7

25 27

77

7

26 77

7

26 77

7

26 77

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7

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26 77

7

25 26 27 77

7

25 26

27 77

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25 26

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7

25 26

27 77

22 25 26 70 74

7

25

26 27 77

7

25 27 77

7

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7

25 26

27 77 7

25 26

27 77

7

25 26

27 77

7

25 26

27 77

7

25 26 27

77

22 25 26 70 74

23 24 25 26 46 69 77

7

25 26 27 77

7

25

26 27

77

7

25

26 27 77

7

25 26 27 77

7

25 26 27 77

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25 26

27 77

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25 26

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25

26 27 77

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25 26 27 77

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25 26 27 77

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25 26 27 77

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26 77

7

25

26 27

77

22 25 26 70 74

7

25 27 77

7

25

27

77

7

25

26 27 77

7

25 26 27 77

7

25 27 77

7

25 26 27 77

7

25 26

27 77 7

25 26

27 77

7

25 26

27 77

7

25 26

27 77

7

25 26

27 77 7

25 26

27 77

7

25 26 27

77

22 25 26 70 74

23 24 25 26 46 69 77

7

25 26 27 77

7

25 26

27 77

7

25 26 27 77

7

25 26

27 77

7

25 26

27 77

7

25 26

27 77

7

25

26 27 77

7

25 26 27 77

7

25 26 27 77

7

25 26 27 77

23 24 25 26 46 69 77

22 25 26 70 74

7

25 27 77

7

25

27

77

7

25 26

27 77

7

25 27

77

7

25 26

27 77

7

25 26

27 77 7

25 26

27 77

7

25 26

27 77

7

25 26

27 77

7

25 26

27 77 7

25 26

27 77

7

25 26

27 77

7

25 26

27 77

22 25 26 70 74

7

25 26

27 77

7

25 26

27 77 7

25 26

27 77 7

25 26

27 77

7

25 26

27 77

7

25 26

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25 26

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7

25 26

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23 24 25 26 46 69 77

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

NC NC

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC NC

NC

NC NC NC

NC

NC NC

NC

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC NC

A12/BC* A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS* CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6 A7

A5

A1

VREFCA

VDDQ

VDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6 NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

DDR3-1333

FBGA

OMIT_TABLE

U2650

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2660

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

FBGA

DDR3-1333

OMIT_TABLE

U2670

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

201

MF

1%

240

1/20W

R2600

2

1

201

240

1% 1/20W MF

R2610

2

1

201

MF

1/20W

1%

240

R2620

2

1

201

240

1% 1/20W MF

R2630

2

1

201

CERM-X5R-1

20%

4V

0.47UF

C2607

1

2

10%

201

X5R

6.3V

0.047UF

C2609

1

2

10%

201

X5R

6.3V

0.047UF

C2608

1

2

10%

201

X5R

6.3V

0.047UF

C2619

1

2

10%

201

X5R

6.3V

0.047UF

C2618

1

2

201

CERM-X5R-1

20%

4V

0.47UF

C2617

1

2

10%

201

X5R

6.3V

0.047UF

C2629

1

2

10%

201

X5R

6.3V

0.047UF

C2628

1

2

201

0.47UF

20%

4V

CERM-X5R-1

C2627

1

2

10%

201

X5R

6.3V

0.047UF

C2639

1

2

10%

201

X5R

6.3V

0.047UF

C2638

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2637

1

2

10%

201

X5R

6.3V

0.047UF

C2679

1

2

10%

201

X5R

6.3V

0.047UF

C2678

1

2

201

20%

4V

CERM-X5R-1

0.47UF

C2677

1

2

10%

201

X5R

6.3V

0.047UF

C2669

1

2

10%

201

X5R

6.3V

0.047UF

C2668

1

2

201

0.47UF

20%

CERM-X5R-1

4V

C2667

1

2

10%

201

X5R

6.3V

0.047UF

C2659

1

2

10%

201

X5R

6.3V

0.047UF

C2658

1

2

201

240

1% 1/20W MF

R2670

2

1

201

MF

1/20W

1%

240

R2660

2

1

201

20%

4V

CERM-X5R-1

0.47UF

C2657

1

2

10%

201

X5R

6.3V

0.047UF

C2649

1

2

10%

201

X5R

6.3V

0.047UF

C2648

1

2

201

0.47UF

20%

4V

CERM-X5R-1

C2647

1

2

201

240

1% 1/20W MF

R2650

2

1

201

MF

1/20W

1%

240

R2640

2

1

20% 10V

402

2.2UF

X5R-CERM

C2640

1

2

10V

20%

2.2UF

X5R-CERM

402

C2600

1

2

20% 10V

402

2.2UF

X5R-CERM

C2641

1

2

X5R-CERM

2.2UF

402

10V

20%

C2650

1

2

20% 10V

402

2.2UF

X5R-CERM

C2601

1

2

X5R-CERM

2.2UF

20% 10V

402

C2610

1

2

X5R-CERM

2.2UF

402

10V

20%

C2651

1

2

X5R-CERM

2.2UF

402

10V

20%

C2611

1

2

X5R-CERM

2.2UF

402

10V

20%

C2660

1

2

X5R-CERM

2.2UF

402

10V

20%

C2661

1

2

X5R-CERM

2.2UF

20% 10V

402

C2620

1

2

X5R-CERM

2.2UF

402

10V

20%

C2621

1

2

X5R-CERM

2.2UF

402

10V

20%

C2670

1

2

X5R-CERM

2.2UF

402

10V

20%

C2671

1

2

2.2UF

10V

X5R-CERM

20%

402

C2630

1

2

X5R-CERM

2.2UF

402

10V

20%

C2631

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2643

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2644

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2603

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2604

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2645

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2653

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2605

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2613

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2654

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2614

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2655

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2663

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2615

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2623

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2664

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2665

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2624

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2625

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2673

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2633

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2634

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2674

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2675

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2635

1

2

DDR3-1333

FBGA

OMIT_TABLE

U2600

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2610

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2620

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2630

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3-1333

FBGA

OMIT_TABLE

U2640

K4 L8

H8 M8 K8 N4 N8 J8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4 D4

A1 A4 A11 F2 F10

H2 H10

N1

N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10J9E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

DDR3 SDRAM Bank B (2 OF 2)

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

PP0V75_S3_MEM_VREFCA_B

MEM_B_DQ<2>

PP1V35_S3_MEM

MEM_B_DQ<51>

MEM_B_BA<2>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_A<3> MEM_B_A<6>

MEM_B_A<1>

MEM_B_CKE<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_RAS_L

MEM_B_ZQ<15>

MEM_B_WE_L MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_BA<1> MEM_B_BA<0>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<5> MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<61>

MEM_B_DQS_N<7>

MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_DQS_P<7>

MEM_B_DQ<60>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_A<2>MEM_B_A<2>

MEM_B_DQ<47>

MEM_B_CS_L<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_RAS_L

MEM_B_ZQ<14>

MEM_B_WE_L MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_BA<1> MEM_B_BA<0>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<5> MEM_B_A<8>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<53>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQ<52>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<50>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_RESET_L

MEM_B_A<5>

MEM_B_DQ<41>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<1>

MEM_B_CLK_P<1> MEM_B_RAS_L

MEM_B_ZQ<13>

MEM_B_WE_L MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_BA<1> MEM_B_BA<0>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<45>

MEM_B_DQS_N<5>

MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_DQS_P<5>

MEM_B_DQ<44>

MEM_B_DQ<46>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<40>

MEM_B_A<2>

MEM_B_A<6> MEM_B_A<5>

MEM_B_A<4> MEM_B_A<3>

MEM_B_CLK_P<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<1>

MEM_B_RAS_L

MEM_B_ZQ<12>

MEM_B_WE_L MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_BA<1> MEM_B_BA<0>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<37>

MEM_B_DQS_N<4>

MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_DQS_P<4>

MEM_B_DQ<36>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_A<2>

MEM_B_WE_L

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_RAS_L

MEM_B_ZQ<11>

MEM_B_WE_L MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_BA<1> MEM_B_BA<0>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<5> MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<1>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<28>

MEM_B_DQS_N<3>

MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_DQS_P<3>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<24>

MEM_B_DQ<26>

MEM_B_DQ<29>

MEM_B_DQ<27>

MEM_B_DQ<25>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<8>

MEM_B_DQ<19>

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_RAS_L

MEM_B_ZQ<10>

MEM_B_WE_L MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_BA<1> MEM_B_BA<0>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<6>

PP0V75_S3_MEM_VREFCA_B

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<21>

MEM_B_DQS_N<2>

MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_DQS_P<2>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<18>

MEM_B_DQ<20>

MEM_B_A<2>MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQS_N<1>

MEM_B_DQ<12>

MEM_B_DQ<9>

MEM_B_DQ<6>

MEM_B_DQ<3>

MEM_B_CKE<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<1>

MEM_B_CLK_P<1> MEM_B_RAS_L

MEM_B_ZQ<9>

MEM_B_WE_L MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_BA<1> MEM_B_BA<0>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<5> MEM_B_A<8>

MEM_B_A<6>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_CS_L<1>

MEM_B_DQS_P<1>

MEM_B_DQ<10>

MEM_B_DQ<15>

MEM_B_DQ<8>

MEM_B_DQ<11>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_A<11>

MEM_B_CS_L<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_RAS_L

MEM_B_ZQ<8>

MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_BA<1> MEM_B_BA<0>

MEM_RESET_L

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<5> MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<1>

PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<12> MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_BA<2>

MEM_B_A<14> MEM_B_A<15>

MEM_B_DQ<4>

MEM_B_DQS_N<0>

MEM_B_CKE<1>

MEM_B_DQS_P<0>

MEM_B_DQ<7>

MEM_B_DQ<0>

MEM_B_DQ<5>

MEM_B_DQ<1>

MEM_B_A<2>

PP1V35_S3_MEM

<SCH_NUM>

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w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN

IN IN

IN

IN IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Place Source Cterm at neckdown at first DRAM

MEM Clock Termination

Place RC end termination after last DRAM

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

7

25 26 77

1/32W

4X0201

5%

36

RP2730

1 8

5%361/32W

4X0201

RP2703

1 8

1/32W

4X0201

5%

36

RP2702

1 8

1/32W

36

5%

4X0201

RP2701

2 7

4X0201

1/32W

5%

36

RP2701

4 5

4X0201

1/32W

36

5%

RP2702

2 7

4X0201

1/32W

36

5%

RP2706

2 7

CERM-X5R-1

4V

20%

0.47UF

201

C2704

1

2

20% 4V CERM-X5R-1

0.47UF

201

C2702

1

2

20% 4V CERM-X5R-1

0.47UF

201

C2700

1

2

20% 4V CERM-X5R-1

0.47UF

201

C2723

1

2

5%

4X0201

1/32W

36

RP2728

2 7

20% 4V

0.47UF

CERM-X5R-1 201

C2727

1

2

20% 4V CERM-X5R-1

0.47UF

201

C2725

1

2

20% CERM-X5R-1

0.47UF

4V 201

C2707

1

2

20%

0.47UF

CERM-X5R-1

4V 201

C2703

1

2

0.47UF

CERM-X5R-1

4V

20%

201

C2705

1

2

3.3PF

CERM

25V

5%

PLACE_NEAR=U2600.F8:3.2mm

201

C2765

1

2

30

1/20W

MF

5%

201

R2766

1 2

CERM

25V

3.3PF

5%

PLACE_NEAR=U2470.F8:3.2mm

201

C2755

1

2

1/32W

36

4X0201

5%

RP2730

2 7

30

1/20W

MF

5%

201

R2765

1 2

5% MF

1/20W

30

201

R2756

1 2

5%

30

1/20W

MF

201

R2755

1 2

6.3V

CERM-X5R

0201

0.1UF

10%

C2766

1 2

6.3V

CERM-X5R

0201

0.1UF

10%

C2756

1 2

6.3V

CERM-X5R

0201

0.1UF

10%

C2751

1 2

6.3V

CERM-X5R

0201

0.1UF

10%

C2761

1 2

30

1/20W

MF

5%

201

R2750

1 2

36

4X0201

1/32W

5%

RP2724

2 7

5% MF

1/20W

30

201

R2751

1 2

CERM

3.3PF

25V

5%

PLACE_NEAR=U2370.F8:3.2mm

201

C2750

1

2

30

MF

1/20W

5%

201

R2760

1 2

1/20W

30

MF

5%

201

R2761

1 2

3.3PF

5%

25V

CERM

PLACE_NEAR=U2500.F8:3.2mm

201

C2760

1

2

7

23 77

7

23 77

7

25 77

7

25 77

7

24 77

20% 4V CERM-X5R-1

0.47UF

201

C2730

1

2

7

24 77

7

26 77

7

26 77

4X0201

1/32W

5%

36

RP2705

1 8

7

24 77

4X0201

5%361/32W

RP2705

2 7

7

23 24 77

36

4X0201

1/32W

5%

RP2725

2 7

7

25 26 77

1/32W

5%

4X0201

36

RP2725

3 6

0.47UF

CERM-X5R-1

4V

20%

201

C2728

1

2

7

25 26 77

5%

1/32W

4X0201

36

RP2725

1 8

7

25 26 77

36

5%

1/32W

4X0201

RP2705

3 6

7

23 24 77

36

5%

1/32W

4X0201

RP2705

4 5

7

23 24 77

4X0201

36

5%

1/32W

RP2725

4 5

7

25 26 77

20% 4V CERM-X5R-1

0.47UF

201

C2726

1

2

5%

1/32W

4X0201

36

RP2720

1 8

7

26 77

7

25 26 77

7

25 26 77

7

25 26 77

7

25 77

7

25 77

7

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7

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7

23 24 77

7

23 24 77

7

23 24 77

7

23 24 77

1/32W

4X0201

5%

36

RP2724

4 5

4X0201

5%361/32W

RP2730

4 5

1/32W

36

4X0201

5%

RP2720

3 6

4X0201

1/32W

36

5%

RP2720

2 7

36

1/32W

4X0201

5%

RP2722

2 7

7

25 26 77

4X0201

1/32W

36

5%

RP2722

4 5

5%361/32W

4X0201

RP2726

3 6

4X0201

1/32W

36

5%

RP2728

3 6

5%361/32W

4X0201

RP2728

4 5

36

5%

1/32W

4X0201

RP2726

2 7

1/32W

4X0201

36

5%

RP2724

3 6

36

5%

4X0201

1/32W

RP2722

3 6

5%361/32W

4X0201

RP2720

4 5

36

5%

1/32W

4X0201

RP2728

1 8

4X0201

5%

1/32W

36

RP2724

1 8

7

25 26 77

5%

36

4X0201

1/32W

RP2722

1 8

36

4X0201

1/32W

5%

RP2726

4 5

20% 4V

0.47UF

CERM-X5R-1 201

C2724

1

2

0.47UF

4V

20% CERM-X5R-1

201

C2722

1

2

CERM-X5R-1

0.47UF

20% 4V

201

C2720

1

2

5%

1/32W

4X0201

36

RP2706

3 6

36

5%

4X0201

1/32W

RP2701

1 8

4X0201

1/32W

5%

36

RP2701

3 6

1/32W

5%

36

4X0201

RP2704

4 5

1/32W

5%

4X0201

36

RP2704

2 7

7

25 26 77

4X0201

1/32W

5%

36

RP2707

4 5

36

5%

4X0201

1/32W

RP2702

4 5

1/32W

4X0201

5%

36

RP2703

3 6

5%

36

4X0201

1/32W

RP2707

1 8

0.47UF

CERM-X5R-1

4V

20%

201

C2710

1

2

0.47UF

CERM-X5R-1

4V

20%

201

C2708

1

2

0.47UF

CERM-X5R-1

4V

20%

201

C2706

1

2

5%

4X0201

1/32W

36

RP2707

2 7

7

23 24 77

7

23 24 77

1/32W

4X0201

5%

36

RP2730

3 6

7

23 24 77

7

24 77

7

23 24 77

7

23 24 77

7

23 24 77

7

23 24 77

7

23 77

7

23 24 77

7

23 24 77

7

23 24 77

4X0201

1/32W

36

5%

RP2726

1 8

7

24 77

7

23 24 77

36

1/32W

5%

4X0201

RP2703

4 5

4X0201

36

1/32W

5%

RP2704

1 8

36

1/32W

5%

4X0201

RP2706

4 5

4X0201

36

5%

1/32W

RP2702

3 6

1/32W

4X0201

5%

36

RP2704

3 6

1/32W

5%

4X0201

36

RP2703

2 7

1/32W

5%

4X0201

36

RP2707

3 6

36

4X0201

1/32W

5%

RP2706

1 8

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

DDR3 Termination

MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<2> MEM_A_A<1>

PPVTT_S0_DDR

MEM_A_A<11> MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<3>

MEM_A_A<12>

MEM_A_CS_L<1> MEM_A_A<15>

MEM_A_ODT<1> MEM_A_A<10>

MEM_A_RAS_L MEM_A_CKE<0>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<5> MEM_A_BA<1>

MEM_A_BA<2> MEM_A_WE_L

MEM_A_A<0>

MEM_A_BA<0>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_BA<1> MEM_B_A<0>

MEM_B_CKE<1> MEM_B_ODT<1>

MEM_B_CAS_L

MEM_B_A<15>

MEM_B_A<9> MEM_B_A<14>

PPVTT_S0_DDR

MEM_B_A<7> MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<1>

MEM_B_A<11>

MEM_B_A<13>

MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_B_A<12>

MEM_B_CS_L<1>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_WE_L

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_RAS_L MEM_B_ODT<0>

MEM_B_CS_L<0> MEM_B_BA<2>

MEM_B_A<10>

MEM_A_CLK0_TERM_R

MEM_A_CLK1_TERM_R

MEM_B_CLK0_TERM_R

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_A_CLK_N<1>

MEM_B_CLK1_TERM_R

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_A_CLK_P<1>

<SCH_NUM>

27 OF 118

27 OF 81

21 27 60 69 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN

OUT

IN IN

OUT

BI

IN

BI

OUT IN

OUT

IN

OUT OUT

BI BI

IN

IN IN IN OUT

OUT OUT

BI BI

IN

OUT OUT OUT

OUT

IN

IN IN

IN

OUT

PORTS

MISC

(1 OF 2)

PCIE GEN2

DISPLAY PORT

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_3_P

PERP_2 PERN_2

PETN_3

PETP_3

PETN_1

PETP_1

PETP_0 PETN_0

XTAL_25_OUT

XTAL_25_IN

EE_CS_N

DPSNK0_0_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_2_P

DPSNK0_AUX_N

DPSNK0_AUX_P

DPSNK0_HPD

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_3_N

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

DPSRC_0_N

DPSRC_0_P

DPSRC_1_N

DPSRC_1_P

DPSRC_2_N

DPSRC_2_P

DPSRC_3_N

DPSRC_3_P

DPSRC_AUX_N

DPSRC_AUX_P

DPSRC_HPD_OD

EE_CLK

EE_DI EE_DO

GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0 GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1 GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2

GPIO_14 GPIO_15

GPIO_2/TMU_CLK_IN/AC_PRESENT

GPIO_3/FORCE_PWR GPIO_4/WAKE_OD_N

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

GPIO_6_OD/CIO_SDA_OD GPIO_7_OD/CIO_SCL_OD

GPIO_8/EN_CIO_PWR_OD*

GPIO_9/SX_CTRL_OD*

MONDC0

MONOBSN

MONOBSP

PA_AUX_N

PA_AUX_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO0_TX_P/DPSRC_0_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_CIO1_TX_N/DPSRC_2_N

PA_CIO1_TX_P/DPSRC_2_P

PA_CONFIG1/CIO_0_LSEO PA_CONFIG2/CIO_0_LSOE

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_DPSRC_HPD

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PB_AUX_N

PB_AUX_P

PB_CIO2_RX_N

PB_CIO2_RX_P

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO3_RX_N

PB_CIO3_RX_P

PB_CIO3_TX_N/DPSRC_2_N

PB_CIO3_TX_P/DPSRC_2_P

PB_CONFIG1/CIO_2_LSEO PB_CONFIG2/CIO_2_LSOE

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_DPSRC_3_N

PB_DPSRC_3_P

PB_DPSRC_HPD

PB_LSRX/CIO_3_LSOE

PB_LSTX/CIO_3_LSEO

PCIE_CLKREQ_OD_N

PCIE_RST_0_N PCIE_RST_1_N PCIE_RST_2_N PCIE_RST_3_N

PERN_0

PERN_1

PERN_3

PERP_0

PERP_1

PERP_3

PERST_OD_N

PETN_2

PETP_2

PWR_ON_POC_RSTN

RBIAS

REFCLK_100_IN_N

REFCLK_100_IN_P

RSENSE

RSVD

TCK

TDI

TDO TEST_EN

THERMDA

TMS

TMU_CLK_OUT

MONDC1

TEST_PWR_GOOD

DPSNK0_3_P DPSNK0_3_N

VCC

DO/IO1

GND

THRM_PAD

CS*

CLK

WP*

HOLD*

DI/IO0

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

6 - PCIE_RST_2_N 7 - PCIE_RST_3_N

1 - GPIO_1

4 - GPIO_5

2 - GPIO_2 3 - GPIO_3

0 - GPIO_13

5 - PCIE_RST_1_N

11 - GPIO_0

10 - GPIO_14

12 - GPIO_12 13 - GPIO_10 14 - PB_LSTX 15 - PB_LSRX

9 - GPIO_11

8 - GPIO_15

NOTE: The following pins require testpoints:

Divides 3.3V to 1.8V

DEBUG: For monitoring clock

Use AA8 GND ball for THERM_DN

(TBT_SPI_CS_L)

If strap != bit then security is enabled?

Security strap setting is XORed with bit in the flash, so the active-level depends on the code in the flash.

Used for straps in host mode

(TBT_SPI_CLK)

(TBT_SPI_MOSI) (TBT_SPI_MISO)

SNK1 AC Coupling

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

SNK0 AC Coupling

DEBUG: For monitoring current/voltage

MF

1/20W

201

3.3K

5%

R2890

1

2

12 70

100

5% MF

1/20W 201

R2825

1

2

31

31 78

31

31 78

31 72 78

31 78

31 72 78

32

32 78

32

32 78

MF

1/20W

201

100K

5%

R2830

1

2

MF

1/20W

201

100K

5%

R2831

1

2

31 78

MF

1/20W 201

3.3K

5%

R2893

1

2

0201

0.1UF

X5R-CERM

16V10%

C2829

1 2

12 70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

0201

0.1UF

X5R-CERM

10% 16V

C2828

1 2

0201

0.1UF

X5R-CERM

16V10%

C2827

1 2

0201

0.1UF

X5R-CERM

10% 16V

C2826

1 2

0201

0.1UF

X5R-CERM

16V10%

C2825

1 2

0201

X5R-CERM

0.1UF

10% 16V

C2824

1 2

0201

0.1UF

X5R-CERM

16V10%

C2823

1 2

0201

0.1UF

X5R-CERM

10% 16V

C2822

1 2

1%

1K

201

1/20W MF

R2855

1

2

0201

0.1UF

X5R-CERM

16V10%

C2821

1 2

0201

0.1UF

X5R-CERM

16V10%

C2820

1 2

0201

0.1UF

X5R-CERM

16V10%

C2830

1 2

0201

0.1UF

X5R-CERM

16V10%

C2831

1 2

0201

0.1UF

X5R-CERM

16V10%

C2832

1 2

0201

0.1UF

X5R-CERM

16V10%

C2833

1 2

0201

X5R-CERM

0.1UF

16V10%

C2834

1 2

0201

0.1UF

X5R-CERM

16V10%

C2835

1 2

0201

0.1UF

X5R-CERM

16V10%

C2836

1 2

0201

0.1UF

X5R-CERM

16V10%

C2837

1 2

0201

0.1UF

X5R-CERM

16V10%

C2838

1 2

0201

X5R-CERM

0.1UF

16V10%

C2839

1 2

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

BYPASS=U2890:2mm

1UF

10%

6.3V CERM

402

C2890

1

2

12 70 74

31

32

20

32 78

32

20

31 78

31

28 30 31

31

28 31

28 32 33

32

28 32

28 29

20 41 42 43

11

19 75

201

MF

1/20W

1%

806

R2895

1 2

1/20W MF 201

1K

5%

R2896

1

2

MF

5%

1/20W

NO STUFF

10K

201

R2899

1

2

11 76

29

NONE

NOSTUFF

NONE NONE

OMIT

0201

R2815

1

2

5%

10K

201

1/20W

MF

R2888

1

2

10K

201

MF

1/20W

5%

R2887

1

2

NO STUFF

5%

201

1/20W MF

10K

R2886

1

2

NO STUFF

5%

10K

201

1/20W

MF

R2885

1

2

100K

MF

1/20W

201

5%

R2880

1

2

20

28 33

14 20

5%

201

1/20W MF

100K

R2883

1

2

FCBGA

REDWOOD-RIDGE

CRITICAL

OMIT_TABLE

U2800

D19

E20

D17

E18

D15

E16

D13

E14

G2

G4

AB5

D11

E12

D9

E10

D7

E8

D5

E6

H1

H3

U4

B9

A8

B11

A10

B13

A12

B15

A14

J2

J4

AC2

U8

T5

AA2

Y3

R8 N2 R2 P3 F3

T1 T3

F1

U2 L6 H5 Y7 Y1 T7 V7 M7

AD23 AC24

W16

W18

L2

L4

E22

G22

E24

G24

J22

L22

J24

L24

P1 K5

B17

A16

B19

A18

M3

J6

N8

K1

K3

N22

R22

N24

R24

U22

W22

U24

W24

D3 M1

B21

A20

B23

A22

N6

P7

M5

V3

W6 AB3 AD3 V1

AA10

AB13

AA16

AB19

AB9

AA12

AB15

AA18

P5

AD7

AD11

AD15

AD19

AD5

AD9

AD13

AD17

R4

W20

AD21

AB21

U20

AD1 L8

AA6

W2

U6 R6 W8

AB7

AB1

AA4

AA24 AB23

USON

4MBIT

W25X40CLXIG

OMIT_TABLE

CRITICAL

U2890

6

1

5 2

479

8

3

28 30

28 31 32

5%

10K

201

1/20W MF

R2861

1

2

MF

1/20W 201

10K

5%

R2863

1

2

MF

1/20W 201

10K

5%

NO STUFF

R2867

1

2

MF

1/20W 201

10K

5%

R2862

1

2

MF

1/20W

201

5%

100K

R2881

1

2

10K

201

1/20W

MF

5%

R2829

1

2

100K

MF

1/20W

201

5%

R2884

1

2

MF

1/20W 201

5%

100K

R2882

1

2

28 70

100K

MF

1/20W

201

5%

R2878

1

2

5%

201

1/20W MF

100K

R2879

1

2

5%

201

1/20W

MF

100K

R2832

1

2

0.1UF

0201

10%

16V X5R-CERM

C2801

1 2

0201

10%

0.1UF

16V X5R-CERM

C2800

1 2

0201

10%

0.1UF

16V X5R-CERM

C2802

1 2

0201

10%

16V X5R-CERM

0.1UF

C2803

1 2

MF

1/20W

201

3.3K

5%

R2892

1

2

0.1UF

10%

X5R-CERM

0201

16V

C2804

1 2

0201

0.1UF

10%

16V X5R-CERM

C2805

1 2

0201

10%

0.1UF

16V X5R-CERM

C2806

1 2

0201

10%

0.1UF

16V X5R-CERM

C2807

1 2

16V10%

X5R-CERM

0.1UF

0201

C2840

1 2

16V10%

X5R-CERM

0.1UF

0201

C2841

1 2

16V10%

X5R-CERM

0.1UF

0201

C2842

1 2

MF

1/20W 201

3.3K

5%

R2891

1

2

16V10%

X5R-CERM

0.1UF

0201

C2843

1 2

16V10%

X5R-CERM

0.1UF

0201

C2845

1 2

16V10%

0.1UF

X5R-CERM

0201

C2844

1 2

10% 16V

0.1UF

X5R-CERM

0201

C2846

1 2

10% 16V

0.1UF

X5R-CERM

0201

C2847

1 2

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

5

70 74

SYNC_DATE=01/14/2013

SYNC_MASTER=T29_RR

Thunderbolt Host (1 of 2)

TBT_CLKREQ_L

PP3V3_TBTLC

NC_DP_TBTSRC_ML_CN<0>

NC_DP_TBTSRC_AUXCH_CN

TBT_B_DP_PWRDN TBT_A_HV_EN

SYSCLK_CLK25M_TBT_R

PCIE_CLK100M_TBT_P

TBT_PWR_ON_POC_RST_L

TBT_PCIE_RESET_L

TBT_TMU_CLK_OUT

NC_DP_TBTSRC_ML_CP<3> NC_DP_TBTSRC_ML_CN<3>

NC_DP_TBTSRC_ML_CN<2> NC_DP_TBTSRC_ML_CP<1>

PCIE_TBT_R2D_C_N<0>

TBT_DDC_XBAR_EN_L

TBT_B_R2D_C_N<0>

TBT_EN_CIO_PWR_L

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_N<0>

SYSCLK_CLK25M_TBT

PP3V3_TBTLC

DP_TBTSNK0_ML_C_P<0>

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_N<2>

PCIE_TBT_R2D_C_P<3>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK1_ML_P<0>

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_N<1>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<1>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<2>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_P<3>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_AUXCH_C_P

PCIE_TBT_D2R_P<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<3>

TBT_THERMD_P

JTAG_TBT_TDI

TBT_RSENSE

PCIE_CLK100M_TBT_N

TBT_RBIAS

PCIE_TBT_D2R_C_P<2> PCIE_TBT_D2R_C_N<2>

PCIE_TBT_R2D_P<3>

PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_N<3>

TP_TBT_PCIE_RESET0_L

TBT_B_LSTX TBT_B_LSRX

DP_TBTPB_HPD

DP_TBTPB_ML_C_P<3> DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>

TBT_B_CONFIG2_RC

TBT_B_CONFIG1_BUF

TBT_B_R2D_C_P<1> TBT_B_R2D_C_N<1>

TBT_B_D2R_P<1> TBT_B_D2R_N<1>

TBT_B_R2D_C_P<0>

TBT_B_D2R_P<0> TBT_B_D2R_N<0>

DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N

TBT_A_LSTX TBT_A_LSRX

DP_TBTPA_HPD

DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1>

TBT_A_CONFIG2_RC

TBT_A_CONFIG1_BUF

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

TBT_A_D2R_P<1> TBT_A_D2R_N<1>

TBT_A_R2D_C_N<0> TBT_A_D2R_P<0>

TBT_A_D2R_N<0>

DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N

TP_TBT_MONDC0

TBT_B_DP_PWRDNTBT_A_DP_PWRDN

TBT_B_CIO_SELTBT_A_CIO_SEL

TBT_B_HV_ENTBT_A_HV_EN

NC_DP_TBTSRC_ML_CP<2>

NC_DP_TBTSRC_ML_CP<0>

DP_TBTSNK1_HPD

DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<1> DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<0> DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_HPD

DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_P<2> DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0> DP_TBTSNK0_ML_N<0>

NC_TBT_XTAL25OUT

PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_P<1> PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<3> PCIE_TBT_D2R_C_N<3>

PCIE_TBT_R2D_N<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2> DP_TBTSNK1_ML_N<2>

TBTROM_HOLD_L

TBTROM_WP_L

TBT_BATLOW_L TBTDP_AUXIO_EN

TBT_DFT_STRAP_3

TBT_DFT_STRAP_1

PCIE_TBT_R2D_P<2>

PP3V3_TBTLC

TBT_A_R2D_C_P<0>

NC_DP_TBTSRC_ML_CN<1>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<1>

PCIE_TBT_R2D_N<1>

TP_TBT_MONDC1

TBT_MONOBSN

TBT_MONOBSP

TBT_SPI_MISO

TBT_SPI_CLK

TBT_SPI_CS_L

TBT_SPI_MOSI

TBT_TEST_PWR_GOOD

TBT_TEST_EN

JTAG_TBT_TDO

JTAG_TBT_TCK

JTAG_TBT_TMS

NC_DP_TBTSRC_AUXCH_CP

TBT_PWR_EN

TBT_CIO_PLUG_EVENT_L HDMITBTMUX_SEL_TBT

SMC_PME_S4_DARK_L

TBT_ROM_SECURITY_XOR

TBT_A_DP_PWRDN

TBT_B_HV_EN

TBT_BATLOW_L

PP3V3_S4_TBT

TBTDP_AUXIO_EN

TBT_DDC_XBAR_EN_L HDMITBTMUX_SEL_TBT

TBT_EN_CIO_PWR_L

PP3V3_S4_TBT

DP_TBTSRC_HPD

TBT_GPIO7

TBT_GPIO2

PP3V3_TBTLC

<SCH_NUM>

28 OF 118

28 OF 81

19 20 28 29 69

72

28 32

28 30 31

75

72

74

72 74

19 20 28 29 69

28 74

48 81

72

74

72

74

72

74

72

74

72 74

72

28 74

72

72 74

72

74

72

74

72

74

72 74

28 74

72

74

19 20 28 29 69

72

28 74

72 74

78

72

28 31

28 32 33

28 30

28 29 30 46 69

28 31 32

28 33

28 70

28 29

28 29 30 46 69

28

19 20 28 29 69

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

GND

VCC

(2 OF 2)

VSSVSS

VCC3P3_RDV_DECAP

VCC3P3_LC

VCC3P3

VCC1P0_RDV_DECAP

VCC1P0_CIO

SVR_VCC1P0

SVR_AMON

SVR_IND0

NC

SDG

VOUT

GND

ON

VIN

IN

OUT

IN

D

SYM_VER_3

S G

G

D

S

OUT

GND

SENSE

ENABLE SENSE_OUT

CT

VCC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

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A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

Vth = 2.508V nominal

TBT "POC" Power-up Reset

Delay = 4.04ms nominal

Internal switch not functional on RR.

100 mA EDP

3.1 W (Dual-Port)

2.4 W (Single-Port)

POC input to RR - 150 mA EDP

SVR input to RR - 1100 mA EDP

1900 mA EDP

700 mA EDP

1200 mA EDP

25 mA EDP

EDP: 1.25 A

1.05V TBT "CIO" Switch

Pull-up (S0) on PCH page

Load Switch

11.5 mOhm Max

8 mOhm Typ

Max Current = 4A (85C)

@ 1.05V

R(on)

Type

Part

Isolated to reduce noise from SVR

Push-pull output

TPS22920

U2950

20%

1.0UF

X5R

6.3V

0201-1

C2906

1

2

FCBGA

REDWOOD-RIDGE

OMIT_TABLE

CRITICAL

U2800

B5

A4 A6 B3

J8

K9 L14 M15 M17 P17 V19

J10 J12

R14 T11 T15 U10 U14 V11

K11 L10 M11 N10 N14 P11 P15 R10

G10 G12

K19

K7 L16 M19 P19 T19 U18 V15 V17 W12

G14

W14

G16 G18 H19

H9 J18 K15 K17

D1 E2 H11 N4 V5 W4

Y5

H13 H15 H17 H7 L18 N18 R18 W10

A2 A24

AC14 AC16 AC18 AC20 AC22

AC4 AC6 AC8

B1

B7

AA14

C10 C12 C14 C16 C18

C2 C20 C22 C24

C4

AA20

C6

C8 D21 D23

E4 F11 F13 F15 F17 F19

AA22

F21 F23

F5

F7

F9

G20 G6 G8 H21 H23

AA8 J14

J16 J20 K13 K21 K23 L12 L20 M13 M21

AB11

M23 M9 N12 N16 N20 P13 P21 P23 P9 R12

AB17

R16 R20 T13 T17 T21 T23 T9 U12 U16 V13

AC10

V21 V23 V9 Y11 Y13 Y15 Y17 Y19 Y21 Y23

AC12

Y9

20%

1.0UF

X5R

6.3V

0201-1

C2911

1

2

0201-1

X5R

6.3V

1.0UF

20%

C2910

1

2

SM

680NH-30%-3.6A-35MOHM

CRITICAL

L2920

1 2

6.3V

CERM-X5R

0402-1

10UF

20%

C2922

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2923

1

2

NSR1020MW2T1G

SOD-323

CRITICAL

D2920

A

K

DMN5L06VK-7

SOT-563

Q2945

6

2

1

5%

100K

201

MF

1/20W

R2945

1

2

CSP

TPS22920

CRITICAL

U2940

D1

D2

A2 B2 C2

A1 B1 C1

20% X5R

6.3V 0201-1

1.0UF

C2940

1

2

20%

1.0UF

X5R

6.3V 0201-1

C2981

1

2

20%

1.0UF

X5R

6.3V 0201-1

C2980

1

2

0201-1

6.3V X5R

20%

1.0UF

C2970

1

2

28

0201-1

6.3V X5R

1.0UF

20%

C2960

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2961

1

2

20%

10UF

0402-1

CERM-X5R

6.3V

C2953

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2952

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2951

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2950

1

2

PLACE_NEAR=C2953.1:1mm

SM

XW2960

1

2

28

16V

X7R-CERM

0201

10%

330PF

C2995

1

2

1/20W MF 201

24.9K

1%

R2991

1

2

25V X5R

10%

0.1UF

402

C2990

1

2

14

5% MF

201

100K

1/20W

R2995

1

2

19 30 41 42

5%

100K

1/20W MF 201

R2990

1

2

DFN1006H4-3

DMN32D2LFB4

Q2995

3

1

2

X7R-CERM

10% 50V

0.001UF

0402

C2991

1

2

SOT-563

DMN5L06VK-7

Q2945

3

5

4

12

TPS3895ADRY

USON

CRITICAL

U2990

5

1

2

3

4

6

1/20W

100K

201

MF

5%

R2992

1

2

0201-1

6.3V X5R

1.0UF

20%

C2903

1

2

20%

10UF

0402-1

CERM-X5R

6.3V

C2920

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2921

1

2

20%

6.3V X5R

0201-1

1.0UF

C2904

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2905

1

2

0201-1

6.3V X5R

1.0UF

20%

C2900

1

2

1.0UF

X5R

6.3V

20%

0201-1

C2901

1

2

0201-1

6.3V X5R

1.0UF

20%

C2902

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2932

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2931

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2930

1

2

Thunderbolt Host (2 of 2)

SYNC_MASTER=T29_RR

SYNC_DATE=01/14/2013

TBT_PWR_ON_POC_RST_L TBTPOCRST_CT

TBT_EN_CIO_PWR_L

TBT_EN_CIO_PWR

PP1V05_TBT

PP1V05_TBTRDV

MIN_LINE_WIDTH=0.38 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3_TBTRDV

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.50 MM

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.20 MM

P1V05TBT_SW

PP1V05_TBTCIO

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_S4_TBT_F

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3_S4_TBT

PP1V05_TBT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM VOLTAGE=1.05V

PP3V3_S0

TBT_PWR_REQ_L

TBTPOCRST_SENSE

PP3V3_S4_TBT

PP3V3_S0

SMC_DELAYED_PWRGD

TBTPOCRST_MR_L

TBT_POC_RESET_L

PP3V3_TBTLC

VOLTAGE=3.3V

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.15 MM

<SCH_NUM>

29 OF 118

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29

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11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

19 20 28 29 69

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN

SGD

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

IN

SYM_VER_2

G S

D

SDG

OUT

D

SYM_VER_3

S G

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Freq = 480KHz

Max Current = 2A?

Id(max): 3.7A @ 70C

8-13V Input

- =PPVIN_SW_TBTBST (8-13V Boost Input)

<R1>

Vds(max): -30V

SI8409DB:

Vgs(max): +/-12V Vgs(th): -1.4V

<Ra>

<Rb>

Vout = 1.6V * (1 + Ra / Rb)

no XW necessary.

GND inside package,

SGND shorted to

Max Vgs: 10V

UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO = 4.55V (falling), 4.95 (rising)

Changes required for 2S.

<R2>

Second FET needed for dual-port designs.

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

BOM options provided by this page:

Vout = 15.47V

add property on another page.

Voltage not specified here,

Rds(on): 46mOhm @ 4.5V Vgs

Pull-up on RR page

- =PP15V_TBT_REG (15V Boost Output)

(NONE)

Thunderbolt 15V Boost Regulator

BATLOW# Isolation

5%

402

MF-LF

1/16W

330K

R3081

1

2

5%

402

1/16W MF-LF

470K

R3080

1

2

402

X5R

0.1UF

10% 25V

C3080

1

2

1/16W MF-LF

1%

73.2K

402

R3092

1

2

5%

402

330K

MF-LF

1/16W

R3087

1

2

1%

MF-LF

1/16W

402

26.7K

R3094

1

2

402

10% CERM-X5R

6.3V

0.33UF

C3094

1

2

5%

402

1/16W MF-LF

330K

R3088

1

2

19 29 41 42

5%

402

50V CERM

100PF

NO STUFF

C3089

1

2

15.8K

MF-LF

402

1/16W

1%

R3096

1

2

33UF-0.06OHM

25V POLY-TANT

20%

CASE-D3L

C3095

1

2

25V

10%

10UF

X5R

1206-2

C3096

1

2

805

10% X5R

25V

10UF

NO STUFF

C3097

1

2

5% 50V

68PF

COG-CERM 0402

C3087

1

2

X5R-CERM

402

10V

20%

2.2UF

C3085

1

2

BGA

CRITICAL

SI8409DB

Q3080

2 3

1

4

402

1/16W MF-LF

49.9K

1%

R3093

1

2

402

1/16W MF-LF

200K

1%

R3091

1

2

25V

20%

0603

X5R-CERM

10UF

C3090

1

2

20%

0603

25V

X5R-CERM

10UF

C3091

1

2

CRITICAL

3.3UH-6.5A

PIMB063T-SM

L3095

1 2

5% 50V C0G-CERM 0402

10PF

C3088

1

2

QFN

LT3957

CRITICAL

U3090

25

31

1213141516

17

28

1 2 10 35 36

33

6

3

42324

37

32

8

9

202138

34

30

27

137K

402

MF-LF

1%

1/16W

R3095

1

2

SM

PLACE_NEAR=C3095.1:2 mm

XW3095

12

5%

0

0201

1/20W

MF

R3089

1

2

0402

50V

10% X7R-CERM

0.001UF

C3099

1

2

0.0033UF

50V

10% X7R-CERM

0402

C3093

1

2

2.2UF

402

X5R-CERM

10V

20%

C3092

1

2

20%

2.2UF

10V 402

X5R-CERM

C3086

1

2

PWRDI5

PDS540XF

CRITICAL

D3095

1

2

3

28 31

DMN32D2LFB4

DFN1006H4-3

Q3005

3

1

2

DMN5L06VK-7

SOT-563

Q3088

6

2

1

DMN5L06VK-7

SOT-563

Q3088

3

5

4

28 30

DFN1006H4-3

DMN32D2LFB4

Q3000

3

1

2

12 41 43

Thunderbolt Mobile Support

SYNC_DATE=01/14/2013

SYNC_MASTER=T29_RR

PP3V3_S4_TBT

TBT_BATLOW_L

GND_TBTBST_SGND

MIN_LINE_WIDTH=0.5 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

TBT_A_HV_EN

SMC_DELAYED_PWRGD

TBTBST_SS

TBTBST_PWREN_DIV_L

TBTBST_SHDN_DIV

TBTBST_FBX

TBTBST_INTVCC

TBTBST_VC

TBTBST_SNS2

DIDT=TRUE

MIN_LINE_WIDTH=0.5 mm

TBTBST_BOOST

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

TBTBST_VSNS

TBTBST_PWREN_L

TBTBST_VC_RC

MAKE_BASE=TRUE

TBT_BATLOW_L

PM_BATLOW_L

PPBUS_G3H

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_SW_TBTBST

TBTBST_SNS1

PP15V_TBT

TBTBST_RT

TBTBST_EN_UVLO

<SCH_NUM>

30 OF 118

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w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN IN

OUT

IN IN

V3P3

ISET_V3P3

OUT

THRM

GND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD

IN

OUT

BI

IN

OUT

OUT OUT

OUT

IN IN

BI BI

IN IN

OUT

TB+

LSRX

AUX+

CA_DET

DPMLO+ DPMLO-

HPD

THMPAD

GND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENA

TB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN IN

IN

ML_LANE1P

GND1

ML_LANE0N

GND0

ML_LANE0P

ML_LANE1N

ML_LANE2N

RETURN

HPD CONFIG1 CONFIG2 GND2 ML_LANE3P ML_LANE3N GND4

DP_PWR

AUX_CHP AUX_CHN

ML_LANE2P

GND3

SHIELD PINS

PORT B

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

wake from Thunderbolt devices.

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

on AC-coupled signals.

470k R’s for ESD protection

TBT Dir

Thunderbolt Connector A

ISET_Sx with CD3210.

Nominal Min Max

15.75V Max

3.3V/HV Power MUX

IV3P3 1100mA 1030mA 1200mA

TBT: RX_1

TBT: RX_0

TBT: TX_1

For 12V systems:

Nominal Min Max IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

12V: See

Single R on ISET_V3P3 OK.

requires two R’s per HV

below

(IPU) (IPD)

(IPD)

(IPU)

TBT: RX_1

TBT: LSX_A_R2P/P2R (P/N)

High: 2.0 - 5.0V

DP Source must pull

TBT: LSX_R2P/P2R (P/N)

(Both C’s)

DP Dir

(0-18.9V)

TBT: TX_0

(0-18.9V)

TBT Dir

(Both C’s)

Sink HPD range:

ILIM = 40000 / RISET

Low: 0 - 0.8V

Single-fault protection

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

V3P3 must be S4 to support

<RV3P3>

TBT: Unused

greater than or equal to 100K (DPv1.1a).

down HPD input with

514-0876

DP Dir

0.01UF

X7R-CERM

0402

10% 50V

C3200

1

2

28 78

0.01UF

X5R-CERM

10% 16V

0201

C3202

1

2

12

5%

201

MF

1/20W

R3201

1 2

0.01UF

X7R-CERM

10% 50V

0402

C3201

1

2

1K

MF

201

5%

1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

R3294

1

2

1K

MF 201

5% 1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

R3295

1

2

100K

MF 201

5% 1/20W

R3241

1

2

10UF

CERM-X5R 0402

20%

6.3V

C3286

1

2

0.1UF

0201

10% 16V

X5R-CERM

C3285

1

2

0.1UF

X5R-CERM 0201

10% 16V

C3281

1

2

22UF

X5R-CERM-1

603

6.3V

20%

C3280

1

2

CRITICAL

POLY-TANT

CASE-B2-SM

20%

6.3V

100UF

C3287

1

2

1M

MF

201

5%

1/20W

R3252

1

2

1M

MF 201

5% 1/20W

R3251

1

2

330PF

X7R-CERM

0201

10% 16V

C3294

1

2

330PF

X7R-CERM 0201

10% 16V

C3295

1

2

0603

FERR-120-OHM-3A

CRITICAL

L3200

1 2

28

X5R 402

10% 25V

0.1UF

C3210

1

2

GND_VOID=TRUE

1/20W

5%

201

MF

470K

R3270

1

2

GND_VOID=TRUE

1/20W

5%

201

MF

470K

R3271

1

2

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

C3271

1 2

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

C3270

1 2

28 72 78

28 78

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

C3272

1 2

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

C3273

1 2

GND_VOID=TRUE

1/20W

5%

201

MF

470K

R3273

1

2

GND_VOID=TRUE

1/20W

5%

201

MF

470K

R3272

1

2

CD3211A0RGPR

QFN

CRITICAL

U3210

5

16 4

123

13

15

11 10

9

8

12 14

17

21

19 20

18

6 7

28 30

32 65 66

32 45 66

36.5K

MF 201

1% 1/20W

R3212

1

2

0.1UF

X5R 402

10% 25V

C3211

1

2

X5R-CERM

16V

10%

0201

0.1UF

C3220

1

2

28

33

28

28 72 78

28 78

X5R

20%

6.3V

0.22UF

0201

C3232

1 2

X5R

0201

20%

6.3V

0.22UF

C3233

1 2

28 78

0201

X5R-CERM

16V10%

0.1UF

C3230

1 2

16V10%

0.1UF

0201

X5R-CERM

C3231

1 2

28 78

X5R

0201

20%

6.3V

0.22UF

C3278

1 2

X5R

0201

20%

6.3V

0.22UF

C3279

1 2

28 78

TBTHV:P15V

22.6K

MF 201

1% 1/20W

R3211

1

2

TBTHV:P15V

22.6K

MF

201

1%

1/20W

R3210

1

2

TBTHV:P15V

1/20W

1%

201

MF

22.6K

R3214

1

2

1/20W

1%

201

MF

22.6K

TBTHV:P15V

R3213

1

2

4.7UF

X5R-CERM

0603

10% 25V

C3215

1

2

GND_VOID=TRUE

25V

10%

0201

X5R-CERM

0.01UF

C3205

1

2

10%

0.01UF

X5R-CERM

0201

25V

GND_VOID=TRUE

C3206

1

2

28

20%

0.47UF

CERM-X5R-1

201

GND_VOID=TRUE

4V

C3274

1 2

20%

0.47UF

CERM-X5R-1

GND_VOID=TRUE

4V 201

C3275

1 2

CRITICAL

HVQFN24-COMBO

CBTL05024

SIGNAL_MODEL=TBT_MUX

U3220

1 2

24

23 22

1816

5

4

10

11

6

20

19

9

21

1712

13

14

157

8

25

3

28 32

28

470K

MF

201

5%

1/20W

R3279

1

2

470K

MF 201

5% 1/20W

R3278

1

2

GND_VOID=TRUE

CERM-X5R-1

20%

0.47UF

4V 201

C3277

1 2

CERM-X5R-1

GND_VOID=TRUE

20%

0.47UF

4V 201

C3276

1 2

MDP-J44

CRITICAL

F-RT-TH

J3200

B18

B16

B4 B6

B20

B1

B7B8

B13B14

B2

B5

B3

B11

B9

B17

B15

B12

B10

B19

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S24

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

118S0145

2

R3210,R3213

TBTHV:P12V

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

2

R3211,R3214

118S0145

TBTHV:P12V

SYNC_DATE=12/18/2012

SYNC_MASTER=J15_REFERENCE

Thunderbolt Connector A

TBT_A_HPD

TBT_A_D2R1_AUXDDC_N

TBT_A_D2R1_AUXDDC_P

PP3V3RHV_S4_TBTAPWR_F

MIN_LINE_WIDTH=0.38 MM VOLTAGE=15V

MIN_NECK_WIDTH=0.20 MM

DP_TBTPA_ML_P<3> DP_A_LSX_ML_P<1>

VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBTACONN_7_C

TBT_A_R2D_N<0>

MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM

TBTACONN_1_C

TBT_A_R2D_P<0>

DP_A_LSX_ML_N<1>

TBT_A_R2D_N<1>

TBT_A_D2R_C_P<0> TBT_A_D2R_C_N<0>

DP_TBTPA_ML_N<3>

TBT_A_R2D_P<1>

TBT_A_CONFIG1_RC

PM_SLP_S3_R_L

TBTAPWRSW_ISET_S0_R

TBT_A_CONFIG2_RC

PP3V3_S5

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3_S4_TBTAPWR

DP_TBTPA_DDC_CLK

VOLTAGE=18V

TBTACONN_20_RC

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1>

DP_TBTPA_AUXCH_C_P

TBT_A_D2R_P<0> TBT_A_D2R_N<0>

DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3>

TBT_A_R2D_C_P<0>

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

TBT_A_R2D_C_N<0>

PP3V3_S4_TBTAPWR

TBT_A_CONFIG1_RC

DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

TBT_A_HPD

DP_TBTPA_ML_P<1> DP_TBTPA_ML_N<1>

DP_TBTPA_AUXCH_N

TBT_A_DP_PWRDN

TBTDP_AUXIO_EN

TBT_A_D2R1_AUXDDC_P

TBT_A_D2R1_AUXDDC_N

TBT_A_CONFIG1_BUF

DP_TBTPA_DDC_DATA

TBT_A_LSTX TBT_A_LSRX

DP_TBTPA_HPD

TBTAPWRSW_ISET_S3_R

DP_TBTPA_AUXCH_P

DP_TBTPA_AUXCH_C_N

TBT_A_D2R_N<1>

TBT_A_D2R_C_P<1>

TBT_A_D2R_P<1>

PP15V_TBT

TBTAPWRSW_ISET_S3

TBTAPWRSW_ISET_S0

S4_PWR_EN TBT_A_HV_EN

TBTAPWRSW_ISET_V3P3

PP3V3RHV_S4_TBTAPWR

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=15V

TBT_A_CIO_SEL

TBT_A_D2R_C_N<1>

<SCH_NUM>

32 OF 118

31 OF 81

31

31 78

78

31 78

78

31 78

78

31

12 14 15 17 18 19 21 32 34 61 64 65

66 69 70 71 81

31

31 78

31

78

31 78

78

30 32 69

78

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

IN IN

OUT

IN IN

V3P3

ISET_V3P3

OUT

THRM

GND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD

IN

OUT

BI

IN

OUT

OUT OUT

OUT

IN IN

BI BI

IN IN

OUT

TB+

LSRX

AUX+

CA_DET

DPMLO+ DPMLO-

HPD

THMPAD

GND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENA

TB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN IN

IN

ML_LANE1P

GND3

GND4

HPD

CONFIG2 GND2

RETURN

AUX_CHN

CONFIG1

ML_LANE3N

ML_LANE3P

AUX_CHP

GND0

DP_PWR

ML_LANE0P

GND1

ML_LANE0N

ML_LANE1N

ML_LANE2N

ML_LANE2P

PORT A

SHIELD PINS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

12V: See

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

IV3P3 1100mA 1030mA 1200mA

TBT: TX_1

514-0876

<RV3P3>

Nominal Min Max

wake from Thunderbolt devices.

15.75V Max

(Both C’s)

DP Dir

TBT Dir

(Both C’s)

on AC-coupled signals.

470k R’s for ESD protection

(Both C’s)

TBT Dir

(0-18.9V)

TBT: TX_0

(0-18.9V)

DP Dir

(Both C’s)

TBT: LSX_R2P/P2R (P/N)

greater than or equal

Low: 0 - 0.8V

High: 2.0 - 5.0V

Sink HPD range:

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1

(IPU) (IPD)

(IPD)

(IPU)

3.3V/HV Power MUX

Single-fault protection

below

ILIM = 40000 / RISET

ISET_Sx with CD3210.

requires two R’s per HV

Single R on ISET_V3P3 OK.

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

Nominal Min Max

For 12V systems:

TBT: RX_0

TBT: Unused

Thunderbolt Connector B

to 100K (DPv1.1a).

down HPD input with

TBT: RX_1

DP Source must pull

V3P3 must be S4 to support

0.01UF

X7R-CERM

0402

10% 50V

C3300

1

2

28 78

0.01UF

X5R-CERM 0201

10% 16V

C3302

1

2

1/20W

201

12

5% MF

R3301

1 2

0.01UF

X7R-CERM 0402

10% 50V

C3301

1

2

1K

MF

201

5%

1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

R3394

1

2

1K

MF 201

5% 1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

R3395

1

2

100K

MF 201

5% 1/20W

R3341

1

2

10UF

CERM-X5R 0402

20%

6.3V

C3386

1

2

0.1UF

X5R-CERM

0201

10% 16V

C3385

1

2

X5R-CERM

0.1UF

0201

10% 16V

C3381

1

2

22UF

X5R-CERM-1

603

6.3V

20%

C3380

1

2

POLY-TANT

CASE-B2-SM

20%

6.3V

CRITICAL

100UF

C3387

1

2

1M

MF

201

5%

1/20W

R3352

1

2

1M

MF 201

5% 1/20W

R3351

1

2

330PF

X7R-CERM

0201

10% 16V

C3394

1

2

330PF

X7R-CERM 0201

10% 16V

C3395

1

2

CRITICAL

FERR-120-OHM-3A

0603

L3300

1 2

28

0.1UF

X5R 402

10% 25V

C3310

1

2

GND_VOID=TRUE

1/20W

5%

201

MF

470K

R3370

1

2

GND_VOID=TRUE

1/20W

5%

201

MF

470K

R3371

1

2

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

C3371

1 2

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

C3370

1 2

28 78

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

C3372

1 2

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

C3373

1 2

GND_VOID=TRUE

1/20W

5%

201

MF

470K

R3373

1

2

GND_VOID=TRUE

1/20W

5%

201

MF

470K

R3372

1

2

CD3211A0RGPR

CRITICAL

QFN

U3310

5

16 4

123

13

15

11 10

9

8

12 14

17

21

19 20

18

6 7

28 33

31 65 66

31 45 66

201

MF

1/20W

1%

36.5K

R3312

1

2

0.1UF

X5R 402

10% 25V

C3311

1

2

X5R-CERM

16V

10%

0201

0.1UF

C3320

1

2

28

33

28

28 78

0.22UF

6.3V

20%

0201

X5R

C3332

1 2

0.22UF

6.3V

20%

0201

X5R

C3333

1 2

28 78

0.1UF

10% 16V X5R-CERM

0201

C3330

1 2

0201

0.1UF

X5R-CERM

10% 16V

C3331

1 2

28 78

X5R

0201

20%

6.3V

0.22UF

C3378

1 2

X5R

0201

20%

6.3V

0.22UF

C3379

1 2

28 78

22.6K

MF 201

1% 1/20W

TBTHV:P15V

R3311

1

2

22.6K

TBTHV:P15V

MF

201

1%

1/20W

R3310

1

2

1/20W

1%

201

MF

22.6K

TBTHV:P15V

R3314

1

2

1/20W

1%

201

MF

22.6K

TBTHV:P15V

R3313

1

2

4.7UF

X5R-CERM

0603

10% 25V

C3315

1

2

GND_VOID=TRUE

25V

10%

0201

X5R-CERM

0.01UF

C3305

1

2

0.01UF

X5R-CERM

0201

10% 25V

GND_VOID=TRUE

C3306

1

2

28

20%

0.47UF

CERM-X5R-1

201

GND_VOID=TRUE

4V

C3374

1 2

20%

0.47UF

CERM-X5R-1

GND_VOID=TRUE

4V 201

C3375

1 2

HVQFN24-COMBO

CRITICAL

CBTL05024

SIGNAL_MODEL=TBT_MUX

U3320

1 2

24

23 22

1816

5

4

10

11

6

20

19

9

21

1712

13

14

157

8

25

3

28 31

28

470K

MF

201

5%

1/20W

R3379

1

2

470K

MF 201

5% 1/20W

R3378

1

2

CERM-X5R-1

20%

0.47UF

4V 201

GND_VOID=TRUE

C3376

1 2

CERM-X5R-1

20%

0.47UF

4V 201

GND_VOID=TRUE

C3377

1 2

F-RT-TH

CRITICAL

MDP-J44

J3200

A18

A16

A4 A6

A20

A1

A7A8

A13A14

A2

A5

A3

A11

A9

A17

A15

A12

A10

A19

S1

S10

S11S2S23

S3S4S5

S6

S7S8S9

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

118S0145

2

R3310,R3313

TBTHV:P12V

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

2

R3311,R3314

TBTHV:P12V

118S0145

Thunderbolt Connector B

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=12/18/2012

TBT_B_HV_EN

PP3V3_S5

TBTBPWRSW_ISET_V3P3

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_S4_TBTBPWR

VOLTAGE=15V

PM_SLP_S3_R_L

S4_PWR_EN

MIN_NECK_WIDTH=0.20 MM

PP3V3_S4_TBTBPWR

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM

TBTBPWRSW_ISET_S3

PP15V_TBT

DP_TBTPB_AUXCH_N

DP_TBTPB_AUXCH_C_P

DP_TBTPB_AUXCH_C_N

VOLTAGE=18V

TBTBCONN_20_RC

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBTBPWRSW_ISET_S3_R TBTBPWRSW_ISET_S0_R

DP_TBTPB_HPD

TBT_B_LSRX

TBT_B_LSTX

DP_TBTPB_DDC_DATA DP_TBTPB_DDC_CLK

TBT_B_CONFIG1_BUF

TBT_B_D2R1_AUXDDC_N TBT_B_D2R1_AUXDDC_P

TBT_B_CIO_SEL TBTDP_AUXIO_EN TBT_B_DP_PWRDN

DP_TBTPB_ML_N<1>

DP_TBTPB_ML_P<1>

TBT_B_HPD

DP_B_LSX_ML_N<1>

DP_B_LSX_ML_P<1>

TBT_B_CONFIG1_RC

DP_TBTPB_AUXCH_P

PP3V3_S4_TBTBPWR

TBT_B_CONFIG1_RC TBT_B_CONFIG2_RC

TBT_B_R2D_C_N<0>

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0>

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_C_P<3>

TBT_B_D2R_N<0>

TBT_B_D2R_P<0>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_P<1>

TBT_B_D2R_N<1> TBT_B_D2R_P<1>

TBT_B_D2R_C_P<1>

TBT_B_D2R_C_N<1>

TBT_B_R2D_P<1> TBT_B_R2D_N<1>

DP_B_LSX_ML_N<1>

TBT_B_R2D_N<0>

TBTBCONN_7_C

VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBT_B_R2D_P<0>

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=15V

PP3V3RHV_S4_TBTBPWR_F

VOLTAGE=18.9V

TBTBCONN_1_C

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBT_B_D2R1_AUXDDC_P

DP_TBTPB_ML_P<3> DP_TBTPB_ML_N<3>

TBT_B_D2R_C_P<0>

TBT_B_D2R1_AUXDDC_N

TBT_B_D2R_C_N<0>

TBT_B_HPD

DP_B_LSX_ML_P<1>

TBTBPWRSW_ISET_S0

<SCH_NUM>

33 OF 118

32 OF 81

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66 69 70 71 81

32

30 31 69

78

32 78

78

32

32 78

32

78

32

78

32 78

78

32 78

78

32 78

78

32

32 78

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w w w . c h i n a f i x . c o m

BI

OUT

BI

OUT

SBI

INB+

VCC

OUTA1+ OUTA1-

OUTA0+ OUTA0-

SAO

OUTB1+ OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

SAI

INB-

GND

THRM

ENB

PAD

BI

IN

BI

IN

SDG

IN

OUT

SDG

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDC Crossbar

Only necessary on dual-port hosts.

NEVER SEND AUXCH THROUGH CROSSBAR!

SAI/SBI = 0: INA == OUTB0, INB == OUTA0

DP++ spec violation, should remove!

2.2k pull-ups are required by PCH to indicate active display interface.

On single-port hosts alias TBTPA_DDC to TBTSNK0_DDC.

Second TBT Port HV Boost Enable

SAI/SBI = 1: INA == OUTA0, INB == OUTB0

32

31

CRITICAL

QFN

TS3DS10224

U3400

16

10

5

2

1

4

3

17

18

19

20

9

8

7

6

14

15

12 11

21

13

12 70

0.1UF

402

CERM

10V

20%

C3480

1

2

2.2K

1%

1/20W

MF

201

R3451

1

2

1% 1/20W MF 201

2.2K

R3452

1

2

201

2.2K

1%

1/20W

MF

R3453

1

2

2.2K

1% 1/20W MF 201

R3454

1

2

SOT-563

DMN5L06VK-7

Q3410

3

5

4

28

30

SOT-563

DMN5L06VK-7

Q3410

6

2

1

28 32

1/16W

1%

402

MF-LF

100K

R3400

1

2

SYNC_MASTER=J15_REFERENCE

SYNC_DATE=11/16/2012

DDC Crossbar

DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_DATA

DP_TBTPA_DDC_DATA

DP_TBTPA_DDC_CLK

DP_TBTSNK0_DDC_CLK

DP_TBTPB_DDC_CLK

TBT_DDC_XBAR_EN_L

TBTBST_PWREN_L

TBT_B_HV_EN

PP3V3_S0

DP_TBTPB_DDC_DATA

TBT_DDC_XBAR_EN

<SCH_NUM>

34 OF 118

33 OF 81

11 12 13 14 15 17 19 20 29 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

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IN

OUT

IN

OUT

IN

OUT

IN

OUT

SYM_VER_2

G S

D

BI BI

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

IN

NC

OUT

GND

VOUTONVIN

IN

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

RESET*

+

-

PAD

(OD)

DLY

VREF

SYM_VER-1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BLUETOOTH

SEL OUTPUT

AIRPORT

516S1016

Max Current = 2A (85C)

1A PEAK

CURRENT SENSE

155S0367

TPS22924C

18.5 mOhm Typ

@ 2.5V

R(on)

Type

Load Switch

25.8 mOhm Max

Part

3.3V WLAN Switch

H USB_BT

Delay = 130 ms +/- 20%

Supervisor & CLKREQ # Isolation

L USB_BT_WAKE

FERR-120-OHM-3A

0603

L3504

1 2

PLACE_NEAR=J3501.1:2.54MM

402

20% 10V

0.1uF

CERM

C3521

1

2

10V

20%

402

CERM

PLACE_NEAR=J3501.1:2.54MM

0.1uF

C3522

1

2

13 76

11 76

PLACE_NEAR=J3501.5:2.54MM

X7R-CERM0402

16V

0.1UF

10%

C3531

1 2

PLACE_NEAR=J3501.4:2.54MM

X7R-CERM0402

16V

0.1UF

10%

C3530

1 2

12 36 71 76

0.01UF

X7R-CERM 0402

16V

10%

C3532

1

2

20

11 18

CERM 402

20% 10V

0.1uF

C3540

1

2

232K

MF-LF 402

1% 1/16W

R3554

1

2

100K

MF-LF 402

1% 1/16W

R3555

1

2

100K

MF-LF 402

1% 1/16W

R3553

1

2

41 42 71

NOSTUFF

X5R-CERM 0201

16V

0.1UF

10%

C3570

1

2

OMIT_TABLE

0201

0.6NH+/-0.1NH-0.85A

L3570

1 2

NOSTUFF

X5R-CERM 0201

16V

0.1UF

10%

C3571

1

2

NOSTUFF

X5R-CERM 0201

16V

0.1UF

10%

C3573

1

2

OMIT_TABLE

0.6NH+/-0.1NH-0.85A

0201

L3571

1 2

NOSTUFF

X5R-CERM 0201

16V

0.1UF

10%

C3572

1

2

NOSTUFF

0201

16V

0.1UF

10% X5R-CERM

C3575

1

2

OMIT_TABLE

0201

0.6NH+/-0.1NH-0.85A

L3573

1 2

X5R-CERM 0201

16V

0.1UF

10%

NOSTUFF

C3574

1

2

NOSTUFF

0201

16V

0.1UF

10% X5R-CERM

C3577

1

2

0201

OMIT_TABLE

0.6NH+/-0.1NH-0.85A

L3574

1 2

16V 0201

10% X5R-CERM

NOSTUFF

0.1UF

C3576

1

2

13 76

34

47

0402-LF

PLACE_NEAR=J3501.18:2.54MM

FERR-120-OHM-1.5A

L3505

12

NO_XNET_CONNECTION=TRUE

DMN32D2LFB4

DFN1006H4-3

Q3510

3

1

2

13 75

15K

MF

1% 1/20W

201

R3512

1

2

SIGNAL_MODEL=MOJO_MUX_USBONLY

CRITICAL

TQFN

PI3USB102EZLE

U3510

6

7

3

4

5

8

10

9

2

1

12 21 38 41 66 68 71

6.3V CERM-X5R 0201

0.1UF

10%

C3510

1

2

39 41 43

CRITICAL

TPS22924

CSP

U3550

C1

C2

A2 B2

A1 B1

34 41 66

SLG4AP041V

TDFN

CRITICAL

U3540

6

5

7

3

8

4

2

9

1

SSD-X29-D1

F-RT-SM

CRITICAL

J3501

19

20

21

1

10 11 12

13 14 15 16 17 18

2 3 4 5 6 7 8 9

CRITICAL

TCM0605-1

90-OHM-50MA

PLACE_NEAR=J3501.7:2.54MM

L3501

1

2 3

4

L3570,L3571,L3573,L3574

RES, 0OHM, 0201

4

117S0201

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

X29C CONNECTOR

PP3V3_WLAN

VOLTAGE=3.3V

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.2 mm

PCIE_AP_D2R_PI_N

PCIE_AP_D2R_PI_P

PM_WLAN_EN

AP_RESET_L

PP3V3_WLAN_F

PM_WLAN_EN

USB_BT_WAKEN

USB_BT_N

SMC_PME_S4_WAKE_L

PCIE_AP_D2R_N

PCIE_AP_R2D_PI_P

PCIE_AP_R2D_PI_N

PCIE_AP_R2D_C_P

PP3V3_S5

AP_CLKREQ_L

P3V3WLAN_VMON

VOLTAGE=3.3V

PP3V3_WLAN_R

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm

PP3V3_WLAN_F

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

PCIE_AP_R2D_C_N

PP3V3_S4

PM_SLP_S4_L

USB_BT_P

PCIE_AP_D2R_P

PP3V3_S4

WIFI_EVENT_L

PCIE_WAKE_L

USB_BT_CONN_P

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_S3RS4_BT_F

VOLTAGE=3.3V

PCIE_AP_R2D_N

PCIE_CLK100M_AP_N

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_CONN_N

PCIE_CLK100M_AP_CONN_P

AP_CLKREQ_Q_L

USB_BT_CONN_N

AP_RESET_CONN_L

PCIE_AP_R2D_P

<SCH_NUM>

35 OF 118

34 OF 81

42 71

71 76

34 41 66

34 47

76

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

20 34 39 42 43 46 47 65 66 68 69 70 71

71 75

71

71 76

71

71 75

71

71 76

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

OUT

IN

NC

08

NC

IN

IN IN

OUT

IN

OUT

NC

08

IN

NC

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

514S0449

GND_VOIDGND_VOID

OOB Isolation

APN 343S0511

Delay = ~55ms

Supervisor & CLKREQ# Isolation

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

Gumstick3 Connector

41

10V X5R-CERM 0201

PLACE_NEAR=L3700.1:1mm

0.1UF

10%

C3702

1

2

PLACE_NEAR=J3700.1:3mm

FERR-26-OHM-6A

0603

CRITICAL

L3700

1 2

PLACE_NEAR=L3700.1:1mm

10V X5R-CERM 0201

0.1UF

10%

C3701

1

2

MF

1%

100K

1/20W 201

R3742

1

2

201

100K

1/20W

MF

5%

R3740

1

2

1% MF

1/20W

232K

201

R3741

1

2

11

CERM-X5R

10%

0.1UF

6.3V 0201

C3740

1

2

20

35 65

SOT891

74LVC1G08

CRITICAL

BYPASS=U3711:5 mm

U3711

2

1

35

6

4

0201

X5R-CERM

10V

0.1UF

10%

C3719

1

2

13 76

16V

0201

GND_VOID=TRUE

X5R-CERM

0.1UF

10%

C3716

1 2

16V

0201X5R-CERM

GND_VOID=TRUE

0.1UF

10%

C3717

1 2

16V

0201X5R-CERM

0.1UF

10%

GND_VOID=TRUE

C3713

1 2

0201

GND_VOID=TRUE

16V

X5R-CERM

0.1UF

10%

C3712

1 2

16V

0201X5R-CERM

0.1UF

10%

GND_VOID=TRUE

C3715

1 2

GND_VOID=TRUE

X5R-CERM

16V

0201

0.1UF

10%

C3714

1 2

16V

X5R-CERM 0201

GND_VOID=TRUE

0.1UF

10%

C3711

1 2

16V

0201X5R-CERM

GND_VOID=TRUE

10%

0.1UF

C3710

1 2

11 76

13 76

35 65

41

20

18

F-RT-SM

TRUE

TRUE TRUE

TRUE

SSD-GS3

TRUE

CRITICAL

TRUE

J3700

1

10 11 12 13 14 15 16

17 18 19

2

20 21 22 23 24 25 26 27 28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

50

51

52

53

54 55 56 57 58

59

6

60 61 62 63

7 8 9

100K

MF

1%

201

1/20W

R3700

1

2

74LVC1G08

CRITICAL

SOT891

U3710

2

1

3 5

6

4

41

10V 0201

X5R-CERM

BYPASS=U3710:5 mm

0.1UF

10%

C3718

1

2

SLG4AP016V

TDFN

CRITICAL

U3740

6

5

7

3

8

4

2

9

1

SYNC_DATE=06/08/2013

SYNC_MASTER=CLEAN_MLB_KEPLER

SSD Connector

SSD_RESET_CONN_L

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_C_P<3>

SSD_RESET_L

PCIE_SSD_R2D_N<0>

PCIE_SSD_R2D_N<3> PCIE_SSD_R2D_P<3>

PCIE_SSD_R2D_P<2>

PCIE_SSD_R2D_P<1>

PCIE_CLK100M_SSD_P

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<3>

SSD_PWR_FET_EN

SMC_PWRFAIL_WARN_L

MIN_LINE_WIDTH=0.6mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.15mm

PP3V3_S0SW_SSD_FLT

SMC_OOB1_R2D_CONN_L

SSD_PWR_FET_EN

MAKE_BASE=TRUE

SSD_PWR_FET_EN

PP3V42_G3H

PP3V3_S0SW_SSD

SSD_PWR_FET_EN SSD_CLKREQ_L

SSD_CLKREQ_CONN_L

P3V3SSD_VMON

SSD_DEVSLP

SMC_OOB1_D2R_CONN_L

SMC_OOB1_R2D_L

PP3V3_S0SW_SSD

PP3V3_S0

PP3V3_S0SW_SSD

SMC_OOB1_D2R_L

PCIE_SSD_D2R_N<1>

PCIE_CLK100M_SSD_N

PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<0>

SSD_PCIE_SEL_L

PCIE_SSD_D2R_N<2>

PP3V3_S0

PCIE_SSD_D2R_P<1>

NC_SSD_MFG_RSVD

PCIE_SSD_R2D_P<0>

PCIE_SSD_R2D_N<2>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_R2D_C_P<0>

<SCH_NUM>

37 OF 118

35 OF 81

76

35 65 35 65

19 38 39 41 42 43 44 50 56 57 66 69 71

35 46 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

35 46 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

76

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

NC NC

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

SYM 1 OF 3

DEBUG_15

DEBUG_14

DDR_PWR_SEL

SENSOR_WAKE*

PCIE_WAKE*

PCIE_CLKREQ*

JTAG_SRST*

JTAG_TRST*

JTAG_TMS

JTAG_TDO

PCIE_REFCLKN

DEBUG_03 DEBUG_04 DEBUG_05

DEBUG_09

PCIE_RDP0

DEBUG_06

DEBUG_00 DEBUG_01 DEBUG_02

DEBUG_07 DEBUG_08

DEBUG_10 DEBUG_11 DEBUG_12 DEBUG_13

DEBUG_16

GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07

I2C_CLK_DBG I2C_CLK_SENSOR I2C_DATA_DBG I2C_DATA_SENSOR

JTAG_TCK JTAG_TDI

MIPI_CP_CLK

PCIE_RDN0

PCIE_REFCLKP

PCIE_RST*

PCIE_TDN0

RESET*

SHUTDOWN*

UARTCTS UARTRTS

UARTRXD UARTTXD

XTAL_N

XTAL_P

MIPI_DM0

MIPI_DP0

MIPI_CM_CLK

PCIE_TDP0

PCIE_TESTN

MIPI_DP1 MIPI_DM1

STRAP_XTAL_FREQ

STRAP_XTAL_SEL

TEST_OUT

TEST_MODE

PCIE_TESTP

SYM 2 OF 3

DDR_CK_N0

DDR_CK_P0

DDR_CAS*

DDR_RAS*

DDR_CKE

DDR_AD00 DDR_AD01 DDR_AD02 DDR_AD03 DDR_AD04 DDR_AD05 DDR_AD06 DDR_AD07 DDR_AD08 DDR_AD09 DDR_AD10 DDR_AD11 DDR_AD12 DDR_AD13 DDR_AD14

DDR_BA0 DDR_BA1 DDR_BA2

DDR_CS*

DDR_DM0 DDR_DM1

DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15

DDR_DQS_N0

DDR_DQS_N1

DDR_DQS_P0

DDR_DQS_P1

DDR_RESET*

DDR_WE*

DDR_ZQ

SR_VLXD_O

VDD_1P35A

PCIE_GND

XTAL_AVDD1P2

VDDC

VDD1P8_O

SR_VLXC_O

SR_VDD_3P3D

SR_VDD_3P3C

SR_PVSSD

SR_PVSSC

PMU_AVSS

OTP_VDD3P3

DDR_VDDIO_CK

MIPI_AGND

VDD_3P3A

DDR_VREF_O

VSSC

XTAL_AVSS

DDR_VDDIO

PCIE_VDD1P2

VSENSE_D

VSENSE_C

PCIE_PVDD1P2

DDR_AVDD1P8

MIPI_AVDD1P8

PLL_VDD1P8

VDD1P2_O

VDDO18

SYM 3 OF 3

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

BI BI BI

BI BI

OUT OUT OUT

IN

OUT

IN

OUT

NC NC NC NC

NC

NC NC NC

NC NC NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

L3901:1 L3902:1

A1 SILICON BUG

PU = 25MHz

(=PP3V3_S3RS0_CAMERA)

PD = 1.35V

PU on PCH page

11

37

37 71

5%

201

1/20W MF

100K

NOSTUFF

R3930

1

2

5%

201

MF

1/20W

100K

NOSTUFF

R3932

1

2

13 18

20

6.3V CERM-X5R 0201

0.1UF

10%

C3900

1

2

0201

6.3V CERM-X5R

0.1UF

10%

C3924

1

2

20%

1.0UF

0201-1

6.3V X5R

C3923

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C3922

1

2

20%

1.0UF

0201-1

6.3V X5R

C3921

1

2

BYPASS=U3900.D6:2.54MM

6.3V CERM-X5R 0201

0.1UF

10%

C3910

1

2

BYPASS=U3900.D6:2.54MM

6.3V CERM-X5R 0201

0.1UF

10%

C3951

1

2

5%

201

1/20W MF

100K

R3901

1

2

37

37 76

5%

201

1/20W MF

100K

CAM_XTAL:YES

R3906

1

2

5%

201

1/20W MF

100K

CAM_XTAL:NO

R3907

1

2

5%

201

1/20W MF

100K

R3904

1

2

1008

1.0UH-1.6A-55MOHM

PLACE_NEAR=U3900.M13:4MM

L3901

1 2

1008

PLACE_NEAR=U3900.K13:4MM

1.0UH-1.6A-55MOHM

L3902

1 2

BYPASS=U3900.K13:2.54MM

4.7UF

20%

402

6.3V X5R

C3912

1

2

402

20%

4.7UF PLACE_NEAR=U3900.M13:2.54MM

6.3V

X5R

C3915

1

2

0402

22NH

L3906

1 2

BYPASS=U3900.L7:2.54MM

6.3V CERM-X5R 0201

0.1UF

10%

C3916

1

2

4.7UF

20%

402

6.3V X5R

C3928

1

2

PLACE_NEAR=U3900.M14:2.54MM

4.7UF

20%

402

6.3V X5R

C3926

1

2

BYPASS=U3900.J1:2.54MM

6.3V CERM-X5R 0201

0.1UF

10%

C3919

1

2

BYPASS=U3900:5mm

6.3V CERM-X5R 0201

0.1UF

10%

C3937

1

2

BYPASS=U3900:5mm

6.3V CERM-X5R 0201

0.1UF

10%

C3935

1

2

BYPASS=U3900:5mm

6.3V CERM-X5R 0201

0.1UF

10%

C3940

1

2

20%

402

4.7UF

BYPASS=U3900:7mm

6.3V X5R

C3942

1

2

CERM 402-LF

20%

2.2UF

BYPASS=U3900.F15:2.54MM

6.3V

C3941

1

2

402

10V

1UF

BYPASS=U3900.G15:2.54MM

X5R

10%

C3939

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C3960

1

2

CRITICAL

BCM15700

OMIT_TABLE

FBGA

U3900

G12

B11 C14 B14 A15 E11 E10 F11 F10 G11 G10 H11 H10 J10 K11 K10 L11 L10

R12 P12 P11 P10 P9 N11 N10 N9

D15 R10 C15

R9

C11

F13 E12 F12 D12 D11

R7

P7

R8

R6

P8

P6

P13

A7

B7

A10

B10

R14

B8

A8

C9

B9

N12

E15 R13 H12

C13

C12

M10

J12

D13 D14

E13 E14

A12

A13

OMIT_TABLE

FBGA

CRITICAL

BCM15700

U3900

L3 M4 N3 M3 M1 M2 P4 N2 P3 P2 J4 R2 L1 P1 R4

K3 L2 K2

H4

G2

H2

J3 L4

C1 C4

C2 E3 E4 D3 F3 F1 F4 F2 B5 C3 B1 B4 A5 C5 B2 B3

D2

A3

E2

A2

H3

R3

J2

G3

OMIT_TABLE

FBGA

BCM15700

CRITICAL

U3900

J1

A4 D4 G4 K4 N4

G5

N5

N7 N8 N6

L7

D7

C10

C7

D9

C8

D6

G14 M12

N13 P14 P15 R15

K15 L12 L13 L14 L15

M14 M15 N15

H14 H15 J13 J14 J15

M13 N14

K13 K14

F15

G15

F14

J11

F6 F7 F8 F9 L6 L5 L8 L9

B15

R11

M11 K12

A1 A6

G9 H5 H6 H7 H8 H9 J5 J6 J7 J8

B6

J9 K1 K5 K6 K7 K8 K9

A14

M9 N1

D1

P5 R1 R5

E9

D5 E5 G1 G6 G7 G8

B13

B12

0201

16V

1000PF

X7R-CERM

BYPASS=U3900.J1:2.54MM

10%

C3918

1

2

0201

BYPASS=U3900:3mm

16V

1000PF

X7R-CERM

10%

C3934

1

2

0201

X7R-CERM

1000PF

16V

BYPASS=U3900.L7:2.54MM

10%

C3917

1

2

BYPASS=U3900:3mm

X7R-CERM

1000PF

16V 0201

10%

C3936

1

2

BYPASS=U3900.D7:2.54MM

X7R-CERM

1000PF

16V 0201

10%

C3938

1

2

37 79

37

5%

201

1/20W MF

100K

NO STUFF

R3910

1

2

5%

201

1/20W MF

100K

R3911

1

2

201

1/20W

MF

240

1%

R3912

1 2

5%

201

1/20W

MF

1K

R3913

1

2

5%

201

1/20W

MF

1K

R3914

1

2

37 79

SM

XW3900

1 2

SM

XW3901

1 2

5%

201

1/20W MF

100K

R3990

1

2

NOSTUFF

6.3V CERM-X5R 0201

0.1UF

10%

C3990

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C3927

1

2

0201-1

20%

1.0UF

6.3V X5R

C3930

1

2

37 79

0201-1

1.0UF

20%

6.3V X5R

C3932

1

2

20%

10UF

4V 402

X5R

C3931

1

2

402

10UF

20% 4V X5R

C3933

1

2

5%

201

1/20W MF

100K

CAM_A1

R3915

1

2

4.7UF

20%

402

6.3V X5R

C3914

1

2

402

20%

4.7UF

6.3V X5R

C3913

1

2

0603

220-OHM-1.4A

L3903

1 2

0603

220-OHM-1.4A

L3904

1 2

5%

0

0201

1/20W

MF

NOSTUFF

R3991

1 2

12 34 71 76

BYPASS=U3900.L9:2.54MM

6.3V CERM-X5R 0201

0.1UF

10%

C3975

1

2

6.3V CERM-X5R 0201

0.1UF

10%

BYPASS=U3900.L9:2.54MM

C3974

1

2

0201

X7R-CERM

1000PF

16V

BYPASS=U3900.F9:2.54MM

10%

C3973

1

2

BYPASS=U3900.F9:2.54MM

6.3V

0.1UF

10% 0201

CERM-X5R

C3972

1

2

X7R-CERM

1000PF

16V 0201

BYPASS=U3900.F6:2.54MM

10%

C3971

1

2

BYPASS=U3900.F6:2.54MM

6.3V CERM-X5R 0201

0.1UF

10%

C3970

1

2

5%

201

1/20W MF

51K

R3975

1

2

5%

201

1/20W MF

51K

R3976

1

2

5%

201

1/20W MF

100K

R3920

1

2

5%

201

1/20W MF

100K

R3921

1

2

5%

201

1/20W MF

100K

NOSTUFF

R3934

1

2

330K

MF

1/20W 201

5%

R3931

1

2

330K

MF

1/20W 201

5%

R3933

1

2

330K

MF

1/20W 201

5%

R3935

1

2

5%

201

1/20W

MF

NOSTUFF

100K

R3936

1

2

5%

201

1/20W

MF

100K

NOSTUFF

R3937

1

2

37 79

SYNC_DATE=06/13/2013

Camera 1 of 2

SYNC_MASTER=CLEAN_MLB_KEPLER

CAM_RAMCFG0

CAM_RAMCFG1

PP1V8_CAM

PCIE_CAMERA_R2D_N

PP1V2_CAM

P1V35_CAM_SRVLXD_PHASE

TP_CAM_LV_JTAG_TMS

TP_CAM_LV_JTAG_TDO

TP_CAM_LV_JTAG_TDI

TP_CAM_LV_JTAG_TCK

TP_CAM_TEST_MODE2

TP_CAM_TEST_MODE1

TP_CAM_TEST_MODE0

TP_CAM_LV_JTAG_TRSTN

GND_CAM_PVSSC

MEM_CAM_A<14>

MEM_CAM_A<13>

PP1V2_CAM_XTALPCIEVDD

MEM_CAM_A<12>

MEM_CAM_BA<0>

PP3V3_S3RS0_CAMERA

PCIE_CLK100M_CAMERA_C_P

PP1V8_CAM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=1.8V

PP1V2_CAM_XTALPCIEVDD

PP1V2_CAM_PCIE_VDD_FLT

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

GND_CAM_PVSSD

PP1V8_CAM

CAM_GPIO3

PP1V8_CAM

P1V2_CAM_SRVLXC_PHASE

CAM_RAMCFG2

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP1V35_CAM

VOLTAGE=1.35V

CAM_RAMCFG0

CAM_XTAL_SEL

CAM_XTAL_FREQ

CAM_TEST_MODE

CAM_TEST_OUT

CAM_UARTCTS TP_CAM_UARTRTS

CAM_UARTRXD TP_CAM_UARTTXD

CAM_RAMCFG1

I2C_CAM_SMBDBG_DAT

I2C_CAM_SMBDBG_CLK

MIPI_CLK_N

MIPI_CLK_P

GND_CAM_PVSSC

VOLTAGE=1.2V

PP1V2_CAM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V8_CAM

MIN_NECK_WIDTH=0.2MM

PP1V2_CAM_XTALPCIEVDD

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM

VOLTAGE=1.2V

PP1V35_CAM

PP1V2_CAM

PP1V2_CAM_PCIE_PVDD_FLT

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=1.2V

PP0V675_CAM_VREF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0.675V

PP1V35_DDR_CLK

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=1.35V

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V2_CAM_SRVLXC_PHASE

P1V35_CAM_SRVLXD_PHASE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

MEM_CAM_ZQ_S2

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3>

MEM_CAM_A<5>

MEM_CAM_A<4>

MEM_CAM_A<6> MEM_CAM_A<7> MEM_CAM_A<8>

MEM_CAM_A<10>

MEM_CAM_A<9>

MEM_CAM_A<11>

MEM_CAM_BA<1> MEM_CAM_BA<2>

MEM_CAM_CLK_P MEM_CAM_CLK_N

MEM_CAM_DM<0> MEM_CAM_DM<1>

MEM_CAM_CKE MEM_CAM_CS_L

MEM_CAM_DQ<15>

MEM_CAM_DQ<14>

MEM_CAM_DQ<13>

MEM_CAM_DQ<12>

MEM_CAM_DQ<11>

MEM_CAM_DQ<10>

MEM_CAM_DQ<9>

MEM_CAM_DQ<8>

MEM_CAM_DQ<7>

MEM_CAM_DQ<6>

MEM_CAM_DQ<5>

MEM_CAM_DQ<4>

MEM_CAM_DQ<3>

MEM_CAM_DQ<2>

MEM_CAM_DQ<1>

MEM_CAM_DQ<0>

CAM_JTAG_SRST_L

CAMERA_PWR_EN

CAM_SENSOR_WAKE_L

TP_CAM_JTAG_TMS

TP_CAM_JTAG_TDI TP_CAM_JTAG_TDO

TP_CAM_JTAG_TRST_L CAM_JTAG_SRST_L

TP_CAM_JTAG_TCK

I2C_CAM_SMBDBG_DAT

I2C_CAM_SMBDBG_CLK

MIPI_DATA_N

MIPI_DATA_P

PCIE_CAMERA_R2D_P

PCIE_CAMERA_D2R_C_N

PCIE_CAMERA_D2R_C_P

PP1V8_CAM

CAM_DEBUG_RESET_L

CAM_PWR_SEL

CAM_XTAL_SEL

PP1V8_CAM

CAM_XTAL_FREQ

GND_CAM_PVSSD

CAM_UARTCTS CAM_UARTRXD

CLK25M_CAM_CLKP CLK25M_CAM_CLKN

CAMERA_CLKREQ_L

PCIE_CLK100M_CAMERA_C_N

MEM_CAM_DQS_P<0> MEM_CAM_DQS_N<0>

MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1>

MEM_CAM_RAS_L MEM_CAM_WE_L MEM_CAM_CAS_L MEM_CAM_RESET_L

CAM_TEST_MODE

PP1V8_CAM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

GND_CAM_PVSSD

PCIE_WAKE_L

GND_CAM_PVSSC

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

CAM_TEST_OUT

CAM_PCIE_RESET_L CAM_PCIE_WAKE_L

PP1V2_CAM_XTALPCIEVDD

CAM_RAMCFG2

I2C_CAM_SCK

I2C_CAM_SDA

<SCH_NUM>

39 OF 118

36 OF 81

36

36 37

36

19 36

13 47 69

19 36

36

36 37

36

36 37 79

36

19 36

36 37 79

36

37 79

36

36 37

36

36 37

36

36 37

36

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

OUT

IN

BI

IN

BI

SYM_VER-1

BI IN

A4

A14

DQSL*

DQL1

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

DQL7

DQL4

DQL3

DQL2

DQL0

ZQ

DQU3

DQU2

DQU4

CS*

CKE

DQU7

DQU6

DQSU*

DQU0

DQSL

A13

A11

A10/AP

A8

A5

A7

A9

CK

DML DMU

DQL5 DQL6

DQSU

DQU1

DQU5

VREFCA

VREFDQ

CK*

WE*

VDDQ

A12/BC*

NC NC NC NC NC

BI BI BI BI BI BI BI BI

BI BI

IN IN

BI BI BI BI BI BI BI BI

IN

IN IN IN

IN

IN IN IN IN IN IN IN IN IN IN IN IN IN IN

IN IN IN

IN

NC NC

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: TBD PPM crystal required

remove DRAM SPD Straps

1

0

CFG 0

0 1

CFG 1

MICRON

SAMSUNG

HYNIX

VENDOR

1

0 1

1

CFG 2

A

ELPIDA

DIE REV

DRAM CFG Chart

96.2 mA peak

77.2 mA nominal max

ALS

CAMERA SENSOR

518S0892

B

36 76

13 76

X5R-CERM 0201

16V

0.1UF

10%

C4033

1 2

X5R-CERM 0201

16V

0.1UF

10%

C4032

1 2

16V

0201X5R-CERM

0.1UF

10%

C4031

1 2

16V

0201X5R-CERM

0.1UF

10%

C4030

1 2

13 76

36 76

NO STUFF

MF

1/20W

0201

0

5%

R4009

1 2

NO STUFF

MF

1/20W

0201

0

5%

R4010

1 2

MF

1/20W

020105%

R4008

1 2

CAM_XTAL:YES

MF

1/20W

020105%

R4007

1 2

5%

0

0201

1/20W

MF

R4000

1 2

201

0.47UF

CERM-X5R-1

4V

20%

BYPASS=U4000.H9:4mm

C4004

1

2

10V

2.2UF

20% X5R-CERM

402

BYPASS=U4000.K2:4mm

C4008

1

2

20% 10V X5R-CERM 402

2.2UF

BYPASS=U4000.D2:4mm

C4006

1

2

1M

1%

NOSTUFF

MF

1/20W 201

R4012

1

2

NP0-C0G-CERM

25V

CAM_XTAL:YES

12PF

0201

5%

C4015

1 2

0201

25V

NP0-C0G-CERM

12PF

CAM_XTAL:YES

5%

C4014

1 2

10%

0.1UF

0201

CERM-X5R

6.3V

C4009

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U4000.R9:4mm

C4007

1

2

0.1uF

10V

CERM

402

20%

C4013

1

2

36 71

10%

0.1UF

0201

CERM-X5R

6.3V

C4005

1

2

36 79

0402-LF

FERR-120-OHM-1.5A

L4010

12

X5R

10UF

4V

20%

402

BYPASS=U4000.B2:4mm

C4003

1

2

X5R

10UF

402

20% 4V

BYPASS=U4000.A1:4mm

C4002

1

2

CRITICAL

90-OHM-50MA

TCM0605-1

PLACE_NEAR=J4002.2:2.54MM

L4009

1

2 3

4

CRITICAL

TCM0605-1

90-OHM-50MA

PLACE_NEAR=J4002.5:2.54MM

L4007

1

2 3

4

41 44 48 71 80

201

1/20W

MF

1K

1%

R4022

1

2

201

1/20W

MF

1K

1%

R4023

1

2

4GB-DDR3-256MX16

K4B4G1646B-HYK0

CRITICAL

OMIT_TABLE

FBGA

U4000

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

F3 G3

C7 B7

D7 C3 C8 C2 A7 A2 B8 A3

J1 J9 L1 L9 M7

K1

J3

T2

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

36 79

10%

0.1UF

0201

CERM-X5R

6.3V

C4011

1

2

36 79

10%

0.1UF

0201

CERM-X5R

6.3V

C4010

1

2

36 79

36

36 79

201

1/20W MF

84.5

1%

R4020

1

2

36 79

201

1/20W MF

NO STUFF

82

1%

R4021

1

2

36 79

5%

201

1/20W

MF

1K

R4002

1

2

5%

201

1/20W

MF

NOSTUFF

1K

R4003

1

2

201

1/20W MF

240

1%

R4004

1

2

5%

0

0201

1/20W

MF

CAM_WAKE:YES

R4030

1 2

25V

100PF

0201

NP0-CERM

5%

C4016

1

2

5%

0

0201

1/20W

MF

CAM_WAKE:NO

R4031

1

2

CCR20-AK7100-1

F-RT-SM

CRITICAL

J4002

14

13

1

10 11 12

2 3 4 5 6 7 8 9

X5R-CERM 0201

16V

0.1UF

10%

C4061

1 2

X5R-CERM 0201

16V

0.1UF

10%

C4062

1 2

0402-LF

FERR-120-OHM-1.5A

NOSTUFF

L4011

12

5%

NO STUFF

100PF

0201

NP0-CERM

25V

R4006

1

2

36 79

CAM_XTAL:YES

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

CRITICAL

Y4000

24

13

36

36 76

11 76

5%

201

1/20W MF

100K

R4005

1

2

19 75

Camera 2 of 2

SYNC_MASTER=CLEAN_MLB_KEPLER

SYNC_DATE=06/13/2013

MEM_CAM_CKE

PP5V_S3

MIPI_CLK_CONN_N MIPI_CLK_CONN_P

PP0V675_MEM_CAM_VREFCA

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PP0V675_MEM_CAM_VREFDQ

PP0V675_CAM_VREF

MEM_CAM_CKE_R

MEM_CAM_A<5>

MEM_CAM_A<4>

MEM_CAM_WE_L

MEM_CAM_CS_L

MEM_CAM_CAS_L

MEM_CAM_RAS_L

MEM_CAM_BA<0>

MEM_CAM_A<12>

MEM_CAM_A<9> MEM_CAM_A<10>

MEM_CAM_A<8>

MEM_CAM_A<7>

MEM_CAM_A<1> MEM_CAM_A<2>

MEM_CAM_DQ<13>

MEM_CAM_DQ<9>

MEM_CAM_DQS_P<1>

MEM_CAM_DQ<6>

MEM_CAM_DQ<5>

MEM_CAM_DM<1>

MEM_CAM_DQS_P<0>

MEM_CAM_DQS_N<1>

MEM_CAM_DQ<14> MEM_CAM_DQ<15>

MEM_CAM_DQ<12>

MEM_CAM_DQ<10> MEM_CAM_DQ<11>

MEM_CAM_DQ<0>

MEM_CAM_DQ<2> MEM_CAM_DQ<3> MEM_CAM_DQ<4>

MEM_CAM_DQ<7>

MEM_CAM_DQ<1>

MEM_CAM_DQS_N<0>

MEM_CAM_DM<0>

MEM_CAM_A<6>

MEM_CAM_A<0>

MEM_CAM_A<3>

MEM_CAM_RESET_L

MEM_CAM_ZQ_DDR

MEM_CAM_A<11>

MEM_CAM_BA<1>

MEM_CAM_DQ<8>

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

PP5V_S3RS0_ALSCAM_F

PP5V_S0

CAM_SENSOR_WAKE_L_CONN

SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SCL I2C_CAM_SCK I2C_CAM_SDA

MIPI_DATA_CONN_N MIPI_DATA_CONN_P

MIPI_DATA_N

MIPI_DATA_P

MIPI_CLK_N

MIPI_CLK_P

MEM_CAM_CLK_N

MEM_CAM_BA<2>

MEM_CAM_CLK_P

MEM_CAM_ODT

MEM_CAM_A<13> MEM_CAM_A<14>

PP1V35_CAM

CLK25M_CAM_CLKP

CLK25M_CAM_XTALN

CLK25M_CAM_CLKN

SYSCLK_CLK25M_CAMERA

CLK25M_CAM_XTALP_R

CLK25M_CAM_XTALP

PCIE_CAMERA_R2D_P

PCIE_CAMERA_R2D_N

PCIE_CAMERA_D2R_P

PCIE_CAMERA_D2R_N

PCIE_CLK100M_CAMERA_C_P

PCIE_CLK100M_CAMERA_C_N

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_D2R_C_P

PCIE_CAMERA_R2D_C_N

PCIE_CLK100M_CAMERA_P

PCIE_CAMERA_D2R_C_N

PCIE_CLK100M_CAMERA_N

PP1V8_CAM

CAM_SENSOR_WAKE_L_CONN

CAM_SENSOR_WAKE_L

<SCH_NUM>

40 OF 118

37 OF 81

21 60 65 66 69 71

71 79

79

36 79

71

18 19 49 50 58 59 62 63 65 66 69 70 71

37 71

71 79

79

36 79

36

37 71

36

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

OUT

IN

SYM_VER-1

GND

VBUS

SSTX+

SSRXGND

SSTX-

D+

D-

GND SXRX+

BI

IN

OUT

IN

OUT

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

FAULT*

IN_1

IN_0

ILIM

OUT1

OUT2

EN

GND

THRM

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

USB/SMC Debug Mux

SEL=0 Choose SMC

CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX

Place L4605 and L4615 at connector pin

Left USB Port A

SEL=1 Choose USB

We can add protection to 5V if we want, but leaving NC for now

USB Port Power Switch

514-0934

13 75

FERR-120-OHM-3A

0603

CRITICAL

L4605

1 2

16V10%

0201

X5R-CERM

0.1UF

GND_VOID=TRUE

C4611

1 2

16V10%

0201

X5R-CERM

0.1UF

GND_VOID=TRUE

C4610

1 2

CRITICAL

TCM0605-1

90-OHM-50MA

L4600

1

2 3

4

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D4611

1

2

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

D4610

1

2

TSSLP-2-1

ESD0P2RF-02LS

CRITICAL

D4613

1

2

CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

D4612

1

2

6.3V

20%

CASE-B2-SM1

POLY-TANT

220UF-35MOHM

CRITICAL

C4696

1

2

1/16W

402

MF-LF

22.1K

1%

R4600

1

2

1%

22.1K

MF

1/20W

201

R4601

1

2

NOSTUFF

MF

1/20W

0201

0

5%

R4651

1 2

NOSTUFF

MF

1/20W

0201

0

5%

R4652

1 2

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D4600

1

2

TSSLP-2-1

CRITICAL

ESD0P2RF-02LS

D4601

1

2

CRITICAL

F-RT-TH

USB3.0-J44-ALT

J4600

5 6

4

7

10

11

20 21 22 23

12 13 14 15 16 17 18 19

9

3

2

8

1

603

6.3V

20% X5R

10UF

C4695

1

2

20% 402

CERM

0.1UF

10V

C4691

1

2

13 75

0.1UF

CERM

20% 10V

402

C4650

1

2

100K

1/16W MF-LF 402

5%

R4650

1

2

41 42 75

41

16V

20%

0402

X7R-CERM

0.01UF

C4605

1

2

18

X5R

10UF

20%

6.3V 603

C4690

1

2

MF-LF

402

1/16W

0

5%

R4690

1

2

NOSTUFF

0.47UF

10V X5R

0402

10%

C4692

1

2

CRITICAL

SIGNAL_MODEL=MOJO_MUX_USBONLY

PI3USB102EZLE

TQFN

U4650

6

7

3

4

5

8

10

9

2

1

SON

TPS2557DRB

CRITICAL

U4600

4

8

1

5

2 3

6 7

9

SYNC_MASTER=J15_MLB

USB 3.0 CONNECTORS

SYNC_DATE=10/31/2012

USB_LT1_N

USB3_EXTA_R2D_N

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_P

USB3_EXTA_R2D_C_N

USB3_EXTA_R2D_P

USB_LT1_P

USB_EXTA_MUXED_N

USB_EXTA_MUXED_P

SMC_DEBUGPRT_TX_L

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

PP5V_S3_LTUSB_A_F

MIN_LINE_WIDTH=0.5 mm

SMC_DEBUGPRT_RX_L

USB_EXTA_OC_L

USB_ILIM

USB_ILIM_R

PM_SLP_S4_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_LTUSB_A_ILIM

PP3V42_G3H

USB_PWR_EN

PP5V_S4

USB_EXTA_P

SMC_DEBUGPRT_EN_L

USB_EXTA_N

<SCH_NUM>

46 OF 118

38 OF 81

75

12 21 34 41 66 68 71

19 35 39 41 42 43 44 50 56 57 66 69 71

51 61 65 66 67 68 69 71

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NC

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSSD+D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER2)

P0_1

OUT

NC

NC NC

NC

IN

SDG

OUT

VDD

OUT_1

GND

THRM

OE

OUT_ALL#

OUT_3

OUT_2

IN_1

IN_3

IN_2

(IPD)

PAD

IN

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

337S4426

- KEYBOARD SCANNER

- USB INTERFACES TO MLB

- SPI HOST TO Z2

- TRACKPAD PICK BUTTONS

LID OPEN => SMC_LID_LC ~ 3.42V

WHEN THE LID IS CLOSED

THE TPAD BUTTONS WILL BE DISABLE

518S0752

Keyboard Connector

Pull-up in U5110.

PIN NAME

ISSP SCLK/I2C SCL

ISSP SDATA/I2C SDA

(PP3V3_S3_PSOC)

36E-3 W

16.32E-6 W

POWERV_SNS

0.204 V

0.0255 V

0.6 V

75.2E-6 W

0.72E-3 W 96E-6 W

294E-6 W

0.012 V

0.021 V

0.0188 V

R_SNS

2.55 KOHM

0.2 OHM

1.5 OHM

10 OHM

4.7 OHM

60MA (MAX)

10UA 80UA

CURRENT

V+

VDD

IC

14MA (MAX)

8MA (TYP)

60MA (MAX)

VDD

VOUT

18V BOOSTER

TMP102

3V3 LDO

PSOC

516S0689

VIN

4MA (MAX)

0.255E-6 W

PSOC USB CONTROLLER

LID CLOSE => SMC_LID_LC < 0.50V

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

PLACE THESE COMPONENTS CLOSE TO J5800

TPAD Buttons Disable

IPD Flex Connector

No IPD on OE input pin PP3V3_S4 (symbol error).

Keys ANDed with PSoC power to isolate when PSoC is not powered.

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

SMC Manual Reset & Isolation

BYPASS=U5701.22:19:5 mm

NP0-CERM 0201

25V

5%

100PF

C4802

1

2

10%

6.3V CERM-X5R

0.1UF

0201

BYPASS=U5701.22:19:8 mm

C4803

1

2

BYPASS=U5701.22:19:11 mm

6.3V

20% X5R

402

4.7UF

C4801

1

2

MLF-1

CY8C24794

OMIT

CRITICAL

U4801

20

21

45544653475248

51

25182617271628

15

412

421

435644

55

3310

349

358

367

376

385

394

403

2914

3013

3112

3211

24

235722 49

19

50

34 41 43

1.5

MF-LF

1/16W

5%

402

PLACE_SIDE=BOTTOM

R4804

2 1

1/20W

MF

220K

201

5%

R4803

1

2

BYPASS=U5701.49:50:5 mm

0201

100PF

5% NP0-CERM

25V

C4804

1

2

10%

6.3V

0.1UF

BYPASS=U5701.49:50:8 mm

CERM-X5R 0201

C4805

1

2

BYPASS=U5701.49:50:11 mm

6.3V

20% X5R

4.7UF

402

C4806

1

2

0201

10V

10%

0.1UF

X5R-CERM

PLACE_NEAR=L4807.1:2MM

C4807

1

2

FERR-120-OHM-1.5A

0402-LF

PLACE_NEAR=J5800.18:3MM

L4807

1 2

0201

1/20W

MF

5%

0

R4808

1 2

NOSTUFF

0201

0.1UF

CERM-X5R

6.3V

10%

C4808

1

2

49.9K

1% MF

1/20W

201

R4800

1

2

CRITICAL

55560-0228

M-ST-SM

J4800

1

10

1112 1314 1516 1718 19

2

20

2122

34 56 78 9

41 42 43 71

DMN5L06VK-7

SOT-563

CRITICAL

Q4801

6

2

1

42

0.1UF

X7R-CERM

BYPASS=U4850.10:5:5 mm

0402

16V

10%

C4850

1

2

41 42 71

CERM

0.1UF

402

10V

20%

PLACE_NEAR=J4813.5:5MM

C4810

1

2

MF-LF

402

1/16W

5%

1K

R4810

1 2

402

1/16W MF-LF

0

5%

R4815

1 2

113

MF-LF

402

1/16W

1%

R4814

1 2

F-RT-SM

CRITICAL

FF14A-30C-R11DL-B-3H

J4813

31

32

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

TQFN

SLG4AP4103

U4850

5

1

2

3

4

9

8

7

6

11

10

1/20W

24

MF

5%

201

R4802

1 2

1/20W

MF

24

201

5%

R4801

1 2

66

SYNC_MASTER=CHANG_J45

SYNC_DATE=03/15/2013

KEYBOARD/TRACKPAD (1 OF 2)

PP3V42_G3H

Z2_KEY_ACT_L

MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM

PP3V3_TPAD_CONN

Z2_MISO PICKB_L

Z2_CS_L

SMC_LID

BUTTON_DISABLE

PP3V3_S4

WS_KBD23 WS_KBD22 WS_KBD21

SMBUS_SMC_2_S3_SDA

PP5V_S5

PSOC_SCLK

PSOC_F_CS_L

PSOC_MISO PSOC_MOSI

Z2_CLKIN

Z2_HOST_INTN

WS_KBD4

WS_KBD20 WS_KBD19 WS_KBD18

WS_KBD5

TP_P7_7

Z2_CLKIN

TP_ISSP_SDATA_P1_0

WS_KBD6

TP_PSOC_SDA

TP_PSOC_SCL

TP_ISSP_SCLK_P1_1

TP_PSOC_P1_3

Z2_HOST_INTN WS_LEFT_SHIFT_KEY

BUTTON_DISABLE

PP3V3_S4

WS_KBD17 WS_KBD16N

WS_KBD14

WS_KBD15_C

WS_KBD12

WS_KBD13

WS_KBD11 WS_KBD10 WS_KBD9 WS_KBD8

WS_KBD3

USB_TPAD_R_N

USB_TPAD_R_P

WS_CONTROL_KEY Z2_KEY_ACT_L

PSOC_MISO PSOC_F_CS_L PSOC_MOSI PSOC_SCLK Z2_MISO Z2_CS_L

Z2_SCLK

Z2_MOSI

TPAD_VBUS_EN

USB_TPAD_P

USB_TPAD_N

WS_LEFT_SHIFT_KEY

PP3V3_S4

WS_CONTROL_KEY

WS_LEFT_OPTION_KEY

WS_LEFT_SHIFT_KBD

WS_CONTROL_KBD

WS_LEFT_OPTION_KBD

PP3V3_S4

WS_KBD15_CAP WS_KBD16_NUM

WS_KBD8

WS_KBD7

WS_CONTROL_KBD

WS_LEFT_OPTION_KBD

WS_LEFT_SHIFT_KBD

WS_KBD23

WS_KBD22

WS_KBD19 WS_KBD20 WS_KBD21

WS_KBD11

WS_KBD13 WS_KBD14

WS_KBD18

WS_KBD6

WS_KBD5

WS_KBD4

WS_KBD3

WS_KBD2

WS_KBD1

WS_KBD15_C

SMC_ONOFF_L

WS_KBD_ONOFF_L

WS_LEFT_OPTION_KEY

WS_KBD7 WS_KBD1 WS_KBD2

Z2_MOSI

SMC_TPAD_RST_L

Z2_SCLK

SMC_PME_S4_WAKE_L PICKB_L

PP5V_S5_CUMULUS

VOLTAGE=5V

MIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.20MM

SMBUS_SMC_2_S3_SCL

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V

PP3V3_S3_PSOC

WS_KBD16N

WS_KBD17

PP3V42_G3H

WS_KBD12

WS_KBD10

WS_KBD9

39 OF 81

<SCH_NUM>

48 OF 118

19 35 38 39 41 42 43 44 50 56 57 66 69 71

39 71

39 71 39 71

39 71

39

20 34 39 42 43 46 47 65 66 68 69 70 71

39 71

41 44 71 80

61 65 69 71

39 71

39

20 34 39 42 43 46 47 65 66 68 69 70 71

39 71

39

39 71

39

39 71

75

39

39 71

13 75

39

20 34 39 42 43 46 47 65 66 68 69 70 71

39

39 71

20 34 39 42 43 46 47 65 66 68 69 70 71

71

39 71

39

71

39

39 71

41 44 71 80

39

39 71

19 35 38 39 41 42 43 44 50 56 57 66 69 71

39 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

516S0899

.

Keyboard Backlight Connector

F-ST-SM

AA07A-S010-VA1

CRITICAL

J4915

11

12

13 14

1

10

2

34 56 78 9

SYNC_DATE=03/15/2013

KEYBOARD/TRACKPAD (2 OF 2)

SYNC_MASTER=CHANG_J45

KBDBKLT_RETURN1

KBDBKLT_RETURN2

PPVOUT_S0_KBDBKLT

<SCH_NUM>

49 OF 118

40 OF 81

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LPC0AD3 LPC0CLK LPC0FRAME*

LPC0AD1 LPC0AD2

AIN08

AIN07 LPC0CLKRUN* LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119 PP4/IRQ120

C0-

WT2CCP0/PH0 WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2 SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127 PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4 PF5

T1CCP0/PJ0

T2CCP0/PJ2 T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

BI BI BI BI

IN IN

IN BI OUT

IN OUT

BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT OUT OUT OUT

OUT

IN

OUT

OUT OUT OUT

IN

OUT

IN

OUT

OUT OUT

NC

OUT

BI OUT

IN OUT

OUT

IN

OUT

IN

OUT

IN

IN OUT

OUT

BI

IN

OUT

IN

NC

OUT

IN

OUT

BI

IN

BI

OUT

IN

BI

NC

OUT

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

If SMS interrupt is not used, pull up to SMC rail.

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

(OD)

(OD) (OD)

(OD)

NOTE: Unused pins have "SMC_Pxx" names. Unused

(OD)

those designated as inputs require pull-ups.

pins designed as outputs can be left floating,

(OD)

LM4FSXAH5BB

BGA

OMIT_TABLE

U5000

E2 E1 F2 F1 B3 A3 B4 A4 B5 A5 B6 A6 C1 C2 B1 B2 G2 G1 H1 H2 B7 A7 B8 A8

K2 K1 L2

E10 D13

M4 N2 N8 M8 L8 K8 N7 M7 N4 N3

B13 A13 C12 D11 H12

G11

D12

F13

C13

F12

H13

L1

C4 C6

L9 K9

J4 J2

B12

C11

A12

H11 L13

G3

D10

L11 N12 N11 M11

M13 L12

M5

J12

J13

L5 D8 K6

D4 E4 F5

N5 N6 K5 M6 L6

M2 M3 L4 N1

L10 K10

M9 N9

F4 F3

C9 B9 A9 C8

D5

C5

L3 M1

F11 E11

E13 E12

K7 L7

K3 K4

J3 H4 H3 G4

H10

LM4FSXAH5BB

BGA

OMIT_TABLE

U5000

A1 C7

K11

D9 E5 F9 H5 H9 J5 J8 J11

C3 E3

M12

A2

G12

G13

B11

G10 C10

A10 A11 B10

K12

D7 E6 E8 E9

F10

J7 J9

J10

D3

J1 J6

K13

D6

D1

D2

N13

M10

N10

PLACE_NEAR=U5000.A1:4MM

SM

XW5000

12

42 50 57 71

CERM-X5R

6.3V 0201

0.1UF

10%

C5014

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C5015

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C5016

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C5017

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C5013

1

2

42

MF

1M

5% 1/20W

201

R5002

1

2

16V X5R-CERM 0201

0.1UF

10%

C5006

1

2

16V X5R-CERM 0201

0.1UF

10%

C5005

1

2

0201

X5R-CERM

16V

0.1UF

10%

C5009

1

2

X5R-CERM 0201

16V

0.1UF

10%

C5008

1

2

16V X5R-CERM 0201

0.1UF

10%

C5004

1

2

X5R-CERM 0201

16V

0.1UF

10%

C5003

1

2

X5R-CERM 0201

16V

0.1UF

10%

C5007

1

2

13 50 71 76

19 76

13 50 71 76

20

13 50 71

12 50 71

12 20 50 71

14

37 44 48 71 80

44 48 80

39 44 71 80

43 80

43

44 56 57 71 80

43 46

43

43 45

43 46

43 45

43 46

43 45

43 47

43 45

43 47

43

43 47

43

43 47

43

43 46

42 61 66

12 71 76

19 29 30 42

42

38 42 75

43

50

38

43

18 19 58 66 71

42

12 18 76

12 19 71 76

6.3V CERM-X5R 0201

0.1UF

10%

C5001

1

2

14

42

42 50 71

49

63

49

43

34 39 43

39 42 43 71

42

42 43 56 57

42

12 21 66 71

12 21 34 38 66 68 71

12 66

39 42 71

20 28 42 43

42 66

12 30 43

34 42 71

43

42

43

61 66

19 42

0402

30-OHM-1.7A

L5001

1 2

6

42 58 74

35

43

35

1UF

25V 402

X5R

10%

C5011

1

2

25V

1UF

402

X5R

10%

C5010

1

2

25V 402

1UF

X5R

10%

C5012

1

2

56

12 18 19 71 76

42

6

74

43

12 42

43

0.01UF

X5R-CERM 0201

10V

10%

C5020

1

2

402

CERM

1UF

6.3V

10%

C5021

1

2

402

1UF

CERM

6.3V

10%

C5002

1

2

43

34 66

35

SMC

SYNC_MASTER=CHANG_J45

SYNC_DATE=03/15/2013

SMC_SYS_KBDLED

SMC_FAN_1_CTL

TP_SMC_MPM5_LED_CHG

NC_SYS_TDM_ONEWIRE SYS_ONEWIRE NC_HISIDE_ISENSE_OC

ALL_SYS_PWRGD SMC_THRMTRIP

SMC_DCIN_ISENSE

PP3V3_S5_SMC_VDDA

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 MM

SMC_OOB1_R2D_L NC_IR_RX_OUT_RC NC_BDV_BKL_PWM

PM_BATLOW_L

PM_PWRBTN_L

NC_MEM_EVENT_L SMC_ADAPTER_EN

PM_PCH_SYS_PWROK

SMC_TOPBLK_SWP_L

SMC_BIL_BUTTON_L SMC_DP_HPD_L

PM_SLP_S3_L

PM_SLP_S5_L

NC_ENET_ASF_GPIO

SMC_PME_S4_DARK_L SMC_S4_WAKESRC_EN

SMC_TX_L

SMBUS_SMC_1_S0_SCL

NC_SMBUS_SMC_3_SDA

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_1_S0_SDA

NC_SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SDA

SMC_CPU_HI_ISENSE

SMC_LCDPANEL_ISENSE

SMC_X29_ISENSE

SPI_DESCRIPTOR_OVERRIDE_L

SMC_CPUDDR_ISENSE

SMC_XTAL

SMC_TDI

NC_SMC_ADC18

NC_SMC_ADC15 NC_SMC_ADC16

NC_SMC_ADC19 SMC_S2_ISENSE

SMC_WAKE_SCI_L

SMC_DEBUGPRT_TX_L

SMC_S5_PWRGD_VIN

SMC_TBT_ISENSE

NC_SMC_ADC2

SMC_CPUPKG_VSENSE

GND_SMC_AVSS

PP3V3_S5_AVREF_SMC

SMC_RESET_L

SMC_OTHER5V_HI_ISENSE

SMC_PBUS_VSENSE

SMC_TDO

SMC_WAKE_L

SMC_CPUPKG_ISENSE

CPU_THRMTRIP_3V3

SPI_SMC_MISO

SMC_OOB1_D2R_L

SMC_PME_S4_WAKE_L

SMC_EXTAL

SMC_CLK32K

WIFI_EVENT_L

PM_SYSRST_L

SMC_DEBUGPRT_EN_L

SPI_SMC_CS_L

NC_SYS_GFX_OVERTEMP

SPI_SMC_CLK

SPI_SMC_MOSI

NC_SMC_SYS_LED

SMC_PROCHOT

SMC_DELAYED_PWRGD

NC_SYS_GFX_THROTTLE_L

SMC_DEBUGPRT_RX_L

PM_DSW_PWRGD

SMC_PM_G2_EN

CPU_CATERR_L

CPU_PROCHOT_L

NC_SMC_ADC21

SMC_LCDBKLT_ISENSE

NC_SMC_ADC14

SMC_DCIN_VSENSE

LPC_AD<0> LPC_AD<1>

SMC_FAN_1_TACH

SMC_FAN_0_TACH

SMC_FAN_0_CTL

SMBUS_SMC_5_G3_SDA

LPC_SERIRQ

LPC_FRAME_L

PM_CLKRUN_L LPC_PWRDWN_L

SMBUS_SMC_0_S0_SCL

SMC_RUNTIME_SCI_L

SMBUS_SMC_0_S0_SDA

SMC_TCK

NC_SMBUS_SMC_3_SCL

SMBUS_SMC_5_G3_SCL

SMC_TMS

SMC_LRESET_L

LPC_CLK33M_SMC

LPC_AD<3>

LPC_AD<2>

SMC_VCCIO_CPU_DIV2

SMC_OTHER3V3_HI_ISENSE

SMC_CHGR_BMON_ISENSE

SMC_SSD_ISENSE

SMC_P1V35MEM_ISENSE

PP3V42_G3H

PM_WLAN_EN

PM_SLP_S4_L

G3_POWERON_L

SMC_LID

SMC_PECI_L

CPU_PECI_R

NC_SMC_ODD_DETECT

SMC_ONOFF_L

SMC_BC_ACOK

SMS_INT_L

S5_PWRGD

MIN_LINE_WIDTH=0.25 MM

PP1V2_S5_SMC_VDDC

MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.2V

SMC_RX_L

SMC_PWRFAIL_WARN_L

<SCH_NUM>

50 OF 118

41 OF 81

42

42 50 71

42

42 45 46 47

42 71

42 50 71

42

42 50 71

42

19 35 38 39 42 43 44 50 56 57 66 69 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

NC

OUT

BI

OUT

SYM_VER_2

G S

D

SDG

SN0903049

PAD

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Used on mobiles to support SMC reset via keyboard.

SMC Reset "Button", Supervisor & AVREF Supply

SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ

MR1* and MR2* must both be low to cause manual reset.

SMC Crystal Circuit

Mobiles: 3.42V

(IPU)

To SMC

From SMC

SMC12 PECI SUPPORT

From/To CPU/PCH

Debug Power "Buttons"

NOTE: Internal pull-ups are to VIN, not V+.

Mac Mini: 5V

5%

201

1/20W

MF

10K

R5170

1 2

5%

201

1/20W

MF

100K

R5171

1 2

5%

201

1/20W

MF

10K

R5173

1 2

5%

201

1/20W

MF

100K

R5174

1 2

5%

201

1/20W

MF

10K

R5177

1 2

5%

201

1/20W

MF

10K

R5178

1 2

5%

201

1/20W

MF

10K

R5179

1 2

5%

201

1/20W

MF

10K

R5180

1 2

5%

201

1/20W

MF

10K

R5185

1 2

41 42

14 76

5%

0

OMIT

1/10W MF-LF 603

SILK_PART=PWR_BTN

PLACE_SIDE=BOTTOM

R5115

1

2

6

41 58 74

41

5%

201

1/20W

MF

10K

R5189

1 2

5%

201

1/20W

MF

10K

R5181

1 2

5%

201

1/20W

MF

470K

R5187

1 2

5%

201

1/20W

MF

10K

R5193

1 2

5%

201

1/20W

MF

10K

R5172

1 2

5%

0

PLACE_SIDE=TOP

MF-LF

SILK_PART=PWR_BTN

603

OMIT

1/10W

R5116

1

2

5%

0

PLACE_SIDE=BOTTOM

1/10W MF-LF 603

SILK_PART=SMC_RST

OMIT

R5101

1

2

39 41 42 71

39

0201

X5R-CERM

10%

0.01UF

10V

C5101

1

2

20%

10uF

X5R 603

6.3V

C5125

1

2

0201

10V

10%

0.01UF

X5R-CERM

C5126

1

2

41 50 57 71

12

5%

201

1/20W

MF

22

PLACE_NEAR=U1100.Y6:5.1mm

R5112

1 2

41

5%

201

1/20W

MF

100K

R5190

1 2

5%

201

1/20W

MF

20K

R5175

1 2

5%

201

1/20W

MF

20K

R5176

1 2

5%

201

1/20W

MF

10K

R5186

1 2

5%

201

1/20W MF

1K

R5188

1

2

5%

201

1/20W

MF

100K

R5169

1 2

5%

201

1/20W MF

330

R5131

1

2

NONE

NOSTUFF

OMIT

0201

R5133

1

2

5%

0

0201

1/20W

MF

R5132

1 2

41

201

1/20W MF

100K

1%

R5197

1

2

201

1/20W MF

100K

1%

R5196

1

2

5%

201

1/20W

MF

100K

R5192

1 2

41 42

6

14 74

5%

201

1/20W

MF

100K

R5194

1 2

5%

201

1/20W

MF

10K

NOSTUFF

R5195

1 2

CRITICAL

MMBT3904LP-7

DFN1006-3

Q5158

1

3

2

5%

201

1/20W

MF

43

R5134

1 2

41

6

14 74

39 41 42 71

5%

201

1/20W

MF

3.3K

R5158

1 2

5%

201

1/20W

MF

100K

R5198

1 2

5%

201

1/20W

MF

100K

R5191

1 2

5%

0201

NP0-C0G-CERM

25V

12PF

C5111

1

2

5% NP0-C0G-CERM

0201

25V

12PF

C5110

1

2

201

1/20W

MF

2.49K

1%

R5110

1 2

12.000MHZ-30PPM-10PF-85C

CRITICAL

3.2X2.5MM-SM-1

Y5110

2 4

1 3

0.47UF

CERM-X5R

402

10%

6.3V

C5120

1

2

X5R 402

4.7UF

6.3V

20%

NO STUFF

C5127

1

2

5%

201

1/20W MF

100K

R5100

1

2

402

MF-LF

1/16W

5%

0

R5127

1 2

DMN32D2LFB4

DFN1006H4-3

CRITICAL

Q5130

3

1

2

SOT-563

DMN5L06VK-7

Q5159

6

2

1

DMN5L06VK-7

SOT-563

Q5159

3

5

4

CRITICAL

DFN

VREF-3.3V-VDET-3.0V

U5110

4

2

6 7

8

5

9

1

3

SMC Shared Support

SYNC_DATE=11/12/2012

SYNC_MASTER=CHANG_J45

SMC_ONOFF_L

PP3V42_G3H

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.4 mm

PP3V42_G3H_SMC_SPVSR

PM_CLK32K_SUSCLK_R

SMC_ADAPTER_EN

CPU_THRMTRIP_3V3

PM_THRMTRIP_L_R

SMC_THRMTRIP

SMC_VCCIO_CPU_DIV2

CPU_PECI_R

CPU_PECI

PP3V3_S4

PP3V42_G3H

PP3V3_WLAN

PP1V05_S0

SMS_INT_L

SMC_BC_ACOK

SMC_TDI

SPI_DESCRIPTOR_OVERRIDE_L

SMC_BIL_BUTTON_L

SMC_TX_L

SMC_TCK

SMC_LID

SMC_ONOFF_L

SMC_DEBUGPRT_RX_L

WIFI_EVENT_L

SMC_PM_G2_EN

SMC_S4_WAKESRC_EN

SMC_DELAYED_PWRGD

SMC_THRMTRIP

CPU_THRMTRIP_3V3

SMC_S5_PWRGD_VIN

SMC_TDO

SMC_PME_S4_DARK_L

SMC_TMS

SMC_DEBUGPRT_TX_L

G3_POWERON_L

SMC_RX_L

SMC_PECI_L_R

SMC_PECI_L

CPU_PROCHOT_L

SMC_PROCHOT

SMC_CLK32K

PM_THRMTRIP_L

SMC_ROMBOOT

PM_THRMTRIP_B_L

PP1V05_S0

SMC_XTAL

SMC_ONOFF_L

SMC_MANUAL_RST_L

SMC_RESET_L

SMC_TPAD_RST_L

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

PP3V3_S5_AVREF_SMC

SMC_EXTAL

SMC_XTAL_R

MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm

GND_SMC_AVSS

PP3V42_G3H

<SCH_NUM>

51 OF 118

42 OF 81

19 35 38 39

41 42

43 44

50 56

57 66

69 71

12 41

41

20 34 39 43 46 47 65 66 68 69 70 71

19 35 38 39 41 42 43 44 50 56 57 66 69 71

34 71

14 15 17 18 42 62 66 69 71

41

41 43 56 57

41 50 71

19 41

41

41 50 71

39 41 43 71

39 41 42 71

38 41 75

34 41 71

41 61 66

41 66

19 29 30 41

41 42

41

41 50 71

20 28 41 43

41 50 71

38 41 75

41

41 50 71

50 71

14 15 17 18 42 62 66 69 71

41

41 71

41

41 45 46 47

19 35 38 39 41 42 43 44 50 56 57 66 69 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

NC

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Hall Effect pads

APN: 998-3029

Spare S4 IRQ

HALL-SENSOR-MLB-PADS-K99

SM

OMIT_TABLE

J5250

1 2 3 4 5

6

7

8

10%

0402

X7R-CERM

50V

0.001UF

C5250

1

2

1/20W

MF

0

5%

0201

R5250

1 2

41

12 30 41 43

1K

201

1/20W

MF

5%

R5283

1 2

34 39 41 43

12 30 41 43

12

100K

MF

1/20W

201

5%

R5282

1

2

34 39 41 43

5%

201

1/20W

100K

MF

R5259

1

2

41

J5250 CRITICAL1607-6811

SUBASSY,PCBA HALL EFFECT,K99

SMC Project Support

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

PP3V42_G3H

SMC_LID_R

PP3V3_S4

SMC_LCDPANEL_ISENSE

SMC_OTHER5V_HI_ISENSE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

NC_SMC_ADC18

NO_TEST=TRUE

SMC_S2_ISENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_ADC21

NO_TEST=TRUE

SMC_BC_ACOK SMC_BC_ACOK

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_HISIDE_ISENSE_OC

NC_SYS_GFX_OVERTEMP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMBUS_SMC_3_SDA

SMC_OTHER3V3_HI_ISENSE

MAKE_BASE=TRUE

SMC_SSD_ISENSESMC_SSD_ISENSE

SMC_CPUPKG_VSENSE

SMC_CPUPKG_ISENSE

MAKE_BASE=TRUE

NC_SMC_ADC2

NO_TEST=TRUE

NC_HISIDE_ISENSE_OC

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_P1V35MEM_ISENSE

SMC_OTHER3V3_HI_ISENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

SMC_CPUDDR_ISENSE

SMC_LCDPANEL_ISENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

SMC_OTHER5V_HI_ISENSE

MAKE_BASE=TRUE

NC_SMC_ADC14

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SYS_GFX_OVERTEMP

NO_TEST=TRUE

NC_SYS_GFX_THROTTLE_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SYS_GFX_THROTTLE_L

NO_TEST=TRUE

NC_SYS_TDM_ONEWIRE

MAKE_BASE=TRUE

NC_SYS_TDM_ONEWIRE

NC_MEM_EVENT_L

SMC_CPUPKG_ISENSE

NC_SMC_ADC16

SMC_P1V35MEM_ISENSE

NC_SMC_ADC15

SMC_DCIN_VSENSE

NC_SMC_ADC2

NC_SMC_ADC14

SMC_CPU_HI_ISENSE

SMC_DCIN_ISENSE

NC_SMC_ADC19

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_ADC15

NO_TEST=TRUE

NC_BDV_BKL_PWM

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

NO_TEST=TRUE

SMC_PME_S4_DARK_L

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_CPUPKG_VSENSE

NC_SMC_SYS_LED

NC_ENET_ASF_GPIO

NC_IR_RX_OUT_RC

NC_SMC_ODD_DETECT NC_SMC_ODD_DETECT

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_SYS_LED

MAKE_BASE=TRUE

NC_ENET_ASF_GPIO

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_EVENT_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_ADC16

NO_TEST=TRUE

SMC_LID

MAKE_BASE=TRUE

SMC_CHGR_BMON_ISENSE

SMC_TOPBLK_SWP_L

SMC_PME_S4_WAKE_L

PCH_STRP_TOPBLK_SWP_L

PM_BATLOW_L

MAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

PP3V3_S4

SMC_CHGR_BMON_ISENSE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

NC_IR_RX_OUT_RC

NO_TEST=TRUE

PM_BATLOW_L

NC_BDV_BKL_PWM

SMC_DP_HPD_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMBUS_SMC_3_SCL

NC_SMBUS_SMC_4_ASF_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

SMC_X29_ISENSE

MAKE_BASE=TRUE

SMC_X29_ISENSE

NC_SMC_ADC21

SMC_S2_ISENSE

NC_SMC_ADC19

NC_SMC_ADC18

NC_SMBUS_SMC_3_SDA

NC_SMBUS_SMC_3_SCL

NC_SMBUS_SMC_4_ASF_SDA

NC_SMBUS_SMC_4_ASF_SCL

SMC_TBT_ISENSE

MAKE_BASE=TRUE

SMC_TBT_ISENSE

SMC_CPUDDR_ISENSE

<SCH_NUM>

52 OF 118

43 OF 81

20 28 41 42 43

19 35 38 39 41 42 44 50 56 57 66

69 71

71

20 34 39 42 43 46 47 65 66 68 69 70 71

41 43 47

41 43 45

41 43 47

41 43

41 43 47

41 43

41 42 43 56 57 41 42 43 56 57

41 43

41 43 80

41 43 45

41 43 46 41 43 46

41 43 46

41 43

41 43 45

41 43 46

41 43 45

41 43 47

41 43 45

41 43

41 43 41 43

41 43

41 43 46

41 43

41 43 46

41 43

41 43 45

41 43

41 43 45

41 43

41 43 47

41 43

20 28 41 42 43

41 43 45

41 43 46

41 43

41 43 41 43

41 43

39 41 42 71

41 43 45

20 34 39 42 43 46 47 65 66 68 69 70 71

41 43 45

41 43

41 43 80

41 43

41 43 47 41 43 47

41 43

41 43 47

41 43

41 43 80

41 43

41 43 46 41 43 46

41 43 47

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

L&R Fin Stack Temp

EMC1412-A: U5860

(Write: 0x30 Read: 0x31)

(MASTER)

(WRITE: 0xCC READ: 0xCD)

J9510 -> U9700

HDMI Redriver (on RIO)

U7100

(WRITE: 0x58 READ: 0x59)

LED BACKLIGHT

VRef DACs

Margin Control

SMC "2" SMBUS CONNECTIONS

NOTE: SMC RMT bus remains powered and may be active in S3 state

J4002

ALS

(Write: 0x72 Read: 0x73)

J1800 & J1850

XDP Connectors

SMC "0" SMBus Connections

U2201

ISL6258 - U7100

(Write: 0x12 Read: 0x13)

Lynx Point

U1100

(Write: 0x88 Read: 0x89)

access PCH & CPU via PECI.

PCH "SMLink 1" Connections

PCH "SMLink 0" Connections

J4801

(Write: 0x90 Read: 0x91)

SMC "3" SMBUS CONNECTIONS

Unused

U5000

(MASTER)

SMC

SMC "4" SMBUS CONNECTIONS

SMC

(MASTER)

U5000

Unused

Battery Charger

Battery

(Write: 0x16 Read: 0x17)

J7050

SMC "5" SMBUS CONNECTIONS

SMC

(MASTER)

U5000

EMC1414-A: U5870

(Write: 0x98 Read: 0x99)

CPU/DDR3/PCH/AIRFLOW TEMP

U5000

(MASTER)

SMC

SMC "1" SMBUS CONNECTIONS

(Write: 0x98 Read: 0x99)

(MASTER) (MASTER)

SMC

U1100

SMC

U5000

(MASTER)

Trackpad

PCH SMBus "0" Connections

X29 TEMP

(WRITE: 0X92 READ: 0X93)

TMP105: U5823

(MASTER)

U1100

Lynx Point

SMLink 1 is slave port to

Lynx Point

U2200

U5000

(Write: 0x98 Read: 0x99)

2.0K

MF

1/20W

201

5%

R5380

1

2

2.0K

MF

1/20W 201

5%

R5381

1

2

1K

MF

1/20W

201

5%

R5370

1

2

1K

MF

1/20W 201

5%

R5371

1

2

2.0K

MF-LF 402

1/16W

5%

R5351

1

2

2.0K

MF-LF

1/16W

402

5%

R5350

1

2

1/16W

402

MF-LF

8.2K

5%

R5310

1

2

1/16W 402

MF-LF

8.2K

5%

R5311

1

2

NO STUFF

8.2K

MF

1/20W 201

5%

R5321

1

2

NO STUFF

8.2K

MF

1/20W

201

5%

R5320

1

2

MF

1/20W

0201

0

5%

R5323

1 2

MF

1/20W

0201

0

5%

R5322

1 2

1/16W 402

MF-LF

1K

5%

R5301

1

2

1/16W

402

MF-LF

1K

5%

R5300

1

2

1K

MF

1/20W 201

5%

R5361

1

2

1K

MF

1/20W

201

5%

R5360

1

2

SMBus Connections

SYNC_MASTER=CHANG_J45

SYNC_DATE=11/26/2012

SMBUS_PCH_DATA

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

PP3V3_S3

SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_2_S3_SDA

SMBUS_PCH_CLK SMBUS_PCH_DATA

SMBUS_PCH_CLK

PP3V3_S0

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

PP3V3_S0

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

PP3V42_G3H

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_0_S0_SCL

SML_PCH_1_DATA

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SML_PCH_0_DATA

SML_PCH_0_CLK

MAKE_BASE=TRUE

SML_PCH_1_CLK

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_2_S3_SCL

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_PCH_CLK

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

PP3V3_S0

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

<SCH_NUM>

53 OF 118

44 OF 81

13 18 22 44 63 68

71 76

41 44 48 80

13 20 21 22 46 47 65 68 69 71

39 41 44 71 80

37 41 44 48 71 80

39 41 44 71 80

13 18 22 44 63 68

71 76

13 18 22 44 63 68

71 76

13 18 22 44 63 68

71 76

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

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55 65 66 67 69 71 81

41 44 48 80

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

41 44 56 57 71 80

19 35 38 39 41 42 43 50 56 57 66 69 71

41 44 56 57 71 80

41 44 48 80

41 44 56 57 71 80

37 41 44 48 71 80

13 76

41

44 56

57 71 80

41

44 56

57

71

80

13 76

41 44 48

80

41 44 48

80

39 41 44 71 80

13 18 22 44 63 68 71 76

37 41 44 48 71 80

39

41 44

71

80

39

41 44

71 80

37

41 44

48 71 80

37 41 44 48 71 80

13 18 22 44 63 68 71 76

37 41 44 48 71 80

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

37

41 44

48

71

80

37 41 44 48 71 80

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

IN

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN-

IN+ REF

V+

GND

OUT

IN-

IN+ REF

V+

GND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

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NOTICE OF PROPRIETARY PROPERTY:

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12

D

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C

PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EDP Current:5A

Gain:100x

Gain:50x

OTHERS (3.3V) High Side Current Sense / Filter

EDP Current:21.6A

SMC_ADC3

divider when SUS present.

Power Drop across R5400 at EDP becomes 1.21W

SMC Key IC0R

Enables DC-In VSense

RTHEVENIN = 4567 Ohms

SMC KEY VD0R

PBUS Voltage Sense Enable & Filter

Enables PBUS VSense divider when in S0.

RTHEVENIN = 4508 Ohms

Divider set for Vin max of 22.32V Divider set for Vin max of 13.98V

SMC_ADC5

SMC Key VP0R

SMC_ADC4

SMC Key ID0R

EDP Current:4.6A

IPBR

SMC_ADC7

SMC_ADC8

SMC_ADC9

SMC Key IO3R

SMC_ADC13

OTHERS (5V) High Side Current Sense / Filter

COMPUTING High Side Current Sense / Filter

DC-In Voltage Sense Enable & Filter

SMC Key IO5R

Gain:100x

EDP Current:5A

DC-IN (AMON) Current Sense Filter

CHARGER BMON HIGH SIDE (BATTERY DISCHARGE) CURRENT SENSE & FILTER

From charger

57

41 43 57

6.3V X5R

20%

0201

0.22UF

PLACE_NEAR=U5000.B5:5MM

C5403

1

2

1/20W

1%

4.53K

MF

201

PLACE_NEAR=U5000.B5:5MM

R5403

1 2

41 43

201

1/20W

MF

4.53K

1%

PLACE_NEAR=U5000.A5:5MM

R5433

1 2

20%

0.22UF

X5R

6.3V 0201

PLACE_NEAR=U5000.A5:5MM

C5433

1

2

41 43

CRITICAL

SC70

INA213

U5400

2

5

4

6

1

3

0.1UF

402

10V

20%

CERM

C5401

1

2

10V CERM

20%

0.1UF

402

C5431

1

2

0612

CRITICAL

1W 1%

MF

0.003

R5400

123

4

1W

CRITICAL

1%

MF

0.005

0612-3

R5430

123

4

41 43

0201

X5R-CERM

PLACE_NEAR=U5000.A4:5MM

6.3V

10%

0.022UF

C5421

1

2

201

PLACE_NEAR=U5000.A4:5MM

1%

45.3K

MF

1/20W

R5423

1 2

45.3K

1% MF

1/20W

201

PLACE_NEAR=U5000.B3:5MM

R5441

1 2

10% 10V X7R-CERM

2200PF

0201

PLACE_NEAR=U5000.B3:5MM

C5441

1

2

402

MF-LF

1/16W

100K

1%

R5402

1

2

31 32 66

41 43

PLACE_NEAR=U5000.A3:5MM

201

1/20W

MF

1%

19.1K

R5401

1

2

PLACE_NEAR=U5000.A3:5MM

0201

X5R

0.22UF

20%

6.3V

C5404

1

2

5.90K

1%

PLACE_NEAR=U5000.A3:5MM

201

1/20W

MF

R5404

1

2

SOT-963

NTUD3169CZ

CRITICAL

Q5400

6

3

2

5

1

4

1%

100K

402

MF-LF

1/16W

R5405

1

2

41 43

1/16W

1%

MF-LF

402

100K

R5412

1

2

12 65 66

201

1/20W

MF

30.9K

1%

PLACE_NEAR=U5000.F1:5MM

R5413

1

2

0.22UF

6.3V X5R

20%

PLACE_NEAR=U5000.F1:5MM

0201

C5414

1

2

PLACE_NEAR=U5000.F1:5MM

201

1/20W

MF

1%

5.36K

R5414

1

2

SOT-963

NTUD3169CZ

CRITICAL

Q5410

6

3

2

5

1

4

MF-LF

1/16W

1%

402

100K

R5411

1

2

5% MF-LF

1/16W

PLACE_NEAR=U5400.6:5MM

20K

402

R5409

1

2

MF-LF

1/16W

5%

PLACE_NEAR=U5430.6:5MM

20K

402

R5439

1

2

41 43

0.22UF

6.3V

PLACE_NEAR=U5000.A5:5MM

0201

X5R

20%

C5426

1

2

1/20W

PLACE_NEAR=U5000.A5:5MM

1%

4.53K

MF

201

R5426

1 2

5% 1/16W MF-LF

PLACE_NEAR=U5420.6:5MM

20K

402

R5429

1

2

402

0.1UF

20%

CERM

10V

C5422

1

2

0.005

MF 1%

CRITICAL

1W

0612-3

R5420

123

4

SC70

CRITICAL

INA214

U5430

2

5

4

6

1

3

SC70

CRITICAL

INA214

U5420

2

5

4

6

1

3

SYNC_MASTER=CHANG_J45

SYNC_DATE=12/21/2012

High Side Voltage and Current Sensing

PM_SLP_SUS_L

HS_OTHER5V_IOUT

PP3V3_S0

SMC_OTHER5V_HI_ISENSE

SMC_OTHER3V3_HI_ISENSE

PPBUS_G3H

PPVIN_S5_HS_OTHER3V3_ISNS

GND_SMC_AVSS

DCIN_S5_VSENSE

PPBUS_G3H

PPVIN_S5_HS_OTHER5V_ISNS

GND_SMC_AVSS

CHGR_BMON

SMC_CHGR_BMON_ISENSE

GND_SMC_AVSS

CHGR_AMON

SMC_DCIN_ISENSE

GND_SMC_AVSS

PBUSVSENS_EN_L_DIV

HS_COMPUTING_IOUT

DCINVSENS_EN_L PBUSVSENS_EN_L

SMC_DCIN_VSENSE

GND_SMC_AVSS

PPBUS_G3H

GND_SMC_AVSS

PPDCIN_G3H_ISOL

PBUS_S0_VSENSE

PM_SLP_S3_R_L

GND_SMC_AVSS

SMC_CPU_HI_ISENSE

ISNS_HS_COMPUTING_N

PPVIN_S5_HS_COMPUTING_ISNS

PPBUS_G3H

PDCINVSENS_EN_L_DIV

ISNS_HS_COMPUTING_P

PP3V3_S0

ISNS_HS_OTHER3V3_P

ISNS_HS_OTHER3V3_N

HS_OTHER3V3_IOUT

ISNS_HS_OTHER5V_P

ISNS_HS_OTHER5V_N

SMC_PBUS_VSENSE

<SCH_NUM>

54 OF 118

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55 65 66 67 69 71 81

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55 65 66 67 69 71 81

30 45 56 57 63 69 71

61 69

41 42 45 46 47

30 45 56 57 63 69 71

61 69

41 42 45 46 47

30 45 56 57 63 69 71

41 42 45 46 47

56 57 69

41 42 45 46 47

81

58 59 60 62 69

30 45 56 57 63 69 71

81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

81

w w w . c h i n a f i x . c o m

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OUT

V-

V+

+

-

V-

V+

+

-

OUT

V-

V+

+

-

IN

V-

V+

+

-

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TBT Router CURRENT SENSE

DDR3 1.35V DRAM ONLY CURRENT SENSE / FILTER

EDP: 95A TDP :45A

SSD CURRENT SENSE

GAIN: 130X

SMC_ADC23

IHSC

SMC_ADC6

EDP CURRENT:8A

Gain: 182x

GAIN:136.6X

IM0C

SMC_ADC10

IC0C

SMC_ADC1

SMC_ADC0

VC0C

CPU PKG Load Side Current Sense / Filter

Max VOut: 3.3V at 95.8A

Scale: 29.03A / V

Gain:137.77x

(Effective Sense R is 0.25mOhm due to summing of the 3 phases)

Individual Sense R is 0.75mOhm

CPU Vcore Voltage Sense / Filter

EDP CURRENT: 5A

Sense Resistor 0.005 Ohm

IHDC

SENSE RESISTOR 0.010 OHM EDP CURRENT: 0.94 A

GAIN: 274X

41 43

PLACE_NEAR=U5000.B6:7mm

201

1/20W

MF

4.53K

1%

R5577

1 2

PLACE_NEAR=U5000.B6:5mm

6.3V X5R

20%

0.22UF

0201

C5577

1

2

402

1/16W MF-LF

1%

7.32K

R5573

1 2

NO_XNET_CONNECTION=TRUE

402

1%

MF-LF

1M

1/16W

R5576

1 2

1/16W

402

1%

1M

MF-LF

R5575

1

2

1%

7.32K

MF-LF

402

1/16W

R5574

1 2

OPA333DCKG4

SC70-5

U5560

1

3

4

2

5

0402

20%

0.1UF

X7R-CERM

10V

C5560

1

2

0201

20%

X5R

0.22UF

6.3V

PLACE_NEAR=U5000.B4:5MM

C5540

1

2

4.53K

1/20W

MF

1%

201

PLACE_NEAR=U5000.B4:7MM

R5564

1 2

10V CERM

20%

402

0.1UF

C5558

1

2

OPA333DCKG4

SC70-5

U5540

1

3

4

2

5

NO_XNET_CONNECTION=TRUE

402

1/16W MF-LF

1%

1M

R5563

1 2

NO_XNET_CONNECTION=TRUE

1/16W

402

1%

1M

MF-LF

R5562

1

2

402

MF-LF

1%

1/16W

7.68K

R5504

1 2

1%

1/16W

402

MF-LF

7.68K

R5561

1 2

41 43

0201

20%

6.3V X5R

PLACE_NEAR=U5000.E1:5MM

0.22UF

C5501

1

2

1%

4.53K

MF

201

PLACE_NEAR=U5000.E1:5MM

1/20W

R5506

1 2

SENSOR_NONPROD:Y

20%

0402

0.1UF

10V

PLACE_NEAR=U5550.5:3MM

X7R-CERM

C5550

1

2

CRITICAL

SC70-5

OPA333DCKG4

SENSOR_NONPROD:Y

U5550

1

3

4

2

5

732K

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

1/16W

402

1%

MF-LF

R5555

1 2

1/16W

1%

MF-LF

402

SENSOR_NONPROD:Y

3.57K

R5503

1 2

NO_XNET_CONNECTION=TRUE

402

1/16W

732K

1% MF-LF

SENSOR_NONPROD:Y

R5554

1

2

SENSOR_NONPROD:Y

1/16W

1%

MF-LF

402

3.57K

R5507

1 2

0.5%

402

NO_XNET_CONNECTION=TRUE

MF

1/16W

5.23K

PLACE_NEAR=R7310.3:5MM

SENSOR_NONPROD:Y

R5505

1 2

59 81

5.23K

SENSOR_NONPROD:Y

1/16W

MF

402

0.5%

PLACE_NEAR=R7330.3:5MM

NO_XNET_CONNECTION=TRUE

R5500

1 2

5.23K

0.5%

SENSOR_NONPROD:Y

402

1/16W

MF

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7320.3:5MM

R5508

1 2

1/16W

0.5%

402

5.23K

MF

SENSOR_NONPROD:Y

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7310.4:5MM

R5570

1 2

MF

402

0.5%

5.23K

1/16W

PLACE_NEAR=R7320.4:5MM

SENSOR_NONPROD:Y

NO_XNET_CONNECTION=TRUE

R5571

1 2

59 81

1/16W

402

MF

0.5%

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7330.4:5MM

SENSOR_NONPROD:Y

5.23K

R5572

1 2

59 81

6.3V

0201

20%

X5R

PLACE_NEAR=U5000.A8:5MM

0.22UF

C5500

1

2

MF

201

PLACE_NEAR=U5000.A8:5MM

4.53K

1/20W

1%

R5502

1 2

CERM

10V

0.1UF

20%

402

C5551

1

2

OPA333DCKG4

SC70-5

U5500

1

3

4

2

5

201

1M

1% MF

NO_XNET_CONNECTION=TRUE

1/20W

R5501

1 2

1%

1M

201

MF

1/20W

R5553

1

2

1/20W

MF

1%

3.65K

201

R5551

1 2

1% MF

1/20W

3.65K

201

R5552

1 2

0.010

1/2W

1%

CRITICAL

MF

1206-1

R5559

123

4

5%

0

402

1/16W MF-LF

PLACE_NEAR=U5550.4:7MM

SENSOR_NONPROD:N

R5530

1 2

58

CRITICAL

0612

1W

1%

MF

0.003

R5560

123

4

0612-3

CRITICAL

0.005

1% 1W MF

R5549

1 2

3 4

41 43

4.53K

1%

1/20W

MF

201

PLACE_NEAR=U5000.E2:7MM

R5520

1 2

PLACE_NEAR=U5000.E2:5MM

0.22UF

X5R

6.3V

20%

0201

C5520

1

2

SM

PLACE_NEAR=R7310.2:5 MM

XW5520

1 2

SYNC_MASTER=CHANG_J45

SYNC_DATE=03/15/2013

Load Side Voltage and Current Sensing

ISNS_TBT_N

PP3V3_S4

PP3V3_S4_TBT

ISNS_TBT_R_P

ISNS_SSD_R_N

ISNS_SSD_R_P

ISNS_SSD_IOUT

PP1V35_S3_MEM

PP3V3_S0SW_SSD

PP3V3_S0

CPUVR_ISNS3_N

PP3V3_S4

SMC_SSD_ISENSE

SMC_TBT_ISENSE

PP1V35_S3

ISNS_1V35_MEM_P

ISNS_1V35_MEM_N

GND_SMC_AVSS

SMC_CPUPKG_VSENSE

GND_SMC_AVSS

CPUVSENSE_INPPVCC_S0_CPU

PP3V3_S0

CPUVR_ISNS1_P

CPUVR_ISUM_R_P

CPUVR_ISNS3_P

CPUVR_ISNS2_P

SMC_CPUPKG_ISENSE

CPUVR_ISNS_P

CPUVR_ISUM_R_N

CPUVR_ISNS2_N

CPUVR_ISNS1_N

GND_SMC_AVSS

PP3V3_S3

ISENSE_P1V35MEM_IOUT

ISNS_1V35_MEM_R_P

ISNS_1V35_MEM_R_N

SMC_P1V35MEM_ISENSE

CPUVR_IMON

GND_SMC_AVSS

CPUVR_ISNS_N

CPUVR_ISUM_IOUT

GND_SMC_AVSS

ISNS_SSD_P

ISNS_SSD_N

PP3V3_S0SW_SSD_R

ISNS_TBT_IOUT

ISNS_TBT_P

ISNS_TBT_R_N

<SCH_NUM>

55 OF 118

46 OF 81

81

20 34 39 42 43 46

47 65 66

68 69 70

71

28 29 30 69

81

23 24 25 26 69 77

35 69

71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

20 34 39 42 43 46 47 65 66 68 69 70 71

21 22 60 65 69 71

81

41 42 45 46 47

6 8

10 59 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

81

41 42 45 46 47

13 20 21 22 44 47 65 68 69 71

81

41 42 45 46 47

81

65 69

81

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

IN

OUT

IN-

IN+ REF

V+

GND

IN

V-

V+

+

-

IN

OUT

IN-

IN+ REF

V+

GND

V-

V+

+

-

V-

V+

+

-

IN

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU DDR CURRENT SENSE

Sense Resistor 0.010 Ohm EDP Current: 820mA

EDP CURRENT: 1.0A

EDP Current: 1.06A

IAPC

SMC_ADC22

Gain: 316x

SMC_ADC11

IC3C

ILDC

SMC_ADC12

GAIN: 100X

SMC_ADC17

GAIN: 383X

LCD BKLT Current Sense

IBLC

NEED KEY FOR THIS SENSOR

S2 CAMERA CONTROLLER CURRENT SENSE

GAIN: 100X

EDP Current: 0.75A

GAIN: 332X

SMC_ADC20

ICMC

.

EDP CURRENT: 4.2A

Sense Resistor 0.005 Ohm

X29 AIRPORT CURRENT SENSE

LCD PANEL CURRENT SENSE

0.1UF

SENSOR_NONPROD:Y

CERM 402

20%

10V

C5682

1

2

201

1%

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

MF

1/20W

1M

R5684

1 2

SENSOR_NONPROD:Y

201

1%

1/20W

MF

3.16K

R5681

1 2

201

1%

SENSOR_NONPROD:Y

1/20W

MF

3.16K

R5682

1 2

201

SENSOR_NONPROD:Y

NO_XNET_CONNECTION=TRUE

MF

1/20W

1M

1%

R5683

1

2

81

ISNS_CPUDDR_P

INA214

SC70

SENSOR_NONPROD:Y

U5670

2

5

4

6

1

3

0.1UF

SENSOR_NONPROD:Y

10V

20%

402

CERM

C5670

1

2

81

OPA333DCKG4

SENSOR_NONPROD:Y

SC70-5

U5682

1

3

4

2

5

81

ISNS_CPUDDR_N

X5R

6.3V

SENSOR_NONPROD:Y

0.22UF

PLACE_NEAR=U5000.G1:5MM

20%

0201

C5601

1

2

0.1UF

SENSOR_NONPROD:Y

CERM 402

20%

10V

C5602

1

2

201

SENSOR_NONPROD:Y

1/20W

1%

PLACE_NEAR=U5000.G1:7MM

MF

4.53K

R5601

1 2

SENSOR_NONPROD:Y

INA214

SC70

U5601

2

5

4

6

1

3

X5R

6.3V

20%

0201

SENSOR_NONPROD:Y

0.22UF

PLACE_NEAR=U5000.B8:7MM

C5631

1

2

201

1/20W

1% MF

4.53K

PLACE_NEAR=U5000.B8:7MM

SENSOR_NONPROD:Y

R5634

1 2

10%

0.1UF

0201

CERM-X5R

6.3V

SENSOR_NONPROD:Y

C5630

1

2

SENSOR_NONPROD:Y

OPA333DCKG4

SC70-5

U5630

1

3

4

2

5

510K

201

NO_XNET_CONNECTION=TRUE

MF

1/20W

SENSOR_NONPROD:Y

1%

R5633

1 2

SENSOR_NONPROD:Y

620

201

MF

1%

1/20W

R5630

1 2

SENSOR_NONPROD:Y

620

201

MF

1%

1/20W

R5631

1 2

SENSOR_NONPROD_R

CRITICAL

SM

XW5635

510K

201

1%

1/20W

MF

SENSOR_NONPROD:Y

NO_XNET_CONNECTION=TRUE

R5632

1

2

X5R

6.3V

0201

20%

0.22UF

PLACE_NEAR=U5000.A6:5MM

SENSOR_NONPROD:Y

C5681

1

2

X5R

6.3V

20%

SENSOR_NONPROD:Y

PLACE_NEAR=U5000.C1:7MM

0.22UF

0201

C5671

1

2

201

PLACE_NEAR=U5000.C1:7MM

1/20W

1% MF

4.53K

SENSOR_NONPROD:Y

R5671

1 2

SENSOR_NONPROD:Y

201

1%

4.53K

MF

1/20W

PLACE_NEAR=U5000.A6:7MM

R5685

1 2

201

3.01K

MF

1/20W

1%

SENSOR_NONPROD:Y

R5600

1 2

SENSOR_NONPROD_R

CRITICAL

SM

XW5675

201

3.01K

MF

1%

1/20W

SENSOR_NONPROD:Y

R5670

1 2

S2_PWR:S0

1/16WMF-LF

5%

0

402

R5677

1 2

0

5%

MF-LF

402

S2_PWR:S3

1/16W

R5676

1 2

201

NO_XNET_CONNECTION=TRUE

1M

MF

1/20W

SENSOR_NONPROD:Y

1%

R5672

1

2

201

NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

1% MF

1M

1/20W

R5673

1 2

SC70-5

OPA333DCKG4

SENSOR_NONPROD:Y

U5600

1

3

4

2

5

X5R

6.3V

PLACE_NEAR=U5000.H1:7MM

20%

0201

0.22UF

SENSOR_NONPROD:Y

C5600

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

SENSOR_NONPROD:Y

C5603

1

2

201

SENSOR_NONPROD:Y

PLACE_NEAR=U5000.H1:7MM

1/20W

MF

4.53K

1%

R5674

1 2

63 81

41 43

Debug Sensors

SYNC_MASTER=CHANG_J45

SYNC_DATE=12/21/2012

C5601,C5631,C5600,C5681,C5671,C5618

SENSOR_NONPROD:N

7

117S0008

RES,MTL FILM,100K,5,1/20W,0201,SMD,LF

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

PP3V3_S3RS0_CAMERA_R

PP3V3_S3RS0_CAMERA

PP3V3_WLAN_R

PP3V3_WLAN_F

ISNS_AIRPORT_R_N

ISNS_AIRPORT_IOUT

NC_ISNS_AIRPORTP ISNS_AIRPORT_R_P

NC_ISNS_AIRPORTN

SMC_S2_ISENSE

NC_ISNS_S2N

PP3V3_S3

SMC_X29_ISENSE

PP3V3_S0

NC_ISNS_S2P

SMC_LCDPANEL_ISENSE

ISNS_LCD_PANEL_N

GND_SMC_AVSS

PP3V3_S3

PP3V3_S0

GND_SMC_AVSS

ISNS_S2_R_N

LCDBKLT_IOUT

GND_SMC_AVSS

ISNS_LCD_PANEL_P

LCD_PANEL_IOUT

GND_SMC_AVSS

ISNS_CPU_DDR_R_N

ISNS_CPU_DDR_R_P

ISNS_CPU_DDR_IOUT

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

PP3V3_S0

SMC_LCDBKLT_ISENSE

SMC_CPUDDR_ISENSE

ISNS_S2_R_P

ISNS_S2_OUT

PP3V3_S4

PP3V3_S3

<SCH_NUM>

56 OF 118

47 OF 81

13 36 69

34

81

13 20 21 22 44 46 47 65 68 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46

47 48 49 51 52 55 65

66 67 69 71 81

41 42 45 46 47

13 20 21 22 44 46 47 65 68 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

41 42 45 46 47

81

41 42 45 46 47

81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

81

20 34 39 42 43 46 65 66 68 69 70 71

13 20 21 22 44 46 47 65 68 69 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

BI

DP1

THERM*/ADDR

DN1

THRM_PAD

VDD

SMDATA

SMCLK

GND

ALERT*

DP2/DN3

DN2/DP3

BI

V+

GNDS

SDA

SCL

A0

ALERT

NC

THERM*/ADDR

ALERT*

GND

VDD

DN

DP

SMDATA SMCLK

THRM

PAD

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Use GND pin B1 on U2800 for N leg

LEFT FIN STACK TEMPERATURE

Placement note:

PLACE Q5803 ON BOTTOM SIDE NEAR RIGHT FIN STACK

Th1H

RIGHT FIN STACK TEMPERATURE

CLOSE TO THE LEFT FIN STACK

PLACE U5860 ON TOP SIDE

Th2H

LEFT FIN STACK/RIGHT FIN STACK

PCH PROXIMITY TEMPERATURE

PLACE Q5803 ON TOP SIDE NEAR DDR3

Placement note:

Write Address: 0x98 Read Address: 0x99

TW0P

WRITE ADDRESS: 0X92

Placement note:

PLACE U5823 ON BOTTOM NEAR X29 CONN

READ ADDRESS: 0X93

X29 PROXIMITY

TC0P

Placement note:

Read Address: 0x99

Write Address: 0x98

TP0P

Ta0P

AIRFLOW PROXIMITY TEMPERATURE

TM0P

CLOSE TO BOARD EDGE

Placement note:

PLACE Q5802 ON TOP SIDE

PLACE U5870 ON TOP SIDE UNDER CPU

PLACE Q5804 ON TOP SIDE UNDER PCH

Placement note:

THSP

DDR3 PROXIMITY TEMPERATURE

CPU PROXIMITY TEMPERATURE

DDR3 PROXIMITY/CPU PROXIMITY/PCH PROXIMITY/AIRFLOW PROXIMITY

TBT DIE

1/16W

5%

402

MF-LF

10K

R5872

1

2

1/16W

5%

402

MF-LF

10K

R5871

1

2

CRITICAL

BC846BMXXH

SOT732-3

Q5804

1

3

2

1/16W

5%

402

MF-LF

10K

R5851

1

2

10K

MF-LF 402

5% 1/16W

R5852

1

2

0.1UF

X7R-CERM 0402

20% 10V

C5850

1

2

47

402

5%

MF-LF

1/16W

R5850

1 2

CRITICAL

BC846BMXXH

SOT732-3

Q5802

1

3

2

CERM

402

10% 50V

PLACE_NEAR=U5870.3:5mm

PLACE_NEAR=U5870.2:5mm

NO_XNET_CONNECTION=TRUE

0.0022uF

C5871

1

2

28 48 81

SM

PLACE_NEAR=U2800.AC6:2mm

XW5820

1 2

10K

402

5% 1/16W

NOSTUFF

PLACE_SIDE=TOP

MF-LF

R5820

1

2

CRITICAL

BC846BMXXH

SOT732-3

Q5806

1

3

2

EMC1414-A-AIA

DFN

U5870

83

5

2

4

6

10

9

7

11

1

41 44 48 80

WCSP-6

CRITICAL

TMP105

PLACE_SIDE=BOTTOM

PLACE_NEAR=J3501:5MM

U5823

C2

B2

A2

B1

A1

C1

0.1uF

20% 10V CERM 402

C5823

1

2

10K

402

1/16W

5%

MF-LF

R5822

1

2

CRITICAL

EMC1412-A

TQFN

U5860

6

3

2

5

8

7

4

9

1

CRITICAL

BC846BMXXH

SOT732-3

Q5803

1

3

2

PLACE_NEAR=U5860.2:5mm

PLACE_NEAR=U5860.3:5mm

NO_XNET_CONNECTION=TRUE

0.0022uF

CERM

402

10% 50V

C5852

1

2

37 41 44 71 80

41 44 48 80

10V X7R-CERM

0.1UF

0402

20%

C5870

1

2

47

MF-LF

402

5%

1/16W

R5870

1 2

0.0022uF

CERM

402

10% 50V

PLACE_NEAR=U5870.4:5mm PLACE_NEAR=U5870.5:5mm

NO_XNET_CONNECTION=TRUE

C5890

1

2

SYNC_MASTER=CHANG_J45

SYNC_DATE=11/26/2012

Thermal Sensors

DDR3THMSNS_D1_P

TBT_THERMD_N

TBT_THERMD_P

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

PP3V3_S0

CPUTHMSNS_ALERT_L

CPUTHMSNS_THM_L

DDR3THMSNS_D1_N

SMBUS_SMC_1_S0_SCL

X29THMSNS_A0

PP3V3_S0

SMBUS_SMC_1_S0_SDA

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm VOLTAGE=3.3V

PP3V3_S0_CPUTHMSNS_R

PP3V3_S0

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 mm

PP3V3_S0_FINTHMSNS_R

FINTHMSNS_ALERT_L

FINTHMSNS_THM_L

MAKE_BASE=TRUE

TBT_THERMD_P

FINTHMSNS_D_P

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

FINTHMSNS_D_N

<SCH_NUM>

58 OF 118

48 OF 81

81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

81

28 48

81

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

IN

OUT

IN

NC

NC NC

D

S

G

D

S

G

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

518S0769

Left Fan

Right Fan

518S0769

47K

5%

1/16W

402

MF-LF

R6050

1

2

5%

1/16W

402

47K

MF-LF

R6055

1 2

MF-LF

402

5%

1/16W

47K

R6060

1

2

1/16W

5%

402

MF-LF

47K

R6065

1 2

100K

201

MF

1/20W

5%

R6051

1

2

201

MF

100K

5%

1/20W

R6061

1

2

41

CRITICAL

FF14A-5C-R11DL-B-3H

F-RT-SM

J6050

7

6

1 2 3 4 5

FF14A-5C-R11DL-B-3H

F-RT-SM

CRITICAL

J6060

7

6

1 2 3 4 5

SOT-563

DMN5L06VK-7

Q6060

3

5

4

SOT-563

DMN5L06VK-7

Q6060

6

2

1

41

NOSTUFF

0

1/16W MF-LF

5%

402

R6071

1 2

MF-LF

1/16W

NOSTUFF

0

5%

402

R6072

1 2

SYNC_DATE=10/31/2012

Fan Connectors

SYNC_MASTER=J15_MLB

FAN_LT_PWM

PP3V3_S0

PP3V3_S3_FAN_CTL

SMC_FAN_1_TACH

PP3V3_S0

PP3V3_S3_FAN_CTL

SMC_FAN_1_CTL

FAN_RT_PWM

SMC_FAN_0_CTL

PP5V_S0

SMC_FAN_0_TACH

PP3V3_S0

FAN_LT_TACH

FAN_RT_TACH

PP3V3_S0

PP5V_S0

<SCH_NUM>

60 OF 118

49 OF 81

71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

49 70

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

49 70

71

18 19 37 49 50 58 59 62 63 65 66 69 70 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

18 19 37 49 50 58 59 62 63 65 66 69 70 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

OUT

IN

BI

IN

OUT

BI

IN

OUT

WP*

SI

HOLD*

VSS

SCK

CE*

VDD

SO

BI

IN

BI

IN

OUT

IN

IN BI

BI BI BI

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

WF: This termination is wrong for dual/quad-IO.

LPC+SPI Connector

516S1039

SPI ROM

override. Quad-IO support is

NOTE: Not all ROM APNs currently

compatible with Matt card ROM

used support quad-IO. Also not

for experimentation only.

NOTE: If HOLD* is asserted ROM will ignore SPI cycles in normal and dual-IO modes.

SMC12 SPI SUPPORT

(SPI_IO<0>)

(SPI_IO<1>)

SPI Bus Series Termination

5%

0

PLACE_NEAR=U1100.AH1:5mm

1/16W

402

MF-LF

R6112

1 2

41 42 71

42 71

41 42 57 71

41 42 71

12 20 41 71

13 41 71

50 71

12 41 71

14 50 71

13 41 71 76

50 71

5%

0

LPCPLUS_R:YES

MF-LF 402

1/16W

PLACE_NEAR=J6100.12:5mm

R6126

1

2

5%

PLACE_NEAR=R6126.2:5mm

402

MF-LF

33

1/16W

R6121

1 2

5%

0

LPCPLUS_R:YES

MF-LF 402

1/16W

PLACE_NEAR=J6100.14:5mm

R6125

1

2

5%

PLACE_NEAR=R6125.2:5mm

1/16W

402

MF-LF

33

R6120

1 2

5%

0

LPCPLUS_R:YES

MF-LF 402

1/16W

PLACE_NEAR=J6100.11:5mm

R6128

1

2

5%

33

PLACE_NEAR=U6100.2:5mm

1/16W

402

MF-LF

R6123

1 2

5%

0

LPCPLUS_R:YES

MF-LF 402

1/16W

PLACE_NEAR=J6100.9:5mm

R6127

1

2

5%

PLACE_NEAR=R6127.2:5mm

33

MF-LF

402

1/16W

R6122

1 2

LPCPLUS_CONN:YES

CRITICAL

M-ST-SM

DF40C-30DP-0.4V

J6100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

CRITICAL

OMIT_TABLE

SST25VF064C

SOIC

64MBIT

U6100

1

7

6

5

2

8

4

3

402

20% CERM

0.1UF

10V

C6100

1

2

5%

SPI:DUAL_IO

402

3.3K

MF-LF

1/16W

R6101

1

2

13 76

PLACE_NEAR=R6101.2:5mm

15

MF-LF

402

1%

1/16W

SPI:QUAD_IO

R6130

1 2

13

PLACE_NEAR=R6102.2:5mm

SPI:QUAD_IO

MF-LF

402

1%

1/16W

15

R6131

1 2

13

5%

0

SPI:DUAL_IO

402

MF-LF

1/16W

R6102

1 2

14 50 71

14 71

50 71

41 42 71

20 71 76

41 42 71

19 71 76

13 41 71 76

5%

201

1/20W

MF

12

R6103

1 2

5%

0

0201

1/20W

MF

R6104

1 2

5%

0

0201

1/20W

MF

R6100

1 2

5%

0

0201

1/20W

MF

R6124

1 2

41

5%

0

1/16W MF-LF

402

PLACE_NEAR=U1100.AJ7:5mm

R6110

1 2

13 76

5%

0

PLACE_NEAR=U1100.AJ11:5mm

MF-LF

402

1/16W

R6111

1 2

13 76

SPI ROM / LPC+SPI Conn.

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

SPIROM_WP_L

SPIROM_HOLD_L

SPI_MLB_MOSI

SPI_MLB_CLK

SPI_MLB_CS_L

SPI_MLB_MISO

SPI_ALT_MISO SPI_ALT_MOSI SPI_ALT_CLK SPI_ALT_CS_L

SPI_CS0_L

SPI_MOSI

SPI_MISO

SPI_IO<2>

SPI_CS0_R_L

SPI_IO<3>

SPI_CLK_R

SPI_MOSI_R

SPIROM_USE_MLB

SPIROM_HOLD_L

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MISO

SPI_MLB_MOSI

SPIROM_WP_L

PP3V3_SUS

SMC_TX_L

SMC_TDO

TP_SMC_MD1

TP_SMC_TRST_L

LPCPLUS_RESET_L

LPCPLUS_GPIO

LPC_AD<3>

LPC_AD<1>

SPI_ALT_MOSI

LPC_AD<2>

LPC_AD<0>

LPC_CLK33M_LPCPLUS

SMC_TMS

SMC_RX_L

SMC_ROMBOOT

SMC_RESET_L

SMC_TCK

SMC_TDI

LPC_PWRDWN_L

LPC_SERIRQ

SPI_ALT_CS_L

SPI_ALT_CLK

PM_CLKRUN_L

SPIROM_USE_MLB

LPC_FRAME_L

SPI_ALT_MISO

PP5V_S0

PP3V42_G3H

SPI_SMC_CS_L

SPI_SMC_CLK

SPI_SMC_MOSI

SPI_SMC_MISO

SPI_CLK

<SCH_NUM>

61 OF 118

50 OF 81

50

50 71

76

50

11 12 13 14 15 17 64 65 66 69

71

18 19 37 49 58 59 62 63 65 66 69 70 71

19 35 38 39 41 42 43 44 56 57 66 69 71

76

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ANALOG

SYM 1 OF 2

AGND

HPGND

HSGND

PLLGND

VA_PLL

VA

VA_REF

VA_HP

SENSE_A1 SENSE_A2

HPOUT_L HPOUT_R

HS3 HS4

HS4_REF

SENSE_B2

SENSE_B1

SENSE_D

SENSE_C

HS3_REF

HSIN+ HSIN-

LINEOUT1_L-

LINEOUT1_L+

LINEOUT1_R+ LINEOUT1_R-

LINEOUT2_L-

LINEOUT2_L+

LINEOUT2_R-

LINEOUT2_R+

LINEOUT3_R+

LINEOUT3_L+

LINEOUT3_R-

LINEOUT4_L+ LINEOUT4_L-

LINEOUT4_R+ LINEOUT4_R-

LINEOUT3_L-

VREF_ADC

VCOM

FLYN

FLYP

VHP_FILT-

VREF_DAC

LINEIN_L+

LINEIN_R-

LINEIN_R+

LINEIN_L-

MICBIAS2_R

MICBIAS2_L

MICBIAS1_R

MICBIAS1_L

MICIN1_L+

MICIN2_L-

MICIN1_L-

MICIN1_R+

MICIN2_L+

MICIN2_R+ MICIN2_R-

HSBIAS_IN HSBIAS HSBIAS_REF HSBIAS_FILT

MICIN1_R-

OUT

NR/FB

NC

IN

EN

GND

OUT

IN IN

IN IN IN IN

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACE XW6201 NEAR 5V SOURCE

4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2456

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

RT. SUBWOOFER AMP. SIG. SOURCE

LFT SUBWOOFER AMP. SIG. SOURCE

RT. SPKR AMP. SIG. SOURCE

LFT. SPKR AMP. SIG. SOURCE

AUDIO CODEC, ANALOG BLOCKS

APPLE P/N 353S4080

CS4208-CRZR

VFBGA

U6201

M11

L6

L9

L10

B10 B11

A8

A10C8C10

A12 A13

C13

B13

C12

B12

L13

N11

L12

M13

D13

M6

N6

M10

N10

M9

N9

E13

E12

F12

F11

G11

F13

G13

G12

J11

H11

J13

J12

K12

K11

L11

K13

L8 L7

L5 L4

M8

N8

M7

N7

M5

N5

M4

N4

A2

C11 D12

E11 D11 M3 L3

N13A9A1

H12

M12

A11

N12

H13

0.1UF

0402

10%

X7R-CERM

16V

BYPASS=U6201.A1:A2:5 MM

C6212

1

2

BYPASS=U6201.N13:M11:5 mm

0402

16V

0.1UF

10%

X7R-CERM

C6216

1

2

BYPASS=U6201.H12:H13:5 mm

10UF

16V

20%

CRITICAL

TANT-POLY

0805-LLP-1

C6215

1

2

20%

CRITICAL

4V

X5R

15UF

0402

C6219

1 2

53 81

CRITICAL

0603-LLP

1UF-10OHM

25V

TANT

20%

C6210

1

2

TANT-POLY

20% 16V

CRITICAL

10UF

0805-LLP-1

C6211

1

2

CRITICAL

0402

20%

4V

X5R

15UF

BYPASS=U6201.A8:B10:5 mm

C6222

1

2

0402

X5R-CERM

10V

20%

4.7UF

C6221

1

2

X5R 402

25V

10%

1UF

C6220

1 2

2.21K

MF

1%

1/20W

201

R6206

1 2

10% X5R

25V 402

1UF

C6224

1 2

10% 25V

402

X5R

1UF

C6225

1 2

SM

XW6201

1 2

MF

201

5%

NOSTUFF

1/20W

2.2K

R6200

1 2

0201

FERR-22-OHM-1A-0.065-OHM

L6200

1 2

X5R 402

10V

10%

1UF

C6201

1

2

SON

CRITICAL

TPS71745

U6200

4

2

6

5

3

1

SM

XW6200

1 2

0201-1

10V

20%

1.0UF

X5R-CERM

CRITICAL

C6203

1

2

0402

0.1UF

16V

X7R-CERM

BYPASS=U6201.H12:L10:5 mm

10%

C6218

1

2

55 71

55

54 81

10UF

20%

TANT-POLY

16V

0805-LLP-1

C6217

1

2

55 71

25V

0.01UF

0201

X5R-CERM

CRITICAL

10%

C6202

1

2

0.1UF

16V

10%

X7R-CERM

0402

C6214

1

2

CRITICAL

10UF

20% 10V X5R-CERM 0402-1

C6213

1

2

0402

CRITICAL

120-OHM-25%-1.3A

L6201

1 2

16V 0201

0.1UF

10%

X5R-CERM

C6226

1 2

0402

16V

0.1UF

X7R-CERM

10%

C6200

1

2

5%

22K

MF

1/20W

201

R6207

1 2

AUDIO:CODEC, ANALOG

SYNC_MASTER=JOE_J45

SYNC_DATE=07/30/2013

PP4V5_AUDIO_ANALOG

VREF_DAC

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM

MIN_NECK_WIDTH=0.07MM

AUD_CH_HS_GND

MIN_LINE_WIDTH=0.5MM

MIN_LINE_WIDTH=0.3MM

HS_MIC_P

MIN_NECK_WIDTH=0.07MM

HS_MIC_N

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.07MM

AUD_US_HS_GND

MIN_LINE_WIDTH=0.5MM

MIN_LINE_WIDTH=0.20MM

PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V

MIN_NECK_WIDTH=0.15MM

GND_AUDIO_CODEC

CODEC_MICIN2

TP_AUD_CODEC_MICBIAS2_R

MIN_NECK_WIDTH=0.07MM

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.3MM

PP5V_S4

GND_AUDIO_CODEC

4V5_NR

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.5MM VOLTAGE=0V

MIN_NECK_WIDTH=0.07MM

AUD_HP_PORT_R

MIN_LINE_WIDTH=0.3MM

GND_AUDIO_CODEC

AUD_HSBIAS_FILT

NC_AUD_LO4_LN

NC_AUD_LO4_LP

AUD_LO3_R_N

AUD_LO3_L_P

GND_AUDIO_CODEC

CODEC_VCOM

NC_AUD_LO4_RP

AUD_LO3_R_P

AUD_LO3_L_N

AUD_LO2_L_P

MIN_LINE_WIDTH=0.4MM

AUD_HP_PORT_REFCH

MIN_NECK_WIDTH=0.07MM

MIN_LINE_WIDTH=0.4MM

AUD_HP_PORT_REFUS

MIN_NECK_WIDTH=0.07MM

CODEC_VREF_ADC

GND_AUDIO_CODEC

NC_AUD_LO4_RN

AUD_LO2_R_N

AUD_LO2_R_P

AUD_LO2_L_N

NC_AUD_LO1_RN

NC_AUD_LO1_RP

NC_AUD_LO1_LP NC_AUD_LO1_LN

AUD_TYPEDET

CODEC_HS_MIC_N

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.06MM

MIN_NECK_WIDTH=0.06MM

MIN_LINE_WIDTH=0.3MM

CODEC_HS_MIC_P

AUD_TIPDET_2

AUD_TIPDET_1

PP3V3_S0

PP3V3_S0_AUDIO_ANALOG

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1 mm

VHP_FILTN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM

CODEC_FLYP

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.07MM

CODEC_FLYN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM

GND_AUDIO_CODEC

TP_AUD_CODEC_MICBIAS1_L

TP_AUD_CODEC_MICBIAS1_R

TP_AUD_CODEC_MICBIAS2_L

GND_AUDIO_CODEC

AUD_HSBIAS_IN

AUD_HSBIAS_REF

AUD_HSBIAS

4V5_REG_IN

VOLTAGE=5V

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

4V5_REG_EN

PM_SLP_S3_BUF_L

PP3V3_S0

VOLTAGE=5V

MIN_NECK_WIDTH=0.20MM

PP5V_S4_AUDIO_XW

MIN_LINE_WIDTH=0.60MM

<SCH_NUM>

62 OF 118

51 OF 81

51

51 55

38 61 65 66 67 68 69 71

51 55

81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

51 55

65 66 68 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

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DIGITAL

SYM 2 OF 2

VD

VL_HD

VL_IF

VL_SP

VL_DM

NC

DMIC_SCL3

DMIC_SDA3

DMIC_SCL2

DMIC_SDA2

DMIC_SCL1

DMIC_SDA1

DMIC_SCL0

DMIC_SDA0

SPDIF_OUT

SPDIF_IN

SCL

SDA

SDIN_B

SDOUT_B

LRCK_B

SCLK_B

MCLK_B

RST*

SDO3

SDO2

SDO1

SDO0

GPIO0 GPIO1

GPIO5

GPIO4

GPIO3

GPO0

SYNC

BCLK

SDI0

GPO1

SDI1

SCLK_A

MCLK_A

LRCK_A SDOUT_A SDIN_A

GPIO2

DGND

LGND

PP

OUT

IN

OUT

IN

OUT

IN

OUT

PP

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

APPLE P/N 353S4080

AUDIO CODEC, DIGITAL BLOCKS

CS4208-CRZR

VFBGA

U6201

F2

J1

N2

M1

L1

L2

N3

N1

M2

K2

H3 H2 H1 C4 C5 C7

C9 B9

F1E3F3J3K3

B4

B5

A5

A6

F6 F7 F8 G6 G7 G8 H6 H7 H8

D3

B7

B2

B6

C6

D1 C1

B3

A4

D2 C2 C3 B1

A3

B8

G3 G2

E2

J2K1E1G1A7

SHORT

402

OMIT

R6302

1 2

201

5%

MF

1/20W

100K

R6323

1 2

201

MF

5%

100K

1/20W

R6325

1

2

P3MM

SM

PLACE_NEAR=U6201.D1:5 mm

PP6305

1

54

FERR-22-OHM-1A-0.065-OHM

0201

L6300

1 2

11 76

11 52 76

201

MF

5%

22

1/20W

R6331

1 2

10UF

20%

0402-1

X5R-CERM

10V

C6305

1

2

10%

0.1UF

0402

16V X7R-CERM

BYPASS=U6201.E1:F1:5 mm

C6302

1

2

0402-1

X5R-CERM

10V

20%

10UF

C6306

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U6201.A7:E3:5 mm

C6307

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U6201.G1:F1:5 mm

C6303

1

2

4.7UF

20% 4V

402

X5R-1

C6300

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U6201.K1:K3:5 mm

C6304

1

2

11 52 76

1/16W

402

5%

33

MF-LF

R6330

1 2

55

75

402

MF-LF

1/16W

1%

R6332

1 2

55 71

52 55 71

10%

0.1UF

BYPASS=U6201.J2:J1:5 mm

X7R-CERM 0402

16V

C6301

1

2

53

201

MF

5%

100K

1/20W

R6324

1

2

201

1/20W

5%

MF

100K

NOSTUFF

R6322

1 2

PLACE_NEAR=U6201.F2:5 mm

P3MM

SM

PP6302

1

P3MM

SM

PLACE_NEAR=U6201.N3:5 mm

PP6301

1

P3MM

SM

PLACE_NEAR=U6201.E2:5 mm

PP6303

1

P3MM

SM

PLACE_NEAR=U6201.D2:5 mm

PP6304

1

54

55 71

AUDIO:CODEC, DIGITAL

SYNC_MASTER=JOE_J45

SYNC_DATE=07/30/2013

PP3V3_S0

DFET_OPENCH

PD_CS4208_GPIO1

SPKRCONN_L_ID SPKRCONN_R_ID

DFET_OPENUS

HDA_BIT_CLK

CS4208_HDA_SDOUT0_R

MIN_NECK_WIDTH=0.07MM

VOLTAGE=1.5V

PP1V5_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.6 MM

GPIO0_SPKR_SHUTDOWN

NC_CS4208_LRCLKA NC_CS4208_SDOUTA

NC_CS4208_LRCLKB

DMIC_SDA3

DMIC_CLK3

NC_CS4208_SCLKB

DMIC_CLK3_R

NC_CS4208_GPO0

PP3V3_S0

NC_CS4208_GPO1

HDA_RST_L

HDA_SYNC

HDA_SDOUT

CS4208_HDA_SDOUT0_R

HDA_BIT_CLK

HDA_SDOUT

CS4208_SPDIF_IN

PP1V5_S0

DMIC_SDA3

HDA_SDIN0

TP_CS4208_HDA_SDOUT1

HDA_SYNC

NC_CS4208_MCLKB

NC_CS4208_SCLKA

NC_CS4208_SDOUTB

NC_CS4208_MCLKA

NC_DMIC_CLK1

NC_DMIC_CLK2

SPDIF_OUT_JACK

CS4208_SPDIF_OUT

NC_DMIC_CLK0

<SCH_NUM>

63 OF 118

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55 65 66 67 69 71 81

52 76

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

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11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

11 52 76

52 76

11 52 76

11 12 13 15 17 19 64 66 68 69 71

52 55 71

w w w . c h i n a f i x . c o m

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VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

OUT

VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

OUT

IN

OUT

IN

OUT

IN

OUT

IN-

IN+

OUT+ OUT-

GAIN

SHDN*

PVDD

NC

PGND

IN-

IN+

OUT+ OUT-

GAIN

SHDN*

PVDD

NC

PGND

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

1ST ORDER FC (SUB) = NOM 9 HZ

1ST ORDER FC (L&R) = NOM 569 HZ

GAIN = +3 DB

APN: 353S2888 & 353S2958

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

CRITICAL

0402

FERR-1000-OHM

L6430

1 2

16V

0.22UF

CRITICAL

CERM

402

10%

C6443

1 2

16V

CERM

402

10%

0.22UF

CRITICAL

C6444

1 2

0.22UF

10%

402

CERM

CRITICAL

16V

C6434

1 2

0.22UF

10%

402

CERM

CRITICAL

16V

C6433

1 2

CRITICAL

WLCSP

SSM2375

U6430

B2

A3

C1

A1

B1

B3

C3

A2

C2

55 71 81

0201

X5R-CERM

16V

10%

0.1UF

BYPASS=U6430.C2:C1:5 mm

C6431

1

2

SSM2375

WLCSP

CRITICAL

U6440

B2

A3

C1

A1

B1

B3

C3

A2

C2

55 71 81

BYPASS=U6440.C2:C1:5 mm

16V X7R-CERM 0402

0.1UF

10%

C6441

1

2

6.3V

20%

CASE-A4

TANT-POLY

47UF

CRITICAL

C6422

1

2

20%

TANT

6.3V

CASE-AL1

100UF

CRITICAL

C6432

1

2

CASE-AL1

TANT

6.3V

20%

100UF

CRITICAL

C6442

1

2

X7R-CERM

4700PF

50V

0402

10%

C6436

1

2

X7R-CERM

50V

0402

10%

4700PF

C6446

1

2

100K

5%

MF-LF

402

1/16W

R6400

1

2

FERR-1000-OHM

0402

CRITICAL

L6401

1 2

51 81

52

0402

CRITICAL

FERR-1000-OHM

L6411

1 2

55 71 81

X7R-CERM

16V 0402

0.1UF

10%

BYPASS=U6410.A1:A2:5 mm

C6411

1

2

X5R-CERM

16V

10%

0.1UF

0201

BYPASS=U6420.A1:A2:5 mm

C6421

1

2

CRITICAL

FERR-1000-OHM

0402

L6421

1 2

51 81

55 71 81

47UF

TANT-POLY

20%

6.3V

CRITICAL

CASE-A4

C6412

1

2

0402

CRITICAL

FERR-1000-OHM

L6410

1 2

51 81

0402

CRITICAL

FERR-1000-OHM

L6420

1 2

51 81

CRITICAL

10%

0402

X7R-CERM

50V

0.01UF

C6423

1 2

0.01UF

X7R-CERM

10% 50V

CRITICAL

0402

C6424

1 2

0402

0.01UF

10% 50V

X7R-CERM

CRITICAL

C6414

1 2

0.01UF

0402

CRITICAL

X7R-CERM

50V

10%

C6413

1 2

55 71 81

CRITICAL

MAX98300

WLP

U6410

C3

B3

A3

B2

C1

B1

A2

A1

C2

1/16W

402

MF-LF

5%

100K

R6410

1

2

MAX98300

CRITICAL

WLP

U6420

C3

B3

A3

B2

C1

B1

A2

A1

C2

100K

1/16W

5%

402

MF-LF

R6420

1

2

51 81

CRITICAL

FERR-1000-OHM

0402

L6441

1 2

FERR-1000-OHM

CRITICAL

0402

L6440

1 2

51 81

0402

CRITICAL

FERR-1000-OHM

L6431

1 2

51 81

SYNC_DATE=07/30/2013

SYNC_MASTER=JOE_J45

AUDIO: SPEAKER AMP

PP5V_S0_AUDIO_AMP_L

LSUB_GAIN

RSUB_GAIN

PP5V_S0_AUDIO_AMP_R

SPKR_L_GAIN

SPKR_SHUTDOWN

AUD_LO2_L_P

SPKR_SHUTDOWN

AUD_LO3_L_N

AUD_LO3_L_P

AUD_LO3_R_N

AUD_LO3_R_P

AUD_LO2_R_N

SPKR_R_GAIN

AUD_LO2_R_P

AUD_LO2_L_N

NO_TEST=TRUE

LSUBIN_P

LSUBIN_N

NO_TEST=TRUE

RSUBIN_N

SPKRAMP_RIN_P

NO_TEST=TRUE

AUD_SPKRAMP_RSUBIN_P

AUD_SPKRAMP_LIN_N

SPKRAMP_LIN_N

NO_TEST=TRUE

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_RIN_N

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SL_OUT_N

NO_TEST=TRUE

SPKRAMP_RIN_N

SPKRCONN_L_OUT_N

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_L_OUT_P

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_R_OUT_P

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_R_OUT_N

MIN_NECK_WIDTH=0.10 MM

RSUBIN_P

NO_TEST=TRUE

SPKRCONN_SR_OUT_N

MIN_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SR_OUT_P

MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM

SPKRCONN_SL_OUT_P

PP5V_S0_AUDIO_AMP_R

AUD_SPKRAMP_RSUBIN_N

GPIO0_SPKR_SHUTDOWN

SPKR_SHUTDOWN

PP5V_S0_AUDIO_AMP_L

SPKRAMP_LIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LIN_P

AUD_SPKRAMP_LSUBIN_N

AUD_SPKRAMP_LSUBIN_P

<SCH_NUM>

64 OF 118

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53

81

53 70

81

53

53 70

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OUT

IN

OUT

IN

PSEL

CP

GND

OUT2

OUT1

VDD

PSEL

CP

GND

OUT2

OUT1

VDD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

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C

PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(SEE RADAR # 6210118)

R/C6550 FILTER TO ADDRESS OUT-OF-BAND NOISE ISSUE SEEN ON EARLY HEADSETS

51 81

201

100K

1/20W

MF

5%

R6556

1

2

402

MF-LF

1/16W

2.2K

5%

R6550

1 2

27PF

CRITICAL

NP0-C0G

25V 0201

5%

C6558

1

2

1/16W

5%

2.2K

402

MF-LF

R6559

1 2

55 81

1000PF

25V

5% 0402

NP0-C0G

C6501

1

2

52

54 55 71

54 55

52

25V NP0-C0G

1000PF

5%

0402

C6502

1

2

402

1/16W MF-LF

10K

5%

R6520

1

2

10% X5R-CERM

0.1UF

16V 0201

BYPASS=U6501.B2:3MM

C6542

1

2

CERM-X5R

1.0UF

0402

10% 35V

C6530

1

2

10% 10V

CRITICAL

0201

X7R-CERM

3300PF

C6550

1

2

0.01UF

10V X5R-CERM 0201

10%

BYPASS=U6501.B2:3MM

C6543

1

2

TAIC3027A0YFFR

WCSP

U6500

C1

B1

A1 A2

C2

B2

WCSP

TAIC3027A0YFFR

U6501

C1

B1

A1 A2

C2

B2

10%

0201

X5R-CERM

10V

0.01UF

BYPASS=U6500.B2:3MM

C6563

1

2

16V

0.1UF

10% X5R-CERM

BYPASS=U6500.B2:3MM

0201

C6562

1

2

35V

10%

0402

CERM-X5R

1.0UF

C6560

1

2

5%

10K

MF-LF

1/16W

402

R6521

1

2

AUDIO: JACK

SYNC_DATE=07/30/2013

SYNC_MASTER=JOE_J45

DFET_CPO2

AUD_CONN_RING2_XW

AUD_CONN_SLEEVE_XW

HS_MIC_N

HS_MIC_P

MIN_NECK_WIDTH=0.06MM

AUD_HS_MIC_N

MIN_LINE_WIDTH=0.2MM

AUD_HS_MIC_P

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.06MM

DFET_OPENUS

DFET_CPO1

DFET_OPENCH

<SCH_NUM>

65 OF 118

54 OF 81

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IN

IN IN

OUT

IN

OUT

IN

OUT

IN

NC

GND

VDD

AUDIO GND

SHELL

VIN

MIC

DET2 DET1 1RTN

2RTN

R.AUDIO

AUDIO GND

PINS

POF

OPERATING VOLTAGE 3.3

AUDIO

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

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A

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PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DFET CONTROL

APN: 514-0875

HIGH = FG, LOW = MERRY

SUB

DMIC 1

HEADSET MIC

LEFT SPEAKER ID RIGHT SPEAKER ID

OUTPUT

GPIO4

2-MIC CONNECTOR

APN: 518S0769

OTHER CODEC GPIO LINES

0X0E (14)

0X1C (28)

3.3V

0X09 (9)

GPIO2 INPUT GPIO3

0X21 (33)

0X13 (19)

0X12 (18)

N/A

CONVERTER

0X04 (4)

SPDIF OUT

0X02 (2)

FUNCTION

0X10 (16)

VOLUME CONVERTER

MUTE CONTROL

FUNCTION

N/A

N/AHP/HS OUT

CODEC INPUT SIGNAL PATHS

HP=80HZ

INPUT

SPEAKER CONNECTOR

APN: 518S0672

0X03 (3)

0X02 (2)

PIN COMPLEX

0X07 (7)

0X18 (24)

2.7V

DMIC 2 0X1C (28)

CODEC GPIO0 CODEC GPIO0

3.3V

VREF

CODEC OUTPUT SIGNAL PATHS

HIGH = FG, LOW = MERRY

PIN COMPLEX

0X04 (4)

0X03 (3)TWEETERS

HIGH = DFETs OPEN

M-RT-SM

78171-6006

CRITICAL

J6602

7

8

1 2 3 4 5 6

M-RT-SM

CRITICAL

78171-6006

J6603

7

8

1 2 3 4 5 6

53 71 81

52 71

53 71 81

52 71

53 71 81

52 71

402

OMIT

SHORT

R6680

1 2

51 71

54 81

51

51 71

CRITICAL

0201

FERR-470-OHM

L6606

1 2

CRITICAL

0402

120-OHM-25%-1.3A

L6605

1 2

FERR-470-OHM

CRITICAL

0201

L6607

1 2

0402

120-OHM-25%-1.3A

CRITICAL

L6604

1 2

51

FERR-470-OHM

0201

CRITICAL

L6608

1 2

10V

1UF

402-1

X5R

10%

C6600

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C6601

1

2

5%

402

10K

1/16W MF-LF

R6601

1

2

PLACE_NEAR=J6600.3:2.54mm

SM

XW6600

1 2

SM

PLACE_NEAR=J6600.5:2.54mm

XW6602

1 2

SM

XW6601

1 2

SM

XW6603

1 2

F-RT-SM

FF14A-5C-R11DL-B-3H

J6601

7

6

1 2 3 4 5

CRITICAL

SOD882

ESDALC5-1BM2

DZ6607

1

2

ESDALC5-1BM2

SOD882

CRITICAL

DZ6602

1

2

CRITICAL

SOD882

ESDALC5-1BM2

DZ6606

1

2

CRITICAL

ESDALC5-1BM2

SOD882

DZ6604

1

2

ESDALC5-1BM2

SOD882

CRITICAL

DZ6601

1

2

SOD882

CRITICAL

ESDALC5-1BM2

DZ6603

1

2

ESDALC5-1BM2

CRITICAL

SOD882

DZ6605

1

2

52

0201

5%

100PF

25V

NP0-CERM

C6608

1

2

0402

CRITICAL

120-OHM-25%-1.3A

L6611

1 2

0402

CRITICAL

120-OHM-25%-1.3A

L6612

1 2

0402

CRITICAL

120-OHM-25%-1.3A

L6613

1 2

CRITICAL

0402

120-OHM-25%-1.3A

L6614

1 2

5%

100PF

NP0-CERM

25V 0201

C6607

1

2

100PF

5%

0201

NP0-CERM

25V

C6602

1

2

NP0-CERM

25V 0201

5%

100PF

C6605

1

2

0201

5%

100PF

NP0-CERM

25V

C6606

1

2

100PF

NP0-CERM

0201

25V

5%

C6604

1

2

0201

5%

100PF

25V NP0-CERM

C6603

1

2

F-RT-TH

AUDIO-SPDIF-J44

J6600

1

10 11

12 13 14 15

2

3 4

5 6

7

8

9

2.2K

5%

201

1/20W

MF

R6603

1

2

201

MF

1/20W

5%

2.2K

R6602

1

2

SYNC_MASTER=JOE_J45

SYNC_DATE=07/30/2013

AUDIO: JACK TRANSLATORS

AUD_HP_PORT_REFUS

AUD_HP_PORT_L

AUD_HP_PORT_R

GND_AUDIO_CODEC

AUD_CONN_TIPDET_2

MIN_NECK_WIDTH=0.06MM

AUD_CONN_HP_LEFT

MIN_LINE_WIDTH=0.3MM

AUD_CONN_TIPDET_1

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.06MM

AUD_CONN_HP_RIGHT

AUD_TIPDET_2

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.06MM

AUD_CONN_RING2

MIN_NECK_WIDTH=0.06MM

MIN_LINE_WIDTH=0.4MM

AUD_CONN_SLEEVE

DMIC_CLK3

DMIC_SDA2

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.5MM

AUD_CONN_SLEEVE_XW

PP3V3_S0

AUD_CONN_TYPEDET

AUD_CH_HS_GND

AUD_CONN_RING2_XW

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.1MM

SPKRCONN_SR_OUT_N

SPKRCONN_R_OUT_N

SPKRCONN_R_OUT_P

DMIC_SDA3

PP3V3_S0

AUD_TYPEDET

SPKRCONN_L_ID

SPKRCONN_L_OUT_P

SPKRCONN_SR_OUT_P

SPKRCONN_R_ID

SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N

SPKRCONN_L_OUT_N

AUD_HP_PORT_REFCH

AUD_HS_MIC_P

AUD_US_HS_GND

AUD_HS_MIC_N

SPDIF_OUT_JACK

AUD_TIPDET_1

<SCH_NUM>

66 OF 118

55 OF 81

51

71

54 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

54

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 67 69 71 81

w w w . c h i n a f i x . c o m

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VCC

EXT INT

NC

GND

NC

POS

NEG

SYS_DETECT

SDA

POS

POS SCL

NEG NEG NEG

VER 1

NC NC

BI

NC

G

D

S

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

IN

Y

B

A

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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C

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D

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PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

1-Wire OverVoltage Protection

send transients onto ADAPTER_SENSE when AC is

The chassis ground will otherwise float and can

Vout = 1.25V * (1 + Ra / Rb)

APN:353S3733

300MA MAX OUTPUT

Vout = 3.425V

(Switcher limit)

MagSafe DC Power Jack

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

<Rb>

<Ra>

BATTERY CONNECTOR

518-0376

6.8V Zener

for D2 design only

When input voltage is 2V the FET will be off

connected.

518S0508

When input voltage is at 16V+, FET will conduct and power charger and 3.42V reg

properly detected.

blocking the leakage path and 22.1K can be

sparkitecture requirements

Input impedance of 22.1K meets

6AMP-32V-0.0095OHM

0603

CRITICAL

F7005

1 2

20%

0603

CERM

50V

0.01UF

NOSTUFF

C7005

1

2

MAX9940

SC70-5

CRITICAL

U7000

5

2

4

3

1

402

0.1UF

X5R

25V

10%

C7050

1

2

603-1

1UF

X5R

25V

10%

C7060

1

2

CRITICAL

SC-75

RCLAMP2402B

D7050

3

1

2

5% 1/16W

402

10K

MF-LF

R7050

1

2

5%

NP0-C0G-CERM 0201

22PF

50V

C7095

1

2

201

1/20W

MF

200K

1%

R7096

1

2

X5R-CERM-1

22UF

6.3V 603

20%

C7099

1

2

201

1/20W

MF

1%

348K

R7095

1

2

5%

MF-LF

805

10

1/8W

R7005

1 2

MF

1/3W

47

1%

805

R7020

1 2

SOT-323

BAT30CWFILM

CRITICAL

D7005

1

2

3

CRITICAL

33UH-20%-0.39A-0.435OHM

DP418C-SM

L7095

1 2

402

10% 10V

CERM

0.22UF

C7094

1

2

CRITICAL

F-ST-TH

BAT-J5

J7050

1021 1122

112 213 314 415 516 617 718 819 920

WTB-PWR-M82

M-RT-SM

CRITICAL

J7000

1 2 3 4 5 6

41

5%

MF-LF

2.0K

1/16W

402

R7029

1

2

POWERPAK

SI5419DU

Q7010

1

4

5

5A

5%

201

1/20W MF

100K

R7010

1

2

201

1/20W MF

1%

22.1K

R7012

1

2

CDZ6.8B

SM

D7010

A

K

4.7UF

35V

10%

X5R-CERM

0603

C7091

1

2

X5R-CERM

35V

10%

0603

4.7UF

C7090

1

2

X5R-CERM

4.7UF

10% 35V

0603

NOSTUFF

C7092

1

2

0603

4.7UF

X5R-CERM

35V

10%

C7093

1

2

X5R-CERM

10% 35V

0603

NOSTUFF

4.7UF

C7096

1

2

NOSTUFF

0603

X5R-CERM

35V

10%

4.7UF

C7097

1

2

0402

X5R

25V

10%

0.047UF

C7012

1

2

5%

201

1/20W

MF

10K

R7011

1 2

LT3470AED

CRITICAL

DFN

U7090

2

3

1

5

7

8 4

9

6

PLACEMENT_NOTE=PLACE NEAR U7100 and U7001

0.1UF

CERM 402

20% 10V

C7008

1

2

41 42 43 57

SOT665

TC7SZ08FEAPE

CRITICAL

U7001

2

1

3

5

4

10V

20%

402

CERM

0.1UF

C7000

1

2

5%

0

0201

1/20W

MF

R7001

1 2

OMIT

NONE NONE

402

NONE

NOSTUFF

C7001

1

2

201

1/20W MF

1%

49.9K

NOSTUFF

R7002

1

2

DC-In & Battery Connectors

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

VOLTAGE=18.5V

PPBUS_G3H_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm

SWITCH_NODE=TRUE DIDT=TRUE

MIN_NECK_WIDTH=0.25 mm

DIDT=TRUE

P3V42G3H_BOOST

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=1MM VOLTAGE=20V

PP20V_DCIN_FUSE

VOLTAGE=20V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PPVIN_G3H_P3V42G3H

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PP20V_DCIN_CONN_R

VOLTAGE=20V

PPDCIN_G3H_ISOL

PPBUS_G3H

ADAPTER_SENSE

SMC_BC_ACOK

SYS_ONEWIRE

PP3V42_G3H

PPDCIN_G3H

TP_TDM_ONEWIRE_MPM

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

PPVBAT_G3H_CONN

PP3V42_G3H

P3V42G3H_FB

P3V42G3H_SHDN_L

SYS_DETECT_L

DCIN_ISOL_GATE

DCIN_ISOL_GATE_R

SMC_BC_ACOK_VCC

<SCH_NUM>

70 OF 118

56 OF 81

71

45 57 69

30 45 57 63 69 71

71

19 35 38 39 41 42

43 44 50

56 57 66

69 71

57 69 71

41 44 57 71 80

57 71

19 35 38 39 41 42 43 44 50 56 57 66 69 71

71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

OUT

IN

BI

OUT

AMON BMON ACOK

LGATE

PHASE

BOOT

SGATE AGATE

CSIP CSIN

DCIN

VNEG CSOP CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE ICOMP VCOMP

ACIN

SDA VFRQ CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

G

D

S

IN

NC

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

NCNCNC

G

S

D

S

D

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(L7130 limit) f = 400 kHz

Reverse-Current Protection

(CHGR_DCIN)

(CHGR_SGATE)

For Erp Lot6 spec

TO SYSTEM

(P5V1_BIAS)

(CHGR_CSO_P)

(PPVBAT_G3H_CHGR_R)

(GND)

Vout = 5.50V

Vout = 1.25V * (1 + Ra / Rb)

20V/V

TO/FROM BATTERY

36V/V

(AGND)

(CHGR_BGATE)

(CHGR_AGATE)

(PPVBAT_G3H_CHGR_R)

353S2392

(OD)

Max Current = 8A

(Switcher limit)

100MA MAX OUTPUT

<Rb>

<Ra>

FROM ADAPTER

30mA max load

(CHGR_CSO_N)

Inrush Limiter

152S1466

Sparkitecture impedance is set by R7112 in D2

Divider sets ACIN threshold at 13.55V

ACIN pin threshold is 3.2V, +/- 50mV

0.1UF

50V

10%

0402

X5R-CERM

C7142

1

2

470PF

CERM 0402

10% 50V

C7116

1

2

1/16W

3.01K

MF-LF

402

1%

R7116

1

2

220PF

X7R-CERM

0402

10% 50V

C7115

1

2

330K

MF-LF 402

5% 1/16W

R7115

1

2

1UF

X5R 402

10% 10V

C7102

1

2

X5R

10% 10V

402-1

1UF

C7100

1

2

4.7

MF-LF

402

5%

1/16W

R7101

1 2

X7R-CERM

10%

0.01UF

0402

16V

C7157

1

2

0.1UF

X7R-CERM

0402

10% 16V

C7156

1

2

SM

PLACE_NEAR=U7100.29:1mm

PLACE_NEAR=U7100.22:1mm

XW7100

1 2

1UF

X5R 402

10% 10V

C7101

1

2

0.1UF

X5R 402

10% 25V

C7121

1

2

0.1UF

X5R 402

10% 25V

C7122

1

2

X5R-CERM 0402

10% 10V

0.047UF

C7120

1

2

0.22UF

CERM 402

10%

PLACE_NEAR=U7100.25:2mm

10V

C7125

1

2

CRITICAL

RJK0305DPB

LFPAK-HF

Q7135

5

4

1 2 3

10

MF-LF

402

5%

1/16W

R7122

1 2

1/16W

402

10

MF-LF

5%

R7121

1 2

2.2

MF-LF

4025%

1/16W

R7151

1 2

0

MF-LF

4025%

1/16W

R7152

1 2

45

41 44 56 71 80

0.01UF

X7R-CERM

0402

10% 16V

C7111

1

2

1UF

X5R 402

10% 16V

C7150

1

2

0.001UF

X7R-CERM

0402

10% 50V

C7126

1

2

41 42 43 56

MF-LF

0.020

0.5%

0612

1W

CRITICAL

R7120

214

3

0.001UF

X7R-CERM 0402

10% 50V

C7137

1

2

X7R-CERM

0.001UF

0402

10% 50V

C7145

1

2

CRITICAL

ISL6259

TQFN

U7100

3

14

1

9

16

15

25

6

27

28

17

18

2

5

21

22

23

11 10

26

13

29

24

7

19

20

4

12

8

100K

MF-LF 402

5% 1/16W

NO STUFF

R7102

1

2

66

CRITICAL

SI7137DP

SO-8

Q7155

5

4

1 2 3

CRITICAL

BAT30CWFILM

SOT-323

D7105

1

2

3

1K

MF-LF

402

1%

1/16W

R7112

1

2

CRITICAL

RJK0332DPB-01

LFPAK-SM

Q7130

5

4

1 2 3

CRITICAL 68UF

POLY-TANT CASE-D2E-SM

20% 16V

C7140

1

2

20

MF-LF

402

5%

1/16W

R7105

1 2

CRITICAL

1UF

X5R 603

10% 35V

C7135

1

2

CRITICAL

1UF

X5R 603

10% 35V

C7136

1

2

603-1

1UF

X5R

10% 25V

C7155

1

2

0

MF-LF

402

5%

1/16W

R7100

1 2

41 42

50

71

0.1UF

402

X5R

10% 25V

C7185

1

2

470K

MF-LF

402

1%

1/16W

R7185

1

2

332K

MF-LF

402

1%

1/16W

R7186

1

2

1/16W

62K

MF-LF 402

5%

R7181

1

2

402

100K

MF-LF

5% 1/16W

R7180

1

2

CRITICAL

0603

8AMP-32V-0.006OHM

F7141

1 2

CRITICAL

0603

8AMP-32V-0.006OHM

F7140

1 2

CRITICAL

0.005

MF

1% 1W

0612-3

R7150

2 1 4 3

CRITICAL

4.7UH-20%-14.5A-9MOHM

PIME173T-SM

L7130

1 2

CRITICAL 10UF

TANT-POLY CASE-D2-SM

20% 35V

C7130

1

2

CRITICAL

10UF

TANT-POLY CASE-D2-SM

20% 35V

C7131

1

2

CRITICAL 10UF

TANT-POLY CASE-D2-SM

20% 35V

C7132

1

2

CRITICAL

10UF

TANT-POLY CASE-D2-SM

20% 35V

C7133

1

2

CRITICAL

10UF

TANT-POLY CASE-D2-SM

20% 35V

C7134

1

2

1K

5%

402

MF-LF

1/16W

R7142

1

2

681K

MF

201

1%

1/20W

R7195

1

2

CRITICAL

10UF

X5R 0603

20% 10V

C7198

1

2

200K

MF

201

1%

1/20W

R7196

1

2

0.22UF

CERM

402

10% 10V

C7194

1

2

CRITICAL

33UH-20%-0.39A-0.435OHM

DP418C-SM

L7195

1 2

22PF

NP0-C0G-CERM 0201

5% 50V

C7195

1

2

4.7UF

X5R-CERM

0805

10% 35V

C7190

1

2

CRITICAL

LT3470A

DFN

U7190

2

3

1

5

7

8 4

9

6

0

MF-LF

4025%

1/16W

NOSTUFF

R7190

1 2

0

MF-LF

4025%

1/16W

CHGR_5V:LDO

R7191

1 2

CRITICAL

10UF

X5R 0603

20% 10V

C7199

1

2

0

4025%

1/16W

CHGR_5V:LDO

MF-LF

R7192

1 2

0.22UF

X5R-CERM

0603-1

10% 50V

C7105

1

2

130K

MF-LF 402

1% 1/16W

R7110

1

2

40.2K

MF-LF 402

1% 1/16W

R7111

1

2

603

OMIT

NONE NONE

NONE

NOSTUFF

C7180

1

2

DIRECTFET-MC

CRITICAL

IRF9395TRPBF

Q7180

879

10

6

3

415

2

PBus Supply & Battery Charger

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

VOLTAGE=12.6V

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=20V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

CHGR_PHASE

SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_BOOT

MIN_NECK_WIDTH=0.2 mm

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=5.1V

DIDT=TRUE

SWITCH_NODE=TRUE

P5V1_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

DIDT=TRUE

P5V1_BOOST

GATE_NODE=TRUE

DIDT=TRUE

CHGR_LGATE

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

CHGR_DCIN_D_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

P5V1_VIN

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

P5V1_BIAS

CHGR_SGATE_DIV

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H_INRUSH

MIN_NECK_WIDTH=0.25 mm VOLTAGE=20V

GND_CHGR_AGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

CHGR_UGATE

CHGR_SGATE

CHGR_DCIN

PPDCIN_G3H_ISOL

CHGR_CSO_P

CHGR_CSI_R_P

CHGR_CSI_R_N

CHGR_CSI_N

CHGR_ACIN

CHGR_CELL

CHGR_VNEG_R

PP3V42_G3H

P5V1_FB

SMBUS_SMC_5_G3_SDA

CHGR_ICOMP_RC

CHGR_VNEG

CHGR_RST_L

CHGR_VFRQ

GND_CHGR_AGND

SMBUS_SMC_5_G3_SCL

CHGR_VCOMP

CHGR_AMON

SMC_RESET_L

CHGR_DCIN_D_R

CHGR_DCIN

PP5V1_CHGR_VDDP

CHGR_ICOMP

CHGR_VCOMP_R

CHGR_BMON SMC_BC_ACOK

CHGR_CSO_N

PPBUS_G3H

PPDCIN_G3H

CHGR_CSI_P

CHGR_AGATE

CHGR_CSO_R_N

CHGR_CSO_R_P

PP5V1_CHGR_VDD

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=5.1V

CHGR_BGATE

PPVBAT_G3H_CHGR_R

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.6V

PPVBAT_G3H_CONN

<SCH_NUM>

71 OF 118

57 OF 81

57

45 56 69

80

81

80

19 35 38 39 41 42 43 44 50 56 66 69 71

57

80

30 45 56 63 69 71

56 69 71

80

81

56 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

BI

IN

OUT

IN

OUT

ISEN3

ISEN2

ISEN1

IMON

ISUMN

ISUMP

FB2

FB

RTN

COMP

SCLK

ALERT*

SDA

NTC

VINVDD

FCCM

PWM1

PWM2

PWM3

DRSEL

PGOOD

THRM

VR_ON

PROG3

NC

NC NC

PROG2

SLOPE

VR_HOT*

PROG1

PAD

OUT

NC

NC NC

OUT OUT OUT

NC

IN IN IN

IN

OUT

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(CPU_VCCSENSE_N)

(GND)

(CPUVR_ISUMP)

8

74

8

74

8

74

18 19 41 66 71

6

41 42 74

PLACE_NEAR=U7200.32:2mm

54.9

1% MF

1/20W

201

R7279

1

2

PLACE_NEAR=U7200.30:2mm

1%

110

MF

1/20W 201

R7280

1

2

OMIT_TABLE

ISL95826

CRITICAL

LLP

U7200

31

6

25

7 8

18

3

12 11 10

14

15

9

19 21 24

5

2

28 27 26 20

22

23

13

32

30

29

33

16

17

4

1

19

59

1%

1/16W

0402

2.49M

MF

R7224

1 2

1/16W MF-LF

10

402

5%

R7202

1 2

PLACE_NEAR=U7200.17:2mm

X7R

25V

10%

0.22UF

0402

C7202

1

2

1/16W MF-LF

402

1

5%

R7201

1 2

402-1

1UF

10% 10V X5R

PLACE_NEAR=U7200.16:2mm

C7201

1

2

59

0201

20%

6.3V X6S-CERM

0.22UF

C7210

1

2

6.3V

20%

0201

0.22UF

X6S-CERM

C7211

1

2

0.22UF

X6S-CERM 0201

6.3V

20%

C7212

1

2

59

6.3V 0201

X6S

10%

0.1UF

C7213

1

2

4.02K

1% MF

1/20W 201

R7220

1

2

1%

154K

MF

1/20W 201

R7221

1

2

46

90.9K

1% MF

1/20W 201

R7230

1

2

0201

10V

1500PF

10% X7R

C7230

1

2

59

220PF

X7R-CERM

25V

10%

NO_XNET_CONNECTION=TRUE

201

C7214

1

2

1%

845

MF

1/20W

201

R7215

1 2

2700PF

10%

X7R-CERM

10V

201

C7215

1 2

39PF

NP0-C0G

25V

201

5%

C7216

1 2

8

74

9

74

X7R-CERM 0201

330PF

10% 16V

C7260

1

2

330PF

10% 16V X7R-CERM 0201

C7261

1

2

0201

1800PF

25V

10%

X7R-CERM

C7240

1

2

100PF

NO_XNET_CONNECTION=TRUE

25V

0201

NP0-CERM

5%

C7242

12

18PF

NP0-C0G-CERM

0201

25V

NO_XNET_CONNECTION=TRUE

5%

C7241

1

2

365K

1%

NO_XNET_CONNECTION=TRUE

MF

1/20W

201

R7240

1

2

1K

1% MF

1/20W

201

R7242

12

MF

1/20W

0201

0

5%

R7243

1 2

9.31K

1% MF

1/20W

201

R7235

1 2

95.3K

1% MF

1/20W

201

R7236

1

2

100KOHM

0201

R7237

1

2

2K

1%

NO STUFF

NO_XNET_CONNECTION=TRUE

MF

1/20W

201

R7250

1 2

NO STUFF

330PF

X7R-CERM

16V

10%

0201

C7250

1

2

2.87K

1% MF

1/20W

201

R7241

1 2

1%

487

MF

1/20W

201

R7210

1 2

1%

102K

MF

1/20W 201

R7223

1

2

1%

9.31K

MF

1/20W 201

R7222

1

2

25V

47PF

NP0-C0G-CERM

0201

5%

C7231

1

2

0.01UF

X7R-CERM 0402

10% 16V

C7279

1

2

CPU VR12.5 VCC Regulator IC

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

1

353S4170

IC,ISL95826R6200,PWM,PGOOD,SCREEN,32P,QFN

CRITICAL

U7200

CPUVR_NTC_R

CPU_VIDALERT_L

CPU_VIDSOUT

CPUVR_NTC

PPVCCIO_S0_CPU

CPU_VCCSENSE_P_R

CPUVR_COMP

CPUVR_ISUMP

CPUVR_FB2

ALL_SYS_PWRGD

CPUVR_PROG2

CPU_VCCSENSE_P

CPUVR_ISUMN

CPUVR_COMP_RC

CPUVR_PROG3

CPUVR_PWM1

CPUVR_ISUMN_RC

PPVIN_S5_HS_COMPUTING_ISNS

CPU_VCCSENSE_P_RC

CPUVR_PGOOD

CPUVR_PWM3 CPUVR_PWM2

CPUVR_FCCM

CPUVR_DRSEL

PP5V_S0

CPUVR_SLOPE

VOLTAGE=12.9V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVIN_S0_CPUVR_VIN

VOLTAGE=5V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP5V_S0_CPUVR_VDD

CPUVR_ISUMN_R CPUVR_IMON

CPUVR_ISEN1 CPUVR_ISEN2

CPUVR_FB_RC

CPUVR_FB

CPU_VCCSENSE_N

CPU_PROCHOT_L

CPUVR_ISEN3

CPUVR_PROG1

CPU_VIDSCLK

<SCH_NUM>

72 OF 118

58 OF 81

5 6 8

10 18

45 59 60 62 69 18 19 37 49 50 59 62 63 65 66

69 70 71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

IN

OUT

IN

OUT

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

NC

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

NC

IN

NC

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Additonal Input Bulk Caps

THESE TWO CAPS ARE FOR EMC

Vout = 1.85V max 95A max output f = 450 kHz

THESE TWO CAPS ARE FOR EMC

152S1538

353S3836

PHASE 1

PHASE 3

PHASE 2

353S3836

152S1538

20% 16V

CASE-D2E-SM

POLY-TANT

68UF

CRITICAL

C7372

1

2

20% 16V POLY-TANT CASE-D2E-SM

68UF

CRITICAL

C7371

1

2

CRITICAL

CASE-D2E-SM

POLY-TANT

68UF

20% 16V

C7370

1

2

0402

X7R-CERM

50V

10%

0.001UF

C7319

1

2

X7R-CERM

50V 0402

10%

0.001UF

C7318

1

2

16V X6S-CERM 0402

10%

1UF

C7317

1

2

0603

NOSTUFF

CRITICAL

16V X6S-CERM

20%

10UF

C7316

1

2

20% 16V X6S-CERM 0603

10UF

CRITICAL

NOSTUFF

C7315

1

2

CRITICAL

0612

MF

1% 1W

0.00075

R7310

1 2 3 4

3.9

1%

201

MF

1/20W

R7314

1

2

POLY-TANT CASE-D2E-SM

20% 16V

68UF

CRITICAL

C7314

1

2

CRITICAL

CASE-D2E-SM

POLY-TANT

20% 16V

68UF

C7313

1

2

0.36UH-20%-36A-0.00108OHM

CRITICAL

PIMS103T-SM

L7310

1 2

603

MF-LF

1/10W

2.2

5%

NOSTUFF

R7312

1

2

0.001UF

NOSTUFF

50V

10% X7R-CERM

0402

C7312

1

2

58

58 59

20% 16V

CASE-D2E-SM

POLY-TANT

68UF

CRITICAL

C7373

1

2

NO_XNET_CONNECTION=TRUE

10K

1/20W

1% MF

201

R7316

1

2

1/20W

201

1K

1% MF

R7315

1

2

58

58 59

NO_XNET_CONNECTION=TRUE

201

MF

1%

1/20W

10K

R7317

1 2

0.001UF

10% 50V

0402

X7R-CERM

C7329

1

2

58 59

10%

0402

50V

0.001UF

X7R-CERM

C7328

1

2

16V

1UF

10%

0402

X6S-CERM

C7327

1

2

3.9

1%

201

MF

1/20W

R7324

1

2

20%

0603

16V X6S-CERM

CRITICAL

NOSTUFF

10UF

C7326

1

2

NOSTUFF

16V

0603

X6S-CERM

20%

10UF

CRITICAL

C7325

1

2

CRITICAL

68UF

16V

20%

POLY-TANT CASE-D2E-SM

C7324

1

2

16V

68UF

POLY-TANT CASE-D2E-SM

20%

CRITICAL

C7323

1

2

0.36UH-20%-36A-0.00108OHM

PIMS103T-SM

CRITICAL

L7320

1 2

0402

50V

10%

NOSTUFF

0.001UF

X7R-CERM

C7322

1

2

1% MF

201

1/20W

10K

NO_XNET_CONNECTION=TRUE

R7326

1

2

1/20W

MF

201

1K

1%

R7325

1

2

MF-LF

1/10W

2.2

603

5%

NOSTUFF

R7322

1

2

58

10%

0.001UF

50V X7R-CERM 0402

C7339

1

2

58 59

0402

X7R-CERM

50V

10%

0.001UF

C7338

1

2

0402

X6S-CERM

16V

1UF

10%

C7337

1

2

3.9

1%

201

MF

1/20W

R7334

1

2

10UF

0603

X6S-CERM

16V

20%

CRITICAL

NOSTUFF

C7336

1

2

0603

X6S-CERM

16V

10UF

20%

NOSTUFF

CRITICAL

C7335

1

2

POLY-TANT CASE-D2E-SM

CRITICAL

16V

20%

68UF

C7334

1

2 POLY-TANT CASE-D2E-SM

16V

68UF

20%

CRITICAL

C7333

1

2

PIMS103T-SM

0.36UH-20%-36A-0.00108OHM

CRITICAL

L7330

1 2

0.001UF

50V

10% X7R-CERM

0402

NOSTUFF

C7332

1

2

201

1% MF

10K

1/20W

NO_XNET_CONNECTION=TRUE

R7336

1

2

1/20W

MF

1%

201

1K

R7335

1

2

1/10W

603

MF-LF

5%

2.2

NOSTUFF

R7332

1

2

58

58 59

58

58 59

FDMF6808N

PQFN

CRITICAL

U7310

4

5

37

41

39

6

36

8

16

17

262728

18192021222324

25

7

40

38

2

3

9 10 11 12 13 14 42

15 29 30 31 32 33 34 35 43

1

1/16W

402

0

MF-LF

5%

R7311

21

0.22UF

402

CERM

16V

10%

C7311

1 2

0402

X6S-CERM

10% 16V

1UF

C7310

1

2

FDMF6808N

PQFN

CRITICAL

U7320

4

5

37

41

39

6

36

8

16

17

262728

18192021222324

25

7

40

38

2

3

9 10 11 12 13 14 42

15 29 30 31 32 33 34 35 43

1

0402

X6S-CERM

10% 16V

1UF

C7320

1

2

402

0

1/16W MF-LF

5%

R7321

21

402

0.22UF

CERM

16V

10%

C7321

1 2

58 59

1UF

16V

10%

X6S-CERM

0402

C7330

1

2

CRITICAL

PQFN

FDMF6808N

U7330

4

5

37

41

39

6

36

8

16

17

262728

18192021222324

25

7

40

38

2

3

9 10 11 12 13 14 42

15 29 30 31 32 33 34 35 43

1

402

5%

MF-LF

1/16W

0

R7331

21

10% 16V

CERM

0.22UF

402

C7331

1 2

58

58 59

MF

1% 1W

0.00075

0612

CRITICAL

R7320

12 34

1%

0.00075

1W MF

0612

CRITICAL

R7330

1 2 3 4

68UF

CRITICAL

POLY-TANT CASE-D2E-SM

16V

20%

C7376

1

2

CRITICAL

68UF

CASE-D2E-SM

POLY-TANT

16V

20%

C7375

1

2

CRITICAL

CASE-D2E-SM

POLY-TANT

68UF

20% 16V

C7374

1

2

16V

SM

TANT

15UF

20%

CRITICAL

C7377

1

2

SM

TANT

15UF

20% 16V

CRITICAL

C7378

1

2

SM

TANT

15UF

20% 16V

CRITICAL

C7379

1

2

SM

TANT

15UF

20% 16V

CRITICAL

C7380

1

2

201

MF

1%

1/20W

NO_XNET_CONNECTION=TRUE

10K

R7318

1 2

NO_XNET_CONNECTION=TRUE

1%

10K

201

1/20W

MF

R7327

1 2

NO_XNET_CONNECTION=TRUE

1%

10K

201

1/20W

MF

R7328

1 2

NO_XNET_CONNECTION=TRUE

1%

10K

201

1/20W

MF

R7337

1 2

MF

1/20W

201

10K

1%

NO_XNET_CONNECTION=TRUE

R7338

1 2

CRITICAL

CASE-D2E-SM

POLY-TANT

68UF

20% 16V

C7381

1

2

CRITICAL

POLY-TANT CASE-D2E-SM

68UF

20% 16V

C7382

1

2

CRITICAL

CASE-D2E-SM

POLY-TANT

68UF

20% 16V

C7383

1

2

16V

20%

68UF

POLY-TANT CASE-D2E-SM

CRITICAL

C7384

1

2

SYNC_MASTER=J15_MLB

CPU VR12.5 VCC Power Stage

SYNC_DATE=10/31/2012

CPUVR_ISUMN

CPUVR_ISNS1_P

PPVIN_S5_HS_COMPUTING_ISNS

PPVCC_S0_CPU_PH3

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

CPUVR_PH2_SNUB

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUVR_PHASE3

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=1.5 MM

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=1.5 MM

CPUVR_PHASE2

MIN_NECK_WIDTH=0.2 MM

CPUVR_BOOT2_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_PHASE1

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

CPUVR_BOOT3

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

CPUVR_BOOT1

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

CPUVR_BOOT3_RC

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_BOOT1_RC

CPUVR_PH3_SNUB

DIDT=TRUE

CPUVR_PH1_SNUB

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

PPVCC_S0_CPU_PH1

PPVCC_S0_CPU_PH2

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

CPUVR_BOOT2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_ISEN3

CPUVR_ISNS2_N

CPUVR_ISNS1_N

CPUVR_ISEN2

CPUVR_ISNS3_N

CPUVR_ISNS1_N

CPUVR_FCCM

CPUVR_ISUMN

CPUVR_ISNS3_NCPUVR_ISNS3_P

CPUVR_ISUMP

CPUVR_ISNS2_P CPUVR_ISNS2_N

CPUVR_PWM2

PP5V_S0

CPUVR_FCCM

CPUVR_PWM3

PP5V_S0

CPUVR_ISUMN

CPUVR_ISNS1_N

CPUVR_ISNS2_N

CPUVR_PWM1

PP5V_S0

CPUVR_PHASE1_K

CPUVR_PHASE2_K

CPUVR_PHASE3_K

CPUVR_ISNS3_N

CPUVR_ISEN1

PPVCC_S0_CPU

<SCH_NUM>

73 OF 118

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46 59 81

46 81

46 81 46 59

81

18 19 37 49 50 58 59 62 63 65 66 69 70 71

46 59 81

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66 69 70 71

46 59 81

6 8

10 46 69 71

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w w w . c h i n a f i x . c o m

IN

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

IN

VSW

PGND

TGR

TG

BG

VIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

f = 400 kHz

Vout = 1.35V 18A max output (Q7335 limit)

10mA max load

(VDDQ/VTTREF Enable)

(DDRREG_VDDQSNS)

(DDRREG_LL)

152S0905

(VTT Enable)

C7460, C7461 close to memory

DDR3L (1V35 S3) REGULATOR

(DDRREG_DRVH)

(DDRREG_DRVL)

BYPASS=U7400.12:10:5MM

10V 603

X5R

10UF

20%

C7400

1

2

16V

CASE-D2E-SM

POLY-TANT

68UF

20%

CRITICAL

C7430

1

2

1/16W

5%

402

MF-LF

1

R7430

1 2

16V

20%

CASE-D2E-SM

POLY-TANT

68UF

CRITICAL

C7431

1

2

603-1

25V

10% X5R

1UF

C7432

1

2

0.1UF

X7R

10% 50V

603-1

C7425

1 2

50V

10%

0402

X7R-CERM

0.001UF

C7433

1

2

270UF

2V

20%

CASE-B4-SM

TANT

CRITICAL

C7440

1

2

0.68UH-18A-3.3MOHM

CRITICAL

PCMB103T

L7430

1 2

2V

20%

CASE-B4-SM

TANT

270UF

CRITICAL

C7441

1

2

6.3V

20%

603

X5R

10UF

C7445

1

2

X7R-CERM

50V

10%

0402

0.001UF

C7446

1

2

PLACE_NEAR=C7440.1:1MM

SM

XW7401

1

2

66

TPS51916

QFN

CRITICAL

U7400

14

11

7

19

10

20

8

17 16

13

21

18

12 15

9

2

6

3

4

5

1

66

SM

PLACE_NEAR=C7461.1:3mm

XW7460

1 2

SM

XW7400

1

2

0.22UF

10% 10V

402

CERM

BYPASS=U7400.5:7:5mm

C7450

1

2

603

PLACE_NEAR=C2730.1:1mm

6.3V

20% X5R

10UF

C7460

1

2

21 70

16V

10%

0402

X7R-CERM

0.1UF

C7415

1

2

PLACE_NEAR=C2724.1:3mm

10UF

X5R 603

20%

6.3V

C7461

1

2

200K

MF-LF 402

1% 1/16W

R7417

1

2

MF-LF 402

1% 1/16W

19.6K

R7415

1

2

MF-LF

1/16W

1%

402

60.4K

R7416

1

2

16V

10% 0402

X7R-CERM

0.01UF

C7416

1

2

BYPASS=U7400.2:10:5MM

10V

20% 603

X5R

10UF

C7401

1

2

25V

10% X5R

1UF

603-1

C7434

1

2

SON5X6

CSD58872Q5D

CRITICAL

Q7430

5

9

3

4

1

6 7 8

1/16W

1%

402

MF-LF

52.3K

R7418

1

2

16V

TANT

20%

CRITICAL

SM

15UF

C7435

1

2

1.35V DDR3L SUPPLY

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

GND_DDRREG_SGND

VOLTAGE=0V

DDRREG_EN

DDRREG_1V8_VREF

DDRREG_VTTSNS

PPVIN_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DDRREG_VSW

DIDT=TRUE

SWITCH_NODE=TRUE

DDRREG_VDDQSNS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

SWITCH_NODE=TRUE

DIDT=TRUE

DDRREG_LL

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DDRREG_DRVH

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST

DIDT=TRUE

GATE_NODE=TRUE

DDRREG_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVH_R

PP1V35_S3

DDRREG_PGOOD

PPVTT_S0_DDR

PP1V35_S3

DDRREG_FB

PP5V_S3

PPVTTDDR_S3

MEMVTT_EN

DDRREG_TRIP

DDRREG_MODE

<SCH_NUM>

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OUT

IN

EN

EN2EN1

DRVL2

SKIPSEL1 SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2 CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

IN

OUT

VSW

PGND

TGR

TG

BG

VIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

F = 400 KHZ

VOUT = 5V 100MA MAX OUTPUT

VOUT = 3.3V 10A MAX OUTPUT

VOUT = 5.0V

F = 400 KHZ

152S0754

(P5VP3V3_VREF2)

11A MAX OUTPUT

(P5VP3V3_VREF2)

1UF

X5R

603-1

10% 25V

C7500

1

2

CRITICAL

1.0UH-22A

PCMC063T-SM

L7560

12

0.1UF

10% 50V X7R

603-1

C7564

1

2

10UF

X5R 603

20%

6.3V

C7590

1

2

X7R 603-1

10% 50V

0.1UF

C7524

1

2

20%

CASE-D3L-SM

POLY-TANT

6.3V

330UF

CRITICAL

C7552

1

2

CRITICAL

805

20% X5R

10UF

10V

C7550

1

2

25V

10% 603-1

X5R

1UF

C7581

1

2

X5R-CERM

2.2UF

402

20% 10V

C7503

1

2

6.3V

10UF

X5R 603

20%

C7505

1

2

402

1% 1/16W MF-LF

249K

R7506

1

2

66

SM

PLACE_NEAR=L7560.2:3MM

XW7561

1

2

0.22UF

CERM

402

10% 10V

C7501

1

2

23.2K

MF-LF

402

1%

1/16W

R7560

1

2

10K

MF-LF

402

1%

1/16W

R7561

1

2

40.2K

MF-LF 402

1% 1/16W

R7520

1

2

10K

MF-LF 402

1% 1/16W

R7521

1

2

POLY-TANT

CASE-D2E-SM

16V

20%

68UF

CRITICAL

C7580

1

2

0.15UF

402

X5R

10V

10%

C7588

1 2

PLACE_NEAR=L7560.1:3MM

SM

XW7560

1

2

10% 10V X5R 402

0.15UF

C7518

1 2

3.24K

MF-LF

402

1%

1/16W

R7547

1 2

1/16W

1%

402

MF-LF

4.75K

R7556

1

2

SM

PLACE_NEAR=L7520.1:3MM

XW7520

1

2

SM

PLACE_NEAR=L7520.2:3MM

XW7521

1

2

12.1K

MF-LF

402

1%

1/16W

R7536

1

2

10K

MF-LF 402

1% 1/16W

R7537

1

2

CERM

402

15PF

50V

5%

C7537

1

2

SM

PLACE_NEAR=L7560.2:3MM

XW7562

1

2

SM

PLACE_NEAR=L7520.1:3MM

XW7522

1

2

330UF

POLY-TANT CASE-D3L-SM

20%

6.3V

CRITICAL

C7592

1

2

20.0K

1/16W

1%

402

MF-LF

R7539

1

2

47PF

50V CERM 402

5%

C7539

1

2

12.1K

MF-LF 402

1% 1/16W

R7538

1

2

66

10%

0.0033UF

X7R-CERM

0402

50V

NO STUFF

C7599

1

2

NO STUFF

1/10W MF-LF

1

5%

603

R7599

1

2

10

MF-LF

603

1/10W

NO STUFF

5%

R7598

1

2

10% 50V

0402

X7R-CERM

0.001UF

C7572

1

2

50V

10% 0402

X7R-CERM

0.001UF

C7583

1

2

X7R-CERM 0402

10% 50V

0.001UF

C7570

1

2

10% 0402

X7R-CERM

50V

0.001UF

C7571

1

2

TPS51980

QFN

CRITICAL

U7501

10

15

8

17

7

18

1

24

30

27

12

4

21

28

11

14

5

20

3

6

19

32

25

33

2

31

26

9

16

23

13

22

29

20%

CASE-D2E-SM

68UF

CRITICAL

POLY-TANT

16V

C7542

1

2

16V

CASE-D2E-SM

20%

POLY-TANT

68UF

CRITICAL

C7582

1

2

41 42 66

CRITICAL

RJK0214DPA

WPAK2

Q7560

2

1

6

7

3 4 5

1K

1/16W

1%

402

MF-LF

R7546

1 2

4.02K

MF-LF 402

1/16W

1%

R7516

1

2

MF-LF

402

1/16W

0

5%

R7563

1 2

1

MF-LF

402

1/16W

5%

R7544

1

2

X5R

10% 25V

1UF

603-1

C7541

1

2

66

41 66

NO STUFF

0.001UF

X7R-CERM 0402

10% 50V

C7598

1

2

PLACE_NEAR=U7501.28:1MM

SM

XW7500

1

2

CRITICAL

CSD58872Q5D

SON5X6

Q7520

5

9

3

4

1

6 7 8

SKIP_5V3V3:AUDIBLE

MF

1/20W

0201

0

5%

R7500

1

2

SKIP_5V3V3:INAUDIBLE

MF

1/20W

0201

0

5%

R7501

1

2

6.3V CASE-B2-SM

20% POLY-TANT

150UF-0.035OHM

CRITICAL

C7553

1

2

CRITICAL

20%

150UF-0.035OHM

6.3V

POLY-TANT

CASE-B2-SM

C7554

1

2

20%

6.3V

150UF-0.035OHM

CRITICAL

POLY-TANT

CASE-B2-SM

C7593

1

2

2.2UH-20%-13A-9MOHM

CRITICAL

PCMB103T-SM

L7520

1

2

4700PF

CERM 402

10% 100V

C7536

1

2

4700PF

CERM

402

10%

100V

C7538

1

2

CRITICAL

20%

6.3V

POLY-TANT

CASE-B2-SM

150UF-0.035OHM

C7594

1

2

CASE-B2-SM

NO STUFF CRITICAL

POLY-TANT

20%

6.3V

150UF-0.035OHM

C7555

1

2

CRITICAL

SM

15UF

20% 16V

TANT

C7585

1

2

SM

16V

TANT

20%

15UF

CRITICAL

C7584

1

2

15UF

TANT

20%

SM

CRITICAL

16V

C7543

1

2

CRITICAL

68UF

20% 16V

CASE-D2E-SM

POLY-TANT

C7544

1

2

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

5V / 3.3V Power Supply

PP5V_S4

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P5VS4_VSW

P3V3S5_COMP2

MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

GND_5V3V3_AGND

MIN_LINE_WIDTH=0.2 MM

P3V3S5_VFB2_R

P3V3S5_COMP2_R

P5VS4_CSN1

P5VS4_VFB1

P3V3S5_VBST

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

SMC_PM_G2_EN

P5VS4_COMP1

P5VS4_PGOOD

P5VS4_VFB1_R

P3V3S5_EN

P5VS4_COMP1_R

P5VS4_EN

PP5V_S4

S5_PWRGD

P5VP3V3_VREG3

P5VP3V3_SKIPSEL

P3V3S5_RF

P5VS4_CSP1

P3V3S5_CSP2_R

DIDT=TRUE

P5VS4_SNUBR

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

P3V3S5_DRVH

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

SWITCH_NODE=TRUE

DIDT=TRUE

P5VS4_LL

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

P5VS4_TG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P3V3S5_SNUBR

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

P5VS4_VBST

DIDT=TRUE

P5VS4_DRVH

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

P5VS4_DRVL

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

DIDT=TRUE

P3V3S5_DRVL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM

P3V3S5_TG

MIN_NECK_WIDTH=0.2 MM

PP5V_S5

P3V3S5_CSP2

PPVIN_S5_HS_OTHER3V3_ISNS

PP3V3_S5

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM

P3V3S5_LL

MIN_NECK_WIDTH=0.2 MM

P3V3S5_VFB2

P3V3S5_CSN2

P5VP3V3_VREF2

DIDT=TRUE

P5VS4_CSP1_R

PPVIN_S5_HS_OTHER5V_ISNS

61 OF 81

<SCH_NUM>

75 OF 118

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39 65 69 71

45 69

12 14 15 17 18 19 21 31 32 34

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OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Vout = 1.05V 12A MAX OUTPUT

Vout = 0.5V * (1 + Ra / Rb)

(PCHVCCIOS0_OCSET)

(PCHVCCIOS0_VO)

1V05 S0 REGULATOR

376S0953

OCP = 14.4A

f = 300 kHz

152S0955

OCP = R7641 x 8.5uA / R7640

1/16W

1%

3.01K

MF-LF 402

R7644

1

2

66

16V

10%

603

X5R

2.2UF

BYPASS=Q9800.13:1:5mm

C7602

1

2

NO STUFF

1/16W

5%

402

MF-LF

0

R7603

1

2

SM

PLACE_NEAR=U7600.1:1mm

XW7600

1 2

ISL95870

UTQFN

CRITICAL

U7600

123

6

5

1

15

7

16

9

10

14

2

4

11

13

8

5%

402

MF-LF

2.2

1/16W

R7601

1

2

BYPASS=Q9800.14:16:5mm

10V

20%

603

X5R

10UF

C7601

1

2

10% 16V

402

X5R

1UF

C7630

1

2

0402

10% 50V

X7R-CERM

0.0018UF

C7640

12

PLACE_NEAR=L7630.2:1.5mm

0402

CERM

1000PF

5%

25V

C7623

1

2

CRITICAL

POLY-TANT

68UF

CASE-D2E-SM

20% 16V

C7620

1

2

CRITICAL

68UF

POLY-TANT

CASE-D2E-SM

20% 16V

C7621

1

2

0402

5% CERM

BYPASS=Q7630.2:5:6mm

25V

1000PF

C7622

1

2

CASE-B4-SM

TANT

CRITICAL

270UF

20% 2V

C7648

1

2

1W

1%

0612

MF-1

0.001

CRITICAL

R7640

2 1 4 3

2V

20%

CASE-B4-SM

TANT

270UF

CRITICAL

C7649

1

2

1/10W

5%

603

MF-LF

0

R7630

1

2

50V

5%

0402

C0G-CERM

10PF

C7604

1

2

WPAK2

RJK0214DPA

CRITICAL

Q7630

2

1

6

7

3 4 5

SM

PLACE_NEAR=U1100.AJ12:1MM

XW7601

1 2

SM

PLACE_NEAR=U1100.AK14:1MM

XW7602

1 2

5%

1.2K

1/16W 402

MF-LF

R7642

1

2

5%

1.2K

1/16W

402

MF-LF

R7641

1

2

C0G-CERM

50V

5% 0402

10PF

C7605

1

2

CRITICAL

PCMC063T-SM

0.68UH-25A-5.5MOHM

L7630

1 2

0.047UF

16V

10% 0402

X7R-CERM

C7603

1

2

1/16W

1%

402

MF-LF

2.74K

R7645

1

2

1%

402

MF-LF

2.74K

1/16W

R7605

1

2

MF-LF

1/16W

1%

402

3.01K

R7604

1

2

1V05V POWER SUPPLY

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

P1V05S0_RTN P1V05S0_FSEL

P1V05S0_VO

P1V05S0_FB

P1V05S0_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

SWITCH_NODE=TRUE

P1V05S0_OCSET

P1V05S0_AGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0V

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V05_S0_REG_R

PPVIN_S5_HS_COMPUTING_ISNS

P1V05S0_CS_N

PP5V_S0

P1V05S0_SENSE_N

PP1V05_S0

P1V05S0_PGOOD

P1V05S0_EN

P1V05S0_SREF

P1V05S0_SENSE_P

PP1V05_S0

P1V05S0_DRVL

MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

P1V05S0_BOOT_RC

DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm

P1V05S0_DRVH

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE

PP5V_S0_P1V05S0_VCC

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm

P1V05S0_CS_P

P1V05S0_VBST

DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

<SCH_NUM>

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81

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81

14 15 17 18 42 62

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81

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http://sualaptop365.edu.vn

GND_SW

SW2 FB2

KEYB1 KEYB2

SDA

SCL

PWM_KEYB

EN

SENSE_OUT

FB

THRM

GNDA

GNDD

GND_SW2

SD VSENSE_N VSENSE_P

SW

ISET_KEYB

GD

VDDA

VDDD

SW

PAD

IN

OUT

VDDA VDDD

SDA_M

FILTER

SYNC PWM

EN SDA SCL

ISET

NC NC NC

SCL_M

OUT1 OUT2 OUT3 OUT4 OUT5 OUT6

THRM

GNDD

GND_L

GNDA

GND

PAD

NC NC NC

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Page Notes

Power aliases required by this page:

- =PPVIN_S0_LCDBKLT (9-12.6V LCD Backlight Input)

- =PP5V_S0_KBDLED (5V Keyboard Backlight Input)

BOM options provided by this page:

C7723, C7724 SHOULD BE PLACED MIRRORED

(PPBUS_S0_BKLT_PWR_F)

(PPBUS_S0_BKLT_PWR_R)

353S4159

PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE

C7718, C7719 SHOULD BE PLACED MIRRORED

BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds

C7720, C7721 SHOULD BE PLACED MIRRORED

(IPU)

152S1527

371S0572

152S1701

BKLT:PROD - Stuffs 0 ohm series R for production

C7715, C7716 SHOULD BE PLACED MIRRORED

- =PP5V_S0_BKLTCTRL (5V Backlight Driver Input)

APN353S4229

LP8548B1SQ_-03

LLP

CRITICAL

U7701

17

21

8

4

7

232422

3

20

13 14

12

15

11

16

19

6

1

2

25

18

5

9

10

603-HF

3AMP-32V-467

CRITICAL

F7700

1 2

22UH-20%-2.4A-0.105OHM

DEM8030C-SM

CRITICAL

L7710

1 2

CRITICAL

PST041H-CDH46D14-SM

10UH-20%-1.4A-0.17OHM

L7720

1 2

201

1/20W MF

80.6K

1%

R7701

1

2

X7R-CERM 0201

1000PF

10% 16V

C7700

1

2

1%

63.4K

402

1/16W MF-LF

R7702

1

2

FDC638APZ_SBMS001

CRITICAL

SSOT6-HF

Q7706

1

2

5

6

3

4

0.1UF

X5R-CERM

10% 16V

0201

C7722

1

2

10%

2.2UF

X5R-CERM 603

25V

C7721

1

2

50V

0.001UF

10% X7R-CERM

0402

C7725

1

2

5%

0

0201

1/20W

MF

R7747

1 2

5% 0201

33PF

25V

NO STUFF

NPO-C0G

C7747

1

2

5%

0

0201

1/20W

MF

R7742

1 2

402-2

10V

10%

1UF

X5R

C7740

1

2

402-2

1UF

X5R

10% 10V

C7741

1

2

5% 1/20W MF

1M

201

R7740

1

2

10.2

1/16W

TF

402

0.1%

BKLT:ENG

R7723

1 2

SM

XW7700

1 2

402

X5R

25V

0.1UF

10%

C7712

1

2

12 70 71

41

NOSTUFF

0.001UF

10%

402

CERM

50V

C7701

1

2

25V

4.7UF

0603

X6S-CERM

10%

C7710

1

2

X6S-CERM

10%

4.7UF

0603

25V

C7711

1

2

201

1/20W MF

31.6K

1%

R7741

1

2

RB160M-60G

SOD-123

CRITICAL

D7720

A K

10% 50V X7R 0805

1.0UF

C7723

1

2

50V X7R 0805

10%

1.0UF

C7724

1

2

X5R-CERM

10% 25V

2.2UF

603

C7720

1

2

5%

NO STUFF

25V NPO-C0G 0201

33PF

C7742

1

2

SM

PLACE_NEAR=D7720.K:2MM

XW7720

1

2

0.025

1%

0612

1W

MTL

R7700

1 2 3 4

47 81

LP8549B1SP_-03

CRITICAL

LLP

U7750

10

13

9

21

12

3

17

14 15 16

24 23 22 20 19 18

7

6

2

5

1

8

25

11

4

BKLT:ENG

402

0.1%

10.2

TF

1/16W

R7724

1 2

150K

1%

MF-LF

1/16W

402

R7709

1

2

402

1/16W MF-LF

1%

18.2K

R7708

1

2

1210-1

10%

2.2UF

X7R

100V

PLACE_NEAR=D7701.K:3MM

CRITICAL

C7715

1

2

DFLS2100

POWERDI-123

CRITICAL

PLACE_NEAR=L7710.2:3MM

D7701

A K

1210-1

X7R

10%

2.2UF

CRITICAL

PLACE_NEAR=D7701.K:5MM

100V

C7716

1

2

1210-1

X7R

2.2UF

10%

CRITICAL

PLACE_NEAR=D7701.K:3MM

100V

C7718

1

2

1210-1

PLACE_NEAR=D7701.K:5MM

100V

2.2UF

CRITICAL

10%

X7R

C7719

1

2

X7R-CERM 0603

PLACE_NEAR=R7708.1:5MM

10%

1000PF

100V

C7717

1

2

PLACE_NEAR=L7710.2:3MM

PWRPK-1212-8

SI7812DN

CRITICAL

Q7701

5

4

1 2 3

402

BKLT:ENG

TF

10.2

0.1%

1/16W

R7722

1 2

402

BKLT:ENG

0.1%

TF

10.2

1/16W

R7721

1 2

1/16W

402

TF

0.1%

10.2

BKLT:ENG

R7720

1 2

67 71

402

BKLT:ENG

10.2

TF

0.1%

1/16W

R7719

1 2

BKLT:ENG

1/16W

TF

10.2

0.1%

402

R7718

1 2

67 71

0201

5%

0

1/20W

MF

NOSTUFF

R7755

1 2

402

1/16W

10.2

TF

0.1%

BKLT:ENG

R7717

1 2

402-2

1UF

10V X5R

10%

C7750

1

2

402-2

10% 10V

1UF

X5R

C7751

1

2

27.4K

1% 1/16W MF-LF 402

R7754

1

2

SM

XW7701

1 2

1UF

NOSTUFF

10V

10% X5R

402-2

C7753

1 2

NOSTUFF

X5R

10% 10V

1UF

402-2

C7752

12

5%

0

1/20W

MF

NOSTUFF

0201

R7752

1 2

5%

201

1/20W

MF

100K

NOSTUFF

R7753

1 2

0

1/16W MF-LF 402

5%

R7703

1

2

5%

0

0201

1/20W

MF

R7757

1 2

5%

0

0201

1/20W

MF

R7758

1 2

5%

201

1/20W MF

NOSTUFF

4.7K

R7761

1

2

5%

201

1/20W

MF

4.7K

NOSTUFF

R7760

1

2

MF-LF

402

5%

10K

1/16W

R7756

1

2

1/20W

5%

0

0201

MF

R7780

1 2

1/20W

5%

0

0201

MF

R7781

1 2

5%

0

0201

1/20W

MF

R7782

1 2

12 70

5%

0

1/16W

402

MF-LF

R7783

1 2

0

402

MF-LF

5% 1/16W

R7744

1

2

0

402

MF-LF

5%

1/16W

R7743

1

2

10% 50V X7R 0805

1.0UF

C7726

1

2

0805

X7R

50V

10%

1.0UF

C7727

1

2

SYNC_DATE=06/13/2013

LCD/KBD Backlight Driver

SYNC_MASTER=CLEAN_MLB_KEPLER

R7717,R7718,R7719,R7720,R7721,R7722,R7723,R7724

RES,MTL FILM,0 OHM,1A MAX,0402,SMD

116S0004

BKLT:PROD

8

BKLT_EN_R_JERRY

BKL_1_SCL

BKLT_ISET_LCD

BKLT_ISET_KEYB

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.35 mm

BKL_ISEN6

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

BKLT_SENSE_OUT

PP5V_S0

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PP5V_S0_KBDLED_R

PP5V_S0

GND_BKLT_SGND

BKLT_FLT

LED_RETURN_6

MIN_LINE_WIDTH=0.35 mm MIN_NECK_WIDTH=0.20 mm

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.35 mm

LED_RETURN_3

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.35 mm

MIN_LINE_WIDTH=0.35 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.35 mm

LED_RETURN_1

MIN_NECK_WIDTH=0.25 MM

KBDBKLT_RETURN2

MIN_LINE_WIDTH=0.5 MM

PPBUS_G3H

MIN_NECK_WIDTH=0.25 MM

PPBUS_S0_LCDBKLT_FUSED

VOLTAGE=12.6V

MIN_LINE_WIDTH=2 MM

VOLTAGE=12.6V

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.6V

PPBUS_SW_BKL

PPBUS_S0_LCDBKLT_PWR_SW

DIDT=TRUE

SWITCH_NODE=TRUE

VOLTAGE=45V

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM

BKLT_FLT_RC

EDP_IG_BKL_ON

BKLT_SCL_R

BKL_FET_CNTL_R

MIN_LINE_WIDTH=0.6 MM DIDT=TRUE

MIN_NECK_WIDTH=0.25 MM

GND_BKLT_SGND

BKLT_EN_R

BKLT_SDA_R

BKLT_SCL_R

SMBUS_PCH_DATA

EDP_IG_BKL_PWM

SMBUS_PCH_CLK

LCD_FSS

BKL_1_SDA

BKL_ISEN5

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN4

BKLT_KEYB2

BKL_SW

DIDT=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=2 mm

MIN_LINE_WIDTH=0.6 MM

BKL_FET_CNTL

MIN_NECK_WIDTH=0.25 MM DIDT=TRUE

MIN_NECK_WIDTH=0.25 mm

GND_LCDBKLT_SGND

MIN_LINE_WIDTH=0.5 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN3

BKLT_SYNC

BKL_ISEN1

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKLT_SDA_R

SMC_SYS_KBDLED

LCD_BKLT_PWM_R

ISNS_LCDBKLT_P

BKL_FB

GND_LCDBKLT_SGND

PP5V_S0

BKLT_KEYB1

BKLT_SDA

BKLT_SCL

BKLT_PWM_KEYB

VOLTAGE=0V

GND_BKLT_SGND

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

KBDBKLT_SW

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM DIDT=TRUE

ISNS_LCDBKLT_N

BKLT_SD

PPVOUT_BKLT_FB2

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=40V

KBDBKLT_RETURN1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

PPVOUT_S0_KBDBKLT

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=40V

GND_BKLT_SGND

PP5V_S0_BKLT_VDDD

MIN_LINE_WIDTH=0.4 MM VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

PP5V_S0_BKLT_VDDA

VOLTAGE=5V MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

LCDBKLT_EN_L

MIN_NECK_WIDTH=0.25 MM VOLTAGE=55V

MIN_LINE_WIDTH=0.5 MM

PPVOUT_S0_LCDBKLT

<SCH_NUM>

77 OF 118

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63

40 71

30 45 56 57 69 71

69

63

13 18 22 44

68 71

76

13 18 22 44

68 71

76

63

18 19 37 49 50 58 59 62 63 65 66 69 70 71

63

40 71

63

67 71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

Freq = 1.6MHZ

<Ra>

Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups. Alternative is strong voltage

Vout = 1.05V Max Current = 0.35A

1.05V SUS LDO

Lynx Point-H requires JTAG pull-ups to be powered at 1.05V in SUS.

dividers (200/100) to 3.3V SUS, which burns 100mW in all S-states.

Max Current = 1.5A

1.5V S0 Regulator

Vout = 1.508V

65 66

CRITICAL

ISL8009B

DFN

U7810

2

7

8

3

54

9

6

1

22UF

805

20%

6.3V CERM

CRITICAL

C7850

1

2

PCMB042T-IHLP1616BZ

2.2UH-3A

CRITICAL

L7870

1 2

MF-LF 402

1% 1/16W

113K

R7881

1

2

27PF

CERM

5%

50V

0402-1

C7876

1

2

MF-LF 402

1%

100K

1/16W

R7880

1

2

47UF

0805

X5R

CRITICAL

20%

6.3V

C7871

1

2

66

XDP_PCH

2.2UF

X5R 402

10%

6.3V

C7841

1

2

XDP_PCH

CRITICAL

TPS720105

SON

U7840

4

3

5

6

2

1

7

XDP_PCH

1UF

CERM

402

10%

6.3V

C7840

1

2

SYNC_DATE=10/31/2012

Misc Power Supplies

SYNC_MASTER=J15_MLB

PP1V5_S0

P1V5S0_PGOOD

P3V3S0_P1V5_S0_EN

PP3V3_S5

PP1V05_SUS

PP3V3_SUS

P1V5S0_FB

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

P1V5S0_SW

<SCH_NUM>

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18 69

11 12 13 14 15 17 50 65 66 69

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http://sualaptop365.edu.vn

IN

D

S

G

IN

D

S

G

D

S

G

IN

S

G

D

OUT

D

S

G

IN

GND

VDD

D

SON

CAP

SDG

S

G

D

GND

VOUT

ON

VIN

IN

SDG

SYM_VER_2

G S

D

SYM_VER_2

G S

D

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

1.3 A (EDP)

2.8 A (EDP)

0.3 A (EDP)

1.1 A (EDP)

26 mOhm @1.8V

P-TYPE 8V/5V

SiA427

LOADING

EDP is per J45 Power Budget rev5

3.3V S4 FET

Max Current = 2A

P-TYPE 8V/5V

LOADING

CHANNEL

26 mOhm @1.8V

0.8V/ms = 19.75nF

CHANNEL

LOADING

MOSFET

5 A (EDP)

SI7615DN

5.0V S0 FET

3.3V S0 SSD FET

LOADING

SiA427

3.3V S3 FET

CHANNEL

5.5 mOhm @4.5V

5.5 MOHM @4.5V

P-TYPE 20V/12V

P-TYPE 8V/5V

SiA427

Slew rate :

RDS(ON)

SLG5AP1438V

MOSFET

Type R(on)

@ 2.5V

Part

TPS22924C

U8030

25.8 mOhm Max

18.5 mOhm Typ

Load Switch

3.3V S0 Switch

APN 353S2741

3.3V S3 FET

1.35V S3/S0 FET

LOADING

RDS(ON)

CHANNEL

SI7615DN

RDS(ON)

26 mOhm @1.8V

P-TYPE 8V/5V

CHANNEL

SiA427MOSFET

4.8 A (EDP)

9.6 mOhm

N-TYPE

LOADING

26 mOhm @1.8V

RDS(ON)

CHANNEL

MOSFET

RDS(ON)

3.3V SUS FET

1.35V S3/S0 FET

5V S3 FET

3.3V SUS FET

5V S3 FET

3.3V S4 FET

CHANNEL

5.0V S0 FET

RDS(ON)

MOSFET

P-TYPE 20V/12V

3.3V S0 SSD FET

MOSFET

LOADING

RDS(ON)

376S0945

0.5 A (EDP)

Integ. MOSFET

21

0402

X7R-CERM

16V

10%

0.01UF

C8010

1 2

10%

16V

402

X5R

0.033UF

C8011

1

2

5% 1/16W MF-LF

402

39K

R8010

1 2

402

MF-LF

1/16W

47K

5%

R8012

1

2

66

CRITICAL

SC70-6L

SIA413DJ

Q8010

1

3

4 7

0.1UF

402

CERM

10V

20%

C8001

1

2

31 32 66

220K

MF-LF

1/16W

402

5%

R8002

1

2

402

1/16W

47K

5%

MF-LF

R8000

1

2

402

X5R

16V

10%

0.033UF

C8009

1

2

SC70-6L

CRITICAL

SIA413DJ

Q8000

1

3

4 7

0402

X7R-CERM

16V

10%

0.01UF

C8000

1 2

0.033UF

X5R

16V

402

10%

C8021

1

2

SC70-6L

CRITICAL

SIA413DJ

Q8020

1

3

4 7

X7R-CERM

16V

0.01UF

10%

0402

C8020

1 2

1/16W

100K

MF-LF

402

5%

R8022

1

2

12K

402

MF-LF

1/16W

5%

R8020

1 2

12 45 66

66

402

MF-LF

1/16W

270K

5%

R8062

1

2

402

MF-LF

1/16W

6.2K

5%

R8060

1 2

CERM-X5R

10.0V

10%

402

0.12UF

C8061

1

2

X5R

10% 10V

0402

0.47UF

C8060

1 2

SI7615DN

PWRPK-1212-8

CRITICAL

Q8060

5

4

1 2 3

0.018UF

10%

402

X7R

16V

C8002

1

2

SC70-6L

SIA427DJ

CRITICAL

Q8050

1

3

4 7

402

X5R

16V

10%

0.033UF

C8051

1

2

402

1/16W

5.1K

MF-LF

5%

R8050

1 2

402

MF-LF

1/16W

200K

5%

R8052

1

2

0402

X7R-CERM

16V

10%

0.01UF

C8050

1 2

66

SENSOR_NONPROD_R

SM

XW8005

SLG5AP1438V

TDFN

CRITICAL

U8001

7 3

8

2 5

1

DMN5L06VK-7

SOT-563

Q8002

6

2

1

DMN5L06VK-7

SOT-563

Q8052

6

2

1

10% 16V

0402

0.01UF

X7R-CERM

C8070

1 2

PWRPK-1212-8

SI7615DN

PLACE_NEAR=R5549.2:6mm

CRITICAL

Q8070

5

4

1 2 3

0.033UF

16V

402

X5R

10%

C8071

1

2

1/16W

402

33K

MF-LF

5%

R8070

1 2

402

MF-LF

1/16W

47K

5%

R8072

1

2

TPS22924

CRITICAL

CSP

U8030

C1

C2

A2 B2

A1 B1

6.3V

1UF

X5R 402

10%

C8030

1

2

64 66

DMN5L06VK-7

SOT-563

Q8002

3

5

4

SOT-563

DMN5L06VK-7

Q8052

3

5

4

DMN32D2LFB4

DFN1006H4-3

Q8012

3

1

2

DMN32D2LFB4

DFN1006H4-3

Q8072

3

1

2

SSD_PWR_EN:GPIO

MF

1/20W

0201

0

5%

R8073

1 2

SSD_PWR_EN:S0

MF

1/20W

0201

0

5%

R8074

1 2

SYNC_DATE=10/31/2012

Power FETs

SYNC_MASTER=J15_MLB

PP1V35_S3RS0_FET

PP1V35_S3RS0_CPUDDR

PP3V3_S3

PP3V3_S5

PP5V_S0

P3V3_SSD_SS

P3V3_SSD_EN_L

NC_ISNS_CPUDDRN

PP3V3_S5

P3V3S3_SS

P3V3S3_S4

P5V0S0_SS

PP5V_S3

PP3V3_S4

S4_PWR_EN

P1V35CPU_SLEW_CTL

PP3V3_SUS

PP3V3_S0PP3V3_S5

P3V3S0_P1V5_S0_EN

PM_SLP_SUS_L

P3V3SUS_SS

P5VS0_EN

P3V3S4_EN_L

PP5V_S4

P5V0S0_EN_L

P3V3S3_EN

P5VS3_EN

P3V3SUS_EN_L

PP3V3_S5

PM_SLP_S3_BUF_L

PP3V3_S0SW_SSD_R

P5VS3_EN_L

SSD_PWR_EN

SSD_PWR_FET_EN

PP1V35_S3

NC_ISNS_CPUDDRP

P5VS3_SS

P3V3S3_EN_L

PP5V_S5

CPUVDDQ_EN

PP5V_S4

<SCH_NUM>

80 OF 118

65 OF 81

68 69

6 8

10 21 66 69 81

13 20 21 22 44 46 47 68 69 71

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

12 14 15 17 18 19 21 31 32 34 61 64

65 66 69 70 71 81

18 19 37 49 50 58 59 62 63 66 69 70 71

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

21 37 60 66 69 71

20 34 39 42 43 46 47 66 68 69 70 71

11 12 13 14 15 17 50 64 66 69

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 69 71 81 12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71

81

38 51 61 65 66 67 68 69 71

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

51 66 68 71

46 69

13 18

35

21 22 46 60

69

71

39 61 69 71

38 51 61 65 66 67 68 69 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

OUT

IN

OUT

IN

OUT

IN

NC

Q3

Q2

Q4

Q1

OUT

IN

SENSE

CT

VDD

GND

RESET*

MR*

IN

OUT

IN

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

OUT

IN

OUT

IN

NC

OUT

IN

OUT

SYM_VER_2

G S

D

SYM_VER_2

G S

D

SDG SDG

OUT

G

D

S

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

P1V5S0_PGOOD from U7810

1V05_VMON divider

0.716V @1.02V

S0 Rail PGOOD Circuitry

(ISL Version in development)

Vbe 0.7V max @2mA

P5V_VMON divider

353S2310

(IPU)

0.717V @1.31V

keep R8171 DDRCPU 1.35V only

3.16V @4.5V

Q1 Vth 0.7~1V @Id 250uA

V4MON: 0.572V-0.630V

V3MON: 0.572V-0.630V

Thresholds: VDD: 2.734V-3.010V

V2MON: 2.815V-3.099V

(For development only)

Deep Sleep (dS4AC)

0

S0 ENABLE

3V3 Divider:1.07V

CHGR VFRQ Generation

Vce(sat) 0.1V max @1mA

1V5 S0 "PGOOD" Delay

S5 Rail Enables & PGOOD

Power State Debug LEDs

VFRQ Low: Fix Frequency

VFRQ High: Variable Frequency

VBEon: 0.58~0.7V

1V5 Divider:0.75~0.85V

Vgs:0.7V~1.0V

Unused PGOOD signals

S3 ENABLE

SMC-->PM_DSW_PWRGD

S5_PWRGD-->SMC

PM_RSMRST_L goes to U1100.C21

Battery Off (G3HotAC)

SMC_ADAPTER_EN

State

0

1

Mobile System Power State Table

0 00

0

1

0

353S2809

(PM_SLP_S3_BUF_L)

5.0V Divider:1.07V

Min delay time

1V35_VMON divider

Deep Sleep (dS5AC)

0

PM_SLP_S3_L

0

1

0

PM_SLP_S4_LPM_SLP_S5_L

1

11

1

PM_SLP_SUS_L

1

SMC_S4_WAKESRC_EN

1 0 0

0

00

0

0 0

0

1

1 1 10

X

SMC_PM_G2_ENABLE

Sleep (S3)

Sleep (S3AC)

Run (S0)

1 1

0 1

10

0

1

toggle 3Hz

Deep Sleep (dS4)

Deep Sleep (dS5)

Battery Off (G3Hot)

PM_SLP_S4_L:100K pull down in PCH page

threhold is 3.07V

0

U8130 Sense input

No stuff C8131, 12ms

S0 Rail PGOOD (BJT Version)

PM_SLP_S3_L:100K pull down in PCH page

PM_SLP_S5_L:100K pull down on PCH page

S4 Power Enable

CPUVCORE ENABLE

PM_SLP_SUS_L: 100K pull down on PCH page

3.3V SUS Detect

3.3V SUS Enable

NOTE: S4 term is guaranteed by S4 pull-up on open-drain AP_PWR_EN signal.

"WLAN" = ("S4" && "AP_PWR_EN" && ("AC" || "S0"))

WLAN Enable Generation

60 66

65 66

0

MF-LF

PLACE_NEAR=Q8012.1:6mm

5%

402

1/16W

R8112

1

2

NO STUFF

10% CERM-X5R

402

6.3V

PLACE_NEAR=Q8012.1:6mm

0.47UF

C8112

1

2

18 19 41 58 66 71

31 32 45 66

62 66

5%

402

1/16W MF-LF

5.1K

PLACE_NEAR=U7400.16:6mm

R8111

1

2

0.47UF

CERM-X5R 402

10%

6.3V

PLACE_NEAR=U7400.16:6mm

C8110

1

2

12 21 34 38 41 66 68 71

PLACE_NEAR=U7600.3:6mm

5% 1/16W MF-LF 402

130K

R8185

1

2

402

6.3V

10%

0.82UF

X5R

PLACE_NEAR=U7600.3:6mm

C8185

1

2

1/16W MF-LF 402

5%

100K

R8131

1

2

57

12 21 41 71

31 32 65 66

10K

5% 1/16W MF-LF

402

R8167

1

2

18 19 41 58 66 71

100

5%

1/16W

402

MF-LF

R8157

1

2

100

402

5%

MF-LF

1/16W

R8169

1 2

5% MF-LF

402

1/16W

470K

R8165

1

2

61

330

402

5%

S0PGOOD_ISL

MF-LF

1/16W

R8162

1 2

62

150K

1/16W MF-LF

402

1%

R8156

1

2

5%

MF-LF

1/16W

1K

402

R8153

1 2

1% 1/16W MF-LF

402

54.9K

R8151

1

2

15.0K

402

1%

MF-LF

1/16W

R8152

1

2

DFN2015H4-8

ASMCC0179

CRITICAL

Q8150

5

7

1

6

4

8

2

3

1K

MF-LF

1/16W

5%

402

R8154

1 2

5%

1K

402

MF-LF

1/16W

R8155

1 2

31 32 65 66

12 41

TPS3808G33DBVRG4

CRITICAL

SOT23-6

U8130

4

2

3

15

6

0.001UF

20%

402

50V CERM

NO STUFF

C8131

1

2

5%

402

1/16W MF-LF

100K

R8133

1

2

0.1uF

20%

CERM

402

10V

BYPASS=U8130.6::2:2.3mm

C8130

1

2

MF-LF

5%

100

402

1/16W

R8168

1 2

64

MF-LF

5%

402

100

1/16W

R8178

1 2

64 65 66

12 71 76

41 42 61 66

0.0033UF

10% 50V X7R-CERM

PLACE_NEAR=U7501.21:7mm

NO STUFF

0402

C8142

1

2

402

MF-LF

1/16W

5%

PLACE_NEAR=U7501.21:7mm

100

R8140

1 2

61 66

41 61

66

MF-LF

5%

402

100K

1/16W

PLACE_NEAR=U7501.20:7mm

R8141

1

2

S0PGOOD_ISL

TDFN

ISL88042IRTEZ

CRITICAL

U8160

4

1

8

9

3 5 6

2

7

1/16W

402

6.04K

S0PGOOD_ISL

MF-LF

1%

R8172

1

2

1/16W

S0PGOOD_ISL

MF-LF

1%

402

15.0K

R8173

1

2

S0PGOOD_ISL

10K

1%

MF-LF

402

1/16W

R8170

1

2

S0PGOOD_ISL

12.4K

1%

1/16W

402

MF-LF

R8171

1

2

1%

S0PGOOD_ISL

1/16W MF-LF

402

6.04K

R8160

1

2

1/16W

MF-LF

1%

402

15.0K

S0PGOOD_ISL

R8161

1

2

12 45 65 66 12 45 65 66

31 32 65 66

402

CERM-X5R

10%

6.3V

0.47UF

PLACE_NEAR=Q8052.2:6MM

NO STUFF

C8113

1

2

402

MF-LF

5%

PLACE_NEAR=Q8052.2:6MM

1/16W

0

R8113

1

2

65 66

31 32 45 66

41 42

SOT891

74LVC1G32

U8170

2

1

35

6

4

BYPASS=U8170.6:3:2.3mm

0.1uF

20% 10V

CERM

402

C8170

1

2

NO STUFF

0.47UF

10%

6.3V CERM-X5R 402

PLACE_NEAR=J4801.17:10MM

C8114

1

2

1/20W MF

3.3K

201

PLACE_NEAR=J4801.17:10MM

5%

R8114

1

2

39

PLACE_NEAR=U8160.2:4mm

0402

10V

20%

X7R-CERM

S0PGOOD_ISL

0.1UF

C8160

1

2

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S5_ON

GREEN-56MCD-2MA-2.65V LTQH9G-SM

D8190

A

K

SILK_PART=S4_ON

DBGLED

PLACE_SIDE=BOTTOM

GREEN-56MCD-2MA-2.65V LTQH9G-SM

D8191

A

K

SILK_PART=S0_ON

PLACE_SIDE=BOTTOM

DBGLED

GREEN-56MCD-2MA-2.65V LTQH9G-SM

D8193

A

K

DBGLED

PLACE_SIDE=BOTTOM SILK_PART=S3_ON

GREEN-56MCD-2MA-2.65V LTQH9G-SM

D8192

A

K

20K

5%

201

1/20W MF

DBGLED

R8190

1

2

20K

1/20W MF 201

5%

DBGLED

R8191

1

2

20K

5% 1/20W

201

DBGLED

MF

R8192

1

2

20K

DBGLED

1/20W 201

MF

5%

R8193

1

2

MF-LF

DBGLED

0

5%

402

1/16W

PLACE_SIDE=BOTTOM

R8194

12

470K

201

5% 1/20W MF

R8120

1

2

60

1%

15.0K

402

1/16W MF-LF

R8158

1

2

7.15K

402

1%

1/16W MF-LF

R8159

1

2

5%

20K

1/16W MF-LF 402

R8186

1

2

64 65 66

CERM

10%

6.3V 402

0.68UF

C8186

1

2

CERM

10%

6.3V 402

PLACE_NEAR=Q8052.5:6mm

0.68UF

NO STUFF

C8187

1

2

0

402

5% MF-LF

1/16W

PLACE_NEAR=Q8052.5:6mm

R8187

1

2

65 66

X5R 402

6.3V

10%

2.2UF

PLACE_NEAR=U7501.4:6mm

C8174

1

2

402

1/16W MF-LF

43K

5%

PLACE_NEAR=U7501.4:6mm

R8174

1

2

61 66

DFN1006H4-3

DMN32D2LFB4

Q8131

3

1

2

DMN32D2LFB4

DFN1006H4-3

DBGLED

Q8191

3

1

2

DMN5L06VK-7

SOT-563

DBGLED

Q8190

6

2

1

SOT-563

DBGLED

DMN5L06VK-7

Q8190

3

5

4

MF-LF

5%

1/16W

240

402

R8175

1 2

820

402

MF-LF

1/16W

5%

PLACE_NEAR=R8185.2:6mm

R8138

1 2

SC70-HF

MC74VHC1G08

U8180

3

2

1

4

5

12 45 65 66

41 42

61

66

100K

NO STUFF

402

MF-LF

1/16W

5%

R8180

1

2

SOD-523

BAT54XV2T1

PLACE_NEAR=R8138.1:6mm

D8185

A

K

PLACE_NEAR=R8174.1:6mm

SOD-523

BAT54XV2T1

D8174

A

K

20% 10V

CERM

402

0.1uF

BYPASS=U8180.5:3:2.3mm

C8180

1

2

18 19 41 58 66 71

DMB53D0UV

SOT-563

CRITICAL

Q8151

6

2

1

MF-LF

1/16W

402

23.7K

1%

R8136

1

2

SOT-563

DMB53D0UV

CRITICAL

Q8151

5

3

4

X5R 402

6.3V

2.2UF

10%

C8134

1

2

1/16W

402

1%

MF-LF

54.9K

R8135

1

2

MF-LF

1%

1/16W

61.9K

402

R8134

1

2

1/16W

5%

402

MF-LF

100

R8137

1 2

402

MF-LF

1/16W

2.0K

1%

R8139

1

2

34 41 66

MF

1/20W 201

330K

5%

R8125

1

2

34 41 66

51 65 66 68 71

PLACE_NEAR=U8160.2:4mm

10V

0402

S0PGOOD_ISL

0.1UF

20%

X7R-CERM

C8161

1

2

PLACE_NEAR=U8160.2:4mm

402

1/16W

5%

10

MF-LF

S0PGOOD_ISL

R8195

1 2

1/16W

5%

402

MF-LF

10

S0PGOOD_ISL

PLACE_NEAR=U8160.7:4mm

R8196

1 2

PLACE_NEAR=U8160.2:7mm

0.1UF

10V

0402

NOSTUFF

20%

X7R-CERM

C8162

1

2

PLACE_NEAR=U8160.2:7mm

20%

X7R-CERM

0402

10V

NOSTUFF

0.1UF

C8163

1

2

PLACE_NEAR=U8160.1 :4mm

5%

100K

402

NOSTUFF

1/16W MF-LF

R8197

1

2

SYNC_MASTER=CHANG_J45

SYNC_DATE=03/15/2013

Power Control 1/ENABLE

PM_SLP_S3_BUF_L

P5VS0_EN

PM_SLP_SUS_L

PP3V3_S5

PM_SLP_S3_L

P5VS4_EN_D

PP3V3_S5

P5VS4_EN

MAKE_BASE=TRUE

P3V3S0_P1V5_S0_EN

MAKE_BASE=TRUE

P1V05S0_EN

PM_SLP_S3_R_L

PP3V3_S5

P3V3S0_P1V5_S0_EN

P1V05S0_EN

SMC_S4_WAKESRC_EN

PM_SLP_SUS_L

P3V3S0_P1V5_S0_EN

P5VS3_EN

DDRREG_EN

PP3V3_S5

VMON_5V_DIV

PP5V_S0

PP3V3_SUS

DBGLED_S0

PM_SLP_S4_L

S4_PWR_EN

PP3V3_SUS

P1V05_EN_D

S4_PWR_EN S4_PWR_EN

VMON_Q4_BASE

PM_SLP_S5_L

P3V3S3_EN

DBGLED_S3

PM_RSMRST_L

S4_PWR_EN

DBGLED_S4_D

ALL_SYS_PWRGD

PP3V42_G3H

S5_PWRGD

PP3V3_S0

PP1V35_S3RS0_CPUDDR

VMON_3V3_DIV

CHGR_VFRQ

PP5V_S4

PP5V_S3

DDRREG_PGOOD

P5VS4_PGOOD

TP_SUS_PGOOD_MR_L

SMC_PM_G2_EN

P3V3S5_EN

SUS_PGOOD_CT

VMON_Q3_BASE

PM_SLP_S3_BUF_L

TPAD_VBUS_EN

DBGLED_S3_D

PM_SLP_S3_R_L

ALL_SYS_PWRGD

PP3V42_G3H

PP1V5_S0

DELAY_1V5S0_PGD

PM_P1V5_PGD_DIV

PM_1V5_PGD_L_R

PP3V3_S5

PM_1V5_PGD_L

DBGLED_S0_D

PM_SLP_S3_R_L

MAKE_BASE=TRUE

PM_SLP_S3_R_L

MAKE_BASE=TRUE

P3V3S5_EN

SMC_PM_G2_EN

MAKE_BASE=TRUE

PM_SLP_SUS_L

MAKE_BASE=TRUE

S5_PWRGD

MAKE_BASE=TRUE

ALL_SYS_PWRGD

MAKE_BASE=TRUE

P5VS0_EN

MAKE_BASE=TRUE

VMON_Q2_BASE

S0PGD_C

ALL_SYS_PWRGD

PP3V3_S5

PM_WLAN_EN

MAKE_BASE=TRUE

PP3V3_S4

PM_WLAN_EN

PM_SLP_S4_L

MAKE_BASE=TRUE

DDRREG_EN

P5VS3_EN

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

P5VS4_EN

MAKE_BASE=TRUE

S4_PWR_EN

P1V5S0_PGOOD

PP3V3_S5_DBGLED

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 MM

P1V05_VID_VMON

ALL_SYS_PWRGD

PM_SLP_S3_BUF_L

PP3V3_S0 PP3V3_S0

PP1V05_S0

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_VMON_P7

MIN_LINE_WIDTH=0.5 MM

ALL_SYS_PWRGD_R

PP1V35_S3RS0_CPUDDR

VMON_MR

P5V_DIV_VMON

S0PGD_BJT_GND_R

PP3V3_S0_VMON_P7

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

PP3V3_S0_VMON_P2

MIN_NECK_WIDTH=0.2 MM

P1V05S0_PGOOD

VMON_MR

P1V5_DIV_VMON

PP5V_S0

DBGLED_S4DBGLED_S5

<SCH_NUM>

81 OF 118

66 OF 81

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

12 14 15 17 18 19 21 31 32 34 61 64 65

66 69 70 71 81

64 65 66

62 66

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

18 19 37 49 50 58 59 62 63 65 66 69 70 71

11 12 13 14 15 17 50 64 65 66 69

12 21 34 38 41 66 68 71

31 32 65 66

11 12 13 14 15 17 50 64 65 66 69

19 35 38 39 41 42 43 44 50 56 57 66 69 71

41 61 66

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

6 8

10 21 65

66 69

81

38 51 61 65 67 68 69 71

21 37 60 65 69 71

51 65 66 68 71

31 32 45 66

19 35 38 39 41 42 43 44 50 56 57 66 69 71

11 12 13 15 17 19 52 64

68 69 71

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

61 66

18 19 41 58 66 71

65 66

18 19 41 58 66 71

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

20 34 39 42 43 46 47 65 68 69 70 71

60 66

65 66

61 66

51 65 66 68 71

11 12

13

14

15

17

19

20

29

33

35

44

45

46

47

48

49

51

52

55

65

66

67

69

71

81

11 12 13 14 15 17 19 20 29 33 35 44 45 46

47 48 49

51 52 55 65

66 67 69 71

81

14 15 17 18 42 62 69 71

66

6 8

10 21 65 66 69

81

66

18 19 37 49

50 58

59 62

63

65

66

69

70

71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

IN

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

IN

BI

NC

OUT

SYM_VER-2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LCD PANEL INTERFACE (eDP)

518S0829

LCD Panel HPD & AUX strapping

10%

0.1UF

0402

X7R-CERM

16V

C8301

1

2

FERR-220-OHM

0805

CRITICAL

L8300

1 2

12 70 71

10% 50V

X7R-CERM

0402

0.001UF

C8302

1

2

10%

0.1UF

0402

X7R-CERM

16V

C8309

1

2

FPF1009

CRITICAL

MFET-2X2-8IN

U8300

617

2

3

4

5

10%

0.1UF

0402

X7R-CERM

16V

C8311

1

2

X5R

6.3V

10UF

20%

603

C8312

1

2

10%

0.1UF

16V 0201

X5R-CERM

C8321

1 2

10% 16V

0201

X5R-CERM

0.1UF

C8320

1 2

5

70 74

5

70 74

10% 16V

0201

X5R-CERM

0.1UF

C8323

1 2

10%

0.1UF

16V 0201

X5R-CERM

C8322

1 2

5

70 74

5

70 74

0201

10%

0.1UF

16V

X5R-CERM

C8325

1 2

10%

0.1UF

16V 0201

X5R-CERM

C8324

1 2

5

70 74

5

70 74

10%

0.1UF

16V

X5R-CERM

0201

C8327

1 2

10%

0.1UF

16V

X5R-CERM

0201

C8326

1 2

5

70 74

5

70 74

10%

0.1UF

16V 0201

X5R-CERM

C8329

1 2

10%

0.1UF

16V 0201

X5R-CERM

C8328

1 2

5

70 74

5

70 74

20525-130E-01

F-RT-SM

CRITICAL

J8300

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30

31

32

33 34 35 36 37 38 39

4

40 41

5 6 7 8 9

0603

X7R

1000PF

100V

10%

C8300

1

2

63 71

MF

1/20W

0201

0

5%

R8300

1 2

20

1M

MF

1/20W 201

5%

R8302

1

2

1M

MF

1/20W 201

5%

R8303

1

2

1M

MF

1/20W 201

5%

R8301

1

2

1M

MF

1/20W

201

5%

R8313

1 2

1M

MF

1/20W

201

5%

R8314

1 2

1M

MF

1/20W

201

5%

R8315

1 2

1M

MF

1/20W

201

5%

R8316

1 2

1M

MF

1/20W

201

5%

R8312

1 2

1M

MF

1/20W

201

5%

R8317

1 2

1M

MF

1/20W

201

5%

R8318

1 2

1M

MF

1/20W

201

5%

R8311

1 2

DLP0NS

15OHM-100MA-8.5GHZ

CRITICAL

FL8300

1 2

34

CRITICAL

DLP0NS

15OHM-100MA-8.5GHZ

FL8302

1 2

34

15OHM-100MA-8.5GHZ

DLP0NS

CRITICAL

FL8301

1 2

34

CRITICAL

DLP0NS

15OHM-100MA-8.5GHZ

FL8303

1 2

34

CRITICAL

SM

SENSOR_NONPROD_R

XW8320

9.1PF

0201

C0G-CERM 50V

+/-0.1PF

C8350

1

2

9.1PF

0201

C0G-CERM 50V

+/-0.1PF

C8351

1

2

9.1PF

0201

C0G-CERM 50V

+/-0.1PF

C8352

1

2

9.1PF

0201

C0G-CERM 50V

+/-0.1PF

C8353

1

2

9.1PF

0201

C0G-CERM 50V

+/-0.1PF

C8354

1

2

+/-0.1PF

50V

C0G-CERM 0201

9.1PF

C8355

1

2

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

eDP Display Connector

VOLTAGE=5V

PP5VR3V3_SW_LCD_ISNS

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP5VR3V3_SW_LCD_UF

NC_ISNS_LCD_PANELN

DP_INT_ML_N<0>

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<2>

DP_INT_ML_C_P<2>

DP_INT_ML_C_N<1>

DP_INT_ML_C_P<1>

DP_INT_ML_C_N<0>

DP_INT_AUXCH_C_N

DP_INT_AUXCH_C_P

LCD_HPD

LCD_FSS

DP_INT_ML_F_N<3>

DP_INT_ML_F_P<3>

DP_INT_ML_F_N<2>

DP_INT_ML_F_P<2>

DP_INT_ML_F_N<1>

DP_INT_ML_F_P<1>

NC_ISNS_LCD_PANELP

DP_INT_ML_P<3>

DP_INT_ML_P<2>

DP_INT_ML_N<3>

DP_INT_ML_N<2>

DP_INT_ML_P<1>

DP_INT_ML_N<0>

DP_INT_ML_P<0>

DP_INT_ML_N<1>

DP_INT_AUX_P

LCD_HPD_CONN

DP_INT_ML_F_N<0>

DP_INT_ML_F_P<0>

PP5V_S4

PP5VR3V3_SW_LCD

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVOUT_S0_LCDBKLT

LCD_HPD_CONN DP_INT_AUX_P

PP3V3_S0

DP_INT_AUX_N

DP_INT_ML_N<2>

DP_INT_ML_P<2>

DP_INT_ML_N<1>

DP_INT_ML_N<3>

DP_INT_ML_P<3>

DP_INT_AUX_N

DP_INT_ML_P<0>

DP_INT_ML_P<1>

LED_RETURN_1

EDP_IG_PANEL_PWR

DP_INT_ML_C_N<3>

DP_INT_ML_C_P<0>

LED_RETURN_2

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

<SCH_NUM>

83 OF 118

67 OF 81

67 71 74

74

67 71 74

67 71

74

38 51 61 65 66 68 69 71

71

63 71

67 71 67 71 74

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 65 66 69 71 81

67 71 74

63 71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

IN IN

BI BI

IN

OUT OUT

IN

IN IN

OUT OUT

IN IN

IN

TP

GND

IN IN IN

BI

OUT

IN

BI

IN

OUT OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Note. Pin1 in symbol is different to 516S0853 in J15.

516S1106

Board-to-Board (Flex) Connector

518S0829

Wire-to-Board (Micro-coax) Connector

70 71 74

13 71 75

13 75

13 71 75

20525-130E-01

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

F-RT-SM

GND_VOID=TRUE

J9500

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30

31

32

33 34 35 36 37 38 39

4

40 41

5 6 7 8 9

70 71 74

13 20 71 76

5

70 71 74

5

70 71 74

NO_XNET_CONNECTION=TRUE

BEAD-PROBE

SM

BP9501

1

BEAD-PROBE

SM

NO_XNET_CONNECTION=TRUE

BP9502

1

NO_XNET_CONNECTION=TRUE

SM

BEAD-PROBE

BP9505

1

SM

NO_XNET_CONNECTION=TRUE

BEAD-PROBE

BP9506

1

BEAD-PROBE

SM

NO_XNET_CONNECTION=TRUE

BP9503

1

SM

NO_XNET_CONNECTION=TRUE

BEAD-PROBE

BP9504

1

GND_VOID=TRUE

10%

0.1UF

X5R-CERM

16V

0201

C9501

1 2

GND_VOID=TRUE

0.1UF

0201

16V

X5R-CERM

10%

C9502

1 2

20590-032E-25

F-ST-SM

J9510

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132

3334

3536

4

56 78 9

51 65 66 71

12 21 34 38 41 66 71

12 70 71

12 70 71 20 71

13 18 71

13 18 22 44 63 71 76

12 20 70

18 71

0

5%

1/16W

402

MF-LF

RIO_PWR:1V5

R9535

12

5%

0

402

RIO_PWR:1V35

1/16W MF-LF

R9534

12

20% 402

CERM

10V

0.1uF

C9510

1

2

0.1uF

20% 402

CERM

10V

C9511

1

2

RIO Connectors

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

USB3_SD_D2R_P USB3_SD_D2R_N

HDMI_DATA_N<2>

HDMI_DATA_P<2>

HDMI_DATA_N<1>

HDMI_DATA_P<0> HDMI_DATA_N<0>

USB3_EXTB_D2R_P

USB_EXTB_P USB_EXTB_N

USB3_EXTB_R2D_N

USB3_EXTB_R2D_P

USB3_SD_R2D_C_N

USB3_EXTB_R2D_C_P

USB3_EXTB_R2D_C_N

SMBUS_PCH_CLK

PM_SLP_S4_L

PP1V35_S3RS0_FET

PP1V5_S0

USB3_SD_R2D_C_P

HDMI_DATA_P<1>

HDMI_CLK_N

HDMI_CLK_P

USB3_EXTB_D2R_N

PP5V_S4

PP1V5R1V35_S0_RIO

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V

HDMI_DDC_CLK

PM_SLP_S3_BUF_L

SD_PWR_EN RIO_SDCONN_STATE_CHANGE_L

USB_EXTB_OC_L

HDMI_HPD

HDMI_DDC_DATA

PP3V3_S3

SMBUS_PCH_DATA

PP3V3_S4

<SCH_NUM>

95 OF 118

68 OF 81

71 75

65 69

11 12 13 15 17 19 52 64 66 69 71

38 51 61 65 66 67 69 71

71

13 20 21 22 44 46 47 65 69 71

20 34 39 42 43 46 47 65 66 69 70 71

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TBT RAILS

1.5V/1.35V/1.05V/VCORE/BKLT Rails

G3H/5V Rails 3.3V Rails

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

Power Aliases

PPVIN_S4_TPAD

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H_ISOL

VOLTAGE=20V

MIN_NECK_WIDTH=0.25 MM

MAKE_BASE=TRUE

PPDCIN_G3H_ISOL PPDCIN_G3H_ISOL

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.42V

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

PP3V42_G3H

PP5V_S0

PP3V3_S0

PPVCC_S0_CPU

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

PPVCC_S0_CPU

PP3V3_S0

PP5V_S5

PPVRTC_G3H

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=3.42V

PPVRTC_G3H

PP3V3_S0

PP3V3_S3

PP3V3_S5

VOLTAGE=3.3V MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5

PP3V3_S4

VOLTAGE=3.3V MAKE_BASE=TRUEMIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.5 MM

PP3V3_S5

PP3V3_S4

PP3V3_S4 PP3V3_S4

PP3V3_S4

PP3V3_S5

PPBUS_G3H

PP1V5_S0

PP3V3_S4

PP1V5_S0

PP3V3_SUS

PP3V3_SUS PP3V3_SUS PP3V3_SUS

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

PP3V3_S4

PP3V3_SUS

PP3V3_SUS PP3V3_SUS

PPBUS_G3H PPBUS_G3H

PPBUS_G3H

PP3V3_S3

PP3V3_S3 PP3V3_S3

PP3V3_S3

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V

PP3V3_S3

MIN_NECK_WIDTH=0.2 MM

PP3V3_SUS

PP3V3_S3

PP1V35_S3RS0_CPUDDR

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.35V MAKE_BASE=TRUE

PP1V35_S3RS0_CPUDDR

PP3V3_S5 PP3V3_S5

PPBUS_G3H

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=5V MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP5V_S0

PP3V3_S5

PPVIN_S5_HS_COMPUTING_ISNS

PPVTTDDR_S3

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_TBTLC

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S0

MIN_NECK_WIDTH=0.075 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

PP5V_S4

PP5V_S5

VOLTAGE=5V

PP5V_S5

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.1 MM

MAKE_BASE=TRUE

PP5V_S4 PP5V_S4

PPDCIN_G3H_ISOL

PP1V35_S3

MIN_NECK_WIDTH=0.17 MM

VOLTAGE=1.35V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.2 MM

PP1V35_S3

VOLTAGE=1.35V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.17 MM

PP1V35_S3_MEM

PP1V35_S3RS0_FET

VOLTAGE=1.5V

PP1V5_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.35V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

PP1V35_S3RS0_FET

PP15V_TBT

PPBUS_SW_BKL

PP3V3_S4_TBT

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0SW_SSD_R

MAKE_BASE=TRUE

VOLTAGE=3.3V

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM

PP3V3_S0SW_SSD

MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE

PPVIN_S5_HS_OTHER3V3_ISNS

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.6 MM

PPVIN_S5_HS_OTHER5V_ISNS

PP3V3_S5 PP3V3_S5 PP3V3_S5

PP3V3_SUS

PP1V5_S0

PP3V3_S5

PP3V3_S5 PP3V3_S5

PP1V35_S3_MEM

PP1V5_S0

PPVTT_S0_DDR

VOLTAGE=12.8V

PPVIN_SW_TBTBST

PP1V35_S3

PP1V05_S0

PP1V05_S0 PP1V05_S0

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V

PP1V05_S0

PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V5_S0

MAKE_BASE=TRUE

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.4 mm

PPVTT_S0_DDR

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S3

PP3V3_S5

PP3V3_S4

PP5V_S0

PPBUS_G3H

PPVIN_S5_HS_OTHER5V_ISNS

PP1V5_S0 PP1V5_S0

PPVTT_S0_DDR

MAKE_BASE=TRUE

PPVTTDDR_S3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM VOLTAGE=0.675V

PP1V5_S0

PP15V_TBT PP15V_TBT

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=20V

PP3V3_S0

PP3V3_SUS PP3V3_SUS

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP3V3_S3RS0_CAMERA

VOLTAGE=3.3V MAKE_BASE=TRUE

PP5V_S3

PP3V3_S3RS0_CAMERA

PP3V3_S0SW_SSD

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V MAKE_BASE=TRUEMIN_NECK_WIDTH=0.1 MM

PP3V3_S4_TBT

PP3V3_S0SW_SSD_R

PPVCC_S0_CPU

PPDCIN_G3H

PP3V42_G3H

PPVIN_S4_TPAD

MIN_NECK_WIDTH=0.25 MM

PPVIN_S4_TPAD

VOLTAGE=28V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVIN_S5_HS_OTHER5V_ISNS

MAKE_BASE=TRUE

PP5V_S0

PP5V_S3

PPVIN_S5_HS_OTHER3V3_ISNS

PPVIN_S5_HS_COMPUTING_ISNS

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PP15V_TBT

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=15V MAKE_BASE=TRUE

MIN_LINE_WIDTH=2 MM

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 MM

PPBUS_SW_BKL

PP1V35_S3

PP1V35_S3RS0_CPUDDR

PPVCC_S0_CPU

PP3V3_S4

PP1V05_S0

PP1V35_S3

PP1V05_SUS

PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS

PP1V35_S3RS0_FET

PP1V35_S3_MEM

PP1V35_S3

PPVTT_S0_DDR

PP1V35_S3RS0_CPUDDR

PP3V3_TBTLC

PPBUS_G3H

PP5V_S5

PP3V42_G3H PP3V42_G3H PP3V42_G3H

PP3V42_G3H

PP3V42_G3H PP3V42_G3H PP3V42_G3H

PP3V42_G3H

PP3V42_G3H PP3V42_G3H

PPVRTC_G3H

PPVIN_S5_HS_OTHER3V3_ISNS

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

PP5V_S4

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PP5V_S3

PP5V_S4

PP5V_S0

PP5V_S4

MIN_NECK_WIDTH=0.085 MM MAKE_BASE=TRUE

VOLTAGE=0V

GND

MIN_LINE_WIDTH=0.6 MM

<SCH_NUM>

100 OF 118

69 OF 81

69

56 57 69 71

45 56 57 69

19 35 38 39 41 42 43 44 50 56 57 66 69 71

18 19 37 49 50 58 59 62 63 65 66 69 70 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

6 8

10 46 59 69 71

6 8

10 46 59 69 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

39 61 65 69

71

11 12 15 19

69

11 12 15 19 69

11 12 13 14 15 17 19 20 29 33 35 44

45 46 47 48 49 51 52 55 65

66 67 69 71 81

13 20 21 22 44 46 47 65 68 69

71

12 14 15 17 18 19 21 31 32 34 61 64 65 66

69 70 71 81

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69

70 71 81

12 14 15 17 18 19 21 31 32 34

61 64 65 66 69 70 71 81

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

20 34 39 42 43 46 47 65 66 68 69 70 71

20 34 39 42 43 46 47 65 66 68

69 70 71

12 14 15 17 18 19 21 31

32 34 61 64 65 66 69 70 71

81

20 34 39 42 43 46 47 65 66 68 69 70 71

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

30 45 56 57 63 69 71

11 12 13 15 17 19 52 64 66 68 69 71

20 34 39 42 43 46 47 65 66 68 69 70 71

11 12 13 15 17 19 52 64 66 68 69 71

11 12 13 14 15 17 50 64 65 66 69

18 64 69

20 34 39 42 43 46 47 65 66 68 69 70 71

11 12 13 14 15 17 50 64 65 66 69

11 12 13 14 15 17 50 64 65 66

69

30 45 56 57 63 69 71

13 20 21 22 44 46 47 65 68 69

71

13 20 21 22 44 46 47 65 68 69 71

11 12 13 14 15 17 50 64 65 66 69

13 20 21 22 44 46 47 65 68 69 71

6 8

10 21 65 66

69 81

6 8

10 21 65

66 69 81

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

18 19 37 49 50 58 59 62 63 65 66 69 70 71

18 19 37 49 50 58 59 62 63 65 66 69 70

71

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

45 58 59 60 62 69

19 20 28 29 69

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

38 51 61 65

66 67

68 69

71

39 61 65 69 71

38 51 61 65 66 67 68 69 71

45 56 57 69

21 22 46 60 65 69 71

23 24 25 26 46 69 77

65 68 69

11 12 13 15 17 19 52 64 66 68 69 71

65 68 69

30 31 32 69

63 69

28 29 30 46 69

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

46 65 69

35 46 69 71

45 58 59 60

62 69

45 61 69

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

11 12 13 14 15 17 50 64 65 66 69

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

23 24 25 26 46 69 77

11 12 13 15 17 19 52 64 66 68 69 71

21 27 60 69 71

30

21 22 46 60 65 69 71

14 15 17 18 42 62 66 69 71

11 12 13 15 17 19 52 64 66 68 69 71

21 27 60 69 71

11 12 13 14 15 17 19 20 29 33

35 44 45 46

47 48 49 51 52 55 65 66 67 69

71 81

11 12 13 14 15 17 19 20 29

33

35 44 45 46 47 48 49 51

52

55 65 66 67 69 71 81

11 12 13 14

15 17 19 20 29 33 35 44 45 46

47 48

49 51 52 55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33

35 44 45 46

47 48 49 51 52 55 65 66 67 69

71 81

11 12 13 14 15 17 19 20 29

33

35 44 45 46 47 48 49 51

52

55 65 66 67 69 71 81

11 12 13 14

15 17 19 20 29 33 35 44 45 46

47 48

49 51 52 55 65 66 67 69 71 81

11 12 13 14 15 17 19

20 29 33 35 44 45 46 47 48 49

51 52

55 65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33

35 44 45 46

47 48 49 51 52 55 65 66 67 69

71 81

11 12 13

14 15 17

19 20 29

33 35 44 45 46 47 48 49

51 52 55 65 66 67 69

71 81

11 12 13 14

15 17

19 20

29 33

35 44

45 46 47 48 49 51 52 55 65

66 67 69 71 81

11 12 13 14 15 17 19 20 29 33

35

44 45 46 47 48 49 51 52 55 65

66

67 69 71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

11 12 13 14 15 17 19

20

29

33

35

44

45

46

47

48

49

51

52

55

65

66

67

69

71

81

11 12 13 14 15 17 19 20 29 33

35 44 45 46

47 48 49 51 52 55 65 66 67 69

71 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

11 12 13 14 15 17 19 20 29 33

35 44 45 46

47 48 49 51 52 55 65 66 67 69

71 81

11 12 13 14 15 17 19 20 29

33

35 44 45 46 47 48 49 51

52

55 65 66 67 69 71 81

11 12 13 14

15 17 19 20 29 33 35 44 45 46

47 48

49 51 52 55 65 66 67 69 71 81

13 20 21 22 44 46 47 65 68 69 71

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

12 14 15 17 18 19 21 31 32 34

61 64

65 66 69 70 71 81

12 14 15 17 18 19 21 31 32 34

61 64 65 66 69 70 71

81

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71 81

20 34 39 42 43 46 47 65 66 68 69 70

71

18 19 37 49 50 58 59 62 63 65

66 69

70 71

30 45 56 57 63 69 71

45 61 69

11 12 13 15 17 19 52 64 66 68 69 71

60 69 71

11 12 13 15 17 19 52 64 66 68 69 71

30 31 32 69

56 57 69 71

11 12 13 14 15 17 50 64 65 66

69

11 12 13 14 15 17 50 64 65 66 69

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

13 36 47 69

21 37 60 65 66 69 71

13 36 47 69

35 46 69 71

28 29 30 46 69

46 65 69

6 8

10 46 59 69 71

56 57 69 71

19 35 38 39

41 42

43 44

50 56

57 66

69 71

69 69

45 61 69

18 19 37 49 50 58 59 62 63 65

66 69 70 71

18 19 37 49 50 58 59 62 63 65 66 69 70 71

21 37 60 65

66 69

71

21 37 60 65 66 69 71

45 58 59 60 62 69

30 31 32 69

63 69

6 8

10 21 65 66 69 81

20 34 39 42 43 46 47 65 66 68 69 70 71

21 22 46 60 65 69 71

45 58 59 60 62 69

23 24 25 26 46 69 77

21 22 46 60 65 69 71

21 27 60 69 71

6 8

10 21 65 66 69 81

19 20 28 29 69

30 45 56 57

63 69

71

39 61 65 69 71

19 35 38 39 41 42 43 44 50 56 57 66 69 71

19 35 38 39 41 42 43 44 50 56

57 66 69 71

11 12 15 19 69

45 61 69

38 51 61 65 66 67 68 69 71

21 37 60 65 66 69 71

38 51 61 65 66 67 68 69 71

18 19 37 49

50 58

59 62

63 65

66 69

70 71

38 51 61 65 66 67 68 69 71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Thunderbolt Signals Through PEG

MAKE_BASE

VOLTAGE

Unused PEG Lanes

CPU signals

Unused signals

Display Aliases

SM

XWA202

1 2

SM

XWA203

1 2

5

28 74

5

28 74

5

28 74

5

28 74

1/20W

0

MF

5%

0201

RA201

1 2

NOSTUFF

0

5%

1/20W

MF

0201

RA202

1 2

Signal Aliases

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

MAKE_BASE=TRUE

HDMI_HPD

HDMI_CLK_N

PP3V3_S3_FAN_CTL

DP_TBTSNK1_DDC_DATA

MAKE_BASE=TRUE

EDP_IG_PANEL_PWR EDP_IG_BKL_ON

DP_TBTSNK0_HPD

TP_DP_IG_C_MLP<3..0>

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3_FAN_CTL

MAKE_BASE=TRUE

DP_TBTSNK1_HPD

HDMI_HPD

PP3V3_S5

PP3V3_S4

DP_INT_AUXCH_C_N

MAKE_BASE=TRUE

PP5V_S0_AUDIO_AMP_R

VOLTAGE=5V

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

MIN_LINE_WIDTH=0.4MM

PP5V_S0_AUDIO_AMP_L

PP5V_S0

MAKE_BASE=TRUE

HDMI_DDC_DATA

HDMI_DDC_CLK

MAKE_BASE=TRUE

HDMI_CLK_P

HDMITBTMUX_SEL_TBT SDCONN_OC_L

PEG_CLKREQ_L

AUD_IP_PERIPHERAL_DET

ENET_LOW_PWR_PCH

DPMUX_UC_IRQ

TBT_GO2SX_BIDIR

AUD_I2C_INT_L

MEM_VDD_SEL_1V5_L

BT_PWRRST_L

ENET_CLKREQ_L

DP_INT_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_N

AUD_IPHS_SWITCH_EN_PCH

=PEG_D2R_P<15..4>

=PEG_D2R_N<3..0> =PEG_R2D_C_P<3..0> =PEG_R2D_C_N<3..0>

=PEG_R2D_C_N<15..4>

TP_DP_IG_A_MLN<3..0>

TP_DP_IG_A_MLP<3..0>

EDP_IG_BKL_PWM

TP_DP_IG_B_MLP<3..0>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_DDC_DATA DP_TBTSNK0_DDC_CLK

DP_TBTSNK1_HPD

TP_DP_IG_C_MLN<3..0>

HDMI_CLK_P

TP_DP_IG_D_MLN<2..0>

TP_DP_IG_D_MLP<2..0>

DP_TBTSNK1_AUXCH_C_N DP_TBTSNK1_DDC_DATA DP_TBTSNK1_DDC_CLK

TP_DP_IG_B_MLN<3..0>

DP_TBTSNK1_AUXCH_C_P

DP_INT_AUXCH_C_P

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFCA_A

MEMVTT_EN

FW_PWR_EN_PCH

PP0V75_S3_MEM_VREFDQ_B

ENET_MEDIA_SENSE_RDIV

PP0V75_S3_MEM_VREFCA_B

0.675V

TRUE

0.675V

PP0V75_S3_MEM_VREFCA_A

TRUE

0.675V

PP0V75_S3_MEM_VREFDQ_B

TRUE

MAKE_BASE=TRUE

MEMVTT_EN

MAKE_BASE=TRUE

HDMI_DATA_N<0..2>

MAKE_BASE=TRUE

HDMI_DATA_P<0..2>

MAKE_BASE=TRUE

HDMI_CLK_N

MAKE_BASE=TRUE

HDMI_DDC_CLK

DP_TBTSNK1_AUXCH_C_N

MAKE_BASE=TRUE

DP_TBTSNK1_DDC_CLK

MAKE_BASE=TRUE

DP_INT_AUXCH_C_P

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_N<3..0>

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_DATA

DP_TBTSNK0_AUXCH_C_N

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_P

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_CLK

MAKE_BASE=TRUE

DP_TBTSNK1_ML_C_N<3..0>

MAKE_BASE=TRUE

DP_TBTSNK1_ML_C_P<3..0>

DP_TBTSNK1_AUXCH_C_P

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_INT_ML_C_P<3..0>

MAKE_BASE=TRUE

EDP_IG_PANEL_PWR

MAKE_BASE=TRUE

DP_INT_ML_C_N<3..0>

MAKE_BASE=TRUE

EDP_IG_BKL_PWM

TP_PEG_R2D_CN<15..4>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3..0>

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<3..0>

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<3..0>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<3..0>

MAKE_BASE=TRUE

TP_PEG_D2RP<15..4>

MAKE_BASE=TRUE

TP_PEG_D2RN<15..4>

MAKE_BASE=TRUE

TP_PEG_R2D_CP<15..4>

MAKE_BASE=TRUE

DP_TBTSNK0_HPD

PP0V75_S3_MEM_VREFDQ_A

TRUE

0.675V

EDP_IG_BKL_ON

MAKE_BASE=TRUE

=PEG_D2R_P<3..0>

=PEG_R2D_C_P<15..4>

=PEG_D2R_N<15..4>

DP_TBT_SEL

HDMI_DDC_DATA

FW_PME_L

WOL_EN

<SCH_NUM>

102 OF 118

70 OF 81

12 20 68 70

5

68 70 71 74

49 70

12 33 70

12 67 70 71

12 63 70 71

12 28 70

49 70

12 28 70

12 20 68 70

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 71 81

20 34 39 42 43 46 47 65 66 68 69 71

5

67 70 74

53

18 19 37 49 50 58 59 62 63 65 66 69 71

12 68 70 71

5

68 70 71 74

28

12

11

12

14

12

14

12

11

5

67 70 74

12 28 70 74

12

12 63 70

12 28 70 74

12 33 70

12 28 70

5

68 70 71 74

5

12 28 70 74

12 33 70

12 28 70 74

5

67 70 74

22 23 24 70 74 77

22 25 26 70 74

22 23 24 70 74 77

21 60 70

14

22 25 26 70 74

11

22 25 26 70 74

22 23 24 70 74 77

22 25 26 70 74

21 60 70

68 71 74

5

68 70 71 74

12 68 70 71

12 28 70 74

12 33 70

5

67 70 74

5

28 74

12 33 70

12 28 70 74

12 33 70

5

28 74

5

28 74

12 28 70 74

5

28 74

5

67 74

12 67 70 71

5

67 74

12 63 70

5

12 28 70

22 23 24 70 74 77

12 63 70 71

11

12 68 70 71

14

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Power Sequence

FUNC_TEST

XDP

FUNC_TEST

Power Rails

4X

J3501 - airport

FUNC_TEST

J6100 - lpc + spi

FUNC_TEST

2X

8X

J7050 - battery

J7000 - DC PWR

3X

16X

4X

2X GND

FUNC_TEST

J9500 - rio coax

19X

10X

5X

3X

3X 5X

J6050 - left fan

J5150 - hall effect

J6060 - right fan

5X

3X

J9510 - rio flex

J4813 - keyboard

J4915 - kbd bklt

2X

2X GND

J6603 - R speaker

J6602 - L speaker

J6601 - mic

J6701 - audio flex

J4002 - Camera

J8300 - eDP

2X

Functional Test Points

J4800 - ipd flex

I1918

I1919 I1920

I1921

I1922

I1923

I1924

I1925 I1927

I1928

I1929

I1930

I1931 I1932

I1934

I1935

I1936

I1938 I1939

I1940

I1941

I1942

I1943

I1944

I1948 I1949

I1950

I1951 I1952

I1953

I1954

I1955

I1956

I1957 I1958

I1959 I1960

I1961

I1962 I1963

I1965

I1966

I1967

I1968

I1969

I1970 I1971

I1972

I1973 I1974

Functional Test Points

SYNC_MASTER=J15_MLB

SYNC_DATE=10/31/2012

FAN_RT_TACH

TRUE

PCIE_AP_R2D_N

TRUE

PP3V3_S3RS4_BT_F

TRUE

SPI_ALT_MISO

TRUE

TP_SMC_MD1

LPCPLUS_GPIO

TRUE

SMC_RX_L

TP_SMC_TRST_L

TRUE

PSOC_MOSI

TRUE

PSOC_MISO

TRUE

SMBUS_SMC_2_S3_SDA

TRUE TRUE

SMC_LID SMC_T101_COM_1

TRUE

PSOC_SCLK

TRUE

Z2_KEY_ACT_L

TRUE

PSOC_F_CS_L

TRUE

PICKB_L

PP5V_S5

TRUE

PP3V3_S4

SMBUS_SMC_2_S3_SCL

TRUE

Z2_CS_L

TRUE

Z2_MOSI

TRUE

Z2_MISO

TRUE

Z2_CLKIN

TRUE

LED_RETURN_2

TRUE

LED_RETURN_3

TRUE

PP5VR3V3_SW_LCD PPVOUT_S0_LCDBKLT

TRUE

PM_SLP_S3_L

PP3V3_S5

TRUE

PP5V_S0

TRUE

PP5V_S5

TRUE TRUE

PPBUS_G3H PPDCIN_G3H

TRUE TRUE

PPVCC_S0_CPU PPVTTDDR_S3

TRUE

PP3V3_S0SW_SSD

TRUE

WS_KBD4 WS_KBD5

TRUE

WS_KBD6

TRUE

PP3V3_S0

TRUE

PP3V42_G3H

TRUE

PP5V_S3

TRUE

AP_CLKREQ_Q_L

TRUE

SMC_TX_L

TRUE

SPI_ALT_CS_L

TRUE

SPI_ALT_MOSI

TRUE

SYS_DETECT_L

FAN_LT_TACH

TRUE

WIFI_EVENT_L

Z2_SCLK

TRUE

Z2_HOST_INTN

TRUE

MIPI_CLK_CONN_N

TRUE TRUE

MIPI_CLK_CONN_P

MIPI_DATA_CONN_N

TRUE

USB3_SD_D2R_P

TRUE

USB3_SD_D2R_N

PP3V3_S0

TRUE

FAN_RT_PWM

TRUE

PP3V42_G3H

TRUE

SMBUS_PCH_DATA

TRUE

PP1V05_S0

TRUE

LPC_AD<3>

TRUE

LPC_AD<1>

LPCPLUS_RESET_L

TRUE TRUE

LPC_AD<0>

PCIE_AP_D2R_PI_P

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE TRUE

PCIE_WAKE_L

TRUE

PP5V_S0

TRUE

DP_INT_AUX_N

PPVBAT_G3H_CONN

TRUE

XDP_CPU_PREQ_L XDP_CPU_PRDY_L

TRUE

CH_HS_MIC

TRUE

PP3V3_S0

TRUE

US_HS_MIC

TRUE

SPKRCONN_L_ID

TRUE

SPKRCONN_L_OUT_N

TRUE

SPKRCONN_L_OUT_P

TRUE

SPKRCONN_SL_OUT_N

TRUE

DMIC_CLK3

TRUE

AUD_CONN_SLEEVE_XW

TRUE

AUD_TYPEDET

TRUE

AUD_TIPDET_INV

TRUE

AUD_HP_PORT_R

TRUE

DMIC_SDA3

TRUE

EDP_IG_BKL_ON

TRUE

KBDBKLT_RETURN1

TRUE

PP3V3_S4

HDMI_DATA_N<0>

TRUE

HDMI_CLK_N

TRUE

HDMI_CLK_P

TRUE

HDMI_DATA_N<1>

TRUE

HDMI_DATA_P<0>

TRUE TRUE

HDMI_DATA_P<1>

RIO_SDCONN_STATE_CHANGE_L

TRUE

PP3V3_S4

TRUE

PP5V_S4

TRUE

PM_SLP_S4_L

TRUE

PP3V3_S3

TRUE

PM_SLP_S3_BUF_L

TRUE

SMBUS_PCH_CLK

TRUE

HDMI_DDC_DATA HDMI_HPD_L

TRUE

HDMI_DDC_CLK

SD_PWR_EN

TRUE

PP1V5R1V35_S0_RIO

TRUE

USB_EXTB_P

TRUE

USB_EXTB_N

TRUE

USB_EXTB_OC_L

TRUE

USB3_EXTB_D2R_N

TRUE

USB3_SD_R2D_C_P

TRUE

USB3_SD_R2D_C_N

USB3_EXTB_R2D_P

TRUE

USB3_EXTB_R2D_N

TRUE

USB3_EXTB_D2R_P

TRUE

HDMI_DATA_P<2>

TRUE

HDMI_DATA_N<2>

TRUE

I2C_CAM_SCK

TRUE

I2C_CAM_SDA

TRUE

PP5V_S3RS0_ALSCAM_F

TRUE

SMBUS_SMC_0_S0_SCL

TRUE

SMBUS_SMC_0_S0_SDA

TRUE

PP5V_S0

TRUE

FAN_LT_PWM

TRUE

SMC_LID_R

TRUE

CAM_SENSOR_WAKE_L_CONN

TRUE

MIPI_DATA_CONN_P

TRUE

PP3V3_WLAN

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

PCIE_AP_R2D_P

TRUE

SMC_ONOFF_L

TRUE

EDP_IG_PANEL_PWR

TRUE

PLT_RESET_L

TRUE

PM_PCH_SYS_PWROK

TRUE

ALL_SYS_PWRGD

TRUE

PM_DSW_PWRGD

TRUE

XDP_CPU_TCK

TRUE TRUE

XDP_PCH_TCK

TRUE

XDP_CPU_TDI

TRUE

XDP_CPU_TDO

TRUE

XDP_CPUPCH_TRST_L

TRUE

XDP_PCH_TMS

TRUE

XDP_PCH_TDI

TRUE

XDP_CPU_TMS

PP1V5_S0

TRUE

PP1V35_S3

TRUE

LED_RETURN_6

TRUE

PPVTT_S0_DDR

WS_LEFT_SHIFT_KBD

TRUE

KBDBKLT_RETURN2

TRUE

PPVOUT_S0_KBDBKLT

TRUE

AP_RESET_CONN_L

TRUE

PCIE_AP_D2R_PI_N

TRUE

USB_BT_CONN_N

TRUE TRUE

USB_BT_CONN_P

LPC_AD<2>

TRUE

LPC_CLK33M_LPCPLUS

TRUE

LPC_FRAME_L

TRUE TRUE

LPC_PWRDWN_L LPC_SERIRQ

TRUE TRUE

PM_CLKRUN_L PP5V_S0

TRUE

SMC_RESET_L

TRUE

SMC_TCK

TRUE

SMC_TDI

TRUE

SMC_TDO

TRUE

SMC_TMS

TRUE

SPI_ALT_CLK

PP3V42_G3H

TRUE

WS_KBD1

TRUE

WS_KBD10

TRUE

WS_KBD11

TRUE

WS_KBD13

TRUE

WS_KBD12

TRUE

WS_KBD14 WS_KBD15_CAP

TRUE

WS_KBD16_NUM

TRUE

WS_KBD18

TRUE

WS_KBD17

TRUE

WS_KBD19

TRUE

WS_KBD2

TRUE

WS_KBD20

TRUE

WS_KBD22

TRUE

WS_KBD21

TRUE

WS_KBD23

TRUE

WS_KBD3

WS_KBD7

TRUE

WS_KBD9

TRUE

WS_KBD8

TRUE

WS_KBD_ONOFF_L

TRUE TRUE

WS_LEFT_OPTION_KBD

DMIC_SDA2

TRUE

SPKRCONN_SL_OUT_P

TRUE

SPKRCONN_R_ID

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_SR_OUT_N

TRUE

SPKRCONN_SR_OUT_P

ADAPTER_SENSE

TRUE

PP20V_DCIN_FUSE

TRUE

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

TRUE

DP_INT_AUX_P

DP_INT_ML_N<1>

TRUE

DP_INT_ML_N<0>

TRUE

DP_INT_ML_N<3>

TRUE

DP_INT_ML_N<2>

TRUE

DP_INT_ML_P<0>

TRUE

DP_INT_ML_P<1>

TRUE

DP_INT_ML_P<2>

TRUE

LCD_FSS

TRUE

DP_INT_ML_P<3>

TRUE

LCD_HPD_CONN

TRUE

LED_RETURN_1

TRUE

LED_RETURN_4 LED_RETURN_5

TRUE

PP3V3_S3

TRUE

PP3V3_S5_AVREF_SMC

TRUE

AUD_CONN_MIC_XW

TRUE

AUD_SPDIF_OUT_JACK

TRUE

AUD_HP_PORT_L

XDP_PCH_TDO

TRUE

PM_PCH_PWROK

TRUE

PM_RSMRST_L

TRUE

PM_SYSRST_L

TRUE

CPU_CFG<3>

TRUE

WS_CONTROL_KBD

SPIROM_USE_MLB

TRUE

SMC_ROMBOOT

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

<SCH_NUM>

104 OF 118

71 OF 81

49

34 76

34

50

14 50

41 42 50

50

39

39 41 44 80

39 41 42 43

39

39 61 65 69 71

20 34 39 42 43 46 47 65 66 68 69 70 71

39 41 44 80

39

63 67

67

63 67

12 21 41 66

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 81

18 19 37 49 50 58 59 62 63 65 66 69 70 71

39 61 65 69 71

30 45 56 57 63 69

56 57 69

6 8

10 46 59 69

60 69

35 46 69

39

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

19 35 38 39 41 42 43 44 50 56 57 66 69 71

21 37 60 65 66 69

34

41 42 50

50

56

49

34 41 42

39

37 79

13 20 68 76

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

49

19 35 38 39 41 42 43 44 50 56 57 66 69 71

13 18 22 44 63 68 76

14 15 17 18 42 62 66 69

13 41 50 76

20 50 76

13 41 50 76

34 76

12 34 36 76

18 19 37 49 50 58 59 62 63 65 66 69 70 71

67 74

56 57

6

18 74

6

18 74

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67 69 71 81

52 55

53 55 81

52 55

54 55

51 55

52 55

12 63 70

40 63

20 34 39 42 43 46 47 65 66 68 69 70 71

68 70 74

5

68 70 74

5

68 70 74

20 68

20 34 39 42 43 46 47 65 66 68 69 70 71

38 51 61 65 66 67 68 69

12 21 34 38 41 66 68

13 20 21 22 44 46 47 65 68 69 71

51 65 66 68

13 18 22 44 63 68 76

12 68 70

13 18 68

68

13 68 75

18 68

13 68 75

13 20 68 76

68 75

13 68 75

68 70 74

36 37

37

37 41 44 48 80

18 19 37 49 50 58 59 62 63 65 66 69 70 71

49

43

37

37 79

34 42

34 76

39 41 42

12 67 70

12 18 20 21

12 18 19 41 76

18 19 41 58 66

12 41 76

6

18 74

11 18

6

18 74

6

18 74

6

18 74

11 18

6

18 74

11 12 13 15 17 19 52 64 66 68 69

21 22 46 60 65 69

63 67

21 27 60 69

39

40 63

34

34 76

34 75

13 41 50 76

19 50 76

13 41 50 76

12 20 41 50

13 41 50

12 41 50

18 19 37 49 50 58 59 62 63 65 66 69 70 71

41 42 50 57

41 42 50

50

19 35 38 39 41 42 43 44 50 56 57 66 69 71

39

55

53 55 81

52 55

53 55 81

56

41 44 56 57 80

67 74

63 67

67 74

67

63 67

13 20 21 22 44 46 47 65 68 69 71

41 42

51 55

11 18

12 19 76

12 66 76

12 19 41 76

6

18 74

39

14 50

42 50

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

TP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MAKE_BASE

Thunderbolt

NC NO_TESTs

PLACEABLE BEAD-PROBES FOR TBT

NO_TESTNO_TEST

PCH

MAKE_BASE

SM

BEAD-PROBE

NO_XNET_CONNECTION=TRUE

BPA532

1

BEAD-PROBE

SM

NO_XNET_CONNECTION=TRUE

BPA531

1

BEAD-PROBE

SM

NO_XNET_CONNECTION=TRUE

BPA535

1

I1975

I1976

I1977

I1978

SYNC_DATE=10/31/2012

SYNC_MASTER=J15_MLB

NC & No Test

NC_CLINK_DATA

NC_PCI_CLK33M_OUT2 NC_PCI_CLK33M_OUT3 NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3

NC_CLINK_CLK

NC_CLINK_RESET_L

TRUE TRUE

NC_PCI_CLK33M_OUT2

TRUE

NC_PCI_CLK33M_OUT3

TRUE

DMI_N2S_P<3..1>

TRUETRUE

NC_PCIE_CLK100M_GPUP

TRUE TRUE

NC_PCIE_CLK100M_PE5P

TRUE TRUE

NC_PCIE_CLK100M_ENETSDN

TRUETRUE

NC_PCIE_CLK100M_PEGBN NC_PCIE_CLK100M_PEGBP NC_PCIE_CLK100M_SWN

NC_SATA_ODD_D2RP NC_SATA_ODD_R2D_CN

NC_SATA_D_R2D_CP

NC_USB_EXTCP

NC_USB_SDP

NC_DP_IG_D_AUXCHP

TRUE TRUE

NC_USB_7N

TRUE

NC_USB_6P

TRUE

TRUE TRUE

NC_SATA_D_R2D_CP

NC_SATA_B_R2D_CN

TRUETRUE

NC_PCIE_CLK100M_GPUN

NC_USB3_SPARE_D2RN

TRUE TRUE

NC_DP_IG_D_AUXCHP

NC_PCIE_CLK100M_GPUN NC_PCIE_CLK100M_GPUP NC_PCIE_CLK100M_PE5N

TRUE

NC_DP_IG_D_AUXCHN

TRUE

TRUE TRUE

NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P

NC_DP_IG_D_AUXCHN

TRUE TRUE

NC_USB3_EXTC_D2RP

TRUETRUE

NC_USB3_EXTD_D2RP

NC_PCIE_CLK100M_ENETSDN NC_PCIE_CLK100M_ENETSDP

NC_PCIE_CLK100M_PEGBN

NC_PCIE_CLK100M_ENETP

NC_PCIE_CLK100M_ENETN

NC_PCH_GPIO67_CLKOUTFLEX3

TRUE TRUE

NC_USB_7PNC_USB_7P NC_USB_EXTDN NC_USB_EXTDP NC_USB_PSOCN

TRUE

NC_USB_WLANP

TRUE

NC_PCIE_CLK100M_SWP NC_PCH_GPIO64_CLKOUTFLEX0

NC_PCH_GPIO65_CLKOUTFLEX1

NC_USB_4P

NC_USB_PSOCN

TRUE TRUE

NC_USB_PSOCP

TRUE TRUE

TRUE

NC_USB_IRN

TRUE

NC_USB_IRP

TRUETRUE

NC_USB_IRP

NC_USB_IRN

NC_USB_PSOCP

TRUE TRUE

NC_USB_EXTDN

TRUE

NC_USB_6N

TRUE

NC_USB_SDN

TRUETRUE

TRUE TRUE

NC_USB_EXTCP

TRUE

NC_USB_EXTCN

TRUE

NC_PCH_GPIO65_CLKOUTFLEX1

TRUE TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

TRUETRUE

NC_PCH_GPIO67_CLKOUTFLEX3

TRUETRUE

TRUE TRUE

NC_PCIE_CLK100M_ENETSDP

NC_USB3_SPARE_R2D_CP

TRUE TRUE

NC_USB3_EXTC_R2D_CP

NC_PCH_GPIO66_CLKOUTFLEX2

NC_USB_4N

TRUE TRUE

NC_SATA_F_D2RN

NC_SATA_D_R2D_CN

TRUE TRUE

NC_SATA_ODD_R2D_CP

NC_SATA_ODD_R2D_CN

TRUE TRUE

TRUE

NC_SATA_ODD_D2RN

TRUE

NC_SATA_B_D2RP

TRUE TRUE

NC_SATA_A_D2RP

TRUETRUE

NC_USB3_SPARE_D2RN

TRUE TRUE

NC_USB3_EXTD_D2RN

NC_SATA_ODD_D2RN

NC_SATA_A_D2RP

TRUETRUE

NC_PCIE_ENET_R2D_CN

TRUE TRUE

NC_USB_7N

TRUETRUE

NC_SATA_D_D2RP

NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP

NC_USB_EXTCN

NC_USB_SDN

NC_USB_WLANN

NC_USB_6N NC_USB_6P

TRUETRUE

NC_PCIE_ENET_D2RP

NC_SATA_D_D2RN

NC_HDA_SDIN3

TRUE TRUE

NC_PCI_PME_L

TRUETRUE

NC_SATA_F_R2D_CP

TRUETRUE

NC_SATA_D_D2RP

NC_USB_EXTDP

TRUETRUE

TRUE

NC_USB_4N

TRUE

TRUETRUE

NC_USB_4P

TRUETRUE

NC_PCIE_CLK100M_ENETN

TRUE TRUE

NC_PCIE_CLK100M_ENETP

TRUE TRUE

NC_PCIE_CLK100M_PEGBP

NC_PCIE_CLK100M_SWP

TRUETRUE

NC_USB_SMCP NC_USB_SMCN

TRUETRUE

NC_ITPXDP_CLK100MP

NC_USB3_EXTC_D2RP

NC_USB3_SPARE_D2RP

TRUE TRUE

NC_SMC_INTERFACE_2

TRUE TRUE

NC_TBT_XTAL25OUT

TRUETRUE

TRUE TRUE

NC_HDA_SDIN2

NC_SATA_A_D2RN

TRUETRUE

NC_SATA_A_R2D_CN

TRUETRUE

TRUE TRUE

NC_USB3_EXTC_R2D_CN

TRUETRUE

NC_USB3_EXTD_R2D_CP

NC_SATA_A_R2D_CP

TRUETRUE TRUETRUE

NC_SATA_B_D2RN

TRUETRUE

NC_SATA_B_R2D_CP

NC_USB_SMCN

TRUE TRUE

NC_USB_SMCP

TRUETRUE

TRUE TRUE

NC_CLINK_DATA

TRUE

NC_CLINK_RESET_L

TRUE

TRUE TRUE

NC_CLINK_CLK

NC_LPC_DREQ0_L

TRUE TRUE

TRUE

NC_HDA_SDIN1

TRUE

TRUE TRUE

NC_ITPXDP_CLK100MN

TRUE

NC_USB_SDP

TRUE

NC_USB_WLANN

TRUE

NC_SATA_F_R2D_CN

TRUETRUE

NC_SATA_D_D2RN

TRUE TRUE

NC_SATA_ODD_D2RP

TRUE TRUE

NC_DP_TBTSRC_AUXCH_CN

NC_USB3_EXTC_D2RN

TRUE TRUE

NC_PCH_GPIO64_CLKOUTFLEX0

TRUETRUE

TRUE TRUE

NC_USB3_SPARE_R2D_CN

TRUETRUE

NC_USB3_EXTD_R2D_CN

TRUE TRUE

NC_DP_TBTSRC_AUXCH_CP

NC_DP_TBTSRC_ML_CP<3..0>

TRUETRUE

PCIE_TBT_R2D_P<3..0>

TRUE

PCIE_TBT_R2D_N<3..0>

TRUE

PCIE_TBT_D2R_C_P<3..0>

TRUE

PCIE_TBT_D2R_C_N<3..0>

TRUE

DMI_S2N_P<3..1>

TRUE

DMI_S2N_N<3..1>

TRUE

DMI_N2S_N<3..1>

TRUE TRUE

NC_PCIE_CLK100M_SWN

NC_SATA_F_D2RP

TRUE TRUE

NC_SATA_D_R2D_CN

NC_SMC_INTERFACE_2

NC_TBT_XTAL25OUT

NC_DP_TBTSRC_AUXCH_CN

NC_DP_TBTSRC_AUXCH_CP

TP_DP_TBTSRC_ML_CN<3..0>

NC_PCIE_ENET_R2D_CP

NC_PCIE_ENET_D2RP

NC_PCIE_ENET_D2RN

NC_USB3_EXTD_R2D_CP

NC_USB3_EXTD_R2D_CN

NC_USB3_EXTD_D2RN NC_USB3_EXTD_D2RP

NC_USB3_EXTC_R2D_CP

NC_USB3_EXTC_D2RN

NC_USB3_SPARE_R2D_CP

NC_USB3_SPARE_R2D_CN

NC_USB3_SPARE_D2RP

TBT_A_R2D_C_P<1> TBT_A_D2R_P<1> TBT_A_D2R_N<1>

NC_SATA_F_D2RN

NC_USB_WLANP

NC_ITPXDP_CLK100MN

NC_PCI_PME_L

NC_ITPXDP_CLK100MP

NC_LPC_DREQ0_L

NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP

NC_SATA_B_D2RP

NC_SATA_B_D2RN

NC_SATA_A_R2D_CP

NC_USB3_EXTC_R2D_CN

NC_SATA_A_R2D_CN

NC_SATA_A_D2RN

NC_PCIE_ENET_R2D_CN

TP_DP_TBTSRC_ML_CP<3..0>

TRUETRUE

NC_DP_TBTSRC_ML_CN<3..0>

TRUE

NC_PCIE_ENET_D2RN

TRUE

TRUETRUE

NC_PCIE_ENET_R2D_CP

NC_SATA_ODD_R2D_CP

<SCH_NUM>

105 OF 118

72 OF 81

13 72

11 72

13 72

11 72

5

12 74

11 72

13 72 75

12 72

13 72 75

11 72

11 72 75

11 72

13 72

12 72

11 72

12 72

11 72

12 72

13 72 75

11 72

13 72 75 13 72 75

13 72 75

13 72

11 72

13 72

13 72 75

13 72 75 13 72 75

13 72 75

13 72

13 72 75

11 72

13 72

13 72 75

11 72

13 72

11 72

11 72 75

13 72

13 72 75

11 72

11 72 75

72

13 72 75

11 72

13 72 75

13 72

13 72 75

72

11 72

12 72

11 72

13 72 75

13 72

11 72

72 75

11 72 74

13 72 75

13 72

72

28 72

11 72

11 72 75

13 72 75

11 72 75

72 75

13 72

11 72

11 72 74

13 72 75

13 72

11 72

28 72

13 72 75

11 72

13 72

13 72 75

28 72

28

28 74

5

12 74

5

12 74

5

12 74

11 72

72

28 72

72

13 72 75

13 72

28 31 78

11 72

13 72

11 72 74

12 72

11 72 74

13 72

11 72 75

13 72 75

11 72 75

72

28

72

11 72

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

J15 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

Note: Outer dielectric is 0.058 mm nominal, Inner dielectric is 0.053 mm nominal.

Stackup-Defined Spacing Rules

0.1 MM

*

DEFAULT

?

=DEFAULT

*

STANDARD

?

=STANDARD

1:1_DIFFPAIR

Y*

=STANDARD

0.1 MM0.1 MM

=STANDARD

P072_SPACE

**

BGA

1x_DIELECTRIC

TOP,BOTTOM

?

0.058 MM

P075_SPACE

0.075 MM

?

*

P65_BGA

P65BGA

*

1X_DIELECTRIC

0.101 MM

?

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

P65BGA

* *

P075_SPACE

BGA_P1MM

0.1 MM

?

*

BGA_P2MM

*

0.2 MM

?

P072_SPACE

0.071 MM

*

?

1:1_SPACING

0.1 MM

*

0.120 MM

80_OHM_DIFFYISL2,ISL11

0.120 MM

0.092 MM 0.092 MM

* =STANDARDN

=STANDARD

85_OHM_DIFF

=STANDARD

=STANDARD =STANDARD

0.200 MM

Y

90_OHM_DIFF

ISL2,ISL11

0.078 MM 0.078 MM

0.200 MM

Y

ISL3,ISL4,ISL9,ISL10

90_OHM_DIFF

0.078 MM0.078 MM

0.200 MM0.200 MM

90_OHM_DIFF

N* =STANDARD =STANDARD

=STANDARD=STANDARD =STANDARD

Y

ISL2,ISL11

0.120 MM 0.120 MM

85_OHM_DIFF

0.080 MM 0.080 MM

ISL3,ISL4,ISL9,ISL10

0.120 MM0.120 MM

85_OHM_DIFF

Y

0.080 MM 0.080 MM

0.053 MM

?

ISL3,ISL4,ISL9,ISL10

1x_DIELECTRIC

0.071MM 0.071MM

Y*

0.075MM 0.126MM

P65_BGA

TOP,BOTTOM

90_OHM_DIFF

Y

0.101 MM 0.101 MM

0.180 MM0.180 MM

0.125 MM

TOP,BOTTOM

85_OHM_DIFF

0.125 MM

Y

0.105 MM 0.105 MM

0.155 MM

Y

80_OHM_DIFF

TOP,BOTTOM

0.125 MM

0.155 MM

0.125 MM

0.120 MM 0.120 MM

Y

80_OHM_DIFF

0.092 MM

ISL3,ISL4,ISL9,ISL10

0.092 MM

=STANDARD=STANDARD

=STANDARD* N

80_OHM_DIFF

=STANDARD

Y

0.146 MM

0.120 MM0.120 MM

TOP,BOTTOM

72_OHM_DIFF

0.146 MM

0.105 MM0.105 MM

0.120 MM

72_OHM_DIFF

Y

0.120 MM

ISL2,ISL11

0.120 MM

Y

ISL3,ISL4,ISL9,ISL10

72_OHM_DIFF

0.120 MM

0.105 MM 0.105 MM

=STANDARD =STANDARD

=STANDARDN* =STANDARD

72_OHM_DIFF

=STANDARD

=STANDARD* Y

0.1 MM

=STANDARD

27P4_OHM_SE

0.186 MM

Y

0.095 MM

TOP,BOTTOM

27P4_OHM_SE

0.265 MM

SYNC_DATE=12/10/2012

SYNC_MASTER=SIDLE_J45

PCB Rule Definitions

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

MM

NO_TYPE,BGA,P65BGA

16.2

Y

TOP,BOTTOM

50_OHM_SE

0.095 MM0.095 MM

0.066 MM

Y =STANDARD=STANDARD

=STANDARD

*

50_OHM_SE

0.066 MM

0.083 MM 0.083 MM

45_OHM_SE =STANDARD

=STANDARDY* =STANDARD

=STANDARD

=STANDARD =STANDARD* Y

40_OHM_SE

0.102 MM 0.090 MM

=STANDARD=STANDARD

=STANDARD37_OHM_SE

Y*

0.118 MM 0.090 MM

0.165 MM

TOP,BOTTOM

37_OHM_SE

Y

0.095 MM

=45_OHM_SE 10 MM=45_OHM_SE

*

DEFAULT

Y

0 MM 0 MM

0.116 MM0.116 MM

Y

45_OHM_SE

TOP,BOTTOM

40_OHM_SE

TOP,BOTTOM

Y

0.095 MM0.145 MM

10 MM

=DEFAULTSTANDARD =DEFAULT

Y

=DEFAULT

*

=DEFAULT

<SCH_NUM>

110 OF 118

73 OF 81

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SPACING

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

DP AUX NET PROPERTIES

CPU Net Properties

PHYSICAL

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

Some signals require 27.4-ohm single-ended impedance.

SOURCE: IVB PLATFORM DG , Tables 205-207

DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.

SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.

DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.

MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.

Spacing Rule Sets

CPU Signal Constraints

SPACING

NET_TYPE

DIGITAL VIDEO SIGNAL CONSTRAINTS

PEG - SSD & TBT

Most CPU signals with impedance requirements are 50-ohm single-ended.

ELECTRICAL_CONSTRAINT_SET

DP / HDMI NET PROPERTIES

I125

I126

I130

I132

I133

I134

I135

I136

I140

I141

I144

I145

I146

I147

I150

I151

I152

I153

I154

I155

I156

I157

I158

I159

I166

I167

I170

I171

I210

I211

I212

I213

I223

I224

I225

I226

I227

I228

I229

I230

I231

I232

I233

I234

I235 I236

I237 I238

I239

I240 I241

I242

I243 I244

I245

I246

SYNC_DATE=12/10/2012

CPU Constraints

SYNC_MASTER=SIDLE_J45

8 MIL

* ?

CPU_8MIL

?*

20 MIL

CPU_COMP

=10X_DIELECTRIC

?

DMICLK2N2S TOP,BOTTOM

?

=4X_DIELECTRIC

TOP,BOTTOM

DMICLK2OTHER

DMI_S2N

*

DMI_TXRX

DMI_N2S

=2x_DIELECTRIC

?

TOP,BOTTOM

CPU_AGTL

* ?

0.457 MM

CPU_VID

?*

CPU_VCCSENSE

25 MIL

CPU_ITP

* ?

=2:1_SPACING

DMICLK2N2S

=6X_DIELECTRIC

?*

DMI_S2N

*

DMI_N2S

DMI_TXRX

*

DMICLK2OTHER

*

CLK_DMI

=3X_DIELECTRIC

?*

PEG_2SAME

=10X_DIELECTRIC

?

PEG_2CLK

TOP,BOTTOM

PEG_D2R

*

PEG_R2D

PEG_TXRX

PEG_2SAME

*

=SAMEPEG_*

=7X_DIELECTRIC

PEG_2CLK

*

?

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

DP_85D

*

=85_OHM_DIFF =85_OHM_DIFF

=4x_DIELECTRIC

?

DP_2OTHER

*

=7x_DIELECTRIC

?*

HDMICLK_2CLK

=4x_DIELECTRIC

HDMICLK_2DP

?*

=3x_DIELECTRIC

?*

DP_2SAME

=7x_DIELECTRIC

*

HDMICLK_2OTHER

?

CLK_*

PEG_2CLK

*

PEG_*

* *

PEG_* PEG_2OTHER

=4X_DIELECTRIC

?

*

PEG_2OTHER

=6X_DIELECTRIC

PEG_TXRX

*

?

*

CLK_*

HDMI_CLK

HDMICLK_2CLK

HDMI_CLK

HDMICLK_2DP

*

DISPLAYPORT

*

DISPLAYPORT

DP_2OTHER

*

DISPLAYPORT

DP_2SAME

*

=SAME

HDMICLK_2OTHER

=10x_DIELECTRIC

TOP,BOTTOM

?

HDMICLK_2DP

TOP,BOTTOM

?

=6x_DIELECTRIC

?

=STANDARD

CPU_AGTL

*

DMICLK2N2S

*

CLK_DMI DMI_N2S

=10X_DIELECTRIC

TOP,BOTTOM

?

DMI_TXRX

=STANDARD

*

=STANDARD

=50_OHM_SE =50_OHM_SE=50_OHM_SE

CPU_50S

=50_OHM_SE

=STANDARD

=45_OHM_SE=45_OHM_SE

*

=STANDARD

CPU_45S

=45_OHM_SE =45_OHM_SE

HDMI_CLK

* *

HDMICLK_2OTHER

CLK_DMI

DMICLK2S2N

*

DMI_S2N

=4X_DIELECTRIC

?*

DMICLK2OTHER

*

=6X_DIELECTRIC

?

DMI_TXRX

=3X_DIELECTRIC

DMI_2SAME

?*

HDMICLK_2CLK

?

=10x_DIELECTRIC

TOP,BOTTOM

DP_2OTHER

?

=6x_DIELECTRIC

TOP,BOTTOM

=4x_DIELECTRIC

TOP,BOTTOM

?

DP_2SAME

=6X_DIELECTRIC

?

TOP,BOTTOMPEG_2OTHER

?

=4X_DIELECTRIC

TOP,BOTTOM

PEG_2SAME

PEG_TXRX

?

=10X_DIELECTRIC

TOP,BOTTOM

=6X_DIELECTRIC

?

TOP,BOTTOM

DMICLK2S2N

=80_OHM_DIFF

=80_OHM_DIFF=80_OHM_DIFF

=80_OHM_DIFF

*

=80_OHM_DIFF

PEG_80D

=80_OHM_DIFF

DMI_* =SAME

DMI_2SAME

*

=3X_DIELECTRIC

?*

DMICLK2S2N

TOP,BOTTOM?=4X_DIELECTRIC

DMI_2SAME

?*

12 MIL

CPU_VREF

7 MIL

=27P4_OHM_SE

7 MIL

*

=27P4_OHM_SE

CPU_27P4S

=27P4_OHM_SE =27P4_OHM_SE

=85_OHM_DIFF

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

CPU_85D

DP_INT_AUXCH_C_P

DP_INT_IG_AUX

DP_85D

DISPLAYPORT

DP_INT_ML_F_N<3..0>

DISPLAYPORT

DP_85D

CPU_PROCHOT_L

CPU_45S

CPU_AGTL

CPU_PROCHOT_L

CPU_45S CPU_ITP

XDP_DBRESET_L

XDP_BDRESET_L

XDP_BPM CPU_45S

XDP_BPM_L<3..0>

CPU_ITP

DP_INT_IG_AUX

DP_INT_AUXCH_C_N

DP_85D

DISPLAYPORT

XDP_BPM_L

CPU_45S CPU_ITP

XDP_BPM_L<7..4>

DP_INT_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_INT_ML_P<3..0>

DISPLAYPORT

DP_85D

DP_INT_ML_F_P<3..0>

DISPLAYPORT

DP_85D

CPU_45S CPU_VID

CPU_PECI

CPU_45S CPU_ITPXDP_TMS

XDP_CPU_TMS

CPU_45S CPU_ITP

XDP_CPU_TCK

XDP_TCK

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_45S CPU_VID

CPU_VIDALERT_L

CPU_VID

CPU_SM_RCOMP<2..0>

CPU_27P4S

CPU_SM_RCOMP CPU_COMP

CPU_8MIL

PM_THRMTRIP_L

CPU_45S

CPU_45S CPU_VIDCPU_VID

CPU_VIDSCLK

DISPLAYPORT

DP_TBTSNK1_ML_N<3..0>

DP_85D

TBTSNK0_AUXCH

DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N

TBTSNK0_AUXCH

DP_85D DP_85D

DP_TBTSNK0_AUXCH_C_P

DP_85D

DP_TBTSNK0_AUXCH_C_N DP_TBTSNK1_AUXCH_P

TBTSNK1_AUXCH

DP_85D DP_85D

TBTSNK1_AUXCH

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_ML_P<3..0>

DISPLAYPORT

DP_85D

DP_TBTSNK1_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_TBT_ML1

CPU_VCCSENSE_N

CPU_27P4S

CPU_VCCSENSECPU_VCCSENSE

CLK_PCIE

CPU_CLK135M_DPLLREF_P

CPU_85DCPU_CLK135_PLL

CPU_CLK135_PLL CPU_85D

CPU_CLK135M_DPLLSS_P

CLK_PCIE

CLK_DMICPU_85DDMI_CLK

DMI_CLK100M_CPU_P

CPU_AGTL

FDI_CSYNC

CPU_50S

FDI_CSYNC

CPU_PWRGD

CPU_45S

CPU_AGTL

CPU_PWRGD

CPU_45S CPU_ITP

XDP_PREQ_L

XDP_CPU_PREQ_L

CPU_EDP_COMP

CPU_27P4S

CPU_EDP_RCOMP

CPU_COMP

CPU_45SXDP_TDI CPU_ITP

XDP_CPU_TDI

PEG_R2D

PCIE_TBT_R2D_C_P<3..0>

CPU_85D

PCIE_TBT_R2D_C_N<3..0>

PEG_R2DCPU_85D

CPU_DIMMB_VREFDQ

CPU_VREFCPU_MEM_VREF

PEG_D2R

PEG_D2R_TBT

PCIE_TBT_D2R_P<3..0>

CPU_85D

DMI_S2NCPU_85DDMI_S2N

DMI_S2N_N<3:0>

CPU_45S CPU_ITPCPU_CFG

CPU_CFG<19..0>

CPU_45S CPU_ITP

XDP_CPU_TDO

XDP_TDO

CLK_PCIE_85D

NC_ITPXDP_CLK100MN

CLK_PCIE

XDP_CLK_PCH

CLK_PCIE_85D CLK_PCIE

NC_ITPXDP_CLK100MP

XDP_CLK_PCH

XDP_CPUPCH_TRST_L

CPU_45S CPU_ITP

XDP_TRST_L

CPU_CLK135M_DPLLREF_N

CLK_PCIE

CPU_CLK135_PLL CPU_85D

CPU_MEM_VREF

MEM_PWR

PP0V75_S3_MEM_VREFCA_A

PCIE_TBT_R2D_N<3..0>

PEG_R2D_TBT

PEG_R2DCPU_85D

CPU_VREF

PP0V75_S3_MEM_VREFDQ_B

CPU_MEM_VREF

CPU_DIMMA_VREFDQ

CPU_VREFCPU_MEM_VREF

CPU_45SPM_SYNC

CPU_AGTL

PM_SYNC

CPU_COMPCPU_PEG_COMP

CPU_PEG_RCOMP

CPU_27P4S

DMI_N2S

DMI_N2S_N<3:0>

CPU_85DDMI_N2S

DMI_CLK

DMI_CLK100M_CPU_N

CLK_DMICPU_85D

CPU_45S

PM_MEM_PWRGD

CPU_AGTL

CPU_CLK135_PLL CPU_85D

CPU_CLK135M_DPLLSS_N

CLK_PCIE

PEG_R2D

PCIE_TBT_R2D_P<3..0>

PEG_R2D_TBT

CPU_85D

PCIE_TBT_D2R_C_P<3..0>

PEG_D2RCPU_85D

PCIE_TBT_D2R_C_N<3..0>

PEG_D2RCPU_85D

PEG_D2R_TBT

PCIE_TBT_D2R_N<3..0>

CPU_85D PEG_D2R

CPU_VREFCPU_MEM_VREF

PP0V75_S3_MEM_VREFCA_B

CPU_MEM_VREF

PP0V75_S3_MEM_VREFDQ_A

MEM_PWR

CPU_45S CPU_VIDCPU_VID

CPU_VIDSOUT

DISPLAYPORT

HDMI_DATA

DP_85D

HDMI_DATA_P<2..0>

DP_85D

DP_TBTSNK1_AUXCH_C_P

HDMI_CLK_N

HDMI_CLK

DP_85D

HDMI_CLK

DP_85D

DISPLAYPORT

DP_TBTSNK0_ML_N<3..0>

DP_85D

DP_TBTSNK1_AUXCH_C_N

HDMI_CLK_P

HDMI_CLK HDMI_CLK

DP_85D

HDMI_DATA_N<2..0>

DISPLAYPORT

HDMI_DATA

DP_85D

DP_TBTSNK1_ML_C_P<3..0>

DP_85D

DISPLAYPORT

DP_TBT_ML1

DP_TBTSNK0_ML_P<3..0>

DP_85D

DISPLAYPORT

DP_TBTSNK0_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_TBT_ML0

DP_TBTSNK0_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_TBT_ML0

XDP_CPU_PRDY_L

CPU_ITPCPU_45S

XDP_PRDY_L

CPU_45S

CPU_AGTLCPU_CATERR_L

CPU_CATERR_L

CPU_AGTL

FDI_INT

CPU_50SFDI_INT

DMI_N2S

DMI_N2S_P<3:0>

CPU_85DDMI_N2S

DMI_S2N_P<3:0>

DMI_S2N DMI_S2NCPU_85D

DISPLAYPORT

DP_85D

DP_INT_ML_P<3..0>

DP_85D

DP_INT_IG_ML

DP_INT_ML_C_P<3..0>

DISPLAYPORT

DP_INT_IG_AUX

DP_85D

DP_INT_AUX_P

DISPLAYPORT

DP_85D

DP_INT_ML_N<3..0>

DISPLAYPORT

DP_INT_IG_ML

DP_85D

DP_INT_ML_C_N<3..0>

DISPLAYPORT

DP_INT_IG_AUX

DP_INT_AUX_N

DISPLAYPORT

DP_85D

<SCH_NUM>

111 OF 118

74 OF 81

5

67 70

67

6

41 42 58

6

18 19

6

18

5

67 70

6

18

67 71 74

67

6

14 42

6

18 71

6

18 71

8

58

8

58

6

14 42

8

58

28

12 28 70

28

5

28 70

9

58

6

11

6

11

6

11

5

12

6

14 18

6

18 71

5

6

18 71

5

28 70

5

28 70

7

22

5

28 70

5

12 72

6

18 71

6

18 71

11 72

6

18 71

6

11

22 23 24 70 77

28 72

22 25 26 70

7

22

6

12

5

12 72

6

11

6

12 21

6

11

28 72

5

28 70

22 25 26 70

22 23 24 70 77

8

58

68 70 71

12 28 70

5

68 70 71

28

12 28 70

5

68 70 71

5

28 70

28

5

28 70

5

28 70

6

18 71

6

41

5

12

5

12 72

5

12 72

67 71 74

5

67 70

67 71

67 71 74

5

67 70

67 71

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

USB 3.0 INTERFACE CONSTRAINTS

USB 2.0 Interface Constraints

System Clock Signal Constraints

NOTE: 25MHz system clocks very sensitive to noise.

ELECTRICAL_CONSTRAINT_SET

Clock Net Properties

NET_TYPE

PHYSICAL

SPACING

NOTE: Latest Intel DG calls out 50ohms SE for sys clocks

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PCH Net Properties

SATA Interface Constraints

I213

I220

I221

I222 I223

I228

I229

I230

I231

I238

I239

I244

I245

I248

I249

I250

I251

I253

I254

I255

I256

I259

I260

I261

I262

I263

I264

I265

I266

I267

I268

I271

I272

I273

I274

I281 I282

I283 I284

I285

I286

I287

I288

I290

I291

I292

I293

I294

I295

I296 I297

I298

I299

I300 I301

I302 I303

SYNC_MASTER=SIDLE_J45

SYNC_DATE=12/10/2012

PCH Constraints 1

USB3_2OTHER

=4X_DIELECTRIC

?

*

?

SATA_2SAME TOP,BOTTOM

=4x_DIELECTRIC

=45_OHM_SE

=45_OHM_SE=45_OHM_SE

=45_OHM_SE

SATA_45SE

*

SATA_D2R

*

SATA_R2D

SATA_TXRX

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

SATA_85D

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

*

=6X_DIELECTRIC

SATA_TXRX

* ?

PCH_USB_RBIAS

=STANDARD

=STANDARD=STANDARD

=STANDARD

*

=STANDARD=STANDARD

=85_OHM_DIFF

*

USB_85D

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

=4X_DIELECTRIC

* ?

SATA_2OTHER

* ?

SATA_RCOMP

=6X_DIELECTRIC

*

SATA_2SAME

SATA_*

=SAME

=3X_DIELECTRIC

SATA_2SAME

* ?

SATA_*

*

SATA_2OTHER

*

?

TOP,BOTTOM

=10X_DIELECTRIC

SATA_RCOMP

=37_OHM_SE =37_OHM_SE

SATA_37SE

=37_OHM_SE

=37_OHM_SE=37_OHM_SE

*

?

*

CLK_SLOW

=4x_DIELECTRIC

?

*

CLK_25M =5x_DIELECTRIC

USB3_2SAME

=4x_DIELECTRIC

?

TOP,BOTTOM

USB3_2OTHER

USB3_*

**

USB3_TXRX

*

USB3_D2RUSB3_R2D

USB3_*

*

=SAME USB3_2SAME

=45_OHM_SE

=STANDARD

=45_OHM_SE=45_OHM_SE=45_OHM_SE

CLK_25M_45S

=STANDARD*

=45_OHM_SE =45_OHM_SE=45_OHM_SE=45_OHM_SE

CLK_SLOW_45S

=STANDARD =STANDARD*

=10X_DIELECTRIC

USB3_TXRX

?

TOP,BOTTOM

USB3_2OTHER

TOP,BOTTOM

=6X_DIELECTRIC

?

*

USB3_TXRX

=6X_DIELECTRIC

?

*

=3X_DIELECTRIC

USB3_2SAME

=6X_DIELECTRICBT_WAKE

?

TOP,BOTTOM

USB_RBIAS

=10X_DIELECTRIC

?

TOP,BOTTOM

?

USB

=6X_DIELECTRIC

TOP,BOTTOM

SATA_2OTHER

?

=6X_DIELECTRIC

SATA_TXRX

?

TOP,BOTTOM

=10X_DIELECTRIC

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

USB3_85D

*

=6X_DIELECTRIC

USB_RBIAS

* ?

=4X_DIELECTRIC

USB *

?

*

BT_WAKE

?

=4X_DIELECTRIC

USB_TPAD_R_P

USB

USB_85D

USB_TPAD_R_N

USB_85D

USB

USB_85D

USB

USB_TPAD

USB_TPAD_P

USB_TPAD

USB_TPAD_N

USB

USB_85D

USB_NC

USB

USB_85D

NC_USB_6N NC_USB_7P

USB

USB_NC

USB_85D

USB_EXTB_N

USB

USB_85D

USB_EXTB

USB_85D

USB

USB_EXTB_P

NC_USB_IRN

USB_NC

USB_85D

USB

USB_85D

NC_USB_EXTCP

USB_NC

USB

USB_85D

USB

USB_LT1_P

USB_EXTA

USB

USB_EXTA_MUXED_P

USB_85D

USB_EXTA

PCH_SATA_RCOMP

SATA_45SE

PCH_SATA_RCOMP

SATA_RCOMP

SATA_85D SATA_D2R

NC_SATA_B_D2RN

USB_85D

USB

USB_LT1_N

USB_EXTA

SATA_85D SATA_R2D

NC_SATA_B_R2D_CP

USB

USB_EXTA_MUXED_N

USB_85D

USB_EXTA

CPU_ITPCPU_45S

SMC_DEBUGPRT_TX_L

CPU_ITP

SMC_DEBUGPRT_RX_L

CPU_45S

USB_85D

USB_EXTA

USB

USB_EXTA_N

USB

USB_EXTA_P

USB_85D

USB_EXTA

SATA_R2DSATA_85D

NC_SATA_A_R2D_CN

SATA_D2RSATA_85D

NC_SATA_A_D2RN

SATA_85D SATA_R2D

NC_SATA_B_R2D_CN

SATA_85D SATA_D2R

NC_SATA_B_D2RP

SATA_R2DSATA_85D

NC_SATA_A_R2D_CP

SATA_D2RSATA_85D

NC_SATA_A_D2RP

USB_85D

NC_USB_SDN

USB_NC

USB

USB_85DUSB_SMC

USB

NC_USB_SMCP

USB_NC

USB_85D

USB

NC_USB_EXTCN

NC_USB_SMCN

USB_SMC

USB

USB_85D

USB_BT_N

USB_BT

USB

USB_85D USB_85D

USB_BT_CONN_P

USB

USB_BT_CONN_N

USB_85D

USB

USB_85D

USB3_EXTB_D2R_C_N

USB3_D2R

USB3_EXTB_R2D_P

USB3_R2DUSB3_EXTB_TX

USB_85D

NC_USB_EXTDP

USB

USB_NC

USB_85D

NC_USB_IRP

USB

USB_NC

USB_85D

PCH_USB_RBIAS

USB_RBIAS

PCH_USB_RBIASPCH_USB_RBIAS

USB_NC

NC_USB_7N

USB

USB_85D

NC_USB_EXTDN

USB_NC

USB_85D

USB

USB_85D

USB_BT_P

USB

USB_BT

USB3_EXTA_RX

USB_85D

USB3_D2R

USB3_EXTA_D2R_P

USB3_EXTB_D2R_C_P

USB3_D2R

USB_85D

USB3_EXTB_R2D_C_P

USB3_R2D

USB_85D

NC_USB3_EXTC_D2RP

USB3_D2R

NC_USB3 USB_85D NC_USB3

USB3_D2R

NC_USB3_EXTC_D2RN

USB_85D USB_85D

NC_USB3_EXTC_R2D_CP

USB3_R2D

NC_USB3_EXTC_R2D_CN

USB3_R2D

USB_85D

NC_USB3_EXTD_D2RP

USB3_D2R

NC_USB3 USB_85D

USB_85D

NC_USB3_EXTD_R2D_CP

USB3_R2D

USB3_EXTA_D2R_C_N

USB3_D2R

USB_85D

USB3_R2D

USB3_EXTA_R2D_N

USB3_EXTA_TX

USB_85D

USB3_EXTB_R2D_C_N

USB3_R2D

USB_85D

USB3_D2R

USB3_EXTA_D2R_C_P

USB_85D

CLK_25M_45S

SYSCLK_CLK25M_TBT

CLK_25M

SYSCLK_CLK25M_TBT

USB3_EXTA_D2R_N

USB3_D2R

USB_85D

USB3_EXTA_RX

USB_85D

USB3_R2D

USB3_EXTB_R2D_N

USB3_EXTB_TX

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_TBT_R

NC_USB_6P

USB

USB_NC

USB_85D

NC_USB3_EXTD_D2RN

USB3_D2R

NC_USB3

CLK_25M_45S

SYSCLK_CLK25M_CAM

SYSCLK_CLK25M_CAMERA

CLK_25M

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_SB_R

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_SB

CLK_SLOW_45S CLK_SLOW

SYSCLK_CLK32K_RTC

USB_85D

USB

USB_NC

NC_USB_SDP

USB3_EXTA_R2D_P

USB3_EXTA_TX USB3_R2D

USB_85D

USB3_R2D

NC_USB3_EXTD_R2D_CN

USB3_EXTB_D2R_N

USB_85D

USB3_D2RUSB3_EXTB_RX

USB3_EXTB_D2R_P

USB3_EXTB_RX USB3_D2R

USB_85D

USB3_EXTA_R2D_C_N

USB3_R2D

USB_85D

USB3_R2D

USB3_EXTA_R2D_C_P

<SCH_NUM>

112 OF 118

75 OF 81

39

13 39

13 72

13 68 71

13 72

38

11

11 72

38

11 72

38

38 41 42

13 38

11 72

13 72

72

13 72

72

13 34

34 71

68 71

13 72

13

13 72

13 34

13 38

13 68

13 72

38

13 68

19 28

13 38

68 71

28

13 72

19 37

11

11 19

13 72

38

13 72

13 68 71

13 38

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ELECTRICAL_CONSTRAINT_SET

PCI-Express

PCH Single Net Constraints

SPI Interface Constraints

HD Audio Interface Constraints

ELECTRICAL_CONSTRAINT_SET

SPACING

PHYSICAL

PCH Net Properties

NET_TYPE

PHYSICAL

NET_TYPE

SPACING

PCH Net Properties

SMBus Interface Constraints

LPC Bus Constraints

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I275

I276

I281

I282

I293 I298

I299

I300

I303

I304

I307

I308

I313

I314 I315

I316

I317

I318

I319

I320

I321

I322

I323 I324

I325

I326

I327 I328

I329

I330 I331

I332

I333

I334

I335 I336

I337

I338

I339

I340

PCH Constraints 2

SYNC_DATE=12/10/2012

SYNC_MASTER=SIDLE_J45

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE

LPC_45S

=STANDARD

*

=STANDARD

=45_OHM_SE

CLK_LPC_45S

=45_OHM_SE=45_OHM_SE

=STANDARD=STANDARD

*

=45_OHM_SE

6 MIL

* ?

LPC

?

CLK_LPC

*

8 MIL

SMB

*

=2x_DIELECTRIC

?

HDA_45S

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE

=STANDARD

*

=STANDARD

=85_OHM_DIFF

*

=85_OHM_DIFFCLK_PCIE_85D =85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

*

=85_OHM_DIFF

PCIE_85D

=85_OHM_DIFF

=10X_DIELECTRIC

PCIECLK_2OTHER

TOP,BOTTOM

?

PCIE_TXRX

*

?

=6X_DIELECTRIC

*

?

PCIE_2OTHER

=4X_DIELECTRIC

PCIE_2CLK

*

=7X_DIELECTRIC

?

=7X_DIELECTRIC

*

?

PCIECLK_2OTHER

PCIE_2SAME

?*

=2X_DIELECTRIC

SMB_45S

=45_OHM_SE=45_OHM_SE=45_OHM_SE

=STANDARD

*

=STANDARD

=45_OHM_SE

=10X_DIELECTRIC

PCIE_2CLK

?

TOP,BOTTOM

PCIECLK_2OTHER

CLK_PCIE

**

PCIE_2CLK

PCIE_*

*

CLK_*

* *

PCIE_*

PCIE_2OTHER

*

SPI

?

8 MIL

PCIE_D2R

*

PCIE_R2D

PCIE_TXRX

=SAME

*

PCIE_*

PCIE_2SAME

TOP,BOTTOM

=4X_DIELECTRIC

?

PCIE_2SAME

=6X_DIELECTRIC

PCIE_2OTHER

?

TOP,BOTTOM

=10X_DIELECTRIC

?

TOP,BOTTOM

PCIE_TXRX

PCH_SE

* ?

=2x_DIELECTRIC

?

PCH_SE

=3x_DIELECTRIC

TOP,BOTTOM

=45_OHM_SE

PCH_45S

=STANDARD=STANDARD

*

=45_OHM_SE=45_OHM_SE =45_OHM_SE

=45_OHM_SE

SPI_45S

=STANDARD

*

=STANDARD

=45_OHM_SE =45_OHM_SE =45_OHM_SE

HDA

=2x_DIELECTRIC

?

*

PCIE_SSD_D2R_P<3..0>

PCIE_D2RPCIE_D2R_SSD PCIE_85D

PCIE_SSD_R2D_N<3..0>

PCIE_R2DPCIE_85D

PCIE_D2R

PCIE_SSD_D2R_N<3..0>

PCIE_D2R_SSD PCIE_85D

PCIE_SSD_R2D_C_P<3..0>

PCIE_R2D_SSD PCIE_R2DPCIE_85D

PCIE_R2D

PCIE_SSD_R2D_C_N<3..0>

PCIE_R2D_SSD PCIE_85D

PCH_PM_NET

PCH_RCIN_L

PCH_SE

PCH_45S

PCIE_SSD_R2D_P<3..0>

PCIE_R2DPCIE_85D

HDA_45S

HDA_SDIN0

HDA

HDA_45S

HDA_RST_L

HDA

HDA_RST_L

SMB_45S

SMBUS_PCH_1_DATA

SMB

SML_PCH_1_DATA

SMB

SML_PCH_0_DATA

SMB_45S

SMBUS_PCH_0_DATA

SMB_45S

SMB

SMBUS_PCH_DATA

PCIE_CAMERA_D2R_C_P

PCIE_85D PCIE_D2R

PM_THRMTRIP_L_R

PCH_SE

PCH_45S

PCH_PM_NET

PCH_SE

PM_PWRBTN_L

PCH_45S

PCH_PM_NET

PM_PCH_PWROK

PCH_SE

PCH_45S

PCH_PM_NET

PCH_SE

PCH_DSWVRMEN

PCH_PM_NET

PCH_45S

PCH_SE

PM_DSW_PWRGD

PCH_45S

PCH_PM_NET

PCH_SE

PCH_INTRUDER_L

PCH_45S

PCH_PM_NET

PCH_SE

PCH_INTVRMEN_L

PCH_45S

PCH_PM_NET

SPI_45S

SPI_MOSI

SPI

SPI_MOSI

PCIE_85D PCIE_R2D

PCIE_AP_R2D_PI_P

PCIE_AP_D2R_N

PCIE_85D PCIE_D2R

PCIE_AP_D2R

PCIE_85D

PCIE_CAMERA_R2D_C_P

PCIE_R2D

PCIE_D2R

PCIE_CAMERA_D2R_P

PCIE_85D

PCIE_CAMERA_D2R

PCIE_85D

PCIE_CAMERA_D2R

PCIE_D2R

PCIE_CAMERA_D2R_N

PCIE_85D PCIE_R2D

PCIE_AP_R2D_C_P

USB3_SD_R2D

USB3_85D USB3_R2D

USB3_SD_R2D_C_P

USB3_85D USB3_R2D

USB3_SD_R2D

USB3_SD_R2D_C_N

USB3_85D

USB3_SD_D2R

USB3_D2R

USB3_SD_D2R_P

SPI_45S

SPI

SPI_CLK_R

CLK_LPC

PCH_LPC_CLK0

LPC_CLK33M_SMC

CLK_LPC_45S

HDA_45S

HDA_SDOUT_R

HDA

SPI_45S

SPI

SPI_MOSI_R

PCIE_CLK100M_CAMERA_C_N

CLK_PCIE_85D CLK_PCIE

PCIE_CLK100M_CAMERA_C_P

CLK_PCIE_85D CLK_PCIE

PCIE_CLK100M_SSD_N

CLK_PCIECLK_PCIE_85D

PCIE_CLK100M_ENET

PCIE_85D CLK_PCIE

PCIE_CLK100M_SD_P

PCIE_CLK100M_ENET

PCIE_85D CLK_PCIE

PCIE_CLK100M_SD_N

CLK_PCIEPCIE_85D

PCIE_CLK100M_AP

PCIE_CLK100M_AP_P

PCH_CLK96M_DOT_P

CLK_PCIE

PCIE_CLK100M_DOT

CLK_PCIE_85D CLK_PCIE_85D CLK_PCIE

PCH_CLK96M_DOT_N

PCIE_CLK100M_DOT

CLK_PCIEPCIE_85D

PCIE_CLK100M_SATA

PCH_CLK100M_SATA_P

PCIE_85D

PCIE_CLK100M_SATA

PCH_CLK100M_SATA_N

CLK_PCIE

CLK_PCIE_85D

PCIE_CLK100M_TBT

PCIE_CLK100M_TBT_P

CLK_PCIE

PCIE_CLK100M_PCH

CLK_PCIE_85D

PCIE_CLK100M_PCH_N

CLK_PCIE

LPC_CLK33M_SMC_R

CLK_LPC

CLK_LPC_45S

PCIE_85D PCIE_D2R

PCIE_CAMERA_D2R_C_N

PCIE_R2D

PCIE_CAMERA_R2D_C_N

PCIE_85D

LPC_CLK33M_LPCPLUS

CLK_LPC_45S

CLK_LPC

PCH_LPC_CLK0

LPC_CLK33M_LPCPLUS_R

CLK_LPC

CLK_LPC_45S

PCIE_CLK100M

PCH_CLK33M_PCIIN

CLK_PCIE

CPU_45S

PCIE_85D PCIE_R2D

PCIE_CAMERA_R2D_N

PCIE_CAMERA_R2D

PCIE_85D

PCIE_AP_R2D

PCIE_AP_R2D_N

PCIE_R2D

PCIE_85D PCIE_R2D

PCIE_AP_R2D_C_N

PCIE_85D PCIE_R2D

PCIE_CAMERA_R2D_P

PCIE_CAMERA_R2D

PCIE_R2DPCIE_85D

PCIE_AP_R2D

PCIE_AP_R2D_P

USB3_SD_D2R_N

USB3_85D

USB3_SD_D2R

USB3_D2R

SPI_45S

SPI

SPI_MISO

PCIE_85D CLK_PCIE

PCIE_CLK100M_AP_CONN_N

PCIE_85D CLK_PCIE

PCIE_CLK100M_AP_CONN_P

PCIE_85D

PCIE_CLK100M_AP_N

CLK_PCIE

PCIE_CLK100M_AP

SPI_CLK SPI_45S

SPI

SPI_CLK

PCIE_CLK100M_PCH

CLK_PCIECLK_PCIE_85D

PCIE_CLK100M_PCH_P

PCH_CLK14P3M_REFCLK

CLK_PCIEPCIE_CLK100M

CPU_45S

LPC_45S

LPCPLUS_RESET_L

LPC

LPC_RESET_L

SPI_45S

SPI

SPI_CS0_R_L

LPC_45S

LPC_AD

LPC_AD<3..0>

LPC

CLK_PCIE

PCIE_CLK100M_SSD_P

PCIE_CLK100M_FW

CLK_PCIE_85D

PCIE_85D PCIE_D2R

PCIE_AP_D2R_PI_N

PCIE_CLK100M_S2

PCIE_CLK100M_CAMERA_P

CLK_PCIECLK_PCIE_85D

CLK_PCIE_85D

PCIE_CLK100M_TBT_N

CLK_PCIE

PCIE_CLK100M_TBT

PCIE_CLK100M_CAMERA_N

CLK_PCIECLK_PCIE_85D

PCIE_CLK100M_S2

CLK_PCIEPCIE_CLK100M

PCH_CLK33M_PCIOUT

CPU_45S

LPC_45S

LPC

LPC_FRAME_L

HDA_45S

HDA_SDOUT

HDA

HDA_SDIN0_R

CS4208_HDA_SDOUT0_R

HDA_45S

HDA

SPI_45S

SPI

SPI_CS0

SPI_CS0_L

SMB_45S

SMB

SMBUS_PCH_CLK

PCIE_AP_R2D_PI_N

PCIE_85D PCIE_R2D

PCIE_AP_D2R_PI_P

PCIE_85D PCIE_D2R

PCIE_AP_D2R_P

PCIE_85D PCIE_D2R

PCIE_AP_D2R

SMB_45S

SMB

SMBUS_PCH_1_CLK

SML_PCH_1_CLK

HDA_45S

HDA

HDA_BIT_CLK

HDA_45S

HDA

HDA_SYNC

HDA_45S

HDA

HDA_RST_R_L

HDA

HDA_SYNC_R

HDA_45S

PCH_SE

PCIE_WAKE_L

PCH_PCIE_WAKE

PCH_45S

PCH_SE

PM_PCH_SYS_PWROK

PCH_45S

PCH_PM_NET

PM_PCH_PWROK

PCH_45S

PCH_SE

PCH_PM_NET

PCH_SE

PM_SYSRST_L

PCH_45S

PCH_PM_NET

PCH_SE

PM_RSMRST_L

PCH_45S

PCH_PM_NET

PCH_45S

PCH_SE

PCH_SRTCRST_L

PCH_PM_NET

HDA_45S

HDA

HDA_BIT_CLK_R

SMB_45S

SMBUS_PCH_0_CLK

SMB

SML_PCH_0_CLK

<SCH_NUM>

113 OF 118

76 OF 81

13 35

35

13 35

14

35

11 52

13 44

13 18 22 44 63 68 71

36 37

14 42

12 18 41

12 19 71 76

12

12 41 71

11

50

34

13 34

13 37

13 34

13 20 68 71

13 50

19 41

11 19

13 50

36 37

11 35

11 34

11

11 28

11

11 19

36 37

13 37

19 50 71

11 19

36 37

34 71

13 34

36 37

34 71

13 20 68 71

13 50

34 71

11 34

50

11

20 50 71

13 50

13 41 50 71

11 35

34 71

11 37

11 28

11 37

11 19

13 41 50 71

11 52

52

50

13 18 22 44 63 68 71

34

34 71

13 34

13 44

11 52

11

12 34 36 71

12 18 19 41 71

12 19 71 76

12 19 41 71

12 66 71

11

13 44

http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DQ signals should be matched within 0.508mm of associated DQS pair

DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm]. CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

Memory Bus Spacing Group Assignments

Memory Bus Constraints

ELECTRICAL_CONSTRAINT_SET

Memory Net Properties

SPACING

PHYSICAL

Spacing Rule Sets

Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max.

SOURCE: Need to re-confirm CRW DG for memory down (Intel not yet provided)

A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs.

CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs.

NET_TYPE

DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.

SOURCE: Double checked with Doc#486985 Chief River SFF Platform DG: Memory Down

DDR3 (Memory Down):

Memory to Power Spacing

Memory to GND Spacing

I101

I103

I105

I106

I108

I109

I110

I111

I112

I113

I114

I115

I116

I117

I118

I119

I120 I121

I122

I123

I124

I125

I126

I127

I128

I129

I130

Memory Constraints

SYNC_MASTER=SIDLE_J45

SYNC_DATE=12/10/2012

?

=8x_DIELECTRIC

TOP,BOTTOM

MEM_2OTHERMEM

MEM_CTRL2CTRL

*

MEM_CTRLMEM_CTRL

=2x_DIELECTRIC

* ?

MEM_2PWR

MEM_DATA2SELF

=2x_DIELECTRIC

* ?

?

=2x_DIELECTRIC

MEM_DQS2OWNDATA

*

=4x_DIELECTRIC

?

MEM_2OTHERMEM

*

=2x_DIELECTRIC

?*

MEM_CTRL2CTRL

MEM_CMD2CMD

* ?

=2x_DIELECTRIC =2x_DIELECTRIC

MEM_CMD2CTRL

?*

GND

*

MEM_*

MEM_2GND

* *

MEM_PWR DEFAULT

MEM_PWR

MEM_*

*

MEM_2PWR

MEM_2OTHERMEM

*

MEM_*MEM_*

MEM_DATA2SELF

=SAME

MEM_*_DATA_*

*

MEM_CMDMEM_CMD

MEM_CMD2CMD

*

MEM_DQS2OWNDATA

MEM_B_DQS_6

MEM_B_DATA_6

*

MEM_B_DQS_4

MEM_B_DATA_4

MEM_DQS2OWNDATA

MEM_B_DATA_2

*

MEM_DQS2OWNDATA

MEM_B_DQS_2

MEM_DQS2OWNDATA

*

MEM_B_DQS_0

MEM_B_DATA_0

MEM_A_DQS_6

*

MEM_DQS2OWNDATA

MEM_A_DATA_6

*

MEM_DQS2OWNDATA

MEM_A_DQS_4

MEM_A_DATA_4

*

MEM_A_DQS_5

MEM_A_DATA_5

MEM_DQS2OWNDATA

*

MEM_A_DATA_2

MEM_A_DQS_2

MEM_DQS2OWNDATA

*

MEM_A_DATA_1

MEM_A_DQS_1

*

MEM_CTRL

*

MEM_2OTHER

TOP,BOTTOM

MEM_CMD2CMD

?

=5x_DIELECTRIC

MEM_DQS2OWNDATA

MEM_A_DATA_0

*

MEM_A_DQS_0

MEM_CLK2CLK

* ?

=4x_DIELECTRIC

=5x_DIELECTRIC

TOP,BOTTOM

?

MEM_DATA2SELF

=5x_DIELECTRIC

TOP,BOTTOM

?

MEM_CTRL2CTRL

?

=8x_DIELECTRIC

TOP,BOTTOM

MEM_CLK2CLK

MEM_DQS2OWNDATA

*

MEM_A_DATA_3

MEM_A_DQS_3

*

MEM_CLK

*

MEM_2OTHER

=6x_DIELECTRIC

?*

?

=2x_DIELECTRIC

*

MEM_2GND

=40_OHM_SE

=STANDARD

=40_OHM_SE =40_OHM_SE =40_OHM_SE

MEM_40S

=STANDARD*

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

*

MEM_85D

=85_OHM_DIFF

=45_OHM_SE

MEM_45S

=45_OHM_SE=45_OHM_SE=45_OHM_SE

* =STANDARD =STANDARD

=72_OHM_DIFF=72_OHM_DIFF

MEM_72D

* =72_OHM_DIFF

=72_OHM_DIFF

=37_OHM_SE=37_OHM_SE

=STANDARD* =STANDARD

=37_OHM_SE =37_OHM_SE

MEM_37S

MEM_DQS2OWNDATA

TOP,BOTTOM?=5x_DIELECTRIC

MEM_CMD2CTRL

TOP,BOTTOM?=5x_DIELECTRIC

TOP,BOTTOM

MEM_2PWR

?

=4x_DIELECTRIC

MEM_2GND

TOP,BOTTOM?=4x_DIELECTRIC TOP,BOTTOM

MEM_2OTHER

?

=10x_DIELECTRIC

*

MEM_CTRL

MEM_CMD2CTRL

MEM_CMD

*

MEM_CLK MEM_CLK

MEM_CLK2CLK

*

MEM_DQS2OWNDATA

MEM_B_DQS_7

MEM_B_DATA_7

*

MEM_B_DQS_5

MEM_B_DATA_5

MEM_DQS2OWNDATA

*

MEM_DQS2OWNDATA

MEM_B_DQS_3

MEM_B_DATA_3

MEM_B_DQS_1

MEM_DQS2OWNDATA

*

MEM_B_DATA_1

*

MEM_DQS2OWNDATA

MEM_A_DQS_7

MEM_A_DATA_7

*

MEM_2OTHER

*

MEM_CMD

* *

MEM_2OTHER

MEM_*_DQS_*

MEM_2OTHER

* *

MEM_*_DATA_*

MEM_B_CLK1

MEM_72D MEM_CLK

MEM_B_CLK_N<1>

MEM_B_CNTL0

MEM_40S

MEM_CTRL

MEM_B_CKE<0>

MEM_CTRL

MEM_B_CNTL1

MEM_40S

MEM_B_CKE<1>

MEM_CTRL

MEM_B_CNTL1

MEM_40S

MEM_B_ODT<1>

MEM_45S

MEM_B_DATA_3

MEM_B_DQ<31..24>

MEM_B_DATA_3

MEM_40S MEM_CMD

MEM_B_CMD

MEM_B_WE_L

MEM_40S

MEM_B_CMD

MEM_CMD

MEM_B_CAS_L

MEM_40S

MEM_B_CMD

MEM_CMD

MEM_B_RAS_L

MEM_CTRL

MEM_B_CNTL1

MEM_40S

MEM_B_CS_L<1>

MEM_A_DQS_6

MEM_A_DQS6

MEM_A_DQS_N<6>

MEM_85D

MEM_A_DQS_2

MEM_A_DQS2

MEM_A_DQS_P<2>

MEM_85D

MEM_A_DATA_6MEM_A_DATA_6

MEM_A_DQ<55..48>

MEM_45S

MEM_A_DATA_3MEM_A_DATA_3

MEM_A_DQ<31..24>

MEM_45S

MEM_A_DATA_2MEM_A_DATA_2

MEM_A_DQ<23..16>

MEM_45S

MEM_A_DATA_1MEM_A_DATA_1

MEM_A_DQ<15..8>

MEM_45S

MEM_A_DATA_0MEM_A_DATA_0

MEM_A_DQ<7..0>

MEM_45S

MEM_CMD

MEM_A_CMD

MEM_A_WE_L

MEM_40S

MEM_A_RAS_L

MEM_CMD

MEM_A_CMD

MEM_40S

MEM_CMD

MEM_A_CAS_L

MEM_A_CMD

MEM_40S

MEM_A_DQS_1

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_85D

PP0V75_S3_MEM_VREFDQ_A

MEM_PWR

PP0V75_S3_MEM_VREFCA_A

MEM_PWR MEM_PWR

PP1V35_S3_MEM

MEM_B_DQS5

MEM_B_DQS_5

MEM_B_DQS_P<5>

MEM_85D

MEM_B_DQS_4

MEM_B_DQS4

MEM_B_DQS_N<4>

MEM_85D

MEM_B_DATA_7 MEM_B_DATA_7

MEM_B_DQ<63..56>

MEM_45S

MEM_B_DQ<55..48>

MEM_B_DATA_6 MEM_B_DATA_6

MEM_45S

MEM_A_DQS_6

MEM_A_DQS6

MEM_A_DQS_P<6>

MEM_85D

MEM_A_DQS5

MEM_A_DQS_5

MEM_A_DQS_N<5>

MEM_85D

MEM_A_DQS_3

MEM_A_DQS_P<3>

MEM_85D

MEM_A_DQS3

MEM_A_DATA_5MEM_A_DATA_5

MEM_A_DQ<47..40>

MEM_45S

MEM_A_DATA_7

MEM_A_DQ<63..56>

MEM_A_DATA_7

MEM_45S

MEM_A_DQS_1

MEM_A_DQS1

MEM_A_DQS_N<1>

MEM_85D

MEM_A_DATA_4MEM_A_DATA_4

MEM_A_DQ<39..32>

MEM_45S

MEM_A_DQS_P<4>

MEM_A_DQS_4

MEM_A_DQS4

MEM_85D

MEM_A_DQS_7

MEM_A_DQS_P<7>

MEM_A_DQS7

MEM_85D

MEM_72D MEM_CLK

MEM_A_CLK_N<1>

MEM_A_CLK1

MEM_72D

MEM_B_CLK0

MEM_B_CLK_N<0>

MEM_CLK

MEM_B_CLK1

MEM_CLKMEM_72D

MEM_B_CLK_P<1>

MEM_CTRL

MEM_40S

MEM_B_ODT<0>

MEM_B_CNTL0

MEM_CTRL

MEM_B_CNTL0

MEM_40S

MEM_B_CS_L<0>

MEM_B_DQS0

MEM_B_DQS_0

MEM_B_DQS_P<0>

MEM_85D

MEM_B_DQS_1

MEM_B_DQS1

MEM_B_DQS_N<1>

MEM_85D

MEM_B_DQS0

MEM_B_DQS_0

MEM_B_DQS_N<0>

MEM_85D

MEM_B_DQS1

MEM_B_DQS_1

MEM_B_DQS_P<1>

MEM_85D

MEM_B_DQS2

MEM_B_DQS_2

MEM_B_DQS_P<2>

MEM_85D

MEM_B_DQS_3

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_85D

MEM_B_DQS3

MEM_B_DQS_N<3>

MEM_B_DQS_3

MEM_85D

MEM_B_DQS6

MEM_B_DQS_6

MEM_B_DQS_P<6>

MEM_85D

MEM_B_DQS6

MEM_B_DQS_6

MEM_B_DQS_N<6>

MEM_85D

MEM_B_DQS_7

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_85D

MEM_CLKMEM_72D

MEM_B_CLK_P<0>

MEM_B_CLK0

MEM_A_CNTL1

MEM_CTRL

MEM_40S

MEM_A_CKE<1>

MEM_A_DQS_3

MEM_A_DQS3

MEM_85D

MEM_A_DQS_N<3>

MEM_A_DQS_5

MEM_A_DQS_P<5>

MEM_A_DQS5

MEM_85D

MEM_B_DQS_7

MEM_B_DQS7

MEM_B_DQS_N<7>

MEM_85D

MEM_B_DQS_5

MEM_B_DQS5

MEM_B_DQS_N<5>

MEM_85D

MEM_B_DQS_4

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_85D

MEM_B_DQS_2

MEM_B_DQS2

MEM_B_DQS_N<2>

MEM_85D

MEM_A_CNTL1

MEM_CTRL

MEM_40S

MEM_A_CS_L<1>

MEM_A_BA<2..0>

MEM_40S MEM_CMD

MEM_A_CMD

MEM_CTRL

MEM_40S

MEM_A_ODT<0>

MEM_A_CNTL0

MEM_CTRL

MEM_A_ODT<1>

MEM_A_CNTL1

MEM_40S

MEM_CMDMEM_40S

MEM_A_A<15..0>

MEM_A_CMD

MEM_CTRL

MEM_40S

MEM_A_CS_L<0>

MEM_A_CNTL0

MEM_40S

MEM_CTRL

MEM_A_CKE<0>

MEM_A_CNTL0

MEM_72D MEM_CLK

MEM_A_CLK_P<1>

MEM_A_CLK1

MEM_72D MEM_CLK

MEM_A_CLK_N<0>

MEM_A_CLK0

MEM_72D MEM_CLK

MEM_A_CLK_P<0>

MEM_A_CLK0

MEM_45S

MEM_B_DQ<7..0>

MEM_B_DATA_0MEM_B_DATA_0

MEM_40S

MEM_B_CMD

MEM_CMD

MEM_B_BA<2..0>

MEM_CMDMEM_40S

MEM_B_A<15..0>

MEM_B_CMD

MEM_A_DQS_0

MEM_A_DQS0

MEM_A_DQS_N<0>

MEM_85D

MEM_A_DQS_0

MEM_A_DQS_P<0>

MEM_A_DQS0

MEM_85D

MEM_B_DATA_5MEM_B_DATA_5

MEM_B_DQ<47..40>

MEM_45S

MEM_B_DATA_4MEM_B_DATA_4

MEM_B_DQ<39..32>

MEM_B_DATA_2 MEM_B_DATA_2

MEM_B_DQ<23..16>

MEM_45S

MEM_B_DATA_1

MEM_B_DQ<15..8>

MEM_B_DATA_1

MEM_45S

MEM_A_DQS_7

MEM_A_DQS7

MEM_A_DQS_N<7>

MEM_85D

MEM_A_DQS4

MEM_A_DQS_4

MEM_A_DQS_N<4>

MEM_85D

MEM_A_DQS_2

MEM_A_DQS_N<2>

MEM_A_DQS2

MEM_85D

<SCH_NUM>

114 OF 118

77 OF 81

7

26 27

7

25 27

7

26 27

7

26 27

7

25 26

7

25 26 27

7

25 26 27

7

25 26 27

7

26 27

7

23 24

7

23 24

7

23 24

7

23 24

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http://sualaptop365.edu.vn

w w w . c h i n a f i x . c o m

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Only used on dual-port hosts.

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

Thunderbolt IC Net Properties

Only used on hosts supporting Thunderbolt video-in

SPACING

Thunderbolt SPI Signal Constraints

TBT_DP Interface Constraints

NET_TYPE

SOURCE: Bill Cornelius’s Thunderbolt Routing Notes

Thunderbolt/DP Connector Signal Constraints

DisplayPort Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

Thunderbolt/DP Net Properties

I308

I309

I310

I311

I312

I313 I314

I315

I316 I317

I318 I319

I320

I321

I322

I323

I324

I325

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I328 I329

I330

I331

I332

I333

I334

I335

I336

I337

I338

I339

I340

I341

I342

I343

SYNC_MASTER=SIDLE_J45

SYNC_DATE=12/10/2012

Thunderbolt Constraints

=4X_DIELECTRIC

* ?

TBTDP_2OTHER

TBTDP_TXRX

?*

=6X_DIELECTRIC

?

TBTDP_2SAME

*

=3X_DIELECTRIC

?

*

=2x_DIELECTRICTBT_SPI

TBTDP_85D

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

*

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

TBTDP_TXRX

TBTDP_D2RTBTDP_R2D

*

TBTDP_2OTHER

TBTDP_*

**

=6X_DIELECTRIC

?

TOP,BOTTOM

TBTDP_2OTHER

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

* =85_OHM_DIFF =85_OHM_DIFF

TBTDP_85D

TOP,BOTTOM

TBTDP_2SAME

?

=4x_DIELECTRIC

TBTDP_*

=SAME

*

TBTDP_2SAME

=10X_DIELECTRIC

TBTDP_TXRX TOP,BOTTOM

?

=45_OHM_SE =45_OHM_SE=45_OHM_SE=45_OHM_SE

TBT_SPI_45S

* =STANDARD=STANDARD

TBTDP_R2D

TBT_A_R2D_N<1..0>

TBT_A_R2D TBTDP_85D

TBT_A_R2D

TBT_A_R2D_P<1..0>

TBTDP_R2DTBTDP_85D

DP_85D

DP_TBTPA_AUXCH_P

TBT_A_AUXCH

DP_85D

DP_TBTPA_AUXCH_C_N

TBT_A_AUXCH

TBTDP_85D TBTDP_D2R

TBT_A_D2R_P<0>

TBT_A_D2R0

TBTDP_85D

TBT_A_D2R_C_N<0>

TBT_A_D2R0

TBTDP_D2R

DP_TBTPA_ML_N<3>

DISPLAYPORT

DP_85D

DP_TBTPA_ML

DP_85D

DISPLAYPORTDP_TBTPA_ML

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_N<1>

DISPLAYPORT

DP_85D

DP_A_LSX_ML

TBTDP_R2D

TBT_A_R2D_C_N<1..0>

TBT_A_R2D TBTDP_85D

DP_TBTPA_ML_P<1>

DISPLAYPORT

DP_85D

DP_A_LSX_ML

DP_TBTPA_ML_N<1>

DP_85D

DISPLAYPORTDP_A_LSX_ML

DP_A_LSX_ML_P<1>

DP_85D

DISPLAYPORTDP_A_LSX_ML

DP_TBTPA_ML_C_P<1>

DP_85D

DISPLAYPORTDP_A_LSX_ML

TBTDP_R2D

TBT_A_R2D_C_P<1..0>

TBT_A_R2D TBTDP_85D

DP_85D

DISPLAYPORTDP_TBTPA_ML

DP_TBTPA_ML_C_P<3>

TBTDP_D2RTBTDP_85D

TBT_A_D2R_C_P<1>

TBT_A_D2R1

DP_85D

DP_TBTPA_AUXCH_C_P

TBT_A_AUXCH

TBTDP_D2R

TBT_A_D2R1_AUXDDC_N

TBTDP_85D

TBT_A_D2R1

TBTDP_D2R

TBT_A_D2R1_AUXDDC_P

TBT_A_D2R1

TBTDP_85D

TBTDP_D2R

TBT_A_D2R_N<1>

TBT_A_D2R1

TBTDP_85D

TBTDP_D2RTBTDP_85D

TBT_A_D2R_C_N<1>

TBT_A_D2R1

DISPLAYPORT

DP_TBTSRC_ML_C_P<3..0>

DP_85D

DP_TBTSRC_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_TBTSRC_AUXCH_C_P

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_TBTSRC_AUXCH_C_N

DP_85D

TBT_SPI

TBT_SPI_CLK

TBT_SPI_CLK TBT_SPI_45S

TBT_SPI_MOSI

TBT_SPI

TBT_SPI_45S

TBT_SPI

TBT_SPI_CS_L

TBT_SPI_45S

TBT_SPI_MISO

TBT_SPI

TBT_SPI_45S

TBT_A_D2R_P<1>

TBTDP_D2RTBTDP_85D

TBT_A_D2R1

TBTDP_85D TBTDP_D2R

TBT_A_D2R_N<0>

TBT_A_D2R0

TBT_A_D2R_C_P<0>

TBTDP_D2RTBTDP_85D

TBT_A_D2R0

DP_85D

DISPLAYPORT

DP_A_LSX_ML_N<1>

DP_A_LSX_ML

DP_TBTPB_ML_C_N<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

DP_TBTPB_ML_P<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

DP_TBTPB_ML_N<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

DP_B_LSX_ML_P<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

DP_B_LSX_ML_N<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML DP_TBTPB_ML

DP_TBTPB_ML_C_P<3>

DISPLAYPORT

DP_85D

DP_TBTPB_ML

DP_TBTPB_ML_C_N<3>

DISPLAYPORT

DP_85D

DP_TBTPB_ML

DP_TBTPB_ML_P<3>

DISPLAYPORT

DP_85D

TBT_B_D2R0

TBT_B_D2R_C_P<0>

TBTDP_85D TBTDP_D2R

DP_TBTPB_ML

DP_TBTPB_ML_N<3>

DISPLAYPORT

DP_85D

TBT_B_D2R0

TBT_B_D2R_P<0>

TBTDP_D2RTBTDP_85D

TBT_B_D2R0

TBT_B_D2R_N<0>

TBTDP_D2RTBTDP_85D

TBT_B_D2R1

TBT_B_D2R_C_N<1>

TBTDP_85D TBTDP_D2R

TBT_B_D2R1

TBT_B_D2R_C_P<1>

TBTDP_85D TBTDP_D2R

TBT_B_R2D

TBT_B_R2D_C_N<1..0>

TBTDP_R2DTBTDP_85D

TBT_B_D2R1

TBT_B_D2R_P<1>

TBTDP_D2RTBTDP_85D

TBT_B_D2R1

TBT_B_D2R_N<1>

TBTDP_D2RTBTDP_85D

TBT_B_D2R1

TBT_B_D2R1_AUXDDC_P

TBTDP_85D TBTDP_D2R

TBT_B_D2R1

TBT_B_D2R1_AUXDDC_N

TBTDP_85D TBTDP_D2R

TBT_B_AUXCH

DP_TBTPB_AUXCH_C_P

DP_85D

TBT_B_AUXCH

DP_TBTPB_AUXCH_C_N

DP_85D

TBT_B_AUXCH

DP_TBTPB_AUXCH_P

DP_85D

TBT_B_AUXCH

DP_TBTPB_AUXCH_N

DP_85D

DP_TBTPB_ML_C_P<1>

DISPLAYPORT

DP_85D

DP_B_LSX_ML

TBT_B_R2D

TBT_B_R2D_P<1..0>

TBTDP_R2DTBTDP_85D

TBT_B_D2R0

TBT_B_D2R_C_N<0>

TBTDP_85D TBTDP_D2R

TBT_B_R2D

TBT_B_R2D_N<1..0>

TBTDP_R2DTBTDP_85D

TBT_B_R2D

TBT_B_R2D_C_P<1..0>

TBTDP_R2DTBTDP_85D

DP_85D

DP_TBTPA_AUXCH_N

TBT_A_AUXCH

DISPLAYPORT

DP_85D

DP_TBTPA_ML

DP_TBTPA_ML_P<3>

<SCH_NUM>

115 OF 118

78 OF 81

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31

28 31

31

28 31

28 31 72

28 31

31

28 31

31

28 31 72

31

28

28 31 72

28 31

31

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32

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32

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32

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http://sualaptop365.edu.vn

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Memory Bus Constraints

NET_TYPE

PHYSICAL

SPACING

Memory to GND Spacing

Memory to Power Spacing

Spacing Rule Sets

ELECTRICAL_CONSTRAINT_SET

MIPI Interface Constraints

Memory Bus Spacing Group Assignments

Camera Net Properties

I101

I102

I103 I104

I106

I107

I108

I109

I110

I127

I128

I129 I130

I131

I132

I133

I134

I145 I146

I147

I148

I149

Camera Constraints

SYNC_MASTER=SIDLE_J45

SYNC_DATE=12/10/2012

S2_MEM_DQS1

S2_DQS2OWNDATA

S2_MEM_DATA1

*

S2MEM_2OTHER

* ?

=6x_DIELECTRIC

?*

S2MEM_2GND

=2x_DIELECTRIC

MIPI_2OTHER

?

*

=4X_DIELECTRIC

MIPI_2CLK

*

=6X_DIELECTRIC

?

MIPICLK_2OTHER

*

=7X_DIELECTRIC

?

* *

MIPI_2OTHER

MIPI_DATA

*

MIPI_2CLK

CLK_MIPI

MIPI_DATA

*

CLK_MIPI

*

MIPICLK_2OTHER

=45_OHM_SE

=STANDARD

=45_OHM_SE

=STANDARD

=45_OHM_SE

*

S2_MEM_45S =45_OHM_SE

* =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

S2_MEM_85D

*

MIPI_85D

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

GND

S2MEM_2GND

S2_MEM_*

*

S2_2OTHERMEM

*

S2_MEM_*S2_MEM_*

S2_MEM_CTRL S2_MEM_CTRL

S2_CTRL2CTRL

*

S2_MEM_CMD

S2_CMD2CMD

S2_MEM_CMD

*

S2_MEM_CLK

*

S2MEM_2OTHER

*

S2MEM_2OTHER

S2_MEM_CTRL

* *

S2MEM_2OTHER

**

S2_MEM_CMD

S2_MEM_DQS0

S2_DQS2OWNDATA

S2_MEM_DATA0

*

S2_MEM_PWR

**

DEFAULT

S2MEM_2PWR

S2_MEM_*

S2_MEM_PWR

*

=SAME

*

S2_DATA2SELF

S2_MEM_DATA*

S2MEM_2OTHERS2_MEM_DATA*

* *

S2_MEM_DQS*

**

S2MEM_2OTHER

S2_MEM_CMD

S2_MEM_CTRL

S2_CMD2CTRL

*

=2x_DIELECTRIC

S2_DATA2SELF

?*

=2x_DIELECTRIC

S2MEM_2PWR

=2x_DIELECTRIC

?*

S2_DQS2OWNDATA

S2_2OTHERMEM

=4x_DIELECTRIC

* ?

S2_CMD2CTRL

=2x_DIELECTRIC

?*

S2_CTRL2CTRL

=2x_DIELECTRIC

?*

S2_CMD2CMD

=4x_DIELECTRIC

TOP,BOTTOM

?

S2_CTRL2CTRL

S2MEM_2GND TOP,BOTTOM

=4x_DIELECTRIC

?

S2_2OTHERMEM

?

=6x_DIELECTRIC

TOP,BOTTOM

=4x_DIELECTRIC

TOP,BOTTOM

?

S2_CMD2CMD

TOP,BOTTOM

?

S2_DQS2OWNDATA =4x_DIELECTRIC

TOP,BOTTOM

=4x_DIELECTRIC

?

S2_DATA2SELF

MIPI_2OTHER

TOP,BOTTOM

?

=6X_DIELECTRIC

TOP,BOTTOM

?

=8X_DIELECTRIC

MIPI_2CLK

?

TOP,BOTTOM

=10X_DIELECTRIC

MIPICLK_2OTHER

TOP,BOTTOM

?

S2_CMD2CTRL

=4x_DIELECTRIC

S2MEM_2PWR?TOP,BOTTOM

S2MEM_2OTHER

?

=10x_DIELECTRIC

TOP,BOTTOM

MIPI_DATA_S2

MIPI_DATA

MIPI_DATA_P

MIPI_85D

MIPI_DATA_N

MIPI_DATA

MIPI_DATA_S2 MIPI_85D

MIPI_DATA_CONN_P

MIPI_DATA

MIPI_85D

MIPI_DATA_CONN_N

MIPI_DATA

MIPI_85D

S2_MEM_85D

S2_MEM_DQS1S2_MEM_DQS1

MEM_CAM_DQS_P<1>

S2_MEM_DATA1

S2_MEM_45S

S2_MEM_DATA_1

MEM_CAM_DQ<15..8>

PP0V675_MEM_CAM_VREFCA

S2_MEM_PWR

CLK_MIPI

MIPI_CLK_N

MIPI_CLK_S2

MIPI_85D

MEM_CAM_BA<2>

S2_MEM_45SS2_MEM_CMD S2_MEM_CMD

S2_MEM_CMDS2_MEM_CMD S2_MEM_45S

MEM_CAM_BA<0>

S2_MEM_45S

S2_MEM_CTRLS2_MEM_CNTL

MEM_CAM_CS_L

S2_MEM_CLK S2_MEM_85D S2_MEM_CLK

MEM_CAM_CLK_N

MIPI_CLK_P

CLK_MIPI

MIPI_CLK_S2

MIPI_85D

S2_MEM_CTRL

S2_MEM_45SS2_MEM_CMD

MEM_CAM_RAS_L

S2_MEM_CTRL

MEM_CAM_CKE

S2_MEM_45S

S2_MEM_CNTL

S2_MEM_45S

S2_MEM_CTRL

S2_MEM_CMD

MEM_CAM_CAS_L

S2_MEM_CTRL

S2_MEM_45S

MEM_CAM_ODT

S2_MEM_CLK S2_MEM_CLKS2_MEM_85D

MEM_CAM_CLK_P

MIPI_CLK_CONN_N

MIPI_85D CLK_MIPI

S2_MEM_CMD

MEM_CAM_BA<1>

S2_MEM_CMD S2_MEM_45S

PP0V675_CAM_VREF

S2_MEM_PWR

S2_MEM_CMD

S2_MEM_A

S2_MEM_45S

MEM_CAM_A<14..0>

MEM_CAM_DQS_P<0>

S2_MEM_DQS0

S2_MEM_85D

S2_MEM_DQS0

CLK_MIPI

MIPI_CLK_CONN_P

MIPI_85D

PP0V675_MEM_CAM_VREFDQ

S2_MEM_PWR

PP1V35_CAM

S2_MEM_DATA0

S2_MEM_45S

S2_MEM_DATA_0

MEM_CAM_DQ<7..0>

S2_MEM_85D

S2_MEM_DQS1S2_MEM_DQS1

MEM_CAM_DQS_N<1>

S2_MEM_CMDS2_MEM_45S

MEM_CAM_WE_L

S2_MEM_CMD

S2_MEM_DATA0

S2_MEM_DATA_0

S2_MEM_45S

MEM_CAM_DM<0>

S2_MEM_DQS0

S2_MEM_85D

S2_MEM_DQS0

MEM_CAM_DQS_N<0>

S2_MEM_45S

S2_MEM_DATA_1

S2_MEM_DATA1

MEM_CAM_DM<1>

<SCH_NUM>

116 OF 118

79 OF 81

36 37

37 71

36 37

37

36 37

37

36 37

37 71

36 37

37 71

37

36 37

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NET_TYPE

PHYSICAL

NET_TYPE

SMBus Charger Net Properties

SPACING

ELECTRICAL_CONSTRAINT_SET

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMC Constraints

SYNC_MASTER=SIDLE_J45

SYNC_DATE=12/10/2012

SMB_45S

SMBUS_SMC_2_S3_SCL

SMB

SMBUS_SMC_2_S3_SCL

SMB_45S

SMB

SMBUS_SMC_1_S0_SCL

SMB_45S

SMBUS_SMC_1_S0_SDA

SMB

SMBUS_SMC_1_S0_SDA

SMB_45S

SMB

SMBUS_SMC_5_SDA

SMBUS_SMC_5_G3_SDA

SMB_45S

SMB

SMBUS_SMC_3_SCL

NC_SMBUS_SMC_3_SCL

SMB_45S

SMB

SMBUS_SMC_3_SDA

NC_SMBUS_SMC_3_SDA

SMB_45S

SMBUS_SMC_0_S0_SCL

SMB

SMB_45S

SMBUS_SMC_2_S3_SDA

SMB

SMBUS_SMC_2_S3_SDA

SMB_45S

SMB

SMBUS_SMC_0_S0_SDA

SMB_45S

SMB

SMBUS_SMC_5_SCL

SMBUS_SMC_5_g3_SCL

1TO1_DIFFPAIR

CHGR_CSI_N

1TO1_DIFFPAIR

CHGR_CSI

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSO

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO_N

<SCH_NUM>

117 OF 118

80 OF 81

39 41 44 71

41 44 48

41 44 56 57 71

41 43

37 41 44 48 71

39 41 44 71

37 41 44 48 71

41 44 56 57 71

57

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http://sualaptop365.edu.vn

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PHYSICAL

NET_TYPE

SPACING

NET_TYPE

PHYSICAL

SPACING

J15 Specific Net Properties

ELECTRICAL_CONSTRAINT_SETELECTRICAL_CONSTRAINT_SET

J15 Specific Net Properties

I357

I358

I359

I360

I361 I362

I405 I406

I407

I408

I419

I420

I421

I422

I423

I424

I425

I426

I429 I430

I431 I432

I433 I434

I435

I436

I440

I441 I442

I445

I446

I447

I448

I449 I450

I451

I452 I453

I454

I455

I456 I457

I458

I459

I460

I461

I462

I463

I480 I481

I482 I483

I484

I485 I486

I487

I488

I489

I490

I491

I492

I493

I494

I495

I498

I499

I502

I503

I510

I511

I514 I515

I516

I517

I518

I519

SYNC_MASTER=SIDLE_J45

Project Specific Constraints

SYNC_DATE=12/10/2012

PCIE_85D

0.09 MM

*

10 MM

SATA_*

PWR_P2MM

*

SB_POWER

MEM_37S 100 MIL0.09 MM

*

GND_P2MMCPU_COMP

*

GND

GND_P2MM

CPU_VCCSENSE

*

GND

0.1 MM

TOP

USB3_85D

500 MIL

DP_85D

0.090 MM

ISL9 0.075 MM

=2X_DIELECTRIC

?

*

AUDIO

*

1TO1_DIFFPAIR

1:1_DIFFPAIR

100 MILMEM_40S 0.09 MM

*

USB3_85D

ISL10

0.090 MM

0.075 MM

GND

*

PCIE_*

GND_P2MM

PCIE_85D

ISL10

0.075 MM

0.090 MM

=2X_DIELECTRIC

THERM

*

?

USB

SB_POWER

*

PWR_P2MM

CLK_PCIE SB_POWER PWR_P2MM

*

GND_P2MM

USB GND

*

=STANDARD

*

?

GND

=2X_DIELECTRIC

*

?

SENSE

=1:1_DIFFPAIR

0.1 MM 0.1 MM

10 MM

0.1 MM

*

AUDIODIFF

0.1 MM

SENSE_1TO1_50S

=50_OHM_SE=50_OHM_SE=50_OHM_SE

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR

DIFFPAIR

=1:1_DIFFPAIR

*

=1:1_DIFFPAIR

500 MILUSB_85D

TOP

0.1 MM

=1:1_DIFFPAIR =1:1_DIFFPAIR

=45_OHM_SE=45_OHM_SE=45_OHM_SE

SENSE_1TO1_45S

=1:1_DIFFPAIR

*

=45_OHM_SE=45_OHM_SE=45_OHM_SE

THERM_1TO1_45S

*

=1:1_DIFFPAIR=1:1_DIFFPAIR

=1:1_DIFFPAIR

0.2 MM

THERM_45S_CPUVRISNS1 =45_OHM_SE=45_OHM_SE=45_OHM_SE

=1:1_DIFFPAIR

0.2 MM

*

100 MIL0.09 MM

*

MEM_72D

100 MIL0.23 MM

BOTTOM

CPU_27P4S

MEM_85D 100 MIL0.09 MM

*

PWR_P2MM

*

1000

0.20 MM

1000

0.20 MM

*

GND_P2MM

*

GND_P2MM

GND

SATA_*

*

GND

CLK_PCIE GND_P2MM

=50_OHM_SE=50_OHM_SE=50_OHM_SE

THERM_1TO1_50S

*

=1:1_DIFFPAIR

=1:1_DIFFPAIR=1:1_DIFFPAIR

ISNS_AIRPORT_R_N

SENSE_1TO1_45S

SENSE

AUDIO_DIFFPAIR

AUDIO

DIFFPAIR

AUD_MIC_IN1_R_N

AUD_MIC_IN1_L_P

DIFFPAIR

AUDIO

AUDIO_DIFFPAIR

DIFFPAIR

AUD_CONN_HS_MIC_P

AUDIO

DIFFPAIR

AUD_CONN_HS_MIC_N

AUDIO

AUDIODIFF

AUD_LO3_R_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO3_L_N

AUDIO

DIFFPAIR

AUDIO

HS_MIC_N

DIFFPAIR

HS_MIC_P

AUDIO

AUD_HS_MIC_N

DIFFPAIR

AUDIO

AUD_SPKRAMP_LIN_N

AUDIODIFF AUDIODIFF

AUDIO

SPKRAMP_RIN_P

AUDIO_DIFFPAIR

AUDIO

SPKRCONN_SL_OUT_P

DIFFPAIR

SPKRCONN_SR_OUT_N

DIFFPAIR

AUDIO

AUDIO_DIFFPAIR

SENSE_1TO1_45S

CPUVR_ISNS_P

SENSE

SENSE_1TO1_45S

SENSE

CPUVR_ISNS_N

CPUTHMSNS_D2_P

THERM_1TO1_45S

THERM

SENSE_DIFFPAIR

ISNS_LCD_PANEL_P

THERM_1TO1_45SSENSE_DIFFPAIR

THERM

CPUTHMSNS_D2_N

SENSE_DIFFPAIR THERM_1TO1_45S

THERM

THERM_1TO1_45S

ISNS_CPUDDR_N

THERM

SENSE_DIFFPAIR

THERM_1TO1_45S

THERM

SENSE_DIFFPAIR

ISNS_CPUDDR_P

AUDIODIFF

AUDIO

AUD_LO3_R_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO3_L_P

AUDIO

SPKRAMP_LIN_N

AUDIO

AUDIODIFF

DIFFPAIR

SPKRCONN_SL_OUT_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_SPKRAMP_RIN_N

AUDIO_DIFFPAIR

AUD_LO2_R_N

AUDIO

AUDIODIFF

AUD_SPKRAMP_RSUBIN_N

AUDIO

AUDIODIFF

AUDIO

AUDIODIFF

AUD_SPKRAMP_LSUBIN_P

RSUBIN_P

AUDIO

AUDIODIFF

SPKRAMP_LIN_P

AUDIO

AUDIODIFF

AUDIO

AUDIODIFF

AUD_SPKRAMP_RIN_P

THERM_1TO1_45S

THERM

P1V05S0_SENSE_N

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO2_L_N

AUDIO

SB_POWER

PP3V3_S5 PP3V3_S0

SB_POWER

AUDIODIFF

CHGR_CSO_R_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_SPKRAMP_LIN_P

AUDIO

AUDIODIFF

AUD_SPKRAMP_LSUBIN_N

AUDIODIFF

SPKRAMP_RIN_N

AUDIO

AUDIODIFF

CHGR_CSI_R_N

AUDIO

AUD_SPKRAMP_RSUBIN_P

AUDIO

AUDIODIFF

ISNS_LCD_PANEL_N

THERM_1TO1_45S

THERM

SENSE_DIFFPAIR

THERM_1TO1_45S

TBT_THERMD_N

THERM

THERM_1TO1_45S

P1V05S0_SENSE_P

SENSE_DIFFPAIR

THERM

THERM_1TO1_45S

THERM

ISNS_SSD_N

THERM_1TO1_45S

ISNS_SSD_R_N

THERM

THERM_1TO1_45S

THERM

SENSE_DIFFPAIR

ISNS_SSD_R_P

THERM_1TO1_45S

ISNS_SSD_P

THERM

SENSE_DIFFPAIR

THERM_1TO1_45S

P1V05S0_CS_N

THERM

AUDIODIFF

ISNS_TBT_R_N

AUDIO

THERM_1TO1_45S

P1V05_GPU_PEX_IOVDD_SNS_P

SENSE_DIFFPAIR

THERM

AUDIO_DIFFPAIR

DIFFPAIR

AUD_MIC_IN1_R_P

AUDIO

AUDIO_DIFFPAIR

SPKRCONN_R_OUT_N

AUDIO

DIFFPAIR

AUDIO_DIFFPAIR

SPKRCONN_SR_OUT_P

AUDIO

DIFFPAIR

PP1V35_S3RS0_CPUDDR

SB_POWER

AUDIODIFF

CHGR_CSI_R_P

AUDIO_DIFFPAIR

AUDIO

THERM_1TO1_45S

TBT_THERMD_P

SENSE_DIFFPAIR

THERM

THERM_45S_CPUVRISNS1

CPUVR_ISNS1_N

SENSE_DIFFPAIR

THERM

SENSE_1TO1_45S

ISNS_S2_N

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_45S

ISNS_S2_P

SENSE_DIFFPAIR

SENSE

THERM_1TO1_45S

P1V05_GPU_PEX_IOVDD_SNS_N

THERM

SENSE_DIFFPAIR

SENSE_1TO1_45S

SENSE

ISNS_HS_COMPUTING_N

SENSE_DIFFPAIR

AUDIODIFF

ISNS_TBT_R_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

ISNS_TBT_P

CODEC_HS_MIC_P

DIFFPAIR

AUDIO_DIFFPAIR

AUDIO

AUDIO_DIFFPAIR

CODEC_HS_MIC_N

DIFFPAIR

AUDIO

DDR3THMSNS_D1_P

THERM_1TO1_45S

THERM

SENSE_DIFFPAIR

ISNS_LCDBKLT_P

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

ISNS_HS_OTHER3V3_N

SENSE_DIFFPAIR

THERM_45S_CPUVRISNS1

CPUVR_ISNS1_P

THERM

ISNS_AIRPORT_R_P

SENSE_1TO1_45S

SENSE

SENSE_1TO1_45S

ISNS_AIRPORT_P

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_45S

ISNS_S2_R_P

SENSE_DIFFPAIR

SENSE

AUDIODIFF

ISNS_TBT_N

AUDIO_DIFFPAIR

AUDIO

THERM_1TO1_45SSENSE_DIFFPAIR

THERM

GFXIMVP_ISNS1_N

ISNS_LCDBKLT_N

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

AUDIO_DIFFPAIR

AUD_LO2_R_P

AUDIODIFF

AUDIO

AUD_MIC_IN1_L_N

DIFFPAIR

AUDIO

DIFFPAIR

AUD_HS_MIC_P

AUDIO

DIFFPAIR

AUDIO_DIFFPAIR

AUDIO

SPKRCONN_R_OUT_P

DIFFPAIR

SPKRCONN_L_OUT_N

AUDIO

AUDIO_DIFFPAIR

LSUBIN_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

DIFFPAIR

SPKRCONN_L_OUT_P

AUDIO

RSUBIN_N

AUDIODIFF

LSUBIN_P

AUDIO

AUDIODIFF

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

ISNS_HS_OTHER5V_N

AUDIODIFF

AUD_LO2_L_P

AUDIO_DIFFPAIR

AUDIO

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

ISNS_HS_COMPUTING_P

DDR3THMSNS_D1_N

THERM_1TO1_45SSENSE_DIFFPAIR

THERM

THERM_1TO1_45S

FINTHMSNS_D_P

THERM

SENSE_DIFFPAIR

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

ISNS_HS_OTHER3V3_P

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

ISNS_HS_OTHER5V_P

SENSE_1TO1_45S

ISNS_1V35_MEM_R_N

SENSE

SENSE_1TO1_45S

ISNS_1V35_MEM_R_P

SENSE

SENSE_1TO1_45S

ISNS_1V35_MEM_N

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_45S

ISNS_AIRPORT_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_1V35_MEM_P

SENSE

SENSE_DIFFPAIR

THERM_1TO1_45SSENSE_DIFFPAIR

THERM

FINTHMSNS_D_N

THERM_1TO1_45S

THERM

ISNS_CPU_DDR_R_N

THERM_1TO1_45S

ISNS_CPU_DDR_R_P

THERM

AUDIODIFF

CHGR_CSO_R_N

AUDIO

THERM_1TO1_45S

P1V05S0_CS_P

SENSE_DIFFPAIR

THERM

THERM_1TO1_45S

GFXIMVP_ISNS1_P

SENSE_DIFFPAIR

THERM

THERM_1TO1_45S

CPUVR_ISUM_R_N

SENSE_DIFFPAIR

THERM

SENSE_1TO1_45S

ISNS_S2_R_N

SENSE_DIFFPAIR

SENSE

THERM_1TO1_45S

GFXIMVP_ISNS1_P

THERM

SENSE_DIFFPAIR

THERM

CPUVR_ISNS3_P

THERM_45S_CPUVRISNS1

SENSE_DIFFPAIR

CPUVR_ISNS2_N

THERM

THERM_45S_CPUVRISNS1

SENSE_DIFFPAIR

THERM

CPUVR_ISNS3_N

THERM_45S_CPUVRISNS1

SENSE_DIFFPAIR

THERM_1TO1_45S

CPUVR_ISUM_R_P

THERM

SENSE_DIFFPAIR

THERM_1TO1_45S

GFXIMVP_ISNS1_N

SENSE_DIFFPAIR

THERM

CPUVR_ISNS2_P

THERM_45S_CPUVRISNS1

SENSE_DIFFPAIR

GND

<SCH_NUM>

118 OF 118

81 OF 81

47

51 53

51 54

54 55

53

53 55 71

46

48

47

48

47

51 53

53

53 55 71

53

51 53

53

62

51 53

12 14 15 17 18 19 21 31 32 34 61 64 65 66 69 70 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

65 66 67

69 71

57

53

57

53

47

48

62

46

62

46

53 55 71

6 8

10 21 65 66 69

57

28 48

46 59

45

46

51

48

47 63

45

46 59

47

46

81

47 63

51 53

54 55

53 55 71

53

53 55 71

53

45

51 53

45

48

45

46

48

47

57

62

81

46

47

81

46 59

46

81

46 59

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Apple MacBook Pro A1398 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual