Apple Macbook Pro A1286 Schematics

DRAWING

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

APPLE INC.

6

DESIGNER

DESCRI PTION O F CHAN GE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

TITLE

DRAWING N UMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/ FINISH

NOTED AS

APPLICABL E

SIZE

D

THIRD ANG LE PROJECT ION

DIMENSION S ARE IN M ILLIMETER S

XX

X.XX

X.XXX

DO NOT SC ALE DRAWIN G

REV

ZONE

ECN

CK APPD

DATE

ENG APPD

DATE

1. ALL RESIST ANCE V ALUES A RE IN OHMS, 0 .1 WAT T +/- 5 %.

2. ALL CAPACI TANCE VALUES ARE IN MICROF ARADS.

3. ALL CRYSTA LS & O SCILLAT OR VAL UES ARE IN HE RTZ.

ANGLES

Schematic / PCB #'s

08/18/2008

SCHEM,MBP 15"MLB

M98 SMBus Connections

45

DDR

07/22/20 08

52

LPC+SPI Debug Connector

44

CHANG_M9 8_MLB

07/01/20 08

51

SMC Support

43

AMASON_M 98_MLB

06/18/20 08

50

SMC

42

T18_MLB

06/18/20 08

49

Front Flex Support

41

CHANG_M9 8_MLB

07/01/20 08

48

External USB Connectors

40

AMASON_M 98_MLB

07/02/20 08

46

SATA Connectors

39

CHANG_M9 8_MLB

07/01/20 08

45

FireWire Ports

38

SENSOR

08/14/20 08

43

FireWire Port Power

37

SENSOR

08/14/20 08

42

FireWire LLC/PHY (FW643)

36

SENSOR

08/14/20 08

41

Ethernet Connector

35

SUMA_M98 _MLB

07/01/20 08

39

Ethernet & AirPort Support

34

SUMA_M98 _MLB

07/01/20 08

38

Ethernet PHY (RTL8211CL)

33

SUMA_M98 _MLB

07/01/20 08

37

ExpressCard Connector

32

YITE_M98 _MLB

07/02/20 08

35

Right Clutch Connector

31

YITE_M98 _MLB

07/02/20 08

34

DDR3 Support

30

T18_MLB

06/18/20 08

33

DDR3 SO-DIMM Connector B

29

DDR

07/22/20 08

32

DDR3 SO-DIMM Connector A

28

DDR

07/22/20 08

31

FSB/DDR3/FRAMEBUF Vref Margining

27

DDR

07/22/20 08

29

SB Misc

26

T18_MLB

12/17/20 07

28

MCP Graphics Support

25

AMASON_M 98_MLB

06/18/20 08

26

MCP Standard Decoupling

24

T18_MLB

06/18/20 08

25

MCP79 A01 Silicon Support

23

T18_MLB

03/31/20 08

24

MCP Power & Ground

22

T18_MLB

06/18/20 08

22

MCP HDA & MISC

21

T18_MLB

06/18/20 08

21

MCP SATA & USB

20

T18_MLB

06/18/20 08

20

MCP PCI & LPC

19

T18_MLB

06/18/20 08

19

MCP Ethernet & Graphics

18

T18_MLB

06/18/20 08

18

MCP PCIe Interfaces

17

T18_MLB

06/18/20 08

17

MCP Memory Misc

16

T18_MLB

06/18/20 08

16

MCP Memory Interface

15

T18_MLB

06/18/20 08

15

MCP CPU Interface

14

T18_MLB

06/18/20 08

14

eXtended Debug Port(MiniXDP)

13

M99_MLB

01/08/20 08

13

CPU Decoupling & VID

12

M87_MLB

10/17/20 07

12

CPU Power & Ground

11

M87_MLB

10/17/20 07

11

CPU FSB

10

M87_MLB

10/17/20 07

10

Signal Aliases

9

(MASTER)

9

Power Aliases

8

(MASTER)

8

Functional / ICT Test

7

N/A

N/A7

JTAG Scan Chain

6

DDR

07/22/20 08

6

BOM Configuration

5

N/A

N/A5

Power Block Diagram

4

N/A

N/A4

Power Block Diagram

3

T18_MLB

12/12/20 07

3

System Block Diagram

2

T18_MLB

12/12/20 07

2

MUXGFX

02/18/20 08

90

103

MCP Constraints 2

MUXGFX

02/18/20 08

89

102

MCP Constraints 1

MUXGFX

02/18/20 08

88

101

Memory Constraints

MUXGFX

02/18/20 08

87

100

CPU/FSB Constraints

MUXGFX

02/01/20 08

86

99

Misc Power Supplies

YITE_M98 _MLB

07/02/20 08

85

98

LCD Backlight Support

YITE_M98 _MLB

07/02/20 08

84

97

LCD BACKLIGHT DRIVER

MUXGFX

07/10/20 08

83

96

Graphics MUX (GMUX)

MUXGFX

07/10/20 08

82

95

1.1V / 1V8 FB Power Supply

MUXGFX

07/10/20 08

81

94

DisplayPort Connector

MUXGFX

07/10/20 08

80

93

Muxed Graphics Support

MUXGFX

02/25/20 08

79

90

LVDS Display Connector

M87_MLB

10/17/20 07

78

89

GPU (G84M) Core Supply

MUXGFX

07/10/20 08

77

88

NV G96 Video Interfaces

MUXGFX

07/09/20 08

76

87

G96 GPIOs & Straps

MUXGFX

07/10/20 08

75

86

NV G96 GPIO/MIO/Misc

MUXGFX

07/10/20 08

74

85

GDDR3 Frame Buffer B (Top)

MUXGFX

07/10/20 08

73

84

GDDR3 Frame Buffer A (Top)

MUXGFX

07/10/20 08

72

82

NV G96 Frame Buffer I/F

MUXGFX

07/10/20 08

71

81

NV G96 Core/FB Power

MUXGFX

07/10/20 08

70

80

NV G96 PCI-E

PWRSQNC

05/12/20 08

69

79

Power FETs

PWRSQNC

05/12/20 08

68

78

Power Control

M99_MLB

12/14/20 07

67

77

Misc Power Supplies

M99_MLB

12/14/20 07

66

76

CPU VTT Power Supply

M99_MLB

01/08/20 08

65

75

1.05V / MCP Core Regulator

M99_MLB

12/13/20 07

64

73

1.5V DDR3 Supply

M99_MLB

01/09/20 08

63

72

5V / 3.3V Power Supply

M87_MLB

10/17/20 07

62

71

IMVP6 CPU VCore Regulator

M99_MLB

12/10/20 07

61

70

PBus Supply & Battery Charger

T18_MLB

12/06/20 07

60

69

DC-In & Battery Connectors

AUDIO

07/09/20 08

59

68

AUDIO: JACK TRANSLATORS

AUDIO

07/09/20 08

58

67

AUDIO: JACKS

AUDIO

07/09/20 08

57

66

AUDIO:SPEAKER AMP

AUDIO

07/09/20 08

56

65

AUDIO: HEADPHONE AMP

AUDIO

07/09/20 08

55

63

AUDIO: LINE IN

AUDIO

07/09/20 08

54

62

AUDIO:CODEC

CHANG_M9 8_MLB

07/01/20 08

53

61

SPI ROM

SENSOR

08/14/20 08

52

59

Sudden Motion Sensor (SMS)

PWRSQNC

05/12/20 08

51

58

WELLSPRING 2

AMASON_M 98_MLB

06/18/20 08

50

57

WELLSPRING 1

M87_MLB

10/17/20 07

49

56

Fan Connectors

SENSOR

08/14/20 08

48

55

Thermal Sensors

SENSOR

08/14/20 08

47

54

Current Sensing

96

109

PCB Rule Definitions

M99_MLB

01/22/20 08

95

108

Project Specific Constraints

MUXGFX

02/21/20 08

94

107

GPU (G96) Constraints

MUXGFX

02/18/20 08

93

106

SMC Constraints

MUXGFX

02/18/20 08

92

105

FireWire Constraints

MUXGFX

02/18/20 08

SENSOR

08/14/20 08

46

53

Current & Voltage Sensing

CRITIC AL051-75 46

1

SCH

SCHEM, FIBBO, M98

Contents Sync

Date

(.csa)

Page

Table of Contents

1

N/A

N/A1

TITLE=ML B

ABBREV=D RAWING

91

104

Ethernet Constraints

MUXGFX

02/18/20 08

Contents Sync

(.csa)

Date

Page

CRITIC AL820-23 30

1

PCBF,F IBBO,M 98

PCB

Contents

(.csa)

Sync

Date

Page

A.0.0

SCHEM,MBP 15MLB

?

1

? ?

96

051-7546

LAST_MODI FIED=Mon Aug 18 01 :48:34 20 08

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

J9400

DISPLA Y PORT

J9000

CONN

LVDS

PG 71

CONN

PG 71

Conn

J4520

PG 17

(UP TO 1 2 DEVICE S)

4

TMDS OUT

Line O ut

2

CTRL

IR

J4710

CLK

SATA

(UP TO F OUR PORT S)

Conns

J6800,6801 ,6802,6803

PG 41

MCP79

PG 19

PCI

PG 19

LPC

3 8 9

PG 40

SATA

U6301 U6500U6400

PG 59

PG 56PG 55

HEADPH ONE

Audio

Codec

FSB

64-Bit

2 UDIMMs

XDP CONN

POWER SUPPLY

PG 28

J3400 U3900

PG 33

Conn

88E111 6

PG 31

GB

E-NET

Amp

Speake r

Amps

PG 54

PG 53

U6200

J4720

PG 57

J4710

U4900

J6950

PG 12

U1000

U1300

J4510

U6600,6605 ,6610,6620

PG 40

J4700

PG 40

HD

E-NET

ODD

Conn

SYNTH

PG 39

U6100

J3900,4635 ,4655

EXTERNAL

USB

PG 40

KEYBOARD

TRACKPAD/

USB

PG 45

POWER SENSE

J5650,5600 ,5610,5611, 5660,5720,5 730,5750

PG 48,49

J4900

DC/BATT

PENRYN

2.X OR 3.X GH Z

INTEL CPU

SPI

PG 20

PG 18

MEMORY

MAIN

800/1067 /1333 MHz

DDR2-800 MHZ

DDR3-106 7/1333MH Z

J2900

DIMM

PG 25,26

SPI

TEMP SENSOR

FAN CONN AND CONTROL

J5100

PG 43

Ser

FanADC

SMC

B,0

Prt

BSB

PWR

Misc

PG 14

Port80,serial

LPC Conn

GPIOs

SATA

1.05V/3GHZ .

RGB OUT

PG 38

PG 13

FSB INTE RFACE

PG 24

SMB

PG 20

HDA

NVIDIA

PG 41

CAMERA

Connecto rs

PG 44

CONN

SMB

DIMM's

10 5 6 7

Bluetooth

PG 52

Boot ROM

U1400

DVI OUT

PCI-E

PG 16

UP TO 20 LANES3

PG 17

LVDS OUT

DP OUT

HDMI OUT

RGMII

PG 18

AirPort

Mini PCI-E

U3700

Line I n

Amp Amp

PG 60

PG 9

System Block Diagram

SYNC_DA TE=12/ 12/2007

A.0.0

2 96

051-7546

SYNC_MA STER=T 18_MLB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

PP3V3_S 0GPU_F ET

P3V3S0_ SS

(PAGE 42)

S0PGOOD_PWROK

P1V5S0_PGOOD

P3V3S3_ SS

(18A MAX CURRENT)

GPUVCORE_IOUT

RSMRST_ IN(P13 )

IMVP_VR _ON

PLT_RST *

PWR_BUT TON(P9 0)

PM_PWRB TN_L

SMC_ONO FF_L

RSMRST_ PWRGD

MCP_PS_PWRGD

PWROK

CPUPWRG D(GPIO 49)

PLT_RST_L

CK_PWRG D

VR_PWRGD_CLKEN

VRMPWRG D

PP5V_S0 _FET

(25A MAX CURRENT)

(5A MAX CURRENT)

PM_SLP_S3_DELAY_L

SMC_ADAPTER_EN

PPVBAT_G3H_CHGR_R

CHGR_BGATE

J6950

BATT_POS_F

6A FUSE

DCIN(16.5V)

U7000

ISL6258A

BATTERY CHARGER

PBUS SUPPLY/

(PAGE 60)

PM_SLP_ S5_L

PM_SLP_ S4_L

PM_SLP_ S3_L

U4900

SLP_S3_ L(P93)

SLP_S4_ L(P94)

SLP_S5_ L(P95)

SMC_RESET_L

PM_RSMRST_L

99ms DLY

RSMRST_ OUT(P1 5)

PWRGD(P1 2)

IMVP_VR _ON(P1 6)

PP1V05_ S5_MCP

(PAGE 68)

LTC2900

P1V8S0_PGOOD

CPUVTTS0_PGOOD

MCPCORES0_PGOOD

P5VRIGHT_PGOOD

P1V05S0_PGOOD

P5VS0_SS

Q7900

PP5V_S3 _FET

P5VS3_SS

Q7910

PP3V3_S 3_FET

PP3V3_S 0_FET

P3V3GPU _SS

P3V3_EN ET_FET

P3V3ENE T_EN_L

(12A MA X CURR ENT)

PPDDR_S 3_REG

PPVTT_S 0_DDR_ LDO

PP5V_RT_REG

MCPCPCORE_S0_REG

(PAGE 65)

ISL6236

U7500

1.1V

MCP_CORE

P1V05S0_EN

MCPCORES0_EN

CPUVTTS0_EN

MCPDDR_EN

P1V8S0_EN

P5VRIGHT_EN

P5VS0_EN

PM_SLP_S3_L

Q3800

WOL_EN

PM_ENET _EN_L

DDRVTT_EN

DDRREG_EN

U7300

(PAGE 63)

TPS51116

0.9V

1.8V

PPVIN_S0_DDRREG_LDO

P1V2ENET_EN

ENETAVDD_EN

PP1V2_E NET_RE G

PP1V9_E NET_RE G

(PAGE 33)

U3850

LTC3407

GOSHAW K6P

PPVOUT _S0_LC DBKLT

Q7930

Q7970

P5V3V3_ S5_PGOOD

P5V_RT _PGOOD

PP5V_R T_REG

PP3V3_S 5_REG (5.5A M AX CUR RENT)

PP5V_S5 _REG (8A MAX CURRE NT)

(PAGE 66)

U7750

ISL8009

CPUVTTS0_PGOOD

PPCPUVTT_S0_REG

CPUVTTS0_EN

PGOOD

(PAG 66)

U7600

TPS51117

VOUT

PP3V42_G3H_REG

(PAGE 59)

U6990

LT3470

3.425V G3HOT

GPU VCORE

U8900

ISL6263B

ISL9504B

CPU VCORE

(PAGE 62)

U7201

TPS51125

3.3V

5V

(PAGE 82)

U9500

TPS511 24

1.8V(R /H)

1.103V (L/H)

VIN

U7400

SC417

(PAGE 64)

(PAGE 84)

U9701

V4

PP1V8_GPU_REG

VOUT1

RST*

U7870

V1 V2 V3 V4

PP1V5_S0_REG

PP3V3_S0

PP5V_S0

VIN

VOUT2

CPUVCORE_IOUT

PPVCORE_CPU_S0

VOUT2

VLDOIN

P3V3S5_EN

(R/H)

VOUT1

EN1

P1V1GPU_EN

PPBUS_G3H

U5400

PP1V1_S0GPU_REG

(PAGE 61)

Q7920

PM_ENET_EN_L

(S0)

P3V3S0_EN

DELAY

Q3805

SMC

LIO_DCIN_ISENSE

Q7055

VOUT1

VIN

EN0

VREG3

ENL

VIN

EN2

VIN

IN

SMC_RESET_L

ENABLE

U5000

RN5VD30A-F

VIN

(L/H)

ADAPTER

VOUT

P1V8FB_EN

VIN

VR_ON

VOUT

A

VIN

U2830

VOUT2

PGOOD1,2

VOUT2

U2850

CPU

U1000

SMC

PWRBTN#

PLTRST*

PWRGOOD

(PAGE 10,11)

RESET*

EN/PSV

S3

RUN1

ENA

EN2

VOUT1

RUN2

S5

VR_PWRGOOD_DELAY

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

RC

MCP79

RSMRST*

U1400

(PAGE 14~22)

U1400

3S2P

A

P60

P5V_RT_EN

PBUSB_VSENSE

Q5315

ENABLES

A

AC

PM_GPUVCORE_EN

SMC PWRGD

IMVP_VR_ON_R

(PAGE 78)

PGOOD

U5498

SMC_GPU_VSENSE

VOUT

D6905

VOUT

U4900

VIN

BKLT_EN

(PAGE 14~22)

SLP_S3#(G17)

SLP_S5#(H17)

Q3810

VOUT

VIN

(S0)

MCP79

(S0)

PBUSVSENS_EN

U7859

SMC_PM_G2_EN

(S5)

PGOOD

Q3801

WOW_EN

PM_ENET_EN

PM_WLAN_EN_L

P17(BTN_OUT)

(PAGE 42)

U5705

PPVCORE_GPU_REG

V

A

LIO_S3_EN

P5VS3_EN

P3V3S3_EN

(9 TO 12.6V)

U5715

8A FUSE

D6905

PPVBAT_G3H_CHGR_REG

SMC_BATT_ISENSE

EN_PSV

GPUVCORE_PGOOD

SMC_CPU_VSENSE

V

VR_PWRGD_CLKEN_L

VIN

U7100

PGOOD

RST*

ALL_SYS_PWRGD

VOUT2

EN1

DELAY

PPBUS_G3H

V

PPVIN_G3H_P3V42G3H

PP3V3_S 5

PP5V_S3

(S5)

CHGR_EN

1.05V

EN_PSV

(PAGE 43)

CPU_PWRGD

(6A MAX CURRENT)

M98 POWER SYSTEM ARCHITECTURE

SYNC_MA STER=T 18_MLB

051-7546

96

A.0.0

SYNC_DA TE=12/ 12/2007

3

Power Block Diagram

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

SYNC_MA STER=N /A

SYNC_DA TE=N/A

4 96

A.0.0

051-7546

Power Block Diagram

www.laptop-schematics.com

BOM OP TIONS

BOM GR OUP

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

PART NUMB ER

ALTERNATE FOR

PART NUMB ER

BOM OPTIO N

REF DES

COMMENTS:

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

BOM OP TIONS

BOM GR OUP

BOM OP TIONS

BOM NA ME

BOM NU MBER

BOM Variants

Bar Code Labels / EEE #'s

Module Parts

M98 BOM Groups

M98_CO MMON

ALTERN ATE,CO MMON,M9 8_COMM ON1,M9 8_COMM ON2,M98 _COMMO N3,M98 _DEBUG ,M98_P ROGPART S

M98_DE BUG

M98_PR OGPART S

M98_CO MMON3

630-95 86

M98_COM MON,EEE_ 2NJ,CPU_ 2_8GHZ,F B_512_Q IMONDA

PCBA,2 .8GHZ, 512QIM_ VRAM,M 98

630-93 35

M98_COM MON,EEE_ 0ZB,CPU_ 2_4GHZ,F B_256_H YNIX

PCBA,2 .4GHZ, 256HYN_ VRAM,M 98

630-93 34

M98_COM MON,EEE_ 0ZA,CPU_ 2_4GHZ,F B_256_S AMSUNG

PCBA,2 .4GHZ, 256SAM_ VRAM,M 98

CRITIC AL826-4393

1

EEE_2N H

LBL,P/N LABEL,P CB,28MM X 6 MM

[EEE:2 NH]

BOM Configuration

5 96

051-7546

SYNC_MA STER=N /A

SYNC_DA TE=N/A

A.0.0

U4900

SMC_PRO G

341S22 89

1

CRITIC AL

IC,SMC, DEVELOPM ENT,M98

CRITIC AL

MCP_B0 1

U1400

338S06 00

1

IC,GMCP,M CP79-B01, 35x35MM,B GA1437

CRITIC AL1CPU_2_ 5GHZ

337S36 40

IC,PDC,SL3B X,PRQ,2.53G, 35W,1066,C0 ,6M,BGA

U1000

[EEE:0 ZD]

1

EEE_0Z D

CRITIC AL826-4393

LBL,P/N LABEL,P CB,28MM X 6 MM

1

CRITIC AL826-4393

EEE_0Z B

[EEE:0 ZB]

LBL,P/N LABEL,P CB,28MM X 6 MM

U4800

1

341S23 84

IR,ENCORE II, CY7C 63803-LQX C

CRITIC AL

1

338S05 54

IC,GPU, 55nm,NV G96-GS, BGA969, LF

U8000

M98_COM MON,EEE_ 0ZD,CPU_ 2_5GHZ,F B_512_Q IMONDA

630-93 37

PCBA,2 .5GHZ, 512QIM_ VRAM,M 98

VRAM4, VRAM_2 56_HYNI X

FB_256_ HYNIX

CRITIC AL

1

LBL,P/N LABEL,P CB,28MM X 6 MM

826-43 93

EEE_2N J

[EEE:2 NJ]

CRITIC AL

[EEE:0 ZC]

826-43 93

EEE_0Z C

1

LBL,P/N LABEL,P CB,28MM X 6 MM

CRITIC AL

1

338S05 63

U4900

SMC_BLA NK

IC,SMC, HS8/2117 ,9MMX9M M,TLP

U8770

HDCP_YE S

341S22 72

1

IC,HDCP R OM,NVG96, 8 PIN SO IC,LF,HF

CRITIC AL

CRITIC AL1CPU_2_ 4GHZ

337S36 39

IC,PDC,SLB4 N,PRQ,2.4G,2 5W,1066,M0, 3M,BGA

U1000

630-93 36

M98_COM MON,EEE_ 0ZC,CPU_ 2_5GHZ,F B_512_S AMSUNG

PCBA,2 .5GHZ, 512SAM_ VRAM,M 98

FB_512_ QIMONDA

VRAM4, VRAM_5 12_QIMO NDA

CRITIC AL

1

U3700

338S05 70

IC,RTL821 1CL,GIGE TRANSCEIV ER,48P TQ FP

CRITIC AL

1

U4100

338S05 23

IC,FW643-06 ,1394B PHY/O HCI LINK/PC I-E,12

338S06 35

IC,GMCP,M CP79-B02, 35x35MM,B GA1437

CRITIC AL

1

U1400

MCP_B0 2

BOOTROM _PROG

U6100

1

IC,EFI ROM,DEVE LOPMENT ,M98

341S23 66 CRITIC AL

CRITIC AL

1

U6100

BOOTROM _BLANK

335S03 84

IC,32MBIT 8-PIN SPI SERIAL F LASH,SOIC8

IC,SGRAM, GDDR3,16M x32,800MH Z,136 FBG A

U8400,U84 50,U8500,U 8550

VRAM_25 6_SAMSUN G

333S04 82 CRITIC AL

4

IC,SGRAM, GDDR3,32M x32,900MH Z,136 FBG A

VRAM_51 2_QIMOND A

CRITIC AL

4

333S04 72

U8400,U84 50,U8500,U 8550

341S23 83

IC,PSOC +W/USB, 56PIN,M LF,M98

CRITIC AL

1

U5701

TPAD_PR OG

138S0603

ALL

138S0602

Murata alt to Samsung

U8400,U84 50,U8500,U 8550

IC,SGRAM, GDDR3,32M x32,900MH Z,136 FBG A

VRAM_51 2_SAMSUN G

CRITIC AL333S0481

4

U8400,U84 50,U8500,U 8550

333S04 83

IC,SGRAM, GDDR3,16M x32,900MH Z,136 FBG A

4

CRITIC AL

VRAM_25 6_HYNIX

337S36 41

CPU_2_ 8GHZU1000

CRITIC AL

1

IC,PDC,SLB4 3,PRQ,2.8G,3 5W,1066,C0, 6M,BGA

ALL

353S1294

LMV2011,OPAMP. GBW

353S1681

ALL

514-0608

FOXLINK RCVR A LT TO FOXCONN

514-0613

ALL

157S0055

Delta alt to T DK Magnetics

157S0058

ALL

514-0607514-0612

FOXLINK XCVR A LT TO FOXCONN

152S0796

ALL

152S0915

Maglayers alt to Cyntec IND

ALL

341S2366341S2367

Macronix alt t o SST

353S1466

ALL

INTERSIL ALT T O INTERSIL

353S2312

ALL

152S0876 152S0867

Maglayer alt t o Delta

ALL

152S0276 152S0683

Maglayers alt to Dale/Vishay

CRITIC AL

LBL,P/N LABEL,P CB,28MM X 6 MM

1

826-43 93

EEE_0Z A

[EEE:0 ZA]

VRAM4, VRAM_5 12_SAMS UNG

FB_512_ SAMSUNG

630-95 85

M98_COM MON,EEE_ 2NH,CPU_ 2_8GHZ,F B_512_S AMSUNG

PCBA,2 .8GHZ, 512SAM_ VRAM,M 98

M98_CO MMON1

ONEWIR E_PU,I SL6258A ,MEMRE SET_HW ,MEMRE SET_MCP ,MCP_B 02,MCP _PROD, MCPSEQ _SMC

M98_CO MMON2

BKLT_P LL_NOT ,BMON_E NG,MIK EY,BOO T_MODE _USER,G PUVID_ 1P00V, MUXGFX

VRAM4, VRAM_2 56_SAMS UNG

FB_256_ SAMSUNG

DPMUX_ EN_S0, DP_ESD, EG_PWR SEQ_HW ,DP_CA _DET_EG _PLD,M CP_CS1 _NO

GMUX_P ROG,BO OTROM_P ROG,SM C_PROG ,TPAD_ PROG

SMC_DE BUG_YE S,XDP,L PCPLUS ,VREFM RGN

www.laptop-schematics.com

IN

B1

OE*

VCCB

B2

B3

B4

GND

A4

A3

A2

A1

VCCA

OUT

GND

VCC

NCNC

YA

NC NC

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

TDO

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

From XDP connector

or via level translator

GPU

U9200

GMUX

U8000

MCP

U1400

From XDP connector

U1000

CPU

To XDP connector and/or level translator

XDP connector

TMS

TCK

TDI

GMUX CPLD Programming Port

6

10 13 87

NLSV4T244

UQFN

JTAG_ALLD EV

CERM

10V

402

20%

0.1UF

JTAG_AL LDEV

20% 10V CERM 402

JTAG_AL LDEV

0.1UF

JTAG_AL LDEV

5%

10K

1/16W MF-LF

402

0

1/16W

5%

MF-LF

402

NOSTUFF

13

CRITIC AL

1909782

M-RT-SM

402

MF-LF

1/16W

5%

0

XDP

PLACEM ENT_NO TE=Plac e near pin U 1000.A B3

0

1/16W MF-LF

5%

402

XDP

PLACEM ENT_NO TE=Plac e near pin U 1400.F 19

74LVC1G 07

SOT886

PLACEM ENT_NO TE=Plac e clos e to U 0600

5%

MF-LF

1/16W

10K

NOSTUFF

402

PLACEM ENT_NO TE=Plac e clos e to U 8000

10K

5% 1/16W MF-LF 402

6

10 13 87

6

10 13 87

13

051-7546

A.0.0

966

SYNC_MAS TER=DDR

SYNC_DAT E=07/22/ 2008

JTAG Scan Chain

=PP1V05_ S0_CPU

MAKE_BASE= TRUE

JTAG_M CP_TRS T_L

XDP_TC K

XDP_TD O

JTAG_G MUX_TC K

GPU_JT AG_TRS T_L

GPU_JT AG_TMS

=PP3V3_S 0_XDP

JTAG_M CP_TDI

JTAG_G MUX_TM S

GPU_JT AG_TCK

GPU_JT AG_TDO

MAKE_BASE= TRUE

TP_GPU _JTAG_ TDO

JTAG_M CP_TDO_ CONN

GPU_JT AG_TMS

=PP3V3 _GPU_V DD33

XDP_TR ST_L

XDP_TM S

XDP_TC K XDP_TD I

XDP_TD O_CONN

MAKE_BASE= TRUE

JTAG_M CP_TDO

GPU_JT AG_TDI

XDP_TM S XDP_TR ST_L

=PP3V3_S 0_XDP

JTAG_L VL_TRA NS_EN_L

JTAG_G MUX_TD O

JTAG_M CP_TMS

MAKE_BASE= TRUE

JTAG_M CP_TCK

JTAG_G MUX_TD I

U0600

2

3

4

5

10

9

8

7

6

12

1

11

C0601

1

2

C0602

1

2

R0601

1

2

R0602

1

2

J0600

7

8

1

2

3

4

5

6

R0603

1 2

R0604

1 2

U0601

2

3

1

5

6

4

R0605

1 2

R0606

1

2

62 13 12

87

11

13

23

76

13

23

10

21

10

87

75

8

21

83

75 75

10

8

83

21

83

8

13

6

10

83

75

6

13

9

75

6 8

21

75

6

9

13

9

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

FUNC_T EST

5 TPs

SATA ODD Connectors

KEYBOARD CONN

Speaker Connectors

FUNC_T EST

Fan Connectors

IPD_FLEX_CONN

LVDS Connectors

POWER RAILS

6 TPs

5 TPs

FUNC_T EST

CPU FSB NO_TESTs

NO_TEST

ICT Test Points

FUNC_T EST

3 TPs

per Fa n

4 TPs

Functional Test Points

per Fa n

FUNC_T EST

EXCARD Connector

I557

I558

I559

I560

I561

I562

I563

I564

I565

I566

I567

I568

I569

I570

I571

I572

I573

I574

I575

I576

I577

I578

I579

I580

I581

I582

I583

I584

I585

I586

I587

I588

I589

I590

I591

I592

I593

I594

I595

I596

I597

I598

I600

I602

I603

I604

I605

I606

I607

I608

I609

I610

I611

I612

I613

I614

I615

I616

I617

I618

I619

I620

I621

I622

I623

I624

I625

I626

I627

I636

I637

I638

I639

I640

I641

I642

I643

I644

I645

I646

I647

I648

I649

I650

I651

I652

I653

I654

I655

I656

I657

I709

I710

I711

I712

I713

I714

I715

I716

I717

I718

I719

I720

I721

I722

I723

I724

I725

I726

I727

I728

I729

I730

I731

I732

I733

I734

I735

I736

I737

I739

I740

I741

I742

I743

I744

I745

I746

I747

I748

I749

I750

I751

I752

I753

I754

I755

I756

I757

I758

I759

I760

I761

I762

I763

I764

I765

7 96

A.0.0

051-7546

Functional / ICT Test

SYNC_MA STER=N /A

SYNC_DA TE=N/A

PP3V3_ S5_AVRE F_SMC

TRUE

PP3V3_S3_LDO

TRUE

PP1V8_ S0GPU_ ISNS_R

TRUE

PP0V9R0 V75_S0_D DRVTT

TRUE

PPCPUFS B_ISNS_R

PPCPUVTT _S0

TRUE

PP1V2R1 V05_S5

TRUE

PP1V05_S 0_REG

TRUE

PP1V8_S 0

PP1V2_ S0

TRUE

PP2V5_ S0

TRUE

PP3V3_ S0

TRUE

PP3V3_ S3

TRUE

PP3V3_ S5

TRUE

PP5V_S 0

TRUE

PP5V_S 3

TRUE

PP3V42 _G3H

TRUE

PPBUS_ CPU_IM VP_ISNS

PPBUS_ G3H

TRUE

PM_SLP_ S3_L

TRUE

SATA_O DD_D2R _C_P

TRUE

SATA_O DD_D2R _C_N

TRUE

SATA_O DD_R2D _N

TRUE

SATA_O DD_R2D _P

PCIE_C LK100M _EXCARD _CONN_ N

TRUE

FSB_DI NV_L<3 ..0>

TRUE

FSB_DS TB_L_N <3..0>

TRUE

FSB_HI T_L

TRUE

FSB_DS TB_L_P <3..0>

TRUE

FSB_HI TM_L

TRUE

FSB_LO CK_L

FSB_D_ L<63.. 0>

TRUE

LED_RETU RN_5

PCIE_E XCARD_ D2R_P

TRUE

PP1V8_ S0GPU_ ISNS

TRUE

LED_RETU RN_4

LED_RETU RN_3

TRUE

=PP5V_ S0_FAN _LT

EXCARD _CLKRE Q_CONN_ L

TRUE

SPKRCO NN_S_N _OUT

SPKRCO NN_R_P _OUT

TRUE

EXCARD _CPUSB _L

TRUE

EXCARD _CPPE_ L

PLT_RE SET_SW ITCH_L

TRUE

PP1V5_ S0_EXC ARD_SWI TCH

TRUE

PCIE_E XCARD_ R2D_N

TRUE

BI_MIC _LO

FAN_LT _TACH

TRUE

LVDS_CON N_A_DATA _N<0>

LVDS_CON N_A_CLK_ F_N

TRUE

LVDS_CON N_B_DATA _P<0>

TRUE

LVDS_CON N_A_CLK_ F_P

LVDS_CON N_A_DATA _N<2>

TRUE

LVDS_CON N_A_DATA _P<1>

TRUE

LVDS_CON N_A_DATA _N<1>

TRUE

LVDS_CON N_B_CLK_ F_N

LVDS_CON N_B_DATA _N<1>

TRUE

FAN_RT _TACH

FSB_AD S_L

TRUE

FSB_AD STB_L< 1..0>

TRUE

FSB_A_ L<31.. 3>

TRUE

LED_RETU RN_2

TRUE

LED_RETU RN_1

TRUE

LVDS_CON N_A_DATA _P<0>

LVDS_DDC _DATA

TRUE

LVDS_CON N_B_DATA _P<1>

LVDS_CON N_A_DATA _P<2>

TRUE

FAN_LT _PWM

TRUE

LVDS_CON N_B_DATA _N<0>

TRUE

LVDS_CON N_B_CLK_ F_P

TRUE

LVDS_CON N_B_DATA _N<2>

LVDS_CON N_B_DATA _P<2>

TRUE

PCIE_C LK100M _EXCARD _CONN_ P

TRUE

LED_RETU RN_6

FAN_RT _PWM

TRUE

SMC_ODD _DETECT

TRUE

SPKRCO NN_R_N _OUT

TRUE

BI_MIC _HI

SPKRCO NN_L_P _OUT

TRUE

WS_KBD6

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD11

TRUE

WS_KBD12

TRUE

WS_KBD13

TRUE

WS_KBD14 WS_KBD15_CAP

TRUE TRUE

WS_KBD16_NUM

TRUE

WS_KBD20 WS_KBD21

TRUE TRUE

WS_KBD22

TRUE

WS_KBD23 WS_KBD_ONOFF_L

TRUE

PSOC_SCLK

TRUE

Z2_RESET

TRUE

Z2_KEY_ACT_L

Z2_HOST_INTN

TRUE

Z2_BOOST_EN

TRUE

WS_KBD2

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

SPKRCO NN_L_N _OUT

TRUE

WS_KBD17

PP1V8R1V 5_S0_FET

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_CONTROL_KBD

TRUE

TPAD_GND_F

KBDLED_ANODE

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_KBD19

TRUE

WS_KBD5

TRUE

WS_KBD7

WS_KBD10

TRUE

WS_KBD18

TRUE

PPVCOR E_S0_C PU

TRUE

PPMCPDDR _ISNS

PP3V3_ S0GPU

TRUE

PPDCIN _G3H

TRUE

PPVOUT _S0_LC DBKLT

TRUE

PPVCOR E_GPU

TRUE

PPVTTD DR_S3

TRUE

PP1V8_ GPUIFPX

TRUE

PCIE_E XCARD_ D2R_N

TRUE

USB2_E XCARD_ CONN_P

TRUE

USB2_E XCARD_ CONN_N

TRUE

PCIE_E XCARD_ R2D_P

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

BI_MIC _SHIEL D

TRUE

PSOC_MOSI

TRUE

PSOC_F_CS_L

TRUE

Z2_BOOT_CFG1

TRUE

PP3V42_G3H

TRUE

SPKRCO NN_S_P _OUT

TRUE

LVDS_DDC _CLK

TRUE

BKL_SYN C

TRUE

PP3V3_SW _LCD

TRUE

=PP3V3_S 0_DDC_LC D

TRUE

FSB_RE Q_L<4. .0>

TRUE

WS_KBD1

TRUE

WS_KBD4

WS_KBD3

TRUE

PP1V0_ FW

PP1V1_S0 GPU_REG

TRUE

PP1V8R1V 5_S3

TRUE

PP1V2R 1V05_E NET

PPVP_F W

TRUE

PP3V3_ ENET_P HY

PSOC_MISO

TRUE

Z2_CLKIN

TRUE

Z2_SCLK

TRUE

Z2_MISO

TRUE

Z2_MOSI

TRUE

Z2_DEBUG3

TRUE

Z2_CS_L

TPAD_GND_F

TRUE

PP18V5_S3

TRUE

PICKB_L

TRUE

PP5V_SW _ODD

TRUE

PP3V3_ S0_EXC ARD_SWI TCH

TRUE

PP3V3_ S3_EXC ARD_SWI TCH

SMBUS_MC P_0_DATA

TRUE

SMBUS_MC P_0_CLK

TRUE

PPVCOR E_S0_MC P

PPVCOR E_S0_MC P_REG

TRUE

GND

TRUE

GND

83 81 68 44 42

90

43

37

87

89

95

94

87

94

95

89

95

43

95

79

87

45

43

95

8

46

34

89

95

14

84

32

84

49

58

89

59

80

94

80

94

80

94

80

14

84

80

94

80

95

84

42

58

59

58

51

93

58

51

84

32

95

89

93

59

51

8

58

80

84

76

14

51

21

42

51

8

7

8

21

39

32

10

79

17

8

79

8

32

57

32

58

49

79

49

10

79

49

79

32

79

49

39

57

58

57

50

51

50

45

57

50

8

50

7

51

50

8

79

8

17

32

45

58

50

7

57

79

8

10

50

8

50

7

51

50

39

32

13

8

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

"G3Hot" (Always-Present) Rails

5300 mA

241 mA max load

1034 mA

Chipset "VCore" Rails

139 mA/ 0 mA

105 mA/ 241 mA

1182 mA

4500 mA

1.8V/DDR 1.5V Rails

5V Rails

3.3V-2.5V Rails

"GPU" Rails

500 mA max supp ly

"FW" (FireWire) Rails

190 mA

500 mA

130 mA

4771 mA

(1.1V f or A01)

OR 0.75 V

ENET Rails

Power Aliases

SYNC_MA STER=( MASTER)

051-7546

A.0.0

968

SYNC_DA TE=(MA STER)

=PPVP_ FW_POR T1 =PPVP_ FW_PHY _CPS_FE T

=PP3V3 _S0GPU _FET

=PP3V3 _FW_FW PHY

=PP1V0 _FW_RE G

=PP1V05 _S0_MCP_ SATA_AVD D0

PP1V2R1 V05_S5

MIN_NECK_W IDTH=0.2 m m VOLTAGE=1. 05V MAKE_BASE= TRUE

MIN_LINE_W IDTH=0.6 m m

=PP3V3 _FW_RE G

=PP1V5 _FC_CO N

=PP3V3 _S3_SM BUS_SMC _A_S3

=PP3V3 _FW_RE G

=PPBUS_G 3H

PPBUS_ CPU_IM VP_ISNS

MIN_LINE _WIDTH=0 .4 mm

MAKE_BAS E=TRUE

VOLTAGE= 12.6V

MIN_NECK _WIDTH=0 .25 mm

=PP3V3 _S3_FE T

=PPVIN _S5_P5V P3V3

=PP3V3 _S0_SM BUS_SMC _B_S0

=PP3V3 _S0_CP UTHMSNS

=PP3V3 _S0_IM VP

=PP3V3 _S0_XD P

=PP3V3 _S0_MCP COREIS NS

=PP3V3 _S0_FA N_RT

=PPVCO RE_S0_M CP

PP1V2_ S0

MIN_LINE_W IDTH=0.6 m m MIN_NECK_W IDTH=0.2 m m

MAKE_BASE= TRUE

VOLTAGE=1. 2V

=PP2V5 _S0_GM UX

=PP1V0 5_ENET _FET

=PP3V3 _S0_MCP

=PP1V8R1 V5_S0_MC P_FET

=PPVIN_S 0_DDRREG _LDO

=PPVIN _S5_CP U_IMVP_ ISNS

=PP3V4 2_G3H_C HGR

=PP3V4 2_G3H_ TPAD

=PP3V4 2_G3H_ CPUCORE ISNS

=PP18V 5_DCIN _CONN

=PP3V3 _S0_EX CARD =PP3V3 _S0_LV DSDDCMU X

=PP3V3 _S0_OD D

=PP3V3 _S0_AU DIO

=PPSPD _S0_MEM _B

=PPSPD _S0_MEM _A

=PP3V3 _S0_DD C_LCD

=PP3V3 _S0_PW RCTL

=PP3V3 _S0_FA N_LT

=PPVIN _S0GPU _P1V8P1 V1

=PP3V3 _S0_GP UTHMSNS

=PP3V3 _S0_SMB US_MCP _1

=PP3V3_ GPU_SMBU S_SMC_0_ S0

MIN_LINE_W IDTH=0.6 m m

MAKE_BASE= TRUE

MIN_NECK_W IDTH=0.2 m m

PP2V5_ S0

VOLTAGE=2. 5V

=PP1V2 _S0_GM UX

=PP1V8 _GPU_I FPX

VOLTAGE= 1.8V MAKE_BAS E=TRUE

MIN_LINE _WIDTH=0 .6 mm

PP1V8_ GPUIFPX

MIN_NECK _WIDTH=0 .15 mm

=PP1V1_G PU_IFPCD _IOVDD

=PP1V1_G PU_VID_P LLVDD

=PP1V1_G PU_H_PLL VDD

=PP1V1_G PU_PLLVD D

=PP1V1 _S0GPU _REG

=PP1V1_G PU_PEX_P LLXVDD

=PP1V1_G PU_PEX_I OVDDQ

=PP1V1_G PU_PEX_I OVDD

=PP1V1_G PU_FBPLL AVDD

MAKE_BAS E=TRUE

PP1V8_ S0GPU_ ISNS

MIN_LINE _WIDTH=0 .6 mm

VOLTAGE= 1.8V

MIN_NECK _WIDTH=0 .2 mm

=PP1V8 _GPU_F B_VDDQ

=PP1V8 _GPU_F BIO

=PP3V3 _GPU_P 1V8S0

=PP1V8 _GPU_F B_VDD

=PP1V8 _GPU_F BVDDQ

=PP1V8 _S0GPU _ISNS

=PP1V5_S 3_MEM_A

=PP1V5_S 3_MEM_B

=PP3V3 _ENET_ MCP_RMG T

=PPVTT_ S0_VTTCL AMP

=PP0V75 _S0_MEM_ VTT_B

=PP0V75 _S0_MEM_ VTT_A

=PP1V05 _ENET_P1 V05ENETF ET

=PP1V05 _S5_MCP_ VDD_AUXC

=PP5V_ S3_MCP DDRFET

=PP5V_ S3_GPU VCORE

=PP5V_ S3_WLA N

MIN_NECK _WIDTH=0 .25 mm

MIN_LINE _WIDTH=0 .5 mm

MAKE_BAS E=TRUE

PP5V_S 3

VOLTAGE= 5V

=PP5V_ S3_BTCA MERA

PPVCOR E_S0_C PU

VOLTAGE= 1.25V

MIN_LINE _WIDTH=0 .6 mm

MAKE_BAS E=TRUE

MIN_NECK _WIDTH=0 .25 mm

=PP3V3 _GPU_V CORELOG IC =PP3V3 _S5_SM C =PP3V3 _S5_LP CPLUS

=PP3V4 2_G3H_ SMBUS_S MC_BSA

=PP1V8R1 V5_S0_FE T

=PP1V2 _S0_RE G

=PP2V5 _S0_RE G

=PP5V_ S3_P1V 05S0FET

=PP1V05 _S5_P1V0 5S0FET

=PP3V3 _ENET_ FET

=PP3V3 _ENET_ PHY

=PP1V0 5_ENET _PHY

=PP1V0 5_ENET _MCP_RM GT

=PP1V0 5_ENET _MCP_PL L_MAC

VOLTAGE =3.3V MAKE_BA SE=TRU E

MIN_NEC K_WIDT H=0.2 m m

PP3V3_ ENET_P HY

MIN_LIN E_WIDT H=0.6 m m

VOLTAGE =1.05V

PP1V2R 1V05_E NET

MIN_LIN E_WIDT H=0.4 M M MIN_NEC K_WIDT H=0.2 m m

MAKE_BA SE=TRU E

=PPVCO RE_S0_ CPU_REG

PP1V8_S 0

MIN_LINE_W IDTH=0.5 m m MIN_NECK_W IDTH=0.2 m m VOLTAGE=1. 8V MAKE_BASE= TRUE

=PP3V3 _GPU_M IO

=PP3V3 _GPU_V DD33

=PP3V3R 1V8_S0_M CP_IFP_V DD

PPVCOR E_GPU

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .2 mm VOLTAGE= 1.2V MAKE_BAS E=TRUE

MIN_LINE _WIDTH=0 .6 mm

MAKE_BAS E=TRUE

VOLTAGE= 1.25V

MIN_NECK _WIDTH=0 .2 mm

PP1V8_ S0GPU_ ISNS_R

=PPVCO RE_GPU

=PP1V8 _S0GPU _ISNS_R

=PPVCO RE_GPU _REG

=PP1V8 _GPU_R EG

=PPBUS _S5_FW _FET

=PP1V0 _FW_FW PHY

MIN_LINE _WIDTH=0 .4 mm

VOLTAGE= 1.00V MAKE_BAS E=TRUE

MIN_NECK _WIDTH=0 .2 mm

PP1V0_ FW

=PPMCP CORE_S0 _REG

=PPDDR_S 3_REG

PP1V05_ S0_MCP_S ATA_AVDD

MAKE_BASE=T RUE

=PP3V4 2_G3H_ PWRCTL

=PP3V3 _S5_RTC _D

=PP5V_ S3_AUD IO_PWR

=PP5V_ RT_REG

=PP5V_ S0_CPUV TTS0

=PP3V4 2_G3H_ SMCUSBM UX

MIN_LINE _WIDTH=0 .4 mm MIN_NECK _WIDTH=0 .2 mm VOLTAGE= 12.6V MAKE_BAS E=TRUE

PPVP_F W

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm

MAKE_BASE=T RUE

VOLTAGE=1.0 5V

PPVCOR E_S0_MC P_REG

=PPVTT_S 3_DDR_BU F

=PP3V3 _FW_P1 V0FW

=PP5V_ S0_CPU _IMVP

=PP5V_ S3_RTU SB

=PP5V_ S3_DDR REG

=PP5V_ S3_IR

=PP5V_ S3_SYS LED

=PPVIN _S5_SM CVREF

=PPVIN _S5_CP U_IMVP

=PP5V_ S0_FAN _RT

=PP3V3 _S3_P3 V3S3FET

=PP3V3 _S5_MC P_A01

=PP3V3 _S5_RE G

=PP3V3 _FW_LA TEVG_AC TIVE

=PP3V3 _S5_ME MRESET

=PP3V3_ S0_BATT CHARGER TMPSNSR

=PP5V_ S3_REG

=PP3V4 2_G3H_ REG

=PP1V05 _S0_MCP_ PEX_AVDD 1

=PP3V3 _S3_VRE FMRGN

=PP1V05_ S0_SMC_L S

=PP1V05_ S0_MCP_F SB

=PP1V05 _S0_MCP_ SATA_DVD D0

=PP5V_ S3_VTT CLAMP

=PP5V_ S0_FAN _LT

=PP5V_ S0_KBD LED =PP5V_ S0GPU_ P1V1P1V 8_GPU =PP5V_ S0_LPC PLUS

=PPVIN _S0_CP UVTTS0

=PPVIN _S5_CP U_IMVP_ ISNS_R

=PP1V8_ S0_REG

=PP3V3_ S0_TPAD

=PP1V05 _S0_FET

PP1V8R1V 5_S0_FET

MIN_LINE_WI DTH=0.6mm MIN_NECK_WI DTH=0.2mm VOLTAGE=1.5 V MAKE_BASE=T RUE

=PP1V5_S 3_MEMRES ET

MIN_NECK_WI DTH=0.1 mm VOLTAGE=1.5 V MAKE_BASE=T RUE

PP1V8R1V 5_S3

MIN_LINE_WI DTH=0.8 mm

=PP3V3 _S0_MCP _DAC_U F

=PP3V3 _S0_MCP _VPLL_ UF

=PP3V3 _S0_MCP _PLL_U F

=PP3V3 R1V5_S0 _MCP_H DA

=PPVCO RE_S0_ CPU

=PP5V_ S3_TPA D

=PPVIN _S0_P1 V05S5

=PPDCI N_S5_C HGR

=PP3V4 2_G3H_ LIDSWIT CH

=PP3V4 2_G3H_ BATT

=PP3V4 2_G3H_ BMON_IS NS

=PP3V3 _S3_SM S

=PPBUS _S0_LCD BKLT

MAKE_BAS E=TRUE

VOLTAGE= 12.6V

MIN_NECK _WIDTH=0 .25 mm

PPBUS_ G3H

MIN_LINE _WIDTH=0 .4 mm

=PP3V3 _S3_EXC ARD

=PP3V3 _S0_LP CPLUS

=PP3V3 _S0_GP U1V8ISN S

=PP3V3 _S0_MCP DDRISN S

=PP3V3 _S0_SM C

MIN_NECK _WIDTH=0 .20MM

MAKE_BAS E=TRUE

PP3V3_ S0

MIN_LINE _WIDTH=0 .30MM

VOLTAGE= 3.3V

=PP3V3 _S3_P1 V8S0

=PP3V3 _S3_SMB US_SMC _MGMT

=PP3V3 _S3_MC P_GPIO

=PP3V3 _S3_WL AN

=PP1V8R1 V5_S0_MC P_MEM

MAKE_BASE=T RUE

PPMCPDDR _ISNS

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm VOLTAGE=1.5 V

=PP1V05_ S0_MCP_S ATA_DVDD

=PP3V3 _S0_GMU X

=PP3V3 _S0_HDC PROM

=PP3V3 _S0_MCP _GPIO

=PP3V3_ S0_P1V2P 2V5

=PP3V3 _S0_VMO N

=PP3V3 _FC_CO N

MIN_LINE _WIDTH=0 .60 MM

VOLTAGE= 5V

PP5V_S 0

MAKE_BAS E=TRUE

MIN_NECK _WIDTH=0 .20 MM

=PP5V_ S0_HDD

=PP5V_ S0_ODD

=PP3V3 _S3_TP AD

=PP3V3 _S3_RE MTHMSNS

=PP3V3 _S5_DP_ PORT_P WR

=PP3V3 _S5_P3 V3ENETF ET

=PP3V3 _S5_P1 V05ENET FET

=PP3V3 _S5_MCP PWRGD

=PP3V3 _S0_P3 V3S0FET

=PP3V3 _S5_RO M

=PP3V3 _FW_LA TEVG

MIN_LINE _WIDTH=0 .50MM MIN_NECK _WIDTH=0 .20MM

MAKE_BAS E=TRUE

PP3V3_ S3

VOLTAGE= 3.3V

=PP1V05_ S0_MCP_P EX_DVDD

PP1V05_ S0_MCP_P EX_AVDD

MAKE_BASE=T RUE

=PP1V05 _S5_MCP

=PPCPUVT T_S0_REG

=PP3V3 _S0_DPC ONN

=PP3V3 _S0_DPM UX

=PPVTT_ S0_DDR_L DO

MAKE_BASE=T RUE

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.3 mm

VOLTAGE=0.7 5V

PPVTTDDR _S3

PP0V9R0 V75_S0_D DRVTT

MIN_LINE_W IDTH=2 mm MIN_NECK_W IDTH=0.2 m m VOLTAGE=0. 9V MAKE_BASE= TRUE

=PP1V05_ S0_CPU

PPCPUVTT _S0

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm VOLTAGE=1.0 5V MAKE_BASE=T RUE

=PP1V05 _S0_MCP_ PEX_AVDD 0

=PP1V05 _S0_MCP_ PEX_DVDD 1

=PP1V05 _S0_MCP_ PEX_DVDD 0

=PP1V05_ S0_VMON

=PP1V05_ S0_MCP_H DMI_VDD

=PP1V05_ S0_MCP_S ATA_DVDD

=PP1V05_ S0_MCP_P LL_UF

=PP1V05_ S0_MCP_P EX_DVDD

=PP1V05_ S0_MCP_A VDD_UF

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm VOLTAGE=1.0 5V

PP1V05_S 0_REG

MAKE_BASE=T RUE

=PPMCPD DR_ISNS

=PP1V5_S 0_MEM_B

=PP1V5_S 0_MEM_A

=PPMCPDD R_ISNS_R

=PP1V5_S 0_CPU

=PP1V5_S 0_EXCARD

=PP1V5_S 0_VMON

=PP3V3 _GPU_LV DS_DDC

=PP3V3 _GPU_P WRCTL

MIN_LINE _WIDTH=0 .30MM

MAKE_BAS E=TRUE

PP3V3_ S0GPU

MIN_NECK _WIDTH=0 .20MM VOLTAGE= 3.3V

PP1V1_S0 GPU_REG

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.6 mm

MAKE_BASE=T RUE

VOLTAGE=1.1 V

=PP1V8 _GPUIFP X_REG

=PP3V3 _S0_FE T

=PP3V3 _S0_SMB US_MCP _0

=PPVBA T_G3H_ P3V42G3 H

=PPVIN _S3_DDR REG

=PPVIN _S0_P5 VRTS0_M CPCORE

=PPVIN _GPU_GP UVCORE

=PPBUS _S5_FWP WRSW

MIN_NECK _WIDTH=0 .25 mm VOLTAGE= 12.6V MAKE_BAS E=TRUE

MIN_LINE _WIDTH=0 .6 mm

PPDCIN _G3H

MAKE_BAS E=TRUE

VOLTAGE= 3.42V

PP3V42 _G3H

MIN_NECK _WIDTH=0 .2 mm

MIN_LINE _WIDTH=0 .3 mm

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .2 mm VOLTAGE= 3.3V MAKE_BAS E=TRUE

PP3V3_ S5

=PP3V3 _S5_MCP _GPIO

=PP3V3 _S5_MCP

=PP3V3 _S5_P1V 05FET

=PP3V3 _S5_PW RCTL

=PP3V3 _GPU_P 3V3GPUF ET

=PP3V3 _S5_LC D

62 13

24

12

46

24

59

79

74

52

76

22

46

21

11

38

13

24

22

58

76

73

74

24

43

24

76

75

25

78

68

64

44

14

49

24

12

46

95

24

19

53

24

10

25

24

12

43

95

20

24

38

69

36

67

20

7

8

32

45

8

61

7

69

63

45

48

62

6

47

49

22

7

83

34

21

69

64

46

61

50

46

60

32

80

39

54

29

28

7

68

49

82

48

45

7

83

77

7

77

75

82

70

72

7

9

72

67

73

71

47

28

29

18

69

29

28

34

22

69

78

31

7

31

7

78

42

44

45

69

86

69

34

33

18

24

7

62

7

75

6

18

7

71

47

46

82

37

36

7

65

64

24

63

26

9

65

66

40

7

27

67

62

40

64

41

43

62

49

69

23

63

37

30

48

63

60

17

27

43

9

20

69

7

51

82

44

66

46

67

51

69

7

30

7

25

24

21

11

51

67

61

41

60

46

52

85

7

32

44

47

43

7

67

45

21

31

16

7

8

83

25

18

86

68

32

7

39

50

48

81

34

26

69

44

38

7

8

24

67

66

81

80

64

7

6

7

17

68

18

8

24

8

24

7

47

29

28

47

11

32

68

80

68

7

67

69

45

60

64

65

78

37

7

18

22

69

68

69

79

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Frame Holes

Thermal Module Holes

MCP79 PCIe PRSNT# Straps

Digital Ground

If fou nd to be nece ssary, will move t o page1 4.csa

Exist in MRB but no t Inte l desi gns. Here fo r CYA.

Extra FSB Pull-ups

TM Hol e

CPU si gnals

TM Hol e TM Hol e

GPU si gnals

ETHERNET ALIASES

GMUX ALIASES

AUDIO ALIASES

Bottom Left GPU

Top GP U Righ t

Left C PU

TM Hol e

Right CPU

These ne ed work. Add ot her PRSN T# strap s if nee ded. .

Bosses for VRAM HS

STDOFF -4.5OD .98H-1 .1-3.4 8-TH

3R2P5

5% 1/16W

402

MF-LF

47K

5%

1/16W

402

0

MF-LF

17

10K

5% 1/16W MF-LF

402

SM

1%

MF-LF

402

10

1/16W

10

1/16W MF-LF

1%

402

STDOFF -4.5OD .98H-1 .1-3.4 8-TH

3R2P5

TH

SL-3.1X2. 7-6CIR-NSP

3R2P5

STDOFF -4.5OD .98H-1 .1-3.4 8-TH

402

0

5% 1/16W MF-LF

17

83

NO STU FF

5%

1/16W

0

402

MF-LF

STDOFF -4.5OD .98H-1 .1-3.4 8-TH

10 14 87

10 13 14 87

10 14 87

10 14 62 87

62

1/16W

402

5%

MF-LF

NO STU FF

220

MF-LF

402

5%

1/16W

NO STU FF

200

MF-LF

1/16W

5%

402

1%

150

MF-LF

1/16W

402

NO STU FF

1%

402

1/16W MF-LF

150

NO STU FF

STDOFF -4.0OD 3.0H-T H

VENICE

STDOFF -4.0OD 3.0H-T H

VENICE

STDOFF -4.0OD 3.0H-T H

1.4DIA -SHORT -EMI-M LB-M97 -M98

SM

4.0OD1 .65H-M 1.6X0. 35

0

5%

1/16W

402

MF-LF

SM

1.4DIA -SHORT -EMI-M LB-M97 -M98

SM

1.4DIA -SHORT -EMI-M LB-M97 -M98

SM

2.0DIA -TALL- EMI-ML B-M97- M98

SM

2.0DIA -TALL- EMI-ML B-M97- M98

SM

2.0DIA -TALL- EMI-ML B-M97- M98

SM

2.0DIA -TALL- EMI-ML B-M97- M98

SM

3R2P5

Signal Aliases

9 96

A.0.0

051-7546

SYNC_MA STER=( MASTER)

SYNC_DA TE=(MA STER)

MIN_NECK _WIDTH=0 .09MM

MIN_LINE _WIDTH=0 .6MM

VOLTAGE= 0V

GND

GND_CH ASSIS_ CLUTCH

GND_BA TT_CHG ND

GND_CH ASSIS_ USB

MAKE_BASE=T RUE

TP_LVDS _IG_B_CL KN

=PP1V0 5_S0_M CP_SATA _AVDD1

LVDS_B _DATA_ N<3>

MAKE_BAS E=TRUE

JTAG_G MUX_TD O

IG_LCD _PWR_E N

IG_BKL T_EN

MAKE_BAS E=TRUE

LVDS_I G_PANE L_PWR

LVDS_IG _BKL_PWM

MAKE_BASE=T RUE

NC_LVD S_IG_A _DATAP< 3>

MAKE_BASE=T RUE

NC_LVD S_B_DA TAP<3>

FSB_BR EQ0_L

CPU_IN TR

FC_PRS NT_L

MAKE_BASE=T RUE

PCIE_F C_R2D_ C_N

MAKE_BASE=T RUE

=MCP_HDM I_TXD_N< 0..2>

MAKE_BAS E=TRUE

PCIE_F W_PRSN T_L

LVDS_A _DATA_ P<3>

MAKE_BAS E=TRUE

NC_RTL 8211_R EGOUT

=RTL82 11_REG OUT

=RTL82 11_ENS WREG

=PP1V0 5_S0_M CP_SATA _DVDD1

PCIE_F C_D2R_ N

MAKE_BASE=T RUE

TP_PE4 _PRSNT _L

MCP_MI I_PD

MAKE_BAS E=TRUE

=MCP_M II_COL

GND_CH ASSIS_ FAN

TP_USB _EXTCP

MAKE_BAS E=TRUE

USB_EX TC_P

=DVI_H PD_GMU X_INT

USB_MI NI_N

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_LVDS_ A_DATAP< 3>

MAKE_BASE=T RUE

TP_LVDS _IG_B_CL KP

GPU_RESE T_L

MAKE_BASE=T RUE

DP_IG_DD C_DATA

=MCP_HDM I_DDC_CL K

DP_IG_ML _N<3>

MAKE_BASE=T RUE

=MCP_HDM I_TXC_N

DP_IG_ML _P<2..0>

MAKE_BASE=T RUE

=MCP_HDM I_TXD_P< 0..2>

=MCP_HDM I_TXC_P

MAKE_BASE= TRUE

PEG_R2D _C_P<0.. 15>

MAKE_BAS E=TRUE

PCIE_R ESET_L

VR_PWR GD_CLK EN_LTP_IMV P6_CLK EN_L

MAKE_BAS E=TRUE

MAKE_BASE=T RUE

CPU_VID< 0..6>

=MCP_BSE L<0..2>

=PEG_D2 R_P<0..1 5>

IMVP6_VI D<0..6>

CPU_BSEL <0..2>

MAKE_BASE=T RUE

MAKE_BAS E=TRUE

PM_SLP _RMGT_ L

LVDS_B_D ATA_N<3>

LVDS_A_D ATA_P<3>

LVDS_IG _B_CLK_N

LVDS_B _DATA_ P<3>

MAKE_BASE=T RUE

NC_LVD S_IG_A _DATAN< 3>

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_LVDS_ B_DATAN< 3>

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_LVDS_ B_DATAP< 3>

PCIE_C LK100M _FC_N

MAKE_BASE=T RUE

PCIE_F C_R2D_ C_P

=MCP_M II_CRS

=MCP_M II_RXE R

USB_EX TC_N

MAKE_BAS E=TRUE

TP_USB _MININ

MAKE_BAS E=TRUE

TP_USB _MINIP

USB_MI NI_P

USB_EX TD_N

USB_EX TD_P

VOLTAGE= 5V

PP5V_S 3_AUDI O_AMP

MIN_NECK _WIDTH=0 .25 mm

MIN_LINE _WIDTH=0 .5 mm

MAKE_BASE=T RUE

NC_LVD S_B_DA TAN<3>

MAKE_BASE=T RUE

NC_LVD S_A_DA TAP<3>

MAKE_BASE =TRUE

AUD_IP HS_SWI TCH_EN

PP5V_S 3_AUDI O

VOLTAGE= 5V

MIN_NECK _WIDTH=0 .25 mm

MIN_LINE _WIDTH=0 .5 mm

TP_USB _EXTDP

MAKE_BAS E=TRUE

NC_LVD S_IG_B _DATAP< 3>

MAKE_BASE=T RUE

TP_SPI_C S1_R_L_U SE_MLB

=DDRVTT_ ENMEM_VTT_ EN

MAKE_BASE=T RUE

=SPI_CS1 _R_L_USE _MLB

=PEG_D2 R_N<0..1 5>

MAKE_BASE= TRUE

PEG_D2R _N<0..15 >

LVDS_I G_B_DA TA_P<3>

LVDS_I G_A_DA TA_P<3>

LVDS_I G_A_DA TA_N<3>

LVDS_A _DATA_ N<3>

LVDS_I G_B_DA TA_N<3>

LVDS_A_D ATA_N<3>

MAKE_BASE=T RUE

TP_LVDS _IG_BKL_ PWM

TP_USB _EXTDN

MAKE_BAS E=TRUE

HDA_BI T_CLK

FC_RES ET_L

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_LVDS_ A_DATAN< 3>

=P3V3E NET_EN

=PP3V3 _ENET_ PHY_VDD REG

PCIE_F C_D2R_ P

MAKE_BASE=T RUE

CPU_DP RSTP_L

GND_CH ASSIS_ BATTCON N

=PP1V0 5_S0_M CP_FSB

TP_PP3 V3_ENE T_PHY_V DDREG

MAKE_BAS E=TRUE

PEG_PR SNT_L

=P1V05 ENET_E N

MAKE_BAS E=TRUE

TP_USB _EXTCN

MAKE_BASE=T RUE

DP_IG_ML _N<2..0>

LVDS_B_D ATA_P<3>

NC_LVD S_IG_B _DATAN< 3>

MAKE_BASE=T RUE

NC_LVD S_A_DA TAN<3>

MAKE_BASE=T RUE

CPU_NM I

GMUX_I NT

MAKE_BAS E=TRUE

PCIE_C LK100M _FC_P

MAKE_BASE=T RUE

TP_PCI E_CLK1 00M_PE4 N

MCP_SP KR

LVDS_IG _B_CLK_P

FC_CLK REQ_L

MAKE_BASE=T RUE

MEM_B_ A<15>

HDA_BI TCLK

MAKE_BAS E=TRUE

=PP5V_ S3_AUD IO_PWR

MAKE_BAS E=TRUE

TP_MEM _A_A<1 5>

GMUX_J TAG_TD O

MAKE_BAS E=TRUE

LVDS_I G_BKL_ ON

GMUX_J TAG_TM S

ALL_EG_P GOOD

DP_IG_ML _P<3>

MAKE_BASE=T RUE

MAKE_BAS E=TRUE

JTAG_G MUX_TD I

EG_RESET _L

MAKE_BASE=T RUE

MEM_A_ A<15>

SMC_MC P_SAFE _MODE

MAKE_BAS E=TRUE

TP_MEM _B_A<1 5>

EG_CLKRE Q_OUT_L

CPU_PE CI_MCP

TP_CPU _PECI_ MCP

MAKE_BAS E=TRUE

=PEG_R2 D_C_P<0. .15>

TP_PCI E_CLK1 00M_PE4 P

TP_PCI E_PE4_ R2D_CP

TP_PCI E_PE4_ R2D_CN

GMUX_J TAG_TD I

MAKE_BASE=T RUE

LCD_BKL T_EN

LVDS_BKL _ON

TP_MCP _GPIO_ 17

MAKE_BAS E=TRUE

AUD_IP _PERIP HERAL_D ET

TP_PCI E_PE4_ D2RN

TP_PCI E_PE4_ D2RP

TP_PE4 _CLKRE Q_L

=PEG_R2 D_C_N<0. .15>

MAKE_BASE= TRUE

PEG_R2D _C_N<0.. 15>

PEG_D2R _P<0..15 >

MAKE_BASE= TRUE

=PP1V8_G PU_FB_VR EF_B

GND_CH ASSIS_ SATA

=PP1V8_G PU_FB_VR EF_A

MAKE_BASE=T RUE

GPU_FB_A _VREF_DI V

MAKE_BASE=T RUE

GPU_FB_B _VREF_DI V

MAKE_BASE=T RUE

TP_LVDS_ MUX_SEL_ EG

LVDS_MUX _SEL_EG

=PP1V8_G PU_FB_VD DQ

DP_IG_DD C_CLK

MAKE_BASE=T RUE

=MCP_HDM I_DDC_DA TA

=MCP_HDM I_HPD

PM_ALL_G PU_PGOOD

MAKE_BASE=T RUE

DP_IG_HP D

MAKE_BASE=T RUE

MAKE_BAS E=TRUE

JTAG_G MUX_TM S

FSB_CP URST_L

GND_CH ASSIS_ LVDS

ZT0980

ZT0940

1

R0930

1

2

R0925

R0902

1 2

XW0900

12

XW0901

12

R0900

R0901

ZT0981

ZT0982

ZT0983

ZT0984

ZT0985

ZT0986

ZT0987

ZT0945

1

ZT0950

ZT0965

1

ZT0960

1

ZT0990

1

ZT0989

1

ZT0988

1

ZT0991

1

R0926

R0927

ZT0930

R0960

1

2

R0950

1

2

R0970

1

2

R0980

1

2

R0990

1

2

ZT0931

1

ZT0932

1

ZT0933

1

ZT0934

1

ZT0935

1

SH0910

1

ZT0951

1

ZT0952

1

ZT0953

1

R0903

SH0912

1

SH0911

1

SH0913

1

SH0902

1

SH0900

1

SH0903

1

SH0901

1

ZT0915

1

24 22

61

83

95

90

80

89

26

87 87

87

89

95

90

59

56

69

44

89

90

95

14

89

95

89

83

89

80

83

60

20

9

6

83

18

9

32

18

9

33

20

32

17

18

20

18

20

9

70

76

18

80 18

18

70

17

62

11

14

17

62

10

21

9

18

9

32

18

20

57

9

19

54

64 26

21

17 70

18

9

18

9

21

32

9

34

33

32

8

34

80

9

83

32

17

21

18

32 29

54

8

17

18

19

83

80

6

83

28

42

14

17

19

83 85

17

70

74

73

83

76

18

68

6

BI

IN

OUT

IN

BI

OUT

BI

OUT

IN

OUT

IN

OUT

BI

LOCK*

INIT*

A20M*

A6*

A3*

A4*

A14*

A16*

REQ0*

REQ1*

REQ2*

REQ3*

REQ4*

BCLK1

BCLK0

THERMTRI P*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20*

A21*

A22*

A23*

A24*

A26*

A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5

RSVD6

RSVD7

RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GRO UP1

ICH

RESERVED

ADDR GRO UP0

TEST7

TEST6

DSTBP1*

DINV1*

D31*

D30*

D25*

D11*

D12*

D13*

D14*

DSTBP0*

DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32*

D1*

D2*

D5*

D16*

D20*

D21*

D22*

D23*

D24*

D26*

D27*

D28*

D29*

DSTBN1*

GTLREF

TEST3

TEST4

TEST5

BSEL0

BSEL1

BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2*

DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3*

DSTBP3*

DINV3*

COMP0

COMP1

COMP2

COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

LAYOUT NOTE:

MAKE T RACE L ENGTH S HORTER THAN 0.5".

COMP0, 2 CONN ECT WIT H ZO=2 7.4OHM ,

MAKE T RACE L ENGTH S HORTER THAN 0.5".

COMP1, 3 CONN ECT WIT H ZO=5 5OHM,

PM_THR MTRIP# SHOULD CONNE CT TO I CH AND GMCH W ITHOUT T (NO STUB)

0.1" A WAY

PLACE TESTPO INT ON FSB_IE RR_L W ITH A G ND

0.5" M AX LEN GTH FOR CPU_G TLREF

REFERE NCED T O GND

PLACE C1000 CLOSE T O CPU_ TEST4 PIN. M AKE SU RE CPU_ TEST4 IS

402

MF-LF

54.9

1/16W

1%

MF-LF 402

1/16W

5%

68

402

1K

MF-LF

1%

1/16W

402

1/16W

2.0K

MF-LF

1%

402

54.9

1/16W MF-LF

1%

402

1%

MF-LF

1/16W

27.4

402

54.9

1/16W MF-LF

1%

402

27.4

1/16W MF-LF

1%

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

9

14 62 87

14 87

62

13 14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

9

87

9

87

9

87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

9

14 87

7

14 87

7

14 87

7

14 87

13 87

6

10 87

13 26

14 43 62 87

48 95

14 43 87

14 87

9

13 14 87

14 87

6

10 13 87

6

10 13 87

6

10 13 87

6

10 13 87

48 95

14 87

9

14 87

9

14 87

402

NOSTUF F

5%

MF-LF

1/16W

0

402

NOSTUF F

1K

MF-LF

5% 1/16W

402

54.9

MF-LF

1%

1/16W

402

54.9

1/16W MF-LF

1%

402

1%

MF-LF

1/16W

54.9

402

1%

MF-LF

1/16W

54.9

14 87

402

1%

MF-LF

1/16W

649

402

MF-LF

NOSTUF F

1K

5%

1/16W

402

16V

10%

0.1uF

NOSTUF F

X5R

402

PLACEM ENT_NO TE=Plac e R102 4 near ITP c onnecto r (if presen t)

54.9

1/16W MF-LF

1%

OMIT

PENRYN

FCBGA

OMIT

PENRYN

FCBGA

CPU FSB

10

A.0.0

051-7546

96

SYNC_MA STER=M 87_MLB

SYNC_DA TE=10/ 17/2007

XDP_TC K

XDP_TD O

XDP_TM S

XDP_TD I

XDP_TR ST_L

=PP1V0 5_S0_C PU

TP_CPU _RSVD8

TP_CPU _RSVD7

TP_CPU _RSVD6

TP_CPU _RSVD5

FSB_A_ L<5>

FSB_A_ L<15>

FSB_A_ L<10>

FSB_AD S_L

CPU_IG NNE_L

CPU_TH ERMD_N

FSB_A_ L<11>

FSB_A_ L<7> FSB_A_ L<8> FSB_A_ L<9>

FSB_A_ L<27>

FSB_A_ L<26>

FSB_A_ L<24>

FSB_A_ L<23>

FSB_A_ L<22>

FSB_A_ L<21>

FSB_A_ L<20>

FSB_BP RI_L

FSB_A_ L<12> FSB_A_ L<13>

FSB_AD STB_L< 0>

FSB_A_ L<17>

FSB_A_ L<19>

FSB_A_ L<28> FSB_A_ L<29> FSB_A_ L<30> FSB_A_ L<31> FSB_A_ L<32> FSB_A_ L<33> FSB_A_ L<34> FSB_A_ L<35> FSB_AD STB_L< 1>

CPU_FE RR_L

CPU_ST PCLK_L CPU_IN TR CPU_NM I CPU_SM I_L

TP_CPU _RSVD0 TP_CPU _RSVD1 TP_CPU _RSVD2 TP_CPU _RSVD3 TP_CPU _RSVD4

FSB_BN R_L

FSB_DE FER_L FSB_DR DY_L FSB_DB SY_L

FSB_BR EQ0_L

CPU_IE RR_L

FSB_CP URST_L FSB_RS _L<0> FSB_RS _L<1> FSB_RS _L<2> FSB_TR DY_L

FSB_HI T_L FSB_HI TM_L

XDP_BP M_L<0> XDP_BP M_L<1> XDP_BP M_L<2> XDP_BP M_L<3> XDP_BP M_L<4> XDP_BP M_L<5> XDP_TC K XDP_TD I XDP_TD O XDP_TM S XDP_TR ST_L XDP_DB RESET_ L

CPU_PR OCHOT_ L CPU_TH ERMD_P

PM_THR MTRIP_ L

FSB_CL K_CPU_ P FSB_CL K_CPU_ N

FSB_RE Q_L<4>

FSB_RE Q_L<3>

FSB_RE Q_L<2>

FSB_RE Q_L<0>

FSB_A_ L<4>

FSB_A_ L<3>

FSB_A_ L<6>

CPU_A2 0M_L

CPU_IN IT_L

FSB_LO CK_L

FSB_RE Q_L<1>

CPU_TE ST1

FSB_D_ L<10>

FSB_D_ L<15> FSB_DS TB_L_N <0>

FSB_D_ L<3> FSB_D_ L<4>

FSB_D_ L<17>

CPU_PS I_L

FSB_CP USLP_L

CPU_PW RGD

FSB_DP WR_L

CPU_DP SLP_L

CPU_DP RSTP_L

CPU_CO MP<3>

CPU_CO MP<2>

CPU_CO MP<1>

CPU_CO MP<0>

FSB_DI NV_L<3 >

FSB_DS TB_L_P <3>

FSB_DS TB_L_N <3>

FSB_D_ L<63>

FSB_D_ L<62>

FSB_D_ L<61>

FSB_D_ L<60>

FSB_D_ L<59>

FSB_D_ L<58>

FSB_D_ L<57>

FSB_D_ L<56>

FSB_D_ L<55>

FSB_D_ L<54>

FSB_D_ L<53>

FSB_D_ L<52>

FSB_D_ L<51>

FSB_D_ L<50>

FSB_D_ L<49>

FSB_D_ L<48>

FSB_DI NV_L<2 >

FSB_DS TB_L_P <2>

FSB_DS TB_L_N <2>

FSB_D_ L<47>

FSB_D_ L<46>

FSB_D_ L<45>

FSB_D_ L<44>

FSB_D_ L<43>

FSB_D_ L<42>

FSB_D_ L<41>

FSB_D_ L<40>

FSB_D_ L<39>

FSB_D_ L<38>

FSB_D_ L<37>

FSB_D_ L<36>

FSB_D_ L<35>

FSB_D_ L<34>

FSB_D_ L<33>

CPU_BS EL<2>

CPU_BS EL<1>

CPU_BS EL<0>

TP_CPU _TEST5

CPU_TE ST4

TP_CPU _TEST3

CPU_GT LREF

FSB_DS TB_L_N <1>

FSB_D_ L<29>

FSB_D_ L<28>

FSB_D_ L<27>

FSB_D_ L<26>

FSB_D_ L<24>

FSB_D_ L<23>

FSB_D_ L<22>

FSB_D_ L<21>

FSB_D_ L<20>

FSB_D_ L<16>

FSB_D_ L<5>

FSB_D_ L<2>

FSB_D_ L<1>

FSB_D_ L<32>

FSB_D_ L<0>

FSB_D_ L<18> FSB_D_ L<19>

FSB_D_ L<6> FSB_D_ L<7> FSB_D_ L<8> FSB_D_ L<9>

FSB_DI NV_L<0 >

FSB_DS TB_L_P <0>

FSB_D_ L<14>

FSB_D_ L<13>

FSB_D_ L<12>

FSB_D_ L<11>

FSB_D_ L<25>

FSB_D_ L<30> FSB_D_ L<31>

FSB_DI NV_L<1 >

FSB_DS TB_L_P <1>

CPU_TE ST2

TP_CPU _TEST7

TP_CPU _TEST6

=PP1V0 5_S0_C PU

FSB_A_ L<25>

FSB_A_ L<18>

FSB_A_ L<16>

FSB_A_ L<14>

R1002

1

2

R1004

1

2

R1005

1

2

R1006

1

2

R1019

R1018

R1017

R1016

R1030

R1007

1

2

R1003

1

2

R1020

R1021

R1022

R1023

R1012

1

2

C1000

1

2

R1024

U1000

N3

P5

P2

L2

P4

P1

R1

Y2

U5

R3

W6

A6

U4

Y5

U1

R4

T5

T3

W2

W5

Y4

J4

U2

V4

W3

AA4

AB2

AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22

A21

E2

AD4

AD3

AD1

AC4

G5

F1

C20

E1

H5

F21

A5

G6

E4

D20

C4

B3

C6

B4

H4

AC2

AC1

D21

K3

H2

K2

J3

L1

C1

F3

F4

G3

M4

N5

T2

V3

B2

F6

D2

D22

D3

A3

D5

AC5

AA6

AB3

A24

B25

C7

AB5

G2

AB6

U1000

B22

B23

C21

R26

U26

AA1

Y1

E22

F24

J24

J23

H22

F26

K22

H23

N22

K25

P26

R23

E26

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

G22

T25

N25

Y22

AB24

V24

V26

V23

T22

U25

U23

F23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

AE24

AD24

G25

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

E25

AC22

AD23

AF22

AC23

E23

K24

G24

H25

N24

U22

AC20

E5

B5

D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6

D7

C23

D25

C24

AF26

AF1

A26

C3

62

13

12

87

11

13

87

13

10

8

87

8

6

87

87 27

6

OUT

VCC

VCCP

VCCA

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

17.0 A (Auto -Halt/S top-Gr ant Su perLFM )

30.4 A (LFM)

2500 m A (aft er VCC stable )

4500 m A (bef ore VCC stabl e)

16.0 A (Deep Sleep SuperL FM)

16.8 A (Slee p Super LFM)

41.0 A (HFM)

(CPU C ORE PO WER)

130 mA

(CPU I O POWE R 1.05V )

(CPU I NTERNA L PLL P OWER 1 .5V)

Low Voltage:

23.0 A (Desi gn Targ et)

18.7 A (LFM) TBD A (Supe rLFM)

TBD A (Slee p Super LFM)

TBD A (Deep er Slee p)

TBD A (Slee p HFM)

TBD A (Auto -Halt/S top-Gr ant HF M)

TBD A (HFM) TBD A (LFM)

Curren t numb ers fro m Mero m for Santa Rosa EM TS, do c #222 21.

TBD A (Auto -Halt/S top-Gr ant LF M)

TBD A (Slee p LFM)

25.5 A (Supe rLFM)

27.4 A (Slee p HFM)

25.0 A (Deep Sleep HFM)

11.5 A (Deep er Slee p)

9.4 A (Enha nced De eper S leep)

TBD A (Slee p HFM)

21.0 A (HFM)

TBD A (Deep Sleep HFM)

TBD A (Auto -Halt/S top-Gr ant Su perLFM )

TBD A (Auto -Halt/S top-Gr ant HF M)

TBD A (Enha nced De eper S leep)

TBD A (Deep er Slee p)

TBD A (Deep Sleep LFM)

TBD A (Deep Sleep HFM)

TBD A (Deep Sleep SuperL FM)

27.4 A (Auto -Halt/S top-Gr ant HF M)

44.0 A (Desi gn Targ et)

Standard Voltage:

Ultra Low Voltage:

17.0 A (Desi gn Targ et)

TBD A (Enha nced De eper S leep)

9

87

9

87

9

87

9

87

9

87

9

87

PLACEMEN T_NOTE=P lace wit hin 1 in ch of CP U, no st ub.

MF-LF 402

100

1% 1/16W

9

87

62 87

MF-LF 402

PLACEMEN T_NOTE=P lace wit hin 1 in ch of CP U, no st ub.

1/16W

1%

100

OMIT

PENRYN

FCBGA

OMIT

PENRYN

FCBGA

SYNC_DA TE=10/ 17/2007

SYNC_MA STER=M 87_MLB

CPU Power & Ground

051-7546

A.0.0

11 9 6

=PPVCO RE_S0_ CPU

CPU_VC CSENSE _N

CPU_VC CSENSE _P

CPU_VI D<6>

CPU_VI D<5>

CPU_VI D<4>

CPU_VI D<3>

CPU_VI D<2>

CPU_VI D<1>

CPU_VI D<0>

=PP1V5 _S0_CP U

=PP1V0 5_S0_C PU

=PPVCO RE_S0_ CPU

R1101

1

2

R1100

1

2

U1000

A7

A9

B9

B10

B12

B14

B15

B17

B18

B20

C9

C10

A10

C12

C13

C15

C17

C18

D9

D10

D12

D14

D15

A12

D17

D18

E7

E9

E10

E12

E13

E15

E17

E18

A13

E20

F7

F9

F10

F12

F14

F15

F17

F18

F20

A15

AA7

AA9

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AB9

A17

AC10

AB10

AB12

AB14

AB15

AB17

AB18

AB20

AB7

AC7

A18

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

A20

AD14

AD15

AD17

AD18

AE9

AE10

AE12

AE13

AE15

AE17

B7

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

B26

C26

G21

V6

R21

R6

T21

T6

V21

W21

J6

K6

M6

J21

K21

M21

N21

N6

AF7

AD6

AF5

AE5

AF4

AE3

AF3

AE2

AE7

U1000

A4

A8

B11

W1

W4

W23

W26

Y3

Y6

Y21

Y24

AA2

AA5

B13

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

B16

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

B19

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

B21

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

B24

AE19

AE23

AE26

A2

AF6

AF8

AF11

AF13

AF16

AF19

C5

AF21

A25

AF25

B1

C8

C11

C14

A11

C16

C19

C2

C22

C25

D1

D4

D8

D11

D13

A14

D16

D19

D23

D26

E3

E6

E8

E11

E14

E16

A16

E19

E21

E24

F5

F8

F11

F13

F16

F19

F2

A19

F22

F25

G4

G1

G23

G26

H3

H6

H21

H24

A23

J2

J5

J22

J25

K1

K4

K23

K26

L3

L6

AF2

L21

L24

M2

M5

M22

M25

N1

N4

N23

N26

B6

P3

P6

P21

P24

R2

R5

R22

R25

T1

T4

B8

T23

T26

U3

U6

U21

U24

V2

V5

V22

V25

62 13

46

12

46

12

10

12

11

12

8

11

8

6

8

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

1x 10uF, 1x 0.01uF

CPU VCORE HF AND BULK DECOUPLING

4x 330uF, 20x 22uF 0805

1x 470uF, 6x 0.1uF 0402

VCCP (CPU I/O) DECOUPLING

WF: Co nsider sharin g bulk cap w ith NB Vtt?

VCCA (CPU AVdd) DECOUPLING

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

2.5V

D2T

20%

470UF

POLY

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

22UF

X5R-CERM 603

6.3V

20%

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

6.3V

20%

22UF

603

X5R-CERM

CRITIC AL

20%

X5R-CERM 603

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM

22UF

603

20%

6.3V

CRITIC AL

X5R-CERM

22UF

6.3V

20%

603

CRITIC AL

22UF

X5R-CERM 603

20%

6.3V

20%

0.1UF

CERM 402

10V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

22UF

X5R-CERM 603

20%

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

20%

CERM 402

0.1UF

10V

20%

CERM 402

0.1UF

10V

20%

0.1UF

CERM 402

10V

20%

CERM 402

0.1UF

10V

20%

CERM 402

0.1UF

10V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

PLACEMEN T_NOTE=P lace nea r CPU pi n B26.

CERM 402

16V

10%

0.01UF

X5R

6.3V

20%

10uF

603

20%

D2T-SM2

POLY-TANT

2.0V

330UF

CRITIC AL

PLACEMEN T_NOTE=P lace in CPU cent er cavit y.

CRITIC AL

330UF

20%

POLY-TANT

D2T-SM2

PLACEMEN T_NOTE=P lace in CPU cent er cavit y.

2.0V

20%

POLY-TANT

CRITIC AL

330UF

2.0V

PLACEMEN T_NOTE=P lace in CPU cent er cavit y.

D2T-SM2

PLACEMEN T_NOTE=P lace in CPU cent er cavit y.

20%

D2T-SM2

POLY-TANT

CRITIC AL

330UF

2.0V

CPU Decoupling & VID

SYNC_MA STER=M 87_MLB

9612

A.0.0

SYNC_DA TE=10/ 17/2007

051-7546

=PP1V5 _S0_CP U

=PPVCO RE_S0_ CPU

=PP1V0 5_S0_C PU

C1208C1207

C1219C1218

C1206C1204

C1216C1214

C1203C1202C1201

C1213C1212C1211

C1200

1

2

C1210

C1236

1

2

C1205 C1209

C1215 C1217

C1237

1

2

C1238

1

2

C1239

1

2

C1240

1

2

C1241

1

2

C1281

1

2

C1280

1

2

C1250

1

2 3

C1251

1

2 3

C1252

1

2 3

C1253

1

2 3

C1235

1

2 3

62 13 11

46

10

11

8

6

IN

BI

OUT

IN

BI

IN

OUT

BI

OUT

IN

OUT

NC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

TCK0

OBSDAT A_A3

OBSDAT A_A1

OBSFN_ C0

OBSDAT A_C0 OBSDAT A_C1

OBSDAT A_C3

Mini-XDP Connector

VCC_OB S_CD

DBR#/H OOK7

Please avoid any ob struct ions on eve n-numb ered si de of J1300

NOTE: This is not the standard XDP pinout.

VCC_OB S_AB

TDO

TDI

RESET# /HOOK6

OBSFN_ D0

SCL

SDA

TRSTn

HOOK3

HOOK2

HOOK1

TMS

OBSDAT A_D0

TCK1

OBSDAT A_B2

PWRGD/ HOOK0

OBSFN_ D1

OBSDAT A_B3

XDP_PR ESENT#

NOTE: XDP_DB RESET_L must be pul led-up to 3.3 V.

OBSFN_ B0

OBSDAT A_C2

OBSFN_ C1

Direction of XDP module

998-1571

ITPCLK #/HOOK 5

ITPCLK /HOOK4

OBSDAT A_D3

OBSDAT A_D2

OBSDAT A_D1OBSDAT A_B1

OBSDAT A_B0

OBSFN_ B1

OBSDAT A_A2

OBSDAT A_A0

OBSFN_ A1

OBSFN_ A0

Use wi th 920 -0620 a dapter board to su pport C PU, MC P debu gging.

MCP79-specific pinout

10 14 87

1K

402

MF-LF

XDP

5%

1/16W

7

21 45 90

7

21 45 90

54.9

MF-LF

1/16W

1%

402

XDP

402

0.1uF

XDP

16V

10%

X5R X5R

10%

0.1uF

XDP

16V

402

10 87

6

10 87

9

10 14 87

XDP

402

MF-LF

1/16W

5%

1K

PLACEMEN T_NOTE=P lace clo se to CP U to min imize st ub.

10 87

6

21

6

21 23

6

21 23

19 90

6

21

6

14 87

6

10 87

6

10 87

6

10 87

10 26

19 23

F-ST-SM

LTH-03 0-01-G- D-NOPE GS

CRITIC AL XDP_CO NN

SYNC_DA TE=01/ 08/2008

051-7546

SYNC_MA STER=M 99_MLB

13

A.0.0

96

eXtended Debug Port(MiniXDP)

FSB_CP URST_L

CPU_PW RGD

XDP_TM S

XDP_TD O_CONN XDP_TR ST_L XDP_TD I

FSB_CL K_ITP_ N

FSB_CL K_ITP_ P

MCP_DE BUG<5>

JTAG_M CP_TMS

MCP_DE BUG<3>

MCP_DE BUG<1>

JTAG_M CP_TRS T_L

JTAG_M CP_TDO _CONN

XDP_BP M_L<5> XDP_BP M_L<4>

XDP_BP M_L<2>

XDP_BP M_L<1> XDP_BP M_L<0>

TP_XDP _OBSFN _B1

TP_XDP _OBSDA TA_B1

TP_XDP _OBSDA TA_B0

XDP_PW RGD

TP_XDP _OBSDA TA_B3

XDP_OB S20

PM_LAT RIGGER _L JTAG_M CP_TCK

SMBUS_ MCP_0_ CLK

SMBUS_ MCP_0_ DATA

XDP_TC K

MCP_DE BUG<0>

XDP_DB RESET_ L

XDP_CP URST_L

MCP_DE BUG<7>

MCP_DE BUG<6>

MCP_DE BUG<4>

JTAG_M CP_TDI

MCP_DE BUG<2>

TP_XDP _OBSDA TA_B2

=PP1V0 5_S0_C PU

=PP3V3 _S0_XD P

XDP_BP M_L<3>

TP_XDP _OBSFN _B0

R1399

1 2

R1315

1

2

C1300

1

2

C1301

1

2

R1303

1 2

J1300

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

78

9

62 12 11 10

8

87

6

IN

OUT

BI

IN

BI

OUT

IN

BI

CPU_BR0#

CPU_BNR#

BCLK_OUT _NB_N

CPU_BR1#

CPU_REQ4 #

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28#

CPU_A29#

CPU_A30#

CPU_A31#

CPU_A32#

CPU_A22#

CPU_A23#

CPU_A24#

CPU_REQ3 #

CPU_REQ2 #

CPU_DBI3 #

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR #

CPU_RS1#

BCLK_VML _COMP_GN D

CPU_COMP _VCC

CPU_TRDY #

CPU_PROC HOT#

CPU_BSEL 0

CPU_RS2#

CPU_BSEL 1

BCLK_IN_ P

BCLK_OUT _CPU_N

CPU_PWRG D

CPU_DSTB P0#

CPU_DSTB P1#

CPU_DBI1 #

CPU_DBI0 #

CPU_DSTB N1#

CPU_DSTB N0#

CPU_DBI2 #

CPU_DSTB P2#

CPU_DSTB N2#

CPU_DSTB P3#

CPU_A4#

CPU_DSTB N3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6#

CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15#

CPU_A16#

CPU_A19#

CPU_A17#

CPU_A18#

CPU_A20#

CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADST B0#

CPU_REQ0 #

CPU_LOCK #

CPU_HIT#

CPU_HITM #

CPU_FERR #

CPU_THER MTRIP#

CPU_PECI

CPU_COMP _GND

CPU_D0#

CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4#

CPU_D5#

CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17#

CPU_D18#

CPU_D16#

CPU_D19#

CPU_D20#

CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24#

CPU_D25#

CPU_D26#

CPU_D27#

CPU_D28#

CPU_D29#

CPU_D30#

CPU_D31#

CPU_D32#

CPU_D33#

CPU_D34#

CPU_D35#

CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39#

CPU_D40#

CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44#

CPU_D45#

CPU_D46#

CPU_D47#

CPU_D52#

CPU_D53#

CPU_D54#

CPU_D55#

CPU_D56#

CPU_D57#

CPU_D58#

CPU_D59#

CPU_D63#

CPU_BPRI #

CPU_DEFE R#

BCLK_OUT _CPU_P

BCLK_OUT _ITP_P

BCLK_OUT _ITP_N

BCLK_OUT _NB_P

BCLK_IN_ N

CPU_A20M #

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESE T#

CPU_SLP#

CPU_DPSL P#

CPU_STPC LK#

CPU_DPRS TP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADST B1#

CPU_IGNN E#

CPU_INIT #

BCLK_VML _COMP_VD D

CPU_RS0#

+V_DLL_D LCELL_AV DD

+V_PLL_M CLK

+V_PLL_F SB

+V_PLL_C PU

CPU_A10#

CPU_BSEL 2

CPU_DBSY #

CPU_DRDY #

CPU_REQ1 #

FSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

270 mA (A01) 206 mA

15 mA

29 mA

20 mA

(MCP_B SEL<0> )

(MCP_B SEL<1> )

(MCP_B SEL<2> )

Loop-b ack cl ock for delay match ing.

9

10 87

9

10 13 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

9

10 87

7

10 87

7

10 87

7

10 87

13 87

10 87

9

10 87

9

10 87

10 13 87

10 87

9

10 62 87

9

10 43 62 87

10 43 87

10 87

49.9

1/16W

1%

402

MF-LF

1/16W

1%

402

MF-LF

49.9

MF-LF

402

1%

1/16W

49.9

1/16W

1%

402

MF-LF

NO STU FF

1K

402

5% 1/16W MF-LF

1K

NO STU FF

402

MF-LF

5%

1/16W

1K

5%

402

MF-LF

NO STU FF

1/16W

402

MF-LF

62

5%

1/16W

402

MF-LF

54.9

1%

NO STU FF

150

1/16W

402

MF-LF

5%

OMIT

MCP79- TOPO-B

(1 OF 11 )

BGA

1/16W

402

MF-LF

62

5%

A.0.0

SYNC_DA TE=06/ 18/2008

MCP CPU Interface

051-7546

9614

SYNC_MA STER=T 18_MLB

PM_THR MTRIP_ L

FSB_D_ L<13>

MCP_BC LK_VML _COMP_G ND

FSB_DP WR_L

CPU_DP SLP_L

FSB_D_ L<38>

FSB_D_ L<43>

FSB_D_ L<45>

CPU_DP RSTP_L

CPU_ST PCLK_L

FSB_CP USLP_L

FSB_CP URST_L

CPU_PW RGD

CPU_SM I_L

CPU_NM I

CPU_IN TR

CPU_IN IT_L

CPU_IG NNE_L

CPU_A2 0M_L

FSB_CL K_MCP_ P FSB_CL K_MCP_ N

FSB_CL K_ITP_ N

FSB_CL K_ITP_ P

FSB_CL K_CPU_ N

FSB_CL K_CPU_ P

FSB_DE FER_L

FSB_BP RI_L

FSB_D_ L<63>

FSB_D_ L<62>

FSB_D_ L<61>

FSB_D_ L<60>

FSB_D_ L<59>

FSB_D_ L<58>

FSB_D_ L<57>

FSB_D_ L<56>

FSB_D_ L<55>

FSB_D_ L<54>

FSB_D_ L<53>

FSB_D_ L<52>

FSB_D_ L<51>

FSB_D_ L<50>

FSB_D_ L<49>

FSB_D_ L<48>

FSB_D_ L<47>

FSB_D_ L<46>

FSB_D_ L<44>

FSB_D_ L<42>

FSB_D_ L<41>

FSB_D_ L<40>

FSB_D_ L<39>

FSB_D_ L<37>

FSB_D_ L<36>

FSB_D_ L<35>

FSB_D_ L<34>

FSB_D_ L<33>

FSB_D_ L<32>

FSB_D_ L<31>

FSB_D_ L<30>

FSB_D_ L<29>

FSB_D_ L<28>

FSB_D_ L<27>

FSB_D_ L<26>

FSB_D_ L<25>

FSB_D_ L<24>

FSB_D_ L<23>

FSB_D_ L<22>

FSB_D_ L<21>

FSB_D_ L<20>

FSB_D_ L<19>

FSB_D_ L<18>

FSB_D_ L<17>

FSB_D_ L<16>

FSB_D_ L<15>

FSB_D_ L<12>

FSB_D_ L<11>

FSB_D_ L<10>

FSB_D_ L<9>

FSB_D_ L<8>

FSB_D_ L<6>

FSB_D_ L<5>

FSB_D_ L<4>

FSB_D_ L<3>

FSB_D_ L<2>

FSB_D_ L<1>

FSB_D_ L<0>

MCP_CP U_COMP _GND

MCP_CP U_COMP _VCC

MCP_BC LK_VML _COMP_V DD

FSB_RS _L<2>

FSB_RS _L<1>

CPU_PR OCHOT_ L

CPU_PE CI_MCP

FSB_TR DY_L

FSB_LO CK_L

FSB_HI TM_L

FSB_HI T_L

FSB_RE Q_L<4>

FSB_RE Q_L<3>

FSB_RE Q_L<2>

FSB_RE Q_L<1>

FSB_RE Q_L<0>

FSB_AD STB_L< 1>

FSB_AD STB_L< 0>

FSB_A_ L<35>

FSB_A_ L<32>

FSB_A_ L<31>

FSB_A_ L<30>

FSB_A_ L<29>

FSB_A_ L<28>

FSB_A_ L<27>

FSB_A_ L<26>

FSB_A_ L<24>

FSB_A_ L<23>

FSB_A_ L<22>

FSB_A_ L<21>

FSB_A_ L<20>

FSB_A_ L<19>

FSB_A_ L<18>

FSB_A_ L<17>

FSB_A_ L<16>

FSB_A_ L<15>

FSB_A_ L<14>

FSB_A_ L<13>

FSB_A_ L<12>

FSB_A_ L<11>

FSB_A_ L<9>

FSB_A_ L<8>

FSB_A_ L<7>

FSB_A_ L<6>

FSB_A_ L<5>

FSB_A_ L<4>

FSB_A_ L<3>

FSB_DI NV_L<3 >

FSB_DS TB_L_N <3>

FSB_DS TB_L_P <3>

FSB_DI NV_L<2 >

FSB_DS TB_L_N <2>

FSB_DS TB_L_P <2>

FSB_DI NV_L<1 >

FSB_DS TB_L_N <1>

FSB_DS TB_L_P <1>

FSB_DI NV_L<0 >

FSB_DS TB_L_N <0>

FSB_DS TB_L_P <0>

=PP1V0 5_S0_M CP_FSB

PP1V05 _S0_MC P_PLL_F SB

FSB_D_ L<14>

FSB_D_ L<7>

FSB_A_ L<10>

FSB_A_ L<25>

FSB_A_ L<34>

FSB_A_ L<33>

FSB_DB SY_L FSB_DR DY_L

FSB_BN R_L

FSB_RS _L<0>

CPU_FE RR_L

FSB_BR EQ0_L

FSB_AD S_L

FSB_BR EQ1_L

=PP1V0 5_S0_M CP_FSB

=MCP_B SEL<2>

=MCP_B SEL<0>

=MCP_B SEL<1>

R1436

1

2

R1431

1

2

R1430

1

2

R1435

1

2

R1422

1

2

R1421

1

2

R1420

1

2

R1415

1

2

R1410

1

2

R1440

1

2

U1400

AK41

AJ40

G41

G42

AL42

AL43

AK42

AL41

AM40

AM39

AF35

AG35

AG39

AE33

AG37

AG38

AG34

AN38

AL39

AG33

AL33

AF41

AJ33

AN36

AJ35

AJ37

AJ36

AJ38

AL37

AL34

AN37

AC34

AJ34

AL38

AL35

AN34

AR39

AN35

AE38

AE34

AC37

AE37

AE35

AB35

AD42

AE36

AK35

AD43

AA41

AE40

AL32

F41

D42

F42

AM42

AM43

Y43

W42

R42

T39

T42

T41

R41

T43

W35

AA37

W33

W34

Y40

AA36

AA34

AA38

AA35

U38

U36

U35

U33

U34

W38

W41

R33

U37

N34

N33

R34

R35

P35

R39

R37

R38

Y39

L37

L39

L38

N36

N38

J39

J38

J37

L42

M42

V42

P41

N41

N40

M40

H40

K42

H41

L41

H43

H42

Y41

K41

J40

H39

M43

Y42

P42

U41

V41

V35

N35

J41

AD39

AA40

AN32

AN33

AM32

AD41

U40

W37

L36

M41

T40

W39

N37

M39

AH40

AB42

AD40

AH39

AH42

AF42

AC43

AG41

E41

AJ41

AH43

AC38

AA33

AC39

AC33

AC35

H38

AC41

AB41

AC42

AM33

AH41

AG42

AG43

AE41

AG27

AH28

AG28

AH27

R1416

1

2

24

22

14

14 9 9

87

8

24

87

8

0A

MEMORY

MEMORY PARTITION 0

CONTRO L

MCKE0A_1

MCKE0A_0

MODT0A_1

MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0 _N

MCLK0A_0 _P

MCLK0A_1 _N

MCLK0A_2 _N

MCLK0A_1 _P

MCLK0A_2 _P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8

MA0_7

MA0_9

MA0_10

MA0_11

MA0_13

MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_ P

MDQS0_0_ N

MDQS0_1_ P

MDQS0_2_ N

MDQS0_1_ N

MDQS0_2_ P

MDQS0_3_ N

MDQS0_4_ P

MDQS0_3_ P

MDQS0_4_ N

MDQS0_5_ N

MDQS0_5_ P

MDQS0_6_ N

MDQS0_6_ P

MDQS0_7_ N

MDQS0_7_ P

MDQM0_2

MDQM0_1

MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4

MDQ0_3

MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9

MDQ0_8

MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15

MDQ0_14

MDQ0_13

MDQ0_12

MDQ0_16

MDQ0_21

MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25

MDQ0_24

MDQ0_23

MDQ0_22

MDQ0_26

MDQ0_29

MDQ0_28

MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35

MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40

MDQ0_39

MDQ0_42

MDQ0_47

MDQ0_46

MDQ0_43

MDQ0_45

MDQ0_44

MDQ0_51

MDQ0_50

MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55

MDQ0_54

MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61

MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

BI

OUT

BI

OUT

MEMORY

CONTRO L

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60

MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56

MDQ1_55

MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51

MDQ1_50

MDQ1_48

MDQ1_47

MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42

MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36

MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31

MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26

MDQ1_25

MDQ1_24

MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11

MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6

MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4

MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_ P

MDQS1_6_ N

MDQS1_6_ P

MDQS1_7_ N

MDQS1_5_ N

MDQS1_5_ P

MDQS1_4_ P

MDQS1_3_ P

MDQS1_4_ N

MDQS1_2_ P

MDQS1_3_ N

MDQS1_1_ P

MDQS1_2_ N

MDQS1_1_ N

MDQS1_0_ P

MDQS1_0_ N

MRAS1#

MCAS1#

MWE1#

MBA1_2

MBA1_1

MBA1_0

MA1_14

MA1_13

MA1_12

MA1_11

MA1_10

MA1_9

MA1_8

MA1_7

MA1_6

MA1_5

MA1_4

MA1_3

MA1_2

MA1_1

MA1_0

MCLK1A_2 _P

MCLK1A_1 _P

MCLK1A_2 _N

MCLK1A_0 _P

MCLK1A_1 _N

MCS1A_1#

MCS1A_0#

MCLK1A_0 _N

MODT1A_1

MODT1A_0

MCKE1A_0

MCKE1A_1

BI

OUT

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

BGA

MCP79- TOPO-B

OMIT

(2 OF 11 )

28 88

29 88

BGA

MCP79- TOPO-B

OMIT

(3 OF 11 )

29 88

96

051-7546

A.0.0

15

SYNC_MA STER=T 18_MLB

SYNC_DA TE=06/ 18/2008

MCP Memory Interface

MEM_B_ DM<0>

MEM_B_ DM<1>

MEM_B_ DM<2>

MEM_B_ DM<3>

MEM_B_ DM<4>

MEM_B_ DM<5>

MEM_B_ DM<6>

MEM_B_ DM<7>

MEM_B_ DQ<0>

MEM_B_ DQ<1>

MEM_B_ DQ<2>

MEM_B_ DQ<3>

MEM_B_ DQ<4>

MEM_B_ DQ<5>

MEM_B_ DQ<6>

MEM_B_ DQ<7>

MEM_B_ DQ<8>

MEM_B_ DQ<9>

MEM_B_ DQ<10>

MEM_B_ DQ<11>

MEM_B_ DQ<12>

MEM_B_ DQ<13>

MEM_B_ DQ<14>

MEM_B_ DQ<15>

MEM_B_ DQ<16>

MEM_B_ DQ<17>

MEM_B_ DQ<18>

MEM_B_ DQ<19>

MEM_B_ DQ<20>

MEM_B_ DQ<21>

MEM_B_ DQ<22>

MEM_B_ DQ<23>

MEM_B_ DQ<24>

MEM_B_ DQ<25>

MEM_B_ DQ<26>

MEM_B_ DQ<27>

MEM_B_ DQ<28>

MEM_B_ DQ<29>

MEM_B_ DQ<30>

MEM_B_ DQ<31>

MEM_B_ DQ<32>

MEM_B_ DQ<33>

MEM_B_ DQ<34>

MEM_B_ DQ<35>

MEM_B_ DQ<36>

MEM_B_ DQ<37>

MEM_B_ DQ<38>

MEM_B_ DQ<39>

MEM_B_ DQ<40>

MEM_B_ DQ<41>

MEM_B_ DQ<42>

MEM_B_ DQ<43>

MEM_B_ DQ<44>

MEM_B_ DQ<45>

MEM_B_ DQ<46>

MEM_B_ DQ<47>

MEM_B_ DQ<48>

MEM_B_ DQ<49>

MEM_B_ DQ<50>

MEM_B_ DQ<51>

MEM_B_ DQ<52>

MEM_B_ DQ<53>

MEM_B_ DQ<54>

MEM_B_ DQ<55>

MEM_B_ DQ<56>

MEM_B_ DQ<57>

MEM_B_ DQ<58>

MEM_B_ DQ<59>

MEM_B_ DQ<60>

MEM_B_ DQ<61>

MEM_B_ DQ<62>

MEM_B_ DQ<63>

MEM_A_ DM<0>

MEM_A_ DM<1>

MEM_A_ DM<2>

MEM_A_ DM<3>

MEM_A_ DM<4>

MEM_A_ DM<5>

MEM_A_ DM<6>

MEM_A_ DM<7>

MEM_A_ DQ<0>

MEM_A_ DQ<1>

MEM_A_ DQ<2>

MEM_A_ DQ<3>

MEM_A_ DQ<4>

MEM_A_ DQ<5>

MEM_A_ DQ<6>

MEM_A_ DQ<7>

MEM_A_ DQ<8>

MEM_A_ DQ<9>

MEM_A_ DQ<10>

MEM_A_ DQ<11>

MEM_A_ DQ<12>

MEM_A_ DQ<13>

MEM_A_ DQ<14>

MEM_A_ DQ<15>

MEM_A_ DQ<16>

MEM_A_ DQ<17>

MEM_A_ DQ<18>

MEM_A_ DQ<19>

MEM_A_ DQ<20>

MEM_A_ DQ<21>

MEM_A_ DQ<22>

MEM_A_ DQ<23>

MEM_A_ DQ<24>

MEM_A_ DQ<25>

MEM_A_ DQ<26>

MEM_A_ DQ<27>

MEM_A_ DQ<28>

MEM_A_ DQ<29>

MEM_A_ DQ<30>

MEM_A_ DQ<31>

MEM_A_ DQ<32>

MEM_A_ DQ<33>

MEM_A_ DQ<34>

MEM_A_ DQ<35>

MEM_A_ DQ<36>

MEM_A_ DQ<37>

MEM_A_ DQ<38>

MEM_A_ DQ<39>

MEM_A_ DQ<40>

MEM_A_ DQ<41>

MEM_A_ DQ<42>

MEM_A_ DQ<43>

MEM_A_ DQ<44>

MEM_A_ DQ<45>

MEM_A_ DQ<46>

MEM_A_ DQ<47>

MEM_A_ DQ<48>

MEM_A_ DQ<49>

MEM_A_ DQ<50>

MEM_A_ DQ<51>

MEM_A_ DQ<52>

MEM_A_ DQ<53>

MEM_A_ DQ<54>

MEM_A_ DQ<55>

MEM_A_ DQ<56>

MEM_A_ DQ<57>

MEM_A_ DQ<58>

MEM_A_ DQ<59>

MEM_A_ DQ<60>

MEM_A_ DQ<61>

MEM_A_ DQ<62>

MEM_A_ DQ<63>

MEM_B_ CKE<0>

MEM_B_ CKE<1>

MEM_B_ ODT<0>

MEM_B_ ODT<1>

MEM_B_ CS_L<0 >

MEM_B_ CS_L<1 >

MEM_B_ CLK_N< 0>

MEM_B_ CLK_P< 0>

MEM_B_ CLK_N< 1>

MEM_B_ CLK_P< 1>

TP_MEM _B_CLK 2N

TP_MEM _B_CLK 2P

MEM_B_ A<0>

MEM_B_ A<1>

MEM_B_ A<2>

MEM_B_ A<3>

MEM_B_ A<4>

MEM_B_ A<5>

MEM_B_ A<6>

MEM_B_ A<7>

MEM_B_ A<8>

MEM_B_ A<9>

MEM_B_ A<10>

MEM_B_ A<11>

MEM_B_ A<12>

MEM_B_ A<13>

MEM_B_ A<14>

MEM_B_ BA<0>

MEM_B_ BA<1>

MEM_B_ BA<2>

MEM_B_ WE_L

MEM_B_ CAS_L

MEM_B_ RAS_L

MEM_B_ DQS_N< 0>

MEM_B_ DQS_P< 0>

MEM_B_ DQS_N< 1>

MEM_B_ DQS_P< 1>

MEM_B_ DQS_N< 2>

MEM_B_ DQS_P< 2>

MEM_B_ DQS_N< 3>

MEM_B_ DQS_P< 3>

MEM_B_ DQS_N< 4>

MEM_B_ DQS_P< 4>

MEM_B_ DQS_N< 5>

MEM_B_ DQS_P< 5>

MEM_B_ DQS_N< 6>

MEM_B_ DQS_P< 6>

MEM_B_ DQS_N< 7>

MEM_B_ DQS_P< 7>

MEM_A_ CKE<0>

MEM_A_ CKE<1>

MEM_A_ ODT<0>

MEM_A_ ODT<1>

MEM_A_ CS_L<0 >

MEM_A_ CS_L<1 >

MEM_A_ CLK_N< 0>

MEM_A_ CLK_P< 0>

MEM_A_ CLK_N< 1>

MEM_A_ CLK_P< 1>

TP_MEM _A_CLK 2N

TP_MEM _A_CLK 2P

MEM_A_ A<0>

MEM_A_ A<1>

MEM_A_ A<2>

MEM_A_ A<3>

MEM_A_ A<4>

MEM_A_ A<5>

MEM_A_ A<6>

MEM_A_ A<7>

MEM_A_ A<8>

MEM_A_ A<9>

MEM_A_ A<10>

MEM_A_ A<11>

MEM_A_ A<12>

MEM_A_ A<13>

MEM_A_ A<14>

MEM_A_ BA<0>

MEM_A_ BA<1>

MEM_A_ BA<2>

MEM_A_ WE_L

MEM_A_ CAS_L

MEM_A_ RAS_L

MEM_A_ DQS_N< 0>

MEM_A_ DQS_P< 0>

MEM_A_ DQS_N< 1>

MEM_A_ DQS_P< 1>

MEM_A_ DQS_N< 2>

MEM_A_ DQS_P< 2>

MEM_A_ DQS_N< 3>

MEM_A_ DQS_P< 3>

MEM_A_ DQS_N< 4>

MEM_A_ DQS_P< 4>

MEM_A_ DQS_N< 5>

MEM_A_ DQS_P< 5>

MEM_A_ DQS_N< 6>

MEM_A_ DQS_P< 6>

MEM_A_ DQS_N< 7>

MEM_A_ DQS_P< 7>

U1400

AR19

AT19

AN19

AW21

AN23

AU15

AR23

AU19

AV19

AN21

AR21

AP21

AU21

AR22

AV21

AW17

AP19

AP23

AP17

AT23

AU23

BC20

BB20

AY24

BA24

AV33

AW33

AR18

AT15

AP35

AR35

AV31

AT31

AW37

AV37

AR33

AU31

AN31

AV29

AN29

AV27

AW38

AR31

AP31

AR29

AP29

AR27

AP27

AR25

AP25

AU27

AT27

AV38

AU25

AR26

AU13

AR14

AT11

AR11

AW13

AV13

AV11

AU11

AR38

AV9

AU9

AY5

AW6

AP11

AW9

AU8

AU7

AV5

AU6

AR37

AR5

AN10

AW5

AV6

AR7

AR6

AN7

AN6

AL7

AL6

AV39

AN9

AP9

AL9

AL8

AW39

AU37

AT37

AR34

AV35

AW29

AN27

AN13

AR10

AU5

AN5

AT39

AU39

AU35

AT35

AU29

AU30

AW25

AV25

AR13

AP13

AW8

AW7

AR9

AR8

AL11

AL10

AV15

AP15

AV17

AR17

U1400

BA18

BB25

BA17

BC28

AW28

BA14

BA29

BA25

BB26

BA26

BA27

AY27

BA28

AY28

BB28

BB17

BB18

BB29

BA15

BB30

AY31

AY19

BA19

BA22

BB22

BB42

BA42

BB16

BB14

AP42

AR41

BC40

BA40

AV41

AV42

AW40

BB40

AY39

BA38

BB36

BA36

AU41

AY40

BA39

AW36

BC36

AY35

BA34

BB32

BA32

AY36

BA35

AU40

AW32

BC32

BA12

AY12

BB9

BB8

AW12

BB12

BB10

BA9

AN40

AY8

BA7

BC4

BB4

BC8

BA8

BA5

BB5

BB2

BA3

AP41

AW3

AW4

BC3

BB3

AY3

AY4

AU3

AU2

AR3

AR4

AT41

AV3

AV2

AT3

AT4

AT40

AW41

AW42

AR42

AY43

BB38

BB34

BA11

AY7

BA2

AT5

AT43

AT42

AY42

BA43

BA37

BB37

BA33

BB33

AY11

BA10

BA6

BB6

AY1

AY2

AT1

AT2

AY15

BB13

AW16

BA16

MCLK1B_2 _P

MCLK1B_1 _N

MCLK1B_0 _P

MCLK1B_1 _P

MCLK1B_2 _N

MCS1B_1#

MCS1B_0#

MCLK1B_0 _N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55

GND56

GND57

GND58

GND60

GND59

GND61

GND62

GND63

GND64

GND52

GND53

GND54

GND51

GND49

GND50

GND48

GND47

GND46

GND44

GND45

GND43

GND42

GND41

GND39

GND40

GND38

GND37

GND36

GND35

GND33

GND34

GND32

GND31

GND30

GND28

GND29

GND27

GND26

GND25

GND24

GND18

GND19

GND17

GND16

GND15

GND13

GND14

GND10

GND12

GND11

GND8

GND9

GND7

GND6

GND5

GND2

GND3

GND4

GND1

MEM_COMP _VDD

MEM_COMP _GND

MODT0B_0

MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0 _N

MCS0B_0#

MCS0B_1#

MCLK0B_2 _N

MCLK0B_1 _P

MCLK0B_0 _P

MCLK0B_1 _N

MCLK0B_2 _P

+V_PLL_X REF_XS

+V_PLL_C ORE

+V_VPLL

+VDD_MEM 1

+VDD_MEM 2

+VDD_MEM 3

+VDD_MEM 4

+VDD_MEM 5

+VDD_MEM 6

+VDD_MEM 7

+VDD_MEM 8

+VDD_MEM 9

+VDD_MEM 10

+VDD_MEM 11

+VDD_MEM 14

+VDD_MEM 15

+VDD_MEM 16

+VDD_MEM 17

+VDD_MEM 18

+VDD_MEM 19

+VDD_MEM 20

+VDD_MEM 22

+VDD_MEM 21

+VDD_MEM 23

+VDD_MEM 24

+VDD_MEM 25

+VDD_MEM 26

+VDD_MEM 30

+VDD_MEM 27

+VDD_MEM 29

+VDD_MEM 31

+VDD_MEM 32

+VDD_MEM 33

+VDD_MEM 34

+VDD_MEM 38

+VDD_MEM 39

+VDD_MEM 40

+VDD_MEM 41

+VDD_MEM 43

+VDD_MEM 44

+VDD_MEM 45

+VDD_MEM 42

+V_PLL_D P

+VDD_MEM 13

+VDD_MEM 12

+VDD_MEM 28

+VDD_MEM 37

+VDD_MEM 36

+VDD_MEM 35

GND21

GND20

GND22

GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

87 mA (A01)

39 mA

TP or NC for DDR2.

19 mA

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

12 mA

17 mA

4771 m A (A01 , DDR3)

1%

40.2

1/16W

402

MF-LF

402

1%

1/16W

40.2

(4 OF 11 )

MCP79- TOPO-B

OMIT

BGA

30

MCP Memory Misc

16 9 6

A.0.0

051-7546

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

TP_MEM _B_CKE <3>

TP_MEM _B_CKE <2>

TP_MEM _B_CS_ L<2>

MCP_ME M_RESE T_L

=PP1V8 R1V5_S 0_MCP_M EM

MCP_ME M_COMP _GND

TP_MEM _A_CLK 4N

TP_MEM _A_CLK 3P

TP_MEM _A_ODT <2> TP_MEM _A_ODT <3>

TP_MEM _A_CKE <2> TP_MEM _A_CKE <3>

TP_MEM _A_CLK 5P TP_MEM _A_CLK 5N

TP_MEM _A_CLK 4P

TP_MEM _A_CLK 3N

TP_MEM _A_CS_ L<2> TP_MEM _A_CS_ L<3>

PP1V05 _S0_MC P_PLL_C ORE

TP_MEM _B_CLK 5P TP_MEM _B_CLK 5N

TP_MEM _B_CLK 4P TP_MEM _B_CLK 4N

TP_MEM _B_CLK 3P TP_MEM _B_CLK 3N

TP_MEM _B_CS_ L<3>

TP_MEM _B_ODT <2> TP_MEM _B_ODT <3>

=PP1V8 R1V5_S 0_MCP_M EM

MCP_ME M_COMP _VDD

R1610

1

2

R1611

1

2

U1400

AA22

AA39

AB22

AB7

AD22

AE20

AF24

AG24

AH35

AK7

AM28

AP12

AT25

AP30

AR36

AU10

F28

BC21

AY9

BC9

D34

F24

G30

G32

H31

K7

M38

M5

M6

M7

M9

N39

N8

P10

P33

P34

P37

P4

P40

P7

R36

R40

R43

R5

T10

T18

T20

AK11

T24

T26

T33

T34

T35

T37

T38

T6

T7

T9

U18

U20

U22

V10

V34

W5

AV23

AN25

BA30

BA31

BB21

BA21

BC24

BB24

AU34

AU33

AY20

BA20

BA23

AY23

BB41

BA41

AU17

AR15

BC16

BA13

AM41

AN41

AN17

AN15

AY16

BC13

AY32

U27

U28

T27

T28

AM17

AN20

AN24

AT17

AP16

AN22

AP20

AP24

AV16

AR16

AR20

AM19

AR24

AW15

AP22

AP18

AU16

AN18

AU24

AT21

AY29

AV24

AM21

AU20

AU22

AW27

BC17

AV20

AY17

AY18

AM15

AU18

AY25

AM23

AY26

AW19

AW24

BC25

AL30

AM31

AM25

AM27

AM29

AN16

BC29

24

16

8

88

24

8

88

PE0_RX0_ P

PE0_RX2_ N

+AVDD0_P EX11

+AVDD0_P EX7

+AVDD0_P EX8

+AVDD1_P EX3

+AVDD1_P EX2

+AVDD1_P EX1

+AVDD0_P EX13

+AVDD0_P EX12

+AVDD0_P EX10

+AVDD0_P EX9

+AVDD0_P EX6

+AVDD0_P EX5

+AVDD0_P EX4

+AVDD0_P EX3

+AVDD0_P EX2

+AVDD0_P EX1

+V_PLL_P EX

+DVDD1_P EX2

+DVDD1_P EX1

+DVDD0_P EX8

+DVDD0_P EX7

+DVDD0_P EX6

+DVDD0_P EX5

+DVDD0_P EX4

+DVDD0_P EX3

+DVDD0_P EX2

+DVDD0_P EX1

PE0_RX0_ N

PE0_RX2_ P

PE0_RX4_ P

PE0_RX6_ P

PEB_PRSN T#

PE1_TX3_ N

PE1_TX3_ P

PE1_TX2_ N

PE1_TX1_ N

PE1_TX2_ P

PE1_TX0_ N

PE1_TX1_ P

PE6_REFC LK_N

PEX_RST0 #

PE1_TX0_ P

PE5_REFC LK_N

PE5_REFC LK_P

PE6_REFC LK_P

PE4_REFC LK_N

PE4_REFC LK_P

PE3_REFC LK_N

PE2_REFC LK_N

PE1_REFC LK_N

PE2_REFC LK_P

PE0_REFC LK_N

PE0_REFC LK_P

PE1_REFC LK_P

PE0_TX15 _N

PE0_TX14 _N

PE0_TX15 _P

PE0_TX13 _N

PE0_TX14 _P

PE0_TX12 _N

PE0_TX12 _P

PE0_TX13 _P

PE0_TX11 _N

PE0_TX11 _P

PE0_TX10 _N

PE0_TX9_ N

PE0_TX10 _P

PE0_TX8_ N

PE0_TX8_ P

PE0_TX9_ P

PE0_TX7_ N

PE0_TX7_ P

PE0_TX6_ N

PE0_TX5_ N

PE0_TX6_ P

PE0_TX4_ N

PE0_TX5_ P

PE0_TX3_ N

PE0_TX3_ P

PE0_TX4_ P

PE0_TX2_ N

PE0_TX2_ P

PE0_TX0_ N

PE0_TX1_ N

PE0_TX1_ P

PE0_TX0_ P

PEX_CLK_ COMP

PE1_RX3_ N

PE1_RX3_ P

PE1_RX2_ N

PE1_RX0_ N

PE1_RX1_ P

PE1_RX2_ P

PE1_RX1_ N

PE_WAKE#

PE1_RX0_ P

PE0_PRSN T_16#

PE0_RX13 _N

PE0_RX14 _P

PE0_RX15 _P

PE0_RX14 _N

PE0_RX15 _N

PE0_RX12 _P

PE0_RX11 _P

PE0_RX13 _P

PE0_RX11 _N

PE0_RX12 _N

PE0_RX10 _N

PE0_RX8_ P

PE0_RX9_ P

PE0_RX10 _P

PE0_RX8_ N

PE0_RX9_ N

PE0_RX5_ N

PE0_RX7_ P

PE0_RX6_ N

PE0_RX7_ N

PE0_RX3_ P

PE0_RX5_ P

PE0_RX3_ N

PE0_RX4_ N

PE0_RX1_ P

PE0_RX1_ N

PEC_PRSN T#

PEC_CLKR EQ#/GPIO_ 50

PE3_REFC LK_P

PED_CLKR EQ#/GPIO_ 51

PED_PRSN T#

PEB_CLKR EQ#/GPIO_ 49

PEE_CLKR EQ#/GPIO_ 16

PEE_PRSN T#/GPIO_4 6

PEF_CLKR EQ#/GPIO_ 17

PEF_PRSN T#/GPIO_4 7

PEG_CLKR EQ#/GPIO_ 18

PEG_PRSN T#/GPIO_4 8

PCI EXPRESS

OUT

IN

OUT

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

If PE1 inter face is not u sed, g round DVDD1_P EX and AVDD1 _PEX.

Minimu m 1.02 5V for Gen2 s upportMinimu m 1.02 5V for Gen2 s upport

Int PU

84 mA (A01)

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

Int PU

206 mA (A01, AVDD0 & 1)

If PE0 inter face is not u sed, g round DVDD0_P EX and AVDD0 _PEX.

57 mA (A01, DVDD0 & 1)

Int PU (S5)

MCP79- TOPO-B

(5 OF 11 )

OMIT

BGA

9

70 89

9

31 89

9

36

23 31 32

36 89

7

32 89

7

32 89

31

32

31 89

36 89

32 89

31 89

32 89

9

2.37K

402

MF-LF

1% 1/16W

NO STU FF

PLACEMEN T_NOTE=P lace wit hin 12.7 mm of U1 400

9

26

83

9

SYNC_MA STER=T 18_MLB

MCP PCIe Interfaces

17 9 6

A.0.0

051-7546

SYNC_DA TE=06/ 18/2008

AUD_IP _PERIP HERAL_D ET

TP_PE4 _CLKRE Q_L

PCIE_E XCARD_ PRSNT_L

TP_PE4 _PRSNT _L

=PP1V0 5_S0_M CP_PEX_ AVDD1

GMUX_J TAG_TD O

=PEG_D 2R_N<1 5>

=PEG_D 2R_N<1 4>

GMUX_J TAG_TC K_L

EXCARD _CLKRE Q_L

PCIE_C LK100M _EXCARD _P

FW_CLK REQ_L PCIE_F W_PRSN T_L

=PEG_D 2R_N<1 >

=PEG_D 2R_P<1 >

=PEG_D 2R_N<4 >

=PEG_D 2R_N<3 >

=PEG_D 2R_P<5 >

=PEG_D 2R_P<3 >

=PEG_D 2R_N<7 >

=PEG_D 2R_N<6 > =PEG_D 2R_P<7 >

=PEG_D 2R_N<5 >

=PEG_D 2R_N<9 >

=PEG_D 2R_N<8 >

=PEG_D 2R_P<1 0>

=PEG_D 2R_P<9 >

=PEG_D 2R_P<8 >

=PEG_D 2R_N<1 0>

=PEG_D 2R_N<1 2>

=PEG_D 2R_N<1 1>

=PEG_D 2R_P<1 3>

=PEG_D 2R_P<1 1>

=PEG_D 2R_P<1 2>

=PEG_D 2R_P<1 5>

=PEG_D 2R_P<1 4>

=PEG_D 2R_N<1 3>

PEG_PR SNT_L

PCIE_M INI_D2 R_P

PCIE_W AKE_L

PCIE_E XCARD_ D2R_P

PCIE_F W_D2R_ P

PCIE_M INI_D2 R_N

PCIE_E XCARD_ D2R_N

TP_PCI E_PE4_ D2RP TP_PCI E_PE4_ D2RN

MCP_PE X_CLK_ COMP

=PEG_R 2D_C_P <0>

=PEG_R 2D_C_P <1> =PEG_R 2D_C_N <1>

=PEG_R 2D_C_N <0>

=PEG_R 2D_C_P <2> =PEG_R 2D_C_N <2>

=PEG_R 2D_C_P <4>

=PEG_R 2D_C_P <3> =PEG_R 2D_C_N <3>

=PEG_R 2D_C_P <5>

=PEG_R 2D_C_N <4>

=PEG_R 2D_C_P <6>

=PEG_R 2D_C_N <5>

=PEG_R 2D_C_N <6> =PEG_R 2D_C_P <7> =PEG_R 2D_C_N <7>

=PEG_R 2D_C_P <9>

=PEG_R 2D_C_P <8> =PEG_R 2D_C_N <8>

=PEG_R 2D_C_P <10>

=PEG_R 2D_C_N <9>

=PEG_R 2D_C_N <10> =PEG_R 2D_C_P <11> =PEG_R 2D_C_N <11>

=PEG_R 2D_C_P <13>

=PEG_R 2D_C_P <12> =PEG_R 2D_C_N <12>

=PEG_R 2D_C_P <14>

=PEG_R 2D_C_N <13>

=PEG_R 2D_C_P <15>

=PEG_R 2D_C_N <14>

=PEG_R 2D_C_N <15>

PCIE_C LK100M _MINI_P

PEG_CL K100M_ P PEG_CL K100M_ N

PCIE_C LK100M _FW_P

PCIE_C LK100M _MINI_N

PCIE_C LK100M _FW_N

PCIE_C LK100M _EXCARD _N

TP_PCI E_CLK1 00M_PE4 P TP_PCI E_CLK1 00M_PE4 N

TP_PCI E_CLK1 00M_PE6 P

TP_PCI E_CLK1 00M_PE5 P TP_PCI E_CLK1 00M_PE5 N

PCIE_M INI_R2 D_C_P

PCIE_R ESET_L

TP_PCI E_CLK1 00M_PE6 N

PCIE_F W_R2D_ C_P

PCIE_M INI_R2 D_C_N

PCIE_E XCARD_ R2D_C_P

PCIE_F W_R2D_ C_N

PCIE_E XCARD_ R2D_C_N

TP_PCI E_PE4_ R2D_CP TP_PCI E_PE4_ R2D_CN

PCIE_M INI_PR SNT_L

=PEG_D 2R_P<6 >

=PEG_D 2R_P<4 >

=PEG_D 2R_P<2 >

=PEG_D 2R_N<0 >

PP1V05 _S0_MC P_PLL_P EX

=PEG_D 2R_N<2 >

=PEG_D 2R_P<0 >

PCIE_F W_D2R_ N

=PP1V0 5_S0_M CP_PEX_ DVDD0

=PP1V0 5_S0_M CP_PEX_ DVDD1

=PP1V0 5_S0_M CP_PEX_ AVDD0

MINI_C LKREQ_ L

TP_MCP _GPIO_ 18

U1400

Y12

AC12

AD12

V12

W12

AA12

AB12

M12

P12

R12

N12

T12

U12

M13

N13

P13

T17

W19

U17

V19

W16

W17

W18

U16

T19

U19

T16

C9 D11

E11

E7

F7

L8

L9

L6

L7

N10

N11

P9

N9

N6

N7

N4

N5

C7

D7

F6

E6

F5

E5

E3

E4

D3

C3

H5

G5

J6

J7

J4

J5

L10

L11

D4

C5

J1

H1

J3

J2

K3

K2

L3

L4

M3

M4

M1

M2

B4

C4

A3

A4

B2

B3

D1

C1

E1

D2

F2

E2

F4

F3

H4

G3

H2

H3

F11

G11

J9

K9

G9

H9

E9

F9

G7

H7

C8

D8

A8

B8

B7

A7

C6

B6

J10

J11

F13

G13

H13

J13

K14

L14

M14

N14

F17

D5

D9

E8

C10

M15

B10

L16

L18

M16

M18

M17

M19

A11

K11

R1710

1

2

9

8

9

89

9

24

8

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

GPIO_7/N FERR*/IGP U_GPIO_7

+V_DUAL_ MACPLL

+VDD_HDM I

+V_PLL_H DMI

+V_PLL_I FPAB

+VDD_IFP B

+VDD_IFP A

+V_TV_DA C

+V_RGB_D AC

+V_DUAL_ RMGT2

MII_COMP _GND

MII_COMP _VDD

LCD_PANE L_PWR/GP IO_58

LCD_BKL_ ON/GPIO_ 59

LCD_BKL_ CTL/GPIO _57

XTALOUT_ TV

GPIO_6/F ERR*/IGPU _GPIO_6

HDMI_TXC _P/ML0_L ANE3_P

HDMI_TXC _N/ML0_L ANE3_N

HDMI_TXD 0_P/ML0_ LANE2_P

HDMI_TXD 0_N/ML0_ LANE2_N

HDMI_TXD 1_P/ML0_ LANE1_P

HDMI_TXD 1_N/ML0_ LANE1_N

HDMI_TXD 2_P/ML0_ LANE0_P

HDMI_TXD 2_N/ML0_ LANE0_N

HPLUG_DE T2/GPIO_ 22

IFPA_TXC _N

XTALIN_T V

DDC_DATA 2/GPIO_2 4

DDC_CLK2 /GPIO_23

RGB_DAC_ RSET

RGB_DAC_ VREF

TV_DAC_V REF

DP_AUX_C H0_P

DP_AUX_C H0_N

HPLUG_DE T3

HDMI_RSE T

HDMI_VPR OBE

RGMII_MD IO

BUF_25MH Z

DDC_DATA 0

DDC_CLK0

RGB_DAC_ RED

RGB_DAC_ GREEN

RGB_DAC_ BLUE

RGB_DAC_ HSYNC

RGB_DAC_ VSYNC

TV_DAC_R ED

TV_DAC_G REEN

IFPA_TXC _P

IFPA_TXD 0_P

IFPA_TXD 0_N

IFPA_TXD 2_P

IFPA_TXD 1_P

IFPA_TXD 1_N

IFPA_TXD 3_P

IFPA_TXD 2_N

IFPB_TXC _P

IFPB_TXC _N

IFPB_TXD 5_P

IFPB_TXD 4_P

IFPB_TXD 4_N

IFPB_TXD 6_P

IFPB_TXD 5_N

IFPB_TXD 6_N

IFPB_TXD 7_P

IFPB_TXD 7_N

DDC_DATA 3

DDC_CLK3

IFPAB_RS ET

IFPAB_VP ROBE

TV_DAC_R SET

RGMII_RX D0

RGMII_IN TR/GPIO_3 5

RGMII_RX D3

RGMII_RX CTL/MII_R XDV

RGMII_RX C/MII_RXC LK

RGMII_RX D2

RGMII_RX D1

MII_RESE T#

RGMII_MD C

RGMII_PW RDWN/GPIO _37

MII_RXER /GPIO_36

MII_COL/ GPIO_20/ MSMB_DAT A

MII_CRS/ GPIO_21/ MSMB_CLK

TV_DAC_B LUE

TV_DAC_H SYNC/GPI O_44

TV_DAC_V SYNC/GPI O_45

+V_DUAL_ RMGT1

MII_VREF

RGMII_TX CTL/MII_T XEN

RGMII_TX C/MII_TXC LK

RGMII_TX D3

RGMII_TX D2

RGMII_TX D1

RGMII_TX D0

+3.3V_DU AL_RMGT1

+3.3V_DU AL_RMGT2

IFPA_TXD 3_N

LAN

DACS

FLAT PANEL

BI

OUT

BI

OUT

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

190 mA (A01, 1.8V)

C / Pr

MCP79 require s a S5 pull- up.

Comp / Pb

206 mA (A01)

103 mA

Okay t o floa t XTALI N_TV a nd XTA LOUT_T V.

Okay t o floa t all R GB_DAC signa ls. DDC_CL K0/DDC _DATA0 pull-u ps sti ll req uired.

Y / Y

TV DAC Disab le:

Okay t o floa t all T V_DAC signal s.

DDC_CL K0/DDC _DATA0 pull-u ps sti ll req uired.

ENET_TXD<0>

1

0

MII

RGMII

Interface

Network Interface Select

NOTE: All Ap ple pro ducts set st rap to

featur e via s oftwar e. Th is avoids a leak age is sue si nce

RGB ON LY

5 mA ( A01)

Displa yPort

DP_IG_ ML_P/N <3>

DP_IG_ ML_P/N <1>

DP_IG_ ML_P/N <2>

DP_IG_ DDC_CL K

TP_DP_ IG_AUX _CHP/N

TMDS_I G_DDC_ DATA

TMDS_I G_TXD_ P/N<2>

TMDS_I G_TXD_ P/N<1>

TMDS_I G_DDC_ CLK

TMDS_I G_TXD_ P/N<0>

TMDS_I G_TXC_ P/N

TMDS/H DMI

=MCP_H DMI_TX C_P/N =MCP_H DMI_TX D_P/N<0 >

MCP Si gnal

=MCP_H DMI_DD C_CLK

=MCP_H DMI_TX D_P/N<1 > =MCP_H DMI_TX D_P/N<2 >

=MCP_H DMI_DD C_DATA

TMDS_I G_HPD

=MCP_H DMI_HP D DP_IG_ AUX_CH _P/N

8 mA 8 mA

16 mA (A01)

95 mA (A01)

LVDS: Power +VDD_I FPx at 1.8V

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

TV / Compo nent

RGB DA C Disa ble:

WF: IF P is c apable of LVD S (1.8 V) or TMDS (3 .3V), need a liases

MII, R GMII pr oducts will enable

83 mA (A01)

131 mA (A01)

Dual-c hannel TMDS: Power +VDD_I FPx at 3.3V

NOTE: 1M pul l-down requir ed on DP_IG_ CA_DET if DP not us ed.

DP_IG_ AUX_CH _P/N

DP_IG_ HPD

DP_IG_ DDC_DA TA

DP_IG_ ML_P/N <0>

Interf ace Mo de

be use d to pr ovide HDMI o r dual -channe l TMDS witho ut

NOTE: HDMI p ort req uires level- shifti ng. IF P inte rface can

level- shifter s.

NOTE: 20K pu ll-down requi red on DP_HP D_DET. NOTE: 1K pul l-down requir ed on DP_IG_ AUX_CH_ N if D P is u sed.

(See b elow)

Alias to DVI _HPD fo r syst ems us ing IF P for D VI.

=DVI_H PD_GMU X_INT:

Pull-d own (2 0k) req uired in all cases .

Alias to HPL UG_DET2 for o ther s ystems .

Alias to GMU X_INT f or sys tems w ith GM UX.

pull-u ps (~1 0K to 3 .3V S0 ). To ensur e pins are lo w by def ault, pull-do wns (1 K or s tronge r) must be us ed.

GPIOs 57-59 (if LCD panel is us ed):

In MCP 79 the se pins have undocu mented intern al

24

33 91

34 91

33 91

25 89

9

80 89

9

25 89

1% 1/16W MF-LF

402

49.9

1/16W MF-LF

49.9

402

1%

80

25

9

(6 OF 11 )

BGA

MCP79- TOPO-B

OMIT

10K

402

1/16W

5%

MF-LF

402

5%

100K

1/16W MF-LF

402

MF-LF

5%

1/16W

100K

44

5%

47K

402

MF-LF

1/16W

33 91

83 89

33 91

83 89

9

89

9

89

9

89

9

89

83 89

33 91

83 89

9

89

9

89

80

9

25 89

33 91

25 89

33 91

18 9 6

A.0.0

051-7546

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

MCP Ethernet & Graphics

=DVI_H PD_GMU X_INT

LVDS_I G_BKL_ PWM

MCP_CL K27M_X TALOUT

TP_MCP _RGB_D AC_RSET TP_MCP _RGB_D AC_VREF

LPCPLU S_GPIO

=PP1V0 5_ENET _MCP_RM GT

=PP3V3 _S5_MC P_GPIO

=PP3V3 _ENET_ MCP_RMG T

=PP3V3 _S0_MC P_GPIO

=PP3V3 _ENET_ MCP_RMG T

ENET_T XD<0> ENET_T XD<1> ENET_T XD<2> ENET_T XD<3>

ENET_C LK125M _TXCLK ENET_T X_CTRL

MCP_MI I_VREF

CRT_IG _VSYNC

CRT_IG _HSYNC

CRT_IG _B_COM P_PB

=MCP_M II_CRS

=MCP_M II_COL

=MCP_M II_RXE R

TP_ENE T_PWRD WN_L

ENET_M DC

ENET_R ESET_L

ENET_R XD<1> ENET_R XD<2>

ENET_C LK125M _RXCLK ENET_R X_CTRL

ENET_R XD<3>

TP_ENE T_INTR _L

ENET_R XD<0>

MCP_TV _DAC_R SET

MCP_IF PAB_VP ROBE

MCP_IF PAB_RS ET

=MCP_H DMI_DD C_CLK =MCP_H DMI_DD C_DATA

LVDS_I G_B_DA TA_N<3>

LVDS_I G_B_DA TA_P<3>

LVDS_I G_B_DA TA_N<2>

LVDS_I G_B_DA TA_N<1> LVDS_I G_B_DA TA_P<2>

LVDS_I G_B_DA TA_N<0>

LVDS_I G_B_DA TA_P<0>

LVDS_I G_B_DA TA_P<1>

LVDS_I G_B_CL K_N

LVDS_I G_B_CL K_P

LVDS_I G_A_DA TA_N<2> LVDS_I G_A_DA TA_P<3>

LVDS_I G_A_DA TA_N<1>

LVDS_I G_A_DA TA_P<1>

LVDS_I G_A_DA TA_P<2>

LVDS_I G_A_DA TA_N<0>

LVDS_I G_A_DA TA_P<0>

LVDS_I G_A_CL K_P

CRT_IG _G_Y_Y

CRT_IG _R_C_P R

TP_MCP _RGB_V SYNC

TP_MCP _RGB_H SYNC

TP_MCP _RGB_B LUE

TP_MCP _RGB_G REEN

TP_MCP _RGB_R ED

MCP_DD C_CLK0 MCP_DD C_DATA 0

MCP_CL K25M_B UF0_R

ENET_M DIO

=MCP_H DMI_HP D

DP_IG_ AUX_CH _N

DP_IG_ AUX_CH _P

MCP_TV _DAC_V REF

LVDS_I G_DDC_ CLK LVDS_I G_DDC_ DATA

MCP_CL K27M_X TALIN

=MCP_H DMI_TX D_N<2>

=MCP_H DMI_TX C_P

LVDS_I G_BKL_ ON LVDS_I G_PANE L_PWR

MCP_MI I_COMP _VDD MCP_MI I_COMP _GND

PP3V3_ S0_MCP _DAC

=PP3V3 R1V8_S 0_MCP_I FP_VDD

PP3V3_ S0_MCP _VPLL

=PP1V0 5_S0_M CP_HDMI _VDD

PP1V05 _ENET_ MCP_PLL _MAC

DP_IG_ CA_DET

MCP_HD MI_VPR OBE

MCP_HD MI_RSE T

LVDS_I G_A_DA TA_N<3>

LVDS_I G_A_CL K_N

=MCP_H DMI_TX D_P<2>

=MCP_H DMI_TX D_N<1>

=MCP_H DMI_TX D_P<1>

=MCP_H DMI_TX D_P<0>

=MCP_H DMI_TX C_N

=MCP_H DMI_TX D_N<0>

R1810

1

2

R1811

1

2

U1400

E23

B31

C30

D31

A31

B30

E31

C43

D43

E16

B15

J31

E35

D35

F35

G35

G33

F33

H33

J33

J30

C31

F31

C35

B35

A32

B32

C32

D32

C33

D33

C34

B34

E32

G31

K31

L31

H29

J29

K29

L29

K30

L30

M30

N30

G39

E37

F40

B26

B27

C27

B22

J23

F23

E28

J24

K24

T23

U23

V23

M29

M28

J32

K32

T25

M27

M26

B40

A39

A40

B39

C39

B38

A41

J22

D21

C21

G23

A23

C22

C23

B23

E24

A24

D24

C26

B24

C24

C25

D25

C36

B36

D36

A36

E36

A35

C37

C38

D38

R1850

1

2

R1861

1

2

R1860

1

2

R1820

1

2

24

21

24

20

18

19

18

25

8

25

91

25

8

25

8

24

OUT

BI

LPC PCIGND

PCI_INTW #

PCI_INTX #

PCI_INTY #

PCI_INTZ #

GND65

LPC_DRQ1 #/GPIO_1 9

LPC_PWRD WN#/GPIO _54/EXT_ NMI#

PCI_TRDY #

LPC_DRQ0 #

LPC_SERI RQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5

PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10

PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15

PCI_AD16

PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21

PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66

GND67

GND69

GND68

GND70

GND71

GND72

GND74

GND73

GND75

GND76

GND77

GND79

GND78

GND80

GND81

GND84

GND83

GND82

GND85

GND86

GND87

GND89

GND88

GND90

GND91

GND92

GND94

GND93

GND95

GND96

GND97

PCI_GNT0 #

PCI_CBE2 #

PCI_CBE0 #

PCI_CBE3 #

PCI_IRDY #

PCI_FRAM E#

PCI_DEVS EL#

PCI_PAR

PCI_SERR #

PCI_STOP #

PCI_RESE T0#

PCI_RESE T1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKI N

LPC_FRAM E#

LPC_AD1

LPC_AD0

LPC_RESE T0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105

GND106

GND107

GND109

GND108

GND110

GND111

GND112

GND115

GND114

GND113

GND116

GND117

GND120

GND119

GND118

GND121

GND122

GND123

GND125

GND124

GND126

GND127

GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKR UN#/GPIO _42

PCI_AD28

PCI_GNT2 #/GPIO_4 1/RS232_ DTR#

PCI_GNT3 #/GPIO_3 9/RS232_ RTS#

PCI_GNT4 #/GPIO_5 3/RS232_ SOUT#

PCI_GNT1 #/FANCTL 2

PCI_CBE1 #

PCI_PERR #/GPIO_4 3/RS232_ DCD#

PCI_REQ3 #/GPIO_3 8/RS232_ CTS#

PCI_REQ4 #/GPIO_5 2/RS232_ SIN#

PCI_PME# /GPIO_30

PCI_REQ2 #/GPIO_4 0/RS232_ DSR#

PCI_REQ0 #

PCI_REQ1 #/FANRPM 2

IN

BI

OUT

IN

OUT

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Strap for Bo ot ROM Select ion (S ee HDA _SDOUT)

Int PU Int PU Int PU

Int PU (S5)

42 44 83 90

26 83 90

42 44 83 90

BGA

(7 OF 11 )

MCP79- TOPO-B

OMIT

42 44

42 44 26 90

42 44

PLACEMEN T_NOTE=P lace clo se to pi n R8

MF-LF 402

1/16W

5%

22

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

5%

1/16W MF-LF

402

19

MF-LF 402

1/16W

5%

10K

1/16W MF-LF

402

22

5%

1/16W MF-LF22402

5%

1/16W MF-LF22402

22

5%

1/16W MF-LF

402

MF-LF1/16W

5%

22

26

36

19

13 23

13 90

9

59

9

051-7546

A.0.0

9619

MCP PCI & LPC

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

GMUX_J TAG_TD I

GMUX_J TAG_TM S

TP_PCI _INTX_ L

TP_PCI _INTZ_ L

FW_PME _L TP_LPC _DRQ0_ L LPC_SE RIRQ

PM_CLK RUN_L

=PP3V3 _S0_MC P_GPIO

MCP_RS 232_SI N_L

MCP_DE BUG<7>

MCP_DE BUG<6>

MCP_DE BUG<5>

MCP_DE BUG<4>

MCP_DE BUG<3>

MCP_DE BUG<2>

MCP_DE BUG<1>

MCP_DE BUG<0>

MCP_RS 232_SI N_L

AUD_IP HS_SWI TCH_EN

CRTMUX _SEL_T V_L

TP_PCI _AD<12 > TP_PCI _AD<13 > TP_PCI _AD<14 >

TP_PCI _AD<16 > TP_PCI _AD<17 > TP_PCI _AD<18 > TP_PCI _AD<19 > TP_PCI _AD<20 > TP_PCI _AD<21 > TP_PCI _AD<22 > TP_PCI _AD<23 > TP_PCI _AD<24 > TP_PCI _AD<25 > TP_PCI _AD<26 > TP_PCI _AD<27 > TP_PCI _AD<28 > TP_PCI _AD<29 > TP_PCI _AD<30 > TP_PCI _AD<31 >

TP_PCI _INTW_ L

TP_PCI _TRDY_ L

TP_PCI _INTY_ L

TP_PCI _AD<15 >

PCI_RE Q0_L PCI_RE Q1_L

TP_PCI _AD<8>

TP_PCI _AD<10 > TP_PCI _AD<11 >

TP_PCI _AD<9>

TP_PCI _PERR_ L

MEM_VT T_EN_R

PCI_CL K33M_M CP

TP_PCI _CLK1 PCI_CL K33M_M CP_R

LPC_PW RDWN_L

LPC_RE SET_L

LPC_FR AME_R_ L

LPC_CL K33M_S MC_R

LPC_AD _R<3>

LPC_AD _R<2>

LPC_AD _R<1>

LPC_AD _R<0>

TP_PCI _CLK0

TP_PCI _RESET 1_L

PM_LAT RIGGER _L

TP_PCI _STOP_ L

TP_PCI _SERR_ L

TP_PCI _PAR

TP_PCI _IRDY_ L

TP_PCI _FRAME _L

TP_PCI _DEVSE L_L

TP_PCI _C_BE_ L<3>

TP_PCI _C_BE_ L<2>

TP_PCI _C_BE_ L<1>

TP_PCI _C_BE_ L<0>

MCP_RS 232_SO UT_L

TP_PCI _GNT1_ L

TP_PCI _GNT0_ L

LPC_AD <0>

LPC_FR AME_L

LPC_AD <2> LPC_AD <3>

LPC_AD <1>

MCP_RS 232_SO UT_L

PCI_RE Q0_L PCI_RE Q1_L CRTMUX _SEL_T V_L

U1400

AB18

H34

AB20

AB21

AB23

AB24

AB25

AB26

AB27

AB28

AB34

AB37

AB4

AB40

AC22

AC36

AC40

AB33

AC5

AD16

AD17

AD18

AD19

AD20

AD24

AD25

AD26

AD27

AD28

AD33

AD34

U24

U26

U39

U4

U8

V16

V17

V18

V20

V22

V24

V26

V27

V28

V33

V37

V4

V40

V7

W20

W22

W24

W36

W40

W43

Y16

Y17

Y18

Y19

Y20

Y22

Y24

Y25

Y26

Y27

AD3

AD2

AD1

AD5

AE9

AE1

AE2

AD4

AE12

AE5

AE6

AC3

AE10

AC9

AC10

AC11

AA1

AA5

Y5

W3

W6

W4

W7

AC4

V3

W8

V2

W9

U3

W11

U2

U5

U1

U6

AE11

T5

U7

AB3

AC6

AB2

AC7

AC8

AA2

AA3

AA6

AA11

W10

R6

R7

R8

R9

AD11

AA9

Y4

R3

U10

R4

U11

P3

P2

N3

N2

N1

AA10

Y1

AB9

T1

T2

V9

T3

U9

T4

R10

R11

AA7

Y2

Y3

R1910

1

2

R1989

1 2

R1991

1 2

R1990

1 2

R1994

1 2

R1992

1 2

R1961

1

2

R1960

1 2

R1950

1 2

R1951

1 2

R1952

1 2

R1953

1 2

21 18

90

8

19

90

44

19

BI

IN

SATA_B0_ RX_N

SATA_A0_ RX_P

SATA_A1_ TX_P

GND160

GND158

GND159

GND157

GND156

GND155

GND153

GND154

GND152

GND151

GND150

GND148

GND149

GND147

GND146

GND145

GND143

GND144

GND142

GND141

GND140

GND139

GND136

GND133

GND134

GND132

GND131

USB_RBIA S_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TER MP

SATA_LED #

SATA_C1_ RX_N

SATA_C1_ RX_P

SATA_C0_ TX_P

SATA_B1_ RX_N

SATA_B1_ RX_P

SATA_B1_ TX_N

SATA_B1_ TX_P

SATA_B0_ TX_N

SATA_B0_ RX_P

SATA_B0_ TX_P

SATA_A1_ RX_N

SATA_A1_ RX_P

SATA_A1_ TX_N

SATA_A0_ TX_P

GND138

GND137

GND135

USB3_P

USB3_N

USB_OC0# /GPIO_25

USB_OC1# /GPIO_26

USB_OC2# /GPIO_27 /MGPIO

USB_OC3# /GPIO_28 /MGPIO

SATA_A0_ RX_N

SATA_A0_ TX_N

SATA_C1_ TX_N

SATA_C1_ TX_P

SATA_C0_ RX_P

SATA_C0_ RX_N

SATA_C0_ TX_N

+V_PLL_U SB

+V_PLL_S ATA

+DVDD0_S ATA1

+DVDD0_S ATA2

+DVDD0_S ATA3

+DVDD0_S ATA4

+DVDD1_S ATA2

+AVDD0_S ATA1

+AVDD0_S ATA2

+AVDD0_S ATA3

+AVDD0_S ATA4

+AVDD0_S ATA5

+AVDD0_S ATA6

+AVDD0_S ATA7

+AVDD0_S ATA8

+AVDD0_S ATA9

+AVDD1_S ATA1

+AVDD1_S ATA2

+AVDD1_S ATA3

+AVDD1_S ATA4

+DVDD1_S ATA1

SATA

USB

OUT

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

If all SATA_ Ax & Bx pins are no t used , groun d DVDD 0_SATA and A VDD0_S ATA.

127 mA (A01, AVDD0 & 1)

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

Geyser Track pad/Key board

AirPor t (PCI e Mini- Card)

Extern al D

Extern al A

Camera

Blueto oth

IR

Extern al B

Extern al C

19 mA (A01)

Minimu m 1.02 5V for Gen2 s upport

Expres sCard

43 mA (A01, DVDD0 & 1)

84 mA (A01)

If all SATA_ Cx pins are n ot use d, gro und DVD D1_SAT A and AVDD1_ SATA.

Minimu m 1.02 5V for Gen2 s upport

40 90

9

90

9

90

9

90

9

90

31 90

41 90

50 90

31 90

40 90

32 90

9

90

9

90

40

32 43

2.49K

402

1/16W

1%

MF-LF

402

1/16W

1%

MF-LF

806

402

1/16W MF-LF

8.2K

5%

8.2K

5%

MF-LF

1/16W

402

MF-LF 402

1/16W

8.2K

5%

8.2K

5%

MF-LF

1/16W

402

BGA

OMIT

MCP79- TOPO-B

(8 OF 11 )

39 89

SYNC_DA TE=06/ 18/2008

20 9 6

A.0.0

051-7546

MCP SATA & USB

SYNC_MA STER=T 18_MLB

=PP1V0 5_S0_M CP_SATA _AVDD1

=PP1V0 5_S0_M CP_SATA _DVDD0

SATA_O DD_D2R _P

SATA_O DD_D2R _N

SATA_O DD_R2D _C_N

SATA_O DD_R2D _C_P

SATA_H DD_D2R _N SATA_H DD_D2R _P

SATA_H DD_R2D _C_N

SATA_H DD_R2D _C_P

TP_SAT A_C_D2 RP

TP_SAT A_C_D2 RN

PP1V05 _S0_MC P_PLL_S ATA

USB_EX TA_OC_ L

TP_USB _11N

TP_USB _11P

TP_USB _10P

USB_EX TC_N

USB_EX CARD_N

USB_EX TB_N

USB_EX TB_P

USB_BT _N

USB_BT _P

USB_TP AD_N

USB_TP AD_P

USB_IR _N

USB_IR _P

USB_CA MERA_N

USB_CA MERA_P

USB_EX TD_N

USB_EX TD_P

USB_MI NI_N

USB_EX TA_N

USB_EX TA_P

MCP_SA TA_TER MP

TP_SAT A_F_D2 RP

TP_SAT A_F_D2 RN

TP_SAT A_F_R2 D_CN

TP_SAT A_E_D2 RN

TP_SAT A_D_R2 D_CN

TP_SAT A_C_R2 D_CN

TP_SAT A_C_R2 D_CP

TP_MCP _SATAL ED_L

TP_SAT A_D_D2 RN

TP_SAT A_E_R2 D_CP TP_SAT A_E_R2 D_CN

TP_SAT A_E_D2 RP

USB_EX TC_P

USB_EX CARD_P

TP_SAT A_D_D2 RP

=PP1V0 5_S0_M CP_SATA _DVDD1

=PP1V0 5_S0_M CP_SATA _AVDD0

TP_SAT A_F_R2 D_CP

TP_SAT A_D_R2 D_CP

USB_EX TB_OC_ L

PP3V3_ S0_MCP _PLL_US B

MCP_US B_RBIA S_GND

EXCARD _OC_L

TP_USB _10N

USB_EX TC_OC_ L

=PP3V3 _S5_MC P_GPIO

USB_MI NI_P

R2010

1

2

R2060

1

2

R2053

1

2

R2052

1

2

R2051

1

2

R2050

1

2

U1400

AD35

AD37

AD38

AE22

AE24

AE39

AE4

AD6

AF16

AF17

AF18

AF20

AF22

AF26

AF27

AF28

AF33

AF34

AF37

AF40

AG18

AG20

AG22

AG26

AG36

AG40

AH18

AH20

AH22

AH24

AJ12

AN11

AK12

AK13

AL12

AM11

AM12

AN12

AL13

AN14

AL14

AM13

AM14

AF19

AG16

AG17

AG19

AH17

AH19

AE16

L28

AJ5

AJ4

AJ6

AJ7

AJ9

AK9

AJ10

AJ11

AJ2

AJ1

AJ3

AK2

AL4

AK3

AL3

AM4

AM2

AM3

AM1

AN1

AN3

AN2

AP2

AP3

E12

AE3

D29

C29

G25

F25

L23

K23

D28

C28

B28

A28

G29

F29

L27

K27

J27

J26

G27

F27

E27

D27

L25

K25

J25

H25

L21

K21

J21

H21

A27

18

9

8

24

89

9

8

24

90

8

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

HDA_SDAT A_IN1/GP IO_2/PS2 _KB_CLK

HDA_SDAT A_IN2/GP IO_3/PS2 _KB_DATA

MCP_VID2 /GPIO_15

MCP_VID1 /GPIO_14

MCP_VID0 /GPIO_13

THERM_DI ODE_N

EXT_SMI/ GPIO_32#

FANCTL1/ GPIO_62

FANRPM1/ GPIO_63

FANCTL0/ GPIO_61

FANRPM0/ GPIO_60

SIO_PME#

KBRDRSTI N#

PKG_TEST

TEST_MOD E_EN

BUF_SIO_ CLK

CPUVDD_E N

SMB_DATA 0

SMB_CLK0

SPKR

HDA_RESE T#

HDA_SYNC

HDA_BITC LK

HDA_SDAT A_OUT

XTALIN_R TC

XTALOUT

XTALOUT_ RTC

JTAG_TRS T#

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI

JTAG_TDO

RTC_RST#

PS_PWRGD

PWRGD_SB

INTRUDER #

LID#

LLB#

PWRBTN#

RSTBTN#

CPU_DPRS LPVR

SLP_S5#

SLP_S3#

HDA_DOCK _RST#/GP IO_5/PS2 _MS_DATA

HDA_DOCK _EN#/GPI O_4/PS2_ MS_CLK

A20GATE

GPIO_12/ SUS_STAT# /ACCLMTR

HDA_SDAT A_IN0

GPIO_1/P WRDN_OK/ SPI_CS1

HDA_PULL DN_COMP

THERM_DI ODE_P

SLP_RMGT #

SMB_CLK1 /MSMB_CL K

SMB_DATA 1/MSMB_D ATA

SMB_ALER T#/GPIO_ 64

SPI_CS0/ GPIO_10

SPI_CLK/ GPIO_11

SPI_DI/G PIO_8

SPI_DO/G PIO_9

SUS_CLK/ GPIO_34

+V_DUAL_ HDA1

+V_DUAL_ HDA2

+V_PLL_N V_H

+V_PLL_S P_SPREF

HDA

MISC

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

(MGPIO 2)

(MGPIO 3)

Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA ( A01)

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

HDA Output Caps

For EM I Redu ction o n HDA interf ace

PCI

not us e LPC f or Boo tROM o verrid e.

LPC_FR AME# h igh for SPI1 ROM ov erride .

SPI0 = SPI_C S0_L, S PI1 = SPI_CS 1_L

Int PU

Int PU (S5)

Int PU

25 MHz

42 MHz

0

LPC RO Ms. So Apple desig ns wil l

0

1

HDA_SYNC

24 MHz

0

1

0

SPI_CLK

SPI_DO

0

1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not pr ovided on th is pag e.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does no t supp ort FW H, onl y

LPC

SPI0

SPI1

I/F HDA_SDOUT

BIOS Boot Select

R1961 and R2 160 sel ects S PI0 RO M by defaul t, LPC + debug card pulls

1

0

LPC_FRAME#

0

1

0

1

Int PU

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not su pport SPI1 o ption. Rev B 01 wil l.

Int PU

Int PU (S5)

(MXM_O K for MXM sys tems)

SAFE m ode: F or ROMS IP r ecovery

USER m ode: N ormal

Connec ts to SMC for automa tic re covery.

44 90

7

34 37 42 44 68 81 83

40 42 43 68

7

13 45 90

45 90

7

13 45 90

45 90

21 65

48 95

21 65

21 31 34

48 95

9

62 87

23 42

54 90

9

90

54 90

MF-LF

1/16W

1%

402

49.9K

1%

49.9K

MF-LF

402

1/16W

1K

MF-LF

1% 1/16W

402

26 90

23 42

MF-LF

402

5%

22

1/16W

MF-LF

5%

1/16W

402

22

5%

22

MF-LF

1/16W

402

5%

10K

MF-LF

1/16W

MF-LF

8.2K

5% 1/16W

402

5%

10K

MF-LF

BOOT_M ODE_SA FE

402

1/16W

5%

10K

402

MF-LF

BOOT_M ODE_US ER

1/16W

402

5%

22

1/16W MF-LF

9

44

49.9

MF-LF

1/16W

1%

402

1/16W MF-LF

5%

10K

6

13 23

6

13 23

6

13

6

13

6

10PF

50V

5%

402

CERM

50V

10PF

5%

402

CERM

50V

10PF

5%

402

CERM

50V

10PF

5%

402

CERM

BGA

(9 OF 11 )

MCP79- TOPO-B

OMIT

39

21 59

26 26

34 37 42 43

21 28 29 42

402

1/16W MF-LF

5%

100K

10K

5% 1/16W

402

MF-LF

402

1/16W MF-LF

5%

10K

22K

5%

MF-LF

1/16W

402

22K

5%

MF-LF

1/16W

402402

1/16W

22K

5%

MF-LF

402

MF-LF

5% 1/16W

100K

1/16W MF-LF

5%

100K

402

MF-LF 402

1/16W

5%

10K10K

5%

MF-LF

1/16W

402

9

21 43

26

42

23 42

23 26

44 90

MCP HDA & MISC

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

21 9 6

A.0.0

051-7546

TP_MCP _BUF_S IO_CLK

=PP3V3 R1V5_S 0_MCP_H DA

MCP_GP IO_4

AP_PWR _EN

=PP3V3 _S3_MC P_GPIO

AUD_I2 C_INT_ L

MCP_GP IO_4

MCP_CP U_VLD

MCP_VI D<0>

PM_DPR SLPVR

HDA_SD IN0

MCP_VI D<0>

MCP_TH MDIODE _P

SMBUS_ MCP_1_ CLK

TP_MCP _LID_L

PM_PWR BTN_L

RTC_RS T_L

MCP_PS _PWRGD

JTAG_M CP_TDI JTAG_M CP_TDO

SMBUS_ MCP_1_ DATA AP_PWR _EN

MCP_VI D<2>

SMBUS_ MCP_0_ DATA

PM_BAT LOW_L

HDA_SD OUT_R

HDA_BI T_CLK_ R

=SPI_C S1_R_L _USE_ML B

SPI_CL K_R

SMC_RU NTIME_ SCI_L

MCP_VI D<1>

PM_SLP _RMGT_ L

TP_SB_ A20GAT E

MCP_HD A_PULL DN_COMP

PP1V05 _S0_MC P_PLL_N V

SPI_CS 0_R_L

RTC_CL K32K_X TALOUT

RTC_CL K32K_X TALIN

MCP_CL K25M_X TALOUT

MCP_CL K25M_X TALIN

JTAG_M CP_TCK

PM_CLK 32K_SU SCLK_R

SPI_MI SO SPI_MO SI_R

SMBUS_ MCP_0_ CLK

MCP_TH MDIODE _N

PM_SYS RST_DE BOUNCE_ L

TP_MCP _KBDRS TIN_L

HDA_RS T_L

HDA_BI T_CLK

HDA_SD OUT

PP3V3_ G3_RTC

=PP3V3 R1V5_S 0_MCP_H DA

HDA_SY NC_R

HDA_SD OUT_R

HDA_RS T_R_L

HDA_BI T_CLK_ R

MCP_VI D<2>

MCP_VI D<1>

JTAG_M CP_TMS

MCP_TE ST_MOD E_EN

JTAG_M CP_TRS T_L

PM_RSM RST_L

SM_INT RUDER_ L

ARB_DE TECT

HDA_SY NC

HDA_RS T_R_L

ODD_PW R_EN_L

MEM_EV ENT_L

SMC_WA KE_SCI _L

=PP3V3 _S0_MC P_GPIO

MEM_EV ENT_L SMC_IG _THROT TLE_L

SMC_AD APTER_ EN

TP_MLB _RAM_V ENDOR

TP_MLB _RAM_S IZE

HDA_SY NC_R

AUD_I2 C_INT_ L

PM_SLP _S3_L

PM_SLP _S4_L

=PP3V3 _S0_MC P

MCP_SP KR

MCP_CP UVDD_E N

ARB_DE TECT

SMC_IG _THROT TLE_L

R2121

1

2

R2120

1

2

R2190

1

2

R2170

1 2

R2171

1 2

R2173

1 2

R2163

1

2

R2160

1

2

R2180

1

2

R2181

1

2

R2172

1 2

R2110

1

2

R2150

1

2

C2171

1

2

C2173

1

2

C2170

1

2

C2172

1

2

U1400

K13

AE7

M22

C17 D17

C18

A12

C12

B12

D12

L26

L24

E15

K17

L17

A15

K15

G15

J14

J15

F15

L15

B20

G19

E19

F19

J19

J18

L13

M25

M24

L20

M20

M21

J16

K16

AE18

AE17

L22

E20

C16

D20

D16

C20

C19

J17

G17

H17

M23

L19

G21

K19

F21

D13

C14

C15

B14

C13

B18

K22

C11

B11

A16

A19

B16

B19

R2147

1

2

R2142

1

2

R2141

1

2

R2157

1

2

R2156

1

2

R2155

1

2

R2151

1

2

R2154

2

1

R2143

1

2

R2140

1

2

42

24

34

24

19

29

24

21

31

59

65

90

26

21

90

65

90

18

28

43

90

22

8

21

8

21

23

21

90

24

22

8

21

8

21

8

21

GND

GND161

GND165

GND166

GND164

GND163

GND162

GND167

GND168

GND171

GND170

GND169

GND172

GND173

GND176

GND175

GND174

GND177

GND178

GND181

GND180

GND179

GND182

GND183

GND184

GND187

GND186

GND185

GND188

GND189

GND192

GND191

GND190

GND193

GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206

GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213

GND214

GND217

GND216

GND215

GND218

GND219

GND222

GND221

GND220

GND223

GND224

GND225

GND228

GND227

GND226

GND229

GND230

GND233

GND232

GND231

GND234

GND235

GND238

GND237

GND236

GND239

GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331

GND332

GND330

GND329

GND328

GND326

GND327

GND325

GND324

GND323

GND321

GND322

GND320

GND319

GND318

GND316

GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305

GND306

GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285

GND286

GND284

GND283

GND282

GND280

GND281

GND279

GND278

GND277

GND275

GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264

GND265

GND266

GND263

GND262

GND259

GND260

GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPU CLK

+VDD_COR E42

+3.3V_DU AL_USB2

+VTT_CPU 17

+VTT_CPU 16

+VTT_CPU 15

+VTT_CPU 14

+VTT_CPU 13

+VTT_CPU 12

+VTT_CPU 11

+VTT_CPU 10

+VTT_CPU 1

+VDD_COR E7

+VDD_COR E1

+VDD_COR E2

+VDD_COR E3

+VDD_COR E4

+VDD_COR E5

+VDD_COR E6

+VDD_COR E13

+VDD_COR E14

+VDD_COR E15

+VDD_COR E16

+VDD_COR E17

+VDD_COR E18

+VDD_COR E19

+VDD_COR E21

+VDD_COR E22

+VDD_COR E23

+VDD_COR E24

+VDD_COR E25

+VDD_COR E26

+VDD_COR E27

+VDD_COR E28

+VDD_COR E29

+VDD_COR E30

+VDD_COR E32

+VDD_COR E33

+VDD_COR E34

+VDD_COR E35

+VDD_COR E36

+VDD_COR E37

+VDD_COR E39

+VDD_COR E40

+VDD_COR E41

+VDD_COR E47

+VDD_COR E48

+VDD_COR E49

+VDD_COR E50

+VDD_COR E51

+VDD_COR E52

+VDD_COR E53

+VDD_COR E54

+VTT_CPU 51

+VTT_CPU 50

+VTT_CPU 47

+VTT_CPU 46

+VTT_CPU 45

+VTT_CPU 43

+VTT_CPU 42

+VTT_CPU 41

+VTT_CPU 40

+VTT_CPU 39

+VTT_CPU 38

+VTT_CPU 37

+VTT_CPU 36

+VTT_CPU 35

+VTT_CPU 34

+VTT_CPU 32

+VTT_CPU 31

+VTT_CPU 30

+VTT_CPU 29

+VTT_CPU 28

+VTT_CPU 26

+VTT_CPU 25

+VTT_CPU 24

+VTT_CPU 23

+VTT_CPU 22

+VTT_CPU 21

+VTT_CPU 20

+VTT_CPU 19

+VTT_CPU 18

+VTT_CPU 9

+VTT_CPU 8

+VTT_CPU 7

+VTT_CPU 6

+VTT_CPU 5

+VTT_CPU 4

+VTT_CPU 3

+VDD_COR E38

+VTT_CPU 33

+VTT_CPU 27

+VDD_COR E55

+VDD_COR E56

+VDD_COR E57

+VDD_COR E58

+VDD_COR E59

+VDD_COR E60

+VDD_COR E61

+VDD_COR E62

+VDD_COR E63

+VDD_COR E64

+VDD_COR E65

+VDD_COR E66

+VDD_COR E67

+VDD_COR E68

+VDD_COR E69

+VDD_COR E70

+VDD_COR E71

+VDD_COR E72

+VDD_COR E73

+VDD_COR E74

+VDD_COR E75

+VDD_COR E76

+VDD_COR E77

+VDD_COR E78

+VDD_COR E79

+VDD_COR E80

+VDD_COR E81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DU AL1

+3.3V_DU AL2

+3.3V_DU AL3

+3.3V_DU AL4

+3.3V_DU AL_USB1

+3.3V_DU AL_USB3

+3.3V_DU AL_USB4

+VDD_AUX C1

+VDD_AUX C3

+VDD_AUX C2

+VDD_COR E43

+VTT_CPU 2

+VDD_COR E46

+VDD_COR E45

+VDD_COR E44

+VTT_CPU 52

+VDD_COR E31

+VTT_CPU 49

+VTT_CPU 48

+VTT_CPU 44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_COR E20

+VDD_COR E12

+VDD_COR E11

+VDD_COR E10

+VDD_COR E9

+VDD_COR E8

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

105 mA (A01)

43 mA

1139 m A

250 mA

16996 mA (A0 1, 1.0V )

23065 mA (A0 1, 1.2V )

80 uA (S0)

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

10 uA (G3)

16 mA

266 mA (A01)

450 mA (A01)

1182 m A (A01 )

BGA

OMIT

MCP79- TOPO-B

(11 OF 1 1) (10 OF 1 1)

BGA

MCP79- TOPO-B

OMIT

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

051-7546

A.0.0

9622

MCP Power & Ground

=PP1V0 5_S0_M CP_FSB

=PPVCO RE_S0_ MCP

PP3V3_ G3_RTC

=PP3V3 _S0_MC P

=PP1V0 5_S5_M CP_VDD_ AUXC

=PP3V3 _S5_MC P

U1400

AH26

AH33

AH34

AH37

AH38

AJ39

AJ8

AK10

AK33

AK34

AK37

AK4

AK40

AL36

AL40

AL5

AM10

AM16

AM18

AM20

AM22

AM24

AM26

AM30

AM34

AM35

AM37

AM38

AM5

AM6

AM7

AM9

AP26

AN28

AN30

AN39

AN4

Y7

AP10

AU26

AP14

AU14

AP28

AP32

AP34

AP36

AP37

AP4

AP40

AP7

AW23

AR28

AR32

AR40

AT10

AR12

AT13

AT29

AT33

AT6

AT7

AT9

AY21

AY22

L12

AU12

AU28

AP33

AU32

AR30

AU36

AU38

AU4

G28

F20

AV28

AV32

AV36

AV4

AV7

AW11

G20

AR43

AW43

AY10

AV12

AY30

AY33

AY34

AY37

AY38

AY41

AV40

BA1

BA4

AW31

AY6

L35

BC33

BC37

BC41

AY14

BC5

C2

D10

D14

D15

D18

D19

D22

D23

D26

D30

D37

D6

E13

E17

E21

E25

E29

E33

F12

F16

F32

F8

G10

G12

G14

G16

BC12

G22

G24

AW20

G34

G4

G43

G6

G8

H11

H15

AW35

H23

AN8

G40

J12

J8

K10

K12

K18

K26

K37

K4

K40

K8

AU1

L40

L43

L5

M10

M34

M35

M37

Y28

Y33

Y34

Y35

Y37

Y38

AB17

AB16

AN26

AD7

M11

AA4

AB19

AY13

P11

Y6

T11

V11

Y11

AH16

T22

U1400

AD10

AE8

AB10

AD9

Y10

AB11

AA8

Y9

G18

H19

J20

K20

G26

H27

J28

K28

A20

T21

U21

V21

AA25

AA26

AA27

AA28

AC16

AC17

AC18

AC19

AC20

AC21

AA17

AC23

AC24

AC25

AC26

AC27

AC28

AD21

AD23

W27

V25

AA18

U25

AE19

AE21

AE23

AE25

AE26

AE27

AE28

AF10

AF11

AA19

AH12

AF2

AF21

AF23

AF25

AF3

AF4

AF7

AH23

AF9

AA20

AG10

AG11

AG12

AG21

AG23

AG25

AG3

AG4

AA21

AG6

AG7

AG5

AG8

AG9

AH1

AH10

AH11

W26

AH2

AA23

W28

AH25

Y21

AH21

AH3

AH4

AH5

AH6

AH7

AH9

AA24

W21

W23

Y23

W25

AF12

AA16

R32

P31

AF32

AE32

AH32

AJ32

AK31

AK32

AD32

AL31

AB32

AC32

B41

B42

C40

C41

C42

D39

D40

D41

E38

E39

E40

F37

F38

F39

G36

G37

G38

H35

H37

J34

J35

J36

K33

K34

K35

L32

L33

L34

M31

M32

M33

N31

N32

P32

Y32

AA32

T32

U32

V32

W32

AG32

24 14 46

24

9

24

26

21

24

8 8

21

8

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

3.3V Interface Pull-ups

These intern al pull -ups a re mis sing i n Revs A01 & A01P.

MCP_A0 1&MCP_ A01P&MC P_A01Q

402

MF-LF1/16W

5%

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

402

MF-LF1/16W

5%

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

5%

1/16W MF-LF

402

10K

5%

1/16W MF-LF

402

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

5%

1/16W MF-LF

402

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

5%

1/16W MF-LF

402

10K

13 19

17 31 32

6

13 21

6

13 21

21 26

21

21 42

MCP_A0 1&MCP_ A01P&MC P_A01Q

5%

1/16W MF-LF

402

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

402

MF-LF1/16W

5%

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

10K

402

MF-LF1/16W

5%

MCP_A0 1&MCP_ A01P&MC P_A01Q

5%

1/16W MF-LF

402

10K

SYNC_D ATE=03 /31/200 8

SYNC_M ASTER= T18_MLB

MCP79 A01 Silicon Support

051-7546

A.0.0

9623

PM_LAT RIGGER _L

PM_SYS RST_DE BOUNCE_ L

SMC_WA KE_SCI _L

PM_BAT LOW_L

PM_PWR BTN_L

SMC_RU NTIME_ SCI_L

JTAG_M CP_TMS

JTAG_M CP_TDI

PCIE_W AKE_L

MAKE_BAS E=TRUE

MCP_LI D_L

TP_MCP _LID_L

=PP3V3 _S5_MC P_A01

R2412

1 2

R2411

1 2

R2410

1 2

R2403

1 2

R2402

1 2

R2401

1 2

R2400

1 2

R2404

1 2

R2413

1 2

R2405

1 2

44

8

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Apple: 4x 4. 7uF 040 2, 4x 1uF 04 02, 6x 0.1uF 0402 ( 23.4 u F)

NV: 1x 10uF 0805, 2 x 4.7u F 0402 , 3x 1 uF 0402 , 9x 0 .1uF 0 402 (2 3.3 uF )

5 mA ( A01)

MCP SA TA (DV DD) Pow er

NV: 1x 4.7uF 0603, 4x 0.1 uF 040 2 (5.1 uF) Apple: 4x 2. 2uF 040 2 (8.8 uF)

1182 m A (A01 )

7 mA ( A01)

19 mA (A01)

333 mA (A01)

4771 m A (A01 , DDR3)

MCP Co re Pow er

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF)

MCP 3. 3V Pow er

MCP Me mory P ower

MCP FS B (VTT ) Power

Apple: 1x 2. 2uF 040 2 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF)

NV: 1x 10uF 0805, 1 x 4.7u F 0402 , 2x 0 .1uF 04 02 (14 .9 uF) Apple: 7x 2. 2uF 040 2 (15. 4 uF)

Apple: 5x 2. 2uF 040 2 (11 uF)

Apple: 1x 2. 2uF 040 2 (2.2 uF)

MCP 1. 05V AU X Power

5 mA ( A01)

MCP 3. 3V/1.5 V HDA P ower

266 mA (A01)

MCP 3. 3V AUX /USB Po wer

Apple: 1x 2. 2uF 040 2 (2.2 uF)

MCP79 Ethernet VRef

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF)

MCP 3. 3V Eth ernet P ower

MCP 1. 05V RM GT Powe r

(No IG vs. E G data)

23065 mA (A0 1, 1.2V ) 16996 mA (A0 1, 1.0V )

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF)

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

MCP PC IE (DV DD) Pow er

105 mA (A01) 131 mA (A01)

83 mA (A01)

84 mA (A01)

87 mA (A01)

37 mA (A01)

206 mA (A01)

127 mA (A01)

43 mA (A01)57 mA (A 01)

450 mA (A01)

19 mA (A01)

562 mA (A01)

NV: 1x 10uF 0805, 1 x 4.7u F 0402 , 2x 1 uF 0402 , 2x 0 .1uF 0 402 (1 6.9 uF )

NV: 1x 10uF 0805, 1 x 4.7u F 0402 , 2x 0 .1uF 04 02 (14 .9 uF) Apple: 2x 2. 2uF 040 2 (4.4 uF)

270 mA (A01)

402

X5R

20%

4.7UF

4V

402

X5R

4V

4.7UF

20%

402

X5R

4V

20%

4.7UF

402

X5R

20%

4.7UF

4V

6.3V

2.2UF

20%

402-LF

CERM

402

X5R

20%

4V

4.7UF

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

402

20%

CERM

0.1UF

10V

402

20%

CERM

0.1UF

10V

402

20%

CERM

0.1UF

10V

402

20%

CERM

0.1UF

10V

402

20%

CERM

0.1UF

10V

402

20%

CERM

0.1UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

6.3V

2.2UF

20%

CERM 402-LF

20%

2.2UF

6.3V

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

402

X5R

20%

4V

4.7UF

CERM 402-LF

CERM

402-LF

20%

2.2UF

6.3V

402

X5R

20%

4.7UF

4V

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

402-LF

CERMCERM

402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

0.1UF

CERM

20%

10V

402

20%

CERM

0.1UF

402

X5R

4V

4.7UF

20%

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

402

X5R

4V

20%

4.7UF

30-OHM -5A

0603

30-OHM -5A

0402

30-OHM -1.7A

0402

30-OHM -1.7A

0402

30-OHM -1.7A

0402

30-OHM -1.7A

0402

402

20%

4V

4.7UF

402

X5R

20%

4V

4.7UF

10V

402

0.1uF

20%

CERM

10V

402

0.1uF

20%

CERM

CERM 402-LF

20%

2.2UF

6.3V

10V

402

20%

0.1UF

CERM

10V

402

20%

0.1UF

CERM

402

X5R

4V

4.7UF

20%

0402

30-OHM -1.7A

402

MF-LF

1%

1/16W

1.47K

10V

402

20%

CERM

0.1UF

402

1.47K

1/16W

1%

MF-LF

18

10V

402

0.1uF

20%

CERM

10V

402

CERM

20%

0.1uF

10V

402

20%

CERM

0.1uF

10V

402

20%

0.1UF

CERM

10V

402

0.1UF

CERM

20%

10V

402

0.1UF

CERM

20%

10V

402

0.1UF

20%

CERM

10V

402

0.1uF

20%

CERM

402

X5R

4V

4.7uF

20%

402

X5R

20%

4V

4.7UF

96

051-7546

A.0.0

24

MCP Standard Decoupling

SYNC_MA STER=T 18_MLB

SYNC_DA TE=06/ 18/2008

VOLTAGE= 1.05V

PP1V05 _S0_MC P_PLL_N V

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .4 MM

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .4 MM

VOLTAGE= 1.05V

PP1V05 _S0_MC P_PLL_C ORE

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM

PP1V05 _S0_MC P_SATA_ AVDD

VOLTAGE= 1.05V

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM

PP1V05 _S0_MC P_PEX_A VDD

VOLTAGE= 1.05V

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM VOLTAGE= 3.3V

PP3V3_ S0_MCP _PLL_US B

VOLTAGE= 1.05V

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .4 MM

PP1V05 _S0_MC P_PLL_P EX

PP1V05 _S0_MC P_PLL_S ATA

VOLTAGE= 1.05V

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM

MIN_NECK _WIDTH=0 .2 MM VOLTAGE= 1.05V

MIN_LINE _WIDTH=0 .4 MM

PP1V05 _ENET_ MCP_PLL _MAC

=PP1V0 5_ENET _MCP_PL L_MAC

=PP3V3 _ENET_ MCP_RMG T

MCP_MI I_VREF

=PP3V3 _S0_MC P

=PP3V3 R1V5_S 0_MCP_H DA

=PP3V3 _S5_MC P

=PP1V0 5_S0_M CP_AVDD _UF

=PP1V0 5_S0_M CP_FSB

=PP1V8 R1V5_S 0_MCP_M EM

=PP1V0 5_S5_M CP_VDD_ AUXC

=PP1V0 5_ENET _MCP_RM GT

=PP3V3 _S0_MC P_PLL_U F

=PPVCO RE_S0_ MCP

=PP3V3 _ENET_ MCP_RMG T

=PP1V0 5_S0_M CP_SATA _DVDD

=PP1V0 5_S0_M CP_PEX_ DVDD

=PP1V0 5_S0_M CP_PLL_ UF

6.3V

20%

VOLTAGE= 1.05V

20%

CERM

6.3V

402-LF

2.2UF

X5R

6.3V

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

PP1V05 _S0_MC P_PLL_F SB

0603

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM

402-HF

MF

1/6W

0.2

1%

C2503

1

2

C2582

1

2

C2588

1

2

C2584

1

2

C2586

1

2

C2555

1

2

C2502

1

2

C2507

1

2

C2506

1

2

C2505

1

2

C2504

1

2

C2511

1

2

C2510

1

2

C2509

1

2

C2508

1

2

C2513

1

2

C2512

1

2

C2536

1

2

C2535

1

2

C2534

1

2

C2533

1

2

C2532

1

2

C2531

1

2

C2530

1

2

C2517

1

2

C2516

1

2

C2515

1

2

C2572

1

2

C2571

1

2

C2520

1

2

C2570

1

2

C2574

1

2

C2573

1

2

C2576

1

2

C2575

1

2

C2553

1

2

C2552

1

2

C2551

1

2

C2550

1

2

C2549

1

2

C2548

1

2

C2547

1

2

C2546

1

2

C2545

1

2

C2544

1

2

C2543

1

2

C2542

1

2

C2541

1

2

C2540

1

2

C2562

1

2

C2564

1

2

C2580

1

2

L2570

1 2

L2575

1 2

L2582

1 2

L2584

1 2

L2588

1 2

L2586

1 2

L2555

1 2

C2500

1

2

C2501

1

2

C2526

1

2

C2525

1

2

C2560

1

2

C2589

1

2

C2590

1

2

C2595

1

2

L2595

1 2

R2590

1

2

C2591

1

2

R2591

1

2

C2521

1

2

C2518

1

2

C2519

1

2

C2581

1

2

C2583

1

2

C2585

1

2

C2587

1

2

C2596

1

2

C2529

1

2

C2528

1

2

R2580

1 2

22

24

22

14

46

24

18

21

22

9

16

22 18

22

18

21

16

8

20

17

20

14

18

8

8 8

8

8 8

8

A2

A1

SCL

A0

VCC

SDA

WP

GND

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

206 mA (A01)

NV: 1x 4.7uF 0603, 2x 0.1 uF 040 2 (4.9 uF)

206 mA (A01)

Apple: 2x 2. 2uF 040 2 (4.4 uF)

16 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF) Apple: ???

HDCP ROM

16 mA (A01)

190 mA (A01, 1.8V)

WF: Op en que stion o n whic h pack ge opt ion(s) nVidia can s upport .

Curren t numb ers fro m emai l Xiao wei Li n provi ded 11 /12/20 07 3:2 2pm (n o offic ial do cument numbe r).

WF: Ch ecklis t says 0-ohm resist or pla ceholde r for ferrit e bead .

Apple: 1x 2. 2uF 040 2 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF)

WF: Ch ecklis t says 0-ohm resist or pla ceholde r for ferrit e bead .

95 mA (A01)

6.3V CERM 402-LF

NO STU FF

2.2UF

20%

NO STU FF

30-OHM -1.7A

0402

NO STU FF

20%

0.1UF

402

10V

NO STU FF

402

1K

1% 1/16W MF-LF

0.1UF

20%

402

CERM

NO STU FF

10V

20%

4.7UF

4V

402

X5R

CERM

4.7UF

6.3V

20%

603

30-OHM -1.7A

0402

20%

402

CERM

10V

0.1uF

OMIT

SOIC

AT24C08

402

10V

0.1UF

20%

CERM

10K

MF-LF

5%

1/16W

402

45

402

MF-LF

1/16W

5%

0

MF-LF

1K

1% 1/16W

CERM 402-LF

20%

2.2UF

6.3V

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=A MASON_M 98_MLB

MCP Graphics Support

25 9 6

A.0.0

051-7546

TP_MCP _RGB_R ED

TP_MCP _RGB_G REEN

CRT_IG _B_COM P_PB

MCP_CL K27M_X TALIN

MCP_CL K27M_X TALOUT

PP3V3_ S0_MCP _DAC

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM VOLTAGE= 3.3V

MCP_IF PAB_VP ROBE

MCP_TV _DAC_R SET

MCP_TV _DAC_V REF

MAKE_BASE=T RUE

NC_MCP _TV_DA C_VREF

MAKE_BASE=T RUE

NC_MCP _CLK27 M_XTALI N

MAKE_BASE=T RUE

NC_MCP _CLK27 M_XTALO UT

NC_MCP _TV_DA C_RSET

MAKE_BASE=T RUE

TP_MCP _RGB_D AC_VREF

=PP3V3 _S0_MC P_DAC_U F

MCP_HD MI_VPR OBE

HDCPRO M_WP

VOLTAGE= 3.3V

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM

PP3V3_ S0_MCP _VPLL

MAKE_BASE=T RUE

NC_MCP _RGB_B LUE

MAKE_BASE=T RUE

NC_MCP _RGB_H SYNCTP_MCP _RGB_H SYNC

TP_MCP _RGB_V SYNC

TP_MCP _RGB_B LUE

MAKE_BASE=T RUE

NC_MCP _RGB_G REEN

MAKE_BASE=T RUE

NC_MCP _RGB_R ED

MAKE_BASE=T RUE

NC_MCP _RGB_V SYNC

CRT_IG _R_C_P R

MAKE_BASE=T RUE

NC_CRT _IG_R_ C_PR

TP_MCP _RGB_D AC_RSET

MAKE_BASE=T RUE

NC_MCP _RGB_D AC_VREF

MAKE_BASE=T RUE

NC_CRT _IG_VS YNC

CRT_IG _VSYNC

MAKE_BASE=T RUE

NC_CRT _IG_HS YNC

CRT_IG _HSYNC

MAKE_BASE=T RUE

NC_CRT _IG_B_ COMP_PB

MAKE_BASE=T RUE

NC_CRT _IG_G_ Y_Y

CRT_IG _G_Y_Y

MAKE_BASE=T RUE

NC_MCP _RGB_D AC_RSET

=PP3V3 R1V8_S 0_MCP_I FP_VDD

=PP1V0 5_S0_M CP_HDMI _VDD

=PP3V3 _S0_MC P_VPLL_ UF

=I2C_H DCPROM _SDA =I2C_H DCPROM _SCL

=PP3V3 _S0_HD CPROM

MCP_IF PAB_RS ET

CERM

402

MCP_HD MI_RSE T

CERM

20%

2.2UF

402-LF

6.3V

R2620

1

2

C2610

1

2

C2650

1

2

L2650

1 2

C2620

1

2

R2630

1

2

C2630

1

2

C2615

1

2

C2640

1

2

L2640

1 2

C2641

1

2

C2616

1

2

U2695

1

2

3

4

6

5

8

7

C2690

1

2

R2690

1

2

R2651

1

2

89

18

89 89

18

8

18

8

18

8

18

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

Y

B

A

VIN

GND

VOUTEN

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

but re sults in MCP7 9 ROMS IP seq uence happeni ng aft er CPU power s up.

NOTE: If CPU _VLD de assert s duri ng S0 MCP79 w ill ta ke sys tem to S5 im mediate ly.

CPUVDD _EN (w hich is 40-10 0ms af ter PS _PWRGD assert ion).

Reset Button

10K pu ll-up to 3.3V S0 in side M CP

LPC Reset (Unbuffered)

Platform Reset Connections

PCIE Reset (Unbuffered)

SMC 99 ms del ay from ALL_S YS_PWR GD to IMVP_VR _ON pl us IMV P6 del ay for

MCP S0 PWRGD & CPU_VLD

VR_PWR GOOD_D ELAY sh ould g uarant ee CPU _VLD do es not go hi gh bef ore

MCPSEQ _SMC r epresen ts MCP 79 'ML B' pow er sequ encing conne ctions ,

MCPSEQ _MIX i s cross betwe en MLB and i nternal power seque ncing, which result s in e arlier ROMSIP and M CP FSB I/O in terfac e init ializa tion.

RTC Crystal

RTC Power Sources

MCP 25MHz Crystal

10 13 21 23

5%

CERM

402

12pF

50V

5%

50V

CERM

402

12pF

402

1/16W

0

5%

MF-LF

1/16W MF-LF

5%

402

10M

NO STU FF

19 83 90

402

0

5%

MF-LF

1/16W

XDP

PLACEMEN T_NOTE=P lace clo se to U1 400

33

MF-LF

5%

1/16W

402

33

5% 1/16W MF-LF

PLACEMEN T_NOTE=P lace clo se to U1 400

402

MF-LF

402

1/16W

5%

0

402

MF-LF

1/16W

5%

0

OMIT

SILK_PART=FP SYS RESET

44

42

21

9

17

PLACEMEN T_NOTE=P lace clo se to U1 400

33

5%

MF-LF

1/16W

402

5%

33

MF-LF

1/16W

PLACEMEN T_NOTE=P lace clo se to U1 400

402

19 90

12pF

402

CERM

5%

50V

12pF

5%

CERM

402

CRITIC AL

25.000 0M

SM-3.2X2 .5MM

402

5%

MF-LF

1/16W

0

1M

5%

1/16W

402

MF-LF

NO STU FF

21

42 90

PLACEMEN T_NOTE=P lace clo se to U1 400

402

MF-LF

5% 1/16W

22

21 90

1/16W

5%

MF-LF

33

402

10V X5R

10%

1UF

NO STU FF

36

MF-LF

1/16W

5%

0

402

9

33

402

5% 1/16W MF-LF

19

42

44 90

42 90

CRITIC AL

32.768 K

7X1.5X1.4 -SM

0

5% 1/16W MF-LF

402

27

402

MF-LF

1/16W

5%

0

85

402

MF-LF

1/16W

5%

0

32

31

1/16W

0

402

5%

MF-LF

33

MF-LF

402

1/16W

5%

PLACEMEN T_NOTE=P lace clo se to U1 400

83

21

62

42 68

402

0

1/16W

5%

MF-LF

MCPSEQ _MIX

20%

MCPSEQ _SMC

10V CERM 402

0.1UF

PLACEMEN T_NOTE=P lace clo se to U1 400

402

0

1/16W MF-LF

5%

MCPSEQ _SMC

21

MF-LF

5%

1/16W

0

402

MCPSEQ _SMC

21

MF-LF

5%

1/16W

0

402

MCPSEQ _MIX

MCPSEQ _SMC

TC7SZ08A FEAPE

SOT665

1UF

10% 10V X5R 402

TSOT-23- 5

MIC5232 -2.8YD 5

10

5%

402

1/16W MF-LF

1.0M

5%

NO STU FF

1/10W

603

MF-LF

6.3V

10%

402

CERM

1UF

2%

0.08F

XHHG SM

3.3V

100

5% 1/16W MF-LF 402

051-7546

26

A.0.0

96

SB Misc

SYNC_MA STER=T 18_MLB

SYNC_DA TE=12/ 17/2007

PCIE_R ESET_L

VR_PWR GOOD_D ELAY

S0_AND _IMVP_ PGOOD

ALL_SY S_PWRG D

XDP_DB RESET_ L

PM_SYS RST_DE BOUNCE_ L

PM_SYS RST_L

LPC_RE SET_L

DEBUG_ RESET_ L

SMC_LR ESET_L

LPC_CL K33M_L PCPLUS

LPC_CL K33M_S MC

PM_CLK 32K_SU SCLK

LPC_CL K33M_G MUX

MEM_VT T_EN

MINI_R ESET_L

EXCARD _RESET _L

BKLT_P LT_RST_ L

FW_RES ET_L

PCA955 7D_RES ET_L

LPC_CL K33M_S MC_R

MEM_VT T_EN_R

PM_CLK 32K_SU SCLK_R

MAKE_BAS E=TRUE

GMUX_P CIE_RE SET_L

=GMUX_ PCIE_R ESET_L

MCP_CP UVDD_E N

MCP_CP U_VLD

MCP_PS _PWRGD

=PP3V3 _S5_MC PPWRGD

PP3V3_ G3_SUPE RCAP

RTC_DI SCHARG E_R

MCP_CL K25M_X TALOUT_ R

PP3V3_ G3_RTC

MIN_NECK _WIDTH=0 .2 mm

MIN_LINE _WIDTH=0 .3 mm

VOLTAGE= 3.3V

=PP3V3 _S5_RT C_D

RTC_CL K32K_X TALOUT_ R

RTC_CL K32K_X TALIN

MCP_CL K25M_X TALIN

MCP_CL K25M_X TALOUT

RTC_CL K32K_X TALOUT

C2810

1 2

C2811

1 2

R2810

1 2

R2811

1

2

R2896

1 2

R2883

1 2

R2881

1 2

R2890

1 2

R2897

1

2

R2826

1 2

R2825

1 2

C2815

1 2

C2816

1 2

Y2815

2 4

1 3

R2815

1 2

R2816

1

2

R2829

1 2

R2899

1 2

C2899

1

2

R2892

1 2

R2870

1 2

Y2810

1 4

R2891

1 2

R2893

1 2

R2895

1 2

R2894

1 2

R2827

1 2

R2851

1 2

C2850

1

2

R2850

1 2

R2853

1 2

R2852

1 2

U2850

C2802

1

2

U2801

3

2

4

1

5

R2801

1

2

R2802

12

C2801

1

2

C2800

1

2

R2800

1

2

22 8 21

8

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0

A1 A2

SCL

SDA

P0

P1 P2

P5

P6

P7

P3

P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

Min DAC code 0x00 0x00 0x0 0 0x00 0x00 0 x00

Max sin k I -3.75 mA - 3.75 mA -3.7 5 mA -3.75 mA -0.91 m A -59 .04 mA

Nominal Vref 0.75 V 0.75 V 0.7 5 V 0.75 V 0.70 V 1 .248 V

Max Vre f 1.250 V 1.250 V 1.2 50 V 1.25 0 V 1.044 V 1 .426 V

(i.e. not simultaneously) due to cur rent limitation of TPS51116 regulator.

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

MEM B V REF DQMEM A V REF DQ

(per DA C LSB)

Signal a liases r equired by this page:

NO_VREFM RGN

VREFMRGN

- =I2C_P CA9557D_ SDA

- =I2C_P CA9557D_ SCL

Requir ed zer o ohm r esisto rs whe n no V REF mar gining circu it stu ffed

Power al iases re quired b y this p age:

ADDR=0 x30(WR )/0x31( RD)

Place close to J310 0.1

ADDR=0 x98(WR )/0x99( RD)

- =PP3V3 _S3_VREF MRGN

- =PPVTT _S3_DDR_ BUF

10mA m ax loa d

- =I2C_V REFDACS_ SDA

Page Notes

Place close to U100 0.AD26

Place close to U850 0, U85 50

BOM opti ons prov ided by this pag e:

- =I2C_V REFDACS_ SCL

- =PP3V3 _S5_VREF MRGN

CPU FSB VREF

FRAME B UFFER VREF

MEM B V REF CA

Place close to J320 0.1

Vref St epping 6.5 m V 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1 .5 mV

Min Vre f 0.375 V 0.375 V 0.3 75 V 0.37 5 V 0.091 V 1 .042 V

Max sou rce I 5 mA 5 mA 5 mA 5 m A 0.52 m A 51 .15 mA

Max DAC code 0x87 0x87 0x8 7 0x87 0x55 0 xFF

DAC cha nnel A B A B C D

MEM A V REF CA

Place close to J310 0.126

Place close to J320 0.126

Place close to U840 0, U84 50

9

1/16W MF-LF

VREFMRGN

1%

49.9

402

10 87

VREFMR GN

0.1UF

20% 10V

402

CERM

100

402

1%

VREFMRGN

1/16W MF-LF

5%

VREFMRGN

MF-LF

402

1/16W

100K

VREFMRGN

1%

200

1/16W MF-LF

402

MF-LF

1/16W

5%

VREFMRGN

402

100K

9

MF-LF

1/16W

402

49.9

1%

VREFMRGN

UCSP

MAX4253

VREFMRGN

UCSP

VREFMRGN

MAX4253

UCSP

VREFMRGN

MAX4253

UCSP

MAX4253

VREFMRGN

UCSP

VREFMRGN

MAX4253

UCSP

MAX4253

VREFMRGN

1%

200

1/16W MF-LF

402

1/16W

402

200

1%

MF-LF

VREFMRGN

1%

200

1/16W MF-LF

402

VREFMRGN

5%

100K

1/16W MF-LF

402

VREFMRGN

100K

1/16W

5%

402

MF-LF

VREFMRGN

402

100

1% 1/16W MF-LF

VREFMRGN

MF-LF

402

1% 1/16W

100

VREFMRGN

402

MF-LF

1/16W

1%

100

VREFMRGN

MF-LF

VREFMRGN

402

1/16W

100K

5%

PCA9557

VREFMR GN

QFN

VREFMR GN

402

0.1UF

20%

CERM

10V

402

100

MF-LF

1% 1/16W

VREFMRGN

5%

402

1/16W

100K

MF-LF

VREFMRGN

26

45

DAC557 4

MSOP

VREFMR GN

45

10V

402

VREFMR GN

0.1UF

CERM

20%

2.2UF

CERM

6.3V

20%

VREFMR GN

402-LF

VREFMR GN

20%

CERM 402

10V

0.1UF

CERM

0.1UF

VREFMR GN

402

20% 10V

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MA STER=D DR

051-7546

A.0.0

9627

SYNC_DA TE=07/ 22/2008

1 R2909 CRITIC AL

NO_VRE FMRGN

116S00 04

RES,MTL FILM,0,5 %,0402,S M,LF

CRITIC AL1 R2911

NO_VRE FMRGN

116S00 04

RES,MTL FILM,0,5 %,0402,S M,LF

R2903 CRITIC AL

NO_VRE FMRGN

1116S0004

RES,MTL FILM,0,5 %,0402,S M,LF

CRITIC AL1 R2905

NO_VRE FMRGN

116S00 04

RES,MTL FILM,0,5 %,0402,S M,LF

=PPVTT_S 3_DDR_BU F

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.3 mm

PP0V75_ S3_MEM_V REFDQ_A

VREFMRGN_ CA_SODIMMB _BUF

VREFMRGN_ CPUFSB_EN

VREFMRGN_ CPUFSB_BUF

VREFMRGN_ FRAMEBUF_E N

VREFMRGN_ FRAMEBUF_B UF

VREFMRGN_ FRAMEBUF

VREFMRGN_ CA_SODIMMB _EN

VREFMRGN_ CA_SODIMM

VREFMRGN_ DQ_SODIMMA _EN

VREFMRGN_ DQ_SODIMMA _BUF

VREFMRGN_ CA_SODIMMA _EN

VREFMRGN_ CA_SODIMMA _BUF

VREFMRGN_ DQ_SODIMMB _EN

VREFMRGN_ CA_SODIMMA _EN

VREFMRGN_ FRAMEBUF_E N

VREFMRGN_ DQ_SODIMMB _EN

VREFMRGN_ CPUFSB_EN

=I2C_VR EFDACS_S DA

PCA9557D_ RESET_L

VREFMRGN_ DQ_SODIMMA _EN

=I2C_VR EFDACS_S CL

VREFMRGN_ CA_SODIMMB _EN

CPU_GTL REF

GPU_FB_B _VREF_DI V

GPU_FB_A _VREF_DI V

=I2C_PC A9557D_S DA

=I2C_PC A9557D_S CL

=PP3V3_S 3_VREFMR GN

VREFMRGN_ CPUFSB

VREFMRGN_ DQ_SODIMM

VREFMRGN_ DQ_SODIMMB _BUF

PP0V75_ S3_MEM_V REFCA_A

MIN_LINE_WI DTH=0.3 mm MIN_NECK_WI DTH=0.1 mm

MIN_LINE_WI DTH=0.3 mm MIN_NECK_WI DTH=0.2 mm

PP0V75_ S3_MEM_V REFDQ_B

MIN_LINE_WI DTH=0.3 mm

PP0V75_ S3_MEM_V REFCA_B

MIN_NECK_WI DTH=0.2 mm

U2901

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

C2903

1

2

C2902

1

2

R2902

1 2

R2901

1 2

R2904

1 2

R2906

1 2

R2910

1 2

R2907

1 2

C2904

1

2

R2912

1 2

R2908

1 2

U2900

9

10

3

6

7

8

1

2

4

5

C2901

1

2

C2900

1

2

C2905

1

2

R2916

1 2

R2914

1 2

R2913

1 2

R2903

1 2

R2915

1 2

R2917

1 2

U2902

C3

C2

C1

C4

B1

B4

U2903

A3

A2

A1

A4

B1

B4

U2902

A3

A2

A1

A4

B1

B4

U2903

C3

C2

C1

C4

B1

B4

U2904

A3

A2

A1

A4

B1

B4

U2904

C3

C2

C1

C4

B1

B4

R2905

1 2

R2909

1 2

R2911

1 2

64

8

28

27

8

28

29

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4*

DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS

DQ58

DQ59

DM7

VSS

DQ57

DQ56

DQ50

DQ51

VSS

DQS6*

DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS

DQ42

SDA

SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60

DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS

DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

CK0

A1

A3

VDD

A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS

DQ44

DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD

ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI

BIBI

BI

IN

BI

IN

BI

IN

BI

IN

BI

DQ16

DM3

DQ26

DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24

DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8

DQ9

DM0

DQ0

DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

OUT

BI

IN

BI

IN

BI

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

(NONE)

BOM options provided by this page:

- =PP1V5_S3 _MEM_A

- =I2C_SODI MMA_SCL

- =PP0V75_S 0_MEM_VTT_A

Power alias es required by this pag e:

- =I2C_SODI MMA_SDA

"Facto ry" (t op) sl ot

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

Signal alia ses required by this pa ge:

- =PPSPD_S0 _MEM_A (2.5 - 3.3V)

- =PP1V5_S0 _MEM_A

SPD ADDR= 0xA0(WR)/ 0xA1(RD)

Page Notes

516-0196

DDR3-SO DIMM-D UAL-M97 -3

F-RT-THB

15 88

0.1UF

CERM 402

20% 10V

6.3V CERM 402-LF

20%

2.2UF

15 88

29 30

15 88

DDR3-SO DIMM-D UAL-M97 -3

CRITIC AL

F-RT-THB

15 88

9

15 88

10V

20%

402

CERM

0.1UF

402-LF

20%

6.3V

2.2UF

CERM

15 88

21 29 42

45

15 88

10K

5%

402

1/16W MF-LF

10K

MF-LF

1/16W

5%

402

2.2UF

20%

CERM 402-LF

6.3V

10UF

20%

X5R

6.3V

603

6.3V

10UF

X5R 603

20%

CERM 402

10V

20%

0.1UF 0.1UF

402

CERM

10V

20%

CERM

0.1UF

20% 10V

402

CERM 402

0.1UF

10V

20%

10V

0.1UF

402

CERM

20%

0.1UF

20%

402

CERM

10V 10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

20%

402

CERM

0.1UF

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

SYNC_MASTER =DDR

SYNC_DATE=0 7/22/2008

DDR3 S O-DIMM Connec tor A

051-7546

A.0.0

9628

MEM_A_BA <2>

MEM_A_DQ <60>

MEM_A_DQ <58>

MEM_A_DQ <59>

MEM_A_SA <0>

=PP1V5 _S0_ME M_A

MEM_A_DQ <3>

MEM_A_DQ <2>

PP0V75_S 3_MEM_VR EFDQ_A

MEM_A_DQ <1>

MEM_A_DQ <0>

MEM_A_DM <0>

MEM_A_DQ <13>

MEM_A_DQ <9>

MEM_A_DQ S_N<1>

MEM_A_DQ S_P<1>

MEM_A_DQ <11>

MEM_A_DQ <14>

MEM_A_DQ <18>

MEM_A_DQ S_N<2>

MEM_A_DQ S_P<2>

MEM_A_DQ <23>

MEM_A_DQ <19>

MEM_A_DQ <30>

MEM_A_DQ <24>

MEM_A_DQ <5>

MEM_A_DQ S_N<0>

MEM_A_DQ S_P<0>

MEM_A_DQ <6>

MEM_A_DQ <7>

MEM_A_DQ <8>

MEM_A_DQ <12>

MEM_A_DM <1>

MEM_RESE T_L

MEM_A_DQ <15>

MEM_A_DQ <10>

MEM_A_DQ <21>

MEM_A_DQ <20>

MEM_A_DM <2>

MEM_A_DQ <17>

MEM_A_DQ <22>

MEM_A_DQ <29>

MEM_A_DQ <28>

MEM_A_DQ S_N<3>

MEM_A_DQ S_P<3>

MEM_A_DQ <26>

MEM_A_DQ <31>

MEM_A_DQ <4>

MEM_A_DM <3>

MEM_A_DQ <16>

=PPSPD_S 0_MEM_A

MEM_A_CK E<1>

MEM_A_A< 15>

MEM_A_A< 14>

MEM_A_A< 4>

MEM_A_A< 2>

MEM_A_CL K_P<1>

MEM_A_A< 0>

MEM_A_CL K_N<1>

MEM_A_RA S_L

MEM_A_OD T<0>

MEM_A_OD T<1>

PP0V75_S 3_MEM_VR EFCA_A

MEM_A_DQ <36>

MEM_A_DQ <37>

MEM_A_DM <4>

MEM_A_DQ <38>

MEM_A_DQ <39>

MEM_A_DQ <40>

MEM_A_DQ <47>

MEM_A_DQ S_N<5>

MEM_A_CK E<0>

MEM_A_A< 12>

MEM_A_A< 9>

MEM_A_A< 8>

MEM_A_A< 3>

MEM_A_A< 1>

MEM_A_CL K_P<0>

MEM_A_BA <0>

MEM_A_WE _L

MEM_A_CA S_L

MEM_A_A< 13>

MEM_A_CS _L<1>

MEM_A_DQ <33>

MEM_A_DQ <34>

MEM_A_DQ <44>

MEM_A_DQ <41>

MEM_A_DQ <46>

MEM_A_DQ S_P<5>

MEM_A_DQ <43>

MEM_A_DQ <48>

MEM_A_DQ <53>

MEM_A_DM <6>

MEM_A_DQ <50>

MEM_A_DQ <49>

MEM_A_DQ <56>

MEM_A_DQ <57>

MEM_A_DQ S_P<7>

MEM_A_DQ S_N<7>

MEM_A_DQ <63>

MEM_A_DQ <62>

MEM_EVEN T_L

=I2C_SOD IMMA_SCL

=I2C_SOD IMMA_SDA

MEM_A_DQ <45>

MEM_A_DM <5>

MEM_A_DQ <42>

MEM_A_DQ <52>

MEM_A_DQ <51>

MEM_A_DQ S_P<6>

MEM_A_DQ S_N<6>

MEM_A_DQ <54>

MEM_A_DQ <55>

MEM_A_DQ <61>

MEM_A_DM <7>

MEM_A_CL K_N<0>

MEM_A_DQ <35>

MEM_A_DQ S_P<4>

MEM_A_DQ S_N<4>

=PP0V75_ S0_MEM_V TT_A

MEM_A_SA <1>

MEM_A_A< 10>

MEM_A_DQ <32>

MEM_A_A< 5>

MEM_A_A< 11>

MEM_A_A< 7>

MEM_A_A< 6>

MEM_A_DQ <27>

MEM_A_DQ <25>

=PP1V5 _S3_ME M_A

MEM_A_CS _L<0>

MEM_A_BA <1>

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101

103

102

104

73 74

136

153

170

187

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

C3131

1

2

C3130

1

2

J3100

11

28

46

63

5

7

33

35

22

24

34

36

39

41

51

53

15

40

42

50

52

57

59

67

69

56

58

17

68

70

4

6

16

18

21

23

12

10

29

27

47

45

64

62

30

1 2

3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

C3136

1

2

C3135

1

2

R3141

1

2

R3140

1

2

C3140

1

2

C3100

1

2

C3101

1

2

C3110

1

2

C3111

1

2

C3112

1

2

C3113

1

2

C3114

1

2

C3115

1

2

C3116

1

2

C3117

1

2

C3118

1

2

C3119

1

2

C3120

1

2

C3121

1

2

C3122

1

2

C3123

1

2

8

27

8

27

8

www.laptop-schematics.com

IN

BI

OUT

BI

IN

BI

IN

BI

IN

BI

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42

DQ43

DQ48

DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15

A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36

DQ37

VSS

DM4

VSS

DQ38

DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD

NC

BA2

CK0

VDD

BA0

WE*

A13

S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54

DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS

DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MT G PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI

IN

BI

IN

BI

IN

BI

DQ2

DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1*

DQS1

DQ10

DQ11

DQ17

DQS2*

DQS2

DQ18

DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6

DQ7

DQ12

DQ13

DM1

RESET*

DQ14

DQ15

DQ20

DQ21

DM2

DQ22

DQ23

DQ28

DQ29

DQS3*

DQS3

DQ30

DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

- =I2C_SODI MMB_SCL

- =I2C_SODI MMB_SDA

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

Power alias es required by this pag e:

Signal alia ses required by this pa ge:

(NONE)

"Expan sion" (botto m) slo t

- =PP1V5_S0 _MEM_B

SPD ADDR= 0xA2(WR)/ 0xA3(RD)

516s0704

Page Notes

BOM options provided by this page:

- =PPSPD_S0 _MEM_B (2.5 - 3.3V)

- =PP0V75_S 0_MEM_VTT_B

- =PP1V5_S3 _MEM_B

15 88

21 28 42

45

10V

20%

402

CERM

0.1UF

15 88

CERM 402-LF

6.3V

20%

2.2UF

10K

1/16W MF-LF

5%

402

10K

5%

402

MF-LF

1/16W

2.2UF

6.3V

402-LF

CERM

20%

603

6.3V X5R

20%

10UF

20%

603

X5R

10UF

6.3V

0.1UF

20% 10V

402

CERM

20% 10V CERM 402

0.1UF

402

10V

20%

0.1UF

CERM

20% 10V

0.1UF

402

CERM

15 88

20%

CERM 402

0.1UF

10V 10V

CERM 402

20%

0.1UF

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

0.1UF

CERM 402

20% 10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

15 88

DDR3-SO DIMM

F-RT-BGA 3

15 88

28 30

15 88

CRITIC AL

DDR3-SO DIMM

F-RT-BGA 3

15 88

9

15 88

CERM

0.1UF

20%

402

10V

2.2UF

6.3V CERM

20%

402-LF

15 88

SYNC_MASTER =DDR

29 9 6

A.0.0

051-7546

SYNC_DATE=0 7/22/2008

DDR3 S O-DIMM Connec tor B

=PP1V5 _S0_ME M_B

MEM_B_DQ <9>

MEM_B_DQ <18>

MEM_B_DQ <22>

MEM_B_DQ <4>

MEM_B_DQ <23>

MEM_B_DQ <19>

MEM_B_DQ S_P<2>

MEM_B_DQ S_N<2>

MEM_B_DQ <16>

MEM_B_DQ <20>

MEM_B_DQ <11>

MEM_B_DQ <14>

MEM_B_DM <1>

MEM_B_DQ <12>

MEM_B_DQ <13>

MEM_B_DQ <27>

MEM_B_DQ <26>

MEM_RESE T_L

MEM_B_DM <3>

MEM_B_DQ <25>

MEM_B_DQ <29>

MEM_B_DQ <7>

MEM_B_DQ <6>

MEM_B_DQ S_P<0>

MEM_B_DQ S_N<0>

MEM_B_DQ <5>

MEM_B_DQ <21>

MEM_B_DQ <17>

MEM_B_DQ <10>

MEM_B_DQ <15>

MEM_B_DQ S_P<1>

MEM_B_DQ S_N<1>

MEM_B_DQ <8>

MEM_B_DQ <30>

MEM_B_DQ <31>

MEM_B_DQ S_P<3>

MEM_B_DQ S_N<3>

MEM_B_DQ <28>

MEM_B_DM <0>

MEM_B_DQ <0>

MEM_B_DQ <1>

PP0V75_S 3_MEM_VR EFDQ_B

MEM_B_DQ <3>

MEM_B_DQ <2>

=PPSPD_S 0_MEM_B

MEM_B_DQ <59>

MEM_B_DQ <63>

MEM_B_SA <0>

MEM_B_SA <1>

MEM_B_DQ <57>

MEM_B_DQ <56>

MEM_B_DM <7>

MEM_B_CA S_L

MEM_B_DQ S_P<4>

MEM_B_DQ <35>

MEM_B_CL K_N<0>

MEM_B_A< 10>

MEM_B_DQ <52>

MEM_B_DQ <51>

MEM_B_DQ S_N<6>

MEM_B_DQ S_P<6>

=I2C_SOD IMMB_SDA

=I2C_SOD IMMB_SCL

=PP0V75_ S0_MEM_V TT_B

MEM_EVEN T_L

MEM_B_DQ <58>

MEM_B_DQ S_N<7>

MEM_B_DQ S_P<7>

MEM_B_DQ <60>

MEM_B_DQ <61>

MEM_B_DQ <50>

MEM_B_DQ <53>

MEM_B_DM <6>

MEM_B_DQ <54>

MEM_B_DQ <48>

MEM_B_DQ <46>

MEM_B_DQ S_P<5>

MEM_B_DQ <47>

MEM_B_DQ <41>

MEM_B_DQ <34>

MEM_B_DQ <32>

MEM_B_DQ <37>

MEM_B_CS _L<1>

MEM_B_A< 13>

MEM_B_WE _L

MEM_B_BA <0>

MEM_B_CL K_P<0>

MEM_B_BA <2>

MEM_B_DQ S_N<5>

MEM_B_DQ <44>

MEM_B_DQ <45>

MEM_B_DQ <39>

MEM_B_DM <4>

MEM_B_DQ <36>

MEM_B_DQ <33>

PP0V75_S 3_MEM_VR EFCA_B

MEM_B_OD T<1>

MEM_B_CS _L<0>

MEM_B_OD T<0>

MEM_B_BA <1>

MEM_B_RA S_L

MEM_B_A< 0>

MEM_B_CL K_P<1>

MEM_B_A< 2>

MEM_B_A< 4>

MEM_B_A< 6>

MEM_B_A< 7>

MEM_B_A< 11>

MEM_B_A< 14>

MEM_B_A< 15>

MEM_B_CK E<1>

MEM_B_DM <5>

MEM_B_DQ S_N<4>

MEM_B_DQ <40>

MEM_B_DQ <55>

MEM_B_DQ <42>

MEM_B_DQ <43>

MEM_B_A< 12>

MEM_B_A< 9>

MEM_B_A< 8>

MEM_B_A< 5>

MEM_B_A< 3>

MEM_B_A< 1>

=PP1V5 _S3_ME M_B

MEM_B_CK E<0>

MEM_B_DQ <24>

MEM_B_DQ <38>

MEM_B_DQ <49>

MEM_B_DQ <62>

MEM_B_DM <2>

MEM_B_CL K_N<1>

J3200

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101

103

102

104

73 74

136

153

170

187

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

205 206

207 208

209 210

211 212

203 204

113

C3231

1

2

C3230

1

2

J3200

11

28

46

63

5

7

33

35

22

24

34

36

39

41

51

53

15

40

42

50

52

57

59

67

69

56

58

17

68

70

4

6

16

18

21

23

12

10

29

27

47

45

64

62

30

1 2

3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

C3236

1

2

C3235

1

2

R3241

1

2

R3240

1

2

C3240

1

2

C3200

1

2

C3201

1

2

C3210

1

2

C3211

1

2

C3212

1

2

C3213

1

2

C3214

1

2

C3215

1

2

C3216

1

2

C3217

1

2

C3218

1

2

C3219

1

2

C3220

1

2

C3221

1

2

C3222

1

2

C3223

1

2

8

27

8

27

8

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

before 1.5V starts to ris e to avoid glitch on MEM _RESET _L.

3.3V i nput m ust be stable befor e

MCP79 cannot contro l this signa l dire ctly si nce it must be hig h in s leep an d MCP MEM ra ils ar e not p owered in sl eep.

DDR3 RESET Support

1/16W

5%

MF-LF

1K

402

CERM

20%

0.1UF

MEMRES ET_HW

402

10V

5%

10K

MEMRES ET_HW

1/16W MF-LF

402

16

MEMRES ET_MCP

MF-LF

5% 1/16W

0

402

MMDT39 04-X-G

MEMRES ET_HW

SOT-363-L F

MF-LF

1/16W

20K

402

5%

MEMRES ET_HW

SOT-363-L F

MMDT39 04-X-G

28 29

5%

20K

MEMRES ET_HW

1/16W MF-LF

402

DDR3 Support

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

30 9 6

A.0.0

051-7546

MEM_RE SET

MCP_ME M_RESE T_L

=PP3V3 _S5_ME MRESET

MEM_RE SET_L

MEM_RE SET_RC _L

=PP1V5 _S3_ME MRESET

R3310

1

2

Q3305

5

3

4

R3305

1

2

Q3305

2

6

1

R3301

1

2

C3300

1

2

R3300

1

2

R3309

1

2

8

OUT

S

G

D

IN

BI

NC NC

IN

OUT

BI

OUT

Y

B

A

IN

NC

SYM_VER-1

D

S G

D

S G

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

BLUETOOTH

275 mA peak

CHANNE L

RDS(ON )

LOADIN G

MOSFET

P-TYPE

FDC606 P

0.8 A (EDP)

26 mOh m @4.5 V

5V S3 WLAN FET

750 m A nomi nal max

1000 m A peak

AIRPORT

518S06 10

206 m A nomi nal max

ALS CAMERA

USB_CAMERA_P

CONN_USB2_BT_N

USB_CAMERA_CONN_N

=PP3V3_S3_WLAN

I2C_ALS_SDA

PP5V_WLAN_F

WLAN_SMIT_RC

WLAN_SMIT_BUF

USB_BT_P

USB_BT_N

MINI_RESET_L

PCIE_CLK100M_MINI_P

PCIE_WAKE_L

I2C_ALS_SCL

VOLTAGE= 5V

MIN_NECK _WIDTH=0 .25 mm

MIN_LINE _WIDTH=0 .5 mm

=PP5V_S3_BTCAMERA

PCIE_CLK100M_MINI_N

PM_WLAN_EN_L

VOLTAGE= 5V

MIN_NECK _WIDTH=0 .5 mm

MIN_LINE _WIDTH=1 mm

=PP5V_S3_WLAN

P5VWLAN_SS

PP5V_WLAN_F

VOLTAGE= 5V

MIN_LINE _WIDTH=1 mm MIN_NECK _WIDTH=0 .5 mm

CONN_USB2_BT_P

USB_CAMERA_CONN_P

MINI_CLKREQ_L

PCIE_MINI_R2D_C_N

PCIE_MINI_R2D_C_P

PCIE_CLK100M_MINI_CONN_P

AP_PWR_EN

MINI_RESET_CONN_L

VOLTAGE= 5V

PP5V_WLAN

MIN_NECK _WIDTH=0 .5 mm

MIN_LINE _WIDTH=1 mm

USB_CAMERA_N

PCIE_CLK100M_MINI_CONN_N

PCIE_MINI_R2D_N

PCIE_MINI_R2D_P

PCIE_MINI_D2R_N

PCIE_MINI_D2R_P

PCIE_MINI_PRSNT_L

PP5V_S3_BTCAMERA_F

VOLTAGE= 5V

MIN_LINE _WIDTH=0 .5 mm MIN_NECK _WIDTH=0 .25 mm

MINI_CLKREQ_Q_L

Right Clutch Connector

31 9 6

A.0.0

051-7546

SYNC_MA STER=Y ITE_M98 _MLB

SYNC_DA TE=07/ 02/2008

PLACEME NT_NOTE= Place cl ose to J 3401.

10V

20%

CERM

402

0.1uF

402

5%

MF-LF

10K

1/16W

100K

MF-LF

402

5%

1/16W

0.033U F

16V X5R

10%

402

X5R

0.1UF

16V

10%

402

34 21

17

SSM6N1 5FEAPE

SOT563

SSM6N1 5FEAPE

SOT563

PLACEME NT_NOTE= Place cl ose to J 3401.

90-OHM DLP0NS

DLP0NS

90-OHM

PLACEME NT_NOTE= Place cl ose to J 3401.

90-OHM- 100MA

DLP11S

PLACEME NT_NOTE= Place cl ose to J 3401.

10%

6.3V

1UF

CERM

402

62K

1/16W

5%

MF-LF 402

5%

33K

1/16W MF-LF 402

20%

X5R

10UF

805

10V

PLACEME NT_NOTE= Place cl ose to Q 3450.

74LVC1G17DRL

SOT-553

26

TC7SZ0 8AFEAP E

SOT665

89 17

90 20

PLACEME NT_NOTE= Place cl ose to Q 3450.

CERM

0.1uF

402

10V

20%

90 20

89 17

10%

PLACEME NT_NOTE= Place cl ose to J 3401.

16V X5R

0.1uF

402

89 17

PLACEME NT_NOTE= Place cl ose to J 3401.

402X5R10%

0.1uF

16V

0.1uF

10V

20%

402

CERM

0402-L F

FERR-120-OHM-1.5A

45

34

FERR-120-OHM-1.5A

0402-L F

F-RT-S M

CRITIC AL

20347-325E-12

FDC606P_G

SOT-6

32 23 17

C3421

1

2

C3420

1

2

C3450

1 2

C3451

1

2

R3450

1 2

R3451

1

2

C3422

1

2

Q3450

1 2 5 6

3

4

J3401

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25

26 27 28 29

3

30

31

32

4 5 6 7 8 9

L3405

12

L3404

12

C3452

1

2

C3430

1 2

C3431

1 2

U3401

2

1

3

5

4

U3402

2

3 1

5

4

R3453

1

2

R3454

1

2

C3453

1

2

L3401

1 2

34

L3402

1 2

34

L3403

1 2

34

Q3401

6

2

1

Q3401

3

5

4

95

8

31

8

31

95

89

NC NC

NC

NC NC

OUT

IN

OUT

IN

OUT

NC

NC NC

NC

OUT

SYM_VER-1

BI

IN

OUT

NC

BI

AUXIN

VIN3P3

VIN1P5

VOUT3P3

AUXOUT

SHDN*

STBY*

SYSRST*

OC*

NC0

PERST*

CPPE*

CPUSB*

VOUT1P5

NC1

NC2

NC3

NC4

GND

RCLKEN

THRML_PA D

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

OUTPUT DECOUPLING

Venice Connector

INPUT DECOUPLING

EXPRESSCARD/34 FLEX CONNECTOR

10uF

6.3V

20%

603

X5R

17

42

26

20 43

0.1uF

X5R16V 4 0210%

VENICE

10% 1 6V

0.1uF

402X5R

PLACEM ENT_NO TE=Plac e clos e to J 3501.

VENICE

9

95

16V

10%

402

X5R

0.1uF

9

95

9

95

9

95

9

95

9

95

9

20%

603

X5R

6.3V

10uF

X5R

0.1uF

16V10%

DLP11S

90-OHM- 100MA

0.1uF

16V 4 02X5R10%

PLACEME NT_NOTE= Place cl ose to J 3500

20 90

17 89

7

17 89

0.1uF

10V

20%

402

CERM

7

17 89

17 23 31

45

M-ST-SM

503219 -0221

CRITIC AL

VENICE

74HC1G00 GWDG

SC70-5

1/16W

5%

402

MF-LF

0

CRITIC AL

TPS223 1

QFN

10uF

X5R 603

20%

6.3V

0.1uF

CERM 402

20% 10V

X5R

10uF

603

20%

6.3V

0.1uF

CERM 402

20% 10V

CERM

0.1uF

402

20% 10V

402

100K

MF-LF

1%

1/16W

0.1uF

CERM

402

20% 10V

0

MF-LF

4025%1/16W

10%

402

X5R

16V

0.1uF

SN74LVC1G 04YZPR

BGA

6.3V

20%

603

X5R

10uF

42 43

74HC1G00 GWDG

SC70-5

CRITIC AL

502250-8727

F-RT-SM

051-7546

96

SYNC_DA TE=07/ 02/2008

SYNC_MA STER=Y ITE_M98 _MLB

32

A.0.0

ExpressCard Connector

USB2_E XCARD_ CONN_N

=SMBUS _EXCAR D_SDA

PCIE_E XCARD_ D2R_P

EXCARD _CPUSB _L

PLT_RE SET_SW ITCH_L

PP3V3_ S0_EXC ARD_SWI TCH

EXCARD _CPPE_ L

PCIE_C LK100M _EXCARD _CONN_ P

PCIE_E XCARD_ D2R_N

PP1V5_ S0_EXC ARD_SWI TCH

PCIE_W AKE_L

=SMBUS _EXCAR D_SCL

PCIE_F C_R2D_ C_P PCIE_F C_R2D_ C_N

EXCARD _CPPE_ L

EXCARD _CPUSB _L

PCIE_C LK100M _EXCARD _CONN_ N

VOLTAGE= 3.3V

MIN_LINE_WIDT H=.3mm MIN_NECK_WIDT H=0.2mm

PP3V3_ S3_EXC ARD_SWI TCH

=PP3V3 _S3_EX CARD

EXCARD _CLKRE Q_CONN_ L

PP3V3_ S0_EXC ARD_SWI TCH

MIN_LINE_WIDT H=.6mm

VOLTAGE= 3.3V

MIN_NECK_WIDT H=0.2mm

=PP1V5 _S0_EX CARD

=PP3V3 _S0_EX CARD

EXCARD_ RCLKEN

=PP1V5 _S0_EX CARD

=PP3V3 _S3_EX CARD

TP_EXC ARD_ST BY_L

EXCARD _SHDN_ L_R

SMC_EX CARD_P WR_EN

EXCARD _RESET _L

EXCARD _OC_L

PLT_RE SET_SW ITCH_L

VOLTAGE= 1.5V

MIN_LINE_WIDT H=.6mm MIN_NECK_WIDT H=0.2mm

PP1V5_ S0_EXC ARD_SWI TCH

PCIE_C LK100M _EXCARD _N

PCIE_E XCARD_ R2D_C_N PCIE_E XCARD_ R2D_C_P

PCIE_E XCARD_ R2D_P

PCIE_C LK100M _EXCARD _CONN_ N

EXCARD _CLKRE Q_CONN_ L

PP3V3_ S3_EXC ARD_SWI TCH

PP3V3_ S0_EXC ARD_SWI TCH

PCIE_E XCARD_ R2D_N

USB2_E XCARD_ CONN_P

PP1V5_ S0_EXC ARD_SWI TCH

PCIE_E XCARD_ R2D_P

FC_RES ET_L

FC_PRS NT_L

=PP1V5 _FC_CO N

=PP3V3 _FC_CO N

PCIE_F C_D2R_ N

PCIE_F C_D2R_ P

PCIE_F C_R2D_ N

PCIE_F C_R2D_ P

PCIE_C LK100M _FC_N

PCIE_C LK100M _FC_P

FC_CLK REQ_L

EXCARD _CLKRE Q_CONN

=PP3V3 _S0_EX CARD

EXCARD _RCLKE N

=PP3V3 _S3_EX CARD

EXCARD _CPUSB _L

SMC_EX CARD_C P

EXCARD _CPPE_ L

PCIE_E XCARD_ PRSNT_L

PCIE_E XCARD_ R2D_N

PCIE_C LK100M _EXCARD _P

EXCARD _CPPE_ L

PCIE_C LK100M _EXCARD _CONN_ P

EXCARD _CLKRE Q_L

402

PLACEME NT_NOTE= Place cl ose to J 3500

USB_EX CARD_N USB2_E XCARD_ CONN_N

USB_EX CARD_P USB2_E XCARD_ CONN_P

DLP0NS

90-OHM

PLACEME NT_NOTE= Place cl ose to J 3500

U3500

17

15

10

9

7

4

5

13

14

16

19

8

18

20

1

6

21

12

2

11

3

C3501

1

2

C3504

1

2

C3505

1

2

C3502

1

2

C3503

1

2

C3500

1

2

C3535

1

2

C3534

1

2

C3531

1

2

C3530

1

2

C3550

1

2

R3561

1

2

C3560

1

2

R3500

1 2

U3561

B1

C1

A2

C2

U3560

3

2

1

4

5

J3500

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

4

5

6

7

8

9

C3573

1 2

C3572

1 2

L3502

1 2

34

C3571

1 2

L3503

1 2

34

C3570

1 2

J3501

23

24

25

26

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

3 4

5 6

7 8

9

U3551

3

2

1

4

5

R3501

1 2

95

89

95

89

95

89

95

32

7

8

7

8

32

8

7

8

95

8

32

8

7

17

7

IN

BI

IN

BI

OUT

IN

TXD[2]

TXCTL

AVDD33

FB12

DVDD12

AVDD12

RXC

MDIO

GND

TXD[3]

RXD[0]

MDI+[0]

CKXTAL1

CKXTAL2

CLK125

RSET

PHYRSTB*

MDC

RXCTL

MDI-[2]

MDI+[2]

MDI+[3]

MDI+[1]

MDI-[1]

ENSWREG

TXD[1]

TXD[0]

RXD[3]/A N1

RXD[1]/T XDLY

TXC

MDI-[3]

LED1/PHY AD1

LED2/RXD LY

LED0/PHY AD0

RXD[2]/A N0

MDI-[0]

REGOUT

VDDREG

DVDD33

REFERENC E

RGMII/MI I

MEDIA DE PENDENT

MANAGEME NT

CLOCK

RESET

LED

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

PLACE R3796 CLOSE T O U140 0, PIN D24

Alias to GND for ex ternal 1.05V suppl y.

Alias to =PP 3V3_ENE T_PHY for in ternal switch er.

WF: Ma rvell numbers , upda te for Realt ek

If int ernal switche r is u sed, m ust pl ace ind uctor within 5mm of U37 00, an d 1x 22 uF & 1 x 0.1u F caps within 5mm o f indu ctor.

NOTE: VDDREG rise t ime mu st be >1ms t o avoid damag e to s witche r.

1x 0.1 uF cap s withi n 5mm of U37 00 pin s 44 & 45.

If int ernal switche r is u sed, m ust pl ace 1x 22uF &

PHYAD = 01 (PHY A ddress 00001 )

WF: Ma rvell numbers , upda te for Realt ek

(221mA typ - 1000ba se-T) ( 7mA typ - Energy Detec t)

(19mA typ - Energy Detect )

(43mA typ - 1000bas e-T)

If int ernal switche r is n ot use d, VDD REG and REGOU T can float.

Configuration Settings:

Hence, RC (R 3725 an d C372 5) are made NOSTUFF .

ENET_R ESET_L is not asser ted wh en WOL is act ive.

per Re alTek request .

Reserv ed for EMI

TXDLY = 0 (No TX CLK De lay)

AN[1:0 ] = 11 (Full auto-n egotia tion) RXDLY = 0 (RXCLK trans itions with data)

0

402

1/16W

5%

MF-LF

NO STU FF

10V CERM 402

20%

0.1UF

2.49K

MF-LF

1%

1/16W

402

NO STU FF

5%

4.7K

402

MF-LF

1/16W

10K

MF-LF

402

5%

1/16W

CRITIC AL

FERR-1 20-OHM -1.5A

0402-LF

0.1UF

16V X5R 402

10%

0.1UF

16V X5R 402

10%

0.1UF

16V X5R 402

10%

16V

0.1UF

X5R 402

10%

0.1UF

16V X5R 402

10%

18 91

34 91

35 91

MF-LF

5%

1/16W

22

402

MF-LF1/16W

5%

22

402

MF-LF1/16W

5%

22

402

22

MF-LF1/16W

5%

402

22

MF-LF1/16W

5%

402

22

MF-LF1/16W

5%

18 91

402

4.7K

MF-LF

5%

1/16W

402

4.7K

MF-LF

5%

1/16W

9

402

MF-LF

5%

4.7K

1/16W

402

4.7K

MF-LF

5% 1/16W

1/16W

5%

4.7K

MF-LF

402

MF-LF

4.7K

5% 1/16W

402

0.1UF

16V X5R 402

10%

16V

0.1UF

X5R 402

10%

FERR-1 20-OHM -1.5A

0402-LF

CRITIC AL

0.1UF

16V X5R

10%

402

0.1UF

16V X5R 402

10%

402

X5R

0.1UF

16V

402

5%

CERM

50V

10PF

22

MF-LF

402

1/16W

5%

18 91

OMIT

RTL821 1CLGR

TQFP

SYNC_DA TE=07/ 01/2008

Ethernet PHY (RTL8211CL)

SYNC_MA STER=S UMA_M98 _MLB

A.0.0

33 9 6

051-7546

ENET_C LK125M _TXCLK_ R

ENET_C LK125M _TXCLK

ENET_T X_CTRL

=PP3V3 _ENET_ PHY

ENET_T XD<2>

VOLTAGE= 3.3V

MIN_NECK _WIDTH=0 .2 MM

PP3V3_ ENET_P HYAVDD

MIN_LINE _WIDTH=0 .6 MM

VOLTAGE= 1.05V

PP1V05 _ENET_ PHYAVDD

MIN_LINE _WIDTH=0 .6 MM MIN_NECK _WIDTH=0 .2 MM

=PP1V0 5_ENET _PHY

ENET_C LK125M _RXCLK_ R

ENET_M DIO

ENET_T XD<3>

ENET_R XD_R<0 >

ENET_M DI_P<0 >

RTL821 1_CLK2 5M_CKXT AL1

TP_RTL 8211_C LK125

ENET_M DC

ENET_R XCTL_R

ENET_M DI_N<2 >

ENET_M DI_P<2 >

ENET_M DI_P<3 >

ENET_M DI_P<1 > ENET_M DI_N<1 >

ENET_T XD<1>

ENET_T XD<0>

ENET_R XD_R<3 >

ENET_R XD_R<1 >

ENET_M DI_N<3 >

RTL821 1_PHYA D1 RTL821 1_RXDL Y

RTL821 1_PHYA D0

ENET_R XD_R<2 >

ENET_M DI_N<0 >

=RTL82 11_REG OUT

=PP3V3 _ENET_ PHY_VDD REG

ENET_R X_CTRL

ENET_R XD<3>

ENET_R XD<2>

ENET_R XD<1>

ENET_R XD<0>

ENET_C LK125M _RXCLK

ENET_R ESET_L

=RTL82 11_ENS WREG

TP_RTL 8211_C KXTAL2

RTL821 1_RSET

RTL821 1_PHYR ST_L

R3724

1 2

C3725

1

2

R3730

1

2

R3725

1

2

R3720

1

2

L3705

1

2

C3705

1

2

C3706

1

2

C3700

1

2

C3701

1

2

C3702

1

2

R3790

1 2

R3791

1 2

R3792

1 2

R3793

1 2

R3794

1 2

R3795

1 2

R3755

1

2

R3756

1

2

R3752

1

2

R3757

1

2

R3750

1

2

R3751

1

2

C3715

1

2

C3716

1

2

L3715

1

2

C3711

1

2

C3710

1

2

C3714

1

2

C3790

1

2

R3796

1 2

U3700

10

40

6

41

42

43

32

28

36

152137

39

3

7

203347

34

35

38

30

2

1

5

4

9

8

12

11

31

29

48

46

19

13

14

16

17

18

22

27

23

24

25

26

44

45

8

91

9

G

DS

IN

OUT

D

SG

IN

D

S G

IN

D

SG

D

SG

D

S

G

D

SG

IN

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

ARB fo r alte rnate p ower o ptions .

=P3V3E NET_EN . Nets separ ated o n

Recomm end al iasing PM_SLP _RMGT_ L and

1.05V ENET FET

WLAN Enable Generation

Recomm end al iasing PM_SLP _RMGT_ L and

"WLAN" = ("S 3" && " AP_PWR _EN" & & ("AC " || "S 0"))

NOTE: S3 ter m is gu arante ed by S3 pul l-up on open- drain AP_PWR _EN si gnal.

RTL8211 25MHz Clock

ARB fo r alte rnate p ower o ptions .

=P1V05 ENET_E N. Net s sepa rated on

I(max) = 1. 7A (85C )

3.3V ENET FET

Rds(on ) = 90 mOhm ma x

MOBILE :

@ 2.5V Vgs:

NOTE: MCP79 can pro vide 2 5MHz c lock, but clo ck run s when ever R MGT ra ils are power ed. Design s must ensure PHY i s powe red whe never RMGT r ails a re, or use se parate cryst al.

1.8V V gs

Non-AR B:

Pull-u p is w ith pow er FET .

SOT-23-HF

CRITIC AL

NTR410 1P

10%

CERM

16V

402

0.01UF

0.033U F

10%

402

X5R

16V

5%

MF-LF

1/16W

100K

402

18 91

402

22

MF-LF

5%

1/16W

PLACEMEN T_NOTE=P lace clo se to U1 400

33 91

0.01UF

16V

10%

CERM 402

402

0.1UF

20%

CERM

10V

31

SOT563

SSM6N1 5FEAPE

21 37 42 43

SSM6N1 5FEAPE

SOT563

21 31

7

21 37 42 44 68 81 83

SSM6N1 5FEAPE

SOT563

SSM6N1 5FEAPE

SOT563

69.8K

1%

1/16W

402

MF-LF

SI2312 BDS

SOT23

CRITIC AL

MF-LF

402

1/16W

10K

5%

SSM6N1 5FEAPE

SOT563

9

SSM6N1 5FEAPE

SOT563

9

402

MF-LF

1/16W

1%

10K

402

MF-LF

5%

1/16W

100K

Ethernet & AirPort Support

051-7546

A.0.0

9634

SYNC_MA STER=S UMA_M98 _MLB

SYNC_DA TE=07/ 01/2008

=P3V3E NET_EN

PM_SLP _S3_L

SMC_AD APTER_ EN

AC_OR_ S0_L

AP_PWR _EN

=PP1V0 5_ENET _FET

=PP3V3 _S5_P1 V05ENET FET

P1V05E NET_SS

P1V05E NET_EN _L

=PP3V3 _S5_P3 V3ENETF ET

=PP3V3 _ENET_ FET

P3V3EN ET_SS

RTL821 1_CLK2 5M_CKXT AL1

MCP_CL K25M_B UF0_R

P3V3EN ET_EN_ L

=PP1V0 5_ENET _P1V05E NETFET

=P1V05 ENET_E N

PM_WLA N_EN_L

P1V05E NET_EN _L_RC

Q3810

3

1

2

C3810

12

C3811

1

2

R3810

1 2

R3895

1 2

C3841

1

2

C3840

1

2

Q3805

3

5

4

Q3801

6

2

1

Q3805

6

2

1

Q3841

6

2

1

R3842

1

2

Q3840

3

1

2

R3800

1

2

Q3801

3

5

4

Q3841

3

5

4

R3841

1 2

R3840

1 2

8

8 8

8

BI

RX

TX

BI

RX

TX

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Place on e of 0.1 uf cap c lose to each cen tertap p in of tr ansformer

Transformers should be

sides of the board

mirrored on opposite

Page Notes

Power aliase s requi red by this page:

BOM op tions provide d by t his pa ge: (NONE)

(NONE)

Signal alias es requ ired b y this page:

514-0596

33 91

TLA-6T213HF

SM

CRITICA L

75

402

5%

MF-LF

1/16W

75

402

1/16W MF-LF

5%

1/16W

5%

402

MF-LF

75 75

402

MF-LF

1/16W

5%

1000PF

CRITIC AL

1206

CERM

10% 2KV

33 91

16V

0.1UF

X5R 402

10%

0.1UF

402

X5R

16V

10%10%

0.1UF

16V X5R 402

TLA-6T213HF

SM

CRITICA L

0.1UF

16V X5R

10%

402

RJ45-M 97-2

CRITICAL

F-RT-TH

33 91

A.0.0

35

051-7546

96

Ethernet Connector

SYNC_MA STER=S UMA_M98 _MLB

SYNC_DA TE=07/ 01/2008

ENETCO NN_CTA P

ENET_M DI_N<0 >

ENET_M DI_P<1 >

ENET_M DI_N<2 >

ENETCO NN_N<1 >

ENETCO NN_P<2 >

ENETCO NN_N<3 >

ENETCO NN_P<3 >

MIN_NECK _WIDTH=0 .25 mm

MIN_LINE _WIDTH=0 .6 mm

ENET_B OB_SMI TH_CAP

ENETCO NN_N<2 >

ENET_C TAP2

ENET_C TAP1

ENET_C TAP0

ENETCO NN_P<0 >

ENET_M DI_P<3 >

ENET_M DI_N<3 >

ENET_C TAP3

ENET_M DI_P<2 >

ENET_M DI_N<1 >

ENET_M DI_P<0 >

ENETCO NN_N<0 >

ENETCO NN_P<1 >

T3901

1

10

11

12

2

3

4

5

6 7

8

9

T3900

1

10

11

12

2

3

4

5

6 7

8

9

R3900

1

2

R3901

1

2

R3902

1

2

R3903

1

2

C3908

1 2

C3906

1

2

C3904

1

2

C3902

1

2

C3900

1

2

J3900

1

10

11

12

2

3

4

5

6

7

8

9

95

DS2

ATBUSH

ATBUSN

VP25

OCR_CTL_ V10

VAUX_DET ECT

TMS

TCK

REFCLKN

PCIE_TXD 0P

TRST*

ATBUSB

TDI

DS1

TPA0N

TPA0P

AVREG

CE

CLKREQN

FW_RESET *

FW620*

JASI_EN

MODE_A

NAND_TRE E

OCR_CTL_ V12

PCIE_RXD 0N

PCIE_RXD 0P

PCIE_TXD 0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK

SCIFDAIN

SCIFDOUT

SCIFMC

SCL

SDA

SE

SM

TDO

TPA1N

TPA2N

TPA2P

TPB0N

TPB0P

TPB1N

TPB1P

TPB2N

TPB2P

TPBIAS0

TPBIAS1

TPBIAS2

TPCPS

VAUX_DIS ABLE

VBUF

VDDH

VP

VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33

VDD10

VREG_VSS

VSS

SERIAL E EPROM

MISCELLA NEOUS

CONTROLL ER

POWER MA NAGEMENT

TEST CON TROLLER

PCI EXPR ESS PHY

CHIP RES ET

SCIF

1394 PHY

NC NC NC

NC

IN

OUT

IN

BI

IN

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

NAND t ree ord er.

NOTE: NT-xx notes s how

NT-10 (IPD)

(IPD) NT-18

NT-12 (IPD)

NT-13

FIXME!!! - TYPO IN SYMBO L REGCTL

(IPU)

(IPD) NT-21

(IPU)

(IPD) NT-20

(IPD) NT-19

(IPD)

NT-9

(Reser ved)

NT-OUT

NT-14 (IPD)

NT-5

NT-17

NT-6

NT-7

NT-16 (IPD)

NT-2 ( IPU)

(OD)

NT-4 ( IPU) NT-3 ( IPU)

NT-1 ( IPU)

135 mA

110 mA Digit al Core

25 mA PCIe S erDes 17 mA PCIe SerDe s

0 mA V Reg PW R

114 mA FireW ire PHY

7 mA I /O

138 mA

(IPD)

(IPU) NT-8

(IPD) NT-11

NT-15 (IPD)

191

1% 1/16W MF-LF 402

CERM-X5R

0.33UF

6.3V

402

10%

1/16W

5%

MF-LF

470K

402

BGA

FW643

OMIT

CRITIC AL

CERM

22PF

5%

50V

402

50V

5%

22PF

CERM

402

390K

MF-LF

5%

1/16W

402

412

MF-LF

1%

1/16W

402

10K

MF-LF

5% 1/16W

402

10K

MF-LF

5% 1/16W

402

FW643_ LDO

1/16W

5%

MF-LF

10K

402

0.1UF

PLACEMEN T_NOTE=P lace C41 76 close to U400 0

16V

X5R 402

10%

0.1UF

PLACEMEN T_NOTE=P lace C41 75 close to U400 0

16V

X5R 402

10%

10K

MF-LF

5% 1/16W

402

0.1UF

PLACEMEN T_NOTE=P lace C41 71 close to U140 0

16V

X5R 402

10%

0.1UF

PLACEMEN T_NOTE=P lace C41 70 close to U140 0

16V

X5R 402

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

20%

CERM

0.1UF

402

10V

CERM

6.3V

402

1UF

10%

CERM

6.3V

402

1UF

10%

89 17

19

17

2.94K

MF-LF

1%

1/16W

402

38

92 38

38

92 38

38

0402-LF

120-OH M-0.3A -EMI

0402-LF

26

0402-LF

120-OH M-0.3A -EMI

24.576 MHZ

SM-3.2X2. 5MM

CRITIC AL

SYNC_DA TE=08/ 14/2008

051-7546

A.0.0

9636

SYNC_MA STER=S ENSOR

FireWire LLC/PHY (FW643)

TP_FW6 43_NAN D_TREE

TP_FW6 43_SE

FW643_ PU_RST _L

PP1V0_ FW_FWP HY_AVDD

MIN_LINE _WIDTH=0 .4 MM

VOLTAGE= 1.0V

MIN_NECK _WIDTH=0 .2 MM

PP3V3_ FW_FWP HY_VDDA

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .4 MM

VOLTAGE= 3.3V

PCIE_F W_D2R_ C_P

PCIE_F W_D2R_ P

PCIE_F W_D2R_ C_N

PCIE_F W_D2R_ N

PCIE_F W_R2D_ P

PCIE_F W_R2D_ C_P

PCIE_F W_R2D_ N

PCIE_F W_R2D_ C_N

FW_P0_ TPA_N FW_P0_ TPA_P

PP3V3_ FW_FWP HY_VP25

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .4 MM

VOLTAGE= 3.3V

FW_P0_ TPB_P

FW_P1_ TPBIAS

TP_FW6 43_VAU X_ENABL E

=FW_PH Y_DS1

=PP3V3 _FW_FW PHY

=FW_PH Y_DS0

=FW_PH Y_DS2

FW643_ REXT

FW643_ R0

FW_CLK 24P576 M_XO_R

FW_P2_ TPBIAS

FW_P0_ TPBIAS

FW_P2_ TPB_P

FW_P2_ TPB_N

FW_P1_ TPB_P

FW_P1_ TPB_N

FW_P0_ TPB_N

FW_P2_ TPA_P

FW_P2_ TPA_N

FW_P1_ TPA_N FW_P1_ TPA_P

FW_PME _L

TP_FW6 43_VBU F

TP_FW6 43_TDO

TP_FW6 43_SM

TP_FW6 43_SDA

TP_FW6 43_SCI FDOUT

TP_FW6 43_SCI FDAIN

TP_FW6 43_SCI FCLK

PCIE_C LK100M _FW_P

FW_RES ET_L

TP_FW6 43_MOD E_A

TP_FW6 43_JAS I_EN

TP_FW6 43_FW6 20_L

FW_CLK REQ_L

TP_FW6 43_CE

TP_FW6 43_AVR EG

TP_FW6 43_TDI

PCIE_C LK100M _FW_N

TP_FW6 43_TCK

TP_FW6 43_TMS

TP_FW6 43_OCR 10_CTL

FW643_ SCL

FW643_ TRST_L

FW643_ REGCTL FW643_ VAUX_D ETECT

FW643_ TPCPS

=PPVP_ FW_PHY _CPS

FW_CLK 24P576 M_XI

FW_CLK 24P576 M_XO

=PP3V3 _FW_FW PHY

=PP1V0 _FW_FW PHY

TP_FW6 43_SCI FMC

R4170

1

2

C4162

1

2

R4162

1

2

U4100

B13

A13

A11

A10

L13

L2

F12

E12

E13

D12

K13

D1

J2

K1

J12

J13

N8

N7

N5

N6

N4

B11

N9

N10

D13

L8

G2

G1

H1

F2

N12

M11

M13

N13

M4

N2

M1

M3

B8

A8

B5

A5

B3

A3

B9

A9

B6

A6

B4

A4

B7

C3

A2

B10

N1

E1

D2

H13

A1

B1

M12N3N11

B12

C13E2E10H2H12K2L1

C1

C12F1G12J1L3

L11M2A12D5D6D8L5

L10L6L9

K12

L12

B2

D4

F7

F8

F10

G4G6G7

G8

G10

H4

H6D7H7

H8

H10

J4J5J9

J10

K4K5K7D9K8K9L7

K6

K10

D10

E4E5E9F4F6

C2

G13

F13

C4151

1 2

C4150

1 2

R4160

1

2

R4150

1 2

R4163

1

2

R4164

1

2

R4165

1

2

C4176

1 2

C4175

1 2

R4166

1

2

C4171

1 2

C4170

1 2

C4130

1

2

C4131

1

2

C4100

1

2

C4101

1

2

C4132

1

2

C4102

1

2

C4103

1

2

C4135

1

2

C4136

1

2

C4104

1

2

C4110

1

2

C4105

1

2

C4106

1

2

C4120

1

2

C4121

1

2

C4122

1

2

C4123

1

2

C4124

1

2

C4141

1

2

C4111

1

2

C4140

1

2

R4161

1

2

L4130

1 2

L4135

1 2

L4110

1 2

Y4150

2 4

1 3

38

36

89

8

38

8

V-

V+

D

SG

IN

D

SG

D

G S

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

Page Notes

Power aliase s requi red by this page:

- =PPB US_S5_ FWPWRSW (syst em sup ply fo r bus p ower)

- =PPV P_FW_S UMNODE (power passt hru su mmation node)

Signal alias es requ ired b y this page:

Late-VG Event Detection

- =PP3 V3_FW_ LATEVG_ ACTIVE

BOM op tions provide d by t his pa ge:

FWLATE VG_3V_ REF Hys teresi s:

2.95V when p ort pow er is on

(NONE)

- FW_P ORT_FA ULT_PU

2.81V on lat e Vg ev ent an d port power is off

FireWire Port Power Switch

Enable s port power when m achine is run ning o r on AC .

5%

402

2.0M

1/16W MF-LF

10V

10%

CERM-X5R

0.33UF

603

402

0.1UF

CERM

10V

20%

200K

1%

MF-LF

402

1/16W

SM-HF

LMC7211

1/16W

5%

402

10K

MF-LF

402

CERM

5%

50V

100pF

10K

MF-LF

1/16W

1%

402

80.6K

MF-LF 402

1% 1/16W

MBR054 0XXH

SOD-123

SOI-HF

NDS940 7

CRITIC AL

16V

20%

402

CERM

0.01uF

402

470K

1/16W

5%

MF-LF

SSM6N1 5FEAPE

SOT563

MF-LF 402

330K

5% 1/16W

43 42 34 21

83 81 68 44 42 34 21

7

PDS540 XF

PWRDI5

CRITIC AL

SSM6N1 5FEAPE

SOT563

SSM3K1 5FV

SOD-VESM -HF

A.0.0

051-7546

37 9 6

FireWire Port Power

SYNC_MA STER=S ENSOR

SYNC_DA TE=08/ 14/2008

1

CRITIC AL

F4260

LITTLEFUSE, 1.5A RESETT ABLE 24V

740S00 80

FW_POR TPWR_E N_FET

FWPWR_ EN_L

=PP3V3 _FW_LA TEVG_AC TIVE

P2V4_F WLATEV G_RC

LATEVG _EVENT _L

FWLATE GV_3V_ REF

MIN_NECK _WIDTH=0 .25 mm

PPBUS_ FW_FWP WRSW_D

MIN_LINE _WIDTH=0 .5 mm

VOLTAGE= 12.6V

PP2V4_ FW_LAT EVG

=PPBUS _S5_FW PWRSW

MIN_LINE _WIDTH=0 .5 mm MIN_NECK _WIDTH=0 .25 mm VOLTAGE= 12.6V

SMC_AD APTER_ EN

FW_POR TPWR_E N

FWPWR_ EN_L_D IV

FW_POR TPWR_E N

=PPBUS _S5_FW _FET

PM_SLP _S3_L

1.5A-2 4V

CRITIC AL

OMIT

1812L150 24HF

PPBUS_ FW_FWP WRSW_F

R4219

1

2

C4219

1

2

C4210

1

2

R4210

1 2

U4210

4

3

1

5

2

R4211

1

2

C4211

1

2

R4212

1

2

R4213

1

2

D4219

12

Q4260

5

6

7

8

4

1

2

3

C4260

1

2

R4260

1

2

Q4261

3

5

4

R4261

1

2

F4260

1 2

D4260

1

2

3

Q4261

6

2

1

Q4262

3

1

2

8

38

8

37

8

GND

CHASSIS

SHLD

CABLE OUTE R

TPA+

TPA(R)

TPA-

VG

NC

VPTPB+

TPB(R)

TPB-

SGD

(SYM-VER2)

G

S

(SYM-VER1)

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

constr ained o n this page. It i s

provid e the a ppropr iate c onstra ints

Config ures P HY for:

"Snapback" & "Late VG" Protection

NOTE: This p age is expect ed to contai n

FireWire PHY Config Straps

- 1-po rt Por table P ower C lass ( 0)

- Port "1" B ilingua l (139 4B)

Power aliase s requi red by this page:

Page Notes

for sn ap-bac k diode s

Late-VG Protection Power

PP2V4_ FWLATE VG need s to b e bias ed to at least 2.1V fo r FW s ignal integr ity and sh ould b e biase d to 2 .4V fo r marg in R4390 should be 390 Ohms max fo r a 3. 3V rail

assume d that FireWi re PHY page will

to app ly to e ntire TPA/TP B XNet s.

Termination

FW spe c call s out 0 .33uF

Place close to FireWire PHY

TI PHY s requ ire 1uF even though

- =PPV P_FW_P ORT1

- =PP3 V3_FW_ LATEVG

514S0605

When a bilin gual de vice i s conn ected to a beta-o nly de vice, t here i s no D C path betwee n them (to av oid gr ound o ffset issue)

BREF s hould be hard -conne cted t o logi c ground for s peed si gnalin g and connec tion

approp riate c onnect ors an d/or t o

NOTE: FireWi re TPA/ TPB pa irs ar e NOT

Cable Power

(GND_F W_PORT 1_VG)

(FW_PO RT1_BR EF)

AREF n eeds t o be is olated from all

INPUT

NC

VP

TPB+

TPB<R>

TPB-

TPA-

TPA<R>

VG

NC

TPA+

ESD an d late -VG rai l

local ground s per 1 394b s pec

(Commo n to a ll port s)

(NONE)

OUTPUT

BILINGUAL

- =GND _CHASS IS_FW_E MI_R

(NONE)

FireWi re Des ign Gui de (FW DG 0.6 , 5/14 /03)

1394b implem entatio n base d on A pple

the ne cessary alias es to map th e FireWi re TPA/ TPB pa irs to their

- =GND _CHASS IS_FW_P ORT1

PORT 1

Note: Trace PPVP_FW _PORT1 must handle up to 5A

Signal alias es requ ired b y this page:

BOM op tions provide d by t his pa ge:

proper ly term inate unused signa ls.

SIGNAL_ MODEL=EM PTY

56.2

MF-LF

402

1%

1/16W

MF-LF

402

1/16W

1%

4.99K

SIGNAL_ MODEL=EM PTY

1% 1/16W MF-LF 402

56.2

220pF

CERM 402

5% 25V

1%

56.2

MF-LF

1/16W

402

SIGNAL_ MODEL=EM PTY

0.33UF

CERM-X5R

6.3V

10%

402

1/16W

1%

MF-LF 402

56.2

SIGNAL_ MODEL=EM PTY

50V

10%

603-1

X7R

0.1uF

PLACEMEN T_NOTE=P lace C43 19 close to conn ector pi n 5.

MF-LF 402

5% 1/16W

1M

0.01UF

50V X7R

10%

402

FERR-2 50-OHM

SM

CRITIC AL

0.01uF

50V

10%

402

X7R

SOT-363

BAV99D W-X-G

10% 50V

0.01uF

402

X7R

BAV99D W-X-G

SOT-363

BAV99D W-X-G

SOT-363

0.01uF

50V

10%

402

X7R

0.01uF

50V

10%

X7R 402

1/16W

1%

402

MF-LF

332

CRITIC AL

SOT23

MMBZ52 27BLT1 H

1394B- M97

CRITIC AL

F-RT-TH1

MF-LF

402

1%

1/16W

10K

402

1/16W

1%

MF-LF

10K

402

10K

1/16W MF-LF

1%

BSS840 2DW

SOT-363

BSS840 2DW

SOT-363

330K

1/16W MF-LF

402

5%

470K

1/16W

5%

402

MF-LF

SYNC_DA TE=08/ 14/2008

SYNC_MA STER=S ENSOR

FireWire Ports

051-7546

A.0.0

38 9 6

CPS_EN _L_DIV

CPS_EN _L

=PP3V3 _FW_FW PHY

PPVP_F W_CPS

MIN_NECK _WIDTH=0 .2 mm

VOLTAGE= 12.6V

MIN_LINE _WIDTH=0 .4 mm

MAKE_BAS E=TRUE

=PPVP_ FW_PHY _CPS_FE T

=PPVP_ FW_PHY _CPS

FW_P1_ TPA_N

PP2V4_ FW_LAT EVG

FW_POR T1_TPB _P

FW_POR T1_TPA _N

FW_POR T1_TPA _P

NC_FW2 _TPBP

MAKE_BAS E=TRUE

FW_P2_ TPB_P

NC_FW2 _TPBN

MAKE_BAS E=TRUE

FW_P0_ TPA_P FW_P2_ TPA_N

FW_POR T1_TPB _N

FW_POR T1_ARE F

MAKE_BAS E=TRUE

NC_FW0 _TPBP

=PP3V3 _FW_FW PHY

=FW_PH Y_DS0

=FW_PH Y_DS1

=FW_PH Y_DS2

MAKE_BAS E=TRUE

FWPHY_ DS0

FWPHY_ DS2

MAKE_BAS E=TRUE

FWPHY_ DS1

FW_P1_ TPA_P

=PPVP_ FW_POR T1

=PP3V3 _FW_LA TEVG

FW_P1_ TPB_N

FW_POR T1_TPB _C

PP2V4_ FW_LAT EVG

MIN_NECK _WIDTH=0 .25 mm VOLTAGE= 2.4V

MIN_LINE _WIDTH=0 .38 mm

MAKE_BAS E=TRUE

FW_POR T1_TPB _N

MAKE_BAS E=TRUE

FW_POR T1_TPA _P

FW_POR T1_TPA _N

MAKE_BAS E=TRUE

FW_P0_ TPB_P

FW_P1_ TPB_P

PPVP_F W_PORT 1_F

MIN_NECK _WIDTH=0 .25 mm VOLTAGE= 33V

MIN_LINE _WIDTH=0 .5 mm

FW_P2_ TPB_N

FW_P0_ TPB_N

MAKE_BAS E=TRUE

NC_FW2 _TPBIA S

MAKE_BAS E=TRUE

NC_FW0 _TPBIA S

NC_FW0 _TPAP

MAKE_BAS E=TRUE

NC_FW2 _TPAN

FW_P2_ TPA_P

FW_P0_ TPA_N

FW_P2_ TPBIAS

FW_P0_ TPBIAS

MAKE_BAS E=TRUE

NC_FW0 _TPAN

MAKE_BAS E=TRUE

NC_FW2 _TPAP

MAKE_BAS E=TRUE

NC_FW0 _TPBN

FW_POR T1_TPB _P

MAKE_BAS E=TRUE

FW_P1_ TPBIAS

R4363

1

2

R4364

1

2

R4362

1

2

C4364

1

2

R4361

1

2

C4360

1

2

R4360

1

2

C4319

1

2

R4319

1

2

C4314

1

2

L4310

1 2

C4310

1

2

DP4310

1

2

6

C4311

1

2

DP4310

4

5

3

DP4311

1

2

6

DP4311

4

5

3

C4313

1

2

C4312

1

2

R4390

1 2

D4390

1

3

J4310

1

10

11

12

13

14

15

2

3

4

5

6

7

8

9

R4381

1

2

R4382

1

2

R4380

1

2

Q4300

3

5

4

Q4300

6

2

1

R4312

1

2

R4311

1

2

38

36

92

38

92

36

92

38

92

8

36

37

38

36

38

8

36

8

36

37

38

36

38

36

OUT

IN

SYM_VER-1

OUT

IN

D

SG

D

SG

SGD

NC

SYM_VER-1

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

ODD Power Control

NOTE: 3.3V m ust be S0 if 5V is S3 or S5 to

SATA HDD Port

SATA ODD Port

518S0654

Indicat es disc presence

516S0617

ensure the dr ive is unpow ered i n S3/S5 .

7

42

33K

MF-LF

1/16W

5%

402

55560-0 168

M-ST-SM-L F

CRITICA L

21

CRITICAL

90-OHM-10 0MA

DLP11S

PLACEME NT_NOTE= Place FL 4520 clo se to J 4500

CRITICAL

DLP11S

90-OHM-10 0MA

PLACEME NT_NOTE= Place FL 4525 clo se to J 4500

20 89

SOT563

SSM6N1 5FEAPE

5%

100K

402

1/16W MF-LF

SOT563

SSM6N1 5FEAPE

5%

100K

402

1/16W MF-LF

402

100K

5% 1/16W MF-LF

10%

402

CERM

0.068U F

10V

16V

10%

CERM

402

0.01UF

SOT-6

FDC606 P_G

CRITICA L

402

0.01UF

16V10%

CERM

PLACEME NT_NOTE= PLACE C4 521 NEXT TO C45 20

402

CERM

10% 16V

0.01UF

PLACEME NT_NOTE= PLACE C4 520 CLOS E TO MC P79

402

CERM

10% 16V

0.01UF

PLACEME NT_NOTE= PLACE C4 526 CLOS E TO J4 500

PLACEME NT_NOTE= PLACE C4 525 NEXT TO C45 26

0.01UF

16V10%

CERM

402

F-ST-SM

CRITIC AL

203740 20E31

CRITIC AL

0603

FERR-7 0-OHM- 4A

10V CERM

20%

402

0.1UF

DLP11S

90-OHM-10 0MA

CRITICAL

402

10V

0.1UF

20%

CERM

DLP11S

CRITICAL

90-OHM-10 0MA

20 89

0.01UF

16V10%

CERM

402

0.01UF

16V10%

CERM

402

0.01UF

16V10%

CERM

402

0.01UF

16V10%

CERM

402

SYNC_DA TE=07/ 01/2008

SYNC_MA STER=C HANG_M9 8_MLB

SATA Connectors

39 9 6

A.0.0

051-7546

SATA_O DD_R2D _N

ODD_PWR _EN_LS5V _L

SATA_HDD _R2D_UF_ P

SATA_HDD _D2R_UF_ P

SATA_HDD _D2R_C_P

SATA_HDD _D2R_C_N

SATA_HDD _D2R_UF_ N

SATA_HDD _R2D_UF_ N

SATA_HDD _R2D_C_N

SATA_HDD _R2D_C_P

SATA_HDD _D2R_P

=PP5V_S0 _HDD

SATA_HDD _D2R_N

SATA_HDD _R2D_P

SATA_HDD _R2D_N

PP5V_S0_ HDD_FLT

SATA_O DD_D2R _C_N SATA_O DD_D2R _C_P

SATA_OD D_D2R_P

SATA_OD D_R2D_UF _N

SATA_O DD_R2D _P

ODD_PWR _EN_L

SATA_OD D_D2R_UF _P

SATA_OD D_D2R_UF _N

SATA_OD D_R2D_C_ N

SATA_OD D_R2D_C_ P

SATA_OD D_R2D_UF _P

ODD_PWR _SS

SATA_OD D_D2R_N

SMC_ODD _DETECT

=PP3V3_ S0_ODD

VOLTAGE= 5V

MIN_NECK _WIDTH=0 .4mm

MIN_LINE _WIDTH=0 .6mm

PP5V_SW _ODD

=PP5V_S 0_ODD

ODD_PWR _EN

=PP3V3_ S0_ODD

PLACEMEN T_NOTE=P LACE L45 00 CLOSE TO J450 1

PLACEMEN T_NOTE=P LACE C45 01 CLOSE TO J450 1

PLACEMEN T_NOTE=P lace FL4 501 clos e to J45 01

PLACEMEN T_NOTE=P LACE C45 02 CLOSE TO J450 1

PLACEMEN T_NOTE=P LACE FL4 502 CLOS E TO J45 01

PLACEMEN T_NOTE=P lace C45 16 close to J450 1

PLACEMEN T_NOTE=P lace C45 10 close to MCP7 9

PLACEMEN T_NOTE=P lace C45 11 next to C4510

PLACEMEN T_NOTE=P lace C45 15 next to C4516

R4590

1

2

J4500

1

10

1112

1314

1516

2

34

56

78

9

FL4520

12

3 4

FL4525

1 2

34

Q4596

3

5

4

R4597

Q4596

6

2

1

R4596

R4595

1 2

C4595

1

2

C4596

1 2

Q4590

1 2 5 6

3

4

C4521

1 2

C4520

1 2

C4526

1 2

C4525

1 2

J4501

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

3

4

5

6

7

8

9

L4500

1 2

C4501

1

2

FL4501

12

3 4

C4502

1

2

FL4502

1 2

34

C4516

1 2

C4510

1 2

C4511

1 2

C4515

1 2

89

39

7

95

89

95

8

89

7

95

7

95

8

7

8

OUT

BI

SYM_VER-1

IN

OUT

IN

SYM_VER-1

BI

OUT

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

OUT2

TPAD

GND

OUT1

OC1*

EN2

EN1

OC2*

IN

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

We can add p rotecti on to 5V if we wan t, but leavin g NC f or now

USB/SMC Debug Mux

Left USB Port B

Left USB Port A

Place L4600 and L46 05 at connec tor pi n

514-0606

Port Power Switch

SEL=0 Choose SMC SEL=1 Choose USB

0603

FERR-2 20-OHM -2.5A

CRITIC AL

CASE-B2- SM

POLY-TAN T

100UF

20%

CRITIC AL

6.3V

10UF

20%

603

X5R

6.3V

0.1UF

402

CERM

10V

20%

20

20 90

CERM

402

10V

0.1UF

SMC_DE BUG_YE S

20%

1/16W MF-LF

5%

10K

402

DLP11S

CRITIC AL

90-OHM-10 0MA

42 43 44

42

402

5%

0

MF-LF

1/16W

SMC_DE BUG_NO

0

402

5% 1/16W MF-LF

16V

402

0.01uF

CERM

20%

402

CERM

16V

0.01uF

20%

CRITIC AL

0603

FERR-2 20-OHM -2.5A

DLP11S

90-OHM-10 0MA

CRITIC AL

6.3V X5R

10UF

603

20%

CASE-B2- SM

6.3V POLY-TAN T

100UF

CRITIC AL

20%

20 90

20

RCLAMP 0502N

CRITIC AL

SLP1210N 6

CRITIC AL

RCLAMP 0502N

603

10UF

X5R

20%

6.3V

USB

CRITIC AL

F-RT-TH-M 97-3

USB

CRITIC AL

MSOP

TPS2064D GN

402

1/16W

5.1K

MF-LF

5%

10% 10V

402

X5R

0.47UF

TQFN

SMC_DE BUG_YE S

CRITIC AL

SIGNAL_M ODEL=USB _MUX

PI3USB 102ZLE

External USB Connectors

SYNC_MA STER=A MASON_M 98_MLB

051-7546

A.0.0

9640

SYNC_DA TE=07/ 02/2008

MIN_LINE _WIDTH=0 .5 mm MIN_NECK _WIDTH=0 .375 mm VOLTAGE= 5V

PP5V_S 3_RTUS B_B_ILI M

PP5V_S 3_RTUS B_B_F

VOLTAGE= 5V

MIN_LINE _WIDTH=0 .5 mm MIN_NECK _WIDTH=0 .375 mm

PP5V_S 3_RTUS B_A_F

MIN_LINE _WIDTH=0 .5 mm MIN_NECK _WIDTH=0 .375 mm VOLTAGE= 5V

USB2_L T1_N

USB2_L T1_P

USB_EX TB_OC_ L

USB2_E XTA_MU XED_N

USB_EX TA_N

USB_EX TA_P

SMC_RX _L SMC_TX _L

=PP3V4 2_G3H_ SMCUSBM UX

USB_PW R_EN

=PP5V_ S3_RTU SB

PM_SLP_S 4_L

USB_LT 2_N

USB_LT 2_P

USB_EX TB_N

USB_EX TB_P

PP5V_S 3_RTUS B_A_ILI M

MIN_NECK _WIDTH=0 .375 mm

MIN_LINE _WIDTH=0 .5 mm

VOLTAGE= 5V

USB_EX TA_OC_ L

USB_DE BUGPRT _EN_L

USB2_E XTA_MU XED_P

L4605

1 2

C4696

1

2

C4695

1

2

C4691

1

2

C4650

1

2

R4650

1

2

L4600

1 2

34

R4651

1 2

R4652

1 2

C4605

1

2

C4615

1

2

L4615

1 2

L4610

1 2

34

C4617

1

2

C4616

1

2

D4600

1

5 42 3

6

D4610

1

5 42 3

6

C4690

1

2

J4600

1

2

3

4

5

6

7

8

J4610

1

2

3

4

5

6

7

8

Q4690

3

4

1

2

8

5

7

6

9

R4690

1

2

C4692

1

2

U4650

6

7

3

4

5

8

10

9

2

1

68 43 42

95

8

21

95

BI

VCC

P1.0/D+

P1.1/D-

P1.2/VRE G

P1.3/SSE L

P1.4/SCL K

P1.5/SMO SI

P1.6/SMI SO

P0.0

P0.1

INT0/P0. 2

INT1/P0. 3

TIO1/P0. 6

NC

TIO0/P0. 5

INT2/P0. 4

VSSP AD

THRML

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

PLACE C4 805 NEAR J4800

16V

402

0.1UF

X7R-CERM

10%

PLACE C4 806 NEAR J4800

402

0.1UF

16V

10%

X7R-CERM

PLACE C4 807 NEAR J4800

402

CERM

0.001UF

50V

10%

5%

10

402

1/16W

MF-LF

PLACE R4 805 NEAR J4800

PLACE C4 808 NEAR J4800

402

CERM

0.001UF

50V

10%

10

5%

402

1/16W

MF-LF

PLACE R4 806 NEAR J4800

402

MF-LF

1/16W

100

5%

PLACE R4 807 NEAR J4800

20 90

X5R

10V

10%

1UF

402-1

CY7C63 803-LQ XC

OMIT

CRITICAL

QFN

0.1UF

402

16V

10%

X7R-CERM

10%

402

50V

0.001UF

CERM

402

1/16W

100

5%

MF-LF

41

F-RT-SM

CRITICAL

FF18-6 A-R11A D-B-3H

PLACE R4 808 NEAR J4800

5%

1/16W

MF-LF

402

4.7

SYNC_MA STER=C HANG_M9 8_MLB

SYNC_DA TE=07/ 01/2008

41 9 6

A.0.0

051-7546

Front Flex Support

IR_VREF_FIL TER

USB_IR_N

DIFFERENTIA L_PAIR=USB2_ IR

USB_IR_P

DIFFERENTIA L_PAIR=USB2_ IR

IR_RX_OUT

IR_RX_OUT_R C

=PP5V_S3_IR

=PP3V42 _G3H_LID SWITCH

=PP5V_S3 _IR

PP5V_S3_I R_R

IR_RX_OU T

PP3V42_G3 H_LIDSWITC H_R

SMC_LID_ R

SMC_LID

SYS_LED_ ANODE

SYS_LED_ ANODE_R

P/N 338 S0633

518S0692

C4805

1

2

C4806

1

2

C4807

1

2

R4805

1 2

C4808

1

2

R4806

1 2

R4807

1 2

C4803

1

2

U4800

5

4

3

8

9

10

20

21

22

23

24

7

6

12

13

15

16

17

18

19

25

2

1

14

11

C4801

1

2

C4804

1

2

R4800

1 2

J4800

1

2

3

4

5

6

R4808

1 2

50

41

43

8

41

42

43

www.laptop-schematics.com

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

BI

OUT

IN

OUT

P13

P14

P15

P16 P66

P10

P11

P12

P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P36

P37

P40

P41

P42

P43

P44

P45

P46

P47

P50

P51

P52

P60

P61

P62

P63

P64

P65

P67

P70

P71

P72

P73

P74

P75

P76

P77

P80

P81

P84

P85

P86

P90

P91

P92

P93

P94

P95

P96

P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0

PA1

PA2

PA3

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE0

PE1

PE2

PE3

PE4

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PH0

PH1

PH2

PH3

PH4

PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

IN

OUT

BI

IN

OUT

BI

IN

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

NOTE: P94 an d P95 a re sho rted, P95 co uld be spare.

(OC) (OC)

If SMS interr upt is not u sed, p ull up to SMC rail.

NOTE: SMS In terrupt can b e acti ve hig h or lo w, ren ame ne t acco rdingl y.

pins d esigned as ou tputs can be left f loatin g,

(OC)

(OC) (OC)

(DEBUG _SW_2)

(DEBUG _SW_1)

(OC)

(OC) (OC)

(OC)

NOTE: Unused pins h ave "S MC_Pxx " name s. Unu sed

(See b elow)

SMC_PB 3:

SMC_IG _THROT TLE_L f or MG system s. Otherw ise, T P/NC ok ay (wa s ISEN SE_CAL _EN)

those designa ted as input s requ ire pul l-ups.

22UF

805

CERM

20%

6.3V

19 44

43 44

43 50

10%

402

CERM-X5R

0.47UF

PLACEM ENT_NO TE=Plac e C490 7 clos e to U 4900 pi n F1

6.3V

10V

402

0.1UF

CERM

20%

10V

402

PLACEM ENT_NO TE=Plac e C492 0 clos e to U 4900 pi ns N14 ,N15

0.1UF

CERM

20%

402

MF-LF

5%

1/16W

4.7

PLACEM ENT_NO TE=Plac e R499 9 clos e to U 4900 pi ns N14 ,N15

10V

402

0.1UF

CERM

20%

SM

21 23

62

10V

402

0.1UF

CERM

20%

21

68

26 68

43

10V

402

0.1UF

CERM

20%

46

47

46

43

43 60

40 42 43 44

68

45

402

1/16W

5%

MF-LF

10K

44

402

1/16W

5%

10K

MF-LF

402

10K

MF-LF

5% 1/16W

402

1/16W

5%

MF-LF

0

NO STU FF

402

1/16W

5%

MF-LF

10K

40

43 60

21 23

7

39

32 43

21 23

43

49

43

49

52

43

52

43

43 44

43

43 44

41 43 50

45

43

40 42 43 44

43

76

19 44

21 28 29

26

44

21 23

19 44

LGA-HF

OMIT

HS82117

OMIT

HS82117

LGA-HF

HS82117

LGA-HF

OMIT

76

52

21 34 37 43

43

9

32

19 44 83 90

26

26 90

51

45

7

21 34 37 44 68 81 83

21 40 43 68

43

26 90

45

43

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

051-7546

A.0.0

9642

SMC

ALL_SY S_PWRG D

SMC_EX CARD_P WR_EN

RSMRST _PWRGD

SMC_PH 2

LPC_PW RDWN_L

SMC_RX _L SMB_MG MT_CLK

SMC_ON OFF_L

PM_SLP _S5_L

SMC_BC _ACOK

PM_CLK RUN_L

SMC_GP U_VSEN SE

SMC_GP U_ISEN SE

SMC_DC IN_ISE NSE SMC_PB US_VSE NSE SMC_BA TT_ISE NSE SMC_NB _MISC_ ISENSE

SMC_WA KE_SCI _L

SMC_PR OCHOT_ 3_3_L SMC_BI L_BUTT ON_L

GND_SM C_AVSS

SMC_PA 5

SMC_PA 0

SYS_ON EWIRE PM_BAT LOW_L

ALS_RI GHT

SMS_ON OFF_L

SMB_MG MT_DAT A

PM_SLP _S4_L

SMB_0_ S0_DAT A

PP3V3_ S5_AVR EF_SMC =PP3V3 _S5_SM C

SMC_RE SET_L

SMC_NM I

SMC_VC L

SMC_KB C_MDE

SMC_MD 1

SMC_TR ST_L

PP3V3_ S5_SMC _AVCC

VOLTAGE= 3.3V

MIN_LINE _WIDTH=0 .25 MM MIN_NECK _WIDTH=0 .20 MM

SMC_EX TAL

SMC_XT AL

SMC_PA 1

PM_SYS RST_L

SMC_OD D_DETE CT

SMC_EX CARD_O C_L SMC_GF X_OVER TEMP_L

SMC_FA N_0_CT L SMC_FA N_1_CT L SMC_FA N_2_CT L SMC_FA N_3_CT L SMC_FA N_0_TA CH SMC_FA N_1_TA CH SMC_FA N_2_TA CH SMC_FA N_3_TA CH

SMS_X_ AXIS SMS_Y_ AXIS SMS_Z_ AXIS SMC_AN ALOG_I D SMC_NB _CORE_ ISENSE SMC_NB _DDR_I SENSE ALS_LE FT

SMC_TD I

SMB_A_ S3_DAT A

SMB_B_ S0_DAT A

LPC_CL K33M_S MC

SMC_SY S_KBDL ED

SMC_TX _L SMC_RX _L SMB_0_ S0_CLK

SMC_PM _G2_EN

SMC_CP U_VSEN SE

SMC_BS _ALRT_ L PM_SLP _S3_L

PM_CLK 32K_SU SCLK

SMC_TM S

SMC_TC K

SMC_P2 6

SMC_TD O

LPC_AD <2>

LPC_AD <1>

SMC_GF X_THRO TTLE_L

USB_DE BUGPRT _EN_L MEM_EV ENT_L

SMB_B_ S0_CLK

PM_RSM RST_L

PM_PWR BTN_L

LPC_AD <0>

LPC_AD <3>

SMC_AD APTER_ EN

SMC_CP U_ISEN SE

SMC_RU NTIME_ SCI_L

SMC_EX CARD_C P

SMC_LI D

ALS_GA IN

SMC_PR OCHOT

SMB_A_ S3_CLK

SMB_BS A_DATA

IMVP_V R_ON

SMC_TX _L

SMC_P2 4

ESTARL DO_EN

SMC_CA SE_OPE N

LPC_FR AME_L SMC_LR ESET_L

LPC_SE RIRQ

SMC_SY S_LED

SMC_P4 1

SMC_TH RMTRIP

SMB_BS A_CLK

=SMC_S MS_INT

SMC_MC P_SAFE _MODE

SMC_PB 3

SMC_RS TGATE_ L

C4902

1

2

C4903

1

2

C4904

1

2

C4905

1

2

C4906

1

2

C4907

1

2

C4920

1

2

R4999

1 2

XW4900

12

R4909

1

2

R4901

1

2

R4902

1

2

R4903

1

2

R4998

1

2

U4900

B12

A13

A12

B13

D11

C13

C12

D10

D13

E11

D12

F11

E13

E12

F13

E10

A9

D9

C8

B7

A8

D8

D7

D6

D4

A5

B4

A1

C2

B2

C1

C3

G2

F3

E4

L13

K12

K11

J12

K13

J10

J11

H12

N10

M11

L10

N11

N12

M13

N13

L12

A7

B6

C7

D5

A6

B5

C6

J4

G3

H2

G1

H4

G4

F4

F1

U4900

N3

N1

M3

M2

N2

L1

K3

L2

B8

C9

B9

A10

C10

B10

C11

A11

G11

G13

F12

H13

G10

G12

H11

J13

M10

N9

K10

L8

M9

N8

K9

L7

K1

J3

K2

J1

K4

K5

N5

M6

L5

M5

N4

L4

M4

M8

N7

K8

K7

K6

N6

M7

L6

E2

F2

J2

A4

B3

C4

U4900

M12

L11

L9

H3

A2

D1

H1

E5

E3

D3

B1M1H10

E1

D2

L3

F10

B11

C5

A3

47

52

46

43

7

8

43

D

S G

CD

GND

NC

OUT

IN

OUT

IN

OUT

BI

OUT

IN

D

S G

GND

OUT

IN

OUT

IN

02

D

SG

NC

OUT

D

SG

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

PART NUMB ER

ALTERNATE FOR

PART NUMB ER

BOM OPTIO N

REF DES

COMMENTS:

SMC Crystal Circuit

NC

Debug Power "Button"

System (Sleep) LED Circuit

SMC FSB to 3.3V Level Shifting

TO SMC

TO CPU

Place R 5015,R5 001 on bottom side

SMC AVREF Supply

SMC Reset "Button" / Brownout Detect

0.1uF

402

CERM

20% 10V

SOT563

SSM6N1 5FEAPE

6.3V

402

0.47UF

CERM-X5R

10%

16V

10%

402

0.01UF

CERM

603

X5R

20%

6.3V

10uF

MF-LF

5%

402

1/16W

0

402

MF-LF

5%

1/16W

10K

402

1/16W5%MF-LF

100K

402

1/16W MF-LF

5%

10K

MF-LF

5%

1/16W

402

10K

5%

MF-LF1/16W

402

100K

2.0K

MF-LF

5%

1/16W

402

ONEWIRE_ PU

MF-LF

5%

1/16W

100K

402

MF-LF

5%

1/16W

10K

402

10K

1/16W5%MF-LF

402

10K

5%

1/16W MF-LF

402

10K

5%

402

MF-LF1/16W

402

MF-LF1/16W

5%

10K

5%

402

MF-LF1/16W

10K

5%

1/16W

10K

402

MF-LF

CRITICAL

NCP303L SN

SOT23-5-H F

5%

100K

402

MF-LF1/16W

42 44

42

10 14 87

603

MF-LF

0

5% 1/10W

OMIT

SILK_PAR T=SMC_RS T

1/10W

0

5%

OMIT

603

MF-LF

SILK_PAR T=PWR_BT N

SOT563-H F

BC847BV- X-F

MF-LF

1/16W

5%

402

3.3K

1/16W

402

3.3K

5%

MF-LF

470

402

MF-LF

1/16W

5%

10 14 62 87

42

SSM6N1 5FEAPE

SOT563

100K

1/16W5%MF-LF

402

100K

MF-LF

5%

1/16W

402

CRITICAL

REF3333

SOT23-3

42 20 32

MF-LF 402

1K

5% 1/16W

1/16W M F-LF

402

10K

5%

1/16W MF-LF

402

5%

10K

5%

0

402

MF-LF

1/16W

5X3.2-SM

20.00M HZ

CRITIC AL

5%

50V

15pF

CERM

402

50V

CERM

5%

15pF

SOT563-H F

BC847BV- X-F

5%

1/16W

402

MF-LF

470K

SOT553-5

SN74LVC 1G02

SSM6N1 5FEAPE

SOT563

74LVC1 G17DRL

SOT-553

0.01UF

402

X7R

10% 25V

0.1UF

402

X5R

16V

10%

10K

5% 1/16W MF-LF 402

SOD

2SA215 4MFV-Y AE

41

SOT563

SSM6N1 5FEAPE

402

1% 1/16W MF-LF

20

1%

MF-LF

1/16W

402

523

1% 1/16W MF-LF

402

1.47K

42

42 43 50

10% 16V

CERM

402

0.01UF

A.0.0

9643

SYNC_DAT E=06/18/ 2008

051-7546

SMC Support

SYNC_MAS TER=AMAS ON_M98_M LB

ALL

353S1278353S1381 Intersil ISL60002-3 3

MAKE_BAS E=TRUE

TP_SMC _P24

SMC_P2 4

SMC_XT AL

SMC_PB 3

ALS_GA IN

SMC_IG _THROT TLE_L

MAKE_BASE=T RUE

MAKE_BAS E=TRUE

TP_SMC _RSTGA TE_L

SMC_RS TGATE_ L

SMC_ONOF F_L

=PP5V_ S3_SYS LED

SYS_LE D_L_VD IV

SYS_LE D_L

SYS_LE D_ILIM

SMC_SY S_LED

SYS_LE D_ANOD E

SMC_TPAD _RST_L

SMC_ONO FF_L

=PP3V3_S 5_SMC

MAKE_BASE=T RUE

SMC_CPU _FSB_ISE NSE

SMC_ANA LOG_ID

SMC_FAN_ 3_TACH

NC_ESTA RLDO_EN

MAKE_BASE=T RUE

SMC_FAN_ 3_CTL

SMC_PA1

MAKE_BASE=T RUE

NC_SMC_F AN_3_TAC H

=PP1V05_ S0_SMC_L S

=PP3V3_S 0_SMC

SMC_PA0

SMC_ONOF F_L

SMC_LID

CPU_PROC HOT_L

SMC_THRM TRIP

CPU_PROC HOT_L_R

SMC_PROC HOT_3_3_ L

CPU_PROC HOT_BUF

SMC_PROC HOT

SMC_EXCA RD_CP

=PP3V3_S 5_SMC

SMC_ADAP TER_EN

=PP3V3 _S0_SM C

=CHGR_AC OK

NC_SMC_F AN_2_TAC H

MAKE_BASE=T RUE

NC_SMC_F AN_3_CTL

MAKE_BASE=T RUE

SMC_BC_A COK

MAKE_BASE=T RUE

ESTARLD O_EN

ALS_LEF T

SMC_MCP _VSENSE

MAKE_BASE=T RUE

ALS_RIG HT

MAKE_BASE=T RUE

SMC_CPU _HI_ISEN SE

SMC_NB_ DDR_ISEN SE

MAKE_BASE=T RUE

SMC_GPU _1V8_ISE NSE

=PPVIN_S 5_SMCVRE F

SMC_BM ON_MUX _SEL

MAKE_BAS E=TRUE

NC_ALS _GAIN

MAKE_BASE=T RUE

MAKE_BAS E=TRUE

TP_SMC _P41

SMC_P2 6

SMC_P4 1

SMC_EX TAL

=SMC_S MS_INT

SMC_XT AL_R

PP3V3_S5 _AVREF_S MC

VOLTAGE=3.3 V

MIN_LINE_WI DTH=0.4 mm MIN_NECK_WI DTH=0.2 mm

PM_THRMT RIP_L

EXCARD_O C_L

SMC_NB_ CORE_ISE NSE

SMC_MCP _CORE_IS ENSE

MAKE_BASE=T RUE

SMC_MCP _DDR_ISE NSE

SMC_NB_ MISC_ISE NSE

SMC_RX_L

SMC_TX_L

SMC_PH2

SYS_ONEW IRE

SMC_BS_A LRT_L

SMC_TMS

SMC_TDO

SMC_TDI

SMC_TCK

SMC_BIL_ BUTTON_L

SMC_BC_A COK

MAKE_BASE=T RUE

NC_SMC_F AN_2_CTL

SMC_FAN_ 2_TACH

SMC_FAN_ 2_CTL

SMC_EXCA RD_OC_L

SMS_IN T_L

MAKE_BAS E=TRUE

SMC_CASE _OPEN

PM_SLP_S 4_L

SMC_PA 5

PM_SLP_S 5_L

PP3V42 _G3H

SMC_BI L_BUTT ON_L

SMC_BI L_BUTT ON_DB_L

MIN_NECK_WI DTH=0.2 mm

GND_SMC_ AVSS

VOLTAGE=0V

MIN_LINE_WI DTH=0.4 mm

SMC_TPAD _RST

SMC_MANU AL_RST_L

SMC_RESE T_L

=PP3V3_S 5_SMC

C5000

1

2

R5000

1

2

C5001

1

2

Q5059

3

5

4

C5020

1

2

C5026

1

2

C5025

1

2

R5095

1 2

R5070

1 2

R5071

1 2

R5072

1 2

R5073

1 2

R5074

1 2

R5075

1 2

R5076

1 2

R5077

1 2

R5078

1 2

R5079

1 2

R5080

1 2

R5085

1 2

R5086

1 2

R5088

1 2

U5000

5

3

2

4

1

R5090

1 2

R5001

1

2

R5015

1

2

Q5060

2

6

1

R5061

1

2

R5062

1 2

R5060

1

2

Q5059

6

2

1

R5091

1 2

R5092

1 2

VR5020

3

1 2

R5089

1 2

R5081

1 2

R5010

1 2

Y5010

1

2

C5011

1 2

C5010

1 2

Q5060

5

3

4

R5087

1 2

U5001

1

2

3

5

4

Q5032

3

5

4

U5050

2

3 1

5

4

C5051

1

2

C5050

1

2

R5051

1

2

Q5030

1

3

2

Q5032

6

2

1

R5030

1

2

R5031

1

2

R5032

1

2

52

42

68

52

50

43

50

43

37

60

44

60

42

47

43

42

43

42

34

43

42

60

44

43

40

8

43

46

42

21

42

8

50

42

8

47

42

8

42

41

32

8

21

8

61 42

42

42 46

42

47

8

46 42

42

7

42 47

47

42

40

42

52

42

21

42

7

42

60

42

8

IN

OUT

IN

VCC

GND

SEL OE*

D+

D-

Y+

Y-

M+

M-

OUT

VCC

GND

SEL OE*

D+

D-

Y+

Y-

M+

M-

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

D

SG

D

SG

GS

D

OUT

IN

BI

OUT

IN

BI

IN

OUT

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

LPC+SPI Connector

NOT SUPP ORTED IN REV A01 OR B01 MCP79 SI LICON

MCP SPI Override Options

From F rank C ard

516S0573

Pull-u p on d ebug ca rd

SPI MUX BYPASS

MUX SEL CONTROLL ED BY FR ANKCARD SWITCH O NCE CS1 IS SUPPO RTED IN M CP

MCP79 Internal SPI MUX Support

SEL LO W OUTP UTS TO M (FRA NKCARD ROM)

SEL HI GH OUT PUTS TO D (ON BOARD ROM)

MCP79 REV A0 1 REQUI RES EX TERNAL MUX, REV B01 STILL DOES NOT SU PPORT INTERNA L MUX

Alternate SPI ROM Support

To Fra nk Car d

not co mpatib le with butto n-mash ing.

SLP_S3 # nVid ia reco mmenda tion,

ENSURE S MCP7 9 SPI_D O OR S PI_CLK INPUT IS LOW WHEN STRAP IS LAT CHED.N OT NEED ED FOR B01 O R LATE R.

Keep v ery sh ort

SPI Frequency Clamp

44 53

21 44 90

21 90

21 44 90

TQFN

CRITIC AL

PI3USB 102ZLE

LPCPLU S

20%

CERM 402

10V

0.1UF

LPCPLU S

44 53

402

1/16W

MF-LF

5%

0

MCP_CS 1_NO

402

MF-LF

1/16W

5%

0

MCP_CS 1_NO

TQFN

LPCPLU S

PI3USB 102ZLE

CRITIC AL

LPCPLU S

10V

20%

CERM

0.1UF

402

44 53

44

40 42 43

44 53

42

42 43

19 42

19 42 83 90

44

19 42 83 90

0

MF-LF

5%

1/16W

402

LPCPLU S_NOT

19 42 83 90

7

21 34 37 42 68 81 83

MF-LF

1/16W

5%

402

0

MCP_A0 1&MCP_ A01Q

MCP_CS 1_NO

402

20K

1/16W MF-LF

5%

53

44 53

44

1/16W MF-LF

0

5%

402

PLACEMEN T_NOTE=P LACE NEX T TO U51 20

MCP_CS 1_YES

0

MF-LF

5%

1/16W

402

LPCPLU S_NOT

42 43

42

40 42 43

18

MF-LF

1/16W

402

5%

100K

MCP_A0 1&MCP_ A01Q

SSM6N1 5FEAPE

MCP_A0 1&MCP_ A01Q

SOT563

SSM6N1 5FEAPE

MCP_A0 1&MCP_ A01Q

402

0

5%

MF-LF

1/16W

5%

MF-LF

0

402

LPCPLU S_NOT

NO STU FF

0

5% 1/16W MF-LF

402

MF-LF

PLACEMEN T_NOTE=P lace nea r J5100

5%

1/16W

402

0

MCP_CS 1_NO

100K

MF-LF

402

5%

1/16W

SSM3J16F V

SOD-VESM-HF

MCP_CS 1_YES

470

1/16W

5%

402

MF-LF

MCP_CS 1_YES

M-ST-SM

LPCPLU S

CRITIC AL

55909- 0374

42 43

19 42

MCP_CS 1_YES& LPCPLUS _NOT

402

0

1/16W MF-LF

5%

PLACEMEN T_NOTE=P LACE NEX T TO U14 00

44

19 42

44

19 42 83 90

26 90

53 90

19

9

21

402

10K

1/16W

5%

MF-LF

402

10K

5%

MF-LF

1/16W

21 44 90

A.0.0

9644

051-7546

SYNC_DA TE=07/ 01/2008

SYNC_MA STER=C HANG_M9 8_MLB

LPC+SPI Debug Connector

=SPI_C S1_R_L _USE_ML B

SMC_TC K

SMC_TD I

LPC_PW RDWN_L

LPC_SE RIRQ

SPI_AL T_CS_L

SPI_AL T_CLK

SPIROM _USE_M LB

LPC_AD <3>

LPC_CL K33M_L PCPLUS LPC_AD <2>

=PP3V3 _S5_LP CPLUS

LPC_FRAM E_PU

LPC_FRAM E_R_L

SPI_CS 1_R_L_ USE_MLB

MAKE_BAS E=TRUE

SMC_RX _L

SMC_NM I

SMC_RE SET_L

=PP5V_ S0_LPC PLUS

=PP3V3_S 5_ROM

SPI_ML B_CS_L

SPI_MI SO_MUX

SPI_AL T_MISO

SMC_TX _L

SMC_MD 1

LPC_FR AME_L PM_CLK RUN_L

SPI_AL T_MOSI

LPC_AD <0> LPC_AD <1>

SMC_TD O SMC_TR ST_L

DEBUG_ RESET_ L

SPI_CL K_MUX

SPI_AL T_MOSI

SPI_MLB_C S_L_MUX

SPI_ALT_C S_L_MUX

=PP3V3_S 5_LPCPLU S

SPI_MI SO

SPIROM _USE_M LB

SPI_CS 0_R_L

SPI_MOSI _R

SPI_CLK_ R

SPI_MISO

SPI_CLK_ MUX

SPI_MISO _MUX

SPI_MOSI _MUX

SMC_TM S

LPCPLU S_GPIO

=PP3V3_S 0_LPCPLU S

=PP3V3_S 5_LPCPLU S

SPI_AL T_CLK

SPIROM _USE_M LB

=PP3V3 _S5_RO M

SPI_MO SI_R

SPI_CL K_R

SPI_AL T_CS_L

SPI_AL T_MISO

SPI_MO SI_MUX

PM_SLP _S3_L

MCP_SP I_FORC E_L

=PP3V3 _S5_MC P_A01

MCP_SP I_FORC E

MCP_FO RCE_SP I_DO_L

SPI_CL K

SPI_MO SI

R5158

1 2

R5156

1 2

R5157

1 2

R5146

1 2

U5120

6

7

3

4

5

8

10

9

2

1

C5124

1

2

R5127

1 2

R5126

1 2

U5110

6

7

3

4

5

8

10

9

2

1

C5114

1

2

R5160

1 2

R5144

1

2

R5147

1 2

R5163

1

2

Q5160

3

5

4

Q5160

6

2

1

R5162

1 2

R5161

1 2

R5142

1 2

R5140

1

2

Q5140

3

1

2

R5141

1

2

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

R5190

1

2

R5191

1

2

53

44

23

8

44

8

44

8

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

MCP79 SMBus "1" Connections

J3500

ExpressCard Slot

MCP79 SMBus "0" Connections

SMC "B" SMBus Connections

Batter y Charger

ISL6258A - U7000

(Write: 0x90 Rea d: 0x91)

MCP79

U2300

Battery

SO-DIMM "A"

Mikey

(WRITE: 0X72 REA D: 0X73)

U6860

(Write: 0xA0 Rea d: 0xA1)

Battery Temp - ( Write: 0 x90 Read : 0x91)

(MASTER)

J6955

(See Tab le)

(Write: 0x12 Rea d: 0x13)

Batter y Charger T emp

TMP102: U5540

(Write: 0x92 Rea d: 0x93)

EMC1043- 1: U5570

MCP Temp

EMC1043- 1: U5500

(Write: 0x98 Rea d: 0x99)

CPU Temp

EMC1043- 1: U5550

J3401

ALS

SMC

J3100 U4900

U2300

(MASTER? )

(MASTER)

U4900

GPU Te mp (Ext)

HDCP ROM

U2690 or U2695

(Write: 0xA0-0xA E,

Read: 0x A1-0xAF)

(Write: 0xA2 Rea d: 0xA3)

J3200

SO-DIMM "B"

U4900

SMC

Battery Manager - (Write : 0x16 R ead: 0x1 7)

(MASTER)

(Write: 0x30 Rea d: 0x31)

(Write: 0x98 Rea d: 0x99)

Margin Control

The bus formerly known a s "Batte ry B"

U2900

Vref DACsSMC

U4900

U2901

(MASTER)

TRACKPAD

J5800U4900

SMC

G96: U80 00

GPU Te mp (Int)

(Write: 0x70 Rea d: 0x71)

U5930

SMS

(Write: 0x72 Rea d: 0x73)

Battery

SMC

(Write: 0x9E Rea d: 0x9F)

(Write: 0x98 Rea d: 0x99)

Battery LED Driv er - (Wr ite: 0x3 6 Read: 0x37)

SMC "Management" SMBus Connections

SMC "Battery A" SMBus Connections

(MASTER)

SMC "A" SMBus Connections

NOTE: SM C RMT bu s remain s powere d and ma y be act ive in S 3 state

SMC "0" SMBus Connections

(MASTER)

MCP79

4.7K

402

MF-LF

5%

1/16W

4.7K

402

MF-LF

5% 1/16W

4.7K

5% 1/16W

402

MF-LFMF-LF

5%

402

4.7K

1/16W

5%

MF-LF 402

3.3K

402

MF-LF

1/16W

3.3K

5%

MF-LF

5%

4.7K

1/16W

402

1/16W

402

5%

4.7K

MF-LF

5% 1/16W MF-LF

402

1.6K

5% 1/16W MF-LF 402

1.6K

2.2K

402

MF-LF

1/16W

5%

2.2K

402

MF-LF

1/16W

5%

402

MF-LF

1/16W

5%

2.0K

402

MF-LF

1/16W

5%

2.0K

M98 SMBus Connections

SYNC_MAS TER=DDR

SYNC_DAT E=07/22/ 2008

A.0.0

45 9 6

051-7546

=SMBUS_E XCARD_SD A

MAKE_BASE=T RUE

SMBUS_MC P_1_DATA

MAKE_BASE=T RUE

SMBUS_SM C_A_S3_S DA

MAKE_BASE=T RUE

SMBUS_SM C_A_S3_S CL

I2C_ALS_ SCL

SMBUS_SM C_B_S0_S CL

MAKE_BASE=T RUE

=I2C_MI KEY_SCL

SMBUS_SM C_MGMT_S DA

MAKE_BASE=T RUE

SMBUS_SM C_MGMT_S CL

MAKE_BASE=T RUE

=SMBUS_M CPTHMSNS _SDA

=PP3V3_S 0_SMBUS_ MCP_0

SMBUS_SM C_0_S0_S DA

MAKE_BASE=T RUE

=SMBUS_B ATT_SCL

=SMBUS_B ATT_SDA

MAKE_BASE=T RUE

SMBUS_SM C_B_S0_S DA =I2C_CPU THMSNS_S DA

=I2C_CPU THMSNS_S CL

=SMBUS_T MPSNSR_S CL

=SMBUS_T MPSNSR_S DA

=GPU_I2C S_SDA

=PP3V3_S 0_SMBUS_ SMC_B_S0

=SMBUS_E XCARD_SC L

=I2C_SOD IMMB_SDA

=I2C_SOD IMMA_SDA

SMB_0_S0 _DATA

SMB_0_S0 _CLK

=I2C_HDC PROM_SCL

=SMBUS_G PUTHMSNS _SDA

=PP3V3_G PU_SMBUS _SMC_0_S 0

SMB_B_S0 _DATA

SMB_B_S0 _CLK

SMB_BSA_ CLK

SMB_BSA_ DATA

=I2C_VRE FDACS_SD A

=I2C_VRE FDACS_SC L

SMB_MGMT _CLK

SMB_MGMT _DATA

=I2C_PCA 9557D_SD A

=I2C_PCA 9557D_SC L

=I2C_TPA D_SCL

=I2C_TPA D_SDA

SMB_A_S3 _CLK

=I2C_SMS _SCL

=I2C_SMS _SDA

I2C_ALS_ SDA

=SMBUS_M CPTHMSNS _SCL

=GPU_I2C S_SCL

=I2C_HDC PROM_SDA

=SMBUS_C HGR_SDA

=SMBUS_C HGR_SCL

SMB_A_S3 _DATA

=I2C_SOD IMMA_SCL

=SMBUS_G PUTHMSNS _SCL

=I2C_MI KEY_SDA

=PP3V3_S 3_SMBUS_ SMC_MGMT

SMBUS_SM C_0_S0_S CL

MAKE_BASE=T RUE

SMBUS_SM C_BSA_SD A

MAKE_BASE=T RUE

SMBUS_SM C_BSA_SC L

MAKE_BASE=T RUE

=PP3V3_S 3_SMBUS_ SMC_A_S3

=I2C_SOD IMMB_SCL

=PP3V42_ G3H_SMBU S_SMC_BS A

MAKE_BASE=T RUE

SMBUS_MC P_1_CLK

=PP3V3_S 0_SMBUS_ MCP_1

SMBUS_MC P_0_CLK

MAKE_BASE=T RUE

SMBUS_MC P_0_DATA

R5200

1

2

R5201

1

2

R5291

1

2

R5290

1

2

R5261

1

2

R5260

1

2

R5251

1

2

R5250

1

2

R5280

1

2

R5281

1

2

R5270

1

2

R5271

1

2

R5230

1

2

R5231

1

2

90

21

90

13

32

21

31

93

59

93

48

8

93

60

93

48

77

8

32

29

28 42

42

25

48

8

42

27

27 42

42

27

51

42

52

31

48

77

25

61

42

28 48

59

8

93

8

29

8

21

8

7

OUT

N-CHN

S

D

G

P-CHN

G

D

S

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

IN

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

INA213 has gain of 50V/V

MCP Voltage Sense / Filter

Place sh ort near U8000 c enter

CPU VCore Load Side Current Sense / Filter

Place sh ort near U1000 c enter

Enables PBUS VSe nse divi der when high.

DCIN Current Sense Filter

Place RC close t o SMC

PBUS Voltage Sense & Filter

Rthevani n = 4573 ohms

Consider INA211 (GAIN 500 version) since I=4.93 Amps across R5388

GPU Voltage Sense / Filter

CPU VCore High Side Current Sensor

Place RC close t o SMC

CPU Voltage Sense / Filter

REGULA TOR SI DE:

LOAD S IDE:

Monitors battery discharge

Place RC close t o SMC

Place RC clo se to S MC

BMON Current Sense - Entire circuit must be near SMC (U4900)

current from battery to PBUS

100K

402

MF-LF

1/16W

5%

42

402

MF-LF

1/16W

1%

27.4K

20%

X5R 402

0.22UF

6.3V

1% 1/16W MF-LF

402

5.49K

FDG6332C G

SC70-6

FDG6332C G

SC70-6

6.19K

1% 1/16W MF-LF

402

62

100K

402

MF-LF

1/16W

5%

X5R 402

20%

6.3V

0.22UF

SM

PLACEM ENT_NO TE=Plac e near U1400 cente r

1/16W

402

1%

MF-LF

4.53K

43

402

17.4K

1% 1/16W MF-LF

INA210

SC70

0.5W MF

0.001

1%

1206

43

X5R

0.22UF

402

6.3V

20%

1%

402

1/16W MF-LF

4.53K

8

0.1UF

CERM

10V

20%

402

BMON_E NG

0.1uF

20% 10V

402

CERM

42

0.22UF

X5R

20%

6.3V

402

43

4.53K

MF-LF

1/16W

402

1%

BMON_E NG

402

1/16W MF-LF

100K

5%

SC70

NC7SB31 57P6XG

BMON_E NG

BMON_P ROD

0

1/16W MF-LF

5%

402

61

INA213

SC70

BMON_E NG

0.1uF

402

10V CERM

20%

95 61

42

402

0.22UF

X5R

20%

6.3V

4.53K

1% 1/16W MF-LF

402

42

6.3V

X5R

20%

402

0.22UF

1%

MF-LF

402

1/16W

4.53K

61

42

0.22UF

402

20%

X5R

6.3V

SM

42

1%

4.53K

402

1/16W MF-LF

402

X5R

20%

0.22UF

6.3V

SM

Current & Voltage Sensing

SYNC_MAS TER=SENS OR

SYNC_DAT E=08/14/ 2008

46 9 6

A.0.0

051-7546

CHGR_C SO_R_P

ISNS_C PU_N

=PP3V4 2_G3H_ CPUCORE ISNS

BMON_A MUX_OU T

CHGR_B MON

MCPVSE NSE_IN

SMC_GPU_ VSENSE

SMC_CPU_ VSENSE

SMC_MC P_VSEN SE

SMC_CPU_ ISENSE

=PPVCORE _S0_CPU

=PPVIN _S5_CP U_IMVP_ ISNS_R

GPUVSENS E_IN

CPUVCO RE_HIS IDE_IOU T

CHGR_A MON

SMC_DCIN _ISENSE

GND_SMC_ AVSS

PPBUS_G3 H

SMC_CPU_ HI_ISENS E

GND_SMC_ AVSS

PBUSVSEN S_EN_L

MIN_LINE_WI DTH=0.20 mm MIN_NECK_WI DTH=0.20 mm VOLTAGE=18. 5V

PPBUS_G3 H_VSENSE

PBUSVSEN S_EN_DIV

SMC_PBUS _VSENSE

GND_SMC_ AVSS

ISNS_C PU_P

CPUVSENS E_IN

=PBUSVSE NS_EN

GND_SM C_AVSS

IMVP6_IM ON

=PPVCORE _GPU_REG

SMC_BA TT_ISE NSE

SMC_BM ON_MUX _SEL

=PP3V4 2_G3H_ BMON_IS NS

=PPVCO RE_S0_ MCP

CHGR_C SO_R_N

BMON_I NA_OUT

GND_SM C_AVSS

=PPVIN _S5_CP U_IMVP_ ISNS

C5359

1

2

R5359

1 2

C5380

1

2

R5380

1 2

C5330

1

2

XW5359

1 2

R5309

1 2

C5309

1

2

XW5309

1 2

R5315

1

2

R5385

1

2

C5385

1

2

R5386

1

2

Q5315

6

2

1

Q5315

3

5

4

R5331

1 2

R5316

1

2

C5399

1

2

XW5399

1 2

R5399

1 2

R5332

1

2

U5388

2

5

4

6

1

3

R5388

123

4

C5335

1

2

R5335

1 2

C5388

1

2

C5369

1

2

C5390

1

2

R5391

1 2

R5371

1

2

U5313

43

1

2

6

5

R5330

12

U5303

2

5

4

6

1

3

C5318

1

2

47

12

46

24

46

11

43

8

43

78

22

43

95

8

42

7

42

95

68

42

8

42

www.laptop-schematics.com

V+

V-

THRM

V+

V-

THRM

V+

V-

THRM

OUT

V+

REFIN +

IN-

OUT

GND

IN

OUT

IN

OUT

IN

OUT

V+

V-

THRM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Gain: 27 4x

MCP MEM VDD Current Sense and CPU FSB 1.05V Current Sense share

MCP MEM VDD Current Sense

GPU 1.8V Current Sense

CPU FSB 1.05V Current Sense

dual package opamp U5440

OPA2333s for proto are placeholders for OPA2330

MCP VCore Current Sense

1.05V CPU Current Sense Filter

GPU 1.8V Current Sense Filter

Place RC close t o SMC

NC

dual package opamp U5410

MCP VCore Current Sense Filter

Gain: 27 4x

Place RC close t o SMC

Gain: 27 4x

Place RC close t o SMC

MCP MEM VDD Current Sense Filter

Place RC close t o SMC

GPU VCore Current Sense Filter

GPU VCore Current Sense

NC

GPU VCore Current Sense and GPU 1.8V Current Sense share

New Gain : 2x can sense c urrent u p to 16. 6 Amps

1/16W

4.53K

MF-LF

1%

402

OPA2333 DRBG4

DFN

OPA2333 DRBG4

DFN

43

6.3V X5R 402

20%

0.22UF

1/16W MF-LF

402

1%

4.53K

43

402

6.3V

20%

X5R

0.22UF

MF-LF

1%

402

1/16W

4.53K

43

6.3V

20%

X5R 402

0.22UF

MF-LF

1/16W

1%

402

4.53K

INA213

SC70

10V

402

20%

0.1UF

CERM

4.53K

402

1% 1/16W MF-LF

10K

402

MF-LF

1%

1/16W

1% 1/16W MF-LF

402

10K

0.22UF

20%

X5R 402

6.3V

470PF

402

50V

10%

CERM

78

43

1/16W MF-LF

402

1%

3.65K

1/16W

402

MF-LF

1%

4.53K

1%

MF

0.002

1/4W

1206

SIGNAL_ MODEL=EM PTY

1% 1/16W MF-LF

1M

402

SIGNAL_ MODEL=EM PTY

10%

CERM

470PF

50V

402

10V CERM

20%

0.1UF

SIGNAL_ MODEL=EM PTY

402

MF-LF

1/16W

1M

1%

402

3.65K

MF-LF

1/16W

SIGNAL_ MODEL=EM PTY

CERM

50V

10%

402

470PF

8

20%

CERM

10V

0.1UF

402

CERM

SIGNAL_ MODEL=EM PTY

470PF

50V

10%

402

1M

1%

402

1/16W MF-LF

SIGNAL_ MODEL=EM PTY

402

MF-LF

SIGNAL_ MODEL=EM PTY

1%

1M

1/16W

SIGNAL_ MODEL=EM PTY

10% 50V

470PF

CERM

402

8

0.002

1%

MF

1/4W

1206

8

3.65K

1%

1/16W

402

MF-LF

42

1%

MF-LF

402

1/16W

3.65K

SIGNAL_ MODEL=EM PTY

CERM

10%

470PF

50V

402

SIGNAL_ MODEL=EM PTY

1M

1% 1/16W MF-LF

402

1/16W

3.65K

1%

MF-LF

402

3.65K

1/16W MF-LF

1%

402

SIGNAL_ MODEL=EM PTY

1/16W MF-LF 402

1%

1M

20%

6.3V X5R 402

0.22UF

CERM

SIGNAL_ MODEL=EM PTY

10% 50V

402

470PF

DFN

OPA2333 DRBG4

SYNC_DA TE=08/ 14/2008

Current Sensing

47 9 6

A.0.0

051-7546

SYNC_MA STER=S ENSOR

DDRISN S_R_N

=PPMCP DDR_IS NS

1V05CP U_N

DDRISN S_R_P

=PP3V3 _S0_MC PCOREIS NS

=PP3V3 _S0_MC PDDRISN S

MCPDDR_I OUT

=PP1V8 _S0GPU _ISNS_R

=PP3V3 _S0_GP U1V8ISN S

P1V8GP UISNS_ R_N

CPU1V0 5_S0_I OUT

1V05CP UISNS_ R_N

DDRISN S_N

SMC_GP U_1V8_ ISENSE

GND_SMC_ AVSS

GPUVCORE _IOUT

GND_SMC_ AVSS

SMC_CPU_ FSB_ISEN SE

SMC_MCP_ CORE_ISE NSE

=PP1V8 _S0GPU _ISNS

MCPCORE_ IOUT

GND_SMC_ AVSS

=PPMCP DDR_IS NS_R

P1V8_S0G PU_IOUT

GPUISE NS_P

DDRISN S_P

P1V8GP U_P

P1V8GP U_N

P1V8GP UISNS_ R_P

1V05CP U_P

1V05CP UISNS_ R_P

SMC_MCP_ DDR_ISEN SE

MCPCOR EISNS_ P

MCPCOR EISNS_ N

GND_SMC_ AVSS

SMC_GPU_ ISENSE

GPUISE NS_N

GFXIMV P6_IMO N

C5465

1

2

R5465

1 2

C5475

1

2

R5475

1 2

C5490

1

2

R5440

1 2

C5470

1

2

R5470

1 2

C5435

1

2

R5495

1 2

U5420

2

5

4

6

1

3

C5420

1

2

R5493

1 2

R5491

1 2

R5498

1 2

C5498

1 2

R5415

1 2

R5413

123

4

R5411

1 2

C5411

1 2

C5410

1

2

R5412

1

2

R5414

1 2

C5412

1

2

C5440

1

2

C5441

1 2

R5441

1 2

R5442

1

2

C5442

1

2

R5445

123

4

R5444

1 2

R5443

1 2

C5432

1 2

R5432

1 2

R5431

1 2

R5436

1 2

R5437

1

2

C5472

1

2

U5410

3

2

1

9

4

8

U5410

5

6

7

9

4

8

U5440

3

2

1

9

4

8

U5440

5

6

7

9

4

8

47

46

95

43

95

43

95

66

95

8

95

42

95

66

95

65

42

95

BI

GND

V+

ADD0

ALERT

SCL

SDA

VDD

THERM*

DN2

SMDATA

SMCLK

ALERT*

GND

DP1

THRM_PAD

DN1

DP2

VDD

THERM*

DN2

SMDATA

SMCLK

ALERT*

GND

DP1

THRM_PAD

DN1

DP2

VDD

THERM*

DN2

SMDATA

SMCLK

ALERT*

GND

DP1

THRM_PAD

DN1

DP2

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

to IC pins a s possi ble

GPU Proximity/GPU Die/Left Heat Pipe

Placement note:

Place U5570 under C PU

MCP Proximity/MCP Die/Right Heat Pipe

Placement note:

CPU Proximity/CPU Die/Right Fin Stack

and cl ose to left f in sta ck

Placement note:

Detect MCP D ie Temp eratur e

Detect GPU D ie Temp eratur e

charge r circ uit

Battery Charger Proximity

Detect Left Heat Pi pe Tem peratu re

Place on top side u nder l eft he at pip e near CPU

Placement note:

Detect CPU D ie Temp eratur e

Compensation for External Diode 1 only

Note: EMC1403 can perform Beta

Keep 2 caps as clos e

TEMP SENSOR HAS ADDRESS WRITE:0X92 , READ: 0X93

to IC pins a s possi ble

Placement note:

Place U5550 near GP U

close to rig ht fin stack

Place U5540 near b attery

Placement note:

Place Q5501 on bott om sid e

Detect Right Fin St ack Te mperat ure

Place U5500 near MC P

Placement note:

Keep 2 caps as clos e

Placement note:

Detect Right Heat P ipe Te mperat ure

518S05 19

402

20% 10V CERM

0.1uF

47

1/16W

5%

MF-LF

402

45

10% 50V

402

CERM

0.0022 uF

SIGNAL_ MODEL=EM PTY

0.0022 uF

CERM

402

50V

10%

402

MF-LF

1/16W

10K

5%

402

1/16W

5%

10K

MF-LF

402

10K

1/16W

5%

MF-LF

1/16W

402

10K

MF-LF

5%

10V

CERM

0.1uF

20%

402

SOT732- 3

BC846BMXXH

95 10

95 21

45

10K

5% 1/16W MF-LF

402 402

MF-LF

1/16W

10K

5%

402

0.1uF

20% 10V CERM

402

47

MF-LF

5%

1/16W

402

0.0022 uF

10% 50V

CERM

SIGNAL_ MODEL=EM PTY

0.0022 uF

CERM

402

50V

10%

95 76

SOT732- 3

BC846BMXXH

HPA0033 0AI

SOT563

78171- 0002

M-RT-SM

EMC140 3-1

DFN

CRITIC AL

DFN

EMC140 3-1

CRITIC AL

EMC140 3-1

CRITIC AL

DFN

45

402

20% 10V

0.1uF

CERM

1/16W

402

47

5%

MF-LF

402

SIGNAL_ MODEL=EM PTY

0.0022 uF

CERM

50V

10%

SIGNAL_ MODEL=EM PTY

402

50V

CERM

0.0022 UF

10%

SYNC_DA TE=08/ 14/2008

48 9 6

A.0.0

051-7546

SYNC_MA STER=S ENSOR

Thermal Sensors

GPUTHM SNS_D_ P

PP3V3_ S0_GPU THMSNS_ R

VOLTAGE= 3.3V

MIN_NECK _WIDTH=0 .25 mm

MIN_LINE _WIDTH=0 .38 mm

GPUTHM SNS_TH M_L

GPUTHM SNS_D_ N

=SMBUS _GPUTH MSNS_SD A

=SMBUS _GPUTH MSNS_SC L

GPUTHM SNS_AL ERT_L

GPU_TD IODE_P

GPU_TD IODE_N

REMTHM SNS_AL ERT_L

MCPTHM SNS_D_ P

=I2C_C PUTHMS NS_SCL

MIN_LINE _WIDTH=0 .25 mm MIN_NECK _WIDTH=0 .25 mm VOLTAGE= 3.3V

PP3V3_ S0_CPU THMSNS_ R

CPUTHM SNS_TH M_L

CPUTHM SNS_D2 _N

=I2C_C PUTHMS NS_SDA

CPUTHM SNS_AL ERT_L

CPU_TH ERMD_P

CPU_TH ERMD_N

CPUTHM SNS_D2 _P

MIN_LINE _WIDTH=0 .38 mm

VOLTAGE= 3.3V

MIN_NECK _WIDTH=0 .25 mm

PP3V3_ S3_REM THMSNS_ R

=PP3V3 _S3_RE MTHMSNS

MCP_TH MDIODE _N

MCPTHM SNS_D_ N

MCP_TH MDIODE _P

REMTHM SNS_TH M_L

=SMBUS _MCPTH MSNS_SD A

=SMBUS _MCPTH MSNS_SC L

=PP3V3 _S0_CP UTHMSNS

=PP3V3 _S0_GP UTHMSNS

=PP3V3_S0_B ATTCHARGERTM PSNSR

=SMBUS_TMPS NSR_SCL

=SMBUS_TMPS NSR_SDA

C5570

1

2

R5570

1 2

C5590

1

2

C5580

1

2

C5500

1

2

R5500

1 2

C5511

1

2

C5521

1

2

R5501

1

2

R5502

1

2

R5572

1

2

R5571

1

2

C5540

1

2

Q5501

1

3

2

R5551

1

2

R5552

1

2

C5550

1

2

R5550

1 2

C5551

1

2

C5552

1

2

Q5503

1

3

2

U5540

4

3

2

1

6

5

J5502

3

4

1

2

U5500

83

5

2

4

6

10

9

7

11

1

U5570

83

5

2

4

6

10

9

7

11

1

U5550

83

5

2

4

6

10

9

7

11

1

95

8

95

8

45

www.laptop-schematics.com

G

S D

G

S D

IN

OUT OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

518S0369

Left Fan

Right Fan

518S0369

1/16W

47K

402

5%

MF-LF

1/16W

5%

MF-LF

402

47K

402

MF-LF

47K

5%

1/16W

402

47K

MF-LF

1/16W

5%

402

MF-LF

5%

1/16W

100K

2N7002 DW-X-G

SOT-363

100K

5%

MF-LF

402

1/16W

2N7002 DW-X-G

SOT-363

M-RT-SM

CRITIC AL

78171-0004

M-RT-SM

CRITIC AL

78171-0004

42

42 42

42

Fan Connectors

A.0.0

051-7546

9649

SYNC_MA STER=M 87_MLB

SYNC_DA TE=10/ 17/2007

FAN_LT _PWM

SMC_FA N_1_CT L

SMC_FA N_1_TA CH

SMC_FA N_0_CT L

FAN_RT _PWM

=PP5V_ S0_FAN _RT

FAN_RT _TACH

=PP3V3 _S0_FA N_RT

FAN_LT _TACH

=PP5V_ S0_FAN _LT =PP3V3 _S0_FA N_LT

SMC_FA N_0_TA CH

R5650

1

2

R5655

1 2

R5660

1

2

R5665

1 2

R5651

1

2

Q5660

3

5

4

R5661

1

2

Q5660

6

2

1

J5650

5

6

1 2 3 4

J5660

5

6

1 2 3 4

8

7 7

8

7

8

7

8

D

G S

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSSD+D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER 2)

P0_1

Y

C

B

A

IN

OUT

IN

Y

B

A

Y

B

A

Y

B

A

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

ISSP DATA

ISSP CLOC K

PSOC PROGRAMMING CONNECTOR

APN 518 S0430

PSOC USB CONTROLLER

KEYBOA RD SCA NNER

TEST PO INTS ARE FOR ON BOARD PR OGRAMMI NG

TO MLB CONNE CTOR

VDD PIN 49

CLOSE T O U5701

VDD PIN 22

CLOSE T O U5701

VOUT

ISOLATION CIRCUIT

USB IN TERFAC ES TO M LB

TPAD BUTTONS DISABLE

PLACE THESE COMPONE NTS CL OSE TO J5800

U5701 CHIP D ECOUPLI NG

TMP102

KEYBOARD CONNECTOR

WHEN T HE LID IS CLO SED

LID CL OSE => SMC_LI D_LC < 0.50V

APN 51 8S0637

75.2E-6 W

294E-6 W

96E-6 W

0.72E-3 W

36E-3 W

16.32E- 6 W

0.255E- 6 W

0.0255 V

0.204 V

0.6 V

0.012 V

0.021 V

0.0188 V

POWERV_SNS

4.7 OHM

1.5 OHM

0.2 OHM

10 OHM

2.55 KO HM

R_SNS

10UA

80UA 60MA MA X

60MA MA X

8MA (TY P)

14MA (M AX)

4MA (MA X)

CURRENT

VIN

VDD

V+

PIN NAM E

IC

3V3 LDO

PSOC

18V BOO STER

PLACE C5701, C5702 & C570 3

ISSP S CLK/I2 C SCL

PLACE C5704, C5705 & C570 6

SPI HO ST TO Z2

APN 33 7S2983

ISSP S DATA/I 2C SDA

THE TP AD BUT TONS WI LL BE DISABL E

LID OP EN => SMC_LID _LC ~ 3.42V

THIS A SSUMES THERE' S A PP 3V42_G 3H PUL L UP ON MLB

APN 31 1S0406

SMC_MANUAL_RESET LOGIC

TRACKP AD PIC K BUTTO NS

SOD-VESM- HF

SSM3K15 FV

402

10% 16V

0.1UF

X7R-CERM

33K

402

1/16W MF-LF

5%

33K

402

1/16W

5%

MF-LF

33K

1/16W

5%

402

MF-LF

603

X5R

6.3V

20%

4.7UF

10% 16V X7R-CERM

0.1UF

402402

CERM

50V

100PF

5% 16V X7R-CERM

10%

0.1UF

402402

CERM

50V

5%

100PF

6.3V

603

X5R

4.7UF

20%

MF-LF

1/16W

5%

402

24

MLF

CY8C24794

CRITIC AL

OMIT

402

MF-LF

5%

24

1/16W

CRITICAL

SN74LVC 1G10

SC70

402

1/16W

1.5

5%

MF-LF

41 42 43

CERM

PLACEMENT _NOTE=NEAR J5713

20%

0.1UF

10V

402

5%

1/16W

402

MF-LF

1K

470

1/16W

402

MF-LF

1%

402

MF-LF

1/16W

10K

1%

F-RT-SM1

FH19C-4 S-0.5SH 25

TPAD_D EBUG

8

50

FF14-3 0A-R11 B-B-3H

F-RT-SM

SOT665

TC7SZ08AF EAPE

CRITICA L

TC7SZ08AF EAPE

SOT665

CRITICA L

TC7SZ08AF EAPE

SOT665

CRITICA L

0.1UF

CERM

402

20% 10V

WELLSPRING 1

SYNC_D ATE=06 /18/2008

A.0.0

SYNC_M ASTER= AMASON_M98_ MLB

051-7546

9650

ISSP_SC LK_P1_1

ISSP_SD ATA_P1_ 0

WS_KBD 1

USB_TPA D_R_P

DIFFERENT IAL_PAIR=U SB2_TPAD NET_SPACI NG_TYPE=US B NET_PHYSI CAL_TYPE=U SB_90D

USB_TP AD_N

DIFFERENT IAL_PAIR=U SB2_TPAD

WS_KBD1 5_CAP

USB_TP AD_P

DIFFERENT IAL_PAIR=U SB2_TPAD

WS_CON TROL_K BD

=PP3V4 2_G3H_ TPAD

WS_LEF T_SHIF T_KEY

WS_LEF T_SHIF T_KBD

=PP3V3 _S3_TP AD

WS_LEF T_OPTI ON_KBD

WS_LEF T_OPTI ON_KEY

SMC_TP AD_RST _L

WS_LEF T_OPTI ON_KEY

WS_KBD 23

BUTTON _DISAB LE

WS_KBD 15_C

WS_KBD 12

PSOC_F _CS_L PSOC_M OSI

WS_CON TROL_K EY

WS_CON TROL_K BD

SMC_LID

BUTTON _DISAB LE

WS_KBD 17 WS_KBD 16N

WS_LEF T_SHIF T_KEY

WS_KBD 8

WS_KBD 1

WS_KBD 2 WS_KBD 3 WS_KBD 4 WS_KBD 5 WS_KBD 6

WS_KBD 18

WS_KBD 17

WS_KBD 14

WS_KBD 11

WS_KBD 10

WS_KBD 21

WS_KBD 20

WS_KBD 19

WS_KBD 23

WS_LEFT_S HIFT_KBD

=PP3V42 _G3H_TP AD

WS_KBD _ONOFF _L

WS_LEFT_O PTION_KBD

WS_CONTRO L_KBD

WS_KBD 7 WS_KBD 8

TP_PSO C_SDA

TP_PSO C_SCL

WS_KBD 11

=PP3V3 _S3_TP AD

WS_KBD 15_C WS_KBD 14

WS_KBD 12

WS_KBD 10 WS_KBD 9

WS_KBD 3

TP_PSO C_P1_3

WS_KBD 13

WS_CON TROL_K EY Z2_KEY _ACT_L

WS_KBD 7

WS_KBD 16N

WS_KBD 18

Z2_HOS T_INTN

TP_P4_ 5 Z2_DEB UG3

Z2_RES ET

Z2_BOO T_CFG1

MIN_NECK_ WIDTH=0.20 MM

MIN_LINE_ WIDTH=0.50 MM

PP3V3_ S3_PSO C

ISSP_S CLK_P1 _1

PSOC_M ISO

PSOC_S CLK Z2_MIS O

Z2_MOS I Z2_SCL K

PICKB_ L

Z2_CS_ L

WS_KBD 2

WS_KBD 19

WS_KBD 20

WS_KBD 21

WS_KBD 22

PP3V3_ S3_PSO C

USB_TPA D_R_N

DIFFERENT IAL_PAIR=U SB2_TPAD NET_SPACI NG_TYPE=US B NET_PHYSI CAL_TYPE=U SB_90D

PP3V3_ S3_PSO C

TP_P7_ 7

Z2_CLK IN

ISSP_S DATA_P 1_0

WS_KBD 5

WS_KBD 4

WS_KBD 6

=PP3V3 _S3_TP AD

=PP3V4 2_G3H_ TPAD

=PP3V3 _S3_TP AD

SMC_ONOFF_L

WS_LEF T_SHIF T_KBD WS_LEF T_OPTI ON_KBD

=PP3V4 2_G3H_ TPAD

WS_KBD 22

WS_KBD1 6_NUM

WS_KBD 13

WS_KBD 9

=PP3V3_ S3_TPAD

=PP3V3 _S3_TP AD

Q5701

3

1

2

C5758

1

2

R5771

1

2

R5770

1

2

R5769

1

2

C5706

1

2

C5705

1

2

C5704

1

2

C5703

1

2

C5702

1

2

C5701

1

2

R5702

1 2

U5701

20

21

45544653475248

51

25182617271628

15

412

421

435644

55

3310

349

358

367

376

385

394

403

2914

3013

3112

3211

24

235722 49

19

50

R5701

1 2

U5703

2

1 3 6

4

5

R5704

1 2

C5710

1

2

R5710

1 2

R5714

1 2

R5715

1 2

J5702

5

6

1

2 3

4

J5713

31

32

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

U5726

2

1

3

5

4

U5727

2

1

3

5

4

U5725

2

1

3

5

4

C5725

12

50

90

50

51

50

51

50

51

50

51

50

43

50

7

20

7

20

7

8

50

7

8

7

50

43

50

7

50

7

50

7

50

7

50

7

8

7

8

50

7

50

7

50

7

50

7

7 7 7

7

50

7

50

7

8

42

7

8

7

8

www.laptop-schematics.com

VDD

VOUT

GND

CE

IN

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

SYM_VER-1

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

trista te SMC _SYS_KB DLED:

KBD BACKLIGHT CONNECTOR

APN 51 8S0612

BOOSTER +18.5VDC FOR SENSORS

APN 152 S0504

- RIPP LE TO MEET ER S

- 100- 300 KH Z CLEAN SPECT RUM

- STAR TUP TI ME LESS THAN 2MS

- R581 2,R581 3,C5818 MODIF IED

BOOSTE R DESI GN CONS IDERAT ION:

- DROO P LINE REGULA TION

- POWE R CONS UMPTION

APN 371 S0313

R5853 ALWAYS PRESEN T

BOM OP TION: KBDLED_ YES

APN 51 6S0689

IPD FLEX CONNECTOR

on key board backlig ht fle x

J5815 pin 1 is grou nded

3V3 LDO FOR IPD

APN 35 3S1364

HIGH= keyboa rd back light not pr esent

LOW = keyboa rd back light presen t

To det ect Ke yboard backli ght, S MC wil l

Keyboard LED Driver

APN 35 3S1401

CRITICA L

M-ST-SM

55560-0 227

2.2UF

X5R

10%

603

16V

MLF

CRITIC AL

MM3243DRRE

1/6W

402-HF

MF

1%

0.2

10%

16V

402

X7R-CERM

0.1UF

4.7UF

603

X5R

6.3V

20%

1/16W

10

1%

MF-LF

402

42

1/16W MF-LF

5%

4.7K

402

MF-LF

1/16W

5%

470K

402

LT3491

DFN

CRITICA L

NO STU FF

5%

MF-LF

402

1/16W

10K

1UF

10% 10V X5R

402-1

1/16W

MF-LF

402

10

1%

CRITIC AL

1098AS-S M

10UH-0. 58A-0.35 OHM

1UF

10% 35V

603

X5R

F-RT-SM

CRITIC AL

FF18-4 A-R11A D-B-3H

PLACEME NT_NOTE= under L5 800 on t op side

1/10W

603

5%

0

MF-LF

0

603

MF-LF

5%

1/10W

PLACEME NT_NOTE= under L5 800 on t op side

PLACEME NT_NOTE= NEAR J58 00

NO STU FF

CRITICA L

0.01H-0.3A- 80V SM-HF

CERM 402

10V

20%

0.1UF

PLACEME NT_NOTE= NEAR J58 00

1/16W MF-LF

0

5%

402

1/16W MF-LF

1M

1%

402

5% 50V CERM

39PF

402

SOD-323

B0520W SXG

603-1

10% 25V X5R

1UF

1/16W MF-LF

1%

71.5K

402

1/16W

1%

MF-LF

100K

VLF3010 AT-SM-H F

3.3UH-870 MA

CRITIC AL

0

5%

1/16W

MF-LF

402

CRITIC AL

QFN

TPS610 45

16V X5R 603

10%

2.2UF

402

10%

X7R-CERM

16V

0.1UF

A.0.0

051-7546

51 9 6

SYNC_D ATE=05 /12/2008

SYNC_M ASTER= PWRSQNC

WELLSPRING 2

SMC_KD BLED_P RESENT_ L

TPAD_G ND_F

PP5V_S 3_TPAD _F

PP5V_S 3_BOOS TER

MIN_NECK_ WIDTH=0.20 MM

MIN_LINE_ WIDTH=0.50 MM

SMC_SY S_KBDL ED

TPAD_G ND_F

PP5V_S 3_TPAD _F

Z2_BOO ST_EN

SWITCH_NO DE=TRUE

MIN_NECK_ WIDTH=0.20 MM

MIN_LINE_ WIDTH=0.50 MM

BOOST_ SW

BOOST_ FB

VOLTAGE=3 V3 MIN_LINE_ WIDTH=0.50 MM MIN_NECK_ WIDTH=0.20 MM

PP5V_S 3_TPAD _F

=PP5V_S3_TPAD

MIN_NECK_ WIDTH=0.20 MM

TPAD_G ND_F

VOLTAGE=0 V MIN_LINE_ WIDTH=0.50 MM

KBDLED_ ANODE

MIN_LINE_W IDTH=0.25 MM MIN_NECK_W IDTH=0.25 MM

KBDLED_ SW

MIN_NECK_W IDTH=0.25 MM

MIN_LINE_W IDTH=0.3 M M

SWITCH_NOD E=TRUE

Z2_MIS O

Z2_MOS I

Z2_DEB UG3

TPAD_G ND_F

0.50MM

0.20MM

Z2_KEY _ACT_L

PSOC_F _CS_L

=I2C_T PAD_SD A

PP18V5 _S3

0.50MM

0.20MM

=I2C_T PAD_SC L

PSOC_S CLK

PSOC_M OSI

PSOC_M ISO

PICKB_ L

Z2_CS_ L

Z2_BOO ST_EN

Z2_HOS T_INTN

Z2_BOO T_CFG1

Z2_CLK IN

0.50MM

0.20MM

PP3V3_S3_LDO

Z2_RES ET

Z2_SCL K

KBDLED _CAP

MIN_LINE_W IDTH=0.25 MM MIN_NECK_W IDTH=0.25 MM

=PP5V_ S0_KBD LED

=PP3V3 _S0_TP AD

PP3V3_S3_LDO

PP5V_S 3_VR

PP3V3_ S3_LDO _R

MIN_LINE_ WIDTH=0.50 MM

MIN_NECK_ WIDTH=0.20 MM

PP18V5 _S3_SW

PP18V5_S3

0.50MM

INPUT_ SW

0.20MM

J5800

1

10

1112 1314 1516 1718 19

2

20

2122

34 56 78 9

C5853

1

2

VR5802

1

4

2

3

R5836

1

2

C5838

1

2

C5854

1

2

R5873

1 2

R5854

1

2

R5853

1

2

U5850

4

6

2

5

3

7

1

R5852

1

2

C5850

1

2

R5855

1

2

L5850

1 2

C5855

1

2

J5815

1

2

3

4

R5800

1 2

R5801

1 2

L5800

1

2 3

4

C5800

1

2

R5806

1 2

R5812

1

2

C5818

1

2

D5802

C5819

1

2

R5813

1

2

R5811

1

2

L5801

R5805

1 2

U5805

53

4

6

1

7

8

9

2

C5817

1

2

C5816

1

2

51

50

51

50

51

50

51

50

51

50

51

7

51

7

51

7

51

8

7

45

7

45

7

8

7

OUT

FS

PD

ST

RES

GND

NC

VOUTX

VOUTY

VOUTZ

VDD

IN

VDDIO

SDI

SDO

VDD

GND

INT

SCK

RESERVED

CSB

NC

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

NC

NoStuff R5931 AND Stuff R5932 if U5930 is not used

Stuff R5931 AND NoStuff R5932 to use U5930

+Y

+X

Front of sys tem

+Y

+X

NC

Front of sys tem

Desired orientation when

NC

Circle indicates pin 1 location when placed

+Z (up )

Desired orientation when placed on board top-side:

+Z (up )

Circle indicates pin 1 location when placed

Pull-u p requ ired if SMS_I NT_L n ot use d.

Digital SMS

in correct orientation

placed on board top-side:

in correct orientation

NC

Analog SMS

R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC

42

0.01UF

402

16V

10% CERM

0.01UF

10% CERM

16V

402

16V

10% CERM

0.01UF

402

10K

5% 1/16W MF-LF

402

CRITIC AL

LGA

AP344ALH

402

10K

1/16W

5% MF-LF

42

0.1UF

X5R

16V

10%

ENG_DI GSMS

402

10% CERM-X5R

402

16V

0.022UF

ENG_DI GSMS

CRITIC AL

ENG_DI GSMS

LGA

273141043

ENG_DI GSMS

MF-LF 402

10K

5% 1/16W

10K

PROD_D IGSMS

MF-LF 402

43

603

20%

10UF

4V X5R

402

X5R

16V

10%

0.1UF

42

SYNC_MA STER=S ENSOR

52 9 6

A.0.0

051-7546

Sudden Motion Sensor (SMS)

SYNC_DA TE=08/ 14/2008

SMS_INT_L

=PP3V3 _S5_SM C

=PP3V3_S3_SMS

=I2C_SMS_SDA

=I2C_SMS_SCL

SMS_Z_ AXIS

SMS_Y_ AXIS

SMS_X_ AXIS

MAKE_BAS E=TRUE

SMS_PW RDN

SMS_SE LFTEST

SMS_ON OFF_L

=PP3V3 _S3_SM S

C5932

1

2

C5931

1

2

U5930

5

3

4

11

12

1

10

6

8

7

2

9

R5931

1

2

R5932

1

2

C5926

1

2

C5922

1

2

C5925

1

2

C5924

1

2

C5923

1

2

R5921

1

2

U5920

1

7

3 6 9

11 13 16

5

15

4

2

14

12

10

8

R5922

1

2

43 42

52

8

45

8

IN

OUT

ININ

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

SPI_CL KSPI_MO SI

Freque ncy

MCP79 SPI Frequency Select

0

1

0

1

0

1

0

1

31 MHz

25 MHz

1 MHz

42 MHz

44

10K

1/16W

5%

MF-LF 402

NO STU FF

402

0

1/16W

5%

MF-LF

PLACEMEN T_NOTE=P LACE CLO SE TO U6 100

44

402

0

1/16W

5%

MF-LF

PLACEMEN T_NOTE=P LACE CLO SE TO U6 100

44 44

402

0

1/16W

5%

MF-LF

PLACEMEN T_NOTE=P LACE CLO SE TO U6 100

MF-LF

5%

1/16W

10K

402

NO STU FF

32MBIT

MX25L320 5DM2I-12 G

CRITIC AL

OMIT

SOP

5%

3.3K

1/16W MF-LF

402 402

MF-LF

3.3K

5% 1/16W

20%

402

CERM

10V

0.1UF

53 9 6

A.0.0

051-7546

SPI ROM

SYNC_MA STER=C HANG_M9 8_MLB

SYNC_DA TE=07/ 01/2008

SPI_MO SI_MUX

SPI_MI SO_MUX

SPI_MO SI

SPI_MI SO_R

=PP3V3 _S5_RO M

SPI_HO LD_L

SPI_WP _L

SPI_ML B_CS_L

SPI_CL K

SPI_CL K_MUX

25MHz is sel ected w ith R5 190 an d R519 1

with R 6190, R6191, R5190 and R5 191

Any of the 4 freque ncies can be selec ted

R6150

1 2

R6190

1

2

U6100

1

4

7

6

5

2

8

3

R6100

1

2

R6101

1

2

C6100

1

2

R6191

1

2

R6105

1 2

R6152

1 2

90

44

90 44

90

8

44

IN

OUT

IN

OUT

IN

OUT

OUTS

OUT

SELB

SELA

BP

IN

GNDENPAD

THRML

SYNC

CD-R

PORT-F-V REFO

PORT-E-V REFO

PORT-B-V REFO

PORT-C-V REFO

PORT-B-R

PORT-B-L

PORT-E-R

PORT-E-L

PORT-H-R

PORT-H-L

PORT-G-R

PORT-G-L

JDREF

VREF

PORT-D-R

PORT-D-L

PORT-C-R

PORT-C-L

SPDIFO

PORT-F-R

PORT-F-L

PORT-A-V REFO/DCVO L

DVSS

CD-GND

BEEP

AVSS2

AVDD2

AVDD1

SDATA_OU T

SDATA_IN

CD-L

SENSE_A

SENSE_B

AVSS1

GPIO1/DM IC-L

BCLK

NC

SPDIFI/E APD/MIDI- I/DMIC-R

PORT-A-L

PORT-A-R

RESET*

GPIO0/DM IC-CLK

PORT-B-V REFO2

DVDD

DVDD_IO

REV B3

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

APPLE P/N 353S1527

AUDIO CODEC

APPLE P/N 353S1897

AUDIO 4.6V REGULATOR

0.1UF

402

10%

X5R

16V

9

21 90

10% 50V CERM 402

0.001U F

10%

402

CERM

50V

402

10%

CERM

50V

0.001U F

50V CERM 402

20%

0.001U F

FERR-2 20-OHM

0402

402

1/16W

1%

20.0K

MF-LF

4.7UF

20%

4V X5R 402

CASE-AL1

6.3V TANT

20%

100UF

CRITIC AL

0402

FERR-2 20-OHM

1K

5% 1/16W MF-LF

402

16V

10%

402

X5R

0.1UF

10% 50V

0.001U F

402

CERM

MF-LF

5%

402

1/16W

33

5% 1/16W

402

100K

MF-LF

100UF

20%

6.3V TANT

CRITIC AL

CASE-AL1

56

57

58

59

55

57

55

SM

1/16W

33

402

5%

MF-LF

5%

20K

MF-LF

402

1/16W

57

TDFN

MAX890 2A

0.015U F

CRITIC AL

X7R

16V

10%

402

SM

16V

10%

TANT

3.3UF

CRITIC AL

SMA-HF

CRITIC AL

10UF

16V

2012-LLP

TANT-POL Y

20%

CRITIC AL

LQFP

ALC885- VB3-GR

SM

59

5%

MF-LF

1/16W

0

402

5%

10K

MF-LF

1/16W

402

10%

0.1UF

X5R

16V

402

MF-LF

1/16W

402

22

5%

59

50V

402

CERM

10%

0.001U F

100K

1/16W

5%

MF-LF 402

9654

A.0.0

051-7546

AUDIO:CODEC

SYNC_DA TE=07/ 09/2008

SYNC_MA STER=A UDIO

NC_AUD _BI_PO RT_H_R

NO_TEST

AUD_CO DEC_VR EF

AUD_CO DEC_JD REF

MIN_LINE _WIDTH=0 .30 MM

GND_AU DIO_CO DEC

VOLTAGE= 0V

MIN_NECK _WIDTH=0 .20 MM

AUD_BI _PORT_ B_L

AUD_BI _PORT_ F_R

AUD_SP DIF_IN AUD_SE NSE_A AUD_SE NSE_B

AUD_BI _PORT_ A_L AUD_BI _PORT_ A_R

CODEC_ DVDD

MIN_LINE _WIDTH=0 .20MM MIN_NECK _WIDTH=0 .20MM

VOLTAGE= 3.3V

HDA_BI TCLK

HDA_SD OUT

AUD_BI _PORT_ C_R

NO_TEST

NC_AUD _BI_PO RT_C_L

AUD_SP DIF_O

AUD_BI _PORT_ B_R

GND_AU DIO_CO DEC

AUD_SP DIF_OU T

AUD_BI _PORT_ F_L

AUD_VR EF_POR T_F

AUD_GP IO_1

BEEP

HDA_SD IN0

CODEC_ SDATA_ IN

AUD_GP IO_0

HDA_SY NC

NO_TEST

NC_BAL _IN_L

=PP3V3 _S0_AU DIO

4V6_RE G_SENS E

NO_TEST

NC_BAL _IN_CO M

NC_VRP

NO_TEST

NC_BAL _IN_R

PP5V_S 3_AUDI O

=PP3V3 _S0_AU DIO

AUD_RE G_SHDN _L

MIN_LINE _WIDTH=0 .20MM MIN_NECK _WIDTH=0 .20MM

AVDD_A DC_DAC

4V6_RE G_BP

NO_TEST

NC_AUD _BI_PO RT_G_R

AUD_GP IO_0_R

AUD_VR EF_POR T_B

NO_TEST

NC_AUD _VREF_ PORT_C

4V6_RE G_SENS E

VOLTAGE= 5V

MIN_LINE _WIDTH=0 .30 MM

AUD_4V 6_REG_ IN

MIN_NECK _WIDTH=0 .20 MM

GND_AU DIO_CO DEC

PP4V6_ AUDIO_ ANALOG

HDA_RS T_L

NO_TEST

NC_AUD _VREF_ PORT_E

AUD_BI _PORT_ E_R

AUD_BI _PORT_ E_L

AUD_VR EF_POR T_A

MIN_LINE _WIDTH=0 .30MM

PP4V6_ AUDIO_ ANALOG

VOLTAGE= 4.6V

MIN_NECK _WIDTH=0 .20MM

NO_TEST

NC_AUD _VREF_ PORT_B2

NC_AUD _BI_PO RT_H_L

NO_TEST

NC_AUD _BI_PO RT_G_L

AUD_BI _PORT_ D_R

AUD_BI _PORT_ D_L

C6201

1

2

L6201

1 2

R6205

1

2

C6220

1

2

C6222

1

2

C6206

1

2

C6203

1

2

C6207

1

2

R6206

1

2

C6200

1

2

C6204

1

2

L6200

1 2

R6220

1 2

C6210

1

2

C6209

1

2

R6203

1 2

R6207

1

2

C6205

1

2

XW6200

1 2

R6250

1 2

R6251

1

2

U6201

7

3

2

1

8

6

4

5

9

C6211

12

XW6203

1 2

C6221

1

2

C6208

1

2

U6200

25

38

26

42

6

12

19

18

20

1

9

4

7

2

3

40

37

39

41

33

21

22

28

32

23

24

29

35

36 14

15

31

16

17

30

43

44

45

46

11

8

5

13

34

47

48

10

27

XW6201

1

2

R6208

1 2

R6221

1

2

C6212

1

2

R6204

1 2

59

57

59

57

56

58

56

59

55

54

56

54

55

54

8

54

9

8

54

V-

V+

V-

V+

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

FC = 1.8 HZ

GAIN = -5.4DB AV = 0.52

Pseudo-Diff Line-In Filter

13.3K

1%

1/16W

402

MF-LFMF-LF

25.5K

1%

1/16W

402

13.3K

MF-LF

1%

402

1/16W

UMAX-HF

MAX425 3EUB

CRITIC AL

402

CERM

50V

10%

0.001U F

CRITIC AL

13.3K

MF-LF

1%

1/16W

402

UMAX-HF

MAX425 3EUB

CRITIC AL

13.3K

1/16W MF-LF

1%

402

25.5K

1% 1/16W MF-LF

402

1%

25.5K

402

MF-LF

1/16W

1%

402

25.5K

MF-LF

27.4K

1/16W MF-LF

1%

402

1/16W

1%

402

MF-LF

27.4K

59

54

58

402

5%

10

MF-LF

1/16W

58

402

1/16W MF-LF

1%

165

54

2.2UF

603

16V X5R

10%

CRITIC AL

603

2.2UF

16V

10%

X5R

CRITIC AL

0402

FERR-2 20-OHM

CRITIC AL

TANT

6.3V

20%

100UF

CASE-AL1

CRITIC AL

0.001U F

402

50V

CERM

10%

6.3V CERM

20%

402-LF

CRITIC AL

2.2UF

2012-LL P

20% 16V

CRITIC AL

10UF

TANT-PO LY

2012-LL P

10UF

16V

20%

TANT-PO LY

CRITIC AL

2012-LL P

20% 16V

TANT-PO LY

CRITIC AL

10UF

2012-LL P

20% 16V

TANT-PO LY

10UF

CRITIC AL

SYNC_M ASTER= AUDIO

051-7546

9655

A.0.0

AUDIO: LINE IN

SYNC_D ATE=07 /09/200 8

GND_AU DIO_CO DEC

AUD_VR EF_POR T_A

AUD_LI FILT_L T_R

AUD_LI _INL_C

AUD_LI FILT_R T_R

AUD_BI _PORT_ A_R

AUD_LI _INR_RAUD_L I_INR_ C

AUD_LI _INR

PP4V6_ AUDIO_ ANALOG

AUD_LI _GND

AUD_CO DEC_IN REF

AUD_PO RTA_R

AUD_LI FILT_R T

AUD_BI _PORT_ A_L

AUD_LI FILT_L T

AUD_LI FILT_S HUTDOWN _L

AUD_LI _INL

MIN_LI NE_WID TH=0.20 MM

PP4V6_ AUDIO_ LINE_IN

MIN_NE CK_WID TH=0.20 MM

AUD_PO RTA_L

AUD_LI _INL_R

GND_AU DIO_CO DEC

R6312

1 2

R6310

1 2

R6313

1 2

U6300

7

8

9

6

10

4

C6300

1

2

R6322

1 2

U6300

3

2

1

5

10

4

R6323

1 2

R6311

1 2

R6320

1 2

R6321

1 2

R6302

1

2

R6303

1

2

R6301

1 2

R6300

1 2

C6312

1 2

C6322

1 2

L6300

1 2

C6302

1

2

C6303

1

2

C6301

1

2

C6310

12

C6311

12

C6320

12

C6321

12

59

57

56

55

59

55

54

IN

SVSS

INL

SHDN*

INR

VDD

PVSS

PGND

SGND

THRM

OUTR

OUTL

C1P

C1N

PAD

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

HP:3.52 HZ VOLTAGE GAIN:1.53

APN:353S1637

Headphone Amplifier (MAX9724A)

1st Order DAC Filter

LP:34 KHZ

56

54

TANT

CRITIC AL

16V

10%

3.3UF

SMA-HF

54

0.001U F

CERM

10% 50V

402

1/16W MF-LF

5%

0

402

SM

0402

FERR-1 000-OH M

58

SM

0

5%

MF-LF

1/16W

402

MAX972 4A

CRITIC AL

TQFN

10UF

2012-LLP

16V

TANT-POL Y

20%

CRITIC AL

10%

10UF

X5R-CERM

16V

0805

CRITIC AL

1UF

10% 10V

402

X5R

10%

402

10V

1UF

X5R

CRITIC AL

MF-LF

5%

1/16W

10K

402

FERR-1 20-OHM -1.5A

0402

2.21K

402

MF-LF

1/16W

1% 1%

1/16W MF-LF

2.21K

402

21K

1% 1/16W MF-LF

402

CRITIC AL

220PF

CERM

25V

5%

402

220PF

CRITIC AL

CERM

25V

5%

402

MF-LF

1/16W

1%

21K

1%

MF-LF

1/16W

13.7K

402

MF-LF

1/16W

13.7K

1%

402

CRITIC AL

TANT

16V

10%

3.3UF

SMA-HF

58

A.0.0

051-7546

56 9 6

SYNC_DA TE=07/ 09/2008

SYNC_MA STER=A UDIO

AUDIO: HEADPHONE AMP

AUD_HP AMP_OU TL_R

PP5V_S 3_AUDI O

AUD_HP AMP_IN L_M

AUD_BI _PORT_ D_L

VOLTAGE= 5V

MIN_NECK _WIDTH=0 .20 mm

PP5V_A UDIO_H PAMP_PV DD_F

MIN_LINE _WIDTH=0 .30 mm

AUD_BI _PORT_ D_R

MIN_LINE _WIDTH=0 .2 mm MIN_NECK _WIDTH=0 .15 mm

AUD_PO RTD_L

MIN_NECK _WIDTH=0 .15 mm

MIN_LINE _WIDTH=0 .2 mm

AUD_PO RTD_R

AUD_GP IO_0

MAX972 4_C1N

MIN_NECK _WIDTH=0 .20 mm

MIN_LINE _WIDTH=0 .30 mm

GND_AU DIO_HP AMP_PGN D

MIN_LINE _WIDTH=0 .2 mm MIN_NECK _WIDTH=0 .15 mm

AUD_HP AMP_OU TL_R

MIN_NECK _WIDTH=0 .10 mm

MIN_LINE _WIDTH=0 .20 mm

MAX972 4_PVSS

AUD_HP AMP_MU TE_L

AUD_HP AMP_IN L_M

AUD_CO DEC_OU TR_C

AUD_CO DEC_OU TL_C

AUD_HP AMP_OU TR_R

AUD_HP AMP_IN R_M

MAX972 4_C1P

MIN_LINE _WIDTH=0 .2 mm MIN_NECK _WIDTH=0 .15 mm

AUD_HP AMP_OU TR_R

GND_AU DIO_CO DEC

MIN_NECK _WIDTH=0 .20 mm

AUD_LO _GND

MIN_LINE _WIDTH=0 .30 mm

R6523

1 2

C6503

1

2

C6504

1

2

R6500

1

2

L6500

1 2

R6514

1

2

R6524

1

2

R6511

1 2

C6511

12

C6521

12

R6521

1 2

R6510

1 2

R6520

1 2

C6510

1 2

C6520

1 2

C6501

1

2

R6513

1 2

XW6500

1 2

L6501

1 2

XW6501

1 2

U6500

3

1

6

8

11

10

247

5

9

13

12

C6500

1

2

C6502

1

2

59 57

54

55

56

9

56

54

IN

OUT

IN

OUT

OUTA

IN_P

OUTB

SYNC_OUT

SYNC_IN

PVDD

SD*

IN_N

PAD

GND

THRML

VDD

OUTA

IN_P

OUTB

SYNC_OUT

SYNC_IN

PVDD

SD*

IN_N

PAD

GND

THRML

VDD

OUTA

IN_P

OUTB

SYNC_OUT

SYNC_IN

PVDD

SD*

IN_N

PAD

GND

THRML

VDD

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

PLACE C6 621/C662 2 CLOSE TO PVDD PIN

PLACE C6 631/C663 2 CLOSE TO PVDD PIN

PLACE C6 611/C661 2 CLOSE TO PVDD PIN

PLACE CLOSE TO U6620 PIN6

PLACE CLOSE TO U6610 PIN6

SPEAKER CHECKPOINTS

53Hz < FC (SUB) < 62Hz

79Hz < FC (L&R) < 93Hz

GAIN = 12DB

APN: 353S1901

2X MONO SPEAKER AMPLIFIERS (LM48310)

1/16W

5%

MF-LF

100K

402

0.1UF

10%

CRITIC AL

16V

402

X7R-CERM

0402

FERR-1 000-OH M

54

0402

FERR-1 000-OH M

7

58 95

7

58 95

7

58 95

402

16V X7R-CERM

10%

CRITIC AL

0.1UF

1/16W

5%

MF-LF

33

402

50V

CRITIC AL

CERM

0.001U F

10% 10%

CRITIC AL

10V X5R

1UF

402-1

20%

47UF

CRITIC AL

CASE-A4

6.3V

TANT-POL Y

10% 50V

402

CERM

CRITIC AL

0.001U F

X5R 402-1

1UF

10% 10V

CRITIC AL

X7R-CERM 402

10% 16V

0.1UF

CRITIC AL

10%

402

16V

CRITIC AL

0.1UF

X7R-CERM

0402

FERR-1 000-OH M

54

0

MF-LF

402

5%

1/16W

0

MF-LF

402

5%

1/16W

5%

402

0

MF-LF

7

58 95

1/16W

5%

402

MF-LF

0

20%

6.3V

CRITIC AL

47UF

TANT-POL Y

CASE-A4

LLP

LM4831 0

CRITIC AL

LLP

LM4831 0

402

5% 1/16W MF-LF

0

NOSTUF F

0

5% 1/16W

402

MF-LF

10%

CRITIC AL

10V X5R

1UF

402-1

10%

0.001U F

CERM

50V

402

CRITIC AL

LLP

CRITIC AL

LM4831 0

TANT

20%

100UF

6.3V

CRITIC AL

CASE-AL1

402

X5R

10%

0.15UF

CRITIC AL

10V

10% 10V

0.15UF

X5R 402

CRITIC AL

0402

FERR-1 000-OH M

54

MF-LF

5%

33

1/16W

402

7

58 95

7

58 95

MF-LF

402

1/16W

5%

0

1/16W

5%

MF-LF

0

402

SYNC_DA TE=07/ 09/2008

AUDIO:SPEAKER AMP

57 9 6

SYNC_MA STER=A UDIO

A.0.0

051-7546

U6610_ SOUT

AUD_BI _PORT_ C_R

AUD_SP KRAMP_ INS_L

AUD_BI _PORT_ B_R

AUD_SP KRAMP_ INR_L

AUD_VR EF_POR T_B

AUD_BI _PORT_ B_L

AUD_SP KRAMP_ INL_L

LM4831 0S_PIN LM4831 0S_NIN

SPKRAM P_S_N_ OUT

SPKRAM P_S_P_ OUT

LM4831 0R_PIN

LM4831 0L_PIN

LM4831 0R_NIN

SPKRAM P_R_N_ OUT

SPKRAM P_R_P_ OUT

LM4831 0L_NIN

SPKRAM P_L_N_ OUT

SPKRAM P_L_P_ OUT

SPKRAM P_SYNC 2

PP5V_S 3_AUDI O_AMP

AUD_SP KRAMP_ SHUTDOW N_L

PP5V_S 3_AUDI O_AMP

SPKRAM P_SYNC 2

U6620_ SOUT

SPKRAM P_SYNC 1

AUD_SP KRAMP_ SHUTDOW N_L

GND_AU DIO_CO DEC

AUD_SP KRAMP_ SHUTDOW N_L

GND_AU DIO_CO DEC

SPKRAM P_SYNC 1

MIN_LINE _WIDTH=0 .30 mm

MIN_NECK _WIDTH=0 .20 MM

SPKRAM P_S_P_ OUT

MIN_LINE _WIDTH=0 .30 mm

SPKRCO NN_R_N _OUT

MIN_NECK _WIDTH=0 .20 MM

MIN_LINE _WIDTH=0 .30 mm

SPKRAM P_S_N_ OUT

MIN_NECK _WIDTH=0 .20 MM MIN_NECK _WIDTH=0 .20 MM

MIN_LINE _WIDTH=0 .30 mm

SPKRCO NN_S_N _OUT

MIN_NECK _WIDTH=0 .20 MM

MIN_LINE _WIDTH=0 .30 mm

SPKRCO NN_S_P _OUT

SPKRCO NN_R_P _OUT

MIN_NECK _WIDTH=0 .20 MM

MIN_LINE _WIDTH=0 .30 mmMIN_LINE _WIDTH=0 .30 mm

MIN_NECK _WIDTH=0 .20 MM

SPKRAM P_R_P_ OUT

SPKRAM P_R_N_ OUT

MIN_NECK _WIDTH=0 .20 MM

MIN_LINE _WIDTH=0 .30 mm

MIN_NECK _WIDTH=0 .20 MM

SPKRCO NN_L_N _OUT

MIN_LINE _WIDTH=0 .30 mm

MIN_NECK _WIDTH=0 .20 MM

SPKRAM P_L_N_ OUT

MIN_LINE _WIDTH=0 .30 mm

MIN_NECK _WIDTH=0 .20 MM

MIN_LINE _WIDTH=0 .30 mm

SPKRCO NN_L_P _OUT

SPKRAM P_L_P_ OUT

MIN_LINE _WIDTH=0 .30 mm

MIN_NECK _WIDTH=0 .20 MM

R6601

1

2

C6613

1 2

L6601

1 2

L6610

1 2

C6614

1

2

R6602

1

2

C6611

1

2

C6610

1

2

C6622

1

2

C6621

1

2

C6620

1

2

C6624

1

2

C6623

1 2

L6620

1 2

R6620

12

R6621

12

R6611

12

R6610

12

C6612

1

2

U6610

8

2

1

10

7

9

4

5

6

11

3

U6620

8

2

1

10

7

9

4

5

6

11

3

R6603

1 2

R6605

1 2

C6630

1

2

C6631

1

2

U6630

8

2

1

10

7

9

4

5

6

11

3

C6632

1

2

C6634

1

2

C6633

1 2

L6630

1 2

R6604

1 2

R6630

12

R6631

12

59

57

56

95

57

55

95

57

9

57

9

57

54

57

54 57

57

IN

OUT

IN

OPERATIN G VOLTAG E 3.3

A - VIN

SHELL

POF

B - VCC

C - GND

AUDIO

SHIELD

PINS

AUDIO

PINS

SHELL

SHIELD

POF

A - VDD

B - GND

C - VOUT

OPERATIN G VOLTAG E 3.3

OUT

BI

OUT

IN

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

APN: 514-0608

APN: 514-0607

AUDIO JACK 2 LINE IN JACK, SPDIF RX

AUDIO JACK 1 LO/HP JACK, SPDIF TX

RETURN FOR HF NOISE

SPEAKER CONNECTOR

APN: 518S0519

APN: 518S0521

MIC CONNECTOR

APN: 518S0520

7

57 95

7

57 95

7

57 95

7

57 95

SM

10

1/16W

402

5%

MF-LF

0.1UF

10%

402

X5R

16V

0402

FERR-2 20-OHM

6.8V-1 00PF

402

CRITIC AL

6.8V-1 00PF

402

6.8V-1 00PF

CRITIC AL

FERR-2 20-OHM

0402

6.8V-1 00PF

402

CRITIC AL

6.8V-1 00PF

402

6.8V-1 00PF

402

CRITIC AL

402

6.8V-1 00PF

402

CRITIC AL

6.8V-1 00PF

56

0402

FERR-1 000-OH M

0402

FERR-1 000-OH M

402

6.8V-1 00PF

CRITIC AL

7

59

7

59

7

59

0402

FERR-1 000-OH M

0402

FERR-1 000-OH M

X5R 402

10% 16V

0.1UF

78171- 0004

CRITIC AL

M-RT-SM

78171- 0003

CRITIC AL

78171- 0002

M-RT-SM

7

57 95

7

57 95

CERM

6.3V

2.2UF

20%

402-LF

0

402

5% 1/16W MF-LF

0

1/16W

5%

MF-LF

402

MF-LF

402

5% 1/16W

0

MF-LF

5%

1/16W

402

5% 1/16W

0

MF-LF

402

0

5%

603

MF-LF

1/10W

402

MF-LF

5%

1/16W

0

1/16W

5%

402

MF-LF

0

1/16W

5%

MF-LF

402

1/16W

0

402

MF-LF

5%

402

MF-LF

5%

1/16W

0

1/16W

5%

MF-LF

0

402

0402

FERR-1 000-OH M

F-RT-TH3

AUDIO-JACK-TRANS-M97

CRITIC AL

F-RT-TH3

AUDIO-RCVR-M97

NOSTUF F

CRITIC AL

CERM

5% 50V

100PF

402

NOSTUF F CRITIC AL

50V

5%

CERM

100PF

402

100PF

CRITIC AL

NOSTUF F

50V CERM

5%

402

NOSTUF F

CRITIC AL

50V

5%

CERM

100PF

402

59

FERR-1 000-OH M

0402

59

50V

5%

402

CERM

100PF

54

55

59

54

56

FERR-2 20-OHM -2.5A

0603

CRITIC AL

FERR-2 20-OHM

CRITIC AL

0402

FERR-2 20-OHM

CRITIC AL

59

10K

MF-LF

5%

1/16W

402

CERM 402

5% 50V

100PF

A.0.0

AUDIO: JACKS

051-7546

SYNC_MA STER=A UDIO

9658

SYNC_DA TE=07/ 09/2008

GND_CH ASSIS_ AUDIO_J ACK

AUD_SP DIF_OU T

AUD_CO NNJ2_T IPDET

AUD_CO NNJ2_S LEEVEDE T

=PP3V3 _S0_AU DIO

GND_CH ASSIS_ AUDIO_J ACK

AUD_CO NNJ1_T IPDET

AUD_CO NNJ1_T IP

=PP3V3 _S0_AU DIO

AUD_CO NNJ1_S LEEVEDE T

AUD_J2 _OPT_O UT

AUD_CO NNJ2_S LEEVE

AUD_CO NNJ2_T IP

AUD_CO NNJ2_R ING

AUD_CO NNJ1_T IPDET_F

AUD_J2 _COM

AUD_LI _GND

AUD_LI _INL

AUD_LI _INR

AUD_CO NNJ2_R ING_F

GND_CH ASSIS_ AUDIO_J ACK

AUD_PO RTD_L

AUD_CO NNJ2_T IPDET_F

AUD_CO NNJ2_T IP_F

AUD_CO NNJ2_S LEEVE_F

AUD_J2 _TIPDE T_R

AUD_SP DIF_IN

AUD_CO NNJ1_S LEEVE2

AUD_CO NNJ1_R ING

AUD_CO NNJ2_S LEEVEDE T_F

AUD_J1 _SLEEV EDET_R

AUD_J1 _TIPDE T_R

AUD_PO RTD_R

AUD_LO _GND

HS_MIC _LO

HS_MIC _HI

AUD_CO NNJ1_S LEEVEDE T_F

AUD_CO NNJ1_T IP_F

AUD_CO NNJ1_S LEEVE2_ F

AUD_CO NNJ1_S LEEVE

AUD_CO NNJ1_S LEEVE_F

AUD_CO NNJ1_R ING_F

SPKRCO NN_S_P _OUT SPKRCO NN_S_N _OUT

SPKRCO NN_R_N _OUT

SPKRCO NN_R_P _OUT

SPKRCO NN_L_P _OUT SPKRCO NN_L_N _OUT

BI_MIC _LO BI_MIC _SHIEL D BI_MIC _HI

L6751

1 2

L6754

1 2

L6756

1 2

C6756

1

2

L6701

1 2

L6704

1 2

L6706

1 2

R6700

1 2

C6705

1

2

XW6701

1 2

R6749

1 2

C6750

1

2

DZ6703

1

2

DZ6754

1

2

DZ6755

1

2

L6758

1 2

DZ6704

1

2

DZ6706

1

2

DZ6702

1

2

DZ6752

1

2

DZ6753

1

2

L6702

1 2

L6703

1 2

DZ6705

1

2

L6705

1 2

L6752

1 2

C6700

1

2

J6782

5

6

1

2

3

4

J6780

4

5

1

2

3

J6781

3

4

1

2

C6701

1

2

R6713

1 2

R6714

1 2

R6715

1 2

R6716

1 2

R6710

1 2

R6711

1 2

R6761

1 2

R6762

1 2

R6764

1 2

R6766

1 2

R6768

1 2

R6701

1 2

J6700

1

10

11

12

13

2

3

4

5

6

7

8

9

J6750

1

10

11

12

2

3

4

5

9

6

7

8

C6782

1

2

C6781

1

2

C6784

1

2

C6783

1

2

59

58

54

58

8

58

8

55

58

OUT

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

D

G S

OUT

IN

OUT

IN

D

SG

D

SG

OUT

IN

OUT

ENABLE

AVDD

SDA

BYPASS

DETECT

GND

MICBIAS

INT*

SCL

OUT

IN

BI

IN

REFERENCE DESIGNATO R(S)

BOM OPTIO N

QTY

DESCRIPTI ON

PART#

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

HS_INT_ L PULL UP ON M CP PAGE

PORT D DETECT (Line-out)

0X14 ( 20,D)

DET AS SIGNMENT

MUTE C ONTROL

PORT E (HEADSET MIC)

PORT G DETECT(SPDIF DELEGATE)

LINE_IN AMP SHUTDOWN CONTROL

0X14 ( 20,D)

VREF_B (100%)

PORT F (BUILT-IN MIC)

PORT A DETECT (Line-in)

PLACE L6800/C6800 CLOSE TO Q 6800/01/02

CODEC OUTPUT SIGNAL PATHS

0X05 ( 05)

0X07 ( 7)

N/A

VREF_B (100%)

VOLUME

SUB

0X03 ( 3)

CONVER TER

0X0A ( 10)

0X07 ( 7)

HEADSE T MIC

BUILT- IN MIC

SPDIF IN

LINE I N

FUNCTI ON

CODEC INPUT SIGNAL PATHS

SPDIF OUT

0X0C ( 12) 0X0D ( 13) 0X0F ( 15)

0X06 ( 6)

0X1B ( 27,E)

0x1F ( SPDIF IN)

0X15 ( 21,A)

MIXER( OUTPUT)

PIN CO MPLEX

0X24 ( 36)

MIKEY MIKEY

N/A

0X24 ( 36)

VREF_F (100%)

0X19 ( 25,F)

N/A

0X08 ( 8)

0X02 ( 2)

MIXER( INPUT)

GPIO_0

0X16 ( 22,G)

0X0F ( 15)

NC

FUNCTI ON

SATELL ITES

N/A

HP/LIN E OUT

NC

VREF_A (50%)

N/A

0X0C ( 12)

NC

0X18 ( 24,B)

CONVER TER

0X0D ( 13)

0X23 ( 35)

0X1A ( 26,C) 0x1E ( SPDIF OUT)

DET AS SIGNMENT 0X15 ( 21,A)

VREF

N/A

PIN CO MPLEX

20%

10V 402

CERM

0.1UF

MF-LF

1/16W

402

47K

5%

1/16W

5%

402

MF-LF

220K

54 59

58

0402

FERR-1 000-OH M

1/16W

1%

402

5.11K

MF-LF

1/16W

100K

5%

402

MF-LF

1/16W

5%

402

MF-LF

220K

402

16V

10%

CERM

0.01UF

54

58 59

402

39.2K

1/16W

1%

MF-LF

0.1UF

10V 402

CERM

20%

1/16W

5%

402

MF-LF

270K

47K

5% 1/16W MF-LF

402

58

1/16W MF-LF

10K

1%

402

SOT563

SSM6N1 5FEAPE

SOT563

SSM6N1 5FEAPE

SOT563 SOT563

SSM6N1 5FEAPE

SOD-VESM -HF

SSM3K1 5FV

54 59

402

2.2K

5% 1/16W MF-LF

402

2.2K

MF-LF

1/16W

5%

50V

10%

402

CERM

0.001U F

402

X5R

25V

CRITIC AL

0.1UF

10%

CERM

5%

50V

15PF

402

MF-LF

100K

1/16W

5%

SM

54

7

58

7

58

7

58

16V

10UF

20%

CRITIC AL

TANT-POL Y 2012-LLP

1/16W

402

MF-LF

5%

100K

SOT563

SSM6N1 5FEAPE

MF-LF

1/16W

5%

100K

402

SSM6N1 5FEAPE

SOT563

55

0402

FERR-1 000-OH M

0402

5%

0

402

MF-LF

1/16W

58

1/16W

MIKEY

2.2K

MF-LF 402

5%

0.001U F

OMIT

402

50V

10% CERM

OMIT

50V

CERM

15PF

5%

402

OMIT

MF-LF

100K

5% 1/16W

402

MIKEY

CRITIC AL

0.1UF

25V X5R 402

10%

SM

54

CD3272A2

WCSP9

MIKEY

402

MIKEY

10K

1% 1/16W MF-LF

MIKEY

100K

5% 1/16W MF-LF

402

MIKEY

CERM

0.01UF

16V

10%

402

0.1UF

10V

20% CERM

FERR-1 000-OH M

MIKEY

0402

CRITIC AL

MIKEY

10UF

603

6.3V X5R

20%

603-HF

MIKEY

CRITIC AL

TANT

6.3V

20%

4.7UF

MIKEY

0

MF-LF

5%

402

1/16W

21

45

9

19

5%01/16W

MF-LF

MIKEY

402

0

MF-LF

MIKEY

1/16W

5%

402

MIKEY

MF-LF

0

1/16W

402

5%

0402

FERR-1 000-OH M

NOSTUF F

131S1513115PF 5% 0 402 CAPACI TOR

C6884 MIKEY

132S0045

MIKEY

1

C6885

100PF 10% 0402 CAPA CITOR

116S000410 OHMS 5% 0402 RESI STOR

C6884

NOMIKEY

0 OHMS 5% 0402 RESI STOR

1

116S0004

C6885

NOMIKEY

116S000410 OHMS 5% 0402 RESI STOR

NOMIKEY

R6883

116S0114

MIKEY

1

100K 5% 0 402 RESIST OR

R6883

SYNC_DA TE=07/ 09/2008

A.0.0

9659

051-7546

SYNC_MA STER=A UDIO

AUDIO: JACK TRANSLATORS

=PP3V3 _S0_AU DIO

HS_SDA

HS_SCL

HS_MIC _HI

AUD_I2 C_INT_ L

AUD_SE NSE_B

HS_INT _L

HS_MIC _BIAS

PP4V6_ AUDIO_ ANALOG

PP3V3_ S0_HS_ RX

MIN_NECK _WIDTH=0 .10 mm

MIN_LINE _WIDTH=0 .10 mm

VOLTAGE= 4.6V

GND_AU DIO_CO DEC

AUD_BI _PORT_ E_L

MAKE_BAS E=TRUE

AUD_LI FILT_S HUTDOWN _L

HS_RST _L

=I2C_M IKEY_S CL

=I2C_M IKEY_S DA

AUD_BI _PORT_ E_R

AUD_IP HS_SWI TCH_EN

GND_AU DIO_CO DEC

HS_MIC _LO

HS_SW_ DET

HS_RX_ BP

AUD_J1 _SLEEV EDET_R

GND_AU DIO_CO DEC

AUD_J1 _SLEEV EDET_R

BI_MIC _HI_F

BI_MIC _HI

BI_MIC _SHIEL D

GND_AU DIO_CO DEC

=PP3V3 _S0_AU DIO

PP3V3_ S0_AUD IO_F

AUD_BI _PORT_ F_R

AUD_VR EF_POR T_F

GND_CH ASSIS_ AUDIO_M IC

GND_AU DIO_CO DEC

BI_MIC _LO

BI_MIC _BIAS

MAKE_BAS E=TRUE

AUD_BI _PORT_ F_L

BI_MIC _LO_F

GND_AU DIO_CO DEC

PP3V3_ S0_AUD IO_F

AUD_LI N_SHUT DOWN

AUD_J1 _TIPDE T_R

AUD_J1 _DET_R C

AUD_J1 _SLEEV EDET_IN V

AUD_IN JACK_I NSERT_L

PP3V3_ S0_AUD IO_F

GND_AU DIO_CO DEC

PP3V3_ S0_AUD IO_F

AUD_PO RTD_DE T_L

GND_AU DIO_CO DEC

AUD_J2 _DET_R C

AUD_SE NSE_A

PP4V6_ AUDIO_ ANALOG

AUD_J2 _TIPDE T_R

AUD_OU TJACK_ INSERT_ L

AUD_SE NSE_A

AUD_PO RTG_DE T_L

C6801

1

2

R6802

1 2

R6801

1

2

L6800

1 2

R6806

1

2

R6803

1 2

R6861

1

2

C6802

1

2

R6813

1

2

C6811

1

2

R6811

1

2

R6812

1 2

R6805

1

2

Q6800

3

5

4

Q6800

6

2

1

Q6801

3

5

4

Q6801

6

2

1

Q6802

3

1

2

R6850

1 2

R6855

1 2

C6851

1

2

C6850

1 2

C6852

1

2

R6852

1

2

XW6850

1 2

XW6851

1 2

C6853

1

2

R6815

1

2

Q6803

6

2

1

R6814

1

2

Q6803

3

5

4

L6851

1 2

L6850

1 2

R6851

1

2

R6882

1

2

C6885

1

2

C6884

1

2

R6883

1

2

C6883

1 2

XW6880

1 2

U6880

A2

C1

A1

B2

C2

C3

B1

B3

A3

R6881

1

2

R6880

1

2

C6881

1

2

C6800

1

2

L6880

1 2

C6880

1

2

C6882

1

2

R6890

12

R6891

12

R6892

12

R6893

12

L6881

1 2

59

57

59

57

58

59

56

58

56

59

54

55

59

55

54

55

8

54

58

54

8

59

54

59

54

59

54

BI

V-

V+

BI

D

S G

D

S G

IN

NC

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

OUT

D

S G

D

SG

G

D S

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Battery Connector

MagSafe DC Power Jack

GND

SIG

The ch assis ground will o therwi se flo at and can send t ransie nts ont o ADAP TER_SE NSE wh en AC i s

1-Wire OverVoltage Protection

Vgs(ma x) = 2 0V

Vgs = 11.750 V @ 20V DCIN Vgs = 7.63V @ 13V D CIN

then t urn of f FET

SYS_ON EWIRE doesn't drive unpow ered U 6990

Q6920 used a s bilat eral s witch to ens ure

Vgs is met w hen SYS _ONEWI RE is high o r low.

Voltag e divi der fro m DCIN ensur es Q69 01

<Ra>

Q6910 restri cts sys tem lo ad to 10K-70 K windo w unti l

3.425V "G3Hot" Supply

Supply needs to gua rantee 3.31V deliv ered to SMC V Ref ge nerato r

NC

516S0698

connec ted.

GND

PWR

Vth = Vdcin * (Rb / (Ra + Rb)) Vth = Vdcin / 2

<Rb>

NC

If ADA PTER_S ENSE > Vth

adapte r dete cts sys tem an d enab les 16 .5V out put.

PWR

<Rb>

<Ra>

(Switc her li mit)

200mA max ou tput

Vout = 3.425

Vout = 1.25V * (1 + Ra / Rb)

518S0588

<Vth>

45 60

MF-LF

402

470K

5%

1/16W

402

CERM

50V

10%

0.001U F

402

270K

1/16W

5%

MF-LF

402

MF-LF

270K

5%

1/16W

402

25V

10%

X5R

0.1UF

100K

402

1/16W MF-LF

5%

1206-1

6AMP-2 4V

CRITIC AL

330K

1/16W

5%

MF-LF

402

MF-LF

402

270K

5%

1/16W

CERM 402

50V

10%

0.001U F

LM397

SOT23-5- HF

CRITIC AL

MF-LF 402

1/16W

1%

24.3K

PLACEMEN T_NOTE=P lace nea r L6900

0.01UF

50V CERM

20%

603

1/16W MF-LF

100K

5%

402

42 43

SSM6N1 5FEAPE

CRITIC AL

SOT563

CRITIC AL

SOT563

SSM6N1 5FEAPE

1/16W

402

1K

MF-LF

5%

42 43

MF-LF

1/16W

402

270K

5%

47

805

1/8W

5%

MF-LF

10UF

805

X5R

10% 25V

CRITICAL

33UH

CDPH4D19FHF- SM

402

5%

50V

CERM

22pF

1%

402

MF-LF

200K

1/16W

402

1/16W

1%

MF-LF

348K

X5R-CERM

6.3V

20%

22UF

603

SOT665

HN2D01 JEAPE

LT3470 ETS8

CRITICAL

TSOT23-8

6.3V

0.22UF

20%

X5R 402

FERR-5 0-OHM

SM-LF

0.001U F

50V

402

CERM

10%

43

402

0.001UF

50V

CERM

10%

CERM

5%

47PF

402

50V

5%

47PF

50V

402

CERM

0.001UF

50V CERM 402

10%

CRITICAL

78171- 0005

M-RT-SM

CRITIC AL

78048- 0573

BAT-M9 8

F-RT-SM

CRITIC AL

SOT563

SSM6N15F EAPE

CRITIC AL

SOT563

SSM6N15F EAPE

CRITIC AL

BSS84V

SOT-563

SC-75

RCLAMP24 02B

CRITICAL

SC-75

RCLAMP24 02B

CRITICAL

45 60

SYNC_DA TE=12/ 06/2007

SYNC_MA STER=T 18_MLB

A.0.0

051-7546

9660

DC-In & Battery Connectors

SMC_BS _ALRT_ L

=SMBUS _BATT_ SCL =SMBUS _BATT_ SDA

GND_BA TT_CHG ND

ADAPTE R_SENS E

=PP18V 5_DCIN _CONN

ONEWIR E_PWR_ EN_L_DI V

MIN_NECK _WIDTH=0 .20mm

MIN_LINE _WIDTH=0 .25mm

PP18V5 _DCIN_ ONEWIRE

VOLTAGE= 18.5V

ONEWIR E_EN

SMC_BC _ACOK_ RC

ONEWIR E_PWR_ EN_L

VOLTAGE= 18.5V

MIN_NECK _WIDTH=0 .20mm

MIN_LINE _WIDTH=1 mm

PP18V5 _DCIN_ FUSE

PPVIN_G3 H_P3V42G 3H

PPVBAT _G3H_C ONN

MIN_NECK _WIDTH=0 .3 mm

PPDCIN _S5_P3 V42G3H

MIN_LINE _WIDTH=0 .3 mm

VOLTAGE= 18.5V

P3V42G3 H_BOOST

MIN_NECK _WIDTH=0 .25 mm VOLTAGE= 12.6V

MIN_LINE _WIDTH=0 .4 mm

=PPVBA T_G3H_ P3V42G3 H

ONEWIR E_ESD

=PP3V42_ G3H_REG

ONEWIR E_DCIN _DIV

SYS_ON EWIRE

SMC_BC _ACOK

SYS_ON EWIRE_ BILAT

MIN_LINE_WI DTH=0.5 mm

SWITCH_NODE =TRUE

MIN_NECK_WI DTH=0.25 mm

P3V42G3H _SW

P3V42G3H _FB

=PP18V 5_DCIN _CONN

=PP3V4 2_G3H_ BATT

=SMBUS _BATT_ SCL

SMC_BI L_BUTTO N_DB_L

=SMBUS _BATT_ SDA

MIN_NECK _WIDTH=0 .4 mm

MIN_LINE _WIDTH=0 .6 mm

PPVBAT _G3H_C ONN_F

VOLTAGE= 12.6V

ONEWIR E_OVER VOLT

R6911

1

2

C6910

1

2

R6917

1

2

R6915

1

2

C6915

1

2

R6913

1

2

F6905

1 2

R6912

1

2

R6918

1

2

C6917

1

2

U6915

2

4

1

3

5

R6920

1

2

C6905

1

2

R6914

1

2

Q6920

3

5

4

Q6920

6

2

1

R6910

1 2

R6916

1

2

R6905

1 2

C6990

1

2

L6995

1 2

C6995

1

2

R6996

1

2

R6995

1

2

C6999

1

2

D6905

1

3

5

4

2

U6990

7

6

8

4

2

1

5

3

C6994

1

2

L6950

1 2

C6950

1

2

C6954

1

2

C6953

1

2

C6952

1

2

C6955

1

2

J6955

6

7

1

2

3

4

5

J6900

1

2

3

4

5

J6950

10

11

1

2

3

4

5

6

7

8

9

Q6915

6

2

1

Q6915

3

5

4

Q6910

6

2

1

D6900

3

1

2

D6950

3

1

2

43

60

42

45

8

61

8

G

S

D

CSON

CSOP

VNEG

VCOMP

ICOMP

VREF

ACIN

SDA

VHST

SCL

VDDP

BGATE

VDD

ACOK

THRM_PAD

AGATE

AGND

AMON

BMON

BOOT

CSIN

CSIP

DCIN

LGATE

PGND

PHASE

UGATE

TRKL*

NC

S

D

G

S

D

G

OUT

IN

BI

OUT

GND

VCC

D

S G

D

S G

D

G

S

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

FROM ADAPTER

sparki tectur e requi rement s

thresh old at 13.07V

Input impeda nce of ~40K m eets

Inrush Limiter

is 3.2 V, +/- 50mV

Divide r sets ACIN

VREF = 3.2V, < 300u A

(CHGR_ AGATE)

Reverse-Current Protection

not po wered to coun ter TL 331 bi as cur rent.

TO SYSTEM

152S0542

R7075 clamps CHGR_A MON wh en cha rger i s

2S Bat tery D efault

(L7030 limit )

(PPVBA T_G3H_ CHGR_R)

20V/V 32V/V

(CHGR_ CSO_P) (CHGR_ CSO_N)

(OD)

3S Bat tery D efault

Max Cu rrent = 8.5A

ACIN p in thr eshold

30mA m ax loa d

(OD)

f = 40 0 kHz

(CHGR_ DCIN)

1. L7 030 ch anged f rom T1 8 MLB induct or to 1 52S054 2.

4. Q7 060 an d Q7065 chang ed to 376S06 67.

2. Ad ded Q7 056, C7 058,R7 055,R7 056..

5. Q7 055 an d Q7056 chang ed to 376S06 66.

3. U7 000 Th ermal P ad is now co nnecte d to GN D, not throu gh XW.

M99 di fferen ces fro m last sync on 12/ 02/07 t o T18 MLB:

402

9.31K

1/16W MF-LF

1%

0.033U F

X5R

10% 16V

402

470PF

10% 50V CERM 402

3.01K

MF-LF

1%

1/16W

402

10% 50V

0.001U F

CERM

402

56.2K

1% 1/16W MF-LF 402

10V

10%

X5R

1UF

402

1UF

402

10V

10%

X5R

MF-LF

5%

1/16W

402

4.7

SOD-723- HF

1SS418

1%

MF-LF

30.1K

402

1/16W

10%

X5R

25V

0.1UF

402

MF-LF

1/16W

470K

5%

1/16W

1%

1.82K

402

MF-LF

57.6K

1/16W

402

1%

MF-LF

16V

10%

CERM

402

0.01uF

10%

0.1UF

16V X5R 402

HAT112 7H

CRITIC AL

LFPAK-SM

SM

QFN

ISL625 8A

CRITIC AL

OMIT

10V

10%

X5R

1UF

402 25V

10%

X5R

0.1UF

402

25V

10%

402

0.1UF

X5R

10% 16V

0.047U F

402

CERM

SIGNAL_MO DEL=EMPTY

X5R

10% 25V

402

0.1UF

LFPAK-HF

RJK030 5DPB

CRITIC AL

10

402

MF-LF

1/16W

5%

1/16W

402

10

5%

MF-LF

RJK030 5DPB

LFPAK-HF

CRITIC AL

22UF

20% 25V POLY-TAN T CASE-D2- SM

POLY-TAN T

20%

22UF

25V

CASE-D2- SM

CRITIC AL

10%

X5R

1UF

25V

603-1

CRITIC AL

20% 25V

22UF

POLY-TAN T

CASE-D2- SM

CRITIC AL

8AMP-2 4V

1206

402

5%

MF-LF

1/16W

10

1/16W MF-LF

5%

402

1UF

X5R

10% 25V

603-1

SOD-723-H F

1SS418

NOSTUF F

MF-LF

5%

1/16W

402

62K

100K

5%

MF-LF

1/16W

402

1UF

X5R

25V

10%

603-1

330K

1/16W MF-LF 402

5%

10%

X5R 402

25V

0.1UF

CRITIC AL

SOI

HAT112 8R01HAT1128R 01

SOI

CRITIC AL

46

46 61

45

16V

10%

0.01UF

CERM 402

16V

402

0.1uF

10%

X5R

SIGNAL_MO DEL=EMPTY

X5R

16V

10%

402

0.1uF

50V

10%

0.001U F

CERM 402

43

MF

CRITIC AL

1W

0.5%

0.01

0612

CRITIC AL

0612

0.5%

0.02

MF

1W

TL331

SOT23-5

CRITIC AL

4.7UH- 10.2A

FDA1254F- SM

SSM6N1 5FEAPE

SOT563

1/16W MF-LF

5%

1M

402

SOT563

SSM6N1 5FEAPE

X7R 402

1000PF

10% 25V

402

X7R

1000PF

X5R

16V

10%

0.1UF

402

LFPAK-SM

HAT112 7H

CRITIC AL

330K

5% MF-LF 402 1/16W

5%

1M

402 1/16W

MF-LF

61 9 6

A.0.0

051-7546

SYNC_MA STER=M 99_MLB

SYNC_DA TE=12/ 10/2007

PBus Supply & Battery Charger

CRITIC AL353S18 32

1

U7000

IC,ISL625 8A,BAT CH ARGER,4X4 MM,QFN28

ISL625 8A

ISL625 8

CRITIC AL353S18 11

1

U7000

IC,ISL625 8,BAT CHA RGER,28P, 4X4,QFN,L

CHGR_D CIN

=PPDCI N_S5_C HGR

=PP3V4 2_G3H_ CHGR

CHGR_A CIN

CHGR_A GATE

CHGR_C SO_R_P

BATT_P OS_GAT E

CHGR_C SI_R_P

VOLTAGE= 18.5V

MIN_NECK _WIDTH=0 .4 mm

MIN_LINE _WIDTH=0 .6 mm

PPDCIN _S5_IN RUSH

CHGR_S GATE_D IV

MIN_LINE _WIDTH=0 .3 mm MIN_NECK _WIDTH=0 .3 mm

MIN_LINE _WIDTH=0 .3 mm

CHGR_A GATE_D IV

MIN_NECK _WIDTH=0 .3 mm

=SMBUS _CHGR_ SCL =SMBUS _CHGR_ SDA

=PP3V4 2_G3H_ CHGR

CHGR_A MON

SGATE_ P0V1_V REF

AMON_C LAMP

PP5V1_ CHGR_V DD

CHGR_A MON CHGR_B MON =CHGR_ ACOK

VOLTAGE= 5.1V

MIN_NECK _WIDTH=0 .2 mm

PP5V1_ CHGR_V DDP

MIN_LINE _WIDTH=0 .2 mm

MIN_NECK _WIDTH=0 .25 mm

CHGR_S GATE

MIN_LINE _WIDTH=0 .3 mm

TP_CHG R_TRKL

CHGR_V COMP_R

=PPBUS _G3H

GND_BA TT_CHG ND

VOLTAGE= 12.6V

PPVBAT _G3H_C ONN

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .4 mm

PPVBAT _G3H_F ET

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .4 mm VOLTAGE= 12.6V

CHGR_C SO_P

CHGR_V COMP

CHGR_C SO_N

CHGR_V NEG

CHGR_I COMP

CHGR_V NEG_R

PP5V1_ CHGR_V DD

MIN_LINE _WIDTH=0 .2 mm MIN_NECK _WIDTH=0 .2 mm VOLTAGE= 5.1V

CHGR_C SI_N

GND_CH GR_AGN D

MIN_NECK _WIDTH=0 .2 mm VOLTAGE= 0V

MIN_LINE _WIDTH=0 .2 mm

CHGR_L GATE

MIN_NECK _WIDTH=0 .4 mm VOLTAGE= 12.6V

MIN_LINE _WIDTH=0 .6 mm

PPVBAT _G3H_C HGR_REG

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .2 mm SWITCH_N ODE=TRUE

CHGR_P HASE

PPVBAT _G3H_C HGR_R

VOLTAGE= 12.6V

MIN_NECK _WIDTH=0 .4 mm

MIN_LINE _WIDTH=0 .6 mm

CHGR_C SO_R_N

CHGR_C SI_P

CHGR_C SI_R_N

MIN_NECK _WIDTH=0 .4 mm

MIN_LINE _WIDTH=0 .6 mm

PPDCIN _S5_FE T_CHGR

VOLTAGE= 18.5V

CHGR_B GATE

CHGR_B OOT CHGR_U GATE

PPDCIN _S5_CH GR_R

MIN_LINE _WIDTH=0 .6 mm

VOLTAGE= 18.5V

MIN_NECK _WIDTH=0 .4 mm

R7011

1

2

C7042

1

2

C7016

1

2

R7016

1

2

C7015

1

2

R7015

1

2

C7002

1

2

C7000

1

2

R7001

1 2

D7005

1

2

R7010

1

2

C7060

1

2

R7060

1

2

R7071

1

2

R7070

1

2

C7057

1

2

C7056

1

2

Q7055

5

4

1

2

3

XW7000

1 2

U7000

3

14

1

6

26

9

16

15

25

27

28

17

18

2

5

21

22

23

11

10

29

13

24

7

19

20

12

8

4

C7001

1

2

C7021

1

2

C7022

1

2

C7020

1

2

C7035

1

2

Q7035

5

4

1 2 3

R7022

1 2

R7021

1 2

Q7030

5

4

1 2 3

C7030

1

2

C7031

1

2

C7032

1

2

C7040

1

2

F7040

1

2

R7051

1 2

R7052

1 2

C7033

1

2

D7040

1 2

R7066

1

2

R7065

1

2

C7055

1

2

R7061

1

2

C7005

1

2

Q7060

5 6 7 8

4

1 2 3

Q7065

5 6 7 8

4

1 2 3

C7011

1

2

C7070

1

2

C7050

1

2

C7026

1

2

R7050

2 1

4 3

R7020

123

4

U7070

1

3

4

5

2

L7030

1

2

3

Q7074

3

5

4

R7074

1

2

Q7074

6

2

1

C7034

1

2

C7041

1

2

C7058

1

2

Q7056

5

4

1 2 3

R7057

1 2

R7056

1 2

61

95

61

60

95

8

46

95

8

46

61

8

9

60

93

61

93

46

93

95

IN

OUT

IN

OUT

IN

OUT

IN

OUT

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT*

NTC

VR_ON

PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3

VID2

VID4

VID5

VID6

PGND2

VIN V DD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1

BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Place R7131 Between L7100 ,L7101 and C PU

1

2-Phase

DCM

1-Phase

0

(IMVP6 _FB)

(IMVP6 _PHASE 1)

(GND_I MVP6_S GND)

DCM

44A MAX CURRENT

1-Phase

Operation

DPRSTP*

1

(GND_I MVP6_S GND)

Place R 7126 in hot

(IMVP6 _PHASE 2)

(IMVP6 _ISEN1 )

These caps are for Q7100

spot of reg cir cuit.

0 1

(IMVP6 _VO)

Mode

CCM

PSI*

(GND)

(ISL9504A)

LAYOUT NOTE:

DPRSLPVR

(IMVP6 _VSUM)

CCM

1

0 0

0

1

0 1

(IMVP6 _VO)

(GND)

(IMVP6 _COMP)

(IMVP6 _VW)

These caps are for Q7102

(IMVP6 _ISEN2 )

(IMVP6 _NTC)

(PGD_IN)

1/16W MF-LF

402

10K

1%

10%

0.22UF

10V

CERM

402

SM

25V

603

X5R

20%

0.22UF

9

10 14 87

21 87

10

9

62

26

SM

10K

1/16W MF-LF

402

1%

402

0.22UF

10V

10%

CERM

603

25V

0.22UF

20%

X5R

10

1/16W

402

1%

MF-LF

402

10

1/16W

1%

X5R 402

10V

10%

1UF

1/16W MF-LF

402

1%

10

X5R 402

10%

0.1uF

16V

499

1/16W

402

1%

MF-LF

402

CERM

50V

10%

0.001U F

6.81K

1% 1/16W MF-LF 402

20%

6.3V X5R-CERM 402

4.7UF

CERM

402

0.01uF

16V

10%

402

1%

1K

1/16W MF-LF

1%

402

1/16W MF-LF

1K

50V

402

220PF

X7R-CERM

10%

97.6K

402

1/16W MF-LF

1%

402

MF-LF

1/16W

5%

1

1/16W

402

MF-LF

1

5%

CERM

50V

10%

NO STU FF

0.001u F

402

1/16W MF-LF

1%

3.92K

CERM

50V

402

5%

180pF

402

MF-LF

1K

1% 1/16W

1% 1/16W MF-LF

402

2.61K

402

11K

1/16W

1%

MF-LF

0.22UF

CERM-X5R

10%

402

6.3V

0.068U F

10V CERM 402

10%

402

0

1/16W MF-LF

5%

SIGNAL_M ODEL=EMP TY

16V

10%

CERM

402

0.01UF

402

16V

0.01uF

10%

CERM

NO STU FF

5%

1/16W

402

MF-LF

0

CERM

402

16V

0.01uF

10%

0.22UF

6.3V

20%

402

X5R

SM

1/10W

3.65K

MF-LF 603

1%

3.65K

1/10W

603

MF-LF

1%

CRITIC AL

0.36UH -30A-1 .05MOHM

PCMC104T -SM

0.36UH -30A-1 .05MOHM

PCMC104T -SM

CRITIC AL

0.1UF

X5R 402

10% 16V

9

87

9

87

9

87

9

87

9

87

9

87

9

87

50V

0.001U F

402

CERM

10%

CERM 402

50V

10%

470PF

402

MF-LF

1%

1/16W

255

10%

402

16V

0.015U F

X7R

1%

402

13.3K

1/16W MF-LF

10%

1UF

603-1

25V X5R

CRITIC AL

0603-LF

10KOHM -5%

1/16W

147K

402

MF-LF

1%

402

MF-LF

4.02K

1/16W

1%

MF-LF

1/16W

5%

10K

402

SM

62

11 87

402

CRITIC AL

470K

1/16W

0

MF-LF

402

5%

10 14 43 87

68

MF-LF 402

1/16W

5%

QFN

ISL9504 BCRZ

CRITIC AL

RJK030 5DPB

LFPAK-HF

CRITIC AL

RJK032 8DPB

LFPAK-HF

RJK030 5DPB

CRITIC AL

RJK032 8DPB

LFPAK-HF

CASE-D2-S M

POLY-TANT

22UF

25V

CRITIC AL

20%

CASE-D2-S M

POLY-TANT

22UF

25V

CRITIC AL

20%

22UF

20%

POLY-TANT

CASE-D2-S M

CRITIC AL

25V

10%

X5R

1UF

603-1

46

I848I849

5%

1/16W

0

MF-LF

402

X7R 402

1000PF

25V

10%

1000PF

10%

X7R 402

25V

10% 25V

1000PF

402

X7R

25V X7R 402

1000PF

10%

IMVP6 CPU VCore Regulator

SYNC_MA STER=M 87_MLB

051-7546

A.0.0

62 9 6

SYNC_DA TE=10/ 17/2007

IMVP_V R_ON_R

IMVP6_ VSEN_N

VOLTAGE= 3.3V

PP3V3_ S0_IMV P6_3V3

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .25 MM

IMVP6_ FB

MIN_NECK _WIDTH=0 .20 MM

GND_IM VP6_SG ND

VOLTAGE= 0V

MIN_LINE _WIDTH=0 .50 MM

=PP5V_ S0_CPU _IMVP

IMVP6_ UGATE1

=PPVIN _S5_CP U_IMVP

VOLTAGE= 5V

PP5V_S 0_IMVP 6_VDD

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .25 MM

VR_PWR GOOD_D ELAY

IMVP6_ VID<5>

IMVP6_ VID<3>

IMVP6_ VR_TT_ L IMVP6_ NTC

IMVP6_ SOFT

IMVP6_ RBIAS

IMVP6_ VDIFF

IMVP6_ COMP_R C

IMVP6_ COMP IMVP6_ VW

IMVP6_ PHASE1

IMVP6_ FB2

IMVP6_ ISEN1

IMVP6_ VSUM1

VOLTAGE= 12.6V

MIN_NECK _WIDTH=0 .2 MM

PPVIN_ S5_IMV P6_VIN

MIN_LINE _WIDTH=0 .25 MM

=PP3V3 _S0_IM VP

=PP1V05_ S0_CPU

IMVP6_ VID<4>

IMVP6_ VID<2>

IMVP6_ VID<0>

IMVP6_ VID<1>

CPU_DP RSTP_L

IMVP6_ IMON

VR_PWR GD_CLK EN_L

CPU_PS I_L

IMVP6_ NTC_R

IMVP6_ UGATE2

IMVP6_ PHASE2

IMVP6_ VW

MIN_LINE _WIDTH=0 .25 MM MIN_NECK_W IDTH=0.20 MM

IMVP6_ LGATE2

MIN_NECK _WIDTH=0 .2 MMMIN_LINE _WIDTH=0 .5 MM

IMVP6_ LGATE2

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .25 MM

IMVP6_ ISEN2

MIN_NECK _WIDTH=0 .25 MMMIN_LINE _WIDTH=0 .25 MM

IMVP6_ VO2

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .25 MM

IMVP6_ VSEN_N

IMVP6_ VO2

IMVP_V R_ON

IMVP6_ VDIFF_ RC

IMVP_V R_ON_R

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .25 MM

IMVP6_ VSEN_P

MIN_NECK _WIDTH=0 .2 MM

IMVP6_ ISEN1

MIN_LINE _WIDTH=0 .25 MM

MIN_NECK _WIDTH=0 .2 MMMIN_LINE_W IDTH=0.5 MM

IMVP6_ UGATE1

MIN_NECK _WIDTH=0 .25 MMMIN_LINE_W IDTH=0.2 5 MM

IMVP6_ VSUM1

IMVP6_ BOOT2

MIN_LINE _WIDTH=0 .25 MM MIN_NECK_W IDTH=0.20 MM

IMVP6_ OCSET

MIN_NECK _WIDTH=0 .20 MM

IMVP6_ VO

MIN_LINE _WIDTH=0 .25 MM

MIN_LINE _WIDTH=0 .25 MM MIN_NECK_W IDTH=0.20 MM

IMVP6_ DFB

MIN_NECK _WIDTH=0 .20 MMMIN_LINE_W IDTH=0.2 5 MM

IMVP6_ RBIAS

MIN_NECK _WIDTH=0 .20 MMMIN_LINE_W IDTH=0.2 5 MM

IMVP6_ VDIFF IMVP6_ FB2

MIN_LINE _WIDTH=0 .25 MM MIN_NECK_W IDTH=0.20 MM

MIN_NECK _WIDTH=0 .2 MMMIN_LINE_W IDTH=1.5 MM

IMVP6_ PHASE1

MIN_LINE _WIDTH=0 .25 MM

IMVP6_ BOOT1

MIN_NECK _WIDTH=0 .2 MM

MIN_NECK _WIDTH=0 .2 MMMIN_LINE_W IDTH=0.5 MM

IMVP6_ LGATE1

MIN_NECK _WIDTH=0 .25 MM

IMVP6_ VO1

MIN_LINE _WIDTH=0 .25 MM

MIN_NECK _WIDTH=0 .25 MMMIN_LINE _WIDTH=0 .25 MM

IMVP6_ VSUM2

IMVP6_ VO1

CPU_VC CSENSE _N

CPU_VC CSENSE _P

MIN_NECK _WIDTH=0 .2 MMMIN_LINE _WIDTH=0 .5 MM

IMVP6_ UGATE2

MIN_LINE _WIDTH=0 .25 MM

IMVP6_ BOOT2

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=1 .5 MM

IMVP6_ PHASE2

MIN_NECK _WIDTH=0 .2 MM

PM_DPR SLPVR

MIN_LINE _WIDTH=0 .25 MM MIN_NECK_W IDTH=0.20 MM

IMVP6_ COMP

MIN_LINE _WIDTH=0 .25 MM MIN_NECK_W IDTH=0.20 MM

IMVP6_ SOFT

CPU_PR OCHOT_ L

IMVP6_ VSUM2

IMVP6_ VO_R

IMVP6_ ISEN2

MIN_NECK _WIDTH=0 .20 MMMIN_LINE_W IDTH=0.2 5 MM

IMVP6_ FB

MIN_NECK _WIDTH=0 .20 MMMIN_LINE_W IDTH=0.2 5 MM

IMVP6_ DROOP

IMVP6_ LGATE1

IMVP6_ VID<6>

IMVP6_ BOOT1

IMVP_D PRSLPV R

=PPVCO RE_S0_ CPU_REG

IMVP6_ VSEN_P

IMVP6_ DFB

IMVP6_ DROOP

IMVP6_ VO

IMVP6_ OCSET

IMVP6_ VSUM

R7100

1 2

C7103

1 2

XW7104

12

C7115

1

2

XW7102

12

R7105

1 2

C7104

1 2

C7127

1

2

R7120

1 2

R7112

1 2

C7126

1

2

R7121

1 2

C7130

1

2

R7119

1 2

C7107

1

2

R7110

1

2

C7135

1

2

C7110

1

2

R7113

1

2

R7109

1

2

C7113

1

2

R7114

1

2

R7104

1

2

R7107

1

2

C7116

1

2

R7117

1 2

C7129

1

2

R7118

1

2

R7130

1

2

R7115

1

2

C7128

1

2

C7134

1

2

R7122

1 2

C7131

1

2

C7132

1

2

R7123

1 2

C7133

1

2

C7121

1

2

XW7100

1 2

R7101

1

2

R7106

1

2

L7100

1 2

L7101

1 2

C7196

1

2

C7106

1

2

C7114

1

2

R7111

1

2

C7105

1

2

R7116

1

2

C7109

1

2

R7131

1

2

R7108

1

2

R7127

1

2

R7197

1

2

XW7103

1 2

XW7101

1 2

R7126

1

2

R7198

1 2

R7199

1

2

U7100

48

36

26

47

10

17

45

46

16

11

12

21

3

24

23

32

30

25

6

8

33

29

1

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

Q7100

5

4

1 2 3

Q7103

5

4

1 2 3

Q7102

5

4

1 2 3

Q7101

5

4

1 2 3

C7117

1

2

C7153

1

2

C7155

1

2

C7154

1

2

R7160

1 2

C7108

1

2

C7152

1

2

C7156

1

2

C7157

1

2

13 12 11 10

87

8

87 87

87

62

8

62

8

62

8

6

62

42 62

62

87

8

62

OUT

Q1

Q2

SW

DRVH1

SKIPSEL

VBST1

GND

THRM_PAD

ENTRIP1

VFB1

VO1

DRVL1

LL1

EN0

VCLK

ENTRIP2

PGOOD

VO2

VFB2

DRVL2

LL2

DRVH2

VBST2

VREG5

VREG3

VREF

VIN

TONSEL

D

SG

D

SG

D

SG

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

PART NUMB ER

ALTERNATE FOR

PART NUMB ER

BOM OPTIO N

REF DES

COMMENTS:

One ma ster P GOOD fo r both 5V an d 3V3

Vout = 5.0V

(P3V3S5 _V02)

1. L7 260 ch anged f rom M8 8 MLB induct ors to 152S06 93.

2. Q7 220 ch anged t o 372S 0512. Q7225 change d to 3 76S051 1.

4. Ad ded R7 200, R7 220,R7 221, R 7260,R 7261, C 7201.

.

M99 di fferen ces fro m last sync on 11/ 01/07 t o M88 MLB:

3. U7 200 ch anged t o 353S 2087.

(P5VS5_ VO1)

6A max outpu t

(Q7220 limit )

f=365K Hz f=460K Hz

Vout = 3.3V

(L7260 limit )

5.5A m ax out put

X5R

25V

603-1

10%

1UF

IHLP2525CZ

4.7UH-5. 5A

CRITICAL

603-1

X5R

10% 25V

1UF

0.1UF

X7R

603-1

10% 50V

20%

6.3V

10UF

603

X5R

603-1

X7R

50V

10%

0.1UF

CRITICAL

6.3V

20%

CASE-D3L-SM 1

330UF

POLY-TANT

805

X5R

20%

10UF

10V

CRITICAL

20%

6.3V POLY-TANT

150UF

CASE-B2-SM

POLY-TANT

CASE-D2-SM

CRITICAL

20% 25V

22UF

603-1

10%

X5R

1UF

25V

CRITICAL

25V

22UF

20%

POLY-TANT

CASE-D2-SM

IHLP2525C Z-SM1

2.2UH-1 4A

CRITICAL

1/16W MF-LF 402

75K

1%

10UF

6.3V

20%

X5R 603

10UF

20%

X5R 603

6.3V

75K

402

1/16W

1%

MF-LF

68

PLACEMENT_N OTE=Place XW 7260 next t o L7260.

SM

PLACEMENT_N OTE=Place XW 7220 next t o L7220.

SM

NO STUFF

402

CERM

5% 25V

220PF

PLACEMENT_N OTE=Place XW 7200 next t o U7200 pin 15.

SM

FDMS960 0S

MLP

CRITICAL

QFN

TPS51125

402

0.22UF

CERM

10% 10V

PATH=I621

1/16W

402

MF-LF

1%

6.49K

10K

1/16W

402

MF-LF

1%

15K

PATH=I623

1/16W MF-LF 402

5%

10K

MF-LF 402

1/16W

1%

SSM6N1 5FEAPE

SOT563

SSM6N1 5FEAPE

SOT563

SSM6N1 5FEAPE

10K

1/16W MF-LF 402

5%

LFPAK-HF

CRITIC AL

RJK030 5DPB

CRITIC AL

RJK030 1DPB

LFPAK-HF

5%

1/16W

NO STUFF

10

402

MF-LF

100PF

5%

NO STUFF

50V

CERM

402

NO STUFF

10

5%

1/16W

402

MF-LF

NO STUFF

50V

CERM

402

100PF

5%

0

5%

MF-LF

1/16W

402

0

MF-LF

1/16W

5%

402

5V / 3.3V Power Supply

SYNC_MAS TER=M99_ MLB

63 9 6

A.0.0

051-7546

SYNC_DAT E=01/09/ 2008

376S0668

FET FDM8678S altern ate to Si7108

376S0651

ALL

152S0693152S0778

4.7uH inductor Cynt ec a;ternate to MagLayers

ALL

376S0652

ALL

FET FDM8676 alterna te to Si7110

376S0669

PP5V_S5 _REG_XW

=P5VS3_E N

P5VS3_EN _L

P3V3S5_E N_L

=PP3V42_ G3H_PWRC TL

P5VS5_VF B

P5V3V3_P GOOD

P5VS5_RC

PP3V3_S5_ REG_XW

P3V3S5_R C

P5VP3V3_ VREF

P5VP3V3_ VREG3

P5VS5_VB ST_R

P5VP3V3_ VREG5

P3V3S5_V BST_R

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.6 mm

GATE_NODE=T RUE

P5VS5_DR VL

P3V3S5_L L

SWITCH_NODE =TRUE

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.6 mm

=PPVIN _S5_P5V P3V3

P5VS5_DR VH

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm

GATE_NODE=T RUE

P5VS5_EN TRIP

=PP5V_S3 _REG

MIN_NECK_WI DTH=0.2 mm

P5VS5_LL

MIN_LINE_WI DTH=0.6 mm

SWITCH_NODE =TRUE

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.6 mm

P5VS5_VB ST

P3V3S5_E NTRIP

MIN_NECK_WI DTH=0.2 mm

P3V3S5_V BST

MIN_LINE_WI DTH=0.6 mm

P3V3S5_V FB

=PP3V3_S 5_REG

P3V3S5_D RVL

GATE_NODE=T RUE

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.6 mm

MIN_NECK_WI DTH=0.2 mm

P3V3S5_D RVH

GATE_NODE=T RUE

MIN_LINE_WI DTH=0.6 mm

VOLTAGE=0V

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm

GND_P5VP 3V3_SGND

C7200

1

2

L7260

1 2

C7241

1

2

C7264

1

2

C7290

1

2

C7224

1

2

C7252

1

2

C7250

1

2

C7292

1

2

C7240

1

2

C7281

1

2

C7280

1

2

L7220

1 2

R7200

1

2

C7203

1

2

C7205

1

2

R7206

1

2

XW7260

1

2

XW7220

1

2

C7208

1

2

XW7200

1 2

Q7260

2349

1

8

56

7

10

U7201

21 10

19 12

13

1 6

15

20 11

23

14

25

4

22 9

18

2 5

16

24 7

3

8

17

C7201

1

2

R7260

1

2

R7261

1

2

R7220

1

2

R7221

1

2

Q7211

3

5

4

Q7210

6

2

1

Q7210

3

5

4

R7210

1

2

Q7220

5

4

123

Q7225

5

4

123

R7222

1

2

C7222

1

2

R7262

1

2

C7262

1

2

R7264

12

R7224

12

68

8

8 8

MODE

VDDQSNS

COMP

NC0

NC1

VTTSNS

VTT

VTTREF

PGOOD

S3

S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 O F 2)

IN

OUT

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

(DDRRE G_DRVH )

f = 40 0 kHz

Vout = 1.50V or 1.8 0V

(DDRRE G_FB)

(DDRRE G_LL)

Vout = VDDQS NS/2

(DDRRE G_VDDQ SNS)

10mA m ax loa d

VDDQ PGO OD

VDDQ/VTT REF Enab le

<Rb>

(DDRRE G_CSGN D)

(Q7335 limit )

15A ma x outp ut

<Ra>

Vout = 0.75V * (1 + Ra / Rb)

(DDRRE G_VBST )

VTT Enab le

(DDRRE G_DRVL )

Vout = VTTRE F

0.1UF

10%

X7R

50V

603-1

402

1% 1/16W

15.0K

MF-LF

1/16W MF-LF

1%

402

15.0K

603-1

10%

1UF

X5R

25V

50V

5%

100PF

CERM

402

NO STU FF

CRITIC AL

TPS511 16

QFN

10%

X5R

10V

1UF

402

MF-LF

1/16W

5%

4.7

402

6.3V

20%

22UF

CRITIC AL

X5R-CERM 603

X5R-CERM

6.3V

20%

603

22UF

CRITIC AL

SM

PLACEMEN T_NOTE=P lace nex t to Q73 35

SM

0.033U F

10%

X5R

16V

402

9

69

603

4.7UF

CERM

20%

6.3V

68

MF-LF

402

1/16W

1%

10K

68

22UF

20%

CRITIC AL

25V

POLY-TANT

CASE-D2-S M

POLY-TANT

20%

CRITIC AL

25V

22UF

CASE-D2-S M

CRITIC AL

RJK030 5DPB

LFPAK-HF

1.0UH- 13A-5. 6MOHM

CRITIC AL

PCMB065T- SM

RJK030 1DPB

CRITIC AL

LFPAK-HF

SM

PLACEMEN T_NOTE=P lace nex t to C73 45

20%

603

6.3V X5R

10UF

SM

2.5V

20%

330UF

CASE-C2- SM

POLY-TAN T

CRITIC AL

2.5V

CASE-C2- SM

20%

330UF

POLY-TAN T

6.3V

20%

X5R

10UF

603

10% 25V

1000PF

402

X7R

1000PF

10% 25V

402

X7R

SYNC_DA TE=12/ 13/2007

SYNC_MA STER=M 99_MLB

A.0.0

9664

051-7546

1.5V DDR3 Supply

=PPDDR _S3_RE G

MIN_NECK _WIDTH=0 .2 mm

MIN_LINE _WIDTH=0 .6 mm

SWITCH_N ODE=TRUE

DDRREG _LL

VOLTAGE= 5V

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .2 mm

PP5V_S 3_DDRR EG_V5FI LT

=PPVTT _S3_DD R_BUF

MIN_LINE _WIDTH=0 .2 mm MIN_NECK _WIDTH=0 .2 mm

DDRREG _VDDQS NS

=PPVTT _S0_DD R_LDO

MIN_LINE _WIDTH=2 mm

MIN_NECK _WIDTH=0 .2 mm

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .2 mm

DDRREG _DRVL

GATE_NOD E=TRUE

=DDRRE G_EN

=DDRVT T_EN

DDRREG _PGOOD

DDRREG _CS

MIN_LINE _WIDTH=0 .2 mm MIN_NECK _WIDTH=0 .2 mm

DDRREG _CSGND

DDRREG _FB

GATE_NOD E=TRUE

DDRREG _DRVH

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .2 mm

DDRREG _VBST

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .2 mm

=PP5V_ S3_DDR REG

MIN_NECK _WIDTH=0 .2 mm

MIN_LINE _WIDTH=0 .6 mm

VOLTAGE= 0V

GND_DD RREG_S GND

DDRREG _VTTSN S

=PPVIN _S0_DD RREG_LD O

=PPVIN _S3_DD RREG

C7325

1 2

R7320

1

2

R7321

1

2

C7332

1

2

C7320

1

2

U7300

6

16

17

21

19

3

20

4

7

12

18

13

10

11

25

14

15

22

9

8

23

24

1

5

2

C7305

1

2

R7305

1 2

C7361

1

2

C7360

1

2

XW7360

1 2

XW7335

1 2

C7350

1

2

C7300

1

2

R7310

1

2

C7330

1

2

C7331

1

2

Q7330

5

4

1 2 3

L7330

1 2

Q7335

5

4

1 2 3

XW7345

1

2

C7355

1

2

XW7300

1

2

C7341

1

2

C7340

1

2

C7345

1

2

C7333

1

2

C7346

1

2

27 8 8

8

IN

OUT

IN

S

D

G

S

D

G

BOOT1

UGATE1

PHASE1

LGATE1

OUT1

VCC

REFIN2

ILIM2

OUT2

SKIP*

POK2

EN2

UGATE2

PHASE2

BOOT2

LGATE2

PGND

GND

SECFB

PVCC

EN1

ILIM1

FB1

BYP

LDOREFIN

LDO

VIN

VREF3

EN_LDO

TON

REF

POK1

THRM_PAD

D

SG

D

SG

D

SG

OUT

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

<Ra>

(P5VRT S0_LGA TE)

(P5VRT S0_BOO T)

(P5VRT S0_PHA SE)

Vout = 0.7V * (1 + Ra / Rb)

Req = Rb || Rc || Rd || Re

Vout = 2.0V * Req / (Ra + Re q)

Max lo ad 50u A

MCP79 Rev A01 requires higher core & analog voltage

001 +1.159V +0.994V +1.00V

011 +1.049V +0.885V +0.90V

110 +0.913V +0.752V +0.75V 111 +0.876V +0.719V +0.70V

(MCPCO RES0_U GATE)

from PVCC t o VCC)

(Inter nal 10 -ohm pa th

(=P5V_ RTS0_E N)

Max lo ad 100 mA

(MCPCO RES0_L GATE)

<Ra>

Vout = 5.03V

5A max output

f = 400 kHz

(=PP5V _RTS0_ REG)

(P5VRT S0_UGA TE)

(SGND)

(=PPMC PCORE_ S0_REG)

010 +1.101V +0.937V +0.95V

000 +1.224V +1.060V +1.05V

VID<2:0> Voltage Voltage MCP Target

100 +0.995V +0.830V +0.85V 101 +0.952V +0.789V +0.80V

Rev A01 Production

<Rb>

(Q7510 limit?)

<Rc>

(MCPCO RES0_P HASE)

Max Current: 25A? (Q7560 Limit) f = 300 kHz

Vout = See below

68

100PF

402

CERM

5%

50V

NO STU FF

CRITIC AL

CASE-D2- SM

20% 25V

POLY-TAN T

22UF

10%

1UF

25V

603-1

X5R

0.22UF

10% 16V

603

X7R

LFPAK-HF

CRITIC AL

RJK030 5DPB

CRITIC AL

LFPAK-HF

RJK032 8DPB

10UF

X5R

20% 4V

603

68

21

16V

10%

CERM

0.01UF

402

MPL104-SM

0.6UH- 30A-1. 5MOHM

CRITIC AL

330UF

20%

2.5V

CRITIC AL

POLY-TAN T CASE-C2- SM

1000PF

X7R

25V

10%

402

10% 25V X7R

1000PF

SI7108DN

CRITICAL

PWRPK-1212-8 -HF

CRITICAL

20%

330UF

6.3V

CASE-D3L-SM 1

POLY-TANT

20%

10UF

10V X5R 805

2.2UH-1 4A

CRITICAL

IHLP2525C Z-SM1

PWRPK-1212-8 -HF

CRITICAL

SI7110DN

1/16W

4.7

402

MF-LF

5%

1UF

10V

402-1

10%

X5R

1%

1206

MF

1W

0.001

SM

QFN

ISL623 6

CRITIC AL

20% 10V CERM 402

0.1UF

402

1%

100K

MF-LF

1/16W

402

MCP_PR OD

54.9K

1/16W

MF

0.1%

MCP_PR OD

402

1/16W

48.7K

MF

0.1%

CERM-X7R

603

10V

0.22UF

5%

10%

805

25V X5R

10UF

10V

1UF

10%

X5R

402-1

X5R

10V

10%

402-1

1UF

20%

4.7UF

6.3V

402

X5R-CERM

25V

10%

603-1

X5R

1UF

CASE-C2- SM

POLY-TAN T

330UF

20%

2.5V

CRITIC AL

4V

10UF

20%

X5R 603

100K

1/16W MF-LF 402

1%

CASE-D2- SM

POLY-TAN T

25V

CRITIC AL

22UF

20%

SOT563

SSM6N1 5FEAPE

402

MCP_PR OD

MF

0.1% 1/16W

475K

SSM6N1 5FEAPE

SOT563

402

MCP_PR OD

MF

237K

0.1% 1/16W

SOT563

SSM6N1 5FEAPE

MCP_PR OD

402

1/16W MF

110K

0.1%

402

1/16W

5%

0

MF-LF

402

61.9K

1%

MF-LF

NO STU FF

1/16W

PLACEMEN T_NOTE=P lace nex t to C75 16

SM

68

SYNC_DA TE=01/ 08/2008

65 9 6

A.0.0

051-7546

SYNC_MA STER=M 99_MLB

1.05V / MCP Core Regulator

114S04 11

RES,MTL F ILM,1/16W, 100K,1,04 02,SMD,LF

1

R7582

MCP_A01 Q

R7571

MCP_A01 Q

1

RES,MTL F ILM,1/16W, 84.5K,1,0 402,SMD,LF

114S04 04

114S04 22

1

R7582

MCP_A01

RES,MTL F ILM,1/16W, 130K,1,04 02,SMD,LF

R7580

1

MCP_A01

RES,MTL F ILM,1/16W, 523K,1,04 02,SMD,LF

114S04 82

R7580

MCP_A01 Q

114S04 58

1

RES,MTL F ILM,1/16W, 301K,1,04 02,SMD,LF

RES,MTL F ILM,1/16W, 48.7K,1,0 402,SMD,LF

114S03 82

R7570

1

MCP_A01

MCP_A01 Q

R7581

1

RES,MTL F ILM,1/16W, 237K,1,04 02,SMD,LF

114S04 47

114S04 53

1

R7581

MCP_A01

RES,MTL F ILM,1/16W, 267K,1,04 02,SMD,LF

MCP_A01 Q

114S03 73

1

R7570

RES,MTL F ILM,1/16W, 40.2K,1,0 402,SMD,LF

R7571

1

MCP_A01

RES,MTL F ILM,1/16W, 76.8K,1,0 402,SMD,LF

114S04 00

P5V_RT S0_FB

=PP5V_ RT_REG

P5VRTS 0_BOOT

MIN_LINE _WIDTH=0 .6MM MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM MIN_NECK _WIDTH=0 .2MM SWITCH_N ODE=TRUE

P5VRTS 0_PHAS E

P5VRTS 0_VSNS

=P5V_R TS0_EN

P5V_RT S0_ILI M

MIN_NECK _WIDTH=0 .2 MM

GND_MC PREG_S GND

VOLTAGE= 0V

MIN_LINE _WIDTH=0 .5 MM

P5V_RT S0_PGO OD =MCPCO RES0_E N

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

GATE_NOD E=TRUE

P5VRTS 0_UGAT E

PVIN_P 5VRTS0 _MCPCOR E

MCPCOR ES0_PG OOD

MCPCOR ES0_UG ATE

GATE_NOD E=TRUE

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .5 MM

VOLTAGE= 5V

PP5V_S 0_MCPR EG_LDO

MCP_VI D<0>

MCP_VI D<2>

=PPMCP CORE_S 0_REG

MCPCOR ES0_RE FIN MCPCOR ES0_IL IM

=PPVIN _S0_P5 VRTS0_M CPCORE

VOLTAGE= 2V

PP2V_S 0_MCPR EG_REF

P5VRTS 0_LGAT E

MIN_NECK _WIDTH=0 .2MM GATE_NOD E=TRUE

MIN_LINE _WIDTH=0 .6MM

PP5V_S 0_MCPR EG_VCC

MIN_NECK _WIDTH=0 .2 MM VOLTAGE= 5V

MIN_LINE _WIDTH=0 .5 MM

PP3V3_ S0_MCP _VREF

MCP_VI D1_L

MCP_VI D<1>

MCP_VI D2_LMCP_VI D0_L

MCPCOR ES0_LG ATE

GATE_NOD E=TRUE

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .5 MM

MCPCOR ES0_PH ASE

MIN_NECK _WIDTH=0 .2 MM SWITCH_N ODE=TRUE

MIN_LINE _WIDTH=0 .5 MM

MCPCORE ISNS_N

MCPCORE ISNS_P

PPMCPCORE _ISENSE

MCPCOR ES0_BO OT

XW7500

1 2

U7500

17 24

9

14 27

4

11

21

12 31

7

8

18 23

10 30

22

16 25

13

28

19

1

32

20

29

33

2

15 26

365

C7530

1

2

R7564

1

2

R7571

1

2

R7570

1

2

C7564

1

2

C7500

1

2

C7501

1

2

C7503

1

2

C7502

1

2

C7561

1

2

C7565

1

2

C7566

1

2

R7514

1

2

C7560

1

2

Q7580

3

5

4

R7580

1

2

Q7580

6

2

1

R7581

1

2

Q7582

3

5

4

R7582

1

2

R7521

1

2

R7520

1

2

XW7516

1

2

C7520

1

2

C7510

1

2

C7511

1

2

C7514

1

2

Q7560

5

4

1 2 3

Q7565

5

4

1 2 3

C7567

1

2

C7590

1

2

L7560

1 2

C7568

1

2

C7563

1

2

C7569

1

2

Q7511

5

4

123

C7515

1

2

C7516

1

2

L7510

1 2

Q7510

5

4

123

R7500

1

2

C7504

1

2

R5425

1 2

3 4

95

8

47

Q1

Q2

SW

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 O F 2)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

<Rb>

Vout = 0.75V * (1 + Ra / Rb)

Vout = 1.052V 6A max output

(=PPCP UVTT_S 0_REG)

(Q7660 limit?)

f = 360 kHz

1. Ti ed THE RMAL_PA D to P GND. G ND and THERMA L_PAD discon nected .

M99 di fferen ces fro m last sync on 12/ 03/07 t o T18 MLB:

(CPUVT TS0_VF B)

(GND)

<Ra>

(=PPCP UVTT_S 0_REG)

X5R

6.3V

603

20%

10UF

25V

10%

1UF

X5R 603-1

8.06K

402

1%

MF-LF

1/16W

1%

MF-LF 402

20.0K

402

CERM

5%

NO STU FF

50V

100PF

B2-SM

2.0V

POLY-TANT

330UF

20%

CRITIC AL

IHLP2525 CZ-SM1

2.2UH- 14A

CRITIC AL

50V

10%

603-1

X7R

0.1UF

25V

22UF

CRITIC AL

POLY-TAN T

CASE-D2- SM

20%

MLP

FDMS9600S

CRITIC AL

SM

PLACEMEN T_NOTE=P lace XW7 665 next to C766 5

200

1%

MF-LF

402

1/16W

SM

1%

MF-LF 402

6.34K

1/16W

68

QFN

TPS511 17RGY_ QFN14

CRITIC AL

X5R 603

10%

2.2UF

16V

X5R

1UF

10% 10V

402

MF-LF

1%

402

1/16W

165K

1%

0.002

MF

1/4W

1206

CPU VTT Power Supply

66 9 6

051-7546

SYNC_MA STER=M 99_MLB

SYNC_DA TE=12/ 14/2007

A.0.0

CPUVTT S0_VFB

VOLTAGE= 0V

GND_CP UVTTS0 _SGND

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .2 mm

CPUVTT S0_TRI P

MIN_LINE _WIDTH=0 .6MM MIN_NECK _WIDTH=0 .2MM

GATE_NOD E=TRUE

CPUVTT S0_DRV H

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

CPUVTT S0_VBS T

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

CPUVTT S0_LL

SWITCH_N ODE=TRUE

PPCPUFS B_ISNS

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

CPUVTT S0_DRV L

GATE_NOD E=TRUE

1V05CP U_P

=PPCPU VTT_S0 _REG

CPUVTT S0_VSN S

1V05CP U_N

=PPVIN _S0_CP UVTTS0

=PP5V_ S0_CPU VTTS0

CPUVTT S0_TON=CPUVT TS0_EN

MIN_NECK _WIDTH=0 .2 mm VOLTAGE= 5V

MIN_LINE _WIDTH=0 .6 mm

PP5V_S 0_CPUV TTS0_V5 FILT

CPUVTT S0_PGO OD

C7665

1

2

C7695

1

2

R7670

1

2

R7671

1

2

C7670

1

2

C7660

1

2

L7660

1 2

C7680

1

2

C7690

1

2

Q7660

2349

1

8

56

7

10

XW7665

1

2

R7601

1 2

XW7600

1 2

R7685

1

2

U7600

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

C7601

1

2

C7600

1

2

R7679

1

2

R5435

1 2

3 4

95

47

8

47

8

VIN

SW1

SW2

GND

RUN2

RUN1

VFB1

VFB2

PAD

THRML

VI

SW

EN

FB

GND

OUT

IN

S

D

G

S

D

G

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD

COMP

FSET

ISEN

FB

VO

BOOT

VIN

THRML

PAD

VCC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

MCP 1.05V AUXC Supply

1.8V S0 Switcher / 1.0VFW SWITCHER

S5 pow er req uired f or out put di scharg e featu re

<Rb>

300mA max output

f = 2.25 MHz

0.3A max output

(L7770 limit)

5A max output

INPUT RAIL IS 3.3V S0

(Switcher limit)

Vout = 1.001V

f = 1.6 MHz

<Rb>

<Ra>

Vout = 1.816V

(Switcher limit)

MAX CU RRENT = 300MA

1.8V S0 Switcher

(P1V05 S5_VFB )

Vout = 1.052V

f = 400 kHz

(=PP1V 05_S5_ REG)

<Ra>

(GND)

Vout = 0.6V * (1 + Ra/ Rb)

<Ra>

<Rb>

Vout = 0.6V * (1 + Ra / Rb)

CRITIC AL

LTC354 7

DFN-HF

CERM

402

5%

10PF

50V

10uF

X5R 603

20%

6.3V

CRITIC AL

TPS6220 2

SOT23-5

10UH-0 .55A-3 30MOHM

PCAA031B- SM

CRITIC AL

10uF

6.3V X5R

20%

603

1%

MF-LF 402

1/16W

38.3K

68

MF-LF

1/16W

402

5%

4.7

SM

16V

603

X5R

2.2UF

10%

16V

10%

X5R 603

2.2UF

0.1UF

10% 25V X5R 402

2.43K

1%

1/16W

402

MF-LF

10%

1UF

X5R

25V

603-1

402

1/16W

1%

MF-LF

4.42K

402

1/16W

1%

MF-LF

3.74K

PLACEMEN T_NOTE=P lace XW7 775 next to C777 5

SM

B2-SM

2.0V

POLY-TANT

330UF

20%

CRITIC AL

1.5UH- 6.0A

PCMB053T

402

4V

4.7UF

20%

X5R

CRITIC AL

SI7110 DN

PWRPK-121 2-8-HF

CRITIC AL

SI7108 DN

QFN

ISL6269

MF-LF

1/16W

1%

49.9K

402

470PF

50V

10%

402

CERM

5%

402

CERM

50V

33PF

10%

402

CERM

16V

0.01UF

X5R

10% 25V

1UF

603-1

MF-LF 402

1/16W

1%

280K

10PF

CERM

5%

50V

402

187K

1/16W

1%

MF-LF 402

CRITIC AL

2.2UH

CPL2512- SM

4.7UF

402

20% 4V X5R

68

20%

6.3V CERM

402-LF

2.2UF

MF-LF

280K

1%

402

1/16W

CRITIC AL

2.2UH

CPL2512-S M

20%

X5R

4V

402

4.7UF

562K

MF-LF

1%

402

1/16W

Misc Power Supplies

SYNC_MAS TER=M99_ MLB

SYNC_DAT E=12/14/ 2007

051-7546

A.0.0

9667

=PP3V3 _S3_P1 V8S0

P1V0FW _VFB

=P1V8S 0_EN

=PP3V3 _FW_P1 V0FW

P1V05_ S5_PGO OD

=PP1V0 5_S5_M CP

P1V05S 5_COMP _R

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

P1V05S 5_VBST

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

SWITCH_N ODE=TRUE

P1V05S 5_LL

=P1V8F B_EN

P1V8S0 _LX

MIN_NECK _WIDTH=0 .2 mm SWITCH_N ODE=TRUE

MIN_LINE _WIDTH=0 .4 mm

P1V0FW _SW

SWITCH_N ODE=TRUE

MIN_LINE _WIDTH=0 .5 mm MIN_NECK _WIDTH=0 .25 mm

P1V8GP U_SW

=PP1V0 _FW_RE G

=PP1V8_GPUIFPX_REG

=PP3V3 _GPU_P 1V8S0

=PP1V8 _S0_RE G

P1V8S0 _VFB

P1V05S 5_VSNS

=P1V05 S5_EN

=PPVIN _S0_P1 V05S5

VOLTAGE= 5V

MIN_NECK _WIDTH=0 .2 mm

MIN_LINE _WIDTH=0 .6 mm

P5V_P1 V05S5

P5V_P1 V05S5_ V5FILT

=PPVIN _S0_P1 V05S5

P1V05_ S5_COM P

P1V05_ S5_FSE T

MIN_NECK _WIDTH=0 .2 mm

MIN_LINE _WIDTH=0 .6 mm

VOLTAGE= 0V

GND_P1 V05S5_ SGND

P1V05S 5_VFB

GATE_NOD E=TRUE

P1V05S 5_DRVL

MIN_LINE _WIDTH=0 .6MM MIN_NECK _WIDTH=0 .2MM

P1V05S 5_ISEN

P1V05S 5_DRVH

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

GATE_NOD E=TRUE

R7783

1

2

C7782

1

2

R7782

1

2

L7780

1 2

C7785

1

2

C7700

1

2

R7701

1

2

L7700

1 2

C7705

1

2

R7700

1

2

U7700

5

2

7

4

6

9

1

8

3

C7701

1

2

C7760

1

2

U7760

3

4

2

5

1

L7760

1 2

C7762

1

2

R7752

1

2

R7751

1 2

XW7750

1

2

C7751

1

2

C7750

1

2

C7770

1

2

R7779

1

2

C7775

1

2

R7781

1

2

R7780

1

2

XW7775

1

2

C7771

1

2

L7770

1 2

C7776

1

2

Q7770

5

4

1 2 3

Q7771

5

4

1 2 3

U7750

13

5

4

6

3

7

9

11

10

16

15

12

17

14

2

1

8

R7753

1

2

C7754

1

2

C7755

1

2

C7753

1

2

C7752

1

2

83 82

67

8

68

8

OUT

IN

OUT

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

OUT

IN

D

G S

IN

OUT

IN

OUT

IN

OUT

SENSE

CT

VDD

GND

RESET*

MR*

ADJ1

SEL

ADJ2

REF

VCC

TMR

GND

THRM_PAD

RST*

OUT

Y

B

A

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

EXT GPU PWRGD Pullup

SMC_PM_G 2_ENABLE

Sleep (S3)

1.1V GPU ENABLE Graphic MEM ENABLE

BOMOPTIO N: EG

Other S0 RAILS

IG hig h

EG PM_ ALL_GPU_PG OOD

PM_ALL_GF X_PGOOD

(PM_SLP_ S3_L)

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

3.3V 1,05V S5 ENABLE

Run (S0)

G96 GPU requires rails t o come

State

Soft-Off (S5)

Battery Off (G3H ot)

1

0

1

0

1

PM_SLP_S 4_L

0 0

0

1

PM_SLP_S 3_L

0

place X W0402 if needed to sav e trace space f or pin 7,8

3.3V,5V S3 ENABLE

TPS3808 M R* HAS INT ERNAL PUL LUP

1.5V 1.0 5V COMPA RED TO 0 .5V

(PM_S4_S TATE_L)

4) GDDR3 1.8V

up in th e follow ing orde r:

TIE TMR TO GND TRST = 2 00MS

S5 rail PWRGD

NC

Unused PGOOD signal

S0 ENABLE

LTC2909 THRESHOL D IS 3.1 36V

3) GPUVc ore

GPUVCORE ENABLE

1) 1.1V

2) GPU_3 .3V

82 83

402

CERM

16V

20%

0.022UF

NO STU FF

PLACEMENT_NOTE =near U9500

5%

PLACEMENT_NOTE =near U9500

402

MF-LF

EG_PWR SEQ_HW

0

1/16W

EG_PWR SEQ_HW

10K

5%

1/16W

MF-LF

402

EG_PWR SEQ_HW

MF-LF

402

100K

5%

1/16W

83

1/16W

100K

MF-LF

5%

402

1/16W

10K

MF-LF

5%

402

78 83

10%

0.01UF

CERM

PLACEMENT_NOTE =near U8900

16V

402

1/16W

PLACEMENT_NOTE =near U8900

MF-LF

5%

EG_PWR SEQ_HW

0

EG_PWR SEQ_HW

100K

5%

402

MF-LF

1/16W

69

64

100K

5%

MF-LF

402

PLACEMENT_NOTE =near U1400

1/16W

21 40 42 43

67 82 83

NO STUF F

PLACEMENT_NOTE =near U7880

5%

0

402

MF-LF

1/16W

65

EG_PWR SEQ_HW

SOT563

SSM6N15FE APE

EG_PWR SEQ_HW

SOT563

SSM6N15FE APE

SOT563

EG_PWR SEQ_HW

SSM6N15FE APE

SOT563

EG_PWR SEQ_HW

SSM6N15FE APE

63

67

66

10%

0.47UF

402

CERM-X5R

PLACEMENT_NOTE =near U7750

6.3V

100K

402

5%

MF-LF

1/16W

CERM

10V

402

10%

0.068UF

NO STUF F

PLACEMENT_NOTE =near U7201

5.1K

PLACEMENT_NOTE =near U7750

1/16W

402

MF-LF

5%

SOD-VESM-HF

SSM3K15FV

MF-LF

PLACEMENT_NOTE =near U4900

402

100K

1/16W

5%

42

65

69

46

69

65

69

66

67

402

5%

MF-LF

1/16W

PLACEMENT_NOTE =nearU7951

0

65

63

NO STUF F

PLACEMENT_NOTE =nearU7951

402

CERM-X5R

6.3V

10%

0.47UF

5%

1/16W

10K

MF-LF 402

PLACEMENT_NOTE =nearU7700

1/16W

5%

402

PLACEMENT_NOTE =nearQ7971

MF-LF

0

PLACEMENT_NOTE =nearU7600

5%

MF-LF 402

1/16W

33K

402

5%

PLACEMENT_NOTE =nearU7500

1/16W MF-LF

22K

MF-LF

1/16W

5%

100K

402

MF-LF

PLACEMENT_NOTE =near U1400

1/16W

402

5%

100K

7

21 34 37 42 44 81 83

PLACEMENT_NOTE =nearU7700

402

10%

6.3V

0.47UF

CERM-X5R

6.3V

10%

402

CERM-X5R

0.47UF

NO STUF F

PLACEMENT_NOTE =nearQ7971

PLACEMENT_NOTE =nearQ7600

0.47UF

10%

CERM-X5R

6.3V

402

CERM-X5R

PLACEMENT_NOTE =nearU7500

10%

402

6.3V

0.47UF

63

PLACEMENT_NOTE =near U7300

5% 1/16W

5.1K

402

MF-LF

PLACEMENT_NOTE =near U7300

0.47UF

CERM-X5R 402

10%

6.3V

402

1/16W

5%

0

MF-LF

PLACEMENT_NOTE =near U7201

0.47UF

6.3V

402

CERM-X5R

10%

NO STUF F

MF-LF

1/16W

402

5%

PLACEMENT_NOTE =near U7880

0

100K

402

MF-LF

1/16W

5%

0.1uF

20% 10V

CERM

402

SOT23-6

TPS3808G3 3DBVRG4

0.001UF

20% 50V

CERM

402

20%

402

CERM

10V

0.1uF

LTC290 9

DFN

EG_PWR SEQ_HW

402

5%

100K

PLACEMENT_NOTE =near U7972

MF-LF

1/16W

9

68

69 83

402

5%

1/16W

10K

MF-LF

PLACEMENT_NOTE =nearU9900

5.1K

5%

MF-LF 402

PLACEMENT_NOTE =nearU9900

1/16W

10%

6.3V

402

CERM-X5R

0.47UF

PLACEMENT_NOTE =nearU9900

CERM-X5R 402

10%

6.3V

0.47UF

PLACEMENT_NOTE =nearU9900

86

EG_PWR SEQ_HW

0

5%

1/16W

402

MF-LF

402

5%

100

1/16W MF-LF

SOT665

TC7SZ08A FEAPE

26 42

402

16V

20%

0.022UF

NO STU FF

CERM

PLACEMENT_NOTE =near U9500

CERM 402

0.1UF

10V

20%

PLACEMENT_NOTE =near U9500

402

MF-LF

1/16W

5%

EG_PWR SEQ_HW

0

EG_PWR SEQ_HW

5%

1/16W

402

MF-LF

100K

SYNC_D ATE=05 /12/200 8

9668

A.0.0

051-7546

SYNC_M ASTER= PWRSQNC

Power Control

MAKE_BASE =TRUE

GPU_S0_ EN_L

GPUVCOR E_EN_RC_ L

PM_ALL_ GPU_PGOO D

MAKE_BASE =TRUE

P1V8FB_ PGOOD

=PP3V3_ S0_PWRCT L

P3V3GPU _EN

P1V1GPU _PGOOD

=PP3V3_S 5_PWRCTL

EXTGPU_ PWR_EN

P1V8_S0 GPU_EN

MAKE_BASE=TR UE

P1V8_S0 GPU_EN_R C

MAKE_BASE =TRUE

P1V1_GP U_EN

SMC_PM_G 2_EN

MAKE_BASE =TRUE

P1V8S0_ EN

ALL_GFX _PGOOD_R

MAKE_BASE =TRUE

DDRREG_ EN

P5VS3_EN

MAKE_BASE =TRUE

ALL_SYS_ PWRGD

=PP3V3_S 5_PWRCTL

P5V_RTS 0_PGOOD

P5V3V3_ PGOOD

=PP3V3_S 0_PWRCTL

=MCPCOR ES0_EN

=CPUVTTS 0_EN

=P1V2S0 _EN

=PBUSVSE NS_EN

=P3V3S0_ EN

=P5V_RTS 0_EN

=PP3V3_ S0_PWRCT L

=PP3V3_S 5_PWRCTL

MAKE_BASE=T RUE

PM_G2_P1 V05S5_EN

GPUVCOR E_EN_RC

PM_ALL_ GPU_PGOO D

P3V3S5_E N_L

S0PGOOD_ PWROK

=PP3V42_ G3H_PWRC TL

=PP3V3_G PU_PWRCT L

CT

RSMRST_ PWRGD

P1V05_S 5_PGOOD

=P3V3S3_ EN

=P1V05S5 _EN

=DDRREG _EN

=P5VS3_E N

GPUVCOR E_EN_RC_ L

PM_SLP_S 4_L

MAKE_BASE=T RUE

S0PGOOD_ PWROK

=P1V8FB _EN

P1V8S0_ PGOOD

MCPCORE S0_PGOOD

=PP3V3_S 0_VMON

=PP1V5_S 0_VMON

=P1V1GPU _EN

PM_SLP_ S3_L

P1V1_GPU _EN_RC

=MCPDDR _EN

P2V5S0_ EN

MAKE_BASE =TRUE

P1V2_S0 _EN

MCPDDR_ EN

MAKE_BASE =TRUE

CPUVTTS 0_EN

MAKE_BASE =TRUE

=PP3V42_ G3H_PWRC TL

CPUVTTS 0_PGOOD

DDRREG_ PGOOD

TP_DDRR EG_PGOOD

MAKE_BASE =TRUE

S0_PWR_P GOOD

MAKE_BASE=T RUE

=PP1V05_ S0_VMON

=P2V5S0 _EN

P1V05S0_ EN

=P1V8S0 _EN

MAKE_BASE =TRUE

PM_SLP_ S3_L_R

MAKE_BASE =TRUE

MCPCORE S0_EN

=PP3V3_ GPU_PWRC TL

GPUVCOR E_PGOOD

=GPUVCO RE_EN

MAKE_BASE =TRUE

GPUVCOR E_EN

=PP3V3_ S0_PWRCT L

C7889

1

2

R7892

1

2

R7891

1 2

R7890

1

2

C7869

1

2

R7869

1 2

R7868

1 2

C7850

1

2

R7852

12

R7851

1 2

R7850

1 2

R7853

1

2

C7861

1

2

R7864

1 2

R7863

1 2

R7810

1

2

Q7850

6

2

1

Q7850

3

5

4

Q7861

6

2

1

Q7861

3

5

4

C7801

1

2

R7802

12

C7802

1

2

R7801

12

Q7800

3

1

2

R7858

1

2

R7884

1

2

C7884

1

2

R7883

1

2

R7882

1

2

R7881

1

2

R7880

1

2

R7879

1

2

C7883

1

2

C7882

1

2

C7881

1

2

C7880

1

2

R7811

1

2

C7810

1

2

R7812

1

2

C7812

1

2

R7894

1

2

R7840

1

2

C7840

1

2

U7840

4

2

3

15

6

C7841

1

2

C7870

1

2

U7870

8 7

5

6

4

1

9

2

3

R7889

1

2

R7885

1

2

R7886

1

2

C7885

1

2

C7886

1

2

R7888

1

2

R7878

1 2

U7880

2

1

3

5

4

68

63

68

63

68

82

8

82

8

9

68

8

42

67

68

8

64

8

78

8

IN

D

SG

D

SG

IN

D

SG

D

SG

IN

D

SG

D

SG

D

SG

D

SG

IN

S

D

G

D

G S

SGD

S

D

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

3.3V S3 FET

0.087 A (EDP )

CHANNE L

2.1 A (EDP)

1.5V S0 FET

RDS(ON )

1.5V S0 FET

26 mOh m @4.5 V

In ord er to support unpow ering rail, hardwar e must guara ntee M EM_CKE signal s are low before rail is turn ed off , and remain s low u ntil a fter r ail tu rns ba ck on o r DIMM s will e xit se lf-refr esh pr ematur ely. M EM_VTT_ EN out put fr om MCP 79 use d to en able c lamp on VTT rail, which pulls all CK E sign als low throu gh VTT termi nation resist ors.

MCP79 DDR pa d leaka ge is high e nough that nV idia r ecomme nds un poweri ng duri ng sle ep.

MCP79 DDR FETs

81mW m ax pow er

90mA m ax loa d @ 0.9 V

LOADIN G

RDS(ON )

P-TYPE

3.3V S0 FET

RDS(ON )

CHANNE L

LOADIN G

EG

BOM_OP TION

RDS(ON )

CHANNE L

MOSFET

LOADIN G

1.1 A (EDP)

MOSFET

FDC638 P

P-TYPE

MOSFET

3.3V S0 FET

2.9 A (EDP)

26 mOh m @4.5 V

P-TYPE

FDC606 P

3.3V GPU FET

FDC606 P

APN 37 6S0651

LOADIN G

CHANNE L

MOSFET

N-TYPE

SI7108 DN

5.4 A (EDP)

5 mOhm @4.5V

SI7108 DNMOSFET

RDS(ON )

LOADIN G

APN 376 S0651

5 mOhm @4.5V

48 mOh m @4.5 V

N-TYPE

CHANNE L

1.05V S0 FET

3.3V S3 FET

1.05V S0 FET

3.3V GPU FET

9

64

SOT563

SSM6N15FE APE

1/16W

5%

100K

MF-LF

402

0.001UF

402

CERM

20% 50V

NO STUF F

SOT563

SSM6N15FE APE

10

5%

402

1/16W MF-LF

402

X5R

1UF

10V

10%

0.01UF

CERM

402

16V

10%

1/16W

1K

MF-LF

5%

402

5%

51K

MF-LF

402

1/16W

68 83

10V

CERM

402

20%

0.1UF

402

0.068UF

CERM

10% 10V

SOT563

SSM6N15FE APE

5%

47K

402

MF-LF

1/16W

5%

10K

MF-LF

1/16W

402

MF-LF

1/16W

402

100K

5%

SOT563

SSM6N15 FEAPE

68

0.01UF

10% 16V

402

CERM

0.033UF

402

10%

X5R

16V

47K

MF-LF

402

5%

1/16W

10K

402

5% 1/16W MF-LF

10%

402

CERM

16V

0.01UF

16V

0.033UF

10%

X5R 402

47K

5% 1/16W MF-LF

402

100K

MF-LF

402

1/16W

5%

68

SOT563

SSM6N15FE APE

SOT563

SSM6N15FE APE

SM

FDC638P_G

CRITICAL

10V CERM 402

10%

0.068U F

220K

402

1/16W MF-LF

5%

SSM6N1 5FEAPE

SOT563

100K

MF-LF

1/16W

5%

402

MF-LF

1/16W

402

5%

10K

SOT563

SSM6N1 5FEAPE

68

CRITICA L

PWRPK-1212- 8-HF

SI7108D N

SSM3K1 5FV

SOD-VESM- HF

SOT-6

CRITICAL

FDC606P_G

CRITICAL

SOT-6

SI7108D N

PWRPK-1212-8-H F

CRITICA L

SYNC_MAS TER=PWRS QNC

SYNC_DAT E=05/12/ 2008

Power FETs

A.0.0

69

051-7546

96

P3V3GPU_ EN

=PP3V3_S 0_FET

=MCPDD R_EN

=PPVTT _S0_VT TCLAMP

=DDRVT T_EN

VTTCLA MP_EN

=PP5V_ S3_VTT CLAMP

=P3V3S3_ EN

P3V3S3_S S

P1V05_ EN_L

P1V05S 0_EN

MCPDDR _EN_L

=PP5V_ S3_MCP DDRFET

=PP1V8 R1V5_S 0_FET

=PP1V8 R1V5_S 0_MCP_F ET

MCPDDR _SS

MCPDDR _EN_L_ RC

P3V3S0_E N_L

=PP3V3_S 3_FET

=PP3V3_S 3_P3V3S3 FET

=PP3V3_S 0GPU_FET

=PP3V3_G PU_P3V3G PUFET

P3V3GPU_ SS

P3V3S0_S S

=PP3V3_S 0_P3V3S0 FET

P1V05_ EN_L_R C

=PP3V3 _S5_P1 V05FET

=PP1V0 5_S5_P 1V05S0F ET

=PP5V_ S3_P1V 05S0FET

P1V05S 0_SS

P3V3S3_E N_L

VTTCLA MP_L

=PP1V0 5_S0_F ET

P3V3GPU_ EN_L

=P3V3S0_ EN

Q7975

3

5

4

R7976

1

2

C7976

1

2

Q7975

6

2

1

R7975

1

2

C7971

1

2

C7970

1 2

R7970

1 2

R7972

1

2

C7902

1

2

C7903

1

2

Q7971

6

2

1

R7971

1 2

R7901

1 2

R7903

1

2

Q7971

3

5

4

C7910

1 2

C7911

1

2

R7910

1 2

R7912

1

2

C7930

1 2

C7931

1

2

R7930

1 2

R7932

1

2

Q7912

6

2

1

Q7912

3

5

4

Q7910

1

2

5

6

3

4

C7953

1

2

R7952

1 2

Q7951

6

2

1

R7951

1 2

R7953

1

2

Q7951

3

5

4

Q7901

5

4

1 2 3

Q7972

3

1

2

Q7930

1 2 5 6

3

4

Q7970

1 2 5 6

3

4

Q7953

5

4

1 2 3

8

OUT

GND_SENS E

VDD_SENS E

PEX_IOVD DQ23

PEX_IOVD DQ25

PEX_IOVD D5

PEX_IOVD DQ1

PEX_IOVD DQ2

PEX_PLLV DD

PEX_IOVD DQ22

PEX_IOVD DQ6

PEX_IOVD D2

PEX_IOVD D3

PEX_IOVD D4

PEX_IOVD DQ9

PEX_IOVD DQ15

PEX_IOVD DQ16

PEX_IOVD DQ17

PEX_IOVD DQ19

PEX_IOVD DQ20

PEX_IOVD DQ21

PEX_IOVD D1

PEX_IOVD DQ14

PEX_IOVD DQ13

PEX_IOVD DQ12

PEX_IOVD DQ8

PEX_IOVD DQ7

PEX_IOVD DQ5

PEX_IOVD DQ4

PEX_IOVD DQ11

PEX_IOVD DQ24

PEX_IOVD DQ18

PEX_IOVD DQ3

PEX_IOVD DQ10

NC

SYMBOL 2 OF 9

PEX_RFU2

PEX_TX2

PEX_TX3

PEX_TX3*

PEX_TX4

PEX_TX4*

PEX_TX5*

PEX_TX6*

PEX_RFU1

PEX_RX5

PEX_RX3*

PEX_RX4

PEX_RX0

PEX_RX1

PEX_RX0*

PEX_RX9

PEX_RX9*

PEX_RX4*

PEX_RX5*

PEX_RX10

PEX_TX13 *

PEX_TX1

PEX_TX7

PEX_TX10

PEX_TX10 *

PEX_TX11

PEX_TX11 *

PEX_TX12

PEX_TX12 *

PEX_TX13

PEX_TX14

PEX_TX14 *

PEX_TX15 *

PEX_TX9*

PEX_TX8*

PEX_TX2*

PEX_TX1*

PEX_TX0*

PEX_RX15 *

PEX_RX12 *

PEX_RX11 *

PEX_RX10 *

PEX_RX8*

PEX_RX7*

PEX_RX6*

PEX_RX2*

PEX_TX0

PEX_TX9

PEX_TX5

PEX_TX6

PEX_TX8

PEX_TX15

PEX_RX3

PEX_RX6

PEX_RX7

PEX_RX8

PEX_RX11

PEX_RX12

PEX_RX2

PEX_RX1*

PEX_RX15

PEX_RX14 *

PEX_RX14

PEX_RX13

PEX_RX13 *

PEX_TSTC LK_OUT*

PEX_TSTC LK_OUT

PEX_TERM P

PEX_CLKR EQ*

PEX_RST*

PEX_REFC LK*

PEX_REFC LK

PEX_TX7*

SYMBOL 1 OF 9

NC NC

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

- =PP1V2 _GPU_PEX _PLLXVDD

BOM opti ons prov ided by this pag e:

Signal a liases r equired by this page:

PEX 1.1V Current = 2A

- =PP1V2 _GPU_PEX _IOVDDQ

250mA

180mA

(NONE)

- =PP1V2 _GPU_PEX _IOVDD

(NONE)

1500mA

Power al iases re quired b y this p age:

Page Notes

9

89

0.1uF

10% X 5R16V 40 2

0.1uF

10% X 5R16V 40 2

9

89

9

89

0.1uF

10% X 5R16V 40 2

0.1uF

10% X 5R16V 40 2

9

89

9

89

0.1uF

10% X 5R16V 40 2

0.1uF

10% X 5R16V 40 2

9

89

9

89

0.1uF

10% X 5R16V 40 2

0.1uF

10% X 5R16V 40 2

9

89

9

89

0.1uF

10% 16V X5R 40 2

0.1uF

10% 16V X5R 40 2

9

89

10% 16V X5R 40 2

0.1uF

9

89

0.1uF

10% 16V X5R 40 2

0.1uF

10% 16V X5R 40 2

9

89

9

89

0.1uF

10% X 5R16V 40 2

0.1uF

10% X 5R16V 40 2

9

89

9

89

0.1uF

10% X 5R16V 40 2

X5R 402

0.1uF

10% 16V

0.1uF

10% X 5R16V 40 2

9

89

9

89

0.1uF

10% 16V X5R 40 2

0.1uF

10% X 5R16V 40 2

9

89

9

89

0.1uF

10% 16V X5R 40 2

0.1uF

10% 16V X5R 40 2

9

89

0.1uF

X5R 40210% 16V

9

89

0.1uF

10% 16V X5R 40 2

10%

0.1uF

16V X5R 402

9

89

9

89

0.1uF

10% X 5R16V 40 2

0.1uF

10% X 5R16V 40 2

9

89

9

89

0.1uF

10% X 5R16V 40 2

10% X 5R 40216V

0.1uF

10% X 5R16V 40 2

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

CERM 603

6.3V

20%

4.7UF

6.3V CERM 402

10%

1UF

0.1UF

10V

402

20%

CERM

0.1uF

X5R 40210% 16V

10V

20%

402

CERM

0.1UF

603

6.3V CERM

20%

4.7UF

6.3V CERM

4.7UF

20%

603

20%

805

6.3V

22UF

CERM-X5R

0.1uF

10% X 5R 40216V

1UF

10%

6.3V CERM 402

22UF

CERM-X5R 805

20%

6.3V

20%

CERM

4.7UF

6.3V

603

1UF

CERM 402

10%

6.3V

402

CERM

6.3V

10%

1UF

402

CERM

0.1UF

20% 10V

20%

0.1UF

402

CERM

10V

20% 10V CERM 402

0.1UF

0.1uF

16V 4 02X5R10%

10NH-6 00MA

0603

0.1uF

X5R 40210% 16V

OMIT

BGA

NB9P-G S

BGA

NB9P-G S

OMIT

1/16W

1%

402

MF-LF

2.49K

200

MF-LF

402

1%

1/16W

5%

0

402

MF-LF

1/16W

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

X5R

0.1uF

40210% 16V

0.1uF

40210% 16V X 5R

0.1uF

X5R 40210% 16V

10% 16V

0.1uF

X5R 402

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

0.1uF

X5R 40210% 16V

402X5R10% 16V

0.1uF

X5R 40210% 16V

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

17 89

9

0.1uF

10% 402X5R16V

0.1uF

10% 402X5R16V

9

89

9

89

9

89

9

89

0.1uF

10% 16V X5R 40 2

0.1uF

10% 16V X5R 40 2

9

89

9

89

0.1uF

10% X 5R16V 40 2

0.1uF

10% 16V X5R 40 2

9

89

SYNC_MAS TER=MUXG FX

NV G96 PCI-E

9670

SYNC_DAT E=07/10/ 2008

051-7546

A.0.0

GPU_RE SET_R_ L

GPU_RE SET_L

PEG_R2 D_N<12 >

PEG_R2 D_P<13 > PEG_R2 D_N<13 >

PEG_R2 D_N<14 >

=PP1V1 _GPU_P EX_IOVD DQ =PP1V1 _GPU_P EX_IOVD D

PEG_R2 D_C_P< 10>

MIN_NECK _WIDTH=0 .25 mm

PP1V1_ GPU_PE X_PLLVD D_F

MIN_LINE _WIDTH=0 .25 mm

VOLTAGE= 1.2V

PEG_R2 D_C_P< 3>

PEG_R2 D_N<7>

PEG_R2 D_N<10 >

PEG_R2 D_N<11 >

PEG_R2 D_C_P< 12>

PEG_R2 D_N<15 >

PEG_R2 D_C_P< 6>

PEG_R2 D_P<11 >

GPU_GN D_SENS E

PEG_R2 D_N<0>

PEG_R2 D_N<1>

PEG_R2 D_P<1>

PEG_R2 D_P<0>

PEG_R2 D_C_N< 13>

PEG_R2 D_C_N< 8>

PEG_R2 D_C_P< 8>

PEG_R2 D_C_P< 7>

PEG_R2 D_C_N< 6>

PEG_R2 D_C_P< 5>

PEG_R2 D_C_N< 4>

PEG_R2 D_C_N< 3>

PEG_R2 D_C_N< 2>

PEG_R2 D_C_P< 2>

PEG_D2 R_P<0>

PEG_D2 R_N<0>

PEG_D2 R_N<1>

PEG_D2 R_P<1>

PEG_D2 R_N<2>

PEG_D2 R_P<2>

PEG_D2 R_N<3>

PEG_D2 R_P<3>

PEG_D2 R_N<4>

PEG_D2 R_P<4>

PEG_D2 R_P<5>

PEG_D2 R_N<5>

PEG_D2 R_N<8>

PEG_D2 R_P<9>

PEG_D2 R_N<6>

PEG_D2 R_P<6>

PEG_D2 R_P<7>

PEG_D2 R_N<7>

PEG_D2 R_P<8>

PEG_D2 R_N<9>

PEG_D2 R_N<14 >

PEG_D2 R_P<13 >

PEG_D2 R_N<12 >

PEG_D2 R_N<10 >

PEG_D2 R_N<11 >

PEG_D2 R_P<11 >

PEG_D2 R_P<12 >

PEG_D2 R_P<14 >

PEG_D2 R_N<13 >

PEG_D2 R_P<15 >

PEG_D2 R_N<15 >

PEG_R2 D_P<2> PEG_R2 D_N<2>

PEG_R2 D_C_P< 4>

PEG_D2 R_C_N< 5>

PEG_D2 R_C_N< 6>

PEG_R2 D_N<3>

PEG_R2 D_P<4>

PEG_R2 D_N<9>

PEG_R2 D_P<10 >

PEG_D2 R_C_P< 1>

PEG_D2 R_C_P< 7> PEG_D2 R_C_N< 7>

PEG_D2 R_C_P< 10>

PEG_D2 R_C_P< 11> PEG_D2 R_C_N< 11>

PEG_D2 R_C_P< 12> PEG_D2 R_C_N< 12>

PEG_D2 R_C_N< 9>

PEG_D2 R_C_N< 8>

PEG_R2 D_N<8>

PEG_R2 D_N<6>

PEG_D2 R_C_P< 9>

PEG_D2 R_C_P< 5>

PEG_D2 R_C_P< 6>

PEG_D2 R_C_P< 8>

PEG_R2 D_P<3>

PEG_R2 D_P<6>

PEG_R2 D_P<7>

PEG_R2 D_P<8>

PEG_R2 D_P<15 >

PEG_R2 D_P<14 >

NC_GPU _DFM

NO_TEST=TRU E

PEG_R2 D_C_N< 5>

PEG_R2 D_C_N< 7>

PEG_R2 D_C_N< 1>

PEG_R2 D_N<5>

PEG_R2 D_P<5>

PEG_R2 D_N<4>

PEG_R2 D_P<9>

PEG_R2 D_C_N< 10>

PEG_R2 D_C_N< 9>

PEG_R2 D_C_P< 11>

PEG_R2 D_C_N< 12>

PEG_R2 D_P<12 >

PEG_D2 R_C_N< 4>

PEG_D2 R_C_P< 4>

PEG_D2 R_C_N< 3>

PEG_D2 R_C_P< 3>

PEG_D2 R_C_N< 2>

PEG_D2 R_C_P< 2>

PEG_D2 R_C_N< 1>

PEG_D2 R_C_N< 0>

PEG_D2 R_C_P< 0>

GPU_VD D_SENS E

PEG_D2 R_C_N< 10>

PEG_D2 R_P<10 >

PEG_D2 R_C_N< 14>

PEX_TS TCLK_P

PEG_D2 R_C_P< 14>

PEG_D2 R_C_N< 13>

PEG_D2 R_C_P< 13>

PEX_TS TCLK_N

PEX_TE RMP_PD

PEG_D2 R_C_P< 15> PEG_D2 R_C_N< 15>

PEG_R2 D_C_P< 13>

TP_PEX _CLKRE Q_L

PEG_R2 D_C_N< 11>

PEG_R2 D_C_P< 9>

PEG_R2 D_C_P< 1>

PEG_R2 D_C_N< 0>

PEG_R2 D_C_P< 0>

PEG_R2 D_C_P< 15>

PEG_R2 D_C_P< 14>

PEG_R2 D_C_N< 14>

PEG_R2 D_C_N< 15>

PEG_CL K100M_ N

PEG_CL K100M_ P

=PP1V1 _GPU_P EX_PLLX VDD

C8020

1 2

C8021

1 2

C8050

1 2

C8051

1 2

C8048

1 2

C8049

1 2

C8046

1 2

C8047

1 2

C8044

1 2

C8045

1 2

C8042

1 2

C8043

1 2

C8040

1 2

C8041

1 2

C8038

1 2

C8039

1 2

C8036

1 2

C8037

1 2

C8034

1 2

C8035

1 2

C8032

1 2

C8033

1 2

C8030

1 2

C8031

1 2

C8028

1 2

C8029

1 2

C8026

1 2

C8027

1 2

C8024

1 2

C8025

1 2

C8022

1 2

C8023

1 2

C8055

1 2

C8056

1 2

C8085

1 2

C8086

1 2

C8083

1 2

C8084

1 2

C8081

1 2

C8082

1 2

C8079

1 2

C8080

1 2

C8077

1 2

C8078

1 2

C8075

1 2

C8076

1 2

C8073

1 2

C8074

1 2

C8071

1 2

C8072

1 2

C8069

1 2

C8070

1 2

C8067

1 2

C8068

1 2

C8065

1 2

C8066

1 2

C8063

1 2

C8064

1 2

C8061

1 2

C8062

1 2

C8059

1 2

C8060

1 2

C8057

1 2

C8058

1 2

C8001

1

2

C8003

1

2

C8004

1

2

C8005

1

2

C8016

1

2

C8015

1

2

C8000

1

2

C8002

1

2

C8006

1

2

C8007

1

2

C8008

1

2

C8009

1

2

C8010

1

2

C8011

1

2

C8017

1

2

L8015

1 2

U8000

AD19

H32

AD6

AF6

AG6

AJ5

D35

AK15

AL7

E7

E35

F7

M7

A2

P6

P7

R7

U7

V6

AB7

AK16

AK17

AK21

AK24

AK27

AG11

AG24

AG25

AG26

AJ14

AJ15

AJ19

AJ21

AJ22

AJ24

AJ25

AG12

AJ27

AK18

AK20

AK23

AK26

AL16

AG13

AG15

AG16

AG17

AG18

AG22

AG23

AG14

AD20

U8000

AR13

AR16

AR17

AG19

AG20

AM16

AP17

AN17

AN19

AP19

AN28

AP28

AR28

AR29

AP29

AN29

AN31

AP31

AR31

AR32

AR34

AP34

AR19

AR20

AP20

AN20

AN22

AP22

AR22

AR23

AP23

AN23

AN25

AP25

AR25

AR26

AP26

AN26

AG21

AJ17

AJ18

AL17

AM17

AM18

AM19

AM27

AM28

AL28

AK28

AK29

AL29

AM29

AM30

AM31

AM32

AN32

AP32

AL19

AK19

AL20

AM20

AM21

AM22

AL22

AK22

AL23

AM23

AM24

AM25

AL25

AK25

AL26

AM26

R8050

1 2

R8060

1 2

R8020

1 2

89

8

89

78

89

89 89

89

78

89

8

VDD VDD

SYMBOL 9 OF 9

SYMBOL 7 OF 9

FBVDDQ FBV DDQ

SYMBOL 8 OF 9

GNDGND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Power al iases re quired b y this p age:

- =PPVCO RE_GPU

(NONE)

- =PP1V8 _GPU_FBV DDQ

BOM opti ons prov ided by this pag e:

Signal a liases r equired by this page:

Nvidia P RD for G B-128 us es 4x4.7 uF, 8x0. 47uF, 16 x0.1uF

Page Notes

???A @ ? ??MHz 1. 8V GDDR3

???A @ ? ??/???MH z Core/M em Clk f or VDD

4.7UF

20%

X5R-CERM 402

6.3V

4.7UF

20%

X5R-CERM

6.3V

402

4.7UF

20%

X5R-CERM

6.3V

402

CERM-X5R 402

6.3V

0.47UF

10%

6.3V

0.47UF

10%

CERM-X5R 402

20% 10V

402

CERM

0.1UF

0.47UF

6.3V

10%

CERM-X5R 402

6.3V

0.47UF

10%

CERM-X5R 402

6.3V

0.47UF

10%

CERM-X5R 402

6.3V

0.47UF

10%

CERM-X5R 402

CERM

20%

402

0.1UF

10V10V

0.1UF

20%

402

CERM

6.3V

0.47UF

10%

CERM-X5R 402

6.3V

0.47UF

10%

CERM-X5R 402

20% 10V

402

CERM

0.1UF0.1UF

20% 10V CERM 402

6.3V

0.47UF

10%

CERM-X5R 402

6.3V

0.47UF

10%

CERM-X5R 402

0.47UF

6.3V

10%

CERM-X5R

402

10%

6.3V

0.47UF

402

CERM-X5R

0.1UF

20% 10V

402

CERM

6.3V CERM

20%

603

4.7UF

0.1UF

20% 10V

402

CERM

10V

20%

0.1UF

402

CERM

10V

20%

0.1UF

402

CERM

6.3V

20%

603

4.7UF

20%

0.1UF

10V

402

CERM

0.1UF

20% 10V

CERM

402

10V

20%

CERM

0.1UF

402

10V

0.1UF

20%

402

CERM

0.1UF

402

CERM

20% 10V

CERM

0.1UF

402

20% 10V

0.1UF

402

CERM

20% 10V

402

CERM

10V

0.1UF

20%

CERM 402

20% 10V

0.1UF

0.47UF

6.3V

10%

CERM-X5R

402

CERM-X5R

10%

6.3V

402

0.47UF

402

6.3V

10%

CERM-X5R

0.47UF

402

6.3V

10%

0.47UF

CERM-X5R

402

6.3V

10%

CERM-X5R

0.47UF

402

6.3V

10%

CERM-X5R

0.47UF

BGA

OMIT

NB9P-GS

BGA

OMIT

NB9P-GS

BGA

NB9P-GS

SYNC_MAS TER=MUXG FX

NV G96 Core/FB Power

SYNC_DAT E=07/10/ 2008

A.0.0

051-7546

71 9 6

=PPVCORE _GPU

=PP1V8_G PU_FBVDD Q

C8101

1

2

C8100

1

2

C8102

1

2

C8107

1

2

C8112

1

2

C8117

1

2

C8106

1

2

C8105

1

2

C8110

1

2

C8111

1

2

C8116

1

2

C8115

1

2

C8104

1

2

C8109

1

2

C8114

1

2

C8113

1

2

C8108

1

2

C8103

1

2

C8160

1

2

C8166

1

2

C8159

1

2

C8151

1

2

C8158

1

2

C8165

1

2

C8164

1

2

C8150

1

2

C8157

1

2

C8163

1

2

C8162

1

2

C8156

1

2

C8122

1

2

C8121

1

2

C8120

1

2

C8119

1

2

C8118

1

2

C8161

1

2

C8167

1

2

C8169

1

2

C8168

1

2

C8171

1

2

C8170

1

2

U8000

L11

L20

AC20

AC21

AC22

AC23

AC24

AC25

AD12

AD14

AD16

AD18

L21

AD22

W20

L22

L23

L24

L25

M12

M14

M16

M18

L12

M20

M22

M24

P11

P13

P15

P17

P19

P21

P23

L13

P25

R11

R12

R13

R14

R15

R16

R17

R18

R19

L14

R20

R21

R22

R23

R24

R25

T12

T14

T16

T18

L15

T20

T22

T24

V11

V13

V15

V17

V19

V21

V23

L16

V25

W11

W12

W13

W14

W15

W16

W17

W18

W19

L17

AD24

W21

W22

W23

W24

W25

Y12

Y14

Y16

Y18

L18

Y20

Y22

Y24

AB11

AB13

AB15

AB17

AB19

AB21

AB23

L19

AB25

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

U8000

B18

E21

G8

G9

G17

G18

G22

H29

J14

J15

J16

J17

J20

J21

J22

J23

J24

J29

N27

P27

R27

T27

U27

U29

V27

V29

V34

W27

Y27

AA27

AA29

AA31

AB27

AB29

AC27

AD27

AE27

AJ28

U8000

B3

B33

V24

V31

Y11

Y13

Y15

Y17

Y19

Y21

Y23

Y25

C2

AA2

AA5

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

C34

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA34

AB12 AB14

E6

AB16

AB18

AB20

AB22

AB24

AC9

AD2

AD5

AD11

AD13

E9

AD15

AD17

AD21

AD23

AD25

AD31

AD34

AE11

AE12

AE13

E12

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

E15

AE24

AE25

AG2

AG5

AG31

AG34

AK2

AK5

AP33

AK31

E18

AK34

AL6

AL9

AL12

AL15

AL18

AL21

AL24

AL27

AL30

E24

AN2

AN34

AP3

AP6

AP9

AP12

AP15

AP18

AP21

AP24

E27

AP27

AP30

B6

E30

F2

F5

F31

F34

J2

J5

J31

J34

L9

B9

M2

M5

M11

M13

M15

M17

M19

M21

M23

M25

B12

M31

M34

N11

N12

N13

N14

N15

N16

N17

N18

B15

N19

N20

N21

N22

N23

N24

N25

P12

P14

P16

B21

P18

P20

P22

P24

R2

R5

R31

R34

T11

T13

B24

T15

T17

T19

T21

T23

T25

U11

U12

U13

U14

B27

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

B30

U25

V2

V5

V9

V12

V14

V16

V18

V20

V22

8

BI

OUT

BI

OUT

BI

IN

OUT

BI

IN

OUT

D

SG

IN

OUT OUT

OUT

FBC_D8

FBC_CMD2

FBC_CMD3

FBC_RFU0

FBC_RFU1 *

FBC_RFU7 *

FBC_RFU6

FBC_RFU5 *

FBC_RFU4

FBC_RFU3 *

FBC_RFU2

FBC_D63

FBC_D62

FBC_D21

FBC_D24

FBC_D25

FBC_D26

FBC_D0

FBC_D2

FBC_CMD1

FBC_CMD0

FBC_D5

FBC_D3

FBC_D4

FBC_D6

FBC_D7

FBC_D9

FBC_D10

FBC_D11

FBC_D12

FBC_D13

FBC_D14

FBC_D15

FBC_D16

FBC_D17

FBC_D18

FBC_D19

FBC_D20

FBC_D23

FBC_D28

FBC_D31

FBC_D34

FBC_D32

FBC_D33

FBC_D36

FBC_D37

FBC_D38

FBC_D39

FBC_D40

FBC_D41

FBC_D42

FBC_D43

FBC_D44

FBC_D45

FBC_D46

FBC_D47

FBC_D48

FBC_D49

FBC_D50

FBC_D51

FBC_D52

FBC_D53

FBC_D54

FBC_D55

FBC_CMD2 6

FBC_CMD2 5

FBC_CMD2 4

FBC_CMD2 3

FBC_CMD2 2

FBC_CMD2 0

FBC_CMD1 9

FBC_CMD1 7

FBC_CMD1 6

FBC_CMD1 4

FBC_CMD1 3

FBC_CMD1 1

FBC_CMD1 0

FBC_CMD9

FBC_CMD8

FBC_CMD7

FBC_CMD6

FBC_CMD5

FBC_CMD4

FBC_CMD2 1

FBC_CMD1 8

FBC_CMD1 5

FBC_CMD1 2

FBC_D1

FBC_D58

FBC_D57

FBC_D56

FBC_D27

FBC_D29

FBC_D30

FBC_D35

FBC_D22

FBC_CLK0 *

FBC_CLK0

FBC_CLK1

FBC_CLK1 *

FBC_DQM0

FBC_DQM1

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_DQS_ RN0

FBC_DQS_ RN1

FBC_DQS_ RN2

FBC_DQS_ RN3

FBC_DQS_ RN4

FBC_DQS_ RN5

FBC_DQS_ RN6

FBC_DQS_ RN7

FBC_DQS_ WP1

FBC_DQS_ WP0

FBC_DQS_ WP2

FBC_DQS_ WP3

FBC_DQS_ WP4

FBC_DQS_ WP5

FBC_DQS_ WP6

FBC_DQS_ WP7

FB_DLLAV DD1

FBC_DEBU G

FB_PLLAV DD1

FB_VREF

FBC_CMD2 8

FBC_CMD2 7

FBC_CMD3 0

FBC_CMD2 9

FBC_D61

FBC_D60

FBC_D59

SYMBOL 4 OF 9

FBA_D62

FBA_D60

FBA_D59

FBA_D57

FBA_D55

FBA_D52

FBA_D48

FBA_D43

FBA_D39

FBA_D36

FBA_D34

FBA_D32

FBA_D30

FBA_D28

FBA_D27

FBA_D26

FBA_D25

FBA_CMD0

FBA_CMD7

FBA_CMD9

FBA_D5

FBA_CMD1

FBA_D0

FBA_D1

FBA_CMD2

FBA_CMD3

FBA_CMD4

FBA_CMD5

FBA_CMD6

FBA_CMD8

FBA_CMD1 0

FBA_CMD1 1

FBA_CMD1 5

FBA_CMD1 4

FBA_CMD1 3

FBA_CMD1 2

FBA_D14

FBA_D15

FBA_D17

FBA_D20

FBA_D23

FBA_D24

FBA_D33

FBA_D35

FBA_D38

FBA_D40

FBA_D41

FBA_D42

FBA_D44

FBA_D45

FBA_D46

FBA_D47

FBA_D49

FBA_D50

FBA_D51

FBA_D53

FBA_D54

FBA_D56

FBA_CMD2 4

FBA_CMD2 3

FBA_CMD2 2

FBA_CMD2 1

FBA_CMD2 0

FBA_CMD1 9

FBA_CMD1 8

FBA_CMD1 7

FBA_CMD1 6

FBA_D22

FBA_D19

FBA_D16

FBA_CMD2 5

FBA_D31

FBA_D18

FBA_D3

FBA_D11

FBA_D10

FBA_D9

FBA_D8

FBA_D7

FBA_D6

FBA_D4

FBA_D2

FBA_D37

FBA_D21

FBA_D29

FBA_DQM5

FBA_DQM6

FBA_DQS_ RN0

FBA_DQM7

FBA_DQS_ RN2

FBA_DQS_ RN1

FBA_DQS_ RN4

FBA_DQS_ RN3

FBA_DQS_ RN5

FBA_DQS_ RN6

FBA_DQS_ RN7

FBA_DQS_ WP0

FBA_DQS_ WP1

FBA_DQS_ WP4

FBA_DQS_ WP5

FBA_DQS_ WP6

FB_DLLAV DD0

FBA_DQS_ WP7

FBA_DEBU G

FB_PLLAV DD0

FB_CAL_P U_GND

FB_CAL_P D_VDDQ

FB_CAL_T ERM_GND

FBA_CLK1 *

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_CLK0 *

FBA_CLK1

FBA_CLK0

FBA_CMD3 0

FBA_DQM0

FBA_DQS_ WP3

FBA_DQS_ WP2

FBA_D58

FBA_D63

FBA_D61

FBA_RFU7 *

FBA_RFU1 *

FBA_RFU3 *

FBA_RFU4

FBA_RFU5 *

FBA_RFU6

FBA_RFU2

FBA_RFU0

FBA_D13

FBA_D12

FBA_CMD2 9

FBA_CMD2 8

FBA_CMD2 7

FBA_CMD2 6

SYMBOL 3 OF 9

NC

NC NC

NC NC NC NC NC NC

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

(NONE)

- =PP1V8 _GPU_FBI O

(NONE)

BOM opti ons prov ided by this pag e:

Power al iases re quired b y this p age:

Page Notes

Signal a liases r equired by this page:

- =PP1V2 _GPU_FBP LLAVDD

73 94

76

73 94

74 94

73 94

CERM

10V

0.1UF

20%

402

73 94

74 94

76

74 94

402

MF-LF

5%

10K

1/16W

74 94

5% 1/16W MF-LF 402

10K

PLACEMEN T_NOTE=P lace clo se to U8 000.

1/16W MF-LF

402

33.2

1%

16V

0.1uF

10%

X5R 402

NO STUFF

1.07K

MF-LF

402

1/16W

1%

FERR-220 -OHM

0402

402

MF-LF

1/16W

1%

PLACEMEN T_NOTE=P lace clo se to U8 000.

48.7

6.3V CERM

1UF

10%

402

10K

MF-LF

1/16W

5%

402

5% 1/16W MF-LF 402

10K

73 94

74 94

SSM6N15F EAPE

SOT563

NO STUFF

402

MF-LF

1/16W

1%

2.49K1.02K

1%

402

MF-LF

1/16W

NO STUFF

73 74 76

73 94 74 94

73 94

76

74 94

76

BGA

NB9P-GS

OMIT

1/16W

402

MF-LF

1%

40.2

PLACEMEN T_NOTE=P lace clo se to U8 000.

0.1UF

20% 10V CERM 402

20%

0.1UF

10V CERM 402

20%

0.1UF

10V CERM 402

60.4

1% 1/16W MF-LF

402

1%

1/16W

60.4

MF-LF

NB9P-GS

BGA

OMIT

NV G96 Frame Buffer I/F

SYNC_MAS TER=MUXG FX

SYNC_DAT E=07/10/ 2008

72 9 6

051-7546

A.0.0

GPU_FB_V REF_UNTE RM_L

MIN_LINE_WI DTH=0.25 mm MIN_NECK_WI DTH=0.25 mm

=PP1V1_G PU_FBPLL AVDD

FB_B_DQ< 51>

FB_B_DQ< 56>

FB_B_DQ< 38>

FB_B_DQ< 39>

FB_B_DQ< 40>

FB_B_DQ< 41>

FB_B_DQ< 54>

FB_B_DQ< 49>

FB_B_DQ< 48>

FB_B_DQM _L<0>

FB_B_DQM _L<1>

FB_B_DQM _L<2>

FB_B_DQM _L<3>

FB_B_DQM _L<4>

=PP1V8_G PU_FBIO

FB_B_DQ< 35>

FB_B_DQ< 50>

FB_B_DQM _L<6>

FB_B_DQM _L<7>

FB_B_DQ< 46>

FB_B_DQ< 47>

FB_B_RDQ S<5>

FB_B_WDQ S<1>

FB_B_MA< 0>

FB_B_MA< 9>

FB_B_MA< 6>

TP_FBC_C MD30

TP_FBC_C MD29

TP_FBC_C MD28

FB_B_DQ< 25>

FB_B_WDQ S<6>

FB_B_WDQ S<5>

FB_B_WDQ S<3>

FB_B_WDQ S<4>

FB_B_WDQ S<2>

FB_B_WDQ S<0>

FB_B_RDQ S<7>

FB_B_RDQ S<6>

FB_B_RDQ S<4>

FB_B_RDQ S<3>

FB_B_RDQ S<2>

FB_B_RDQ S<1>

FB_B_RDQ S<0>

FB_B_DQM _L<5>

FB_B_CLK _P<1>

FB_B_CLK _N<0>

FB_B_DQ< 44>

FB_B_DQ< 45>

FB_B_DQ< 32>

FB_B_DQ< 31>

FB_B_DQ< 30>

FB_B_DQ< 53>

FB_B_DQ< 60>

FB_B_DQ< 36>

FB_VREF_ UNTERM

FB_B_DQ< 52>

FB_B_DQ< 55>

FB_B_DQ< 57>

FB_B_DQ< 59>

FB_B_LMA <4>

FB_B_RAS _L

FB_B_DQ< 61>

FB_B_DQ< 2>

FB_B_DQ< 1>

FB_B_DQ< 0>

FB_B_BA< 0>

FB_B_DRA M_RST

FB_B_LMA <5>

FB_B_BA< 1>

FB_B_UMA <2>

FB_B_UMA <4>

FB_B_UMA <3>

FB_B_CS1 _L

FB_B_CS0 _L

FB_B_MA< 11>

FB_B_CAS _L

FB_B_WE_ L

FB_B_UMA <5>

FB_B_MA< 12>

FB_B_MA< 7>

FB_B_MA< 10>

FB_B_LMA <2>

FB_B_LMA <3>

FB_B_MA< 1>

FB_B_MA< 13>

FB_B_BA< 2>

FB_B_DQ< 58>

FB_B_DQ< 43>

FB_B_DQ< 37>

FB_B_DQ< 33>

FB_B_DQ< 34>

FB_B_DQ< 29>

FB_B_DQ< 28>

FB_B_DQ< 27>

FB_B_DQ< 24>

FB_B_DQ< 23>

FB_B_DQ< 22>

FB_B_DQ< 21>

FB_B_DQ< 20>

FB_B_DQ< 19>

FB_B_DQ< 18>

FB_B_DQ< 17>

FB_B_DQ< 16>

FB_B_DQ< 15>

FB_B_DQ< 14>

FB_B_DQ< 13>

FB_B_DQ< 11>

FB_B_DQ< 10>

FB_B_DQ< 8>

FB_B_DQ< 9>

FB_B_DQ< 7>

FB_B_DQ< 6>

FB_B_DQ< 4>

FB_B_DQ< 3>

FB_B_DQ< 5>

FB_B_DQ< 26>

FB_B_MA< 8>

=PP1V1_G PU_FBPLL AVDD

FB_B_WDQ S<7>

=PP1V8_G PU_FBIO

FB_B_DQ< 12>

FB_B_CLK _N<1>

FB_B_CLK _P<0>

FB_B_CKE

FB_A_BA< 2>

TP_FBA_C MD28

FB_A_DQ< 12>

FB_A_DQ< 13>

FB_A_DQ< 61>

FB_A_DQ< 63>

FB_A_DQ< 58>

FB_A_WDQ S<2>

FB_A_WDQ S<3>

FB_A_DQM _L<0>

TP_FBA_C MD30

FB_A_CLK _P<0>

FB_A_CLK _P<1>

FB_A_CLK _N<0>

FB_A_DQM _L<4>

FB_A_DQM _L<3>

FB_A_DQM _L<2>

FB_A_DQM _L<1>

FB_A_CLK _N<1>

FBCAL_TE RM_GND

FBCAL_PD _VDDQ

FBCAL_PU _GND

FBA_DEBU G

FB_A_WDQ S<7>

VOLTAGE=1 .1V

MIN_LINE_ WIDTH=0.2 MM MIN_NECK_ WIDTH=0.2 MM

PP1V1_GP U_FBPLLA VDD_F

FB_A_WDQ S<5>

FB_A_WDQ S<1>

FB_A_WDQ S<0>

FB_A_RDQ S<7>

FB_A_RDQ S<6>

FB_A_RDQ S<5>

FB_A_RDQ S<3>

FB_A_RDQ S<4>

FB_A_RDQ S<1>

FB_A_RDQ S<2>

FB_A_DQM _L<7>

FB_A_RDQ S<0>

FB_A_DQM _L<6>

FB_A_DQM _L<5>

FB_A_DQ< 29>

FB_A_DQ< 21>

FB_A_DQ< 37>

FB_A_DQ< 2>

FB_A_DQ< 4>

FB_A_DQ< 6>

FB_A_DQ< 7>

FB_A_DQ< 8>

FB_A_DQ< 9>

FB_A_DQ< 10>

FB_A_DQ< 3>

FB_A_DQ< 18>

FB_A_DQ< 31>

FB_A_DQ< 16>

FB_A_DQ< 19>

FB_A_DQ< 22>

FB_A_MA< 7>

FB_A_MA< 10>

FB_A_CKE

FB_A_MA< 0>

FB_A_DQ< 56>

FB_A_DQ< 54>

FB_A_DQ< 53>

FB_A_DQ< 51>

FB_A_DQ< 50>

FB_A_DQ< 47>

FB_A_DQ< 46>

FB_A_DQ< 44>

FB_A_DQ< 42>

FB_A_DQ< 41>

FB_A_DQ< 38>

FB_A_DQ< 35>

FB_A_DQ< 33>

FB_A_DQ< 24>

FB_A_DQ< 23>

FB_A_DQ< 20>

FB_A_DQ< 17>

FB_A_DQ< 15>

FB_A_DQ< 14>

FB_A_BA< 0>

FB_A_UMA <5>

FB_A_MA< 12>

FB_A_DRA M_RST

FB_A_WE_ L

FB_A_CAS _L

FB_A_CS0 _L

FB_A_UMA <3>

FB_A_UMA <4>

FB_A_UMA <2>

FB_A_BA< 1>

FB_A_LMA <5>

FB_A_DQ< 1>

FB_A_DQ< 0>

FB_A_RAS _L

FB_A_DQ< 5>

FB_A_MA< 11>

FB_A_CS1 _L

FB_A_LMA <4>

FB_A_DQ< 25>

FB_A_DQ< 26>

FB_A_DQ< 27>

FB_A_DQ< 28>

FB_A_DQ< 30>

FB_A_DQ< 32>

FB_A_DQ< 34>

FB_A_DQ< 36>

FB_A_DQ< 39>

FB_A_DQ< 43>

FB_A_DQ< 52>

FB_A_DQ< 55>

FB_A_DQ< 57>

FB_A_DQ< 59>

FB_A_DQ< 60>

FB_A_DQ< 62>

FB_A_DQ< 11>

FB_A_DQ< 45>

FB_A_DQ< 40>

FB_A_WDQ S<4>

FB_A_WDQ S<6>

FB_A_DQ< 49>

FB_A_DQ< 48>

TP_FBA_C MD29

FB_A_MA< 13>

FB_B_DQ< 42>

FBC_DEBU G

GPU_FB_V REF

FB_B_DQ< 63>

FB_B_DQ< 62>

FB_A_MA< 1>

FB_A_LMA <3>

FB_A_MA< 8>

FB_A_LMA <2>

FB_A_MA< 6>

FB_A_MA< 9>

C8201

1

2

R8200

1

2

R8250

1

2

R8291

1

2

C8296

1

2

R8295

1

2

L8200

1 2

R8290

1

2

C8200

1

2

R8201

1

2

R8251

1

2

Q8295

6

2

1

R8296

1

2

R8297

1

2

U8000

J19

J18

J27

E17

D17

D23

E23

C17

B19

F19

F23

A22

C22

B17

F24

C25

E22

C20

B22

D18

A19

D22

D20

E19

D19

F18

C19

F22

C23

B20

F21

A20

A23

D21

B23

E20

G21

F20

D11

E11

A11

B8

A8

C8

C11

C10

D12

E13

F17

F15

F10

F16

E16

F14

F13

D13

A13

B13

A14

C16

A17

D8

B16

D16

D24

D26

E25

F25

F27

E28

F28

D29

F8

A25

B25

D25

C26

C28

B28

A28

A29

E29

F29

F9

D30

E31

C33

D33

F32

E32

B29

C29

B31

C31

E8

B32

C32

B34

B35

F12

B11

C13

G19

F11

D10

D15

A16

D27

D28

D34

A34

D9

B10

E14

B14

F26

A26

D31

A31

E10

A10

D14

C14

E26

B26

D32

A32

G11

G12

G14

G15

G24

G25

G27

G28

R8292

1

2

C8202

1

2

C8291

1

2

C8290

1

2

R8293

1

2

R8294

1

2

U8000

K27

L27

M27

AG27

AF27

T32

T31

AC31

AC30

V32

W31

T35

AB31

Y30

Y34

W32

AA30

AA32

Y33

U32

Y31

U31

U34

Y35

W34

V30

U35

U30

U33

AB30

AB33

T33

Y32

W29

AB35

AB34

W35

W33

W30

T34

R30

R32

N35

P35

N34

L33

L32

N33

K31

K30

G30

K32

P31

G32

H30

F30

G31

H33

K35

K33

G34

K34

E33

N30

E34

G33

AG30

AH31

AG32

AF31

AF30

AD30

AC32

AE30

L31

AE32

AF33

AF34

AE35

AE33

AE34

AC35

AB32

AN33

AK32

M32

AL33

AM33

AL31

AK30

AJ30

AH30

AM35

AH33

AH35

AH32

M30

AH34

AM34

AL35

AJ33

L30

P33

P34

T30

P30

P32

J30

H34

AF32

AF35

AL32

AL34

N32

L35

H31

G35

AD32

AC34

AJ31

AJ35

N31

L34

J32

H35

AE31

AC33

AJ32

AJ34

P29

R29

L29

M29

AD29

AE29

AG29

AH29

72

8

76

8

76

IN

BI

IN

OUT

IN

OUT

IN

BI

IN

BI

IN

IN IN

D

SG

D

SG

D

SG

D

SG

IN IN

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ7

DQ10

DQ11

DQ12

DQ13

DQ15

DQ16

DQ18

DQ19

DQ21

DQ23

DQ22

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

A3

A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5

A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ7

DQ10

DQ11

DQ12

DQ13

DQ15

DQ16

DQ18

DQ19

DQ21

DQ23

DQ22

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

A3

A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5

A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

VDD0

VDD1

VDD4

VDD3

VDD2

VSS6

VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0

VSSA1

VDDA0

VDDA1

VDD7

VDD6

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ16

VDDQ17

VDDQ18

VDDQ19

VDDQ20

VDDQ21

VSSQ0

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ15

VSSQ16

VSSQ17

VSSQ18

VSSQ19

VREF0

VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

VDD0

VDD1

VDD4

VDD3

VDD2

VSS6

VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0

VSSA1

VDDA0

VDDA1

VDD7

VDD6

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ16

VDDQ17

VDDQ18

VDDQ19

VDDQ20

VDDQ21

VSSQ0

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ15

VSSQ16

VSSQ17

VSSQ18

VSSQ19

VREF0

VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

BI

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

- =PP1V8 _S0_FB_V REFA

Page Notes

Power al iases re quired b y this p age:

- =PP1V8 _S0_FB_V DD

Signal a liases r equired by this page:

VRAM4

U8400.J12

U8400.J1U8400.J1

(NONE)

BOM opti ons prov ided by this pag e:

Connect to desig nated pi n, then GNDConnect to desig nated pi n, then GND

U8400.J12

549

1%

402

MF-LF

1/16W

1.33K

1% 1/16W MF-LF

402

16V

402

X5R

0.1uF

10%

16V

10%

X5R 402

0.1uF

10%

402

X5R

16V

0.1uF

16V

10%

402

X5R

0.1uF

402

X5R

16V

0.1uF

10%

0.1uF

10% 16V X5R 402

X5R

10% 16V

0.1uF

402

10%

0.1uF

16V

402

X5R

16V

10%

X5R

0.1uF

402

MF-LF

5% 1/16W

402

100

1/16W

1%

402

243

MF-LF

1%

121

402

1/16W MF-LF

VRAM4

243

MF-LF

402

1%

1/16W

402

X5R

16V

10%

0.1uF

16V

10%

402

X5R

0.1uF0 .1uF

10% 16V

402

X5R

5%

1K

402

1/16W MF-LF

402

1%

MF-LF

243

1/16W

1%

121

MF-LF

402

1/16W

VRAM4

402

121

1%

MF-LF

VRAM4

1/16W

1%

121

MF-LF

402

1/16W

VRAM4

72 94

72 73 94

72 94

72 73 94

72 94

72 73 94

72 94

72 73 94

72 94

72 73 94

72 94

72 73 94

72 94

72 73 94

72 94

72 73 94

MF-LF

402

1/16W

1K

5%

402

1%

121

1/16W

VRAM4

MF-LF

10%

0.1uF

X5R

16V

402

0.1uF

X5R 402

10% 16V

243

MF-LF

402

1%

1/16W

100

MF-LF 402

1/16W

5%

1/16W

402

MF-LF

121

1%

VRAM4

MF-LF

1%

402

1/16W

121

VRAM4

1%

121

402

1/16W MF-LF

243

1/16W

402

1%

MF-LF

243

1/16W

1%

402

MF-LF

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

16V

10%

0.1uF

X5R 402

10% 16V

0.1uF

402

10% 16V X5R X5R

0.1uF

10% 16V

402

X5R 402

10% 16V

0.1uF

402

X5R

0.1uF

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

72 94

X5R

6.3V

603

20%

10UF

6.3V

20%

10UF

603

X5R

20%

6.3V X5R 603

10UF

20%

6.3V X5R 603

10UF

16V

10%

402

0.01UF

CERM

10% 16V

402

0.01UF

931

1/16W MF-LF

402

1%

CERM 402

0.01uF

10% 16V

402

MF-LF

1%

1/16W

931

1/16W

1%

MF-LF

402

549

402

1/16W MF-LF

1%

1.33K

72 73 74 76

SSM6N15F EAPE

SOT563

SSM6N15F EAPE

SOT563

1/16W

1%

MF-LF

931

402

549

1/16W

402

MF-LF

1%

1.33K

1/16W

402

1%

MF-LF

CERM 402

0.01UF

16V

10%

SSM6N15F EAPE

SOT563

402

10% 16V

0.01uF

CERM

1/16W MF-LF

402

1%

931

1/16W

1%

402

MF-LF

549

MF-LF

402

1/16W

1%

1.33K

SSM6N15F EAPE

SOT563

72 73 94 72 73 94

OMIT

BGA

K4J103 24QD-HC 11

32MX32- 900MHZ -MFH

CRITIC AL

OMIT

CRITIC AL

32MX32- 900MHZ -MFH

BGA

K4J103 24QD-HC 11

OMIT

CRITIC AL

BGA

K4J103 24QD-HC 11

32MX32- 900MHZ -MFH

CRITIC AL

BGA

OMIT

32MX32- 900MHZ -MFH

K4J103 24QD-HC 11

72 94

16V CERM 402

10%

0.01UF

A.0.0

9673

SYNC_MAS TER=MUXG FX

SYNC_DAT E=07/10/ 2008

051-7546

GDDR3 Frame Buffe r A (Top)

FB_A_RDQ S<6>

FB_A_RDQ S<4>

FB_A_WDQ S<7>

FB_A_WDQ S<5>

FB_A_WDQ S<6>

FB_A_WDQ S<4>

FB_A_BA< 0>

FB_A_BA< 1>

FB_A_BA< 2>

FB_A1_SE N

FB_A_MA< 1>

FB_A_UMA <5>

FB_A_CKE

FB_A_MA< 9>

FB_A_DQ< 60>

FB_A_DQ< 57>

FB_A_DQ< 56>

FB_A_DQ< 59>

FB_A_DQ< 58>

FB_A_DQ< 63>

FB_A_DQ< 61>

FB_A_DQ< 40>

FB_A_DQ< 62>

FB_A_DQ< 44>

FB_A_DQ< 47>

FB_A_DQ< 33>

FB_A_DQ< 32>

FB_A_DQ< 36>

FB_A_DQ< 37>

FB_A_DQ< 38>

FB_A_DQ< 39>

FB_A_DQ< 34>

=PP1V8_G PU_FB_VD DQ

FB_A_MA< 11>FB_A_MA< 11>

FB_A_MA< 10>

FB_A_MA< 9>

FB_A_MA< 8>

FB_A_MA< 7>

FB_A_MA< 6>

FB_A_LMA <5>

FB_A_LMA <4>

FB_A_LMA <3>

FB_A_CKE

FB_A_CS0 _L

FB_A_DQ< 16>

FB_A_DQ< 19>

FB_A_DQ< 21>

FB_A_DQ< 22>

FB_A_DQ< 20>

FB_A_DQ< 26>

FB_A_DQ< 25>

FB_A_DQ< 27>

FB_A_DQ< 17>

FB_A_DQ< 6>

FB_A_DQ< 7>

FB_A_DQ< 8>

FB_A_DQ< 11>

FB_A_DQ< 9>

FB_A_DQ< 10>

FB_A_DQ< 14>

FB_A_DQ< 4>

FB_A_DQ< 15>

FB_A_DQ< 0>

FB_A_DQ< 3>

FB_A_DQ< 2>

FB_A_CLK _N<0>

FB_A_DQM _L<0>

FB_A_BA< 2>

FB_A_BA< 1>

FB_A_BA< 0>

FB_A_WDQ S<2>

FB_A_WDQ S<1>

FB_A_WDQ S<0>

FB_A_WDQ S<3>

FB_A_RDQ S<1>

FB_A_RDQ S<0>

FB_A0_SE N

FB_A_DQ< 13>

FB_A_DQ< 23>

FB_A_DQ< 18>

FB_A_DQ< 1>

FB_A_DQ< 12>

FB_A_DQM _L<1>

FB_A_DQM _L<2>

FB_A_DQM _L<3>

FB_A_CAS _L

FB_A_WE_ L

FB_A0_ZQ

FB_A_RAS _L

FB_A_RDQ S<2>

FB_A_RDQ S<3>

FB_A_DRA M_RST

FB_A_LMA <2>

FB_A_MA< 1>

FB_A_MA< 0>

FB_A_MA< 12>

FB_A_DQ< 24>

FB_A_DQ< 29>

FB_A_DQ< 30>

FB_VREF_ UNTERM

=PP1V8_G PU_FB_VD D =PP1V8_G PU_FB_VD D

=PP1V8_G PU_FB_VR EF_A

FB_A0_VR EF_UNTER M_L

FB_A_DQM _L<4>

FB_A_DQM _L<6>

FB_A_DQM _L<5>

FB_A_DRA M_RST

FB_A_RDQ S<7>

FB_A2_VR EF FB_A3_VR EF

FB_A_CLK 1_TERM

VOLTAGE=0. 9V

=PP1V8_G PU_FB_VR EF_A

FB_A1_VR EF

FB_A2_VR EF_UNTER M_L

FB_A0_VR EF

FB_A_CLK 0_TERM

VOLTAGE=0. 9V

FB_A1_VR EF_UNTER M_L

FB_A3_VR EF_UNTER M_L

FB_A_DQ< 35>

FB_A_MA< 7>

FB_A_RDQ S<5>

FB_A_DQM _L<7>

FB_VREF_ UNTERM

FB_A_UMA <2>

FB_A_UMA <4>

FB_A_DQ< 31>

FB_A_DQ< 28>

FB_A0_MF

FB_A_DQ< 5>

FB_A1_MF

FB_A_DQ< 43>

FB_A_DQ< 41>

FB_A_DQ< 54>

FB_A_MA< 10>

FB_A_UMA <3>

FB_A_MA< 0>

FB_A_MA< 6>

FB_A_MA< 8>

FB_A_DQ< 46>

FB_A_DQ< 45>

FB_A_DQ< 42>

FB_A_DQ< 55>

FB_A_DQ< 50>

FB_A_DQ< 48>

FB_A_DQ< 53>

FB_A_DQ< 52>

FB_A_DQ< 51>

FB_A_DQ< 49>

FB_A1_ZQ

FB_A_RAS _L

FB_A_CAS _L

FB_A_WE_ L

FB_A_CS0 _L

FB_A_CLK _N<1>

FB_A_CLK _P<1>

FB_A_MA< 12>

FB_A_CLK _P<0>

=PP1V8_G PU_FB_VD DQ

C8432

1

2

R8430

1

2

R8431

1

2

C8403

1

2

C8402

1

2

C8404

1

2

C8401

1

2

C8422

1

2

C8423

1

2

C8424

1

2

C8425

1

2

C8426

1

2

R8449

1

2

R8448

1

2

R8445

1

2

R8446

1

2

C8421

1

2

C8415

1

2

C8410

1

2

R8440

1

2

R8447

1

2

R8444

1

2

R8443

1

2

R8442

1

2

R8490

1

2

R8492

1

2

C8471

1

2

C8472

1

2

R8498

1

2

R8499

1

2

R8493

1

2

R8495

1

2

R8494

1

2

R8497

1

2

R8496

1

2

C8473

1

2

C8474

1

2

C8475

1

2

C8476

1

2

C8451

1

2

C8452

1

2

C8460

1

2

C8453

1

2

C8465

1

2

C8454

1

2

C8400

1

2

C8420

1

2

C8450

1

2

C8470

1

2

C8446

1

2

C8496

1

2

R8432

1

2

C8481

1

2

R8482

1

2

R8480

1

2

R8481

1

2

Q8400

6

2

1

Q8450

6

2

1

R8435

1

2

R8433

1

2

R8434

1

2

C8431

1

2

Q8400

3

5

4

C8482

1

2

R8485

1

2

R8483

1

2

R8484

1

2

Q8450

3

5

4

U8450

K9

H11

K11

L9

J3

K10

M9

K4

H2

K3

L4

K2

M4

G9

G4

H3

F9

J11

J10

H9

F4

E3

E10

N10

N3

B2

B3

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

C2

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

C3

T2

T3

E2

F3

F2

G3

B11

B10

A9

H10

D3

D10

P10

P3

V9

J2

V4

D2

D11

P11

P2

H4

A4

U8400

K9

H11

K11

L9

J3

K10

M9

K4

H2

K3

L4

K2

M4

G9

G4

H3

F9

J11

J10

H9

F4

E3

E10

N10

N3

B2

B3

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

C2

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

C3

T2

T3

E2

F3

F2

G3

B11

B10

A9

H10

D3

D10

P10

P3

V9

J2

V4

D2

D11

P11

P2

H4

A4

U8400

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4

E9

E12

H1

H12

A3

A10

G1

G12

L1

L12

V3

V10

J1

J12

B1

B4

L2

L11

P1

P4

P9

P12

T1

T4

T9

T12

B9

B12

D1

D4

D9

D12

G2

G11

U8450

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4

E9

E12

H1

H12

A3

A10

G1

G12

L1

L12

V3

V10

J1

J12

B1

B4

L2

L11

P1

P4

P9

P12

T1

T4

T9

T12

B9

B12

D1

D4

D9

D12

G2

G11

74 74 73

74 74

73

9

73 73

9 8

8 8

9 9

8

IN

BI

IN

OUT

IN

OUT

IN

BI

IN

BI

IN

IN IN

D

SG

D

SG

D

SG

D

SG

ININ

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ7

DQ10

DQ11

DQ12

DQ13

DQ15

DQ16

DQ18

DQ19

DQ21

DQ23

DQ22

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

A3

A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5

A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ7

DQ10

DQ11

DQ12

DQ13

DQ15

DQ16

DQ18

DQ19

DQ21

DQ23

DQ22

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

A3

A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5

A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

(1 OF 2)

MFHIGH

VDD0

VDD1

VDD4

VDD3

VDD2

VSS6

VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0

VSSA1

VDDA0

VDDA1

VDD7

VDD6

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ16

VDDQ17

VDDQ18

VDDQ19

VDDQ20

VDDQ21

VSSQ0

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ15

VSSQ16

VSSQ17

VSSQ18

VSSQ19

VREF0

VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

VDD0

VDD1

VDD4

VDD3

VDD2

VSS6

VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0

VSSA1

VDDA0

VDDA1

VDD7

VDD6

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ16

VDDQ17

VDDQ18

VDDQ19

VDDQ20

VDDQ21

VSSQ0

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ15

VSSQ16

VSSQ17

VSSQ18

VSSQ19

VREF0

VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

BI

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

VRAM4

Connect to desig nated pi n, then GND

U8500.J12

U8500.J1

U8500.J12

(NONE)

U8500.J1

Connect to desig nated pi n, then GND

BOM opti ons prov ided by this pag e:

Signal a liases r equired by this page:

- =PP1V8 _S0_FB_V DD

Power al iases re quired b y this p age:

Page Notes

- =PP1V8 _S0_FB_V REF_B

0.1uF

16V

10%

X5R 402

16V

10%

402

X5R

0.1uF 0.1uF

16V

402

X5R

10%

0.1uF

402

16V

10%

X5R

16V

10%

402

X5R

0.1uF

16V

10%

402

X5R

0.1uF

16V

10%

402

X5R

0.1uF

16V

10%

402

X5R

0.1uF

10%

X5R

0.1uF

402

16V

1/16W

5%

402

MF-LF

100

1/16W

1%

402

MF-LF

243

402

16V

10%

X5R

0.1uF

16V

10%

402

X5R

0.1uF

16V

10%

402

X5R

0.1uF

72 94

72 74 94

72 94

72 74 94

72 94

72 74 94

72 94

72 74 94

72 94

72 74 94

72 94

72 74 94

72 94

72 74 94

72 94

72 74 94

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

1%

243

MF-LF

402

1/16W

100

402

1/16W MF-LF

5%

10%

402

X5R

16V

0.1uF

16V

10%

402

X5R

0.1uF

16V X5R 402

10%

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

0.1uF

X5R 402

10% 16V

16V

10%

402

X5R

0.1uF

16V

10%

402

X5R

0.1uF

16V

10%

402

X5R

0.1uF

X5R 402

10% 16V

72 94

10UF

603

X5R

6.3V

20%

10UF

603

X5R

6.3V

20%

10UF

603

20%

6.3V X5R

10UF

603

X5R

6.3V

20%

MF-LF

1/16W

402

1%

243

1/16W

402

MF-LF

1%

243

121

VRAM4

1/16W

1%

MF-LF

402

VRAM4

MF-LF 402

1% 1/16W

121

VRAM4

402

MF-LF

121

1%

1/16W

402

5%

MF-LF

1/16W

1K

VRAM4

MF-LF

1%

121

402

1/16W

1%

1/16W

402

MF-LF

243

1/16W

402

MF-LF

1%

243

402

VRAM4

MF-LF

121

1% 1/16W

VRAM4

402

1%

121

MF-LF

1/16W

402

121

VRAM4

1%

MF-LF

1/16W

MF-LF

1%

VRAM4

1/16W

121

402

1/16W

1K

5%

MF-LF

16V

10%

402

0.01UF

CERM

0.01UF

CERM

402

10% 16V

402

1/16W

1%

MF-LF

1.33K

1%

402

MF-LF

1/16W

931

10% 16V

402

CERM

0.01uF

1/16W

1%

402

MF-LF

549

MF-LF

1%

1/16W

402

1.33K

1/16W

1%

MF-LF

402

931

402

1/16W

1%

549

MF-LF

10%

402

CERM

0.01uF

16V

72 73 74 76

SSM6N15F EAPE

SOT563

SSM6N15F EAPE

SOT563

CERM

0.01uF

402

10% 16V

1/16W

1%

402

MF-LF

931

MF-LF

402

1%

1/16W

549

1% 1/16W MF-LF

402

1.33K

SSM6N15F EAPE

SOT563

16V

0.01uF

CERM 402

10%

1/16W

1%

MF-LF

402

931

1/16W

1%

402

MF-LF

549

MF-LF

1%

1/16W

402

1.33K

SSM6N15F EAPE

SOT563

72 74 94 72 74 94

OMIT

CRITIC AL

BGA

K4J103 24QD-HC 11

32MX32- 900MHZ -MFH

K4J103 24QD-HC 11

32MX32- 900MHZ -MFH

OMIT

CRITIC AL

BGA

K4J103 24QD-HC 11

32MX32- 900MHZ -MFH

BGA

CRITIC AL

OMIT

BGA

32MX32- 900MHZ -MFH

K4J103 24QD-HC 11

CRITIC AL

OMIT

74 9 6

A.0.0

051-7546

SYNC_MAS TER=MUXG FX

SYNC_DAT E=07/10/ 2008

GDDR3 Frame Buffe r B (Top)

FB_B_DRA M_RST

FB_B_DQ< 58>

FB_B_DQ< 62>

FB_B_DQ< 61>

FB_B_DQ< 60>

FB_B_DQ< 56>

FB_B_DQ< 39>

FB_B_DQ< 38>

FB_B_DQ< 37>

FB_B_MA< 8>

FB_B_CLK _N<1>

FB_B_UMA <3>

FB_B_MA< 1>

FB_B_UMA <4>

FB_B_MA< 0>

FB_B1_MF

FB_B_MA< 7>

FB_B_DQ< 40>

FB_B_DQ< 54>

FB_B_DQ< 55>

FB_B_DQ< 53>

FB_B_DQ< 52>

FB_B_DQ< 41>

FB_B_DQ< 42>

FB_B_DQ< 47>

FB_B_DQ< 44>

FB_B_DQ< 45>

FB_B_DQ< 43>

FB_B_DQ< 46>

FB_B_DQ< 33>

FB_B_DQ< 35>

FB_B_DQ< 34>

FB_B_MA< 12>

FB_B_CKE

FB_B_WE_ L

FB_B_CS0 _L

FB_B_CLK _P<0>

FB_B_MA< 12>

FB_B_CKE

FB_B_RAS _L

FB_B_RDQ S<1>

FB_B_RDQ S<3>

FB_B_WDQ S<0>

FB_B0_SE N

FB_B0_ZQ

FB_B_WDQ S<1>

FB_B_WDQ S<2>

FB_B_WDQ S<3>

FB_B_BA< 0>

FB_B_BA< 2>

FB_B_DQ< 28>

FB_B_DQ< 31>

FB_B_DQ< 27>

FB_B_DQ< 26>

FB_B_DQ< 25>

FB_B_DQ< 30>

FB_B_DQ< 29>

FB_B_DQ< 24>

FB_B_DQ< 22>

FB_B_DQ< 20>

FB_B_DQ< 18>

FB_B_DQ< 23>

FB_B_DQ< 17>

FB_B_DQ< 15>

FB_B_DQ< 11>

FB_B_DQ< 13>

FB_B_DQ< 14>

FB_B_DQ< 3>

FB_B_DQ< 4>

FB_B_DQ< 0>

FB_B_DQ< 2>

FB_B0_MF

FB_B_RDQ S<2>

FB_B_DRA M_RST

FB_B_RDQ S<0>

FB_B_DQ< 5>

FB_B_DQ< 9>

FB_B_DQM _L<3>

FB_B_DQM _L<2>

FB_B_DQ< 12>

FB_B_DQ< 8>

FB_B_DQ< 10>

FB_B_DQ< 6>

FB_B_DQ< 21>

FB_B_DQ< 16>

FB_B_DQ< 19>

FB_B_DQM _L<1>

FB_B_CLK _N<0>

FB_B_MA< 11>

FB_B_CAS _L FB_B_DQ< 1>

FB_B_LMA <3>

FB_B_DQ< 7>

FB_B_LMA <5>

FB_B_LMA <4>

FB_B_MA< 9>

FB_B_MA< 6>

FB_B_MA< 7>

FB_B_LMA <2>

FB_B_MA< 8>

FB_B_DQM _L<0>

FB_VREF_ UNTERM

=PP1V8_G PU_FB_VR EF_B

=PP1V8_G PU_FB_VD DQ

=PP1V8_G PU_FB_VR EF_B

=PP1V8_G PU_FB_VD DQ

FB_B_DQM _L<4>

FB_B_DQ< 48>

=PP1V8_G PU_FB_VD D

VOLTAGE=0. 9V

FB_B_CLK 0_TERM

FB_B1_VR EF_UNTER M_L

FB_B_CLK 1_TERM

VOLTAGE=0. 9V

FB_VREF_ UNTERM

FB_B3_VR EF_UNTER M_L

FB_B2_VR EF FB_B3_VR EF

FB_B1_VR EFFB_B0_VR EF

FB_B0_VR EF_UNTER M_L

FB_B_UMA <5>

FB_B_MA< 10>

FB_B_CS0 _L

FB_B_CAS _L

FB_B_WE_ L

FB_B_BA< 0>

FB_B_DQM _L<6>

FB_B_DQ< 50>

FB_B_DQ< 49>

FB_B_DQM _L<7>

FB_B_DQM _L<5>

FB_B_DQ< 51>

FB_B_BA< 1>

FB_B_WDQ S<6>

FB_B_RDQ S<7>

FB_B_RDQ S<4>

FB_B_RDQ S<5>

FB_B_RDQ S<6>

FB_B1_SE N

FB_B1_ZQ

FB_B_RAS _L

FB_B_WDQ S<4>

FB_B_BA< 2>

FB_B_WDQ S<7>

FB_B_WDQ S<5>

FB_B_MA< 9>

FB_B_MA< 10>

FB_B_MA< 1>

FB_B_MA< 0>

FB_B_BA< 1>

=PP1V8_G PU_FB_VD D

FB_B_MA< 6>

FB_B_MA< 11>

FB_B_DQ< 32>

FB_B_DQ< 36>

FB_B_DQ< 57>

FB_B_DQ< 59>

FB_B_DQ< 63>

FB_B_CLK _P<1>

FB_B_UMA <2>

FB_B2_VR EF_UNTER M_L

C8503

1

2

C8502

1

2

C8504

1

2

C8501

1

2

C8522

1

2

C8523

1

2

C8524

1

2

C8525

1

2

C8526

1

2

R8549

1

2

R8548

1

2

C8521

1

2

C8515

1

2

C8510

1

2

C8571

1

2

C8572

1

2

R8598

1

2

R8599

1

2

C8573

1

2

C8574

1

2

C8575

1

2

C8576

1

2

C8551

1

2

C8552

1

2

C8560

1

2

C8553

1

2

C8565

1

2

C8554

1

2

C8500

1

2

C8520

1

2

C8550

1

2

C8570

1

2

R8546

1

2

R8547

1

2

R8544

1

2

R8545

1

2

R8542

1

2

R8540

1

2

R8543

1

2

R8596

1

2

R8597

1

2

R8595

1

2

R8594

1

2

R8592

1

2

R8593

1

2

R8590

1

2

C8596

1

2

C8546

1

2

R8531

1

2

R8532

1

2

C8531

1

2

R8530

1

2

R8581

1

2

R8582

1

2

R8580

1

2

C8581

1

2

Q8500

6

2

1

Q8550

6

2

1

C8532

1

2

R8535

1

2

R8533

1

2

R8534

1

2

Q8500

3

5

4

C8582

1

2

R8585

1

2

R8583

1

2

R8584

1

2

Q8550

3

5

4

U8550

K9

H11

K11

L9

J3

K10

M9

K4

H2

K3

L4

K2

M4

G9

G4

H3

F9

J11

J10

H9

F4

E3

E10

N10

N3

B2

B3

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

C2

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

C3

T2

T3

E2

F3

F2

G3

B11

B10

A9

H10

D3

D10

P10

P3

V9

J2

V4

D2

D11

P11

P2

H4

A4

U8500

K9

H11

K11

L9

J3

K10

M9

K4

H2

K3

L4

K2

M4

G9

G4

H3

F9

J11

J10

H9

F4

E3

E10

N10

N3

B2

B3

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

C2

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

C3

T2

T3

E2

F3

F2

G3

B11

B10

A9

H10

D3

D10

P10

P3

V9

J2

V4

D2

D11

P11

P2

H4

A4

U8500

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4

E9

E12

H1

H12

A3

A10

G1

G12

L1

L12

V3

V10

J1

J12

B1

B4

L2

L11

P1

P4

P9

P12

T1

T4

T9

T12

B9

B12

D1

D4

D9

D12

G2

G11

U8550

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4

E9

E12

H1

H12

A3

A10

G1

G12

L1

L12

V3

V10

J1

J12

B1

B4

L2

L11

P1

P4

P9

P12

T1

T4

T9

T12

B9

B12

D1

D4

D9

D12

G2

G11

74 74 73 73

74 74

74

9

74

9

73 73

9

8

9

8

8 8

HDA_BCLK

HDA_SYNC

HDA_SDO

HDA_RST*

SPDIF

BUFRST*

JTAG_TMS

MIOA_CLK IN

MIOA_CLK OUT

JTAG_TCK

GPIO20

GPIO23

HDA_SDI

MIOA_D8

MIOA_D10

MIOA_D9

JTAG_TDI

GPIO2

GPIO11

GPIO7

GPIO5

GPIO4

GPIO3

GPIO1

GPIO0

MIOB_VDD Q_4

MIOB_VDD Q_2

GPIO21

GPIO18

GPIO15

GPIO16

GPIO17

GPIO9

GPIO10

GPIO12

GPIO13

GPIO14

GPIO19

JTAG_TDO

JTAG_TRS T*

MIOA_CTL 3

MIOA_D7

MIOA_D6

MIOA_D5

MIOA_D4

MIOA_D3

MIOA_D2

MIOA_D1

MIOA_DE

MIOB_CAL _PD_VDDQ

GPIO6

GPIO8

MIOA_D11

MIOA_D12

MIOA_D13

MIOB_D9

MIOB_D8

MIOB_D7

MIOB_D5

MIOB_D6

MIOB_D3

MIOB_D0

MIOB_DE

MIOB_CLK OUT*

MIOB_CTL 3

MIOB_CLK OUT

MIOB_CLK IN

MIOB_D11

MIOB_D12

MIOB_D13

MIOB_D14

MIOB_D16

MIOB_D17

MIOB_D15

MIOB_HSY NC

MIOB_VSY NC

THERMDP

THERMDN

PGOOD_OU T*

XTAL_IN

XTAL_OUT

XTAL_OUT BUFF

MIOB_D10

MIOB_D4

MIOB_D2

MIOB_D1

MIOA_VSY NC

MIOA_HSY NC

MIOA_D14

MIOA_CLK OUT*

MIOA_D0

MIOB_CAL _PU_GND

MIOB_VDD Q_3

MIOA_VDD Q_3

MIOA_VDD Q_4

MIOA_VDD Q_2

GPIO22

RFU1

ROM_CS*

ROM_SCLK

ROM_SO

STRAP_RE F_3V3

STRAP_RE F_MIOB

VDD33_5

VDD33_1

VDD33_2

VDD33_3

VDD33_4

RFU1_GND

RFU0

RFU0_GND

ROM_SI

MIOA_VDD Q_1

MIOB_VDD Q_1

MIOA_CAL _PU_GND

MIOA_CAL _PD_VDDQ

MIOA_VRE F

MIOB_VRE F

TESTMODE

SP_PLLVD D

PLLVDD

VID_PLLV DD

XTAL_SSI N

SYMBOL 6 OF 9

BI

OUT

IN

OUT

IN

OUT

IN

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

110mA

- =PP3V3 _GPI_MIO

(IPD)

(NONE)

BOM opti ons prov ided by this pag e:

(NONE)

- =PP1V2 _GPU_H_P LLVDD

- =PP3V3 _GPU_VDD 33

Page Notes

Power al iases re quired b y this p age:

- =PP1V2 _GPU_PLL VDD

- =PP1V2 _GPU_VID _PLLVDD

Signal a liases r equired by this page:

Typicall y <??mA

65mA

25mA

50mA

402

MF-LF

1/16W

1%

40.2K

402

10%

CERM-X5R

6.3V

0.47UF 0.47UF

10%

CERM-X5R 402

6.3V

0.1uF

402

16V X5R

10%20%

6.3V

603

4.7UF

CERM

FERR-220 -OHM

0402

FERR-220 -OHM

16V X5R 402

10%

0.1uF

MF-LF

1/16W

10K

5%

402

MF-LF

1/16W

402

10K

5%

MF-LF

49.9

1%

402

1/16W

MF-LF

402

1%

49.9

1/16W

402

MF-LF

1/16W

1%

49.9

16V X5R 402

10%

0.1uF

1/16W

402

MF-LF

5%

10K

402

MF-LF

1/16W

10K

5%

6.3V

402

1UF

10%

CERMCERM

10%

1UF

6.3V

402

MF-LF

1%

49.9

1/16W

0.1uF

16V

402

X5R

10%20%

6.3V CERM

603

4.7UF

0402

FERR-220 -OHM

20%

6.3V CERM

603

4.7UF

402

16V X5R

10%

0.1uF4.7U F

20%

6.3V

603

CERM

4.7UF

CERM

6.3V

20%

603

20%

4.7UF

603

CERM

6.3V

402

10%

6.3V

0.47UF

CERM-X5R

NB9P-GS

OMIT

BGA

402

MF-LF

1/16W

1%

40.2K

1/16W MF-LF 402

10K

5%

10%

0.022UF

402

CERM-X5R

16V

CERM-X5R

16V

10%

0.022UF

402

0.1UF

CERM

10V

20%

402

0.022UF

CERM-X5R

10% 16V

402

0.022UF

CERM-X5R

10% 16V

402

CERM 402

10V

20%

0.1UF

0.47UF

10%

6.3V CERM-X5R 402

0.47UF

10%

6.3V CERM-X5R 402 402

CERM

1UF

6.3V

10%

76

6

76

SYNC_MAS TER=MUXG FX

NV G96 GPIO/MIO/Misc

75

SYNC_DAT E=07/10/ 2008

96

051-7546

A.0.0

GPU_JTAG _TMS

GPU_JTAG _TRST_L

=PP3V3 _GPU_V DD33

GPU_ROM_ CS_L

GPU_ROM_ SCLK

GPU_ROM_ SI

GPU_ROM_ SO

GPU_STRA P_REF_3V 3_PD

GPU_STRA P_REF_MI OB_PD

=PP3V3_G PU_MIO

GPU_XTAL IN

GPU_XTAL OUTBUFF

GPU_XTAL SSIN

GPU_XTAL OUT

PP1V1_GP U_VID_PL LVDD_F

VOLTAGE=1.2 V

MIN_LINE_WI DTH=0.2 mm MIN_NECK_WI DTH=0.2 mm

PP1V1_GP U_PLLVDD _F

MIN_LINE_WI DTH=0.2 mm

VOLTAGE=1.2 V

MIN_NECK_WI DTH=0.2 mm

PP1V1_GP U_H_PLLV DD_F

MIN_NECK_WI DTH=0.2 mm VOLTAGE=1.2 V

MIN_LINE_WI DTH=0.2 mm

=PP3V3_G PU_VDD33

GPU_MIOB _VSYNC

GPU_MIOB _HSYNC

GPU_MIOB _D<14>

GPU_STRA P<1>

GPU_THER MD_P

GPU_THER MD_N

TP_GPU_P GOOD_OUT _L

GPU_GPIO _19

GPU_GPIO _20

GPU_GPIO _21

GPU_GPIO _22

GPU_GPIO _23

GPU_HDA_ BCLK

GPU_SPDI F

GPU_GPIO _12

GPU_GPIO _13

GPU_GPIO _14

GPU_GPIO _15

GPU_GPIO _18

GPU_JTAG _TDO

GPU_MIOA _CTL3

GPU_MIOA _D<1>

GPU_MIOA _D<9>

GPU_MIOA _D<7>

GPU_MIOB _D<10>

GPU_MIOB _D<13>

GPU_MIOB _PU_GND

GPU_MIOB _PD_VDDQ

GPU_MIOA _PU_GND

GPU_MIOA _PD_VDDQ

GPU_TES TMODE_PD

GPU_MIOB _D<11>

GPU_MIOB _D<12>

GPU_STRA P<0>

GPU_STRA P<2>

GPU_MIOB _CLKIN

GPU_MIOA _CLKIN

GPU_JTAG _TDI

GPU_JTAG _TCK

GPU_GPIO _17

GPU_HDA_ SDI

GPU_HDA_ SDO

TP_GPU_B UFRST_L

GPU_HDA_ RST_L

GPU_HDA_ SYNC

GPU_MIOB _CLKOUT_ N

GPU_MIOB _CTL3

GPU_MIOB _DE

GPU_MIOB _D<0>

GPU_MIOB _D<1>

GPU_MIOB _D<2>

GPU_MIOB _D<3>

GPU_MIOB _D<4>

GPU_MIOB _D<5>

GPU_MIOB _D<6>

GPU_MIOB _D<7>

GPU_MIOB _D<8>

GPU_MIOB _D<9>

GPU_MIOB _CLKOUT_ P

GPU_MIOA _DE

GPU_MIOA _D<0>

GPU_MIOA _D<2>

GPU_MIOA _D<3>

GPU_MIOA _D<6>

GPU_MIOA _CLKOUT_ N

GPU_MIOA _D<4>

GPU_MIOA _D<5>

GPU_MIOA _D<8>

GPU_MIOA _D<10>

GPU_MIOA _D<11>

GPU_MIOA _D<12>

GPU_MIOA _D<13>

GPU_MIOA _D<14>

GPU_MIOA _HSYNC

GPU_MIOA _VSYNC

GPU_MIOA _CLKOUT_ P

GPU_GPIO _16

GPU_GPIO _2

GPU_GPIO _3

GPU_GPIO _4

GPU_GPIO _5

GPU_GPIO _6

GPU_GPIO _7

GPU_GPIO _8

GPU_GPIO _9

GPU_GPIO _10

GPU_GPIO _11

GPU_GPIO _0

GPU_GPIO _1

GPU_MIOA _VREF

=PP3V3_G PU_MIO

=PP1V1_G PU_PLLVD D

GPU_MIOB _PD_VDDQ

GPU_MIOA _PD_VDDQ

GPU_MIOB _PU_GND

=PP1V1_G PU_H_PLL VDD

=PP1V1_G PU_VID_P LLVDD

GPU_MIOA _PU_GND

GPU_MIOB _VREF

R8697

1

2

C8601

1

2

C8602

1

2

C8636

1

2

C8635

1

2

L8635

1 2

L8640

1 2

C8617

1

2

R8616

1

2

R8617

1

2

R8620

1

2

R8622

1

2

R8621

1

2

C8619

1

2

R8618

1

2

R8619

1

2

C8611

1

2

C8610

1

2

R8623

1

2

C8631

1

2

C8630

1

2

L8630

1 2

C8633

1

2

C8641

1

2

C8640

1

2

C8643

1

2

C8637

1

2

C8600

1

2

U8000

A4

K1

K2

K4

K5

H7

J4

J6

L1

L2

L4

M4

L7

K3

L5

K6

L6

M6

H3

H2

H1

H4

H5

H6

J7

D7

D6

C7

B7

A7

AP14

AN14

AN16

AR14

AP16

U5

T5

N4

R4

T4

P5

N1

P4

U2

U3

R6

T6

N6

P1

P2

P3

T3

T2

T1

U4

U1

N2

N3

P9

R9

T9

U9

N5

L3

AA7

AA6

AE1

V4

W4

W3

Y1

Y2

AE3

AE2

U6

W6

Y6

W5

W7

V7

Y3

AB3

AB2

AB1

AC4

AC1

AC2

AC3

Y5

W1

AA9

AB9

W9

Y9

AF1

W2

C5

AE9

J25

AK14

J26

K9

C3

D4

D3

C4

AF9

A5

N9

M9

AP35

B4

B5

J9

J10

J11

J12

J13

AD9

B1

B2

D1

D2

R8696

1

2

R8660

1

2

C8691

1

2

C8693

1

2

C8695

1

2

C8690

1

2

C8692

1

2

C8694

1

2

C8697

1

2

C8696

1

2

C8698

1

2

76

75

76

75

76

8

75

8

75

6

76

8

6

75

8

75

8

75

www.laptop-schematics.com

OUT

IN

NC

D

GS

IN

BI

OUT

IN

OUT

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

(I2CS req uires pul lups even if not u sed)

I2CS ties into SMB us connec tion page

RAMCFG [0]

TVMODE [1]

G96 HDCP ROM APN i s 341S227 2, blank device is 335S0574 .

GPU 27MHz Crystal

D 1101 PU 30 k

4 0100 PD 25 k

3 0011 PD 20 k

5 0101 PD 30 k

7 0111 PD 45 k

LCD0_BL_ PWM

LCD0_VDD

VID0

VID2/MEM _VID

THERM

Native F unc

ROM_SC LK

ROM_SI

STRAP 2

STRAP 1

STRAP 0

6 0110 PD 35 k

Config Straps

RAMCFG [3]

USER[3 ]

Strap S1/S2 Bit[3:0 ] PU/P D Rval

F 1111 PU 45 k

2 0010 PD 15 k

RAMCFG [2]

B 1011 PU 20 k

9 1001 PU 10 k

XCLK_2 77

GP

LCD0_BL_ EN

HPDE

GP

Unused Clocks

Unused signals

DVI_MODE 0

G96 MIOA_ DE and MI OA_D<9..0 > are use d as Debu g Port.

GPIOs

HPDF

SWAPRDY_ A

Isolation FETs for DP MUX inputs

PWR_CTL1

HPDD

HDMI_DET ECT1

HDMI_DET ECT0

PEX_PL LEN_TE RM100

PCI_DE VID[0]

3GIO_P ADCFG[ 0]

USER[0 ]

TVMODE [0]

Strapp ing Bi t 0

PCI_DE VID[1]

SLOT_C LK_CFG

Strapp ing Bi t 1

USER[1 ]

ROM_SO

HPDC

Renamed signals

Unused I2C Buses

PWR_CTL0

AC_DET

FAN_PWM

VID1

RAMCFG [1]

0 0000 PD 5k

Physic al

Native F unc

3GIO_P ADCFG[ 3]

PCI_DE VID[3]

E 1110 PU 35 k

C 1100 PU 25 k

A 1010 PU 15 k

8 1000 PU 5k

USER[2 ]

3GIO_P ADCFG[ 2]

PCI_DE VID[4]

DVI_MODE 1

SLI_SYNC

MEM_VREF

GPIOs

PCI_DE VID[2]

Strap S1/S2 Bit[3:0 ] PU/P D Rval

3GIO_P ADCFG[ 1]

SUB_VE NDOR

TVMODE [2]

Strapp ing Bi t 2Strapp ing Bi t 3

1 0001 PD 10 k

Strapp ing Pi n

1/16W MF-LF

GPU_SS_I NT

10K

5%

402

MF-LF

1/16W

5%

402

10K

78

75 76

76 94

5%

402

1/16W MF-LF

0

50V

402

CERM

5%

12pF

CERM

402

5%

12pF

50V

27MHZ

SM-2

CRITIC AL

NO STU FF

MF-LF

1/16W

402

5%

10M

1%

1/16W

45.3K

OMIT

402

MF-LF

1/16W

2.0K

5%

402

MF-LF

15.0K

MF-LF

1/16W

1%

402

1/16W

2.0K

NO STUFF

MF-LF

5%

OMIT

MF-LF

402

5%

2.0K

1/16W

NO STUFF

1/16W

402

1%

MF-LF

4.99K

1% 1/16W MF-LF

402

4.99K

NO STUFF

MF-LF

10K

402

1%

1/16W

45.3K

1/16W

1%

MF-LF

402

1%

MF-LF

45.3K

1/16W

402

NO STUFF

10K

1%

MF-LF

1/16W

MF-LF

402

1/16W

10K

1%

NO STUFF

DP_CA_DE T_EG_FET

SOD-VESM- HF

SSM3K1 5FV

DP_CA_DE T_EG_FET

100K

1% 1/16W MF-LF

402

80 81 83

80

MF-LF

5%

402

4.7K

1/16W 1/16W

5%

4.7K

MF-LF

402

1/16W

5%

4.7K

402

MF-LF

1/16W

5%

4.7K

MF-LF

402

76 80

9

80

76 80

9

80

75

DP_CA_DE T_EG_PLD

402

0

MF-LF

1/16W

5%

83

MF-LF

4025%01/16W

MF-LF

4025%01/16W

42

78

402

MF-LF

1/16W

2.2K

5%

402

MF-LF

1/16W

2.2K

5%

76 83

76 82

72 73 74 76

402

MF-LF

NO STUFF

1K

5%

1/16W

402

MF-LF

1K

1/16W

5%

402

MF-LF

1K

5%

1/16W

402

MF-LF

1K

1/16W

5%

R8708

114S0331

RES,MTL FILM ,1/16W,15.0K ,1,0402,SMD,L F

1

VRAM_256_H YNIX

VRAM_1024_ SAMSUNG

RES,MTL FILM ,1/16W,45.3K ,1,0402,SMD,L F

R8707

1

114S0378

114S0361

R8707

RES,MTL FILM ,1/16W,30.1K ,1,0402,SMD,L F

VRAM_1024_ QIMONDA

1

VRAM_256_S AMSUNG

R8708

114S0343

1

RES,MTL FILM ,1/16W,20.0K ,1,0402,SMD,L F

VRAM_512_Q IMONDA

RES,MTL FILM ,1/16W,30.1K ,1,0402,SMD,L F

R8708

1

114S0361

VRAM_512_S AMSUNG

RES,MTL FILM ,1/16W,45.3K ,1,0402,SMD,L F

1

R8708

114S0378

G96 GPIOs & Straps

SYNC_MAS TER=MUXG FX

A.0.0

051-7546

SYNC_DAT E=07/09/ 2008

9676

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_GPU_I 2CH_SCL

GPU_I2CH _SCL

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_I 2CE_SCL

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_I 2CE_SDA

GPU_I2CH _SDA

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_GPU_I 2CH_SDA

GPU_GPIO _0

GPU_GPIO _4

GPU_GPIO _3

GPU_GPIO _5

GPU_GPIO _6

GPU_GPIO _7

GPU_GPIO _8

GPU_GPIO _9

GPU_GPIO _11

GPU_GPIO _12

GPU_GPIO _21

GPU_VCOR E_VID2

MAKE_BASE=T RUE

GPU_STRA P<1>

GPU_STRA P<2>

=PP3V3 _GPU_V DD33

=PP3V3 _GPU_M IO

DP_EG_DD C_DATA

DP_EG_DD C_CLK

=PP3V3 _GPU_V DD33

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_GPU_I 2CD_SCL

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOB_CLKI N

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_GPU_M IOB_CTL3

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOB_VSYN C

GPU_XTAL OUTBUFF

GPU_CL K27M_X TALOUT_ R

MAKE_BASE=T RUE

LVDS_EG_ DDC_DATA

GPU_THER MD_N

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOB_CLKO UT_P

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOB_D<14 ..0>

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOB_CLKO UT_N

GPU_XTAL SSIN

GPU_MIOB _D<14..0 >

GPU_MIOB _VSYNC

GPU_MIOB _HSYNC

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOB_HSYN C

GPU_MIOB _CLKOUT_ P

GPU_MIOB _CLKOUT_ N

GPU_MIOB _DE

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOB_DE

GPU_MIOB _CTL3

GPU_MIOB _CLKIN

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_I 2CD_SDA

MAKE_BASE=T RUE

GPU_TDIO DE_N

MAKE_BASE=T RUE

GPU_TDIO DE_P

MAKE_BASE=T RUE

GPU_XTAL OUT

MAKE_BASE=T RUE

GPU_CLK2 7M

MAKE_BASE=T RUE

GPU_CLK2 7M_SS

GPU_MIOA _D<9..0>

GPU_MIOA _D<14..1 0>

GPU_MIOA _CLKIN

GPU_MIOA _CLKOUT_ P

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOA_CLKO UT_P

GPU_MIOA _CLKOUT_ N

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_GPU_M IOA_CLKO UT_N

GPU_MIOA _CTL3

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_GPU_M IOA_CTL3

GPU_MIOA _DE

GPU_MIOA _HSYNC

GPU_MIOA _VSYNC

NC_FBA_M A<13>

MAKE_BASE=T RUE

NO_TEST=TRU E

TP_FBA_C MD28

TP_FBC_C MD28

GPU_HDA_ SDO

GPU_HDA_ SYNC

GPU_HDA_ BCLK

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_CPU_ HDA_BCLK

GPU_HDA_ RST_L

MAKE_BASE=T RUE

NC_CPU_ HDA_RST_ L

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_FBA_C MD30

NO_TEST=TRU E

GPU_SPDI F

NO_TEST=TRU E

NC_GPU_S PDIF

MAKE_BASE=T RUE

GPU_HDA_ SDI

MAKE_BASE=T RUE

LVDS_EG_ DDC_CLK

GPU_XTAL SSIN

FB_A_CS1 _L

FB_B_CS1 _L

LVDS_EG_ A_DATA_N <3>

GPU_I2CD _SDA

TP_FBA_C MD30

TP_FBC_C MD29

TP_FBA_C MD29

LVDS_EG_ A_DATA_P <3>

GPU_ROM_ CS_L

TP_FBC_C MD30

FB_B_MA< 13>

FB_A_MA< 13>

LVDS_EG_ B_CLK_N

LVDS_EG_ B_CLK_P

LVDS_EG_ B_DATA_P <3>

LVDS_EG_ B_DATA_N <3>

GPU_I2CC _SDA

GPU_CLK2 7M

MAKE_BASE=T RUE

DP_EG_DD C_CLK

GPU_I2CB _SCL

NC_FBC_C MD30

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_R OM_CS_L

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_FB_A_ CS1_L

NO_TEST=TRU E

NC_FB_B_ CS1_L

MAKE_BASE=T RUE

NO_TEST=TRU E

GPU_I2CE _SDA

GPU_I2CE _SCL

GPU_I2CD _SCL

MAKE_BASE=T RUE

DP_EG_DD C_DATA

MAKE_BASE=T RUE

NC_FBC_C MD29

NO_TEST=TRU E

TP_LVDS_ EG_B_CLK _P

MAKE_BASE=T RUE

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_LVDS_ EG_B_DAT A_N<3>

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOA_D<14 ..10>

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOA_VSYN C

NC_GPU_G PIO_20

MAKE_BASE=T RUE

NC_GPU_G PIO_17

MAKE_BASE=T RUE

NC_GPU_G PIO_18

MAKE_BASE=T RUE

NC_GPU_G PIO_21

GPU_ROM_ SI

MAKE_BASE=T RUE

NC_GPU_G PIO_15

EG_DP_C A_DET

GPU_GPIO _19

GPU_STRA P<0>

DP_CA_ DET

DP_CA_DE T_EG

EG_DP_ CA_DET

GPU_GPIO _20

MAKE_BASE=T RUE

NC_GPU_G PIO_22

NC_GPU_G PIO_23

MAKE_BASE=T RUE

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_LVDS_ EG_A_DAT A_P<3>

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_LVDS_ EG_B_DAT A_P<3>

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_LVDS_ EG_A_DAT A_N<3>

TP_LVDS_ EG_B_CLK _N

MAKE_BASE=T RUE

NC_FBA_C MD29

MAKE_BASE=T RUE

NO_TEST=TRU E

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_FBC_C MD28

NC_FBB_M A<13>

NO_TEST=TRU E

MAKE_BASE=T RUE

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_FBA_C MD28

NO_TEST=TRU E

NC_CPU_ HDA_SDI

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_CPU_ HDA_SD0

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_CPU_ HDA_SYNC

GPU_XTAL IN

GPU_XTAL OUT

GPU_THER MD_P

GPU_I2CA _SCL

GPU_I2CA _SDA

GPU_I2CB _SDA

GPU_I2CC _SCL

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_GPU_I 2CC_SCL

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_I 2CC_SDA

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_GPU_M IOA_HSYN C

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_GPU_M IOA_CLKI N

MAKE_BASE=T RUE

TP_GPU_M IOA_DE

MAKE_BASE=T RUE

TP_GPU_M IOA_D<9. .0>

=PP3V3 _GPU_M IO

TP_GPU_V CORE_VID 3

MAKE_BASE=T RUE

GPU_GPIO _23

SMC_GFX_ OVERTEMP _R_L

MAKE_BASE=T RUE

SMC_GFX_ THROTTLE _R_L

MAKE_BASE=T RUE

GPU_GPIO _14

GPU_GPIO _13

SMC_GFX_ OVERTEMP _L

GPU_GPIO _1

MAKE_BASE=T RUE

GPIO7_FB VDD_ALTV O

=PP3V3 _S0_DD C_LCD

DP_IG_DD C_DATA

DP_IG_DD C_CLK

MAKE_BASE=T RUE

FB_VREF_ UNTERM

GPU_GPIO _22

=PP3V3 _GPU_V DD33

GPU_GPIO _15

MAKE_BASE=T RUE

NC_GPU_G PIO_19

GPU_GPIO _18

GPU_GPIO _17

GPU_GPIO _16

GPU_ROM_ SO

GPU_ROM_ SCLK

GPU_GPIO _2

TP_GPU_G STATE<0>

MAKE_BASE=T RUE

EG_BKLT_ EN

MAKE_BASE=T RUE

EG_LCD_P WR_EN

MAKE_BASE=T RUE

TP_LVDS_ EG_BKL_P WM

MAKE_BASE=T RUE

DP_EG_HP D

NC_GPU_G PIO_0

MAKE_BASE=T RUE

TP_GPU_G STATE<1>

MAKE_BASE=T RUE

SMC_GFX_ THROTTLE _L

EG_BKLT_ EN

GPIO7_FB VDD_ALTV O

FB_VREF_ UNTERM

EG_LCD_P WR_EN

SMC_GFX_ OVERTEMP _R_L

SMC_GFX_ THROTTLE _R_L

GPU_XTAL OUT

GPU_VCOR E_VID1

MAKE_BASE=T RUE

GPU_VCOR E_VID0

GPU_GPIO _10

R8781

1

2

R8780

1

2

R8783

1 2

C8780

1 2

C8781

1 2

Y8780

2 4

1 3

R8782

1

2

R8708

1

2

R8710

1

2

R8712

1

2

R8702

1

2

R8707

1

2

R8709

1

2

R8711

1

2

R8704

1

2

R8706

1

2

R8701

1

2

R8703

1

2

R8705

1

2

Q8742

3

1

2

R8742

1

2

R8750

1

2

R8751

1

2

R8752

1

2

R8753

1

2

R8743

1 2

R8798

1 2

R8799

1 2

R8797

1

2

R8796

1

2

R8795

1

2

R8794

1

2

R8793

1

2

R8792

1

2

76

75

76

75

76

79

74

75

8

75

8

76

95

76

94

76

80

76

75

82

8

73

8

83

77

75

6

8

6

75

80

75

48

75

76

94

75

72

75

80

75

72

77

72

77

75

72

77

76 77

77

76

75

76

75

77

8

75

76

75

76

7

72

75

6

75

76

75

www.laptop-schematics.com

OUT

IFPB_TXC *

I2CD_SDA

I2CB_SCL

I2CS_SDA

I2CS_SCL

I2CC_SCL

I2CC_SDA

IFPEF_RS ET

I2CA_SDA

DACB_RSE T

DACC_VSY NC

DACC_HSY NC

DACC_BLU E

DACC_GRE EN

DACC_RED

DACB_CSY NC

DACB_BLU E

DACB_GRE EN

DACB_RED

DACA_VSY NC

DACA_RED

IFPF_L0*

IFPF_L0

IFPF_AUX *

IFPF_AUX

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

IFPE_AUX

IFPD_L3*

IFPD_L3

IFPD_L2*

IFPD_L2

IFPD_L0*

IFPD_AUX *

IFPC_L3*

IFPC_L2*

IFPC_L0*

IFPC_AUX *

IFPB_TXD 7*

IFPB_TXD 7

IFPB_TXD 6*

IFPB_TXD 5

IFPB_TXD 4*

IFPA_TXD 2*

IFPA_TXD 2

DACC_VRE F

DACC_RSE T

DACC_VDD

DACB_VDD

DACA_VDD

DACA_VRE F

DACA_RSE T

DACA_HSY NC

DACA_GRE EN

DACA_BLU E

IFPF_L1

IFPF_L1*

IFPF_L2

IFPF_L3

IFPF_L2*

IFPF_L3*

IFPE_AUX *

IFPD_L0

IFPD_L1

IFPD_L1*

IFPC_L3

IFPC_L2

IFPC_L1

IFPC_L0

IFPB_TXD 6

IFPB_TXD 4

IFPB_TXC

IFPA_TXD 3*

IFPA_TXD 3

IFPA_TXD 1

IFPA_TXD 1*

IFPA_TXD 0

IFPA_TXD 0*

IFPA_TXC *

IFPA_TXC

I2CA_SCL

IFPCD_RS ET

IFPC_AUX

I2CE_SDA

I2CE_SCL

I2CD_SCL

I2CB_SDA

I2CH_SCL

IFPC_L1*

I2CH_SDA

IFPD_AUX

IFPB_TXD 5*

IFPEF_PL LVDD

IFPAB_PL LVDD

IFPAB_RS ET

IFPF_IOV DD

IFPE_IOV DD

IFPD_IOV DD

IFPC_IOV DD

IFPB_IOV DD

IFPA_IOV DD

DACB_VRE F

IFPCD_PL LVDD

SYMBOL 5 OF 9

OUT

NC NC

NC NC NC NC NC NC NC NC

NC NC

NC NC NC NC NC NC NC NC

NC NC

NC NC NC NC NC NC NC NC

NC NC NC

NC NC

NC NC NC

NC

NC NC NC

NC NCNC

NC

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Page Notes

Power al iases re quired b y this p age:

- =PP3V3 _GPU_IFP CD_IOVDD

Signal a liases r equired by this page:

BOM opti ons prov ided by this pag e:

Place at AG10

I2CS mus t be pul led up i f not us ed

I2CS m ust be pulled up if not u sed.

Sum of p eak curr ents: 24 0mA

Power in puts mus t be pul led down if not used

I2CS add r fixed at 0x9E, 0x9F

(NONE)

- =PP1V8 _GPU_IFP X

Place at AK8

I2CS a ddr fi xed at 0x9E,0 x9F

Place at AG9

?mA peak per dif f pair

?mA peak for all pairs

?mA peak per dif f pair

(NONE)

160mA pe ak

Place at AJ8

80mA pea k

?mA peak for all pairs

402

1%

1K

1/16W MF-LF

0402

FERR-220 -OHM

402

10V

CERM

0.1UF

20%

FERR-220 -OHM

0402

76

83 94

603

6.3V CERM

20%

4.7UF

5%

10K

MF-LF

1/16W

402

5%

10K

1/16W

402

MF-LF

5%

10K

1/16W MF-LF 402

6.3V

4.7UF

CERM

603

20%

CERM

402

10V

0.1UF

20%

603

6.3V CERM

20%

4.7UF

0402

FERR-220 -OHM

402

CERM

10V

20%

0.1UF

402

0.1UF

CERM

10V

20%20%

10V

402

CERM

0.1UF

4.7UF

20%

CERM

603

6.3V

0402

FERR-220 -OHM

20% 10V

402

CERM

0.1UF

BGA

NB9P-GS

OMIT

402

1K

1% 1/16W MF-LF

80 94

1/16W MF-LF

10K

5%

402402

1/16W

10K

MF-LF

5%

76

45

76

1K

NO STUFF

MF-LF 402

1/16W

5% 1/16W MF-LF 402

5%

1K

402

1%

1K

MF-LF

1/16W

SYNC_DAT E=07/10/ 2008

77 9 6

051-7546

A.0.0

SYNC_MAS TER=MUXG FX

NV G96 Video Interfaces

GPU_DACA _VDD

GPU_IFPE F_RSET

VOLTAGE=1.8 V

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.4 mm

PP1V8_GP U_IFPAB_ IOVDD_F

PP1V8_GP U_IFPEF_ PLLVDD_F

GPU_I2CC _SCL

VOLTAGE=1.8 V

MIN_NECK_WI DTH=0.2 mm

PP1V8_GP U_IFPAB_ PLLVDD_F

MIN_LINE_WI DTH=0.3 mm

PP1V1_GP U_IFPEF_ IOVDD_F

GPU_DACB _VDD

=PP1V8_G PU_IFPX

DP_EG_AU X_CH_P

DP_EG_AU X_CH_N

LVDS_EG_ B_DATA_P <2>

LVDS_EG_ B_DATA_N <2>

LVDS_EG_ B_DATA_P <3>

LVDS_EG_ B_DATA_N <3>

DP_EG_ML _N<2>

DP_EG_ML _P<3>

DP_EG_ML _N<1>

DP_EG_ML _P<1>

GPU_IFPA B_RSET

GPU_IFPC D_RSET

PP1V8_GP U_IFPEF_ PLLVDD_F

LVDS_EG_ A_CLK_P

LVDS_EG_ A_DATA_N <2>

DP_EG_ML _P<2>

=PP1V1_G PU_IFPCD _IOVDD

PP1V8_GP U_IFPCD_ PLLVDD_F

GPU_IFPC D_RSET

GPU_IFPE F_RSET

GPU_IFPA B_RSET

LVDS_EG_ A_CLK_N

LVDS_EG_ A_DATA_P <0>

LVDS_EG_ A_DATA_N <0>

LVDS_EG_ A_DATA_N <3>

LVDS_EG_ A_DATA_P <3>

LVDS_EG_ A_DATA_P <2>

LVDS_EG_ B_CLK_P

PP1V8_GP U_IFPCD_ PLLVDD_F

MIN_LINE_WI DTH=0.3 mm MIN_NECK_WI DTH=0.2 mm VOLTAGE=1.8 V

=GPU_I2C S_SDA

GPU_I2CC _SDA

GPU_I2CH _SCL

GPU_I2CB _SDA

GPU_I2CB _SCL

GPU_I2CD _SDA

GPU_I2CD _SCL

GPU_I2CE _SDA

GPU_I2CE _SCL

PP1V1_GP U_IFPCD_ IOVDD_F

LVDS_EG_ B_DATA_N <1>

LVDS_EG_ B_DATA_P <1>

LVDS_EG_ B_DATA_P <0>

DP_EG_ML _N<0>

DP_EG_ML _P<0>

LVDS_EG_ A_DATA_N <1>

LVDS_EG_ A_DATA_P <1>

PP1V1_GP U_IFPEF_ IOVDD_F

DP_EG_ML _N<3>

GPU_DACC _VDD

MIN_LINE_WI DTH=0.4 mm

PP1V1_GP U_IFPCD_ IOVDD_F

VOLTAGE=1.1 V

MIN_NECK_WI DTH=0.1 mm

LVDS_EG_ B_DATA_N <0>

LVDS_EG_ B_CLK_N

GPU_I2CA _SDA

GPU_I2CH _SDA

=GPU_I2C S_SCL

GPU_I2CA _SCL

R8851

1

2

R8850

1

2

L8805

1 2

C8806

1

2

L8815

1 2

C8805

1

2

R8852

1

2

R8853

1

2

R8854

1

2

C8815

1

2

C8801

1

2

C8800

1

2

L8800

1 2

C8803

1

2

C8813

1

2

C8811

1

2

C8810

1

2

L8810

1 2

C8816

1

2

U8000

AL14

AM14

AM13

AM15

AK13

AJ12

AK12

AL13

Y4

AB5

AB4

AA4

AB6

AC6

AC5

AJ4

AL4

AM1

AK4

AH7

AG7

AK6

AM2

G1

G4

G3

G2

E3

E4

F4

G5

D5

E5

F6

G6

E2

E1

AG9

AM11

AM12

AM8

AL8

AM10

AM9

AK10

AL10

AK11

AL11

AK9

AJ11

AG10

AP13

AN13

AN8

AP8

AP10

AN10

AR11

AR10

AN11

AP11

AP2

AN3

AJ8

AM7

AM6

AL5

AM5

AM3

AM4

AP1

AR2

AJ9

AK7

AP4

AN4

AK8

AR8

AR7

AP7

AN7

AN5

AP5

AR5

AR4

AE4

AD4

AE7

AH6

AH5

AH4

AG4

AF4

AF5

AE6

AE5

AJ6

AL1

AF3

AF2

AD7

AL2

AL3

AJ3

AJ2

AJ1

AH1

AH2

AH3

R8855

1

2

R8857

1

2

R8856

1

2

R8860

1

2

R8861

1

2

77

8

77

8

77

PVCC

THRM_PAD

FDE

PGOOD

AF_EN

VR_ON

IMON

VID4

VID3

VID2

VID1

VID0

LGATE

PGND

PHASE

UGATE

BOOT

VSS

VIN

ISP

VO

ISN

ICOMP

RTN

VSEN

VDIFF

FB

COMP

VW

OCSET

SOFT

VDD

RBIAS

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

BOM OP TIONS

BOM GR OUP

GPU VCore Regulator

12A max output (L8920 limit)

(GFXIM VP6_AG ND)

(PPVCO RE_GPU _REG)

Vout = 1.05V - 0.96V

0.9012 5V

1

GPU VCore Setpoints

1

-

Max pe rfBalanc ed

-

Max Ba tt

Voltag e

VID0

0

VID3

1 1

-

M98

-

M98

-

M98

1

1 1

1

VID2 V ID1

1

1.0042 5V

0.9270 0V

0

Other VID states may not be valid

M98 Default Vcore Setpoints

4.99K

MF-LF 402

1% 1/16W

1/16W MF-LF

374K

1%

402

PLACEM ENT_NO TE=Plac e R892 0 at U 8900

5%

1/16W

20

402

MF-LF

20

MF-LF

5%

1/16W

402

PLACEM ENT_NO TE=Plac e R890 8 at U 8900

MF-LF

402

5%

1/16W

10K

5%

10K

1/16W MF-LF 402

CERM

560PF

402

50V

10%

MF-LF

2.21K

402

1/16W

1%

402-1

50V

68PF

5%

CERM

50V

CERM

5%

180PF

402

0.001U F

402

50V CERM

10%

ISL6263C

QFN

CRITIC AL

SM

10% 50V

680pF

402

CERM

MF-LF

1/16W

4.99K

1%

402

1000PF

402

25V

10%

X7R

10%

CERM 402

50V

0.001U F

68

402

10%

CERM

50V

0.001U F

1/16W

10

1%

402

MF-LF

1/16W

1%

402

150K

0.033U F

16V X5R 402

10%

10V

1uF

10%

X5R 402

1

MF-LF

5%

402

1/16W

402

X5R-CERM

20%

4.7UF

6.3V

402

CERM

16V

0.01uF

10%

0.1uF

402

X5R

10% 16V

5%

68PF

50V

402-1

CERM

1/16W MF-LF

402

9.76K

1%

MF-LF 402

1/16W

5.11K

1%

MF-LF

1/16W

402

5.11K

RJK032 8DPB

LFPAK-HF

CRITIC AL

603

10%

X7R

16V

0.22UF

0.68UH -16A

PCMB065T -SM

CRITIC AL

10UF

X5R

6.3V

603

20%

X5R 603

6.3V

10UF

330UF

2.0V POLY-TANT

20%

CRITIC AL

D2T-SM2

5%

402

1K

1/16W MF-LF

RJK030 5DPB

LFPAK-HF

CRITIC AL

22UF

25V

CRITIC AL

POLY-TANT

20%

CASE-D2-S M

603-1

10%

1UF

X5R

25V

603-1

X5R

25V

10%

1UF

1K

1%

1/16W

402

MF-LF

50V

5%

COG

330PF

402

CRITIC AL

POLY-TANT

2.0V

20%

330UF

D2T-SM2

603

6.3V X5R

20%

10UF

603

10UF

6.3V

20%

X5R

CASE-D2-S M

POLY-TANT

CRITIC AL

20%

22UF

25V

0

402

MF-LF

1/16W

5%

402

0

MF-LF

1/16W

5%

1/16W

402

5%

MF-LF

2.2K

GPUVID 2_0

2.2K

402

5%

GPUVID 2_1

MF-LF

1/16W

2.2K

402

GPUVID 1_1

1/16W MF-LF

5%

2.2K

402

MF-LF

1/16W

GPUVID 1_0

1/16W

5%

0

MF-LF 402

76

MF-LF

1/16W

0

5%

402

76

68 83

5%

0

402

MF-LF

1/16W

0.001

MF

1W

1206

1%

402

10% 25V

1000PF

X7R

10% 25V

1000PF

402

X7R

76

GPUVID 0_1

2.2K

5%

MF-LF

402

1/16W

A.0.0

051-7546

9678

SYNC_DA TE=10/ 17/2007

SYNC_MA STER=M 87_MLB

GPU (G84M) Core Supply

GPUVID 2_0,GP UVID1_1 ,GPUVI D0_1

GPUVID _1P00V

GPUVID 2_1,GP UVID1_1 ,GPUVI D0_1

GPUVID _0P90V

MIN_NECK _WIDTH=0 .2MM VOLTAGE= 0V

GND_GF XIMVP6 _AGND

MIN_LINE _WIDTH=0 .6MM

GFXIMV P6_IMO N

GFXIMV P6_VID 2 GFXIMV P6_VID 3

MIN_LINE _WIDTH=0 .3MM

GFXIMV P6_VO

MIN_NECK _WIDTH=0 .2MM

VOLTAGE= 5V

MIN_LINE _WIDTH=0 .3MM MIN_NECK _WIDTH=0 .2MM

PP5V_S 5_GFXI MVP6_VD D

MIN_NECK _WIDTH=0 .2MM

GFXIMV P6_RBI AS

MIN_LINE _WIDTH=0 .3MM

GFXIMV P6_VIN

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .3MM

MIN_LINE _WIDTH=0 .3MM MIN_NECK _WIDTH=0 .2MM

GFXIMV P6_BOO T

GFXIMV P6_OCS ET

MIN_LINE _WIDTH=0 .3MM MIN_NECK _WIDTH=0 .2MM

GFXIMV P6_VID 2

=PPVCO RE_GPU _REG

PPVCOR E_GPU_ REG_R

MIN_LINE _WIDTH=0 .6MM MIN_NECK _WIDTH=0 .2MM

=PP5V_ S3_GPU VCORE

MIN_NECK _WIDTH=0 .3MM

GFXIMV P6_COM P_RC

MIN_LINE _WIDTH=0 .3MM

GPU_VD D_SENS E

MIN_LINE _WIDTH=0 .25 mm VOLTAGE= 1.25V

MIN_NECK _WIDTH=0 .20 mm

GFXIMV P6_VDI FF_RC

MIN_NECK _WIDTH=0 .3MM

MIN_LINE _WIDTH=0 .3MM

GPU_GN D_SENS E

MIN_LINE _WIDTH=0 .25 mm

MIN_NECK _WIDTH=0 .20 mm

VOLTAGE= 0V

=PP3V3 _GPU_V CORELOG IC

=PPVIN _GPU_G PUVCORE

GFXIMV P6_PHA SE_VSUM

MIN_LINE _WIDTH=0 .3MM MIN_NECK _WIDTH=0 .3MM

GFXIMV P6_VID 3 GFXIMV P6_VID 4

GPU_VC ORE_VI D2

GPU_VC ORE_VI D1

GPU_VC ORE_VI D0

=PP3V3 _GPU_V CORELOG IC

GFXIMV P6_VID 0 GFXIMV P6_VID 1

MIN_LINE _WIDTH=0 .3MM

GFXIMV P6_SOF T

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .3MM

GFXIMV P6_VW

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .3MM

GFXIMV P6_COM P

GFXIMV P6_FB

MIN_LINE _WIDTH=0 .3MM MIN_NECK _WIDTH=0 .2MM

GFXIMV P6_VDI FF

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .3MM

GFXIMV P6_UGA TE

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

GFXIMV P6_PHA SE

MIN_LINE _WIDTH=0 .6MM

SWITCH_N ODE=TRUE

MIN_NECK _WIDTH=0 .2MM

GFXIMV P6_LGA TE

MIN_LINE _WIDTH=0 .6MM

GFXIMV P6_VID 0 GFXIMV P6_VID 1

GFXIMV P6_VID 4 =GPUVC ORE_EN GFXIMV P6_AF_ EN

GPUVCO RE_PGO OD

GFXIMV P6_FDE

PP5V_S 5_GFXI MVP6_PV CC

MIN_LINE _WIDTH=0 .3MM MIN_NECK _WIDTH=0 .2MM VOLTAGE= 5V

GFXIMV P6_DRO OP

MIN_LINE _WIDTH=0 .3MM MIN_NECK _WIDTH=0 .2MM

GFXIMV P6_VSE N_P

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .3MM

GFXIMV P6_DFB

GFXIMV P6_VSE N_N

MIN_LINE _WIDTH=0 .3MM MIN_NECK _WIDTH=0 .2MM

GFXIMV P6_VSU M

MIN_LINE _WIDTH=0 .3MM MIN_NECK _WIDTH=0 .2MM

R8951

1

2

R8950

1

2

R8908

1 2

R8920

1 2

R8907

1

2

R8910

1

2

C8951

1 2

R8953

1

2

C8952

1

2

C8950

12

C8920

1

2

U8900

XW8900

1 2

C8953

1

2

R8909

1

2

C8922

1

2

C8923

1

2

C8921

1

2

R8904

1 2

R8905

2 1

C8904

12

C8901

1

2

R8911

1 2

C8902

1

2

C8903

1

2

C8972

1

2

C8971

1 2

R8902

2

1

R8901

1

2

R8900

1 2

Q8951

5

4

1 2 3

C8956

1

2

L8920

1 2

C8965

1

2

C8966

1

2

C8943

1

23

R8930

1

2

Q8950

5

4

1 2 3

C8930

1

2

C8932

1

2

C8933

1

2

R8903

1

2

C8906

1

2

C8942

1

2 3

C8968

1

2

C8967

1

2

C8931

1

2

R8980

R8994

1 2

R8983

R8982

1

2

R8984

R8985

R8988

1

2

R8990

1 2

R8986

12

R8940

1 2

3 4

C8934

1

2

C8969

1

2

R8987

1

2

46

78

47

78

8

70

8

78

8

78

95

www.laptop-schematics.com

D

G S

IN

SYM_VER-1

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

LCD (LVDS) INTERFACE

518S0651

Place cl ose to t he conne ctor

Panel ha s 2K pul l-ups

no-panel case (d evelopme nt).

100K pul l-ups ar e for

1000PF

X7R

10% 25V

402

10%

0.1UF

X5R

16V

402

FERR-250 -OHM

CRITICAL

SM

CERM

10% 50V

402

0.0022uF

1/16W MF-LF

402

5%

100K

MF-LF

402

1/16W

5%

SSM3K1 5FV

SOD-VESM- HF

402

10K

MF-LF

1/16W

5%

MF-LF

1/16W

100K

402

5%

100K

1/16W

402

MF-LF

5%

83

CRITICAL

DLP11S

90-OHM-100MA

CRITICAL

DLP11S

90-OHM-100MA

CRITICAL

F-RT-SM

20474- 040E-1 1

10%

1000PF

X7R

25V

402

SM

FDC638 P_G

CRITICAL

051-7546

A.0.0

9679

SYNC_MAS TER=MUXG FX

SYNC_DAT E=02/25/ 2008

LVDS Display Connector

=PP3V3_S 5_LCD

LCD_PWRE N_L

LCD_PWRE N_L_RC

LVDS_CON N_B_CLK_ F_N

LVDS_CON N_B_DATA _P<0>

LVDS_CON N_B_DATA _P<1>

LVDS_CON N_A_DATA _N<1>

LVDS_CON N_A_DATA _P<1>

LVDS_CON N_A_DATA _N<2>

LVDS_CON N_A_DATA _P<2>

LVDS_CON N_B_DATA _N<0>

LVDS_CON N_A_DATA _N<0>

LVDS_CON N_A_DATA _P<0>

BKL_SYN C

LVDS_CON N_B_DATA _P<2>

LVDS_CON N_B_DATA _N<2>

LVDS_CON N_B_DATA _N<1>

LED_RETU RN_1

LED_RETU RN_2

LED_RETU RN_3

LED_RETU RN_6

PPVOUT _S0_LCD BKLT

LCD_PWR _EN

LVDS_CON N_A_CLK_ P

LVDS_CON N_B_CLK_ P

LVDS_CON N_B_CLK_ N

LVDS_CON N_A_CLK_ N

VOLTAGE=3.3 V

MIN_LINE_WI DTH=0.5 mm

PP3V3_SW _LCD

MIN_NECK_WI DTH=0.25 mm

LVDS_DDC _DATA

LVDS_CON N_A_CLK_ F_N

PP3V3_SW _LCD_UF

MIN_LINE_WI DTH=0.5 mm

VOLTAGE=3.3 V

MIN_NECK_WI DTH=0.25 mm

LVDS_CON N_B_CLK_ F_P

LVDS_DDC _CLK

LED_RETU RN_5

=PP3V3_S 0_DDC_LC D

LED_RETU RN_4

LVDS_CON N_A_CLK_ F_P

C9010

1

2

C9001

1

2

L9000

C9000

1 2

R9001

R9000

1

2

Q9001

3

1

2

R9094

1

2

R9011

1

2

R9010

1

2

L9010

1 2

34

L9011

1 2

34

J9000

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

5

6

7

8

9

C9002

1

2

Q9000

125

6

3

4

94

76

94

80

84

80

84

94

80

94

80

84

8

84

94

8

7

80

7

IN

BI

IN

OUT

BI

IN

BI

IN

BI

IN

OUT

BI

IN

XSD*

HPD_1

DIN1_0-

DIN1_1+

DIN1_2-

DAUX1+

DIN1_3+

DDC_DAT2

DAUX2-

DDC_CLK2

HPD_2

GPU_SEL

TST0

DIN1_2+

DIN1_1-

DOUT_0-

DOUT_1+

DDC_CLK1

DDC_DAT1

DOUT_2+

DOUT_2-

DOUT_3+

DOUT_3-

DIN2_1+

DDC_AUX_ SEL

DIN2_1-

AUX+

AUX-

HPDIN

DIN2_2+

DIN2_2-

DIN2_3+

DIN2_3-

DAUX2+

DIN2_0-

DIN2_0+

DIN1_0+

DAUX1-

DOUT_1-

DOUT_0+

DIN1_3-

VDD

GND

OUT

VCC

C1

C2

C3

C4

A1 B1

A2 B2

A3 B3

A4 B4

GND

THRM

IN

OUT

IN

BI

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

(All 2 4 resi stors)

LO=AUX_C H HI=DDC

LVDS DDC MUX

DisplayPort Mux

HI=PORT2

LO=PORT1

All em ulated LVDS o utputs requi re thi s termi nation

LVDS Transmitter Termination

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

76

9

76

9

81 94

76 81 83

16V10% 402X 5R

0.1uF

16V10% 402X 5R

0.1uF

18 89

0.1UF

CERM 402

20% 10V

MUXGFX

77 94

16V10% 402X 5R

0.1uF

16V

0.1uF

X5R 40210%

77 94

76

81

83

0.1UF

CERM 402

20% 10V

MUXGFX

CBTL06 141EE

BGA

MUXGFX

CRITIC AL

SIGNAL_M ODEL=DPM UX

83

18

SN74LV 4066A

QFN1

83

7

79

76

18

76

18

7

79

10V

CERM

402

0.1UF

20%

5% 1/16W MF-LF 402

20K20K

MF-LF

402

1/16W

5%

83

DPMUX_ EN_S0& DPMUX_E N_PLD

1/16W

402

MF-LF

10K

1%

DPMUX_ EN_PLD

1/16W

402

MF-LF

0

5%

MF-LF

402

1/16W

10K

1%

DPMUX_ EN_HPD

83 94

402

1/16W MF-LF

1%

PLACEM ENT_NO TE=Plac e at U 9200

270

133

1%

402

1/16W MF-LF

PLACEM ENT_NO TE=Plac e at U 9200

SIGNAL_M ODEL=EMP TY

PLACEM ENT_NO TE=Plac e at U 9200

1/16W MF-LF

402

1%

270

402

1/16W MF-LF

PLACEM ENT_NO TE=Plac e at U 9200

1%

270

SIGNAL_M ODEL=EMP TY

PLACEM ENT_NO TE=Plac e at U 9200

1%

MF-LF

1/16W

402

133

PLACEM ENT_NO TE=Plac e at U 9200

1/16W MF-LF

402

1%

270

PLACEM ENT_NO TE=Plac e at U 9200

1/16W MF-LF

402

1%

270

SIGNAL_M ODEL=EMP TY

PLACEM ENT_NO TE=Plac e at U 9200

1%

MF-LF

1/16W

402

133

270

1%

402

MF-LF

1/16W

PLACEM ENT_NO TE=Plac e at U 9200PLACEM ENT_NO TE=Plac e at U 9200

1/16W MF-LF

402

1%

270

SIGNAL_M ODEL=EMP TY

PLACEM ENT_NO TE=Plac e at U 9200

1%

MF-LF

1/16W

402

133

PLACEM ENT_NO TE=Plac e at U 9200

1/16W MF-LF

402

1%

270

1/16W MF-LF

402

PLACEM ENT_NO TE=Plac e at U 9200

1%

270

PLACEM ENT_NO TE=Plac e at U 9200

SIGNAL_M ODEL=EMP TY

1%

MF-LF

1/16W

402

133

402

MF-LF

1/16W

PLACEM ENT_NO TE=Plac e at U 9200

1%

270

1/16W MF-LF

402

PLACEM ENT_NO TE=Plac e at U 9200

1%

270

PLACEM ENT_NO TE=Plac e at U 9200

SIGNAL_M ODEL=EMP TY

1%

MF-LF

1/16W

402

133

402

MF-LF

PLACEM ENT_NO TE=Plac e at U 9200

1/16W

1%

270

402

MF-LF

1/16W

PLACEM ENT_NO TE=Plac e at U 9200

1%

270

SIGNAL_M ODEL=EMP TY

PLACEM ENT_NO TE=Plac e at U 9200

1%

402

MF-LF

1/16W

133

83 94

402

1% 1/16W MF-LF

PLACEM ENT_NO TE=Plac e at U 9200

270

PLACEM ENT_NO TE=Plac e at U 9200

1%

MF-LF

1/16W

402

270

SIGNAL_M ODEL=EMP TY

402

PLACEM ENT_NO TE=Plac e at U 9200

1%

MF-LF

1/16W

133

402

MF-LF

1/16W

PLACEM ENT_NO TE=Plac e at U 9200

1%

270

1UF

10%

6.3V CERM-X5R 402

DPMUX_ EN_HPD

79 94

7

79 94

7

79 94

7

79 94

7

79 94

7

79 94

7

79 94

7

79 94

7

79 94

7

79 94

7

79 94

7

79 94

7

79 94

MF-LF

402

1/16W

100K

5%

MF-LF

402

1/16W

100K

5%

1K

1/16W

402

MF-LF

PLACEM ENT_NO TE=Plac e at U 9320

MUXGFX

1/16W

402

MF-LF

5%

1K

20K

402

1/16W MF-LF

5%

1/16W

402

MF-LF

20K

5%

SYNC_MA STER=M UXGFX

80 9 6

A.0.0

051-7546

SYNC_DA TE=07/ 10/2008

Muxed Graphics Support

LVDS_C ONN_A_ CLK_P

DP_IG_ AUX_CH _N

DP_EG_ HPD

LVDS_B _DATA_ P<2>

LVDS_B _CLK_P

LVDS_A _DATA_ P<0>

DP_EG_ AUX_CH _P DP_EG_ AUX_CH _N

DP_MUX _SEL_E G

=PP3V3 _S0_DP MUX

DP_MUX _EN

DP_MUX _XSD_L

LVDS_C ONN_A_ DATA_N< 0>

LVDS_C ONN_A_ DATA_P< 1>

DP_IG_ AUX_CH _P

DP_IG_ ML_N<3 >

DP_IG_ ML_P<3 >

DP_EG_ ML_P<1 >

DP_IG_ CA_DET

MAKE_BAS E=TRUE

DP_HOT PLUG_D ET

DP_IG_ ML_N<2 >

LVDS_E G_DDC_ DATA

LVDS_D DC_DAT A

LVDS_D DC_SEL _IG

LVDS_A _DATA_ N<0>

LVDS_B _DATA_ N<2>

LVDS_A _DATA_ N<2>

LVDS_A _DATA_ P<2>

LVDS_B _DATA_ P<0>

LVDS_B _DATA_ N<0>

LVDS_B _CLK_N

LVDS_B _DATA_ P<1>

LVDS_B _DATA_ N<1>

LVDS_A _CLK_N

DP_EG_ AUX_CH _C_P

DP_IG_ AUX_CH _C_P

DP_ML_ N<0>

DP_ML_ P<1>

DP_ML_ P<2>

DP_ML_ N<1>

DP_EG_ ML_P<0 > DP_EG_ ML_N<0 >

DP_EG_ ML_N<3 >

DP_EG_ DDC_DA TA

=PP3V3 _S0_LV DSDDCMU X

LVDS_E G_DDC_ CLK

LVDS_I G_DDC_ CLK

LVDS_C ONN_A_ DATA_P< 0>

LVDS_C ONN_A_ DATA_N< 1>

LVDS_C ONN_A_ DATA_P< 2>

LVDS_C ONN_A_ DATA_N< 2>

LVDS_C ONN_B_ CLK_P

LVDS_C ONN_B_ CLK_N

LVDS_C ONN_B_ DATA_P< 0>

LVDS_C ONN_B_ DATA_N< 0>

LVDS_C ONN_B_ DATA_P< 1>

LVDS_C ONN_B_ DATA_P< 2>

LVDS_C ONN_B_ DATA_N< 2>

LVDS_D DC_SEL _EG

LVDS_I G_DDC_ DATA

LVDS_D DC_CLK

LVDS_A _CLK_P

LVDS_C ONN_A_ CLK_N

=PP3V3 _GPU_L VDS_DDC

DP_CA_ DET

MAKE_BAS E=TRUE

DP_ML_ P<0>

DP_HPD _R

DP_IG_ ML_P<0 > DP_IG_ ML_N<0 >

DP_IG_ ML_P<1 > DP_IG_ ML_N<1 >

DP_IG_ ML_P<2 >

=PP3V3 _S0_DP MUX

DP_IG_ DDC_DA TA

DP_IG_ HPD

DP_ML_ N<2>

DP_ML_ P<3>

DP_HPD

DP_EG_ DDC_CL K

DP_EG_ AUX_CH _C_N

DP_EG_ ML_P<3 >

DP_EG_ ML_N<2 >

DP_EG_ ML_P<2 >

DP_EG_ ML_N<1 >

DP_AUX _CH_C_ N

DP_AUX _CH_C_ P

DP_ML_ N<3>

DP_IG_ DDC_CL K

DP_IG_ AUX_CH _C_N

LVDS_A _DATA_ N<1>

LVDS_A _DATA_ P<1>

LVDS_C ONN_B_ DATA_N< 1>

R9371

1

2

R9370

1

2

C9330

1 2

C9331

1 2

C9320

1

2

C9335

1 2

C9336

1 2

C9321

1

2

U9320

H1

H2

J9

H9

J6

H6

C2

H8

H5

J8

J5

A4

B4

A5

B5

A6

B6

A9

A8

B9

B8

D9

D8

E9

E8

F9

F8

B1

B2

D1

D2

E1

E2

F1

F2

B3C8G8H4H7

A1

J2

H3

J1

G2

A2

J4

B7

U9370

1

4

8

11

2

3

9

10

13

5

6

12

7

15

14

C9370

1

2

R9373

1

2

R9372

1

2

R9302

1

2

R9303

1 2

R9301

1

2

R9357

1 2

R9356

1

2

R9352

1 2

R9355

1 2

R9351

1

2

R9350

1 2

R9347

1 2

R9346

1

2

R9342

1 2

R9345

1 2

R9341

1

2

R9340

1 2

R9337

1 2

R9336

1

2

R9332

1 2

R9335

1 2

R9331

1

2

R9330

1 2

R9327

1 2

R9326

1

2

R9322

1 2

R9325

1 2

R9321

1

2

R9320

1 2

C9301

1

2

R9305

1

2

R9304

1

2

R9306

1

2

R9307

1 2

80

8

94

95

8

94

95

BI

IN

IO

NC NC

IO

GND

OUT

IO

NC NC

IO

GND

ML_LANE3 N

HDMI_CEC

GND ML_LANE3 P

ML_LANE2 P

ML_LANE2 N

RETURN

ML_LANE1 N

GND

ML_LANE1 P

DP_C_A_D ET

DP_HPD

ML_LANE0 P

AUX_CHP

AUX_CHN

DP_PWR

ML_LANE0 N

GND

SHIELD P INS

SM PINS

BOT ROW

TH PINS

TOP ROW

IO

NC NC

IO

GND

IO

NC NC

IO

GND

IN

G

D

S

G

D

S

SYM_VER-2

OUT

G

D

S

G

D

S

BI

IN

OC*

OUT

EN

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Port Power Switch

DP Sourc e must p ull

down HPD input w ith

greater than or equal

to 100K (DPv1.1a ).

Q9440 must h ave Dra in to Gate l eakage of <50 0nA an d Gate to So urce r esistan ce of >5MOhm

pull-u p to D P_PWR.

Cable Adapte r

DP to DVI/HD MI

(CA) h as 100 k

80 94

402

5%

1/16W

100K

MF-LF

DP_ESD

SLP2510P 8

CRITIC AL

RCLAMP 0524P

10% X5R

0.1uF

16V 40 2

10% X5R

0.1uF

16V 40 2

76 80 83

10% 16 V 402X5R

0.1uF

16V10 % 402X 5R

0.1uF

5%

1/16W

402

100K

MF-LF

DP_ESD

CRITIC AL

RCLAMP 0524P

SLP2510P 8

SC70-6-1

RCLAMP0504F

CRITIC AL

DP_ESD

F-RT-THSM

CRITIC AL

DSPLYPR T-M97- 2

SLP2510P 8

RCLAMP 0524P

CRITIC AL

DP_ESD

MF-LF

1M

1/16W

402

5%

RCLAMP 0524P

SLP2510P 8

CRITIC AL

DP_ESD

0.1uF

16V10 % 402X 5R

0.1uF

16V10 % 402X 5R

0.1uF

16V10 % 402X 5R

80 94

20% 50V

603

CERM

0.01UF

FERR-1 20-OHM -3A

0603

80 94

2N7002 DW-X-G

SOT-363

2N7002 DW-X-G

SOT-363

5%

1/16W

402

MF-LF

100K

5%

1/16W

402

100K

MF-LF

12-OHM-10 0MA

TCM1210-4 SM

12-OHM-10 0MA

TCM1210-4 SM

12-OHM-10 0MA

TCM1210-4 SM

NO STU FF

MF-LF

4025%

1/16W

0

NO STU FF

MF-LF

4025%

1/16W

NO STU FF

MF-LF

4025%

1/16W

0

NO STU FF

MF-LF

4025%

1/16W

0

NO STU FF

1/16W

402

0

5%

MF-LF

1/16W

402

MF-LF

0

5%

NO STU FF

MF-LF

4025%

1/16W

0

1/16W

5% 40 2

MF-LF

NO STU FF

80

SOT-363

2N7002DW -X-G

SOT-363

2N7002DW -X-G

1M

1/16W

402

MF-LF

5%

1/16W

402

MF-LF

10K

1/16W

402

5%

MF-LF

10K

100K

402

1/16W MF-LF

5%

80 94

7

21 34 37 42 44 68 83

603

10UF

X5R

20%

6.3V

20%

402

CERM

10V

0.1UF

20%

22UF

X5R-CERM

6.3V

603

CRITICAL

SOT23

CRITICAL

TPS2051B

20%

402

CERM

10V

0.1UF

DisplayPort Connector

SYNC_MA STER=M UXGFX

SYNC_DA TE=07/ 10/2008

051-7546

A.0.0

9681

=PP3V3_S 5_DP_POR T_PWR

PM_SLP_S3_ L

VOLTAGE=3.3 V

MIN_NECK_WI DTH=0.20 MM

PP3V3_S0 _DPILIM

MIN_LINE_WI DTH=0.38 MM

TP_DPPWR _OC_L

MIN_NECK _WIDTH=0 .20 MM VOLTAGE= 3.3V

MIN_LINE _WIDTH=0 .38 MM

PP3V3_ S0_DPP WR

DP_AUX _CH_C_ P

DP_HPD

DP_HPD_Q

DP_HPD_L _Q

=PP3V3_S 0_DPCONN

DP_CA_ DET_Q

DP_ML_ CONN_N <1>

DP_ML_ CONN_P <1>

DP_ML_ C_P<1>

DP_ML_ CONN_N <0>

DP_ML_ CONN_P <0>

DP_ML_ C_P<0>

DP_ML_ C_N<0>

DP_ML_ C_N<1>

DP_ML_ C_P<2>

DP_ML_ C_N<2>

DP_ML_ CONN_N <2>

DP_ML_ C_P<3>

DP_ML_ C_N<3>

DP_ML_ CONN_N <3>

DP_ML_ P<3>

DP_ML_ N<2>

DP_ML_ P<2>

DP_ML_ N<1>

DP_ML_ P<1>

DP_ML_ N<0>

DP_ML_ P<0>

=PP3V3 _S0_DP CONN

DP_CA_ DET_L_ Q

DP_CA_ DET

DP_ML_ N<3>

DP_AUX _CH_C_ N

DP_ML_ CONN_P <3>

DP_ML_ CONN_P <2>

HDMI_C EC

R9422

1

2

R9421

1

2

D9411

3

2 1

9

10

C9415

1 2

C9414

1 2

C9411

1 2

C9410

1 2

R9420

1

2

D9410

3

2 1

9

10

D9400

1

3

4

6

2 5

J9400

18

16

4

2

20

1

78

1314

6

21

22

5

3

11

9

17

15

12

10

19

D9411

3

5 4

6 7

R9425

1

2

D9410

3

5 4

6 7

C9417

1 2

C9416

1 2

C9413

1 2

C9412

1 2

C9400

1

2

L9400

1 2

Q9440

3

5

4

Q9440

6

2

1

R9443

1

2

R9442

1

2

FL9403

1

23

4

FL9402

1

2 3

4

FL9401

1

2 3

4

FL9400

1

2 3

4

R9403

1 2

R9413

1 2

R9402

1 2

R9432

1 2

R9401

1 2

R9431

1 2

R9400

1 2

R9430

1 2

Q9441

6

2

1

Q9441

3

5

4

R9445

1

2

R9444

1

2

R9423

1

2

C9480

1

2

C9481

1

2

C9486

1

2

U9480

4

2

5

3

1

C9485

1

2

81

8

94

94 94

94

94 94

8

94

IN

OUT

IN

OUT

Q1

Q2

SW

BOOT1

UGATE1

PHASE1

LGATE1

OUT1

VCC

REFIN2

ILIM2

OUT2

SKIP*

POK2

EN2

UGATE2

PHASE2

BOOT2

LGATE2

PGND

GND

SECFB

PVCC

EN1

ILIM1

FB1

BYP

LDOREFIN

LDO

VIN

VREF3

EN_LDO

TON

REF

POK1

THRM_PAD

D

GS

NC

D

S

G

D

S

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

<Ra>

Vout = 1.8V 6A max output

(SGND)

(=PP1V 8FB_S0 _REG)

<Ra>

f = 400 kHz

(Q9510 limit?)

3A max output

Vout = 1.103V

<Rb>

(Rb sh ould b e betwe en 10K and 1 00K)

f = 300 kHz

<Rb>

(Q9560 limit?)

Vout = 0.7V * (1 + Ra / R b)

from PVCC t o VCC)

(Inter nal 10 -ohm pa th

603

20%

10UF

X5R

6.3V

1UF

10% 25V X5R 603-1

X7R

50V

10%

603-1

0.1UF

603-1

1UF

10% 25V X5R

5.76K

1/16W

1%

402

MF-LF

402

MF-LF

1% 1/16W

10K

10UF

20%

6.3V

603

X5R

MF-LF

1/16W

402

1%

280K

1%

130K

402

1/16W MF-LF

3.3UH- 3.5A

CRITIC AL

PCMB053T

POLY-TAN T B2-SM

CRITIC AL

20%

2.0V

330UF

2.5V

20%

CASE-B2- SM2

POLY-TAN T

220UF

CRITIC AL

68 83

68

67 68 83

68

MMD06CZ- SM

2.2UH- 14A

CRITIC AL

0.1UF

50V

10%

603-1

X7R

25V

20%

22UF

CASE-D2- SM

POLY-TAN T

CRITIC AL

20% 25V

CASE-D2- SM

POLY-TAN T

22UF

CRITIC AL

FDMS9600S

CRITIC AL

MLP

SM

PLACEMEN T_NOTE=P lace nex t to C76 65

402

CERM

50V

5%

100PF

NO STU FF

PLACEMEN T_NOTE=P lace XW9 515 next to C761 5

SM

CRITIC AL

QFN

ISL623 6

25V

10UF

10%

805

X5R

SM

10V

20%

402

CERM

0.1UF

MF-LF

402

1%

1/16W

127K

402

1% 1/16W MF-LF

14.0K

10V

1UF

10%

402-1

X5R

402-1

1UF

10% 10V X5R

78.7K

1/16W

1%

402

MF-LF

SSM3K1 5FV

SOD-VESM- HF

0.01UF

CERM 402

16V

10%

MF-LF

402

5%

4.7

1/16W

SI7904 BDN

CRITICAL

PWRPK-121 2-8

CRITICAL

PWRPK-121 2-8

SI7904 BDN

402-1

X5R

1UF

10V

10%

82 9 6

A.0.0

051-7546

SYNC_MA STER=M UXGFX

SYNC_DA TE=07/ 10/2008

1.1V / 1V8 FB Power Supply

GND_P1 V1P1V8 _SGND

VOLTAGE= 0V

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

GATE_NOD E=TRUE

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

P1V1GP U_DRVL

MIN_LINE _WIDTH=0 .6MM

SWITCH_N ODE=TRUE

P1V1GP U_LL

MIN_NECK _WIDTH=0 .2MM

P1V1GP U_PGOO D

GPIO7_FB VDD_ALTV O

VOLTAGE= 2V

PP2V_S 0GPU_P 1V8_REF

GPU_P1 V8_REF IN

=PPVIN _S0GPU _P1V8P1 V1

PVIN_S 0GPU_P 1V1

=P1V8F B_EN

GPUFB_ VID_L

MIN_NECK _WIDTH=0 .2MM

P1V8FB _LL

MIN_LINE _WIDTH=0 .6MM

SWITCH_N ODE=TRUE

GATE_NOD E=TRUE

MIN_LINE _WIDTH=0 .6MM MIN_NECK _WIDTH=0 .2MM

P1V8FB _DRVH

P1V1GP U_DRVH

GATE_NOD E=TRUE

MIN_LINE _WIDTH=0 .6MM MIN_NECK _WIDTH=0 .2MM

P1V1S0 _VSNS

P1V1GP U_VFB

=PP1V1 _S0GPU _REG

MIN_NECK _WIDTH=0 .2MM

MIN_LINE _WIDTH=0 .6MM

P1V1GP U_VBST

PP5V_S 0GPU_V REF

P1V8FB _PGOOD

P1V8_G PU_VSN S

=PP1V8 _GPU_R EG

P1V8FB _TRIP

MIN_NECK _WIDTH=0 .2MM

P1V8FB _VBST

MIN_LINE _WIDTH=0 .6MM

=P1V1G PU_EN

P1V8FB _DRVL

MIN_LINE _WIDTH=0 .6MM MIN_NECK _WIDTH=0 .2MM GATE_NOD E=TRUE

P1V1GP U_TRIP

=PP5V_ S0GPU_ P1V1P1V 8_GPU

MIN_LINE _WIDTH=0 .5 MM

PP5V_S 0GPU_P 1V1P1V8 _VCC

MIN_NECK _WIDTH=0 .2 MM VOLTAGE= 5V

C9565

1

2

C9595

1

2

C9530

1

2

C9545

1

2

R9520

1

2

R9521

1

2

C9515

1

2

R9535

1

2

R9585

1

2

L9510

1 2

C9510

1

2

C9560

1

2

L9560

1 2

C9580

1

2

C9540

1

2

C9590

1

2

Q9560

2349

1

8

56

7

10

XW9565

12

C9520

1

2

XW9515

1 2

U9500

17 24

9

14 27

4

11

21

12 31

7

8

18 23

10 30

22

16 25

13

28

19

1

32

20

29

33

2

15 26

365

C9500

1

2

XW9500

1 2

C9585

1

2

R9564

1

2

R9563

1

2

C9503

1

2

C9501

1

2

R9562

1

2

Q9565

3

1

2

C9561

1

2

R9500

12

Q9510

5

4

3

Q9510

6

2

1

C9504

1

2

76

8

IN

OUT

IN

OUT

D

S G

IN

OUT

IN

OUT

IN

D

S G

IN

PT17B

PT17A

PT16B

PT16A

PT15A

PT14B

PT4B

PT4A

PT3B

PT3A

PR10B

PR10A

PT32A

PT20B

PT19B

PT19A

PB15B

PB16A

PB16B

PR11B

PR12A

PR13B

PR14B

PR15A

PR15B

PR16A

PR16B

CFG0

GND

GNDIO0

GNDIO1

GNDIO2

GNDIO3

GNDIO4

GNDIO5

GNDIO6

GNDIO7

LRC_GNDP LL

LRC_VCCP LL

PB2A

PB2B

PB14A

PB14B

PB15A

PB17A

PB17B

PB18A

PB18B

PB19A

PB19B

PB20A

PB20B

PB30A

PB30B

PB31A

PB31B

PB32A

PB32B

PL2A

PL2B

PL10A

PL10B

PL11A

PL11B

PL12A

PL12B

PL13A

PL13B

PL14A

PL14B

PL15A

PL15B

PL16A

PL16B

PL18A

PL18B

PL19A

PL19B

PL32A

PL32B

PR2A

PR2B

PR11A

PR12B

PR13A

PR14A

PR18A

PR18B

PR30A

PR30B

PT2A

PT2B

PT14A

PT15B

PT18B

PT20A

PT32B

TCK

TDI

TDO

TMS

TOE

ULC_GNDP LL

ULC_VCCP LL

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCJ

PT18A

VCC

IN

OUT

IN

BI

OUT

IN

OUT

IN

CRITICAL BOM OPTION

PART#

DESCRIPTI ON

QTY

REFERENCE DESIGNATO R(S)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

The MAKE BASE pr operties for the se signa ls are o n the PO WER CONTR OL page.

(Use open -drain PGO OD output to hold o ff the st art of the GPU PWRS EQ until t he first GPU rail's source i s valid)

Required Pulldowns

Required Pullups

(OD)

BANK5

GMUX_JTAG_TCK Inversion

(Tie/stra p low if E GPU doesn 't provide CLKREQ_L output, p rovide pu llup to GP U rail if using CLK REQ_L out put from E GPU)

LVDS Receiver Termination

PM_SLP_S3_L Isolation

(All 1 4 resi stors)

BANK1B ANK2BANK3

(OD)

BANK4 BANK6BANK7

GMUX CPLD

BANK0

7

21 34 37 42 44 68 81

77 83 94

80

76 80 81

80 94

4V

4.7UF

X5R 402

20%

80 94

83

80 94

402

10K

1% 1/16W MF-LF

80 94

SOT563

SSM6N1 5FEAPE

17

5%

MF-LF

402

1/16W

100K

1/16W

4025%

MF-LF

20K

1/16W

5% 402

MF-LF

100K

NO STU FF

1/16W MF-LF

5%

10K

402

MF-LF

4025%

10K

1/16W

9

5%

4.7K

402

MF-LF1/16W

5% 402

MF-LF1/16W

10K

5% 40 2

MF-LF1/16W

1K

0.1UF

10V CERM 402

20%

0.1UF

20%

CERM

10V

402

PLACEM ENT_NO TE=Plac e at U 9200

100

402

1%

MF-LF1/16W

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

100

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

100

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

100

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

83

PLACEM ENT_NO TE=Plac e at U 9200

100

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

100

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

100

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

1%

1/16W MF-LF

402

100

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

100

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

100

PLACEM ENT_NO TE=Plac e at U 9200

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

1/16W

100

402

MF-LF

1%

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

100

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

100

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

PLACEM ENT_NO TE=Plac e at U 9200

100

402

MF-LF1/16W

1%

SIGNAL_MOD EL=EMPTY

83

5% 40 2

1/16W

10K

MF-LF

SILK_PAR T=GMUX_R ST

PLACEM ENT_NO TE=Plac e on t op sid e at U 9200

NO STU FF

402

MF-LF

1%

10K

1/16W

68

68 69

68 82

68 78

67 68 82

26

NO STU FF

0.1UF

CERM

20%

402

10V

20%

402

0.1UF

CERM

10V

NO STU FF

1/16W

EG_PWR SEQ_HW

4025%

0

MF-LF

EG_PWR SEQ_GM UX

1/16W MF-LF

4025%

0

EG_PWR SEQ_GM UX

MF-LF

402

0

5%

1/16W

CERM

10V

20%

402

0.1UF

NO STU FF

20%

402

0.1UF

CERM

10V

NO STU FF

MF-LF

402

0

5%

1/16W

EG_PWR SEQ_GM UX

5%

EG_PWR SEQ_GM UX

MF-LF

402

0

1/16W

18 83 89

1/16W MF-LF

4025%

100K

FERR-220 -OHM

0402

FERR-220 -OHM

0402

9

18 83 89

SSM6N1 5FEAPE

SOT563

18 83 89

CRITIC AL

OMIT

CSBGA-HF

XP28

18 83 89

26

9

83

19 26 90

19 42 44 90

MF-LF

1/16W

1%

10K

402

NO STU FF

19 42 44 90

79

76

9

83

9

83

80 83

80

402

CERM

10V

20%

0.1UF

10V

20%

CERM

0.1UF

402

80 83

83 84

9

6 9

NO STU FF

402

10K

1% 1/16W MF-LF

402

10V CERM

20%

0.1UF

10V CERM

0.1UF

20%

402

20%

CERM

10V

0.1UF

402

CERM

10V

0.1UF

20%

402

CERM

0.1UF

20% 10V

402

0.1UF

10V

402

20%

CERM

20%

402

0.1UF

CERM

10V

0.1UF

10V

402

CERM

20%

0.1UF

20%

402

CERM

10V

402

10V CERM

20%

0.1UF

NO STU FF

402

10K

1% 1/16W MF-LF

0.1UF

402

CERM

20% 10V

20%

402

CERM

10V

0.1UF

CERM 402

0.1UF

20% 10V

0.1UF

402

20% 10V CERM

0.1UF

10V

20%

402

CERM

0.1UF

10V

402

CERM

20%

0.1UF

20%

402

CERM

10V

402

10V CERM

20%

0.1UF

402

20%

CERM

10V

0.1UF

402

1%

MF-LF

1/16W

10K

0.1UF

402

20% 10V CERM

0.1UF

402

CERM

20% 10V

76

9

76

9

77 83 94

10K

1/16W MF-LF

1%

402

77 83 94

U9600

IC,CPLD,L ATTICE,132 CSBGA,M98

341S2350

1

CRITICAL

GMUX_PROG

IC,XP2-8, HF,CPLD,BL ANK

336S0027

U9600

CRITICAL1GMUX_8K_B LANK

83 9 6

A.0.0

051-7546

SYNC_DA TE=07/ 10/2008

SYNC_MA STER=M UXGFX

Graphics MUX (GMUX)

PP3V3_S0 _LRC_F

MIN_NECK_WI DTH=0.2 mm VOLTAGE=3.3 V

MIN_LINE_WI DTH=0.2 mm

PP3V3_S0 _ULC_F

VOLTAGE=3.3 V

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.2 mm

GMUX_I NT

EG_RAIL1 _EN

EG_RAIL3 _EN

EG_RAIL4 _EN

EXTGPU_P WR_EN

GMUX_D EBUG_R ESET_L

DP_MUX _SEL_E G

LVDS_D DC_SEL _IG

LVDS_D DC_SEL _EG

EG_RES ET_L

JTAG_G MUX_TC K

EG_CLK REQ_OU T_L

LVDS_B _DATA_ P<0>

LVDS_B _DATA_ P<1>

LVDS_E G_B_DA TA_P<2>

GMUX_D EBUG_R ESET_L

LVDS_E G_B_DA TA_N<2>

=PP3V3 _S0_GM UX

EG_RES ET_L

DP_MUX _SEL_E G

DP_MUX _EN

EG_RAI L1_EN

LCD_BK LT_EN LCD_BK LT_PWM

LVDS_D DC_SEL _IG

JTAG_G MUX_TD I JTAG_G MUX_TD O JTAG_G MUX_TM S GMUX_T OE

GMUX_C FG0

EG_CLK REQ_OU T_L

EG_CLK REQ_IN _L

LCD_BK LT_PWM

=P1V1GPU _EN

=GPUVCOR E_EN

ALL_EG _PGOOD EG_CLK REQ_IN _L

EG_RAIL2 _EN

LVDS_I G_A_DA TA_N<0>

LVDS_I G_B_DA TA_N<1>

LVDS_I G_A_CL K_N

LVDS_I G_A_DA TA_N<1>

LVDS_I G_B_DA TA_N<2>

LVDS_E G_A_DA TA_N<0>

LVDS_A _DATA_ N<2>

LVDS_A _DATA_ N<0>

LVDS_A _DATA_ P<0>

LVDS_B _CLK_N

LVDS_B _CLK_P

LVDS_A _CLK_N

GMUX_P M_SLP_ S3_L

LVDS_I G_B_DA TA_N<1>

LVDS_I G_A_DA TA_N<0>

GMUX_I NT

=P1V8FB_ EN

P3V3GPU_ EN

JTAG_G MUX_TC K

EG_RAI L3_EN EG_RAI L4_EN

DP_CA_ DET_EG

LVDS_E G_A_DA TA_P<0>

LVDS_E G_B_DA TA_N<0>LVDS_E G_B_DA TA_P<0> LVDS_E G_B_DA TA_N<1>LVDS_E G_B_DA TA_P<1>

LVDS_E G_A_CL K_NLVDS_E G_A_CL K_P

LVDS_E G_A_DA TA_P<0>

LVDS_E G_A_DA TA_N<1>LVDS_E G_A_DA TA_P<1> LVDS_E G_A_DA TA_N<2>LVDS_E G_A_DA TA_P<2>

LVDS_I G_B_DA TA_P<2>

LVDS_I G_B_DA TA_N<0>LVDS_I G_B_DA TA_P<0>

LVDS_I G_A_DA TA_N<2>LVDS_I G_A_DA TA_P<2>

LVDS_I G_A_DA TA_P<1>

LVDS_I G_B_DA TA_P<1>

LVDS_I G_A_CL K_P LVDS_I G_A_DA TA_P<0>

LVDS_B _DATA_ N<1>

LVDS_A _DATA_ P<2>

TP_GMU X_PT32 A

DP_HOT PLUG_D ET

GMUX_J TAG_TC K_L

JTAG_G MUX_TC K

GMUX_P M_SLP_ S3_L

MAKE_BAS E=TRUE

EG_PWR SEQ_EN

LVDS_B _DATA_ N<2>

LVDS_B _DATA_ N<0>

LVDS_A _DATA_ P<1> LVDS_A _DATA_ N<1>

EG_PWR SEQ_EN

TP_GMU X_PT32 B

DP_CA_ DET

LVDS_B _DATA_ P<2>

TP_GMU X_PT20 A TP_GMU X_PT20 B

LVDS_E G_A_CL K_P LVDS_E G_A_CL K_N IG_LCD _PWR_E N EG_LCD _PWR_E N

LVDS_E G_A_DA TA_N<1>

LVDS_E G_A_DA TA_N<2> LVDS_E G_B_DA TA_P<0>

LVDS_E G_A_DA TA_P<1>

LVDS_E G_A_DA TA_N<0>

LVDS_E G_A_DA TA_P<2>

LVDS_E G_B_DA TA_P<2>

LVDS_E G_B_DA TA_N<1>

LVDS_E G_B_DA TA_N<0>

LVDS_E G_B_DA TA_N<2>

LVDS_E G_B_DA TA_P<1>

EG_BKL T_EN

IG_BKL T_EN

LVDS_D DC_SEL _EG

LCD_PW R_EN LPC_AD <0> LPC_AD <1> LPC_AD <2>

EG_RAI L2_EN

LPC_AD <3>

LVDS_I G_B_DA TA_N<2>

LVDS_I G_B_DA TA_P<2>

LPC_FR AME_L

LPC_CL K33M_G MUX

LPC_RE SET_L

=GMUX_ PCIE_R ESET_L

LVDS_I G_A_DA TA_N<1> LVDS_I G_A_DA TA_P<2>

LVDS_I G_A_DA TA_P<0>

TP_GMU X_PL10 B

LVDS_I G_A_DA TA_P<1>

LVDS_M UX_SEL _EG

LVDS_I G_A_CL K_N

LVDS_I G_B_DA TA_N<0>

LVDS_I G_A_CL K_P

LVDS_I G_A_DA TA_N<2>

PM_SLP _S3_L

LVDS_I G_B_DA TA_P<0>

LVDS_I G_B_DA TA_P<1>

TP_GMU X_PL18 B_VSYNC

=PP3V3 _S0_GM UX

TP_GMU X_PL10 A

LVDS_A _CLK_P

=PP3V3 _S0_GM UX

=PP2V5 _S0_GM UX

=PP1V2 _S0_GM UX

=PP3V3 _S0_GM UX

Q9670

6

2

1

R9647

1

2

R9641

1

2

R9646

1

2

R9640

1

2

R9645

1

2

C9600

1

2

R9670

1

2

U9600

K1

J1B8C6

C12

C13

E13

M14

N10

N6P3M2C1E2

M11

P11

P4

N4

N3

M4

P5

M5

P6

M6

P7

M7

N7

N8

P9

N9

P2

N2

P10

M10

P12

P13

N12

P14

C2

D3

D1

E1

D2

E3

F1

G1

F3

G2

H2

G3

H1

H3

L1

L3

K3

L2

B1

B2

N1

P1

D12

D13

D14

E14

E12

F12

F14

G14

G12

G13

H13

H12

H14

J12

L14

M13

A14

B14

N14

N13

B6

C7

A6

A7

C8

C9

A8

B9

A9

C10

B10

A10

A11

B12

A2

A3

B13

A13

A1

B3

C5

A5

K14

L13

K13

L12

K2

B4

A4

B11C4J3

J13

N11P8C11J2J14M8B5B7A12

C14

F13

M12M9M3N5M1C3F2

K12

C9604

1

2

C9605

1

2

C9606

1

2

C9607

1

2

C9608

1

2

C9609

1

2

C9610

1

2

C9611

1

2

C9621

1

2

C9622

1

2

C9612

1

2

C9613

1

2

C9623

1

2

C9624

1

2

C9614

1

2

C9625

1

2

C9615

1

2

C9616

1

2

C9626

1

2

C9627

1

2

C9617

1

2

C9628

1

2

C9629

1

2

Q9670

3

5

4

R9693

1 2

R9692

1 2

R9691

1 2

R9683

1 2

R9682

1 2

R9690

1 2

R9681

1 2

R9680

1 2

C9630

1

2

C9631

1

2

R9666

1 2

R9665

1 2

R9664

1 2

R9663

1 2

R9656

1 2

R9662

1 2

R9661

1 2

R9660

1 2

R9655

1 2

R9651

1 2

R9652

1 2

R9653

1 2

R9654

1 2

R9650

1 2

R9695

1 2

R9679

1

2

C9694

1

2

C9693

1

2

R9630

1 2

R9631

1 2

R9632

1 2

C9692

1

2

C9691

1

2

R9634

1 2

R9633

1 2

R9694

1 2

L9627

1 2

L9631

1 2

94 94

89

94

94 94

94

94 94

89

89 89

89

83

83 83

84

83

83 83

83

83 83

83

83 83

83

9

83

80

9

6

9

77

83

77

83

18

77

6

77 77

77

77 77

18

18 18

18

6

83

8

OUT

IN

S

D

G

IN

G

P-CHN

S

D

G

D

S

N-CHN

IN

RT

DRV

GNDA

ISEN1

ISEN2

ISEN6

ISET

ISWSEN

LPF

LRT

THRM_PAD

VIN

VSEN

ISEN3

ISEN5

ISEN4

SSTCMP

VSYNC

ENA

DIM

VREF

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

*R9707 , R970 8, R970 9, R97 13, R9 714, R 9727, A ND R97 29 SHO ULD AW AY FRO M BOOST CIRCU IT

*Q9701 , D970 1, C970 9, C97 10, L9 701, R 9702, A ND R97 15 SHO ULD AL L BE P LACED N EAR EA CHOTHE R.

*BOOST _FET_C NTL AND PPVOU T_S0_L CDBKLT _SW SHO ULD BE KEPT AS SHO RT AS POSSIBL E.

*R9702 AND R 9715 PI N 1 SH OULD B E PLAC ED NEAR C9709 PIN 2

7

79

7

79

7

79

7

79

7

79

7

79

7

79 84

STPS1H1 00MF

PLACEME NT_NOTE= Place ne ar Q9701

DO222-SM

84 85

SM

PLACEME NT_NOTE= Place ne ar C9709 and Q9 701

0.4

1/6W

MF

1%

402

NOSTUF F

402

47PF

5% 50V CERM

402

1%

MF

1/6W

0.4

PLACEME NT_NOTE= Place ne ar C9709 and Q9 701

CRITIC AL

IHLP2525C Z-SM

22UH-2 .5A

PLACEME NT_NOTE= Place ne ar Q9701

1%

187K

402

MF-LF

1/16W

100

MF-LF

1%

402

X5R

25V

0.1UF

10%

SSOT6

PLACEME NT_NOTE= Place ne ar C9709

FDC5612

NOSTUF F

402

10%

1UF

X5R

10V

402

10%

X5R

25V

0.1UF

PLACEME NT_NOTE= Away fro m Q9701

MF-LF 402

1%

3.01K

1/16W

BKLT_P LL_NOT

PLACEME NT_NOTE= Away fro m Q9701

402

5%

0

MF-LF

1/16W

7

79

1/16W

0

5%

MF-LF

402

BKLT_P LL

402

1/16W

10.2

0.1%

TF

10.2

402

TF

0.1%

1/16W

402

TF

1/16W

10.2

0.1%

10.2

402

TF

0.1%

1/16W

TF

402

10.2

0.1%

1/16W

1%

402

MF-LF

10K

SOT-963

NTUD31 27CXXG

CRITIC AL

1/16W

1%

402

MF-LF

30.1K

NTUD31 27CXXG

SOT-963

CRITIC AL

83

402

MF-LF

5%

0

1/16W

402

100K

MF-LF

1%

1/16W

1/16W MF-LF

5%

2.0M

402

MF-LF

1%

1/16W

402

100

PLACEME NT_NOTE= Away fro m Q9701

1%

MF-LF 402

1/16W

100K

PLACEME NT_NOTE= Away fro m Q9701

1K

402

MF-LF

1%

1/16W

0.01UF

402

CERM

20% 16V

NOSTUF F

CERM

50V

402

10%

0.0022 UF

402-LF

2.2UF

BKLT_P LL

CERM

6.3V

20%

GOSHAWK6P

QFN

BKL_IS WSEN

PLACEME NT_NOTE= Away fro m Q9701

BKLT_P LL

1/16W MF-LF 402

5%

10K

BKLT_P LL

402

0.1UF

10%

X5R

25V

10.2

402

TF

0.1%

1/16W

CRITIC AL

2.2UF

100V

PLACEME NT_NOTE= Place ne ar C9710

1210

X7R

10%

CRITIC AL

PLACEME NT_NOTE= Place ne ar J9000

2.2UF

10%

1210

X7R

100V

1.2M

MF-LF

603

1%

1/10W

71.5K

1%

MF-LF

1/16W

402

X5R

1UF

10% 10V

1%

402

MF-LF

1/16W

100K

402

1/16W

5%

10K

MF-LF

PLACEME NT_NOTE= Place ne ar C9701

SM

CRITIC AL

10UF

X5R

PLACEME NT_NOTE= Place ne ar L9701

10% 25V

805

402

75K

1% 1/16W MF-LF

PLACEME NT_NOTE= Away fro m Q9701

402-HF

0.1

1/6W

1%

MF

SYNC_DAT E=07/02/ 2008

SYNC_MAS TER=YITE _M98_MLB

96

A.0.0

051-7546

LCD BACKLIGHT DRIVER

84

BKL_SS TCMP_R C

BKL_VREF_4V9

BKL_DIM

PPBUS_ S0_LCD BKLT_PW R

MIN_NECK_ WIDTH=0.20 mm

MIN_LINE_ WIDTH=0.5 mm

BKL_IS EN4

MIN_NECK_ WIDTH=0.20 mm

MIN_LINE_ WIDTH=0.5 mm

LED_RETURN_2

BKL_VIN

MIN_NECK_ WIDTH=0.20 mm

MIN_LINE_ WIDTH=0.5 mm

LED_RETURN_1

MIN_NECK_ WIDTH=0.20 mm

MIN_LINE_ WIDTH=0.5 mm

LED_RETURN_3

BKL_SYNC

BKL_VREF_4V9

BKL_LR T_RC

GND_BK L_PWRG ND

BOOST_FET_CNTL

MIN_NECK_ WIDTH=0.20 MM MIN_LINE_ WIDTH=0.6M M

PLACEME NT_NOTE= Place ne ar PPVOU T_S0_LC DBKLT_SW

BKL_VREF_4V9

PPVOUT_S0_LCDBKLT

BKL_LRT

BKLT_EN

PPVOUT_S0_LCDBKLT_SW

MIN_NECK_ WIDTH=0.25 mm

SWITCH_NO DE=TRUE

MIN_LINE_ WIDTH=0.5 mm

VOLTAGE=3 0V

BOOST_ SINK

MIN_LINE_ WIDTH=0.5M M

MIN_NECK_ WIDTH=0.20 MM

MIN_NECK_ WIDTH=0.20 mm

MIN_LINE_ WIDTH=0.5 mm

BKL_IS EN1

BKL_IS EN2

MIN_NECK_ WIDTH=0.20 mm

MIN_LINE_ WIDTH=0.5 mm

MIN_LINE_ WIDTH=0.5M M

GND_BKL _PWRGND_ X

MIN_NECK_ WIDTH=0.20 MM

MIN_NECK_ WIDTH=0.25 mm MIN_LINE_ WIDTH=0.4 mm

VOLTAGE=1 2.6V

PPBUS_S0_LCDBKLT_PWR

MIN_LINE_ WIDTH=0.5 mm

MIN_NECK_ WIDTH=0.20 mm

VOLTAGE=3 0V

PPVOUT_S0_LCDBKLT

GND_BK L_PWRG ND

BKL_VSEN

MIN_NECK_ WIDTH=0.20 mm

MIN_LINE_ WIDTH=0.5 mm

BKL_IS EN6

MIN_NECK_ WIDTH=0.20 mm

MIN_LINE_ WIDTH=0.5 mm

BKL_IS EN5

GND_BK L_PWRG ND

PPVIN_S0_LCDBKLT_BUF

MIN_NECK_ WIDTH=0.20 MM

VOLTAGE=1 2.6V

MIN_LINE_ WIDTH=0.5M M

GND_BK L_PWRG ND

MIN_LINE_ WIDTH=0.5M M

MIN_NECK_ WIDTH=0.20 MM

BKL_ISET

BKL_VREF_IN_4V9

BKL_PWR_EN_L

BKL_VREF_4V9

BKL_VSYNC

LCD_BKLT_PWM

BKL_LPF

BKL_SSTCMP

MIN_LINE_ WIDTH=0.5 mm MIN_NECK_ WIDTH=0.20 mm

LED_RETURN_5

LED_RETURN_6

MIN_NECK_ WIDTH=0.20 mm

MIN_LINE_ WIDTH=0.5 mm

MIN_NECK_ WIDTH=0.20 mm

MIN_LINE_ WIDTH=0.5 mm

LED_RETURN_4

BKL_IS EN3

MIN_LINE_ WIDTH=0.5 mm MIN_NECK_ WIDTH=0.20 mm

BKLT_PWM_RC

BKL_RT

U9701

20

1

5

13

10

11

12

14

15

16

8

2

19

18

6

7

21

3

4

9

17

C9701

1

2

D9701

1 2

R9701

1 2

C9702

1

2

R9704

1 2

R9708

1 2

R9709

1 2

C9705

1

2

C9706

1

2

C9707

1

2

R9714

1 2

C9708

1

2

R9717

1 2

C9709

1

2

C9710

1

2

R9723

1 2

R9724

1 2

C9703

1

2

R9705

1 2

R9706

1 2

XW9701

1 2

R9727

1 2

R9730

12

XW9702

1 2

R9702

1 2

C9712

1

2

R9715

1 2

L9701

1 2

R9731

1 2

C9713

1

2

Q9701

1 2 5 6

3

4

C9714

1

2

R9707

1 2

R9713

1 2

R9734

12

R9718

1 2

R9719

1 2

R9720

1 2

R9721

1 2

R9722

1 2

R9710

1 2

Q9702

3

5

4

R9711

1 2

Q9702

6

2

1

R9733

12

R9700

1 2

R9703

1 2

84

85

79

84

7

84

OUT

IN

D

SG

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

.

MOSFET

CHANNE L

RDS(ON )

FDC638 APZ

PPBUS S0 LCDBkLT FET

P-TYPE

0.4 A (EDP)

LOADIN G

43 mOh m @4.5 V

2AMP-32V

0402-HF

84

402

1/16W MF-LF

301K

1%

147K

402

1/16W MF-LF

0.1UF

402

X5R

10% 16V

8

SSOT6-H F

FDC638 APZ_SB MS001

5%

402

MF-LF

1/16W

4.7K

SOT563

SSM6N1 5FEAPE

SOT563

SSM6N1 5FEAPE

9

85

26

051-7546

A.0.0

9685

LCD Backlight Support

SYNC_MAS TER=YITE _M98_MLB

SYNC_DAT E=07/02/ 2008

MIN_LINE_WI DTH=0.4 mm

PPBUS_S0 _LCDBKLT _FUSED

MIN_NECK_WI DTH=0.25 mm VOLTAGE=12. 6V

MIN_NECK_WI DTH=0.25 mm

MIN_LINE_WI DTH=0.4 mm

VOLTAGE=12. 6V

=PPBUS_S 0_LCDBKL T

PPBUS_S0 _LCDBKLT _PWR

VOLTAGE=12. 6V

MIN_NECK_WI DTH=0.25 mm

MIN_LINE_WI DTH=0.4 mm

LVDS_BKL _ON

BKLT_EN_ L

BKLT_PLT _RST_L

PPBUS_S0 _LCDBKLT _EN_DIV

PPBUS_S0 _LCDBKLT _EN_L

F9800

1 2

R9808

1

2

R9809

1

2

C9802

1

2

Q9806

1 2 5 6

3

4

R9840

1

2

Q9807

3

5

4

Q9807

6

2

1

85

9

IN

VIN

SW1

SW2

GND

RUN2

RUN1

VFB1

VFB2

PAD

THRML

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

<Ra>

2.5V/1.2V S3 Switcher

<Ra>

(Switcher limit)

<Rb>

(Switcher limit)

0.3A max output

<Rb>

Vout = 0.6V * (1 + Ra/ Rb)

f = 2.25 MHz

300mA max output

Vout = 2.5V

Vout = 1.2V

68

DFN-HF

LTC354 7

CRITIC AL

PCAA031B- SM

2.2UH- 1.2A

CRITIC AL

402-LF

CERM

6.3V

20%

2.2UF

PCAA031B -SM

2.2UH- 1.2A

CRITIC AL

150K

402

MF-LF

1% 1/16W

10PF

50V

5%

402

CERM

475K

402

1/16W

1%

MF-LF

280K

1/16W

1%

402

10PF

CERM

5%

50V

402

MF-LF

1% 1/16W

280K

X5R

4V

20%

402

4.7UF

402

4V X5R

20%

86 9 6

A.0.0

051-7546

Misc Power Supplies

SYNC_MA STER=M UXGFX

SYNC_DA TE=02/ 01/2008

=PP3V3 _S0_P1 V2P2V5

=PP2V5 _S0_RE G

P1V2S0 _VFB

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .25 mm SWITCH_N ODE=TRUE

P1V2S0 _SW

MIN_NECK _WIDTH=0 .2 mm

P2V5S0 _SW

SWITCH_N ODE=TRUE

MIN_LINE _WIDTH=0 .6 mm

=P2V5S 0_EN

=P1V2S 0_EN

=PP1V2 _S0_RE G

P2V5S0 _VFB

U9900

5

2

7

4

6

9

1

8

3

L9900

1 2

C9900

1

2

L9980

1 2

R9901

1

2

C9901

1

2

R9900

1

2

R9983

1

2

C9982

1

2

R9982

1

2

C9985

1

2

C9905

1

2

8

68

8

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

FSB 1X signa ls show n in s ignal table on righ t.

Spacin g is 1 x diele ctric betwee n ADDR #, REQ# signa ls, wi th 2x dielec tric sp acing to ADS TB#.

FSB 2X signa ls / gr oups s hown i n sign al tabl e on r ight.

Signal s with in each 4x gr oup sh ould b e match ed wit hin 5 ps of strobe .

FSB 4X signa ls / gr oups s hown i n sign al tabl e on r ight.

DSTB# comple mentary pairs are s paced normall y and are NO T rout ed as differe ntial pairs.

DSTB# comple mentary pairs shoul d be m atched within 1 ps of eac h othe r, all DSTB#s match ed to +/- 300 ps.

FSB (Front-Side Bus) Constraints

CPU / FSB Net Properties

(CPU_V CCSENS E) (CPU_V CCSENS E)

(FSB_C PURST_ L)

(See a bove)

Signal s

NET_TYPE

SPACING

FSB 1X Signa ls

ELECTRIC AL_CONST RAINT_SE T

FSB 4X Signa l Group s

FSB 2X

PHYSICAL

Spacin g is 2 x diele ctric betwee n DATA #, DINV # sign als, w ith 3x diele ctric s pacing to th e DSTB #s.

Signal s with in each 2x gr oup sh ould b e match ed wit hin 20 ps. ADTSB# s shoul d be m atched +/- 3 00 ps.

All 4x /2x/1x FSB si gnals with i mpedan ce requ iremen ts are 50-oh m sing le-ende d.

NOTE: 7 mil gap is for VC CSense pair, which Intel says t o rout e with 7 mil spacin g with out sp ecifyin g a ta rget i mpedan ce.

SR DG recomm ends at least 25 mi ls, >5 0 mils prefer red

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v01 ), Sec tion 2 .2

Most C PU sig nals wi th imp edance requi rements are 5 5-ohm single -ended .

FSB Clock Constraints

Some s ignals requir e 27.4 -ohm s ingle- ended i mpedan ce.

MCP FSB COMP Signal Constraints

SOURCE : Sant a Rosa Platfo rm DG, Rev 0 .9 (#20 517), Sectio ns 4.4 & 5.8 .2.4

Design Guide recomm ends e ach st robe/s ignal g roup i s rout ed on the sa me laye r.

NOTE: Intel Design Guide allows close r spaci ng if signal lengt hs can be sho rtened .

Intel Design Guide recomm ends F SB sig nals be route d only on in ternal layers .

SOURCE : Sant a Rosa Platfo rm DG, Rev 1 .5 (#22 294), Sectio ns 4.2 & 4.3

CPU Signal Constraints

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v01 ), Sec tion 2 .2.4

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v01 ), Sec tion 2 .2.5

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v01 ), Sec tion 2 .2

Signal s with in each 1x gr oup sh ould b e match ed to CPU cl ock, + 0/-100 0 mils.

=2x_DIE LECTRIC

TOP,BOT TOM

?

CPU_AGT L

SYNC_DA TE=02/ 18/2008

SYNC_MA STER=M UXGFX

CPU/FSB Constraints

051-7546

A.0.0

9687

*

=1:1_DI FFPAIR =1:1_DIFFP AIR

FSB_DST B_50S

=50_OHM _SE

=50_OHM _SE =5 0_OHM_SE =50_OHM _SE

=4x_DIE LECTRIC

?

FSB_ADS TB

TOP,BOT TOM

=50_OHM _SE

=STANDA RD

=50_OHM _SE=50_OHM _SE

FSB_50S

=STANDA RD

*

=50_OHM _SE

=4x_DIE LECTRIC

FSB_DAT A?TOP,BOT TOM

=5x_DIE LECTRIC

?

FSB_DST B

TOP,BOT TOM

=3x_DIE LECTRIC

?

TOP,BOT TOM

FSB_ADD R

=3x_DIE LECTRIC

?

TOP,BOT TOM

FSB_1X

=2x_DIE LECTRIC

?

*

FSB_DAT A

=3x_DIE LECTRIC

*

FSB_DST B

?

FSB_ADD R

*

=STANDA RD

*

?

FSB_1X

=STANDA RD

=2x_DIE LECTRIC

*

?

FSB_ADS TB

*

CLK_FSB

?

=3x_DIE LECTRIC

CLK_FSB _100D

*

=100_OH M_DIFF

=100_OH M_DIFF=100_OH M_DIFF =100_OH M_DIFF

=100_OHM_ DIFF

=100_OH M_DIFF

MCP_FSB _COMP

?

*

8 MIL

=STANDA RD=STAN DARD

*

=50_OHM _SE =50_OHM _SE=50_OHM _SE

MCP_50S

=50_OHM _SE

25 MIL

?

CPU_VCC SENSE

*

?

*

CPU_GTL REF

25 MIL

=2:1_SP ACING

?

*

CPU_ITP

25 MIL

*

CPU_COM P

?

*

?

CPU_8MI L

8 MIL

=STANDA RD

*

?

CPU_AGT L

CPU_27P 4S

7 MIL 7 MIL

=27P4_O HM_SE=27P4_O HM_SE

*

=27P4_OH M_SE

=27P4_O HM_SE

=50_OHM _SE=50_OH M_SE =50_OHM _SE=50_OHM _SE

CPU_50S

=STANDA RD=STAN DARD

*

TOP,BOT TOM

?

CLK_FSB =4x_DIE LECTRIC

FSB_DATA _GROUP0

FSB_50S

FSB_DI NV_L<0 >

FSB_DATA

FSB_50S

FSB_1X FSB_1X

FSB_LO CK_L

CPU_50S

CPU_ASYN C

CPU_A2 0M_L

CPU_AGTL

FSB_50S

FSB_DATA

FSB_DATA _GROUP2

FSB_D_ L<47.. 32>

FSB_DS TB_L_N <1>

FSB_DSTB _50S FSB_DSTB

FSB_DSTB 1

FSB_ADST B

FSB_50S

FSB_AD STB_L< 0>

FSB_ADST B0

CPU_VI D<6..0 >

CPU_50S

CPU_8MIL

CPU_50S

IMVP6_ VID<6. .0>

CPU_8MIL

CPU_27P4 S

CPU_VCCS ENSE

IMVP6_ VSEN_P

CPU_VCCS ENSE

IMVP6_ VSEN_N

CPU_27P4 S

CPU_VCCS ENSE

CPU_27P4 S

CPU_VCCS ENSE

CPU_VC CSENSE _N

CPU_VCCS ENSE

CPU_27P4 S

CPU_VCCS ENSE

CPU_VC CSENSE _P

XDP_CP URST_L

CPU_ITPCPU_50S

XDP_BPM_ L5

CPU_50S CPU_ITP

XDP_BP M_L<5>

XDP_BPM_ L

CPU_50S

XDP_BP M_L<4. .0>

CPU_ITP

XDP_TRST _L

CPU_50S CPU_ITP

XDP_TR ST_L

XDP_TCK CPU_50S CPU_ITP

XDP_TC K

XDP_TMS CPU_50S CPU_ITP

XDP_TM S

XDP_TDO CPU_50S CPU_ITP

XDP_TD O

XDP_TDI CPU_50S CPU_ITP

XDP_TD I

CPU_COMP CPU_COMP

CPU_27P4 S

CPU_CO MP<0>

CPU_COMP

CPU_CO MP<1>

CPU_50S

CPU_COMP

CPU_CO MP<2>

CPU_27P4 S

CPU_COMP

CPU_50S

CPU_CO MP<3>

CPU_COMP

CPU_GTLR EF

CPU_GT LREF

CPU_50S

CPU_GTLR EF

CPU_50S

CPU_AGTL

IMVP_D PRSLPV R

CPU_50S

PM_DPRSL PVR

CPU_AGTL

PM_DPR SLPVR

CPU_IERR _L

CPU_50S

CPU_IE RR_L

FSB_CLK_ MCP

CLK_FSB

CLK_FSB_ 100D

FSB_CL K_MCP_ N

FSB_CLK_ MCP

CLK_FSB

CLK_FSB_ 100D

FSB_CL K_MCP_ P

FSB_CLK_ ITP

CLK_FSB_ 100D

CLK_FSB

FSB_CL K_ITP_ N

FSB_CLK_ ITP

CLK_FSB

CLK_FSB_ 100D

FSB_CL K_ITP_ P

FSB_CLK_ CPU

FSB_CL K_CPU_ N

CLK_FSB

CLK_FSB_ 100D

FSB_CLK_ CPU

FSB_CL K_CPU_ P

CLK_FSB

CLK_FSB_ 100D

MCP_FSB_ COMPMCP_CPU_ COMP

MCP_CP U_COMP _GND

MCP_50S

MCP_FSB_ COMPMCP_CPU_ COMP

MCP_CP U_COMP _VCC

MCP_50S

MCP_FSB_ COMPMCP_CPU_ COMP

MCP_BC LK_VML _COMP_G ND

MCP_50S

MCP_FSB_ COMPMCP_CPU_ COMP

MCP_BC LK_VML _COMP_V DD

MCP_50S

CPU_50S

CPU_ASYN C

FSB_DP WR_L

CPU_AGTL

CPU_50S

CPU_DPRS TP_L

CPU_DP RSTP_L

CPU_AGTL

CPU_50S

CPU_FROM _SB

CPU_DP SLP_L

CPU_AGTL

CPU_50S

FSB_CPUS LP_L

FSB_CP USLP_L

CPU_AGTL

CPU_50S

PM_THRMT RIP_L

PM_THR MTRIP_ L

CPU_8MIL

CPU_50S

CPU_ASYN C

CPU_ST PCLK_L

CPU_AGTL

CPU_50S

CPU_ASYN C

CPU_SM I_L

CPU_AGTL

CPU_50S

CPU_PWRG D

CPU_PW RGD

CPU_AGTL

CPU_50S

CPU_PROC HOT_L

CPU_PR OCHOT_ L

CPU_AGTL

CPU_50S

CPU_ASYN C_R

CPU_NM I

CPU_AGTL

CPU_50S

CPU_ASYN C_R

CPU_IN TR

CPU_AGTL

CPU_50S

CPU_INIT _L

CPU_IN IT_L

CPU_AGTL

CPU_50S

CPU_ASYN C

CPU_IG NNE_L

CPU_AGTL

CPU_50S

CPU_FERR _L

CPU_FE RR_L

CPU_8MIL

CPU_50S

CPU_BSEL

CPU_BS EL<2.. 0>

CPU_AGTL

FSB_50S

FSB_1X

FSB_TR DY_L

FSB_1X

FSB_50S

FSB_1X

FSB_RS _L<2.. 0>

FSB_1X

FSB_50S

FSB_CPUR ST_L

FSB_CP URST_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_HI TM_L

FSB_50S

FSB_1X

FSB_HI T_L

FSB_1X

FSB_50S

FSB_1X

FSB_DR DY_L

FSB_1X

FSB_50S

FSB_1X

FSB_DE FER_L

FSB_1X

FSB_50S

FSB_1X

FSB_DB SY_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_BP RI_L

FSB_50S

FSB_1X FSB_1X

FSB_BN R_L

FSB_50S

FSB_BR EQ1_L

FSB_BREQ 1_L

FSB_1X

FSB_50S

FSB_BREQ 0_L

FSB_BR EQ0_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_AD S_L

FSB_AD STB_L< 1>

FSB_ADST B1

FSB_ADST B

FSB_50S

FSB_ADDR _GROUP1

FSB_ADDR

FSB_A_ L<35.. 17>

FSB_ADDR _GROUP0

FSB_RE Q_L<4. .0>

FSB_ADDR

FSB_50S

FSB_ADDR

FSB_ADDR _GROUP0

FSB_A_ L<16.. 3>

FSB_50S

FSB_DSTB _50S FSB_DSTB

FSB_DSTB 3

FSB_DS TB_L_N <3>

FSB_DSTB _50S

FSB_DS TB_L_P <3>

FSB_DSTB

FSB_DSTB 3

FSB_50S

FSB_DATA _GROUP3

FSB_DI NV_L<3 >

FSB_DATA

FSB_50S

FSB_D_ L<63.. 48>

FSB_DATA _GROUP3

FSB_DATA

FSB_DSTB _50S FSB_DSTB

FSB_DSTB 2

FSB_DS TB_L_N <2>

FSB_DSTB _50S

FSB_DS TB_L_P <2>

FSB_DSTB

FSB_DSTB 2

FSB_50S

FSB_DATA _GROUP2

FSB_DI NV_L<2 >

FSB_DATA

FSB_DSTB _50S

FSB_DSTB 1

FSB_DSTB

FSB_DS TB_L_P <1>

FSB_50S

FSB_DATA _GROUP1

FSB_DI NV_L<1 >

FSB_DATA

FSB_50S

FSB_DATA _GROUP1

FSB_D_ L<31.. 16>

FSB_DATA

FSB_DSTB _50S

FSB_DSTB 0

FSB_DSTB

FSB_DS TB_L_N <0>

FSB_DSTB _50S FSB_DSTB

FSB_DSTB 0

FSB_DS TB_L_P <0>

FSB_DATA _GROUP0

FSB_50S

FSB_D_ L<15.. 0>

FSB_DATA

62

14

13

14

43

14

43

14

13

14

10

14

10

11

62

13

10

27

62

14

10

14

13

14

10

14

10

14

10

14

10

7

10

7

9

62

11

13

10

6

10

62

21

10

14

13

10

14

10

9

10

9

10

9

10

9

7

10

14

9

7

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

Memory Net Properties

DQ sig nals s hould b e matc hed wi thin 2 0 ps of assoc iated DQS pa ir. DQS in tra-pa ir matc hing s hould be wit hin 1 p s, no inter- pair m atchin g requi rement . All DQ S pair s shoul d be m atched withi n 100 p s of c locks. CLK in tra-pa ir matc hing s hould be wit hin 1 p s, int er-pai r matc hing s hould b e with in 140 ps. A/BA/c md sig nals sh ould b e matc hed wi thin 75 ps, n o CLK matchi ng req uiremen t.

NET_TYPE

SPACING

ELECTRIC AL_CONST RAINT_SE T

PHYSICAL

Memory Bus Constraints

All me mory s ignals maximu m leng th is 1.005 p s. CL K mini mum le ngth i s 594 p s (len gths i nclude substr ate).

Memory Bus Spacing Group Assignments

Need t o supp ort MEM _*-sty le wil dcards !

DQ/A/B A/cmd signal spacin g is 3 x diel ectric, DQS/C LK is 4x die lectri c.

DQ sig nals s hould b e matc hed wi thin 5 ps of associ ated D QS pai r. DQS in tra-pa ir matc hing s hould be wit hin 1 p s, int er-pai r matc hing s houlw b e with in 180 ps No DQS to cl ock mat ching requir ement. CLK in tra-pa ir matc hing s hould be wit hin 1 p s, int er-pai r matc hing s hould b e with in 2 p s. A/BA/c md sig nals sh ould b e matc hed wi thin 5 ps of CLK pa irs.

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .3.4

MCP MEM COMP Signal Constraints

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .3 SOURCE : Sant a Rosa Platfo rm DG, Rev 1 .0 (#21 112), Sectio n 6.2

DDR3:

DDR2:

MEM_CLK

MEM_DAT A

MEM_DAT A2MEM

*

MEM_DQS

*

MEM_CMD

MEM_CMD 2MEM

MEM_DAT A

MEM_CMD 2MEM

MEM_CMD

*

MEM_CMD 2CMD

MEM_CMDMEM_CMD

*

MEM_CTR L

MEM_CMD 2MEM

MEM_CMD

*

MEM_CLK

MEM_CMD 2MEM

*

MEM_CMD

*

MEM_DQS 2MEM

=3:1_SP ACING

?

*

MEM_2OT HER

25 MIL

?

*

=3:1_SP ACINGMEM_DAT A2MEM

=3:1_SP ACING

?

*

MEM_CMD 2MEM

=1.5:1_ SPACING

?

MEM_DAT A2DATA

*

=2.5:1_ SPACING

?

*

MEM_CTR L2MEM

=4:1_SP ACING

?

*

MEM_CLK 2MEM

?

*

=2:1_SP ACING

MEM_CTR L2CTRL

?

*

MEM_CMD 2CMD

=1.5:1_ SPACING

=40_OHM _SE

=STANDA RD

*

=STANDA RD

=40_OHM _SE =4 0_OHM_SE =40_OHM _SE

MEM_40S _VDD

=40_OHM _SE=40_OHM _SE=40_OHM_SE=40_OHM _SE

=STANDA RD

*

=STANDA RD

MEM_40S

MEM_70D _VDD

=70_OHM _DIFF

=70_OHM_D IFF

=70_OHM _DIFF = 70_OHM_D IFF

*

=70_OHM _DIFF =7 0_OHM_DI FF

MEM_70D

=70_OHM _DIFF=70_OH M_DIFF

*

=70_OHM _DIFF=70_OHM _DIFF

=70_OHM_D IFF

=70_OHM _DIFF

*

MEM_DQS 2MEM

MEM_DQS MEM_CMD

MEM_DQS

MEM_DQS 2MEM

*

MEM_CTR L

MEM_DQS

MEM_DQS 2MEM

*

MEM_CLK

051-7546

A.0.0

9688

Memory Constraints

SYNC_MA STER=M UXGFX

SYNC_DA TE=02/ 18/2008

?

*

8 MIL

MCP_MEM _COMP

=STANDA RD=STAN DARD

*

MCP_MEM _COMP

Y

7 MIL 7 MIL

=STANDA RD

*

MEM_DQS 2MEM

MEM_DQS MEM_DQS

MEM_DQS

MEM_DQS 2MEM

*

MEM_DAT A

MEM_CTR L2MEM

*

MEM_CTR L

MEM_DQS

MEM_CTR L

*

MEM_CTR L2MEM

MEM_DAT A

MEM_CTR L

*

MEM_CTR L

MEM_CTR L2CTRL

*

MEM_CLK

MEM_CTR L2MEM

MEM_CTR L

*

MEM_CLK

MEM_CLK 2MEM

MEM_DQS

MEM_CLK 2MEM

MEM_CLK

*

MEM_DAT A

MEM_CTR L

MEM_CTR L2MEM

*

MEM_CMD

MEM_CTR L

MEM_DAT A2MEM

*

MEM_DAT A

MEM_DQS

*

MEM_DAT A

MEM_DAT A2MEM

*

MEM_DAT A

MEM_DAT A2DATA

MEM_DAT A

MEM_CMD

*

MEM_DAT A

MEM_DAT A2MEM

* *

MEM_CLK

MEM_2OT HER

**

MEM_CTR L

MEM_2OT HER

* *

MEM_DQS

MEM_2OT HER

* *

MEM_CMD

MEM_2OT HER

**

MEM_DAT A

MEM_2OT HER

*

MEM_CLK 2MEM

MEM_CLKMEM_CLK

*

MEM_CLK 2MEM

MEM_CTR L

MEM_CLK

*

MEM_CLK

MEM_CLK 2MEM

MEM_CMD

MEM_B_ CKE<3. .0>

MEM_B_CN TL

MEM_CTRL

MEM_40S_ VDD

MEM_70D_ VDD

MEM_A_ CLK_P< 5..0>

MEM_A_CL K

MEM_CLK

MEM_A_ CKE<3. .0>

MEM_CTRL

MEM_A_CN TL

MEM_40S_ VDD

MEM_70D_ VDD

MEM_A_ CLK_N< 5..0>

MEM_A_CL K

MEM_CLK

MEM_CTRL

MEM_A_ ODT<3. .0>

MEM_A_CN TL

MEM_40S_ VDD

MEM_CTRL

MEM_A_ CS_L<3 ..0>

MEM_A_CN TL

MEM_40S_ VDD

MEM_A_ DM<2>

MEM_DATA

MEM_A_DQ _BYTE2 MEM_40S

MEM_DATA

MEM_A_ DM<3>

MEM_A_DQ _BYTE3 MEM_40S

MEM_A_ DM<4>

MEM_DATA

MEM_A_DQ _BYTE4 MEM_40S

MEM_A_ DM<5>

MEM_DATA

MEM_A_DQ _BYTE5 MEM_40S

MEM_DATA

MEM_A_ DM<6>

MEM_A_DQ _BYTE6 MEM_40S

MEM_A_DQ S3

MEM_A_ DQS_P< 3>

MEM_DQSMEM_70D

MEM_DATA

MEM_A_ DM<1>

MEM_A_DQ _BYTE1 MEM_40S

MEM_A_DQ S0

MEM_A_ DQS_N< 0>

MEM_DQSMEM_70D

MEM_A_DQ S1

MEM_A_ DQS_N< 1>

MEM_DQSMEM_70D

MEM_70D

MEM_A_ DQS_P< 1>

MEM_A_DQ S1

MEM_DQS

MEM_A_DQ S2

MEM_A_ DQS_P< 2>

MEM_DQSMEM_70D

MEM_70D

MEM_A_DQ S2

MEM_A_ DQS_N< 2>

MEM_DQS

MEM_A_DQ S4

MEM_A_ DQS_P< 4>

MEM_DQSMEM_70D

MEM_A_DQ S3

MEM_A_ DQS_N< 3>

MEM_DQSMEM_70D

MEM_A_DQ S5

MEM_A_ DQS_N< 5>

MEM_DQSMEM_70D

MEM_70D

MEM_A_DQ S4

MEM_A_ DQS_N< 4>

MEM_DQS

MEM_70D

MEM_A_DQ S6

MEM_A_ DQS_P< 6>

MEM_DQS

MEM_70D

MEM_A_DQ S7

MEM_A_ DQS_N< 7>

MEM_DQS

MEM_A_ BA<2.. 0>

MEM_A_CM D

MEM_CMD

MEM_40S_ VDD

MEM_DATA

MEM_A_ DM<0>

MEM_A_DQ _BYTE0 MEM_40S

MEM_DATA

MEM_A_DQ _BYTE0

MEM_A_ DQ<7.. 0>

MEM_40S

MEM_DATA

MEM_A_DQ _BYTE6

MEM_A_ DQ<55. .48>

MEM_40S

MEM_A_DQ _BYTE7

MEM_A_ DQ<63. .56>

MEM_DATA

MEM_40S

MEM_A_ CAS_L

MEM_CMD

MEM_A_CM D

MEM_40S_ VDD

MEM_DATA

MEM_A_ DQ<31. .24>

MEM_A_DQ _BYTE3 MEM_40S

MEM_CMD

MEM_A_CM D

MEM_A_ WE_L

MEM_40S_ VDD

MEM_A_DQ _BYTE2

MEM_A_ DQ<23. .16>

MEM_DATA

MEM_40S

MEM_DATA

MEM_A_DQ _BYTE1

MEM_A_ DQ<15. .8>

MEM_40S

MEM_A_CM D

MEM_A_ RAS_L

MEM_CMD

MEM_40S_ VDD

MEM_A_ DQ<39. .32>

MEM_DATA

MEM_A_DQ _BYTE4 MEM_40S

MEM_A_ DQ<47. .40>

MEM_DATA

MEM_A_DQ _BYTE5 MEM_40S

MEM_B_DQ _BYTE5

MEM_B_ DQ<47. .40>

MEM_40S

MEM_DATA

MEM_B_DQ _BYTE4 MEM_40S

MEM_B_ DQ<39. .32>

MEM_DATA

MEM_B_DQ _BYTE1

MEM_B_ DQ<15. .8>

MEM_40S

MEM_DATA

MEM_B_DQ _BYTE2

MEM_B_ DQ<23. .16>

MEM_40S

MEM_DATA

MEM_B_CM D

MEM_B_ WE_L

MEM_CMD

MEM_40S_ VDD

MEM_B_DQ _BYTE3

MEM_B_ DQ<31. .24>

MEM_40S

MEM_DATA

MEM_B_DQ _BYTE7

MEM_B_ DQ<63. .56>

MEM_40S

MEM_DATA

MEM_B_DQ _BYTE6

MEM_B_ DQ<55. .48>

MEM_40S

MEM_DATA

MEM_B_DQ _BYTE0

MEM_B_ DQ<7.. 0>

MEM_40S

MEM_DATA

MEM_B_DQ _BYTE0

MEM_B_ DM<0>

MEM_40S

MEM_DATA

MEM_B_CM D

MEM_B_ BA<2.. 0>

MEM_CMD

MEM_40S_ VDD

MEM_B_DQ S6

MEM_B_ DQS_N< 6>

MEM_70D MEM_DQS

MEM_B_DQ S7

MEM_B_ DQS_P< 7>

MEM_70D MEM_DQS

MEM_B_DQ _BYTE7

MEM_B_ DM<7>

MEM_40S

MEM_DATA

MEM_B_DQ S6

MEM_B_ DQS_P< 6>

MEM_70D MEM_DQS

MEM_B_DQ S5

MEM_B_ DQS_P< 5>

MEM_70D MEM_DQS

MEM_B_DQ S4

MEM_70D

MEM_B_ DQS_N< 4>

MEM_DQS

MEM_B_DQ S5

MEM_B_ DQS_N< 5>

MEM_70D MEM_DQS

MEM_B_DQ S3

MEM_B_ DQS_N< 3>

MEM_70D MEM_DQS

MEM_B_DQ S4

MEM_B_ DQS_P< 4>

MEM_70D MEM_DQS

MEM_B_DQ S2

MEM_B_ DQS_N< 2>

MEM_70D MEM_DQS

MEM_B_DQ S2

MEM_B_ DQS_P< 2>

MEM_70D MEM_DQS

MEM_B_DQ S1

MEM_B_ DQS_P< 1>

MEM_70D MEM_DQS

MEM_B_DQ S1

MEM_B_ DQS_N< 1>

MEM_70D MEM_DQS

MEM_B_DQ S0

MEM_B_ DQS_N< 0>

MEM_70D MEM_DQS

MEM_B_DQ S0

MEM_B_ DQS_P< 0>

MEM_70D MEM_DQS

MEM_B_DQ S3

MEM_B_ DQS_P< 3>

MEM_70D MEM_DQS

MEM_B_DQ _BYTE6

MEM_B_ DM<6>

MEM_40S

MEM_DATA

MEM_B_DQ _BYTE5

MEM_B_ DM<5>

MEM_40S

MEM_DATA

MEM_B_DQ _BYTE3

MEM_B_ DM<3>

MEM_40S

MEM_DATA

MEM_B_DQ S7

MEM_B_ DQS_N< 7>

MEM_70D MEM_DQS

MEM_B_DQ _BYTE4

MEM_B_ DM<4>

MEM_40S

MEM_DATA

MEM_B_DQ _BYTE2

MEM_B_ DM<2>

MEM_40S

MEM_DATA

MEM_B_DQ _BYTE1

MEM_B_ DM<1>

MEM_40S

MEM_DATA

MEM_B_ ODT<3. .0>

MEM_B_CN TL

MEM_CTRL

MEM_40S_ VDD

MEM_B_ CS_L<3 ..0>

MEM_B_CN TL

MEM_CTRL

MEM_40S_ VDD

MEM_70D_ VDD

MEM_CLK

MEM_B_ CLK_N< 5..0>

MEM_B_CL K

MEM_70D_ VDD

MEM_B_ CLK_P< 5..0>

MEM_CLK

MEM_B_CL K

MCP_MEM_ COMP MCP_M EM_COMP MCP_ME M_COMP

MCP_ME M_COMP _VDD

MCP_MEM_ COMP MCP_M EM_COMP MCP_ME M_COMP

MCP_ME M_COMP _GND

MEM_A_DQ S5

MEM_A_ DQS_P< 5>

MEM_DQSMEM_70D

MEM_A_DQ S7

MEM_A_ DQS_P< 7>

MEM_DQSMEM_70D

MEM_B_CM D

MEM_B_ CAS_L

MEM_CMD

MEM_40S_ VDD

MEM_B_CM D

MEM_B_ RAS_L

MEM_CMD

MEM_40S_ VDD

MEM_B_CM D

MEM_CMD

MEM_B_ A<14.. 0>

MEM_40S_ VDD

MEM_A_CM D

MEM_CMD

MEM_A_ A<14.. 0>

MEM_40S_ VDD

MEM_DATA

MEM_A_ DM<7>

MEM_A_DQ _BYTE7 MEM_40S

MEM_A_DQ S0

MEM_DQSMEM_70D

MEM_A_ DQS_P< 0>

MEM_70D

MEM_A_DQ S6

MEM_A_ DQS_N< 6>

MEM_DQS

29

28

29

28

29

28

15

16

15

www.laptop-schematics.com

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

PCI-Express

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .4

Analog Video Signal Constraints

Digital Video Signal Constraints

- 50-o hm fro m first to se cond t ermina tion re sistor .

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .7.1.

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tions 2.5.3 & 2.5. 4.

CRT si gnal s ingle-e nded i mpeden ce var ies by locati on:

- 37.5 -ohm f rom MCP to fi rst te rminat ion res istor.

SATA Interface Constraints

- 75-o hm fro m outpu t of t hree-p ole fi lter to conne ctor ( if pos sible) .

Displa yPort/ TMDS in tra-pa ir mat ching should be 5 p s. In ter-pa ir mat ching s hould be wit hin 15 0 ps. DIspla yPort AUX CH intra- pair m atchin g shoul d be 5 ps. No rel ations hip to other signal s. Max le ngth o f LVDS/ Displa yPort/ TMDS t races: 12 inc hes.

LVDS i ntra-p air mat ching should be 5 mils. Pairs should be wi thin 1 00 mils of cl ock le ngth.

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tions 2.5.1 & 2.5. 2.

R/G/B signal s shoul d be m atched as cl ose as possib le and < 10 inches .

ELECTRIC AL_CONST RAINT_SE T

NET_TYPE

SPACING

PHYSICAL

DISPLAY PORT

?

=4x_DIE LECTRIC

TOP,BOT TOM

50 MIL

CRT_2CL K

*

?

=3x_DIE LECTRIC

TOP,BOT TOM

?

SATA

=100_OH M_DIFF

=100_OHM_ DIFF

=100_OH M_DIFF

*

=100_OH M_DIFF

SATA_10 0D

8 MILSATA_TE RMP

?

*

=100_OH M_DIFF

=100_OHM_ DIFF

=100_OH M_DIFF =10 0_OHM_DI FF

*

LVDS_10 0D

=100_OH M_DIFF

=100_OH M_DIFF =100_O HM_DIFF

DP_100D

=100_OH M_DIFF

*

=100_OH M_DIFF

=100_OHM_ DIFF

=100_OH M_DIFF

DISPLAY PORT

?

*

=3x_DIE LECTRIC

*

SATA

=4x_DIE LECTRIC

?

250 MIL

CRT_2SW ITCHER

?

*

16 MIL

*

?

CRT_SYN C

=2:1_SP ACING

?

*

MCP_DAC _COMP

MCP_DV_ COMP

=STANDA RD=STAN DARD

=STANDA RD

20 MIL20 MIL

Y

*

=3x_DIE LECTRIC

LVDS

*

?

89 9 6

A.0.0

051-7546

SYNC_MA STER=M UXGFX

SYNC_DA TE=02/ 18/2008

MCP Constraints 1

PCIE_90 D

=90_OHM _DIFF

=90_OHM _DIFF =9 0_OHM_DI FF

*

=90_OHM _DIFF

=90_OHM_D IFF

13.1 MM

=100_OH M_DIFF

=100_OHM_ DIFF

CLK_PCI E_100D

=100_OH M_DIFF =100_OHM_D IFF

*

=100_OH M_DIFF =100_OH M_DIFF

?

TOP,BOT TOM

=4X_DIE LECTRIC

PCIE

CRT CR T

*

CRT_2CR T

=50_OHM _SE =50_OHM_S E

=STANDA RD

*

=STANDA RD

=50_OHM _SE

CRT_50S

=50_OHM _SE

20 MIL

CLK_PCI E

?

*

8 MIL

MCP_PEX _COMP

?

*

PCIE

=3X_DIE LECTRIC

?

*

?

CRT_2CR T

=STANDA RD

?

*

CRT

=4:1_SP ACING

TOP,BOT TOM

=4x_DIE LECTRIC

LVDS

?

PCIE_C LK100M _EXCARD _N

CLK_PCIE

CLK_PCIE _100D

TMDS_I G_TXC_ P

DISPLAYP ORT

DP_100D

TMDS_IG_ TXC

LVDS_I G_A_CL K_P

LVDS_IG_ A_CLK

LVDS_100 D

LVDS

TMDS_I G_TXC_ N

DP_100D

DISPLAYP ORTTMDS_IG_TXC

MCP_PE X_CLK_ COMP

MCP_PEX_ COMP

MCP_PEX_ CLK_COMP

CLK_PCIE

CLK_PCIE _100D

MCP_PE3_ REFCLK

PCIE_C LK100M _EXCARD _P

PCIE_E XCARD_ R2D_P

PCIE_90D PCIE

PCIEPCIE_90D

PCIE_E XCARD_ R2D_N

PCIE_90D PCIE

PEG_R2 D_P<15 ..0>

PCIE_90D PCIE

PEG_D2 R_N<15 ..0>

PCIE_M INI_D2 R_N

PCIE_90D PCIE

PCIE_90D

PCIE_MIN I_D2R

PCIE_M INI_D2 R_P

PCIE

PCIE_90D PCIE

PEG_R2 D_C_N< 15..0>

PCIE_M INI_R2 D_P

PCIE_90D PCIE

PEG_R2 D_C_P< 15..0>

PCIE_90D

PEG_R2D

PCIE

PEG_D2 R_C_P< 15..0>

PCIE_90D PCIE

PEG_D2 R_P<15 ..0>

PCIE_90D PCIE

PEG_D2R

PCIE_90D PCIE

PEG_R2 D_N<15 ..0>

PCIE_90D PCIE

PCIE_F W_R2D_ N

PCIE_90D PCIE

PCIE_F W_R2D_ C_P

PCIE_FW_ R2D

PCIE_90D PCIE

PCIE_F W_D2R_ P

PCIE_FW_ D2R

PCIE_90D PCIE

PCIE_F W_D2R_ N

PCIE_90D PCIE

PCIE_F W_D2R_ C_N

PCIE_90D

PCIE_EXC ARD_D2R

PCIE_E XCARD_ D2R_P

PCIE

PCIE_C LK100M _FW_N

CLK_PCIE

CLK_PCIE _100D

MCP_PE2_ REFCLK

PCIE_C LK100M _FW_P

CLK_PCIE _100D

CLK_PCIE

CLK_PCIE _100D

MCP_PE1_ REFCLK

CLK_PCIE

PCIE_C LK100M _MINI_P

PCIE_90D PCIE

PCIE_F W_D2R_ C_P

PCIE_90D PCIE

PCIE_F W_R2D_ P

PCIE_90D

PCIE_M INI_R2 D_C_N

PCIE

CRT_RED

CRT_IG _R_C_P R

CRT

CRT_50S

CRT_GREE N

CRT_50S

CRT_IG _G_Y_Y

CRT

CRT_IG _B_COM P_PB

CRT_BLUE

CRT

CRT_50S

CRT_IG _VSYNC

CRT_SYNC

CRT_50S

CRT_SYNC

MCP_TV _DAC_R SET

MCP_DAC_ COMPMCP_DAC_ RSET

MCP_TV _DAC_V REF

MCP_DAC_ COMPMCP_DAC_ VREF

DP_100D

DISPLAYP ORT

TMDS_I G_TXD_ N<2..0>

TMDS_IG_ TXD

DP_IG_ ML_P<3 ..0>

DISPLAYP ORT

DP_ML

DP_100D

MCP_HD MI_RSE T

MCP_DV_C OMP

MCP_HDMI _RSET

LVDS_I G_A_CL K_N

LVDS_IG_ A_CLK

LVDS_100 D

LVDS

PCIE_90D

PCIE_MIN I_R2D

PCIE

PCIE_M INI_R2 D_C_P

PCIE_M INI_R2 D_N

PCIE_90D PCIE

CRT_SYNC

CRT_50S

CRT_IG _HSYNC

CRT_SYNC

MCP_HD MI_VPR OBE

MCP_HDMI _VPROBE

MCP_DV_C OMP

PEG_D2 R_C_N< 15..0>

PCIE_90D PCIE

PCIE_F W_R2D_ C_N

PCIE_90D PCIE

CLK_PCIE

PCIE_C LK100M _MINI_N

CLK_PCIE _100D

LVDS_IG_ B_CLK

LVDS_100 D

LVDS

LVDS_I G_B_CL K_P

LVDS_I G_B_DA TA_P<2. .0>

LVDS_IG_ B_DATA

LVDS_100 D

LVDS

LVDS_I G_B_DA TA_N<2. .0>

LVDS

LVDS_IG_ B_DATA

LVDS_100 D

LVDS_I G_A_DA TA_P<2. .0>

LVDS

LVDS_100 D

LVDS_IG_ A_DATA

LVDS_I G_A_DA TA_N<2. .0>

LVDS

LVDS_100 D

LVDS_IG_ A_DATA

LVDS_I G_A_DA TA_N<3>

LVDS_IG_ A_DATA3

LVDS_100 D

LVDS

LVDS_I G_A_DA TA_P<3>

LVDS_IG_ A_DATA3

LVDS_100 D

LVDS

LVDS_I G_B_DA TA_N<3>

LVDS_IG_ B_DATA3

LVDS_100 D

LVDS

LVDS_I G_B_DA TA_P<3>

LVDS_IG_ B_DATA3

LVDS_100 D

LVDS

LVDS_IG_ B_CLK

LVDS_100 D

LVDS

LVDS_I G_B_CL K_N

DP_IG_ AUX_CH _P

DP_AUX_C H

DP_100D

DISPLAYP ORT

MCP_SATA _TERMP

SATA_TER MP

MCP_SA TA_TER MP

SATA_O DD_D2R _C_N

SATA

SATA_100 D

SATA_O DD_D2R _C_P

SATA

SATA_ODD _D2R

SATA_100 D

SATA

SATA_O DD_D2R _P

SATA_100 D

SATA_O DD_D2R _N

SATA

SATA_100 D

SATA_O DD_R2D _P

SATA

SATA_100 D

SATA_O DD_R2D _N

SATA

SATA_O DD_R2D _C_N

SATA

SATA_100 D

SATA_H DD_D2R _C_N

SATA

SATA_100 D

SATA_ODD _R2D

SATA_O DD_R2D _C_P

SATA

SATA_100 D

SATA_H DD_D2R _N

SATA

SATA_100 D

SATA_H DD_D2R _C_P

SATA

SATA_100 D

SATA_HDD _D2R

SATA_H DD_D2R _P

SATA

SATA_100 D

SATA

SATA_100 D

SATA_H DD_R2D _P SATA_H DD_R2D _N

SATA

SATA_100 D

SATA_HDD _R2D

SATA_100 D

SATA

SATA_H DD_R2D _C_P SATA_H DD_R2D _C_N

SATA

SATA_100 D

MCP_IFPA B_VPROBE

MCP_IF PAB_VP ROBE

MCP_DV_C OMP

MCP_IF PAB_RS ET

MCP_IFPA B_RSET

CLK_PCIE

PEG_CL K100M_ N

CLK_PCIE _100D

PEG_CL K100M_ P

CLK_PCIE _100D

MCP_PE0_ REFCLK

CLK_PCIE

PCIE_90D

PCIE_E XCARD_ D2R_N

PCIE

PCIE_EXC ARD_R2D

PCIEPCIE_90D

PCIE_E XCARD_ R2D_C_P

PCIE_90D

PCIE_E XCARD_ R2D_C_N

PCIE

TMDS_I G_TXD_ P<2..0>

DISPLAYP ORT

DP_100D

TMDS_IG_ TXD

DISPLAYP ORT

DP_IG_ ML_N<3 ..0>

DP_ML

DP_100D

DISPLAYP ORT

DP_AUX_C H

DP_100D

DP_IG_ AUX_CH _N

95

32

83

32

70

31

70

95

70

36

17

36

31

25

80

25

83

31

95

25

36

31

18

83

18

80

39

25

70

17

32

80

17

18

17

7

70

9

17

9

31

9

70

9

70

36

17

36

7

17

36

17

18

9

18

17

31

18

70

17

9

18

9

18

20

7

20

7

20

39

20

39

20

39

20

18

17

7

17

9

18

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .10.1.

SMBus Interface Constraints

HD Audio Interface Constraints

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .12.1.

SIO Signal Constraints

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .13.

SPI Interface Constraints

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .8.

ELECTRIC AL_CONST RAINT_SE T

PHYSICAL

NET_TYPE

SPACING

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .14.

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .11.1.

USB 2.0 Interface Constraints

SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tion 2 .9.1.

LPC Bus Constraints

PCI Bus Constraints

*

?

PCI

=STANDA RD

*

LPC_55S

=55_OHM _SE =55_OHM_S E =55 _OHM_SE =55_OHM_S E

=STANDA RD

USB

?

TOP,BOT TOM

=4x_DIE LECTRIC

*

CLK_SLO W

?

8 MIL

?

*

8 MIL

MCP_HDA _COMP

=2x_DIE LECTRIC

HDA

*

?

=55_OHM _SE

*

=STANDA RD =STANDA RD

SMB_55S

=55_OHM _SE =5 5_OHM_SE =55_OHM _SE

USB_90D

=90_OHM _DIFF =90 _OHM_DI FF

=90_OHM _DIFF =9 0_OHM_DI FF

=90_OHM_D IFF

*

=90_OHM _DIFF

MCP_USB _RBIAS

8 MIL 8 MIL

=STANDA RD=STANDAR D

=STANDA RD =STANDA RD

*

?

USB

=2x_DIE LECTRIC

?

*

SMB

=55_OHM _SE=55_OHM _SE=55_OHM _SE

=STANDA RD

CLK_PCI _55S

*

=55_OHM _SE

=STANDA RD

=STANDA RD =STANDA RD

=55_OHM _SE =55_OHM_S E =55 _OHM_SE =55_OHM_S E

CLK_LPC _55S

*

?

LPC

6 MIL

?

*

8 MIL

CLK_LPC

051-7546

A.0.0

9690

SYNC_MA STER=M UXGFX

SYNC_DA TE=02/ 18/2008

MCP Constraints 2

=STANDA RD=STAN DARD

*

=55_OHM _SE = 55_OHM_S E =55_O HM_SE

SPI_55S

=55_OHM _SE

*

SPI

?

8 MIL

*

=STANDA RD=STAN DARD

HDA_55S

=55_OHM _SE = 55_OHM_S E =55_O HM_SE=55_OHM _SE

=STANDA RD =STANDA RD

CLK_SLO W_55S

=55_OHM _SE =55_OHM_S E =55 _OHM_SE =55_OHM_S E

*

=STANDA RD

*

=STANDA RD

=55_OHM _SE = 55_OHM_S E =55_O HM_SE

PCI_55S

=55_OHM _SE

*

?

CLK_PCI

8 MIL

CLK_SLOWCLK_SLOW _55S

PM_CLK 32K_SU SCLK

SPI_MO SI_R

SPI_MOSI

SPI

SPI_55S

SPI_MO SI

SPI

SPI_55S

SPI

SPI_MISO

SPI_55S

SPI_MI SO

SPI

SPI_55S

SPI_MI SO_R

SPI

SPI_55SS PI_CS0

SPI_CS 0_R_L

USB_EX TC_P

USB_EXTC

USB

USB_90D

USB_EX TC_N

USB

SPI

SPI_55S

SPI_CS 0_L

HDA_RS T_L

HDA

HDA_55S

HDA_SD IN0

HDA_SDIN 0

HDA

HDA_55S

HDA_SD OUT

HDA

HDA_SDOU T

HDA_55S

USB_EX CARD_N

USB

USB_90D

MCP_US B_RBIA S_GND

MCP_USB_ RBIASMCP _USB_RBI AS

SMB

SMBUS_ MCP_0_ DATA

SMBUS_MC P_0_DATA

SMB_55S

HDA_BI T_CLK

HDA_BIT_ CLK

HDA

HDA_55S

SMB

SMBUS_ MCP_0_ CLK

SMBUS_MC P_0_CLK

SMB_55S

MCP_SUS_ CLK

CLK_SLOW _55S CLK_SLOW

PM_CLK 32K_SU SCLK_R

SPI

SPI_CL K

SPI_55S

SPI_CL K_R

SPI

SPI_CLK SPI_55S

PCI_AD

PCI_AD <31..2 5>

PCI

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_DE VSEL_L

PCI_AD <23..8 >

PCI_AD

PCI

PCI_55S

MCP_DE BUG<7. .0>

MCP_DEBU G

PCI

PCI_55S

HDA_SD IN_COD EC

HDA

HDA_55S

HDA_SY NC_R

HDA

HDA_55S

HDA_RS T_R_L

HDA

HDA_55S

HDA_RST_ L

HDA_BI T_CLK_ R

HDA

HDA_55S

HDA_SY NC

HDA

HDA_SYNC

HDA_55S

USB_EX CARD_P

USB_EXCA RD

USB

USB_90D

USB_EX TB_N

USB

USB_90D

USB_EX TB_P

USB_EXTB

USB

USB_90D

USB_IR _N

USB_90D

USB

USB_IR

USB_90D

USB

USB_IR _P

USB_TP AD_N

USB_90D

USB

USB_TPAD

USB_TP AD_P

USB_90D

USB

USB_BT _N

USB_90D

USB

USB_BT _P

USB_BT

USB_90D

USB

USB_CA MERA_N

USB_90D

USB

USB_CA MERA_P

USB

USB_CAME RA

USB_90D

USB_EX TD_N

USB

USB_90D

USB_EX TD_P

USB

USB_EXTD

USB_90D

USB

USB_MI NI_N

USB_MI NI_P

USB_MINI

USB_90D

USB

USB_EX TA_MUX ED_N

USB

USB_90D

USB_EX TA_MUX ED_P

USB_90D

USB

USB_90D

USB_EX TA_N

USB

LPC_CL K33M_L PCPLUS

CLK_LPC_ 55S

CLK_LPC

USB_EX TA_P

USB_90D

USB

USB_EXTA

LPC_CL K33M_S MC

CLK_LPC_ 55S

CLK_LPC

MCP_LPC_ CLK0

LPC_CL K33M_S MC_R

CLK_LPC_ 55S

CLK_LPC

LPC_55S

LPC_RESE T_L

LPC

LPC_RE SET_L

LPC_55S

LPC_AD

LPC

LPC_AD <3..0>

LPC_55S

LPC

LPC_FRAM E_L

LPC_FR AME_L

MCP_PCI_ CLK2

PCI_CL K33M_M CP_R

CLK_PCI_ 55S

CLK_PCI

PCI_CL K33M_M CP

CLK_PCI_ 55S

CLK_PCI

PCI_INTY _L

PCI_IN TY_L

PCI_55S

PCI

PCI_INTZ _L

PCI

PCI_IN TZ_L

PCI_55S

PCI_INTW _L

PCI

PCI_IN TW_L

PCI_55S

PCI

PCI_IN TX_L

PCI_55S

PCI_INTX _L

PCI

PCI_GNT1 _L

PCI_GN T1_L

PCI_55S

PCI

PCI_GN T0_L

PCI_55S

PCI_GNT0 _L

PCI

PCI_REQ1 _L

PCI_RE Q1_L

PCI_55S

PCI

PCI_CNTL

PCI_FR AME_L

PCI_55S

PCI_REQ0 _L

PCI

PCI_RE Q0_L

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_TR DY_L

PCI_CNTL

PCI

PCI_SE RR_L

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI_ST OP_L

PCI_CNTL

PCI

PCI_PE RR_L

PCI_55S

PCI_CNTL

PCI

PCI_IR DY_L

PCI_55S

PCI

PCI_AD

PCI_PA R

PCI_55S

PCI

PCI_C_ BE_L<3 ..0>

PCI_55S

PCI_C_BE _L

PCI_AD24

PCI

PCI_AD <24>

PCI_55S

HDA_SD OUT_R

HDA

HDA_55S

MCP_HDA_ COMP

MCP_HD A_PULL DN_COMP

MCP_HDA_ PULLDN_C OMP

SMBUS_MC P_1_CLK

SMBUS_ MCP_1_ CLK

SMB

SMB_55S

SMBUS_MC P_1_DATA

SMBUS_ MCP_1_ DATA

SMB

SMB_55S

45

83

21

83

44

42

44

53

44

20

54

32

13

21

13

26

53

44

19

54

32

40

41

50

31

20

40

44

40

42

26

42

45

26

21

44

21

53

21

9

21

20

7

9

7

21

44

21

13

21

20

9

20

26

20

26

19

21

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

SPACING

MCP RGMII (Ethernet) Constraints

NET_TYPE

PHYSICAL

ELECTRIC AL_CONST RAINT_SE T

88E1116R (Ethernet PHY) Constraints

SOURCE : MCP7 3 Inter face D G (DG- 02974- 001_v01 ), Sec tions 2.7.2 & 2.7. 4

SOURCE : MCP7 3 Inter face D G (DG- 02974- 001_v01 ), Sec tion 2 .7.4

051-7546

A.0.0

9691

Ethernet Constraints

SYNC_MA STER=M UXGFX

SYNC_DA TE=02/ 18/2008

12 MIL

ENET_MI I

*

?

MCP_BUF 0_CLK

?

*

=3:1_SP ACING

MCP_MII _COMP

*

=STANDA RD

7.5 MIL

=STANDA RD=STAN DARD

=STANDA RD

7.5 MIL

*

=STANDA RD=STAN DARD

ENET_MI I_55S

=55_OHM _SE

=55_OHM _SE =5 5_OHM_SE =55_OHM _SE

=100_OH M_DIFF =100_OHM_D IFF

=100_OH M_DIFF=100_ OHM_DIFF=100_ OHM_DIFF

*

=100_OHM_ DIFF

ENET_MD I_100D

ENET_MD I

*

?

25 MIL

ENET_MII _55S MCP_BUF0_ CLK

RTL821 1_CLK2 5M_CKXT AL1

ENET_MII

ENET_I NTR_L

ENET_MII _55S

ENET_INT R_L

ENET_MII _55S ENET_MIIENET_MDC

ENET_M DC

ENET_MIIENET_MII _55S

ENET_PWR DWN_L

ENET_P WRDWN_ L

ENET_MII _55S

ENET_M DIO

ENET_MDI O

ENET_MII

ENET_MIIENET_MII _55S

ENET_R XD<0>

ENET_RXD

ENET_MIIENET_MII _55S

ENET_R XD<3.. 1>

ENET_RXD _STRAP

ENET_MDI

ENET_MDI _100D

ENET_M DI_P<3 ..0>

ENET_MDI

ENET_MDI _100D

ENET_M DI_N<3 ..0>

ENET_MDI

ENET_TXD

ENET_T X_CTRL

ENET_MIIENET_MII _55S

ENET_R ESET_L

ENET_MII _55S ENET_MII

ENET_TXD 0

ENET_MIIENET_MII _55S

ENET_T XD<0>

ENET_TXD EN ET_MII_5 5S ENET_MII

ENET_T XD<3.. 1>

ENET_TXC LK

ENET_MIIENET_MII _55S

ENET_C LK125M _TXCLK

ENET_MIIENET_MII _55S

ENET_R X_CTRL

ENET_RXD

MCP_MII_ COMP

MCP_MI I_COMP _GND

MCP_MII_ COMP

ENET_MII _55S MCP_BUF0_ CLK

MCP_CL K25M_B UF0_R

MCP_CLK2 5M_BUF0

ENET_MII _55S ENET_MII

ENET_C LK125M _RXCLK_ R

ENET_RXC LK

ENET_MIIENET_MII _55S

ENET_C LK125M _RXCLK

ENET_MIIENET_MII _55S

ENET_R XD_R<3 ..0>

MCP_MII_ COMP

MCP_MI I_COMP _VDD

MCP_MII_ COMP

34

33

35

33

34

33

18

33

18

33

18

33

18

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

ELECTRIC AL_CONST RAINT_SE T

FireWire Net Properties

SPACING

NET_TYPE

FireWire Interface Constraints

PHYSICAL

Port 2 Not U sed

SYNC_DA TE=02/ 18/2008

SYNC_MA STER=M UXGFX

FireWire Constraints

92 9 6

A.0.0

051-7546

FW_TP

?

=3:1_SP ACING

*

=110_OHM_ DIFF

*

=110_OH M_DIFF

=110_OH M_DIFF =110_OHM_D IFF

FW_110D

=110_OH M_DIFF =11 0_OHM_DI FF

FW_P1_ TPA_P

FW_110D

FW_TP

FW_P1_TP A

FW_P1_ TPA_N

FW_110D

FW_TP

FW_P1_TP A

FW_P1_ TPB_P

FW_110D

FW_TP

FW_P1_TP B

FW_P1_ TPB_N

FW_110D

FW_TP

FW_P1_TP B

FW_110D

FW_TP

FW_P0_ TPB_N

FW_P0_TP B

FW_110D

FW_TP

FW_P0_ TPB_P

FW_P0_TP B

FW_110D

FW_TP

FW_P0_ TPA_N

FW_P0_TP A

FW_TP

FW_110D

FW_P0_ TPA_P

FW_P0_TP A

38

36

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

ELECTRIC AL_CONST RAINT_SE T

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRIC AL_CONST RAINT_SE T

SMBus Charger Net Properties

051-7546

A.0.0

9693

SMC Constraints

SYNC_MA STER=M UXGFX

SYNC_DA TE=02/ 18/2008

=STANDA RD =S TANDARD

0.1 MM 0.1 MM

*

=STANDA RD=STANDARD

1TO1_DI FFPAIR

CHGR_C SO_N

1TO1_DIF FPAIR

CHGR_C SO_P

1TO1_DIF FPAIR

CHGR_CSO

CHGR_C SI_P

1TO1_DIF FPAIR

CHGR_CSI

CHGR_C SI_N

1TO1_DIF FPAIR

SMB_55S

SMBUS_ SMC_A_ S3_SCL

SMBUS_SM C_A_S3_S CL

SMB

SMB_55S

SMBUS_ SMC_A_ S3_SDA

SMBUS_SM C_A_S3_S DA

SMB

SMBUS_ SMC_BS A_SDA

SMBUS_SM C_BSA_SD A

SMB

SMB_55S

SMB

SMBUS_SM C_MGMT_S DA

SMBUS_ SMC_MG MT_SDA

SMB_55S

SMB

SMBUS_ SMC_MG MT_SCL

SMB_55S

SMBUS_SM C_MGMT_S CL

SMB

SMBUS_SM C_BSA_SC L

SMBUS_ SMC_BS A_SCL

SMB_55S

SMBUS_ SMC_0_ S0_SDA

SMBUS_SM C_0_S0_S DA

SMB

SMB_55S

SMBUS_SM C_0_S0_S CL

SMBUS_ SMC_0_ S0_SCL

SMB

SMB_55S

SMB

SMBUS_SM C_B_S0_S DA

SMBUS_ SMC_B_ S0_SDA

SMB_55S

SMB

SMBUS_SM C_B_S0_S CL

SMBUS_ SMC_B_ S0_SCL

SMB_55S

45

61

7

45

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

SPACING

DIspla yPort AUX CH intra- pair m atchin g shoul d be 5 ps. No rel ations hip to other signal s.

Displa yPort/ TMDS in tra-pa ir mat ching should be 5 p s. In ter-pa ir mat ching s hould be wit hin 15 0 ps.

LVDS i ntra-p air mat ching should be 5 mils. Pairs should be wi thin 1 00 mils of cl ock le ngth.

GDDR3 Frame Buffer Signal Constraints

Max le ngth o f LVDS/ Displa yPort/ TMDS t races: 12 inc hes. SOURCE : MCP7 9 Inter face D G (DG- 03328- 001_v0D ), Sec tions 2.5.3 & 2.5. 4.

MUXGFX Net Properties

ELECTRICAL_ CONSTRAINT_S ET

PHYSICAL

NET_TYPE

SPACING

PHYSICAL

ELECTRICAL_ CONSTRAINT_S ET

GDDR3 FB A/B Net Properties

NET_TYPE

PHYSICAL

SPACING

NET_TYPE

SPACING

Digital Video Signal Constraints

From T18 MXM:

NET_TYPE

ELECTRICAL_ CONSTRAINT_S ET

GDDR3 FB C/D Net Properties

PHYSICAL

(CK505_DOT9 6)

G96 Net Properties

ELECTRICAL_ CONSTRAINT_S ET

I138

I139

I142

I143

I144

I145

I148

I149

I152

I153

I155

I157

I158

I159

I160

I161

I182

I183

I184

I185

I190

I191

I192

I193

I194

I195

I196

I197

I198

I199

I200

I201

I202

I203

DISPLAY PORT

?

*

=3x_DIE LECTRIC

?

TOP,BOT TOM

DISPLAY PORT

=4x_DIE LECTRIC

=100_OH M_DIFF=100_ OHM_DIFF

=100_OH M_DIFF

*

=100_OH M_DIFF

=100_OHM_ DIFF

DP_100D

=100_OH M_DIFF

=3x_DIE LECTRIC

LVDS

*

?

=2.5:1_SPA CING

*

GDDR3_DQS

?

*

GDDR3_CMD

?

=2.5:1_SPA CING

GDDR3_CLK

?*

=2.5:1_SPA CING

TOP,BOT TOM

?

LVDS

=4x_DIE LECTRIC

=80_OHM_DI FF=80_OHM_DIFF

*

=80_OHM_DI FF

GDDR3_80D

=80_OHM_DIFF

=80_OHM_DI FF

0.095 MM

=STANDARD=STANDARD

*

GDDR3_40SE =40_OHM_SE

=40_OHM_SE

0.095 MM

12.7 MM

=40_OHM_SE

=STANDARD =STANDA RD

=55_OHM_SE

GDDR3_40R5 5SE

*

0.095 MM

GDDR3_DATA

* ?

=2.5:1_SPA CING

=100_OHM_ DIFF

=100_OH M_DIFF=100_ OHM_DIFF

LVDS_10 0D

*

=100_OH M_DIFF

GPU (G96) Constraints

SYNC_MAS TER=MUXG FX

051-7546

A.0.0

9694

SYNC_DAT E=02/18/ 2008

LVDS_B_DAT A

LVDS_B_D ATA_P<2. .0>

LVDS

LVDS_100D

LVDS_CON N_B_CLK_ F_P

LVDS_100D

LVDS

LVDS_CON N_A_DATA _N<2..0>

LVDS

LVDS_100D

LVDS_CON N_B_CLK_ P

LVDS

LVDS_100D

LVDS_CON N_B_CLK_ F_N

LVDS

LVDS_100D

LVDS_CON N_A_DATA _P<2..0>

LVDS

LVDS_100D

LVDS_CON N_B_CLK_ N

LVDS

LVDS_100D

DP_ML_ N<3..0 >

DP_100D

DISPLAYP ORT

DP_ML_ N<3..0 >

DP_100D

DISPLAYP ORT

DP_ML_ CONN_N <3..0>

DP_100D

DISPLAYP ORT

DP_ML

DP_ML_ CONN_P <3..0>

DP_ML_ C_P<3. .0>

DP_100D

DISPLAYP ORT

DP_ML

DP_ML_ C_N<3. .0>

DP_100D

DISPLAYP ORT

DP_ML_ P<3..0 >DP_ML_P<3. .0>

DISPLAYP ORT

DP_ML

DP_100D

LVDS_CON N_B_DATA _P<2..0>

LVDS

LVDS_100D

LVDS_CON N_B_DATA _N<2..0>

LVDS_100D

LVDS

LVDS_CON N_A_CLK_ N

LVDS_100D

LVDS

LVDS_CON N_A_CLK_ P

LVDS

LVDS_100D

LVDS_CON N_A_CLK_ F_P

LVDS

LVDS_100D

LVDS_CON N_A_CLK_ F_N

LVDS

LVDS_100D

DP_100D

DP_AUX_C H

DISPLAYP ORT

DP_AUX _CH_C_ N

DISPLAYP ORT

DP_AUX_C H

DP_100D

DP_AUX _CH_C_ P

CLK_SLOW

CK505_CLK27 MSS

CLK_SLOW_55 S

GPU_CLK2 7M_SS

LVDS

LVDS_EG_ A_CLK_P

LVDS_EG_A_ CLK

LVDS_100D

LVDS

LVDS_EG_ A_CLK_N

LVDS_EG_A_ CLK

LVDS_100D

CLK_SLOW_55 S

GPU_CLK2 7M

CLK_SLOW

GDDR3_DATAGDDR3_40SE

FB_B_DQM3

FB_A_DQM _L<7>

FB_A_DQ< 55..48>

FB_B_DQ_BYT E2

GDDR3_40SE GDDR3_DATA

GDDR3_DQS

FB_A_RDQ S<7>

GDDR3_40SEF B_B_RDQS3

FB_B_WDQS2

GDDR3_DQS

FB_A_WDQ S<6>

GDDR3_40SE

FB_B_WDQS3

GDDR3_DQS

GDDR3_40SE

FB_A_WDQ S<7>

FB_B_RDQS2

GDDR3_DQS

FB_A_RDQ S<6>

GDDR3_40SE

FB_A_DQ< 47..40>

FB_B_DQ_BYT E1

GDDR3_DATAGDDR3_40SE

GDDR3_DATA

FB_A_DQM _L<4>

FB_B_DQM0

GDDR3_40SE

FB_B_RDQS1

GDDR3_DQS

GDDR3_40SE

FB_A_RDQ S<5>

FB_B_DQM1

GDDR3_40SE GDDR3_DATA

FB_A_DQM _L<5>

FB_B_DQM2

GDDR3_DATA

FB_A_DQM _L<6>

GDDR3_40SE

FB_A_WDQ S<4>

FB_B_WDQS0

GDDR3_DQS

GDDR3_40SE

FB_B_RDQS0 GDDR3_40SE

FB_A_RDQ S<4>

GDDR3_DQS

FB_B_DQ_BYT E0

GDDR3_DATA

FB_A_DQ< 39..32>

GDDR3_40SE

LVDS_EG_ B_DATA_N <2..0>

LVDS

LVDS_100D

LVDS_EG_B_ DATA

DP_100D

DP_EG_ AUX_CH _P

DISPLAYP ORT

DP_AUX_C H

DISPLAYP ORT

DP_100D

DP_EG_ AUX_CH _C_N

DISPLAYP ORT

DP_EG_ ML_N<3 ..0>

DP_ML

DP_100D

DP_EG_ ML_N<3 ..0>

DISPLAYP ORT

DP_AUX_C H

DP_100D

DP_EG_ AUX_CH _N

GDDR3_80D

FB_C_CLK_P

FB_B_CLK _P<0>

GDDR3_CLK

FB_B_WDQ S<1>

GDDR3_DQS

FB_C_WDQS1 GDDR3_40SE

FB_B_WDQ S<0>

GDDR3_DQS

FB_C_WDQS0 GDDR3_40SE

FB_B_UMA <5..2>

FB_D_CMD

GDDR3_CMD

GDDR3_40SE

GDDR3_CMD

FB_C_CMD

FB_B_LMA <5..2>

GDDR3_40SE

GDDR3_CMD

FB_CD_CMD_P D

FB_B_DRA M_RST

GDDR3_40R55 SE

GDDR3_DQS

FB_C_RDQS1

FB_B_RDQ S<1>

GDDR3_40SE

GDDR3_DQS

FB_C_RDQS2

FB_B_RDQ S<2>

GDDR3_40SE

FB_B_RDQ S<3>

FB_C_RDQS3

GDDR3_DQS

GDDR3_40SE

FB_C_DQ_BYT E0

FB_B_DQ< 7..0>

GDDR3_DATAGDDR3_40SE

GDDR3_DATA

FB_C_DQ_BYT E3

FB_B_DQ< 31..24>

GDDR3_40SE

FB_B_RDQ S<4>

GDDR3_DQS

FB_D_RDQS0 GDDR3_40SE

GDDR3_DQS

FB_B_RDQ S<5>

FB_D_RDQS1 GDDR3_40SE

FB_D_RDQS3

FB_B_RDQ S<7>

GDDR3_DQS

GDDR3_40SE

FB_D_DQ_BYT E0

GDDR3_DATA

FB_B_DQ< 39..32>

GDDR3_40SE

FB_B_RDQ S<6>

GDDR3_DQS

FB_D_RDQS2 GDDR3_40SE

FB_A_DQ_BYT E3

GDDR3_DATA

FB_A_DQ< 31..24>

GDDR3_40SE

GDDR3_DATA

FB_A_DQ< 15..8>

GDDR3_40SE

FB_A_DQ_BYT E1

FB_A_DQ_BYT E0

GDDR3_DATA

FB_A_DQ< 7..0>

GDDR3_40SE

FB_A_RDQS3

GDDR3_DQS

FB_A_RDQ S<3>

GDDR3_40SE

FB_A_RDQS2

GDDR3_DQS

FB_A_RDQ S<2>

GDDR3_40SE

FB_A_RDQS1

GDDR3_DQS

GDDR3_40SE

FB_A_RDQ S<1>

FB_A_RDQS0

FB_A_RDQ S<0>

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS3 GDDR3_40SE

GDDR3_DQS

FB_A_WDQ S<3>

FB_A_WDQS2

FB_A_WDQ S<2>

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS1 GDDR3_40SE

GDDR3_DQS

FB_A_WDQ S<1>

FB_AB_CMD_P D

GDDR3_CMD

GDDR3_40R55 SE

FB_A_CKE

FB_AB_CMD

FB_A_WE_ L

GDDR3_40R55 SE

GDDR3_CMD

FB_AB_CMD

GDDR3_40R55 SE

GDDR3_CMD

FB_A_RAS _L

GDDR3_CMDFB_AB_CMD

GDDR3_40R55 SE

FB_A_BA< 2..0>

FB_AB_CMD

GDDR3_40R55 SE

GDDR3_CMD

FB_A_MA< 12..6>

DISPLAYP ORT

DP_100D

DP_EG_ AUX_CH _C_P

FB_A_CLK_P

GDDR3_80D GD DR3_CLK

FB_A_CLK _P<0>

GDDR3_CLKGDDR3_80D

FB_A_CLK _N<0>

FB_A_WDQS0 GDDR3_40SE

FB_A_WDQ S<0>

GDDR3_DQS

GDDR3_80D

FB_B_CLK _N<0>

GDDR3_CLK

GDDR3_80D

FB_D_CLK_P

FB_B_CLK _P<1>

GDDR3_CLK

GDDR3_80D

FB_B_CLK _N<1>

GDDR3_CLK

GDDR3_40R55 SE

FB_CD_CMD

FB_B_MA< 1..0>

GDDR3_CMD

GDDR3_40R55 SE

FB_CD_CMD

FB_B_BA< 2..0>

GDDR3_CMD

FB_B_MA< 12..6>

GDDR3_40R55 SE

FB_CD_CMD GDDR3_CMD

GDDR3_40R55 SE

FB_CD_CMD

FB_B_RAS _L

GDDR3_CMD

GDDR3_40R55 SE

FB_CD_CMD

FB_B_WE_ L

GDDR3_CMD

GDDR3_40R55 SE

FB_CD_CMD

FB_B_CAS _L

GDDR3_CMD

GDDR3_DATA

FB_C_DQM3

FB_B_DQM _L<3>

GDDR3_40SE

FB_B_CS0 _L

GDDR3_CMDFB_CD_CS0

GDDR3_40R55 SE

FB_B_CKE

GDDR3_CMD

FB_CD_CMD_P D

FB_B_WDQ S<2>

GDDR3_DQS

FB_C_WDQS2 GDDR3_40SE

FB_B_WDQ S<3>

GDDR3_DQS

FB_C_WDQS3 GDDR3_40SE

FB_B_RDQ S<0>

GDDR3_DQS

FB_C_RDQS0 GDDR3_40SE

GDDR3_DATA

FB_C_DQ_BYT E1

FB_B_DQ< 15..8>

GDDR3_40SE

GDDR3_DATA

FB_C_DQ_BYT E2

FB_B_DQ< 23..16>

GDDR3_40SE

GDDR3_DATA

FB_B_DQM _L<0>

FB_C_DQM0

GDDR3_40SE

GDDR3_DATA

FB_B_DQM _L<1>

FB_C_DQM1

GDDR3_40SE

GDDR3_DATA

FB_C_DQM2

FB_B_DQM _L<2>

GDDR3_40SE

FB_B_WDQ S<4>

GDDR3_DQS

FB_D_WDQS0 GDDR3_40SE

FB_B_WDQ S<5>

GDDR3_DQS

FB_D_WDQS1 GDDR3_40SE

FB_B_WDQ S<6>

GDDR3_DQS

FB_D_WDQS2 GDDR3_40SE

FB_B_WDQ S<7>

GDDR3_DQS

FB_D_WDQS3 GDDR3_40SE

GDDR3_DATAGDDR3_40SE

FB_B_DQM _L<6>

FB_D_DQM2

GDDR3_DATA

FB_B_DQM _L<5>

GDDR3_40SE

FB_D_DQM1

GDDR3_DATA

FB_B_DQ< 63..56>

FB_D_DQ_BYT E3

GDDR3_40SE

GDDR3_DATA

FB_B_DQ< 55..48>

FB_D_DQ_BYT E2

GDDR3_40SE

GDDR3_DATA

FB_B_DQ< 47..40>

FB_D_DQ_BYT E1

GDDR3_40SE

GDDR3_CLK

FB_B_CLK_P

GDDR3_80D

FB_A_CLK _P<1>

FB_AB_CMD_P D

FB_A_DRA M_RST

GDDR3_40R55 SE

GDDR3_CMD

FB_A_CMD

GDDR3_40SE

FB_A_LMA <5..2>

GDDR3_CMD

FB_A_MA< 1..0>

FB_AB_CMD

GDDR3_40R55 SE

GDDR3_CMD

GDDR3_80D

FB_A_CLK _N<1>

GDDR3_CLK

FB_A_DQ_BYT E2

GDDR3_40SE GDDR3_DATA

FB_A_DQ< 23..16>

GDDR3_DATA

FB_B_DQM _L<7>

GDDR3_40SE

FB_D_DQM3

DISPLAYP ORT

DP_EG_ ML_P<3 ..0>DP_EG_ ML_P<3 ..0>

DP_ML

DP_100D

FB_D_DQM0

FB_B_DQM _L<4>

GDDR3_40SE GDDR3_D ATA

FB_A_CAS _L

FB_AB_CMD

GDDR3_40R55 SE

GDDR3_CMD

FB_AB_CS0

FB_A_CS0 _L

GDDR3_CMD

GDDR3_40R55 SE

FB_B_CMD

FB_A_UMA <5..2>

GDDR3_40SE

GDDR3_CMD

LVDS_EG_ B_DATA_P <2..0>

LVDS

LVDS_100D

LVDS_EG_B_ DATA

LVDS_100D

LVDS_A_C LK_P

LVDS

LVDS_A_CLK

LVDS

LVDS_B_C LK_N

LVDS_100D

LVDS_B_CLK

LVDS_100D

LVDS_B_DAT A

LVDS_B_D ATA_N<2. .0>

LVDS

LVDS_100D

LVDS_A_DAT A

LVDS_A_D ATA_N<2. .0>

LVDS_100D

LVDS

LVDS_A_DAT A

LVDS_A_D ATA_P<2. .0>

LVDS

LVDS_A_C LK_N

LVDS_A_CLK

LVDS_100D

LVDS

LVDS_B_CLK

LVDS_B_C LK_P

LVDS_EG_ A_DATA_N <2..0>

LVDS

LVDS_100D

LVDS_EG_A_ DATA

LVDS_EG_ A_DATA_P <2..0>

LVDS

LVDS_100D

LVDS_EG_A_ DATA

FB_B_DQ_BYT E3

FB_A_DQ< 63..56>

GDDR3_40SE GDDR3_DATA

GDDR3_DQS

FB_B_WDQS1

FB_A_WDQ S<5>

GDDR3_40SE

FB_A_DQM3

GDDR3_DATAGDDR3_40 SE

FB_A_DQM _L<3>

FB_A_DQM2

FB_A_DQM _L<2>

GDDR3_DATAGDDR3_40 SE

FB_A_DQM1

FB_A_DQM _L<1>

GDDR3_DATAGDDR3_40 SE

FB_A_DQM0

GDDR3_DATAGDDR3_40 SE

FB_A_DQM _L<0>

80

83

79

80

79

80

81

79

80

79

81

83

73

83

80

74

73

74

73

74

80

74

73

83

73

80

7

79

7

79

80

81

80

7

79

7

80

76

77

76

72

77

80

77

72

80

72

77

72

77

80

77

72

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

OVERRIDE OVERRID E OVERR IDE OVERRIDE OVERRI DE OVE RRIDE OVERRIDE OVERRIDE

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

OVERRIDE OVERRID E OVERR IDE OVERRIDE OVERRI DE OVE RRIDE OVERRIDE OVERRIDE

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

PHYSICAL_ RULE_SET

AREA_TYPE

NET_PHYSI CAL_TYPE

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

OVERRIDE OVERRID E OVERR IDE OVERRIDE OVERRI DE OVE RRIDE OVERRIDE OVERRIDE

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

OVERRIDE OVERRID E OVERR IDE OVERRIDE OVERRI DE OVE RRIDE OVERRIDE OVERRIDE

Forces power -refere nced m emory signal s (CLK, ADDR,C TRL) t o not route on ISL3 , ISL4 & ISL 10(GND -refere nced p lanes) .

Ground -refer enced m emory signal s (DQ, DQM,DQS ) MAY route on ISL 9 (VDD -refere nced p lane)b ut not next t o VDD island .

(USB_CAM ERA)

(USB_EXT A)

(PCIE_EX CARD)

(PCIE_MI NI)

PHYSICAL

ELECTRICAL_ CONSTRAINT_S ET

NET_TYPE

SPACINGSPACING

NET_TYPE

PHYSICAL

(USB_EXT D)

(USB_EXT A)

M99 Specific Net Properties

Altern ate di ffpair width /gap t hrough BGA f anout areas (95-oh m diff )

Graphics ,SATA Constraint Relaxations

Allow 0.127 mm nec ks for >0.12 7 mm l ines f or GMC H fano ut.

Memory Constraint Relaxations

(USB_EXT D)

ELECTRICAL_ CONSTRAINT_S ET

M99 Specific Net Properties

I124

I125

I126

I127

I128

I129

I130

I131

I132

I133

I134

I135

I136

I137

I138

I139

I140

I141

I142

I143

I144

I145

I146

I147

I148

I149

I150

I151

I152

I153

I154

I155

I156

I157

I158

I159

I160

I161

I162

I163

I164

I165

I166

I167

I168

I169

I170

I171

I172

I173

I174

I175

I176

I177

I178

I179

I180

I181

I182

I183

I184

I185

I186

I187

I188

I189

I190

I191

I192

I193

I194

I195

I196

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

BGA

DP_100D

100_DIFF_B GA

BGA

100_DIFF_B GA

LVDS_100D

ISL3,ISL1 0

N

MEM_70D _VDD

MEM_70D

ISL4,IS L9

MEM_40S _VDD

ISL3,ISL1 0

N

ISL4,IS L9

MEM_40S

BOTTOM

0.127 MM

MEM_70D 6.35 MM

ENET_MDI

GND

*

GND_P2MM

*

GND

MEM_DQS

GND_P2MM

* ?

GND =STANDARD

=2:1_SPACI NG

SENSE

?*

=1:1_DIFFP AIR =1: 1_DIFFPAIR

=1:1_DIFFP AIR=1:1_DIFFP AIR

DIFFPAIR

*

PCIE_90 D

100 MIL0.09 MM

*

BGASATA_100D

100_DIFF_B GA

=2:1_SPACI NG

*

THERM

?

GND_P2MM

*

MEM_DATA

GND

*

GND_P2MMME M_CTRL

GND

?*

PP1V8_MEM =STANDARD

*

GND

SATA

GND_P2MM

*

GND

CLK_PCIE GND_P 2MM

USB

*

GND

GND_P2MM

SB_POWER

*

CLK_PCIE PWR_P 2MM

*

GND_P2MM

GND

PCIE

SATA

PWR_P2MMSB_POWER

*

USB

*

SB_POWER PWR_P2MM

GND_P2MM

*

LVDS

GND

FSB_DSTB

*

FSB_DSTB GND_P2MM

GND_P2MM

CLK_FSB

*

GND

MEM_CMD

*

GND_P2MM

GND

GND_P2MM

*

MEM_CLK

GND

PWR_P2MM

1000

*

0.20 MM

ENETCONN

?*

25 MILS

AUDIO

?

=2:1_SPACI NG

*

=1:1_DIFFP AIR=1:1 _DIFFPAIR

THERM_1TO1 _55S

=55_OHM_SE=55_OHM_SE

*

=55_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFP AIR

=55_OHM_SE

=1:1_DIFFPAIR

*

=55_OHM_SE

SENSE_1TO1 _55S

=1:1_DIFFP AIR

=55_OHM_SE

051-7546

A.0.0

9695

SYNC_MAS TER=MUXG FX

SYNC_DAT E=02/21/ 2008

Projec t Specific Constraints

GND_P2MM

*

0.20 MM

1000

MCP_DV_ COMP

250 MIL

*

0.25 MM

CPU_27P 4S

100 MIL0.23 MM

BOTTOM

MCP_USB _RBIAS

0.1 MMTOP

500 MIL

0.1 MM

500 MIL

MCP_MII _COMP

TOP

0.1 MM

500 MIL

TOP

MCP_DV_ COMP

500 MIL

TOP

USB_90D 0.09 MM

0.1 MM

500 MIL

TOP

MCP_MEM _COMP

*

0.09 MM 100 MIL

MEM_70D _VDD

*

0.09 MM

5.8 MM

MEM_70D

0.09 MM

*

MEM_40S _VDD

5.8 MM

MEM_40S

*

0.09 MM

5.8 MM

CPU_VCCSEN SE

GND_P2MM

GND

*

GND_P2MM

CPU_GTLREF

GND

*

CPU_COMP GND_P 2MM

GND

SENSE

SENSE_1TO1_ 55S

DDRISN S_N

DIFFPAIR

SPKRCO NN_L_P _OUT

AUDIO

SPK_OUT

DIFFPAIR

SPKRCO NN_L_N _OUT

AUDIO

PCIE_90D

PCIE

PCIE_F C_D2R_ P

PCIE_FC_ D2R

PCIE_90D

PCIE

PCIE_F C_D2R_ N

PCIE_90D

PCIE

PCIE_F C_R2D_ P

SENSE_1TO1_ 55S

SENSE

1V05CP U_P

SENSE_DIFFP AIR

GPUISE NS_P

SENSE

SENSE_DIFFP AIR SENSE_1TO1_55S

ENETCONN

ENET_MDI_10 0D

ENETCONN _P<3..0>

ENET_MDI_10 0D

ENETCONN _N<3..0>

ENETCONN

SATA_100 D

SATA_OD D_R2D_UF _P

SATA

SATA_HDD _D2R_UF_ P

SATA

SATA_100 D

SATA_HDD _R2D_UF_ N

SATA

MCPCOREI SNS_P

SENSE

SENSE_DIFFP AIR SENSE_1TO1_55S

SENSE_DIFFP AIR SENSE_1TO1_55 S

SENSE

P1V8GPUI SNS_P

PCIE_C LK100M _EXCARD _CONN_ N

CLK_PCIE

CLK_PCIE _100D

PCIE

PCIE_90D

PCIE_F C_R2D_ N

1V05CP UISNS_ R_P

SENSE_1TO1_ 55S

SENSE

SENSE_DIFFP AIR

SATA_HDD _D2R_UF_ N

SATA_100 D

SATA

USB2_EXT A_MUXED_ P

USB_90D

USB

CONN_US B2_BT_P

USB_90D

USB

USB_LT 2_N

USB_90D

USB

USB2_EX CARD_CON N_N

USB_90D

USB

PCIE_F C_R2D_ C_N

PCIE

PCIE_90D

THERM

CPUTHMSNS_D 2_DP

CPUTHMSN S_D2_P

THERM_1TO1_ 55S

MCP_PE4_ REFCLK

CLK_PCIE _100D

PCIE_C LK100M _FC_P

CLK_PCIE

SATA_OD D_D2R_UF _N

SATA

SATA_100 D

SENSE

SENSE_1TO1_ 55S

GFXIMVP6 _VSEN_N

CPU_THER MD_P

CPU_THERMD_ DP

THERM_1TO1_ 55S

THERM

CLK_PCIE

PCIE_C LK100M _FC_N

CLK_PCIE _100D

DP_IG_ AUX_CH _C_N

DISPLAYPOR T

DP_100D

SENSE_1TO1_ 55S

GFXIMVP6 _VSEN_P

SENSE_DIFFP AIR

SENSE

SATA_OD D_D2R_UF _P

SATA

SATA_100 D

MCPCOREI SNS_N

SENSE_1TO1_ 55S

SENSE

CONN_US B2_BT_N

USB_90D

USB

USB_90D

USB

USB_CAM ERA_CONN _N

USB_90D

USB_CAM ERA_CONN _P

USB

CONN_TP AD_USB_N

USB_90D

USB

CONN_TP AD_USB_P

USB_90D

USB2_L T1_N

USB

USB_90D

USB2_EX CARD_CON N_P

USB_90D

USB

PCIE

PCIE_90D

PCIE_MIN I_R2D_N

PCIE_90D

PCIE

PCIE_MIN I_R2D_P

PCIE_90D

PCIE

PCIE_EXC ARD_R2D_ N

CLK_PCIE _100D

PCIE_CL K100M_MI NI_CONN_ P

CLK_PCIE

CLK_PCIE _100D

PCIE_CL K100M_MI NI_CONN_ N

1TO1_DIF FPAIR

CHGR_C SI_R_P

1TO1_DIF FPAIR

CHGR_C SI_R_N

1TO1_DIF FPAIR

CHGR_C SO_R_N

THERM

CPUTHMSN S_D2_N

THERM_1TO1_ 55S

SATA_HDD _R2D_UF_ P

SATA

SATA_100 D

USB2_EXT A_MUXED_ N

USB

USB_90D

USB

USB_90D

USB2_L T1_P

THERM

CPU_THER MD_N

THERM_1TO1_ 55S

GPUTHMSNS_D _DP

THERM

GPUTHMSN S_D_P

THERM_1TO1_ 55S

SATA_100 D

SATA_OD D_R2D_UF _N

SATA

1TO1_DIF FPAIR

CHGR_C SO_R_P

PCIE_EXC ARD_R2D_ P

PCIE_90D

PCIE

USB_LT 2_P

USB_90D

USB

SB_POWER

PP3V3_S5

DDRISN S_R_P

SENSE_DIFFP AIR

SENSE

SENSE_1TO1_ 55S

CLK_PCIE _100D

PCIE_C LK100M _EXCARD _CONN_ P

CLK_PCIE

PCIE_FC_ R2D

PCIE_F C_R2D_ C_P

PCIE

PCIE_90D

DISPLAYPOR T

DP_IG_ AUX_CH _C_P

DP_100D

DDRISN S_R_N

SENSE

SENSE_1TO1_ 55S

ISNS_C PU_P

SENSE

SENSE_DIFFP AIR SENSE_1TO1_55S

ISNS_C PU_N

SENSE_1TO1_ 55S

SENSE

AUDIO

DIFFPAIR

SPKRAM P_R_P_ OUT

SPKRAM P_S_P_ OUT

AUDIO

DIFFPAIR

SPKRAM P_R_N_ OUT

AUDIO

DIFFPAIR

AUDIO

DIFFPAIR

SPKRAM P_L_P_ OUT

AUDIO

DIFFPAIR

SPKRCO NN_R_N _OUT

DIFFPAIR

SPKRCO NN_S_N _OUT

AUDIO

SPKRAM P_S_N_ OUT

AUDIO

DIFFPAIR

AUDIO

DIFFPAIR

SPKRAM P_L_N_ OUT

DIFFPAIR

SPKRCO NN_R_P _OUT

AUDIO

SPK_OUT

DIFFPAIR

SPKRCO NN_S_P _OUT

AUDIO

SPK_OUT

SENSE_1TO1_ 55S

1V05CP UISNS_ R_N

SENSE

THERM

MCP_THMD IODE_N

THERM_1TO1_ 55S

MCP_THMD IODE_P

THERM

MCP_THERMD_ DP

THERM_1TO1_ 55S

MCPTHMSN S_D_N

THERM

MCPTHMSN S_D_P

MCPTHMSNS_D _DP

THERM

THERM_1TO1_ 55S

GPU_TDIO DE_N

THERM

THERM_1TO1_ 55S

THERM

GPU_TDIO DE_P

GPU_THERMD_ DP

THERM_1TO1_ 55S

THERM

GPUTHMSN S_D_N

THERM_1TO1_ 55S

P1V8GP U_P

SENSE_DIFFP AIR SENSE_1TO1_55S

SENSE

SENSE_1TO1_ 55S

P1V8GP U_N

SENSE

SB_POWER

PP1V5_S0

SENSE_1TO1_ 55S

P1V8GPUI SNS_N

SENSE

SENSE_1TO1_ 55S

P1V8GPUI SNS_R_N

SENSE

GPUISE NS_N

SENSE

SENSE_1TO1_ 55S

1V05CP U_N

SENSE

SENSE_1TO1_ 55S

SENSE

DDRISN S_P

SENSE_DIFFP AIR

PP3V3_S0

SB_POWER

SENSE_1TO1_ 55S

P1V8GPUI SNS_R_P

SENSE_DIFFP AIR

SENSE

GND

58

89

58

57

32

66

65

32

48

32

65

32

89

32

61

48

61

32

8

32

57

48

76

66

8

47

7

9

32

47

35

39

47

7

32

47

39

40

31

40

7

9

48

9

39

78

10

9

80

78

39

47

31

40

7

31

7

31

61

46

48

39

40

10

48

39

46

7

40

7

47

7

9

80

47

46

57

7

57

7

47

21

48

47

7

47

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

AREA_TYPE

SPACING_R ULE_SET

NET_SPACI NG_TYPE1 NET_SPA CING_TYPE2

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

VERSION

ALLEGRO

(MIL or MM)

BOARD UN ITS

BOARD LA YERS

BOARD AR EAS

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

MINIMUM L INE WIDTH

ALLOW ROU TE ON LAYER?

LAYER

MINIMUM N ECK WIDTH

MAXIMUM N ECK LENGTH

DIFFPAIR PRIMARY GA P

DIFFPAIR NECK GAPPHYSICAL_ RULE_SET

LINE-TO-L INE SPACIN G

LAYER

SPACING_R ULE_SET

WEIGHT

NOTE:F rom T18 MLB, changed to re flect M 99 sta ckup.

NOTE: 10 0_DIFF_B GA is 10 0-ohms d ifferent ial impe dance on outer la yers and 95-ohms on inne r layers .

M99 Board-Specific Spacing & Physical Constraints

0.140 M M

?

*

2X_DIEL ECTRIC

=STANDARD =STANDARD

0.1 MM 0.1 MM

Y*

1:1_DIFFPA IR

=STANDARD

0.170 MM

0.150 MM 0.150 M M

TOP,BOTTOM

Y

70_OHM_DIF F

0.095 MM

0.150 MM0.150 MM

0.170 MM

Y

70_OHM_DIF F

ISL2,ISL11

0.170 MM

=STANDARD

*

70_OHM_DIF F

N

=STANDARD

1.8:1_SPAC ING

0.18 MM

?*

=STANDARD

=STANDARD=STANDARD=STANDARD

=STANDARD

N*

90_OHM_DIF F

0.102 MM

ISL3,ISL4

90_OHM_DIF F

Y

0.102 MM

0.220 MM 0.220 M M

0.102 MM 0.102 MM

0.220 MMISL9,ISL10

90_OHM_DIF F

Y

0.220 MM

0.115 MM

90_OHM_DIF F

ISL2,ISL11

Y

0.115 MM

0.230 MM 0.230 M M

0.115 MM

90_OHM_DIF F

TOP,BOTTOM

Y

0.230 MM0.230 MM

0.095 MM

=STANDARD =STANDARD

100_OHM_DI FF

* N

=STANDARD=STANDARD

=STANDARD

0.080 MM

Y

ISL3,ISL4

100_OHM_DI FF

0.200 MM0.200 MM

0.080 MM

0.200 MM

0.080 MM

0.200 MM

Y

100_OHM_DI FF

ISL9,ISL10

0.080 MM

?*

0.4 MM

4:1_SPACIN G

1.5:1_SPAC ING

?*

0.15 MM

96 9 6

A.0.0

051-7546

SYNC_MAS TER=M99_ MLB

SYNC_DAT E=01/22/ 2008

PCB Rule Definitions

=STANDARD=STANDARD

0.090 MM

* Y

50_OHM_SE =STANDARD

0.090 MM

0.095 MM0.310 MM

27P4_OHM_S EYTOP,BOTTOM

0.160 MM0.160 MM

0.175 MM0.175 MM

Y

70_OHM_DIF F

ISL3,ISL4

0.095 MM

TOP,BOTTOM

0.165 MM

Y

40_OHM_SE

Y

TOP,BOTTOM

50_OHM_SE

0.095 MM0.110 MM

0.090 MM

55_OHM_SE

TOP,BOTTOM

Y

0.090 MM

=DEFAULT=DEFAU LT

*

=DEFAULT =DEFAUL T

STANDARD

Y

10 MM

=50_OHM_SE

Y*

0 MM

DEFAULT

0 MM

=50_OHM_SE

14 MM

0.076 MM

=STANDARD

*

=STANDARD

55_OHM_SE

Y

0.076 MM

=STANDARD

STANDARD

*

=DEFAULT

?

=DEFAULT

?

BGA_P1MM

*

=DEFAULTBGA_P2MM

?

0.077 MM

0.330 MM

Y

0.077 MM

110_OHM_DI FF

0.330 MM

ISL9,ISL10

0.089 MM

Y

100_OHM_DI FF

ISL2,ISL11

0.220 MM 0.220 M M

0.089 MM

0.089 MM 0.089 MM

TOP,BOTTOM

100_OHM_DI FF

Y

0.220 MM0.220 MM

0.330 MM

0.077 MM

ISL3,ISL4

0.077 MM

110_OHM_DI FF

0.330 MM

Y

=STANDARD

=STANDARD =STANDARD

110_OHM_DI FF

*

=STANDARD

N

=STANDARD

0.250 MM0.250 MM

27P4_OHM_S E

Y*

=STANDARD

0.210 M M

3X_DIEL ECTRIC

*

?

0.280 M M

*

4X_DIEL ECTRIC

?

5X_DIEL ECTRIC

0.350 M M

*

?

0.160 MM0.160 MM

0.175 MM 0.175 M M

Y

70_OHM_DIF F

ISL9,ISL10

0.135 MM

=STANDARD

0.135 MM

=STANDARD

*

40_OHM_SE

Y

0.180 MM0.180 MM

0.125 MM0.125 MM

Y

ISL3,ISL4

80_OHM_DIF F

0.180 MM 0.180 M M

0.125 MM0.125 MM

80_OHM_DIF FYISL9,ISL10

0.140 MM

0.190 MM0.190 MM

0.140 MM

80_OHM_DIF F

ISL2,ISL11

Y

0.190 MM 0.190 M M

0.140 MM

80_OHM_DIF F

TOP,BOTTOM

Y

0.095 MM

=STANDARD

N

=STANDARD

80_OHM_DIF F

*

=STANDARD

TOP,ISL2,IS L3,ISL4,ISL5 ,ISL6,ISL7, ISL8,ISL9,IS L10,ISL11,B OTTOM

15.5.1

MM

NO_TYPE,BGA

BGA

BGA_P2MM

*

CLK_FSB

0.077 MM

ISL2,ISL11

110_OHM_DI FF

Y

0.330 MM 0.330 M M

0.077 MM

Y

110_OHM_DI FF

TOP,BOTTOM

0.077 MM 0.077 MM

0.330 MM 0.330 M M

0.075 MM

0.125 MM 0.125 M M

Y

ISL9,ISL10

0.075 MM

100_DIFF_B GA

0.075 MM

0.125 MM 0.125 M MI SL3,ISL4

Y

0.075 MM

100_DIFF_B GA

=100_OHM_D IFF =100_OHM_DIFF

=100_OHM_D IFF =10 0_OHM_DIFF

*

=100_OHM_D IFF

=100_OHM_DIF F

100_DIFF_B GA

BGA

CLK_PCIE

*

BGA_P2MM

BGA

BGA_P1MM

* *

FSB_DSTB BGA_P 3MMFSB_DSTB

BGA

CLK_SLOW

*

BGA_P2MM

BGA

*

BGA_P2MM

MEM_CLK

0.1 MM

*

DEFAULT

?

=DEFAULT

* ?

BGA_P3MM

2:1_SPACIN G

?

0.2 MM

*

2.5:1_SPAC ING

?*

0.25 MM

?*

3:1_SPACIN G

0.3 MM

Apple Macbook Pro A1286 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual