Apple Macbook Pro A1286 Schematics

DRAWING

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

APPLE INC.

6

DESIGNER

DESCRI PTION O F CHAN GE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

TITLE

DRAWING N UMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/ FINISH

NOTED AS

APPLICABL E

SIZE

D

THIRD ANG LE PROJECT ION

DIMENSION S ARE IN M ILLIMETER S

XX

X.XX

X.XXX

DO NOT SC ALE DRAWIN G

REV

ZONE

ECN

CK APPD

DATE

ENG APPD

DATE

1. ALL RESIST ANCE V ALUES A RE IN OHMS, 0 .1 WAT T +/- 5 %.

2. ALL CAPACI TANCE VALUES ARE IN MICROF ARADS.

3. ALL CRYSTA LS & O SCILLAT OR VAL UES ARE IN HE RTZ.

ANGLES

Schematic / PCB #'s

08/18/2008

SCHEM,MBP 15"MLB

M98 SMBus Connections

45

DDR

07/22/20 08

52

LPC+SPI Debug Connector

44

CHANG_M9 8_MLB

07/01/20 08

51

SMC Support

43

AMASON_M 98_MLB

06/18/20 08

50

SMC

42

T18_MLB

06/18/20 08

49

Front Flex Support

41

CHANG_M9 8_MLB

07/01/20 08

48

External USB Connectors

40

AMASON_M 98_MLB

07/02/20 08

46

SATA Connectors

39

CHANG_M9 8_MLB

07/01/20 08

45

FireWire Ports

38

SENSOR

08/14/20 08

43

FireWire Port Power

37

SENSOR

08/14/20 08

42

FireWire LLC/PHY (FW643)

36

SENSOR

08/14/20 08

41

Ethernet Connector

35

SUMA_M98 _MLB

07/01/20 08

39

Ethernet & AirPort Support

34

SUMA_M98 _MLB

07/01/20 08

38

Ethernet PHY (RTL8211CL)

33

SUMA_M98 _MLB

07/01/20 08

37

ExpressCard Connector

32

YITE_M98 _MLB

07/02/20 08

35

Right Clutch Connector

31

YITE_M98 _MLB

07/02/20 08

34

DDR3 Support

30

T18_MLB

06/18/20 08

33

DDR3 SO-DIMM Connector B

29

DDR

07/22/20 08

32

DDR3 SO-DIMM Connector A

28

DDR

07/22/20 08

31

FSB/DDR3/FRAMEBUF Vref Margining

27

DDR

07/22/20 08

29

SB Misc

26

T18_MLB

12/17/20 07

28

MCP Graphics Support

25

AMASON_M 98_MLB

06/18/20 08

26

MCP Standard Decoupling

24

T18_MLB

06/18/20 08

25

MCP79 A01 Silicon Support

23

T18_MLB

03/31/20 08

24

MCP Power & Ground

22

T18_MLB

06/18/20 08

22

MCP HDA & MISC

21

T18_MLB

06/18/20 08

21

MCP SATA & USB

20

T18_MLB

06/18/20 08

20

MCP PCI & LPC

19

T18_MLB

06/18/20 08

19

MCP Ethernet & Graphics

18

T18_MLB

06/18/20 08

18

MCP PCIe Interfaces

17

T18_MLB

06/18/20 08

17

MCP Memory Misc

16

T18_MLB

06/18/20 08

16

MCP Memory Interface

15

T18_MLB

06/18/20 08

15

MCP CPU Interface

14

T18_MLB

06/18/20 08

14

eXtended Debug Port(MiniXDP)

13

M99_MLB

01/08/20 08

13

CPU Decoupling & VID

12

M87_MLB

10/17/20 07

12

CPU Power & Ground

11

M87_MLB

10/17/20 07

11

CPU FSB

10

M87_MLB

10/17/20 07

10

Signal Aliases

9

(MASTER)

9

Power Aliases

8

(MASTER)

8

Functional / ICT Test

7

N/A

N/A7

JTAG Scan Chain

6

DDR

07/22/20 08

6

BOM Configuration

5

N/A

N/A5

Power Block Diagram

4

N/A

N/A4

Power Block Diagram

3

T18_MLB

12/12/20 07

3

System Block Diagram

2

T18_MLB

12/12/20 07

2

MUXGFX

02/18/20 08

90

103

MCP Constraints 2

MUXGFX

02/18/20 08

89

102

MCP Constraints 1

MUXGFX

02/18/20 08

88

101

Memory Constraints

MUXGFX

02/18/20 08

87

100

CPU/FSB Constraints

MUXGFX

02/01/20 08

86

99

Misc Power Supplies

YITE_M98 _MLB

07/02/20 08

85

98

LCD Backlight Support

YITE_M98 _MLB

07/02/20 08

84

97

LCD BACKLIGHT DRIVER

MUXGFX

07/10/20 08

83

96

Graphics MUX (GMUX)

MUXGFX

07/10/20 08

82

95

1.1V / 1V8 FB Power Supply

MUXGFX

07/10/20 08

81

94

DisplayPort Connector

MUXGFX

07/10/20 08

80

93

Muxed Graphics Support

MUXGFX

02/25/20 08

79

90

LVDS Display Connector

M87_MLB

10/17/20 07

78

89

GPU (G84M) Core Supply

MUXGFX

07/10/20 08

77

88

NV G96 Video Interfaces

MUXGFX

07/09/20 08

76

87

G96 GPIOs & Straps

MUXGFX

07/10/20 08

75

86

NV G96 GPIO/MIO/Misc

MUXGFX

07/10/20 08

74

85

GDDR3 Frame Buffer B (Top)

MUXGFX

07/10/20 08

73

84

GDDR3 Frame Buffer A (Top)

MUXGFX

07/10/20 08

72

82

NV G96 Frame Buffer I/F

MUXGFX

07/10/20 08

71

81

NV G96 Core/FB Power

MUXGFX

07/10/20 08

70

80

NV G96 PCI-E

PWRSQNC

05/12/20 08

69

79

Power FETs

PWRSQNC

05/12/20 08

68

78

Power Control

M99_MLB

12/14/20 07

67

77

Misc Power Supplies

M99_MLB

12/14/20 07

66

76

CPU VTT Power Supply

M99_MLB

01/08/20 08

65

75

1.05V / MCP Core Regulator

M99_MLB

12/13/20 07

64

73

1.5V DDR3 Supply

M99_MLB

01/09/20 08

63

72

5V / 3.3V Power Supply

M87_MLB

10/17/20 07

62

71

IMVP6 CPU VCore Regulator

M99_MLB

12/10/20 07

61

70

PBus Supply & Battery Charger

T18_MLB

12/06/20 07

60

69

DC-In & Battery Connectors

AUDIO

07/09/20 08

59

68

AUDIO: JACK TRANSLATORS

AUDIO

07/09/20 08

58

67

AUDIO: JACKS

AUDIO

07/09/20 08

57

66

AUDIO:SPEAKER AMP

AUDIO

07/09/20 08

56

65

AUDIO: HEADPHONE AMP

AUDIO

07/09/20 08

55

63

AUDIO: LINE IN

AUDIO

07/09/20 08

54

62

AUDIO:CODEC

CHANG_M9 8_MLB

07/01/20 08

53

61

SPI ROM

SENSOR

08/14/20 08

52

59

Sudden Motion Sensor (SMS)

PWRSQNC

05/12/20 08

51

58

WELLSPRING 2

AMASON_M 98_MLB

06/18/20 08

50

57

WELLSPRING 1

M87_MLB

10/17/20 07

49

56

Fan Connectors

SENSOR

08/14/20 08

48

55

Thermal Sensors

SENSOR

08/14/20 08

47

54

Current Sensing

96

109

PCB Rule Definitions

M99_MLB

01/22/20 08

95

108

Project Specific Constraints

MUXGFX

02/21/20 08

94

107

GPU (G96) Constraints

MUXGFX

02/18/20 08

93

106

SMC Constraints

MUXGFX

02/18/20 08

92

105

FireWire Constraints

MUXGFX

02/18/20 08

SENSOR

08/14/20 08

46

53

Current & Voltage Sensing

CRITIC AL051-75 46

1

SCH

SCHEM, FIBBO, M98

Contents Sync

Date

(.csa)

Page

Table of Contents

1

N/A

N/A1

TITLE=ML B

ABBREV=D RAWING

91

104

Ethernet Constraints

MUXGFX

02/18/20 08

Contents Sync

(.csa)

Date

Page

CRITIC AL820-23 30

1

PCBF,F IBBO,M 98

PCB

Contents

(.csa)

Sync

Date

Page

A.0.0

SCHEM,MBP 15MLB

?

1

? ?

96

051-7546

LAST_MODI FIED=Mon Aug 18 01 :48:34 20 08

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

J9400

DISPLA Y PORT

J9000

CONN

LVDS

PG 71

CONN

PG 71

Conn

J4520

PG 17

(UP TO 1 2 DEVICE S)

4

TMDS OUT

Line O ut

2

CTRL

IR

J4710

CLK

SATA

(UP TO F OUR PORT S)

Conns

J6800,6801 ,6802,6803

PG 41

MCP79

PG 19

PCI

PG 19

LPC

3 8 9

PG 40

SATA

U6301 U6500U6400

PG 59

PG 56PG 55

HEADPH ONE

Audio

Codec

FSB

64-Bit

2 UDIMMs

XDP CONN

POWER SUPPLY

PG 28

J3400 U3900

PG 33

Conn

88E111 6

PG 31

GB

E-NET

Amp

Speake r

Amps

PG 54

PG 53

U6200

J4720

PG 57

J4710

U4900

J6950

PG 12

U1000

U1300

J4510

U6600,6605 ,6610,6620

PG 40

J4700

PG 40

HD

E-NET

ODD

Conn

SYNTH

PG 39

U6100

J3900,4635 ,4655

EXTERNAL

USB

PG 40

KEYBOARD

TRACKPAD/

USB

PG 45

POWER SENSE

J5650,5600 ,5610,5611, 5660,5720,5 730,5750

PG 48,49

J4900

DC/BATT

PENRYN

2.X OR 3.X GH Z

INTEL CPU

SPI

PG 20

PG 18

MEMORY

MAIN

800/1067 /1333 MHz

DDR2-800 MHZ

DDR3-106 7/1333MH Z

J2900

DIMM

PG 25,26

SPI

TEMP SENSOR

FAN CONN AND CONTROL

J5100

PG 43

Ser

FanADC

SMC

B,0

Prt

BSB

PWR

Misc

PG 14

Port80,serial

LPC Conn

GPIOs

SATA

1.05V/3GHZ .

RGB OUT

PG 38

PG 13

FSB INTE RFACE

PG 24

SMB

PG 20

HDA

NVIDIA

PG 41

CAMERA

Connecto rs

PG 44

CONN

SMB

DIMM's

10 5 6 7

Bluetooth

PG 52

Boot ROM

U1400

DVI OUT

PCI-E

PG 16

UP TO 20 LANES3

PG 17

LVDS OUT

DP OUT

HDMI OUT

RGMII

PG 18

AirPort

Mini PCI-E

U3700

Line I n

Amp Amp

PG 60

PG 9

System Block Diagram

SYNC_DA TE=12/ 12/2007

A.0.0

2 96

051-7546

SYNC_MA STER=T 18_MLB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

PP3V3_S 0GPU_F ET

P3V3S0_ SS

(PAGE 42)

S0PGOOD_PWROK

P1V5S0_PGOOD

P3V3S3_ SS

(18A MAX CURRENT)

GPUVCORE_IOUT

RSMRST_ IN(P13 )

IMVP_VR _ON

PLT_RST *

PWR_BUT TON(P9 0)

PM_PWRB TN_L

SMC_ONO FF_L

RSMRST_ PWRGD

MCP_PS_PWRGD

PWROK

CPUPWRG D(GPIO 49)

PLT_RST_L

CK_PWRG D

VR_PWRGD_CLKEN

VRMPWRG D

PP5V_S0 _FET

(25A MAX CURRENT)

(5A MAX CURRENT)

PM_SLP_S3_DELAY_L

SMC_ADAPTER_EN

PPVBAT_G3H_CHGR_R

CHGR_BGATE

J6950

BATT_POS_F

6A FUSE

DCIN(16.5V)

U7000

ISL6258A

BATTERY CHARGER

PBUS SUPPLY/

(PAGE 60)

PM_SLP_ S5_L

PM_SLP_ S4_L

PM_SLP_ S3_L

U4900

SLP_S3_ L(P93)

SLP_S4_ L(P94)

SLP_S5_ L(P95)

SMC_RESET_L

PM_RSMRST_L

99ms DLY

RSMRST_ OUT(P1 5)

PWRGD(P1 2)

IMVP_VR _ON(P1 6)

PP1V05_ S5_MCP

(PAGE 68)

LTC2900

P1V8S0_PGOOD

CPUVTTS0_PGOOD

MCPCORES0_PGOOD

P5VRIGHT_PGOOD

P1V05S0_PGOOD

P5VS0_SS

Q7900

PP5V_S3 _FET

P5VS3_SS

Q7910

PP3V3_S 3_FET

PP3V3_S 0_FET

P3V3GPU _SS

P3V3_EN ET_FET

P3V3ENE T_EN_L

(12A MA X CURR ENT)

PPDDR_S 3_REG

PPVTT_S 0_DDR_ LDO

PP5V_RT_REG

MCPCPCORE_S0_REG

(PAGE 65)

ISL6236

U7500

1.1V

MCP_CORE

P1V05S0_EN

MCPCORES0_EN

CPUVTTS0_EN

MCPDDR_EN

P1V8S0_EN

P5VRIGHT_EN

P5VS0_EN

PM_SLP_S3_L

Q3800

WOL_EN

PM_ENET _EN_L

DDRVTT_EN

DDRREG_EN

U7300

(PAGE 63)

TPS51116

0.9V

1.8V

PPVIN_S0_DDRREG_LDO

P1V2ENET_EN

ENETAVDD_EN

PP1V2_E NET_RE G

PP1V9_E NET_RE G

(PAGE 33)

U3850

LTC3407

GOSHAW K6P

PPVOUT _S0_LC DBKLT

Q7930

Q7970

P5V3V3_ S5_PGOOD

P5V_RT _PGOOD

PP5V_R T_REG

PP3V3_S 5_REG (5.5A M AX CUR RENT)

PP5V_S5 _REG (8A MAX CURRE NT)

(PAGE 66)

U7750

ISL8009

CPUVTTS0_PGOOD

PPCPUVTT_S0_REG

CPUVTTS0_EN

PGOOD

(PAG 66)

U7600

TPS51117

VOUT

PP3V42_G3H_REG

(PAGE 59)

U6990

LT3470

3.425V G3HOT

GPU VCORE

U8900

ISL6263B

ISL9504B

CPU VCORE

(PAGE 62)

U7201

TPS51125

3.3V

5V

(PAGE 82)

U9500

TPS511 24

1.8V(R /H)

1.103V (L/H)

VIN

U7400

SC417

(PAGE 64)

(PAGE 84)

U9701

V4

PP1V8_GPU_REG

VOUT1

RST*

U7870

V1 V2 V3 V4

PP1V5_S0_REG

PP3V3_S0

PP5V_S0

VIN

VOUT2

CPUVCORE_IOUT

PPVCORE_CPU_S0

VOUT2

VLDOIN

P3V3S5_EN

(R/H)

VOUT1

EN1

P1V1GPU_EN

PPBUS_G3H

U5400

PP1V1_S0GPU_REG

(PAGE 61)

Q7920

PM_ENET_EN_L

(S0)

P3V3S0_EN

DELAY

Q3805

SMC

LIO_DCIN_ISENSE

Q7055

VOUT1

VIN

EN0

VREG3

ENL

VIN

EN2

VIN

IN

SMC_RESET_L

ENABLE

U5000

RN5VD30A-F

VIN

(L/H)

ADAPTER

VOUT

P1V8FB_EN

VIN

VR_ON

VOUT

A

VIN

U2830

VOUT2

PGOOD1,2

VOUT2

U2850

CPU

U1000

SMC

PWRBTN#

PLTRST*

PWRGOOD

(PAGE 10,11)

RESET*

EN/PSV

S3

RUN1

ENA

EN2

VOUT1

RUN2

S5

VR_PWRGOOD_DELAY

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

RC

MCP79

RSMRST*

U1400

(PAGE 14~22)

U1400

3S2P

A

P60

P5V_RT_EN

PBUSB_VSENSE

Q5315

ENABLES

A

AC

PM_GPUVCORE_EN

SMC PWRGD

IMVP_VR_ON_R

(PAGE 78)

PGOOD

U5498

SMC_GPU_VSENSE

VOUT

D6905

VOUT

U4900

VIN

BKLT_EN

(PAGE 14~22)

SLP_S3#(G17)

SLP_S5#(H17)

Q3810

VOUT

VIN

(S0)

MCP79

(S0)

PBUSVSENS_EN

U7859

SMC_PM_G2_EN

(S5)

PGOOD

Q3801

WOW_EN

PM_ENET_EN

PM_WLAN_EN_L

P17(BTN_OUT)

(PAGE 42)

U5705

PPVCORE_GPU_REG

V

A

LIO_S3_EN

P5VS3_EN

P3V3S3_EN

(9 TO 12.6V)

U5715

8A FUSE

D6905

PPVBAT_G3H_CHGR_REG

SMC_BATT_ISENSE

EN_PSV

GPUVCORE_PGOOD

SMC_CPU_VSENSE

V

VR_PWRGD_CLKEN_L

VIN

U7100

PGOOD

RST*

ALL_SYS_PWRGD

VOUT2

EN1

DELAY

PPBUS_G3H

V

PPVIN_G3H_P3V42G3H

PP3V3_S 5

PP5V_S3

(S5)

CHGR_EN

1.05V

EN_PSV

(PAGE 43)

CPU_PWRGD

(6A MAX CURRENT)

M98 POWER SYSTEM ARCHITECTURE

SYNC_MA STER=T 18_MLB

051-7546

96

A.0.0

SYNC_DA TE=12/ 12/2007

3

Power Block Diagram

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

SYNC_MA STER=N /A

SYNC_DA TE=N/A

4 96

A.0.0

051-7546

Power Block Diagram

www.laptop-schematics.com

BOM OP TIONS

BOM GR OUP

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

PART NUMB ER

ALTERNATE FOR

PART NUMB ER

BOM OPTIO N

REF DES

COMMENTS:

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

BOM OP TIONS

BOM GR OUP

BOM OP TIONS

BOM NA ME

BOM NU MBER

BOM Variants

Bar Code Labels / EEE #'s

Module Parts

M98 BOM Groups

M98_CO MMON

ALTERN ATE,CO MMON,M9 8_COMM ON1,M9 8_COMM ON2,M98 _COMMO N3,M98 _DEBUG ,M98_P ROGPART S

M98_DE BUG

M98_PR OGPART S

M98_CO MMON3

630-95 86

M98_COM MON,EEE_ 2NJ,CPU_ 2_8GHZ,F B_512_Q IMONDA

PCBA,2 .8GHZ, 512QIM_ VRAM,M 98

630-93 35

M98_COM MON,EEE_ 0ZB,CPU_ 2_4GHZ,F B_256_H YNIX

PCBA,2 .4GHZ, 256HYN_ VRAM,M 98

630-93 34

M98_COM MON,EEE_ 0ZA,CPU_ 2_4GHZ,F B_256_S AMSUNG

PCBA,2 .4GHZ, 256SAM_ VRAM,M 98

CRITIC AL826-4393

1

EEE_2N H

LBL,P/N LABEL,P CB,28MM X 6 MM

[EEE:2 NH]

BOM Configuration

5 96

051-7546

SYNC_MA STER=N /A

SYNC_DA TE=N/A

A.0.0

U4900

SMC_PRO G

341S22 89

1

CRITIC AL

IC,SMC, DEVELOPM ENT,M98

CRITIC AL

MCP_B0 1

U1400

338S06 00

1

IC,GMCP,M CP79-B01, 35x35MM,B GA1437

CRITIC AL1CPU_2_ 5GHZ

337S36 40

IC,PDC,SL3B X,PRQ,2.53G, 35W,1066,C0 ,6M,BGA

U1000

[EEE:0 ZD]

1

EEE_0Z D

CRITIC AL826-4393

LBL,P/N LABEL,P CB,28MM X 6 MM

1

CRITIC AL826-4393

EEE_0Z B

[EEE:0 ZB]

LBL,P/N LABEL,P CB,28MM X 6 MM

U4800

1

341S23 84

IR,ENCORE II, CY7C 63803-LQX C

CRITIC AL

1

338S05 54

IC,GPU, 55nm,NV G96-GS, BGA969, LF

U8000

M98_COM MON,EEE_ 0ZD,CPU_ 2_5GHZ,F B_512_Q IMONDA

630-93 37

PCBA,2 .5GHZ, 512QIM_ VRAM,M 98

VRAM4, VRAM_2 56_HYNI X

FB_256_ HYNIX

CRITIC AL

1

LBL,P/N LABEL,P CB,28MM X 6 MM

826-43 93

EEE_2N J

[EEE:2 NJ]

CRITIC AL

[EEE:0 ZC]

826-43 93

EEE_0Z C

1

LBL,P/N LABEL,P CB,28MM X 6 MM

CRITIC AL

1

338S05 63

U4900

SMC_BLA NK

IC,SMC, HS8/2117 ,9MMX9M M,TLP

U8770

HDCP_YE S

341S22 72

1

IC,HDCP R OM,NVG96, 8 PIN SO IC,LF,HF

CRITIC AL

CRITIC AL1CPU_2_ 4GHZ

337S36 39

IC,PDC,SLB4 N,PRQ,2.4G,2 5W,1066,M0, 3M,BGA

U1000

630-93 36

M98_COM MON,EEE_ 0ZC,CPU_ 2_5GHZ,F B_512_S AMSUNG

PCBA,2 .5GHZ, 512SAM_ VRAM,M 98

FB_512_ QIMONDA

VRAM4, VRAM_5 12_QIMO NDA

CRITIC AL

1

U3700

338S05 70

IC,RTL821 1CL,GIGE TRANSCEIV ER,48P TQ FP

CRITIC AL

1

U4100

338S05 23

IC,FW643-06 ,1394B PHY/O HCI LINK/PC I-E,12

338S06 35

IC,GMCP,M CP79-B02, 35x35MM,B GA1437

CRITIC AL

1

U1400

MCP_B0 2

BOOTROM _PROG

U6100

1

IC,EFI ROM,DEVE LOPMENT ,M98

341S23 66 CRITIC AL

CRITIC AL

1

U6100

BOOTROM _BLANK

335S03 84

IC,32MBIT 8-PIN SPI SERIAL F LASH,SOIC8

IC,SGRAM, GDDR3,16M x32,800MH Z,136 FBG A

U8400,U84 50,U8500,U 8550

VRAM_25 6_SAMSUN G

333S04 82 CRITIC AL

4

IC,SGRAM, GDDR3,32M x32,900MH Z,136 FBG A

VRAM_51 2_QIMOND A

CRITIC AL

4

333S04 72

U8400,U84 50,U8500,U 8550

341S23 83

IC,PSOC +W/USB, 56PIN,M LF,M98

CRITIC AL

1

U5701

TPAD_PR OG

138S0603

ALL

138S0602

Murata alt to Samsung

U8400,U84 50,U8500,U 8550

IC,SGRAM, GDDR3,32M x32,900MH Z,136 FBG A

VRAM_51 2_SAMSUN G

CRITIC AL333S0481

4

U8400,U84 50,U8500,U 8550

333S04 83

IC,SGRAM, GDDR3,16M x32,900MH Z,136 FBG A

4

CRITIC AL

VRAM_25 6_HYNIX

337S36 41

CPU_2_ 8GHZU1000

CRITIC AL

1

IC,PDC,SLB4 3,PRQ,2.8G,3 5W,1066,C0, 6M,BGA

ALL

353S1294

LMV2011,OPAMP. GBW

353S1681

ALL

514-0608

FOXLINK RCVR A LT TO FOXCONN

514-0613

ALL

157S0055

Delta alt to T DK Magnetics

157S0058

ALL

514-0607514-0612

FOXLINK XCVR A LT TO FOXCONN

152S0796

ALL

152S0915

Maglayers alt to Cyntec IND

ALL

341S2366341S2367

Macronix alt t o SST

353S1466

ALL

INTERSIL ALT T O INTERSIL

353S2312

ALL

152S0876 152S0867

Maglayer alt t o Delta

ALL

152S0276 152S0683

Maglayers alt to Dale/Vishay

CRITIC AL

LBL,P/N LABEL,P CB,28MM X 6 MM

1

826-43 93

EEE_0Z A

[EEE:0 ZA]

VRAM4, VRAM_5 12_SAMS UNG

FB_512_ SAMSUNG

630-95 85

M98_COM MON,EEE_ 2NH,CPU_ 2_8GHZ,F B_512_S AMSUNG

PCBA,2 .8GHZ, 512SAM_ VRAM,M 98

M98_CO MMON1

ONEWIR E_PU,I SL6258A ,MEMRE SET_HW ,MEMRE SET_MCP ,MCP_B 02,MCP _PROD, MCPSEQ _SMC

M98_CO MMON2

BKLT_P LL_NOT ,BMON_E NG,MIK EY,BOO T_MODE _USER,G PUVID_ 1P00V, MUXGFX

VRAM4, VRAM_2 56_SAMS UNG

FB_256_ SAMSUNG

DPMUX_ EN_S0, DP_ESD, EG_PWR SEQ_HW ,DP_CA _DET_EG _PLD,M CP_CS1 _NO

GMUX_P ROG,BO OTROM_P ROG,SM C_PROG ,TPAD_ PROG

SMC_DE BUG_YE S,XDP,L PCPLUS ,VREFM RGN

www.laptop-schematics.com

IN

B1

OE*

VCCB

B2

B3

B4

GND

A4

A3

A2

A1

VCCA

OUT

GND

VCC

NCNC

YA

NC NC

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

TDO

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

From XDP connector

or via level translator

GPU

U9200

GMUX

U8000

MCP

U1400

From XDP connector

U1000

CPU

To XDP connector and/or level translator

XDP connector

TMS

TCK

TDI

GMUX CPLD Programming Port

6

10 13 87

NLSV4T244

UQFN

JTAG_ALLD EV

CERM

10V

402

20%

0.1UF

JTAG_AL LDEV

20% 10V CERM 402

JTAG_AL LDEV

0.1UF

JTAG_AL LDEV

5%

10K

1/16W MF-LF

402

0

1/16W

5%

MF-LF

402

NOSTUFF

13

CRITIC AL

1909782

M-RT-SM

402

MF-LF

1/16W

5%

0

XDP

PLACEM ENT_NO TE=Plac e near pin U 1000.A B3

0

1/16W MF-LF

5%

402

XDP

PLACEM ENT_NO TE=Plac e near pin U 1400.F 19

74LVC1G 07

SOT886

PLACEM ENT_NO TE=Plac e clos e to U 0600

5%

MF-LF

1/16W

10K

NOSTUFF

402

PLACEM ENT_NO TE=Plac e clos e to U 8000

10K

5% 1/16W MF-LF 402

6

10 13 87

6

10 13 87

13

051-7546

A.0.0

966

SYNC_MAS TER=DDR

SYNC_DAT E=07/22/ 2008

JTAG Scan Chain

=PP1V05_ S0_CPU

MAKE_BASE= TRUE

JTAG_M CP_TRS T_L

XDP_TC K

XDP_TD O

JTAG_G MUX_TC K

GPU_JT AG_TRS T_L

GPU_JT AG_TMS

=PP3V3_S 0_XDP

JTAG_M CP_TDI

JTAG_G MUX_TM S

GPU_JT AG_TCK

GPU_JT AG_TDO

MAKE_BASE= TRUE

TP_GPU _JTAG_ TDO

JTAG_M CP_TDO_ CONN

GPU_JT AG_TMS

=PP3V3 _GPU_V DD33

XDP_TR ST_L

XDP_TM S

XDP_TC K XDP_TD I

XDP_TD O_CONN

MAKE_BASE= TRUE

JTAG_M CP_TDO

GPU_JT AG_TDI

XDP_TM S XDP_TR ST_L

=PP3V3_S 0_XDP

JTAG_L VL_TRA NS_EN_L

JTAG_G MUX_TD O

JTAG_M CP_TMS

MAKE_BASE= TRUE

JTAG_M CP_TCK

JTAG_G MUX_TD I

U0600

2

3

4

5

10

9

8

7

6

12

1

11

C0601

1

2

C0602

1

2

R0601

1

2

R0602

1

2

J0600

7

8

1

2

3

4

5

6

R0603

1 2

R0604

1 2

U0601

2

3

1

5

6

4

R0605

1 2

R0606

1

2

62 13 12

87

11

13

23

76

13

23

10

21

10

87

75

8

21

83

75 75

10

8

83

21

83

8

13

6

10

83

75

6

13

9

75

6 8

21

75

6

9

13

9

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

FUNC_T EST

5 TPs

SATA ODD Connectors

KEYBOARD CONN

Speaker Connectors

FUNC_T EST

Fan Connectors

IPD_FLEX_CONN

LVDS Connectors

POWER RAILS

6 TPs

5 TPs

FUNC_T EST

CPU FSB NO_TESTs

NO_TEST

ICT Test Points

FUNC_T EST

3 TPs

per Fa n

4 TPs

Functional Test Points

per Fa n

FUNC_T EST

EXCARD Connector

I557

I558

I559

I560

I561

I562

I563

I564

I565

I566

I567

I568

I569

I570

I571

I572

I573

I574

I575

I576

I577

I578

I579

I580

I581

I582

I583

I584

I585

I586

I587

I588

I589

I590

I591

I592

I593

I594

I595

I596

I597

I598

I600

I602

I603

I604

I605

I606

I607

I608

I609

I610

I611

I612

I613

I614

I615

I616

I617

I618

I619

I620

I621

I622

I623

I624

I625

I626

I627

I636

I637

I638

I639

I640

I641

I642

I643

I644

I645

I646

I647

I648

I649

I650

I651

I652

I653

I654

I655

I656

I657

I709

I710

I711

I712

I713

I714

I715

I716

I717

I718

I719

I720

I721

I722

I723

I724

I725

I726

I727

I728

I729

I730

I731

I732

I733

I734

I735

I736

I737

I739

I740

I741

I742

I743

I744

I745

I746

I747

I748

I749

I750

I751

I752

I753

I754

I755

I756

I757

I758

I759

I760

I761

I762

I763

I764

I765

7 96

A.0.0

051-7546

Functional / ICT Test

SYNC_MA STER=N /A

SYNC_DA TE=N/A

PP3V3_ S5_AVRE F_SMC

TRUE

PP3V3_S3_LDO

TRUE

PP1V8_ S0GPU_ ISNS_R

TRUE

PP0V9R0 V75_S0_D DRVTT

TRUE

PPCPUFS B_ISNS_R

PPCPUVTT _S0

TRUE

PP1V2R1 V05_S5

TRUE

PP1V05_S 0_REG

TRUE

PP1V8_S 0

PP1V2_ S0

TRUE

PP2V5_ S0

TRUE

PP3V3_ S0

TRUE

PP3V3_ S3

TRUE

PP3V3_ S5

TRUE

PP5V_S 0

TRUE

PP5V_S 3

TRUE

PP3V42 _G3H

TRUE

PPBUS_ CPU_IM VP_ISNS

PPBUS_ G3H

TRUE

PM_SLP_ S3_L

TRUE

SATA_O DD_D2R _C_P

TRUE

SATA_O DD_D2R _C_N

TRUE

SATA_O DD_R2D _N

TRUE

SATA_O DD_R2D _P

PCIE_C LK100M _EXCARD _CONN_ N

TRUE

FSB_DI NV_L<3 ..0>

TRUE

FSB_DS TB_L_N <3..0>

TRUE

FSB_HI T_L

TRUE

FSB_DS TB_L_P <3..0>

TRUE

FSB_HI TM_L

TRUE

FSB_LO CK_L

FSB_D_ L<63.. 0>

TRUE

LED_RETU RN_5

PCIE_E XCARD_ D2R_P

TRUE

PP1V8_ S0GPU_ ISNS

TRUE

LED_RETU RN_4

LED_RETU RN_3

TRUE

=PP5V_ S0_FAN _LT

EXCARD _CLKRE Q_CONN_ L

TRUE

SPKRCO NN_S_N _OUT

SPKRCO NN_R_P _OUT

TRUE

EXCARD _CPUSB _L

TRUE

EXCARD _CPPE_ L

PLT_RE SET_SW ITCH_L

TRUE

PP1V5_ S0_EXC ARD_SWI TCH

TRUE

PCIE_E XCARD_ R2D_N

TRUE

BI_MIC _LO

FAN_LT _TACH

TRUE

LVDS_CON N_A_DATA _N<0>

LVDS_CON N_A_CLK_ F_N

TRUE

LVDS_CON N_B_DATA _P<0>

TRUE

LVDS_CON N_A_CLK_ F_P

LVDS_CON N_A_DATA _N<2>

TRUE

LVDS_CON N_A_DATA _P<1>

TRUE

LVDS_CON N_A_DATA _N<1>

TRUE

LVDS_CON N_B_CLK_ F_N

LVDS_CON N_B_DATA _N<1>

TRUE

FAN_RT _TACH

FSB_AD S_L

TRUE

FSB_AD STB_L< 1..0>

TRUE

FSB_A_ L<31.. 3>

TRUE

LED_RETU RN_2

TRUE

LED_RETU RN_1

TRUE

LVDS_CON N_A_DATA _P<0>

LVDS_DDC _DATA

TRUE

LVDS_CON N_B_DATA _P<1>

LVDS_CON N_A_DATA _P<2>

TRUE

FAN_LT _PWM

TRUE

LVDS_CON N_B_DATA _N<0>

TRUE

LVDS_CON N_B_CLK_ F_P

TRUE

LVDS_CON N_B_DATA _N<2>

LVDS_CON N_B_DATA _P<2>

TRUE

PCIE_C LK100M _EXCARD _CONN_ P

TRUE

LED_RETU RN_6

FAN_RT _PWM

TRUE

SMC_ODD _DETECT

TRUE

SPKRCO NN_R_N _OUT

TRUE

BI_MIC _HI

SPKRCO NN_L_P _OUT

TRUE

WS_KBD6

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD11

TRUE

WS_KBD12

TRUE

WS_KBD13

TRUE

WS_KBD14 WS_KBD15_CAP

TRUE TRUE

WS_KBD16_NUM

TRUE

WS_KBD20 WS_KBD21

TRUE TRUE

WS_KBD22

TRUE

WS_KBD23 WS_KBD_ONOFF_L

TRUE

PSOC_SCLK

TRUE

Z2_RESET

TRUE

Z2_KEY_ACT_L

Z2_HOST_INTN

TRUE

Z2_BOOST_EN

TRUE

WS_KBD2

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

SPKRCO NN_L_N _OUT

TRUE

WS_KBD17

PP1V8R1V 5_S0_FET

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_CONTROL_KBD

TRUE

TPAD_GND_F

KBDLED_ANODE

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_KBD19

TRUE

WS_KBD5

TRUE

WS_KBD7

WS_KBD10

TRUE

WS_KBD18

TRUE

PPVCOR E_S0_C PU

TRUE

PPMCPDDR _ISNS

PP3V3_ S0GPU

TRUE

PPDCIN _G3H

TRUE

PPVOUT _S0_LC DBKLT

TRUE

PPVCOR E_GPU

TRUE

PPVTTD DR_S3

TRUE

PP1V8_ GPUIFPX

TRUE

PCIE_E XCARD_ D2R_N

TRUE

USB2_E XCARD_ CONN_P

TRUE

USB2_E XCARD_ CONN_N

TRUE

PCIE_E XCARD_ R2D_P

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

BI_MIC _SHIEL D

TRUE

PSOC_MOSI

TRUE

PSOC_F_CS_L

TRUE

Z2_BOOT_CFG1

TRUE

PP3V42_G3H

TRUE

SPKRCO NN_S_P _OUT

TRUE

LVDS_DDC _CLK

TRUE

BKL_SYN C

TRUE

PP3V3_SW _LCD

TRUE

=PP3V3_S 0_DDC_LC D

TRUE

FSB_RE Q_L<4. .0>

TRUE

WS_KBD1

TRUE

WS_KBD4

WS_KBD3

TRUE

PP1V0_ FW

PP1V1_S0 GPU_REG

TRUE

PP1V8R1V 5_S3

TRUE

PP1V2R 1V05_E NET

PPVP_F W

TRUE

PP3V3_ ENET_P HY

PSOC_MISO

TRUE

Z2_CLKIN

TRUE

Z2_SCLK

TRUE

Z2_MISO

TRUE

Z2_MOSI

TRUE

Z2_DEBUG3

TRUE

Z2_CS_L

TPAD_GND_F

TRUE

PP18V5_S3

TRUE

PICKB_L

TRUE

PP5V_SW _ODD

TRUE

PP3V3_ S0_EXC ARD_SWI TCH

TRUE

PP3V3_ S3_EXC ARD_SWI TCH

SMBUS_MC P_0_DATA

TRUE

SMBUS_MC P_0_CLK

TRUE

PPVCOR E_S0_MC P

PPVCOR E_S0_MC P_REG

TRUE

GND

TRUE

GND

83 81 68 44 42

90

43

37

87

89

95

94

87

94

95

89

95

43

95

79

87

45

43

95

8

46

34

89

95

14

84

32

84

49

58

89

59

80

94

80

94

80

94

80

14

84

80

94

80

95

84

42

58

59

58

51

93

58

51

84

32

95

89

93

59

51

8

58

80

84

76

14

51

21

42

51

8

7

8

21

39

32

10

79

17

8

79

8

32

57

32

58

49

79

49

10

79

49

79

32

79

49

39

57

58

57

50

51

50

45

57

50

8

50

7

51

50

8

79

8

17

32

45

58

50

7

57

79

8

10

50

8

50

7

51

50

39

32

13

8

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

"G3Hot" (Always-Present) Rails

5300 mA

241 mA max load

1034 mA

Chipset "VCore" Rails

139 mA/ 0 mA

105 mA/ 241 mA

1182 mA

4500 mA

1.8V/DDR 1.5V Rails

5V Rails

3.3V-2.5V Rails

"GPU" Rails

500 mA max supp ly

"FW" (FireWire) Rails

190 mA

500 mA

130 mA

4771 mA

(1.1V f or A01)

OR 0.75 V

ENET Rails

Power Aliases

SYNC_MA STER=( MASTER)

051-7546

A.0.0

968

SYNC_DA TE=(MA STER)

=PPVP_ FW_POR T1 =PPVP_ FW_PHY _CPS_FE T

=PP3V3 _S0GPU _FET

=PP3V3 _FW_FW PHY

=PP1V0 _FW_RE G

=PP1V05 _S0_MCP_ SATA_AVD D0

PP1V2R1 V05_S5

MIN_NECK_W IDTH=0.2 m m VOLTAGE=1. 05V MAKE_BASE= TRUE

MIN_LINE_W IDTH=0.6 m m

=PP3V3 _FW_RE G

=PP1V5 _FC_CO N

=PP3V3 _S3_SM BUS_SMC _A_S3

=PP3V3 _FW_RE G

=PPBUS_G 3H

PPBUS_ CPU_IM VP_ISNS

MIN_LINE _WIDTH=0 .4 mm

MAKE_BAS E=TRUE

VOLTAGE= 12.6V

MIN_NECK _WIDTH=0 .25 mm

=PP3V3 _S3_FE T

=PPVIN _S5_P5V P3V3

=PP3V3 _S0_SM BUS_SMC _B_S0

=PP3V3 _S0_CP UTHMSNS

=PP3V3 _S0_IM VP

=PP3V3 _S0_XD P

=PP3V3 _S0_MCP COREIS NS

=PP3V3 _S0_FA N_RT

=PPVCO RE_S0_M CP

PP1V2_ S0

MIN_LINE_W IDTH=0.6 m m MIN_NECK_W IDTH=0.2 m m

MAKE_BASE= TRUE

VOLTAGE=1. 2V

=PP2V5 _S0_GM UX

=PP1V0 5_ENET _FET

=PP3V3 _S0_MCP

=PP1V8R1 V5_S0_MC P_FET

=PPVIN_S 0_DDRREG _LDO

=PPVIN _S5_CP U_IMVP_ ISNS

=PP3V4 2_G3H_C HGR

=PP3V4 2_G3H_ TPAD

=PP3V4 2_G3H_ CPUCORE ISNS

=PP18V 5_DCIN _CONN

=PP3V3 _S0_EX CARD =PP3V3 _S0_LV DSDDCMU X

=PP3V3 _S0_OD D

=PP3V3 _S0_AU DIO

=PPSPD _S0_MEM _B

=PPSPD _S0_MEM _A

=PP3V3 _S0_DD C_LCD

=PP3V3 _S0_PW RCTL

=PP3V3 _S0_FA N_LT

=PPVIN _S0GPU _P1V8P1 V1

=PP3V3 _S0_GP UTHMSNS

=PP3V3 _S0_SMB US_MCP _1

=PP3V3_ GPU_SMBU S_SMC_0_ S0

MIN_LINE_W IDTH=0.6 m m

MAKE_BASE= TRUE

MIN_NECK_W IDTH=0.2 m m

PP2V5_ S0

VOLTAGE=2. 5V

=PP1V2 _S0_GM UX

=PP1V8 _GPU_I FPX

VOLTAGE= 1.8V MAKE_BAS E=TRUE

MIN_LINE _WIDTH=0 .6 mm

PP1V8_ GPUIFPX

MIN_NECK _WIDTH=0 .15 mm

=PP1V1_G PU_IFPCD _IOVDD

=PP1V1_G PU_VID_P LLVDD

=PP1V1_G PU_H_PLL VDD

=PP1V1_G PU_PLLVD D

=PP1V1 _S0GPU _REG

=PP1V1_G PU_PEX_P LLXVDD

=PP1V1_G PU_PEX_I OVDDQ

=PP1V1_G PU_PEX_I OVDD

=PP1V1_G PU_FBPLL AVDD

MAKE_BAS E=TRUE

PP1V8_ S0GPU_ ISNS

MIN_LINE _WIDTH=0 .6 mm

VOLTAGE= 1.8V

MIN_NECK _WIDTH=0 .2 mm

=PP1V8 _GPU_F B_VDDQ

=PP1V8 _GPU_F BIO

=PP3V3 _GPU_P 1V8S0

=PP1V8 _GPU_F B_VDD

=PP1V8 _GPU_F BVDDQ

=PP1V8 _S0GPU _ISNS

=PP1V5_S 3_MEM_A

=PP1V5_S 3_MEM_B

=PP3V3 _ENET_ MCP_RMG T

=PPVTT_ S0_VTTCL AMP

=PP0V75 _S0_MEM_ VTT_B

=PP0V75 _S0_MEM_ VTT_A

=PP1V05 _ENET_P1 V05ENETF ET

=PP1V05 _S5_MCP_ VDD_AUXC

=PP5V_ S3_MCP DDRFET

=PP5V_ S3_GPU VCORE

=PP5V_ S3_WLA N

MIN_NECK _WIDTH=0 .25 mm

MIN_LINE _WIDTH=0 .5 mm

MAKE_BAS E=TRUE

PP5V_S 3

VOLTAGE= 5V

=PP5V_ S3_BTCA MERA

PPVCOR E_S0_C PU

VOLTAGE= 1.25V

MIN_LINE _WIDTH=0 .6 mm

MAKE_BAS E=TRUE

MIN_NECK _WIDTH=0 .25 mm

=PP3V3 _GPU_V CORELOG IC =PP3V3 _S5_SM C =PP3V3 _S5_LP CPLUS

=PP3V4 2_G3H_ SMBUS_S MC_BSA

=PP1V8R1 V5_S0_FE T

=PP1V2 _S0_RE G

=PP2V5 _S0_RE G

=PP5V_ S3_P1V 05S0FET

=PP1V05 _S5_P1V0 5S0FET

=PP3V3 _ENET_ FET

=PP3V3 _ENET_ PHY

=PP1V0 5_ENET _PHY

=PP1V0 5_ENET _MCP_RM GT

=PP1V0 5_ENET _MCP_PL L_MAC

VOLTAGE =3.3V MAKE_BA SE=TRU E

MIN_NEC K_WIDT H=0.2 m m

PP3V3_ ENET_P HY

MIN_LIN E_WIDT H=0.6 m m

VOLTAGE =1.05V

PP1V2R 1V05_E NET

MIN_LIN E_WIDT H=0.4 M M MIN_NEC K_WIDT H=0.2 m m

MAKE_BA SE=TRU E

=PPVCO RE_S0_ CPU_REG

PP1V8_S 0

MIN_LINE_W IDTH=0.5 m m MIN_NECK_W IDTH=0.2 m m VOLTAGE=1. 8V MAKE_BASE= TRUE

=PP3V3 _GPU_M IO

=PP3V3 _GPU_V DD33

=PP3V3R 1V8_S0_M CP_IFP_V DD

PPVCOR E_GPU

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .2 mm VOLTAGE= 1.2V MAKE_BAS E=TRUE

MIN_LINE _WIDTH=0 .6 mm

MAKE_BAS E=TRUE

VOLTAGE= 1.25V

MIN_NECK _WIDTH=0 .2 mm

PP1V8_ S0GPU_ ISNS_R

=PPVCO RE_GPU

=PP1V8 _S0GPU _ISNS_R

=PPVCO RE_GPU _REG

=PP1V8 _GPU_R EG

=PPBUS _S5_FW _FET

=PP1V0 _FW_FW PHY

MIN_LINE _WIDTH=0 .4 mm

VOLTAGE= 1.00V MAKE_BAS E=TRUE

MIN_NECK _WIDTH=0 .2 mm

PP1V0_ FW

=PPMCP CORE_S0 _REG

=PPDDR_S 3_REG

PP1V05_ S0_MCP_S ATA_AVDD

MAKE_BASE=T RUE

=PP3V4 2_G3H_ PWRCTL

=PP3V3 _S5_RTC _D

=PP5V_ S3_AUD IO_PWR

=PP5V_ RT_REG

=PP5V_ S0_CPUV TTS0

=PP3V4 2_G3H_ SMCUSBM UX

MIN_LINE _WIDTH=0 .4 mm MIN_NECK _WIDTH=0 .2 mm VOLTAGE= 12.6V MAKE_BAS E=TRUE

PPVP_F W

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm

MAKE_BASE=T RUE

VOLTAGE=1.0 5V

PPVCOR E_S0_MC P_REG

=PPVTT_S 3_DDR_BU F

=PP3V3 _FW_P1 V0FW

=PP5V_ S0_CPU _IMVP

=PP5V_ S3_RTU SB

=PP5V_ S3_DDR REG

=PP5V_ S3_IR

=PP5V_ S3_SYS LED

=PPVIN _S5_SM CVREF

=PPVIN _S5_CP U_IMVP

=PP5V_ S0_FAN _RT

=PP3V3 _S3_P3 V3S3FET

=PP3V3 _S5_MC P_A01

=PP3V3 _S5_RE G

=PP3V3 _FW_LA TEVG_AC TIVE

=PP3V3 _S5_ME MRESET

=PP3V3_ S0_BATT CHARGER TMPSNSR

=PP5V_ S3_REG

=PP3V4 2_G3H_ REG

=PP1V05 _S0_MCP_ PEX_AVDD 1

=PP3V3 _S3_VRE FMRGN

=PP1V05_ S0_SMC_L S

=PP1V05_ S0_MCP_F SB

=PP1V05 _S0_MCP_ SATA_DVD D0

=PP5V_ S3_VTT CLAMP

=PP5V_ S0_FAN _LT

=PP5V_ S0_KBD LED =PP5V_ S0GPU_ P1V1P1V 8_GPU =PP5V_ S0_LPC PLUS

=PPVIN _S0_CP UVTTS0

=PPVIN _S5_CP U_IMVP_ ISNS_R

=PP1V8_ S0_REG

=PP3V3_ S0_TPAD

=PP1V05 _S0_FET

PP1V8R1V 5_S0_FET

MIN_LINE_WI DTH=0.6mm MIN_NECK_WI DTH=0.2mm VOLTAGE=1.5 V MAKE_BASE=T RUE

=PP1V5_S 3_MEMRES ET

MIN_NECK_WI DTH=0.1 mm VOLTAGE=1.5 V MAKE_BASE=T RUE

PP1V8R1V 5_S3

MIN_LINE_WI DTH=0.8 mm

=PP3V3 _S0_MCP _DAC_U F

=PP3V3 _S0_MCP _VPLL_ UF

=PP3V3 _S0_MCP _PLL_U F

=PP3V3 R1V5_S0 _MCP_H DA

=PPVCO RE_S0_ CPU

=PP5V_ S3_TPA D

=PPVIN _S0_P1 V05S5

=PPDCI N_S5_C HGR

=PP3V4 2_G3H_ LIDSWIT CH

=PP3V4 2_G3H_ BATT

=PP3V4 2_G3H_ BMON_IS NS

=PP3V3 _S3_SM S

=PPBUS _S0_LCD BKLT

MAKE_BAS E=TRUE

VOLTAGE= 12.6V

MIN_NECK _WIDTH=0 .25 mm

PPBUS_ G3H

MIN_LINE _WIDTH=0 .4 mm

=PP3V3 _S3_EXC ARD

=PP3V3 _S0_LP CPLUS

=PP3V3 _S0_GP U1V8ISN S

=PP3V3 _S0_MCP DDRISN S

=PP3V3 _S0_SM C

MIN_NECK _WIDTH=0 .20MM

MAKE_BAS E=TRUE

PP3V3_ S0

MIN_LINE _WIDTH=0 .30MM

VOLTAGE= 3.3V

=PP3V3 _S3_P1 V8S0

=PP3V3 _S3_SMB US_SMC _MGMT

=PP3V3 _S3_MC P_GPIO

=PP3V3 _S3_WL AN

=PP1V8R1 V5_S0_MC P_MEM

MAKE_BASE=T RUE

PPMCPDDR _ISNS

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm VOLTAGE=1.5 V

=PP1V05_ S0_MCP_S ATA_DVDD

=PP3V3 _S0_GMU X

=PP3V3 _S0_HDC PROM

=PP3V3 _S0_MCP _GPIO

=PP3V3_ S0_P1V2P 2V5

=PP3V3 _S0_VMO N

=PP3V3 _FC_CO N

MIN_LINE _WIDTH=0 .60 MM

VOLTAGE= 5V

PP5V_S 0

MAKE_BAS E=TRUE

MIN_NECK _WIDTH=0 .20 MM

=PP5V_ S0_HDD

=PP5V_ S0_ODD

=PP3V3 _S3_TP AD

=PP3V3 _S3_RE MTHMSNS

=PP3V3 _S5_DP_ PORT_P WR

=PP3V3 _S5_P3 V3ENETF ET

=PP3V3 _S5_P1 V05ENET FET

=PP3V3 _S5_MCP PWRGD

=PP3V3 _S0_P3 V3S0FET

=PP3V3 _S5_RO M

=PP3V3 _FW_LA TEVG

MIN_LINE _WIDTH=0 .50MM MIN_NECK _WIDTH=0 .20MM

MAKE_BAS E=TRUE

PP3V3_ S3

VOLTAGE= 3.3V

=PP1V05_ S0_MCP_P EX_DVDD

PP1V05_ S0_MCP_P EX_AVDD

MAKE_BASE=T RUE

=PP1V05 _S5_MCP

=PPCPUVT T_S0_REG

=PP3V3 _S0_DPC ONN

=PP3V3 _S0_DPM UX

=PPVTT_ S0_DDR_L DO

MAKE_BASE=T RUE

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.3 mm

VOLTAGE=0.7 5V

PPVTTDDR _S3

PP0V9R0 V75_S0_D DRVTT

MIN_LINE_W IDTH=2 mm MIN_NECK_W IDTH=0.2 m m VOLTAGE=0. 9V MAKE_BASE= TRUE

=PP1V05_ S0_CPU

PPCPUVTT _S0

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm VOLTAGE=1.0 5V MAKE_BASE=T RUE

=PP1V05 _S0_MCP_ PEX_AVDD 0

=PP1V05 _S0_MCP_ PEX_DVDD 1

=PP1V05 _S0_MCP_ PEX_DVDD 0

=PP1V05_ S0_VMON

=PP1V05_ S0_MCP_H DMI_VDD

=PP1V05_ S0_MCP_S ATA_DVDD

=PP1V05_ S0_MCP_P LL_UF

=PP1V05_ S0_MCP_P EX_DVDD

=PP1V05_ S0_MCP_A VDD_UF

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm VOLTAGE=1.0 5V

PP1V05_S 0_REG

MAKE_BASE=T RUE

=PPMCPD DR_ISNS

=PP1V5_S 0_MEM_B

=PP1V5_S 0_MEM_A

=PPMCPDD R_ISNS_R

=PP1V5_S 0_CPU

=PP1V5_S 0_EXCARD

=PP1V5_S 0_VMON

=PP3V3 _GPU_LV DS_DDC

=PP3V3 _GPU_P WRCTL

MIN_LINE _WIDTH=0 .30MM

MAKE_BAS E=TRUE

PP3V3_ S0GPU

MIN_NECK _WIDTH=0 .20MM VOLTAGE= 3.3V

PP1V1_S0 GPU_REG

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.6 mm

MAKE_BASE=T RUE

VOLTAGE=1.1 V

=PP1V8 _GPUIFP X_REG

=PP3V3 _S0_FE T

=PP3V3 _S0_SMB US_MCP _0

=PPVBA T_G3H_ P3V42G3 H

=PPVIN _S3_DDR REG

=PPVIN _S0_P5 VRTS0_M CPCORE

=PPVIN _GPU_GP UVCORE

=PPBUS _S5_FWP WRSW

MIN_NECK _WIDTH=0 .25 mm VOLTAGE= 12.6V MAKE_BAS E=TRUE

MIN_LINE _WIDTH=0 .6 mm

PPDCIN _G3H

MAKE_BAS E=TRUE

VOLTAGE= 3.42V

PP3V42 _G3H

MIN_NECK _WIDTH=0 .2 mm

MIN_LINE _WIDTH=0 .3 mm

MIN_LINE _WIDTH=0 .6 mm MIN_NECK _WIDTH=0 .2 mm VOLTAGE= 3.3V MAKE_BAS E=TRUE

PP3V3_ S5

=PP3V3 _S5_MCP _GPIO

=PP3V3 _S5_MCP

=PP3V3 _S5_P1V 05FET

=PP3V3 _S5_PW RCTL

=PP3V3 _GPU_P 3V3GPUF ET

=PP3V3 _S5_LC D

62 13

24

12

46

24

59

79

74

52

76

22

46

21

11

38

13

24

22

58

76

73

74

24

43

24

76

75

25

78

68

64

44

14

49

24

12

46

95

24

19

53

24

10

25

24

12

43

95

20

24

38

69

36

67

20

7

8

32

45

8

61

7

69

63

45

48

62

6

47

49

22

7

83

34

21

69

64

46

61

50

46

60

32

80

39

54

29

28

7

68

49

82

48

45

7

83

77

7

77

75

82

70

72

7

9

72

67

73

71

47

28

29

18

69

29

28

34

22

69

78

31

7

31

7

78

42

44

45

69

86

69

34

33

18

24

7

62

7

75

6

18

7

71

47

46

82

37

36

7

65

64

24

63

26

9

65

66

40

7

27

67

62

40

64

41

43

62

49

69

23

63

37

30

48

63

60

17

27

43

9

20

69

7

51

82

44

66

46

67

51

69

7

30

7

25

24

21

11

51

67

61

41

60

46

52

85

7

32

44

47

43

7

67

45

21

31

16

7

8

83

25

18

86

68

32

7

39

50

48

81

34

26

69

44

38

7

8

24

67

66

81

80

64

7

6

7

17

68

18

8

24

8

24

7

47

29

28

47

11

32

68

80

68

7

67

69

45

60

64

65

78

37

7

18

22

69

68

69

79

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Frame Holes

Thermal Module Holes

MCP79 PCIe PRSNT# Straps

Digital Ground

If fou nd to be nece ssary, will move t o page1 4.csa

Exist in MRB but no t Inte l desi gns. Here fo r CYA.

Extra FSB Pull-ups

TM Hol e

CPU si gnals

TM Hol e TM Hol e

GPU si gnals

ETHERNET ALIASES

GMUX ALIASES

AUDIO ALIASES

Bottom Left GPU

Top GP U Righ t

Left C PU

TM Hol e

Right CPU

These ne ed work. Add ot her PRSN T# strap s if nee ded. .

Bosses for VRAM HS

STDOFF -4.5OD .98H-1 .1-3.4 8-TH

3R2P5

5% 1/16W

402

MF-LF

47K

5%

1/16W

402

0

MF-LF

17

10K

5% 1/16W MF-LF

402

SM

1%

MF-LF

402

10

1/16W

10

1/16W MF-LF

1%

402

STDOFF -4.5OD .98H-1 .1-3.4 8-TH

3R2P5

TH

SL-3.1X2. 7-6CIR-NSP

3R2P5

STDOFF -4.5OD .98H-1 .1-3.4 8-TH

402

0

5% 1/16W MF-LF

17

83

NO STU FF

5%

1/16W

0

402

MF-LF

STDOFF -4.5OD .98H-1 .1-3.4 8-TH

10 14 87

10 13 14 87

10 14 87

10 14 62 87

62

1/16W

402

5%

MF-LF

NO STU FF

220

MF-LF

402

5%

1/16W

NO STU FF

200

MF-LF

1/16W

5%

402

1%

150

MF-LF

1/16W

402

NO STU FF

1%

402

1/16W MF-LF

150

NO STU FF

STDOFF -4.0OD 3.0H-T H

VENICE

STDOFF -4.0OD 3.0H-T H

VENICE

STDOFF -4.0OD 3.0H-T H

1.4DIA -SHORT -EMI-M LB-M97 -M98

SM

4.0OD1 .65H-M 1.6X0. 35

0

5%

1/16W

402

MF-LF

SM

1.4DIA -SHORT -EMI-M LB-M97 -M98

SM

1.4DIA -SHORT -EMI-M LB-M97 -M98

SM

2.0DIA -TALL- EMI-ML B-M97- M98

SM

2.0DIA -TALL- EMI-ML B-M97- M98

SM

2.0DIA -TALL- EMI-ML B-M97- M98

SM

2.0DIA -TALL- EMI-ML B-M97- M98

SM

3R2P5

Signal Aliases

9 96

A.0.0

051-7546

SYNC_MA STER=( MASTER)

SYNC_DA TE=(MA STER)

MIN_NECK _WIDTH=0 .09MM

MIN_LINE _WIDTH=0 .6MM

VOLTAGE= 0V

GND

GND_CH ASSIS_ CLUTCH

GND_BA TT_CHG ND

GND_CH ASSIS_ USB

MAKE_BASE=T RUE

TP_LVDS _IG_B_CL KN

=PP1V0 5_S0_M CP_SATA _AVDD1

LVDS_B _DATA_ N<3>

MAKE_BAS E=TRUE

JTAG_G MUX_TD O

IG_LCD _PWR_E N

IG_BKL T_EN

MAKE_BAS E=TRUE

LVDS_I G_PANE L_PWR

LVDS_IG _BKL_PWM

MAKE_BASE=T RUE

NC_LVD S_IG_A _DATAP< 3>

MAKE_BASE=T RUE

NC_LVD S_B_DA TAP<3>

FSB_BR EQ0_L

CPU_IN TR

FC_PRS NT_L

MAKE_BASE=T RUE

PCIE_F C_R2D_ C_N

MAKE_BASE=T RUE

=MCP_HDM I_TXD_N< 0..2>

MAKE_BAS E=TRUE

PCIE_F W_PRSN T_L

LVDS_A _DATA_ P<3>

MAKE_BAS E=TRUE

NC_RTL 8211_R EGOUT

=RTL82 11_REG OUT

=RTL82 11_ENS WREG

=PP1V0 5_S0_M CP_SATA _DVDD1

PCIE_F C_D2R_ N

MAKE_BASE=T RUE

TP_PE4 _PRSNT _L

MCP_MI I_PD

MAKE_BAS E=TRUE

=MCP_M II_COL

GND_CH ASSIS_ FAN

TP_USB _EXTCP

MAKE_BAS E=TRUE

USB_EX TC_P

=DVI_H PD_GMU X_INT

USB_MI NI_N

NO_TEST=TRU E

MAKE_BASE=T RUE

NC_LVDS_ A_DATAP< 3>

MAKE_BASE=T RUE

TP_LVDS _IG_B_CL KP

GPU_RESE T_L

MAKE_BASE=T RUE

DP_IG_DD C_DATA

=MCP_HDM I_DDC_CL K

DP_IG_ML _N<3>

MAKE_BASE=T RUE

=MCP_HDM I_TXC_N

DP_IG_ML _P<2..0>

MAKE_BASE=T RUE

=MCP_HDM I_TXD_P< 0..2>

=MCP_HDM I_TXC_P

MAKE_BASE= TRUE

PEG_R2D _C_P<0.. 15>

MAKE_BAS E=TRUE

PCIE_R ESET_L

VR_PWR GD_CLK EN_LTP_IMV P6_CLK EN_L

MAKE_BAS E=TRUE

MAKE_BASE=T RUE

CPU_VID< 0..6>

=MCP_BSE L<0..2>

=PEG_D2 R_P<0..1 5>

IMVP6_VI D<0..6>

CPU_BSEL <0..2>

MAKE_BASE=T RUE

MAKE_BAS E=TRUE

PM_SLP _RMGT_ L

LVDS_B_D ATA_N<3>

LVDS_A_D ATA_P<3>

LVDS_IG _B_CLK_N

LVDS_B _DATA_ P<3>

MAKE_BASE=T RUE

NC_LVD S_IG_A _DATAN< 3>

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_LVDS_ B_DATAN< 3>

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_LVDS_ B_DATAP< 3>

PCIE_C LK100M _FC_N

MAKE_BASE=T RUE

PCIE_F C_R2D_ C_P

=MCP_M II_CRS

=MCP_M II_RXE R

USB_EX TC_N

MAKE_BAS E=TRUE

TP_USB _MININ

MAKE_BAS E=TRUE

TP_USB _MINIP

USB_MI NI_P

USB_EX TD_N

USB_EX TD_P

VOLTAGE= 5V

PP5V_S 3_AUDI O_AMP

MIN_NECK _WIDTH=0 .25 mm

MIN_LINE _WIDTH=0 .5 mm

MAKE_BASE=T RUE

NC_LVD S_B_DA TAN<3>

MAKE_BASE=T RUE

NC_LVD S_A_DA TAP<3>

MAKE_BASE =TRUE

AUD_IP HS_SWI TCH_EN

PP5V_S 3_AUDI O

VOLTAGE= 5V

MIN_NECK _WIDTH=0 .25 mm

MIN_LINE _WIDTH=0 .5 mm

TP_USB _EXTDP

MAKE_BAS E=TRUE

NC_LVD S_IG_B _DATAP< 3>

MAKE_BASE=T RUE

TP_SPI_C S1_R_L_U SE_MLB

=DDRVTT_ ENMEM_VTT_ EN

MAKE_BASE=T RUE

=SPI_CS1 _R_L_USE _MLB

=PEG_D2 R_N<0..1 5>

MAKE_BASE= TRUE

PEG_D2R _N<0..15 >

LVDS_I G_B_DA TA_P<3>

LVDS_I G_A_DA TA_P<3>

LVDS_I G_A_DA TA_N<3>

LVDS_A _DATA_ N<3>

LVDS_I G_B_DA TA_N<3>

LVDS_A_D ATA_N<3>

MAKE_BASE=T RUE

TP_LVDS _IG_BKL_ PWM

TP_USB _EXTDN

MAKE_BAS E=TRUE

HDA_BI T_CLK

FC_RES ET_L

MAKE_BASE=T RUE

NO_TEST=TRU E

NC_LVDS_ A_DATAN< 3>

=P3V3E NET_EN

=PP3V3 _ENET_ PHY_VDD REG

PCIE_F C_D2R_ P

MAKE_BASE=T RUE

CPU_DP RSTP_L

GND_CH ASSIS_ BATTCON N

=PP1V0 5_S0_M CP_FSB

TP_PP3 V3_ENE T_PHY_V DDREG

MAKE_BAS E=TRUE

PEG_PR SNT_L

=P1V05 ENET_E N

MAKE_BAS E=TRUE

TP_USB _EXTCN

MAKE_BASE=T RUE

DP_IG_ML _N<2..0>

LVDS_B_D ATA_P<3>

NC_LVD S_IG_B _DATAN< 3>

MAKE_BASE=T RUE

NC_LVD S_A_DA TAN<3>

MAKE_BASE=T RUE

CPU_NM I

GMUX_I NT

MAKE_BAS E=TRUE

PCIE_C LK100M _FC_P

MAKE_BASE=T RUE

TP_PCI E_CLK1 00M_PE4 N

MCP_SP KR

LVDS_IG _B_CLK_P

FC_CLK REQ_L

MAKE_BASE=T RUE

MEM_B_ A<15>

HDA_BI TCLK

MAKE_BAS E=TRUE

=PP5V_ S3_AUD IO_PWR

MAKE_BAS E=TRUE

TP_MEM _A_A<1 5>

GMUX_J TAG_TD O

MAKE_BAS E=TRUE

LVDS_I G_BKL_ ON

GMUX_J TAG_TM S

ALL_EG_P GOOD

DP_IG_ML _P<3>

MAKE_BASE=T RUE

MAKE_BAS E=TRUE

JTAG_G MUX_TD I

EG_RESET _L

MAKE_BASE=T RUE

MEM_A_ A<15>

SMC_MC P_SAFE _MODE

MAKE_BAS E=TRUE

TP_MEM _B_A<1 5>

EG_CLKRE Q_OUT_L

CPU_PE CI_MCP

TP_CPU _PECI_ MCP

MAKE_BAS E=TRUE

=PEG_R2 D_C_P<0. .15>

TP_PCI E_CLK1 00M_PE4 P

TP_PCI E_PE4_ R2D_CP

TP_PCI E_PE4_ R2D_CN

GMUX_J TAG_TD I

MAKE_BASE=T RUE

LCD_BKL T_EN

LVDS_BKL _ON

TP_MCP _GPIO_ 17

MAKE_BAS E=TRUE

AUD_IP _PERIP HERAL_D ET

TP_PCI E_PE4_ D2RN

TP_PCI E_PE4_ D2RP

TP_PE4 _CLKRE Q_L

=PEG_R2 D_C_N<0. .15>

MAKE_BASE= TRUE

PEG_R2D _C_N<0.. 15>

PEG_D2R _P<0..15 >

MAKE_BASE= TRUE

=PP1V8_G PU_FB_VR EF_B

GND_CH ASSIS_ SATA

=PP1V8_G PU_FB_VR EF_A

MAKE_BASE=T RUE

GPU_FB_A _VREF_DI V

MAKE_BASE=T RUE

GPU_FB_B _VREF_DI V

MAKE_BASE=T RUE

TP_LVDS_ MUX_SEL_ EG

LVDS_MUX _SEL_EG

=PP1V8_G PU_FB_VD DQ

DP_IG_DD C_CLK

MAKE_BASE=T RUE

=MCP_HDM I_DDC_DA TA

=MCP_HDM I_HPD

PM_ALL_G PU_PGOOD

MAKE_BASE=T RUE

DP_IG_HP D

MAKE_BASE=T RUE

MAKE_BAS E=TRUE

JTAG_G MUX_TM S

FSB_CP URST_L

GND_CH ASSIS_ LVDS

ZT0980

ZT0940

1

R0930

1

2

R0925

R0902

1 2

XW0900

12

XW0901

12

R0900

R0901

ZT0981

ZT0982

ZT0983

ZT0984

ZT0985

ZT0986

ZT0987

ZT0945

1

ZT0950

ZT0965

1

ZT0960

1

ZT0990

1

ZT0989

1

ZT0988

1

ZT0991

1

R0926

R0927

ZT0930

R0960

1

2

R0950

1

2

R0970

1

2

R0980

1

2

R0990

1

2

ZT0931

1

ZT0932

1

ZT0933

1

ZT0934

1

ZT0935

1

SH0910

1

ZT0951

1

ZT0952

1

ZT0953

1

R0903

SH0912

1

SH0911

1

SH0913

1

SH0902

1

SH0900

1

SH0903

1

SH0901

1

ZT0915

1

24 22

61

83

95

90

80

89

26

87 87

87

89

95

90

59

56

69

44

89

90

95

14

89

95

89

83

89

80

83

60

20

9

6

83

18

9

32

18

9

33

20

32

17

18

20

18

20

9

70

76

18

80 18

18

70

17

62

11

14

17

62

10

21

9

18

9

32

18

20

57

9

19

54

64 26

21

17 70

18

9

18

9

21

32

9

34

33

32

8

34

80

9

83

32

17

21

18

32 29

54

8

17

18

19

83

80

6

83

28

42

14

17

19

83 85

17

70

74

73

83

76

18

68

6

BI

IN

OUT

IN

BI

OUT

BI

OUT

IN

OUT

IN

OUT

BI

LOCK*

INIT*

A20M*

A6*

A3*

A4*

A14*

A16*

REQ0*

REQ1*

REQ2*

REQ3*

REQ4*

BCLK1

BCLK0

THERMTRI P*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20*

A21*

A22*

A23*

A24*

A26*

A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5

RSVD6

RSVD7

RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GRO UP1

ICH

RESERVED

ADDR GRO UP0

TEST7

TEST6

DSTBP1*

DINV1*

D31*

D30*

D25*

D11*

D12*

D13*

D14*

DSTBP0*

DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32*

D1*

D2*

D5*

D16*

D20*

D21*

D22*

D23*

D24*

D26*

D27*

D28*

D29*

DSTBN1*

GTLREF

TEST3

TEST4

TEST5

BSEL0

BSEL1

BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2*

DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3*

DSTBP3*

DINV3*

COMP0

COMP1

COMP2

COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

LAYOUT NOTE:

MAKE T RACE L ENGTH S HORTER THAN 0.5".

COMP0, 2 CONN ECT WIT H ZO=2 7.4OHM ,

MAKE T RACE L ENGTH S HORTER THAN 0.5".

COMP1, 3 CONN ECT WIT H ZO=5 5OHM,

PM_THR MTRIP# SHOULD CONNE CT TO I CH AND GMCH W ITHOUT T (NO STUB)

0.1" A WAY

PLACE TESTPO INT ON FSB_IE RR_L W ITH A G ND

0.5" M AX LEN GTH FOR CPU_G TLREF

REFERE NCED T O GND

PLACE C1000 CLOSE T O CPU_ TEST4 PIN. M AKE SU RE CPU_ TEST4 IS

402

MF-LF

54.9

1/16W

1%

MF-LF 402

1/16W

5%

68

402

1K

MF-LF

1%

1/16W

402

1/16W

2.0K

MF-LF

1%

402

54.9

1/16W MF-LF

1%

402

1%

MF-LF

1/16W

27.4

402

54.9

1/16W MF-LF

1%

402

27.4

1/16W MF-LF

1%

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

9

14 62 87

14 87

62

13 14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

9

87

9

87

9

87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

9

14 87

7

14 87

7

14 87

7

14 87

13 87

6

10 87

13 26

14 43 62 87

48 95

14 43 87

14 87

9

13 14 87

14 87

6

10 13 87

6

10 13 87

6

10 13 87

6

10 13 87

48 95

14 87

9

14 87

9

14 87

402

NOSTUF F

5%

MF-LF

1/16W

0

402

NOSTUF F

1K

MF-LF

5% 1/16W

402

54.9

MF-LF

1%

1/16W

402

54.9

1/16W MF-LF

1%

402

1%

MF-LF

1/16W

54.9

402

1%

MF-LF

1/16W

54.9

14 87

402

1%

MF-LF

1/16W

649

402

MF-LF

NOSTUF F

1K

5%

1/16W

402

16V

10%

0.1uF

NOSTUF F

X5R

402

PLACEM ENT_NO TE=Plac e R102 4 near ITP c onnecto r (if presen t)

54.9

1/16W MF-LF

1%

OMIT

PENRYN

FCBGA

OMIT

PENRYN

FCBGA

CPU FSB

10

A.0.0

051-7546

96

SYNC_MA STER=M 87_MLB

SYNC_DA TE=10/ 17/2007

XDP_TC K

XDP_TD O

XDP_TM S

XDP_TD I

XDP_TR ST_L

=PP1V0 5_S0_C PU

TP_CPU _RSVD8

TP_CPU _RSVD7

TP_CPU _RSVD6

TP_CPU _RSVD5

FSB_A_ L<5>

FSB_A_ L<15>

FSB_A_ L<10>

FSB_AD S_L

CPU_IG NNE_L

CPU_TH ERMD_N

FSB_A_ L<11>

FSB_A_ L<7> FSB_A_ L<8> FSB_A_ L<9>

FSB_A_ L<27>

FSB_A_ L<26>

FSB_A_ L<24>

FSB_A_ L<23>

FSB_A_ L<22>

FSB_A_ L<21>

FSB_A_ L<20>

FSB_BP RI_L

FSB_A_ L<12> FSB_A_ L<13>

FSB_AD STB_L< 0>

FSB_A_ L<17>

FSB_A_ L<19>

FSB_A_ L<28> FSB_A_ L<29> FSB_A_ L<30> FSB_A_ L<31> FSB_A_ L<32> FSB_A_ L<33> FSB_A_ L<34> FSB_A_ L<35> FSB_AD STB_L< 1>

CPU_FE RR_L

CPU_ST PCLK_L CPU_IN TR CPU_NM I CPU_SM I_L

TP_CPU _RSVD0 TP_CPU _RSVD1 TP_CPU _RSVD2 TP_CPU _RSVD3 TP_CPU _RSVD4

FSB_BN R_L

FSB_DE FER_L FSB_DR DY_L FSB_DB SY_L

FSB_BR EQ0_L

CPU_IE RR_L

FSB_CP URST_L FSB_RS _L<0> FSB_RS _L<1> FSB_RS _L<2> FSB_TR DY_L

FSB_HI T_L FSB_HI TM_L

XDP_BP M_L<0> XDP_BP M_L<1> XDP_BP M_L<2> XDP_BP M_L<3> XDP_BP M_L<4> XDP_BP M_L<5> XDP_TC K XDP_TD I XDP_TD O XDP_TM S XDP_TR ST_L XDP_DB RESET_ L

CPU_PR OCHOT_ L CPU_TH ERMD_P

PM_THR MTRIP_ L

FSB_CL K_CPU_ P FSB_CL K_CPU_ N

FSB_RE Q_L<4>

FSB_RE Q_L<3>

FSB_RE Q_L<2>

FSB_RE Q_L<0>

FSB_A_ L<4>

FSB_A_ L<3>

FSB_A_ L<6>

CPU_A2 0M_L

CPU_IN IT_L

FSB_LO CK_L

FSB_RE Q_L<1>

CPU_TE ST1

FSB_D_ L<10>

FSB_D_ L<15> FSB_DS TB_L_N <0>

FSB_D_ L<3> FSB_D_ L<4>

FSB_D_ L<17>

CPU_PS I_L

FSB_CP USLP_L

CPU_PW RGD

FSB_DP WR_L

CPU_DP SLP_L

CPU_DP RSTP_L

CPU_CO MP<3>

CPU_CO MP<2>

CPU_CO MP<1>

CPU_CO MP<0>

FSB_DI NV_L<3 >

FSB_DS TB_L_P <3>

FSB_DS TB_L_N <3>

FSB_D_ L<63>

FSB_D_ L<62>

FSB_D_ L<61>

FSB_D_ L<60>

FSB_D_ L<59>

FSB_D_ L<58>

FSB_D_ L<57>

FSB_D_ L<56>

FSB_D_ L<55>

FSB_D_ L<54>

FSB_D_ L<53>

FSB_D_ L<52>

FSB_D_ L<51>

FSB_D_ L<50>

FSB_D_ L<49>

FSB_D_ L<48>

FSB_DI NV_L<2 >

FSB_DS TB_L_P <2>

FSB_DS TB_L_N <2>

FSB_D_ L<47>

FSB_D_ L<46>

FSB_D_ L<45>

FSB_D_ L<44>

FSB_D_ L<43>

FSB_D_ L<42>

FSB_D_ L<41>

FSB_D_ L<40>

FSB_D_ L<39>

FSB_D_ L<38>

FSB_D_ L<37>

FSB_D_ L<36>

FSB_D_ L<35>

FSB_D_ L<34>

FSB_D_ L<33>

CPU_BS EL<2>

CPU_BS EL<1>

CPU_BS EL<0>

TP_CPU _TEST5

CPU_TE ST4

TP_CPU _TEST3

CPU_GT LREF

FSB_DS TB_L_N <1>

FSB_D_ L<29>

FSB_D_ L<28>

FSB_D_ L<27>

FSB_D_ L<26>

FSB_D_ L<24>

FSB_D_ L<23>

FSB_D_ L<22>

FSB_D_ L<21>

FSB_D_ L<20>

FSB_D_ L<16>

FSB_D_ L<5>

FSB_D_ L<2>

FSB_D_ L<1>

FSB_D_ L<32>

FSB_D_ L<0>

FSB_D_ L<18> FSB_D_ L<19>

FSB_D_ L<6> FSB_D_ L<7> FSB_D_ L<8> FSB_D_ L<9>

FSB_DI NV_L<0 >

FSB_DS TB_L_P <0>

FSB_D_ L<14>

FSB_D_ L<13>

FSB_D_ L<12>

FSB_D_ L<11>

FSB_D_ L<25>

FSB_D_ L<30> FSB_D_ L<31>

FSB_DI NV_L<1 >

FSB_DS TB_L_P <1>

CPU_TE ST2

TP_CPU _TEST7

TP_CPU _TEST6

=PP1V0 5_S0_C PU

FSB_A_ L<25>

FSB_A_ L<18>

FSB_A_ L<16>

FSB_A_ L<14>

R1002

1

2

R1004

1

2

R1005

1

2

R1006

1

2

R1019

R1018

R1017

R1016

R1030

R1007

1

2

R1003

1

2

R1020

R1021

R1022

R1023

R1012

1

2

C1000

1

2

R1024

U1000

N3

P5

P2

L2

P4

P1

R1

Y2

U5

R3

W6

A6

U4

Y5

U1

R4

T5

T3

W2

W5

Y4

J4

U2

V4

W3

AA4

AB2

AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22

A21

E2

AD4

AD3

AD1

AC4

G5

F1

C20

E1

H5

F21

A5

G6

E4

D20

C4

B3

C6

B4

H4

AC2

AC1

D21

K3

H2

K2

J3

L1

C1

F3

F4

G3

M4

N5

T2

V3

B2

F6

D2

D22

D3

A3

D5

AC5

AA6

AB3

A24

B25

C7

AB5

G2

AB6

U1000

B22

B23

C21

R26

U26

AA1

Y1

E22

F24

J24

J23

H22

F26

K22

H23

N22

K25

P26

R23

E26

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

G22

T25

N25

Y22

AB24

V24

V26

V23

T22

U25

U23

F23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

AE24

AD24

G25

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

E25

AC22

AD23

AF22

AC23

E23

K24

G24

H25

N24

U22

AC20

E5

B5

D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6

D7

C23

D25

C24

AF26

AF1

A26

C3

62

13

12

87

11

13

87

13

10

8

87

8

6

87

87 27

6

OUT

VCC

VCCP

VCCA

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

17.0 A (Auto -Halt/S top-Gr ant Su perLFM )

30.4 A (LFM)

2500 m A (aft er VCC stable )

4500 m A (bef ore VCC stabl e)

16.0 A (Deep Sleep SuperL FM)

16.8 A (Slee p Super LFM)

41.0 A (HFM)

(CPU C ORE PO WER)

130 mA

(CPU I O POWE R 1.05V )

(CPU I NTERNA L PLL P OWER 1 .5V)

Low Voltage:

23.0 A (Desi gn Targ et)

18.7 A (LFM) TBD A (Supe rLFM)

TBD A (Slee p Super LFM)

TBD A (Deep er Slee p)

TBD A (Slee p HFM)

TBD A (Auto -Halt/S top-Gr ant HF M)

TBD A (HFM) TBD A (LFM)

Curren t numb ers fro m Mero m for Santa Rosa EM TS, do c #222 21.

TBD A (Auto -Halt/S top-Gr ant LF M)

TBD A (Slee p LFM)

25.5 A (Supe rLFM)

27.4 A (Slee p HFM)

25.0 A (Deep Sleep HFM)

11.5 A (Deep er Slee p)

9.4 A (Enha nced De eper S leep)

TBD A (Slee p HFM)

21.0 A (HFM)

TBD A (Deep Sleep HFM)

TBD A (Auto -Halt/S top-Gr ant Su perLFM )

TBD A (Auto -Halt/S top-Gr ant HF M)

TBD A (Enha nced De eper S leep)

TBD A (Deep er Slee p)

TBD A (Deep Sleep LFM)

TBD A (Deep Sleep HFM)

TBD A (Deep Sleep SuperL FM)

27.4 A (Auto -Halt/S top-Gr ant HF M)

44.0 A (Desi gn Targ et)

Standard Voltage:

Ultra Low Voltage:

17.0 A (Desi gn Targ et)

TBD A (Enha nced De eper S leep)

9

87

9

87

9

87

9

87

9

87

9

87

PLACEMEN T_NOTE=P lace wit hin 1 in ch of CP U, no st ub.

MF-LF 402

100

1% 1/16W

9

87

62 87

MF-LF 402

PLACEMEN T_NOTE=P lace wit hin 1 in ch of CP U, no st ub.

1/16W

1%

100

OMIT

PENRYN

FCBGA

OMIT

PENRYN

FCBGA

SYNC_DA TE=10/ 17/2007

SYNC_MA STER=M 87_MLB

CPU Power & Ground

051-7546

A.0.0

11 9 6

=PPVCO RE_S0_ CPU

CPU_VC CSENSE _N

CPU_VC CSENSE _P

CPU_VI D<6>

CPU_VI D<5>

CPU_VI D<4>

CPU_VI D<3>

CPU_VI D<2>

CPU_VI D<1>

CPU_VI D<0>

=PP1V5 _S0_CP U

=PP1V0 5_S0_C PU

=PPVCO RE_S0_ CPU

R1101

1

2

R1100

1

2

U1000

A7

A9

B9

B10

B12

B14

B15

B17

B18

B20

C9

C10

A10

C12

C13

C15

C17

C18

D9

D10

D12

D14

D15

A12

D17

D18

E7

E9

E10

E12

E13

E15

E17

E18

A13

E20

F7

F9

F10

F12

F14

F15

F17

F18

F20

A15

AA7

AA9

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AB9

A17

AC10

AB10

AB12

AB14

AB15

AB17

AB18

AB20

AB7

AC7

A18

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

A20

AD14

AD15

AD17

AD18

AE9

AE10

AE12

AE13

AE15

AE17

B7

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

B26

C26

G21

V6

R21

R6

T21

T6

V21

W21

J6

K6

M6

J21

K21

M21

N21

N6

AF7

AD6

AF5

AE5

AF4

AE3

AF3

AE2

AE7

U1000

A4

A8

B11

W1

W4

W23

W26

Y3

Y6

Y21

Y24

AA2

AA5

B13

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

B16

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

B19

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

B21

AD16

AD19

AD22

AD25

AE1

AE4

AE8

AE11

AE14

AE16

B24

AE19

AE23

AE26

A2

AF6

AF8

AF11

AF13

AF16

AF19

C5

AF21

A25

AF25

B1

C8

C11

C14

A11

C16

C19

C2

C22

C25

D1

D4

D8

D11

D13

A14

D16

D19

D23

D26

E3

E6

E8

E11

E14

E16

A16

E19

E21

E24

F5

F8

F11

F13

F16

F19

F2

A19

F22

F25

G4

G1

G23

G26

H3

H6

H21

H24

A23

J2

J5

J22

J25

K1

K4

K23

K26

L3

L6

AF2

L21

L24

M2

M5

M22

M25

N1

N4

N23

N26

B6

P3

P6

P21

P24

R2

R5

R22

R25

T1

T4

B8

T23

T26

U3

U6

U21

U24

V2

V5

V22

V25

62 13

46

12

46

12

10

12

11

12

8

11

8

6

8

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

1x 10uF, 1x 0.01uF

CPU VCORE HF AND BULK DECOUPLING

4x 330uF, 20x 22uF 0805

1x 470uF, 6x 0.1uF 0402

VCCP (CPU I/O) DECOUPLING

WF: Co nsider sharin g bulk cap w ith NB Vtt?

VCCA (CPU AVdd) DECOUPLING

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

2.5V

D2T

20%

470UF

POLY

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

22UF

X5R-CERM 603

6.3V

20%

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

6.3V

20%

22UF

603

X5R-CERM

CRITIC AL

20%

X5R-CERM 603

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM

22UF

603

20%

6.3V

CRITIC AL

X5R-CERM

22UF

6.3V

20%

603

CRITIC AL

22UF

X5R-CERM 603

20%

6.3V

20%

0.1UF

CERM 402

10V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

CRITIC AL

22UF

X5R-CERM 603

20%

6.3V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

20%

CERM 402

0.1UF

10V

20%

CERM 402

0.1UF

10V

20%

0.1UF

CERM 402

10V

20%

CERM 402

0.1UF

10V

20%

CERM 402

0.1UF

10V

CRITIC AL

X5R-CERM 603

20%

22UF

6.3V

PLACEMEN T_NOTE=P lace nea r CPU pi n B26.

CERM 402

16V

10%

0.01UF

X5R

6.3V

20%

10uF

603

20%

D2T-SM2

POLY-TANT

2.0V

330UF

CRITIC AL

PLACEMEN T_NOTE=P lace in CPU cent er cavit y.

CRITIC AL

330UF

20%

POLY-TANT

D2T-SM2

PLACEMEN T_NOTE=P lace in CPU cent er cavit y.

2.0V

20%

POLY-TANT

CRITIC AL

330UF

2.0V

PLACEMEN T_NOTE=P lace in CPU cent er cavit y.

D2T-SM2

PLACEMEN T_NOTE=P lace in CPU cent er cavit y.

20%

D2T-SM2

POLY-TANT

CRITIC AL

330UF

2.0V

CPU Decoupling & VID

SYNC_MA STER=M 87_MLB

9612

A.0.0

SYNC_DA TE=10/ 17/2007

051-7546

=PP1V5 _S0_CP U

=PPVCO RE_S0_ CPU

=PP1V0 5_S0_C PU

C1208C1207

C1219C1218

C1206C1204

C1216C1214

C1203C1202C1201

C1213C1212C1211

C1200

1

2

C1210

C1236

1

2

C1205 C1209

C1215 C1217

C1237

1

2

C1238

1

2

C1239

1

2

C1240

1

2

C1241

1

2

C1281

1

2

C1280

1

2

C1250

1

2 3

C1251

1

2 3

C1252

1

2 3

C1253

1

2 3

C1235

1

2 3

62 13 11

46

10

11

8

6

IN

BI

OUT

IN

BI

IN

OUT

BI

OUT

IN

OUT

NC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

TCK0

OBSDAT A_A3

OBSDAT A_A1

OBSFN_ C0

OBSDAT A_C0 OBSDAT A_C1

OBSDAT A_C3

Mini-XDP Connector

VCC_OB S_CD

DBR#/H OOK7

Please avoid any ob struct ions on eve n-numb ered si de of J1300

NOTE: This is not the standard XDP pinout.

VCC_OB S_AB

TDO

TDI

RESET# /HOOK6

OBSFN_ D0

SCL

SDA

TRSTn

HOOK3

HOOK2

HOOK1

TMS

OBSDAT A_D0

TCK1

OBSDAT A_B2

PWRGD/ HOOK0

OBSFN_ D1

OBSDAT A_B3

XDP_PR ESENT#

NOTE: XDP_DB RESET_L must be pul led-up to 3.3 V.

OBSFN_ B0

OBSDAT A_C2

OBSFN_ C1

Direction of XDP module

998-1571

ITPCLK #/HOOK 5

ITPCLK /HOOK4

OBSDAT A_D3

OBSDAT A_D2

OBSDAT A_D1OBSDAT A_B1

OBSDAT A_B0

OBSFN_ B1

OBSDAT A_A2

OBSDAT A_A0

OBSFN_ A1

OBSFN_ A0

Use wi th 920 -0620 a dapter board to su pport C PU, MC P debu gging.

MCP79-specific pinout

10 14 87

1K

402

MF-LF

XDP

5%

1/16W

7

21 45 90

7

21 45 90

54.9

MF-LF

1/16W

1%

402

XDP

402

0.1uF

XDP

16V

10%

X5R X5R

10%

0.1uF

XDP

16V

402

10 87

6

10 87

9

10 14 87

XDP

402

MF-LF

1/16W

5%

1K

PLACEMEN T_NOTE=P lace clo se to CP U to min imize st ub.

10 87

6

21

6

21 23

6

21 23

19 90

6

21

6

14 87

6

10 87

6

10 87

6

10 87

10 26

19 23

F-ST-SM

LTH-03 0-01-G- D-NOPE GS

CRITIC AL XDP_CO NN

SYNC_DA TE=01/ 08/2008

051-7546

SYNC_MA STER=M 99_MLB

13

A.0.0

96

eXtended Debug Port(MiniXDP)

FSB_CP URST_L

CPU_PW RGD

XDP_TM S

XDP_TD O_CONN XDP_TR ST_L XDP_TD I

FSB_CL K_ITP_ N

FSB_CL K_ITP_ P

MCP_DE BUG<5>

JTAG_M CP_TMS

MCP_DE BUG<3>

MCP_DE BUG<1>

JTAG_M CP_TRS T_L

JTAG_M CP_TDO _CONN

XDP_BP M_L<5> XDP_BP M_L<4>

XDP_BP M_L<2>

XDP_BP M_L<1> XDP_BP M_L<0>

TP_XDP _OBSFN _B1

TP_XDP _OBSDA TA_B1

TP_XDP _OBSDA TA_B0

XDP_PW RGD

TP_XDP _OBSDA TA_B3

XDP_OB S20

PM_LAT RIGGER _L JTAG_M CP_TCK

SMBUS_ MCP_0_ CLK

SMBUS_ MCP_0_ DATA

XDP_TC K

MCP_DE BUG<0>

XDP_DB RESET_ L

XDP_CP URST_L

MCP_DE BUG<7>

MCP_DE BUG<6>

MCP_DE BUG<4>

JTAG_M CP_TDI

MCP_DE BUG<2>

TP_XDP _OBSDA TA_B2

=PP1V0 5_S0_C PU

=PP3V3 _S0_XD P

XDP_BP M_L<3>

TP_XDP _OBSFN _B0

R1399

1 2

R1315

1

2

C1300

1

2

C1301

1

2

R1303

1 2

J1300

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

78

9

62 12 11 10

8

87

6

IN

OUT

BI

IN

BI

OUT

IN

BI

CPU_BR0#

CPU_BNR#

BCLK_OUT _NB_N

CPU_BR1#

CPU_REQ4 #

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28#

CPU_A29#

CPU_A30#

CPU_A31#

CPU_A32#

CPU_A22#

CPU_A23#

CPU_A24#

CPU_REQ3 #

CPU_REQ2 #

CPU_DBI3 #

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR #

CPU_RS1#

BCLK_VML _COMP_GN D

CPU_COMP _VCC

CPU_TRDY #

CPU_PROC HOT#

CPU_BSEL 0

CPU_RS2#

CPU_BSEL 1

BCLK_IN_ P

BCLK_OUT _CPU_N

CPU_PWRG D

CPU_DSTB P0#

CPU_DSTB P1#

CPU_DBI1 #

CPU_DBI0 #

CPU_DSTB N1#

CPU_DSTB N0#

CPU_DBI2 #

CPU_DSTB P2#

CPU_DSTB N2#

CPU_DSTB P3#

CPU_A4#

CPU_DSTB N3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6#

CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15#

CPU_A16#

CPU_A19#

CPU_A17#

CPU_A18#

CPU_A20#

CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADST B0#

CPU_REQ0 #

CPU_LOCK #

CPU_HIT#

CPU_HITM #

CPU_FERR #

CPU_THER MTRIP#

CPU_PECI

CPU_COMP _GND

CPU_D0#

CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4#

CPU_D5#

CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17#

CPU_D18#

CPU_D16#

CPU_D19#

CPU_D20#

CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24#

CPU_D25#

CPU_D26#

CPU_D27#

CPU_D28#

CPU_D29#

CPU_D30#

CPU_D31#

CPU_D32#

CPU_D33#

CPU_D34#

CPU_D35#

CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39#

CPU_D40#

CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44#

CPU_D45#

CPU_D46#

CPU_D47#

CPU_D52#

CPU_D53#

CPU_D54#

CPU_D55#

CPU_D56#

CPU_D57#

CPU_D58#

CPU_D59#

CPU_D63#

CPU_BPRI #

CPU_DEFE R#

BCLK_OUT _CPU_P

BCLK_OUT _ITP_P

BCLK_OUT _ITP_N

BCLK_OUT _NB_P

BCLK_IN_ N

CPU_A20M #

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESE T#

CPU_SLP#

CPU_DPSL P#

CPU_STPC LK#

CPU_DPRS TP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADST B1#

CPU_IGNN E#

CPU_INIT #

BCLK_VML _COMP_VD D

CPU_RS0#

+V_DLL_D LCELL_AV DD

+V_PLL_M CLK

+V_PLL_F SB

+V_PLL_C PU

CPU_A10#

CPU_BSEL 2

CPU_DBSY #

CPU_DRDY #

CPU_REQ1 #

FSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

270 mA (A01) 206 mA

15 mA

29 mA

20 mA

(MCP_B SEL<0> )

(MCP_B SEL<1> )

(MCP_B SEL<2> )

Loop-b ack cl ock for delay match ing.

9

10 87

9

10 13 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

9

10 87

7

10 87

7

10 87

7

10 87

13 87

10 87

9

10 87

9

10 87

10 13 87

10 87

9

10 62 87

9

10 43 62 87

10 43 87

10 87

49.9

1/16W

1%

402

MF-LF

1/16W

1%

402

MF-LF

49.9

MF-LF

402

1%

1/16W

49.9

1/16W

1%

402

MF-LF

NO STU FF

1K

402

5% 1/16W MF-LF

1K

NO STU FF

402

MF-LF

5%

1/16W

1K

5%

402

MF-LF

NO STU FF

1/16W

402

MF-LF

62

5%

1/16W

402

MF-LF

54.9

1%

NO STU FF

150

1/16W

402

MF-LF

5%

OMIT

MCP79- TOPO-B

(1 OF 11 )

BGA

1/16W

402

MF-LF

62

5%

A.0.0

SYNC_DA TE=06/ 18/2008

MCP CPU Interface

051-7546

9614

SYNC_MA STER=T 18_MLB

PM_THR MTRIP_ L

FSB_D_ L<13>

MCP_BC LK_VML _COMP_G ND

FSB_DP WR_L

CPU_DP SLP_L

FSB_D_ L<38>

FSB_D_ L<43>

FSB_D_ L<45>

CPU_DP RSTP_L

CPU_ST PCLK_L

FSB_CP USLP_L

FSB_CP URST_L

CPU_PW RGD

CPU_SM I_L

CPU_NM I

CPU_IN TR

CPU_IN IT_L

CPU_IG NNE_L

CPU_A2 0M_L

FSB_CL K_MCP_ P FSB_CL K_MCP_ N

FSB_CL K_ITP_ N

FSB_CL K_ITP_ P

FSB_CL K_CPU_ N

FSB_CL K_CPU_ P

FSB_DE FER_L

FSB_BP RI_L

FSB_D_ L<63>

FSB_D_ L<62>

FSB_D_ L<61>

FSB_D_ L<60>

FSB_D_ L<59>

FSB_D_ L<58>

FSB_D_ L<57>

FSB_D_ L<56>

FSB_D_ L<55>

FSB_D_ L<54>

FSB_D_ L<53>

FSB_D_ L<52>

FSB_D_ L<51>

FSB_D_ L<50>

FSB_D_ L<49>

FSB_D_ L<48>

FSB_D_ L<47>

FSB_D_ L<46>

FSB_D_ L<44>

FSB_D_ L<42>

FSB_D_ L<41>

FSB_D_ L<40>

FSB_D_ L<39>

FSB_D_ L<37>

FSB_D_ L<36>

FSB_D_ L<35>

FSB_D_ L<34>

FSB_D_ L<33>

FSB_D_ L<32>

FSB_D_ L<31>

FSB_D_ L<30>

FSB_D_ L<29>

FSB_D_ L<28>

FSB_D_ L<27>

FSB_D_ L<26>

FSB_D_ L<25>

FSB_D_ L<24>

FSB_D_ L<23>

FSB_D_ L<22>

FSB_D_ L<21>

FSB_D_ L<20>

FSB_D_ L<19>

FSB_D_ L<18>

FSB_D_ L<17>

FSB_D_ L<16>

FSB_D_ L<15>

FSB_D_ L<12>

FSB_D_ L<11>

FSB_D_ L<10>

FSB_D_ L<9>

FSB_D_ L<8>

FSB_D_ L<6>

FSB_D_ L<5>

FSB_D_ L<4>

FSB_D_ L<3>

FSB_D_ L<2>

FSB_D_ L<1>

FSB_D_ L<0>

MCP_CP U_COMP _GND

MCP_CP U_COMP _VCC

MCP_BC LK_VML _COMP_V DD

FSB_RS _L<2>

FSB_RS _L<1>

CPU_PR OCHOT_ L

CPU_PE CI_MCP

FSB_TR DY_L

FSB_LO CK_L

FSB_HI TM_L

FSB_HI T_L

FSB_RE Q_L<4>

FSB_RE Q_L<3>

FSB_RE Q_L<2>

FSB_RE Q_L<1>

FSB_RE Q_L<0>

FSB_AD STB_L< 1>

FSB_AD STB_L< 0>

FSB_A_ L<35>

FSB_A_ L<32>

FSB_A_ L<31>

FSB_A_ L<30>

FSB_A_ L<29>

FSB_A_ L<28>

FSB_A_ L<27>

FSB_A_ L<26>

FSB_A_ L<24>

FSB_A_ L<23>

FSB_A_ L<22>

FSB_A_ L<21>

FSB_A_ L<20>

FSB_A_ L<19>

FSB_A_ L<18>

FSB_A_ L<17>

FSB_A_ L<16>

FSB_A_ L<15>

FSB_A_ L<14>

FSB_A_ L<13>

FSB_A_ L<12>

FSB_A_ L<11>

FSB_A_ L<9>

FSB_A_ L<8>

FSB_A_ L<7>

FSB_A_ L<6>

FSB_A_ L<5>

FSB_A_ L<4>

FSB_A_ L<3>

FSB_DI NV_L<3 >

FSB_DS TB_L_N <3>

FSB_DS TB_L_P <3>

FSB_DI NV_L<2 >

FSB_DS TB_L_N <2>

FSB_DS TB_L_P <2>

FSB_DI NV_L<1 >

FSB_DS TB_L_N <1>

FSB_DS TB_L_P <1>

FSB_DI NV_L<0 >

FSB_DS TB_L_N <0>

FSB_DS TB_L_P <0>

=PP1V0 5_S0_M CP_FSB

PP1V05 _S0_MC P_PLL_F SB

FSB_D_ L<14>

FSB_D_ L<7>

FSB_A_ L<10>

FSB_A_ L<25>

FSB_A_ L<34>

FSB_A_ L<33>

FSB_DB SY_L FSB_DR DY_L

FSB_BN R_L

FSB_RS _L<0>

CPU_FE RR_L

FSB_BR EQ0_L

FSB_AD S_L

FSB_BR EQ1_L

=PP1V0 5_S0_M CP_FSB

=MCP_B SEL<2>

=MCP_B SEL<0>

=MCP_B SEL<1>

R1436

1

2

R1431

1

2

R1430

1

2

R1435

1

2

R1422

1

2

R1421

1

2

R1420

1

2

R1415

1

2

R1410

1

2

R1440

1

2

U1400

AK41

AJ40

G41

G42

AL42

AL43

AK42

AL41

AM40

AM39

AF35

AG35

AG39

AE33

AG37

AG38

AG34

AN38

AL39

AG33

AL33

AF41

AJ33

AN36

AJ35

AJ37

AJ36

AJ38

AL37

AL34

AN37

AC34

AJ34

AL38

AL35

AN34

AR39

AN35

AE38

AE34

AC37

AE37

AE35

AB35

AD42

AE36

AK35

AD43

AA41

AE40

AL32

F41

D42

F42

AM42

AM43

Y43

W42

R42

T39

T42

T41

R41

T43

W35

AA37

W33

W34

Y40

AA36

AA34

AA38

AA35

U38

U36

U35

U33

U34

W38

W41

R33

U37

N34

N33

R34

R35

P35

R39

R37

R38

Y39

L37

L39

L38

N36

N38

J39

J38

J37

L42

M42

V42

P41

N41

N40

M40

H40

K42

H41

L41

H43

H42

Y41

K41

J40

H39

M43

Y42

P42

U41

V41

V35

N35

J41

AD39

AA40

AN32

AN33

AM32

AD41

U40

W37

L36

M41

T40

W39

N37

M39

AH40

AB42

AD40

AH39

AH42

AF42

AC43

AG41

E41

AJ41

AH43

AC38

AA33

AC39

AC33

AC35

H38

AC41

AB41

AC42

AM33

AH41

AG42

AG43

AE41

AG27

AH28

AG28

AH27

R1416

1

2

24

22

14

14 9 9

87

8

24

87

8

0A

MEMORY

MEMORY PARTITION 0

CONTRO L

MCKE0A_1

MCKE0A_0

MODT0A_1

MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0 _N

MCLK0A_0 _P

MCLK0A_1 _N

MCLK0A_2 _N

MCLK0A_1 _P

MCLK0A_2 _P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8

MA0_7

MA0_9

MA0_10

MA0_11

MA0_13

MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_ P

MDQS0_0_ N

MDQS0_1_ P

MDQS0_2_ N

MDQS0_1_ N

MDQS0_2_ P

MDQS0_3_ N

MDQS0_4_ P

MDQS0_3_ P

MDQS0_4_ N

MDQS0_5_ N

MDQS0_5_ P

MDQS0_6_ N

MDQS0_6_ P

MDQS0_7_ N

MDQS0_7_ P

MDQM0_2

MDQM0_1

MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4

MDQ0_3

MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9

MDQ0_8

MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15

MDQ0_14

MDQ0_13

MDQ0_12

MDQ0_16

MDQ0_21

MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25

MDQ0_24

MDQ0_23

MDQ0_22

MDQ0_26

MDQ0_29

MDQ0_28

MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35

MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40

MDQ0_39

MDQ0_42

MDQ0_47

MDQ0_46

MDQ0_43

MDQ0_45

MDQ0_44

MDQ0_51

MDQ0_50

MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55

MDQ0_54

MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61

MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

BI

OUT

BI

OUT

MEMORY

CONTRO L

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60

MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56

MDQ1_55

MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51

MDQ1_50

MDQ1_48

MDQ1_47

MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42

MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36

MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31

MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26

MDQ1_25

MDQ1_24

MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11

MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6

MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4

MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_ P

MDQS1_6_ N

MDQS1_6_ P

MDQS1_7_ N

MDQS1_5_ N

MDQS1_5_ P

MDQS1_4_ P

MDQS1_3_ P

MDQS1_4_ N

MDQS1_2_ P

MDQS1_3_ N

MDQS1_1_ P

MDQS1_2_ N

MDQS1_1_ N

MDQS1_0_ P

MDQS1_0_ N

MRAS1#

MCAS1#

MWE1#

MBA1_2

MBA1_1

MBA1_0

MA1_14

MA1_13

MA1_12

MA1_11

MA1_10

MA1_9

MA1_8

MA1_7

MA1_6

MA1_5

MA1_4

MA1_3

MA1_2

MA1_1

MA1_0

MCLK1A_2 _P

MCLK1A_1 _P

MCLK1A_2 _N

MCLK1A_0 _P

MCLK1A_1 _N

MCS1A_1#

MCS1A_0#

MCLK1A_0 _N

MODT1A_1

MODT1A_0

MCKE1A_0

MCKE1A_1

BI

OUT

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

BGA

MCP79- TOPO-B

OMIT

(2 OF 11 )

28 88

29 88

BGA

MCP79- TOPO-B

OMIT

(3 OF 11 )

29 88

96

051-7546

A.0.0

15

SYNC_MA STER=T 18_MLB

SYNC_DA TE=06/ 18/2008

MCP Memory Interface

MEM_B_ DM<0>

MEM_B_ DM<1>

MEM_B_ DM<2>

MEM_B_ DM<3>

MEM_B_ DM<4>

MEM_B_ DM<5>

MEM_B_ DM<6>

MEM_B_ DM<7>

MEM_B_ DQ<0>

MEM_B_ DQ<1>

MEM_B_ DQ<2>

MEM_B_ DQ<3>

MEM_B_ DQ<4>

MEM_B_ DQ<5>

MEM_B_ DQ<6>

MEM_B_ DQ<7>

MEM_B_ DQ<8>

MEM_B_ DQ<9>

MEM_B_ DQ<10>

MEM_B_ DQ<11>

MEM_B_ DQ<12>

MEM_B_ DQ<13>

MEM_B_ DQ<14>

MEM_B_ DQ<15>

MEM_B_ DQ<16>

MEM_B_ DQ<17>

MEM_B_ DQ<18>

MEM_B_ DQ<19>

MEM_B_ DQ<20>

MEM_B_ DQ<21>

MEM_B_ DQ<22>

MEM_B_ DQ<23>

MEM_B_ DQ<24>

MEM_B_ DQ<25>

MEM_B_ DQ<26>

MEM_B_ DQ<27>

MEM_B_ DQ<28>

MEM_B_ DQ<29>

MEM_B_ DQ<30>

MEM_B_ DQ<31>

MEM_B_ DQ<32>

MEM_B_ DQ<33>

MEM_B_ DQ<34>

MEM_B_ DQ<35>

MEM_B_ DQ<36>

MEM_B_ DQ<37>

MEM_B_ DQ<38>

MEM_B_ DQ<39>

MEM_B_ DQ<40>

MEM_B_ DQ<41>

MEM_B_ DQ<42>

MEM_B_ DQ<43>

MEM_B_ DQ<44>

MEM_B_ DQ<45>

MEM_B_ DQ<46>

MEM_B_ DQ<47>

MEM_B_ DQ<48>

MEM_B_ DQ<49>

MEM_B_ DQ<50>

MEM_B_ DQ<51>

MEM_B_ DQ<52>

MEM_B_ DQ<53>

MEM_B_ DQ<54>

MEM_B_ DQ<55>

MEM_B_ DQ<56>

MEM_B_ DQ<57>

MEM_B_ DQ<58>

MEM_B_ DQ<59>

MEM_B_ DQ<60>

MEM_B_ DQ<61>

MEM_B_ DQ<62>

MEM_B_ DQ<63>

MEM_A_ DM<0>

MEM_A_ DM<1>

MEM_A_ DM<2>

MEM_A_ DM<3>

MEM_A_ DM<4>

MEM_A_ DM<5>

MEM_A_ DM<6>

MEM_A_ DM<7>

MEM_A_ DQ<0>

MEM_A_ DQ<1>

MEM_A_ DQ<2>

MEM_A_ DQ<3>

MEM_A_ DQ<4>

MEM_A_ DQ<5>

MEM_A_ DQ<6>

MEM_A_ DQ<7>

MEM_A_ DQ<8>

MEM_A_ DQ<9>

MEM_A_ DQ<10>

MEM_A_ DQ<11>

MEM_A_ DQ<12>

MEM_A_ DQ<13>

MEM_A_ DQ<14>

MEM_A_ DQ<15>

MEM_A_ DQ<16>

MEM_A_ DQ<17>

MEM_A_ DQ<18>

MEM_A_ DQ<19>

MEM_A_ DQ<20>

MEM_A_ DQ<21>

MEM_A_ DQ<22>

MEM_A_ DQ<23>

MEM_A_ DQ<24>

MEM_A_ DQ<25>

MEM_A_ DQ<26>

MEM_A_ DQ<27>

MEM_A_ DQ<28>

MEM_A_ DQ<29>

MEM_A_ DQ<30>

MEM_A_ DQ<31>

MEM_A_ DQ<32>

MEM_A_ DQ<33>

MEM_A_ DQ<34>

MEM_A_ DQ<35>

MEM_A_ DQ<36>

MEM_A_ DQ<37>

MEM_A_ DQ<38>

MEM_A_ DQ<39>

MEM_A_ DQ<40>

MEM_A_ DQ<41>

MEM_A_ DQ<42>

MEM_A_ DQ<43>

MEM_A_ DQ<44>

MEM_A_ DQ<45>

MEM_A_ DQ<46>

MEM_A_ DQ<47>

MEM_A_ DQ<48>

MEM_A_ DQ<49>

MEM_A_ DQ<50>

MEM_A_ DQ<51>

MEM_A_ DQ<52>

MEM_A_ DQ<53>

MEM_A_ DQ<54>

MEM_A_ DQ<55>

MEM_A_ DQ<56>

MEM_A_ DQ<57>

MEM_A_ DQ<58>

MEM_A_ DQ<59>

MEM_A_ DQ<60>

MEM_A_ DQ<61>

MEM_A_ DQ<62>

MEM_A_ DQ<63>

MEM_B_ CKE<0>

MEM_B_ CKE<1>

MEM_B_ ODT<0>

MEM_B_ ODT<1>

MEM_B_ CS_L<0 >

MEM_B_ CS_L<1 >

MEM_B_ CLK_N< 0>

MEM_B_ CLK_P< 0>

MEM_B_ CLK_N< 1>

MEM_B_ CLK_P< 1>

TP_MEM _B_CLK 2N

TP_MEM _B_CLK 2P

MEM_B_ A<0>

MEM_B_ A<1>

MEM_B_ A<2>

MEM_B_ A<3>

MEM_B_ A<4>

MEM_B_ A<5>

MEM_B_ A<6>

MEM_B_ A<7>

MEM_B_ A<8>

MEM_B_ A<9>

MEM_B_ A<10>

MEM_B_ A<11>

MEM_B_ A<12>

MEM_B_ A<13>

MEM_B_ A<14>

MEM_B_ BA<0>

MEM_B_ BA<1>

MEM_B_ BA<2>

MEM_B_ WE_L

MEM_B_ CAS_L

MEM_B_ RAS_L

MEM_B_ DQS_N< 0>

MEM_B_ DQS_P< 0>

MEM_B_ DQS_N< 1>

MEM_B_ DQS_P< 1>

MEM_B_ DQS_N< 2>

MEM_B_ DQS_P< 2>

MEM_B_ DQS_N< 3>

MEM_B_ DQS_P< 3>

MEM_B_ DQS_N< 4>

MEM_B_ DQS_P< 4>

MEM_B_ DQS_N< 5>

MEM_B_ DQS_P< 5>

MEM_B_ DQS_N< 6>

MEM_B_ DQS_P< 6>

MEM_B_ DQS_N< 7>

MEM_B_ DQS_P< 7>

MEM_A_ CKE<0>

MEM_A_ CKE<1>

MEM_A_ ODT<0>

MEM_A_ ODT<1>

MEM_A_ CS_L<0 >

MEM_A_ CS_L<1 >

MEM_A_ CLK_N< 0>

MEM_A_ CLK_P< 0>

MEM_A_ CLK_N< 1>

MEM_A_ CLK_P< 1>

TP_MEM _A_CLK 2N

TP_MEM _A_CLK 2P

MEM_A_ A<0>

MEM_A_ A<1>

MEM_A_ A<2>

MEM_A_ A<3>

MEM_A_ A<4>

MEM_A_ A<5>

MEM_A_ A<6>

MEM_A_ A<7>

MEM_A_ A<8>

MEM_A_ A<9>

MEM_A_ A<10>

MEM_A_ A<11>

MEM_A_ A<12>

MEM_A_ A<13>

MEM_A_ A<14>

MEM_A_ BA<0>

MEM_A_ BA<1>

MEM_A_ BA<2>

MEM_A_ WE_L

MEM_A_ CAS_L

MEM_A_ RAS_L

MEM_A_ DQS_N< 0>

MEM_A_ DQS_P< 0>

MEM_A_ DQS_N< 1>

MEM_A_ DQS_P< 1>

MEM_A_ DQS_N< 2>

MEM_A_ DQS_P< 2>

MEM_A_ DQS_N< 3>

MEM_A_ DQS_P< 3>

MEM_A_ DQS_N< 4>

MEM_A_ DQS_P< 4>

MEM_A_ DQS_N< 5>

MEM_A_ DQS_P< 5>

MEM_A_ DQS_N< 6>

MEM_A_ DQS_P< 6>

MEM_A_ DQS_N< 7>

MEM_A_ DQS_P< 7>

U1400

AR19

AT19

AN19

AW21

AN23

AU15

AR23

AU19

AV19

AN21

AR21

AP21

AU21

AR22

AV21

AW17

AP19

AP23

AP17

AT23

AU23

BC20

BB20

AY24

BA24

AV33

AW33

AR18

AT15

AP35

AR35

AV31

AT31

AW37

AV37

AR33

AU31

AN31

AV29

AN29

AV27

AW38

AR31

AP31

AR29

AP29

AR27

AP27

AR25

AP25

AU27

AT27

AV38

AU25

AR26

AU13

AR14

AT11

AR11

AW13

AV13

AV11

AU11

AR38

AV9

AU9

AY5

AW6

AP11

AW9

AU8

AU7

AV5

AU6

AR37

AR5

AN10

AW5

AV6

AR7

AR6

AN7

AN6

AL7

AL6

AV39

AN9

AP9

AL9

AL8

AW39

AU37

AT37

AR34

AV35

AW29

AN27

AN13

AR10

AU5

AN5

AT39

AU39

AU35

AT35

AU29

AU30

AW25

AV25

AR13

AP13

AW8

AW7

AR9

AR8

AL11

AL10

AV15

AP15

AV17

AR17

U1400

BA18

BB25

BA17

BC28

AW28

BA14

BA29

BA25

BB26

BA26

BA27

AY27

BA28

AY28

BB28

BB17

BB18

BB29

BA15

BB30

AY31

AY19

BA19

BA22

BB22

BB42

BA42

BB16

BB14

AP42

AR41

BC40

BA40

AV41

AV42

AW40

BB40

AY39

BA38

BB36

BA36

AU41

AY40

BA39

AW36

BC36

AY35

BA34

BB32

BA32

AY36

BA35

AU40

AW32

BC32

BA12

AY12

BB9

BB8

AW12

BB12

BB10

BA9

AN40

AY8

BA7

BC4

BB4

BC8

BA8

BA5

BB5

BB2

BA3

AP41

AW3

AW4

BC3

BB3

AY3

AY4

AU3

AU2

AR3

AR4

AT41

AV3

AV2

AT3

AT4

AT40

AW41

AW42

AR42

AY43

BB38

BB34

BA11

AY7

BA2

AT5

AT43

AT42

AY42

BA43

BA37

BB37

BA33

BB33

AY11

BA10

BA6

BB6

AY1

AY2

AT1

AT2

AY15

BB13

AW16

BA16

MCLK1B_2 _P

MCLK1B_1 _N

MCLK1B_0 _P

MCLK1B_1 _P

MCLK1B_2 _N

MCS1B_1#

MCS1B_0#

MCLK1B_0 _N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55

GND56

GND57

GND58

GND60

GND59

GND61

GND62

GND63

GND64

GND52

GND53

GND54

GND51

GND49

GND50

GND48

GND47

GND46

GND44

GND45

GND43

GND42

GND41

GND39

GND40

GND38

GND37

GND36

GND35

GND33

GND34

GND32

GND31

GND30

GND28

GND29

GND27

GND26

GND25

GND24

GND18

GND19

GND17

GND16

GND15

GND13

GND14

GND10

GND12

GND11

GND8

GND9

GND7

GND6

GND5

GND2

GND3

GND4

GND1

MEM_COMP _VDD

MEM_COMP _GND

MODT0B_0

MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0 _N

MCS0B_0#

MCS0B_1#

MCLK0B_2 _N

MCLK0B_1 _P

MCLK0B_0 _P

MCLK0B_1 _N

MCLK0B_2 _P

+V_PLL_X REF_XS

+V_PLL_C ORE

+V_VPLL

+VDD_MEM 1

+VDD_MEM 2

+VDD_MEM 3

+VDD_MEM 4

+VDD_MEM 5

+VDD_MEM 6

+VDD_MEM 7

+VDD_MEM 8

+VDD_MEM 9

+VDD_MEM 10

+VDD_MEM 11

+VDD_MEM 14

+VDD_MEM 15

+VDD_MEM 16

+VDD_MEM 17

+VDD_MEM 18

+VDD_MEM 19

+VDD_MEM 20

+VDD_MEM 22

+VDD_MEM 21

+VDD_MEM 23

+VDD_MEM 24

+VDD_MEM 25

+VDD_MEM 26

+VDD_MEM 30

+VDD_MEM 27

+VDD_MEM 29

+VDD_MEM 31

+VDD_MEM 32

+VDD_MEM 33

+VDD_MEM 34

+VDD_MEM 38

+VDD_MEM 39

+VDD_MEM 40

+VDD_MEM 41

+VDD_MEM 43

+VDD_MEM 44

+VDD_MEM 45

+VDD_MEM 42

+V_PLL_D P

+VDD_MEM 13

+VDD_MEM 12

+VDD_MEM 28

+VDD_MEM 37

+VDD_MEM 36

+VDD_MEM 35

GND21

GND20

GND22

GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

87 mA (A01)

39 mA

TP or NC for DDR2.

19 mA

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

12 mA

17 mA

4771 m A (A01 , DDR3)

1%

40.2

1/16W

402

MF-LF

402

1%

1/16W

40.2

(4 OF 11 )

MCP79- TOPO-B

OMIT

BGA

30

MCP Memory Misc

16 9 6

A.0.0

051-7546

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

TP_MEM _B_CKE <3>

TP_MEM _B_CKE <2>

TP_MEM _B_CS_ L<2>

MCP_ME M_RESE T_L

=PP1V8 R1V5_S 0_MCP_M EM

MCP_ME M_COMP _GND

TP_MEM _A_CLK 4N

TP_MEM _A_CLK 3P

TP_MEM _A_ODT <2> TP_MEM _A_ODT <3>

TP_MEM _A_CKE <2> TP_MEM _A_CKE <3>

TP_MEM _A_CLK 5P TP_MEM _A_CLK 5N

TP_MEM _A_CLK 4P

TP_MEM _A_CLK 3N

TP_MEM _A_CS_ L<2> TP_MEM _A_CS_ L<3>

PP1V05 _S0_MC P_PLL_C ORE

TP_MEM _B_CLK 5P TP_MEM _B_CLK 5N

TP_MEM _B_CLK 4P TP_MEM _B_CLK 4N

TP_MEM _B_CLK 3P TP_MEM _B_CLK 3N

TP_MEM _B_CS_ L<3>

TP_MEM _B_ODT <2> TP_MEM _B_ODT <3>

=PP1V8 R1V5_S 0_MCP_M EM

MCP_ME M_COMP _VDD

R1610

1

2

R1611

1

2

U1400

AA22

AA39

AB22

AB7

AD22

AE20

AF24

AG24

AH35

AK7

AM28

AP12

AT25

AP30

AR36

AU10

F28

BC21

AY9

BC9

D34

F24

G30

G32

H31

K7

M38

M5

M6

M7

M9

N39

N8

P10

P33

P34

P37

P4

P40

P7

R36

R40

R43

R5

T10

T18

T20

AK11

T24

T26

T33

T34

T35

T37

T38

T6

T7

T9

U18

U20

U22

V10

V34

W5

AV23

AN25

BA30

BA31

BB21

BA21

BC24

BB24

AU34

AU33

AY20

BA20

BA23

AY23

BB41

BA41

AU17

AR15

BC16

BA13

AM41

AN41

AN17

AN15

AY16

BC13

AY32

U27

U28

T27

T28

AM17

AN20

AN24

AT17

AP16

AN22

AP20

AP24

AV16

AR16

AR20

AM19

AR24

AW15

AP22

AP18

AU16

AN18

AU24

AT21

AY29

AV24

AM21

AU20

AU22

AW27

BC17

AV20

AY17

AY18

AM15

AU18

AY25

AM23

AY26

AW19

AW24

BC25

AL30

AM31

AM25

AM27

AM29

AN16

BC29

24

16

8

88

24

8

88

PE0_RX0_ P

PE0_RX2_ N

+AVDD0_P EX11

+AVDD0_P EX7

+AVDD0_P EX8

+AVDD1_P EX3

+AVDD1_P EX2

+AVDD1_P EX1

+AVDD0_P EX13

+AVDD0_P EX12

+AVDD0_P EX10

+AVDD0_P EX9

+AVDD0_P EX6

+AVDD0_P EX5

+AVDD0_P EX4

+AVDD0_P EX3

+AVDD0_P EX2

+AVDD0_P EX1

+V_PLL_P EX

+DVDD1_P EX2

+DVDD1_P EX1

+DVDD0_P EX8

+DVDD0_P EX7

+DVDD0_P EX6

+DVDD0_P EX5

+DVDD0_P EX4

+DVDD0_P EX3

+DVDD0_P EX2

+DVDD0_P EX1

PE0_RX0_ N

PE0_RX2_ P

PE0_RX4_ P

PE0_RX6_ P

PEB_PRSN T#

PE1_TX3_ N

PE1_TX3_ P

PE1_TX2_ N

PE1_TX1_ N

PE1_TX2_ P

PE1_TX0_ N

PE1_TX1_ P

PE6_REFC LK_N

PEX_RST0 #

PE1_TX0_ P

PE5_REFC LK_N

PE5_REFC LK_P

PE6_REFC LK_P

PE4_REFC LK_N

PE4_REFC LK_P

PE3_REFC LK_N

PE2_REFC LK_N

PE1_REFC LK_N

PE2_REFC LK_P

PE0_REFC LK_N

PE0_REFC LK_P

PE1_REFC LK_P

PE0_TX15 _N

PE0_TX14 _N

PE0_TX15 _P

PE0_TX13 _N

PE0_TX14 _P

PE0_TX12 _N

PE0_TX12 _P

PE0_TX13 _P

PE0_TX11 _N

PE0_TX11 _P

PE0_TX10 _N

PE0_TX9_ N

PE0_TX10 _P

PE0_TX8_ N

PE0_TX8_ P

PE0_TX9_ P

PE0_TX7_ N

PE0_TX7_ P

PE0_TX6_ N

PE0_TX5_ N

PE0_TX6_ P

PE0_TX4_ N

PE0_TX5_ P

PE0_TX3_ N

PE0_TX3_ P

PE0_TX4_ P

PE0_TX2_ N

PE0_TX2_ P

PE0_TX0_ N

PE0_TX1_ N

PE0_TX1_ P

PE0_TX0_ P

PEX_CLK_ COMP

PE1_RX3_ N

PE1_RX3_ P

PE1_RX2_ N

PE1_RX0_ N

PE1_RX1_ P

PE1_RX2_ P

PE1_RX1_ N

PE_WAKE#

PE1_RX0_ P

PE0_PRSN T_16#

PE0_RX13 _N

PE0_RX14 _P

PE0_RX15 _P

PE0_RX14 _N

PE0_RX15 _N

PE0_RX12 _P

PE0_RX11 _P

PE0_RX13 _P

PE0_RX11 _N

PE0_RX12 _N

PE0_RX10 _N

PE0_RX8_ P

PE0_RX9_ P

PE0_RX10 _P

PE0_RX8_ N

PE0_RX9_ N

PE0_RX5_ N

PE0_RX7_ P

PE0_RX6_ N

PE0_RX7_ N

PE0_RX3_ P

PE0_RX5_ P

PE0_RX3_ N

PE0_RX4_ N

PE0_RX1_ P

PE0_RX1_ N

PEC_PRSN T#

PEC_CLKR EQ#/GPIO_ 50

PE3_REFC LK_P

PED_CLKR EQ#/GPIO_ 51

PED_PRSN T#

PEB_CLKR EQ#/GPIO_ 49

PEE_CLKR EQ#/GPIO_ 16

PEE_PRSN T#/GPIO_4 6

PEF_CLKR EQ#/GPIO_ 17

PEF_PRSN T#/GPIO_4 7

PEG_CLKR EQ#/GPIO_ 18

PEG_PRSN T#/GPIO_4 8

PCI EXPRESS

OUT

IN

OUT

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

If PE1 inter face is not u sed, g round DVDD1_P EX and AVDD1 _PEX.

Minimu m 1.02 5V for Gen2 s upportMinimu m 1.02 5V for Gen2 s upport

Int PU

84 mA (A01)

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

Int PU

206 mA (A01, AVDD0 & 1)

If PE0 inter face is not u sed, g round DVDD0_P EX and AVDD0 _PEX.

57 mA (A01, DVDD0 & 1)

Int PU (S5)

MCP79- TOPO-B

(5 OF 11 )

OMIT

BGA

9

70 89

9

31 89

9

36

23 31 32

36 89

7

32 89

7

32 89

31

32

31 89

36 89

32 89

31 89

32 89

9

2.37K

402

MF-LF

1% 1/16W

NO STU FF

PLACEMEN T_NOTE=P lace wit hin 12.7 mm of U1 400

9

26

83

9

SYNC_MA STER=T 18_MLB

MCP PCIe Interfaces

17 9 6

A.0.0

051-7546

SYNC_DA TE=06/ 18/2008

AUD_IP _PERIP HERAL_D ET

TP_PE4 _CLKRE Q_L

PCIE_E XCARD_ PRSNT_L

TP_PE4 _PRSNT _L

=PP1V0 5_S0_M CP_PEX_ AVDD1

GMUX_J TAG_TD O

=PEG_D 2R_N<1 5>

=PEG_D 2R_N<1 4>

GMUX_J TAG_TC K_L

EXCARD _CLKRE Q_L

PCIE_C LK100M _EXCARD _P

FW_CLK REQ_L PCIE_F W_PRSN T_L

=PEG_D 2R_N<1 >

=PEG_D 2R_P<1 >

=PEG_D 2R_N<4 >

=PEG_D 2R_N<3 >

=PEG_D 2R_P<5 >

=PEG_D 2R_P<3 >

=PEG_D 2R_N<7 >

=PEG_D 2R_N<6 > =PEG_D 2R_P<7 >

=PEG_D 2R_N<5 >

=PEG_D 2R_N<9 >

=PEG_D 2R_N<8 >

=PEG_D 2R_P<1 0>

=PEG_D 2R_P<9 >

=PEG_D 2R_P<8 >

=PEG_D 2R_N<1 0>

=PEG_D 2R_N<1 2>

=PEG_D 2R_N<1 1>

=PEG_D 2R_P<1 3>

=PEG_D 2R_P<1 1>

=PEG_D 2R_P<1 2>

=PEG_D 2R_P<1 5>

=PEG_D 2R_P<1 4>

=PEG_D 2R_N<1 3>

PEG_PR SNT_L

PCIE_M INI_D2 R_P

PCIE_W AKE_L

PCIE_E XCARD_ D2R_P

PCIE_F W_D2R_ P

PCIE_M INI_D2 R_N

PCIE_E XCARD_ D2R_N

TP_PCI E_PE4_ D2RP TP_PCI E_PE4_ D2RN

MCP_PE X_CLK_ COMP

=PEG_R 2D_C_P <0>

=PEG_R 2D_C_P <1> =PEG_R 2D_C_N <1>

=PEG_R 2D_C_N <0>

=PEG_R 2D_C_P <2> =PEG_R 2D_C_N <2>

=PEG_R 2D_C_P <4>

=PEG_R 2D_C_P <3> =PEG_R 2D_C_N <3>

=PEG_R 2D_C_P <5>

=PEG_R 2D_C_N <4>

=PEG_R 2D_C_P <6>

=PEG_R 2D_C_N <5>

=PEG_R 2D_C_N <6> =PEG_R 2D_C_P <7> =PEG_R 2D_C_N <7>

=PEG_R 2D_C_P <9>

=PEG_R 2D_C_P <8> =PEG_R 2D_C_N <8>

=PEG_R 2D_C_P <10>

=PEG_R 2D_C_N <9>

=PEG_R 2D_C_N <10> =PEG_R 2D_C_P <11> =PEG_R 2D_C_N <11>

=PEG_R 2D_C_P <13>

=PEG_R 2D_C_P <12> =PEG_R 2D_C_N <12>

=PEG_R 2D_C_P <14>

=PEG_R 2D_C_N <13>

=PEG_R 2D_C_P <15>

=PEG_R 2D_C_N <14>

=PEG_R 2D_C_N <15>

PCIE_C LK100M _MINI_P

PEG_CL K100M_ P PEG_CL K100M_ N

PCIE_C LK100M _FW_P

PCIE_C LK100M _MINI_N

PCIE_C LK100M _FW_N

PCIE_C LK100M _EXCARD _N

TP_PCI E_CLK1 00M_PE4 P TP_PCI E_CLK1 00M_PE4 N

TP_PCI E_CLK1 00M_PE6 P

TP_PCI E_CLK1 00M_PE5 P TP_PCI E_CLK1 00M_PE5 N

PCIE_M INI_R2 D_C_P

PCIE_R ESET_L

TP_PCI E_CLK1 00M_PE6 N

PCIE_F W_R2D_ C_P

PCIE_M INI_R2 D_C_N

PCIE_E XCARD_ R2D_C_P

PCIE_F W_R2D_ C_N

PCIE_E XCARD_ R2D_C_N

TP_PCI E_PE4_ R2D_CP TP_PCI E_PE4_ R2D_CN

PCIE_M INI_PR SNT_L

=PEG_D 2R_P<6 >

=PEG_D 2R_P<4 >

=PEG_D 2R_P<2 >

=PEG_D 2R_N<0 >

PP1V05 _S0_MC P_PLL_P EX

=PEG_D 2R_N<2 >

=PEG_D 2R_P<0 >

PCIE_F W_D2R_ N

=PP1V0 5_S0_M CP_PEX_ DVDD0

=PP1V0 5_S0_M CP_PEX_ DVDD1

=PP1V0 5_S0_M CP_PEX_ AVDD0

MINI_C LKREQ_ L

TP_MCP _GPIO_ 18

U1400

Y12

AC12

AD12

V12

W12

AA12

AB12

M12

P12

R12

N12

T12

U12

M13

N13

P13

T17

W19

U17

V19

W16

W17

W18

U16

T19

U19

T16

C9 D11

E11

E7

F7

L8

L9

L6

L7

N10

N11

P9

N9

N6

N7

N4

N5

C7

D7

F6

E6

F5

E5

E3

E4

D3

C3

H5

G5

J6

J7

J4

J5

L10

L11

D4

C5

J1

H1

J3

J2

K3

K2

L3

L4

M3

M4

M1

M2

B4

C4

A3

A4

B2

B3

D1

C1

E1

D2

F2

E2

F4

F3

H4

G3

H2

H3

F11

G11

J9

K9

G9

H9

E9

F9

G7

H7

C8

D8

A8

B8

B7

A7

C6

B6

J10

J11

F13

G13

H13

J13

K14

L14

M14

N14

F17

D5

D9

E8

C10

M15

B10

L16

L18

M16

M18

M17

M19

A11

K11

R1710

1

2

9

8

9

89

9

24

8

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

GPIO_7/N FERR*/IGP U_GPIO_7

+V_DUAL_ MACPLL

+VDD_HDM I

+V_PLL_H DMI

+V_PLL_I FPAB

+VDD_IFP B

+VDD_IFP A

+V_TV_DA C

+V_RGB_D AC

+V_DUAL_ RMGT2

MII_COMP _GND

MII_COMP _VDD

LCD_PANE L_PWR/GP IO_58

LCD_BKL_ ON/GPIO_ 59

LCD_BKL_ CTL/GPIO _57

XTALOUT_ TV

GPIO_6/F ERR*/IGPU _GPIO_6

HDMI_TXC _P/ML0_L ANE3_P

HDMI_TXC _N/ML0_L ANE3_N

HDMI_TXD 0_P/ML0_ LANE2_P

HDMI_TXD 0_N/ML0_ LANE2_N

HDMI_TXD 1_P/ML0_ LANE1_P

HDMI_TXD 1_N/ML0_ LANE1_N

HDMI_TXD 2_P/ML0_ LANE0_P

HDMI_TXD 2_N/ML0_ LANE0_N

HPLUG_DE T2/GPIO_ 22

IFPA_TXC _N

XTALIN_T V

DDC_DATA 2/GPIO_2 4

DDC_CLK2 /GPIO_23

RGB_DAC_ RSET

RGB_DAC_ VREF

TV_DAC_V REF

DP_AUX_C H0_P

DP_AUX_C H0_N

HPLUG_DE T3

HDMI_RSE T

HDMI_VPR OBE

RGMII_MD IO

BUF_25MH Z

DDC_DATA 0

DDC_CLK0

RGB_DAC_ RED

RGB_DAC_ GREEN

RGB_DAC_ BLUE

RGB_DAC_ HSYNC

RGB_DAC_ VSYNC

TV_DAC_R ED

TV_DAC_G REEN

IFPA_TXC _P

IFPA_TXD 0_P

IFPA_TXD 0_N

IFPA_TXD 2_P

IFPA_TXD 1_P

IFPA_TXD 1_N

IFPA_TXD 3_P

IFPA_TXD 2_N

IFPB_TXC _P

IFPB_TXC _N

IFPB_TXD 5_P

IFPB_TXD 4_P

IFPB_TXD 4_N

IFPB_TXD 6_P

IFPB_TXD 5_N

IFPB_TXD 6_N

IFPB_TXD 7_P

IFPB_TXD 7_N

DDC_DATA 3

DDC_CLK3

IFPAB_RS ET

IFPAB_VP ROBE

TV_DAC_R SET

RGMII_RX D0

RGMII_IN TR/GPIO_3 5

RGMII_RX D3

RGMII_RX CTL/MII_R XDV

RGMII_RX C/MII_RXC LK

RGMII_RX D2

RGMII_RX D1

MII_RESE T#

RGMII_MD C

RGMII_PW RDWN/GPIO _37

MII_RXER /GPIO_36

MII_COL/ GPIO_20/ MSMB_DAT A

MII_CRS/ GPIO_21/ MSMB_CLK

TV_DAC_B LUE

TV_DAC_H SYNC/GPI O_44

TV_DAC_V SYNC/GPI O_45

+V_DUAL_ RMGT1

MII_VREF

RGMII_TX CTL/MII_T XEN

RGMII_TX C/MII_TXC LK

RGMII_TX D3

RGMII_TX D2

RGMII_TX D1

RGMII_TX D0

+3.3V_DU AL_RMGT1

+3.3V_DU AL_RMGT2

IFPA_TXD 3_N

LAN

DACS

FLAT PANEL

BI

OUT

BI

OUT

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

190 mA (A01, 1.8V)

C / Pr

MCP79 require s a S5 pull- up.

Comp / Pb

206 mA (A01)

103 mA

Okay t o floa t XTALI N_TV a nd XTA LOUT_T V.

Okay t o floa t all R GB_DAC signa ls. DDC_CL K0/DDC _DATA0 pull-u ps sti ll req uired.

Y / Y

TV DAC Disab le:

Okay t o floa t all T V_DAC signal s.

DDC_CL K0/DDC _DATA0 pull-u ps sti ll req uired.

ENET_TXD<0>

1

0

MII

RGMII

Interface

Network Interface Select

NOTE: All Ap ple pro ducts set st rap to

featur e via s oftwar e. Th is avoids a leak age is sue si nce

RGB ON LY

5 mA ( A01)

Displa yPort

DP_IG_ ML_P/N <3>

DP_IG_ ML_P/N <1>

DP_IG_ ML_P/N <2>

DP_IG_ DDC_CL K

TP_DP_ IG_AUX _CHP/N

TMDS_I G_DDC_ DATA

TMDS_I G_TXD_ P/N<2>

TMDS_I G_TXD_ P/N<1>

TMDS_I G_DDC_ CLK

TMDS_I G_TXD_ P/N<0>

TMDS_I G_TXC_ P/N

TMDS/H DMI

=MCP_H DMI_TX C_P/N =MCP_H DMI_TX D_P/N<0 >

MCP Si gnal

=MCP_H DMI_DD C_CLK

=MCP_H DMI_TX D_P/N<1 > =MCP_H DMI_TX D_P/N<2 >

=MCP_H DMI_DD C_DATA

TMDS_I G_HPD

=MCP_H DMI_HP D DP_IG_ AUX_CH _P/N

8 mA 8 mA

16 mA (A01)

95 mA (A01)

LVDS: Power +VDD_I FPx at 1.8V

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

TV / Compo nent

RGB DA C Disa ble:

WF: IF P is c apable of LVD S (1.8 V) or TMDS (3 .3V), need a liases

MII, R GMII pr oducts will enable

83 mA (A01)

131 mA (A01)

Dual-c hannel TMDS: Power +VDD_I FPx at 3.3V

NOTE: 1M pul l-down requir ed on DP_IG_ CA_DET if DP not us ed.

DP_IG_ AUX_CH _P/N

DP_IG_ HPD

DP_IG_ DDC_DA TA

DP_IG_ ML_P/N <0>

Interf ace Mo de

be use d to pr ovide HDMI o r dual -channe l TMDS witho ut

NOTE: HDMI p ort req uires level- shifti ng. IF P inte rface can

level- shifter s.

NOTE: 20K pu ll-down requi red on DP_HP D_DET. NOTE: 1K pul l-down requir ed on DP_IG_ AUX_CH_ N if D P is u sed.

(See b elow)

Alias to DVI _HPD fo r syst ems us ing IF P for D VI.

=DVI_H PD_GMU X_INT:

Pull-d own (2 0k) req uired in all cases .

Alias to HPL UG_DET2 for o ther s ystems .

Alias to GMU X_INT f or sys tems w ith GM UX.

pull-u ps (~1 0K to 3 .3V S0 ). To ensur e pins are lo w by def ault, pull-do wns (1 K or s tronge r) must be us ed.

GPIOs 57-59 (if LCD panel is us ed):

In MCP 79 the se pins have undocu mented intern al

24

33 91

34 91

33 91

25 89

9

80 89

9

25 89

1% 1/16W MF-LF

402

49.9

1/16W MF-LF

49.9

402

1%

80

25

9

(6 OF 11 )

BGA

MCP79- TOPO-B

OMIT

10K

402

1/16W

5%

MF-LF

402

5%

100K

1/16W MF-LF

402

MF-LF

5%

1/16W

100K

44

5%

47K

402

MF-LF

1/16W

33 91

83 89

33 91

83 89

9

89

9

89

9

89

9

89

83 89

33 91

83 89

9

89

9

89

80

9

25 89

33 91

25 89

33 91

18 9 6

A.0.0

051-7546

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

MCP Ethernet & Graphics

=DVI_H PD_GMU X_INT

LVDS_I G_BKL_ PWM

MCP_CL K27M_X TALOUT

TP_MCP _RGB_D AC_RSET TP_MCP _RGB_D AC_VREF

LPCPLU S_GPIO

=PP1V0 5_ENET _MCP_RM GT

=PP3V3 _S5_MC P_GPIO

=PP3V3 _ENET_ MCP_RMG T

=PP3V3 _S0_MC P_GPIO

=PP3V3 _ENET_ MCP_RMG T

ENET_T XD<0> ENET_T XD<1> ENET_T XD<2> ENET_T XD<3>

ENET_C LK125M _TXCLK ENET_T X_CTRL

MCP_MI I_VREF

CRT_IG _VSYNC

CRT_IG _HSYNC

CRT_IG _B_COM P_PB

=MCP_M II_CRS

=MCP_M II_COL

=MCP_M II_RXE R

TP_ENE T_PWRD WN_L

ENET_M DC

ENET_R ESET_L

ENET_R XD<1> ENET_R XD<2>

ENET_C LK125M _RXCLK ENET_R X_CTRL

ENET_R XD<3>

TP_ENE T_INTR _L

ENET_R XD<0>

MCP_TV _DAC_R SET

MCP_IF PAB_VP ROBE

MCP_IF PAB_RS ET

=MCP_H DMI_DD C_CLK =MCP_H DMI_DD C_DATA

LVDS_I G_B_DA TA_N<3>

LVDS_I G_B_DA TA_P<3>

LVDS_I G_B_DA TA_N<2>

LVDS_I G_B_DA TA_N<1> LVDS_I G_B_DA TA_P<2>

LVDS_I G_B_DA TA_N<0>

LVDS_I G_B_DA TA_P<0>

LVDS_I G_B_DA TA_P<1>

LVDS_I G_B_CL K_N

LVDS_I G_B_CL K_P

LVDS_I G_A_DA TA_N<2> LVDS_I G_A_DA TA_P<3>

LVDS_I G_A_DA TA_N<1>

LVDS_I G_A_DA TA_P<1>

LVDS_I G_A_DA TA_P<2>

LVDS_I G_A_DA TA_N<0>

LVDS_I G_A_DA TA_P<0>

LVDS_I G_A_CL K_P

CRT_IG _G_Y_Y

CRT_IG _R_C_P R

TP_MCP _RGB_V SYNC

TP_MCP _RGB_H SYNC

TP_MCP _RGB_B LUE

TP_MCP _RGB_G REEN

TP_MCP _RGB_R ED

MCP_DD C_CLK0 MCP_DD C_DATA 0

MCP_CL K25M_B UF0_R

ENET_M DIO

=MCP_H DMI_HP D

DP_IG_ AUX_CH _N

DP_IG_ AUX_CH _P

MCP_TV _DAC_V REF

LVDS_I G_DDC_ CLK LVDS_I G_DDC_ DATA

MCP_CL K27M_X TALIN

=MCP_H DMI_TX D_N<2>

=MCP_H DMI_TX C_P

LVDS_I G_BKL_ ON LVDS_I G_PANE L_PWR

MCP_MI I_COMP _VDD MCP_MI I_COMP _GND

PP3V3_ S0_MCP _DAC

=PP3V3 R1V8_S 0_MCP_I FP_VDD

PP3V3_ S0_MCP _VPLL

=PP1V0 5_S0_M CP_HDMI _VDD

PP1V05 _ENET_ MCP_PLL _MAC

DP_IG_ CA_DET

MCP_HD MI_VPR OBE

MCP_HD MI_RSE T

LVDS_I G_A_DA TA_N<3>

LVDS_I G_A_CL K_N

=MCP_H DMI_TX D_P<2>

=MCP_H DMI_TX D_N<1>

=MCP_H DMI_TX D_P<1>

=MCP_H DMI_TX D_P<0>

=MCP_H DMI_TX C_N

=MCP_H DMI_TX D_N<0>

R1810

1

2

R1811

1

2

U1400

E23

B31

C30

D31

A31

B30

E31

C43

D43

E16

B15

J31

E35

D35

F35

G35

G33

F33

H33

J33

J30

C31

F31

C35

B35

A32

B32

C32

D32

C33

D33

C34

B34

E32

G31

K31

L31

H29

J29

K29

L29

K30

L30

M30

N30

G39

E37

F40

B26

B27

C27

B22

J23

F23

E28

J24

K24

T23

U23

V23

M29

M28

J32

K32

T25

M27

M26

B40

A39

A40

B39

C39

B38

A41

J22

D21

C21

G23

A23

C22

C23

B23

E24

A24

D24

C26

B24

C24

C25

D25

C36

B36

D36

A36

E36

A35

C37

C38

D38

R1850

1

2

R1861

1

2

R1860

1

2

R1820

1

2

24

21

24

20

18

19

18

25

8

25

91

25

8

25

8

24

OUT

BI

LPC PCIGND

PCI_INTW #

PCI_INTX #

PCI_INTY #

PCI_INTZ #

GND65

LPC_DRQ1 #/GPIO_1 9

LPC_PWRD WN#/GPIO _54/EXT_ NMI#

PCI_TRDY #

LPC_DRQ0 #

LPC_SERI RQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5

PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10

PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15

PCI_AD16

PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21

PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66

GND67

GND69

GND68

GND70

GND71

GND72

GND74

GND73

GND75

GND76

GND77

GND79

GND78

GND80

GND81

GND84

GND83

GND82

GND85

GND86

GND87

GND89

GND88

GND90

GND91

GND92

GND94

GND93

GND95

GND96

GND97

PCI_GNT0 #

PCI_CBE2 #

PCI_CBE0 #

PCI_CBE3 #

PCI_IRDY #

PCI_FRAM E#

PCI_DEVS EL#

PCI_PAR

PCI_SERR #

PCI_STOP #

PCI_RESE T0#

PCI_RESE T1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKI N

LPC_FRAM E#

LPC_AD1

LPC_AD0

LPC_RESE T0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105

GND106

GND107

GND109

GND108

GND110

GND111

GND112

GND115

GND114

GND113

GND116

GND117

GND120

GND119

GND118

GND121

GND122

GND123

GND125

GND124

GND126

GND127

GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKR UN#/GPIO _42

PCI_AD28

PCI_GNT2 #/GPIO_4 1/RS232_ DTR#

PCI_GNT3 #/GPIO_3 9/RS232_ RTS#

PCI_GNT4 #/GPIO_5 3/RS232_ SOUT#

PCI_GNT1 #/FANCTL 2

PCI_CBE1 #

PCI_PERR #/GPIO_4 3/RS232_ DCD#

PCI_REQ3 #/GPIO_3 8/RS232_ CTS#

PCI_REQ4 #/GPIO_5 2/RS232_ SIN#

PCI_PME# /GPIO_30

PCI_REQ2 #/GPIO_4 0/RS232_ DSR#

PCI_REQ0 #

PCI_REQ1 #/FANRPM 2

IN

BI

OUT

IN

OUT

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Strap for Bo ot ROM Select ion (S ee HDA _SDOUT)

Int PU Int PU Int PU

Int PU (S5)

42 44 83 90

26 83 90

42 44 83 90

BGA

(7 OF 11 )

MCP79- TOPO-B

OMIT

42 44

42 44 26 90

42 44

PLACEMEN T_NOTE=P lace clo se to pi n R8

MF-LF 402

1/16W

5%

22

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

5%

1/16W MF-LF

402

19

MF-LF 402

1/16W

5%

10K

1/16W MF-LF

402

22

5%

1/16W MF-LF22402

5%

1/16W MF-LF22402

22

5%

1/16W MF-LF

402

MF-LF1/16W

5%

22

26

36

19

13 23

13 90

9

59

9

051-7546

A.0.0

9619

MCP PCI & LPC

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

GMUX_J TAG_TD I

GMUX_J TAG_TM S

TP_PCI _INTX_ L

TP_PCI _INTZ_ L

FW_PME _L TP_LPC _DRQ0_ L LPC_SE RIRQ

PM_CLK RUN_L

=PP3V3 _S0_MC P_GPIO

MCP_RS 232_SI N_L

MCP_DE BUG<7>

MCP_DE BUG<6>

MCP_DE BUG<5>

MCP_DE BUG<4>

MCP_DE BUG<3>

MCP_DE BUG<2>

MCP_DE BUG<1>

MCP_DE BUG<0>

MCP_RS 232_SI N_L

AUD_IP HS_SWI TCH_EN

CRTMUX _SEL_T V_L

TP_PCI _AD<12 > TP_PCI _AD<13 > TP_PCI _AD<14 >

TP_PCI _AD<16 > TP_PCI _AD<17 > TP_PCI _AD<18 > TP_PCI _AD<19 > TP_PCI _AD<20 > TP_PCI _AD<21 > TP_PCI _AD<22 > TP_PCI _AD<23 > TP_PCI _AD<24 > TP_PCI _AD<25 > TP_PCI _AD<26 > TP_PCI _AD<27 > TP_PCI _AD<28 > TP_PCI _AD<29 > TP_PCI _AD<30 > TP_PCI _AD<31 >

TP_PCI _INTW_ L

TP_PCI _TRDY_ L

TP_PCI _INTY_ L

TP_PCI _AD<15 >

PCI_RE Q0_L PCI_RE Q1_L

TP_PCI _AD<8>

TP_PCI _AD<10 > TP_PCI _AD<11 >

TP_PCI _AD<9>

TP_PCI _PERR_ L

MEM_VT T_EN_R

PCI_CL K33M_M CP

TP_PCI _CLK1 PCI_CL K33M_M CP_R

LPC_PW RDWN_L

LPC_RE SET_L

LPC_FR AME_R_ L

LPC_CL K33M_S MC_R

LPC_AD _R<3>

LPC_AD _R<2>

LPC_AD _R<1>

LPC_AD _R<0>

TP_PCI _CLK0

TP_PCI _RESET 1_L

PM_LAT RIGGER _L

TP_PCI _STOP_ L

TP_PCI _SERR_ L

TP_PCI _PAR

TP_PCI _IRDY_ L

TP_PCI _FRAME _L

TP_PCI _DEVSE L_L

TP_PCI _C_BE_ L<3>

TP_PCI _C_BE_ L<2>

TP_PCI _C_BE_ L<1>

TP_PCI _C_BE_ L<0>

MCP_RS 232_SO UT_L

TP_PCI _GNT1_ L

TP_PCI _GNT0_ L

LPC_AD <0>

LPC_FR AME_L

LPC_AD <2> LPC_AD <3>

LPC_AD <1>

MCP_RS 232_SO UT_L

PCI_RE Q0_L PCI_RE Q1_L CRTMUX _SEL_T V_L

U1400

AB18

H34

AB20

AB21

AB23

AB24

AB25

AB26

AB27

AB28

AB34

AB37

AB4

AB40

AC22

AC36

AC40

AB33

AC5

AD16

AD17

AD18

AD19

AD20

AD24

AD25

AD26

AD27

AD28

AD33

AD34

U24

U26

U39

U4

U8

V16

V17

V18

V20

V22

V24

V26

V27

V28

V33

V37

V4

V40

V7

W20

W22

W24

W36

W40

W43

Y16

Y17

Y18

Y19

Y20

Y22

Y24

Y25

Y26

Y27

AD3

AD2

AD1

AD5

AE9

AE1

AE2

AD4

AE12

AE5

AE6

AC3

AE10

AC9

AC10

AC11

AA1

AA5

Y5

W3

W6

W4

W7

AC4

V3

W8

V2

W9

U3

W11

U2

U5

U1

U6

AE11

T5

U7

AB3

AC6

AB2

AC7

AC8

AA2

AA3

AA6

AA11

W10

R6

R7

R8

R9

AD11

AA9

Y4

R3

U10

R4

U11

P3

P2

N3

N2

N1

AA10

Y1

AB9

T1

T2

V9

T3

U9

T4

R10

R11

AA7

Y2

Y3

R1910

1

2

R1989

1 2

R1991

1 2

R1990

1 2

R1994

1 2

R1992

1 2

R1961

1

2

R1960

1 2

R1950

1 2

R1951

1 2

R1952

1 2

R1953

1 2

21 18

90

8

19

90

44

19

BI

IN

SATA_B0_ RX_N

SATA_A0_ RX_P

SATA_A1_ TX_P

GND160

GND158

GND159

GND157

GND156

GND155

GND153

GND154

GND152

GND151

GND150

GND148

GND149

GND147

GND146

GND145

GND143

GND144

GND142

GND141

GND140

GND139

GND136

GND133

GND134

GND132

GND131

USB_RBIA S_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TER MP

SATA_LED #

SATA_C1_ RX_N

SATA_C1_ RX_P

SATA_C0_ TX_P

SATA_B1_ RX_N

SATA_B1_ RX_P

SATA_B1_ TX_N

SATA_B1_ TX_P

SATA_B0_ TX_N

SATA_B0_ RX_P

SATA_B0_ TX_P

SATA_A1_ RX_N

SATA_A1_ RX_P

SATA_A1_ TX_N

SATA_A0_ TX_P

GND138

GND137

GND135

USB3_P

USB3_N

USB_OC0# /GPIO_25

USB_OC1# /GPIO_26

USB_OC2# /GPIO_27 /MGPIO

USB_OC3# /GPIO_28 /MGPIO

SATA_A0_ RX_N

SATA_A0_ TX_N

SATA_C1_ TX_N

SATA_C1_ TX_P

SATA_C0_ RX_P

SATA_C0_ RX_N

SATA_C0_ TX_N

+V_PLL_U SB

+V_PLL_S ATA

+DVDD0_S ATA1

+DVDD0_S ATA2

+DVDD0_S ATA3

+DVDD0_S ATA4

+DVDD1_S ATA2

+AVDD0_S ATA1

+AVDD0_S ATA2

+AVDD0_S ATA3

+AVDD0_S ATA4

+AVDD0_S ATA5

+AVDD0_S ATA6

+AVDD0_S ATA7

+AVDD0_S ATA8

+AVDD0_S ATA9

+AVDD1_S ATA1

+AVDD1_S ATA2

+AVDD1_S ATA3

+AVDD1_S ATA4

+DVDD1_S ATA1

SATA

USB

OUT

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

If all SATA_ Ax & Bx pins are no t used , groun d DVDD 0_SATA and A VDD0_S ATA.

127 mA (A01, AVDD0 & 1)

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

Geyser Track pad/Key board

AirPor t (PCI e Mini- Card)

Extern al D

Extern al A

Camera

Blueto oth

IR

Extern al B

Extern al C

19 mA (A01)

Minimu m 1.02 5V for Gen2 s upport

Expres sCard

43 mA (A01, DVDD0 & 1)

84 mA (A01)

If all SATA_ Cx pins are n ot use d, gro und DVD D1_SAT A and AVDD1_ SATA.

Minimu m 1.02 5V for Gen2 s upport

40 90

9

90

9

90

9

90

9

90

31 90

41 90

50 90

31 90

40 90

32 90

9

90

9

90

40

32 43

2.49K

402

1/16W

1%

MF-LF

402

1/16W

1%

MF-LF

806

402

1/16W MF-LF

8.2K

5%

8.2K

5%

MF-LF

1/16W

402

MF-LF 402

1/16W

8.2K

5%

8.2K

5%

MF-LF

1/16W

402

BGA

OMIT

MCP79- TOPO-B

(8 OF 11 )

39 89

SYNC_DA TE=06/ 18/2008

20 9 6

A.0.0

051-7546

MCP SATA & USB

SYNC_MA STER=T 18_MLB

=PP1V0 5_S0_M CP_SATA _AVDD1

=PP1V0 5_S0_M CP_SATA _DVDD0

SATA_O DD_D2R _P

SATA_O DD_D2R _N

SATA_O DD_R2D _C_N

SATA_O DD_R2D _C_P

SATA_H DD_D2R _N SATA_H DD_D2R _P

SATA_H DD_R2D _C_N

SATA_H DD_R2D _C_P

TP_SAT A_C_D2 RP

TP_SAT A_C_D2 RN

PP1V05 _S0_MC P_PLL_S ATA

USB_EX TA_OC_ L

TP_USB _11N

TP_USB _11P

TP_USB _10P

USB_EX TC_N

USB_EX CARD_N

USB_EX TB_N

USB_EX TB_P

USB_BT _N

USB_BT _P

USB_TP AD_N

USB_TP AD_P

USB_IR _N

USB_IR _P

USB_CA MERA_N

USB_CA MERA_P

USB_EX TD_N

USB_EX TD_P

USB_MI NI_N

USB_EX TA_N

USB_EX TA_P

MCP_SA TA_TER MP

TP_SAT A_F_D2 RP

TP_SAT A_F_D2 RN

TP_SAT A_F_R2 D_CN

TP_SAT A_E_D2 RN

TP_SAT A_D_R2 D_CN

TP_SAT A_C_R2 D_CN

TP_SAT A_C_R2 D_CP

TP_MCP _SATAL ED_L

TP_SAT A_D_D2 RN

TP_SAT A_E_R2 D_CP TP_SAT A_E_R2 D_CN

TP_SAT A_E_D2 RP

USB_EX TC_P

USB_EX CARD_P

TP_SAT A_D_D2 RP

=PP1V0 5_S0_M CP_SATA _DVDD1

=PP1V0 5_S0_M CP_SATA _AVDD0

TP_SAT A_F_R2 D_CP

TP_SAT A_D_R2 D_CP

USB_EX TB_OC_ L

PP3V3_ S0_MCP _PLL_US B

MCP_US B_RBIA S_GND

EXCARD _OC_L

TP_USB _10N

USB_EX TC_OC_ L

=PP3V3 _S5_MC P_GPIO

USB_MI NI_P

R2010

1

2

R2060

1

2

R2053

1

2

R2052

1

2

R2051

1

2

R2050

1

2

U1400

AD35

AD37

AD38

AE22

AE24

AE39

AE4

AD6

AF16

AF17

AF18

AF20

AF22

AF26

AF27

AF28

AF33

AF34

AF37

AF40

AG18

AG20

AG22

AG26

AG36

AG40

AH18

AH20

AH22

AH24

AJ12

AN11

AK12

AK13

AL12

AM11

AM12

AN12

AL13

AN14

AL14

AM13

AM14

AF19

AG16

AG17

AG19

AH17

AH19

AE16

L28

AJ5

AJ4

AJ6

AJ7

AJ9

AK9

AJ10

AJ11

AJ2

AJ1

AJ3

AK2

AL4

AK3

AL3

AM4

AM2

AM3

AM1

AN1

AN3

AN2

AP2

AP3

E12

AE3

D29

C29

G25

F25

L23

K23

D28

C28

B28

A28

G29

F29

L27

K27

J27

J26

G27

F27

E27

D27

L25

K25

J25

H25

L21

K21

J21

H21

A27

18

9

8

24

89

9

8

24

90

8

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

HDA_SDAT A_IN1/GP IO_2/PS2 _KB_CLK

HDA_SDAT A_IN2/GP IO_3/PS2 _KB_DATA

MCP_VID2 /GPIO_15

MCP_VID1 /GPIO_14

MCP_VID0 /GPIO_13

THERM_DI ODE_N

EXT_SMI/ GPIO_32#

FANCTL1/ GPIO_62

FANRPM1/ GPIO_63

FANCTL0/ GPIO_61

FANRPM0/ GPIO_60

SIO_PME#

KBRDRSTI N#

PKG_TEST

TEST_MOD E_EN

BUF_SIO_ CLK

CPUVDD_E N

SMB_DATA 0

SMB_CLK0

SPKR

HDA_RESE T#

HDA_SYNC

HDA_BITC LK

HDA_SDAT A_OUT

XTALIN_R TC

XTALOUT

XTALOUT_ RTC

JTAG_TRS T#

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI

JTAG_TDO

RTC_RST#

PS_PWRGD

PWRGD_SB

INTRUDER #

LID#

LLB#

PWRBTN#

RSTBTN#

CPU_DPRS LPVR

SLP_S5#

SLP_S3#

HDA_DOCK _RST#/GP IO_5/PS2 _MS_DATA

HDA_DOCK _EN#/GPI O_4/PS2_ MS_CLK

A20GATE

GPIO_12/ SUS_STAT# /ACCLMTR

HDA_SDAT A_IN0

GPIO_1/P WRDN_OK/ SPI_CS1

HDA_PULL DN_COMP

THERM_DI ODE_P

SLP_RMGT #

SMB_CLK1 /MSMB_CL K

SMB_DATA 1/MSMB_D ATA

SMB_ALER T#/GPIO_ 64

SPI_CS0/ GPIO_10

SPI_CLK/ GPIO_11

SPI_DI/G PIO_8

SPI_DO/G PIO_9

SUS_CLK/ GPIO_34

+V_DUAL_ HDA1

+V_DUAL_ HDA2

+V_PLL_N V_H

+V_PLL_S P_SPREF

HDA

MISC

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

(MGPIO 2)

(MGPIO 3)

Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA ( A01)

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

HDA Output Caps

For EM I Redu ction o n HDA interf ace

PCI

not us e LPC f or Boo tROM o verrid e.

LPC_FR AME# h igh for SPI1 ROM ov erride .

SPI0 = SPI_C S0_L, S PI1 = SPI_CS 1_L

Int PU

Int PU (S5)

Int PU

25 MHz

42 MHz

0

LPC RO Ms. So Apple desig ns wil l

0

1

HDA_SYNC

24 MHz

0

1

0

SPI_CLK

SPI_DO

0

1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not pr ovided on th is pag e.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does no t supp ort FW H, onl y

LPC

SPI0

SPI1

I/F HDA_SDOUT

BIOS Boot Select

R1961 and R2 160 sel ects S PI0 RO M by defaul t, LPC + debug card pulls

1

0

LPC_FRAME#

0

1

0

1

Int PU

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not su pport SPI1 o ption. Rev B 01 wil l.

Int PU

Int PU (S5)

(MXM_O K for MXM sys tems)

SAFE m ode: F or ROMS IP r ecovery

USER m ode: N ormal

Connec ts to SMC for automa tic re covery.

44 90

7

34 37 42 44 68 81 83

40 42 43 68

7

13 45 90

45 90

7

13 45 90

45 90

21 65

48 95

21 65

21 31 34

48 95

9

62 87

23 42

54 90

9

90

54 90

MF-LF

1/16W

1%

402

49.9K

1%

49.9K

MF-LF

402

1/16W

1K

MF-LF

1% 1/16W

402

26 90

23 42

MF-LF

402

5%

22

1/16W

MF-LF

5%

1/16W

402

22

5%

22

MF-LF

1/16W

402

5%

10K

MF-LF

1/16W

MF-LF

8.2K

5% 1/16W

402

5%

10K

MF-LF

BOOT_M ODE_SA FE

402

1/16W

5%

10K

402

MF-LF

BOOT_M ODE_US ER

1/16W

402

5%

22

1/16W MF-LF

9

44

49.9

MF-LF

1/16W

1%

402

1/16W MF-LF

5%

10K

6

13 23

6

13 23

6

13

6

13

6

10PF

50V

5%

402

CERM

50V

10PF

5%

402

CERM

50V

10PF

5%

402

CERM

50V

10PF

5%

402

CERM

BGA

(9 OF 11 )

MCP79- TOPO-B

OMIT

39

21 59

26 26

34 37 42 43

21 28 29 42

402

1/16W MF-LF

5%

100K

10K

5% 1/16W

402

MF-LF

402

1/16W MF-LF

5%

10K

22K

5%

MF-LF

1/16W

402

22K

5%

MF-LF

1/16W

402402

1/16W

22K

5%

MF-LF

402

MF-LF

5% 1/16W

100K

1/16W MF-LF

5%

100K

402

MF-LF 402

1/16W

5%

10K10K

5%

MF-LF

1/16W

402

9

21 43

26

42

23 42

23 26

44 90

MCP HDA & MISC

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

21 9 6

A.0.0

051-7546

TP_MCP _BUF_S IO_CLK

=PP3V3 R1V5_S 0_MCP_H DA

MCP_GP IO_4

AP_PWR _EN

=PP3V3 _S3_MC P_GPIO

AUD_I2 C_INT_ L

MCP_GP IO_4

MCP_CP U_VLD

MCP_VI D<0>

PM_DPR SLPVR

HDA_SD IN0

MCP_VI D<0>

MCP_TH MDIODE _P

SMBUS_ MCP_1_ CLK

TP_MCP _LID_L

PM_PWR BTN_L

RTC_RS T_L

MCP_PS _PWRGD

JTAG_M CP_TDI JTAG_M CP_TDO

SMBUS_ MCP_1_ DATA AP_PWR _EN

MCP_VI D<2>

SMBUS_ MCP_0_ DATA

PM_BAT LOW_L

HDA_SD OUT_R

HDA_BI T_CLK_ R

=SPI_C S1_R_L _USE_ML B

SPI_CL K_R

SMC_RU NTIME_ SCI_L

MCP_VI D<1>

PM_SLP _RMGT_ L

TP_SB_ A20GAT E

MCP_HD A_PULL DN_COMP

PP1V05 _S0_MC P_PLL_N V

SPI_CS 0_R_L

RTC_CL K32K_X TALOUT

RTC_CL K32K_X TALIN

MCP_CL K25M_X TALOUT

MCP_CL K25M_X TALIN

JTAG_M CP_TCK

PM_CLK 32K_SU SCLK_R

SPI_MI SO SPI_MO SI_R

SMBUS_ MCP_0_ CLK

MCP_TH MDIODE _N

PM_SYS RST_DE BOUNCE_ L

TP_MCP _KBDRS TIN_L

HDA_RS T_L

HDA_BI T_CLK

HDA_SD OUT

PP3V3_ G3_RTC

=PP3V3 R1V5_S 0_MCP_H DA

HDA_SY NC_R

HDA_SD OUT_R

HDA_RS T_R_L

HDA_BI T_CLK_ R

MCP_VI D<2>

MCP_VI D<1>

JTAG_M CP_TMS

MCP_TE ST_MOD E_EN

JTAG_M CP_TRS T_L

PM_RSM RST_L

SM_INT RUDER_ L

ARB_DE TECT

HDA_SY NC

HDA_RS T_R_L

ODD_PW R_EN_L

MEM_EV ENT_L

SMC_WA KE_SCI _L

=PP3V3 _S0_MC P_GPIO

MEM_EV ENT_L SMC_IG _THROT TLE_L

SMC_AD APTER_ EN

TP_MLB _RAM_V ENDOR

TP_MLB _RAM_S IZE

HDA_SY NC_R

AUD_I2 C_INT_ L

PM_SLP _S3_L

PM_SLP _S4_L

=PP3V3 _S0_MC P

MCP_SP KR

MCP_CP UVDD_E N

ARB_DE TECT

SMC_IG _THROT TLE_L

R2121

1

2

R2120

1

2

R2190

1

2

R2170

1 2

R2171

1 2

R2173

1 2

R2163

1

2

R2160

1

2

R2180

1

2

R2181

1

2

R2172

1 2

R2110

1

2

R2150

1

2

C2171

1

2

C2173

1

2

C2170

1

2

C2172

1

2

U1400

K13

AE7

M22

C17 D17

C18

A12

C12

B12

D12

L26

L24

E15

K17

L17

A15

K15

G15

J14

J15

F15

L15

B20

G19

E19

F19

J19

J18

L13

M25

M24

L20

M20

M21

J16

K16

AE18

AE17

L22

E20

C16

D20

D16

C20

C19

J17

G17

H17

M23

L19

G21

K19

F21

D13

C14

C15

B14

C13

B18

K22

C11

B11

A16

A19

B16

B19

R2147

1

2

R2142

1

2

R2141

1

2

R2157

1

2

R2156

1

2

R2155

1

2

R2151

1

2

R2154

2

1

R2143

1

2

R2140

1

2

42

24

34

24

19

29

24

21

31

59

65

90

26

21

90

65

90

18

28

43

90

22

8

21

8

21

23

21

90

24

22

8

21

8

21

8

21

GND

GND161

GND165

GND166

GND164

GND163

GND162

GND167

GND168

GND171

GND170

GND169

GND172

GND173

GND176

GND175

GND174

GND177

GND178

GND181

GND180

GND179

GND182

GND183

GND184

GND187

GND186

GND185

GND188

GND189

GND192

GND191

GND190

GND193

GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206

GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213

GND214

GND217

GND216

GND215

GND218

GND219

GND222

GND221

GND220

GND223

GND224

GND225

GND228

GND227

GND226

GND229

GND230

GND233

GND232

GND231

GND234

GND235

GND238

GND237

GND236

GND239

GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331

GND332

GND330

GND329

GND328

GND326

GND327

GND325

GND324

GND323

GND321

GND322

GND320

GND319

GND318

GND316

GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305

GND306

GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285

GND286

GND284

GND283

GND282

GND280

GND281

GND279

GND278

GND277

GND275

GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264

GND265

GND266

GND263

GND262

GND259

GND260

GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPU CLK

+VDD_COR E42

+3.3V_DU AL_USB2

+VTT_CPU 17

+VTT_CPU 16

+VTT_CPU 15

+VTT_CPU 14

+VTT_CPU 13

+VTT_CPU 12

+VTT_CPU 11

+VTT_CPU 10

+VTT_CPU 1

+VDD_COR E7

+VDD_COR E1

+VDD_COR E2

+VDD_COR E3

+VDD_COR E4

+VDD_COR E5

+VDD_COR E6

+VDD_COR E13

+VDD_COR E14

+VDD_COR E15

+VDD_COR E16

+VDD_COR E17

+VDD_COR E18

+VDD_COR E19

+VDD_COR E21

+VDD_COR E22

+VDD_COR E23

+VDD_COR E24

+VDD_COR E25

+VDD_COR E26

+VDD_COR E27

+VDD_COR E28

+VDD_COR E29

+VDD_COR E30

+VDD_COR E32

+VDD_COR E33

+VDD_COR E34

+VDD_COR E35

+VDD_COR E36

+VDD_COR E37

+VDD_COR E39

+VDD_COR E40

+VDD_COR E41

+VDD_COR E47

+VDD_COR E48

+VDD_COR E49

+VDD_COR E50

+VDD_COR E51

+VDD_COR E52

+VDD_COR E53

+VDD_COR E54

+VTT_CPU 51

+VTT_CPU 50

+VTT_CPU 47

+VTT_CPU 46

+VTT_CPU 45

+VTT_CPU 43

+VTT_CPU 42

+VTT_CPU 41

+VTT_CPU 40

+VTT_CPU 39

+VTT_CPU 38

+VTT_CPU 37

+VTT_CPU 36

+VTT_CPU 35

+VTT_CPU 34

+VTT_CPU 32

+VTT_CPU 31

+VTT_CPU 30

+VTT_CPU 29

+VTT_CPU 28

+VTT_CPU 26

+VTT_CPU 25

+VTT_CPU 24

+VTT_CPU 23

+VTT_CPU 22

+VTT_CPU 21

+VTT_CPU 20

+VTT_CPU 19

+VTT_CPU 18

+VTT_CPU 9

+VTT_CPU 8

+VTT_CPU 7

+VTT_CPU 6

+VTT_CPU 5

+VTT_CPU 4

+VTT_CPU 3

+VDD_COR E38

+VTT_CPU 33

+VTT_CPU 27

+VDD_COR E55

+VDD_COR E56

+VDD_COR E57

+VDD_COR E58

+VDD_COR E59

+VDD_COR E60

+VDD_COR E61

+VDD_COR E62

+VDD_COR E63

+VDD_COR E64

+VDD_COR E65

+VDD_COR E66

+VDD_COR E67

+VDD_COR E68

+VDD_COR E69

+VDD_COR E70

+VDD_COR E71

+VDD_COR E72

+VDD_COR E73

+VDD_COR E74

+VDD_COR E75

+VDD_COR E76

+VDD_COR E77

+VDD_COR E78

+VDD_COR E79

+VDD_COR E80

+VDD_COR E81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DU AL1

+3.3V_DU AL2

+3.3V_DU AL3

+3.3V_DU AL4

+3.3V_DU AL_USB1

+3.3V_DU AL_USB3

+3.3V_DU AL_USB4

+VDD_AUX C1

+VDD_AUX C3

+VDD_AUX C2

+VDD_COR E43

+VTT_CPU 2

+VDD_COR E46

+VDD_COR E45

+VDD_COR E44

+VTT_CPU 52

+VDD_COR E31

+VTT_CPU 49

+VTT_CPU 48

+VTT_CPU 44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_COR E20

+VDD_COR E12

+VDD_COR E11

+VDD_COR E10

+VDD_COR E9

+VDD_COR E8

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

105 mA (A01)

43 mA

1139 m A

250 mA

16996 mA (A0 1, 1.0V )

23065 mA (A0 1, 1.2V )

80 uA (S0)

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

10 uA (G3)

16 mA

266 mA (A01)

450 mA (A01)

1182 m A (A01 )

BGA

OMIT

MCP79- TOPO-B

(11 OF 1 1) (10 OF 1 1)

BGA

MCP79- TOPO-B

OMIT

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=T 18_MLB

051-7546

A.0.0

9622

MCP Power & Ground

=PP1V0 5_S0_M CP_FSB

=PPVCO RE_S0_ MCP

PP3V3_ G3_RTC

=PP3V3 _S0_MC P

=PP1V0 5_S5_M CP_VDD_ AUXC

=PP3V3 _S5_MC P

U1400

AH26

AH33

AH34

AH37

AH38

AJ39

AJ8

AK10

AK33

AK34

AK37

AK4

AK40

AL36

AL40

AL5

AM10

AM16

AM18

AM20

AM22

AM24

AM26

AM30

AM34

AM35

AM37

AM38

AM5

AM6

AM7

AM9

AP26

AN28

AN30

AN39

AN4

Y7

AP10

AU26

AP14

AU14

AP28

AP32

AP34

AP36

AP37

AP4

AP40

AP7

AW23

AR28

AR32

AR40

AT10

AR12

AT13

AT29

AT33

AT6

AT7

AT9

AY21

AY22

L12

AU12

AU28

AP33

AU32

AR30

AU36

AU38

AU4

G28

F20

AV28

AV32

AV36

AV4

AV7

AW11

G20

AR43

AW43

AY10

AV12

AY30

AY33

AY34

AY37

AY38

AY41

AV40

BA1

BA4

AW31

AY6

L35

BC33

BC37

BC41

AY14

BC5

C2

D10

D14

D15

D18

D19

D22

D23

D26

D30

D37

D6

E13

E17

E21

E25

E29

E33

F12

F16

F32

F8

G10

G12

G14

G16

BC12

G22

G24

AW20

G34

G4

G43

G6

G8

H11

H15

AW35

H23

AN8

G40

J12

J8

K10

K12

K18

K26

K37

K4

K40

K8

AU1

L40

L43

L5

M10

M34

M35

M37

Y28

Y33

Y34

Y35

Y37

Y38

AB17

AB16

AN26

AD7

M11

AA4

AB19

AY13

P11

Y6

T11

V11

Y11

AH16

T22

U1400

AD10

AE8

AB10

AD9

Y10

AB11

AA8

Y9

G18

H19

J20

K20

G26

H27

J28

K28

A20

T21

U21

V21

AA25

AA26

AA27

AA28

AC16

AC17

AC18

AC19

AC20

AC21

AA17

AC23

AC24

AC25

AC26

AC27

AC28

AD21

AD23

W27

V25

AA18

U25

AE19

AE21

AE23

AE25

AE26

AE27

AE28

AF10

AF11

AA19

AH12

AF2

AF21

AF23

AF25

AF3

AF4

AF7

AH23

AF9

AA20

AG10

AG11

AG12

AG21

AG23

AG25

AG3

AG4

AA21

AG6

AG7

AG5

AG8

AG9

AH1

AH10

AH11

W26

AH2

AA23

W28

AH25

Y21

AH21

AH3

AH4

AH5

AH6

AH7

AH9

AA24

W21

W23

Y23

W25

AF12

AA16

R32

P31

AF32

AE32

AH32

AJ32

AK31

AK32

AD32

AL31

AB32

AC32

B41

B42

C40

C41

C42

D39

D40

D41

E38

E39

E40

F37

F38

F39

G36

G37

G38

H35

H37

J34

J35

J36

K33

K34

K35

L32

L33

L34

M31

M32

M33

N31

N32

P32

Y32

AA32

T32

U32

V32

W32

AG32

24 14 46

24

9

24

26

21

24

8 8

21

8

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

3.3V Interface Pull-ups

These intern al pull -ups a re mis sing i n Revs A01 & A01P.

MCP_A0 1&MCP_ A01P&MC P_A01Q

402

MF-LF1/16W

5%

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

402

MF-LF1/16W

5%

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

5%

1/16W MF-LF

402

10K

5%

1/16W MF-LF

402

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

5%

1/16W MF-LF

402

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

5%

1/16W MF-LF

402

10K

13 19

17 31 32

6

13 21

6

13 21

21 26

21

21 42

MCP_A0 1&MCP_ A01P&MC P_A01Q

5%

1/16W MF-LF

402

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

402

MF-LF1/16W

5%

10K

MCP_A0 1&MCP_ A01P&MC P_A01Q

10K

402

MF-LF1/16W

5%

MCP_A0 1&MCP_ A01P&MC P_A01Q

5%

1/16W MF-LF

402

10K

SYNC_D ATE=03 /31/200 8

SYNC_M ASTER= T18_MLB

MCP79 A01 Silicon Support

051-7546

A.0.0

9623

PM_LAT RIGGER _L

PM_SYS RST_DE BOUNCE_ L

SMC_WA KE_SCI _L

PM_BAT LOW_L

PM_PWR BTN_L

SMC_RU NTIME_ SCI_L

JTAG_M CP_TMS

JTAG_M CP_TDI

PCIE_W AKE_L

MAKE_BAS E=TRUE

MCP_LI D_L

TP_MCP _LID_L

=PP3V3 _S5_MC P_A01

R2412

1 2

R2411

1 2

R2410

1 2

R2403

1 2

R2402

1 2

R2401

1 2

R2400

1 2

R2404

1 2

R2413

1 2

R2405

1 2

44

8

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

Apple: 4x 4. 7uF 040 2, 4x 1uF 04 02, 6x 0.1uF 0402 ( 23.4 u F)

NV: 1x 10uF 0805, 2 x 4.7u F 0402 , 3x 1 uF 0402 , 9x 0 .1uF 0 402 (2 3.3 uF )

5 mA ( A01)

MCP SA TA (DV DD) Pow er

NV: 1x 4.7uF 0603, 4x 0.1 uF 040 2 (5.1 uF) Apple: 4x 2. 2uF 040 2 (8.8 uF)

1182 m A (A01 )

7 mA ( A01)

19 mA (A01)

333 mA (A01)

4771 m A (A01 , DDR3)

MCP Co re Pow er

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF)

MCP 3. 3V Pow er

MCP Me mory P ower

MCP FS B (VTT ) Power

Apple: 1x 2. 2uF 040 2 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF)

NV: 1x 10uF 0805, 1 x 4.7u F 0402 , 2x 0 .1uF 04 02 (14 .9 uF) Apple: 7x 2. 2uF 040 2 (15. 4 uF)

Apple: 5x 2. 2uF 040 2 (11 uF)

Apple: 1x 2. 2uF 040 2 (2.2 uF)

MCP 1. 05V AU X Power

5 mA ( A01)

MCP 3. 3V/1.5 V HDA P ower

266 mA (A01)

MCP 3. 3V AUX /USB Po wer

Apple: 1x 2. 2uF 040 2 (2.2 uF)

MCP79 Ethernet VRef

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF)

MCP 3. 3V Eth ernet P ower

MCP 1. 05V RM GT Powe r

(No IG vs. E G data)

23065 mA (A0 1, 1.2V ) 16996 mA (A0 1, 1.0V )

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF)

Curren t numb ers fro m emai l Poon acha K ongetir a prov ided 1 1/30/2 007 4: 04pm (n o offi cial d ocumen t numbe r).

MCP PC IE (DV DD) Pow er

105 mA (A01) 131 mA (A01)

83 mA (A01)

84 mA (A01)

87 mA (A01)

37 mA (A01)

206 mA (A01)

127 mA (A01)

43 mA (A01)57 mA (A 01)

450 mA (A01)

19 mA (A01)

562 mA (A01)

NV: 1x 10uF 0805, 1 x 4.7u F 0402 , 2x 1 uF 0402 , 2x 0 .1uF 0 402 (1 6.9 uF )

NV: 1x 10uF 0805, 1 x 4.7u F 0402 , 2x 0 .1uF 04 02 (14 .9 uF) Apple: 2x 2. 2uF 040 2 (4.4 uF)

270 mA (A01)

402

X5R

20%

4.7UF

4V

402

X5R

4V

4.7UF

20%

402

X5R

4V

20%

4.7UF

402

X5R

20%

4.7UF

4V

6.3V

2.2UF

20%

402-LF

CERM

402

X5R

20%

4V

4.7UF

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

402

20%

CERM

0.1UF

10V

402

20%

CERM

0.1UF

10V

402

20%

CERM

0.1UF

10V

402

20%

CERM

0.1UF

10V

402

20%

CERM

0.1UF

10V

402

20%

CERM

0.1UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

6.3V

2.2UF

20%

CERM 402-LF

20%

2.2UF

6.3V

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

402

X5R

20%

4V

4.7UF

CERM 402-LF

CERM

402-LF

20%

2.2UF

6.3V

402

X5R

20%

4.7UF

4V

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

402-LF

CERMCERM

402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

CERM

20%

0.1UF

10V

402

0.1UF

CERM

20%

10V

402

20%

CERM

0.1UF

402

X5R

4V

4.7UF

20%

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

402

X5R

4V

20%

4.7UF

30-OHM -5A

0603

30-OHM -5A

0402

30-OHM -1.7A

0402

30-OHM -1.7A

0402

30-OHM -1.7A

0402

30-OHM -1.7A

0402

402

20%

4V

4.7UF

402

X5R

20%

4V

4.7UF

10V

402

0.1uF

20%

CERM

10V

402

0.1uF

20%

CERM

CERM 402-LF

20%

2.2UF

6.3V

10V

402

20%

0.1UF

CERM

10V

402

20%

0.1UF

CERM

402

X5R

4V

4.7UF

20%

0402

30-OHM -1.7A

402

MF-LF

1%

1/16W

1.47K

10V

402

20%

CERM

0.1UF

402

1.47K

1/16W

1%

MF-LF

18

10V

402

0.1uF

20%

CERM

10V

402

CERM

20%

0.1uF

10V

402

20%

CERM

0.1uF

10V

402

20%

0.1UF

CERM

10V

402

0.1UF

CERM

20%

10V

402

0.1UF

CERM

20%

10V

402

0.1UF

20%

CERM

10V

402

0.1uF

20%

CERM

402

X5R

4V

4.7uF

20%

402

X5R

20%

4V

4.7UF

96

051-7546

A.0.0

24

MCP Standard Decoupling

SYNC_MA STER=T 18_MLB

SYNC_DA TE=06/ 18/2008

VOLTAGE= 1.05V

PP1V05 _S0_MC P_PLL_N V

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .4 MM

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .4 MM

VOLTAGE= 1.05V

PP1V05 _S0_MC P_PLL_C ORE

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM

PP1V05 _S0_MC P_SATA_ AVDD

VOLTAGE= 1.05V

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM

PP1V05 _S0_MC P_PEX_A VDD

VOLTAGE= 1.05V

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM VOLTAGE= 3.3V

PP3V3_ S0_MCP _PLL_US B

VOLTAGE= 1.05V

MIN_NECK _WIDTH=0 .2 MM

MIN_LINE _WIDTH=0 .4 MM

PP1V05 _S0_MC P_PLL_P EX

PP1V05 _S0_MC P_PLL_S ATA

VOLTAGE= 1.05V

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM

MIN_NECK _WIDTH=0 .2 MM VOLTAGE= 1.05V

MIN_LINE _WIDTH=0 .4 MM

PP1V05 _ENET_ MCP_PLL _MAC

=PP1V0 5_ENET _MCP_PL L_MAC

=PP3V3 _ENET_ MCP_RMG T

MCP_MI I_VREF

=PP3V3 _S0_MC P

=PP3V3 R1V5_S 0_MCP_H DA

=PP3V3 _S5_MC P

=PP1V0 5_S0_M CP_AVDD _UF

=PP1V0 5_S0_M CP_FSB

=PP1V8 R1V5_S 0_MCP_M EM

=PP1V0 5_S5_M CP_VDD_ AUXC

=PP1V0 5_ENET _MCP_RM GT

=PP3V3 _S0_MC P_PLL_U F

=PPVCO RE_S0_ MCP

=PP3V3 _ENET_ MCP_RMG T

=PP1V0 5_S0_M CP_SATA _DVDD

=PP1V0 5_S0_M CP_PEX_ DVDD

=PP1V0 5_S0_M CP_PLL_ UF

6.3V

20%

VOLTAGE= 1.05V

20%

CERM

6.3V

402-LF

2.2UF

X5R

6.3V

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

PP1V05 _S0_MC P_PLL_F SB

0603

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM

402-HF

MF

1/6W

0.2

1%

C2503

1

2

C2582

1

2

C2588

1

2

C2584

1

2

C2586

1

2

C2555

1

2

C2502

1

2

C2507

1

2

C2506

1

2

C2505

1

2

C2504

1

2

C2511

1

2

C2510

1

2

C2509

1

2

C2508

1

2

C2513

1

2

C2512

1

2

C2536

1

2

C2535

1

2

C2534

1

2

C2533

1

2

C2532

1

2

C2531

1

2

C2530

1

2

C2517

1

2

C2516

1

2

C2515

1

2

C2572

1

2

C2571

1

2

C2520

1

2

C2570

1

2

C2574

1

2

C2573

1

2

C2576

1

2

C2575

1

2

C2553

1

2

C2552

1

2

C2551

1

2

C2550

1

2

C2549

1

2

C2548

1

2

C2547

1

2

C2546

1

2

C2545

1

2

C2544

1

2

C2543

1

2

C2542

1

2

C2541

1

2

C2540

1

2

C2562

1

2

C2564

1

2

C2580

1

2

L2570

1 2

L2575

1 2

L2582

1 2

L2584

1 2

L2588

1 2

L2586

1 2

L2555

1 2

C2500

1

2

C2501

1

2

C2526

1

2

C2525

1

2

C2560

1

2

C2589

1

2

C2590

1

2

C2595

1

2

L2595

1 2

R2590

1

2

C2591

1

2

R2591

1

2

C2521

1

2

C2518

1

2

C2519

1

2

C2581

1

2

C2583

1

2

C2585

1

2

C2587

1

2

C2596

1

2

C2529

1

2

C2528

1

2

R2580

1 2

22

24

22

14

46

24

18

21

22

9

16

22 18

22

18

21

16

8

20

17

20

14

18

8

8 8

8

8 8

8

A2

A1

SCL

A0

VCC

SDA

WP

GND

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

206 mA (A01)

NV: 1x 4.7uF 0603, 2x 0.1 uF 040 2 (4.9 uF)

206 mA (A01)

Apple: 2x 2. 2uF 040 2 (4.4 uF)

16 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF) Apple: ???

HDCP ROM

16 mA (A01)

190 mA (A01, 1.8V)

WF: Op en que stion o n whic h pack ge opt ion(s) nVidia can s upport .

Curren t numb ers fro m emai l Xiao wei Li n provi ded 11 /12/20 07 3:2 2pm (n o offic ial do cument numbe r).

WF: Ch ecklis t says 0-ohm resist or pla ceholde r for ferrit e bead .

Apple: 1x 2. 2uF 040 2 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1 uF 040 2 (4.8 uF)

WF: Ch ecklis t says 0-ohm resist or pla ceholde r for ferrit e bead .

95 mA (A01)

6.3V CERM 402-LF

NO STU FF

2.2UF

20%

NO STU FF

30-OHM -1.7A

0402

NO STU FF

20%

0.1UF

402

10V

NO STU FF

402

1K

1% 1/16W MF-LF

0.1UF

20%

402

CERM

NO STU FF

10V

20%

4.7UF

4V

402

X5R

CERM

4.7UF

6.3V

20%

603

30-OHM -1.7A

0402

20%

402

CERM

10V

0.1uF

OMIT

SOIC

AT24C08

402

10V

0.1UF

20%

CERM

10K

MF-LF

5%

1/16W

402

45

402

MF-LF

1/16W

5%

0

MF-LF

1K

1% 1/16W

CERM 402-LF

20%

2.2UF

6.3V

SYNC_DA TE=06/ 18/2008

SYNC_MA STER=A MASON_M 98_MLB

MCP Graphics Support

25 9 6

A.0.0

051-7546

TP_MCP _RGB_R ED

TP_MCP _RGB_G REEN

CRT_IG _B_COM P_PB

MCP_CL K27M_X TALIN

MCP_CL K27M_X TALOUT

PP3V3_ S0_MCP _DAC

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM VOLTAGE= 3.3V

MCP_IF PAB_VP ROBE

MCP_TV _DAC_R SET

MCP_TV _DAC_V REF

MAKE_BASE=T RUE

NC_MCP _TV_DA C_VREF

MAKE_BASE=T RUE

NC_MCP _CLK27 M_XTALI N

MAKE_BASE=T RUE

NC_MCP _CLK27 M_XTALO UT

NC_MCP _TV_DA C_RSET

MAKE_BASE=T RUE

TP_MCP _RGB_D AC_VREF

=PP3V3 _S0_MC P_DAC_U F

MCP_HD MI_VPR OBE

HDCPRO M_WP

VOLTAGE= 3.3V

MIN_LINE _WIDTH=0 .4 MM MIN_NECK _WIDTH=0 .2 MM

PP3V3_ S0_MCP _VPLL

MAKE_BASE=T RUE

NC_MCP _RGB_B LUE

MAKE_BASE=T RUE

NC_MCP _RGB_H SYNCTP_MCP _RGB_H SYNC

TP_MCP _RGB_V SYNC

TP_MCP _RGB_B LUE

MAKE_BASE=T RUE

NC_MCP _RGB_G REEN

MAKE_BASE=T RUE

NC_MCP _RGB_R ED

MAKE_BASE=T RUE

NC_MCP _RGB_V SYNC

CRT_IG _R_C_P R

MAKE_BASE=T RUE

NC_CRT _IG_R_ C_PR

TP_MCP _RGB_D AC_RSET

MAKE_BASE=T RUE

NC_MCP _RGB_D AC_VREF

MAKE_BASE=T RUE

NC_CRT _IG_VS YNC

CRT_IG _VSYNC

MAKE_BASE=T RUE

NC_CRT _IG_HS YNC

CRT_IG _HSYNC

MAKE_BASE=T RUE

NC_CRT _IG_B_ COMP_PB

MAKE_BASE=T RUE

NC_CRT _IG_G_ Y_Y

CRT_IG _G_Y_Y

MAKE_BASE=T RUE

NC_MCP _RGB_D AC_RSET

=PP3V3 R1V8_S 0_MCP_I FP_VDD

=PP1V0 5_S0_M CP_HDMI _VDD

=PP3V3 _S0_MC P_VPLL_ UF

=I2C_H DCPROM _SDA =I2C_H DCPROM _SCL

=PP3V3 _S0_HD CPROM

MCP_IF PAB_RS ET

CERM

402

MCP_HD MI_RSE T

CERM

20%

2.2UF

402-LF

6.3V

R2620

1

2

C2610

1

2

C2650

1

2

L2650

1 2

C2620

1

2

R2630

1

2

C2630

1

2

C2615

1

2

C2640

1

2

L2640

1 2

C2641

1

2

C2616

1

2

U2695

1

2

3

4

6

5

8

7

C2690

1

2

R2690

1

2

R2651

1

2

89

18

89 89

18

8

18

8

18

8

18

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

Y

B

A

VIN

GND

VOUTEN

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

but re sults in MCP7 9 ROMS IP seq uence happeni ng aft er CPU power s up.

NOTE: If CPU _VLD de assert s duri ng S0 MCP79 w ill ta ke sys tem to S5 im mediate ly.

CPUVDD _EN (w hich is 40-10 0ms af ter PS _PWRGD assert ion).

Reset Button

10K pu ll-up to 3.3V S0 in side M CP

LPC Reset (Unbuffered)

Platform Reset Connections

PCIE Reset (Unbuffered)

SMC 99 ms del ay from ALL_S YS_PWR GD to IMVP_VR _ON pl us IMV P6 del ay for

MCP S0 PWRGD & CPU_VLD

VR_PWR GOOD_D ELAY sh ould g uarant ee CPU _VLD do es not go hi gh bef ore

MCPSEQ _SMC r epresen ts MCP 79 'ML B' pow er sequ encing conne ctions ,

MCPSEQ _MIX i s cross betwe en MLB and i nternal power seque ncing, which result s in e arlier ROMSIP and M CP FSB I/O in terfac e init ializa tion.

RTC Crystal

RTC Power Sources

MCP 25MHz Crystal

10 13 21 23

5%

CERM

402

12pF

50V

5%

50V

CERM

402

12pF

402

1/16W

0

5%

MF-LF

1/16W MF-LF

5%

402

10M

NO STU FF

19 83 90

402

0

5%

MF-LF

1/16W

XDP

PLACEMEN T_NOTE=P lace clo se to U1 400

33

MF-LF

5%

1/16W

402

33

5% 1/16W MF-LF

PLACEMEN T_NOTE=P lace clo se to U1 400

402

MF-LF

402

1/16W

5%

0

402

MF-LF

1/16W

5%

0

OMIT

SILK_PART=FP SYS RESET

44

42

21

9

17

PLACEMEN T_NOTE=P lace clo se to U1 400

33

5%

MF-LF

1/16W

402

5%

33

MF-LF

1/16W

PLACEMEN T_NOTE=P lace clo se to U1 400

402

19 90

12pF

402

CERM

5%

50V

12pF

5%

CERM

402

CRITIC AL

25.000 0M

SM-3.2X2 .5MM

402

5%

MF-LF

1/16W

0

1M

5%

1/16W

402

MF-LF

NO STU FF

21

42 90

PLACEMEN T_NOTE=P lace clo se to U1 400

402

MF-LF

5% 1/16W

22

21 90

1/16W

5%

MF-LF

33

402

10V X5R

10%

1UF

NO STU FF

36

MF-LF

1/16W

5%

0

402

9

33

402

5% 1/16W MF-LF

19

42

44 90

42 90

CRITIC AL

32.768 K

7X1.5X1.4 -SM

0

5% 1/16W MF-LF

402

27

402

MF-LF

1/16W

5%

0

85

402

MF-LF

1/16W

5%

0

32

31

1/16W

0

402

5%

MF-LF

33

MF-LF

402

1/16W

5%

PLACEMEN T_NOTE=P lace clo se to U1 400

83

21

62

42 68

402

0

1/16W

5%

MF-LF

MCPSEQ _MIX

20%

MCPSEQ _SMC

10V CERM 402

0.1UF

PLACEMEN T_NOTE=P lace clo se to U1 400

402

0

1/16W MF-LF

5%

MCPSEQ _SMC

21

MF-LF

5%

1/16W

0

402

MCPSEQ _SMC

21

MF-LF

5%

1/16W

0

402

MCPSEQ _MIX

MCPSEQ _SMC

TC7SZ08A FEAPE

SOT665

1UF

10% 10V X5R 402

TSOT-23- 5

MIC5232 -2.8YD 5

10

5%

402

1/16W MF-LF

1.0M

5%

NO STU FF

1/10W

603

MF-LF

6.3V

10%

402

CERM

1UF

2%

0.08F

XHHG SM

3.3V

100

5% 1/16W MF-LF 402

051-7546

26

A.0.0

96

SB Misc

SYNC_MA STER=T 18_MLB

SYNC_DA TE=12/ 17/2007

PCIE_R ESET_L

VR_PWR GOOD_D ELAY

S0_AND _IMVP_ PGOOD

ALL_SY S_PWRG D

XDP_DB RESET_ L

PM_SYS RST_DE BOUNCE_ L

PM_SYS RST_L

LPC_RE SET_L

DEBUG_ RESET_ L

SMC_LR ESET_L

LPC_CL K33M_L PCPLUS

LPC_CL K33M_S MC

PM_CLK 32K_SU SCLK

LPC_CL K33M_G MUX

MEM_VT T_EN

MINI_R ESET_L

EXCARD _RESET _L

BKLT_P LT_RST_ L

FW_RES ET_L

PCA955 7D_RES ET_L

LPC_CL K33M_S MC_R

MEM_VT T_EN_R

PM_CLK 32K_SU SCLK_R

MAKE_BAS E=TRUE

GMUX_P CIE_RE SET_L

=GMUX_ PCIE_R ESET_L

MCP_CP UVDD_E N

MCP_CP U_VLD

MCP_PS _PWRGD

=PP3V3 _S5_MC PPWRGD

PP3V3_ G3_SUPE RCAP

RTC_DI SCHARG E_R

MCP_CL K25M_X TALOUT_ R

PP3V3_ G3_RTC

MIN_NECK _WIDTH=0 .2 mm

MIN_LINE _WIDTH=0 .3 mm

VOLTAGE= 3.3V

=PP3V3 _S5_RT C_D

RTC_CL K32K_X TALOUT_ R

RTC_CL K32K_X TALIN

MCP_CL K25M_X TALIN

MCP_CL K25M_X TALOUT

RTC_CL K32K_X TALOUT

C2810

1 2

C2811

1 2

R2810

1 2

R2811

1

2

R2896

1 2

R2883

1 2

R2881

1 2

R2890

1 2

R2897

1

2

R2826

1 2

R2825

1 2

C2815

1 2

C2816

1 2

Y2815

2 4

1 3

R2815

1 2

R2816

1

2

R2829

1 2

R2899

1 2

C2899

1

2

R2892

1 2

R2870

1 2

Y2810

1 4

R2891

1 2

R2893

1 2

R2895

1 2

R2894

1 2

R2827

1 2

R2851

1 2

C2850

1

2

R2850

1 2

R2853

1 2

R2852

1 2

U2850

C2802

1

2

U2801

3

2

4

1

5

R2801

1

2

R2802

12

C2801

1

2

C2800

1

2

R2800

1

2

22 8 21

8

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0

A1 A2

SCL

SDA

P0

P1 P2

P5

P6

P7

P3

P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

DESCRI PTION

REFERE NCE DE S

BOM OP TION

QTY

PART N UMBER

CRITIC AL

Min DAC code 0x00 0x00 0x0 0 0x00 0x00 0 x00

Max sin k I -3.75 mA - 3.75 mA -3.7 5 mA -3.75 mA -0.91 m A -59 .04 mA

Nominal Vref 0.75 V 0.75 V 0.7 5 V 0.75 V 0.70 V 1 .248 V

Max Vre f 1.250 V 1.250 V 1.2 50 V 1.25 0 V 1.044 V 1 .426 V

(i.e. not simultaneously) due to cur rent limitation of TPS51116 regulator.

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

MEM B V REF DQMEM A V REF DQ

(per DA C LSB)

Signal a liases r equired by this page:

NO_VREFM RGN

VREFMRGN

- =I2C_P CA9557D_ SDA

- =I2C_P CA9557D_ SCL

Requir ed zer o ohm r esisto rs whe n no V REF mar gining circu it stu ffed

Power al iases re quired b y this p age:

ADDR=0 x30(WR )/0x31( RD)

Place close to J310 0.1

ADDR=0 x98(WR )/0x99( RD)

- =PP3V3 _S3_VREF MRGN

- =PPVTT _S3_DDR_ BUF

10mA m ax loa d

- =I2C_V REFDACS_ SDA

Page Notes

Place close to U100 0.AD26

Place close to U850 0, U85 50

BOM opti ons prov ided by this pag e:

- =I2C_V REFDACS_ SCL

- =PP3V3 _S5_VREF MRGN

CPU FSB VREF

FRAME B UFFER VREF

MEM B V REF CA

Place close to J320 0.1

Vref St epping 6.5 m V 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1 .5 mV

Min Vre f 0.375 V 0.375 V 0.3 75 V 0.37 5 V 0.091 V 1 .042 V

Max sou rce I 5 mA 5 mA 5 mA 5 m A 0.52 m A 51 .15 mA

Max DAC code 0x87 0x87 0x8 7 0x87 0x55 0 xFF

DAC cha nnel A B A B C D

MEM A V REF CA

Place close to J310 0.126

Place close to J320 0.126

Place close to U840 0, U84 50

9

1/16W MF-LF

VREFMRGN

1%

49.9

402

10 87

VREFMR GN

0.1UF

20% 10V

402

CERM

100

402

1%

VREFMRGN

1/16W MF-LF

5%

VREFMRGN

MF-LF

402

1/16W

100K

VREFMRGN

1%

200

1/16W MF-LF

402

MF-LF

1/16W

5%

VREFMRGN

402

100K

9

MF-LF

1/16W

402

49.9

1%

VREFMRGN

UCSP

MAX4253

VREFMRGN

UCSP

VREFMRGN

MAX4253

UCSP

VREFMRGN

MAX4253

UCSP

MAX4253

VREFMRGN

UCSP

VREFMRGN

MAX4253

UCSP

MAX4253

VREFMRGN

1%

200

1/16W MF-LF

402

1/16W

402

200

1%

MF-LF

VREFMRGN

1%

200

1/16W MF-LF

402

VREFMRGN

5%

100K

1/16W MF-LF

402

VREFMRGN

100K

1/16W

5%

402

MF-LF

VREFMRGN

402

100

1% 1/16W MF-LF

VREFMRGN

MF-LF

402

1% 1/16W

100

VREFMRGN

402

MF-LF

1/16W

1%

100

VREFMRGN

MF-LF

VREFMRGN

402

1/16W

100K

5%

PCA9557

VREFMR GN

QFN

VREFMR GN

402

0.1UF

20%

CERM

10V

402

100

MF-LF

1% 1/16W

VREFMRGN

5%

402

1/16W

100K

MF-LF

VREFMRGN

26

45

DAC557 4

MSOP

VREFMR GN

45

10V

402

VREFMR GN

0.1UF

CERM

20%

2.2UF

CERM

6.3V

20%

VREFMR GN

402-LF

VREFMR GN

20%

CERM 402

10V

0.1UF

CERM

0.1UF

VREFMR GN

402

20% 10V

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MA STER=D DR

051-7546

A.0.0

9627

SYNC_DA TE=07/ 22/2008

1 R2909 CRITIC AL

NO_VRE FMRGN

116S00 04

RES,MTL FILM,0,5 %,0402,S M,LF

CRITIC AL1 R2911

NO_VRE FMRGN

116S00 04

RES,MTL FILM,0,5 %,0402,S M,LF

R2903 CRITIC AL

NO_VRE FMRGN

1116S0004

RES,MTL FILM,0,5 %,0402,S M,LF

CRITIC AL1 R2905

NO_VRE FMRGN

116S00 04

RES,MTL FILM,0,5 %,0402,S M,LF

=PPVTT_S 3_DDR_BU F

MIN_NECK_WI DTH=0.2 mm

MIN_LINE_WI DTH=0.3 mm

PP0V75_ S3_MEM_V REFDQ_A

VREFMRGN_ CA_SODIMMB _BUF

VREFMRGN_ CPUFSB_EN

VREFMRGN_ CPUFSB_BUF

VREFMRGN_ FRAMEBUF_E N

VREFMRGN_ FRAMEBUF_B UF

VREFMRGN_ FRAMEBUF

VREFMRGN_ CA_SODIMMB _EN

VREFMRGN_ CA_SODIMM

VREFMRGN_ DQ_SODIMMA _EN

VREFMRGN_ DQ_SODIMMA _BUF

VREFMRGN_ CA_SODIMMA _EN

VREFMRGN_ CA_SODIMMA _BUF

VREFMRGN_ DQ_SODIMMB _EN

VREFMRGN_ CA_SODIMMA _EN

VREFMRGN_ FRAMEBUF_E N

VREFMRGN_ DQ_SODIMMB _EN

VREFMRGN_ CPUFSB_EN

=I2C_VR EFDACS_S DA

PCA9557D_ RESET_L

VREFMRGN_ DQ_SODIMMA _EN

=I2C_VR EFDACS_S CL

VREFMRGN_ CA_SODIMMB _EN

CPU_GTL REF

GPU_FB_B _VREF_DI V

GPU_FB_A _VREF_DI V

=I2C_PC A9557D_S DA

=I2C_PC A9557D_S CL

=PP3V3_S 3_VREFMR GN

VREFMRGN_ CPUFSB

VREFMRGN_ DQ_SODIMM

VREFMRGN_ DQ_SODIMMB _BUF

PP0V75_ S3_MEM_V REFCA_A

MIN_LINE_WI DTH=0.3 mm MIN_NECK_WI DTH=0.1 mm

MIN_LINE_WI DTH=0.3 mm MIN_NECK_WI DTH=0.2 mm

PP0V75_ S3_MEM_V REFDQ_B

MIN_LINE_WI DTH=0.3 mm

PP0V75_ S3_MEM_V REFCA_B

MIN_NECK_WI DTH=0.2 mm

U2901

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

C2903

1

2

C2902

1

2

R2902

1 2

R2901

1 2

R2904

1 2

R2906

1 2

R2910

1 2

R2907

1 2

C2904

1

2

R2912

1 2

R2908

1 2

U2900

9

10

3

6

7

8

1

2

4

5

C2901

1

2

C2900

1

2

C2905

1

2

R2916

1 2

R2914

1 2

R2913

1 2

R2903

1 2

R2915

1 2

R2917

1 2

U2902

C3

C2

C1

C4

B1

B4

U2903

A3

A2

A1

A4

B1

B4

U2902

A3

A2

A1

A4

B1

B4

U2903

C3

C2

C1

C4

B1

B4

U2904

A3

A2

A1

A4

B1

B4

U2904

C3

C2

C1

C4

B1

B4

R2905

1 2

R2909

1 2

R2911

1 2

64

8

28

27

8

28

29

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4*

DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS

DQ58

DQ59

DM7

VSS

DQ57

DQ56

DQ50

DQ51

VSS

DQS6*

DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS

DQ42

SDA

SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60

DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS

DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

CK0

A1

A3

VDD

A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS

DQ44

DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD

ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI

BIBI

BI

IN

BI

IN

BI

IN

BI

IN

BI

DQ16

DM3

DQ26

DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24

DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8

DQ9

DM0

DQ0

DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

OUT

BI

IN

BI

IN

BI

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

(NONE)

BOM options provided by this page:

- =PP1V5_S3 _MEM_A

- =I2C_SODI MMA_SCL

- =PP0V75_S 0_MEM_VTT_A

Power alias es required by this pag e:

- =I2C_SODI MMA_SDA

"Facto ry" (t op) sl ot

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

Signal alia ses required by this pa ge:

- =PPSPD_S0 _MEM_A (2.5 - 3.3V)

- =PP1V5_S0 _MEM_A

SPD ADDR= 0xA0(WR)/ 0xA1(RD)

Page Notes

516-0196

DDR3-SO DIMM-D UAL-M97 -3

F-RT-THB

15 88

0.1UF

CERM 402

20% 10V

6.3V CERM 402-LF

20%

2.2UF

15 88

29 30

15 88

DDR3-SO DIMM-D UAL-M97 -3

CRITIC AL

F-RT-THB

15 88

9

15 88

10V

20%

402

CERM

0.1UF

402-LF

20%

6.3V

2.2UF

CERM

15 88

21 29 42

45

15 88

10K

5%

402

1/16W MF-LF

10K

MF-LF

1/16W

5%

402

2.2UF

20%

CERM 402-LF

6.3V

10UF

20%

X5R

6.3V

603

6.3V

10UF

X5R 603

20%

CERM 402

10V

20%

0.1UF 0.1UF

402

CERM

10V

20%

CERM

0.1UF

20% 10V

402

CERM 402

0.1UF

10V

20%

10V

0.1UF

402

CERM

20%

0.1UF

20%

402

CERM

10V 10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

20%

402

CERM

0.1UF

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

SYNC_MASTER =DDR

SYNC_DATE=0 7/22/2008

DDR3 S O-DIMM Connec tor A

051-7546

A.0.0

9628

MEM_A_BA <2>

MEM_A_DQ <60>

MEM_A_DQ <58>

MEM_A_DQ <59>

MEM_A_SA <0>

=PP1V5 _S0_ME M_A

MEM_A_DQ <3>

MEM_A_DQ <2>

PP0V75_S 3_MEM_VR EFDQ_A

MEM_A_DQ <1>

MEM_A_DQ <0>

MEM_A_DM <0>

MEM_A_DQ <13>

MEM_A_DQ <9>

MEM_A_DQ S_N<1>

MEM_A_DQ S_P<1>

MEM_A_DQ <11>

MEM_A_DQ <14>

MEM_A_DQ <18>

MEM_A_DQ S_N<2>

MEM_A_DQ S_P<2>

MEM_A_DQ <23>

MEM_A_DQ <19>

MEM_A_DQ <30>

MEM_A_DQ <24>

MEM_A_DQ <5>

MEM_A_DQ S_N<0>

MEM_A_DQ S_P<0>

MEM_A_DQ <6>

MEM_A_DQ <7>

MEM_A_DQ <8>

MEM_A_DQ <12>

MEM_A_DM <1>

MEM_RESE T_L

MEM_A_DQ <15>

MEM_A_DQ <10>

MEM_A_DQ <21>

MEM_A_DQ <20>

MEM_A_DM <2>

MEM_A_DQ <17>

MEM_A_DQ <22>

MEM_A_DQ <29>

MEM_A_DQ <28>

MEM_A_DQ S_N<3>

MEM_A_DQ S_P<3>

MEM_A_DQ <26>

MEM_A_DQ <31>

MEM_A_DQ <4>

MEM_A_DM <3>

MEM_A_DQ <16>

=PPSPD_S 0_MEM_A

MEM_A_CK E<1>

MEM_A_A< 15>

MEM_A_A< 14>

MEM_A_A< 4>

MEM_A_A< 2>

MEM_A_CL K_P<1>

MEM_A_A< 0>

MEM_A_CL K_N<1>

MEM_A_RA S_L

MEM_A_OD T<0>

MEM_A_OD T<1>

PP0V75_S 3_MEM_VR EFCA_A

MEM_A_DQ <36>

MEM_A_DQ <37>

MEM_A_DM <4>

MEM_A_DQ <38>

MEM_A_DQ <39>

MEM_A_DQ <40>

MEM_A_DQ <47>

MEM_A_DQ S_N<5>

MEM_A_CK E<0>

MEM_A_A< 12>

MEM_A_A< 9>

MEM_A_A< 8>

MEM_A_A< 3>

MEM_A_A< 1>

MEM_A_CL K_P<0>

MEM_A_BA <0>

MEM_A_WE _L

MEM_A_CA S_L

MEM_A_A< 13>

MEM_A_CS _L<1>

MEM_A_DQ <33>

MEM_A_DQ <34>

MEM_A_DQ <44>

MEM_A_DQ <41>

MEM_A_DQ <46>

MEM_A_DQ S_P<5>

MEM_A_DQ <43>

MEM_A_DQ <48>

MEM_A_DQ <53>

MEM_A_DM <6>

MEM_A_DQ <50>

MEM_A_DQ <49>

MEM_A_DQ <56>

MEM_A_DQ <57>

MEM_A_DQ S_P<7>

MEM_A_DQ S_N<7>

MEM_A_DQ <63>

MEM_A_DQ <62>

MEM_EVEN T_L

=I2C_SOD IMMA_SCL

=I2C_SOD IMMA_SDA

MEM_A_DQ <45>

MEM_A_DM <5>

MEM_A_DQ <42>

MEM_A_DQ <52>

MEM_A_DQ <51>

MEM_A_DQ S_P<6>

MEM_A_DQ S_N<6>

MEM_A_DQ <54>

MEM_A_DQ <55>

MEM_A_DQ <61>

MEM_A_DM <7>

MEM_A_CL K_N<0>

MEM_A_DQ <35>

MEM_A_DQ S_P<4>

MEM_A_DQ S_N<4>

=PP0V75_ S0_MEM_V TT_A

MEM_A_SA <1>

MEM_A_A< 10>

MEM_A_DQ <32>

MEM_A_A< 5>

MEM_A_A< 11>

MEM_A_A< 7>

MEM_A_A< 6>

MEM_A_DQ <27>

MEM_A_DQ <25>

=PP1V5 _S3_ME M_A

MEM_A_CS _L<0>

MEM_A_BA <1>

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101

103

102

104

73 74

136

153

170

187

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

C3131

1

2

C3130

1

2

J3100

11

28

46

63

5

7

33

35

22

24

34

36

39

41

51

53

15

40

42

50

52

57

59

67

69

56

58

17

68

70

4

6

16

18

21

23

12

10

29

27

47

45

64

62

30

1 2

3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

C3136

1

2

C3135

1

2

R3141

1

2

R3140

1

2

C3140

1

2

C3100

1

2

C3101

1

2

C3110

1

2

C3111

1

2

C3112

1

2

C3113

1

2

C3114

1

2

C3115

1

2

C3116

1

2

C3117

1

2

C3118

1

2

C3119

1

2

C3120

1

2

C3121

1

2

C3122

1

2

C3123

1

2

8

27

8

27

8

www.laptop-schematics.com

IN

BI

OUT

BI

IN

BI

IN

BI

IN

BI

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42

DQ43

DQ48

DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15

A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36

DQ37

VSS

DM4

VSS

DQ38

DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD

NC

BA2

CK0

VDD

BA0

WE*

A13

S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54

DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS

DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MT G PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI

IN

BI

IN

BI

IN

BI

DQ2

DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1*

DQS1

DQ10

DQ11

DQ17

DQS2*

DQS2

DQ18

DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6

DQ7

DQ12

DQ13

DM1

RESET*

DQ14

DQ15

DQ20

DQ21

DM2

DQ22

DQ23

DQ28

DQ29

DQS3*

DQS3

DQ30

DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFOR MATION CON TAINED HE REIN IS TH E PROPRIE TARY PROPERTY OF APPLE C OMPUTER, INC. THE P OSSESSOR AGREES TO THE FOLLO WING

II NOT TO REPRODUCE OR COPY IT

III NOT T O REVEAL O R PUBLISH IN WHOLE OR PART

I TO MAIN TAIN THE D OCUMENT I N CONFIDEN CE

NOTICE OF PRO PRIETA RY PROP ERTY

DRAWING N UMBER

SHT

OF

SIZE

D

- =I2C_SODI MMB_SCL

- =I2C_SODI MMB_SDA

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

Power alias es required by this pag e:

Signal alia ses required by this pa ge:

(NONE)

"Expan sion" (botto m) slo t

- =PP1V5_S0 _MEM_B

SPD ADDR= 0xA2(WR)/ 0xA3(RD)

516s0704

Page Notes

BOM options provided by this page:

- =PPSPD_S0 _MEM_B (2.5 - 3.3V)

- =PP0V75_S 0_MEM_VTT_B

- =PP1V5_S3 _MEM_B

15 88

21 28 42

45

10V

20%

402

CERM

0.1UF

15 88

CERM 402-LF

6.3V

20%

2.2UF

10K

1/16W MF-LF

5%

402

10K

5%

402

MF-LF

1/16W

2.2UF

6.3V

402-LF

CERM

20%

603

6.3V X5R

20%

10UF

20%

603

X5R

10UF

6.3V

0.1UF

20% 10V

402

CERM

20% 10V CERM 402

0.1UF

402

10V

20%

0.1UF

CERM

20% 10V

0.1UF

402

CERM

15 88

20%

CERM 402

0.1UF

10V 10V

CERM 402

20%

0.1UF

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

0.1UF

CERM 402

20% 10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

15 88

DDR3-SO DIMM

F-RT-BGA 3

15 88

28 30

15 88

CRITIC AL

DDR3-SO DIMM

F-RT-BGA 3

15 88

9

15 88

CERM

0.1UF

20%

402

10V

2.2UF

6.3V CERM

20%

402-LF

15 88

SYNC_MASTER =DDR

29 9 6

A.0.0

051-7546

SYNC_DATE=0 7/22/2008

DDR3 S O-DIMM Connec tor B

=PP1V5 _S0_ME M_B

MEM_B_DQ <9>

MEM_B_DQ <18>

MEM_B_DQ <22>

MEM_B_DQ <4>

MEM_B_DQ <23>

MEM_B_DQ <19>

MEM_B_DQ S_P<2>

MEM_B_DQ S_N<2>

MEM_B_DQ <16>

MEM_B_DQ <20>

MEM_B_DQ <11>

MEM_B_DQ <14>

MEM_B_DM <1>

MEM_B_DQ <12>

MEM_B_DQ <13>

MEM_B_DQ <27>

MEM_B_DQ <26>

MEM_RESE T_L

MEM_B_DM <3>

MEM_B_DQ <25>

MEM_B_DQ <29>

MEM_B_DQ <7>

MEM_B_DQ <6>

MEM_B_DQ S_P<0>

MEM_B_DQ S_N<0>

MEM_B_DQ <5>

MEM_B_DQ <21>

MEM_B_DQ <17>

MEM_B_DQ <10>

MEM_B_DQ <15>

MEM_B_DQ S_P<1>

MEM_B_DQ S_N<1>

MEM_B_DQ <8>

MEM_B_DQ <30>

MEM_B_DQ <31>

MEM_B_DQ S_P<3>

MEM_B_DQ S_N<3>

MEM_B_DQ <28>

MEM_B_DM <0>

MEM_B_DQ <0>

MEM_B_DQ <1>

PP0V75_S 3_MEM_VR EFDQ_B

MEM_B_DQ <3>

MEM_B_DQ <2>

=PPSPD_S 0_MEM_B

MEM_B_DQ <59>

MEM_B_DQ <63>

MEM_B_SA <0>

MEM_B_SA <1>

MEM_B_DQ <57>

MEM_B_DQ <56>

MEM_B_DM <7>

MEM_B_CA S_L

MEM_B_DQ S_P<4>

MEM_B_DQ <35>

MEM_B_CL K_N<0>

MEM_B_A< 10>

MEM_B_DQ <52>

MEM_B_DQ <51>

MEM_B_DQ S_N<6>

MEM_B_DQ S_P<6>

=I2C_SOD IMMB_SDA

=I2C_SOD IMMB_SCL

=PP0V75_ S0_MEM_V TT_B

MEM_EVEN T_L

MEM_B_DQ <58>

MEM_B_DQ S_N<7>

MEM_B_DQ S_P<7>

MEM_B_DQ <60>

MEM_B_DQ <61>

MEM_B_DQ <50>

MEM_B_DQ <53>

MEM_B_DM <6>

MEM_B_DQ <54>

MEM_B_DQ <48>

MEM_B_DQ <46>

MEM_B_DQ S_P<5>

MEM_B_DQ <47>

MEM_B_DQ <41>

MEM_B_DQ <34>

MEM_B_DQ <32>

MEM_B_DQ <37>

MEM_B_CS _L<1>

MEM_B_A< 13>

MEM_B_WE _L

MEM_B_BA <0>

MEM_B_CL K_P<0>

MEM_B_BA <2>

MEM_B_DQ S_N<5>

MEM_B_DQ <44>

MEM_B_DQ <45>

MEM_B_DQ <39>

MEM_B_DM <4>

MEM_B_DQ <36>

MEM_B_DQ <33>

PP0V75_S 3_MEM_VR EFCA_B

MEM_B_OD T<1>

MEM_B_CS _L<0>

MEM_B_OD T<0>

MEM_B_BA <1>

MEM_B_RA S_L

MEM_B_A< 0>

MEM_B_CL K_P<1>

MEM_B_A< 2>

MEM_B_A< 4>

MEM_B_A< 6>

MEM_B_A< 7>

MEM_B_A< 11>

MEM_B_A< 14>

MEM_B_A< 15>

MEM_B_CK E<1>

MEM_B_DM <5>

MEM_B_DQ S_N<4>

MEM_B_DQ <40>

MEM_B_DQ <55>

MEM_B_DQ <42>

MEM_B_DQ <43>

MEM_B_A< 12>

MEM_B_A< 9>

MEM_B_A< 8>

MEM_B_A< 5>

MEM_B_A< 3>

MEM_B_A< 1>

=PP1V5 _S3_ME M_B

MEM_B_CK E<0>

MEM_B_DQ <24>

MEM_B_DQ <38>

MEM_B_DQ <49>

MEM_B_DQ <62>

MEM_B_DM <2>

MEM_B_CL K_N<1>

J3200

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101

103

102

104

73 74

136

153

170

187

129

131

141

143

130

132

140

142

147

149

157

159

146

148

158

160

163

165

175

177

164

166

174

176

181

183

191

193

180

182

192

194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

205 206

207 208

209 210

211 212

203 204

113

C3231

1

2

C3230

1

2

J3200

11

28

46

63

5

7

33

35

22

24

34

36

39

41

51

53

15

40

42

50

52

57

59

67

69

56

58

17

68

70

4

6

16

18

21

23

12

10

29

27

47

45

64

62

30

1 2

3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

C3236

1

2

C3235

1

2

R3241

1

2

R3240

1

2

C3240

1

2

C3200

1

2

C3201

1

2

C3210

1

2

C3211

1

2

C3212

1

2

C3213

1

2

C3214

1

2

C3215

1

2

C3216

1

2

C3217

1

2

C3218

1

2

C3219

1

2

C3220

1

2

C3221

1

2

C3222

1

2

C3223

1

2

8

27

8

27

8

Apple Macbook Pro A1286 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual