Apple macbook pro a1278 Schematic

APPLE INC.

6

DESIGNER

DESCRIPTION OF CHANGE

REV.

A

D

C

B

A

D

C

B

87

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TITLE

DRAWING NUMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

DO NOT SCALE DRAWING

REV

ZONE

ECN

CK APPD

DATE

ENG APPD

DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLES

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

5/6/2009

Schematic / PCB #’s

K24 MLB SCHEMATIC

PVT RELEASE

12/22/2008

35

YUN_K19_MLB

42

FireWire Port Power

11/02/2008

34

K19_MLB

41

FireWire LLC/PHY (FW643)

04/04/2008

33

SUMA

39

ETHERNET CONNECTOR

07/01/2008

32

SUMA

38

Ethernet & AirPort Support

05/23/2008

31

SUMA

37

Ethernet PHY (RTL8211CL)

01/30/2009

30

VEMURI

35

SECUREDIGITAL CARD READER

04/22/2008

29

YITE

34

04/04/2008

28

T18_MLB

33

DDR3 Support

05/09/2008

27

BEN

32

DDR3 SO-DIMM Connector B

06/30/2008

26

BEN

31

DDR3 SO-DIMM Connector A

03/31/2008

25

BEN

29

FSB/DDR3 Vref Margining

04/05/2008

24

RAYMOND

28

SB Misc

12/12/2007

23

T18_MLB

26

MCP Graphics Support

04/04/2008

22

T18_MLB

25

MCP Standard Decoupling

04/04/2008

21

T18_MLB

22

MCP Power & Ground

06/26/2008

20

T18_MLB

21

MCP HDA & MISC

04/04/2008

19

T18_MLB

20

MCP SATA & USB

04/04/2008

18

T18_MLB

19

04/04/2008

17

T18_MLB

18

MCP Ethernet & Graphics

04/04/2008

16

T18_MLB

17

MCP PCIe Interfaces

04/04/2008

15

T18_MLB

16

MCP Memory Misc

04/04/2008

14

T18_MLB

15

MCP Memory Interface

04/04/2008

13

T18_MLB

14

MCP CPU Interface

11/07/2008

K19_MLB

13

eXtended Debug Port(MiniXDP)

03/31/2008

11

RAYMOND

12

CPU Decoupling

12/12/2007

10

T18_MLB

11

CPU Power & Ground

12/12/2007

9

T18_MLB

10

CPU FSB

8

M97_MLB

9

SIGNAL ALIAS

04/21/2008

7

BEN

8

Power Aliases

6

M97_MLB

7

FUNC TEST

5

M97_MLB

5

Revision History

4

M97_MLB

4

BOM Configuration

03/13/2008

3

DRAGON

3

12/12/2007

2

T18_MLB

2

System Block Diagram

70

06/30/2008

AMASON

94

DisplayPort Connector

69

04/18/2008

AMASON

93

DISPLAYPORT SUPPORT

68

04/04/2008

NMARTIN

90

LVDS CONNECTOR

67

12/11/2008

YUAN.MA

79

POWER FETS

66

12/11/2008

YUAN.MA

78

POWER SEQUENCING

65

01/23/2008

RAYMOND

77

MISC POWER SUPPLIES

64

02/08/2008

RAYMOND

76

CPU VTT(1.05V) SUPPLY

63

12/10/2008

K19_MLB

75

MCP CORE REGULATOR

62

01/31/2008

RAYMOND

74

IMVP6 CPU VCore Regulator

61

01/31/2008

RAYMOND

73

1.5V/0.75V DDR3 SUPPLY

60

02/08/2008

RAYMOND

72

5V/3.3V SUPPLY

59

01/31/2008

RAYMOND

70

PBUS Supply/Battery Charger

58

12/11/2008

YUNWU

69

DC-In & Battery Connectors

57

03/20/2009

AUDIO

68

AUDIO: JACK TRANSLATORS

56

03/20/2009

AUDIO

67

AUDIO: JACK

55

12/18/2008

AUDIO

66

AUDI0: SPEAKER AMP

54

02/03/2009

AUDIO

65

AUDIO: HEADPHONE FILTER

53

01/31/2009

AUDIO

63

AUDIO: LINE INPUT FILTER

52

03/04/2009

62

AUDIO: CODEC/REGULATOR

51

05/02/2008

CHANGZHANG

61

SPI ROM

50

06/26/2008

YUNWU

59

SMS

49

05/09/2008

YUAN.MA

58

WELLSPRING 2

48

04/22/2008

YUAN.MA

57

WELLSPRING 1

47

01/18/2008

CHANGZHANG

56

Fan

46

03/20/2008

YUNWU

55

Thermal Sensors

45

12/17/2008

YUNWU

54

Current Sensing

44

02/04/2008

YUNWU

53

VOLTAGE SENSING

43

04/21/2008

BEN

52

K24 SMBUS CONNECTIONS

42

05/09/2008

CHANGZHANG

51

LPC+SPI Debug Connector

41

05/28/2008

YUAN.MA

50

SMC Support

40

06/26/2008

T18_MLB

49

SMC

39

05/28/2008

YUAN.MA

48

Front Flex Support

38

01/18/2008

YUAN.MA

46

External USB Connectors

37

12/04/2008

K19_MLB

45

SATA Connectors

81

K24 RULE DEFINITIONS

109

M97_MLB

80

K24 SPECIAL CONSTRAINTS

107

M97_MLB

01/04/2008

79

SMC Constraints

106

T18_MLB

12/01/2008

78

FireWire Constraints

105

K19_MLB

03/19/2008

77

Ethernet Constraints

104

T18_MLB

12/14/2007

76

MCP Constraints 2

103

T18_MLB

01/04/2008

75

MCP Constraints 1

102

T18_MLB

01/04/2008

74

Memory Constraints

101

T18_MLB

01/04/2008

73

CPU/FSB Constraints

100

T18_MLB

06/30/2008

72

LCD Backlight Support

98

YITE

PCBF,MLB,K24 CRITICAL820-2530

PCB1

08/22/2007

1

T17_MLB

1

Page

(.csa)

Sync

Date Date

Contents

Page

(.csa)

Sync

12/05/2008

71

LCD BACKLIGHT DRIVER

97

KIRAN

36

11/02/2008

K19_MLB

43

FireWire Ports

Sync

(.csa)

Date

Page

CRITICAL

1 SCH

051-7898

SCHEM,MLB,K24

051-7898

SCHEM,MLB,K24

811

?

MCP PCI & LPC

Contents

AUDIO

Power Block Diagram

Table of Contents

A

0000713283

K24 MLB PVT RELEASE

5/6/09

Right Clutch Connector

Contents

12

A

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

J9000

CONN

Conn

J4520

PG 17

Line Out

2

CTRL

CLK

J6800,6801,6802,6803

PG 41

PG 19

LPC

SATA

U6301 U6500U6400

PG 56PG 55

HEADPHONE

Audio

Codec

FSB

64-Bit

2 UDIMMs

XDP CONN

POWER SUPPLY

U3900

PG 33

Conn

PG 31

GB

E-NET

Amp

Speaker

Amps

PG 54

PG 53

PG 57

U4900

J6950

PG 12

U1000

U1300

J4510

U6600,6605,6610,6620

HD

E-NET

ODD

U6100

USB

PG 45

POWER SENSE

J5650,5600,5610,5611,5660,5720,5730,5750

PG 48,49

J4900

DC/BATT

PENRYN

2.X OR 3.X GHZ

INTEL CPU

SPI

PG 20

PG 18

MEMORY

MAIN

DDR2-800MHZ DDR3-1067/1333MHZ

J2900

DIMM

PG 25,26

SPI

TEMP SENSOR

FAN CONN AND CONTROL

J5100

PG 43

Ser

B,0

Prt

BSB

PWR

Misc

Port80,serial

LPC Conn

GPIOs

1.05V/3GHZ.

RGB OUT

PG 38

PG 13

FSB INTERFACE

PG 24

PG 20

HDA

NVIDIA

PG 41

16

PG 52

Boot ROM

U1400

DVI OUT

PG 17

LVDS OUT

HDMI OUT

RGMII

U3700

Line In

Amp Amp

PG 60

PG 9

PG 71

DP OUT

LVDS

PG 34

J4310

J9400

PG 34

FIREWIRE PORT

FW643

CONN

RTL8211CL

PG 56

EXTERNAL

J3900,4635,4655

USB

Connectors

PG 39

J4710

PG 40

J4710

TRACKPAD/

PG 40

J4720

PG 40

MCP79

J3500

PCI-E

PG 34

UP TO 20 LANES3

PG 16

CONN

DISPLAY PORT

Conn

SATA

PG 44

Conns

3

PCI

(UP TO FOUR PORTS)

PG 18

SMB

J4700

IR

SD CARD READER

PG 30

TMDS OUT

PG 71

PG 40

KEYBOARD

U6200

CONN

CAMERA

Bluetooth

DIMM’s

0

SMB

PG 20

J3400

Mini PCI-E

AirPort

PG 28

SYNTH

800/1067/1333 MHz

PG 14

45

(UP TO 12 DEVICES)

7

11

SMC

ADC Fan

PG 38

SATA

SYNC_MASTER=T18_MLB

051-7898

81

2

4.7.0

SYNC_DATE=12/12/2007

System Block Diagram

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

=DDRREG_EN

R7572

1.5V

TPS62202

U7200

TPS51125

(4A MAX

CURRENT)

EN1

SMC_BATT_ISENSE

U5403

(4A MAX CURRENT)

PP5V_S3

PP4V5_AUDIO_ANALOG

TPS7174S

4.5V AUDIO

U6200

PPBUS_G3H

(Q3841)

CPUVTTS0_PGOOD

RSMRST*

22

PWRGOOD

CPUVTTS0_EN

PBUS_VSENSE

IMVP_VR_ON(P16)

SLP_S3_L

SLP_S4_L

05

PPVOUT_S0_LCDBKLT

(S5)

P16

P60

BKLT_EN

PP1V5_S0

1.05V SO

PGOOD1,2

VOUT2

VREG3

K24 POWER SYSTEM ARCHITECTURE

02

VIN

PP1V05_S0

VOUT

U2850

23

R5492

SMC_CPU_VSENSE

3.425V G3HOT

Q5315

MCP_PS_PWRGD

PP3V3_S5

PPBUS_G3H

V

VOUT

VIN

CPU VCORE

PP3V42_G3H_REG

SMC PWRGD

04

PP3V3_S3_FET

U6990

LT3470

ENABLE

CPUPWRGD(GPIO49)

PPVBAT_G3H_CHGR_REG

02

FSB_CPURST_L

31

LPC_RESET_L

VOUT

ISL9504B

PS_PWRGD

VOUT

CPU_RESET#

13

07

29

U1400

U1000

CPU

RESET*

32

PPVIN_G3H_P3V42G3H

RN5VD30A-F

U5000

U7750

VIN

EN

PLTRST*

30

P3V3S5_EN_L

SMC_PM_G2_EN

(9 TO 12.6V)

(12A MAX CURRENT)

(1A MAX CURRENT)

PPVCORE_S0_MCP

EN2

U7500

PP1V5_S0_FET

5V

0.75V

U9701

11-2

Q3801

15-1

P3V3S3_EN

PCI_RESET0#

SMC_ADAPTER_EN

PPVCORE_S0_MCP_REG_R

PP0V75_S0_REG

(Q7901 & Q7971)

PP1V5_S3_REG

P17(BTN_OUT)

RST*

PWR_BUTTON(P90)

SMC_ONOFF_L

SLP_S5_L

LTC2909

U7870

6A FUSE

DCIN(16.5V)

PM_SLP_S3_L

U7300

S3

MCP_CORE

RST*

V1

PP1V5_S0

1.8V LDO

CPUVTTS0_EN

MCPDDR_EN

16-3

PM_SLP_S3_L

MCP79

S5

=DDTVTT_EN

14

F7000

DELAY

02

CHGR_EN

U7760

PPVBAT_G3H_CHGR_OUT

TPS51116

ADAPTER

RSMRST_OUT(P15)

RSMRST_IN(P13)

PLT_RST*

PP1V05_S0

PP3V3_S0

19-1

S0PGOOD_PWROK

SLP_S3_L(P93)

U4900

MCPCORESO_PGOOD

P5V3V3_PGOOD

RSMRST_PWRGD

IMVP_VR_ON

28

P3V3ENET_EN_L

PP1V8_S0_REG

SLP_S4_L(P94)

PM_RSMRST_L

ALL_SYS_PWRGD

25

SMC

PP3V3_S0_FET

VOUT

25

02

VIN

BATTERY CHARGER

PBUS SUPPLY/

06-1

17

16-3

03

16-2

10

09

24

18

16-2

20

21

02

16

04-1

16-1

16-2

16-4

16-2

15

11-3

DELAY

RC

11-1

11

3S2P

06

26

02

D6905

01

ENABLES

PWRBTN*

S3 TO S0

FETS

(25A MAX CURRENT)

P5V_LT_S3_PGOOD

CPUVTTS0_PGOOD

P1V05S0_EN

P5VRTS0_EN_L

CHGR_BGATE

SMC

V3

WOL_EN

DELAY

RC

(S0)

P3V3S0_EN

PBUSVSENS_EN

MCPCORES0_EN

P1V8S0_EN

P3V3_ENET_FET

MCPCORES0_EN

VOUT1

EN1

EN2

VIN

CPU_PWRGD

7A FUSE

SLP_S5_L(P95)

PWRGD(P12)

IMVP_VR_ON

SMC_RESET_L

PM_PWRBTN_L

99ms DLY

IN

AC

(S5)

A

V2

MCP79

PP3V3_S5_REG

D6905

VOUT2

P3V3S0_EN

DDRREG_EN

P5VLTS3_EN

DELAY

RC

FETS

(RT)

VOUT1

ENA

VOUT

DELAY

RC

Q3810

PM_ENET_EN_L

VIN

ISL6258A

U7000

5V (LT)

ISL6236

VOUT2

VOUT1

VIN

PM_SLP_S4_L

SLP_S3#

U1400

05

Q7800

SMC_PM_G2_EN

J6950

F6905

PP5V_S0_CPUVTTS0

PPBUS_G3H_CPU_ISNS

PPBUS_G3H_CPU_ISNS_R

EN_PSV

PGOOD

(S0)

V

Q7050

VIN

LP8543

U4900

PP18V5_DCIN_CONN

01

BATT_POS_F

Q3802

U7400

PGOOD

PP1V05_S5_REG

VR_PWRGOOD_DELAY

P5V3V3_PGOOD

04

08

VOUT

06

Q7930

3.3V

P5VRTS0_EN_L

P1V05_S5_EN

P1V05ENET_EN

Q7910

P3V3S3_EN

Q7940

P5VS0_EN

1.05V (S5)

(8A MAX CURRENT)

(44A MAX CURRENT)

SMC_CPU_ISENSE

VR_ON

PP5V_S3_REG

ISL8009

PP5V_S3_REG

PP5V_S0_FET

PP1V05_ENET_FET

PPVCORE_S0_CPU

U7600

TPS51117

(1.05V)

CPUVTT

3

4.7.0

Power Block Diagram

81

051-7898

SYNC_DATE=03/13/2008

SYNC_MASTER=DRAGON

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

Alternate Parts

Module Parts

Programmable Parts

LOCKED BOOTROM APN IS 341S2443

Bar Code Labels / EEE #’s

POWER

SIGNAL(High Speed)

DEVELOPMENT BOM

11

10

9

8

SIGNAL

GROUND

7

6

5

4

3

2

Top

GROUND

POWER

BOTTOM

GROUND

SIGNAL

BOM Groups

BOM Variants

SIGNAL(High Speed)

K24 BOARD STACK-UP

826-4393 CRITICAL

1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:6GD]

EEE_6GD

826-4393

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:6GC]

EEE_6GC

826-4393 CRITICAL

1

[EEE:6G4]

EEE_6G4

K24 MLB DEVELOPMENT BOM

085-0741

DEVEL_BOM

DEVEL

CRITICAL

1

338S0375

1

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

337S2983

1

341S2093

1

341S2503

IC,PRGRM,WELLSPRING CONTROLLER

1

338S0563

1

SYNC_MASTER=M97_MLB

BOM Configuration

81

4.7.0

051-7898

4

CRITICAL

IR_PROG

IR_BLANK

U4800

U4900

U4800

CRITICAL

U5701

CRITICAL335S0610

341S2441

U5701

CRITICAL

WELLSPRING_PROG

BOOTROM_PROG

CRITICAL

IC,PRGRM,EFI BOOTROM,UNLOCK,K24

U6100

IC,CY7C63833,ENCORE II,USB CONTROLLER

K24_COMMON

MCP_B03

U6100

CRITICAL

U1000

1

337S3704

337S3646

1

U1000

CRITICAL

IC,SMC,HS8/2117,9X9MM,TLP,HF

K24_DEBUG_ENG

K24_MCP

341S2445

1

CRITICAL

U4900

IC,SMC,K24

337S3756

337S3639

U1400

1

337S3761

338S0710

1

U1000

LBL,P/N LABEL,PCB,28MM X 6 MM

K24_DEBUG_PVT

LPCPLUS

CPU_2_66GHZ

SMC_PROG

BOOTROM_BLANK

K24_PROGPARTS

CRITICAL

1

K24_DEVEL_PVT

K24_DEVEL_ENG

K24_DEBUG_PROD

SMC_BLANK

CRITICAL

PDC,SLGE2,PRQ,2.26,25W,1066,R0,3M,BGA

K24_MISC

U1000

085-0741

K24 MLB DEVELOPMENT BOM

PCBA,MLB,BEST,K24

WELLSPRING_BLANK

BMON_PROD,SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

ONEWIRE_PU,DP_ESD,MIKEY,BKLT_PROD,SUPERCAP_NO,LDO_NO

MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC

DEVEL_BOM,BMON_PROD,SMC_DEBUG_YES,XDP,NO_VREFMRGN

DEVEL_BOM,SMC_DEBUG_YES,XDP

BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG

PCBA,MLB,BETTER,K24

BMON_ENG,XDP_CONN,LPCPLUS,VREFMRGN,FWPHY_WAKE_YES

CPU_2_53GHZ

CPU_2_4GHZ

CPU_2_26GHZ

CPU_2_0GHZ

COMMON,ALTERNATE,K24_MCP,K24_MISC,K24_DEBUG_PVT,K24_PROGPARTS

K24_DEVEL_PVT

K24_COMMON,CPU_2_26GHZ,EEE_6GC,KB_BL

K24_COMMON,CPU_2_53GHZ,EEE_6GD,KB_BL

152S1025

MAGLAYERS AS ALTERNATE

TOKO AS ALTERNATE

ALL

MOLEX AS ALTERNATE

516S0709

516-0213

152S0847

152S0874

152S0685

MAGLAYERS AS ALTERNATE

ALL

KEMET AS ALTERNATE

DALE/VISHAY AS ALTERNATE

DELTA AS ALTERNATE

152S1024

ALL

104S0018

152S0778

128S0093

152S0693

ALL

516S0706

516-0201

152S0586

152S0516

128S0218

104S0023

152S0796

MOLEX AS ALTERNATE

157S0058 157S0055

CYNTEC AS ALTERNATE

IC,IR CONTROLLER,M97

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

IC,GMCP,MCP79,35X35MM,BGA1437,B03

PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA

PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA

PDC,SLB4N,PRQ,2.4,25W,1066,M0,3M,BGA

PDC,SLG8E,PRQ,2.0,25W,1066,M0,3M,BGA

630-9924

630-9923

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Revision History

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

SYNC_MASTER=M97_MLB

4.7.0

Revision History

051-7898

81

5

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

KBD BACKLIGHT CONN

SATA HDD/IR/SIL

(NEED TO ADD 4 GND TP)

SATA ODD CONN

(NEED TO ADD 3 GND TP)

(NEED 3 TP)

BATT POWER CONN

(NEED 4 TP)

(NEED 3 TP)

(NEED TO ADD 2 GND TP)

(NEED TO ADD 4 GND TP)

DEBUG VOLTAGE

(NEED 3 TP)

(NEED 2 TP)

(NEED TO ADD 1 GND TP)

(NEED TO ADD 5 GND TP)

BATT SIGNAL CONN

(NEED TO ADD 5 GND TP)

IPD_FLEX_CONN

(NEED TO ADD 6 GND TP)

Fan Connectors

RIGHT CLUTCH CONN

(NEED TO ADD 3 GND TP)

SPEAKER FUNC_TEST

LVDS FUNC_TEST

KEYBOARD CONN

DC POWER CONN

Functional Test Points

(NEED TO ADD 4 GND TP)

THERMAL FUNC_TEST

MIC FUNC_TEST

(NEED 2 TP)

(NEED 3 TP)

I12

I15

I16

I226

I227

I228

I229

I230

I231

I232

I233

I237

I238

I239

I245

I246

I247

I248

I249

I250

I251

I252

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I264

I265

I266

I267

I268

I269

I270

I271

I272

I273

I274

I275

I276

I278

I279

I280

I281

I282

I283

I284

I285

I287

I288

I289

I290

I291

I292

I293

I294

I295

I296

I297

I298

I299

I300

I301

I302

I303

I304

I305

I307

I308

I309

I311

I312

I313

I314

I315

I317

I318

I319

I320

I321

I322

I323

I324

I325

I326

I327

I328

I329

I330

I331

I332

I333

I334

I335

I336

I337

I338

I339

I340

I341

I342

I343

I344

I345

I346

I347

I348

I349

I350

I351

I352

I353

I354

I355

I356

I357

I358

I359

I360

I361

I362

I363

I364

I365

I366

I368

I369

I370

I371

I372

I374

I375

I376

I377

I378

I379

I380

I381

I382

I383

I385

I386

I387

I388

I389

I390

I391

I392

I393

I394

I395

SYNC_MASTER=M97_MLB

FUNC TEST

051-7898

81

4.7.0

6

PPVOUT_S0_LCDBKLT

TRUE

CONN_USB2_BT_N

TRUE

MINI_CLKREQ_Q_L

TRUE TRUE

MINI_RESET_CONN_L

PCIE_MINI_R2D_N

TRUE

PCIE_WAKE_L

TRUE

SMBUS_SMC_A_S3_SCL

TRUE TRUE

SMBUS_SMC_A_S3_SDA

TRUE

Z2_MOSI

TRUE

WS_KBD5

TRUE

Z2_SCLK

PSOC_MISO

TRUE

Z2_KEY_ACT_L

TRUE

Z2_RESET

TRUE

Z2_CLKIN

Z2_BOOST_EN

TRUE

Z2_MISO

CONN_USB2_BT_P

TRUE

USB_CAMERA_CONN_N

TRUE

PCIE_CLK100M_MINI_CONN_P

TRUE

PCIE_MINI_D2R_P

TRUE

PP5V_S3_BTCAMERA_F

TRUE

PCIE_CLK100M_MINI_CONN_N

PCIE_MINI_R2D_P

TRUE

PCIE_MINI_D2R_N

TRUE

SPKRAMP_SUB_P_OUT

TRUE

SPKRAMP_SUB_N_OUT

TRUE

SPKRAMP_R_P_OUT

TRUE

ADAPTER_SENSE

LVDS_IG_DDC_CLK

TRUE

LVDS_IG_DDC_DATA

TRUE

LVDS_IG_A_DATA_P<0>

TRUE

LVDS_IG_A_DATA_N<0>

TRUE

LVDS_IG_A_DATA_P<2>

TRUE

LVDS_IG_A_DATA_N<1>

TRUE

BI_MIC_HI

TRUE TRUE

BI_MIC_SHIELD

PP3V3_S0_LCD_F

TRUE

PP5V_S0

TRUE

LVDS_IG_A_DATA_P<1>

PP3V3_LCDVDD_SW_F

TRUE

PP5V_WLAN

TRUE

LED_RETURN_3

TRUE

WS_KBD10

TRUE

PP18V5_DCIN_FUSE

TRUE

FAN_RT_PWM

TRUE

PSOC_MOSI

TRUE

Z2_CS_L

BI_MIC_LO

TRUE

FAN_RT_TACH

SPKRAMP_R_N_OUT

TRUE

SPKRAMP_L_P_OUT

TRUE

SPKRAMP_L_N_OUT

TRUE

WS_KBD8

WS_KBD14

TRUE

WS_KBD4

TRUE

WS_KBD6

TRUE

WS_KBD7

TRUE

LVDS_IG_A_DATA_N<2>

WS_KBD9

TRUE

Z2_HOST_INTN

TRUE

Z2_DEBUG3

PP18V5_S3

TRUE

USB_CAMERA_CONN_P

TRUE

PP3V3_S3_LDO

TRUE

PICKB_L

TRUE

PSOC_F_CS_L

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PSOC_SCLK

TRUE

SMBUS_SMC_A_S3_SDA

SYS_DETECT_L

TRUE

PP3V42_G3H

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMC_BIL_BUTTON_L SMC_LID_R

TRUE

LVDS_IG_A_CLK_F_P

TRUE

LVDS_IG_A_CLK_F_N

TRUE

LED_RETURN_2

TRUE

LED_RETURN_1

TRUE

MCPTHMSNS_D2_P

TRUE

MCPTHMSNS_D2_N

PPVCORE_S0_CPU

TRUE

PPVCORE_S0_MCP

TRUE

PP1V05_S0

TRUE

PP0V75_S0

TRUE

PP1V5_S0

TRUE

PP5V_S0

PP1V8_S0

TRUE

PP1V5_S3

TRUE

PP3V3_S0

TRUE

PP3V3_S3

TRUE TRUE

PP5V_S3 PP1V1R1V05_S5

TRUE

PP3V3_S5

TRUE

PP1V2R1V05_ENET

TRUE

PP3V42_G3H

TRUE

PPBUS_G3H

TRUE TRUE

PP3V3_ENET_PHY

PP3V3_G3_RTC

TRUE

PP5V_WLAN

TRUE

PP5V_SW_ODD

TRUE

PP5V_S0_HDD_FLT

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP18V5_S3

TRUE

PP4V5_AUDIO_ANALOG

TRUE

PP3V3_S3_LDO

TRUE TRUE

PP3V3_LCDVDD_SW_F

PPVOUT_S0_LCDBKLT

TRUE

SMC_PM_G2_EN PM_SLP_S4_L

TRUE

PM_SLP_S3_L

TRUE

BATT_POS_F

TRUE

SATA_ODD_D2R_C_N

TRUE

LED_RETURN_6

WS_KBD3

TRUE

WS_KBD2

TRUE

WS_KBD1

TRUE

PP3V42_G3H

TRUE

PP3V3_S3

TRUE

LED_RETURN_4

TRUE

LED_RETURN_5

SATA_ODD_R2D_N

TRUE

TP_BKL_SYNC

TRUE

WS_KBD12

WS_KBD11

TRUE

WS_KBD13

SATA_HDD_R2D_N

TRUE

WS_KBD16_NUM

TRUE

WS_KBD15_CAP

TRUE

WS_KBD17

TRUE

PP5V_S0_HDD_FLT

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_D2R_C_N

TRUE

SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA

TRUE

SATA_ODD_R2D_P

TRUE

SATA_ODD_D2R_C_P

TRUE

SMC_ODD_DETECT

TRUE

SYS_LED_ANODE_R

TRUE

PP5V_S3_IR_R

TRUE

IR_RX_OUT

TRUE

PP5V_SW_ODD

TRUE

WS_KBD20

TRUE

WS_KBD18

TRUE

WS_KBD23

SMC_KDBLED_PRESENT_L

TRUE

KBDLED_ANODE

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_KBD_ONOFF_L

TRUE

WS_KBD21

TRUE

WS_CONTROL_KBD

TRUE

WS_KBD19

TRUE

WS_KBD22

SATA_HDD_R2D_P

TRUE

6C3

68B2 71C1

29B7 76B3

29C7

29A7

29C7 75D3

16B6 29C7

6C5

43D2 79D3

6C5

43D2 79D3

48C8 49C3

48C6 48D2

48C8 49C3

48C8 49C1

48C6 49C3

49C3 49C5

48C8 49C3

29B7 76C3

29C7 75D3

16B6 29C7 75D3

29C7

29C7 75D3

16B6 29C7 75D3

55C2 56B2

55B2 56B2

55C2 56B2

58D7

17B3 68C5

17A3 68C5

17B3 68C2 75B3

56C2 57B1

68C3

6D3 7D5

17B3 68C2 75B3

6C3

68C2

6C3 29C5

68B3 71B1

48C6 48D2

58D6

47B4

48C8 49C1

48C8 49C3

56C2 57B1

47C4

55C2 56A2

55B2 56B2

55A2 56B2

48C6 48D2

48C2 48C6

48C6 48D2

48D2 48C6

17B3 68C2 75B3

48C6 48D2

48D8 49C3

48C8 49C3

6C3

49C1 49D3

29B7 76C3

6C3

49B4 49C3

48D8 49C1

48C8 49C1

6D5

43D2 79D3

48C8 49C1

6D5

43D2 79D3

58A8

6B5 6D3 7D1

6A7

43C5 79D3

6A7

43C5 79D3

40C5 58C4

58C2

68C2 75B3

68B3 71B1

46B5 80D3

7D7

7C7

7D7

7C7

7C6

6D7 7D5

7B6

7D3

7D5

6B5 7D3

7C3

7B3

7B5

6A7 6B5 7D1

7C1

7B5

20C8 21A5 24D4

6D5

29C5

6B7

37D3

6B7

37B6

40D4 41C6

6C5

49C1 49D3

52A5 52D2 52D7

6C5

49B4 49C3

6C7

68C2

6C7

68B2 71C1

40D5 60C5 66D8

20C3 40C5 41A2 66C8

20C3 32B7 35A5 40C5 66D5 70D8

58B8 59A3 58A7

75A3 37C6

68B3 71A1

48C6 48D2

6A7 6D3 7D1

6D3 7D3

68B3 71B1

6A7

37C6 75A3

68C2

48C6 48D2

48D2 48C6

48C6 48D2

75A3 37A5

48C2

48C2 48D6

37B6

6C3

75A3 37B5

6A7

79D3 43C5

37C6 75A3

75A3 37C6

40B8 37C7

37A7

39D4 37A7

6C3

37D3

48C2 48D7

49A4 49A6

49A4

48B3 48B5 48C2

48C2

48C2 48D7

48B3 48B5 48C2

48C2 48D7

75A3 37A5

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

"S5" RAILS

"ENET" RAILS

206 mA (A01)

57 mA (A01)

206 mA (A01)

127 mA (A01)

& CPU VTT SENSING RES.)

(BEFORE HIGH SIDE SENSING RES.)

127 mA (A01)

(AFTER HIGH SIDE CPU VCORE

127 mA (A01)

(CPU VCORE PWR)

"S0,S0M" RAILS

"S3" RAILS

"FIREWIRE" RAILS

43 mA (A01)

"G3H" RAILS

(MCP VCORE AFTER SENSE RES)

PEX & SATA AVDD/DVDD aliases

Power Aliases

051-7898

7

81

4.7.0

SYNC_MASTER=BEN

=PP1V05_S0_MCP_PEX_DVDD0

PP3V42_G3H

VOLTAGE=3.42V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_PWRCTL

=PPVIN_S5_SMCVREF

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 mm

PP1V5_S3

=PP1V5_S3_MEM_A

=PP1V5_S3_HDD

=PP3V3_S3_FET

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_PDCISENS

=PP3V3_S3_SMBUS_SMC_MGMT

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=3.3V

PP3V3_S3

=PP3V3_S3_WLAN

=PP3V3_S3_VREFMRGN

=PP1V5_S3_MEM_B

=PP3V3_S3_TPAD

=PP3V3_S3_CARDREADER

=PP5V_S0_MCPREG

=PP5V_S0_HDD

=PP5V_S0_CPU_IMVP

=PP5V_S3_P5VS0FET =PP5V_S3_ODD

=PP5V_S3_AUDIO_AMP

=PP5V_S3_AUDIO

=PP5V_S3_1V5S30V75S0

=PP5V_S3_TPAD =PP5V_S3_WLAN

=PP5V_S3_VTTCLAMP =PP5V_S3_MCPDDRFET =PP5V_S3_SYSLED

=PP5V_S3_IR =PP5V_S3_BTCAMERA

=PP5V_S3_EXTUSB

=PP5V_S3_REG

=PP3V3_S3_SMS

=PP3V3_S3_MCP_GPIO

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S3

VOLTAGE=5V MAKE_BASE=TRUE

=PP1V5_S3_P1V5S0FET

=PP5V_S0_DP_AUX_MUX

=PP1V05_S0_CPU

=PP3V3_S5_P1V05FWFET

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_S5

=PPVTT_S3_DDR_BUF

=PP3V3_S0_FET

=PP1V05_S0_SMC_LS =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_AVDD_UF

PP1V05_S0

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

=PP1V05_S0_VMON

=PP3V3_S0_MCP

=PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP_DAC_UF

PP3V3_S0

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PP5V_S0_FET

=PP1V05_S0_MCP_SATA_DVDD

=PP1V5_S3_REG

=PP3V3_S0_MCP_GPIO

=PP3V3_FW_LATEVG_ACTIVE

=PP3V3_S0_FWPWRCTL

=PP3V3_S0_P3V3FWFET

=PP3V3_S0_MCPDDRISNS =PP3V3_S0_MCP_PLL_VLDO

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_P1V8S0

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_TPAD

=PP3V3_S0_CPUVTTISNS

=PP3V3_S0_VMON

=PPSPD_S0_MEM_B =PP3V3_S0_PWRCTL

=PP3V3_S0_DPCONN =PPSPD_S0_MEM_A

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS

=PP3V3_S0_MCP_PLL_UF

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_IMVP

=PP3V3_S0_LCD

=PP3V3_S0_FAN_RT =PP3V3_S0_AUDIO

=PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_ODD

=PP3V3_S0_XDP

PP5V_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=5V MAKE_BASE=TRUE

=PP1V0_FW_FWPHY

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_FW

VOLTAGE=3.3V

=PP3V3_S0_P1V05FWFET

=PP3V3_FW_FWPHY

=PP3V3_FW_FET

=PPBUS_S5_FW_FET

=PPVP_FW_PHY_CPS_FET

=PP3V3_S5_P3V3S0FET =PP3V3_S5_P1V05S5

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P3V3S3FET

=PP3V3_S5_PWRCTL

=PP3V3_S5_LCD

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V1R1V05_S5

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

=PP3V3_S5_P1V05ENETFET

=PP3V3_S5_MCP

=PP3V3_S5_MEMRESET

=PP3V3_S5_MCPPWRGD

=PP1V05_ENET_P1V05ENETFET

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_S5_REG

=PP1V05_ENET_PHY

=PP3V3_S5_DP_PORT_PWR

=PP3V3_FW_LATEVG

=PP1V5_S0_CPU

=PP1V8_S0_AUDIO

=PPVCORE_S0_CPU =PPVCORE_S0_CPU_VSENSE

=PP1V05_S0_MCP_HDMI_VDD

=PPCPUVTT_S0_REG

=PP1V05_S0_MCP_SATA_DVDD0

=PPVCORE_S0_MCP_VSENSE

=PP0V75_S0_REG

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.3 MM

=PP5V_S0_VMON

=PP5V_S0_CPUVTTS0

=PP5V_S0_KBDLED

=PP5V_S0_LPCPLUS =PP5V_S0_FAN_RT

=PP5V_S0_BKL

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_PEX_DVDD

=PPVCORE_S0_MCP

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V8_S0_REG

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V8_S0

MIN_LINE_WIDTH=0.5 MM

=PP1V05_S0_MCP_PLL_UF

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PPVTT_S3_DDR_BUF

=PP1V05_S0_MCP_SATA_AVDD0

=PPVIN_S5_1V5S30V75S0

=PPBUS_S0_LCDBKLT

=PPCPUVCORE_VTT_ISNS_R

=PPBUS_G3HRS5 =PPBUS_S5_FWPWRSW

=PPVIN_S3_5VS3

=PPVIN_S5_3V3S5

MIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6V

PPBUS_G3H

=PPCPUVCORE_VTT_ISNS

=PPBUS_G3H

=PPVIN_S0_MCPCORE

=PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=12.6V

PPBUS_G3H_CPU_ISNS

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_PEX_AVDD0

MAKE_BASE=TRUE

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V

PP18V5_G3H

=PP18V5_DCIN_CONN

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.6 MM

=PPVCORE_S0_CPU_REG

=PP1V5_S0_FET

=PP1V8R1V5_S0_MCP_MEM

=PP1V5_S0_VMON

=PP0V75_S0_MEM_VTT_B

=PP0V75_S0_MEM_VTT_A

=PPVTT_S0_VTTCLAMP

=PP3V3_ENET_FET

=PP1V05_ENET_FET

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_ENET_PHY

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

=PP1V05_ENET_MCP_RMGT

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V2R1V05_ENET

=PP1V05_ENET_MCP_PLL_MAC

=PP3V3_S5_MCP_GPIO =PP3V3_S5_ROM

=PP1V0_FW_FET

PP1V05_FW

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

=PPVP_FW_PORT1

PPVP_FW

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE

=PP3V3_S5_REG

=PP3V3_ENET_PHY

=PP3V3_ENET_MCP_RMGT

=PP1V5_S0_MCP_PLL_VLDO

=PP1V5_S0_MEM_MCP

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5 mm

PP1V5_S0

MAKE_BASE=TRUE

PP0V75_S0

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_MCP

MAKE_BASE=TRUE

=PPMCPCORE_S0_REG

=PP1V05_FW_P1V05FWFET =PP1V05_FWPWRCTL

=PP1V05_S0_MCP_PLL_UF_R

=PP1V05_S0_MCP_FSB

=PP1V5_S3_MEMRESET

=PP3V42_G3H_REG

=PP3V42_G3H_CHGR

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V42_G3H_TPAD =PP3V42_G3H_BATT

=PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PP3V42_G3H_RTC_D

=PP3V42_G3H_BMON_ISNS

=PP3V42_G3H_ONEWIRE

=PP18V5_G3H_CHGR

=PP3V42_G3H_AUDIO

16B6

6A7 6B5 6D3

38B8

66B3 66C8 66D8

41C8

6D3

26D7

37B8

67D6

43D3

61B3

43B5

6D3 6B5

29A6

25D8

27D7

48A6 48B5 48C5 48D2

30D7

63D4

37B3

62D8

67B8

37D5

55B7 55C7 55D7

52A8 52D2 54D5 56B6

61C5

49B6 49D7

29C1

67A3

67D4

41B8

37A8 39D7

29C3

38C7

60B8

50B7

20A3

6D3

67D3

69B6

9D5

10C6 11B6 12D6

35C7

6D3

25D3 61D8

67C6

7A8

22D8

22D4

6D3

66A8

20C2 21B3 22B8

43D8

23C7

23D4

6D3

67B6

7A8

22D6

61C1

17C1 18D1 20A4

35A8

35B1 35D2

35D6

45D8

65C6

71C7

65D8

43C8

49A6

45C7

66A8

27A8

66A5

70B8 70C8

26A8

46D6

41A1 41D3

46B6

22B6

20D3 20D8 22A8

62D8

68C5

47C5

52A8 52D2 56D8 57B8 57D3

43D5

43C3

37C7 37D6

12D6

6D3 6D7

34D8 35D3

35C7

34B1 34D2

35D8

36B6

36D5

35D4

35B1

36C6

67C8

65B8

32D5

67D8

66B3

68C8

6D3

32C5

21B3 22B8

28C4

24B8

32C4

21A3 22D8

65A5

31D2

70D8

36A7

10B6 11B6

52D7

10B5 10D6 11D6

44D8

17A6 23D7

64C2

19B6

44D8

61C8

6D3

66B5

64C8

49A5

42D5

47C5

71D4

7D7

22D6

7D7

22D8

21D5 22D8

17B6 23D7

65C5

6D3

22C4 65B1

22D1

19B6

61C2

72D8

45B8

44B8

35B7

60C6 60C7

60C3

6C3

45B7

59C1

63D5

64C6

62C3 62D4 62D8

19B6

16A6

16A3

16B3

22D2

58C8 58D1

62D1

67D1

15C3 15C7 22C8

66A8

27A4

26A4

67B3

32D2

32B2

6C3

17D3 22D6

6C3

22A8

17C7 19C1

42B5 42C7 51C6

35C5

36C3

60B1

31D7

17D3 17D7 22A5 22B6

65B6

27B3

6D3

63B8 63C1 63C7

35C6

35B4

65B3

13A2 13B7 21D3 22C8

28C6

58B4

59A8 59C6 59D5

43C5

48B5 48C2 48C3 48C5

58C2 58C4

40D4 41C1 41C7

41C3

41D8

42C7 42D5 42C8

24D8

45B8

58D2

59D8

56B6

OUT

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

HEATSINK STANDOFFS

FIREWIRE PRESENT SIGNALS

BELOW CPU

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

USB ALIASES

UNUSED USB PORTS

DP HOTPLUG PULL-DOWN

UNUSED GPU LANES

ETHERNET ALIASES

UNUSED ADDRESS PINS

SO-DIMM ALIASES

UNUSED EXPRESS CARD LANE

PCI-E ALIASES

LEFT OF CPU

ABOVE CPU

BELOW MCP

DACS ALIASES

UNUSED CRT & TV-OUT INTERFACE

266

(RSVD)

100

133

333

200

(166)

(400)

FSB MHZ

0 0 1

1 1 1

0 1 0

0 0 0

0 1 1 1 0 0 1 0 1 1 1 0

BSEL<2..0>

CPU FSB FREQUENCY STRAPS

FW ALIASES

LAN ALIASES

UNUSED LVDS SIGNALS

LVDS ALIASES

MISC MCP79 ALIASES

FAN STANDOFF

MLB MOUNTING (TO TOPCASE) SCREW HOLES

EMI POGO PINS

EMI IO POGO PINS

Z0912

3R2P5

OMIT

1

OMIT

1

Z0909

3R2P5

Z0911

OMIT

1

Z0908

OMIT

3R2P5

1

Z0901

STDOFF-4.5OD.98H-1.1-3.48-TH

1

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0904

1

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902

1

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0903

1

2

1/16W

5% MF-LF

402

R0930

47K

13A7

9B4

73C3

402

20K

1/16W

5% MF-LF

2

1

R0940

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0905

1

OMIT

3R2P5

1

Z0910

OMIT

1.4DIA-SHORT-EMI-MLB-M97-M98

ZS0901

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0905

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0906

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0904

SM

1

SM

1

ZS0907

2.0DIA-TALL-EMI-MLB-M97-M98

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

OMIT

1

ZS0902

1.4DIA-SHORT-EMI-MLB-M97-M98

ZS0900

OMIT

SM

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

OMIT

ZS0903

1

Z0907

OMIT

3R2P5

1

Z0906

3R2P5

1

OMIT

NOSTUFF

R0950

1

0

5%

1/16W

402

MF-LF

2

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

OMIT

ZS0908

1

ZS0909

1.4DIA-SHORT-EMI-MLB-M97-M98

OMIT

1

SM

R0931

22

1

2

1/16W

5% MF-LF

402

SIGNAL ALIAS

SYNC_MASTER=M97_MLB

8

4.7.0

81

051-7898

ZS0900,ZS0901,ZS0902,ZS0903,ZS0908,ZS0909

POGO PIN,SHORT,EMI,MLB,K19/K24

CRITICAL870-1801

6

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

MAKE_BASE=TRUE

USB_EXCARD_P

MAKE_BASE=TRUE

TP_USB_EXCARD_N

TP_USB_MINI_P

MAKE_BASE=TRUE

CRT_IG_R_C_PR

CRT_IG_G_Y_Y

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

FW643_WAKE_L=FW_PME_L

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

FW_PLUG_DET_LFW_PME_L

MAKE_BASE=TRUE

TP_PCIE_CLK100M_EXCARD_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_P3

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATA_N3

MAKE_BASE=TRUE

TP_PCIE_CLK100M_EXCARD_P

CPU_PECI_MCP

GMUX_JTAG_TDO GMUX_JTAG_TDI

CPU_BSEL<0:2>

MAKE_BASE=TRUE

=MCP_BSEL<0:2>

MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_TV_DAC_RSET

USB_EXCARD_N

=MCP_MII_RXER

USB_EXTD_N

TP_USB_EXTD_N

MAKE_BASE=TRUE

TP_USB_EXCARD_P

MAKE_BASE=TRUE

TP_USB_EXTC_N

USB_EXTD_P

TP_USB_EXTD_P

MAKE_BASE=TRUE

TP_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

PCIE_EXCARD_PRSNT_L

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

TP_PCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_CLK_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATA_P<3:0>

MAKE_BASE=TRUE

EXCARD_CLKREQ_L

TP_EXCARD_CLKREQ_L

MAKE_BASE=TRUE

TP_PCIE_EXCARD_PRSNT_L

TP_PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

LVDS_IG_B_DATA_N<3:0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_CLK_N

TP_PEG_CLK100M_N

MAKE_BASE=TRUE

TP_PEG_CLK100M_P

=MCP_MII_COL

MEM_B_A<15>

MAKE_BASE=TRUE

PM_SLP_RMGT_L

=RTL8211_REGOUT

PEG_CLK100M_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2R_P<15:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15:0>

TP_MEM_A_A15

MAKE_BASE=TRUE

TP_MEM_B_A15

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<15:0>

MCP_TV_DAC_VREF

MCP_CLK27M_XTALOUT

MEM_A_A<15>

CRT_IG_VSYNC

NO_TEST=TRUE

NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

NO_TEST=TRUE

=P3V3ENET_EN

=PEG_R2D_C_P<15:0>

=P1V05ENET_EN

TP_PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

=PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

=RTL8211_ENSWREG

MAKE_BASE=TRUE

TP_PEG_PRSNT_L

NO_TEST=TRUE

NC_CRT_IG_B_COMP_PB

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

MCP_CLK27M_XTALIN

GMUX_JTAG_TCK_L

MCP_MII_PD

MAKE_BASE=TRUE

HPLUG_DET2

MAKE_BASE=TRUE

=MCP_MII_CRS

MAKE_BASE=TRUE

TP_PCIE_EXCARD_D2R_N

PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

NC_PEG_D2R_N<15:0>

NO_TEST=TRUE

=PEG_D2R_P<15:0>

PEG_CLK100M_N

PEG_PRSNT_L

=PEG_R2D_C_N<15:0>

USB_EXTC_P

PCIE_FW_PRSNT_L

LVDS_IG_B_CLK_P

GMUX_JTAG_TMS

MAKE_BASE=TRUE

TP_GMUX_JTAG_TMS

TP_GMUX_JTAG_TDI

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDO

MAKE_BASE=TRUE

TP_GMUX_JTAG_TCK_L

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

MAKE_BASE=TRUE

TP_USB_MINI_N

USB_MINI_P USB_MINI_N

TP_USB_EXTC_P

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_EXCARD_P

LVDS_IG_B_CLK_N

=DVI_HPD_GMUX_INT

USB_EXTC_N

TP_RTL8211_CLK125

NO_TEST=TRUE

NC_LVDS_IG_B_DATA_N<3:0>

MAKE_BASE=TRUE

LVDS_IG_B_DATA_P<3:0>

=PEG_D2R_N<15:0>

19C3

17C3

34B2 35C8

35B1 35D7 18B7

13B6

16B6

18D4

17C6

19C3

17D6

19D3

16B6

16C6

16B3

16C6

17B3

17D6

27D5

20C3

31C2

16C3

17C6

26D5

17C3

32C5

16C3 16D3

32B5

31C2

31C6

17C6

16B6

17D6

16B6

16C6 16D6

16C3

16C6

16C3 16D3

19C3

16C6 35D3

17B3

18D4

17B3

19D3

16C3

17B3

17B6

19C3

31B6

17B3

16C6 16D6

BI

IN

OUT

IN

BI

OUT

BI

OUT

IN

OUT

IN

OUT

BI

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACEMENT_NOTE (all 4 resistors):

CPU JTAG Support

SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL

R1000

1

2

1%

1/16W

54.9

MF-LF

402

R1002

1

2

68

5% 1/16W MF-LF

402

R1005

1

2

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.

402

1K

MF-LF

1% 1/16W

R1006

1

2

PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.

1%

MF-LF

2.0K

1/16W

402

R1023

1

2

Place within 12.7mm of CPU

54.9

1% 1/16W MF-LF

402

R1022

1

2

Place within 12.7mm of CPU

27.4

1% 1/16W MF-LF 402

R1021

1

2

Place within 12.7mm of CPU

402

MF-LF

1/16W

1%

54.9

R1020

1

2

Place within 12.7mm of CPU

27.4

1% 1/16W MF-LF 402

13C3 73D3

13B3 73D3

13D6 73D3

13B3 73D3

13D6 73D3

13A3 62C7 73B3

13A3 73B3

62C7

12C7 13A3 73C3

13D3 73D3

13D6 73D3

13D3 73D3

13C3 73D3

13D6 73D3

8B2

73C3

8B2

73C3

8B2

73C3

13D6 73D3

13C6 73D3

13B6 73D3

13C6 73C3

13B6 73C3

13B3 73C3

13B6 73C3

12C6 73A3

9B6

12B3 73A3

12B3 24A3

13B6 41D4 62C8 73C3

46D5 80D3

13B7 41C4 73B3

13A3 73C3

12C2 13A3 73C3

13A6 73C3

13B6 73C3

9A6

12B6 73A3

9B6

12B3 73A3

9B6

12B3 73A3

9A6

12B3 73A3

46D5 80D3

13B3 73B3

13A3 73C3

13A3 73B3

13B7 73C3

R1010

12

NO STUFF

5%

MF-LF

1/16W

0

402

R1011

1

2

NO STUFF

1/16W

5%

MF-LF

1K

402

R1001

1

2

54.9

402

MF-LF

1%

1/16W

R1090

12

54.9

1/16W MF-LF

1%

402

R1091

12

1%

MF-LF

1/16W

54.9

402

R1093

12

1%

MF-LF

1/16W

54.9

402

13C6 73C3

R1094

12

1%

MF-LF

1/16W

649

402

R1012

1

2

402

MF-LF

1K

5% 1/16W

NO STUFF

C1014

1

2

PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

NO STUFF

X5R

0.1uF

10% 16V

402

U1000

B22

B23

C21

R26

U26

AA1

Y1

E22

F24

J24

J23

H22

F26

K22

H23

N22

K25

P26

R23

E26

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

G22

T25

N25

Y22

AB24

V24

V26

V23

T22

U25

U23

F23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

AE24

AD24

G25

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

E25

AC22

AD23

AF22

AC23

E23

K24

G24

H25

N24

U22

AC20

E5

B5

D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6

D7

C23

D25

C24

AF26

AF1

A26

C3

FCBGA

PENRYN

OMIT

R1092

12

PLACEMENT_NOTE=Place R1092 near ITP connector (if present)

54.9

1/16W MF-LF

1%

402

U1000

N3

P5

P2

L2

P4

P1

R1

Y2

U5

R3

W6

A6

U4

Y5

U1

R4

T5

T3

W2

W5

Y4

J4

U2

V4

W3

AA4

AB2

AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22

A21

E2

AD4

AD3

AD1

AC4

G5

F1

C20

E1

H5

F21

A5

G6

E4

D20

C4

B3

C6

B4

H4

AC2

AC1

D21

K3

H2

K2

J3

L1

C1

F3

F4

G3

M4

N5

T2

V3

B2

F6

D2

D22

D3

A3

D5

AC5

AA6

AB3

A24

B25

C7

AB5

G2

AB6

FCBGA

OMIT

PENRYN

SYNC_DATE=12/12/2007

SYNC_MASTER=T18_MLB

CPU FSB

9

4.7.0

051-7898

81

FSB_A_L<6>

CPU_INTR CPU_NMI CPU_SMI_L

CPU_STPCLK_L

CPU_IGNNE_L

CPU_FERR_L

CPU_A20M_L

FSB_ADSTB_L<1>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<25> FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<20> FSB_A_L<21>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

TP_CPU_RSVD_D3

TP_CPU_RSVD_D22

TP_CPU_RSVD_D2

TP_CPU_RSVD_F6

FSB_A_L<5>

FSB_A_L<15>

FSB_A_L<10>

FSB_ADS_L

CPU_THERMD_N

FSB_A_L<11>

FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_BPRI_L

FSB_A_L<12> FSB_A_L<13>

FSB_ADSTB_L<0>

TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2

FSB_BNR_L

FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L

FSB_BREQ0_L

CPU_IERR_L

FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L

FSB_HIT_L FSB_HITM_L

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L

CPU_PROCHOT_L CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P FSB_CLK_CPU_N

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_A_L<16>

FSB_A_L<14>

FSB_A_L<4>

FSB_A_L<3>

CPU_INIT_L

FSB_LOCK_L

=PP1V05_S0_CPU

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<0> CPU_COMP<1>

CPU_TEST4

CPU_TEST2

CPU_TEST1

CPU_GTLREF

XDP_TCK

XDP_TRST_L

FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_DSTB_L_N<2> FSB_DSTB_L_P<2> FSB_DINV_L<2>

FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_DINV_L<3>

CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD

CPU_PSI_L

FSB_CPUSLP_L

TP_CPU_TEST7

TP_CPU_TEST6

TP_CPU_TEST3

TP_CPU_TEST5

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

FSB_DINV_L<1>

FSB_DSTB_L_P<1>

FSB_DSTB_L_N<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<0>

FSB_D_L<15>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

XDP_TMS

XDP_TDO

XDP_TDI

73B3

7D7

10C6 11B6 12D6

73B3

73A3

73B3

25B1 73B3

9C6

12B6 73A3

9C6

12B3 73A3

9C6

12B3 73A3

9C6

12B3 73A3

9C6

12B3 73A3

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

30.4 A (SV LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL

(BR1#)

44 A (SV Design Target)

23 A (LV Design Target)

(CPU IO POWER 1.05V)

(CPU INTERNAL PLL POWER 1.5V)

(CPU CORE POWER)

130 mA

41 A (SV HFM)

(Socket-P KEY)

4500 mA (before VCC stable) 2500 mA (after VCC stable)

62C7 73A3

PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.

1/16W

1%

100

402

MF-LF

2

1

R1101

62C7 73A3

62A5 73A3

PENRYN

OMIT

FCBGA

AE7

AE2

AF3

AE3

AF4

AE5

AF5

AD6

AF7

N6

N21

M21

K21

J21

M6

K6

J6

W21

V21

T6

T21

R6

R21

V6

G21

C26

B26

AF20

AF18

AF17

AF15

AF14

AF12

AF10

AF9

AE20

AE18

B7

AE17

AE15

AE13

AE12

AE10

AE9

AD18

AD17

AD15

AD14

A20

AD12

AD10

AD9

AD7

AC18

AC17

AC15

AC13

AC12

AC9

A18

AC7

AB7

AB20

AB18

AB17

AB15

AB14

AB12

AB10

AC10

A17

AB9

AA20

AA18

AA17

AA15

AA13

AA12

AA10

AA9

AA7

A15

F20

F18

F17

F15

F14

F12

F10

F9

F7

E20

A13

E18

E17

E15

E13

E12

E10

E9

E7

D18

D17

A12

D15

D14

D12

D10

D9

C18

C17

C15

C13

C12

A10

C10

C9

B20

B18

B17

B15

B14

B12

B10

B9

A9

A7

U1000

OMIT

PENRYN

FCBGA

V25

V22

V5

V2

U24

U21

U6

U3

T26

T23

B8

T4

T1

R25

R22

R5

R2

P24

P21

P6

P3

B6

N26

N23

N4

N1

M25

M22

M5

M2

L24

L21

AF2

L6

L3

K26

K23

K4

K1

J25

J22

J5

J2

A23

H24

H21

H6

H3

G26

G23

G1

G4

F25

F22

A19

F2

F19

F16

F13

F11

F8

F5

E24

E21

E19

A16

E16

E14

E11

E8

E6

E3

D26

D23

D19

D16

A14

D13

D11

D8

D4

D1

C25

C22

C2

C19

C16

A11

C14

C11

C8

B1

AF25

A25

AF21

C5

AF19

AF16

AF13

AF11

AF8

AF6

A2

AE26

AE23

AE19

B24

AE16

AE14

AE11

AE8

AE4

AE1

AD25

AD22

AD19

AD16

B21

AD13

AD11

AD8

AD5

AD2

AC24

AC21

AC19

AC16

AC14

B19

AC11

AC8

AC6

AC3

AB26

AB23

AB19

AB16

AB13

AB11

B16

AB8

AB4

AB1

AA25

AA22

AA19

AA16

AA14

AA11

AA8

B13

AA5

AA2

Y24

Y21

Y6

Y3

W26

W23

W4

W1

B11

A8

A4

U1000

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.

1/16W

1%

100

402

MF-LF

2

1

R1100

8110

4.7.0

051-7898

SYNC_DATE=12/12/2007

SYNC_MASTER=T18_MLB

CPU Power & Ground

CPU_VCCSENSE_N

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

CPU_VID<0> CPU_VID<1> CPU_VID<2>

=PP1V05_S0_CPU

=PP1V5_S0_CPU

CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>

=PPVCORE_S0_CPU

7D7

10D6 11D6

7D7 9D5

11B6 12D6

7B6

11B6

7D7

10B5 11D6

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACEMENT_NOTE (C1240-C1243):

VCCA (CPU AVdd) DECOUPLING

VCCP (CPU I/O) DECOUPLING

4X 330UF. 20X 22UF 0805

CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)

REMOVE C1244 & C1245

CPU VCore HF and Bulk Decoupling

REMOVE NO STUFF CAPS C1220 TO C1231

SYNC FROM T18

1x 330uF, 6x 0.1uF 0402

1x 10uF, 1x 0.01uF

PLACEMENT_NOTE (C1200-C1219):

CRITICAL

CERM-X5R

6.3V

20%

22UF

C1206

1

2

Place inside socket cavity on secondary side.

805

2.0V

D2T-SM2

PLACEMENT_NOTE=Place C1260 between CPU & NB.

POLY-TANT

CRITICAL

330UF

20%

C1260

1

23

CRITICAL

2

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1204

1

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1216

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

C1214

1

2

22UF

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1208

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1203

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1207

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

C1202

1

2

22UF

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

1

2

C1201

CRITICAL

Place inside socket cavity on secondary side.

22UF

805

20%

6.3V CERM-X5R

C1213

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1212

1

2

CERM-X5R

6.3V

20%

805

22UF

CRITICAL

Place inside socket cavity on secondary side.

C1211

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1219

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1200

1

2

C1210

CRITICAL

6.3V

Place inside socket cavity on secondary side.

CERM-X5R

20%

805

1

2

22UF

10V

402

0.1UF

20%

C1261

1

CERM

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1205

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1209

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1215

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1217

1

2

10V

402

0.1UF

CERM

20%

C1262

1

2

C1263

10V

402

0.1UF

CERM

20%

1

2

10V

402

0.1UF

CERM

20%

C1264

1

2

0.1UF

CERM

10V

402

20%

C1265

1

2

10V

402

0.1UF

CERM

20%

C1266

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1218

1

2

PLACEMENT_NOTE=Place C1281 near CPU pin B26.

10%

402

CERM

16V

0.01UF

C1251

1

2

6.3V

603

X5R

20%

10uF

C1250

1

2

470UF-4MOHM

CRITICAL

Place on secondary side.

NOSTUFF

20%

1

C1240

32

D2T-SM

POLY-TANT

2.0V

470UF-4MOHM

CRITICAL

Place on secondary side.

D2T-SM

20%

2.0V POLY-TANT

32

1

C1241

CRITICAL

C1242

470UF-4MOHM

Place on secondary side.

32

1

D2T-SM

POLY-TANT

20%

2.0V

CRITICAL

Place on secondary side.

32

1

D2T-SM

470UF-4MOHM

2.0V

20%

POLY-TANT

C1243

CPU Decoupling

SYNC_DATE=03/31/2008

SYNC_MASTER=RAYMOND

8111

4.7.0

051-7898

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

7D7 9D5

10C6 12D6

7B6

10B6

7D7

10B5 10D6

IN

BI

OUT

IN

BI

IN

OUT

BI

OUT

IN

OUT

NC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TDI

OBSDATA_C1

PWRGD/HOOK0

TCK1 TCK0

OBSDATA_A3

OBSFN_C0

OBSDATA_C0

Mini-XDP Connector

Please avoid any obstructions on even-numbered side of J1300

NOTE: This is not the standard XDP pinout.

VCC_OBS_AB

OBSFN_D0

SCL

SDA

HOOK3

HOOK1

TMS

OBSDATA_B2

OBSFN_D1

OBSDATA_B3

XDP_PRESENT#

OBSFN_B0

OBSFN_C1

998-1571

ITPCLK/HOOK4

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1OBSDATA_B1

OBSFN_B1

OBSDATA_A0

OBSFN_A1

OBSFN_A0

Use with 920-0620 adapter board to support CPU, MCP debugging.

OBSDATA_B0

OBSDATA_A1

OBSDATA_A2

Direction of XDP module

ITPCLK#/HOOK5 VCC_OBS_CD

OBSDATA_C3

OBSDATA_D0

HOOK2

RESET#/HOOK6

TDO

DBR#/HOOK7 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

TRSTn

OBSDATA_C2

MCP79-specific pinout

9B2

13A3 73C3

R1399

12

1/16W

5%

XDP

MF-LF

402

1K

20C3 43D8 76B3

R1315

1

2

XDP

402

1%

1/16W

54.9

MF-LF

C1300

1

2

X5R

10% 16V

XDP

0.1uF

402

C1301

1

2

402

16V

XDP

0.1uF

10%

X5R

9C5

73A3

9C6

73A3

9A6 9C6

73A3

9D6

13A3 73C3

402

MF-LF

1/16W

5%

1K

R1303

PLACEMENT_NOTE=Place close to CPU to minimize stub.

XDP

12

9C6

73A3

9C6

73A3

9C6

73A3

9C6

73A3

20B7

18D7 76D3

20B7

13B3 73B3

9A6 9C6

73A3

9B6 9C6

73A3

9B6 9C6

73A3

9C6

24A3

18C4

2

51

49

47

45

44

15

17

19

54

12

53

LTH-030-01-G-D-NOPEGS

XDP_CONN CRITICAL

J1300

F-ST-SM

59

57

55

41

43

35

39

37

31

33

25

27

29

21

23

13

11

9

7

5

1

34

6

8

10

14

20

16

18

22

24

26

30

28

34

32

38

40

36

42

46

48

50

56

52

58

60

9B6 9C6

73A3

20B7

eXtended Debug Port(MiniXDP)

81

4.7.0

12

SYNC_MASTER=K19_MLB

051-7898

SYNC_DATE=11/07/2008

MCP_DEBUG<4>

XDP_TDO

JTAG_MCP_TDO

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<3>

MCP_DEBUG<3>

=PP3V3_S0_XDP

XDP_CPURST_L

FSB_CLK_ITP_P FSB_CLK_ITP_N

XDP_DBRESET_L

XDP_TRST_L XDP_TDI XDP_TMS

JTAG_MCP_TMS

MCP_DEBUG<2>

JTAG_MCP_TDI

MCP_DEBUG<5>

MCP_DEBUG<6> MCP_DEBUG<7>

JTAG_MCP_TRST_L

FSB_CPURST_L

MCP_DEBUG<1>

MCP_DEBUG<0>

XDP_TCK

SMBUS_MCP_0_DATA

JTAG_MCP_TCK

PM_LATRIGGER_L

=PP1V05_S0_CPU

XDP_OBS20

TP_XDP_OBSDATA_B3

XDP_PWRGD

TP_XDP_OBSDATA_B2

TP_XDP_OBSDATA_B1

TP_XDP_OBSFN_B1

TP_XDP_OBSFN_B0

XDP_BPM_L<2>

XDP_BPM_L<4>

CPU_PWRGD

SMBUS_MCP_0_CLK

TP_XDP_OBSDATA_B0

XDP_BPM_L<5>

7C5

73A3

7D7 9D5

10C6 11B6

IN

OUT

BI

IN

BI

OUT

IN

BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32#

CPU_A22# CPU_A23# CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2# CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6# CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15# CPU_A16#

CPU_A19#

CPU_A17# CPU_A18#

CPU_A20# CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT# CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0# CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4# CPU_D5# CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17# CPU_D18#

CPU_D16#

CPU_D19# CPU_D20# CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39# CPU_D40# CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44# CPU_D45# CPU_D46# CPU_D47#

CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK# CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY# CPU_DRDY#

CPU_REQ1#

FSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

270 mA (A01)

206 mA

15 mA

29 mA

20 mA

(MCP_BSEL<0>)

(MCP_BSEL<1>)

(MCP_BSEL<2>)

Loop-back clock for delay matching.

8B1

9C8

73C3

9D6

12C2 73C3

9B2

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9C4

73D3

9B4

73D3

9B4

73D3

9B4

73D3

9B4

73D3

9B4

73D3

9B4

73D3

9B4

73D3

9B4

73D3

9B4

73D3

9B4

73D3

9B4

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9B2

73D3

9B2

73D3

9B2

73D3

9B2

73D3

9B2

73D3

9B2

73D3

9B2

73D3

9B2

73D3

9B2

73D3

9B2

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C8

73C3

9C4

73D3

9C4

73D3

9C4

73D3

9B4

73D3

9B4

73D3

9B4

73D3

9C2

73D3

9C2

73D3

9C2

73D3

9B2

73D3

9B2

73D3

9B2

73D3

9D8

73D3

9C8

73C3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D8

73D3

9D6

73C3

9D6

73C3

9D6

73C3

9D6

73C3

9D6

73C3

9D6

73C3

9D6

73C3

9D6

73C3

9D6

73C3

9D6

73C3

9D6

73C3

9D6

73C3

9B6

73B3

9B6

73B3

12C3 73B3

9D6

73C3

9D6

73C3

9C8

73C3

9C8

73C3

9D6

73C3

9C8

73C3

9B8

73C3

9B8

73B3

9B2

12C7 73C3

9B2

73B3

9B2

73B3

9B2

73B3

9C8

73B3

9B2

62C7 73B3

8C4

9C5

41D4 62C8 73C3

9C6

41C4 73B3

9C8

73C3

9C8

73C3

2

1

R1436

MF-LF 402

1% 1/16W

49.9

2

1

R1431

49.9

MF-LF

402

1%

1/16W

2

1

R1430

1/16W

1%

402

MF-LF

49.9

2

1

R1435

MF-LF 402

1% 1/16W

49.9

2

1

R1422

MF-LF

1/16W

5%

402

1K

NO STUFF

2

1

R1421

1/16W

5%

MF-LF

402

NO STUFF

1K

2

1

R1420

1/16W

NO STUFF

MF-LF

402

5%

1K

2

1

R1415

5%

62

MF-LF

402

1/16W

2

1

R1410

1%

54.9

MF-LF

402

1/16W

2

1

R1440

5%

MF-LF 402

1/16W

150

NO STUFF

AH27

AG28

AH28

AG27

AE41

AG43

AG42

AH41

AM33

AC42

AB41

AC41

H38

AC35

AC33

AC39

AA33

AC38

AH43

AJ41

E41

AG41

AC43

AF42

AH42

AH39

AD40

AB42

AH40

M39

N37

W39

T40

M41

L36

W37

U40

AD41

AM32

AN33

AN32

AA40

AD39

J41

N35

V35

V41

U41

P42

Y42

M43

H39

J40

K41

Y41

H42

H43

L41

H41

K42

H40

M40

N40

N41

P41

V42

M42

L42

J37

J38

J39

N38

N36

L38

L39

L37

Y39

R38

R37

R39

P35

R35

R34

N33

N34

U37

R33

W41

W38

U34

U33

U35

U36

U38

AA35

AA38

AA34

AA36

Y40

W34

W33

AA37

W35

T43

R41

T41

T42

T39

R42

W42

Y43

AM43

AM42

F42

D42

F41

AL32

AE40

AA41

AD43

AK35

AE36

AD42

AB35

AE35

AE37

AC37

AE34

AE38

AN35

AR39

AN34

AL35

AL38

AJ34

AC34

AN37

AL34

AL37

AJ38

AJ36

AJ37

AJ35

AN36

AJ33

AF41

AL33

AG33

AL39

AN38

AG34

AG38

AG37

AE33

AG39

AG35

AF35

AM39

AM40

AL41

AK42

AL43

AL42

G42

G41

AJ40

AK41

U1400

BGA

(1 OF 11)

MCP79-TOPO-B

OMIT

2

1

R1416

5%

62

MF-LF 402

1/16W

SYNC_MASTER=T18_MLB

13 81

051-7898

MCP CPU Interface

SYNC_DATE=04/04/2008

4.7.0

=MCP_BSEL<1> =MCP_BSEL<0>

=MCP_BSEL<2>

=PP1V05_S0_MCP_FSB

FSB_BREQ1_L

FSB_ADS_L

FSB_BREQ0_L

CPU_FERR_L

FSB_RS_L<0>

FSB_BNR_L

FSB_DRDY_L

FSB_DBSY_L

FSB_A_L<33> FSB_A_L<34>

FSB_A_L<25>

FSB_A_L<10>

FSB_D_L<7>

FSB_D_L<14>

PP1V05_S0_MCP_PLL_FSB

=PP1V05_S0_MCP_FSB

FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_DINV_L<0>

FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_DINV_L<1>

FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> FSB_DINV_L<2>

FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> FSB_DINV_L<3>

FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32>

FSB_A_L<35>

FSB_ADSTB_L<0> FSB_ADSTB_L<1>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_TRDY_L

CPU_PECI_MCP CPU_PROCHOT_L

FSB_RS_L<1> FSB_RS_L<2>

MCP_BCLK_VML_COMP_VDD

MCP_CPU_COMP_VCC MCP_CPU_COMP_GND

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6>

FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12>

FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37>

FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42>

FSB_D_L<44>

FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

FSB_BPRI_L FSB_DEFER_L

FSB_CLK_CPU_P FSB_CLK_CPU_N

FSB_CLK_ITP_P FSB_CLK_ITP_N

FSB_CLK_MCP_N

FSB_CLK_MCP_P

CPU_A20M_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_SMI_L

CPU_PWRGD FSB_CPURST_L

FSB_CPUSLP_L

CPU_STPCLK_L CPU_DPRSTP_L

FSB_D_L<45>

FSB_D_L<43>

FSB_D_L<38>

CPU_DPSLP_L FSB_DPWR_L

MCP_BCLK_VML_COMP_GND

FSB_D_L<13>

PM_THRMTRIP_L

7D7

13A2 21D3 22C8

73C3

22C2

7D7

13B7 21D3 22C8

73B3

0A

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1 MCKE0A_0

MODT0A_1 MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8 MA0_7

MA0_9

MA0_10

MA0_11

MA0_13 MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2 MDQM0_1 MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4 MDQ0_3 MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12

MDQ0_16

MDQ0_21 MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22

MDQ0_26

MDQ0_29 MDQ0_28 MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35 MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40 MDQ0_39

MDQ0_42

MDQ0_47 MDQ0_46

MDQ0_43

MDQ0_45 MDQ0_44

MDQ0_51 MDQ0_50 MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55 MDQ0_54 MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61 MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

BI

OUT

BI

OUT

MEMORY

CONTROL

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60 MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56 MDQ1_55 MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51 MDQ1_50

MDQ1_48 MDQ1_47 MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42 MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36 MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31 MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11 MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6 MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4 MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N MDQS1_0_P MDQS1_0_N

MRAS1# MCAS1#

MWE1#

MBA1_2 MBA1_1 MBA1_0

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1# MCS1A_0#

MCLK1A_0_N

MODT1A_1 MODT1A_0

MCKE1A_0

MCKE1A_1

BI

OUT

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AR17

AV17

AP15

AV15

AL10

AL11

AR8

AR9

AW7

AW8

AP13

AR13

AV25

AW25

AU30

AU29

AT35

AU35

AU39

AT39

AN5

AU5

AR10

AN13

AN27

AW29

AV35

AR34

AT37

AU37

AW39

AL8

AL9

AP9

AN9

AV39

AL6

AL7

AN6

AN7

AR6

AR7

AV6

AW5

AN10

AR5

AR37

AU6

AV5

AU7

AU8

AW9

AP11

AW6

AY5

AU9

AV9

AR38

AU11

AV11

AV13

AW13

AR11

AT11

AR14

AU13

AR26

AU25

AV38

AT27

AU27

AP25

AR25

AP27

AR27

AP29

AR29

AP31

AR31

AW38

AV27

AN29

AV29

AN31

AU31

AR33

AV37

AW37

AT31

AV31

AR35

AP35

AT15

AR18

AW33

AV33

BA24

AY24

BB20

BC20

AU23

AT23

AP17

AP23

AP19

AW17

AV21

AR22

AU21

AP21

AR21

AN21

AV19

AU19

AR23

AU15

AN23

AW21

AN19

AT19

AR19

U1400

(2 OF 11)

OMIT

MCP79-TOPO-B

BGA

26B5 74C3

26A7 74C3

26B7 74C3

26B5 74C3

26C2 74C3

26B4 74C3

26C2 74C3

26C4 74D3

26D4 74D3

26A5 74D3

26B7 74D3

26A7 74D3

26B5 74D3

26B7 74D3

26B5 74D3

26B7 74D3

26B5 74D3

26B7 74D3

26B5 74D3

26B7 74D3

26B5 74D3

26B7 74D3

26C5 74D3

26B5 74D3

26B7 74D3

26C7 74D3

26C2 74D3

26C4 74D3

26C2 74D3

26C4 74D3

26B4 74D3

26B2 74D3

26C4 74D3

26B2 74D3

26C2 74D3

26B4 74D3

26C4 74D3

26C2 74D3

26C4 74D3

26C2 74D3

26C4 74D3

26C2 74D3

26C4 74D3

26D2 74D3

26C2 74D3

26D4 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26D5 74D3

26D7 74D3

26A5 74C3

26B7 74C3

26B5 74C3

26B7 74C3

26C4 74C3

26C2 74C3

26B2 74C3

26C4 74C3

26D2 74C3

26C2 74C3

27A5 74A3

27B7 74A3

27B5 74A3

27B7 74A3

27B2 74A3

27B7 74A3

27C2 74A3

27C4 74A3

27C2 74A3

27D2 74A3

27B5 74B3

27A5 74B3

27A7 74B3

27B5 74B3

27A7 74B3

27A5 74B3

27B7 74B3

27B5 74B3

27B7 74B3

27B5 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C5 74C3

27C7 74C3

27C7 74B3

27C5 74B3

27D5 74B3

27D7 74B3

BA16

AW16

BB13

AY15

AT2

AT1

AY2

AY1

BB6

BA6

BA10

AY11

BB33

BA33

BB37

BA37

BA43

AY42

AT42

AT43

AT5

BA2

AY7

BA11

BB34

BB38

AY43

AR42

AW42

AW41

AT40

AT4

AT3

AV2

AV3

AT41

AR4

AR3

AU2

AU3

AY4

AY3

BB3

BC3

AW4

AW3

AP41

BA3

BB2

BB5

BA5

BA8

BC8

BB4

BC4

BA7

AY8

AN40

BA9

BB10

BB12

AW12

BB8

BB9

AY12

BA12

BC32

AW32

AU40

BA35

AY36

BA32

BB32

BA34

AY35

BC36

AW36

BA39

AY40

AU41

BA36

BB36

BA38

AY39

BB40

AW40

AV42

AV41

BA40

BC40

AR41

AP42

BB14

BB16

BA42

BB42

BB22

BA22

BA19

AY19

AY31

BB30

BA15

BB29

BB18

BB17

BB28

AY28

BA28

AY27

BA27

BA26

BB26

BA25

BA29

BA14

AW28

BC28

BA17

BB25

BA18

U1400

(3 OF 11)

OMIT

MCP79-TOPO-B

BGA

27B7 74B3

27B5 74B3

27B7 74B3

27B5 74B3

27B7 74B3

27C7 74B3

27B5 74B3

27C5 74B3

27B7 74B3

27B5 74B3

27B7 74B3

27B5 74B3

27B4 74B3

27B2 74B3

27C2 74B3

27C4 74B3

27B2 74B3

27B4 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27D2 74B3

27C4 74B3

27D4 74B3

27C2 74B3

27A7 74B3

27D4 74B3

27B5 74B3

27B7 74B3

27B5 74B3

27B4 74B3

27C2 74B3

27C4 74B3

MCP Memory Interface

SYNC_DATE=04/04/2008

SYNC_MASTER=T18_MLB

14

4.7.0

051-7898

81

MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<0> MEM_A_DQS_N<0>

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

MEM_A_BA<2> MEM_A_BA<1> MEM_A_BA<0>

MEM_A_A<14> MEM_A_A<13> MEM_A_A<12> MEM_A_A<11> MEM_A_A<10> MEM_A_A<9> MEM_A_A<8> MEM_A_A<7> MEM_A_A<6> MEM_A_A<5> MEM_A_A<4> MEM_A_A<3> MEM_A_A<2> MEM_A_A<1> MEM_A_A<0>

TP_MEM_A_CLK2P TP_MEM_A_CLK2N

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CS_L<1> MEM_A_CS_L<0>

MEM_A_ODT<1> MEM_A_ODT<0>

MEM_A_CKE<1> MEM_A_CKE<0>

MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0>

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0>

MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>

TP_MEM_B_CLK2P TP_MEM_B_CLK2N

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CS_L<1> MEM_B_CS_L<0>

MEM_B_ODT<1> MEM_B_ODT<0>

MEM_B_CKE<1> MEM_B_CKE<0>

MEM_A_DQ<63> MEM_A_DQ<62> MEM_A_DQ<61> MEM_A_DQ<60> MEM_A_DQ<59> MEM_A_DQ<58> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<48> MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<41> MEM_A_DQ<40> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<31> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<1> MEM_A_DQ<0>

MEM_A_DM<7> MEM_A_DM<6> MEM_A_DM<5> MEM_A_DM<4> MEM_A_DM<3> MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>

MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<31> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<16> MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9> MEM_B_DQ<8> MEM_B_DQ<7> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<4> MEM_B_DQ<3> MEM_B_DQ<2> MEM_B_DQ<1> MEM_B_DQ<0>

MEM_B_DM<7> MEM_B_DM<6> MEM_B_DM<5> MEM_B_DM<4> MEM_B_DM<3> MEM_B_DM<2> MEM_B_DM<1> MEM_B_DM<0>

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55 GND56 GND57 GND58

GND60

GND59

GND61 GND62 GND63 GND64

GND52 GND53 GND54

GND51

GND49 GND50

GND48

GND47

GND46

GND44 GND45

GND43

GND42

GND41

GND39 GND40

GND38

GND37

GND36

GND35

GND33 GND34

GND32

GND31

GND30

GND28 GND29

GND27

GND26

GND25

GND24

GND18 GND19

GND17

GND16

GND15

GND13 GND14

GND10

GND12

GND11

GND8 GND9

GND7

GND6

GND5

GND2 GND3 GND4

GND1

MEM_COMP_VDD MEM_COMP_GND

MODT0B_0 MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0# MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE +V_VPLL

+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8

+VDD_MEM9 +VDD_MEM10 +VDD_MEM11

+VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34

+VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41

+VDD_MEM43 +VDD_MEM44 +VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22 GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

87 mA (A01)

39 mA

TP or NC for DDR2.

19 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

12 mA

17 mA

4771 mA (A01, DDR3)

2

1

R1610

MF-LF

402

1/16W

40.2

1%

2

1

R1611

40.2

1/16W

1%

402

MF-LF

BC29

AN16

AM29

AM27

AM25

AM31

AL30

BC25

AW24

AW19

AY26

AM23

AY25

AU18

AM15

AY18

AY17

AV20

BC17

AW27

AU22

AU20

AM21

AV24

AY29

AT21

AU24

AN18

AU16

AP18

AP22

AW15

AR24

AM19

AR20

AR16

AV16

AP24

AP20

AN22

AP16

AT17

AN24

AN20

AM17

T28

T27

U28

U27

AY32

BC13

AY16

AN15

AN17

AN41

AM41

BA13

BC16

AR15

AU17

BA41

BB41

AY23

BA23

BA20

AY20

AU33

AU34

BB24

BC24

BA21

BB21

BA31

BA30

AN25

AV23

W5

V34

V10

U22

U20

U18

T9

T7

T6

T38

T37

T35

T34

T33

T26

T24

AK11

T20

T18

T10

R5

R43

R40

R36

P7

P40

P4

P37

P34

P33

P10

N8

N39

M9

M7

M6

M5

M38

K7

H31

G32

G30

F24

D34

BC9

AY9

BC21

F28

AU10

AR36

AP30

AT25

AP12

AM28

AK7

AH35

AG24

AF24

AE20

AD22

AB7

AB22

AA39

AA22

U1400

BGA

OMIT

MCP79-TOPO-B

(4 OF 11)

28C6

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

051-7898

4.7.0

8115

MCP Memory Misc

MCP_MEM_COMP_VDD

=PP1V8R1V5_S0_MCP_MEM

TP_MEM_B_ODT<3>

TP_MEM_B_ODT<2>

TP_MEM_B_CS_L<3>

TP_MEM_B_CLK3N

TP_MEM_B_CLK3P

TP_MEM_B_CLK4N

TP_MEM_B_CLK4P

TP_MEM_B_CLK5N

TP_MEM_B_CLK5P

PP1V05_S0_MCP_PLL_CORE

TP_MEM_A_CS_L<3>

TP_MEM_A_CS_L<2>

TP_MEM_A_CLK3N

TP_MEM_A_CLK4P

TP_MEM_A_CLK5N

TP_MEM_A_CLK5P

TP_MEM_A_CKE<3>

TP_MEM_A_CKE<2>

TP_MEM_A_ODT<3>

TP_MEM_A_ODT<2>

TP_MEM_A_CLK3P

TP_MEM_A_CLK4N

MCP_MEM_COMP_GND

=PP1V8R1V5_S0_MCP_MEM

MCP_MEM_RESET_L

TP_MEM_B_CS_L<2>

TP_MEM_B_CKE<2> TP_MEM_B_CKE<3>

74A3

7B6

15C3 22C8

22B2

74A3

7B6

15C7 22C8

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7 +AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N PE0_TX15_P

PE0_TX13_N PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N

PE0_TX6_P

PE0_TX4_N

PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_P

PED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT

IN

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

57 mA (A01, DVDD0 & 1)

Int PU

84 mA (A01)

Int PU

206 mA (A01, AVDD0 & 1)

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX. If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

Int PU (S5)

K11

A11

M19

M17

M18

M16

L16

B10

M15

C10

E8

D9

D5

F17

N14

M14

L14

K14

J13

H13

G13

F13

J11

J10

B6

C6

A7

B7

B8

A8

D8

C8

H7

G7

F9

E9

H9

G9

K9

J9

G11

F11

H3

H2

G3

H4

F3

F4

E2

F2

D2

E1

C1

D1

B3

B2

A4

A3

C4

B4

M2

M1

M4

M3

L4

L3

K2

K3

J2

J3

H1

J1

C5

D4

L11

L10

J5

J4

J7

J6

G5

H5

C3

D3

E4

E3

E5

F5

E6

F6

D7

C7

N5

N4

N7

N6

N9

P9

N11

N10

L7

L6

L9

L8

F7

E7

E11

D11

C9

T16

U19

T19

U16

W18

W17

W16

V19

U17

W19

T17

P13

N13

M13

U12

T12

R12

P12

M12

AB12

AA12

W12

V12

AD12

AC12

Y12

U1400

BGA

OMIT

(5 OF 11)

MCP79-TOPO-B

N12

L18

8D6

6D5

29C7 75D3

6D5

29C7 75D3

8C6

35D3

6D5

29C7

34C1 75D3

8D6

29D7

8D6

29C5 75D3

34C1 75D3

34C2

8D6

8C6

29C5 75D3

8D6

2

1

R1710

PLACEMENT_NOTE=Place within 12.7mm of U1400

NO STUFF

1/16W

1%

MF-LF 402

2.37K

24C4

8C4

30B7

SYNC_DATE=04/04/2008

051-7898

4.7.0

8116

MCP PCIe Interfaces

SYNC_MASTER=T18_MLB

=PEG_R2D_C_P<11> =PEG_R2D_C_N<11>

=PEG_R2D_C_N<9>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<13>

PCIE_EXCARD_PRSNT_L

MINI_CLKREQ_L

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_DVDD1

=PEG_D2R_P<0>

=PEG_D2R_N<2>

PP1V05_S0_MCP_PLL_PEX

=PEG_D2R_N<0>

=PEG_D2R_P<2>

=PEG_D2R_P<4>

=PEG_D2R_P<6>

TP_PCIE_PE4_R2D_CN

TP_PCIE_PE4_R2D_CP

PCIE_EXCARD_R2D_C_N

PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_FW_R2D_C_P

TP_PCIE_CLK100M_PE6N

PCIE_RESET_L

PCIE_MINI_R2D_C_P

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

PEG_CLK100M_N

PEG_CLK100M_P

PCIE_CLK100M_MINI_P

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14> =PEG_R2D_C_P<15>

=PEG_R2D_C_N<13> =PEG_R2D_C_P<14>

=PEG_R2D_C_N<12>

=PEG_R2D_C_P<12>

=PEG_R2D_C_N<10>

=PEG_R2D_C_P<10>

=PEG_R2D_C_N<8> =PEG_R2D_C_P<9>

=PEG_R2D_C_N<7>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<6>

=PEG_R2D_C_N<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_N<4> =PEG_R2D_C_P<5>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_N<2>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<1>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<0>

MCP_PEX_CLK_COMP

PEG_PRSNT_L

=PEG_D2R_N<13> =PEG_D2R_P<14>

=PEG_D2R_P<15>

=PEG_D2R_N<14>

=PEG_D2R_N<15>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_D2R_P<13>

=PEG_D2R_N<11>

=PEG_D2R_N<12>

=PEG_D2R_N<10>

=PEG_D2R_P<8>

=PEG_D2R_P<9>

=PEG_D2R_P<10>

=PEG_D2R_N<8>

=PEG_D2R_N<9>

=PEG_D2R_N<5>

=PEG_D2R_P<7>

=PEG_D2R_N<6>

=PEG_D2R_N<7>

=PEG_D2R_P<3>

=PEG_D2R_P<5>

=PEG_D2R_N<3>

=PEG_D2R_N<4>

=PEG_D2R_P<1> =PEG_D2R_N<1>

PCIE_CLK100M_EXCARD_P

EXCARD_CLKREQ_L

AUD_IP_PERIPHERAL_DET GMUX_JTAG_TCK_L

=PP1V05_S0_MCP_PEX_DVDD0

PCIE_EXCARD_D2R_N

PCIE_EXCARD_D2R_P

TP_PCIE_PE4_D2RN

TP_PCIE_PE4_D2RP

PCIE_FW_D2R_N

PCIE_FW_D2R_P

PCIE_MINI_D2R_N

PCIE_MINI_D2R_P

PCIE_WAKE_L

GMUX_JTAG_TDO

CARDREADER_RESET

PCIE_FW_PRSNT_L

TP_PE4_PRSNT_L

TP_PE4_CLKREQ_L

FW_CLKREQ_L

PCIE_MINI_PRSNT_L

7A6

22C2

75C3

57A4

7A6

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1 +3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

BI

OUT

BI

OUT

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

190 mA (A01, 1.8V)

C / Pr

MCP79 requires a S5 pull-up.

Comp / Pb

206 mA (A01)

103 mA

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable:

Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1

0MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This avoids a leakage issue since

RGB ONLY

5 mA (A01)

DisplayPort

DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

DP_IG_DDC_CLK

TP_DP_IG_AUX_CHP/N

TMDS_IG_DDC_DATA

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N

TMDS/HDMI

=MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N<0>

MCP Signal

=MCP_HDMI_DDC_CLK

=MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2>

=MCP_HDMI_DDC_DATA

TMDS_IG_HPD

=MCP_HDMI_HPD DP_IG_AUX_CH_P/N

8 mA 8 mA

16 mA (A01)

95 mA (A01)

LVDS: Power +VDD_IFPx at 1.8V

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

DP_IG_AUX_CH_P/N

DP_IG_HPD

DP_IG_DDC_DATA

DP_IG_ML_P/N<0>

Interface Mode

be used to provide HDMI or dual-channel TMDS without

NOTE: HDMI port requires level-shifting. IFP interface can

level-shifters.

NOTE: 20K pull-down required on DP_HPD_DET. NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

(See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.

Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal

22A4

31B6 77D3

32A5 77D3

31C1 77D3

31B1 77D3

31B7 77C3

8D4

71A7 72B7

68C8

72B7 72C8

69D3

69C7 75B3

8B4

69D3

23C7 75B3

8D4

2

1

R1810

49.9

402

MF-LF

1/16W

1%

2

1

R1811

1%

402

49.9

MF-LF

1/16W

69A5

8D4

8C4

D38

C38

C37

A35

E36

A36

D36

B36

C36

D25

C25

C24

B24

C26

D24

A24

E24

B23

C23

C22

A23

G23

C21

D21

J22

A41

B38

C39

B39

A40

A39

B40

M26

M27

T25

K32

J32

M28

M29

V23

U23

T23

K24

J24

E28

F23

J23

B22

C27

B27

B26

F40

E37

G39

N30

M30

L30

K30

L29

K29

J29

H29

L31

K31

G31

E32

B34

C34

D33

C33

D32

C32

B32

A32

B35

C35

F31

C31

J30

J33

H33

F33

G33

G35

F35

D35

E35

J31

B15

E16

D43

C43

E31

B30

A31

D31

C30

B31

E23

U1400

OMIT

MCP79-TOPO-B

BGA

(6 OF 11)

2

1

R1850

MF-LF

5% 1/16W

402

10K

2

1

R1861

MF-LF

1/16W

100K

5%

402

2

1

R1860

100K

1/16W

5%

MF-LF

402

42C3

2

1

R1820

1/16W MF-LF

402

47K

5%

31C6 77D3

68B3 75B3

6C7

68C2 75B3

6C7

68C2 75B3

6C7

68C2 75B3

31C6 77D3

6C7

68C2 75B3

6C7

68C2 75B3

6C7

68C2 75B3

8D4

8C4

31C6 77D3

8C4

6C7

68C5

6C7

68C5

69D3

23C6 75B3

31C6 77D3

23C6 75B3

31C8 77D3

31B6 77C3

31B6 77D3

MCP Ethernet & Graphics

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

051-7898

4.7.0

8117

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXD_P<1> =MCP_HDMI_TXD_N<1> =MCP_HDMI_TXD_P<2>

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_N<3>

MCP_HDMI_RSET MCP_HDMI_VPROBE

DP_IG_CA_DET

PP1V05_ENET_MCP_PLL_MAC

=PP1V05_S0_MCP_HDMI_VDD

PP3V3_S0_MCP_VPLL

=PP3V3R1V8_S0_MCP_IFP_VDD

PP3V3_S0_MCP_DAC

MCP_MII_COMP_GND

MCP_MII_COMP_VDD

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

=MCP_HDMI_TXC_P

=MCP_HDMI_TXD_N<2>

MCP_CLK27M_XTALIN

LVDS_IG_DDC_DATA

LVDS_IG_DDC_CLK

MCP_TV_DAC_VREF

DP_IG_AUX_CH_P DP_IG_AUX_CH_N

=MCP_HDMI_HPD

ENET_MDIO

MCP_CLK25M_BUF0_R

MCP_DDC_DATA0

MCP_DDC_CLK0

TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR CRT_IG_G_Y_Y

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<2>

LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_N<2> LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3>

=MCP_HDMI_DDC_DATA

=MCP_HDMI_DDC_CLK

MCP_IFPAB_RSET MCP_IFPAB_VPROBE

MCP_TV_DAC_RSET

ENET_RXD<0>

TP_ENET_INTR_L

ENET_RXD<3>

ENET_RX_CTRL

ENET_CLK125M_RXCLK

ENET_RXD<2>

ENET_RXD<1>

ENET_RESET_L

ENET_MDC

TP_ENET_PWRDWN_L

=MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS

CRT_IG_B_COMP_PB

CRT_IG_HSYNC CRT_IG_VSYNC

MCP_MII_VREF

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<3>

ENET_TXD<2>

ENET_TXD<1>

ENET_TXD<0>

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

=PP3V3_S5_MCP_GPIO

=PP1V05_ENET_MCP_RMGT

LPCPLUS_GPIO

TP_MCP_RGB_DAC_VREF

TP_MCP_RGB_DAC_RSET

MCP_CLK27M_XTALOUT

LVDS_IG_BKL_PWM

=DVI_HPD_GMUX_INT

22A6

7D7

23D7

23C5

7B6

23D7

23D2

77D3

7B5

17D7 22A5 22B6

7C5

18D1 20A4

7B5

17D3 22A5 22B6

7A3

19C1

7A5

22D6

OUT

BI

LPC PCIGND

PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0# LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5 PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10 PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15 PCI_AD16 PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21 PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66 GND67

GND69

GND68

GND70 GND71 GND72

GND74

GND73

GND75 GND76 GND77

GND79

GND78

GND80 GND81

GND84

GND83

GND82

GND85 GND86 GND87

GND89

GND88

GND90 GND91 GND92

GND94

GND93

GND95 GND96 GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR# PCI_STOP#

PCI_RESET0# PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105 GND106 GND107

GND109

GND108

GND110 GND111 GND112

GND115

GND114

GND113

GND116 GND117

GND120

GND119

GND118

GND121 GND122 GND123

GND125

GND124

GND126 GND127 GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0# PCI_REQ1#/FANRPM2

IN

BI

OUT

IN

OUT

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Int PU (S5)

Int PU

Strap for Boot ROM Selection (See HDA_SDOUT)

40C8 42D5 76C3

24D4 76C3

40C8 42D5 76C3

40C8 42D3 76C3

Y3

Y2

AA7

R11

R10

T4

U9

T3

V9

T2

T1

AB9

Y1

AA10

N1

N2

N3

P2

P3

U11

R4

U10

R3

Y4

AA9

AD11

R9

R8

R7

R6

W10

AA11

AA6

AA3

AA2

AC8

AC7

AB2

AC6

AB3

U7

T5

AE11

U6

U1

U5

U2

W11

U3

W9

V2

W8

V3

AC4

W7

W4

W6

W3

Y5

AA5

AA1

AC11

AC10

AC9

AE10

AC3

AE6

AE5

AE12

AD4

AE2

AE1

AE9

AD5

AD1

AD2

AD3

Y27

Y26

Y25

Y24

Y22

Y20

Y19

Y18

Y17

Y16

W43

W40

W36

W24

W22

W20

V7

V40

V4

V37

V33

V28

V27

V26

V24

V22

V20

V18

V17

V16

U8

U4

U39

U26

U24

AD34

AD33

AD28

AD27

AD26

AD25

AD24

AD20

AD19

AD18

AD17

AD16

AC5

AB33

AC40

AC36

AC22

AB40

AB4

AB37

AB34

AB28

AB27

AB26

AB25

AB24

AB23

AB21

AB20

H34

AB18

U1400

OMIT

MCP79-TOPO-B

(7 OF 11)

BGA

40C5 42D5

40C8 42D3 24B4 76C3

40C5 42D3

2

1

R1910

22

5% 1/16W

402

MF-LF

PLACEMENT_NOTE=Place close to pin R8

21

R1989

8.2K

5%

1/16W MF-LF

402

21

R1991

8.2K

5%

1/16W MF-LF

402

21

R1990

8.2K

5%

1/16W MF-LF

402

21

R1994

8.2K

5%

1/16W MF-LF

402

21

R1992

402

MF-LF1/16W

5%

8.2K

18D2

2

1

R1961

10K

5% 1/16W

402

MF-LF

21

R1960

5%

22

402

MF-LF1/16W

21

R1950

402

22

MF-LF1/16W

5%

21

R1951

402

22

MF-LF1/16W

5%

21

R1952

402

MF-LF1/16W

5%

22

21

R1953

22

5%

1/16W MF-LF

402

24C4

8C2

18D2

18D2 35A4 35C4 35C7 35D6

12C6

12C3 76D3

57D3

8C4

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

MCP PCI & LPC

18 81

4.7.0

051-7898

TP_PCI_AD<14>

TP_PCI_AD<21>

TP_PCI_INTX_L

TP_PCI_TRDY_L

LPC_SERIRQ

TP_PCI_AD<20>

TP_PCI_AD<15>

TP_PCI_AD<9>

MCP_DEBUG<5>

MCP_DEBUG<4>

TP_PCI_AD<23> TP_PCI_AD<24>

TP_PCI_AD<26>

PM_LATRIGGER_L

TP_PCI_AD<11>

TP_PCI_AD<13>

GMUX_JTAG_TDI

GMUX_JTAG_TMS

TP_PCI_INTZ_L

FW_PME_L TP_LPC_DRQ0_L

PM_CLKRUN_L

=PP3V3_S0_MCP_GPIO

MCP_RS232_SIN_L

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<3>

MCP_DEBUG<2>

MCP_DEBUG<1>

MCP_DEBUG<0>

MCP_RS232_SIN_L

AUD_IPHS_SWITCH_EN

FW_PWR_EN

TP_PCI_AD<12>

TP_PCI_AD<16> TP_PCI_AD<17> TP_PCI_AD<18> TP_PCI_AD<19>

TP_PCI_AD<22>

TP_PCI_AD<25>

TP_PCI_AD<27> TP_PCI_AD<28> TP_PCI_AD<29> TP_PCI_AD<30> TP_PCI_AD<31>

TP_PCI_INTW_L

TP_PCI_INTY_L

PCI_REQ0_L PCI_REQ1_L

TP_PCI_AD<8>

TP_PCI_AD<10>

TP_PCI_PERR_L

MEM_VTT_EN_R

PCI_CLK33M_MCP

TP_PCI_CLK1 PCI_CLK33M_MCP_R

LPC_PWRDWN_L

LPC_RESET_L

LPC_FRAME_R_L

LPC_CLK33M_SMC_R

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

LPC_AD_R<0>

TP_PCI_CLK0

TP_PCI_RESET1_L

TP_PCI_STOP_L

TP_PCI_SERR_L

TP_PCI_PAR

TP_PCI_IRDY_L

TP_PCI_FRAME_L

TP_PCI_DEVSEL_L

TP_PCI_C_BE_L<3>

TP_PCI_C_BE_L<2>

TP_PCI_C_BE_L<1>

TP_PCI_C_BE_L<0>

MCP_RS232_SOUT_L

TP_PCI_GNT1_L

TP_PCI_GNT0_L

LPC_AD<0>

LPC_FRAME_L

LPC_AD<2> LPC_AD<3>

LPC_AD<1>

MCP_RS232_SOUT_L

PCI_REQ0_L PCI_REQ1_L FW_PWR_EN

7C5

17C1 20A4

18D7

18D2 76D3

76C3

18D4

18D7 76D3

18D7 35A4 35C4 35C7 35D6

BI

IN

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158 GND159

GND157

GND156

GND155

GND153 GND154

GND152

GND151

GND150

GND148 GND149

GND147

GND146

GND145

GND143 GND144

GND142

GND141

GND140

GND139

GND136

GND133 GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9

+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT

IN

OUT

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ExpressCard

Bluetooth

External B

External C

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

127 mA (A01, AVDD0 & 1)

43 mA (A01, DVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

External D

External A

Camera

IR

84 mA (A01)

19 mA (A01)

AirPort (PCIe Mini-Card)

Geyser Trackpad/Keyboard

38A8 76C3

8C6

29B5 76C3

39D7 76B3

48B8 76B3

29B5 76C3

38A4 76B3

38B4 76B3

8C6

38C7

41C4

2

1

R2010

2.49K

402

1/16W

1%

MF-LF

2

1

R2060

402

1/16W

1%

MF-LF

806

2

1

R2053

402

1/16W MF-LF

8.2K

5%

2

1

R2052

8.2K

5%

MF-LF

1/16W

402

2

1

R2051

MF-LF 402

1/16W

8.2K

5%

2

1

R2050

8.2K

5%

MF-LF

1/16W

402

D27

F27

G27

J25

H25

K23

G25

U1400

MCP79-TOPO-B

BGA

(8 OF 11)

A27

H21

J21

K21

L21

K25

L25

E27

J26

J27

K27

L27

F29

G29

A28

B28

C28

D28

L23

F25

C29

D29

AE3

E12

AP3

AP2

AN2

AN3

AN1

AM1

AM3

AM2

AM4

AL3

AK3

AL4

AK2

AJ3

AJ1

AJ2

AJ11

AJ10

AK9

AJ9

AJ7

AJ6

AJ4

AJ5

L28

AE16

AH19

AH17

AG19

AG17

AG16

AF19

AM14

AM13

AL14

AN14

AL13

AN12

AM12

AM11

AL12

AK13

AK12

AN11

AJ12

AH24

AH22

AH20

AH18

AG40

AG36

AG26

AG22

AG20

AG18

AF40

AF37

AF34

AF33

AF28

AF27

AF26

AF22

AF20

AF18

AF17

AF16

AD6

AE4

AE39

AE24

AE22

AD38

AD37

AD35

OMIT

37A2 75A3

37B2 75A3

37C3 75A3

30C7 76B3

SYNC_DATE=04/04/2008

19 81

4.7.0

051-7898

MCP SATA & USB

SYNC_MASTER=T18_MLB

TP_USB_10N

USB_BT_N

USB_IR_P

USB_CAMERA_N

USB_CAMERA_P

USB_EXTD_P

USB_MINI_N

USB_MINI_P

USB_EXTA_N

USB_EXTA_P

TP_SATA_D_D2RP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RN TP_SATA_E_D2RP

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

TP_MCP_SATALED_L

TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN

TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN

TP_SATA_D_D2RN

TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN

TP_SATA_F_D2RN TP_SATA_F_D2RP

MCP_SATA_TERMP

USB_EXTD_N

USB_IR_N

USB_TPAD_P

PP1V05_S0_MCP_PLL_SATA

TP_SATA_C_D2RN TP_SATA_C_D2RP

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N

SATA_ODD_D2R_N SATA_ODD_D2R_P

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD0

=PP1V05_S0_MCP_SATA_AVDD1

=PP3V3_S5_MCP_GPIO

USB_TPAD_N

USB_BT_P

USB_EXTC_OC_L EXCARD_OC_L

USB_EXTB_OC_L

USB_EXTA_OC_L

USB_EXTB_N

USB_EXTB_P

USB_EXCARD_P USB_EXCARD_N

TP_USB_10P

USB_EXTC_N

USB_EXTC_P

USB_CARDREADER_P USB_CARDREADER_N

22B4

76B3

75A3

22B2

7A6

7A3

17C7

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

SLP_S3*

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

SLP_RMGT*

HDA_BITCLK

HDA_SDATA_OUT

THERM_DIODE_N

THERM_DIODE_P

HDA_RESET*

HDA_PULLDN_COMP

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

EXT_SMI/GPIO_32*

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME*

KBRDRSTIN*

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_SYNC

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST*

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI JTAG_TDO

RTC_RST*

PS_PWRGD

PWRGD_SB

INTRUDER*

LID* LLB*

PWRBTN* RSTBTN*

CPU_DPRSLPVR

SLP_S5*

HDA_SDATA_IN0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

SPI_CS0/GPIO_10 SPI_CLK/GPIO_11

SPI_DI/GPIO_8 SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1 +V_DUAL_HDA2

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

GPIO_1/PWRDN_OK/SPI_CS1

A20GATE

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

+V_PLL_SP_SPREF

+V_PLL_NV_H

MISC

HDA

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

automatic recovery.

Connects to SMC for

USER mode: Normal

recovery

SAFE mode: For ROMSIP

(MXM_OK for MXM systems)

Int PU (S5)

Int PU

SPI1 option. Rev B01 will.

NOTE: MCP79 rev A01 does not support

Int PU (S5)

Int PD

Int PU

1

0

1

0

LPC_FRAME#

0

1

default, LPC+ debug card pulls

R1961 and R2160 selects SPI0 ROM by

BIOS Boot Select

HDA_SDOUT

I/F

SPI1

SPI0

LPC

NOTE: MCP79 does not support FWH, only

Frequency

SPI Frequency Select

1 MHz

NOTE: Straps not provided on this page.

31 MHz

Frequency

BUF_SIO_CLK Frequency

14.31818 MHz

1

0

SPI_DO SPI_CLK

0

1

0

24 MHz

HDA_SYNC

1

0

LPC ROMs. So Apple designs will

042 MHz

25 MHz

Int PU Int PU Int PU (S5)

Int PU

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

LPC_FRAME# high for SPI1 ROM override.

not use LPC for BootROM override.

PCI

For EMI Reduction on HDA interface

HDA Output Caps

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

7 mA (A01)

37 mA (A01)

20 mA 17 mA

Int PU (S5) Int PU (S5)

(MGPIO3)

(MGPIO2)

42A5 42C8 76A3

6C3

32B7 35A5 40C5 66D5 70D8

6C3

40C5 41A2 66C8

12B6 43D8 76B3

43B8 76B3

12B6 43D8 76B3

43B8 76B3

20A3 63D8

46B5 80D3

20A3 63C8

20A3 29D5 32C7

46B5 80D3

8D1

62D8 73B3

40B8

52C7 76A3

52C7 76B3

52C7 76A3

52C7 76B3

52C7 76A3

2

1

R2121

MF-LF

1/16W

1%

402

49.9K

2

1

R2120

1%

49.9K

MF-LF

402

1/16W

2

1

R2190

1K

MF-LF

1% 1/16W

402

24B4 76A3

40C5

40B8

21

R2170

MF-LF

402

5%

22

1/16W

21

R2171

MF-LF

5%

1/16W

402

22

21

R2173

5%

22

MF-LF

1/16W

402

2

1

R2163

402

5%

10K

MF-LF

1/16W

2

1

R2160

MF-LF

8.2K

5% 1/16W

402

2

1

R2180

5%

10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

2

1

R2181

5%

10K

402

MF-LF

BOOT_MODE_USER

1/16W

21

R2172

402

5%

22

1/16W MF-LF

42B8

2

1

R2110

49.9

MF-LF

1/16W

1%

402

2

1

R2150

402

1/16W MF-LF

5%

10K

12C3

12B6

12C3

2

1

C2171

10PF

50V

5%

402

CERM

2

1

C2173

50V

10PF

5%

402

CERM

2

1

C2170

50V

10PF

5%

402

CERM

2

1

C2172

50V

10PF

5%

402

CERM

B19

B16

A19

A16

B11

C11

K22

B18

C13

B14

C15

C14

D13

F21

K19

G21

L19

M23

H17

G17

J17

C19

C20

D16

D20

C16

E20

L22

AE17

AE18

K16

J16

M21

M20

L20

M24

M25

L13

J18

J19

F19

E19

G19

B20

L15

F15

J15

J14

G15

K15

A15

L17

K17

E15

L24

L26

D12

B12

C12

A12

C18

D17C17

M22

AE7

K13

U1400

BGA

(9 OF 11)

MCP79-TOPO-B

OMIT

37D6

20A4 57D3

24A5 24A8

32B7 35B5 40D5 41B2

20A4 26A5 27A5 40B8

2

1

R2147

402

1/16W MF-LF

5%

100K

2

1

R2142

10K

5% 1/16W

402

MF-LF

2

1

R2141

402

1/16W MF-LF

5%

10K

2

1

R2157

22K

5%

MF-LF

1/16W

402

2

1

R2156

22K

5%

MF-LF

1/16W

402

2

1

R2155

402

1/16W

22K

5%

MF-LF

2

1

R2151

402

MF-LF

5% 1/16W

100K

1

2

R2154

1/16W MF-LF

5%

100K

402

2

1

R2143

MF-LF 402

1/16W

5%

10K

2

1

R2140

10K

5%

MF-LF

1/16W

402

41C5

20A4 41D4

24C8

24B8

24C8

24A5

40D8

40C8

24A1

42A5 42B7 76A3

42A5 42C7 76A3

42B7 76A3

MCP HDA & MISC

SYNC_DATE=06/26/2008

SYNC_MASTER=T18_MLB

20 81

4.7.0

051-7898

SMC_IG_THROTTLE_L

TP_MCP_BUF_SIO_CLK

ARB_DETECT

=PP3V3R1V5_S0_MCP_HDA

MCP_GPIO_4

AP_PWR_EN

=PP3V3_S3_MCP_GPIO

AUD_I2C_INT_L

MCP_GPIO_4

MCP_CPU_VLD

MCP_VID<0>

PM_DPRSLPVR

HDA_SDIN0

MCP_CPUVDD_EN

MCP_VID<0>

MCP_THMDIODE_P

SMBUS_MCP_1_CLK

TP_MCP_LID_L

PM_PWRBTN_L

RTC_RST_L

MCP_PS_PWRGD

JTAG_MCP_TDI JTAG_MCP_TDO

SMBUS_MCP_1_DATA AP_PWR_EN

MCP_VID<2>

SMBUS_MCP_0_DATA

PM_BATLOW_L

HDA_SDOUT_R

HDA_BIT_CLK_R

=SPI_CS1_R_L_USE_MLB

SPI_CLK_R

SMC_RUNTIME_SCI_L

MCP_VID<1>

PM_SLP_RMGT_L

TP_SB_A20GATE

MCP_HDA_PULLDN_COMP

PP1V05_S0_MCP_PLL_NV

SPI_CS0_R_L

RTC_CLK32K_XTALOUT

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT

MCP_CLK25M_XTALIN

JTAG_MCP_TCK

PM_CLK32K_SUSCLK_R

SPI_MISO SPI_MOSI_R

SMBUS_MCP_0_CLK

MCP_THMDIODE_N

PM_SYSRST_DEBOUNCE_L

TP_MCP_KBDRSTIN_L

HDA_RST_L

HDA_BIT_CLK

HDA_SDOUT

PP3V3_G3_RTC

=PP3V3R1V5_S0_MCP_HDA

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

HDA_BIT_CLK_R

MCP_VID<2>

MCP_VID<1>

JTAG_MCP_TMS

MCP_TEST_MODE_EN

JTAG_MCP_TRST_L

PM_RSMRST_L

SM_INTRUDER_L

ARB_DETECT

HDA_SYNC

HDA_RST_R_L

ODD_PWR_EN_L

MEM_EVENT_L

SMC_WAKE_SCI_L

=PP3V3_S0_MCP_GPIO

MEM_EVENT_L SMC_IG_THROTTLE_L

SMC_ADAPTER_EN

TP_MLB_RAM_VENDOR

TP_MLB_RAM_SIZE

HDA_SYNC_R

AUD_I2C_INT_L

PM_SLP_S3_L

PM_SLP_S4_L

=PP3V3_S0_MCP

MCP_SPKR

20A4

7C5

20D8 22A8

20A4

20C3 29D5 32C7

7D3

20C3 57D3

20C3

20C3 63D8

20A7 76A3

20A7 76B3

76A3

22A2

6C3

21A5 24D4

7C5

20D3 22A8

20D4 76B3

20D4 76A3

20D4 76B3

20C3 63C8

20B3

20A7 76A3

7C5

17C1 18D1

20B3 26A5 27A5 40B8

20B3 41D4

20A7 76B3

7C5

21B3 22B8

GND

GND161

GND165 GND166

GND164

GND163

GND162

GND167 GND168

GND171

GND170

GND169

GND172 GND173

GND176

GND175

GND174

GND177 GND178

GND181

GND180

GND179

GND182 GND183 GND184

GND187

GND186

GND185

GND188 GND189

GND192

GND191

GND190

GND193 GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206 GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213 GND214

GND217

GND216

GND215

GND218 GND219

GND222

GND221

GND220

GND223 GND224 GND225

GND228

GND227

GND226

GND229 GND230

GND233

GND232

GND231

GND234 GND235

GND238

GND237

GND236

GND239 GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331 GND332

GND330

GND329

GND328

GND326 GND327

GND325

GND324

GND323

GND321 GND322

GND320

GND319

GND318

GND316 GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305 GND306 GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285 GND286

GND284

GND283

GND282

GND280 GND281

GND279

GND278

GND277

GND275 GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264 GND265 GND266

GND263

GND262

GND259 GND260 GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6

+VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19

+VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30

+VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37

+VDD_CORE39 +VDD_CORE40 +VDD_CORE41

+VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3 +3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

105 mA (A01)

43 mA

1139 mA

250 mA

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

80 uA (S0)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

10 uA (G3)

16 mA

266 mA (A01)

450 mA (A01)

1182 mA (A01)

T22

AH16

Y11

V11

T11

Y6

P11

AY13

AB19

AA4

M11

AD7

AN26

AB16

AB17

Y38

Y37

Y35

Y34

Y33

Y28

M37

M35

M34

M10

L5

L43

L40

AU1

K8

K40

K4

K37

K26

K18

K12

K10

J8

J12

G40

AN8

H23

AW35

H15

H11

G8

G6

G43

G4

G34

AW20

G24

G22

BC12

G16

G14

G12

G10

F8

F32

F16

F12

E33

E29

E25

E21

E17

E13

D6

D37

D30

D26

D23

D22

D19

D18

D15

D14

D10

C2

BC5

AY14

BC41

BC37

BC33

L35

AY6

AW31

BA4

BA1

AV40

AY41

AY38

AY37

AY34

AY33

AY30

AV12

AY10

AW43

AR43

G20

AW11

AV7

AV4

AV36

AV32

AV28

F20

G28

AU4

AU38

AU36

AR30

AU32

AP33

AU28

AU12

L12

AY22

AY21

AT9

AT7

AT6

AT33

AT29

AT13

AR12

AT10

AR40

AR32

AR28

AW23

AP7

AP40

AP4

AP37

AP36

AP34

AP32

AP28

AU14

AP14

AU26

AP10

Y7

AN4

AN39

AN30

AN28

AP26

AM9

AM7

AM6

AM5

AM38

AM37

AM35

AM34

AM30

AM26

AM24

AM22

AM20

AM18

AM16

AM10

AL5

AL40

AL36

AK40

AK4

AK37

AK34

AK33

AK10

AJ8

AJ39

AH38

AH37

AH34

AH33

AH26

U1400

(11 OF 11)

MCP79-TOPO-B

OMIT

BGA

AG32

W32

V32

U32

T32

AA32

Y32

P32

N32

N31

M33

M32

M31

L34

L33

L32

K35

K34

K33

J36

J35

J34

H37

H35

G38

G37

G36

F39

F38

F37

E40

E39

E38

D41

D40

D39

C42

C41

C40

B42

B41

AC32

AB32

AL31

AD32

AK32

AK31

AJ32

AH32

AE32

AF32

P31

R32

AA16

AF12

W25

Y23

W23

W21

AA24

AH9

AH7

AH6

AH5

AH4

AH3

AH21

Y21

AH25

W28

AA23

AH2

W26

AH11

AH10

AH1

AG9

AG8

AG5

AG7

AG6

AA21

AG4

AG3

AG25

AG23

AG21

AG12

AG11

AG10

AA20

AF9

AH23

AF7

AF4

AF3

AF25

AF23

AF21

AF2

AH12

AA19

AF11

AF10

AE28

AE27

AE26

AE25

AE23

AE21

AE19

U25

AA18

V25

W27

AD23

AD21

AC28

AC27

AC26

AC25

AC24

AC23

AA17

AC21

AC20

AC19

AC18

AC17

AC16

AA28

AA27

AA26

AA25

V21

U21

T21

A20

K28

J28

H27

G26

K20

J20

H19

G18

Y9

AA8

AB11

Y10

AD9

AB10

AE8

AD10

U1400

OMIT

MCP79-TOPO-B

BGA

(10 OF 11)

MCP Power & Ground

21 81

4.7.0

051-7898

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

=PP3V3_S5_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP3V3_S0_MCP

PP3V3_G3_RTC

=PPVCORE_S0_MCP

=PP1V05_S0_MCP_FSB

7A3

22B8

7B3

22D8

7C5

20C2 22B8

6C3

20C8 24D4

7C6

22D8

7D7

13A2 13B7 22C8

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

19 mA (A01)

450 mA (A01)

43 mA (A01)

127 mA (A01)

206 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

37 mA (A01)

87 mA (A01)

84 mA (A01)

83 mA (A01)

131 mA (A01)105 mA (A01)

MCP PCIE (DVDD) Power

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

23065 mA (A01, 1.2V)

(No IG vs. EG data)

270 mA (A01)

MCP 3.3V Ethernet Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

5 mA (A01)

MCP 1.05V AUX Power

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) Apple: 5x 2.2uF 0402 (11 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP Core Power

4771 mA (A01, DDR3)

333 mA (A01)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

MCP SATA (DVDD) Power

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

Apple: 4x 2.2uF 0402 (8.8 uF)

16996 mA (A01, 1.0V)

57 mA (A01)

562 mA (A01)

5 mA (A01)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

MCP 1.05V RMGT Power

Apple: 7x 2.2uF 0402 (15.4 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

X5R-1

4V

4.7UF

20%

402

C2582

1

2

X5R-1

20%

4.7UF

4V

402

C2588

1

2

X5R-1

4.7UF

20%

4V

402

C2584

1

2

X5R-1

4V

4.7UF

20%

402

C2586

1

2

1

C2555

6.3V

2.2UF

20%

402-LF

CERM

X5R-1

4.7UF

4V

20%

402

C2502

1

2 2

1

C2507

10V

10%

1UF

402-1

X5R

2

1

C2506

10V

10%

1UF

402-1

X5R

2

1

C2505

10V

10%

1UF

402-1

X5R

2

1

C2504

10V

10%

1UF

402-1

X5R

2

1

C2511

10V

402

20%

CERM

0.1UF

2

1

C2510

10V

402

20%

CERM

0.1UF

2

1

C2509

10V

402

20%

CERM

0.1UF

2

1

C2508

10V

402

20%

CERM

0.1UF

2

1

C2513

10V

402

20%

CERM

0.1UF

2

1

C2512

10V

402

20%

CERM

0.1UF

6.3V

2

1

C2536

CERM 402-LF

20%

2.2UF

2

1

C2535

CERM 402-LF

20%

2.2UF

6.3V

2

1

C2534

CERM 402-LF

20%

6.3V

2.2UF

402-LF

C2533

2

1

CERM

20%

2.2UF

6.3V

2.2UF

C2532

2

1

CERM 402-LF

20%

6.3V

2

1

C2531

CERM 402-LF

6.3V

2.2UF

20%

2

1

C2530

CERM 402-LF

20%

2.2UF

6.3V

C2517

2

1

10V

10%

1UF

402-1

X5R

C2516

2

1

10V

10%

1UF

402-1

X5R

X5R-1

4.7UF

4V

20%

C2515

1

2

402

2

1

C2572

CERM 402-LF

20%

2.2UF

6.3V

2

1

C2571

CERM 402-LF

20%

2.2UF

6.3V

X5R-1

4V

4.7UF

20%

402

C2520

1

2 2

1

C2570

CERM 402-LF

20%

2.2UF

6.3V 2

1

C2574

CERM 402-LF

20%

2.2UF

6.3V

2

1

C2573

CERM 402-LF

20%

2.2UF

6.3V

2

1

C2576

6.3V

2.2UF

20%

402-LF

CERM

402-LF

2

1

C2575

CERM

20%

2.2UF

6.3V

2

1

C2553

CERM 402-LF

20%

6.3V

2.2UF

2

1

C2552

CERM 402-LF

20%

2.2UF

6.3V

2

1

C2551

CERM 402-LF

20%

6.3V

2.2UF

2

1

C2550

CERM 402-LF

20%

2.2UF

6.3V

2

1

C2549

10V

402

CERM

20%

0.1UF

2

1

C2548

10V

402

CERM

20%

0.1UF

2

1

C2547

10V

402

CERM

20%

0.1UF

2

1

C2546

10V

402

CERM

20%

0.1UF

2

1

C2545

10V

402

CERM

20%

0.1UF0.1UF

2

1

C2544

10V

402

CERM

20%

2

1

C2543

10V

402

CERM

20%

0.1UF0.1UF

C2542

2

1

10V

402

CERM

20%

0.1UF

2

1

C2541

10V

402

20%

CERM

X5R-1

20%

4.7UF

4V

402

C2540

1

2

1

C2562

CERM 402-LF

20%

2.2UF

6.3V

2

1

C2564

6.3V

2.2UF

20%

402-LF

CERM

X5R-1

4.7UF

20%

4V

402

C2580

1

2

21

L2570

30-OHM-5A

0603

21

L2575

0603

30-OHM-5A

L2582

21

0402

30-OHM-1.7A

21

L2584

0402

30-OHM-1.7A

21

L2588

0402

30-OHM-1.7A

21

L2586

30-OHM-1.7A

0402

21

L2555

30-OHM-1.7A

X5R-1

4V

20%

402

C2500

1

2

4.7UF

X5R-1

4.7UF

4V

402

C2501

1

2

20%

0402

L2580

30-OHM-1.7A

21

CERM

20%

2

1

C2526

10V

402

0.1uF

2

1

C2525

10V

402

0.1uF

20%

CERM

C2560

2

1

CERM 402-LF

20%

2.2UF

6.3V

C2589

0.1UF

2

1

10V

402

20%

CERM

2

1

C2590

10V

402

20%

0.1UF

CERM

X5R-1

20%

4.7UF

4V

402

C2595

1

2

21

L2595

0402

30-OHM-1.7A

2

1

R2590

402

MF-LF

1%

1/16W

1.47K

2

1

C2591

10V

402

20%

CERM

0.1UF

2

1

R2591

402

1.47K

1/16W

1%

MF-LF

17D3

2

1

C2521

10V

402

0.1uF

20%

CERM

C2518

2

1

10V

402

CERM

20%

0.1uF

2

1

C2519

10V

402

20%

CERM

0.1uF

20%

CERM

0.1UF

402

10V

C2581

1

2

C2583

0.1UF

2

1

10V

402

20%

CERM

C2585

2

1

10V

402

0.1UF

CERM

20%

C2587

2

1

10V

402

0.1UF

CERM

20%

2

1

C2596

10V

402

0.1UF

20%

CERM

2

1

C2529

10V

402

0.1uF

20%

CERM

4.7UF

X5R-1

20%

4V

402

C2528

1

2

C2592

603

X5R

6.3V

20%

10UF

2

1

X5R-1

4.7UF

4V

20%

402

C2503

1

2

81

051-7898

4.7.0

22

MCP Standard Decoupling

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

=PP1V05_S0_MCP_PEX_DVDD

=PPVCORE_S0_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_S0_MCP_PLL_UF PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_PEX

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_NV

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_CORE

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_SATA_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PEX_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_S0_MCP_PLL_USB

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_ENET_MCP_PLL_MAC

=PP1V05_ENET_MCP_PLL_MAC

=PP3V3_ENET_MCP_RMGT

MCP_MII_VREF

=PP3V3_S0_MCP

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S5_MCP

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_FSB

=PP1V8R1V5_S0_MCP_MEM

=PP1V05_ENET_MCP_RMGT

=PP3V3_S0_MCP_PLL_UF

=PP3V3_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

7A8 7D7

7C6

21D5

7B3

21A3

7B8

65B1 13A6

16A6

20C7

15C6

7A8

19C3

19B6

17C6

7B5

17D3 17D7 22B6

7C5

20C2 21B3

7C5

20D3 20D8

7A3

21B3

7D7

13A2 13B7 21D3

7B6

15C3 15C7

7A5

17D3

7C5

7B5

17D3 17D7 22A5

7A8 7D7

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672

REMOVE HDCP ROMS

CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC

SYNC FROM T18 REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT

NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

206 mA (A01) 206 mA (A01)

16 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

16 mA (A01)

95 mA (A01)

190 mA (A01, 1.8V)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: ???

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

6.3V

2.2UF

20%

402-LF

CERM

2

1

C2650

NO STUFF

30-OHM-1.7A

0402

21

L2650

NO STUFF

CERM

10V

20%

0.1UF

NO STUFF

402

2

1

C2620

1

2

R2630

MF-LF

1/16W

1%

1K

402

NO STUFF

20%

402

CERM

NO STUFF

10V

0.1UF

2

1

C2630

X5R-1

C2615

1

2

402

4V

4.7UF

20%

CERM

4.7UF

6.3V

20%

603

2

1

C2640

30-OHM-1.7A

0402

21

L2640

10V

20%

402

CERM

0.1uF

2

1

C2641

402

20%

CERM

0.1UF

10V

2

1

C2616

402

2

1

R2651

0

5% 1/16W MF-LF

402

1/16W

1%

1K

MF-LF

2

1

R2620

CERM 402-LF

20%

2.2UF

6.3V

2

1

C2610

SYNC_DATE=12/12/2007

SYNC_MASTER=T18_MLB

MCP Graphics Support

23 81

4.7.0

051-7898

VOLTAGE=3.3V

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MCP_IFPAB_VPROBE

PP3V3_S0_MCP_VPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

MCP_HDMI_VPROBE

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP_DAC_UF

MCP_HDMI_RSET

MCP_IFPAB_RSET

=PP1V05_S0_MCP_HDMI_VDD

17C3

17A3 75B3

17B6

17A6 75B3

7B6

17B6

7C5

17A6 75B3 17A3 75B3

7D7

17A6

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

Y

B

A

IN

OUT

VIN

GND

VOUTEN

NC

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PCIE Reset (Unbuffered)

PLACE C2819 CLOSE TO MCP79

MCPSEQ_MIX is cross between MLB and internal power sequencing, which

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for

RTC Crystal

MCP S0 PWRGD & CPU_VLD

10K pull-up to 3.3V S0 inside MCP

Reset Button

but results in MCP79 ROMSIP sequence happening after CPU powers up.

LPC Reset (Unbuffered)

REMOVE R2824 AND NET PCI_CLK33M_SLOT_A

CHANGE Y2810 AND U2850 TO SMALLER PARTS

REMOVE UNUSED PCIE RESET SIGNALS

ALIAS MEM_VTT_EN TO =DDRVTT_EN

CHANGE RESET BUTTOM TO RESET PADS

SYNC FROM T18

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,

results in earlier ROMSIP and MCP FSB I/O interface initialization.

VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

CHANGE RTC COIN CELL TO LDO & SUPERCAP

Platform Reset Connections

MCP 25MHz Crystal

RTC Power Sources

PLACE C2800 AT COOLEST SPOT ON MLB

12pF

402

5%

50V

21

CERM

C2810

402

C2811

12

12pF

5%

50V

CERM

1

2

NO STUFF

R2811

10M

402

MF-LF

5%

1/16W

18C3 76C3

R2883

12

33

MF-LF

5%

1/16W

402

PLACEMENT_NOTE=Place close to U1400

R2881

12

33

5% 1/16W MF-LF

402

R2891

2

0

MF-LF

402

5% 1/16W

1

42D5

40C8

29A6

20B7

16B3

R2826

12

PLACEMENT_NOTE=Place close to U1400

402

5% 1/16W MF-LF

33

PLACEMENT_NOTE=Place close to U1400

R2825

12

MF-LF

5%

1/16W

33

402

18B3 76C3

402

CERM

50V

12pF

21

5%

C2815

12pF

C2816

12

5%

50V

CERM

402

25.0000M

Y2815

CRITICAL

3

24

1

SM-3.2X2.5MM

1

2

402

1M

NO STUFF

R2816

1/16W

5%

MF-LF

20B7

40C5 76A3

R2829

12

PLACEMENT_NOTE=Place close to U1400

402

MF-LF

5%

1/16W

22

20B3 76A3

72C8

R2892

2

1/16W MF-LF

5%

0

1

402

61C8 67A3

R2870

33

402

5% 1/16W MF-LF

21

18C4

42D3 76C3

40C8 76C3

20C7

X5R

10%

1UF

10V

402

NO STUFF

2

1

C2899

33

402

MF-LF

1/16W

5%

21

R2899

NO STUFF

0

MF-LF

1/16W

5%

402

SILK_PART=SYS RST

2

1

R2890

R2898

12

402

5% 1/16W MF-LF

XDP

0

40B8

9C6

12B3

25A5

402

MF-LF

0

5%

1

1/16W

2

R2871

Y2810

14

CRITICAL

7X1.5X1.4-SM

32.768K

2%

XHHG

3.3V

SM

2

SUPERCAP_YES

0.08F

C2800

1

R2815

1/16W MF-LF

402

5%

0

2

1

2

1

0

5% 1/16W MF-LF

402

R2810

3

5

1

4

2

SOT665

TC7SZ08AFEAPE

U2850

20B3

62C7

40D8 66A4

21

R2851

402

0

1/16W

5%

MF-LF

MCPSEQ_MIX

2

1

C2850

402

20%

CERM

0.1UF

MCPSEQ_SMC

10V

21

R2850

402

0

1/16W

5%

MF-LF

PLACEMENT_NOTE=Place close to U1400

MCPSEQ_SMC

20B7

21

R2852

MF-LF

5%

1/16W

0

402

MCPSEQ_MIX

21

R2853

MF-LF

5%

1/16W

0

402

MCPSEQ_SMC

20B7

12

MF-LF

402

R2819

100

SUPERCAP_YES

C2870

1UF

X5R

10%

2

1

402

10V

1

2

3

4

U2801

5

CRITICAL

TSOT-23-5

MIC5232-2.8YD5

SUPERCAP_YES

2

1

10% 10V X5R 402

SUPERCAP_YES

0.47UF

C2871

PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79

10%

1UF

1

402

CERM

6.3V

C2819

2

35D1

21

402

0

1/16W MF-LF

5%

R2820

SUPERCAP_NO

2

1/16W

1

5%

0

MF-LF

402

R2895

30A7

051-7898

24

4.7.0

81

SB Misc

SYNC_MASTER=RAYMOND

SYNC_DATE=04/05/2008

CARDREADER_PLT_RST_L

MINI_RESET_L

PCIE_RESET_L

MAKE_BASE=TRUE

=FW_RESET_L

PCA9557D_RESET_L

BKLT_PLT_RST_L

LPC_CLK33M_LPCPLUS

RTC_CLK32K_XTALOUT

=PP3V42_G3H_RTC_D

MAKE_BASE=TRUE

MEM_VTT_EN

LPC_CLK33M_SMC_R

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

MCP_CLK25M_XTALIN

MCP_CLK25M_XTALOUT

PP3V3_G3_SUPERCAP

SMC_LRESET_L

=PP3V3_S5_MCPPWRGD

VR_PWRGOOD_DELAY

S0_AND_IMVP_PGOOD

ALL_SYS_PWRGD

MCP_CPUVDD_EN

MCP_CPU_VLD

MCP_PS_PWRGD

XDP_DBRESET_L

PM_SYSRST_DEBOUNCE_L

PM_SYSRST_L

DEBUG_RESET_L

RTC_CLK32K_XTALIN

=DDRVTT_EN

LPC_CLK33M_SMC

PM_CLK32K_SUSCLK

MEM_VTT_EN_R

PM_CLK32K_SUSCLK_R

LPC_RESET_L

MIN_LINE_WIDTH=0.3 mm

PP3V3_G3_RTC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

7D1

7A3

6C3

20C8 21A5

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC NC

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

NC

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CPU FSB VREF

MEM B VREF CA

Place close to J3100.126

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

BOM options provided by this page:

NO_VREFMRGN

ADDR=0x98(WR)/0x99(RD)

Required zero ohm resistors when no VREF margining circuit stuffed

ADDR=0x30(WR)/0x31(RD)

MEM B VREF DQ

VREFMRGN

Place close to J3200.126

Place close to J3200.1

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

10mA max load

Page Notes

MEM A VREF DQ MEM A VREF CA

Place close to J3100.1

Place close to U1000.AD26

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA

(per DAC LSB)

- =I2C_VREFDACS_SCL

- =I2C_PCA9557D_SCL

Min DAC code 0x00 0x00 0x00 0x00 0x00

- =I2C_PCA9557D_SDA

- =I2C_VREFDACS_SDA

- =PP3V3_S5_VREFMRGN

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA

Max DAC code 0x87 0x87 0x87 0x87 0x55

DAC channel A B A B C

VREFMRGN

MAX4253

UCSP

U2903

C3

C2

C1

C4

B1

B4

VREFMRGN

MF-LF

1/16W

1%

100

402

R2904

12

100

1/16W

1%

402

VREFMRGN

MF-LF

R2906

12

VREFMRGN

100

1% 1/16W MF-LF

402

R2910

12

MF-LF

1/16W

VREFMRGN

1%

402

100

R2914

12

1/16W

VREFMRGN

1%

MF-LF

100

402

R2912

12

U2904

VREFMRGN

MAX4253

UCSP

C3

C2

C1

C4

B1

B4

A4

VREFMRGN

MAX4253

UCSP

U2904

A3

A2

A1

B1

B4

C2902

VREFMRGN

0.1UF

2

20% 10V

1

402

CERM

MAX4253

VREFMRGN

UCSP

U2903

A3

A2

A1

A4

B1

B4

VREFMRGN

MAX4253

UCSP

U2902

C3

C2

C1

C4

B1

B4

MAX4253

VREFMRGN

UCSP

U2902

A3

A2

A1

A4

B1

B4

402

21

R2911

MF-LF

1/16W

200

1%

VREFMRGN

402

21

R2909

MF-LF

1/16W

200

1%

VREFMRGN

402

21

R2905

MF-LF

1/16W

200

1%

VREFMRGN

402

21

R2903

MF-LF

1/16W

200

1%

VREFMRGN

MF-LF

21

1/16W

100K

402

5%

VREFMRGN

R2902

21

1/16W

5%

100K

VREFMRGN

MF-LF

402

R2901

1/16W MF-LF

21

5%

402

VREFMRGN

100K

R2907

15

3

4

5

1

2

6

7

9

12

13

14

16

10

11

17

8

QFN

VREFMRGN

PCA9557

U2901

0.1UF

CERM 402

2

1

C2904

VREFMRGN

10V

20%

R2908

100K

MF-LF

21

5%

1/16W

402

VREFMRGN

24C1

43A3

U2900

3

7

VREFMRGN

1

2

4

10 5

8

6

9

DAC5574

MSOP

43B3

2

1

C2901

10V

402

VREFMRGN

0.1UF

20%

CERM

VREFMRGN

C2900

2.2UF

402-LF

CERM

6.3V

20%

402

2

1

C2905

20% 10V

0.1UF

VREFMRGN

CERM

MF-LF

402

5%

R2913

12

100K

1/16W

VREFMRGN

0.1UF

20%

2

1

402

10V CERM

C2903

VREFMRGN

9B4

73B3

FSB/DDR3 Vref Margining

SYNC_MASTER=BEN

051-7898

4.7.0

8125

SYNC_DATE=03/31/2008

R2905

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

NO_VREFMRGN

1 CRITICAL

R2911

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

NO_VREFMRGN

1 CRITICAL

RES,MTL FILM,0,5%,0402,SM,LF

R2909116S0004

NO_VREFMRGN

CRITICAL1

RES,MTL FILM,0,5%,0402,SM,LF

116S0004 1

NO_VREFMRGN

R2903 CRITICAL

=PPVTT_S3_DDR_BUF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

VREFMRGN_DQ_SODIMMB_BUF

=PP3V3_S3_VREFMRGN

CPU_GTLREF

VREFMRGN_CA_SODIMM

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMA_EN

PCA9557D_RESET_L

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CPUFSB_BUF

VREFMRGN_CPUFSB

7C4

61D8

27B3

26B3

27D5

26D5

7D3

25B5

25A5

25B5

25A5

25B3

25C3

25D3

25B3

25C3

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4* DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI

BIBI

BI

IN

BI

IN

BI

IN

BI

IN

BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

OUT

BI

IN

BI

IN

BI

IN

BI

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SPD ADDR=0xA0(WR)/0xA1(RD)

- =PP1V5_S0_MEM_A

- =PP0V75_S0_MEM_VTT_A

DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)

Signal aliases required by this page:

BOM options provided by this page:

(NONE)

- =I2C_SODIMMA_SCL

"Factory" (top) slot

Page Notes

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP1V5_S3_MEM_A

Power aliases required by this page:

- =I2C_SODIMMA_SDA

516-0201

603

X5R

6.3V

2

1

C3100

10UF

20%

603

C3101

2

1

X5R

10UF

20%

6.3V

DDR3-SODIMM-DUAL-M97-3

J3100

90

86

84

91

131

105 107

124

195

201 203

127

135 137 139

143

151

103

197

189 191 193

187

179

183

181

175 177

173

169 171

167

165

163

159 161

153 155 157

200 202 204

196 198

192

190

194

186 188

180 182 184

178

176

174

170 172

166 168

164

160 162

154 156 158

149

145 147

141

133

129

125

123

117

121

119

115

113

109 111

99

101

97

95

93

87 89

85

83

81

79

77

75

73

150 152

144 146 148

142

140

138

134 136

128

132

130

126

118 120 122

114 116

108 110 112

104 106

100

98

102

96

94

92

88

82

80

78

74

185

199

F-RT-THB

76

14B7 74D3

402

0.1UF

20%

2

1

C3131

CERM

10V

2.2UF

20%

C3130

CERM

2

1

402-LF

6.3V

14B7 74D3

14A5 74D3

14D5 74C3

14B7 74D3

14A7 74C3

14B7 74D3

27C2 28C5

14B7 74D3

14C7 74D3

14B7 74C3

14C7 74D3

14B7 74D3

14D5 74C3

14B7 74D3

14C7 74D3

CRITICAL

19

55 57

DDR3-SODIMM-DUAL-M97-3

J3100

37 39

61 63 65 67 69 71

4

72

70

68

66

64

62

60

58

56

52 54

50

48

46

42 44

40

38

36

32 34

30

28

26

24

22

20

18

16

14

12

10

8

6

2

59

53

51

47 49

45

41 43

35

31 33

29

27

25

21 23

13

11

9

5 7

1 3

17

15

F-RT-THB

14A7 74D3

14B7 74D3

14D5 74C3

14B7 74D3

14D5 74C3

14B7 74D3

14C7 74D3

14D5 74C3

8D2

14C5 74D3

14B5 74D3

14C5 74D3

14B5 74D3

14C7 74D3

14B7 74C3

14C7 74D3

14B7 74D3

14B5 74D3

14C7 74D3

14B7 74C3

14C7 74D3

14D5 74C3

14C7 74D3

14D5 74C3

2

1

C3136

10V

20%

402

CERM

0.1UF

2

1

C3135

402-LF

20%

6.3V

2.2UF

CERM

14D7 74D3

14C7 74D3

14D7 74D3

14B7 74C3

14D7 74D3

14D5 74C3

14D7 74D3

20A4 20B3 27A5 40B8

2

1

C3151

20%

2.2UF

6.3V

402-LF

CERM

43D6

2

1

C3150

CERM 402-LF

20%

2.2UF

6.3V

14A5 74D3

14C5 74D3

14B5 74D3

14C5 74D3

14B5 74D3

14C7 74D3

14D5 74C3

14C7 74D3

14B7 74C3

14C7 74D3

14D7 74D3

14D5 74C3

14D7 74D3

14B7 74C3

14D7 74D3

2

1

10K

5%

402

1/16W MF-LF

R3141

2

1

10K

MF-LF

1/16W

5%

R3140

402

2

1

C3140

2.2UF

20%

CERM 402-LF

6.3V

CRITICAL

0204-1

C3110

20%

0.1UF

X6S-CERM

6.3V

1

2

CRITICAL

C3117

X6S-CERM

6.3V

20%

0.1UF

0204-1

1

2

CRITICAL

C3116

X6S-CERM

6.3V

20%

0.1UF

0204-1

1

2

CRITICAL

C3115

6.3V

20%

0.1UF

X6S-CERM 0204-1

1

2

CRITICAL

C3114

X6S-CERM

6.3V

20%

0.1UF

0204-1

1

2

CRITICAL

C3113

X6S-CERM

6.3V

20%

0.1UF

0204-1

1

2

CRITICAL

2

C3112

X6S-CERM

6.3V

20%

0.1UF

0204-1

1

CRITICAL

C3111

20%

0.1UF

6.3V X6S-CERM 0204-1

1

2

SYNC_MASTER=BEN

SYNC_DATE=06/30/2008

DDR3 SO-DIMM Connector A

051-7898

4.7.0

8126

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<5>

MEM_A_DQ<33>

MEM_A_A<10>

MEM_A_SA<1>

=PP0V75_S0_MEM_VTT_A

MEM_A_DQS_N<4> MEM_A_DQS_P<4>

MEM_A_DQ<38>

MEM_A_CLK_N<0>

MEM_A_SA<0>

MEM_A_DQ<58> MEM_A_DQ<59>

MEM_A_DM<7>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<54> MEM_A_DQ<51>

MEM_A_DQS_N<6> MEM_A_DQS_P<6>

MEM_A_DQ<52>

MEM_A_DQ<49>

MEM_A_DQ<46>

MEM_A_DM<5>

MEM_A_DQ<47>

=I2C_SODIMMA_SDA =I2C_SODIMMA_SCL

MEM_EVENT_L

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQS_N<7> MEM_A_DQS_P<7>

MEM_A_DQ<57> MEM_A_DQ<56>

MEM_A_DQ<50>

MEM_A_DQ<55>

MEM_A_DM<6>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<34>

MEM_A_DQ<32>

MEM_A_CS_L<1>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_BA<0>

MEM_A_CLK_P<0>

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_DQS_N<5>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<36>

MEM_A_ODT<1>

MEM_A_CS_L<0> MEM_A_ODT<0>

MEM_A_RAS_L

MEM_A_CLK_N<1>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_CKE<1>

=PPSPD_S0_MEM_A

MEM_A_DQ<25>

MEM_A_DM<2>

MEM_A_DQ<23> MEM_A_DQ<16>

MEM_A_DQ<4>

MEM_A_DQ<22>

MEM_A_DQ<19>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<31>

MEM_A_DQ<27>

MEM_A_DM<3>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<14>

MEM_A_DQ<11>

MEM_RESET_L

MEM_A_DM<1>

MEM_A_DQ<13>

MEM_A_DQ<9>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQ<5>

MEM_A_DQ<20> MEM_A_DQ<21>

MEM_A_DQ<30>

MEM_A_DQ<26>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQ<24>

MEM_A_DQ<15>

MEM_A_DQ<10>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQ<8> MEM_A_DQ<12>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<1>

MEM_A_DQS_P<5>

MEM_A_DQ<35>

=PP1V5_S3_MEM_A

MEM_A_A<0>

MEM_A_CLK_P<1>

MEM_A_BA<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<37>

MEM_A_DM<4>

MEM_A_DQ<41>

MEM_A_DQ<48>

MEM_A_DQ<53>

MEM_A_DM<0>

MEM_A_DQ<0>

7C7

7C5

25D1

7D3

25C1

IN

BI

OUT

BI

IN

BI

IN

BI

IN

BI

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMB_SCL

BOM options provided by this page:

Page Notes

Power aliases required by this page:

516S0706

- =I2C_SODIMMB_SDA

SPD ADDR=0xA2(WR)/0xA3(RD)

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

DDR3 GROUND RETURN CAPS (MCP SIDE)

"Expansion" (bottom) slot

DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)

- =PP1V5_S0_MEM_B

(NONE)

516S0706

14B1 74B3

20%

6.3V

0204-1

1

2

CRITICAL

C3214

0.1UF

X6S-CERM

14D1 74A3

14D3 74B3

20A4 20B3 26A5 40B8

2

C3251

2.2UF

CERM 402-LF

6.3V

20%

1

43C6

2

402-LF

C3250

2.2UF

6.3V

20%

CERM

1

C3210

6.3V

0.1UF

20%

1

2

CRITICAL

X6S-CERM 0204-1

20%

X5R

2

1

6.3V

C3201

10UF

603

C3231

10V

20%

402

CERM

0.1UF

2

1

603

6.3V

10UF

20%

1

2

X5R

C3200

14A1 74B3

14C1 74B3

14B1 74B3

14B1 74C3

14C1 74B3

14B1 74B3

14C3 74B3

14D1 74A3

C3213

0.1UF

6.3V

20%

0204-1

1

2

CRITICAL

X6S-CERM

14D1 74A3

14C3 74B3

14B3 74B3

14D3 74B3

C3212

6.3V

20%

0.1UF

1

2

CRITICAL

X6S-CERM 0204-1

14D3 74B3

14D1 74A3

14D3 74B3

14B3 74B3

14D3 74B3

C3230

CERM 402-LF

6.3V

20%

2.2UF

1

2

R3241

10K

1/16W MF-LF

5%

402

2

1

2

MF-LF

1/16W

402

5%

10K

R3240

1

2

C3240

20%

CERM 402-LF

6.3V

2.2UF

C3229

X6S-CERM

0.1UF

20%

6.3V

1

2

0204-1

CRITICAL

C3228

X6S-CERM

0.1UF

20%

6.3V

1

2

0204-1

CRITICAL

C3227

20%

0.1UF

1

2

6.3V X6S-CERM 0204-1

CRITICAL

X6S-CERM

0.1UF

20%

6.3V

1

2

C3226

0204-1

CRITICAL

C3225

X6S-CERM

1

2

20%

0.1UF

6.3V

0204-1

CRITICAL

14B3 74B3

C3224

X6S-CERM

20%

6.3V

1

2

0204-1

CRITICAL

0.1UF

0204-1

20%

1

2

C3223

CRITICAL

0.1UF

6.3V X6S-CERMX6S-CERM

20%

6.3V

1

2

C3222

0204-1

CRITICAL

0.1UF

113 115 117 119 121 123 125 127

145

142 144

93

F-RT-BGA3

205

199

195

193

189 191

197

201 203

183

179

206

212211

210209

207 208

181

185 187

94

103 105 107

175 177

173

169 171

155

200 202

196 198

192

190

186 188

180 182 184

176

174

170 172

168

164

160 162

156

141

133

129 131

109 111

79

77

75

73

152

134 136

132

126

118 120 122

114 116

108 110 112

104 106

98

102

96

92

88 90

86

84

82

80

76

153

135

149 151

167

165

163

159

157

83

81

85 87 89 91

95 97 99

158

178

166

194

204

101

124

138

146

161

137

143

150

147 148

128

139

154

140

J3200

74

78

130

100

DDR3-SODIMM

72

15 17

3

1

7

5

9 11 13

19

23

21

25 27 29

33

31

35

43 45

49

47

51 53 55

59

57

2

6 8 10 12 14 16 18 20 22 24 26 28 30

34

32

36 38 40

44

42

46 48 50

54

52

56 58 60

68 70

4

71

65

63

61

39

37

F-RT-BGA3

CRITICAL

DDR3-SODIMM

J3200

62 64

69

67

66

41

14B3 74B3

C3211

6.3V

20%

1

2

CRITICAL

0.1UF

X6S-CERM 0204-1

14A1 74B3

14D1 74A3

14B3 74B3

14A3 74B3

14B3 74B3

26C2 28C5

14B3 74B3

14C3 74B3

14B3 74B3

14C3 74B3

14B3 74B3

14C3 74B3

14D1 74A3

14C3 74B3

14A3 74B3

14B3 74B3

14D1 74A3

14B3 74B3

14D1 74A3

14B3 74B3

14C3 74B3

14B3 74B3

14D1 74A3

8D2

14C1 74B3

14B3 74B3

14C1 74B3

14B1 74B3

14B1 74C3

14C1 74B3

14B1 74B3

0204-1

C3217

20%

0.1UF

1

CRITICAL

X6S-CERM

6.3V

2

14B1 74B3

14C3 74B3

14B3 74B3

14C3 74B3

14B3 74B3

14C3 74B3

14B1 74B3

14C3 74B3

C3216

20%

0.1UF

0204-1

1

2

CRITICAL

X6S-CERM

6.3V

14C3 74B3

14B3 74B3

14C3 74B3

14D1 74A3

14C3 74B3

2

C3236

20%

CERM

1

402

0.1UF

10V

6.3V

2

2.2UF

C3235

CERM

20%

402-LF

1

C3215

6.3V

20%

0204-1

1

2

CRITICAL

0.1UF

X6S-CERM

14C3 74B3

14D3 74B3

14B3 74B3

14D3 74B3

14D1 74A3

27 81

4.7.0

051-7898

SYNC_DATE=05/09/2008

DDR3 SO-DIMM Connector B

SYNC_MASTER=BEN

MEM_B_DQ<4>

MEM_B_DQ<30>

MEM_B_DQS_N<3>

MEM_B_DQ<25>

MEM_B_DQ<29>

MEM_B_DQ<23>

MEM_B_DQ<18>

MEM_B_DM<2>

MEM_B_DQ<16>

MEM_B_DQ<11>

MEM_B_DQ<8>

MEM_RESET_L

MEM_B_DM<1>

MEM_B_DQ<9>

MEM_B_DQ<12>

MEM_B_DQ<2>

MEM_B_DQ<7>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQ<5>

MEM_B_DQS_N<1>

MEM_B_DQ<60>

MEM_B_CAS_L

MEM_B_A<10>

MEM_B_DQ<55> MEM_B_DQ<54>

MEM_B_A<13>

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_A<0>

MEM_B_A<4>

MEM_B_DQ<46>

MEM_B_A<12> MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<1>

MEM_B_DQ<47>

MEM_B_A<15>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_A<5>

MEM_B_A<2>

MEM_B_DQ<61>

MEM_B_DQ<41>

MEM_B_CLK_N<0>

MEM_B_DM<5>

MEM_B_A<3>

MEM_B_DQS_N<6>

MEM_B_DQ<53>

MEM_B_DQ<39>

MEM_B_DQ<35>

MEM_B_DQ<37> MEM_B_DQ<32>

MEM_B_DQS_N<4> MEM_B_DQS_P<4>

MEM_B_DM<0>

MEM_B_DQ<6>

MEM_B_DQ<14>

MEM_B_DQS_P<1>

MEM_B_A<6>

MEM_B_DQ<26> MEM_B_DQ<31>

MEM_B_DQ<21>

MEM_B_CLK_P<1>

MEM_B_SA<1>

=PPSPD_S0_MEM_B

MEM_B_CKE<1>

MEM_B_A<14>

MEM_B_A<11> MEM_B_A<7>

MEM_B_DQ<27>

MEM_B_DQS_N<2>

MEM_B_DQ<20> MEM_B_DQ<17>

MEM_B_DQ<13>

MEM_B_DQ<3>

MEM_B_DM<3>

=PP1V5_S0_MEM_MCP

MEM_B_DQS_P<3>

MEM_B_CLK_P<0>

MEM_B_DQ<57>

MEM_B_DQ<48>

MEM_B_DQ<43>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_RAS_L

MEM_B_BA<1>

MEM_B_CLK_N<1>

MEM_B_DQ<15> MEM_B_DQ<10>

MEM_B_DQ<59>

MEM_B_DQ<51> MEM_B_DQ<50>

MEM_B_DM<6>

MEM_B_DQ<52>

MEM_B_DQ<62>

=PP0V75_S0_MEM_VTT_B

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

MEM_EVENT_L

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DQ<63>

MEM_B_DQ<42>

MEM_B_DQS_P<5>

MEM_B_ODT<1>

MEM_B_DQS_N<5>

MEM_B_DQ<44>

MEM_B_DQ<40>

MEM_B_DQ<38> MEM_B_DQ<34>

MEM_B_DM<4>

MEM_B_DQ<33>

MEM_B_DQ<36>

PP0V75_S3_MEM_VREFCA_B

MEM_B_DQ<28>

MEM_B_DQS_P<2>

MEM_B_DQ<22> MEM_B_DQ<19>

MEM_B_DQ<24>

MEM_B_SA<0>

MEM_B_DM<7>

MEM_B_DQ<58>

MEM_B_WE_L

MEM_B_DQ<45>

=PP1V5_S3_MEM_B

MEM_B_BA<0>

MEM_B_CS_L<1>

MEM_B_DQ<49>

MEM_B_DQ<56>

MEM_B_DQS_P<6>

25C1

7C5

7B6

7C7

25C1

7D3

IN

OUT

D

Q2

SG

Q1

B

C

E

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

must be high before 1.5V starts to

3.3V S5 is used because MEM_RESET

rise to avoid glitch on MEM_RESET_L.

DDR3 RESET Support

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.

15C3

5% 1/16W MF-LF

402

100K

R3305

1

2

26C2 27C2

5% 1/16W MF-LF

402

1K

R3310

1

2

402

0

1/16W MF-LF

5%

R3309

21

R3300

5%

402

MF-LF

1/16W

10K

1

2

DMB53D0UDW

SOT-363

Q3305

5

3

64

21

10V

0.1UF

20%

CERM 402

C3300

1

2

MF-LF

402

1/16W

20K

5%

R3301

1

2

DDR3 Support

051-7898

4.7.0

8128

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

MCP_MEM_RESET_L

=PP1V5_S3_MEMRESET

MEM_RESET_RC_L

MEM_RESET_L

MEM_RESET

=PP3V3_S5_MEMRESET

7D3

7A3

OUT

IN

BI

NC NC

IN

OUT

BI

OUT

Y

B

A

IN

NC

SYM_VER-1

D

SG

D

SG

OUT

IN

D

GS

S

G

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TPCP8102

5V S3 WLAN FET

MOSFET

BLUETOOTH

CHANNEL

0.8 A (EDP)

518S0610

275 mA peak

RDS(ON)

LOADING

P-TYPE

26 mOhm @4.5V

750 mA nominal max

1000 mA peak

ALS

206 mA nominal max

CAMERA

AIRPORT

6D5

16B6

CRITICAL

20347-325E-12

F-RT-SM

9

8

7

6

5

4

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3401

0402-LF

FERR-120-OHM-1.5A

21

L3405

29A4 32C6

43C1

FERR-120-OHM-1.5A

0402-LF

21

L3404

CERM

402

20% 10V

0.1uF

2

1

C3452

16V

0.1uF

10% X5R 402

PLACEMENT_NOTE=Place close to J3401.

21

C3430

16B3 75D3

402

0.1uF

X5R16V

PLACEMENT_NOTE=Place close to J3401.

10%

21

C3431

16C3 75D3

19D3 76C3

20% 10V

402

0.1uF

CERM

PLACEMENT_NOTE=Place close to Q3450.

2

1

C3421

19D3 76C3

19C3 76C3

6D5

16B6 75D3

6D5

16B6 75D3

SOT665

TC7SZ08AFEAPE

4

5

3

1

2

U3401

24C1

74LVC1G17DRL

5

13

2

U3402

SOT-553

4

PLACEMENT_NOTE=Place close to Q3450.

10V

805

10UF

X5R

20%

2

1

C3420

33K

5%

MF-LF 402

1/16W

2

1

R3453

R3454

62K

1/16W

402

MF-LF

5%

2

1

402

CERM

1UF

6.3V

10%

2

1

C3453

PLACEMENT_NOTE=Place close to J3401.

DLP11S

90-OHM-100MA

43

21

L3401

CRITICAL

L3402

12

34

DLP0NS

90-OHM

PLACEMENT_NOTE=Place close to J3401.

CRITICAL

L3403

12

34

PLACEMENT_NOTE=Place close to J3401.

90-OHM DLP0NS

1

2

6

Q3401

SOT563

SSM6N15FEAPE

SOT563

SSM6N15FEAPE

4

5

3

Q3401

16C6

20A3 20C3 32C7

SSM3K15FV

SOD-VESM-HF

2

1

3

Q3455

1

MF-LF

5%

1

402

2

1/16W

R3455

23V1K-SM

213

4

6587

CRITICAL

Q3450

TPCP8102

0.1UF

C3450

402

10% 16V X5R

21

402

10%

X5R

16V

0.033UF

2

1

C3451

R3450

1/16W

5%

402

MF-LF

100K

21

1/16W

10K

MF-LF

5%

402

2

1

R3451

0.1uF

402

CERM

20% 10V

PLACEMENT_NOTE=Place close to J3401.

2

1

C3422

051-7898

SYNC_DATE=04/22/2008

4.7.0

8129

Right Clutch Connector

SYNC_MASTER=YITE

PCIE_CLK100M_MINI_CONN_N

PCIE_CLK100M_MINI_N

P5VWLAN_SS

PM_WLAN_EN_L

=PP3V3_S3_WLAN

WLAN_SMIT_RC

WLAN_SMIT_DISCHRG

USB_BT_P

PP5V_WLAN_F

PCIE_MINI_R2D_P

MINI_RESET_CONN_L

MINI_CLKREQ_Q_L

PCIE_MINI_D2R_N

PCIE_MINI_D2R_P

AP_PWR_EN

PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N

PCIE_CLK100M_MINI_P

USB_BT_N

PCIE_MINI_PRSNT_L

PCIE_MINI_R2D_N

USB_CAMERA_N

PCIE_CLK100M_MINI_CONN_P

MINI_CLKREQ_L

PM_WLAN_EN_L

=PP5V_S3_BTCAMERA

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

PCIE_WAKE_L

MINI_RESET_L

USB_CAMERA_P

WLAN_SMIT_BUF

CONN_USB2_BT_N

CONN_USB2_BT_P

USB_CAMERA_CONN_N

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm

PP5V_WLAN

VOLTAGE=5V

USB_CAMERA_CONN_P

=I2C_ALS_SCL

=I2C_ALS_SDA

PP5V_S3_BTCAMERA_F

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm

VOLTAGE=5V

PP5V_WLAN_F

MIN_LINE_WIDTH=1 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

=PP5V_S3_WLAN

6D5

75D3

29C1 32C6

7D3

29C3

6D5

75D3

6C5

6D5

75D3

6D5

75D3

7C3

6D5

76C3

6C3 6D5

6D5

76C3

6D5

29A5

7C3

BI

VDD

WRITE_PROTECT_SW

CARD_DETECT_SW CARD_DETECT_GND

DAT6 DAT7

DAT1

CD/DAT3

DAT2

DAT4

DAT5

VSS

CLK CMD

DAT0

SHLD_PIN

SHLD_PIN SHLD_PIN

SHLD_PIN

NC

NC NC NC NC NC

NC NC

D

SG

D

SG

IN

X2

DP

CS

PMOSO

D1

VDD5V

D0

SK

DI

DO

D4

D2

D5

DM

GPIO2

D7

X1

GPIO3

GPIO1

VDD18O

AVDD

EXTRSTZ*

D3

DVDD

TESTMOD

CLK

D6

RREF

SD_CDZ

XD_CDZ

XD_CE

XD_WEZ XD_RBZ XD_WPZ

MS_INS

SD_WP

SD_CMD

PDMOD

MS_BS

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

MAX CURRENT = 250MA

IPD/

IPU/

PDMOD: POWER DOWN MODES

IPD/

IPU/

IPD/

/IPD

IPD/

/IPD

(PDMOD)

10K HIGH = REMOTE WAKE UP ENABLE

NC = DISABLE (DEFAULT)

IPU/

/IPU

10K LOW = POWER SAVING MODE ENABLE

0

5% 1/16W

402

MF-LF

2

10UF

6.3V

603

20%

X5R

C3500

1

2

CERM

0.1UF

20% 10V

402

C3501

1

2

5%

1M

MF-LF

402

R3503

12

1/16W

20%

CERM

10V

402

1

2

C3505

0.1UF

C3506

402

0.1UF

CERM

20% 10V

1

2

2.2UF

6.3V CERM1

20%

603

1

2

10V

402

CERM

20%

0.1UF

C3508

1

2

20% 10V

402

CERM

0.1UF

C3502

1

2

10V

20%

402

CERM

0.1UF

C3503

1

2

20%

CERM

10V

0.1UF

C3504

1

2

19C3 76B3

33PF

402

5%

CERM

C3511

12

CRITICAL

Y3500

12

8X4.5X1.4-SM

402

5%

CERM

50V

12

33PF

0805-1

0.22UH

L3500

12

10UF

C3514

1

2

MF-LF

1/16W

39K

402

5%

1

2

R3505

10V

20%

0.1UF

NO STUFF

CERM 402

1

2

402

R3506

MF-LF

1/16W

1%

715

1

2

402

5%

10K

1/16W MF-LF

R3507

1

2

MF-LF 402

NO STUFF

10K

5% 1/16W

R3508

1

2

NO STUFF

10K

1/16W MF-LF 402

5%

R3509

1

2

10K

1/16W MF-LF 402

5%

R3510

1

2

402

5%

0

1/16W MF-LF

12

1/16W

402

MF-LF

5%

10K

R3512

1

2

NO STUFF

402

5%

MF-LF

1/16W

10K

R3513

1

2

SSM6N15FEAPE

SOT563

3

5

4

SSM6N15FEAPE

Q3500

6

2

1

24C1

051-7898

4.7.0

SECUREDIGITAL CARD READER

SYNC_MASTER=VEMURI

SYNC_DATE=01/30/2009

8130

CARDREADER_XTAL1

CARDREADER_RESET

PP3V3_S3_CARDREADER_DVDD

PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

SD_CLK

CARDREADER_RESET_L

PP3V3_S3_CARDREADER_AVDD

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN

PP1V8_S3_CARDREADER

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

SD_WP

SD_CMD

MIN_LINE_WIDTH=0.30MM

PP3V3_SW_SD_PWR

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PLACEMENT_NOTE=KEEP THIS NET AS SHORT AS POSSIBLE

CARDREADER_XTAL2

PP3V3_S3_CARDREADER_DVDD

MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.40MM

CARDREADER_GPIO1

PP3V3_S3_CARDREADER_DVDD

CARDREADER_PLT_RST

CARDREADER_PLT_RST_L

CARDREADER_GPIO2

R3502

1

12.000M-100PPM

R3511

402603

X5R

6.3V

20%

=PP3V3_S3_CARDREADER

50V

C3513

C3512

NO STUFF

SOT563

SD_CD_L

U3500

GL137A

CRITICAL

14

8

20

364325

40

19

22

21

28

37

30

7

47

38

13

46

48

35

4

11

6

18

29

26

15

17

39

32

10

23

1

31

42

44 45

24

3 41 2

33

12

9

5

342716

LQFP

USB_CARDREADER_P

SD_D<1>

SD_D<0>

SD_D<4>

SD_D<2>

SD_D<5>

USB_CARDREADER_N

CARDREADER_GPIO2

SD_D<7>

CARDREADER_GPIO1

SD_D<3>

CARDREADER_TEST_MOD

SD_D<6>

CARDREADER_RREF

CARDREADER_PDMOD

16

6

3

4

20

19

18

17

13

12

11

10

9

8

7

2

5

1

14

15

F-RT-TH

C3507

CRITICAL

1

16B6

OMIT

CONN,SD CARD READER,OPTN B,HF,K19/K24

J3500

SD-CARD-K19

J3500

516-0225

Q3500

30A7 30B4

78C3

30B4 30D6

7C3

30C6 30C6

30A7 30D6

78D3

78C3

30A6

78C3

30A7

78C3

IN

BI

IN

BI

OUT

IN

DVDD33

VDDREG

REGOUT

MDI-[0]

RXD[2]/AN0

LED0/PHYAD0

LED2/RXDLY

LED1/PHYAD1

MDI-[3]

RXD[1]/TXDLY

RXD[3]/AN1

MDI-[1]

MDI+[1]

MDI+[3]

MDI+[2] MDI-[2]

RXCTL

MDC

PHYRSTB*

RSET

CLK125

CKXTAL2

CKXTAL1

MDI+[0]

RXD[0]

GND

MDIO

RXC

TXCTL

AVDD10

DVDD10

ENSWREG

TXD[3]

TXD[2]

TXD[1]

TXD[0]

TXC

AVDD33

FB10

LED

RESET

CLOCK

MANAGEMENT

MEDIA DEPENDENT

RGMII/MII

REFERENCE

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Marvell numbers, update for Realtek

PHYAD = 01 (PHY Address 00001) AN[1:0] = 11 (Full auto-negotiation)

(19mA typ - Energy Detect)

ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE. HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.

Alias to =PP3V3_ENET_PHY for internal switcher.

Reserved for EMI per RealTek request.

PLACE R3796 CLOSE TO U1400, PIN D24

Alias to GND for external 1.05V supply.

If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

If internal switcher is used, must place 1x 22uF &

RXDLY = 0 (RXCLK transitions with data)

WF: Marvell numbers, update for Realtek

(221mA typ - 1000base-T) ( 7mA typ - Energy Detect)

(43mA typ - 1000base-T)

If internal switcher is not used, VDDREG and REGOUT can float.

TXDLY = 0 (No TXCLK Delay)

Configuration Settings:

21

R3724

402

1/16W

5%

MF-LF

0

2

1

C3725

0.1UF

NO STUFF

10V

402

CERM

20%

2

1

R3730

MF-LF

402

1/16W

1%

2.49K

2

1

R3725

MF-LF 402

NO STUFF

1/16W

4.7K

5%

2

1

R3720

402

1/16W MF-LF

5%

10K

2

1

L3705

0402-LF

FERR-120-OHM-1.5A

CRITICAL

2

1

C3705

10%

402

X5R

16V

0.1UF

2

1

C3706

10%

402

X5R

16V

0.1UF

2

1

C3700

10%

402

X5R

16V

0.1UF

2

1

C3701

10%

402

X5R

0.1UF

16V

2

1

C3702

10%

402

X5R

16V

0.1UF

17D3 77D3

17D3 77C3

17D3 77D3

17C3 77D3

17C3 77C3

32A3 77D3

33B8 77C3

33C8 77C3

33B8 77C3

33C8 77C3

21

R3790

402

22

1/16W5%MF-LF

21

R3791

22

5%

1/16W MF-LF

402

21

R3792

22

5%

1/16W MF-LF

402

21

R3793

5%

1/16W MF-LF22402

21

R3794

5%

1/16W MF-LF22402

21

R3795

5%

1/16W MF-LF22402

17D6 77D3

2

1

R3755

1/16W

5%

MF-LF

4.7K

402

2

1

R3756

1/16W

5%

MF-LF

4.7K

402

8D2

2

1

R3752

1/16W

4.7K

5%

MF-LF

402

2

1

R3757

1/16W

5%

MF-LF

4.7K

402

2

1

R3750

402

MF-LF

4.7K

5%

1/16W

2

1

R3751

402

1/16W

5%

4.7K

MF-LF

2

1

L3715

CRITICAL

0402-LF

FERR-120-OHM-1.5A

2

1

C3711

402

10%

X5R

16V

0.1UF

2

1

C3710

10%

402

X5R

16V

0.1UF

2

1

C3714

16V

0.1UF

X5R 402

10%

2

1

C3790

NO STUFF

10PF

50V

CERM

5%

402

21

R3796

0

5% 1/16W

402

MF-LF

17D3 77D3

TQFP

3

6

22

23 24 25 26

39

283610

40

27

19

31

7

473320

14

1

42 43

32

46

29

30

13

9

8

11

4 5

41

18

16

12

35 38

34

17

2

48

45

44

372115

CRITICAL

U3700

RTL8251CA-VB-GR

051-7898

8131

4.7.0

SYNC_MASTER=SUMA

Ethernet PHY (RTL8211CL)

SYNC_DATE=05/23/2008

=PP3V3_ENET_PHY

=PP3V3_ENET_PHY_VDDREG

=RTL8211_REGOUT

ENET_MDI_N<0>

ENET_RXD_R<2>

RTL8211_PHYAD0

RTL8211_RXDLY

RTL8211_PHYAD1

ENET_MDI_N<3>

ENET_RXD_R<1>

ENET_RXD_R<3>

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

PP3V3_ENET_PHYAVDD

ENET_MDI_N<1>

ENET_MDI_P<1>

ENET_MDI_P<3>

ENET_MDI_P<2> ENET_MDI_N<2>

ENET_RXCTL_R

ENET_MDC

RTL8211_PHYRST_L

RTL8211_RSET

TP_RTL8211_CLK125

TP_RTL8211_CKXTAL2

RTL8211_CLK25M_CKXTAL1

ENET_MDI_P<0>

ENET_RXD_R<0>

ENET_MDIO

ENET_CLK125M_RXCLK_R

ENET_TX_CTRL

=PP1V05_ENET_PHY

=RTL8211_ENSWREG

ENET_TXD<3>

ENET_TXD<2>

ENET_TXD<1>

ENET_TXD<0>

ENET_CLK125M_TXCLK_R

ENET_RESET_L

ENET_CLK125M_TXCLK

ENET_RX_CTRL

ENET_RXD<3>

ENET_RXD<2>

ENET_RXD<1>

ENET_RXD<0>

ENET_CLK125M_RXCLK

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_ENET_PHYAVDD

C3715

1

2

6.3V CERM

402-LF

2.2UF

20%

C3716

1

2

2.2UF

6.3V

20%

CERM

402-LF

7B5

8D2

77D3

8D2

77D3

7A5

77D3

G

DS

IN

OUT

D

SG

IN

D

SG

IN

D

SG

D

SG

D

S

G

D

SG

IN

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

I(max) = 1.7A (85C)

Rds(on) = 90mOhm max

@ 2.5V Vgs:

3.3V ENET FET

1.05V ENET FET

MOBILE:

RTL8211 25MHz Clock

1.8V Vgs

=P1V05ENET_EN. Nets separated on

Recommend aliasing PM_SLP_RMGT_L and

ARB for alternate power options.

Non-ARB:

=P3V3ENET_EN. Nets separated on

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.

Recommend aliasing PM_SLP_RMGT_L and

ARB for alternate power options.

Pull-up is with power FET.

Q3810

3

1

2

SOT-23-HF

NTR4101P

CRITICAL

C3810

12

CERM

16V

0.01UF

402

10%

C3811

1

2

16V X5R 402

10%

0.033UF

R3810

12

1/16W

5%

100K

402

MF-LF

17C3 77D3

R3895

12

PLACEMENT_NOTE=Place close to U1400

1/16W

5%

MF-LF

22

402

31B6 77D3

C3841

1

2

10%

402

CERM

0.01UF

16V

C3840

1

2

402

10V

CERM

20%

0.1UF

29A4 29C1

Q3805

3

5

4

SOT563

SSM6N15FEAPE

20C7 35B5 40D5 41B2

Q3801

SSM6N15FEAPE

SOT563

2

1

6

20A3 20C3 29D5

6C3

20C3 35A5 40C5 66D5 70D8

Q3805

6

2

1

SOT563

SSM6N15FEAPE

Q3841

6

2

1

SSM6N15FEAPE

SOT563

R3842

1

2

MF-LF

402

1%

1/16W

69.8K

Q3840

3

1

2

CRITICAL

SOT23

SI2312BDS

R3800

1

2

1/16W MF-LF

402

5%

10K

Q3801

SSM6N15FEAPE

SOT563

5

4

3

8D2

Q3841

3

5

4

SOT563

SSM6N15FEAPE

8D2

R3841

12

MF-LF

1%

1/16W

402

10K

R3840

MF-LF

402

100K

21

1/16W

5%

SYNC_DATE=07/01/2008

SYNC_MASTER=SUMA

32 81

4.7.0

051-7898

Ethernet & AirPort Support

AP_PWR_EN

P1V05ENET_SS

P1V05ENET_EN_L_RC

=P3V3ENET_EN

SMC_ADAPTER_EN

PM_WLAN_EN_L

AC_OR_S0_L

=P1V05ENET_EN

=PP1V05_ENET_FET

P3V3ENET_EN_L

MCP_CLK25M_BUF0_R

RTL8211_CLK25M_CKXTAL1

P3V3ENET_SS

=PP3V3_ENET_FET

PM_SLP_S3_L

=PP1V05_ENET_P1V05ENETFET

P1V05ENET_EN_L

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P1V05ENETFET

7B6

7B3

7A3

BI

RX

TX

RX

TX

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ETHERNET CONNECTOR

PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902

514-0636

- COPY THIS PAGE FROM K36 CSA.39

31B3 77C3

CRITICAL

2

402-1

1

10PF

C3911

50V CERM

5%

CRITICAL

2

1

402-1

5%

C3912

10PF

50V CERM

CRITICAL

2

1

402-1

50V

10PF

C3913

5%

CERM

CRITICAL

2

1

402-1

C3914

50V CERM

10PF

5%

10PF

CRITICAL

2

1

402-1

C3915

5%

CERM

50V

CRITICAL

C3916

2

1

402-1

10PF

50V

5%

CERM

CRITICAL

2

1

402-1

C3917

50V CERM

10PF

5%

CRITICAL

2

1

402-1

C3918

5%

10PF

CERM

50V

RJ45-M97-3

J3900

CRITICAL

1

2

4

12

11

10

9

6

5

3

7

8

F-RT-TH

C3902

1

2

X5R

16V

402

10%

0.1UF

X5R

10%

402

16V

0.1UF

2

1

C3900 C3901

1

2

10% 16V X5R

0.1UF

402

1

2

10%

X5R

16V

402

0.1UF

C3903

R3900

12

75

MF-LF1/16W

1%

402

1%

R3901

12

1/16W MF-LF

402

75

R3902

12

1%

1/16W

402

MF-LF

75

R3903

12

402

1/16W

75

1%

MF-LF

C3910

1

2

1000PF

CRITICAL

CERM 1206

10% 2KV

CRITICAL

11

1

T3902

10

12

2

3

4

5

67

8

9

SM

TLA-6T213HF

T3901

1

10

11

12

2

3

4

5

67

8

9

SM

TLA-6T213HF

CRITICAL

81

051-7898

4.7.0

33

SYNC_MASTER=SUMA

SYNC_DATE=04/04/2008

ETHERNET CONNECTOR

ENET_MDI_TRAN_P<0>

ENET_MDI_TRAN_N<0>

ENET_MDI_TRAN_P<2>

ENET_MDI_TRAN_N<1>

ENET_MDI_TRAN_N<2>

ENET_MDI_TRAN_P<1>

ENET_MDI_TRAN_P<3>

ENET_MDI_TRAN_N<3>

ENET_CONN_CTAP

ENET_MDI_P<2>

ENET_MDI_N<1>

ENET_MDI_P<3>

ENET_MDI_P<1>

ENET_CENTER_TAP<0>

ENET_CENTER_TAP<3>

ENET_CENTER_TAP<1>

MIN_NECK_WIDTH=0.25MM

ENET_BOB_SMITH_CAP

MIN_LINE_WIDTH=0.6MM

ENET_CENTER_TAP<2>

PLACEMENT_NOTE=PLACE C3911-C3918 ON MDI LINES WITHOUT ANY STUBS

ENET_MDI_N<2>

ENET_MDI_P<0>

ENET_MDI_N<3>

ENET_MDI_N<0>

77C3

DS2

ATBUSH ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620* JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK SCIFDAIN SCIFDOUT

SCIFMC

SCL SDA

SE SM

TDO

TPA1N

TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P

TPBIAS0 TPBIAS1 TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH

VP

VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33

VDD10

VREG_VSS

VSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NC NC NC

NC

IN

OUT

IN

BI

IN

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

NT-2 (IPU)

NT-1 (IPU)

FIXME!!! - TYPO IN SYMBOL REGCTL

NT-4 (IPU)

NAND tree order.

NOTE: NT-xx notes show

NT-10 (IPD)

(IPD) NT-18

NT-12 (IPD)

NT-13

(IPU)

(IPD) NT-21

(IPU)

(IPD) NT-20

(IPD) NT-19

(IPD)

NT-9

(Reserved)

NT-OUT

NT-14 (IPD)

NT-5

NT-17

NT-16 (IPD)

(OD)

NT-3 (IPU)

17 mA PCIe SerDes

0 mA VReg PWR

114 mA FireWire PHY

138 mA

(IPD)

(IPU) NT-8

NT-15 (IPD)

7 mA I/O

25 mA PCIe SerDes

NT-7 NT-6

135 mA

(IPD) NT-11

110 mA Digital Core

R4170

1

2

402

MF-LF

1/16W

1%

191

C4162

1

2

10%

402

6.3V

0.33UF

CERM-X5R

R4162

1

2

402

470K

MF-LF

5%

1/16W

CRITICAL

U4100

FW643E

BGA

G7

K8K9L7

L12

E2

H12H2L1

M12K2C1F1G12J1C12

A5

F12

F13

G13

C2

F6F4E9

D10

D9

K7K5K4

J10

J4

H10

H8

H7D7H6

H4

G4

F10

F8

F7

D4

B2

K12

L10

L5

D6D5A12

M2

B1

H13

D2

B10

A2

C3

B7

A4

B4

A6

B6

A9

B9

A3

B3

B5

N13

M13

M11

N12

H1

G1

G2

L8

D13

N10

B11

N4

N5

N7

N8

J13

K1

J2

D1

D12

K13

L2

L13

A10

N3

N11

A1

A8

B8

E12

N2

B13

E4

E5

J5

N1

N6

N9

M4

M3

E1

J12

D8

L6

L9

K6

K10

L3

L11

J9

G6

G10

G8

A11

A13

C13

E10

E13

B12

F2

M1

C4151

12

402

50V

5%

22PF

CERM

C4150

12

402

CERM

5%

50V

22PF

R4160

1

2

MF-LF

1/16W

200K

1%

402

21

412

MF-LF

1%

1/16W

402

R4150

R4163

1

2

402

1/16W

5%

MF-LF

10K

R4164

1

2

402

1/16W

5%

MF-LF

10K

R4165

1

2

402

10K

MF-LF

5%

1/16W

FW643_LDO

C4176

12

10%

402X5R

16V

PLACEMENT_NOTE=Place C4176 close to U4000

0.1UF

C4175

12

10%

402X5R

16V

PLACEMENT_NOTE=Place C4175 close to U4000

0.1UF

R4166

1

2

402

1/16W

5%

MF-LF

10K

C4171

12

10%

402X5R

16V

PLACEMENT_NOTE=Place C4171 close to U1400

0.1UF

12

10%

402X5R

16V

PLACEMENT_NOTE=Place C4170 close to U1400

0.1UF

C4170

1

2

10%

1UF

6.3V CERM

C4130

402

C4131

1

10%

1UF

402

CERM

6.3V 2

2

1

1UF

402

6.3V CERM

10%

1

2

10%

1UF

402

6.3V CERM

C4101

C4132

1UF

1

2

10%

6.3V CERM

402

C4102

1

2

10%

1UF

402

6.3V CERM

C4103

1

2

10%

1UF

402

6.3V CERM

C4135

1

10%

1UF

402

CERM

6.3V 2

C4136

2

10%

1UF

1

CERM

6.3V

402

C4104

1

2

10%

1UF

402

6.3V CERM

C4110

1

1UF

6.3V

10%

2

402

CERM

C4105

1

2

10%

1UF

402

6.3V CERM

C4106

1

2

10%

1UF

402

6.3V CERM

C4120

1

2

10%

1UF

6.3V CERM

402

C4121

1

2

10%

1UF

402

6.3V CERM

1

2

10%

1UF

402

CERM

C4122

6.3V

C4123

1

2

10%

1UF

402

6.3V CERM

C4124

1

2

10%

1UF

402

6.3V CERM

C4141

1

2

10V

402

0.1UF

CERM

20%

C4111

1

2

10%

1UF

402

6.3V CERM

C4140

1

10%

1UF

402

6.3V CERM

2

16C3

16B3 75D3

16B6 75D3

8C2

35C8

35C4

R4161

1

2

402

1/16W

1%

MF-LF

2.94K

36D3

36C4 78D3

36B8 78D3

36C4

36C4 78D3

36B8 78D3

36C4

36D4

35A4 36C8

36D4

L4130

12

120-OHM-0.3A-EMI

0402-LF

L4135

12

0402-LF

120-OHM-0.3A-EMI

35C1

21

L4110

120-OHM-0.3A-EMI

Y4150

24

13

CRITICAL

SM-3.2X2.5MM

24.576MHZ

FireWire LLC/PHY (FW643)

SYNC_MASTER=K19_MLB

34 81

4.7.0

051-7898

SYNC_DATE=11/02/2008

R4100

RES,0.68 OHM,1%,0402,SMD

1

CRITICAL

PCIE_FW_D2R_C_P

PCIE_FW_D2R_C_N

PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P

PCIE_FW_R2D_P

TP_FW643_SCIFDAIN

TP_FW643_SCIFCLK

TP_FW643_SCIFDOUT TP_FW643_SCIFMC

FW643_TPCPS

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

FW_P0_TPA_N FW_P0_TPA_P

FW_P0_TPB_P

TP_FW643_VAUX_ENABLE

=FW_PHY_DS1

=PP3V3_FW_FWPHY

=FW_PHY_DS0

=FW_PHY_DS2

FW_P2_TPB_P

FW_P2_TPB_N

FW_P1_TPB_P

FW_P1_TPB_N

FW_P0_TPB_N

FW_P2_TPA_P

FW_P2_TPA_N

FW_P1_TPA_N FW_P1_TPA_P

TP_FW643_VBUF

TP_FW643_TDO

TP_FW643_SDA

FW_RESET_L

TP_FW643_JASI_EN

TP_FW643_FW620_L

TP_FW643_AVREG

TP_FW643_TMS

FW643_SCL

FW643_TRST_L

FW643_VAUX_DETECT

=PPVP_FW_PHY_CPS

FW_CLK24P576M_XO

FW_CLK24P576M_XO_R

FW643_REXT

TP_FW643_SE

TP_FW643_CE

TP_FW643_SM

TP_FW643_OCR10_CTL

FW643_PU_RST_L

FW643_R0

FW_P2_TPBIAS

FW_P1_TPBIAS

FW_P0_TPBIAS

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY_VP25

=PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.0V

PP1V0_FW_FWPHY_AVDD

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY_VDDA

PCIE_FW_R2D_N

TP_FW643_TCK TP_FW643_TDI

TP_FW643_MODE_A

FW_CLK24P576M_XI

TP_FW643_NAND_TREE

=FW_CLKREQ_L

FW643_REGCTL

=FW_PME_L

C4100

0402-LF

PP1V0_FW_R

=PP1V0_FW_FWPHY

402

1

0

R4100

2

OMIT

MF-LF

1/16W

5%

114S0558

75D3

7B1

34D2 35D8 36B6 36D5

36C4

7B1

34B1 35D8 36B6 36D5

75D3

7A1

35D3

E

Q2

C

BD

Q1

GS

G

D

S

G

D

S

IN

G

DS

D

SG

D

SG

D

SG

D

S

G

IN

D

SG

D

SG

OUT

IN

OUT

IN

G

D

S

G

D

S

G

D

S

IN

V-

V+

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT OF

SIZE

D

1.05V FW FET

- =PP3V3_FW_LATEVG_ACTIVE

- =PPVP_FW_SUMNODE (power passthru summation node)

is running or on AC.

Enables port power when machine

Page Notes

@ 2.5V Vgs:

3.08V when port power is on

FireWire Port Power Switch

3.3V FW FET

I(max) = 1.7A (85C)

Power aliases required by this page:

PP1V05_FW PGOOD/FW_RESET_L

Rds(on) = 90mOhm max

BOM options provided by this page:

(NONE)

Signal aliases required by this page:

- =PPBUS_S5_FWPWRSW (system supply for bus power)

2.91V when late Vg event and port power is off

FWLATEVG Hysteresis:

Late-VG Event Detection

0.1UF

20% 10V

2

CERM

1

C4210

402

R4210

200K

1% 1/16W MF-LF

402

21

R4211

402

MF-LF

2

1

10K

5%

1/16W

2

1

100pF

CERM

402

5%

50V

C4211

1%

10K

2

1

1/16W 402

2

1

R4213

MF-LF

1% 1/16W

402

80.6K

21

R4263

100

1%

402

1/16W MF-LF

NOSTUFF

X5R

1UF

10%

402

10V

C4263

1

2

NOSTUFF

12

65

CRITICAL

SOT-563

4

DMB54D0UV

Q4262

SOT563

BC847CDXV6TXG

Q4270

CRITICAL

1

6

2

4

3

5

Q4270

CRITICAL

SOT563

BC847CDXV6TXG

MF-LF

330K

402

2

1

1/16W

5%

2

1

56K

MF-LF 402

5% 1/16W

2

1

R4274

5%

402

MF-LF

100K

1/16W

2

1

R4273

12K

402

MF-LF

1/16W

5%

2

1

R4272

1/16W

1K

5%

402

MF-LF

1

2

6

DMB53D0UV

SOT-563

CRITICAL

Q4275

4

3

5

CRITICAL

DMB53D0UV

SOT-563

1

2

6

Q4299

DMB53D0UV

SOT-563

CRITICAL

21

R4283

402

5%

MF-LF

1/16W

10K

24C1

2

1

C4281

6.3V

1UF

10%

CERM

402

4

3

5

Q4299

SOT-563

DMB53D0UV

CRITICAL

21

R4280

10K

1/16W

1%

MF-LF

402

2

1

R4281

402

100K

5% MF-LF

1/16W

2

1

R4290

10K

5%

402

MF-LF

1/16W

21

R4291

100K

MF-LF

402

5%

1/16W

2

1

C4290

16V

10%

402

X5R

0.033UF

2

1

3

Q4291

NTR4101P

SOT-23-HF

CRITICAL

21

C4291

10% 16V

402

CERM

0.01UF

4

5

3

Q4290

SSM6N15FEAPE

SOT563

Q4293

4

5

3

SSM6N15FEAPE

SOT563

MF-LF

1/16W

10K

402

5%

R4295

1

2

MF-LF

2

100K

1

R4296

1/16W

5%

402

21

220K

402

MF-LF

1/16W

5%

R4297

1

2

6

Q4293

SSM6N15FEAPE

SOT563

2

1

0.068UF

CERM 402

10% 10V

C4295

2

1

3

Q4295

CRITICAL

SI2312BDS

SOT23

34B2

1

2

6

Q4264

SSM6N15FEAPE

SOT563

4

5

3

Q4264

SOT563

SSM6N15FEAPE

16C6 8C6

16C6

2

1

C4270

0.1UF

10% 16V X5R 402

36C8 34B6

35D7 8C1

34A2

35C7 35C4 35A4 18D7 18D2

2

1

0.1UF

CERM

20% 10V

402

C4296

2

1

402

1K

5% MF-LF

1/16W

35D6 35C7 35C4 18D7 18D2

FWPHY_WAKE_YES

4

SOT-563

5

DMB53D0UV

CRITICAL

3

Q4276

FWPHY_WAKE_YES

CRITICAL

Q4276

DMB53D0UV

6

SOT-563

1

2

FWPHY_WAKE_YES

5% 1/16W MF-LF

100K

R4276

2

1

402

SM

21

D4260

FDC638P_G

5

CRITICAL

6

2

1

4

3

SM

Q4260

300K

1/16W

2

R4260

1

MF-LF

5%

SOT-363

4

5

3

470K

1

1/16W

5%

402

MF-LF

SOT-363

1

2

6

Q4261

2N7002DW-X-G

41B2

40D5

32B7

20C7

70D8 66D5 40C5 32B7 20C3 6C3

FWPHY_WAKE_YES

R4277

402

1/16W

10K

5%

MF-LF

2

1

SM-HF

3

4

5

2

1

LMC7211

U4210

FireWire Port Power

SYNC_MASTER=YUN_K19_MLB

8135

051-7898

4.7.0

LATEVG_EVENT

FW_PLUG_DET

FWPWR_EN_L

P1V05_FW_EN_L

=PP3V3_S5_P1V05FWFET

=PP1V0_FW_FET

P1V05FW_SS

SMC_ADAPTER_EN

FW_PWR_EN

PM_SLP_S3_L

VOLTAGE=12.6V

=PPBUS_S5_FW_FET

=PP3V3_S0_FWPWRCTL

FW_P1_TPBIAS

=PP1V05_FWPWRCTL

LATEVG_FAULT_EVENT_PNP

=PP1V05_FW_P1V05FWFET

=PP3V3_FW_FET

=PP3V3_S0_P3V3FWFET

LATEVG_RETRY_RC

=PP3V3_S0_FWPWRCTL

=PP1V0_FW_FWPHY

FW_RESET_L

P1V0_RESET_GATE

P1V0_FW_RC

=FW_RESET_L

FW_PLUG_DET_L

FW_DET_EMIT

FW_P1_TPBIAS_R

FW_PWR_EN

P3V3FW_SS

P3V3FW_EN_L

PCIE_FW_PRSNT_L

MAKE_BASE=TRUE

FW_CLKREQ_L

=PP3V3_S0_P1V05FWFET

FW_CLKREQ_PHY_L

MAKE_BASE=TRUE

=FW_CLKREQ_L

FW_PWR_EN

FW_PLUG_DET_L

FW_PWR_EN

FW_WAKE

P2V4_FWLATEVG_RC

=FW_PME_L

=PP3V3_FW_FWPHY

PP2V4_FW_LATEVG

FW_PWR_EN_L

FWLATEGV_3V_REF

=PP3V3_FW_LATEVG_ACTIVE

LATEVG_FAULT_EVENT

=PPBUS_S5_FWPWRSW

FWPWR_EN_L_DIV

P1V05_FW_EN_L_RC

CRITICAL

MIN_LINE_WIDTH=0.5 mm VOLTAGE=12.6V

CRS08-1.5A-30V

PPBUS_FW_FWPWRSW_D

MIN_NECK_WIDTH=0.25 mm

R4270

PPBUS_FW_FWPWRSW_F

R4271

CRITICAL

F4260

1.1A-24V

MIN_LINE_WIDTH=0.5 mm

MINISMDC110H24

12

MIN_NECK_WIDTH=0.25 mm

SYNC_DATE=12/22/2008

Q4275

FW_DET_MIRROR

MF-LF

R4212

3

2

R4275

2N7002DW-X-G

Q4261

R4261

402

C4260

2

1

402

10%

X5R

25V

0.1UF

21

R4265

1/16W

402

MF-LF

1%

10K

7A3

7B2

35D2 7B5

7C7

7B2

7B5

35B1 7B5

34D8 7A1

7B1

35D6 35C7 35A4 18D7 18D2

35B1 8C1

35D6 35C4 35A4 18D7 18D2

34B2

8C2

36B6 34D2 34B1

36D5

7B1

36C5 36A5

7A3

7C1

SC/NC

TPA+

TPA(R)

VG

VPTPB+

TPB(R)

TPB-

TPA-

CHASSIS

GND

SGD

(SYM-VER2)

G

S

(SYM-VER1)

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

"Snapback" & "Late VG" Protection

Late-VG Protection Power

to at least 2.1V for FW signal integrity

R4390 should be 390 Ohms max for a 3.3V rail

constrained on this page. It is

provide the appropriate constraints

Configures PHY for:

NOTE: This page is expected to contain

- 1-port Portable Power Class (0)

- Port "1" Bilingual (1394B)

for snap-back diodes

PP2V4_FWLATEVG needs to be biased

and should be biased to 2.4V for margin

assumed that FireWire PHY page will

Termination

FW spec calls out 0.33uF

Place close to FireWire PHY

TI PHYs require 1uF even though

- =PPVP_FW_PORT1

- =PP3V3_FW_LATEVG

514S0605

beta-only device, there is no DC path between them (to avoid ground offset issue)

BREF should be hard-connected to logic ground for speed signaling and connection

appropriate connectors and/or to

NOTE: FireWire TPA/TPB pairs are NOT

Cable Power

(GND_FW_PORT1_VG)

(FW_PORT1_BREF)

AREF needs to be isolated from all

INPUT

NC

TPB<R>

TPB-

TPA-

TPA+

ESD and late-VG rail

(Common to all ports)

(NONE)

OUTPUT

BILINGUAL

- =GND_CHASSIS_FW_EMI_R

(NONE)

FireWire Design Guide (FWDG 0.6, 5/14/03)

1394b implementation based on Apple

the necessary aliases to map the FireWire TPA/TPB pairs to their

- =GND_CHASSIS_FW_PORT1

PORT 1

BOM options provided by this page:

properly terminate unused signals.

FireWire PHY Config Straps

NC

VP

TPB+

VG

TPA<R>

When a bilingual device is connected to a

Note: Trace PPVP_FW_PORT1 must handle up to 5A

local grounds per 1394b spec

Power aliases required by this page:

to apply to entire TPA/TPB XNets.

Signal aliases required by this page:

Page Notes

R4363

1

2

1/16W

1%

402

MF-LF

56.2

SIGNAL_MODEL=EMPTY

R4364

1

2

4.99K

1%

1/16W

402

MF-LF

R4362

1

2

56.2

402

MF-LF

1/16W

1%

SIGNAL_MODEL=EMPTY

C4364

1

2

25V

5%

402

CERM

220pF

R4361

1

2

SIGNAL_MODEL=EMPTY

402

1/16W MF-LF

56.2

1%

C4360

1

2

402

10%

6.3V CERM-X5R

0.33UF

R4360

1

2

SIGNAL_MODEL=EMPTY

56.2

402

MF-LF

1% 1/16W

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

C4319

1

2

0.1uF

X7R

603-1

10% 50V

R4319

1

2

1M

1/16W

5%

402

MF-LF

C4314

1

2

402

10%

X7R

50V

0.01UF

CRITICAL

L4310

12

SM

FERR-250-OHM

C4310

1

2

X7R 402

10% 50V

0.01uF

DP4310

1

2

6

BAV99DW-X-G

SOT-363

C4311

1

2

402

0.01uF

50V

10%

X7R

CRITICAL

SOT-363

BAV99DW-X-G

DP4310

4

5

3

2

BAV99DW-X-G

DP4311

1

6

SOT-363

CRITICAL

DP4311

4

5

3

BAV99DW-X-G

SOT-363

C4313

1

2

X7R 402

10% 50V

0.01uF

C4312

1

2

402

X7R

10% 50V

0.01uF

R4390

12

332

MF-LF

402

1%

1/16W

D4390

1

3

MMBZ5227BLT1H

SOT23

CRITICAL

J4310

1

10

11

12

13

2

3

4

5

6

7

8

9

CRITICAL

F-RT-TH

1394B-M97

R4381

1

2

10K

1/16W

1%

402

MF-LF

R4382

1

2

10K

MF-LF

1%

1/16W

402

R4380

1

2

1%

MF-LF

1/16W

10K

402

Q4300

3

5

4

SOT-363

BSS8402DW

Q4300

6

2

1

SOT-363

BSS8402DW

R4312

1

2

5%

402

MF-LF

1/16W

330K

R4311

1

2

MF-LF

402

5%

1/16W

470K

8136

4.7.0

051-7898

FireWire Ports

SYNC_MASTER=K19_MLB

SYNC_DATE=11/02/2008

MAKE_BASE=TRUE

FWPHY_DS2

VOLTAGE=33V

PPVP_FW_PORT1_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

FW_PORT1_AREF

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=12.6V

PPVP_FW_CPS

MIN_NECK_WIDTH=0.2 mm

FW_P1_TPBIAS

MAKE_BASE=TRUE

FW_PORT1_TPB_P

NC_FW0_TPBN

MAKE_BASE=TRUE

NC_FW2_TPAP

MAKE_BASE=TRUE

NC_FW0_TPAN

MAKE_BASE=TRUE

FW_P0_TPBIAS FW_P2_TPBIAS FW_P0_TPA_N

FW_P2_TPA_P

NC_FW2_TPAN

MAKE_BASE=TRUE

NC_FW0_TPAP

NC_FW0_TPBIAS

MAKE_BASE=TRUE

NC_FW2_TPBIAS

MAKE_BASE=TRUE

FW_P0_TPB_N

FW_P2_TPB_N

FW_P1_TPB_P

FW_P0_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_TPA_P

FW_PORT1_TPB_N

MAKE_BASE=TRUE

VOLTAGE=2.4V

PP2V4_FW_LATEVG

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

FW_PORT1_TPB_C

FW_P1_TPB_N

=PP3V3_FW_LATEVG

=PPVP_FW_PORT1

FW_P1_TPA_P

FWPHY_DS1

MAKE_BASE=TRUE

FWPHY_DS0

MAKE_BASE=TRUE

=FW_PHY_DS2

=FW_PHY_DS1

=FW_PHY_DS0

=PP3V3_FW_FWPHY

NC_FW0_TPBP

MAKE_BASE=TRUE

FW_P2_TPA_N

FW_P0_TPA_P

MAKE_BASE=TRUE

NC_FW2_TPBN

FW_P2_TPB_P

MAKE_BASE=TRUE

NC_FW2_TPBP

FW_P1_TPA_N

=PPVP_FW_PHY_CPS

=PPVP_FW_PHY_CPS_FET

=PP3V3_FW_FWPHY

CPS_EN_L

CPS_EN_L_DIV

FW_PORT1_TPB_P

FW_PORT1_TPB_N

PP2V4_FW_LATEVG

FW_PORT1_TPA_N

FW_PORT1_TPA_P

34B6 35A4

36B5

34B6

34C6 78D3

34B6

34B6 78D3

34B6

34B6 78D3

36B5

35A8 36C5

34B6 78D3

7A3

7B1

34B6 78D3

34C6

7B1

34B1 34D2 35D8 36B6

34B6

34B6 78D3

34B6

34B6 78D3

34B7

7B1

34B1 34D2 35D8 36D5

36B7

35A8 36A5

36B7

S

G

D

OUT

IN

SYM_VER-1

OUT

IN

D

SG

D

SG

SYM_VER-1

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Indicates disc presence

516S0616

SATA ODD

ODD Power Control

NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.

516S0687

SATA HDD/IR/SIL

2

R4531

1/16W

4.7

5%

1

402

MF-LF

0.001UF

10% 50V

402

1

2

CERM

C4531

MF-LF

10

R4532

1

1/16W

402

2

5%

402

X7R-CERM

10% 16V

0.1UF

1

2

C4532

17

19

18

F-ST-SM

CRITICAL

J4501

54722-0224

22

20

12

8

6

4

2

21

15

11

9

5

3

1

14

10

7

16

13

213

4

6587

23V1K-SM

TPCP8102

Q4590

CRITICAL

2

6.3V

10%

C4503

402

1UF

1

CERM

2

0402

FERR-220-OHM

1

L4502

6B7

40B8

R4590

1/16W

5%

MF-LF

33K

402

1

2

20B3

CRITICAL

DLP11S

90-OHM-100MA

PLACEMENT_NOTE=Place FL4520 close to J4500

FL4520

12

34

DLP11S

CRITICAL

12

34

FL4525

90-OHM-100MA

PLACEMENT_NOTE=Place FL4525 close to J4500

19D6 75A3

SOT563

SSM6N15FEAPE

Q4596

3

5

4

1/16W

5%

402

MF-LF

100K

R4597

SOT563

SSM6N15FEAPE

Q4596

6

2

1

1/16W

5%

402

MF-LF

100K

R4596

5%

1/16W

402

MF-LF

100K

R4595

12

2

CERM

0.068UF

10V

10%

402

C4595

1

C4596

10% 16V

402

CERM

0.01UF

12

16V10% 402

CERM

0.01UF

PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520

C4521

12

16V10% 402

CERM

0.01UF

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79

C4520

12

CERM

16V10% 402

0.01UF

12

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500

C4526

PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

10% 402

CERM

0.01UF

C4525

12

16V

FERR-70-OHM-4A

21

0603

L4500

CRITICAL

2

1

0.1UF

CERM 402

20% 10V

C4501

DLP11S

90-OHM-100MA

3

FL4501

12

4

CRITICAL

C4502

10V

20%

402

CERM

0.1UF

1

2

FL4502

43

21

90-OHM-100MA

DLP11S

CRITICAL

19D6 75A3

21

C4516

0.01UF

CERM

40210% 16V

16V10% 402

CERM

0.01UF

C4510

12

1

C4511

2

0.01UF

CERM

40210% 16V

16V10%

0.01UF

21

C4515

CERM

402

11

9

5

54722-0164

15

13

7

3

1

16

14

12

10

8

6

4

2

F-ST-SM

J4500

CRITICAL

SYNC_DATE=12/04/2008

SATA Connectors

SYNC_MASTER=K19_MLB

051-7898

4.7.0

8137

SYS_LED_ANODE_R

SATA_HDD_R2D_N

SATA_HDD_D2R_C_P

=PP5V_S3_IR

MIN_LINE_WIDTH=0.6mm VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

PP5V_SW_ODD

MIN_LINE_WIDTH=0.6mm

PP5V_S0_HDD_FLT

MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

PP5V_S3_IR_R

ODD_PWR_SS

=PP5V_S3_ODD

SMC_ODD_DETECT

SATA_HDD_D2R_C_N

SATA_HDD_D2R_N

=PP5V_S0_HDD

ODD_PWR_EN

ODD_PWR_EN_L

ODD_PWR_EN_LS5V_L

=PP3V3_S0_ODD

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_UF_N

SATA_HDD_R2D_UF_P

SATA_HDD_D2R_P

SATA_HDD_D2R_UF_N

SATA_HDD_D2R_UF_P

SATA_ODD_D2R_C_P

SATA_ODD_R2D_P SATA_ODD_R2D_N

=PP3V3_S0_ODD

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_N

SATA_ODD_D2R_P

SATA_ODD_R2D_UF_P

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_UF_P

SATA_ODD_D2R_UF_N

SATA_HDD_R2D_P

=PP1V5_S3_HDD

IR_RX_OUT

PP1V5_S3_HDD_FLT

SYS_LED_ANODE

SATA_ODD_D2R_C_N

PLACEMENT_NOTE=PLACE C4503 CLOSE TO J4501

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

PLACEMENT_NOTE=Place FL4501 close to J4501

PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501

PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

PLACEMENT_NOTE=Place C4516 close to J4501

PLACEMENT_NOTE=Place C4510 close to MCP79

PLACEMENT_NOTE=Place C4511 next to C4510

PLACEMENT_NOTE=Place C4515 next to C4516

6A7 6B7

75A3

6B7

75A3

7C3

39D7

6B7 6C3

6A7

7C3

6B7

75A3

7D5

7C5

37C7

75A3

6B7

75A3

6B7

75A3

6A7 6B7

75A3

7C5

37D6

75A3

6B7

75A3

7D3

6A7 39D4

41A6

6B7

75A3

OUT

BI

SYM_VER-1

IN

OUT

IN

SYM_VER-1

BI

OUT

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

IN

OUT2

TPAD

GND

OUT1

OC1*

EN2

EN1

OC2*

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION

We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.

USB/SMC Debug Mux

Port Power Switch

USB PORT B (BACK PORT)

SEL=0 Choose SMC

Place L4600 and L4605 at connector pin

SEL=1 Choose USB

USB PORT A (FRONT PORT)

STUFF R4691 IF USING TPS2060(ACTIVE LOW ENABLE) STUFF R4690 IF USING TPS2064(ACTIVE HIGH ENABLE)

We can add protection to 5V if we want, but leaving NC for now

514-0638

FERR-220-OHM-2.5A

1

L4605

2

CRITICAL

PLACEMENT_NOTE=NEAR J4600

0603

POLY-TANT

100UF

C4696

CRITICAL

6.3V

20%

2

1

CASE-B2-SM

20%

10UF

6.3V 2

1

C4695

X5R 603

C4691

10V

0.1UF

2

1

20%

CERM 402

19C2

19D3 76C3

402

1

2

C4650

10V

20%

SMC_DEBUG_YES

0.1UF

CERM

MF-LF 402

1/16W

1

2

10K

5%

R4650

1

DLP0NS

90-OHM

PLACEMENT_NOTE=NEAR J4600

43

2

L4600

CRITICAL

40B8 40C5 41B2 42C3

40B8 40C5 41C2 42C5

40B8

21

R4651

402

5%

0

MF-LF

1/16W

SMC_DEBUG_NO

12

MF-LF

1/16W

5%

402

0

SMC_DEBUG_NO

R4652

2

1

0.01uF

16V

402

CERM

C4605

20%

0.01uF

C4615

2

1

CERM

20% 16V

402

PLACEMENT_NOTE=NEAR J4610

CRITICAL

L4615

0603

21

FERR-220-OHM-2.5A

PLACEMENT_NOTE=NEAR J4610

43

12

DLP0NS

L4610

90-OHM

CRITICAL

1

X5R

10UF

2

C4617

603

6.3V

20%

CASE-B2-SM

6.3V POLY-TANT

20%

CRITICAL

100UF

2

1

C4616

19C3 76B3

19C2

24

D4600

5

1

RCLAMP0502N

6

3

SLP1210N6

CRITICAL

6

3245

1

SLP1210N6

CRITICAL

RCLAMP0502N

D4610

6.3V

603

C4690

2

1

10UF

X5R

20%

NOSTUFF

SMC_DEBUG_YES

U4650

PI3USB102ZLE

CRITICAL

TQFN

4

5

2

1

6

7

8

10

39

66B6

MSOP

2

5

3

4

8

7

19

6

CRITICAL

U4690

TPS2064DGN

F-RT-TH-M97-4

8

7

6

5

3

4

2

1

USB

CRITICAL

J4600

J4610

F-RT-TH-M97-4

8

7

6

5

3

4

2

1

USB

CRITICAL

SYNC_DATE=01/18/2008

38 81

4.7.0

051-7898

SYNC_MASTER=YUAN.MA

External USB Connectors

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_RTUSB_B_F

CONN_USB_EXTB_N CONN_USB_EXTB_P

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

CONN_USB_EXTA_N

CONN_USB_EXTA_P

USB_EXTA_MUXED_N

PP5V_S3_RTUSB_B_ILIM

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

PP5V_S3_RTUSB_A_ILIM

USB_EXTA_OC_L

USB_EXTB_OC_L

=PP5V_S3_EXTUSB

USB_EXTA_N

USB_EXTA_P

SMC_RX_L SMC_TX_L

USB_DEBUGPRT_EN_L

USB_EXTB_P

USB_EXTB_N

USB_EXTA_MUXED_P

=PP3V42_G3H_SMCUSBMUX

=USB_PWR_EN

76B3

76C3

7C3

76C3

7D1

IN

P0_3/INT1 P0_4/INT2 P0_5/TIO0 P0_6/TIO1

P0_7

P0_2/INT0

P0_1

THRM_PAD

NC

P1_7

P1_6/MISO

P1_5/SMOSI

P1_4/SCLK

P3_1

P3_0

P1_3/SSEL

P1_2/VREG

VDD

P1_1/D-

P1_0/D+

VSS

NC

P2_1

P2_0

P0_0

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

6A7

37A7

2

1

C4801

0.1UF

402

16V

10%

X7R-CERM

13

16

33

22

21

8

9

26

25

24

23

20

18

15

14

32

1

2

3

4

5

6

7

31

30

29

28

27

19

17

12

11

10

U4800

CRITICAL

OMIT

CY7C63833

QFN

C4803

2

1

402-1

X5R

10V

10%

1UF

19D3 76B3

21

R4800

MF-LF

5%

100

1/16W

402

2

1

C4804

10%

402

50V

0.001UF

CERM

Front Flex Support

SYNC_MASTER=YUAN.MA

SYNC_DATE=05/28/2008

39 81

4.7.0

051-7898

USB_IR_N

DIFFERENTIAL_PAIR=USB2_IR

USB_IR_P

DIFFERENTIAL_PAIR=USB2_IR

IR_VREF_FILTER

IR_RX_OUT

IR_RX_OUT_RC

=PP5V_S3_IR

CYPRESS ’ENCORE II’ USB CONTROLLER

P/N 338S0375

7C3

37A8

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

IN

OUT

P13 P14 P15 P16 P66

P10 P11 P12

P17

P20 P21 P22 P23 P24 P25 P26 P27

P30 P31 P32 P33 P34

P36 P37

P40 P41 P42 P43 P44 P45 P46 P47

P50 P51 P52

P60 P61 P62 P63 P64 P65

P67

P70 P71 P72 P73 P74 P75 P76 P77

P80 P81

P84 P85 P86

P90 P91 P92 P93 P94 P95 P96 P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0 PA1 PA2 PA3

PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

PE0 PE1 PE2 PE3 PE4 PF0

PF1 PF2 PF3 PF4 PF5 PF6 PF7

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

PH0 PH1 PH2 PH3 PH4 PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

BI

IN

OUT

BI

IN

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

(See below)

(OC) (OC)

pins designed as outputs can be left floating,

(OC)

(DEBUG_SW_2)

(DEBUG_SW_1)

(OC)

(OC) (OC)

(OC)

SMC_PB3:

SMC_IG_THROTTLE_L for MG systems. Otherwise, TP/NC okay (was ISENSE_CAL_EN)

those designated as inputs require pull-ups.

NOTE: Unused pins have "SMC_Pxx" names. Unused

(OC)

NOTE: P94 and P95 are shorted, P95 could be spare.

22UF

805

CERM

20%

6.3V

C4902

1

2

42D3 18C3

42D3 41D6

41C7 48C3 41C2 41A3

10%

402

CERM-X5R

6.3V 2

PLACEMENT_NOTE=PLACE C4907 CLOSE TO U4900 PIN E1

1

C4907

0.47UF

CERM

2

402

10V

0.1UF

20%

1

C4903

1

0.1UF

20%

PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PINS M12

CERM

10V

C4920

402

2

PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PINS M12

1/16W MF-LF

402

R4999

5%

4.7

12

CERM

10V

402

0.1UF

20%

C4904

1

2

SM

XW4900

12

20C7

62C7

CERM

10V

402

0.1UF

20%

C4905

1

2

20B7

66B1

66A4 24B8

41D5

10V

402

0.1UF

CERM

20%

1

2

C4906

45B1

44D6

41B2

41D5

45B1

44B4

45A4

41B2

41D5 58D2 41B2

41C2 42C5 40C5 38A8

42C3 41B2 40C5 38A8

66D8 60C5

6C3

43B5

402

1/16W

5%

MF-LF

10K

R4909

1

2

42C3

42D5

402

1/16W

5%

10K

MF-LF

R4901

1

2

402

10K

MF-LF

5% 1/16W

R4902

1

2

402

1/16W

5%

MF-LF

0

R4903

1

2

NO STUFF

402

1/16W

5%

10K

1

2

MF-LF

R4998

38A6

58D5

20C7

37C7

6B7

41B2

20C7

41C6

47B5

41D5

41B2

47C5

50B4

41D5

50B4

41D5

41C5

41D5

42D3 41B2

41B2

42D3 41B2

42D5 41B2

58C1 48A5 41C2

43C6

43D3

43C3

41C2

41C5

42C3 41B2 40B8 38A8

42C5 41C2 40B8 38A8

41C6

41B2

42D3 18B7

27A5 26A5 20B3 20A4

24B3

42C5

20C7

42D5 18B7

41D5

50B7

41B2 35B5 32B7 20C7

58C4

6A7

41D5

41A8

41C4

41D5

J12 K13 J10

H2

B13 D11

L10

N12

C13 C12 J11

B12 A13 A12

D10

D13 E11 D12 F11 E13 E12 F13 E10

A9 D9 C8 B7 A8

D7 D6

D4 A5 B4 A1 C2 B2 C1 C3

G2 F3 E4

L13 K12 K11

H12

N10 M11

N11

M13 N13 L12

A7 B6

A6 B5 C6

J4 G3

G1 H4 G4 F4 F1

D8

D5

C7

LGA-HF

OMIT

H8S2117

U4900

L1

N2

N3 N1 M3 M2

K3 L2

B8 C9

B9 A10 C10 B10 C11 A11

G11 G13 F12 H13 G10 G12 H11 J13

M10

N9 K10

L8

M9

N8

K9

L7

K1 J3 K2 J1 K4 K5

N5 M6 L5 M5 N4 L4 M4

M8 N7 K8 K7 K6 N6 M7 L6

E2 F2 J2 A4 B3 C4

LGA-HF

H8S2117

OMIT

M12

OMIT

H8S2117

D3

F10

E3

C5

B11

L3

D2

E1

H10

M1

E5

H1

D1

H3

L9

A2

A3

LGA-HF

U4900

L11

B1

76C3 42D5 18B3

76C3 42D3 18B3

76C3 42D5 18C3

24D1

76C3 24B1

49A6

43D6

20C3 70D8 66D5 35A5 32B7

6C3

66C8 41A2 20C3

41A2

76A3 24B1

43D6

43B5

41D1

SYNC_DATE=06/26/2008

SYNC_MASTER=T18_MLB

051-7898

4.7.0

8140

SMC

PP3V3_S5_AVREF_SMC

PP3V3_S5_SMC_AVCC

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=3.3V

=PP3V3_S5_SMC

SMC_RESET_L

GND_SMC_AVSS

SMC_TCK

MEM_EVENT_L

USB_DEBUGPRT_EN_L

PM_SYSRST_L

SMC_PA0

SMB_0_S0_CLK

SMC_SYS_KBDLED

SMC_TRST_L

SMC_KBC_MDE

SMC_VCL

SMC_NMI

SMB_0_S0_DATA

PM_SLP_S5_L

PM_SLP_S3_L

SMC_BS_ALRT_L

SMC_BC_ACOK

SMC_ONOFF_L

SMC_RX_L

SMC_BATT_ISENSE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_CPU_VSENSE

SMC_CPU_ISENSE

SMC_RX_L

SMC_TX_L

SMC_GFX_THROTTLE_L

SMS_ONOFF_L

SMB_MGMT_DATA

SMC_P41

LPC_SERIRQ

LPC_FRAME_L

LPC_AD<2>

ALL_SYS_PWRGD

ALS_GAIN

SMC_PH2

SMC_PROCHOT

SMB_B_S0_CLK

SMB_B_S0_DATA

SMB_A_S3_CLK

SMB_A_S3_DATA

SMB_BSA_CLK

SMB_BSA_DATA

=SMC_SMS_INT

SMC_MCP_SAFE_MODE

SMC_LID

SMC_SYS_LED

SMC_TMS

ALS_RIGHT

ALS_LEFT

SMC_NB_DDR_ISENSE

SMC_NB_CORE_ISENSE

SMC_ANALOG_ID

SMS_Z_AXIS

SMS_Y_AXIS

SMS_X_AXIS

SMC_FAN_3_TACH

SMC_FAN_2_TACH

SMC_FAN_1_TACH

SMC_FAN_0_TACH

SMC_FAN_3_CTL

SMC_FAN_2_CTL

SMC_FAN_1_CTL

SMC_FAN_0_CTL

SMC_GFX_OVERTEMP_L

SMC_EXCARD_OC_L

SMC_EXCARD_CP

SMC_PB3

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

PM_BATLOW_L

SYS_ONEWIRE

SMC_PA1

SMC_PA5

SMC_XTAL SMC_EXTAL

SMC_MD1

PM_CLK32K_SUSCLK

SMC_WAKE_SCI_L

SMC_RSTGATE_L

SMC_EXCARD_PWR_EN

PM_RSMRST_L

SMC_TDO

SMC_TDI

SMC_CASE_OPEN

LPC_AD<3>

LPC_CLK33M_SMC

SMC_LRESET_L

LPC_AD<1>

LPC_AD<0>

SMC_P26

SMC_P24

ESTARLDO_EN

PM_PWRBTN_L

IMVP_VR_ON

PM_SLP_S4_L

SMC_GPU_VSENSE

SMC_THRMTRIP

SMC_ADAPTER_EN

SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L

RSMRST_PWRGD

SMC_PM_G2_EN

SMC_GPU_ISENSE

SMC_NB_MISC_ISENSE

LPC_PWRDWN_L SMC_TX_L

PM_CLKRUN_L

SMB_MGMT_CLK

6C2

41C6

41D8 41C7 41C3 41C1

7D1

45D7 45C5 45B5 45B2 45A4 45A1 44D6 44C6 44B5 41B6

41C2

41D5

41C2

41C5

41C2

41A2

41A6

41D5

D

SG

IN

OUT

IN

OUT

IN

D

SG

OUT

GND

OUT

IN

02

D

SG

OUT

CD

GND

NC

OUT

IN

OUT

G

D

S

BI

IN

D

SG

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

SMC AVREF Supply

SMC Reset "Button" / Brownout Detect

NC

SMC Crystal Circuit

PLACE R5016 ON TOP SIDE

PLACE R5015,R5001 ON BOTTOM SIDE

Debug Power "Button"

RADAR 5925345

TO SMC

SMC FSB to 3.3V Level Shifting

TO CPU

MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE

System (Sleep) LED Circuit

SSM6N15FEAPE

Q5059

SOT563

5

3

4

2

R5095

1/16W MF-LF

0

1

402

5%

21

R5070

10K

1/16W5%MF-LF

402

21

R5071

MF-LF

5%

1/16W

402

100K

21

R5072

5%

MF-LF1/16W

402

10K

21

10K

402

1/16W5%MF-LF

R5073

21

402

1/16W MF-LF

5%

100K

R5074

100K

R5076

MF-LF

5%

1/16W

12

402

1/16W MF-LF

2

R5077

402

10K

5%

1

2

R5078

402

MF-LF

5%

10K

1

1/16W

10K

1/16W MF-LF

402

12

R5079

5%

R5080

10K

5%

402

MF-LF1/16W

12

21

R5085

10K

5%

1/16W MF-LF

402

21

R5086

10K

1/16W MF-LF

402

5%

21

R5088

402

10K

1/16W5%MF-LF

21

R5090

1/16W MF-LF

402

100K

5%

40A5

9C6

13B7 73B3

SILK_PART=PWR_BTN

603

5%

MF-LF

0

1/10W

2

R5015

1

NOSTUFF

21

R5091

402

MF-LF

5%

1/16W

100K

21

R5092

402

1/16W5%MF-LF

100K

40B8 19C2

40B5

21

5%

10K

402

MF-LF1/16W

R5089

1

2

5X3.2-SM

20.00MHZ

Y5010

CRITICAL

C5011

15pF

21

CERM

5%

50V

402

21

402

50V

15pF

5%

C5010

CERM

21

R5087

MF-LF

402

1/16W

5%

470K

R5016

SILK_PART=PWR_BTN

2

1

1/10W

0

MF-LF

5%

603

NOSTUFF

40B5

Q5032

SSM6N15FEAPE

SOT563

1

2

6

1.47K

402

2

1

MF-LF

1/16W

1%

R5032

523

402

1

1/16W MF-LF

1%

2

R5031

20

1/16W MF-LF

R5030

1%

402

2

1

C5020

1

2

6.3V

402

10%

0.47UF

CERM-X5R

37A8

CRITICAL

Q5030

2SA2154MFV-YAE

SOD

2

3

1

CRITICAL

VR5020

SOT23-3

REF3333

21

3

C5025

1

2

603

20%

10uF

X5R

6.3V

1

2

16V

10%

402

0.01UF

CERM

C5026

1/10W

5%

0

MF-LF 603

SILK_PART=SMC_RST

2

1

R5001

NOSTUFF

1

2

3

5

4

SOT553-5

SN74LVC1G02

U5001

1

0.01UF

402

CERM

16V

2

C5001

10%

10V

20%

CERM

402

0.1uF

2

1

C5000

3

Q5032

SOT563

SSM6N15FEAPE

4

5

1/16W

R5000

1

2

5%

MF-LF

1K

402

40C3 42D3

1

402

MF-LF1/16W

5%

R5051

10K

2

21

402

MF-LF1/16W

R5052

10K

5%

10K

5%

12

R5050

402

MF-LF1/16W

10K

21

402

MF-LF1/16W

5%

R5053

21

MF-LF

402

1/16W

5%

10K

R5055

10K

5%

402

MF-LF1/16W

12

R5054

SOT23-5-HF

2

4

5

3

1

CRITICAL

U5000

NCP303LSN

40B5

MF-LF

R5011

0

1/16W

5%

12

402

R5010

402

MF-LF

1/16W

5%

10K

2

1

40D5

MF-LF

10K

402

5% 1/16W

R5060

1

2

DMB53D0UV

SOT-563

Q5060

6

2

1

402

100K

5% 1/16W MF-LF

R5061

1

2

DMB53D0UV

SOT-563

Q5060

5

3

4

MF-LF

402

3.3K

5%

1/16W

R5062

12

9C5

13B6 62C8 73C3

40A5

SSM6N15FEAPE

SOT563

Q5059

6

2

1

40C5 41C2 41C7 48C3

ALL ISL60002-33, INTERSIL

353S1381 353S1912

SYNC_DATE=05/28/2008

SYNC_MASTER=YUAN.MA

4.7.0

SMC Support

051-7898

41 81

SMC_PROCHOT_3_3_L

=PP3V3_S5_SMC

GND_SMC_AVSS

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

=PPVIN_S5_SMCVREF

=PP3V3_S5_SMC

SMS_INT_L

MAKE_BASE=TRUE

=PP3V3_S5_SMC

SMC_PB3

SMC_PROCHOT

PM_THRMTRIP_L

CPU_PROCHOT_L

CPU_PROCHOT_L_R

CPU_PROCHOT_BUF

=PP3V3_S0_SMC

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

NC_ESTARLDO_EN

MAKE_BASE=TRUE

SMC_NB_CORE_ISENSE

SMC_EXCARD_OC_L

=PP3V3_S5_SMC

MCP_SPKR

SMC_P24

SMC_FAN_3_CTL

MAKE_BASE=TRUE

NC_SMC_PB3

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

=CHGR_ACOK

ALS_RIGHT

SMC_ANALOG_ID

MAKE_BASE=TRUE

SMC_CPU_FSB_ISENSE

SMC_PA5

=PP5V_S3_SYSLED

MAKE_BASE=TRUE

NC_SMC_ANALOG_ID

NC_ALS_GAIN

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL

SMC_BC_ACOK

SMC_NB_MISC_ISENSE

SMC_GPU_ISENSE

MAKE_BASE=TRUE

TP_SMC_EXCARD_PWR_EN

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

SMC_MCP_VSENSE

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

SMC_THRMTRIP

NC_ALS_RIGHT

MAKE_BASE=TRUE

SMC_EXCARD_PWR_EN

SMC_RSTGATE_L

ALS_GAIN

ESTARLDO_EN

SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

SMC_BC_ACOK

SMC_P26

SMC_P41

SMC_GPU_VSENSE

SMC_NB_DDR_ISENSE

ALS_LEFT

SMC_FAN_2_CTL

SMC_FAN_1_CTL

SMC_TPAD_RST

PM_SLP_S5_L

PM_SLP_S4_L

SMC_EXTAL

SMC_ONOFF_L

SMC_TPAD_RST_L

SMC_EXCARD_CP

=PP3V3_S0_SMC

SMC_CASE_OPEN

SMC_XTAL

SMC_SYS_LED

SMC_MANUAL_RST_L

SMC_RESET_L

EXCARD_OC_L

=SMC_SMS_INT

SMC_MCP_SAFE_MODE

SMC_FAN_3_TACH

SMC_PA0

SMC_TDI

SMC_TCK

SMC_PH2

SMC_PA1

SMC_TDO

SMC_ONOFF_L

SMC_TMS

SMC_RX_L

SMC_LID

SMC_TX_L

SMC_GFX_OVERTEMP_L

SMC_FAN_2_TACH

SMC_FAN_1_TACH

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

SMC_ADAPTER_EN

SMC_BS_ALRT_L

SYS_LED_ILIM

SYS_LED_L

SYS_LED_ANODE

SYS_LED_L_VDIV

SMC_ONOFF_L

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm

7D1

40D4 41C1 41C3 41C7

40C2 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7

7D1 7D1

40D4 41C3 41C7 41D8

7D1

40D4 41C1 41C3 41D8

40B8

7C5

41A1

40A8

7D1

40D4 41C1 41C7

41D8

20C3

40C8

40A8

20A4 20B3

59C5

40A8

45B5

40B8

7C3

40C5 41D5 58D2

40C5

45A5

44D6

45C5

40D8

40A5

40C8

40C5 41B2 58D2

40C8

40C5

40A8

40C5

6C3

20C3 40C5 66C8

40C3

48B1

40B8

7C5

41D3

40B5

40C3

40A8

40B8

40B5 42D3

40A5

40B8

40B5 42D5

40C5 41A3 41C7 48C3

40B5 42D5

38A8 40B8 40C5 42C3

40B5 48A5 58C1

38A8 40B8 40C5 42C5

40B8

40A8

45D7

20C7 32B7 35B5 40D5

40C5

40C5 41A3 41C2 48C3

6C2

40D4

IN

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

BI

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Alternate SPI ROM Support

LPC+SPI Connector

SPI MUX BYPASS

516S0573

Pull-up on debug card

SEL LOW OUTPUTS TO M (FRANKCARD ROM)

SEL HIGH OUTPUTS TO D (ON BOARD ROM)

42B5

18B7 40C8

18C3 40C5

40B5 41B2

40C3 41D6

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

55909-0374

CRITICAL

LPCPLUS

M-ST-SM

18B3 40C8 76C3

42C5 76A3

42B5 76A3

18C3 40C8 76C3

18B7 40C5

40B5 41B2

40C1

38A8 40B8 40C5 41B2

17B7

40C1

38A8 40B8 40C5 41C2

42D5 76A3

42D3

42A8 51C3

51C6

24B1 76C3

1

5%

MF-LF

1/16W

20K

402

R5144

2

42D3 76A3

42D5 76A3

42A8 51C6

42A8 51C3

1

2

CERM

20% 10V

402

0.1UF

C5114

LPCPLUS

U5110

1

TQFN

CRITICAL

6

7

3

4

5

8

10

9

2

PI3USB102ZLE

18B3 40C8 76C3

1

2

402

CERM

20%

0.1UF

10V

C5124

LPCPLUS

10

U5120

6

7

3

4

5

8

9

2

1

PI3USB102ZLE

TQFN

CRITICAL

R5190

1

2

MF-LF

5%

1/16W

10K

402

20B3 76A3

20B3 42A5 76A3

20B3 42C7 76A3

18B3 40C8 76C3

20B3 42C8 76A3

20B3 42B7 76A3

LPCPLUS_NOT

R5146

12

5%

MF-LF

1/16W

0

402

PLACEMENT_NOTE=PLACE NEXT TO U1400

R5157

12

LPCPLUS_NOT

402

0

MF-LF

5%

1/16W

R5156

12

LPCPLUS_NOT

402

1/16W

5%

MF-LF

0

R5158

12

LPCPLUS_NOT

402

1/16W

5%

MF-LF

0

20B3 42A5 76A3

10K

R5191

1

2

1/16W MF-LF

5%

402

42B7

20B3 42A5 76A3

42C5 51C6

42C5 51C3

42B5 51C3

20C7

100K

MF-LF

402

5%

1/16W

2

1

R5140

42C5 76A3

SYNC_MASTER=CHANGZHANG

SYNC_DATE=05/09/2008

051-7898

42 81

4.7.0

LPC+SPI Debug Connector

SPI_MOSI_MUX

SPI_MLB_CS_L

=SPI_CS1_R_L_USE_MLB

=PP3V3_S5_LPCPLUS

SPI_CS0_R_L

SPI_ALT_MISO

=PP3V3_S5_LPCPLUS

SPI_CLK_R

SPI_MOSI_R

SPI_ALT_CLK SPI_ALT_MOSI

SPI_ALT_CS_L

SPI_MISO_MUX

=PP3V3_S5_ROM

SMC_TCK

SMC_TDI

LPC_PWRDWN_L

LPC_SERIRQ

SPI_ALT_CS_L

SPI_ALT_CLK

SPIROM_USE_MLB

LPC_AD<3>

LPC_CLK33M_LPCPLUS LPC_AD<2>

SMC_RESET_L

=PP3V3_S5_LPCPLUS

SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L

SPI_ALT_MOSI

LPC_AD<0> LPC_AD<1>

SMC_TDO SMC_TRST_L

DEBUG_RESET_L

SMC_TMS

SMC_RX_L

SMC_NMI

LPCPLUS_GPIO

=PP5V_S0_LPCPLUS

SMC_TX_L

SMC_MD1

SPI_MISO

SPI_MOSI_R

SPI_CLK_R

SPI_MISO

SPI_CLK_MUX

SPI_MISO_MUX

SPI_MOSI_MUX

=PP3V3_S5_ROM

SPI_CLK_MUX

MAKE_BASE=TRUE

SPIROM_USE_MLB

7D1

42C7 42D5

7D1

42C8 42D5

7A3

42C7 51C6

7D1

42C7 42C8

7D5

7A3

42B5 51C6

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(WRITE: ?? READ: 0X??)

LED BACKLIGHT

(Write: 0x98 Read: 0x99)

Vref DACs

SMC "A" SMBus Connections

MCP79 SMBUS "0" CONNECTIONS

U1400

TRACKPAD

(See Table)

SO-DIMM "B"

J3200

(Write: 0xA2 Read: 0xA3)

Battery Temp - (Write: 0x90 Read: 0x91)

Battery Manager - (Write: 0x16 Read: 0x17)

SMC "Battery A" SMBus Connections

SMC

(Write: 0x52 Read: 0x53)

(Write: 0x90 Read: 0x91)

J5800

ALS

J3401

(Write: 0x98 Read: 0x99)

NOTE: SMC RMT bus remains powered and may be active in S3 state

(MASTER)

U4900

SMC

(Write: 0x98 Read: 0x99)

MCP Temp

EMC1403-5: U5535

SMC "0" SMBus Connections

U4900

(MASTER)

BATTERY & BIL

(Write: 0x30 Read: 0x31)

Margin Control

The bus formerly known as "Battery B"

Battery Charger

(Write: 0x12 Read: 0x13)

J6950 & J6955

ISL6258A - U7000

U2900

SMC "Management" SMBus Connections

U4900

SMC

U2901

Battery LED Driver - (Write: 0x36 Read: 0x37)

Battery

U4900

SMC

(MASTER)

SMC

(MASTER)

J3100

(Write: 0xA0 Read: 0xA1)

SO-DIMM "A"

MCP79

(MASTER)

U6860

U9701

(WRITE: 0X72 READ: 0X73)

Mikey

MCP79 SMBUS "1" CONNECTIONS

U1400

MCP79

(MASTER?)

CPU Temp

EMC1403-5: U5515

SMC "B" SMBus Connections

1K

R5201

MF-LF

5% 1/16W

402

1

2

1K

5%

402

R5200

1

2

1/16W MF-LF

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

=I2C_ALS_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

=PP3V3_S0_SMBUS_MCP_1

=I2C_BKL_1_SDA

=I2C_BKL_1_SCL

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

=I2C_SODIMMB_SDA

=I2C_SODIMMB_SCL

=I2C_SODIMMA_SDA

=I2C_SODIMMA_SCL

SMB_MGMT_DATA

SMB_MGMT_CLK

=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

=I2C_VREFDACS_SDA

=I2C_VREFDACS_SCL

SMB_BSA_DATA

SMB_BSA_CLK

=SMBUS_CHGR_SDA

=SMBUS_CHGR_SCL

=SMBUS_BATT_SDA

SMB_B_S0_DATA

SMB_B_S0_CLK

SMB_0_S0_DATA

SMB_0_S0_CLK

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

=I2C_MCPTHMSNS_SCL

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

=I2C_MCPTHMSNS_SDA

SMB_A_S3_CLK

=I2C_TPAD_SDA

=I2C_TPAD_SCL

=I2C_ALS_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA =I2C_CPUTHMSNS_SDA

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

=I2C_CPUTHMSNS_SCL

SMBUS_MCP_1_DATA

MAKE_BASE=TRUE

SMBUS_MCP_1_CLK

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_MCP_0

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_B_S0

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

=PP3V42_G3H_SMBUS_SMC_BSA

=SMBUS_BATT_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SYNC_DATE=04/21/2008

051-7898

8143

4.7.0

K24 SMBUS CONNECTIONS

4.7K

5% 1/16W

402

MF-LF

R5291

1

2

MF-LF

5%

402

4.7K

1/16W

R5290

1

2

R5230

MF-LF

2.0K

5%

402

2

1

1/16W

2.0K

5%

2

1

1/16W MF-LF 402

R5231

MF-LF

402

2

R5250

5%

1/16W

4.7K

1

R5251

5%

2

1

1/16W

402

MF-LF

4.7K

1

2

402

1/16W

R5270

MF-LF

1

2

1/16W MF-LF 402

5%

1K

R5271

402

1/16W MF-LF

5%

4.7K

R5260

1

2

MF-LF

1/16W

5%

402

4.7K

1

2

R5261R5281

MF-LF

5% 1/16W

402

2

1

2.0K

R5280

1/16W MF-LF

5%

402

2

1

2.0K

=PP3V3_S3_SMBUS_SMC_A_S3

SMB_A_S3_DATA

1K

5%

SYNC_MASTER=BEN

29B6

79D3

6D5 6C5

7C5

71B7

57D3

27A5

26A5

40C8

40C5

25A8

25C7

40B5

59C6

58C3 58A6 40A5

40A5

40C5

40B8 46B3

79D3

46B3 40A5

40A5

49C1

29B6

79D3

46D3

79D3

46D3

76B3 20C3

76B3

20C3 12B6

76B3

20C3 12B6

7C5

79D3

7D3

7C5

79D3

6D5 6C5

7D3

79D3

6A7

7D1

58C3 58A6

79D3

6A7

79D3

OUT

D

N-CHANNEL

P-CHANNEL

G

S

D

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MCP Voltage Sense / Filter

CPU Voltage Sense / Filter

divider when high.

PBUS VOLTAGE SENSE ENABLE & FILTER

Place RC close to SMC

RTHEVENIN = 4573 OHMS

Place RC close to SMC

Enables PBUS VSense

41D4

402

0.22UF

C5359

6.3V X5R

20%

2

1

1%

1

4.53K

1/16W MF-LF

R5359

402

2

4

5

1

2

6

3

SOT-963

NTUD3127CXXG

Q5315

66C1

R5316

1

2

1%

1/16W

402

100K

MF-LF

100K

1

2

402

1%

1/16W

R5315

40C5

402

2

1

6.3V

20%

X5R

C5385

0.22UF

1%

402

MF-LF

2

1

R5385

1/16W

27.4K

1% 1/16W MF-LF

402

5.49K

1

R5386

2

XW5359

PLACEMENT_NOTE=Place near U1400 center

SM

21

40C5

4.53K

1/16W

1%

402

21

R5309

MF-LF

402

0.22UF

20%

6.3V

2

1

C5309

X5R

2

PLACEMENT_NOTE=Place near U1000 center

XW5309

SM

1

VOLTAGE SENSING

SYNC_MASTER=YUNWU

SYNC_DATE=02/04/2008

4.7.0

44 81

051-7898

VOLTAGE=18.5V

PPBUS_G3HRS5_VSENSE

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.20 mm

=PBUSVSENS_EN

PBUSVSENS_EN_L

=PPVCORE_S0_MCP_VSENSE

GND_SMC_AVSS

SMC_PBUS_VSENSE

GND_SMC_AVSS

CPUVSENSE_IN

SMC_CPU_VSENSE

GND_SMC_AVSS

=PPVCORE_S0_CPU_VSENSE

PBUSVSENS_EN_L_DIV

=PPBUS_G3HRS5

MCPVSENSE_IN

SMC_MCP_VSENSE

7C6

40C2 41B6 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7

40C2 41B6 44B5 44D6 45A1 45A4 45B2 45B5 45C5 45D7

40C2 41B6 44B5 44C6 45A1 45A4 45B2 45B5 45C5 45D7

7D7

7C1

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

IN

V+

REFIN+

IN-

OUT

GND

IN

OUT

IN

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BMON CURRENT SENSE

Gain: 50x

INA213 has gain of 50V/V

Place RC close to SMC

MCP MEM VDD Current Sense Filter

DC-IN (AMON) CURRENT SENSE

PLACE R5491 AND C5390 CLOSE TO SMC

Place RC close to SMC

REGULATOR SIDE

LOAD SIDE

NOTE: MONITORING CURRENT FROM

BATTERY TO PBUS (BATTERY DISCHARGE)

CPU VCore Load Side Current Sense / Filter

ACROSS R7008

Place RC close to SMC

MCP VCore Current Sense Filter

PLACE U5403 AND C5418 NEAR R7008

MCP MEM VDD Current Sense

For production, stuff R5330 and unstuff U5313

For engineering, stuff U5313 and unstuff R5330

PLACE U5413, R5423, R5431, C5459 NEAR SMC (U4900)

CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE

41D4

X5R

2

6.3V

20%

0.22UF

C5472

1

402

67D1

41D4

C5435

1

X5R

0.22UF

402

2

6.3V

20%

1

2

CERM

0.1uF

402

10V

20%

C5417

4

2

5

3

1

6

SC70

INA213

U5402

7C2

0.01

0.5% 1W

CRITICAL

0612-1

12 34

MF

R5492

7C1

41D4

1

C5436

2

X5R 402

0.22UF

20%

6.3V

40C5

4.53K

1

1/16W

402

2

1%

R5418

MF-LF

21

4.53K

1%

402

R5416

1/16W MF-LF

402

1%

MF-LF

21

R5417

4.53K

1/16W

C5418

0.1uF

20% 10V

402

2

1

CERM

BMON_ENG

6

3

1

U5403

SC70

2

4

5

INA213

BMON_ENG

59C5

BMON_PROD

0

1/16W MF-LF

5%

402

R5431

BMON_ENG

5%

100K

R5423

402

MF-LF

2

1

1/16W

BMON_ENG

0.1uF

C5459

1

CERM

20% 10V

402

2

MF-LF

1%

1/16W

402

21

R5401

4.53K

X5R

20%

6.3V

402

1

2

0.22UF

C5490

40C5

X5R

0.22UF

6.3V

2

1

402

20%

C5470

62C7

R5480

17.4K

MF-LF

402

2

1

1%

1/16W

402

1/16W

6.19K

MF-LF

21

1%

R5471

40C5

4.53K

MF-LF

1/16W

R5481

402

21

1%

2

1

402

0.22UF

20%

6.3V X5R

C5487

BMON_ENG

NC7SB3157P6XG

2

3

1

4

6

5

SC70

U5413

41D4

59B3 80D3

67D1

CRITICAL

SOD

1

2

3

2SA2154MFV-YAE

Q5401

2

402

1

5%

0

R5410

MF-LF

1/16W

12

0

5%

R5411

MF-LF

402

1/16W

R5412

1%

MF-LF

118

1

2

402

10% 16V X5R 402

0.1UF

C5434

20%

402

0.1uF

CERM

10V

C5400

OPA348

U5400

4

1

3

5

2

SC70-5

SYNC_MASTER=YUNWU

051-7898

81

4.7.0

SYNC_DATE=12/17/2008

Current Sensing

45

P1V5_S0_SENSE_C

CPUVTT_IOUT

=PP3V42_G3H_BMON_ISNS

=PP3V3_S0_MCPDDRISNS

SMC_MCP_CORE_ISENSE

=PPCPUVCORE_VTT_ISNS

=PPCPUVCORE_VTT_ISNS_R

GND_SMC_AVSS

P1V5_S0_SENSE_B

GND_SMC_AVSS

BMON_AMUX_OUT

CHGR_CSO_R_P

CHGR_CSO_R_N

GND_SMC_AVSS

SMC_CPU_FSB_ISENSE

GND_SMC_AVSS

SMC_BATT_ISENSE

CHGR_BMON

GND_SMC_AVSS

SMC_BMON_MUX_SEL

IMVP6_IMON

SMC_CPU_ISENSE

CHGR_AMON

SMC_MCP_DDR_ISENSE

P1V5_S0_SENSE_E

=PP3V3_S0_CPUVTTISNS

ISNS_CPUVTT_N

SMC_DCIN_ISENSE

MCPCORES0_IMON

P1V5_S0_SENSE_AMP

P1V5_S0_SENSE

P1V5_S0_KELVIN

BMON_INA_OUT

ISNS_CPUVTT_P

7D1

7B5

40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5

40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B5 45C5 45D7

40C2 41B6 44B5 44C6 44D6 45A4 45B2 45B5 45C5 45D7

40C2 41B6 44B5 44C6 44D6 45A1 45B2 45B5 45C5 45D7

40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45D7

40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45C5 45D7

7C5

80D3

63D8

80D3

BI

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DETECT HEAT-PIPE TEMPERATURE

REPLACED 518S0521 WITH 518S0519

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

DETECT MCP DIE TEMPERATURE

MCP T-Diode Thermal Sensor

PLACEMENT NOTE: PLACE U5535 NEAR MCP

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE

CPU T-Diode Thermal Sensor

PLACEMENT NOTE: PLACE U5515 NEAR CPU

DETECT CPU DIE TEMPERATURE

DETECT FIN-STACK TEMPERATURE

2

1

C5540

CERM

402

0.0022uF

10% 50V

NOSTUFF

SIGNAL_MODOL=EMPTY

43C1

402

10K

MF-LF

5% 1/16W

R5517

1221

R5516

10K

MF-LF

1/16W

402

1%

2

1

R5537

402

1/16W

5%

MF-LF

10K

2

1

R5536

402

10K

1/16W MF-LF

1%

43D3

2

1

C5535

0.1uF

20%

402

CERM

10V

402

CERM

50V

2

C5521

10%

1

SIGNAL_MODOL=EMPTY

0.0022uF

2

1

C5522

SIGNAL_MODOL=EMPTY

CERM

10% 50V

0.0022uF

402

9C6

80D3

9C6

80D3

20C3 80D3

2

1

4

3

M-RT-SM

NOSTUFF

78171-0002

J5590

CRITICAL

SOT732-3

BC846BMXXH

Q5501

1

3

2

EMC1413

U5515

11

5

4

1

9

10

6

3

27

8

DFN

CRITICAL

DFN

8

72

3

6

10

9

1

11

U5535

EMC1413

4

5

0.1uF

20%

402

CERM

10V

2

C5515

1

402

MF-LF

5%

1/16W

47

12

R5515

CERM

50V

10%

0.0022uF

402

C5520

1

2

SIGNAL_MODOL=EMPTY

21

R5535

47

1/16W

402

MF-LF

5%

051-7898

4.7.0

8146

Thermal Sensors

SYNC_MASTER=YUNWU

SYNC_DATE=03/20/2008

=PP3V3_S0_CPUTHMSNS

CPUTHMSNS_THERM_L

CPU_THERMD_P

CPU_THERMD_N

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

CPUTHMSNS_ALERT_L

=PP3V3_S0_MCPTHMSNS

PP3V3_S0_MCPTHMSNS_R

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

MCP_THMDIODE_P

MCPTHMSNS_ALERT_L

MCPTHMSNS_THERM_L

=I2C_MCPTHMSNS_SDA

=I2C_MCPTHMSNS_SCL

MCP_THMDIODE_N

MCPTHMSNS_D2_N

MCPTHMSNS_D2_P

7C5

80D3

7C5

6C7

80D3

6C7

80D3

D

GS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

5V DC TACH

MOTOR CONTROL GND

518S0521

NC

R5665

12

47K

1/16W

5%

MF-LF

402

R5660

1

2

5%

402

MF-LF

1/16W

47K

R5661

1

2

5% 1/16W MF-LF

402

100K

SSM3K15FV

Q5660

SOD-VESM-HF

3

2

1

5

6

1 2 3 4

CRITICAL

78171-0004

M-RT-SM

J5601

051-7898

8147

4.7.0

Fan

SYNC_MASTER=CHANGZHANG

SYNC_DATE=01/18/2008

SMC_FAN_0_TACH

FAN_RT_TACH

SMC_FAN_0_CTL

=PP3V3_S0_FAN_RT

=PP5V_S0_FAN_RT

FAN_RT_PWM

40A8

6D7

40B8

7C5

7D5

6D7

D

GS

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSSD+D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER2)

P0_1

Y

C

B

A

IN

OUT

IN

Y

B

A

Y

B

A

Y

B

A

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

PSOC USB CONTROLLER

APN 337S2983

KEYBOARD CONNECTOR

SMC_MANUAL_RESET LOGIC

NC

ISSP SCLK/I2C SCL

ISSP SDATA/I2C SDA

60MA MAX

VDD

8MA (TYP)

0.2 OHM

0.021 V

0.0188 V

4.7 OHM

4MA (MAX)

96E-6 W

16.32E-6 W

0.012 V

36E-3 W

0.72E-3 W

60MA MAX

14MA (MAX)

3V3 LDO

0.0255 V

0.6 V

0.204 V

SPI HOST TO Z2

TMP102

PLACE C5704, C5705 & C5706

VDD PIN 49

TPAD BUTTONS DISABLE

ISOLATION CIRCUIT

PLACE THESE COMPONENTS CLOSE TO J5800

U5701 CHIP DECOUPLING

THE TPAD BUTTONS WILL BE DISABLE

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V

LID CLOSE => SMC_LID_LC < 0.50V

APN 518S0637

TO MLB CONNECTOR

USB INTERFACES TO MLB

75.2E-6 W

294E-6 W

0.255E-6 W

0.012 V

POWERV_SNS

1.5 OHM

10 OHM

2.55 KOHM

R_SNS

10UA

80UA

CURRENT

VIN

VOUT

V+

PIN NAME

IC

PSOC

18V BOOSTER

PLACE C5701, C5702 & C5703 CLOSE TO U5701 CLOSE TO U5701

VDD

APN 311S0406

KEYBOARD SCANNER

TRACKPAD PICK BUTTONS

VDD PIN 22

Alternate Parts

2

1

SSM3K15FV

3

SOD-VESM-HF

Q5701

X7R-CERM

1

C5758

0.1UF

10%

402

2

16V

2

1

402

MF-LF

33K

5%

R5771

1/16W

33K

R5770

1

2

402

MF-LF

5%

1/16W

R5769

1

2

402

MF-LF

1/16W

5%

33K

2

1

C5706

4.7UF

20%

6.3V X5R 603

2

402

0.1UF

X7R-CERM

16V

10%

C5705

1

2

5%

C5704

100PF

50V CERM 402

1

2

1

C5703

0.1UF

10%

402

X7R-CERM

16V

1

2

402

CERM

50V

5%

100PF

C5702

20%

2

1

4.7UF

X5R 603

6.3V

C5701

24

R5702

12

402

5%

1/16W MF-LF

U5701

5

8

9

10

11

CRITICAL

50

2

565553

3

7

4922

57

23

24

32

31

13 30

14 29

40

4

6

37

36

35

34

33

44

43

1

42

15281627172618

25

484746

45

21

20

MLF

54

19

12

52

51

39

CY8C24794

38

OMIT

41

24

1/16W

5%

2

MF-LF

R5701

1

402

6

3

1

2

5

4

SC70

SN74LVC1G10

U5703

CRITICAL

MF-LF

5%

R5704

1.5

1/16W

402

21

40B5 41C2 58C1

2

1

C5710

402

10V

0.1UF

20%

PLACEMENT_NOTE=NEAR J5713

CERM

402

MF-LF

1/16W

5%

1K

R5710

12

21

R5714

1%

MF-LF

402

1/16W

470

21

R5715

1%

402

10K

MF-LF

1/16W

7C3

48A6 48B5 48C5

J5713

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

18

17

16

15

14

13

12

11

10

1

CRITICAL

FF14-30A-R11B-B-3H

F-RT-SM

31

32

19

CRITICAL

TC7SZ08AFEAPE

1

U5726

5

4

SOT665

2

3

CRITICAL

TC7SZ08AFEAPE

U5727

SOT665

2

4

1

5

3

12

402

CERM

10V

20%

0.1UF

C5727

12

402

0.1UF

C5726

20%

CERM

10V

CRITICAL

SOT665

TC7SZ08AFEAPE

U5725

2

4

1

5

3

12

402

10V

C5725

20%

CERM

0.1UF

311S0406 311S0447

ALL NXP PART AS ALTERNATE

48 81

051-7898

SYNC_MASTER=YUAN.MA

SYNC_DATE=04/22/2008

4.7.0

WELLSPRING 1

WS_LEFT_SHIFT_KBD

=PP3V3_S3_TPAD

WS_CONTROL_KBD

Z2_CS_L

PSOC_MOSI PSOC_SCLK Z2_MISO

Z2_KEY_ACT_L

TP_P4_5 Z2_DEBUG3

TP_ISSP_SCLK_P1_1

PP3V3_S3_PSOC

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

USB_TPAD_N

=PP3V3_S3_TPAD

WS_LEFT_OPTION_KBD

=PP3V3_S3_TPAD

=PP3V42_G3H_TPAD

WS_CONTROL_KEY

WS_KBD_ONOFF_L

SMC_ONOFF_L

WS_KBD1

BUTTON_DISABLE Z2_HOST_INTN

WS_LEFT_OPTION_KBD

WS_KBD20

=PP3V42_G3H_TPAD

USB_TPAD_R_P

DIFFERENTIAL_PAIR=USB2_TPAD

SMC_TPAD_RST_L

WS_KBD18

WS_KBD15_C

WS_KBD16N

WS_KBD7

WS_KBD19

WS_KBD21

WS_KBD23

Z2_MOSI

WS_KBD13

TP_PSOC_P1_3

WS_KBD3

WS_KBD9

WS_KBD10

WS_KBD12

WS_KBD15_C

=PP3V3_S3_TPAD

WS_KBD5

USB_TPAD_P

WS_KBD22

TP_PSOC_SCL

PP3V3_S3_PSOC

TP_PSOC_SDA

Z2_SCLK

WS_KBD7

WS_CONTROL_KBD

WS_LEFT_OPTION_KBD

=PP3V42_G3H_TPAD

WS_LEFT_SHIFT_KBD

WS_KBD22

WS_KBD19 WS_KBD20 WS_KBD21

WS_KBD9 WS_KBD10 WS_KBD11

WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM

WS_KBD17

WS_KBD18

WS_KBD6

WS_KBD5

WS_KBD2

WS_KBD1

WS_KBD8

WS_KBD16N

WS_KBD17

BUTTON_DISABLE

SMC_LID

WS_KBD6

WS_CONTROL_KBD

PSOC_F_CS_L

=PP3V42_G3H_TPAD

WS_CONTROL_KEY

WS_LEFT_SHIFT_KEY

WS_KBD4

WS_KBD3

WS_KBD2

=PP3V3_S3_TPAD

PICKB_L

WS_KBD11

PP3V3_S3_PSOC

WS_KBD14

Z2_CLKIN

TP_ISSP_SDATA_P1_0

TP_P7_7

WS_KBD4

USB_TPAD_R_N

DIFFERENTIAL_PAIR=USB2_TPAD

WS_LEFT_OPTION_KEY

WS_LEFT_SHIFT_KBD

WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY

PSOC_MISO

Z2_RESET

WS_KBD23

WS_KBD8

WS_KBD12

WS_KBD13

6A5

48B5 48C2

7C3

48A6 48B5 48C5 48D2

6A5

48B5 48C2

6C5

49C3

6C5

49C1

6C5

49C1

6C5

49C3

6C5

49C1

6C5

49C3

48B6 48D7

19D3 76B3

7C3

48A6 48B5 48D2

6A5

48B3 48C2

7C3

48A6 48B5 48C5 48D2

7D1

48B5 48C2 48C3 48C5

48B4

6A5

40C5 41A3 41C2 41C7

6B5

48C6

48A5

6C5

49C3

6A5

48B5 48C2

7D1

48B5 48C2 48C5

7D1

48B5 48C2 48C3 48C5

76B3

41C7

48C6

6B5

48D2

6C5

49C3

6B5

48D2

6B5

48D2

6B5

48D2

6B5

48D2

6B5

48D2

48D3

7C3

48B5 48C5 48D2

6B5

48D2

19D3 76B3

48A8 48D7

6C5

49C3

6B5

48C6

6A5

48B3 48B5

6A5

48B3 48B5

7D1

48B5 48C3 48C5

6A5

48B3 48B5

6A5

48D7

6B5

48D7

6B5

48D7

6B5

48D7

6B5

48C6

6B5

48C6

6B5

48C6

6B5

48C6

6B5

48D6

6B5

48D7

6B5

48C6

6B5

48C6

6B5

48D2

6B5

48D2

6B5

48D2

48C3

6B5

48C2

48D8

6B5

48D2

6A5

48B3 48C2

6C5

49C1

7D1

48B5 48C2 48C3

48D8

6B5

48C6

6B5

48C6

6B5

48C6

6C5

49C1

6B5

48D2

48A8 48B6

6B5

48C2

6C5

49C3

6B5

48D2

76B3

48D8

6A5

48B3 48C2

48C4

48B4

6C5

49C1

6C5

49C1

6A5

48D7

6B5

48C6

6B5

48C6

6B5

48C6

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD

GND

VDD

VOUT

GND

CE

IN

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3V3 LDO FOR IPD

IPD FLEX CONNECTOR

APN 353S1401

KEYBOARD BACKLIGHT DRIVNG AND DETECTION

APN 353S1364

APN 152S0504

APN 371S0313

BOOSTER +18.5VDC FOR SENSORS

- RIPPLE TO MEET ERS

- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS

- R5812,R5813,C5818 MODIFIED

BOOSTER DESIGN CONSIDERATION:

To detect Keyboard backlight, SMC will

R5853 ALWAYS PRESENT

tristate SMC_SYS_KBDLED:

LOW = keyboard backlight present

HIGH= keyboard backlight not present

BOM OPTION: KBDLED_YES TURNED ON FOR BEST MLB CONFIG

- DROOP LINE REGULATION

- POWER CONSUMPTION

on keyboard backlight flex

KBD BACKLIGHT CONNECTOR

J5815 pin 1 is grounded

APN 518S0691

APN 516S0689

NC

21

CRITICAL

3

1

16

13

J5800

55560-0228

M-ST-SM

5

7

9

11

15

17

19

6

8

12

14

18

20

22

2

10

4

CRITICAL

D5802

SOD-323

B0520WSXG

603-1

10% 25V X5R

1UF

C5819

1

2

12

402

5%

0

R5806

MF-LF

1/16W

402

10%

X7R-CERM

16V

0.1UF

C5816

1

2

5%

21

1/16W

MF-LF

402

0

R5805

16V X5R 603

10%

1

2

C5817

2.2UF

8

53

41

9

2

7

QFN

TPS61045

U5805

CRITICAL

6

CRITICAL

VLF3010AT-SM-HF

L5801

3.3UH-870MA

100K

R5811

402

1

2

1/16W MF-LF

1%

603

2

1

C5853

2.2UF

10%

16V

X5R

3

2

4

1

VR5802

MM3243DRRE

MLF

CRITICAL

2

1

0.2

402-HF

MF

1/6W

R5836

1%

2

1

10%

16V

402

X7R-CERM

0.1UF

C5838

4.7UF

2

1

C5854

603

X5R

6.3V

20%

R5873

10

1/16W MF-LF

402

12

1%

40C8

KB_BL

1

2

402

4.7K

5%

1/16W

R5854

MF-LF

1

2

402

470K

MF-LF

1/16W

5%

R5853

DFN

3

5

4

7

2

6

1

KB_BL

CRITICAL

U5850

LT3491

1

5%

MF-LF

402

2

10K

R5852

1/16W

NO STUFF

C5850

KB_BL

2

1

1UF

10% 10V X5R

402-1

KB_BL

2

10

1%

1/16W

MF-LF

402

1

R5855

12

KB_BL

CRITICAL

1098AS-SM

10UH-0.58A-0.35OHM

L5850

KB_BL C5855

2

1

10% 35V

603

X5R

1UF

KB_BL

F-RT-SM

2

3

4

1

FF18-4A-R11AD-B-3H

CRITICAL

J5815

50V

5%

CERM

C5818

402

1

2

39PF

MF-LF

1/16W

R5812

1%

402

2

1

1M

71.5K

1/16W

MF-LF

1%

R5813

402

2

1

PLACEMENT_NOTE=NEAR J5800

2

1

C5800

CERM 402

10V

20%

0.1UF

SYNC_DATE=05/09/2008

4.7.0

051-7898

49 81

SYNC_MASTER=YUAN.MA

WELLSPRING 2

0.50MM

0.20MM

PP5V_S3_VR

=PP5V_S3_TPAD

SMC_KDBLED_PRESENT_L

=PP3V3_S0_TPAD

PP3V3_S3_LDO_R

SMC_KDBLED_PRESENT_L

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

KBDLED_CAP

Z2_RESET

PP18V5_S3

PSOC_MOSI

PSOC_SCLK

=I2C_TPAD_SCL

PSOC_F_CS_L

Z2_BOOST_EN

=PP5V_S0_KBDLED

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

KBDLED_ANODE

KBDLED_SW

MIN_LINE_WIDTH=0.3 MM

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

PP3V3_S3_LDO

PP18V5_S3_SW

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

MIN_NECK_WIDTH=0.20MM

PP5V_S3_BOOSTER

MIN_LINE_WIDTH=0.50MM

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

BOOST_SW

SMC_SYS_KBDLED

Z2_CS_L

PSOC_MISO

Z2_BOOST_EN

Z2_MOSI

Z2_KEY_ACT_L

PICKB_L

=I2C_TPAD_SDA

PP3V3_S3_LDO

0.50MM

0.20MM

PP18V5_S3

0.50MM

Z2_CLKIN

Z2_HOST_INTN

Z2_SCLK

Z2_MISO

Z2_DEBUG3

=PP5V_S3_TPAD

0.20MM

0.50MM

INPUT_SW

BOOST_FB

7C3

49D7

6A5

49A6

7C5

6A5

49A4

6C5

48C8

6C3 6C5

49C1

6C5

48C8

6C5

48C8

43D1

6C5

48C8

6C5

49C3

7D5

6A5

6C3 6C5

49C3

6C5

48C8

6C5

48C8

6C5

49C5

6C5

48C8

6C5

48C8

6C5

48D8

43D1

6C3 6C5

49B4

6C3 6C5

49D3

6C5

48C6

6C5

48D8

6C5

48C8

6C5

48C8

6C5

48C8

7C3

49B6

OUT

FS PD ST

RES RES

GND

NC

NC NC

NC

NC NC

VOUTX

VOUTY

VOUTZ

VDD

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC NC

Front of system

+X

+Y

+Z (up)

NC

NC NC NC

NC

in correct orientation

Circle indicates pin 1 location when placed

placed on board top-side:

Desired orientation when

R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC

Analog SMS

1

2

16V

0.01UF

10%

CERM 402

C5923

40A8

1

2

0.1UF

10% 16V X5R 402

C5922

X5R

4V

20%

1

2

603

10UF

C5926

CRITICAL

8

AP344ALH

LGA

10

12

13

11

16

6

3

9

7

4

2

5

1

14

15

U5920

CERM

2

10% 16V

402

1

0.01UF

C5925

402

16V

2

CERM

10%

0.01UF

1

C5924

40C8

MF-LF

2

1

5% 1/16W

10K

R5922

402

MF-LF

1/16W

2

5%

10K

R5921

1

4.7.0

50

051-7898

81

SMS

SYNC_MASTER=YUNWU

SYNC_DATE=06/26/2008

MAKE_BASE=TRUE

SMS_PWRDN

=PP3V3_S3_SMS

SMS_X_AXIS

SMS_Y_AXIS

SMS_Z_AXIS

SMS_SELFTEST

SMS_ONOFF_L

7C3

ININ

IN

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1

0

1

SPI_CLK

0

SPI_MOSI

1

0

1

0

42 MHz

1 MHz

25 MHz

Frequency

MCP79 SPI Frequency Select

31 MHz

42A8 42C5

402

MF-LF

1/16W

3.3K

5%

2

1

R6100

NO STUFF

402

10K

1/16W

5%

MF-LF

2

1

R6190

PLACEMENT_NOTE=PLACE CLOSE TO U6100

MF-LF

5%

1/16W

0

402

21

R6150

42A8 42C5

42B5

SOP

OMIT

CRITICAL

MX25L3205DM2I-12G

32MBIT

3

8

2

5

6

7

4

1

U6100

42A8 42B5

PLACEMENT_NOTE=PLACE CLOSE TO U6100

MF-LF

5%

1/16W

0

402

21

R6152

PLACEMENT_NOTE=PLACE CLOSE TO U6100

MF-LF

5%

1/16W

0

402

21

R6105

NO STUFF

402

MF-LF

5% 1/16W

10K

2

1

R6191

0.1UF

10V

CERM

402

20%

2

1

C6100

1/16W

5%

3.3K

MF-LF 402

2

1

R6101

51 81

4.7.0

051-7898

SPI ROM

SYNC_MASTER=CHANGZHANG

SYNC_DATE=05/02/2008

SPI_MISO_MUX

SPI_MOSI_MUX

SPI_CLK_MUX

SPI_MISO_R

SPI_CLK

SPI_HOLD_L

SPI_MOSI

SPI_MLB_CS_L

SPI_WP_L

=PP3V3_S5_ROM

with R6190, R6191, R5190 and R5191

Any of the 4 frequencies can be selected

25MHz is selected with R5190 and R5191

76A3

76A3 76A3

7A3

42B5 42C7

IN

OUT

IN

OUT

IN

OUT

IN

OUT

NR/FB

NC

IN

EN

GND

OUT

IN

OUT

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+ MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+

/SPDIF_OUT2

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

GPIO0 = ANALOG SW CONTROL

GPIO3 = SPKR AMP SHDN CONTROL

GPIO1 = HP AMP CONTROL

4.5V POWER SUPPLY FOR CODEC

NOTES ON CODEC I/O

NC

APPLE P/N 353S2355

AUDIO CODEC

NC

U6201 CONSUMES 33MA MAX. FROM 1.8V RAIL

NC

NC NC

FR SPKR AMP. SIG. SOURCE

LFT. SPKR AMP. SIG. SOURCE

RT. SPKR AMP. SIG. SOURCE

EXT MIC CODEC INPUT

BI MIC CODEC INPUT

DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS

APPLE P/N 353S2456

C6221

10UF

603-1

1

6.3V 2

X5R

20%

CRITICAL

XW6201

12

SM

C6222

6.3V

1

2

20%

402-LF

CERM

2.2UF 2.2UF

C6223

2

20%

1

6.3V CERM

402-LF

X5R

603-1

1

6.3V

2

20%

10UF

C6220

CRITICAL

0603-SM

1UF

C6224

1

TANT

2

20% 16V

X5R-1

C6210

4.7UF

4V

402

1

20%

2

20D2 76B3

20D2 76A3

20D7 76A3

57D8

55C7

54C7

54B7

55B7

55C7

57C4

57C3

57B4

20%

603-1

1

X5R

2

6.3V

10UF

CRITICAL

C6213

402

X5R

10V

2

10%

1UF

1

C6201

1UF

X5R 402

10V

10%

1

2

C6203

2

0402

FERR-220-OHM

1

L6200

2.21K

1/16W

12

402

MF-LF

1%

R6200

402

X5R

C6200

10V

10%

1

2

1UF

402

16V

0.1UF

10%

C6215

X5R

1

2

10%

402

2

0.1UF

16V X5R

1

C6211

X5R

0.1UF

16V

402

2

1

10%

C6214

1%

MF-LF 402

1/16W

2

1

R6210

2.67K

NOSTUFF

MF-LF

1

1/16W

5%

2

402

100K

R6213

5%

R6211

402

1/16W

1

MF-LF

39

2

0.1UF

C6218

2

1

X5R

16V

10%

402

16V

C6225

10UF

2012-LLP

2

1

20%

TANT-POLY

10UF

2012-LLP

2

1

16V

20%

C6217

TANT-POLY

16V

2012-LLP

10UF

TANT-POLY

C6219

20%

2

1

7C3

52D2 54D5 56B6

7C5

52D2 56D8 57B8 57D3

56D3

6C2

52A5 52D2

7B6

6C2

52A5 52D7

56D3

6C2

52D2 52D7

402-1

10%

1

10V X5R

2

C6216

1UF

TPS71745

1

2

5

3

SON

CRITICAL

4

6

U6200

2

1

402

X7R-CERM

C6202

16V

10%

0.1UF

55C7

55B7

55A7

XW6200

SM

NOSTUFF

R6201

5%

MF-LF

402

0

1/16W

L6201

12

0402

FERR-220-OHM

402

MF-LF

39

5%

1/16W

R6212

53C3

53B3

54C5

U6201

QFN

32

30

31

27

19 20

6

1

5

8

38

4

7

10

16

17

18

21

23

25

26

28

39

40

46

49

35

47

43

22

48

33

36 37

41

15

9

24

45

29

34

11

14

44

2

12

13

3

CS4206ACNZC

CRITICAL

42

56A7

AUDIO: CODEC/REGULATOR

051-7898

4.7.0

8152

AUD_LO2_P_L

AUD_LO1_P_R

TP_AUD_LO1_P_L

MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.30MM

HDA_BIT_CLK

HDA_RST_L

TP_AUD_SPDIF_IN

CS4206_FN

GND_AUDIO_CODEC

AUD_LI_P_R

HDA_SYNC

CS4206_FLYC

VOLTAGE=0V

GND_AUDIO_HP_AMP

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_GPIO_3

TP_AUD_LO1_N_L

AUD_SENSE_A

CS4206_FP

VBIAS_DAC

CS4206_FLYP

PP4V5_AUDIO_ANALOG

AUD_LO1_N_R

AUD_SPDIF_OUT_CHIP

AUD_LI_REF

CS4206_FLYN

=PP5V_S3_AUDIO

MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_R

MIN_LINE_WIDTH=0.30MM

MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_REF

MIN_LINE_WIDTH=0.30MM

CS4206_VCOM

AUD_LI_P_L

AUD_MIC_INP_L AUD_MIC_INN_L

AUD_CODEC_MICBIAS

TP_AUD_DMIC_CLK

AUD_SDI_R

HDA_SDOUT

AUD_MIC_INN_R

CS4206_VREF_ADC

AUD_LO2_N_L

MIN_NECK_WIDTH=0.10MM

VOLTAGE=1.8V MIN_LINE_WIDTH=0.10MM

=PP1V8_S0_AUDIO

HDA_SDIN0

4V5_REG_IN

VOLTAGE=5V

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM

GND_AUDIO_HP_AMP

PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM

=PP3V3_S0_AUDIO

4V5_REG_EN

=PP5V_S3_AUDIO

4V5_NR

AUD_SPDIF_OUT

GND_AUDIO_CODEC

GND_AUDIO_HP_AMP

=PP3V3_S0_AUDIO

AUD_GPIO_0

PP4V5_AUDIO_ANALOG

AUD_GPIO_1 TP_AUD_GPIO_2

MIN_LINE_WIDTH=0.5MM VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

GND_AUDIO_CODEC

AUD_MIC_INP_R

AUD_LO2_P_R AUD_LO2_N_R

PP1V8_S0_AUDIO_DIG

52A5 52B7 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1

52D2 52D7 54C4 54C7 56D2

7C3

52A8 54D5 56B6

52A5 52D7 54C4 54C7 56D2

52B7 52D2 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1

52A5 52D2 54C4 54C7 56D2

7C5

52A8 56D8 57B8 57D3

52A5 52D2 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

VIN = 2VRMS, CODEC VIN = 1.14 VRMS

LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS

FC_HP = 3.6 HZ

NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)

FC_LP = 43KHZ

56A7

56B7

56D2

52C2

52A5 52B7 52D2 56A7 57A8 57B4 57B8 57C3 57C8 57D1

402

10V

2.2UF

C6301

CRITICAL

X5R-CERM

20%

20% 10V

2.2UF

X5R-CERM

402

CRITICAL

C6302

C6312

20%

402

10V

2.2UF

CRITICAL

X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

CRITICAL

C6311

MF-LF

1/16W

402

1%

R6301

7.87K

R6311

MF-LF

1/16W

402

1%

7.87K

MF-LF

1/16W

402

1%

21.5K

R6302

MF-LF

1/16W

402

1%

R6312

21.5K

NOSTUFF

C6303

50V CERM 402

820PF

10%

NOSTUFF

C6313

50V CERM 402

820PF

10%

2

10

1%

402

MF-LF

1/16W

1

R6300

051-7898

53 81

4.7.0

AUDIO: LINE INPUT FILTER

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_R

AUD_LI_REF

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

GND_AUDIO_CODEC

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_P_R

AUD_LI_P_L

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_L

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_L_DIV

AUD_LI_R_DIV

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_GND

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

OUT

SVSS

INL

SHDN*

INR

VDD

PVSS

PGND

SGND

THRM

OUTR

OUTL

C1P C1N

PAD

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

AV_PB = -1V/V, FC_LPF = 35.2KHZ

HP/LO AMP

FOR PROTO2, STUFF R6521 AND NO STUFF R6520 AND R6522 UNTIL RE-TASKABLE IO SW SUPPORT AVAILABLE (FORCES IO INTO OUTPUT MODE).

NC

MAX9724 GAIN/FILTER COMPONENTS

APN: 353S1637

54B4

16V

2

CRITICAL

1

X7R-CERM

402

10%

0.1UF

C6500

5%

1/16W

2

1

MF-LF

402

39

R6500

CRITICAL

C6510

402

X7R-CERM

16V

10%

0.1UF

2

1

1/16W

1

2

MF-LF

402

39

5%

R6510

9

6

5

8

12

4

2

7

13

10

11

1 3

TQFN

MAX9724A

U6500

CRITICAL

C6522

10%

1UF

402

X5R

10V

402

10%

1UF

C6523

CRITICAL

X5R

CRITICAL

C6524

10V X5R 402

10%

1UF

C6501

402

1

2

10%

NO STUFF CRITICAL

50V

CERM

0.0022UF

6.3V

20%

10UF

X5R 603

C6521

402

C6520

10%

X7R-CERM

0.1UF

16V

FERR-120-OHM-1.5A

0402-LF

L6520

402

5%

MF-LF

1/16W

R6522

100K

1/16W MF-LF

402

13.7K

R6531

1%

1/16W

R6530

1%

13.7K

402

MF-LF

402

MF-LF

1/16W

R6533

13.7K

1%

R6532

MF-LF

1/16W

402

13.7K

1%

10% 50V

402

CERM

1

2

NO STUFF

C6511

CRITICAL

0.0022UF

5%

330PF

C6530

CRITICAL

COG 402

50V

C6531

50V COG 402

330PF

5%

CRITICAL

5%

1/16W

402

21

MF-LF

R6520

0

R6521

0

402

MF-LF

1/16W

NO STUFF

5%

54C6

54B6

52C7

54B1 56B7

54B4

54D1 56B7

54C1 56B7

21

402

MF-LF

1/16W

5%

0

R6501

R6511

12

5%

0

MF-LF

1/16W

402

52D2

52A5 52D2 52D7 54C4 56D2

52D2

4.7.0

051-7898

54 81

SYNC_DATE=02/03/2009

SYNC_MASTER=AUDIO

AUDIO: HEADPHONE FILTER

GND_AUDIO_HP_AMP

AUD_GPIO_1

AUD_GPIO_1_R

AUD_LO_AMP_INR_M

AUD_LO_AMP_INL_M

AUD_LO_AMP_OUTL

MAX9724_C1N

=PP5V_S3_AUDIO

AUD_HP_L

MAX9724_C1P

AUD_HP_PORT_L

GND_AUDIO_HP_AMP

AUD_HP_ZOBEL_L

AUD_LO_AMP_INR_M

AUD_LO_AMP_INL_M

AUD_HP_PORT_R

AUD_HP_L

AUD_HP_R

MAX9724_SVSS

AUD_PP5V_F

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_HP_ZOBEL_R

AUD_LO_AMP_OUTR

AUD_LO_AMP_OUTL

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM

AUD_LO_AMP_OUTR

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM

AUD_HP_R

52A5 52D2 52D7 54C7 56D2

54B3

7C3

52A8 52D2 56B6

54C4

IN

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SATELLITE & SUB TWEETER AMPLIFIER

169 HZ < FC < 282 HZ

80 HZ < FC < 132 HZ 6DB

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

APN:353S2524

SUB GAIN

SATELLITE

C6610

10%

0.047UF

16V

21

402

X7R

CRITICAL

52C2

C6607

1UF

X5R

10%

10V

402

1

2

L6620

0402

12

FERR-1000-OHM

L6610

0402

12

FERR-1000-OHM

L6630

FERR-1000-OHM

0402

12

52C2

1UF

X5R

10V

10%

C6609

402

1

2

U6630

TDFN

MAX9705A

CRITICAL

11

U6610

MAX9705A

47

1

10

3

2

6

9

8

5

TDFN

U6620

MAX9705A

TDFN

CRITICAL

X7R

16V

10%

C6611

12

402

CRITICAL

0.047UF

1UF

X5R

10%

C6608

402

1

2

10V

2012-LLP

47UF

C6601

CRITICAL

2

1

TANT1

20%

6.3V

CRITICAL

20%

100UF

C6603

6.3V TANT

2

1

CASE-AL1

2012-LLP

C6605

CRITICAL

6.3V

20%

47UF

TANT1

1

2

R6610

12

1/16W

5%

402

MF-LF

0

52C7

X7R

16V

10%

0.047UF

12

402

C6630

CRITICAL

X5R

10%

16V

0.1UF

C6620

402

CRITICAL

402

MF-LF

1/16W

R6611

100K

5%

L6611

0402

12

FERR-1000-OHM

52C2

0.1UF

X5R

10%

16V

C6621

12

402

CRITICAL

L6621

FERR-1000-OHM

0402

12

52C2

0.047UF

10%

16V

X7R

C6631

12

402

CRITICAL

L6631

FERR-1000-OHM

0402

12

52C2

AUDI0: SPEAKER AMP

4.7.0

55 81

051-7898

SYNC_DATE=12/18/2008

SYNC_MASTER=AUDIO

=PP5V_S3_AUDIO_AMP

SPKRAMP_L_P_OUT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

MAX9705_L_N

MAX9705_L_P

SPKRAMP_L_N_OUT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_SHDN

=PP5V_S3_AUDIO_AMP

MAX9705_SUB_N

MAX9705_SUB_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_SUB_N_OUT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_SUB_P_OUT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_R_N_OUT

=PP5V_S3_AUDIO_AMP

MAX9705_R_N

MAX9705_R_P

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_R_P_OUT

MIN_NECK_WIDTH=0.20 MM

SPKRAMP_SHDN

AUD_LO2_N_R

SPKRAMP_INSUB_P

SPKRAMP_INSUB_N

AUD_GPIO_3

AUD_LO1_P_R

AUD_LO1_N_R

SPKRAMP_INL_P

AUD_LO2_N_L

AUD_LO2_P_L

SPKRAMP_INR_N

SPKRAMP_INL_N

AUD_LO2_P_R

SPKRAMP_INR_P

7C3

55C7 55D7

6D7

56B2

6D7

56B2

55B7 55C7

55A7 55C7

7C3

55B7 55D7

6C7

56B2

6C7

56B2

6C7

56A2

7C3

55B7 55C7

6C7

56B2

55A7 55B7

IN

OUT

BI

VCC

COM1

COM2

EN*

NC1

CB

NO1

NEG

GND

NO2

NC2

RIGHT

MIC

AUDIO

GND

LEFT

SWITCH

DETECT

B - VCC

POF

SHIELD

SHELL

PINS

C - GND

A - VIN

OPERATING VOLTAGE 3.3

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX

APN:518S0519

APN:518S0520

SPEAKER CONNECTOR

APN:518S0521

MIC CONNECTOR

APN:514-0671

CHASSIS GND STITCHES

GND STUFFING OPTIONS FOR CMOS SWITCH

APN: 353S2536

C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES

ANALOG AUDIO IO SWITCH

GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED

GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED

C6700

1

2

CERM

6.3V

10%

402

1UF

55C2

6C7

55B2

6C7

55C2

6C7

55C2

6C7

55A2

6D7

55B2

6D7

CRITICAL

J6703

M-RT-SM

5

1

78171-0004

6

4

3

2

J6702

78171-0002

3

M-RT-SM

2

1

4

CRITICAL

402

2

1

CRITICAL

DZ6704

6.8V-100PF

CRITICAL

402

2

1

6.8V-100PF

DZ6703

6.8V-100PF

2

1

CRITICAL

402

DZ6700

CRITICAL

2

1

6.8V-100PF

DZ6705

402

3

2

4

1

5

M-RT-SM

78171-0003

J6701

CRITICAL

33PF

50V

2

402

1

5%

CERM

C6761

33PF

402

1

2

50V CERM

5%

C6760

1

402

CERM

50V

5%

33PF

2

C6762

C6763

33PF

1

402

CERM

50V

5%

2

MF-LF

402

R6760

1/16W

5%

0

L6702

FERR-1000-OHM

12

0402

FERR-1000-OHM

L6701

0402

21

57C1

402

2

1

CRITICAL

DZ6701

6.8V-100PF

52D2

402

10%

0.0033UF

50V CERM

C6711

SM

XW6700

SM

XW6701

56B3

56A3

5%

1/16W

402

0

R6714

MF-LF

R6715

0

5%

MF-LF

1/16W

402

XW6711

SM

XW6710

SM

0

5%

1/16W

402

MF-LF

R6717

0

R6718

MF-LF

402

5%

1/16W

5%

R6719

0

1/16W MF-LF

402

1/16W MF-LF

402

5%

0

R6716

56C3

R6720

0

5% 1/16W MF-LF

402

A3

B4

U6700

MAX14504

CRITICAL

C3

A1

WLP

B1

A2

C2 B2

B3

A4

C1

C4

100K

1/16W

402

MF-LF

5%

R6721

X5R

C6710

1UF

10% 10V

402

1/16W MF-LF

0

5%

NOSTUFF

R6723

1/16W

0

MF-LF

402

NOSTUFF

R6722

5%

SPDIF-TXRX-K24

F-RT-TH

CRITICAL

6

J6700

4

7 8 9

3

1

2

5

13

12

11

10

R6712

24K

1/16W

5%

402

MF-LF

R6713

5%

24K

MF-LF 402

1/16W

5%

MF-LF

402

NOSTUFF

0

R6725

1/16W

5%

MF-LF

1/16W

402

0

R6724

R6726

0

5%

NOSTUFF

402

MF-LF

1/16W

NOSTUFF

R6727

MF-LF

5%

0

1/16W

402

53C6

53B6

54D1 54B1

54C1 54B1

52C7

L6706

FERR-220-OHM

0402

CRITICAL

52B7

21

0402-LF

FERR-120-OHM-1.5A

L6703

CRITICAL

FERR-220-OHM

21

L6705

CRITICAL

0402

L6704

21

CRITICAL

0402

FERR-220-OHM

57C8 57C6

57C8 57A7

402

5%

1

MF-LF

1/16W

10K

2

R6700

R6701

1/16W

5%

MF-LF

4.7

402

21

C6701

CERM

100PF

50V

5%

2

1

402

SYNC_MASTER=AUDIO

AUDIO: JACK

SYNC_DATE=03/20/2009

81

4.7.0

56

051-7898

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM

AUD_CONN_L

AUD_CONN_R

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.2MM

AUD_SWITCH_GND

SWITCH_CP

AUD_SPDIF_OUT

AUD_LI_L

AUD_GPIO_0

AUD_LO_AMP_OUTR_SWITCH

AUD_LI_L_SWITCH

GND_AUDIO_HP_AMP

=PP3V3_S0_AUDIO

SPKRAMP_L_P_OUT

AUD_J1_TIPDET_R

SPKRAMP_SUB_P_OUT

HS_MIC_LO

HS_MIC_HI

BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI

SPKRAMP_L_N_OUT

SPKRAMP_SUB_N_OUT SPKRAMP_R_P_OUT

SPKRAMP_R_N_OUT

AUD_CONN_L

=PP3V42_G3H_AUDIO

GND_CHASSIS_AUDIO_JACK

GND_AUDIO_CODEC

AUD_CONN_GND

=PP5V_S3_AUDIO

PP_MAX14504_VCC

AUD_LI_R

AUD_LI_R_SWITCH

AUD_SWITCH_CTRL

AUD_LO_AMP_OUTL

AUD_LO_AMP_OUTL_SWITCH

AUD_LO_AMP_OUTR

AUD_CONN_R

AUD_J1_SLEEVEDET_R

AUD_LI_GND

AUD_CONNJ1_SLEEVEDET

AUD_CONNJ1_RING

AUD_CONNJ1_TIP

AUD_CONNJ1_TIPDET

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

AUD_CONN_GND

AUD_HP_PORT_REF

AUD_CONNJ1_MIC

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

AUD_CONNJ1_SLEEVE

54C7 54C4 52D7 52D2 52A5

57D3 57B8 52D2 52A8

7C5

57B1

6D7

57B1

6D7

57B1

6D7

7D1

57D1 57C8 57C3 57B8 57B4 57A8 53B6 52D2 52B7 52A5

56D2

54D5 52D2 52A8

7C3

53B6

56D2 56A7 56D2 56A7

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

IN

OUT

IN

OUT

IN

BI

IN

OUT

IN

GND THM

ENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASS

INT*

SCL

D

SG

D

SG

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LINE IN SATELLITES

0X03 (3)

0X05 (5)

VOLUME 0X02 (2)

CODEC INPUT SIGNAL PATHS

0X0D (B)

DET ASSIGNMENT

0X06 (6)

0X0D (13,B,RIGHT) 0X0D (13,V22,B,LEFT)

PORT A DETECT (HEADPHONES)

MIKEY

N/A

0X09 (A)AND UI ELEMENT

0X09 (A)

DET ASSIGNMENT

NC

APN:376S0613

EXTRACTION NOTIFICATION CKT

PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA

PULLUPS ON MCP PAGE

HEADSET MIC

HP=80HZ, LP=8.82KHZ

APN:353S2256

BUILT-IN MIC

0X06 (6)

CONVERTER

PORT B LEFT(HEADSET MIC)

DRC MIKEY

FUNCTION

HP=80HZ

NC

PORT B RIGHT(BUILT-IN MIC)

FUNCTION

PORT B DETECT(SPDIF DELEGATE)

0X0B (11)

0X10 (16)

0X03 (03)

0X04 (4)

N/A

SPDIF OUT

SUB

HP/LINE OUT

VREF

N/A

0X0A (10)

GPIO_0 AND GPIO_1

N/A

GPIO_3 GPIO_3

0X08 (8)

0X0C (12)

0X09 (9,A)

PIN COMPLEX

GPIO_0 AND GPIO_1

MUTE CONTROL

MIC_BIAS (80%) MIKEY

0X05 (5) 0X04 (4)

0X02 (2)

CODEC OUTPUT SIGNAL PATHS

C6801

1

402

0.1UF

CERM

20%

10V

2

47K

1/16W MF-LF

402

5%

12

R6802

56C3 57A7

R6806

402

39.2K

1/16W

1%

MF-LF

1

2

1/16W

5%

220K

402

MF-LF

12

R6803

R6804

220K

1/16W MF-LF

5%

402

1

2

C6802

2

1

10%

402

0.01UF

CERM

16V

52C7

56C3 57C6

20.0K

1/16W MF-LF

1

1%

R6805

402

2

SOT563

SSM6N15FEAPE

Q6800

3

5

4

Q6800

SSM6N15FEAPE

SOT563

1

2

6

SSM6N15FEAPE

Q6801

4

SOT563

3

5

SOT563

SSM6N15FEAPE

Q6801

2

1

6

2.4K

R6851

1/16W

1%

21

402-1

MF

CERM

402

5%

27PF

1

50V

C6854

2

CRITICAL

1

10% 25V

402

CRITICAL

0.1UF

2

X5R

C6850

2

1

402

50V

CERM

CRITICAL

10%

0.001UF

C6853

402

100K

R6852

5% 1/16W MF-LF

2

1

21

SM

XW6851

52C2

6D7

56C2

6D7

56C2

6D7

56C2

CRITICAL

1

C6852

2.2UF

402

2

6.3V TANT

20%

21

L6851

FERR-1000-OHM

0402

FERR-1000-OHM

0402

L6850

12

56D3

402

5%

MF-LF

1/16W

2.2K

2

MIKEY

1

R6882

C6885

CERM1402

50V

5%

27PF

MIKEY

CRITICAL

2

25V

2

402

10%

1

0.0082UF

CRITICAL

X7R

C6884

MIKEY

R6883

2

5%

1

100K

402

MF-LF

1/16W

MIKEY

X5R

CRITICAL

C6883

0.1UF

10% 25V

402

21

MIKEY

12

SM

XW6880

52C2

MIKEY

1

2

402

1%

MF-LF

R6881

1K

1/16W

R6880

1

5%

2

MF-LF

100K

402

1/16W

MIKEY

C6881

1

0.01UF

2

CERM

10%

402

MIKEY

16V

1

0402

MIKEY

2

FERR-1000-OHM

L6880

TANT

6.3V

1

2

402

2.2UF

MIKEY

20%

CRITICAL

C6882

20A4 20C3

43B6

18D7

1/16W MF-LF

402

2

5%

2.2K

1

R6884

MIKEY

CRITICAL

MIKEY

C6886

0.1UF

X5R

10% 25V

402

21

52C2

C6851

1

CRITICAL

0.1UF

25V X5R 402

2

10%

MF-LF

1/16W

1%

402

21

R6850

100

2.4K

MF

1%

1/16W

R6853

402-1

21

16B6

0

1/16W MF-LF

5%

402

R6861

CERM

0.1UF

1

402

20%

10V

C6861

2

L6862

FERR-1000-OHM

0402

21

7C5

52A8 52D2 56D8 57D3

11

8

4

3

5

1

2

10

6

DRC

MIKEY

7

CD3275

9

U6880

402

CERM

1UF

10%

6.3V

C6880

MIKEY

CRITICAL

SSM6N15FEAPE

6

1

2

SOT563

Q6802

SSM6N15FEAPE

SOT563

Q6802

5

4

3

5%

15K

402

1/16W MF-LF

R6860

10V CERM 402

0.1UF

20%

C6860

5%

220K

402

1/16W MF-LF

R6864

402

MF-LF

1/16W

5%

100K

R6865

R6801

300K

5%

402

1/16W MF-LF

AUDIO: JACK TRANSLATORS

SYNC_MASTER=AUDIO

051-7898

57 81

4.7.0

SYNC_DATE=03/20/2009

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

AUD_J1_SLEEVEDET_R

AUD_J1_DET_RC

HS_MIC_LO

HS_MIC_BIAS

GND_AUDIO_CODEC

BI_MIC_HI

HS_MIC_HI

GND_AUDIO_CODEC

AUD_CODEC_MICBIAS

BI_MIC_LO_F

AUD_MIC_INN_R

GND_AUDIO_CODEC

AUD_MIC_INP_R

BI_MIC_LO

GND_AUDIO_CODEC

MIC_BIAS_FILT

PP3V3_S0_AUDIO_F

HS_RX_BP

HS_MIC_HI_RC

BI_MIC_HI_F

AUD_IPHS_SWITCH_EN

AUD_MIC_INP_L

AUD_MIC_INN_L

HS_SW_DET

GND_AUDIO_CODEC

AUD_I2C_INT_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM

PP3V3_S0_HS_RX

=PP3V3_S0_AUDIO

AUD_J1_SLEEVEDET_R

GND_AUDIO_CODEC

BI_MIC_SHIELD

AUD_J1_TIPDET_INV

TIPDET_FILT

PP3V3_S0_AUDIO_F

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.10MM

VOLTAGE=3.3V

AUD_PERPH_DET_R

AUD_IP_PERIPHERAL_DET

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

AUD_J1_TIPDET_R

PP3V3_S0_AUDIO_F

AUD_PORTA_DET_L

AUD_J1_SLEEVEDET_INV

AUD_OUTJACK_INSERT_L

AUD_PORTB_DET_L

AUD_J1_TIPDET_R

AUD_SENSE_A

56C3 57C8

52A5 52B7 52D2 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1

52A5 52B7 52D2 53B6 56A7 57A8 57B4 57B8 57C3 57C8

52A5 52B7 52D2 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1

57B8 57C8

52A5 52B7 52D2 53B6 56A7 57A8 57B4 57C3 57C8 57D1

7C5

52A8 52D2 56D8 57B8

52A5 52B7 52D2 53B6 56A7 57A8 57B4 57B8 57C3 57D1

52A5 52B7 52D2 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1

57C8

52A5 52B7 52D2 53B6 56A7 57B4 57B8 57C3 57C8 57D1

56C3 57C8

57B8 57C8

NC

VCC

EXTINT

NC

GND

BI

Y

B

A

BI

P3 P4 P5 P6 P7 P8

P1 P2

P9

SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = 1.25V * (1 + Ra / Rb)

<Rb>

(Switcher limit)

250MA MAX OUTPUT

MagSafe DC Power Jack

518-0359

Vout = 3.425V

<Ra>

NC

516S0523

NC

TO SMC

BATTERY CONNECTOR

1-Wire OverVoltage Protection

BIL CONNECTOR

518S0656

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

C6905

50V

1

0.01UF

603

20%

CERM

2

1

2

6.3V

20%

CERM 805

22UF

CRITICAL

C6999

2

L6995

33UH

CDPH4D19FHF-SM

1

CRITICAL

C6994

1

2

X5R

6.3V

402

20%

0.22uF

1/16W MF-LF

348K

1

1%

R6995

402

2

402

CERM

50V

22pF

1

C6995

5%

1

2

402

1%

200K

1/16W

R6996

MF-LF

10%

2

1

805

10UF

C6990

X5R

25V

R6905

12

805

5%

1/8W

47

MF-LF

3

2

1

M-RT-SM

J6900

4

CRITICAL

78048-0573

5

1

5

2

4

3

D6905

HN2D01JEAPE

CRITICAL

SOT665

2

0

R6928

1

402

MF-LF

1/16W

5%

CERM

C6954

1

2

10%

402

50V

0.001UF

10%

402

2

25V

1

X5R

0.1UF

C6950

25V

1

2

402

X5R

0.1UF

C6951

10%

21

5%

402

R6960

1/16W

10K

MF-LF

CRITICAL

F6905

6AMP-24V

1206-1

12

CRITICAL

3

1

D6950

SC-75

2

RCLAMP2402B

C6908

0.1UF

1

402

2

CERM

10V

20%

PLACEMENT_NOTE=PLACE NEAR U6901

1

4

SC70-5

5

2

3

MAX9940

U6900

40B8

1

SOT665

5

3

4

U6901

2

TC7SZ08AFEAPE

1

2

402

1/16W MF-LF

5%

R6950

10K

CRITICAL

CPB6312-0101F

5

J6955

16

12

10

8

6

43

7

15

12

14 13

F-ST-SM

11

9

50V

CERM

402

47PF

5%

1

C6952

2

47PF

5%

1

2

402

50V

C6953

CERM

58A6 43C3

C6955

0.001UF

402

2

10% 50V CERM

1

402

2

1/16W

1

R6961

5%

100

MF-LF

CRITICAL

4

6 7 8

1 2

9

11 12 13

5

10

M-RT-TH

J6950

BAT-K24

3

4

6

5

1

9

8

3

2

LT3470A

DFN

U6990

7

CRITICAL

2.0K

402

5%

1/16W

MF-LF

12

ONEWIRE_PU

R6929

SYNC_DATE=12/11/2008

SYNC_MASTER=YUNWU

DC-In & Battery Connectors

4.7.0

051-7898

8158

P3V42G3H_FB

=PP3V42_G3H_ONEWIRE

SMC_BC_ACOK

=PP18V5_DCIN_CONN

SMC_BC_ACOK_VCC

ADAPTER_SENSE_R

=PP3V42_G3H_BATT

=PP18V5_DCIN_CONN

SMC_LID

SMC_LID_R

=PP3V42_G3H_BATT

=SMBUS_BATT_SCL

=SMBUS_BATT_SDA

SMC_BIL_BUTTON_L

ADAPTER_SENSE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20mm

MIN_LINE_WIDTH=1mm

PP18V5_DCIN_FUSE

P3V42G3H_BOOST

DIDT=TRUE

=SMBUS_BATT_SCL SYS_DETECT_L

BATT_POS_F

MIN_NECK_WIDTH=0.3 mm

BATT_POS_F

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=12.6V

SYS_ONEWIRE

PPDCIN_S5_P3V42G3H

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

=PP3V42_G3H_REG

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm

P3V42G3H_SW

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

DIDT=TRUE

SWITCH_NODE=TRUE

7D1

41D5 41B2 40C5

58C8

7D2

58C2

7D1

58D1

7D2

48A5 41C2 40B5

6A7

58C4

7D1

58C3 43C3

6B3

6C3

58C3 43C3

6A7

59A3 58B8

6A7

59A3 58A7

6A7

7D2

GND

VCC

D

SG

D

SG

CSON

CSOP

VNEG

VCOMP

ICOMP

VREF ACIN

SDA

VHST SCL

VDDP

BGATE

VDD

ACOK

THRM_PAD

AGATE

AGND

AMON BMON

BOOT

CSIN

CSIP

DCIN

LGATE

PGND

PHASE

UGATE

TRKL*

D

G

S

D

G

S

D

G

S

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(CHGR_CSOP)

(CHGR_ACIN)

NC

TO SYSTEM

(??? limited)

MAX CURRENT = 7A

PWM FREQ. = 400 kHz

AMON PULLDOWN LOGIC

(CHGR_CSON)

PBUS SUPPLY / BATTERY CHARGER

(CHGR_CSO_R_N)

BATTERY CHARGE LIMITING FETS

R7020

2

0612-1

MF

0.5%

0.02

1W

CRITICAL

1

2

402

MF-LF

5%

4.7

1/16W

1

R7040

C7025

2

1

0.1UF

10% 25V X5R 402

C7041

1UF

10V X5R

10%

402-1

21

2

1

603-1

1UF

25V

10% X5R

C7023

2

1

603-1

25V

1UF

X5R

C7022

10%

25V

20% POLY-TANT

1

22UF

2

CRITICAL

CASE-D2-SM

C7020

CRITICAL

20%

C7021

25V

22UF

POLY-TANT CASE-D2-SM

2

1

C7040

10% X5R

10V 402-1

1UF

1

2

1UF

X5R

10V

10%

402-1

1

2

C7047

0.1UF

C7010

1

2

10%

402

X5R

25V

C7044

0.01UF

CERM

1

2

16V 402

10%

1/16W

R7045

402

MF-LF

56.2K

1%

2

1

C7045

0.001UF

1

2

50V

CERM

10%

402

MF-LF

R7046

1

2

402

1%

1/16W

3.01K

CERM

470PF

C7046

1

2

10%

402

50V

SM

21

XW7000

50V X7R

10%

402

1

2

0.001UF

C7026

0.1UF

2

X5R

10% 25V

402

1

C7063

R7060

1%

1

2

57.6K

1/16W MF-LF

402

R7099

5%

1

1/16W MF-LF

100K

2

402

2

402

MF-LF

5%

1/16W

100K

1

R7098

5

4

3

1

2

SOT23-5

TL331

U7060

CRITICAL

1

X5R 402

25V

0.1UF

C7060

2

10%

SSM6N15FEAPE

6

Q7070

SOT563

1

2

SOT563

SSM6N15FEAPE

4

5

3

Q7070

2

SM

1

XW7021

SM

XW7020

12

1

0.047UF

10%

402

CERM

2

10V

C7024

1

10

5% 1/16W MF-LF 402

2

R7021

5%

10

1/16W

R7023

MF-LF

1

402

2

10% X5R

25V

0.1UF

1

2

402

C7061

25V

0.1UF

1

2

402

X5R

10%

C7062

1

R7062

2

402

5%

62K

1/16W

MF-LF

12

5%

1/16W

402

MF-LF

62K

R7001

402

16V

12

0.1UF

X5R

10%

C7043

402

1/16W

1%

30.1K

R7010

1

2

MF-LF

R7011

9.31K

1%

402

1

2

1/16W

R7073

5%

1/16W

MF-LF

1K

402

2

1

R7074

1M

5%

1/16W

402

MF-LF

2

1

MF-LF

R7075

1/16W

402

1M

5%

NOSTUFF

2

1

1%

402

R7061

1

2

1.82K

MF-LF

1/16W

Q7020

LFPAK-HF

4

5

321

CRITICAL

RJK0305DPB

CRITICAL

5

321

4

Q7021

RJK0305DPB

LFPAK-HF

F7000

CRITICAL

21

1206

7AMP

1UF

1

25V

10%

X5R

C7011

603-1

2

1

2

20% 16V

33UF

CASED2E-SM

POLY-TANT

CRITICAL

C7008

1/16W

402

MF-LF

10

5%

R7031

R7047

5%

402

1/16W

10

MF-LF

U7000

3

14

1

6

26

9

16

15

27

28

17

18

5

23

11 10

29

13

7

19

12

8

4

20

2

24

22

25

ISL6258A

QFN

CRITICAL

21

0.033UF

C7042

1

2

10% 16V X5R 402

L7000

4.7UH-9.5A

12

CRITICAL

IHLP4040DZ-SM

CRITICAL

SOD-723-HF

1SS418

D7010

12

0.001UF

20%

C7028

1

2

50V 402

CERM

0.001UF

C7027

1

2

50V

20%

402

CERM

CRITICAL

R7008

MF

1W

0.01

0.5%

0612-1

12 34

4

3

5

21

SO-8

CRITICAL

SI7137DP

Q7050

5

4

312

LFPAK-SM

HAT1127H

Q7001

CRITICAL

HAT1127H

LFPAK-SM

213

4

5

Q7000

0.01uF

CERM

16V 402

10%

2

1

C7050 C7051

2

10%

402

1

16V

0.1UF

X5R

SYNC_MASTER=RAYMOND

PBUS Supply/Battery Charger

59

051-7898

4.7.0

81

SYNC_DATE=01/31/2008

=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA

=PP3V42_G3H_CHGR

CHGR_LGATE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

GND_CHGR_SGND

CHGR_CSOP

CHGR_BOOT

DIDT=TRUE

CHGR_CSIP_XW7020

CHGR_LOWCURRENT_GATE

CHGR_CSIN

CHGR_CSIN_XW7021

CHGR_AMON

MIN_LINE_WIDTH=0.6 MM

PP18V5_S5_CHGR_SW_R

MIN_NECK_WIDTH=0.3 MM

PPVDCIN_G3H_PRE2

MIN_LINE_WIDTH=0.6 MM

CHGR_SGATE

=PP18V5_G3H_CHGR

=PP3V42_G3H_CHGR

CHGR_VDD

CHGR_BGATE

CHGR_PHASE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

CHGR_UGATE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CHGR_AGATE

CHGR_VNEG

CHGR_ACIN

CHGR_ICOMP

=PP3V42_G3H_CHGR

CHGR_CSIP

CHGR_VDD_L

CHGR_DCIN

CHGR_LOWCURRENT_REF

=PPBUS_G3H

CHGR_AMON CHGR_BMON

CHGR_VNEG_R

GND_CHGR_SGND

=CHGR_ACOK

CHGR_VDDP

PPVBAT_G3H_CHGR_OUT

CHGR_VCOMP

CHGR_DCIN

CHGR_VDD

CHGR_VDD_R

GND_CHGR_SGND

CHGR_AMON

CHGR_VCOMP_R

BATT_POS_F

CHGR_BGATE

PPVBAT_G3H_CHGR_OUT

CHGR_CSON

CHGR_LOWCURRENT_GATE_R

MIN_NECK_WIDTH=0.25 MM

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 MM

CHGR_CSO_R_P

CHGR_CSO_R_N

PPVDCIN_G3H_PRE

MIN_NECK_WIDTH=0.3 MM

MIN_LINE_WIDTH=0.6 MM

43B3

7D1

59A8 59D5

59B8 59C4

45B3 59B8

59C5

7C1

7D1

59A8 59C6

59A8

59A3

7D1

59C6 59D5

59D8

7C2

45B3 59B8

59D4

45A6

59B6 59B8

41D4 59A5

59C5

59C6

59B6 59C4

45B3 59C5 59D4

6A7

58A7 58B8

59C5

59C1

45A8 80D3

IN

D

SG

D

SG

Q1

Q2

SW

S

D

G

S

D

G

DRVH1

SKIPSEL

VBST1

GND

THRM_PAD

ENTRIP1

VFB1

VO1

DRVL1

LL1

EN0

VCLK

ENTRIP2

PGOOD

VO2

VFB2

DRVL2

LL2

DRVH2

VBST2

VREG5

VREG3

VREF

VIN

TONSEL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Place XW7205 by C7252.

PWM FREQ. = 375 KHZ

MAX CURRENT = 8A

PWM FREQ. = 300 KHZ

Place XW7204 by Pin 2 of L7220.

Place XW7201 between Pin 15 and Pin 25 of U7200.

NC

ROUTING NOTE:

Place XW7203 by Pin1 OF L7260.

SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.

ROUTING NOTE:

<RB>

ROUTING NOTE:

VOUT = (2 * RC / RD) + 2

<RC>

ROUTING NOTE:

VOUT = (2 * RA / RB) + 2

5V_S3/3.3V_S5 POWER SUPPLY

Place XW7202 by C7292.

MAX CURRENT = 4A

1

10UF

603

2

20% X5R

6.3V

C7273

XW7201

SM

12

66C6

66D6

Q7221

1

2

6

SOT563

SSM6N15FEAPE

Q7221

4

5

3

SOT563

21

SM

XW7203

SM

21

XW7205

SM

21

XW7204

SM

21

MF-LF

100K

5%

402

1/16W

1

2

X5R

16V 402

50V 402

C7282

20%

0.001UF

2

1

2

1

50V CERM

2

20%

402

1

0.001UF

C7293

C7253

0.001UF

50V CERM 402

1

2

20%

CRITICAL

C7291

6.3V ELEC

220UF

20%

D1A-SM

2

1

20%

10UF

C7250

2

X5R

1

603

CRITICAL

L7260

4.7UH-13A-15MOHM

PCMB104E4R7-SM

21

R7270

6.49K

1%

402

MF-LF

1/16W

12

R7269

1

402

10K

1% MF-LF

2

1/16W

1

2

0.1UF

1

16V

10% X5R

402

2

MF-LF

21

R7267

402

1% 1/16W

15.0K

R7268

10K

1/16W MF-LF

1%

21

402

C7281

25V

10% X5R

1

2

1UF

603-1

C7290

20% X5R

603

1

10UF

6.3V

2

SI7110DN

Q7260

CRITICAL

5

312

12

CRITICAL

SI7108DN

2413

5

PWRPK-1212-8-HF

Q7261

TPS51125

2

3V3S5_VFB

18

10

12

13

U7200

3

8

7

16

5

4

23

20

6

21

14

25

1

24

19

17

15

5V3V3S5_REG5

11

1

R7271

86.6K

1% 1/16W

402

2

MF-LF

75K

R7272

1%

1

1/16W MF-LF

2

402

C7272

1UF

25V

10% X5R

603-1

1

2

6.3V

1

X5R

20%

10UF

402

2

1

0.22UF

051-7898

60 81

4.7.0

SYNC_DATE=02/08/2008

=PP5V_S3_REG

VOLTAGE=5V VOLTAGE=3.3V

5V_S3_ENTRIP

P5V3V3_PGOOD

3V3S5_ENTRIP

DIDT=TRUE

3V3S5DRVL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

5V_S3_LL

5V_S3_VFB

5VS3_3V3S5_VREF

DIDT=TRUE

5V_S3_DRVL

SMC_PM_G2_EN

=P5VS3_EN_L

GND_5V3V3S5_SGND

3V3S5_VFB_R7270

5V_S3_VFB_XW7203

=P3V3S5_EN_L

=PPVIN_S3_5VS3

3V3S5VO2

5V3V3_REG_EN

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDT=0.2

3V3S5_LL

=PPVIN_S3_5VS3

GND_5V3V3S5_SGND

MIN_LINE_WIDTH=0.6 MM

5V_S3_DRVH

SYNC_MASTER=RAYMOND

=PP3V3_S5_REG

C7242

1UF

10% 25V X5R 603-1

402

CERM

50V

20%

QFN

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

C7260

10% 10V CERM

10%

603

POLY

16V

20%

CRITICAL

CERM

5V_S3_VO1

C7280

CRITICAL

39UF-0.027OHM

20% 16V POLY

6.3V

IHLP2525CZ

C7251

CRITICAL

C7271

XW7202

=PPVIN_S5_3V3S5

39UF-0.027OHM

B1A-SM

2

1

12

DIDT=TRUE

3V3S5_VBST

9

CRITICAL

22

5V_S3_VBST

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

4

PWRPK-1212-8-HF

B1A-SM

2

1

5V/3.3V SUPPLY

POLY

6.3V

20%

150UF

B1A-SM

2

1

L7220

DIDT=TRUE

C7220

4.7UH-5.5A

C7270

R7273

0.001UF

C7240

C7241

0.1UF

2

5V3V3S5_REG3

10

8

7

56

9 4 23

1

FDMS9600S

MLP

CRITICAL

Q7220

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

3V3S5_DRVH

7C4 7B4

66A5

6C3

40D5 66D8

60B5

7C1

60C7

7C1

60C6

60C4

VDDQSET

S3

COMP

VTT

THRM_PAD

DRVH

LL

PGND

CS_GND

CS

PGOOD

NC1

S5

NC0

GND

VTTGND

MODE

DRVL

VTTREF VLDOIN

VBST V5IN

VDDQSNS

VTTSNSV5FILT

SYM (1 OF 2)

S

D

G

S

D

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1.5V/0.75V(DDR3) POWER SUPPLY

USING KEVIN CONNECTION.

PUT 6 VIAS UNDER THE THERMAL PAD

Place XW7301 by L7320.

ROUTING NOTE:

PP0V75_S0

1.5VHIGH

LOW 0.0V

1.5V

0.75V

ROUTING NOTE:

Q7321 PIN1,2.3

CONNECT CS_GND TO

ROUTING NOTE:

NC

<RB>

<RA>

Pin 3 and Pin 25 of U7300.

ROUTING NOTE:

PUT ONE BULK CAP NEXT TO THE LOAD

MAX CURRENT = 12A

PM_SLP_S3_L

S3

HIGH

PM_SLP_S4_L

LOW

PP1V5_S3

0.0V

0.0VS5/G3HOT

S0

STATE

PWM FREQ. = 400 KHZ

VOUT = 0.75V * (1 + RA / RB)

ROUTING NOTE:

Place XW7303 by C7308.

ROUTING NOTE:

NC

Place XW7302 by Q7321.

Place XW7300 between

8

TPS51116

U7300

CRITICAL

16

17

3

4

12

18

10 11

25

14

9

23

24

1

5

QFN

6

22

15

7

2

19

21 20

13

12

CRITICAL

L7320

SM-IHLP-1

402

MF-LF

2

5%

0

1/16W

R7300

1

X5R 402

16V

10%

C7309

0.1uF

2

1

2

6.3V X5R

20%

10UF

603

C7341

1

C7302

2

6.3V X5R

10UF

20%

603

1

2

402

10.7K

1/16W

1%

R7310

MF-LF

R7307

12

4.7

5% 1/16W MF-LF 402

12

SM

XW7300

R7321

402

1/16W

0.1%

20K

MF

21

R7322

12

MF 402

0.1%

20K

1/16W

NO STUFF

C7303

12

5% 50V

100PF

CERM 402

6.3V

C7301

1

2

10UF

X5R 603

20%

10%

12

16V 402

X5R

C7340

0.033UF

22UF

C7307

603

6.3V

20%

2

1

CRITICAL

X5R-CERM-1

603

6.3V

22UF

20%

2

1

C7308

CRITICAL

X5R-CERM-1

X5R

12

402-1

1UF

10V

10%

C7300

CRITICAL

Q7320

35142

SI7110DN

PWRPK-1212-8-HF

23

PWRPK-1212-8-HF

Q7321

CRITICAL

5

4

1

R7399

100K

1/16W

12

402

MF-LF

5%

X5R

25V

10%

1

2

603-1

1

2

402

20% CERM

50V

C7344

1

2

CERM

50V

20%

402

0.001UF

12

SM

XW7301

1SM2

XW7302

XW7303

2

SM

1

CASE-B2-SM

2

1

C7342

2.5V TANT

330UF

20%

CRITICAL

CASE-B2-SM

2

1

2.5V TANT

330UF

20%

C7343

SYNC_MASTER=RAYMOND

1.5V/0.75V DDR3 SUPPLY

SYNC_DATE=01/31/2008

4.7.0

8161

051-7898

1V5S3_VDDQSET

=PP1V5_S3_REG

=PPVIN_S5_1V5S30V75S0

=DDRREG_EN

=PP3V3_S3_PDCISENS

1V5S3_CS

1V5S3_V5FILT

=PPVTT_S3_DDR_BUF

GND_1V5S3_CSGND

GND_1V5S3_SGND

=PP0V75_S0_REG

=DDRVTT_EN

1V5S3_DRVL

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.25 mm

DIDT=TRUE

1V8S3_VBST_RC

DDRREG_PGOOD

DIDT=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

1V5S3_LL

1V5S3_VDDQSNS

DIDT=TRUE

1V5S3_VBST

1V5S3_VTTSNS

=PP5V_S3_1V5S30V75S0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

1V5S3_DRVH

DIDT=TRUE

SI7108DN

CRITICAL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1.5 mm

VOLTAGE=1.5V

1.0UH-13A-5.6M-OHM

CRITICAL

39UF-0.027OHM 39UF-0.027OHM

C7331C7330

C7332 C7333

0.001UF

1UF

POLY

16V

20% 20%

16V POLY

CRITICAL

B1A-SM

2

1

B1A-SM

2

1

7D4

7C1

66C6

7D3

25D3

7C4

7C8

67A3 24C1

66A2

7C3

IN

OUT

IN

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT*

NTC

VR_ON

PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3

VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1

BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(GND)

(IMVP6_VO)

(GND)

MIN_LINE_WIDTH

R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED

(IMVP6_VW)

(NC)

DPRSLPVR

PWM FREQ. = 300 KHZ

LOAD LINE SLOPE = -2.1 MV/A

DCR=0.8MOHM

MIN_NECK_WIDTH

(IMVP6_ISEN2)

(IMVP6_VSUM)

1-PHASE DCM

DCR=0.8MOHM

MPC1055LR36

0

1

0

1

0

1

MPC1055LR36

MIN_NECK_WIDTHMIN_LINE_WIDTH

(IMVP6_VO)

ERT-J1VR103J

(IMVP6_FB)

(IMVP6_COMP)

MIN_LINE_WIDTH MIN_NECK_WIDTH

(IMVP6_PHASE1)

(IMVP6_ISEN1)

(IMVP6_PHASE2)

OPERATION MODE

1-PHASE CCM

0

1-PHASE DCM

0

2-PHASE CCM

MAX CURRENT = 44A

ERT-J0EV474J

IMVP6 CPU VCORE REGULATOR

FROM SMC

PSI*

DPRSTP*

0

NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.

0.0022UF

2

402

50V CERM

1

C7400

NO STUFF

10%

1

2

OMIT

XW7400

SM

R7400

10K

MF-LF

1/16W

1%

402

12

1%

402

MF-LF

1/16W

R7401

1

2

3.65K

2

402

10% 16V

1

X5R

0.1UF

C7415

R7416

13.7K

402

MF-LF

1%

1

2

1/16W

1%

11K

1/16W MF-LF 402

R7415

1

2

402

1/16W

10K

1% MF-LF

R7405

12

0.22uF

10% CERM-X5R

6.3V 402

C7404

12

1/16W

1%

402

3.65K

MF-LF

R7443

1

2

L7401

CRITICAL

0.36UH-30A-0.80MOHM

MPC1055-SM

12

L7400

0.36UH-30A-0.80MOHM

MPC1055-SM

CRITICAL

12

NO STUFF

402

CERM

50V

10%

0.0022UF

C7402

1

2

C7427

0.1UF

10%

X5R 402

1

2

16V

R7420

5%

10

402

1/16W

12

MF-LF

5%

402

10

1/16W

R7412

12

MF-LF

6.3V CERM

1UF

10%

402

C7426

1

2

402

CERM

10% 16V

0.01UF

C7496

1

2

1/16W MF-LF 402

5%

10

R7421

12

0.1uF

X5R 402

10% 16V

C7430

1

2

402

1K

NO STUFF

1/16W

1%

R7413

12

MF-LF

R7409

402

1% 1/16W

1K

1

2

MF-LF

1

R7411

402

1% 1/16W MF-LF

255

2

C7414

10%

402

470PF

50V CERM

1

2

402

1% 1/16W MF-LF

97.6K

1

2

R7414

CERM 402

25V

5%

220PF

C7413

1

2

402

0.001UF

CERM

10%

1

2

50V

C7407

MF-LF

1

1%

402

2

1/16W

6.81K

R7410

R7417

1% 1/16W MF-LF

5.36K

402

21

MF-LF

1%

402

1/16W

1

2

1K

R7418

50V

180pF

CERM 402

5%

C7429

1

2

CERM-X5R

10%

6.3V

0.22UF

402

C7428

1

2

10V CERM 402

C7431

1

10%

2

0.068UF

402

16V

10%

NO STUFF

C7432

12

0.01UF

CERM

16V

10%

402

X7R

12

0.018UF

C7433

0

5%

402

1

2

R7422

1/16W MF-LFMF-LF

1/16W

0

5%

402

R7423

1

2

0.12UF

2

C7434

10%

10.0V CERM-X5R 402

1

10UF

603

20%

6.3V X5R

1

2

C7435

MF-LF

1/16W

1%

402

R7427

12

4.02K

NO STUFF

10% 16V

0.01uF

CERM

C7410

12

402

NO STUFF

X7R 402

10% 16V

0.015uF

12

C7405

402

MF-LF

1/16W

1%

12

R7408

147K

C7406

0.001UF

10% CERM

402

50V

1

2

NO STUFF

0.001UF

50V

C7416

1

2

402

CERM

10%

R7430

3.92K

402

1% MF-LF

1/16W

2

1

CERM-X5R

0.22uF

402

6.3V

10%

C7421

12

402

CERM-X5R

6.3V

10%

0.22uF

C7403

12

1/16W

5%

1

402

MF-LF

R7404

12

5%

1

1/16W MF-LF 402

R7407

12

0603-LF

10KOHM-5%

CRITICAL

R7431

1

2

402

MF-LF

499

R7445

1

2

1/16W

1%

CRITICAL

402

470K

NO STUFF

R7426

12

0

1/16W

1

5%

402

2

MF-LF

R7425

5% 1/16W

402

0

MF-LF

2

R7424

1

5% MF-LF

402

1/16W

12

0

R7406

NO STUFF

1

2

CASED2E-SM

POLY-TANT

33UF

C7409

20%

CRITICAL

16V

1

2

CASED2E-SM

33UF

POLY-TANT

C7417

CRITICAL

16V

20%

CASED2E-SM

POLY-TANT

33UF

CRITICAL

20% 16V

C7408

2

1

2

1

603-1

C7418

X5R

1UF

25V

10%

1UF

25V

10% X5R

C7411

603-1

1

2

312

5

CRITICAL

RJK0305DPB

Q7400

4

LFPAK-HF

RJK0328DPB

3

LFPAK-HF

CRITICAL

Q7401

21

4

5

RJK0305DPB

LFPAK-HF

CRITICAL

Q7402

4

5

321

CRITICAL

RJK0328DPB

LFPAK-HF

Q7403

5

4

123

42

CRITICAL

26

36

14

7

21

3

9

19

5

44

18

20

43

41

39 38 37

13

22

27

35

49

15

4

31

2

28

1

29

8

6

25

30

23

24

12 11

16

46 45

17

10

47

48

34

40

QFN

U7400

33

32

ISL9504BCRZ

NO STUFF

10K

1%

1/16W

MF-LF

402

R7452

12

NO STUFF

1/16W MF-LF

402

1%

R7451

12

10K

MF-LF

1/16W

5%

2.0K

402

1

2

R7447

C7420

CERM

402

20%

0.001UF

50V

1

2

CERM

0.001UF

C7419

50V

20%

402

1

2

402

1

2

C7422

50V

0.001UF

20%

CERM

C7423

402

1

2

CERM

20%

0.001UF

50V

C7401

16V

20%

CRITICAL

33UF

CASED2E-SM

POLY-TANT

SYNC_MASTER=RAYMOND

IMVP6 CPU VCore Regulator

4.7.0

8162

051-7898

SYNC_DATE=01/31/2008

IMVP6_BOOT1

DIDT=TRUE

=PP5V_S0_CPU_IMVP

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PPVIN_S5_IMVP6_VIN

DIDT=TRUE

IMVP6_BOOT2

IMVP6_PHASE1

DIDT=TRUE

IMVP6_UGATE1

DIDT=TRUE

IMVP6_LGATE1

IMVP6_VSUM IMVP6_OCSET

IMVP6_ISEN2

DIDT=TRUE

IMVP6_LGATE2

DIDT=TRUE

IMVP6_PHASE2

DIDT=TRUE

IMVP6_UGATE2

IMVP6_ISEN1

MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PP5V_S0_IMVP6_VDD

MIN_LINE_WIDTH=0.25 MM

=PPVIN_S5_CPU_IMVP

VR_PWRGOOD_DELAY

IMVP6_BOOT2_RC

DIDT=TRUE

IMVP6_DROOP

0.20 MM0.25 MM

IMVP6_VO

0.20 MM0.50 MM

GND_IMVP6_SGND

PM_DPRSLPVR

IMVP6_NTC_R

=PPVIN_S5_CPU_IMVP

GND_IMVP6_SGND

=PPVCORE_S0_CPU_REG

IMVP6_SOFT

0.25 MM 0.20 MM

0.25 MM

IMVP6_DFB

0.20 MM

0.20 MM0.25 MM

IMVP6_DROOP

IMVP6_VSEN

0.25 MM 0.25 MM

0.25 MM0.25 MM

IMVP6_RTN

0.25 MM 0.25 MM

IMVP6_VW

0.25 MM0.25 MM

IMVP6_ISEN2

IMVP6_PHASE1

1.5 MM

0.25 MM

IMVP6_COMP_RC

0.25 MM 0.25 MM

IMVP6_UGATE2

0.25 MM0.25 MM

IMVP6_LGATE2

0.25 MM

IMVP6_OCSET

0.20 MM

0.25 MM 0.25 MM

IMVP6_BOOT2

0.20 MM

IMVP6_FB2

0.25 MM

IMVP6_COMP

0.25 MM 0.20 MM

IMVP6_VO_R

CPU_PROCHOT_L

CPU_VCCSENSE_P

IMVP6_UGATE1

1.5 MM

0.25 MM

IMVP6_BOOT1

0.25 MM0.25 MM

IMVP6_RBIAS

0.25 MM 0.20 MM

IMVP6_VDIFF

0.25 MM 0.20 MM

IMVP6_FB

0.25 MM 0.20 MM

IMVP6_VSUM

IMVP6_PHASE2

0.25 MM0.25 MM

IMVP6_VDIFF_RC

IMVP6_ISEN1

0.25 MM0.25 MM

=PP3V3_S0_IMVP

CPU_VCCSENSE_N

IMVP6_LGATE1

0.25 MM

1.5 MM

IMVP6_IMON

IMVP_DPRSLPVR

IMVP6_SOFT

IMVP6_VDIFF

PP3V3_S0_IMVP6_3V3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

CPU_VID<6>

CPU_VID<2>

CPU_VID<3>

CPU_VID<1>

IMVP6_VO

IMVP6_DFB

IMVP6_VSEN

IMVP6_RTN

CPU_PSI_L

IMVP_VR_ON

IMVP6_NTC

IMVP6_VR_TT

IMVP6_RBIAS

IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW

VOLTAGE=0V

GND_IMVP6_SGND

CPU_DPRSTP_L

CPU_VID<4>

CPU_VID<5>

CPU_VID<0>

DIDT=TRUE

IMVP6_BOOT1_RC

62A8

7D5

62A6

62A8

62A4

62A6

62A8

62D8 62D4

7B1

24A8

62A4

62C6

62C8 62B7

73B3 20C7

62D4 62C3

7B1

62D8 62C3

7B1

62B7 62A4

7D8

62C7

62B6

62C6

62B5

62B6

62B7

62C6

62B7

73C3 41D4 13B6

9C5

73A3 10B5

62C6

62C7

62B7

62C6

7C5

73A3 10A5

62C6

45B3

73B3

62A4

10B6 73A3

62A4

62A4 62A4

9B2

40D8

62A4

62C8

62A4

9B2

13A3 73B3

10B6 73A3

IN

OUT

OCSET

ICOMP

RBIAS

LGATE

THRM_PAD

FDE

IMON

PVCC

PHASE

UGATE

BOOT

VDD

VSS

VIN

VO

VSEN

VDIFF

FB

COMP

VW

SOFT

PGND

ISN

ISP

RTN

PGOOD

AF_EN

VR_ON

OFFSET1

OFFSET0

VID2

VID1

VID0

G

D

S

D

S

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

111 +0.70V

011 +0.90V

000 +1.05V

(MCPCORES0_VSEN)

CONNECT SENSE LINES TO CLOSEST

(MCPCORES0_VDIFF)

PLACE XW NEAR THE MCP,

OF MCP

MCPCORE AND GND BALL

110 +0.75V

f = 300 kHz

(Q7560 Limit)

010 +0.95V

(MCPCORES0_COMP)

(MCPCORES0_VW)

001 +1.00V

(MCPCORES0_ICOMP)

VID<2:0> MCP TARGET

(MCPCORES0_RTN)

(MCPCORES0_LGATE)

(MCPCORES0_UGATE)

(MCPCORES0_ISN)

(MCPCORES0_VO)

(MCPCORES0_PHASE)

101 +0.80V

MCP VCORE POWER SUPPLY

(MCPCORES0_FB)

100 +0.85V

MAX CURRENT: 13A

21

XW7563

OMIT

SM

21

XW7562

SM

OMIT

20A3 20C3

21

R7568

402

1%

MF-LF

1/16W

20

1/16W

21

R7566

402

MF-LF

1%

20

2

1

50V

10% X7R

402

0.001UF

C7570

1% 1/16W

2

R7563

402

MF-LF

100

1

402

20.0K

R7582

2

1

MF-LF

1% 1/16W

PLACEMENT_NOTE=PLACE R7582 ON THE BOTTOM SIDE

402

2

1

20.0K

MF-LF

1% 1/16W

PLACEMENT_NOTE=PLACE R7583 ON THE BOTTOM SIDE

R7583

21

R7592

0

MF-LF

5%

402

1/16W

MF-LF

PLACEMENT_NOTE=PLACE R7580 ON THE BOTTOM SIDE

20.0K

NOSTUFF

2

1

R7580

402

1% 1/16W

20.0K

2

1

1/16W 402

1%

R7581

NOSTUFF

PLACEMENT_NOTE=PLACE R7581 ON THE BOTTOM SIDE

MF-LF

1

R7591

0

MF-LF

402

5%

1/16W

2

1

16V

0.1UF

X7R-CERM

402

10%

C7576

150K

R7572

2

1

MF-LF 402

1% 1/16W

66C1

66A5

21

402

1/16W

5%

0

R7590

MF-LF

2

1

R7561

MF-LF 402

5% 1/16W

1K

21

11

QFN

30

17

5

6

32

10

13

3

23 24

20

31

22

1

9

2

33

16

7

25 26 27

14

8

15

4

19

ISL6263D

28

18

U7500

29

12

21

XW7561

SM

MF-LF

2

1

1%

402

R7575

47.0K

1/16W

1%

R7573

1/16W

10K

MF-LF 402

1

2

1%

402

MF-LF

1/16W

1

R7569

11.3K

R7565

21

0

603

MF-LF

1/10W

5%

21

603

0.22UF

CERM-X7R

C7564

5%

10V

2

1

C7550

X5R 402

16V

10%

1UF

1

2.2

2

603

MF-LF

5%

1/10W

R7560

16V X5R

2

1

1UF

402

10%

C7562

21

R7578

100

402

1% 1/16W MF-LF

21

R7579

2.21K

MF-LF

402

1%

1/16W

21

R7577

133K

1%

1/16W

402

MF-LF

21

C7580

68PF

CERM

402-1

5%

50V

21

C7581

560PF

CERM

402

10% 50V

2

1

R7571

MF-LF 402

1/16W

100

1%

21

C7582

560PF

CERM

402

10% 50V

2

1

C7579

0.001UF

X7R 402

50V

10%

2

1

6.98K

MF-LF 402

1% 1/16W

R7576

MF-LF

5%

2

603

1

1/10W

R7589

NO STUFF

X7R

NO STUFF

0.001UF

50V

C7589

2

10%

1

402

10UF

X5R

4V

2

1

20%

C7566

10% 50V X7R

1

402

2

1

603

10UF

X5R

4V

C7567

20%

25V 603-1

1UF

1

C7561

10% X5R

2

X7R

10%

C7563

0.001UF

1

402

50V

2

1

R7500

1%

100

1/16W MF-LF

402

2

C7573

2

1

50V

5%

47PF

CERM

402

2

1

C7575

50V

5% CERM

47PF

402

21

1/16W

402

MF-LF

5%

R7593

0

20%

CASE-D2E-SM

16V

1

2

68UF

CRITICAL

C7560

1

2

CASE-D2E-SM

POLY-TANT

C7571

16V

20%

68UF

CRITICAL

12

4

MF-1

1W

1%

0612

3

0.001

CRITICAL

4

POWER33-SM

3

5

FDMC8676

Q7560

21

4

MICROFET3X3

321

5

Q7565

CRITICAL

FDMC8678S

L7560

0.82UH-16A

CRITICAL

SPM6550T-COMBO

SYNC_MASTER=K19_MLB

051-7898

4.7.0

8163

SYNC_DATE=12/10/2008

MCP CORE REGULATOR

MCPCORE_SNUBBER

0.2 MM

0.25 MM

DIDT=TRUE

MCPCORES0_BOOT_R

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

MCPCORES0_UGATE

=PP5V_S0_MCPREG

MCPCORES0_PGOOD

=MCPCORES0_EN

MCPCORES0_IMON

MCPCORES0_RSEN_P

MCPCORES0_COMP_C

MCPCORES0_VDIF_C

MCP_VID<0>

MCP_VID<1>

MCPCORES0_RSEN_N

MCPCORES0_IMON_R

PPMCPCORE_S0_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM VOLTAGE=1V

5V_S0_MCPREG_VIN

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

=PPMCPCORE_S0_REG

MCP_VID<2>

MCPCORES0_ISP_R

MCP_VID0_R

=PPVIN_S0_MCPCORE

MCPCORES0_SOFT

MCPCORES0_FB

MCPCORES0_COMP

MCPCORES0_VW

MCPCORES0_VSEN

MCPCORES0_FDE

MCPCORES0_RTN

MCPCORES0_RBIAS

GND_MCPCORES0_AGND

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V MIN_NECK_WIDTH=0.2 MM

MCPCORES0_ICOMP

MCPCORES0_OS0

MCP_VID1_R

MCPCORES0_ISP MCPCORES0_ISN

MCPCORES0_OCSET

MCPCORES0_VO

MCPCORES0_LGATE

MIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCHNODE

MIN_LINE_WIDTH=0.5 MM

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MCPCORES0_PHASE

DIDT=TRUE

MCPCORES0_BOOT

0.25 MM

0.2 MM

MCP_VID2_R

MCPCORES0_OS1

=PPMCPCORE_S0_REG

MCPCORES0_VDIFF

R7525

0.001UF

C7569

603

CRITICAL

270UF

C7565

1

2

TANT

2V

20%

CASE-B4-SM

CRITICAL

20% 2V

270UF

C7568

1

2

TANT CASE-B4-SM

=PPMCPCORE_S0_REG

POLY-TANT

7D5

45D8

7C8

63C1 63C7

7C1

7C8

63B8 63C1

7C8

63B8 63C7

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

IN

OUT

Q1

Q2

SW

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

VOUT = 1.062V

F = 320 KHZ

8A max output

<Ra>

Vout = 0.75V * (1 + Ra / Rb)

CPUVTT POWER SUPPLY

<Rb>

(CPUVTTS0_VFB)

ROUTING NOTE:

(GND)

ROUTING NOTE:

(=PPCPUVTT_S0_REG)

Place XW7601 by C7660.

Place XW7600 between Pin 7 and Pin 15 of U7600.

C7665

1

20%

603

6.3V

2

10UF

X5R

PLACEMENT_NOTE=Place XW7665 next to L7620

2

1

SM

XW7665

NO STUFF

CERM

50V

5%

100PF

2

1

C7670

402

8.45K

R7670

MF-LF

1% 1/16W

2

1

402

1%

402

1/16W

20.0K

2

1

R7671

MF-LF

1/16W

R7603

MF-LF

1

2

1%

402

200K

X5R

1

603-1

10% 25V

2

C7695

1UF

1

2

CASED2E-SM

POLY-TANT

C7630

CRITICAL

20% 16V

33UF

X7R

0.1UF

10% 50V

603-1

1

C7603

2

4.7UF

10%

2

1

C7604

603

X5R-CERM

6.3V

15

TPS51117RGY_QFN14

QFN

3

5

14

4

10

11

2

6

8

12

7

1

9

13

U7600

CRITICAL

XW7600

SM

21

1UF

X5R

10V

402-1

1

2

C7601

10%

66C1

66A5

2

1/16W

1%

MF-LF 402

R7604

1

8.87K

1/16W

402

MF-LF

1%

301

21

R7601

CERM

50V

0.001UF

C7696

402

1

2

20%

1

CERM

0.001UF

50V

20%

2

C7661

402

CRITICAL

L7620

2.2UH-8.0A

PCMB065T-SM

12

SM

2

1

XW7601

CRITICAL

C7660

1

2

330UF

20%

2.5V TANT

CASE-B2-SM

65

CRITICAL

Q7620

MLP

1

249

7

8

10

3

FDMS9600S

SYNC_DATE=02/08/2008

SYNC_MASTER=RAYMOND

4.7.0

051-7898

64 81

CPU VTT(1.05V) SUPPLY

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

CPUVTTS0_VBST

MIN_LINE_WIDTH=0.6MM

CPUVTTS0_TON

=PP5V_S0_CPUVTTS0

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

GND_CPUVTTS0_SGND

CPUVTTS0_VFB

CPUVTTS0_VSNS

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm

PP5V_S0_CPUVTTS0_V5FILT

=CPUVTTS0_EN

CPUVTTS0_TRIP

CPUVTTS0_PGOOD

=PPCPUVTT_S0_REG

=PPVIN_S0_CPUVTTS0

DIDT=TRUE

CPUVTTS0_DRVL

MIN_NECK_WIDTH=0.2MM

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

CPUVTTS0_LL

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

CPUVTTS0_VOUT

DIDT=TRUE

CPUVTTS0_DRVH

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

7D5

7D8

7C1

VI

SW

EN

FB

GND

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

SS

IN0 IN1

THRML_PAD

EN FB

BIAS

OUT0 OUT1

GND

PG

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

<Rb>

VOUT = 0.8V * (1 + RA / RB)

<Ra>

MAX CURRENT = 0.5A

Vout = 1.05V

MAX CURRENT = 0.8A

VOUT = 0.8V * (1 + RA / RB)

MCP 1.05V S5 (AUXC) SUPPLY

MAX CURRENT = 200MA

FREQ = 1.6MHZ

1.8V S0 SWITCHER

1.05V S0 PLL LDO

<Ra>

Vout = 1.05V

<Rb>

12

10UH-0.55A-330MOHM

PCAA031B-SM

20%

1

603

2

C7762

10uF

X5R

6.3V

10uF

20%

X5R

6.3V 2

1

603

C7760

3

SOT23-5

5

4

1

2

TPS62202

U7760

CRITICAL

C7750

6.3V

20%

2

1

CRITICAL

22UF

805

CERM

2

1

MF-LF 402

1/16W

2

1

806K

5%

50V

1

2

CERM

C7776

1V05S5_SW

12

66D6

ISL8009B

DFN

CRITICAL

9

4

3

5

8

1

U7750

7

6

2

12

0

R7744

1/16W

LDO_YES

MF-LF

402

5%

MF-LF

21

R7745

0

5%

1/16W

402

LDO_NO

C7742

4.7UF

20%

1

2

402

4V X5R

LDO_YES

C7740

1

2

1UF

10%

6.3V 402

CERM

LDO_YES

12

402

1/16W

100

LDO_YES

5%

MF-LF

LDO_YES

1

2

CERM

1UF

10%

6.3V 402

C7741

SON

U7740

11

5

6

19

73

10

8

4

0.0022UF

1

2

10% 50V

CERM

402

NOSTUFF

C7743

R7746

1.37K

1%

402

1/16W

MF-LF

LDO_YES

R7747

1%

402

LDO_YES

4.42K

1/16W

MF-LF

SYNC_DATE=01/23/2008

SYNC_MASTER=RAYMOND

MISC POWER SUPPLIES

8165

051-7898

4.7.0

=PP3V3_S0_MCP_PLL_VLDO

PP3V3_S0_MCP_PLL_VLDO_BIAS

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0_MCP_PLL_UF_LDO

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

=PP1V8_S0_REG

=PP3V3_S0_P1V8S0

TP_P1V05S0_LDO_PGOOD

=PP1V5_S0_MCP_PLL_VLDO

=PP3V3_S5_P1V05S5

DIDT=TRUE

P1V05_S5_PGOOD

=P1V05_S5_EN

=P1V8S0_EN

DIDT=TRUE

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_PLL_UF_R

1V05S5_FB

P1V05S0_LDO_FB

CRITICAL

47PF

R7743

P1V8S0_SW

L7760

2

TPS74701

LDO_YES

CRITICAL

1%

=PP1V05_S5_REG

255K

L7770

MF-LF 402

CRITICAL

1%

C7771

20%

47UF

6.3V

402

CRITICAL

P1V05S0_LDO_SS

CERM-X5R 0805

1

2

R7781

1/16W

R7780

IHLP1616BZ-SM

2.2UH-3.25A

7B5

7B8

7B5

7B6

7B4

7A3

66B1

66C1

7B8

22C4

7C7

OUT

D

GS

D

GS

OUT

SENSE

CT

VDD

GND

RESET*

MR*

IN

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

OUT

IN

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

353S2310

Battery Off (G3Hot)

State

00

10

0

Unused PGOOD signal

VOLTAGE MONITOR

Soft-Off (S5)

Sleep (S3)

Run (S0)

11

1

PM_SLP_S3_L

0

1

SMC_PM_G2_ENABLE

1.5V S0 AND 1.05V S0 ENABLE

MCPDDR, CPUVTT,MCPCORES0 ENABLE

3.3V_S0, 1.8V_S0 ENABLE

(S0PGOOD_PWROK)

(PM_SLP_S3_L)

PM_SLP_S4_L

Power Control Signals

S3 ENABLE

3.3V 1.05V S5 ENABLE

(PM_S4_STATE_L)

TPS3808 MR* HAS INTERNAL PULLUP

NC

V2MON THRESHOLD IS 2.866V

V3MON THRESHOLD IS 0.6V V4MON THRESHOLD IS 0.6V

OTHER S0 RAILS PGOOD

60A7

1

2

3

Q7813

SSM3K15FV

SOD-VESM-HF

2

1

3

Q7800

SSM3K15FV

SOD-VESM-HF

21

R7802

MF-LF

402

5%

100K

1/16W

24B8 40D8

1

5%

MF-LF

68K

402

1/16W

2

R7813

2

1

C7813

NO STUFF

10V

402

0.068UF

CERM

10%

2

1

C7802

0.068UF

402

10V

CERM

NO STUFF

10%

5.1K

21

R7801

MF-LF

5%

402

1/16W

65A8

21

R7812

1/16W MF-LF

5%

402

0

21

C7812

CERM-X5R

6.3V

402

0.47UF

10%

NO STUFF

1

R7840

MF-LF

5%

100K

2

402

1/16W

6

51

3

2

4

SOT23-6

U7840

TPS3808G33DBVRG4

2

1

C7840

402

20%

CERM

10V

0.1uF

2

1

C7841

402

50V

CERM

20%

0.001UF

2

1

C7801

402

6.3V

10%

0.47UF

CERM-X5R

60A2

0.1uF

C7870

10V

20%

1

2

CERM

402

60A5

38B7

21

R7859

MF-LF

1/16W

5%

402

100

67C8

ISL88042IRTEZ

U7870

1

7

489

3 5 6

TDFN

2

21

R7884

5.1K

5% 1/16W MF-LF

402

0.47UF

6.3V

402

2

1

C7884

10%

CERM-X5R

67B8

1%

MF-LF

402

1/16W

1

2

10K

R7870

1%

20.0K

MF-LF

1/16W

2

1

402

R7871

67A8

2

1

R7800

100K

1/16W

402

MF-LF

5%

6C3

40D5 60C5

6C3

20C3 40C5 41A2

21

R7811

402

5.1K

5%

MF-LF

1/16W

2

C7810

6.3V

10%

0.47UF

402

CERM-X5R

1

61C8

44B7

MF-LF

402

100K

1/16W

R7810

1

2

5%

65C7

2

1

R7883

10K

5%

1/16W MF-LF

402

2

1

R7882

5% 1/16W MF-LF

0

402

R7881

33K

1/16W

5%

MF-LF

402

1

22

1

22K

MF-LF

1/16W

5%

402

R7880

2

1

C7883

402

CERM-X5R

10%

6.3V

0.47UF

2

1

C7882

6.3V

NO STUFF

0.47UF

CERM-X5R

10%

402

2

1

C7881

402

6.3V

10%

0.47UF

CERM-X5R

2

1

C7880

402

0.47UF

CERM-X5R

6.3V

10%

64B7

6C3

20C3 32B7 35A5 40C5 70D8

2

1

R7879

402

100K

MF-LF

5%

1/16W

63C6

10K

2

1

1/16W

402

5%

R7820

MF-LF

63C6

64B7

67C4

SYNC_DATE=12/11/2008

SYNC_MASTER=YUAN.MA

POWER SEQUENCING

051-7898

81

4.7.0

66

S0PGOOD_PWROK

=PP5V_S0_VMON

PM_SLP_S3_L_INVERT

MAKE_BASE=TRUE

=PP3V3_S0_VMON

MAKE_BASE=TRUE

P3V3S3_EN

RSMRST_PWRGD

DDRREG_PGOOD

=PP3V3_S5_PWRCTL

CT

=P3V3S5_EN_L

MAKE_BASE=TRUE

PM_SLP_S4_L

MAKE_BASE=TRUE

PM_G2_P3V3S5_EN_L

SMC_PM_G2_EN

PM_SLP_S3_L

MAKE_BASE=TRUE

PM_SLP_S3_L_BUF

CPUVTTS0_EN

MAKE_BASE=TRUE

MCPDDR_EN

=PP3V42_G3H_PWRCTL

=P5VS0_EN

=PBUSVSENS_EN

=P1V8S0_EN

MAKE_BASE=TRUE

ALL_SYS_PWRGD

CPUVTTS0_PGOOD

P1V05_S5_PGOOD

MAKE_BASE=TRUE

PM_G2_P1V05S5_EN

=CPUVTTS0_EN

=MCPDDR_EN

=MCPCORES0_EN

=PP3V42_G3H_PWRCTL

=P5VS3_EN_L

=PP3V42_G3H_PWRCTL

MAKE_BASE=TRUE

DDRREG_EN

=USB_PWR_EN

=DDRREG_EN

=P1V05_S5_EN

=P3V3S3_EN

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

=PP1V05_S0_VMON

=PP1V5_S0_VMON

PP3V3_VMON_VDD

P5V3V3_PGOOD

=PP3V3_S0_PWRCTL

MCPCORES0_PGOOD

MCPCORES0_EN

MAKE_BASE=TRUE

=P3V3S0_EN

P3V3S0_EN

MAKE_BASE=TRUE

P1V8S0_EN

MAKE_BASE=TRUE

7D5

7C5

40D8

61B3

7A3

7D1

66C8 66D8

65A8

7D1

66B3 66C8

7D1

66B3 66D8

7D7

7B6

7C5

IN

D

SG

D

SG

IN

D

GS

D

GS

SGD

IN

D

SG

D

SG

D

S

KELVIN

NC

GND

SENSE

G

OUT

D

GS

IN

S

G

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

376S0778

13.5 MOHM @4.5VRDS(ON)

TPCP8102

3.3V S3 FET

LOADING

5.0V S0 FET

3.3V S0 FET

CHANNEL

RDS(ON)

LOADING

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.

BEFORE RAIL IS TURNED OFF, AND REMAINS LOW

WILL EXIT SELF-REFRESH PREMATURELY.

LOW THROUGH VTT TERMINATION RESISTORS.

ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS

UNTIL AFTER RAIL TURNS BACK ON OR DIMMS

MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP

.

1.7 A (EDP)

5.0V S0 FET

CHANNEL

MOSFET

P-TYPE

26 MOHM @4.5V

P-TYPE

FDC606P

1.431 A (EDP)

3.3V S0 FET

MOSFET

1.5V S0 FET

Rome SenseFET

6.3 mOHM @4.5V VGS

5A (EDP)

N-TYPE

LOADING

MOSFET

RDS(ON)

CHANNEL

1.5V S0 FET

(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)

.

0.182 A (EDP)

48 mOhm @4.5V

P-TYPE

FDC638P

3.3V S3 FET

RDS(ON)

CHANNEL

MOSFET

LOADING

CKT FROM T18

81mW max power

90mA max load @ 0.9V

IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW

MCP79 DDRVTT FET

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

SM

FDC638P_G

CRITICAL

Q7910

1

2

5

6

3

4

0.033UF

16V

X5R

10%

402

C7911

1

2

MF-LF

47K

5%

1/16W

402

R7910

12

5%

MF-LF

1/16W

10K

402

R7912

1

2

C7930

16V

10%

CERM

402

0.01UF

12

16V

X5R

402

10%

0.033UF

C7931

1

2

5%

47K

402

MF-LF

1/16W

R7930

12

5%

1/16W

MF-LF

100K

402

R7932

1

2

66B6

66C1

SSM6N15FEAPE

SOT563

Q7975

6

2

1

NO STUFF

0.001UF

402

20% 50V

CERM

C7976

1

2

MF-LF

603

10

5%

1/10W

R7975

12

100K

MF-LF

402

1/16W

5%

R7976

1

2

SSM6N15FEAPE

SOT563

Q7975

3

5

4

24C1 61C8

SSM3K15FV

SOD-VESM-HF

Q7903

3

1

2

SSM3K15FV

Q7905

3

1

2

SOD-VESM-HF

CRITICAL

Q7930

3

FDC606P_G

SOT-6

4

1 2 5 6

66C1

SSM6N15FEAPE

SOT563

Q7971

3

5

4

402

47K

5% 1/16W MF-LF

R7971

12

SSM6N15FEAPE

SOT563

Q7971

6

2

1

CERM 402

0.068UF

10V

10%

C7903

1

2

1/16W

5%

100K

MF-LF

402

R7903

1

2

MF-LF

1/16W

402

10K

5%

R7901

12

CERM

402

20% 10V

0.1UF

C7902

1

2

DFN

ROME

CRITICAL

Q7901

9

4

5

6

8

1237

45C8 45D8

402

0.01UF

16V

CERM

C7940

2

10%

1

0.033UF

C7941

10% 16V

X5R

402

1

2

16V

402

0.01UF

10%

CERM

C7910

12

47K

R7940

5%

1/16W

MF-LF

402

12

5%

402

MF-LF

1/16W

47K

2

1

R7942

SSM3K15FV

SOD-VESM-HF

Q7945

3

1

2

66C1

CRITICAL

Q7940

TPCP8102

7

4

23V1K-SM

865

312

SYNC_MASTER=YUAN.MA

SYNC_DATE=12/11/2008

051-7898

67 81

4.7.0

POWER FETS

=PP5V_S3_P5VS0FET

P5V0S0_EN_L

=P3V3S3_EN

=DDRVTT_EN

=PPVTT_S0_VTTCLAMP

VTTCLAMP_L

VTTCLAMP_EN

=PP5V_S3_VTTCLAMP

P3V3S3_EN_L

=PP3V3_S3_FET

=MCPDDR_EN

MCPDDR_EN_L

P1V5_S0_KELVIN

=PP1V5_S3_P1V5S0FET

=PP1V5_S0_FET

MCPDDR_EN_L_RC

=PP5V_S3_MCPDDRFET

MCPDDR_SS

P1V5_S0_SENSE

=P3V3S0_EN

P3V3S0_EN_L

=P5VS0_EN

=PP3V3_S5_P3V3S3FET

P3V3S3_SS

=PP3V3_S5_P3V3S0FET

P3V3S0_SS

=PP3V3_S0_FET

P5V0S0_SS

=PP5V_S0_FET

7C3

7C7

7C3

7D4

7D3

7C8

7C3

7A3

7D6

SYM_VER-1

NC

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

LVDS CONNECTOR:518S0650

LVDS I/F

LED BKLT I/F

(LVDS DDC POWER)

LCD CONNECTOR

603

X5R

6.3V

20%

10UF

2

1

C9012C9011

1

2

402

16V X5R

10%

0.1UF

120-OHM-0.3A-EMI

0402-LF

CRITICAL

21

L9008

R9014

1

2

402

1K

MF-LF

5% 1/16W

0.001UF

C9015

X7R

10% 50V

402

1

2

C9010

X7R

10% 50V

0.001UF

402

1

2

CRITICAL

AMC2012-SM

90-OHM-200MA

4

32

1

L9080

10%

402

2

1

C9009

16V X5R

0.1UF

F-RT-SM

7

8

18

19

17

22

20

13

12

34

33

32

31

1

2

5

4

3

6

10

9

16

15

14

11

21

23

24

25

26

27

28

29

30

CRITICAL

J9000

20474-030E-11

FPF1009

CRITICAL

5% MF-LF

100K

1/16W 402

2

1

R9009

5%

100K

1/16W 402

2

1

R9008

MF-LF

FERR-120-OHM-1.5A

0402-LF

21

L9004

SYNC_DATE=04/04/2008

LVDS CONNECTOR

SYNC_MASTER=NMARTIN

68 81

4.7.0

051-7898

LVDS_IG_PANEL_PWR

=PP3V3_S5_LCD

=PP3V3_S0_LCD

LED_RETURN_6

LED_RETURN_5

LED_RETURN_4

LED_RETURN_3

LED_RETURN_2

LED_RETURN_1

PPVOUT_S0_LCDBKLT

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<0>

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 MM

VOLTAGE=3.3V

PP3V3_LCDVDD_SW_F

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=3.3V

PP3V3_S0_LCD_F

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_CLK_F_P

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

LVDS_IG_DDC_CLK

LVDS_IG_A_CLK_F_N

LVDS_IG_DDC_DATA

TP_BKL_SYNC

MIN_NECK_WIDTH=0.20 MM

PP3V3_LCDVDD_SW

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

U9000

MFET-2X2

5

4

3

2

1

76

17B6

7A3

7C5

6B7

71A1

6B7

71B1

6B7

71B1

6C7

71B1

6C7

71B1

6C7

71B1

6C3 6C7

71C1

6C7

17B3

75B3

6C7

17B3 75B3

6C7

17B3 75B3

6C7

17B3

75B3

6C3 6C7

6C7

17B3 75B3

6C7

75B3

6C7

17B3

75B3

17B3 75B3

6C7

17B3

6C7

75B3

6C7

17A3

6B7

D

SG

D

GS

BI

D

SG

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

or sinks which do both DP and DVI must depend on the

external adapter for pull ups on DDC lines (since DP

Display Port Interoperability spec says that sources

AUX CH has 100K pull up/down on the MLB)..

1

SSM6N15FEAPE

SOT563

2

6

Q9300

R9301

1/16W

402

MF-LF

5%

33

21

MF-LF

R9300

402

33

1/16W

5%

21

402

16V

10%

21

C9300

X5R

0.1UF

SOD-VESM-HF

SSM3K15FV

2

1

3

Q9301

69D1

17B6 75B3

70C8 75B3

SSM6N15FEAPE

4

3

SOT563

5

Q9300

70B8

17B6

C9301

0.1UF

X5R

16V

10%

21

402

100K

402

MF-LF

1/16W

5%

2

1

R9302

1K

R9306

5%

MF-LF

402

1/16W

1

2

SYNC_DATE=04/18/2008

SYNC_MASTER=AMASON

051-7898

4.7.0

69 81

DISPLAYPORT SUPPORT

DP_IG_AUX_CH_N

DP_IG_DDC_CLK

DP_AUX_CH_C_N

DP_AUX_CH_SW_N

DP_IG_AUX_CH_P

DP_AUX_CH_SW_P

DP_IG_DDC_DATA

DP_AUX_CH_C_P

=MCP_HDMI_TXC_P

=MCP_HDMI_TXD_P<0> =MCP_HDMI_TXD_N<0> =MCP_HDMI_TXD_P<1>

=MCP_HDMI_DDC_CLK

MAKE_BASE=TRUE

DP_HPD

=MCP_HDMI_HPD

DP_ML_P<2>

MAKE_BASE=TRUE

DP_ML_N<2>

MAKE_BASE=TRUE

DP_ML_P<1>

MAKE_BASE=TRUE

DP_ML_N<0>

MAKE_BASE=TRUE

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXD_P<2>

=MCP_HDMI_TXD_N<1>

DP_ML_N<3>

MAKE_BASE=TRUE

DP_ML_P<3>

=MCP_HDMI_TXC_N

DP_ML_P<0>

MAKE_BASE=TRUE

DP_ML_N<1>

MAKE_BASE=TRUE

=MCP_HDMI_DDC_DATA

MAKE_BASE=TRUE

DP_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_DDC_DATA

DDC_CA_DET_LS5V_L

DP_CA_DET

DP_IG_CA_DET

=PP5V_S0_DP_AUX_MUX

75B3

17B6

17A3

70A8 17B6

70C1 75C3

70C1 75C3 17B6

17B6

70C8 75C3

17B6

70C1 75C3

17A3

69C8

7D5

OUT

BI

IN

IO NC NC

IO

GND

OUT

IO NC NC

IO

GND

IO NC NC

IO

GND

IO NC NC

IO

GND

IN

G

D

S

G

D

S

SYM_VER-2

G

D

S

G

D

S

BI

IN

OC*

OUT

EN

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

DP_PWR

ML_LANE2P

AUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P ML_LANE3N

ML_LANE2N

CONFIG1 CONFIG2

BOT ROW TOP ROW

TH PINS SM PINS

SHIELD PINS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Port Power Switch

pull-up to DP_PWR.

100K if DP_HPD is used.

MCP79 requires pull

down HPD input with

(CA) has 100k

to 100K (DPv1.1a).

greater than or equal

DP Source must pull

DP to DVI/HDMI

down HPD input with

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

Cable Adapter

514-0637

69D1

69C4 75B3

75C3 69D1

69D1 75C3

MF-LF

100K

1/16W

5%

402

2

1

R9421

CRITICAL

D9411

3

9

2

10

1

DP_ESD

SLP2510P8

RCLAMP0524P

12

16V

0.1uF

X5R10% 402

C9415

40210% X5R

1

0.1uF

C9414

16V

2

69B7

10% 16V 402

0.1uF

21

X5R

C9411

16V10% 402X5R

0.1uF

21

C9410

1/16W MF-LF

2

1

5%

402

100K

DP_ESD

CRITICAL

D9410

10

9

2

3

1

SLP2510P8

RCLAMP0524P

52

6

4

3

1

SC70-6-1

D9400

RCLAMP0504F

CRITICAL

DP_ESD

3

6

54

SLP2510P8

DP_ESD

7

D9411

CRITICAL

RCLAMP0524P

1M

1/16W

5%

2

1

R9425

MF-LF 402

4

DP_ESD

SLP2510P8

CRITICAL

76

5

3

RCLAMP0524P

16V10%

0.1uF

21

C9417

10% X5R

1

0.1uF

16V10% 402X5R

1

C9413

0.1uF

2

16V 402X5R

21 10%

C9412

75C3

69D1 75C3

21

100K

R9423

402

1/16W MF-LF

2

1

5%

69D1 75C3

4

5

3

Q9440

2N7002DW-X-G

SOT-363

1

2

6

Q9440

2N7002DW-X-G

1/16W

402

MF-LF

2

1

5%

100K

R9443

2

R9442

100K

1/16W

402

5%

1

MF-LF

4

32

FL9401

TCM1210-4SM

12-OHM-100MA

41

2

FL9402

12-OHM-100MA

TCM1210-4SM

3

1

3

4

2

TCM1210-4SM

FL9400

12-OHM-100MA

4

23

TCM1210-4SM

1

12-OHM-100MA

FL9403

1/16W

402

5%

1

MF-LF

R9444

10K

2

R9445

5%

1/16W

402

MF-LF

2

1

10K

3

5

4

SOT-363

2N7002DW-X-G

Q9441

1

2

MF-LF

1/16W

402

5%

1M

R9422

SOT-363

6

2

1

2N7002DW-X-G

Q9441R9446

100K

402

1/16W MF-LF

2

1

5%

20%

6.3V

1

2

603

C9486

X5R-CERM-1

CRITICAL

22UF

69D4 75B3

20C3 66D5 35A5 32B7

6C3

40C5

3

1

2

4

5

17

12

18

19

16

20

11

13

3

5

7

1

14

8

4

22

2

6

15

10

9

DSPLYPRT-M97-1

J9400

CRITICAL

21

F-RT-THSM

SYNC_MASTER=AMASON

051-7898

4.7.0

8170

DisplayPort Connector

SYNC_DATE=06/30/2008

DP_ML_CONN_N<1>

PP3V3_S0_DPPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

DP_ML_C_N<3>

DP_AUX_CH_C_P

DP_ML_C_P<3>

DP_AUX_CH_C_N

=PP3V3_S0_DPCONN

HDMI_CEC

DP_ML_CONN_P<1>

DP_ML_CONN_N<0>

DP_ML_CONN_P<0>

DP_HPD_Q

DP_ML_P<3>

DP_ML_C_N<2>

DP_ML_C_P<2>

DP_ML_C_N<1>

DP_ML_C_P<1>

DP_ML_C_P<0>

DP_ML_C_N<0>

DP_ML_N<0>

DP_ML_CONN_P<2>

DP_ML_CONN_P<3> DP_ML_CONN_N<3>

=PP3V3_S5_DP_PORT_PWR

VOLTAGE=3.3V

PP3V3_S0_DPILIM

DP_ML_CONN_N<2>

DP_CA_DET_Q

DP_CA_DET_L_Q

=PP3V3_S0_DPCONN

DP_CA_DET

DP_HPD_L_Q

DP_ML_N<3>

DP_ML_P<0>

DP_ML_P<1>

DP_ML_N<1>

DP_HPD

D9410

1

TP_DPPWR_OC_L

PM_SLP_S3_L

MIN_NECK_WIDTH=0.20 MM

C9400

402

1

2

6.3V

4.7UF

20%

6.3V

20%

603

C9485

1

2

22UF

C9480

2

6.3V

20%

1

X5R-CERM-1

22UF

C9481

2

1

402

20%

6.3V X5R-CERM

4.7UF

603

U9480

TPS2051B

SOT23

MIN_LINE_WIDTH=0.38 MM

X5R

16V

DP_ML_P<2>

402

DP_ML_N<2>

402

2

C9416

69D1

75C3

0.1uF

R9420

X5R-CERM-1

X5R-CERM

0603

FERR-120-OHM-3A

L9400

CRITICAL

75B3 75C3

75C3

7C5

70B8

75B3

75C3

75B3

7A3

75B3

7C5

70C8

75B3

OUT

NC

ALSI

ALSO

ADR

IF_SEL

PWM

EN

FAULT

THRM

GND_L

GND_SW

OUT6

VIN

VDDIO VLDO

FB

SW

OUT1

OUT2

OUT4

OUT5

OUT7

OUT3SCLK

SDA

GND_S

PAD

NC

IN

D

N-CHANNEL

P-CHANNEL

G

S

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

IF_SEL=0 FOR I2C

* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

*PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.

R9704 SHOULD BE 47K IF RC FILTER IS USED

NEED 2 VIAS

BKL_SWGND HIGH CURRENT

IF_SEL=1 FOR SMBUS

5

10

11

XW9700

BKLT_ENG

PLACEMENT_NOTE=SW9700 PLACE NEAR C9712 C9713

17

BKL_ISEN5

R9719

1

IC,LP8543,WHT LED BKLT CTRLR,QFN24,PROD

BKL_SGND

SM

2

U9701

BKLT_EN

BKL_ISEN6

BKL_ISEN4

BKL_ISEN3

BKL_ISEN2

1

XW9710

CRITICAL

OMIT

=I2C_BKL_1_SCL

=I2C_BKL_1_SDA

PPBUS_S0_LCDBKLT_PWR

BKL_SDA

BKL_SCL

BKL_IF_SEL

BKLT_VLDO_EN_L

PPVIN_BKL

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=6V

MIN_NECK_WIDTH=0.375 MM

VOLTAGE=5V

BKL_VLDO

PPVIN_BKL_R

=PP5V_S0_BKL

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

MIN_NECK_WIDTH=0.20 mm

BKL_ISEN1

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_SWGND

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_3

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm

LVDS_IG_BKL_PWM

=PP3V3_S0_BKL_VDDIO

PPBUS_S0_LCDBKLT_PWR

BKLT_EN_R

BKLT_EN

SWITCH_NODE=TRUE

VOLTAGE=50V

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPBUS_S0_LCDBKLT_PWR_SW

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPVOUT_S0_LCDBKLT

VOLTAGE=50V

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

71

SYNC_MASTER=KIRAN

SYNC_DATE=12/05/2008

LCD BACKLIGHT DRIVER

81

4.7.0

051-7898

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

6

R9717,R9718,R9719,R9720,R9721,R9722

R9700

RES,1/16W,0.1 OHM,1%,0402,SM

1

NO STUFF

1%

100K

R9735

12

402

MF-LF

1/16W

NO STUFF

MF-LF

R9701

402

0

5%

12

NO STUFF

SOT-963

NTUD3127CXXG

Q9701

3

6

2

1

5

4

BKLT_PROD

R9722

12

402

5%

0

MF-LF

1/16W

R9721

BKLT_PROD

1/16W MF-LF

0

5%

402

21

R9720

BKLT_PROD

1/16W MF-LF

0

5%

402

21

BKLT_PROD

1/16W MF-LF

0

5%

402

21

BKLT_PROD

R9718

1/16W MF-LF

0

5%

402

21

R9717

12

0

402

MF-LF

1/16W

5%

BKLT_PROD

402

NO STUFF

R9714

100K

MF-LF

1/16W

5%

2

CERM

50V

5%

C9704

402

1

33PF

NO STUFF

R9704

0

12

5%

1/16W

402

MF-LF

72B7 17B6

5% 1/16W

NO STUFF

R9702

MF-LF

2

402

0

1

1/16W

0

5%

MF-LF

2

R9703

1

402

0.01UF

2

16V

402

CERM

10%

1

5%

402

100K

1/16W MF-LF

R9716

U9701

24

CRITICAL

13

12

21

LLP

6

LP8543SQX

9

1

15

25

7

4

2

20

3

8

22

23

14

18

16

19

SM

2

0.1UF

C9711

402

X5R

10%

1

2

16V

2

X5R 603-1

25V

10%

1

10%

X5R

25V

2

402

NO STUFF

0.1UF

C9723

1

1/16W

R9731

MF-LF

402

1%

2

301K

1/16W MF-LF

2

100K

402

1

1%

R9715

68B3

6C7

68B3

6C7

68B3

6C7

68B3

6B7

R9753

MF-LF

402

21

5%01/16W

68B3

6B7

68B3

6B7

RB160M-40

CRITICAL

2

SOD-123

D9701

1

2

1

1210

10%

2.2UF

X7R

100V

C9797

2

1210

X7R

100V

1

C9799

10%

2.2UF

CERM

2

1206

100V

1

5%

C9796

200PF

22UH-2.5A

CRITICAL

L9701

2

C9713

402

2

1

0.1UF

10%

X5R

25V

CRITICAL

2

805

1

X5R

10UF

25V

10%

2

MF-LF

R9757

402

1/16W

5%

1

0

BKLT_PROD

2

5%

1/16W

402

MF-LF

1

R9700

103S0198

116S0005

C9714

C9712

IHLP2525CZ-SM

1

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

BKL_SWGND

C9710

1UF

BKLT_ENG

353S2670

TP_BKL_FAULT

LVDS_IG_BKL_PWM_RC

43B6

72C3 71C7

71D3

71C2 71B5

7D5

71C5 71B5

71C5 71C2

7B5

72C3 71B7

71B6

68B2

6C7 6C3

OUT

IN

D

SG

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LOADING 0.4 A (EDP)

43 mOhm @4.5V

P-TYPE

FDC638APZ

RDS(ON)

.

MOSFET

CHANNEL

PPBUS S0 LCDBkLT FET

MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS

F9800

12

2AMP-32V

0402-HF

71B7 71C7

1/16W

MF-LF

R9808

301K

1%

402

2

1

147K

1%

MF-LF

1/16W

R9809

402

2

1

16V

10%

X5R

C9802

0.1UF

402

1

2

7C1

CRITICAL

Q9806

FDC638APZ_SBMS001

1 2 5 6

3

4

SSOT6-HF

5%

MF-LF

1/16W

1K

R9841

402

2

1

1K

R9840

5% 1/16W MF-LF 402

2

1

24C1

6

1

2

SOT563

Q9807

SSM6N15FEAPE

Q9807

SSM6N15FEAPE

SOT563

5

4

3

17B6 72B7

LCD Backlight Support

SYNC_MASTER=YITE

SYNC_DATE=06/30/2008

72 81

4.7.0

051-7898

LVDS_IG_BKL_ON

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

=PPBUS_S0_LCDBKLT

BKLT_EN_L

BKLT_PLT_RST_L

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_S0_LCDBKLT_PWR

LVDS_IG_BKL_PWM

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

PPBUS_S0_LCDBKLT_FUSED

PPBUS_S0_LCDBKLT_EN_DIV

PPBUS_S0_LCDBKLT_EN_L

17B6 72C8

17B6 71A7

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

CPU Signal Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

Intel Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MCP FSB COMP Signal Constraints

Some signals require 27.4-ohm single-ended impedance.

FSB Clock Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SR DG recommends at least 25 mils, >50 mils preferred

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

PHYSICAL

FSB 2X

FSB 4X Signal Groups

ELECTRICAL_CONSTRAINT_SET

FSB 1X Signals

SPACING

NET_TYPE

Signals

(See above)

(FSB_CPURST_L)

(CPU_VCCSENSE)

CPU / FSB Net PropertiesFSB (Front-Side Bus) Constraints

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

FSB 4X signals / groups shown in signal table on right. Signals within each 4x group should be matched within 5 ps of strobe.

FSB 2X signals / groups shown in signal table on right.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right.

=2x_DIELECTRIC

* ?

FSB_ADSTB

* ?

FSB_1X =STANDARD

?

FSB_ADDR

*

=STANDARD

=3x_DIELECTRIC

*

FSB_DSTB

?

=2x_DIELECTRIC

?*

FSB_DATA

=3x_DIELECTRIC

?

TOP,BOTTOM

FSB_1X

=3x_DIELECTRIC

?

TOP,BOTTOM

FSB_ADDR

=5x_DIELECTRIC

?

FSB_DSTB

TOP,BOTTOM

=4x_DIELECTRIC

FSB_DATA

?

TOP,BOTTOM

=50_OHM_SE

=STANDARD

=50_OHM_SE=50_OHM_SE

FSB_50S

=STANDARD

*

=50_OHM_SE

=4x_DIELECTRIC

?

FSB_ADSTB

TOP,BOTTOM

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

FSB_DSTB_50S

=50_OHM_SE

=50_OHM_SE =50_OHM_SE =50_OHM_SE

SYNC_DATE=01/04/2008

SYNC_MASTER=T18_MLB

CPU/FSB Constraints

051-7898

4.7.0

8173

=2x_DIELECTRIC

TOP,BOTTOM

?

CPU_AGTL

TOP,BOTTOM

?

CLK_FSB =4x_DIELECTRIC

=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE

CPU_50S

=STANDARD=STANDARD

*

CPU_27P4S

7 MIL 7 MIL

=27P4_OHM_SE=27P4_OHM_SE

*

=27P4_OHM_SE

=STANDARD

* ?

CPU_AGTL

* ?

CPU_8MIL

8 MIL

25 MIL

*

CPU_COMP

?

=2:1_SPACING

?*

CPU_ITP

?*

CPU_GTLREF

25 MIL

?

CPU_VCCSENSE

*

=STANDARD=STANDARD

*

=50_OHM_SE =50_OHM_SE=50_OHM_SE

MCP_50S

=50_OHM_SE

MCP_FSB_COMP

?*

8 MIL

CLK_FSB_100D

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

CLK_FSB

?

=3x_DIELECTRIC

FSB_DATA_GROUP0

FSB_50S

FSB_D_L<15..0>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB0

FSB_DSTB_L_P<0>

FSB_DSTB_50S

FSB_DSTB0

FSB_DSTB

FSB_DSTB_L_N<0>

FSB_50S

FSB_DATA_GROUP1

FSB_D_L<31..16>

FSB_DATA

FSB_50S

FSB_DATA_GROUP1

FSB_DINV_L<1>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB1

FSB_DSTB

FSB_DSTB_L_P<1>

FSB_50S

FSB_DATA_GROUP2

FSB_DINV_L<2>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB_L_P<2>

FSB_DSTB

FSB_DSTB2

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB2

FSB_DSTB_L_N<2>

FSB_50S

FSB_D_L<63..48>

FSB_DATA_GROUP3

FSB_DATA

FSB_50S

FSB_DATA_GROUP3

FSB_DINV_L<3>

FSB_DATA

FSB_DSTB_50S

FSB_DSTB_L_P<3>

FSB_DSTB

FSB_DSTB3

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB3

FSB_DSTB_L_N<3>

FSB_ADDR

FSB_ADDR_GROUP0

FSB_A_L<16..3>

FSB_50S

FSB_ADDR_GROUP0

FSB_REQ_L<4..0>

FSB_ADDR

FSB_50S

FSB_ADDR_GROUP1

FSB_ADDR

FSB_A_L<35..17> FSB_ADSTB_L<1>

FSB_ADSTB1

FSB_ADSTB

FSB_50S

FSB_1X FSB_1X

FSB_ADS_L

FSB_50S

FSB_BREQ0_L

FSB_1X

FSB_50S

FSB_BREQ1_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_BNR_L

FSB_50S

FSB_1X FSB_1X

FSB_BPRI_L

FSB_50S

FSB_1X

FSB_DBSY_L

FSB_1X

FSB_50S

FSB_1X

FSB_DEFER_L

FSB_1X

FSB_50S

FSB_1X

FSB_DRDY_L

FSB_1X

FSB_50S

FSB_1X

FSB_HIT_L

FSB_1X

FSB_50S

FSB_1X FSB_1X

FSB_HITM_L

FSB_50S

FSB_CPURST_L

FSB_1X

FSB_50S

FSB_1X

FSB_RS_L<2..0>

FSB_1X

FSB_50S

FSB_1X

FSB_TRDY_L

FSB_1X

CPU_50S

CPU_BSEL

CPU_BSEL<2..0>

CPU_AGTL

CPU_50S

CPU_FERR_L

CPU_8MIL

CPU_50S

CPU_ASYNC

CPU_IGNNE_L

CPU_AGTL

CPU_50S

CPU_INIT_L

CPU_AGTL

CPU_50S

CPU_ASYNC_R

CPU_INTR

CPU_AGTL

CPU_50S

CPU_ASYNC_R

CPU_NMI

CPU_AGTL

CPU_50S

CPU_PROCHOT_L

CPU_AGTL

CPU_50S

CPU_PWRGD

CPU_AGTL

CPU_50S

CPU_ASYNC

CPU_SMI_L

CPU_AGTL

CPU_50S

CPU_ASYNC

CPU_STPCLK_L

CPU_AGTL

CPU_50S

PM_THRMTRIP_L

CPU_8MIL

CPU_50S

FSB_CPUSLP_L

CPU_AGTL

CPU_50S

CPU_FROM_SB

CPU_DPSLP_L

CPU_AGTL

CPU_50S

CPU_DPRSTP_L

CPU_AGTL

CPU_50S

CPU_ASYNC

FSB_DPWR_L

CPU_AGTL

MCP_FSB_COMPMCP_CPU_COMP

MCP_BCLK_VML_COMP_VDD

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_BCLK_VML_COMP_GND

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_CPU_COMP_VCC

MCP_50S

MCP_FSB_COMPMCP_CPU_COMP

MCP_CPU_COMP_GND

MCP_50S

FSB_CLK_CPU

FSB_CLK_CPU_P

CLK_FSB

CLK_FSB_100D

FSB_CLK_CPU

FSB_CLK_CPU_N

CLK_FSB

CLK_FSB_100D

FSB_CLK_ITP

CLK_FSB

CLK_FSB_100D

FSB_CLK_ITP_P

FSB_CLK_ITP

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP_N

FSB_CLK_MCP

CLK_FSB

CLK_FSB_100D

FSB_CLK_MCP_P

FSB_CLK_MCP

CLK_FSB

CLK_FSB_100D

FSB_CLK_MCP_N

CPU_IERR_L

CPU_50S

CPU_IERR_L

CPU_50S

PM_DPRSLPVR

CPU_AGTL

PM_DPRSLPVR

CPU_50S

CPU_AGTL

IMVP_DPRSLPVR

CPU_GTLREF

CPU_50S

CPU_GTLREF

CPU_COMP

CPU_50S

CPU_COMP<3>

CPU_COMP

CPU_COMP<2>

CPU_27P4S

CPU_COMP

CPU_COMP<1>

CPU_50S

CPU_COMP

CPU_COMP CPU_COMP

CPU_27P4S

CPU_COMP<0>

XDP_TDI CPU_50S CPU_ITP

XDP_TDI

XDP_TDO CPU_50S CPU_ITP

XDP_TDO

XDP_TMS CPU_50S CPU_ITP

XDP_TMS

XDP_TCK CPU_50S CPU_ITP

XDP_TCK

XDP_TRST_L

CPU_50S CPU_ITP

XDP_TRST_L

XDP_BPM_L

CPU_50S

XDP_BPM_L<4..0>

CPU_ITP

XDP_BPM_L5

CPU_50S CPU_ITP

XDP_BPM_L<5> XDP_CPURST_L

CPU_ITPCPU_50S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

IMVP6_VSEN_N

CPU_27P4S

CPU_VCCSENSE

IMVP6_VSEN_P

CPU_50S

IMVP6_VID<6..0>

CPU_8MIL

CPU_VID<6..0>

CPU_50S

CPU_8MIL

FSB_ADSTB

FSB_50S

FSB_ADSTB_L<0>

FSB_ADSTB0

FSB_DSTB_L_N<1>

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB1

FSB_50S

FSB_DATA

FSB_DATA_GROUP2

FSB_D_L<47..32>

CPU_50S

CPU_ASYNC

CPU_A20M_L

CPU_AGTL

FSB_50S

FSB_1X FSB_1X

FSB_LOCK_L

FSB_DATA_GROUP0

FSB_50S

FSB_DINV_L<0>

FSB_DATA

9C4

13D3

9C4

13D6

9C4

13D6

9B4 9C4

13C3 13D3

9B4

13D6

9B4

13D6

9C2

13D6

9C2

13D6

9C2

13D6

9B2 9C2

13B3

9B2

13D6

9B2

13D6

9B2

13D6

9D8

13C6 13D6

9D8

13B6

9C8 9D8

13C6

9C8

13B6

9D6

13B6

9D6

13B6

9D6

13B6

9D6

13B3

9D6

13B6

9D6

13B3

9D6

13B6

9D6

13B6

9D6

13B6

9D6

12C2 13A3

9D6

13A6

9D6

13B6

8B2 9B4

9C8

13B7

9C8

13A3

9D6

13A3

9C8

13A3

9B8

13A3

9C5

13B6 41D4 62C8

9B2

12C7 13A3

9B8

13A3

9C8

13A3

9C6

13B7 41C4

9B2

13A3

9B2

13A3

9B2

13A3 62C7

9B2

13A3

13A6

9B6

13B3

9B6

13B3

12C3 13B3

13A4

9D6

20C7 62D8

62C7

9B4

25B1

9B3

9B6 9C6

12B3

9B6 9C6

12B3

9B6 9C6

12B3

9A6 9C6

12B6

9A6 9C6

12B3

9C6

12C6

9C5

12C6

12C4

10B5 62A5

10A5 62A5

10B6 62C7

9D8

13B6

9B4

13D6

9C2

13B3 13C3

9C8

13A3

9D6

13B6

9C4

13D6

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

Memory Net Properties

DQ signals should be matched within 20 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. All DQS pairs should be matched within 100 ps of clocks. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

Memory Bus Constraints

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Spacing Group Assignments

Need to support MEM_*-style wildcards!

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. A/BA/cmd signals should be matched within 5 ps of CLK pairs.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

MCP MEM COMP Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

DDR3:

DDR2:

MCP_MEM_COMP

8 MIL

* ?

=STANDARD

7 MIL7 MIL

Y

MCP_MEM_COMP

*

=STANDARD =STANDARD

MEM_DQSMEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS

MEM_CMD

*

MEM_CTRL2MEM

MEM_CTRL

MEM_DQS

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

MEM_CTRL2MEM

MEM_CLK

*

MEM_DQS

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

MEM_CLK2MEM

MEM_CLK

*

MEM_CLK

MEM_CTRL

MEM_CLK2MEM

*

MEM_CLK MEM_CLK

MEM_CLK2MEM

*

MEM_2OTHER

MEM_DATA

**

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

MEM_DQS

**

MEM_2OTHER

MEM_CTRL

**

MEM_2OTHER

MEM_CLK

**

MEM_DATA2MEM

MEM_DATA

*

MEM_CMD

MEM_DATA

MEM_DATA2DATA

MEM_DATA

*

MEM_DATA2MEM

MEM_DATA

*

MEM_DQS

MEM_DATA

*

MEM_DATA2MEM

MEM_CTRL

*

MEM_DATA2MEM

MEM_DATA

MEM_CLK

MEM_CMD2MEM

MEM_CMD

*

MEM_DQS

*

MEM_CMD

MEM_CMD2MEM

MEM_DATA

*

MEM_CMD MEM_CMD

MEM_CMD2CMD

*

MEM_CMD

MEM_CMD2MEM

MEM_CTRL

MEM_CMD

*

MEM_CMD2MEM

MEM_CLK

?

=3:1_SPACING

MEM_DQS2MEM

*

25 MIL

MEM_2OTHER

* ?

MEM_DATA2MEM =3:1_SPACING

* ?

MEM_CMD2MEM

* ?

=3:1_SPACING

MEM_DATA2DATA

* ?

=1.5:1_SPACING

MEM_CTRL2MEM

* ?

=2.5:1_SPACING

MEM_CLK2MEM

* ?

=4:1_SPACING

MEM_CTRL2CTRL

=2:1_SPACING

* ?

=1.5:1_SPACING

MEM_CMD2CMD

* ?

MEM_40S_VDD

=40_OHM_SE=40_OHM_SE=40_OHM_SE

=STANDARD

*

=STANDARD

=40_OHM_SE

MEM_40S

=STANDARD

*

=STANDARD

=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

=70_OHM_DIFF=70_OHM_DIFF

*

=70_OHM_DIFF=70_OHM_DIFF

=70_OHM_DIFF

MEM_70D_VDD

=70_OHM_DIFF

=70_OHM_DIFF =70_OHM_DIFF

*

=70_OHM_DIFF =70_OHM_DIFF

MEM_70D

MEM_CMDMEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS

MEM_CLK

*

MEM_DQS2MEM

MEM_DQS

SYNC_DATE=01/04/2008

SYNC_MASTER=T18_MLB

Memory Constraints

74 81

4.7.0

051-7898

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_CKE<3..0>

MEM_CLK

MEM_A_CLK

MEM_A_CLK_P<5..0>

MEM_70D_VDD

MEM_40S_VDD

MEM_A_CNTL

MEM_CTRL

MEM_A_CKE<3..0>

MEM_CLK

MEM_A_CLK

MEM_A_CLK_N<5..0>

MEM_70D_VDD

MEM_40S_VDD

MEM_A_CNTL

MEM_A_ODT<3..0>

MEM_CTRL

MEM_40S_VDD

MEM_A_CNTL

MEM_A_CS_L<3..0>

MEM_CTRL

MEM_40SMEM_A_DQ_BYTE2

MEM_DATA

MEM_A_DM<2>

MEM_40SMEM_A_DQ_BYTE3

MEM_A_DM<3>

MEM_DATA

MEM_40SMEM_A_DQ_BYTE4

MEM_DATA

MEM_A_DM<4>

MEM_40SMEM_A_DQ_BYTE5

MEM_DATA

MEM_A_DM<5>

MEM_40SMEM_A_DQ_BYTE6

MEM_A_DM<6>

MEM_DATA

MEM_70D MEM_DQS

MEM_A_DQS_P<3>

MEM_A_DQS3

MEM_40SMEM_A_DQ_BYTE1

MEM_A_DM<1>

MEM_DATA

MEM_70D MEM_DQS

MEM_A_DQS_N<0>

MEM_A_DQS0

MEM_70D MEM_DQS

MEM_A_DQS_N<1>

MEM_A_DQS1

MEM_DQS

MEM_A_DQS1

MEM_A_DQS_P<1>

MEM_70D

MEM_70D MEM_DQS

MEM_A_DQS_P<2>

MEM_A_DQS2

MEM_DQS

MEM_A_DQS_N<2>

MEM_A_DQS2

MEM_70D

MEM_70D MEM_DQS

MEM_A_DQS_P<4>

MEM_A_DQS4

MEM_70D MEM_DQS

MEM_A_DQS_N<3>

MEM_A_DQS3

MEM_70D MEM_DQS

MEM_A_DQS_N<5>

MEM_A_DQS5

MEM_DQS

MEM_A_DQS_N<4>

MEM_A_DQS4

MEM_70D

MEM_DQS

MEM_A_DQS_P<6>

MEM_A_DQS6

MEM_70D

MEM_DQS

MEM_A_DQS_N<7>

MEM_A_DQS7

MEM_70D

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_A_BA<2..0>

MEM_40SMEM_A_DQ_BYTE0

MEM_A_DM<0>

MEM_DATA

MEM_40S

MEM_A_DQ<7..0>

MEM_A_DQ_BYTE0

MEM_DATA

MEM_40S

MEM_A_DQ<55..48>

MEM_A_DQ_BYTE6

MEM_DATA

MEM_40S

MEM_DATA

MEM_A_DQ<63..56>

MEM_A_DQ_BYTE7

MEM_40S_VDD

MEM_A_CMD

MEM_CMD

MEM_A_CAS_L

MEM_40SMEM_A_DQ_BYTE3

MEM_A_DQ<31..24>

MEM_DATA

MEM_40S_VDD

MEM_A_WE_L

MEM_A_CMD

MEM_CMD

MEM_40S

MEM_DATA

MEM_A_DQ<23..16>

MEM_A_DQ_BYTE2

MEM_40S

MEM_A_DQ<15..8>

MEM_A_DQ_BYTE1

MEM_DATA

MEM_40S_VDD

MEM_CMD

MEM_A_RAS_L

MEM_A_CMD

MEM_40SMEM_A_DQ_BYTE4

MEM_DATA

MEM_A_DQ<39..32>

MEM_40SMEM_A_DQ_BYTE5

MEM_DATA

MEM_A_DQ<47..40>

MEM_DATA

MEM_40S

MEM_B_DQ<47..40>

MEM_B_DQ_BYTE5

MEM_DATA

MEM_B_DQ<39..32>

MEM_40SMEM_B_DQ_BYTE4

MEM_DATA

MEM_40S

MEM_B_DQ<15..8>

MEM_B_DQ_BYTE1

MEM_DATA

MEM_40S

MEM_B_DQ<23..16>

MEM_B_DQ_BYTE2

MEM_40S_VDD

MEM_CMD

MEM_B_WE_L

MEM_B_CMD

MEM_DATA

MEM_40S

MEM_B_DQ<31..24>

MEM_B_DQ_BYTE3

MEM_DATA

MEM_40S

MEM_B_DQ<63..56>

MEM_B_DQ_BYTE7

MEM_DATA

MEM_40S

MEM_B_DQ<55..48>

MEM_B_DQ_BYTE6

MEM_DATA

MEM_40S

MEM_B_DQ<7..0>

MEM_B_DQ_BYTE0

MEM_DATA

MEM_40S

MEM_B_DM<0>

MEM_B_DQ_BYTE0

MEM_40S_VDD

MEM_CMD

MEM_B_BA<2..0>

MEM_B_CMD

MEM_DQSMEM_70D

MEM_B_DQS_N<6>

MEM_B_DQS6

MEM_DQSMEM_70D

MEM_B_DQS_P<7>

MEM_B_DQS7

MEM_DATA

MEM_40S

MEM_B_DM<7>

MEM_B_DQ_BYTE7

MEM_DQSMEM_70D

MEM_B_DQS_P<6>

MEM_B_DQS6

MEM_DQSMEM_70D

MEM_B_DQS_P<5>

MEM_B_DQS5

MEM_DQS

MEM_B_DQS_N<4>

MEM_70D

MEM_B_DQS4

MEM_DQSMEM_70D

MEM_B_DQS_N<5>

MEM_B_DQS5

MEM_DQSMEM_70D

MEM_B_DQS_N<3>

MEM_B_DQS3

MEM_DQSMEM_70D

MEM_B_DQS_P<4>

MEM_B_DQS4

MEM_DQSMEM_70D

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_DQSMEM_70D

MEM_B_DQS_P<2>

MEM_B_DQS2

MEM_DQSMEM_70D

MEM_B_DQS_P<1>

MEM_B_DQS1

MEM_DQSMEM_70D

MEM_B_DQS_N<1>

MEM_B_DQS1

MEM_DQSMEM_70D

MEM_B_DQS_N<0>

MEM_B_DQS0

MEM_DQSMEM_70D

MEM_B_DQS_P<0>

MEM_B_DQS0

MEM_DQSMEM_70D

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_DATA

MEM_40S

MEM_B_DM<6>

MEM_B_DQ_BYTE6

MEM_DATA

MEM_40S

MEM_B_DM<5>

MEM_B_DQ_BYTE5

MEM_DATA

MEM_40S

MEM_B_DM<3>

MEM_B_DQ_BYTE3

MEM_DQSMEM_70D

MEM_B_DQS_N<7>

MEM_B_DQS7

MEM_DATA

MEM_40S

MEM_B_DM<4>

MEM_B_DQ_BYTE4

MEM_DATA

MEM_40S

MEM_B_DM<2>

MEM_B_DQ_BYTE2

MEM_DATA

MEM_40S

MEM_B_DM<1>

MEM_B_DQ_BYTE1

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_ODT<3..0>

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_B_CS_L<3..0>

MEM_B_CLK

MEM_B_CLK_N<5..0>

MEM_CLK

MEM_70D_VDD

MEM_B_CLK

MEM_CLK

MEM_B_CLK_P<5..0>

MEM_70D_VDD

MCP_MEM_COMP_VDD

MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MCP_MEM_COMP_GND

MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

MEM_70D MEM_DQS

MEM_A_DQS_P<5>

MEM_A_DQS5

MEM_70D MEM_DQS

MEM_A_DQS_P<7>

MEM_A_DQS7

MEM_40S_VDD

MEM_CMD

MEM_B_CAS_L

MEM_B_CMD

MEM_40S_VDD

MEM_CMD

MEM_B_RAS_L

MEM_B_CMD

MEM_40S_VDD

MEM_B_A<14..0>

MEM_CMD

MEM_B_CMD

MEM_40S_VDD

MEM_A_A<14..0>

MEM_CMD

MEM_A_CMD

MEM_40SMEM_A_DQ_BYTE7

MEM_A_DM<7>

MEM_DATA

MEM_A_DQS_P<0>

MEM_70D MEM_DQS

MEM_A_DQS0

MEM_DQS

MEM_A_DQS_N<6>

MEM_A_DQS6

MEM_70D

14A1 27D5 27D7

14B5 26C5 26C7

14A5 26D5 26D7

14B5 26C5 26C7

14B5 26C5

14B5 26C5 26C7

14B7 26B4

14B7 26C2

14B7 26B5

14B7 26B7

14B7 26B5

14D5 26C4

14A7 26C2

14D5 26D2

14D5 26C4

14D5 26B2

14D5 26C2

14D5 26B7

14D5 26C4

14D5 26B5

14D5 26B7

14D5 26A5

14C5 26C5 26C7

14A7 26C4

14B7 26C2 26C4 26D2 26D4

14D7 26B5 26B7

14D7 26A5 26A7 26B5 26B7

14C5 26C7

14C7 26C2 26C4

14C5 26C7

14B7 14C7 26B2 26B4 26C2 26C4

14B7 26C2 26C4

14C5 26C5

14C7 26B5 26B7 26C5 26C7

14C7 14D7 26B5 26B7

14C3 14D3 27B5 27B7

14C3 27B5 27B7 27C5 27C7

14B3 27C2 27C4

14B3 14C3 27C2 27C4

14C1 27C7

14C3 27B2 27B4 27C2 27C4

14D3 27A5 27A7 27B5 27B7

14D3 27B5 27B7

14B3 27C2 27C4 27D2 27D4

14A3 27C4

14C1 27C5 27C7

14D1 27B7

14D1 27A5

14B3 27A7

14D1 27B7

14D1 27B5

14D1 27B7

14D1 27B5

14D1 27C2

14D1 27B7

14D1 27C4

14D1 27D2

14D1 27C2

14D1 27B2

14B3 27B5

14B3 27B7

14B3 27B4

14D1 27A5

14B3 27B5

14B3 27C2

14A3 27C2

14B1 27C5

14B1 27C5 27C7

15C6

14D5 26B5

14D5 26A5

14C1 27C7

14C1 27C5

14B1 14C1 27C5 27C7

14B5 14C5 26C5 26C7

14B7 26A7

14D5 26C2

14D5 26B7

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

SATA Interface Constraints

Digital Video Signal Constraints

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length. DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps. DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

SPACING

PHYSICAL

NET_TYPE

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

PCI-Express

ELECTRICAL_CONSTRAINT_SET

I182

I183

PCIE

TOP,BOTTOM

=4X_DIELECTRIC

?

CLK_PCIE_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

MCP_PEX_COMP

*

8 MIL

?

PCIE_90D

*

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

DISPLAYPORT

TOP,BOTTOM

=4x_DIELECTRIC

?

PCIE

* ?

=3X_DIELECTRIC

CLK_PCIE

20 MIL

* ?

LVDS

TOP,BOTTOM

=4x_DIELECTRIC

?

=3x_DIELECTRIC

?*

DISPLAYPORT

=3x_DIELECTRIC

?

SATA

TOP,BOTTOM

=3x_DIELECTRIC

?*

LVDS

*

Y 20 MIL 20 MIL =STANDARD

=STANDARD =STANDARD

MCP_DV_COMP

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

LVDS_100D

*

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

DP_100D

SYNC_MASTER=T18_MLB

MCP Constraints 1

051-7898

75

SYNC_DATE=01/04/2008

4.7.0

81

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

SATA_100D

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF

*

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFFSATA_90D_HDD

?

=4x_DIELECTRIC

SATA

*

SATA_TERMP

* ?

8 MIL

PCIE_FW_D2R_N

PCIE_90D

PCIE

PCIE_FW_D2R_C_P

PCIE

PCIE_90D

PCIE_MINI_R2D_P

PCIE_90D

PCIE

PCIE_MINI_R2D_C_P

PCIE

PCIE_MINI_R2D

PCIE_90D

PCIE_MINI_R2D_C_N

PCIE

PCIE_90D

PCIE_MINI_D2R_P

PCIE_90D

PCIE

PCIE_MINI_D2R

PCIE_FW_R2D_P

PCIE_90D

PCIE

PCIE_FW_R2D_N

PCIE

PCIE_90D

PCIE_FW_D2R_P

PCIE_90D

PCIE

PCIE_FW_D2R

PCIE_FW_D2R_C_N

PCIE

PCIE_90D

PCIE_CLK100M_FC_N

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_FC_P

CLK_PCIE_100D

CLK_PCIE

MCP_PE4_REFCLK

PCIE_CLK100M_MINI_CONN_N

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_MINI_CONN_P

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_MINI_N

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_MINI_P

CLK_PCIE_100D

MCP_PE1_REFCLK

CLK_PCIE

PCIE_MINI_R2D_N

PCIE_90D

PCIE

PCIE_MINI_D2R_N

PCIE_90D

PCIE

PCIE_FW_R2D_C_N

PCIE

PCIE_90D

PCIE_FW_R2D_C_P

PCIE

PCIE_90D

PCIE_FW_R2D

MCP_PEX_CLK_COMP

MCP_PEX_COMP

MCP_PEX_CLK_COMP

TMDS_IG_TXC_P

TMDS_IG_TXC

DP_100D

DISPLAYPORT

DP_ML_P<3..0>

DP_ML

DP_100D

DISPLAYPORT

DP_100D

DP_ML_N<3..0>

DP_ML

DP_ML_C_P<3..0>

DP_100D

DISPLAYPORT

DP_ML_C_N<3..0>

DISPLAYPORT

DP_100D

TMDS_IG_TXC_N

DISPLAYPORTTMDS_IG_TXC

DP_100D

DISPLAYPORTTMDS_IG_TXD

DP_100D

TMDS_IG_TXD_N<2..0>

DISPLAYPORT

DP_ML_CONN_N<3..0>

DP_100D

DP_AUX_CH

DISPLAYPORT

DP_100D

DP_IG_AUX_CH_P

DISPLAYPORT

DP_100D

DP_IG_AUX_CH_N

DP_100D

DP_AUX_CH_SW_P

DISPLAYPORT

DP_100D

DP_AUX_CH_SW_N

DISPLAYPORT

DP_100D

DP_AUX_CH_C_P

DP_100D

DISPLAYPORT

DP_AUX_CH_C_N

LVDS

LVDS_100D

LVDS_IG_A_CLK_F_N

LVDS_IG_A_DATA

LVDS

LVDS_100D

LVDS_IG_A_DATA_P<2..0>

LVDS_100D

LVDS_IG_A_DATA

LVDS

LVDS_IG_A_DATA_N<2..0>

MCP_DV_COMP

MCP_IFPAB_RSET

MCP_DV_COMP

MCP_HDMI_RSET

MCP_DV_COMP

MCP_HDMI_VPROBE

SATA

SATA_HDD_R2D_UF_N

SATA_90D_HDD

TMDS_IG_TXD_P<2..0>

DISPLAYPORTTMDS_IG_TXD

DP_100D

MCP_IFPAB_VPROBE

SATA_HDD_D2R_C_N

SATA

SATA_90D_HDD

SATA_ODD_D2R_P

SATA

SATA_100D

SATA_ODD_D2R

SATA_ODD_D2R_N

SATA

SATA_100D

SATA

SATA_100D

SATA_ODD_D2R_UF_P

SATA_ODD_D2R_C_N

SATA_100D

SATA

SATA_100D

SATA

SATA_ODD_R2D_UF_N

SATA_100D

SATA

SATA_ODD_R2D_UF_P

SATA_100D

SATA

SATA_ODD_R2D_N

SATA_HDD_D2R_P

SATA

SATA_HDD_D2R SATA_90D_HDD

SATA_ODD_D2R_C_P

SATA

SATA_100D

SATA

SATA_ODD_D2R_UF_N

MCP_SATA_TERMP

SATA_TERMP

MCP_SATA_TERMP

LVDS

LVDS_100D

LVDS_IG_A_CLK

LVDS_IG_A_CLK_P

LVDS

LVDS_100D

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK

LVDS

LVDS_100D

LVDS_IG_A_CLK_F_P

DISPLAYPORT

DP_100D

DP_ML_CONN_P<3..0>

DP_ML

SATA

SATA_HDD_D2R_C_P

SATA_90D_HDD

SATA

SATA_ODD_R2D_C_N

SATA_100D

SATA

SATA_ODD_R2D_P

SATA_100D

SATA_ODD_R2D

SATA_100D

SATA

SATA_ODD_R2D_C_P

SATA

SATA_HDD_D2R_UF_N

SATA_90D_HDD

SATA

SATA_HDD_D2R_UF_P

SATA_90D_HDD

SATA_HDD_D2R_N

SATA

SATA_90D_HDD

SATA

SATA_HDD_R2D_UF_P

SATA_90D_HDD

SATA

SATA_HDD_R2D_C_N

SATA_90D_HDD

SATA_HDD_R2D

SATA

SATA_HDD_R2D_C_P

SATA_90D_HDD

SATA_HDD_R2D_P

SATA

SATA_90D_HDD

SATA_HDD_R2D_N

SATA

SATA_90D_HDD

16B6 34C1

34C3

6D5

29C7

16B3 29C5

6D5

16B6 29C7

34C3

16B6 34C1

34C3

6D5

29C7

6D5

29C7

16C3 29C5

6D5

29C7

6D5

16B6 29C7

16B3 34C1

16A6

69D1 70C1 70C8

70C2 70C7

70C3 70C4 70C5

17B6 69C7

69C6

69C5

69C4 70C8

69D4 70C8

6C7

68C2

6C7

17B3 68C2

6C7

17B3 68C2

17A3 23C6

17A6 23C7

37A4

17A3 23C6

6B7

37B5

19D6 37C3

37C4

6B7

37C6

37C4

6A7 6B7

37C6

19D6 37B2

6B7

37C6

37C4

19A6

17B3 68B3

6C7

68C2

70C3 70C4 70C5

6B7

37B5

19D6 37C3

6B7

37C6

19D6 37C3

37B4

19D6 37B2

37A4

19D6 37A2

6B7

37A5

6B7

37A5

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

SMBus Interface Constraints

HD Audio Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.

SIO Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SPI Interface Constraints

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.

USB 2.0 Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.

LPC Bus Constraints

PCI Bus Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

=55_OHM_SE

=STANDARD

=55_OHM_SE

*

CLK_PCI_55S

=STANDARD

=55_OHM_SE =55_OHM_SE

=55_OHM_SE

PCI_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD

*

=STANDARD

=90_OHM_DIFF

*

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

USB_90D

=55_OHM_SE

SPI_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

=STANDARD =STANDARD

=4x_DIELECTRIC

TOP,BOTTOM

?

USB

=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

LPC_55S

*

=STANDARD

SMB

* ?

=2x_DIELECTRIC

?*

HDA

=2x_DIELECTRIC

MCP_HDA_COMP

8 MIL

* ?

8 MIL

?

CLK_SLOW

*

=STANDARDPCI

?*

8 MIL

CLK_PCI

?*

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE

HDA_55S

=STANDARD =STANDARD

*

8 MIL

?

SPI

*

CLK_LPC

8 MIL

* ?

6 MIL

LPC

?*

*

CLK_LPC_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD=STANDARD

*

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

CLK_SLOW_55S

=STANDARD=STANDARD

MCP Constraints 2

SYNC_DATE=12/14/2007

SYNC_MASTER=T18_MLB

76 81

4.7.0

051-7898

*

=STANDARD=STANDARD

=STANDARD =STANDARD

8 MIL8 MIL

MCP_USB_RBIAS

USB

?*

=2x_DIELECTRIC

=55_OHM_SE=55_OHM_SE=55_OHM_SE

SMB_55S

=STANDARD=STANDARD

*

=55_OHM_SE

USB_IR

USB_IR_P

USB_90D

USB

USB_IR_N

USB_90D

USB

USB_EXTB_P

USB_EXTB

USB

USB_90D

USB_SD

USB_CARDREADER_P

USB

USB_90D

USB_CARDREADER_N

USB_90D

USB

CONN_USB_EXTB_N

USB

USB_90D

USB

CONN_USB_EXTB_P

USB_TPAD_P

USB_TPAD

USB

USB_90D

USB_TPAD_N

USB_90D

USB

USB_TPAD_R_P

USB

USB_90D

USB_TPAD_R_N

USB

USB_90D

USB_EXTB_N

USB

USB_90D

HDA_55S

HDA_SDIN_CODEC

HDA

HDA_RST_R_L

HDA

HDA_55S

HDA_RST_L

HDA_BIT_CLK_R

HDA

HDA_55S

SMBUS_MCP_1_CLK

SMB

SMB_55S

SMBUS_MCP_0_DATA

SMB

SMBUS_MCP_0_DATA

SMB

SMBUS_MCP_0_CLK

SMB_55S

MCP_USB_RBIAS

MCP_USB_RBIAS_GND

MCP_USB_RBIAS

HDA_SDOUT_R

HDA

HDA_55S

MCP_SUS_CLK

CLK_SLOW_55S

CLK_SLOW

PM_CLK32K_SUSCLK_R

MCP_HDA_COMP

MCP_HDA_PULLDN_COMP

SMBUS_MCP_1_DATA

SMB

SMB_55S

USB_EXTA_MUXED_N

USB_90D

USB

CONN_USB_EXTA_P

USB_90D

USB

CONN_USB_EXTA_N

USB_90D

USB

USB_EXTA_N

USB_90D

USB_EXTA_MUXED_P

USB_90D

USB

PCI_GNT0_L

PCI_55S

PCI

PCI_55S

PCI

PCI_REQ1_L

PCI_55S

PCI_GNT1_L

PCI

PCI_55S

PCI_INTW_L

PCI

PCI_INTW_L

PCI_INTZ_L

PCI_55S

PCI

PCI_INTZ_L

LPC_AD<3..0>

LPC

LPC_AD

LPC_55S

LPC_FRAME_L

LPC

LPC_55S

LPC_RESET_L

LPC

LPC_RESET_L

LPC_55S

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_SMC

LPC_CLK33M_SMC_R

CLK_LPC

CLK_LPC_55S

MCP_LPC_CLK0

USB_EXTA

USB

USB_90D

USB_EXTA_P

PCI_CNTL

PCI_55S

PCI_FRAME_L

PCI

PCI_55S

PCI_REQ0_L

PCI

PCI_REQ0_L

PCI_55S

PCI

PCI_AD<31..25>

PCI_AD

PCI_DEVSEL_L

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI

PCI_AD

PCI_AD<23..8>

PCI_55S

PCI

MCP_DEBUG

MCP_DEBUG<7..0>

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_LPCPLUS

PCI_CLK33M_MCP_R

CLK_PCI_55S

CLK_PCI

MCP_PCI_CLK2

PCI_CLK33M_MCP

CLK_PCI

CLK_PCI_55S

PCI

PCI_INTY_L

PCI_55S

PCI_INTX_L

PCI_55S

PCI

PCI_TRDY_L

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI_SERR_L

PCI

PCI_CNTL

PCI_STOP_L

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_PERR_L

PCI

PCI_CNTL

PCI_55S

PCI_IRDY_L

PCI

PCI_CNTL

PCI_55S

PCI_PAR

PCI_AD

PCI

PCI_C_BE_L

PCI_55S

PCI_C_BE_L<3..0>

PCI

PCI_55S

PCI_AD<24>

PCI

PCI_AD24

CLK_SLOW

CLK_SLOW_55S

PM_CLK32K_SUSCLK

HDA_SDIN0

HDA

HDA_55S

HDA_RST_L

HDA

HDA_55S

HDA_BIT_CLK

HDA

HDA_55S

SPI_ALT_CLK

SPI_55S

SPI

SPI_CLK_R

SPI

SPI_CLK SPI_55S

HDA_SDOUT

HDA

HDA_SDOUT

HDA_55S

SPI

SPI_CLK

SPI_55S

HDA_SYNC

HDA

HDA_SYNC

HDA_55S

HDA_SYNC_R

HDA

HDA_55S

SPI_CS0_R_L

SPI_CS0 SPI_55S

SPI

SPI_MISO

SPI

SPI_MISO

SPI_55S

SPI

SPI_MOSI

SPI

SPI_55S

SPI_MISO_R

SPI_CS0_L

SPI_55S

SPI

SPI_CS1_R_L_USE_MLB

SPI

SPI_55S

SPI_CS1_R_L

SPI

SPI_55S

SPI_ALT_MISO

SPI_55S

SPI

SPI_55S

SPI_ALT_MOSI

SPI

SPI_55S

SPI

SPI_MOSI

SPI_MOSI_R

USB_90D

USB

USB_CAMERA_CONN_P

USB

USB_CAMERA_P

USB_CAMERA

USB_90D

USB

USB_BT_P

USB_BT

USB_BT_N

USB_90D

USB

USB_CAMERA_CONN_N

USB

USB_90D

USB

USB_CAMERA_N

USB_90D

CONN_USB2_BT_N

USB

USB_90D

USB

USB_90D

CONN_USB2_BT_P

19D3 39D7

19C3 38A4

19C3 30C7

38B3

19D3 48B8

48B7

19C3 38B4

20A7 20D4

20C3 43B8

12B6 20C3 43D8

19C4

20A7 20D4

20B3 24B4

20C7

20C3 43B8

38C4

38C3

19D3 38A8

38C4

18D2 18D7

18B3 40C8 42D3 42D5

18C3 40C8 42D5

18C3 24D4

24B1 40C8

18B3 24B4

19D3 38A8

18D2 18D7

12C3 18D7

24B1 42D3

18C5

24B1 40C5

20D7 52C7

20D2 52C7

42C5 42D3

20B3 42A5 42C8

20D2 52C7

51C5

20D2 52C7

20A7 20D4

20B3 42B7

20B3 42A5 42B7

51C4

42B5 42D5

42C5 42D5

20B3 42A5 42C7

6D5

29B7

19D3 29B5

19C3 29B5

6D5

29B7

19D3 29B5

6D5

29B7

6D5

29B7

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SPACING

MCP RGMII (Ethernet) Constraints

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

88E1116R (Ethernet PHY) Constraints

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

=100_OHM_DIFF

ENET_MDI_100D

051-7898

4.7.0

8177

Ethernet Constraints

SYNC_MASTER=T18_MLB

SYNC_DATE=03/19/2008

MCP_MII_COMP

*

=STANDARD

7.5 MIL

=STANDARD=STANDARD

7.5 MIL

=STANDARD

MCP_BUF0_CLK

?*

=3:1_SPACING

12 MIL

ENET_MII

* ?

*

=STANDARD=STANDARD

ENET_MII_55S

=55_OHM_SE

=55_OHM_SE =55_OHM_SE =55_OHM_SE

ENET_MDI

* ?

25 MIL

ENET_MII_55S

ENET_MII

ENET_RXCTL_R

ENET_MII

ENET_MII_55S

ENET_RX_CTRL

ENET_RXD

ENET_MDI_TRAN_N<3..0>

ENET_MDI_100D

ENET_MDI

ENET_MDI_TRAN_P<3..0>

ENET_MDI

ENET_MDI_100D

ENET_MDI

ENET_MDI_100D

ENET_MDI_P<3..0>

ENET_MDI

ENET_MDI_100D

ENET_MDI_N<3..0>

ENET_MDI

ENET_MII

ENET_MII_55S

ENET_RESET_L

ENET_MII_55S

ENET_MII

ENET_TX_CTRL

ENET_TXD

ENET_TXD<0>

ENET_MII_55S

ENET_MII

ENET_TXD0

ENET_TXD<3..1>

ENET_MII

ENET_MII_55S

ENET_TXD

ENET_CLK125M_TXCLK

ENET_MII_55S

ENET_MII

ENET_TXCLK

ENET_MII_55S

ENET_MII

ENET_CLK125M_TXCLK_R

MCP_MII_COMP_GND

MCP_MII_COMP MCP_MII_COMP

ENET_MII

ENET_INTR_L

ENET_MII_55S

ENET_INTR_L

ENET_CLK125M_RXCLK_R

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_RXD<0>

ENET_RXD

ENET_PWRDWN_L

ENET_MII

ENET_MII_55S

ENET_PWRDWN_L

ENET_MII_55S

ENET_MIIENET_MDC

ENET_MDC

ENET_MDIO

ENET_MII

ENET_MII_55S

ENET_MII_55S MCP_BUF0_CLK

RTL8211_CLK25M_CKXTAL1

MCP_BUF0_CLK

MCP_CLK25M_BUF0

ENET_MII_55S

MCP_CLK25M_BUF0_R

ENET_MII

ENET_MII_55S

ENET_RXD<3..1>

ENET_RXD_STRAP

ENET_RXCLK

ENET_MII

ENET_MII_55S

ENET_CLK125M_RXCLK

ENET_MII

ENET_MII_55S

ENET_RXD_R<3..0>

MCP_MII_COMP

MCP_MII_COMP_VDD

MCP_MII_COMP

31B4

17D6 31B1

33B4 33C4 33C5

31B3 33B8 33C8

17C3 31B7

17D3 31B6

17D3 31C6

17D3 31C8

31C6

17C6

31C4

17D6 31C1

17D3 31B6

17C3 31B6

31B6 32A3

17C3 32A5

17D6 31C1

31C4

17C6

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

SD CARD INTERFACE CONSTRAINTS

FireWire Interface Constraints

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SD CARD NET PROPERTIES

Port 2 Not Used

FireWire Net Properties

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

I23

I24

I25

I26

I27

I28

I29

I30

I31

I32

FW_TP

?

=3:1_SPACING

*

=110_OHM_DIFF

*

=110_OHM_DIFF

=110_OHM_DIFF =110_OHM_DIFF

FW_110D

=110_OHM_DIFF =110_OHM_DIFF

*

?

=3X_DIELECTRIC

SD_INTERFACE

*

SD_55S

=55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

051-7898

4.7.0

8178

FireWire Constraints

SYNC_MASTER=K19_MLB

SYNC_DATE=12/01/2008

FW_P1_TPA_P

FW_P1_TPA

FW_TP

FW_110D

FW_P0_TPA_N

FW_P0_TPA

FW_TP

FW_110D

FW_P0_TPA_P

FW_P0_TPA

FW_TP

FW_110D

SD_D<5>

SD_DATA

SD_55S SD_INTERFACE

SD_D<4>

SD_55S

SD_DATA

SD_INTERFACE

SD_D<3>

SD_55S

SD_DATA

SD_INTERFACE

SD_DATA

SD_D<2>

SD_55S SD_INTERFACE

SD_DATA

SD_D<1>

SD_INTERFACESD_55S

SD_D<0>

SD_55S

SD_DATA

SD_INTERFACE

FW_P1_TPB_N

FW_P1_TPB

FW_110D

FW_TP

FW_P1_TPB_P

FW_P1_TPB

FW_110D

FW_TP

FW_P0_TPB_N

FW_110D

FW_P0_TPB

FW_TP

FW_P0_TPB_P

FW_P0_TPB

FW_TP

FW_110D

FW_P1_TPA_N

FW_TP

FW_110D

FW_P1_TPA

SD_D<6>

SD_55S

SD_DATA

SD_INTERFACE

SD_D<7>

SD_55S

SD_DATA

SD_INTERFACE

SD_INTERFACESD_55S

SD_CMD

SD_INTERFACESD_55S

SD_CLK

34B6 36B8

34C6 36C4

34B6 36C4

30C2

34B6 36B8

34B6 36C4

34B6 36B8

30C2

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SMBus Charger Net Properties

SYNC_DATE=01/04/2008

SYNC_MASTER=T18_MLB

SMC Constraints

79 81

4.7.0

051-7898

1TO1_DIFFPAIR

=STANDARD =STANDARD

*

0.1 MM0.1 MM

=STANDARD=STANDARD

1TO1_DIFFPAIR

CHGR_CSO_N

CHGR_CSO

1TO1_DIFFPAIR

CHGR_CSO_P

CHGR_CSI

1TO1_DIFFPAIR

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSI_N

SMB

SMBUS_SMC_A_S3_SCL

SMB_55S

SMB

SMBUS_SMC_A_S3_SDA

SMB_55S

SMB

SMBUS_SMC_BSA_SDA

SMB_55S

SMBUS_SMC_MGMT_SDA

SMB

SMBUS_SMC_MGMT_SCL

SMB_55S

SMBUS_SMC_MGMT_SCL

SMB

SMB_55S

SMBUS_SMC_BSA_SCL

SMB

SMB_55S

SMB

SMBUS_SMC_0_S0_SDA

SMB_55S

SMB

SMBUS_SMC_0_S0_SCL

SMB_55S

SMBUS_SMC_B_S0_SDA

SMB

SMB_55S

SMBUS_SMC_B_S0_SCL

SMB

6C5 6D5

43D2

6C5 6D5

43D2

6A7

43C5

43B5

6A7

43C5

43D5

43C2

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

K24 SENSOR NET PROPERTIES

SPACING

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

=STANDARD =STANDARD

*

0.1 MM0.1 MM

=STANDARD=STANDARD

DIFFPAIR

4.7.0

K24 SPECIAL CONSTRAINTS

051-7898

8180

SYNC_MASTER=M97_MLB

DIFFPAIR

CPUTHMSNS_D2_P

MCP_THMDIODE_N

DIFFPAIR

CHGR_CSO_R_P

DIFFPAIR

CHGR_CSO_R_N

DIFFPAIR

CPUTHMSNS_D2_N

ISNS_CPUVTT_P

DIFFPAIR

MCPTHMSNS_D2_N

DIFFPAIR

CPU_THERMD_P

DIFFPAIR

CPU_THERMD_N

DIFFPAIR

MCP_THMDIODE_P

MCPTHMSNS_D2_P

DIFFPAIR

ISNS_PVCORES0MCP_N

DIFFPAIR

ISNS_PVCORES0MCP_P

DIFFPAIR

ISNS_P1V5S0MCP_N

DIFFPAIR

ISNS_P1V5S0MCP_P

DIFFPAIR

ISNS_CPUVTT_N

46C5

20C3 46B5

45A8 59B3

46C5

45B7

6C7

46B5

9C6

46D5

9C6

46D5

20C3 46B5

6C7

46B5

45B7

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

87

6

5

4

3

21

8

76

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

K24 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

051-7898

4.7.0

8181

SYNC_MASTER=M97_MLB

K24 RULE DEFINITIONS

0.077 MM 0.077 MM

0.330 MM0.330 MM

Y

110_OHM_DIFF

TOP,BOTTOM

0.075 MM 0.075 MM

0.330 MM0.330 MM

Y

110_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

Y

0.091 MM

0.230 MM0.230 MM

0.091 MM

TOP,BOTTOM

100_OHM_DIFF

0.310 MM

Y

27P4_OHM_SE

0.310 MM

TOP,BOTTOM

50_OHM_SE

0.115 MM

Y

0.115 MM

TOP,BOTTOM

0.100 MM

Y

40_OHM_SE

TOP,BOTTOM

0.165 MM

0.126 MM

=STANDARD

Y

40_OHM_SE

*

=STANDARD

0.100 MM

0.076 MM

Y

=STANDARD =STANDARD

=STANDARD55_OHM_SE

0.076 MM

*

=STANDARD=STANDARD

N

=STANDARD =STANDARD

*

=STANDARD

110_OHM_DIFF

TOP,BOTTOM

?

4X_DIELECTRIC

0.280 MM

TOP,BOTTOM

3X_DIELECTRIC

?

0.210 MM

5X_DIELECTRIC

?

TOP,BOTTOM

0.350 MM

0.222 MM0.222 MM

=STANDARD=STANDARD

Y*

27P4_OHM_SE

=STANDARD

Y

=STANDARD =STANDARD

0.1 MM 0.1 MM

=STANDARD

*

1:1_DIFFPAIR

0.315 MM

*

?

5X_DIELECTRIC

0.252 MM

*

?

4X_DIELECTRIC

0.189 MM

*

?

3X_DIELECTRIC

0.126 MM

?

*

2X_DIELECTRIC

?

TOP,BOTTOM

0.140 MM

4:1_SPACING

0.4 MM

* ?

3:1_SPACING

?

0.3 MM

*

?

0.15 MM

*

1.5:1_SPACING

?*

0.2 MM

2:1_SPACING

*

2.5:1_SPACING

?

0.25 MM

BGA_P3MM

?

=DEFAULT

*

?*

BGA_P2MM =DEFAULT

DEFAULT

?

0.1 MM

*

=DEFAULT

?*

STANDARD

=DEFAULT

* ?

BGA_P1MM

CLK_PCIE

*

BGA_P1MM BGA_P2MM

BGA_P2MM

*

CLK_SLOW BGA_P1MM

FSB_DSTB BGA_P3MMFSB_DSTB BGA_P1MM

CLK_PCI

*

BGA_P2MMBGA_P1MM

BGA_P1MM

*

BGA_P2MM

CLK_LPC

BGA_P1MM

CLK_FSB

*

BGA_P2MM

BGA_P1MMBGA_P1MM

**

MEM_CLK

BGA_P1MM BGA_P2MM

*

MEM_40S

STANDARDBGA_P1MM

MEM_40S_VDD

BGA_P1MM STANDARD

0.076 MM 0.076 MM

=STANDARD

Y

=STANDARD=STANDARD

*

50_OHM_SE

=STANDARD

0.224 MM0.224 MM

0.151 MM

Y

70_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

0.100 MM

=STANDARD

N*

=STANDARD

70_OHM_DIFF

=STANDARD

0.200 MM 0.200 MM

0.185 MM

Y

70_OHM_DIFF

TOP,BOTTOM

0.100 MM

N

=STANDARD

90_OHM_DIFF

=STANDARD =STANDARD

*

0.234 MM0.234 MM

0.095 MM0.095 MM

Y

90_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

0.112 MM 0.112 MM

0.220 MM0.220 MM

90_OHM_DIFF

Y

TOP,BOTTOM

ISL3,ISL4,ISL9,ISL10

Y

0.244 MM 0.244 MM

0.075 MM0.075 MM

100_OHM_DIFF

=STANDARD

N

=STANDARD

*

=STANDARD

100_OHM_DIFF

0.090 MM0.090 MM

TOP,BOTTOM

Y

55_OHM_SE

Y

12.7 MM

=DEFAULT

*

=DEFAULT

=DEFAULTSTANDARD

0 MM0 MM

Y

30 MM

*

=50_OHM_SE

DEFAULT 0.100MM

15.5.1

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

MM

NO_TYPE,BGA_P1MM

Apple macbook pro a1278 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual