Apple K90i Schematic

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

DRAWING

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

"EVT3"

SCHEM,FLYING_CLOUD,MLB,K90i

Schematic / PCB #’s

11/22/10

ALIASES RESOLVED

1 OF 86

1 OF 109

2010-08-05

SMC

49

07/07/2010

LINDA_K90I

45

Front Flex Support

48

05/15/2010

K91_MLB

44

External USB Connectors

46

06/01/2010

K91_MLB

43

SATA/IR/SIL Connectors

45

05/15/2010

K91_MLB

42

FireWire Connector

43

07/28/2009

T27_MLB

41

FireWire Port & PHY Power

42

12/15/2009

T27_MLB

40

FireWire LLC/PHY (FW643E)

41

07/20/2009

T27_MLB

39

Ethernet Connector

40

05/26/2010

K91_MLB

38

ETHERNET PHY (CAESAR IV)

39

05/26/2010

K91_MLB

37

T29 Power Support

38

10/12/2010

T29

36

T29 Host (2 of 2)

37

10/12/2010

T29

35

T29 Host (1 of 2)

36

10/12/2010

T29

34

SD READER CONNECTOR

35

05/26/2010

K91_MLB

33

X19/ALS/CAMERA CONNECTOR

34

05/15/2010

K91_MLB

32

FSB/DDR3/FRAMEBUF Vref Margining

33

06/01/2010

K91_MLB

31

CPU Memory S3 Support

32

06/22/2010

ANNE_K90I

30

DDR3 SO-DIMM Connector B

31

MASTER

29

DDR3 Byte/Bit Swaps

30

06/22/2010

ANNE_K90I

28

DDR3 SO-DIMM Connector A

29

MASTER

27

Chipset Support

28

07/08/2010

LINDA_K90I

26

Clock (CK505)

27

06/21/2010

K91_MLB

25

USB HUBS

26

06/08/2010

K91_MLB

24

CPU & PCH XDP

25

06/22/2010

ANNE_K90I

23

PCH DECOUPLING

24

06/25/2010

K91_MLB

22

PCH GROUNDS

23

05/27/2010

K91_MLB

21

PCH POWER

22

06/25/2010

K91_MLB

20

PCH MISC

21

06/18/2010

K91_MLB

19

PCH PCI/FLASHCACHE/USB

20

06/10/2010

K91_MLB

18

PCH DMI/FDI/GRAPHICS

19

06/18/2010

K91_MLB

17

PCH SATA/PCIE/CLK/LPC/SPI

18

06/18/2010

K91_MLB

16

CPU DECOUPLING-II

17

06/28/2010

JACK_K90I

15

CPU DECOUPLING-I

16

06/28/2010

JACK_K90I

14

CPU GROUNDS

14

06/18/2010

ANNE_K90I

13

CPU POWER

13

06/18/2010

ANNE_K90I

12

CPU DDR3 INTERFACES

12

06/18/2010

ANNE_K90I

11

CPU CLOCK/MISC/JTAG

11

06/28/2010

ANNE_K90I

10

CPU DMI/PEG/FDI/RSVD

10

06/22/2010

ANNE_K90I

9

Signal Aliases

9

05/15/2010

K91_MLB

8

Power Aliases

8

05/15/2010

K91_MLB

7

FUNC TEST

7

07/20/2009

K24_MLB

6

BOM Configuration

5

05/28/2009

K17_REF

5

Revision History

4

MASTER

4

Power Block Diagram

3

06/30/2009

K17_REF

3

System Block Diagram

2

06/30/2009

K17_REF

2

PCB Rule Definitions

86

ANNE_K90I

06/08/2010

109

Project Specific Constraints

85

ANNE_K90I

06/08/2010

108

SMC Constraints

84

K91_MLB

05/15/2010

106

T29 Constraints

83

Master

06/21/2010

105

Ethernet/FW Constraints

82

K91_MLB

05/15/2010

104

PCH Constraints 2

81

K91_MLB

05/15/2010

103

PCH Constraints 1

80

K91_MLB

05/15/2010

102

Memory Constraints

79

ANNE_K90I

05/28/2010

101

CPU Constraints

78

ANNE_K90I

06/08/2010

100

LCD Backlight Driver

77

VEMURI_K90I

06/25/2010

97

DisplayPort/T29 A Connector

76

T29

10/16/2010

94

DisplayPort/T29 A MUXing

75

T29

10/16/2010

93

LVDS CONNECTOR

74

K24_MLB

07/20/2009

90

Power Control 1/ENABLE

73

JACK_K90I

10/22/2010

79

Power FETs

72

JACK_K90I

10/22/2010

78

Misc Power Supplies

71

JACK_K90I

08/19/2010

77

CPUVCCIO (1.05V) Power Supply

70

JACK_K90I

08/19/2010

76

CPU IMVP7 & AXG VCore Output

69

JACK_K90I

09/03/2010

75

CPU IMVP7 & AXG VCore Regulator

68

JACK_K90I

10/14/2010

74

1.5V DDR3 Supply

67

JACK_K90I

10/11/2010

73

5V/3.3V SUPPLY

66

JACK_K90I

10/04/2010

72

System Agent Supply

65

JACK_K90I

08/19/2010

71

PBus Supply & Battery Charger

64

JACK_K90I

10/11/2010

70

DC-In & Battery Connectors

63

JACK_K90I

08/20/2010

69

AUDIO: JACK TRANSLATORS

62

LENG_K90I

08/10/2010

68

AUDIO: JACK

61

LENG_K90I

08/10/2010

67

AUDI0: SPEAKER AMP

60

LENG_K90I

08/10/2010

66

AUDIO: HEADPHONE FILTER

59

LENG_K90I

08/10/2010

65

AUDIO: LINE INPUT FILTER

58

LENG_K90I

08/10/2010

63

AUDIO: CODEC/REGULATOR

57

LENG_K90I

08/10/2010

62

SPI ROM56

K91_MLB

05/15/2010

61

Digital Accelerometer

55

LINDA_K90I

07/08/2010

59

WELLSPRING 2

54

LINDA_K90I

07/12/2010

58

WELLSPRING 1

53

LINDA_K90I

07/12/2010

57

Fan52

K24_MLB

07/20/2009

56

Thermal Sensors

51

LINDA_K90I

10/22/2010

55

High Side Current Sensing

50

LINDA_K90I

10/22/2010

54

Voltage & Load Side Current Sensing

49

LINDA_K90I

10/22/2010

53

SMBus Connections

48

K91_MLB

05/26/2010

52

LPC+SPI Debug Connector

47

K91_MLB

05/15/2010

51

Page

Date

Sync

Contents

(.csa)

051-8658

SCH1

CRITICAL

SCHEM,MLB,K90i

Contents

(.csa)

Date

Page Sync

PCBF,MLB,K90i

820-2936 CRITICAL

PCB1

Table of Contents

1

MASTER

1

SMC Support

46

LINDA_K90I

07/08/2010

50

ABBREV=DRAWING

TITLE=MLB

LAST_MODIFIED=Mon Nov 22 19:21:11 2010

SCHEM,FLYING CLOUD,MLB,K90i

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCI

J9400

Display Port

AirPort

X19

PG 32

J3401

PG 41

CONN

FW

J4310

U4100

PG 39

FW643E

1

4 LANEs

CIO

PG 34,35

DP

PG 75

U9390

MUX

0

DP/TMDS

U3600

PCIe x4

J9000

CONN

LVDS

PG 74

SATA

J4500

ODD

CONN

PG 42

PG 26

J4501

CLOCK

SATA CONN

HDD

PG 42

1.05V/3GHZ.

SYSTEM

U2800

GPIO

DP OUT

HDMI OUT

eDP OUT

JTAG

PG 19

LVDS OUT

PG 17

DVI OUT

PG 16

BUFFER

PG 18

PEG

PG 16

TMDS OUT

PCI-E

RGB OUT

PG 38

E-NET

CONN

J4000

U3900

BCM57765

E-NET

PG 37

J3500

PG 33

CONN

SD Card

PG 16

(UP TO 8 LINES)

PG 16

PCI-E

LINE INPUT

U6700

PG 58

FILTER

PG 61

AUDIO IO SWITCH

U6500

HP/LO

AMP

PG 59

PG 16

SMBUS

PG 16

HDA

LINEIN

HPOUT

U6201

DIMM’s

From PCH

PG 16

PG 18

PG 16-21

PG 16

SATA

CLK

COUGAR POINT-MPCH

U1800

INTEL

0 1 2 3 5 74 6

USB

PG 18

(UP TO 14 DEVICES)

8

12

9

1110 13

CTRL

PG 17

U2650

PG 24

HUB-2

P1

USB

P3

PG 32

P2

PG 43

PWR

PG 16

LPC

PG 16

SPI

PG 19

J3401

Bluetooth

X19

J4600

PG 56

SPI

J6700

EXT MIC

EXTERNAL A

USB

PG 61

CONNs

AUDIO

J6701

U6610, U6620, U6630

J6702, J6703

PG 60

AMPs

SPEAKER

SPDIFOUT

AUDIO

PG 57

Codec

CLK

SDA

LINEOUT

J2550

U5701

U4900

MISC

PG 17

FDI

SANDYBRIDGE SFF 2C+2

INTEL CPU

2.2 GHZ

PG 17

DMI

PG 9-13

U1000

RTC

PG 16

2 DIMMs

DDR3-1067/1333MHZ

J2900

J3100

PG 27

DIMM

PG 23

PG 28

XDP CONN

J2500

PCH XDP

PG 23

CONN

PSOC

TP/KB

PG 53

PG 54, 53

U2600

HUB-1

PG 24

USB

P3

P1

J4610

EXTERNAL B

PG 43

USB

KEYBOARD

J5800, J5713

TRACKPAD/

BSB B,0

SMC

PG 45

SMS

ADC Fan

Ser

J5601

U5400, U5410, U5420, U5360

P2

FAN CONN AND CONTROL

U4800

PG 32

J3402

J4501

Controller

PG 44

IR

PG 42

IR

PG 52

PG 49, 50

J5100

POWER SENSE

Port80,serial

LPC+SPI Conn

PG 47

U5920

J6900, J6950

U5510, U5520

Sudden Motion Sensor

PG 51

PG 63

PG 55

DC/BATT

TEMP SENSOR

PG 64-74

POWER SUPPLY

Boot ROM

U6100

PG 76

CONN

T29 Router

/ T29

Prt

CAMERA

System Block Diagram

SYNC_DATE=06/30/2009

SYNC_MASTER=K17_REF

2 OF 109

2 OF 86

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PP24V_T29

T29_A_HV_EN

VOUT

U3890

LT3957

PP3V3_S0 && FWPORT_PWR_EN

DELAY

RC

DELAY

RC

CPUVCCIOS0_EN

P1V8S0_EN

PG71

P5VS0_EN

(PAGE 16~21)

SLP_S3#(F4)

SLP_S4#(H4)

R7978

U1800

(PCH)

(PAGE 44)

P60

SLP_S5#(E4)

COUGAR-POINT

SMC_PM_G2_EN

DELAY

RC

DELAY

RC

DELAY

U4900

SMC

(9 TO 12.6V)

3S2P

J6950

PPVBATT_G3H_CONN

P3V3S0_EN

PM_SLP_S3_L

PG71

PM_SLP_S4_L

P5VS3_EN

PM_SLP_S5_L

DDRREG_EN

P3V3S3_EN

PM_SLP_S3_L_R

PBUSVSENS_EN

PG71

PG 17

Q4260

&&

F9700

LCD_BKLT_EN

BKLT_PLT_RST_L

Q3880

Q9706

PPBUS_SW_LCDBKLT_PWR

VIN

(PAGE 36)

EN

(PAGE 77)

F4260

VOUT

VIN

LP8550

U9701

PPVP_FW

PPVOUT_SW_LCDBKLT

PG71

PG 17

P3V3S5_EN

Q7055

CHGR_BGATE

PPVBAT_G3H_CHGR_R

A

R5410

P3V3S5_EN_L

P5VS3_EN_L

PPBUS_S5_HS_OTHER_ISNS

EN2

(R/H)

3.3V

U7200

EN1

(L/H)

VIN

5V

(PAGE 64)

AC

IN

ADAPTER

J6900

DCIN(16.5V)

6A FUSE

F6905

SMC_DCIN_ISENSE

K9OI POWER SYSTEM ARCHITECTURE

SMC_RESET_L

A

VIN

R7020

PPDCIN_G3H

BATTERY CHARGER

PBUS SUPPLY/

R6990

ISL6259HRTZ

U7000

VOUT

PPVBAT_G3H

R7050

A

SMC_BATT_ISENSE

PPDCIN_S5_P3V42G3H

F7040

PPBUS_G3H

PGOOD

TPS51125

(PAGE 66)

P5V3V3_PGOOD

PM_SLP_S3_L_R

Q7830

Q7810

P3V3S3_EN

PP3V3_S0

PP3V3_S3

U7740

(PAGE 71)

TPS720105

P1V8_S0_EN

FW_PWR_EN

EN

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

EN

(PAGE 40)

U4201

TPS22924

EN

MAX15053EWL

U7760

(PAGE 71)

PP3V3_FW_FWPHY

PP1V8_S0

CAESAR IV

(PAGE 35)

U3900

PP1V05_S5

VOUT2

VOUT1

PP5V_S3

PP3V3_S5

Q7922

PP3V3_ENET

PP5V_S0

MEMVTT_EN

DDRREG_EN

PVCCSA_EN

BCM57765

Q7860

PM_SLP_S3_L_R

VCC

TPS51916

(PAGE 67)

U7300

EN

ISL95870A

(PAGE 65)

U7100

PP1V2_ENET_PHY

PP5V_S0

PGOOD

VOUT

PGOOD

TP_DDRREG_PGOOD

PVCCSA_PGOOD

S5

S3

0.75V

1.5V

VIN

VR_ON

PGOODG

(PAGE 68)

IMON

IMONG

VOUT2

VOUT1

VLDOIN

PGOOD

VOUT

CPUIMVP_IMON

A

PPVCCSA_S0_CPU

PP0V75_S0_DDRVTT

PP1V5_S3

CPUIMVP7_PGOOD

CPUIMVP_IMONG

PP1V05_S0

PP3V3_S0

V

SMC_PBUS_VSENSE

SMC_CPU_HI_ISENSE

R5400

A

D6990

CPUVCCIOS0_EN

CPUIMVP7_VR_ON

PP5V_S0_CPUVCCIOS0

VIN

EN

U7400

U7600

(PAGE 70)

VCC

1.05V

ISL95870

PM6640

U6990

(PAGE 63)

VOUT

ISL95231

3.425V G3HOT

CPU VCORE

VOUT

PGOOD

SMC_CPU_ISENSE

A

PP3V42_G3H

R7640

A

ENABLE

CPUVCCIOS0_PGOOD

V

CPUIMVP7_AXG_PGOOD

U7980

CPUVCCIOS0_PGOOD

PM_SLP_S5_L

PM_SLP_S3_L

PM_SLP_S4_L

SMC_ONOFF_L

ALL_SYS_PWRGD

RSMRST_PWRGD

SLP_S5_L(P95)

SLP_S3_L(P93)

SLP_S4_L(P94)

(PAGE 43)

U4900

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

PP3V3_S5_PWRCTL

PPVCORE_S0_AXG

SMC

U1000

(PAGE 9~13)

CPU

U2850

PM_PCH_PWRGD

U1800

(PCH)

SMC_CPU_FSB_ISENSE

PPCPUVCCIO_S0

SMC_CPU_VSENSE

PPVCORE_S0_CPU

SMC_GFX_VSENSE

EN

(PAGE 44)

SMC PWRGD

U5010

SN0903048

U4202

(PAGE 38)

TPS22924

FW_PWR_EN

PP1V0_FW_FWPHY

SMC_RESET_L

IMVP_VR_ON(P16)

99ms DLY

DRAMPWROK

PROCPWRGD

SYSRST(PA2)

RSMRST_OUT(P15)

RES*

P17(BTN_OUT)

SYS_RERST#

PWRBTN#

PLTRST#

RESET*

(PAGE 16~21)

UNCOREPWRGOOD

COUGAR-POINT

RSMRST#

SM_DRAMPWROK

SMC_RESET_L

CPUIMVP_VR_ON

PM_PWRBTN_L

PM_SYSRST_L

PM_RSMRST_L

PLT_RERST_L

PM_MEM_PWRGD

CPU_PWRGD

PM_SYSRST_L

PM_PWRBTN_L

PM_RSMRST_L

PP1V5_S3RS0

VMON_Q4

VMON_Q2

VMON_Q3

ASMCC0179

(PAGE 73)

Q7970

PP3V3_S5_VMON

6

P5V3V3_PGOOD

P1V8S0_PGOOD

PVCCSA_PGOOD

S0PGOOD_PWROK

4

SYNC_DATE=06/30/2009

SYNC_MASTER=K17_REF

Power Block Diagram

3 OF 109

3 OF 86

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROTO:

Revision History

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

4 OF 109

4 OF 86

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_BOMGROUP_ITEM

K90i BOM GROUPS

Module Parts

Programmable Parts

Development BOM

BOM Variants

Bar Code Labels / EEEE #’s

Alternate Parts

PCBA,2.3G,K90i

639-1699

K90i_COMMON,CPU_2_3GHZ,EEEE_DH8G

K90i MLB DEVELOPMENT BOM

K90i_DEVEL:ENG

085-1998

EEEE_DH8G

[EEEE:DH8G]

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

1

CRITICAL

157S0055157S0058

ALL

Delta alt to TDK Magnetics

ALL

Murata alt to Samsung

138S0603 138S0602

128S0282128S0303

ALL

Panasonic alt to Sanyo

516S0806

Molex alt to Foxconn

516S0805

ALL

TPAD_PROG

CRITICAL

1

U5701

341S3024

IC,TP PSOC,K90,K90i,K91,K91F,K92

BOOTROM_BLANK

1

CRITICAL335S0770

U6100

64 MBIT SPI SERIAL DUAL I/O FLASH

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

1

CRITICAL

EEEE_DDRQ

[EEEE:DDRQ]

[EEEE:DH8F]

EEEE_DH8F

LBL,P/N LABEL,PCB,28MM X 6 MM

1

CRITICAL826-4393

K90i_COMMON,CPU_2_5GHZ,EEEE_DDRQ

639-1294

PCBA,2.5G,K90i

PCBA,2.6G,K90i

639-1698

K90i_COMMON,CPU_2_6GHZ,EEEE_DH8F

639-1581

PCBA,2.7G,K90i

K90i_COMMON,CPU_2_7GHZ,EEEE_DH78

CRITICAL

1

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:DH78]

EEEE_DH78

CRITICAL

1

U3990

335S0663

ENET_BLANK

IC,FLASH,SERIAL,SPI,!MBIT,2V7,8P,SOIC

T29ROM:BLANK

1

335S0777

U3690

CRITICAL

IC,EEPROM,SERIAL,SPI,1Kx8,1.8V,MLP8,LF

ENET_PROG

1

U3990

CRITICAL341S3026

IC ENET,1!MBITFLAH,CIV REV01,K60/K62

BOOTROM_PROG

341T0299 CRITICAL

1

U6100

IC,EFI ROM,K90i

T29ROM:PROG

1

IC,T29 ASSY

U3690

341T0317 CRITICAL

085-1998 CRITICAL

K90i MLB DEVELOPMENT

DEVEL_BOM

DEVEL

1

341S2384 CRITICAL

U4800

IR,ENCORE II, CY7C63803-LQXC

BOOTROM_BLANK

64 MBIT SPI SERIAL DUAL I/O FLASH

335S0769

1

CRITICAL

U6100

SMC_PROG

IC,SMC,K90i

CRITICAL341T0300

U4900

1

SMC_BLANK

1

U4900

CRITICAL

IC,SMC,HS8/2117/9MMx9MM,TLP

338S0895

U4100

1

CRITICAL338S0753

IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12

343S0534

U3900

1

CRITICAL

IC,BCM57765B0,ENET&SD,8X8

T29MCU:BLANK

U9330

337S3997

1

CRITICAL

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

1

CPU_2_7GHZ

CRITICAL

U1000

337S4057

SNB,Q1R3,QS,J1,2.7,35W,2+2,1.30,4M,BGA

337S4064

CPU_2_6GHZ

CRITICAL

U1000

1

SNB,Q1R7,QS,J1,2.6,35W,2+2,1.30,3M,BGA

SYNC_DATE=05/28/2009

SYNC_MASTER=K17_REF

BOM Configuration

CRITICAL

1

U3600

T29:YES

338S0921

IC,T29-C0,220 FCBGA,15x15MM

CPU_2_3GHZ

CRITICAL

U1000

1

337S4024

SNB,Q1R9,QS,J1,2.3,35W,2+2,1.30,3M,BGA

CPU_2_5GHZ

U1000

CRITICAL

1

337S4058

SNB,Q1RA,QS,J1,2.5,35W,2+2,1.30,3M,BGA

K90i_DEBUG:PROD

BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT,LPCPLUS

337S4029

IC,PCH,COUGARPOINT,SLH9D,PRQ,BD82HM65

1

U1800

CRITICAL

1

353S3055

IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN

U9390

Murata alt to Samsung

ALL

138S0691138S0676

Cyntec alt to Vishay

152S0693

ALL

152S0778

Diodes alt to Toshiba

376S0855 376S0613

ALL

Diodes alt to Toshiba

376S0859376S0977

376S0612

Rohm alt to Toshiba

376S0972

ALL

376S0966376S0927

Fairchild alt to Renesas

ALL

376S0801376S0960

Renesas alt to Renesas

ALL

376S0928376S0790

CICLON alt to Fairchild

ALL

376S0761376S0777

AON alt to Siliconix

ALL

376S0895376S0928

Fairchild alt to Renesas

ALL

Fairchild alt to Renesas

376S0845376S0937

Fairchild alt to Fairchild

ALL

376S0958376S0957

ALL

353S1658353S3085

STmicro alt to LT

376S0953

ALL

376S0958

Fairchild alt to Renesas

ALL

376S0927 376S0790

Fairchild alt to CICLON

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT

K90i_DEBUG:PVT

K90i_DEBUG:ENG

DEVEL_BOM,SMC_DEBUG_YES,XDP

K90i_DEVEL:PVT

LPCPLUS,XDP_CONN,XDP_PCH

T29MCU:PROG

1

CRITICAL

U9330

IC,PROGRMD,LPC1112A,T29 PORT MCU,HVQFN25

341S2939

CRITICAL

U1000

CPU_2_2GHZ

1

337S3934

SNB,2C,QXXX,ES1,2.2,35W,B2,3M,GT1,BGA

K90i_COMMON

ALTERNATE,COMMON,K90i_COMMON1,K90i_COMMON2,K90i_DEBUG:ENG,K90i_PROGPARTS,USBHUB_2513B,T29BST:Y

BKLT:ENG,BMON:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,VREFMRGN,S0PGOOD_ISL,IMVPISNS_ENG

K90i_DEVEL:ENG

BOOTROM_PROG,SMC_PROG,TPAD_PROG,ENET_PROG,T29ROM:PROG,T29MCU:PROG

K90i_PROGPARTS

K90i_COMMON2

MIKEY,KB_BL

BATT_3S,CPUMEM_S0,SMC_DEBUG_YES,HUB1_2NONREM,HUB2_3NONREM,T29:YES,DP_SDRV:A2,SDRV_PD,SDRVI2C:MCU

K90i_COMMON1

5 OF 109

5 OF 86

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(NEED TO ADD 5 GND TP)

X19 CONN

(NEED 2 TP)

(NEED TO ADD 3 GND TP)

(NEED TO ADD 5 GND TP)

(NEED TO ADD 2 GND TP)

LPC+SPI DEBUG_CONN

(NEED TO ADD 2 GND TP)

IPD_FLEX_CONN

Functional Test Points

(NEED 3 TP)

(NEED TO ADD 2 GND TP)

(NEED TO ADD 1 GND TP)

MIC FUNC_TEST

(NEED TO ADD 4 GND TP)

SATA HDD/IR/SIL

SATA ODD CONN

(NEED 2 TP)

NO_TEST

(NEED TO ADD 1 GND TP)

Fan Connectors

NC NO_TESTs

(NEED TO ADD 6 GND TP)

SPEAKER FUNC_TEST

(NEED TO ADD 2 GND TP)

CAMERA/ALS CONN

(NEED 2 TP)

(NEED 5 TP)

(NEED TO ADD 3 GND TP)

(NEED 2 TP)

(NEED TO ADD 5 GND TP)

(NEED TO ADD 1 GND TP)

KBD BACKLIGHT CONN

KEYBOARD CONN

(NEED 3 TP)

DC POWER CONN

LVDS FUNC_TEST

BATT POWER CONN

BIL CONN

DEBUG VOLTAGE

NC NO_TESTs

NO_TEST

I12

I15

I16

I226

I227

I228

I229

I230

I231

I245

I246

I247

I248

I249

I250

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I386

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I409 I410

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I601 I602

I603 I604

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I619

I620

I622

FUNC TEST

SYNC_MASTER=K24_MLB

PP5V_S0

TRUE

NC_SDVO_TVCLKINP

NC_SDVO_INTN

MAKE_BASE=TRUE

TRUE

NC_FW643_VBUF

NC_FW643_AVREG

NC_PCH_TP13

NC_SATA_E_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_FW643_TDI

TP_XDP_PCH_OBSFN_D<0..1>

NC_TP_XDP_PCH_OBSFN_D<0..1>

MAKE_BASE=TRUE

TRUE

NC_TP_XDPPCH_HOOK3 NC_TP_XDPPCH_HOOK3

MAKE_BASE=TRUE

TRUE

TP_XDP_PCH_OBSFN_B<0..1>

NC_TP_XDP_PCH_OBSFN_B<0..1>

TRUE MAKE_BASE=TRUE

NC_TP_XDPPCH_HOOK2 NC_TP_XDPPCH_HOOK2

TRUE MAKE_BASE=TRUE

TP_XDP_PCH_OBSFN_A<0..1>

NC_HDA_SDIN2

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

NC_PCH_TP4

NC_PCH_TP9 NC_PCH_TP8

TRUE

PP1V8_S0

TRUE MAKE_BASE=TRUE

NC_FW643_SDA

TRUE MAKE_BASE=TRUE

NC_FW643_SM

TRUE

NC_FW643_TCK

MAKE_BASE=TRUE MAKE_BASE=TRUE

TRUE

NC_FW643_TMS

MAKE_BASE=TRUE

TRUE

NC_FW643_FW620_L

MAKE_BASE=TRUE

NC_FW643_VBUF

TRUE

MAKE_BASE=TRUE

NC_FW643_OCR10_CTL

TRUE

NC_FW643_SDA NC_FW643_SM NC_FW643_TCK NC_FW643_TMS NC_FW643_FW620_L

NC_FW643_OCR10_CTL

NC_CRT_IG_RED

NC_CRT_IG_DDC_CLK

NC_CRT_IG_HSYNC

NC_PCI_CLK33M_OUT3

MAKE_BASE=TRUE

TRUE

NC_CLINK_RESET_L

NC_PCIE_CLK100M_PEBP NC_PCIE_CLK100M_PEBP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBN

MAKE_BASE=TRUE

TRUE

NC_CLINK_DATA

TRUE

MAKE_BASE=TRUE

NC_PCI_PME_L

MAKE_BASE=TRUE

TRUE

NC_PCI_CLK33M_OUT3

NC_HDA_SDIN3 NC_HDA_SDIN3

TRUE

MAKE_BASE=TRUE

NC_HDA_SDIN1 NC_HDA_SDIN1

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN2

NC_PCH_LVDS_VBG

TRUE MAKE_BASE=TRUE

NC_PCH_LVDS_VBG

NC_LVDS_IG_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_CTRL_DATA

NC_LVDS_IG_CTRL_CLK

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_CTRL_CLK

TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_DDC_CLK

NC_CRT_IG_DDC_DATA

TRUE MAKE_BASE=TRUE

NC_CRT_IG_DDC_DATA

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_HSYNC

NC_CRT_IG_GREEN

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_GREEN

NC_CRT_IG_BLUE

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_BLUE

NC_CRT_IG_RED

MAKE_BASE=TRUE

TRUE

=PEG_D2R_P<0..7>

=PEG_R2D_C_N<12..15>

NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P

PP3V3_S0

TRUE

PP3V3_S3

BI_MIC_LO

TRUE

BI_MIC_SHIELD

TRUE

BI_MIC_HI

PP5V_SW_ODD

TRUE

NC_PCIE_CLK100M_PE5N

TRUE

MAKE_BASE=TRUE

NC_SATA_B_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_EDP_AUXP

NC_EDP_AUXN

TRUE

MAKE_BASE=TRUE

NC_EDP_TXP<0..3>

TRUE

MAKE_BASE=TRUE

NC_EDP_AUXN

MAKE_BASE=TRUE

TRUE

NC_PEG_R2D_CP<12..15>

NC_SATA_E_D2RN

NC_SATA_E_R2D_CN

NC_SATA_E_D2RP

NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N

NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE7P

NC_PCIE_CLK100M_PE5P

=PEG_D2R_P<12..15>

=PEG_R2D_C_P<12..15>

=PEG_D2R_N<12..15>

=PEG_D2R_N<0..7>

=PEG_R2D_C_P<0..7> =PEG_R2D_C_N<0..7>

TP_CPU_RSVD<30..45> TP_CPU_RSVD<8..27>

NC_CPU_THERMDC

NC_CPU_THERMDA

TP_EDP_TX_N<0..3> NC_EDP_AUXP

TP_EDP_TX_P<0..3>

NC_PCH_TP16

NC_PCH_TP12

NC_PCH_TP1

NC_PCH_TP7

NC_PCH_TP2

NC_PCH_TP6 NC_PCH_TP5

NC_PCH_TP14

NC_PCH_TP15

NC_LVDS_IG_BKL_PWM

TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKP

NC_SMC_BS_ALRT_L

NC_SDVO_TVCLKINN

NC_SDVO_STALLN

NC_SDVO_INTP

NC_SDVO_INTN

NC_SDVO_STALLP

PP1V5_S3

TRUE

PP1V2_S3_ENET_INTREG

TRUE

USB_CAMERA_CONN_N

TRUE

USB_CAMERA_CONN_P

TRUE

WS_KBD16_NUM

SMBUS_SMC_A_S3_SDA

TRUE

WS_KBD19

TRUE

WS_KBD17

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_D2R_C_P

TRUE

SPKRAMP_R_P_OUT

TRUE

SPKRAMP_R_N_OUT

TRUE

SPKRAMP_L_P_OUT

TRUE

SPKRAMP_L_N_OUT

TRUE

SPKRAMP_SUB_P_OUT

NC_SDVO_TVCLKINN

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINP

TRUE MAKE_BASE=TRUE

NC_SDVO_INTP

TRUE MAKE_BASE=TRUE

NC_PCH_TP1

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP4

TRUE

PCH_VSS_NCTF<15> PCH_VSS_NCTF<17>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<21>

TRUE

PCH_VSS_NCTF<25>

TRUE

PCH_VSS_NCTF<27>

TRUE

PCH_VSS_NCTF<29>

TRUE

MAKE_BASE=TRUE

NC_PCH_TP13

TRUE

MAKE_BASE=TRUE

NC_PCH_TP10

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

MAKE_BASE=TRUE

TRUE

NC_PCH_TP14

MAKE_BASE=TRUE

NC_PCH_TP15

TRUE

MAKE_BASE=TRUE

NC_PCH_TP16

TRUE

MAKE_BASE=TRUE

NC_PCH_TP17

TRUE

MAKE_BASE=TRUE

NC_PCH_TP18

TRUE

NC_PCH_TP9

TRUE

MAKE_BASE=TRUE

NC_PCH_TP12

TRUE

MAKE_BASE=TRUE

NC_PCH_TP8

TRUE

NC_PCH_TP3

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP6

MAKE_BASE=TRUE

TRUE

NC_PCH_TP5

PCH_VSS_NCTF<1>

TRUE

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<9>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<12>

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_B_CLKP

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

TRUE

NC_SMC_BS_ALRT_L

NC_SDVO_STALLN

MAKE_BASE=TRUE

TRUE

NC_SDVO_STALLP

TRUE MAKE_BASE=TRUE

PP5V_SW_ODD

TRUE

LED_RETURN_6

SMC_PM_G2_EN

TRUE

PP3V3_S0_LCD_F

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

KBDLED_ANODE

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_KBD_ONOFF_L

TRUE

WS_KBD22

TRUE

WS_KBD21

TRUE

SMC_KDBLED_PRESENT_L

TRUE

LED_RETURN_5

TRUE

LED_RETURN_4

TRUE

SATA_HDD_R2D_P

TRUE

SYS_DETECT_L

SATA_ODD_D2R_UF_N

TRUE

FAN_RT_TACH

TRUE

LVDS_IG_A_DATA_N<2>

TRUE

LVDS_IG_A_DATA_N<1>

TRUE

MAKE_BASE=TRUE

NC_EDP_TXN<0..3>

TRUE

MAKE_BASE=TRUE

NC_CPU_THERMDA

TRUE

MAKE_BASE=TRUE

NC_CPU_THERMDC

TRUE

MAKE_BASE=TRUE

NC_CPU_RSVD<8..27>

NC_CPU_RSVD<30..45>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PEG_D2RP<0..7>

NC_PEG_R2D_CN<0..7>

TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_CP<0..7>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PEG_D2RN<0..7>

NC_PEG_D2RN<12..15>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PEG_R2D_CN<12..15>

MAKE_BASE=TRUE

TRUE

NC_PEG_D2RP<12..15>

NC_PCIE_CLK100M_PE4N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_PE7P

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE7N

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RN

TRUE

MAKE_BASE=TRUE

NC_SATA_B_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RP NC_SATA_D_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_F_D2RP

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_F_R2D_CP

TRUE

FAN_RT_PWM

PP18V5_S5

TRUE

PP5V_S0

TRUE

PP1V5_S3RS0

TRUE

WS_KBD23

PPVCCSA_S0_CPU

TRUE

WS_KBD18

TRUE

WS_KBD15_CAP

TRUE

WS_KBD14

TRUE

WS_KBD13

TRUE

WS_KBD12

TRUE

WS_KBD11

WS_KBD10

TRUE

WS_KBD3

TRUE

WS_KBD2

TRUE

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_BKL_PWM

NC_TP_XDP_PCH_OBSFN_A<0..1>

TRUE MAKE_BASE=TRUE

TRUE

NC_FW2_TPBP

TRUE

NC_FW2_TPBN NC_FW2_TPBIAS

TRUE

NC_FW2_TPAN

TRUE

NC_FW2_TPAP

TRUE

NC_FW0_TPBP

TRUE

NC_FW0_TPAP

TRUE

NC_FW0_TPBN

TRUE

XDP_PCH_USB_HUB_SOFT_RST_L

TRUE

XDP_PCH_AP_PWR_EN

TRUE

XDP_PCH_SDCONN_STATE_RST_L

TRUE

XDP_PCH_ENET_PWR_EN

TRUE

XDP_PCH_SDCONN_DET_L

TRUE

XDP_PCH_S5_PWRGD

TRUE

XDP_PCH_ISOLATE_CPU_MEM_L

TRUE

XDP_PCH_PWRBTN_L

TRUE

XDP_FW_CLKREQ_L

TRUE

XDP_PCH_AUD_IPHS_SWITCH_EN

TRUE

XDP_AP_CLKREQ_L

NC_PCH_TP17

NC_PCH_TP18

NC_SATA_F_R2D_CP

NC_SATA_F_R2D_CN

NC_SATA_F_D2RP

NC_SATA_F_D2RN

NC_SATA_E_R2D_CP

NC_FW643_TDI

MAKE_BASE=TRUE

TRUE

NC_FW643_AVREG

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_HOOK4 NC_TP_XDP_PCH_HOOK5

TRUE MAKE_BASE=TRUE

NC_TP_XDP_PCH_HOOK4

TRUE MAKE_BASE=TRUE

NC_TP_XDP_PCH_HOOK5

NC_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO64_CLKOUTFLEX0

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO65_CLKOUTFLEX1

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

MAKE_BASE=TRUE

TRUE

NC_PCH_TP3

TRUE

MAKE_BASE=TRUE

NC_PCH_TP2

NC_PCH_TP10

NC_PCH_GPIO67_CLKOUTFLEX3

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

NC_PCH_GPIO66_CLKOUTFLEX2

NC_PCH_GPIO65_CLKOUTFLEX1

PP1V05_S0

TRUE

PP5V_S3

PP3V42_G3H

TRUE

PPBUS_G3H

TRUE

NC_CLINK_DATA

NC_CLINK_CLK

TRUE

MAKE_BASE=TRUE

TRUE

NC_CLINK_RESET_L

NC_SATA_F_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RP

TRUE MAKE_BASE=TRUE

NC_PSOC_P1_3 NC_SATA_B_D2RN

TRUE

SATA_ODD_R2D_N

SATA_ODD_D2R_UF_P

TRUE

PPVOUT_SW_LCDBKLT

NC_CLINK_CLK

TRUE

PP3V3_LCDVDD_SW_F

TRUE

PP18V5_DCIN_FUSE

WS_KBD20

TRUE

PP5V_S3_IR_R

TRUE

SMC_LID_R

SMBUS_SMC_BSA_SDA

TRUE

SMBUS_SMC_BSA_SCL

TRUE

ADAPTER_SENSE

TRUE

WS_KBD6

TRUE

WS_KBD4

PP3V42_G3H

TRUE

PP3V3_S5

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_CONTROL_KBD

MAKE_BASE=TRUE

NC_PSOC_P1_3

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RN

NC_SATA_B_D2RP

NC_SATA_B_R2D_CP NC_SATA_D_D2RN

NC_SATA_B_R2D_CN

NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP

TRUE

PM_SLP_S3_L

PP4V5_AUDIO_ANALOG

TRUE

PCIE_AP_D2R_PI_N

TRUE

PP3V3_WLAN

PP3V3_LCDVDD_SW_F

TRUE

PM_SLP_S4_L

PP5V_S0_HDD_FLT

TRUE

SMBUS_SMC_BSA_SCL

TRUE

WS_KBD9

WS_KBD8

TRUE

WS_KBD7

TRUE

WS_KBD5

TRUE

WS_KBD1

PPVCORE_S0_AXG

TRUE

Z2_DEBUG3

TRUE

Z2_BOOST_EN

Z2_CLKIN

TRUE TRUE

Z2_KEY_ACT_L

PSOC_SCLK

TRUE

SMBUS_SMC_A_S3_SDA

TRUE TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PSOC_MOSI

TRUE

PP3V3_S5

PSOC_F_CS_L

TRUE

PICKB_L

TRUE

PSOC_MISO

TRUE

PP18V5_S5 Z2_CS_L

TRUE

Z2_MISO

TRUE

LPC_CLK33M_LPCPLUS

TRUE

LPC_SERIRQ

TRUE

LPC_AD<3>

TRUE

LPCPLUS_GPIO

TRUE

LPC_FRAME_L

TRUE

LPC_PWRDWN_L

TRUE

LPC_AD<2>

TRUE

LPC_AD<1>

TRUE

LPC_AD<0>

LPCPLUS_RESET_L

TRUE TRUE

PM_CLKRUN_L

TRUE

SMC_RX_L

TRUE

SMC_TCK

TRUE

SMC_TDI

TRUE

SMC_MD1

TRUE

SMC_TDO

TRUE

PP3V42_G3H

TRUE

SMC_TMS

TRUE

PP5V_S0

TRUE

SPIROM_USE_MLB

TRUE

SPI_ALT_MOSI

TRUE

SPI_ALT_MISO

TRUE

SPI_ALT_CS_L

TRUE

SPI_ALT_CLK

TRUE

SMC_TX_L

TRUE

SMC_TRST_L

PPVCORE_S0_CPU

TRUE

USB_BT_P

TRUE

SPKRAMP_SUB_N_OUT

SMC_BIL_BUTTON_L

TRUE

SMBUS_SMC_BSA_SDA

TRUE

IR_RX_OUT

TRUE

SYS_LED_ANODE_R

TRUE

PP5V_S0_HDD_FLT

SATA_ODD_R2D_P

TRUE

Z2_RESET

Z2_HOST_INTN

TRUE

Z2_SCLK

TRUE

Z2_MOSI

AP_TEMP_SMB_SCL_R

TRUE

PCIE_AP_D2R_PI_P

TRUE

SMBUS_SMC_0_S0_SCL

TRUE

PP3V42_G3H

TRUE

SATA_HDD_R2D_N

TRUE

SMC_ODD_DETECT

TRUE

LED_RETURN_3

LED_RETURN_2

TRUE

LVDS_CONN_A_CLK_F_P

TRUE TRUE

LED_RETURN_1

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_IG_A_DATA_P<2>

TRUE

LVDS_IG_A_DATA_P<1>

TRUE

LVDS_IG_A_DATA_P<0>

TRUE

LVDS_IG_A_DATA_N<0>

TRUE

LVDS_DDC_DATA

TRUE

LVDS_DDC_CLK

TRUE

BKL_VSYNC

PP3V3_S0_LCD_F

TRUE

PP3V3_WLAN

TRUE

PPVBAT_G3H_CONN

TRUE

AP_RESET_CONN_L

TRUE

AP_CLKREQ_Q_L

TRUE

USB_BT_N

SMBUS_SMC_0_S0_SDA

TRUE

PCIE_AP_R2D_P

TRUE

NC_CRT_IG_VSYNC

WIFI_EVENT_L_R

TRUE

AP_TEMP_SMB_SDA_R

TRUE

PCIE_WAKE_L

TRUE

PP3V3_S3_BT_F

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

PCIE_AP_R2D_N

TRUE

NC_PCI_PME_L

PP3V3_ENET

TRUE

PP3V3_S5

7 OF 109

6 OF 86

6 7

22 42 47 52 54 65

68 70 72 73 77

6

17

6

17

6

39

6

39

6

16

6

39

23

6

23

6

23

6

23

6

23

6

16

6

16

6

7

14 17 20 22 26 71

6

39

6

39

6

39

6

39

6

39

6

39

6

39

6

39

6

39

6

39

6

39

6

39

6

39

6

17

6

17

6

17

6

18

6

16

6

16

6

16

6

16

6

16

6

16

6

18

6

18

6

16

6

16

6

16

6 16

6

16

6

18

6

18

6

18

6

18

6

18

6 18

6 17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

9

6

7 8

12 16 17

18 19 20 22 23 26 27

29 33 36 37 40

41 42 46 48 49

50

51 52 54 57 61 62 71 72 73 74 75 77 85

7 8

18 24 26

30 31 32 33 48 50 54 55 72 73

61 62

6

42

6

16

6

16

6 9

9

6 9

9

6

16

6

16

6

16

6

19

6

19

6

19

6

19

6 16

9

6

6 9

6

8

18 80

8

18 80

6

17

6

17

6

17

6

17

6

17

7

27 29 30 67

72

37 71

32 80

53

6

32 45 48 54 55 84

53

42 80

60 61 85

6

17

6

17

6

17

6

81

6

81

6

81

6

81

6

17

6

17

6

42

74 77

45 73

6

74

6

32 45 48 54 55 84

32

54

53

54

74 77

42 80

63

42 85

52

18 74 80

9

6

9

6

16

6

16

6

19

6

19

6

19

6

19

6

16

6

16

6

16

6

16

6

16

6

16

6

16

6

16

6

16

6

16

52

6

54

7

10 12 15 30 72 73

85

53

7

12 15

65

53

6

23

39 41

39 41 82

23

6

6 16

6

23

6

23

6

23

6

23

6

16

6

16

6

16

6

16

6

16

6

16

6

16

6

16

7 9

10 12 14

16 17 20 22 23 36 40

45 68 70 73

7

30 32 42 43 44 46 57 59 60 61

66 67 72

6 7

26

43 45 46

47 48 53 63 64 73

7 8

36 40 49 50 63 64 77

6

16

6 16

6

16

6

16

6

53

6

16

42 80

42 85

74 77

6

16

6

74

63

53

42

63

6

45 48 63 64 84

6

45 48 63 64 84

63

53

6 7

26 43 45 46 47 48 53 63 64

73

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

53

6

53

6

16

6

16

6

16

6

16

6

16

6

16

6

16

6

16

17 30 45 73

57

32 81

6

32 46

6

74

17 30 45 73

6

42

6

45 48 63 64 84

53

7 9

12 15 49

69

53 54

54

53 54

6

32 45 48 54 55 84

6

32 45 48 54 55 84

53 54

6 7 8

17 19 20 22 23 24

26 30 46 56 66 72 73 74

76 85

53 54

6

54

53 54

26 47 81

16 45 47

16 45 47 81

19 47

16 45 47 81

17 45 47

16 45 47 81

26 47 81

17 45 47

43 45 46 47

45 46 47

45 47

45 46 47

6 7

26 43 45 46 47 48 53 63 64

73

45 46 47

6 7

22 42 47 52 54 65 68 70 72

73 77

19 47 56

47

43 45 46 47

45 47

7 9

12 14 49

69

24 32 80

60 61 85

45 46 63

6

45 48 63 64 84

42 44

42

6

42

42 80

53 54

32

32 81

32 45 48 51 84

6 7

26 43 45 46 47

48 53 63 64 73

42 80

42 45

74 77

74 85

74 77

74 85

18 74 80

8

18 74

8

18 74

74 77

6

74

6

32 46

63 64

32

24 32 80

32 45 48 51 84

32 81

32

17 26 32

32

32 85

32 81

6

18

7

26 37 71 73

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

3.3V Rails

ENET Rails

"G3Hot" (Always-Present) Rails

2A max supply

1.8V/1.5V/1.2V/1.05V Rails

1V05 S0 LDO

Chipset "VCore" Rails

? mA

"FW" (FireWire) Rails

5V Rails

T29 Rails (off when no cable)

SYNC_MASTER=K91_MLB

Power Aliases

SYNC_DATE=05/15/2010

PP3V3_S3

PP1V0_FW_FWPHY

PP3V3_S0

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.5 MM

PP3V3_S0

PP0V75_S0_DDRVTT

VOLTAGE=0.75V

MIN_LINE_WIDTH=2 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mm

PP5V_S5

PP15V_T29

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=17.8V

MIN_NECK_WIDTH=0.2 MM

PP15V_T29

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_T29

PP3V3_T29 PP3V3_T29

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_T29

MIN_LINE_WIDTH=0.4 MM

PP1V05_T29

PP3V3_S3

PPDCIN_G3H

PPBUS_S5_HS_OTHER_ISNS

VOLTAGE=12.8V

PPVIN_SW_T29BST

PP3V42_G3H

PP1V05_SUS

PP5V_S3

PP5V_S3 PP5V_S3

PP5V_S3

PP3V3_S3

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP5V_S5

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.50MM

PP5V_SUS

PP3V3_T29

PP5V_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S3

PP5V_SUS

PPVRTC_G3H PPVRTC_G3H

MAKE_BASE=TRUE

VOLTAGE=3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V5_S3

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.8 MM

PP5V_S3

PP5V_S0

PP5V_S3

PP5V_SUS

PP5V_S0

PP1V05_S0

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

PPVTTDDR_S3

MAKE_BASE=TRUE

PPDCIN_G3H PPDCIN_G3H

PPBUS_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PPBUS_S5_HS_COMPUTING_ISNS

PPBUS_S5_HS_OTHER_ISNS

VOLTAGE=12.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PPBUS_S5_HS_OTHER_ISNS

MIN_NECK_WIDTH=0.2 mm

PP3V3_T29

PPVP_FW PPVP_FW

PP3V3_ENET

PP3V42_G3H

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_ENET

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVRTC_G3H

PP0V75_S0_DDRVTT

PPVP_FW

PP1V0_FW_FWPHY

PP3V3_FW_FWPHY

PP1V05_SUS

PP3V3_ENET

PP3V3_FW_FWPHY

PPVCCSA_S0_CPU

PP3V3_FW_FWPHY

PP3V3_ENET

PPBUS_G3H

MAKE_BASE=TRUE

PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

VOLTAGE=12.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PPVP_FW

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.0V

PP1V0_FW_FWPHY

PP1V05_S0

PP5V_S5

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.25V

MAKE_BASE=TRUE

PPVCORE_S0_CPU PPVCORE_S0_CPU

PPVCORE_S0_AXG

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0_CPU_VCCPQE

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V

PP1V05_S0_CPU_VCCPQE

PP1V8_S0_CPU_VCCPLL_R

PP1V05_T29

PP1V05_S0_PCH_VCCADPLL

PPVCORE_S0_AXG

MAKE_BASE=TRUE

PPVCORE_S0_AXG

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V

PPVCORE_S0_AXG

PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V8_S0_CPU_VCCPLL_R

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

PPVTTDDR_S3

PP1V8_S0

PP3V42_G3H

PP1V8_S0

MIN_NECK_WIDTH=0.2 MM

PP1V5_S3RS0

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mm

PP1V5_S0

VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=2 mm

PP1V5_S3

PP1V5_S3 PP1V5_S3

PP1V5_S3RS0

PP1V5_S0 PP1V5_S0

PP1V5_S0

PP1V8_S0

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2 MM

PP3V42_G3H

PPBUS_S5_HS_COMPUTING_ISNS

PPBUS_G3H

PPBUS_S5_HS_COMPUTING_ISNS

PP3V3_S3

PP1V05_S0_PCH_VCCADPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

PP3V42_G3H

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPDCIN_G3H

MAKE_BASE=TRUE

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE

PPBUS_G3H

PP1V5_S0

PP1V5_S3RS0

PPBUS_G3H

PP15V_T29

PPBUS_G3H

PP3V42_G3H

PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H

PP3V3_S5

PPVCORE_S0_CPU

PP1V5_S0

PP1V5_S3RS0

PP0V75_S0_DDRVTT

PP1V5_S3_CPU_VCCDQ

PP1V05_S0

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V

MAKE_BASE=TRUE

PP5V_S5

PP3V3_S4

VOLTAGE=0.9V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVCCSA_S0_CPUPPVCCSA_S0_CPU

PP3V3_S3

MIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3

MIN_LINE_WIDTH=0.50MM

PP3V3_S4

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP5V_S0

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP5V_S0

VOLTAGE=5V

MIN_LINE_WIDTH=0.4 MM

PP5V_S3

VOLTAGE=3.3V

PP3V3_S4

MIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.50MM

PP3V3_S5

PP3V3_S4

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5

MIN_NECK_WIDTH=0.2 MM

PP3V3_SUS

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP3V3_SUS

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_SUS

8 OF 109

7 OF 86

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

7

39 40

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

7

27 29 30 67

7

54 66 72

7 8

36 76

7 8

36 76

7

16 19 26 34 35 36

7

16 19 26 34 35 36

7

16 19 26 34 35 36

7

35 36

7

35 36

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

6 7 8

18 24 26 30 31 32

33 48 50 54 55 72 73

7

49 63

64

7

50 66

36

6 7

26 43 45 46 47 48 53 63 64

73

7

23 71

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72 6 7

30 32 42 43 44 46 57 59 60

61 66 67 72 6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

6 7 8

18 24 26

30 31 32 33 48 50 54 55 72 73

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

7

54 66 72

7

22 72

7

16 19 26 34 35 36

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

7

22 72

7

16 17

20 26

7

16 17 20 26

6 7

27 29 30

67 72

6 7

30 32 42

43 44 46 57 59

60 61 66 67 72

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7

22 42 47

52 54 65 68 70

72 73 77

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

7

22 72

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

7

31 67

7

49 63 64

7

49 63 64

7

50 65 67 68 69 70

7

50 65 67 68 69 70

7

50 65 67 68 69 70

7

50 66

7

50 66

7

50 66

7

16 19 26 34 35 36

7

40 41

7

40 41

6 7

26 37 71 73

6 7

26 43 45 46 47 48 53 63 64

73

6 7

26 37 71 73

7

16 17 20 26

7

27 29 30 67

7

27 29 30 67

7

27 29 30 67

7

40 41

7

39 40

7

39 40 41

7

23 71

6 7

26 37 71 73

7

39 40 41

6 7

12 15 65

7

39 40 41

6 7

26 37 71 73

6 7

26 37 71 73

6 7 8

36 40 49 50 63 64 77

7

39 40 41

7

23 71

7

40 41

7

39 40

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

7

54 66 72

7

54 66 72

6 7 9

12

14 49 69

6 7 9

12

14 49 69 6 7 9

12

14 49 69

6 7 9

12

15 49 69

7

12 15

7

10 12

14

7

10 12 14

7

12 14

7

35 36

7

20 71

7

20 71

6 7 9

12 15 49 69

6 7 9

12

15 49 69

6 7 9

12

15 49 69

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73 6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73 6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73 6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73 6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73 6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68

70 73

7

12 14

7 31 67

6 7

14 17 20 22 26 71

6 7

14 17 20 22 26 71

6 7

14 17 20 22 26 71

6 7

26 43 45 46 47 48 53 63 64

73

6 7

26 43 45 46 47 48 53 63 64

73

6 7

14 17 20 22 26 71

6 7

14 17 20 22 26 71

6 7

14 17 20 22 26 71

6 7

10 12 15 30 72 73 85

7

16 20 22 26 42 57 71

6 7

27 29 30 67 72

6 7

27 29 30 67 72

6 7

27 29 30 67 72

6 7

27 29 30 67 72

6 7

27 29 30 67 72

6 7

27 29 30 67 72

6 7

10 12 15 30 72 73 85

7

16 20 22 26 42 57 71

7

16 20 22 26 42 57 71

7

16 20 22 26 42 57 71

6 7

14 17 20 22 26 71

6 7

14 17 20 22 26 71

6 7

26 43 45 46 47 48 53 63 64

73

6 7

26 43 45 46

47 48 53 63 64

73

7

50 65 67 68 69 70

7

50 65 67 68 69 70

7

50 65 67 68 69 70

6 7 8

36

40 49 50

63 64 77

7

50 65

67 68 69

70

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

7

20 71

6 7

26 43 45 46

47 48 53

63 64 73

7

49 63 64

6 7 8

36 40 49 50 63 64 77

6 7 8

36 40 49

50 63 64 77

6 7 8

36 40 49 50 63 64 77

7

16 20 22 26 42 57 71

6 7

10 12 15 30 72 73 85

6 7 8

36 40 49 50 63 64 77

7 8

36 76

6 7 8

36 40 49 50 63 64 77

6 7 8

36 40 49 50 63 64 77

6 7

26 43 45 46 47 48 53 63 64

73

6 7

26 43 45 46 47 48 53 63 64

73 6 7

26 43 45 46 47 48 53 63 64

73 6 7

26 43 45 46 47 48 53 63 64

73 6 7

26 43 45 46 47 48 53 63 64

73

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 9

12 14 49 69

7

16 20 22 26 42 57 71

6 7

10 12 15 30 72 73 85

7

27 29 30 67

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23 36 40 45 68 70 73

7

54 66 72

7

46 53 54 72

6 7

12 15 65

6 7

12 15 65

6 7 8

18

24 26 30 31 32 33 48 50 54 55

72 73

6 7 8

18 24 26 30 31 32 33 48 50 54 55 72 73

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

6 7 8

18 24 26 30 31 32

33 48 50

54 55 72 73

6 7 8

18 24 26 30

31 32 33 48 50 54 55 72 73

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

7

46 53 54 72

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52

54 57 61 62 71 72 73 74 75 77

85

6 7 8

12 16 17 18 19 20 22 23 26 27 29 33 36 37 40 41 42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7

8

12

16

17 18 19 20 22 23 26 27 29 33 36 37 40 41 42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7 8 12 16 17 18 19 20 22 23 26 27 29 33 36 37 40 41 42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46 48 49 50 51 52 54 57

61

62 71 72 73 74 75 77 85

6 7

8

12 16 17 18 19 20 22 23 26 27

29

33 36 37 40 41 42 46 48 49

50

51 52 54 57 61 62 71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37

40 41 42 46 48 49 50 51 52

54

57 61 62 71 72 73 74 75 77

85

6 7

8

12 16 17 18 19 20 22 23 26 27

29

33 36 37 40 41 42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36

37 40 41 42 46 48 49 50 51

52

54 57 61 62 71 72 73 74 75

77

85

6 7

8

12

16

17 18 19 20 22 23 26 27 29

33 36 37 40 41 42 46 48

49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33

36 37 40 41 42 46 48 49 50

51

52 54 57 61 62 71 72 73 74

75

77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33

36 37 40 41 42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33

36 37 40 41 42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33

36 37 40 41 42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48

49 50 51 52 54 57 61 62 71 72

73

74 75 77 85

6 7

8

12 16 17 18 19 20 22 23 26

27 29 33 36 37 40

41 42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7

8

12 16 17 18 19 20 22 23 26 27 29

33 36 37 40 41 42

46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7

8

12 16 17 18 19 20 22 23 26

27 29

33 36 37 40 41 42 46 48 49

50 51 52

54 57 61 62 71 72 73 74

75

77 85

6 7 8 12 16 17 18 19 20 22 23 26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54

57 61 62 71 72 73 74 75 77 85 6 7 8 12 16 17 18 19 20 22 23 26 27 29 33 36 37 40 41 42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33

36 37 40 41 42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49

50 51 52 54 57 61 62 71 72

73 74

75 77 85

6 7

8

12

16

17 18 19 20 22 23 26 27 29

33 36 37 40 41

42 46 48 49 50 51 52 54 57 61 62 71 72 73 74 75 77 85

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7

22 42 47 52 54 65 68 70 72

73 77

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

7

46 53 54 72

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24

26

30 46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46

56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24

26 30 46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

7

16 17 18 19 20 22 46 71 72

73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46

71 72 73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72 73

OUT

IN

OUT

IN

OUT

IN

OUT

IN

EN

ILIM

FAULT*

GND

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

T29 JTAG

BELOW CPU

FAN STANDOFF

CPU signals

LEFT OF CPU

Digital Ground

Heat Spreader Holes for T29, PCH

HEATSINK STANDOFFS

T29 DP Ports

EMI TALL POGO PINS

EMI IO (SHORT) POGO PINS

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

Unused T29 Ports

Unused PGOOD signal

DPA PWR SW : Nostuff, Backup

MLB MOUNTING (TO TOPCASE) SCREW HOLES

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0904

1

2.0DIA-TALL-EMI-MLB-M97-M98

SM

ZS0905

1

1.4DIA-SHORT-EMI-MLB-K19-K24

SM

ZS0903

1

1.4DIA-SHORT-EMI-MLB-K19-K24

SM

ZS0900

1

3R2P5

OMIT

Z0911

1

3R2P5

OMIT

Z0908

1

3R2P5

OMIT

Z0906

1

2.0DIA-TALL-EMI-MLB-M97-M98

SM

ZS0906

1

1.4DIA-SHORT-EMI-MLB-K19-K24

SM

ZS0908

1

SM

1.4DIA-SHORT-EMI-MLB-K19-K24

ZS0901

1

SM

1.4DIA-SHORT-EMI-MLB-K19-K24

ZS0909

1

1.4DIA-SHORT-EMI-MLB-K19-K24

SM

ZS0902

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0907

1

3R2P5

OMIT

Z0912

1

OMIT

3R2P5

Z0909

1

OMIT

3R2P5

Z0910

1

3R2P5

OMIT

Z0907

1

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0905

1

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902

1

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0920

1

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0904

1

NO STUFF

MF-LF 402

1/16W

5%

10K

R0906

1

2

1/16W

NO STUFF

10K

5%

MF-LF

402

R0905

1

2

402

0

5% 1/16W MF-LF

R0910

1 2

83

34 34

8

72

8

67

MF-LF

1/16W

5%

402

100K

R0908

1

2

5% 1/16W MF-LF

402

2.2K

R0920

1

2

MF-LF

2.2K

402

1/16W

5%

R0921

1

2

MF-LF

1/16W

402

5%

2.2K

R0922

1

2

2.2K

402

5% 1/16W MF-LF

R0923

1

2

8

19 23 34

8

19 34

8

19 34

8

19 23 34

8

19 34

8

19 34

2.2K

5% 1/16W MF-LF

402

R0925

1

2

5% 1/16W MF-LF

402

2.2K

R0924

1

2

34 34

STDOFF-4.0OD1.85H-SM

Z0950

1

STDOFF-4.0OD1.85H-SM

Z0951

1

STDOFF-4.0OD1.85H-SM

Z0952

1

5% 1/16W

10K

402

MF-LF

R0916

1

2

5%

402

10K

1/16W MF-LF

R0915

1

2

201

1/20W

MF

5%

0

NO STUFF

R0917

1 2

5%

NO STUFF

0

MF

1/20W

201

R0918

1 2

TPS2553

NOSTUFF

SOT-23

U0950

3 4

2

5

1

6

1/16W MF-LF 402

5%

20K

NOSTUFF

R0950

1

2

5%

1/8W

805

MF-LF

0

T29BST:N

R0960

1 2

0.01UF

10% 10V X5R 201

C0960

1

2

0.01UF

10% 10V X5R 201

C0962

1

2

0.01UF

10% 10V X5R 201

C0970

1

2

10%

0.01UF

10V X5R 201

C0964

1

2

201

1/20W

MF

5%

51

R0970

1 2

10%

0.01UF

10V X5R 201

C0971

1

2

201

1/20W

MF

5%

51

R0971

1 2

51

MF

201

5%

1/20W

R0973

1 2

0.01UF

10% 10V X5R 201

C0973

1

2

0.01UF

10% 10V X5R 201

C0972

1

2

51

1/20W

5%

201

MF

R0972

1 2

NO STUFF

10K

5%

402

MF-LF

1/16W

R0903

1

2

NO STUFF

10K

1/16W MF-LF 402

5%

R0904

1

2

SYNC_DATE=05/15/2010

Signal Aliases

SYNC_MASTER=K91_MLB

NC_PCH_CLKOUT_DPP

DP_A_BIAS0

TP_ISSP_SCLK_P1_1

MAKE_BASE=TRUE

T29_A_BIAS_R2DN0

T29_A_BIAS

JTAG_ISP_TCK

MAKE_BASE=TRUE

TP_ISSP_SDATA_P1_0 TP_ISSP_SDATA_P1_0

VOLTAGE=3.3V

T29_A_BIAS_R2DP0

T29_A_BIAS_R2DP1

T29_A_BIAS

VOLTAGE=3.3V

T29_A_BIAS_D2RP1

VOLTAGE=3.3V

T29_A_BIAS_D2RN1

T29_A_BIAS_R2DN1

VOLTAGE=3.3V

DP_A_BIAS2

NC_FSB_CLK133M_PCH_N

PP15V_T29PPBUS_G3H

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FSB_CLK133M_PCH_P

DP_IG_ML_P<3..0>

DP_EXTA_AUXCH_C_N

NC_FSB_CLK133M_PCH_P

TP_ISSP_SCLK_P1_1

PP3V3_SW_DPAPWR

T29_A_HV_EN

SMC_S4_WAKESRC_EN

PP3V3_S5

DPAPWR_ILIM

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2RP

NC_PEG_CLK100MN

MAKE_BASE=TRUE

NC_USB_HUB2_OCS4

MAKE_BASE=TRUE

PU_USB_HUB2_PRT4_P

MAKE_BASE=TRUE

PU_USB_HUB2_PRT4_N

JTAG_ISP_TDI

MEMVTT_EN

TP_DP_IG_B_MLP<3..0>

NC_PCIE_CLK100M_EXCARDN NC_PCIE_CLK100M_EXCARDP

T29_A_RSVD_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FSB_CLK133M_PCH_N

JTAG_ISP_TDO

MAKE_BASE=TRUE

JTAG_ISP_TDO

NC_PCIE_EXCARD_D2RP NC_PCIE_EXCARD_R2D_CN

=PEG_R2D_C_N<11..8> =PEG_D2R_P<11..8>

DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

T29_LSEO<2>

T29_R2D_C_P<2..3>

T29_D2R_N<2..3>

USB_T29A_P

PCIE_PCH_R2D_C_N<5..8>

NC_PCH_CLKOUT_DPN

NC_PCH_CLKOUT_DPP

TRUE

MAKE_BASE=TRUE

NC_USB_HUB1_OCS4

MAKE_BASE=TRUE

DP_EXTA_DDC_DATA

=PEG_D2R_N<11..8>

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_CN

DP_IG_C_CTRL_CLK

DP_T29SNK0_AUXCH_C_N

T29_LSOE<3>

MAKE_BASE=TRUE

T29_LSEO<3>

T29_LSOE<2>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_BCM57765_CE_L_MS_INS_L

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

NC_LVDS_IG_B_DATAN<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

DP_T29SNK0_AUXCH_C_P

MAKE_BASE=TRUE

DP_T29SNK1_HPD

MAKE_BASE=TRUE

DP_T29SNK1_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_T29SNK1_ML_C_N<3..0>

MAKE_BASE=TRUE

DP_T29SNK1_AUXCH_C_P

MAKE_BASE=TRUE

DP_T29SNK1_AUXCH_C_N

MAKE_BASE=TRUE

TP_BCM57765_TRAFFICLED_L

MAKE_BASE=TRUE

LCD_IG_PWR_EN

MAKE_BASE=TRUE

LCD_BKLT_PWM

MAKE_BASE=TRUE

LVDS_DDC_DATA

LVDS_DDC_CLK

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

DP_IG_D_CTRL_CLK

MAKE_BASE=TRUE

DP_T29SNK0_AUXCH_C_N

MAKE_BASE=TRUE

DP_T29SNK0_ML_C_N<3..0>

MAKE_BASE=TRUE

PEG_R2D_C_N<11..8> PEG_D2R_P<11..8> PEG_D2R_N<11..8>

=PEG_R2D_C_P<11..8>

DP_T29SNK1_HPD

DP_IG_C_CTRL_DATA

LCD_BKLT_EN

TP_BCM57765_TRAFFICLED_L

DP_T29SNK1_AUXCH_C_N

DP_T29SNK1_AUXCH_C_P

TP_DP_IG_D_MLN<3..0>

TP_DP_IG_D_MLP<3..0>

DP_T29SNK0_AUXCH_C_P

TP_DP_IG_C_MLN<3..0>

TP_DP_IG_C_MLP<3..0>

DP_T29SNK0_HPD

LCD_BKLT_PWM

LCD_IG_PWR_EN

LVDS_DDC_DATA

LVDS_DDC_CLK

NC_LVDS_IG_A_DATAN<3>

NC_LVDS_IG_A_DATAP<3>

LVDS_IG_B_DATA_N<0..3>

LVDS_IG_B_DATA_P<0..3>

TP_LVDS_IG_B_CLKN

TP_LVDS_IG_B_CLKP

PU_USB_HUB2_PRT4_P

NC_BCM57765_CE_L_MS_INS_L

TP_DDRREG_PGOOD

TP_P1V5S3RS0_RAMP_DONETP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

DP_T29SNK0_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_T29SNK0_HPD

MAKE_BASE=TRUE

PCIE_T29_R2D_C_P<3..0>

MAKE_BASE=TRUE

PCIE_T29_D2R_P<3..0>

MAKE_BASE=TRUE

PCIE_T29_D2R_N<3..0>

PCIE_T29_R2D_C_N<3..0>

MAKE_BASE=TRUE

NC_T29_D2RN<2..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_T29_R2D_CN<2..3>

NO_TEST=TRUE

NC_T29_R2D_CP<2..3>

MAKE_BASE=TRUE

T29_R2D_C_N<2..3>

DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

DP_EXTA_HPD

MAKE_BASE=TRUE

DP_EXTA_DDC_CLK

DP_EXTA_HPD

DP_IG_C_CTRL_DATA

MAKE_BASE=TRUE

DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

DP_IG_D_CTRL_CLK

MAKE_BASE=TRUE

DP_EXTA_DDC_DATA

PP3V3_S0

PU_USB_HUB2_PRT4_N

MAKE_BASE=TRUE

NC_T29_D2RP<2..3>

NO_TEST=TRUE

USB_EXTC_P

TP_CPU_VTT_SELECT

T29_D2R_P<2..3>

USB_EXTC_N

T29_A_RSVD_P

MAKE_BASE=TRUE

MEMVTT_EN

DP_EXTA_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_EXTA_AUXCH_C_P

MAKE_BASE=TRUE

DP_EXTA_AUXCH_C_P

DP_EXTA_AUXCH_C_N

MAKE_BASE=TRUE

DP_IG_ML_N<3..0>

MAKE_BASE=TRUE

DP_EXTA_ML_C_N<3..0>

DP_EXTA_DDC_CLK

PP3V3_S0

PEG_R2D_C_P<11..8>

MAKE_BASE=TRUE

FW643_WAKE_L

MAKE_BASE=TRUE

TP_SMC_EXCARD_PWR_EN

NC_PCIE_EXCARD_D2RN

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARDN

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_CPNC_PCIE_EXCARD_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_PCH_CLKOUT_DPN

TRUE

MAKE_BASE=TRUE

NC_PCIE_PCH_D2RN<5..8>

PCIE_PCH_D2R_N<5..8>

MAKE_BASE=TRUE

TRUE

NC_PCIE_PCH_R2D_CN<5..8>

MAKE_BASE=TRUE

TRUE

NC_PCIE_PCH_D2RP<5..8>

PCIE_PCH_D2R_P<5..8>

MAKE_BASE=TRUE

NC_PEG_CLK100MPNC_PEG_CLK100MP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PCH_R2D_CP<5..8>

PCIE_PCH_R2D_C_P<5..8>

NC_PEG_CLK100MN

MIN_LINE_WIDTH=0.5 MM VOLTAGE=12.6V

MIN_NECK_WIDTH=0.375 MM

MAKE_BASE=TRUE

PPBUS_SW_BKL

PPBUS_SW_LCDBKLT_PWR

MAKE_BASE=TRUE

NC_USB_HUB1_OCS4

PU_USB_HUB2_PRT4_P

NC_USB_HUB2_OCS4

LCD_BKLT_EN

MAKE_BASE=TRUE

PP3V3_S3

PU_USB_HUB2_PRT4_N

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

USB_T29A_N

MAKE_BASE=TRUE

FW_PLUG_DET_L

FW643_WAKE_L

TP_SMC_EXCARD_PWR_EN

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2RN

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_EXCARDP

DP_EXTA_AUXCH_C_P

TP_DP_IG_B_MLN<3..0>

DP_EXTA_AUXCH_C_N

JTAG_ISP_TDI

MAKE_BASE=TRUE

JTAG_ISP_TCK

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GND

VOLTAGE=0V

9 OF 109

8 OF 86

8

16

75

8

53

75

8

75 76

8

53

8

53

75

8

75 76

76

75

8

80

7

36 76

6 7

36 40 49 50 63 64 77

8

80

8

17 75

80 81

8

80

8

53

75 76

36 75 76 45 46 73 76

6 7

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

8

16

8

16 81

8

24

8

24

8

24

8

30 67

17

8

16 81

8

16 81

75 80

8

80

8

16

8

16

9

8

17

8

67

24 80

8

16

8

16

8

24

8

17 75

9

8

16

8

17

8

17 34 83

8

37

6 8

18 80

6 8

18 80

18

8

18 80

8

18 80

8

17 34 83

8

17 34

34 83

8

17 34 83

8

17 34 83

8

37

8

18 74

8

18 77

6 8

18 74

6 8

18 74

18

8

17

8

17 34 83

34 83

78

9

8

17 34

8

17

8

18 77

8

37

8

17 34 83

8

17 34 83

17

8

17 34 83

17

8

17 34

8

18 77

8

18 74

6 8

18 74

6 8

18 74

8

18 80

8

18 80

80

6 8

18 80

6 8

18 80

8

24

8

37

8

72

34 83

8

17 34 34

81

34 81

34

8

17

8

17 75

8

17 75

8

17 75

8

17

8

17

8

17

8

17 75

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

8

24

34

24 80

8

24 80

75 80

8

30 67

75 81

8

17 75

80 81

8

17 75 80 81

8

17 75 80 81

80

75 81

8

17 75

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

78

8

39 40

8

16

8

16 81

8

16

8

16

8

16

8

16 81

8

16 81

8

16 81

8

77

8

77

8

24

8

24

8

24

8

18 77

6 7

18 24 26 30 31 32 33 48

50 54 55 72 73

8

24

8

24 80

8

19 40

8

19 40

8

39 40

8

16

8

16 81

8

17 75 80 81

17

8

17 75 80 81

IN IN IN IN

IN

OUT

IN

IN IN IN IN IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT OUT OUT

OUT

IN

IN IN IN IN IN

IN

IN IN

OUT

OUT OUT OUT OUT

IN IN

IN

IN IN

NC

EDP_TX_3

EDP_TX_0 EDP_TX_1 EDP_TX_2

EDP_TX_2* EDP_TX_3*

EDP_TX_0* EDP_TX_1*

EDP_AUX

EDP_AUX*

EDP_COMPIO

EDP_HPD

EDP_ICOMPO

FDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3

FDI1_TX_1

FDI1_TX_0

FDI1_TX_2 FDI1_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI1_TX_3*

FDI1_TX_2*

FDI0_TX_1

FDI0_TX_0

FDI0_TX_2

FDI1_TX_1*

FDI0_TX_3*

FDI1_TX_0*

FDI0_TX_2*

FDI0_TX_1*

DMI_TX_1* DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI0_TX_0*

DMI_RX_2*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0*

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_2*

PEG_RX_0* PEG_RX_1*

PEG_RX_3* PEG_RX_4* PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8* PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0 PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7 PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_1* PEG_TX_2*

PEG_TX_0*

PEG_TX_3* PEG_TX_4* PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8* PEG_TX_9*

PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2 PEG_TX_3 PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

(1 OF 9)

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

VSS_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

VCC_VAL_SENSE

CFG_17

CFG_16

CFG_15

CFG_10 CFG_11 CFG_12 CFG_13 CFG_14

CFG_5 CFG_6 CFG_7 CFG_8 CFG_9

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4

RSVD_28 RSVD_29

RSVD_30

RSVD_32

RSVD_31

RSVD_34

RSVD_33

RSVD_35 RSVD_36 RSVD_37 RSVD_38

RSVD_40

RSVD_39

RSVD_42 RSVD_43

RSVD_41

RSVD_44

RSVD_45

DC_TEST_A4 DC_TEST_C4

DC_TEST_D1

DC_TEST_D3

DC_TEST_A58

DC_TEST_C59

DC_TEST_A59

DC_TEST_C61

DC_TEST_A61

DC_TEST_D61

DC_TEST_BE61

DC_TEST_BD61

DC_TEST_BG61

DC_TEST_BE59

DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BE3

DC_TEST_BG3

DC_TEST_BE1 DC_TEST_BD1

DC_TEST_BG1

VCC_DIE_SENSE

RSVD_7

RSVD_6

RSVD_8 RSVD_9 RSVD_10

RSVD_12

RSVD_11

RSVD_13 RSVD_14 RSVD_15

RSVD_17

RSVD_16

RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22

RSVD_24

RSVD_23

RSVD_25

RSVD_27

RSVD_26

RESERVED

(5 OF 9)

OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

Note. VOLTAGE=1.25V

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

This would require routing processor signal balls BE7 and BG7 for Sandy Bridge 2-core to SO-DIMM connectors directly. FETs are needed in order to avoid potential leakage while system is in S3 state.

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

NOTE: Intel is investigating future processor VREF_DQ generation to replace M1 and M2.

FOR SANDYBRIDGE PROCESSOR

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

This signal can be left as no-connect if entire eDP interface is disabled.

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.

If HPD is disabled while eDP interface is still enabled,

(refer to latest Processor EDS for DC specifications).

to convert the active high signal from Embedded DisplayPort sink device

Therefore, an inverting level shifter is required on the motherboard

NOTE: The EDP_HPD processor input is a low voltage active low signal.

shared with other interfaces.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating

Intel Doc 438297 Huron River SFF DG rev1.0 section 2.2.1 recommendation.

NOTE: Intel validation sense lines per

to low voltage signals for the processor

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

These can be Placed close to J2500 and Only for debug access

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

even if internal Graphics is disabled since they are

17 78

6

8

6

8

6

8

6

8

6

8

6

8

6

8

6

1/16W

PLACE_NEAR=U1000.G3:12.7MM

MF-LF

402

24.9

1%

R1010

1 2

9

23 78

9

23 78

9

23 78

9

23 78

9

23 78

9

23 78

9

23 78

9

23 78

9

23

1K

MF-LF

402

1/16W

5%

NOSTUFF

R1042

1

2

5%

1K

NOSTUFF

1/16W

402

MF-LF

R1049

1

2

5%

1K

NOSTUFF

MF-LF

1/16W

402

R1043

1

2

5%

1K

NOSTUFF

402

1/16W MF-LF

R1041

1

2

5%

1K

NOSTUFF

1/16W MF-LF

402

R1040

1

2

17 78

402

PLACE_NEAR=U1000.AF3:12.7MM

24.9

MF-LF

1/16W

1%

R1030

1 2

MF-LF

10K

EDP

PLACE_NEAR=U1000.AG11:12.7MM

1%

1/16W

402

R1031

1 2

1/16W MF-LF

5%

0

402

NOSTUFF

R1023

1 2

1% 1/16W MF-LF 402

1K

NOSTUFF

R1022

1

2

MF-LF

5%

0

1/16W

402

NOSTUFF

R1021

1 2

402

MF-LF

1/16W

1%

1K

NOSTUFF

R1020

1

2

5% 1/16W MF-LF

1K

EDP

402

R1044

1

2

NOSTUFF

1K

1/16W

402

5%

MF-LF

R1046

1

2

1K

MF-LF

402

1/16W

5%

R1045

1

2

1/16W MF-LF

1K

402

5%

NOSTUFF

R1047

1

2

1%

49.9

MF-LF

402

1/16W

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.H43:50.8MM

NOSTUFF

R1064

1

2

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.H45:50.8MM

MF-LF

NOSTUFF

1%

402

1/16W

49.9

R1070

1

2

PLACE_NEAR=U1000.K43:50.8MM

PLACE_SIDE=BOTTOM

NOSTUFF

49.9

1%

402

MF-LF

1/16W

R1065

1

2

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.K45:50.8MM

49.9

402

MF-LF

1/16W

1%

NOSTUFF

R1071

1

2

SANDY-BRIDGE

OMIT_TABLE

CRITICAL

BGA

MOBILE-2C-35W

U1000

N3

M2

P7

P6

P3

P1

P11

P10

K3

K1

M7

M8

P4

N4

T3

R2

AF4

AG4

AF3

AG11

AD2

AC1

AC3

AA4

AC4

AE10

AE11

AE6

AE7

AA11

AA10

U6

U7

W10

W11

W3

W1

AA7

AA6

AC12

AG8

W7

W6

T4

V4

AA3

Y2

AC8

AC9

U11

G3 G1 G4

K22

H22

K19

J21

F8

G8

C8

A8

C5

B6

H6

H8

F6

E5

K6

K7

C21

B22

D19

D21

C19

A19

D16

D17

C13

B14

D12

D13

C11

A11

C9

B10

F22

G22

A23

C23

K13

J14

G13

H13

K10

M10

G10

F10

D8

D9

K4

J4

D24

D23

E21

F21

G19

H19

B18

C17

K17

K15

G17

F17

E14

F14

C15

A15

OMIT_TABLE

CRITICAL

BGA

MOBILE-2C-35W

SANDY-BRIDGE

U1000

B50 C51

K49 K53 F53 G53 L51 F51 D52 L53

B54 D53 A51 C53 C55 H49 A55 H51

A4

A58 A59

A61

BD1

BD61

BE1

BE3

BE59

BE61

BG1

BG3

BG4

BG58

BG59

BG61

C4

C59

C61

D1

D3

D61

AG13

AH2

AM14 AM15

AT21

AT49

AU19 AU21

AV19

AY21

AY22

BA19

BA22

BB19

BB21

BD21 BD22 BD25 BD26

BE22

BE24

BE26

BE7

BF23

BG22

BG26

BG7

H48

K24

K48

L42 L45 L47

M13 M14

N42

N50

P13

U14 W14

H45

F48

H43 K43

K45

51 85

CPU DMI/PEG/FDI/RSVD

PP0V75_S3_MEM_VREFDQ_B

NC_PEG_R2D_CN<13>

NC_PEG_R2D_CN<12>

=PEG_R2D_C_N<10> =PEG_R2D_C_N<11>

NC_PEG_R2D_CN<14>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<10> =PEG_R2D_C_P<11>

TP_CPU_VCC_DIE_SENSE

PP0V75_S3_MEM_VREFDQ_A

PPVCORE_S0_CPU

CPU_CFG<16> CPU_CFG<3>

CPU_CFG<0>

CPU_CFG<1>

CPU_CFG<2>

NC_PEG_R2D_CP<15>

NC_PEG_R2D_CP<14>

NC_PEG_R2D_CP<12>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_P<0> =PEG_R2D_C_P<1>

NC_PEG_R2D_CN<15>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<6> =PEG_R2D_C_N<7>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<1>

NC_PEG_D2RP<15>

NC_PEG_D2RP<14>

NC_PEG_D2RP<13>

NC_PEG_D2RP<12>

=PEG_D2R_P<11>

=PEG_D2R_P<9>

=PEG_D2R_P<8>

=PEG_D2R_P<7>

=PEG_D2R_P<5> =PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2> =PEG_D2R_P<3>

=PEG_D2R_P<1>

=PEG_D2R_P<0>

NC_PEG_D2RN<15>

NC_PEG_D2RN<13> NC_PEG_D2RN<14>

=PEG_D2R_N<11> NC_PEG_D2RN<12>

=PEG_D2R_N<10>

=PEG_D2R_N<8>

CPU_PEG_COMP DMI_S2N_N<0> DMI_S2N_N<1>

DMI_S2N_N<3>

DMI_N2S_N<0>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<2>

FDI_DATA_N<0>

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<2>

DMI_N2S_N<1>

FDI_DATA_N<1> FDI_DATA_N<2>

FDI_DATA_N<4>

FDI_DATA_N<3>

FDI_DATA_N<5>

FDI_DATA_P<2>

FDI_DATA_P<0> FDI_DATA_P<1>

FDI_DATA_N<6> FDI_DATA_N<7>

FDI_INT

FDI_FSYNC<1>

FDI_FSYNC<0>

FDI_DATA_P<7>

FDI_DATA_P<6>

FDI_DATA_P<3>

FDI_LSYNC<0>

DMI_N2S_N<3>

FDI_LSYNC<1> EDP_COMP

NC_EDP_AUXN NC_EDP_AUXP

NC_EDP_TXN<1>

NC_EDP_TXN<0>

NC_EDP_TXN<3>

NC_EDP_TXN<2>

NC_EDP_TXP<2>

NC_EDP_TXP<1>

NC_EDP_TXP<0>

NC_EDP_TXP<3>

TP_CPU_DC_TEST_BD1

CPU_DC_TEST_C4_BE1_BG1

CPU_DC_TEST_C4_BE3_BG3

TP_CPU_DC_TEST_BG4

TP_CPU_DC_TEST_BG58

CPU_DC_TEST_BG59_BG61

TP_CPU_DC_TEST_BD61

CPU_DC_TEST_BE59_BE61

TP_CPU_DC_TEST_D61

CPU_DC_TEST_C61_A61

CPU_DC_TEST_C59_A59

TP_CPU_DC_TEST_A58

TP_CPU_DC_TEST_D1

CPU_DC_TEST_C4_D3

TP_CPU_DC_TEST_A4

CPU_MEM_VREFDQ_B

CPU_MEM_VREFDQ_A

CPU_CFG<2>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<6>

CPU_CFG<5>

CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<11>

CPU_CFG<10>

CPU_CFG<15> CPU_CFG<16> CPU_CFG<17>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3>

CPU_CFG<7>

CPU_CFG<0>

=PEG_D2R_N<5>

=PEG_D2R_N<7>

=PEG_D2R_N<9>

=PEG_D2R_N<6>

PP1V05_S0

FDI_DATA_P<4> FDI_DATA_P<5>

CPU_THERMD_N

CPU_THERMD_P

CPU_CFG<13>

CPU_CFG<4>

=PEG_D2R_P<10>

PPVCORE_S0_AXG

CPU_CFG<3>

CPU_CFG<1>

=PEG_D2R_N<1>

=PEG_D2R_N<0>

CPU_MEM_VREFDQ_A

PP1V05_S0

EDP_HPD

CPU_CFG<6> CPU_CFG<5> CPU_CFG<4>

CPU_MEM_VREFDQ_B

NC_PEG_R2D_CP<13>

=PEG_R2D_C_P<9>

DMI_S2N_P<3>

CPU_AXG_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_VCC_VALSENSE_N

CPU_VCC_VALSENSE_P

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_N<2>

10 OF 109

9 OF 86

29 31

27 31

6 7

12 14 49 69

9

23

9

23 78

9

23 78

9

23 78

9

23 78

78

6

9

23 78

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7

12 15 49

69

9

6 7 9

10

12 14 16

17 20 22

23 36 40

45 68 70

73

9

23 78

9

23 78

9

23 78

9

BI BI BI BI BI

IN

OUT

IN IN

OUT

BI

NC

OUT

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_DRAMRST*

BCLK_ITP

BCLK_ITP*

DPLL_REF_CLK*

DPLL_REF_CLK

BCLK*

BCLK

RESET*

SM_DRAMPWROK

UNCOREPWRGOOD

PM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

TCK

PRDY*

THERMTRIP*

CATERR*

PROCHOT*

PECI

(2 OF 9)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

IN

OUT

IN IN

IN

OUT

IN

IN IN

IN

OUT

BI BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

Unused eDP CLK

(IPU)

23 78

23

10K

1/16W

402

5%

MF-LF

R1111

1

2

17 30 78

19 23 78

30

16 78

17

19 78

46 68 78

19 45 78

MF-LF

402

1/16W

1%

75

R1126

1

2

1/16W

402

200

1%

MF-LF

R1114

1

2

MF-LF

1/16W

402

25.5

1%

R1113

1

2

402

1/16W MF-LF

140

1%

R1112

1

2

78

OMIT_TABLE

CRITICAL

BGA

SANDY-BRIDGE

MOBILE-2C-35W

U1000

J3 H2

N59 N58

G58 E55 E59 G55 G59 H60 J59 J61

C49

K58

AG3 AG1

A48

C48

N53 N55

C57

F49

C45

D44

BE45

AT30

BF44 BE43 BG43

L56

M60 L59

D45

L55 J58

B46

MF-LF

402

1/16W

5%

56

R1103

12

1/16W

5%

1K

MF-LF 402

R1140

1

2

402

MF-LF

5% 1/16W

1K

R1141

1

2

402

MF-LF

1/16W

62

5%

R1101

1

2

NOSTUFF

402

1/16W

1K

MF-LF

5%

R1100

1

2

23 78

200

1/16W

402

MF-LF

1%

R1120

1

2

130

402

1%

MF-LF

1/16W

R1121

12

16 78

17 78

NOSTUFF

MF-LF

1/16W

5%

51

402

R1104

1

2

1/16W MF-LF

1%

402

43.2

R1125

12

23 26

1K

NOSTUFF

MF-LF

1/16W

402

5%

R1102

1

2

23 26 78

23 78

CPU CLOCK/MISC/JTAG

DMI_CLK100M_CPU_N

DMI_CLK100M_CPU_P

DPLL_REF_CLKP DPLL_REF_CLKN

ITPCPU_CLK100M_P ITPCPU_CLK100M_N

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

XDP_CPU_TMS XDP_CPU_TRST_L

PP1V05_S0

PLT_RST_BUF_L

PP1V05_S0

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1>

PP1V05_S0_CPU_VCCPQE

XDP_CPU_TDI

XDP_CPU_TCK

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TDO

CPU_PECI

CPU_CATERR_L

CPU_SM_RCOMP<2>

PM_THRMTRIP_L

CPU_PWRGD

CPU_PROCHOT_R_L

CPU_MEM_RESET_L

PM_MEM_PWRGD_R

PM_SYNC

CPU_PROC_SEL_L

PM_MEM_PWRGD

PP1V5_S3RS0

CPU_PROCHOT_L

PLT_RESET_LS1V1_L

11 OF 109

10 OF 86

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

78

7

12 14

78

6 7

12 15 30 72 73 85

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SA_MA_14 SA_MA_15

SA_MA_12 SA_MA_13

SA_MA_11

SA_MA_9

SA_MA_10

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_1

SA_MA_0

SA_DQS_7

SA_DQS_5 SA_DQS_6

SA_DQS_3 SA_DQS_4

SA_DQS_2

SA_DQS_0 SA_DQS_1

SA_DQS_7*

SA_DQS_6*

SA_DQS_5*

SA_DQS_4*

SA_DQS_3*

SA_DQS_2*

SA_DQS_0* SA_DQS_1*

SA_ODT_1

SA_ODT_0

SA_CS_1*

SA_CS_0*

SA_CKE_1

SA_CK_1*

SA_CK_1

SA_CKE_0

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_CAS*

SA_BS_0 SA_BS_1 SA_BS_2

SA_DQ_62 SA_DQ_63

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_50 SA_DQ_51

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_42 SA_DQ_43

SA_DQ_41

SA_DQ_39 SA_DQ_40

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_34 SA_DQ_35

SA_DQ_31

SA_DQ_33

SA_DQ_32

SA_DQ_29 SA_DQ_30

SA_DQ_26

SA_DQ_28

SA_DQ_27

SA_DQ_24 SA_DQ_25

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_19 SA_DQ_20

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQ_11 SA_DQ_12

SA_DQ_9 SA_DQ_10

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_5

SA_DQ_4

SA_DQ_3

SA_DQ_2

SA_DQ_1

SA_DQ_0

(3 OF 9)

MEMORY CHANNEL A

SB_MA_15

SB_MA_14

SB_MA_12 SB_MA_13

SB_MA_11

SB_MA_10

SB_MA_9

SB_MA_7 SB_MA_8

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_1

SB_MA_0

SB_DQS_7

SB_DQS_6

SB_DQS_5

SB_DQS_4

SB_DQS_3

SB_DQS_2

SB_DQS_1

SB_DQS_0

SB_DQS_7*

SB_DQS_6*

SB_DQS_5*

SB_DQS_4*

SB_DQS_3*

SB_DQS_2*

SB_DQS_1*

SB_DQS_0*

SB_ODT_0 SB_ODT_1

SB_CS_1*

SB_CS_0*

SB_CKE_1

SB_CK_1

SB_CK_1*

SB_CK_0*

SB_CKE_0

SB_CK_0

SB_DQ_37

SB_DQ_36

SB_DQ_34 SB_DQ_35

SB_DQ_33

SB_DQ_31 SB_DQ_32

SB_DQ_30

SB_DQ_29

SB_DQ_26 SB_DQ_27 SB_DQ_28

SB_DQ_24 SB_DQ_25

SB_DQ_21 SB_DQ_22 SB_DQ_23

SB_DQ_20

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_8 SB_DQ_9

SB_DQ_7

SB_DQ_6

SB_DQ_4 SB_DQ_5

SB_DQ_3

SB_DQ_2

SB_DQ_1

SB_DQ_0

SB_DQ_39

SB_DQ_38

SB_DQ_40 SB_DQ_41 SB_DQ_42

SB_DQ_44

SB_DQ_43

SB_DQ_46

SB_DQ_45

SB_DQ_47

SB_DQ_49

SB_DQ_48

SB_DQ_51

SB_DQ_50

SB_DQ_52

SB_DQ_54

SB_DQ_53

SB_DQ_56

SB_DQ_55

SB_DQ_57

SB_DQ_59

SB_DQ_58

SB_DQ_61

SB_DQ_60

SB_DQ_62

SB_BS_0

SB_DQ_63

SB_BS_2

SB_BS_1

SB_RAS*

SB_CAS*

SB_WE*

(4 OF 9)

MEMORY CHANNEL B

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

28 79

27 28 79

28 79

27 79

28 79

28 29 79

28 79

29 79

27 79

27 28 79

28 79

27 28 79

28 79

27 79

29 79

28 29 79

28 79

28 29 79

28 79

29 79

OMIT_TABLE

CRITICAL

BGA

MOBILE-2C-35W

SANDY-BRIDGE

U1000

BD37 BF36 BA28

BE39

AU36 AV36

AT40 AU40

AY26

BB26

BB40 BC41

AG6 AJ6

AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

AP11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14

AL6

BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48

AJ10

BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56

AJ8

AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53

AL8

AN55 AN52 AG55 AK56

AL7 AR11

AP6

AJ11

AL11

AR10

AR8

AY11

AV11

AU17

AT17

AW45

AV45

AV51

AY51

AT56

AT55

AK54

AK55

BG35 BB34

BE37 BA30 BC30 AW41 AY28 AU26

BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32

AY40 BA41

BD39 AT41

OMIT_TABLE

CRITICAL

SANDY-BRIDGE

MOBILE-2C-35W

BGA

U1000

BG39 BD42 AT22

AV43

BA34 AY34

BA36 BB36

AR22

BF27

BE41 BE47

AL4 AL1

AV4 BA4 AU3 AR3 AY2 BA3 BE9

BD9 BD13 BF12

AN3

BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14

AR4

BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53

AK4

BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58

AK3

AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59

AN4

AM60 AL59 AF61 AH60

AR1

AU4

AT2

AM2

AL3

AV1

AV3

BE11

BG11

BD18

BD17

BE51

BG51

BA61

BA59

AR59

AT60

AK61

AK59

BF32 BE33

BD43 AT28 AV28 BD46 AT26 AU22

BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28

AT43 BG47

BF40 BD45

SYNC_DATE=06/18/2010

CPU DDR3 INTERFACES

MEM_A_A<14> MEM_A_A<15>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<9> MEM_A_A<10>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<5> MEM_A_DQS_P<6>

MEM_A_DQS_P<3> MEM_A_DQS_P<4>

MEM_A_DQS_P<2>

MEM_A_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<0> MEM_A_DQS_N<1>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CKE<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<50> MEM_A_DQ<51>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<42> MEM_A_DQ<43>

MEM_A_DQ<41>

MEM_A_DQ<39> MEM_A_DQ<40>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<31>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<29> MEM_A_DQ<30>

MEM_A_DQ<26>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15>

MEM_A_DQ<11> MEM_A_DQ<12>

MEM_A_DQ<9> MEM_A_DQ<10>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQS_P<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<12> MEM_B_A<13>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<7> MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CKE<1>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CLK_N<0> MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<34> MEM_B_DQ<35>

MEM_B_DQ<33>

MEM_B_DQ<31> MEM_B_DQ<32>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28>

MEM_B_DQ<24> MEM_B_DQ<25>

MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<8> MEM_B_DQ<9>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<4> MEM_B_DQ<5>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<47>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<52>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<57>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<62>

MEM_B_BA<0>

MEM_B_DQ<63>

MEM_B_BA<1> MEM_B_BA<2>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_RAS_L

MEM_A_DQ<46>

12 OF 109

11 OF 86

OUT OUT

OUT

IN

BI

OUT

VCCIO_29

VCCIO_28

VCCIO_27

VCCIO_26

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_22

VCCIO_21

VCCIO_20

VCCIO_19

VCCIO_18

VCCIO_17

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_49

VCCIO_48

VCCIO_5

VCCIO_4

VCCIO_3

VCCIO_47

VCCIO_46

VCCIO_45

VCCIO_44

VCCIO_43

VCCIO_1

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_32

VCCIO_31

VCCIO_30

VCCIO_51

VCCIO_50

VCC_76

VCC_75

VCC_74

VCC_73

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_64

VCC_63

VCC_62

VCC_61

VCC_60

VCC_59

VCC_58

VCC_57

VCC_56

VCC_55

VCC_54

VCC_53

VCC_52

VCC_51

VCC_50

VCC_49

VCC_48

VCC_47

VCC_46

VCC_45

VCC_44

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_35

VCC_34

VCC_33

VCC_32

VCC_31

VCC_30

VCC_29

VCC_28

VCC_27

VCC_26

VCC_25

VCC_24

VCC_23

VCC_22

VCC_21

VCC_20

VCC_19

VCC_18

VCC_17

VCC_16

VCC_15

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCCIO_SEL

VCCPQE_1 VCCPQE_2

VIDALERT*

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

LINES

SENSE

SVID QUIET

RAIL

PEG AND DDR

CORE SUPLLY

(6 OF 9)

(7 OF 9)

SENSE

LINE

1.8V

RAIL

SA RAIL

QUIET

RAIL

SENSE

LINE

DDR3-1.5V RAILS

GRPHICS

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_10

VDDQ_9

VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18

VDDQ_20

VDDQ_19

VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26

VCCDQ_1 VCCDQ_2

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID_0 VCCSA_VID_1

SM_VREF

VAXG_1 VAXG_2

VAXG_4

VAXG_3

VAXG_5 VAXG_6 VAXG_7 VAXG_8 VAXG_9 VAXG_10 VAXG_11 VAXG_12 VAXG_13 VAXG_14 VAXG_15 VAXG_16 VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25

VAXG_28

VAXG_26 VAXG_27

VAXG_30

VAXG_29

VAXG_33

VAXG_31 VAXG_32

VAXG_35

VAXG_34

VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43

VAXG_45

VAXG_44

VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56

VAXG_SENSE VSSAXG_SENSE

VCCPLL_1 VCCPLL_2 VCCPLL_3

VCCSA_2

VCCSA_1

VCCSA_3 VCCSA_4 VCCSA_5 VCCSA_6 VCCSA_7 VCCSA_8 VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13

VCCSA_15

VCCSA_14

VCCSA_16

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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8 7 5 4 2 1

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

(IPU)

For Future Compatibility

(NOT controlled by VCCIO_SEL)

(IPU)

Fixed at 1.05V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

68 78

70 78

65

1/16W

10K

402

MF-LF

5%

R1320

1

2

1%

MF-LF

PLACE_NEAR=U1000.C44:2.54mm

402

130

1/16W

R1302

1

2

PLACE_NEAR=R1310.2:2.54mm

1/16W

1%

75

MF-LF 402

R1300

1

2

402

1/16W

43

5%

MF-LF

PLACE_NEAR=U1000.A44:38mm

R1310

1 2

5%0MF-LF1/16W

402

R1311

1 2

5%

MF-LF

0

402

1/16W

R1312

1 2

68 78

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.F43:50.8mm

1%

1/16W

402

MF-LF

100

R1360

1

2

PLACE_NEAR=U1000.AN16:50.8mm

1%

MF-LF 402

1/16W

NOSTUFF

100

PLACE_SIDE=BOTTOM

R1362

1

2

NOSTUFF

PLACE_NEAR=U1000.G43:50.8mm

PLACE_SIDE=BOTTOM

MF-LF

1/16W

1%

100

402

R1361

1

2

100

PLACE_SIDE=BOTTOM

NOSTUFF

PLACE_NEAR=U1000.AN17:50.8mm

402

MF-LF

1/16W

1%

R1363

1

2

MF-LF

10K

402

5%

1/16W

R1314

1

2

5% 1/16W MF-LF

10K

402

R1313

1

2

PLACE_SIDE=BOTTOM

MF-LF

402

1/16W

100

1%

PLACE_NEAR=U1000.F45:50.8mm

NOSTUFF

R1370

1

2

PLACE_SIDE=BOTTOM

1%

100

1/16W

402

MF-LF

PLACE_NEAR=U1000.BC43:50.8mm

R1380

1

2

NOSTUFF

PLACE_SIDE=BOTTOM

MF-LF

1/16W

1%

100

402

PLACE_NEAR=U1000.G45:50.8mm

R1371

1

2

PLACE_NEAR=U1000.BA43:50.8mm

PLACE_SIDE=BOTTOM

MF-LF

1/16W

1%

100

402

R1381

1

2

5%

1/16W

402

MF-LF

100

SM_VREF_EXT

PLACE_NEAR=U1000.BJ44:2.54mm

R1331

1

2

5%

1/16W

100

SM_VREF_EXT

402

MF-LF

PLACE_NEAR=U1000.BJ44:2.54mm

R1330

1

2

402

10% X5R

16V

PLACE_NEAR=U1000.BJ44:2.54mm

0.1UF

SM_VREF_EXT

C1330

1

2

100

MF-LF

1%

1/16W

402

PLACE_NEAR=U1000.U10:50.8mm

R1382

1

2

65

MOBILE-2C-35W

SANDY-BRIDGE

OMIT_TABLE

CRITICAL

BGA

U1000

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

F43

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20

AF46

AG15 AG16 AG17 AG20 AG21

AG48 AG50 AG51

AJ14 AJ15

AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

BC22

AN16

W16 W17

AM25 AN22

A44 B43 C44

G43

AN17

OMIT_TABLE

CRITICAL

BGA

MOBILE-2C-35W

SANDY-BRIDGE

U1000

AY43

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61

F45

T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

AM28 AN26

BB3 BC1 BC4

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21

U10

U15 V16 V17 V18 V21

D48 D49

W20

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

BC43 BA43

G45

SYNC_MASTER=ANNE_K90I

CPU POWER

SYNC_DATE=06/18/2010

PP3V3_S0

CPU_VIDALERT_L_R

PP1V05_S0

PP1V5_S3_CPU_VCCDQ

PP1V05_S0

CPU_VCCSENSE_P

CPU_AXG_SENSE_N

PP1V8_S0_CPU_VCCPLL_R

PPVCORE_S0_AXG

PPVCCSA_S0_CPU

CPU_VCCSASENSE

CPU_VCCSA_VID<1>

CPU_VDDQ_SENSE_P

CPU_DDR_VREF

VOLTAGE=0.75V

CPU_VIDSCLK

CPU_VIDSCLK_R

PPVCORE_S0_CPU

CPU_VIDALERT_L

PP1V05_S0_CPU_VCCPQE

CPU_VIDSOUT

CPU_VIDSOUT_R

PPVCORE_S0_CPU

PP1V5_S3RS0

CPU_VCCIO_SEL

PP1V5_S3RS0

CPU_VCCIOSENSE_N

PP1V05_S0

CPU_VCCIOSENSE_P

CPU_VCCSENSE_N

CPU_VCCSA_VID<0>

CPU_DDR_VREF

CPU_AXG_SENSE_P

CPU_VDDQ_SENSE_N

PPVCCSA_S0_CPU

PPVCORE_S0_AXG

13 OF 109

12 OF 86

6 7 8

16 17 18 19 20 22 23 26

27 29 33 36 37 40 41 42 46 48

49 50 51 52 54 57 61 62 71 72

73 74 75 77 85

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

7

15

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68

70 73

7

14

6 7 9

12

15 49 69

6 7

12 15

65

12

6 7 9

12 14 49 69

7

10

14

6 7 9

12 14

49 69

6 7

10 12 15 30 72 73 85

6 7

10 12 15 30 72 73 85

6 7

10 12 15 30 72 73 85

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

12

6 7

12 15 65

6 7 9

12 15 49 69

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF

(9 OF 9)

VSS

(8 OF 9)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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A

B

C

345678

D

B

8 7 5 4 2 1

OMIT_TABLE

CRITICAL

SANDY-BRIDGE

MOBILE-2C-35W

BGA

U1000

BG13 BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

C29 C35 C40

D10 D14 D18 D22 D26 D29 D35

D4

D40 D43 D46 D50 D54 D58

D6

E25 E29

E3

E35 E40 F13 F15 F19 F29 F35 F40 F55

G48 G51

G6

G61

H10 H14 H17 H21

H4

H53 H58

J1 J49 J55

K11 K21 K51

K8

L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

M4

M58

M6

N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

P14 P16 P18 P21 P58 P59

P9

R17 R20

R4

R46 T1 T47 T50 T51 T52 T53 T55 T56

U13

U8

V20 V61

W13 W15 W18 W21 W46

W8

Y4 Y47 Y58 Y59

OMIT_TABLE

CRITICAL

MOBILE-2C-35W

SANDY-BRIDGE

BGA

U1000

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53

A9

AA1

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AA8

AB16 AB18 AB21 AB48 AB61

AC10 AC14 AC46

AC6

AD17 AD20

AD4

AD61

AE13

AE8

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59

AG10 AG14 AG18 AG47 AG52 AG61

AG7

AH4 AH58

AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AJ7

AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

AM13 AM20 AM22 AM26 AM30

AM34 AM38

AM4

AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54

AP10 AP51 AP55

AP7

AR13 AR17 AR21 AR41 AR48 AR61

AR7

AT14 AT19 AT36

AT4

AT45 AT52 AT58 AU1

AU11 AU28 AU32 AU51

AU7

AV17 AV21 AV22 AV34 AV40 AV48 AV55

AW13 AW43 AW61

AW7

AY14 AY19 AY30 AY36

AY4

AY41 AY45 AY49 AY55 AY58

AY9

BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53

BC13

BC5

BC57

BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56

BD8

BE5 BG9

CPU GROUNDS

14 OF 109

13 OF 86

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345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Note:The smallest 10mOhm available in the library are 0805s

PLACEMENT_NOTE (C1672-C1681):

PLACEMENT_NOTE (C1684-C167F):

CPU VCCPLL Low pass filter

Intel recommendation (Section 6.2): 35x 2.2uF, 25x 22uF, 4x 470uF

CPU VCORE DECOUPLING

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

PLACEMENT_NOTE (C1640-C1645):

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

PLACEMENT_NOTE (C1667-C1679):

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

CPU VCCIO/VCCPQ DECOUPLING

PLACEMENT_NOTE (C1655-C1666):

PLACEMENT_NOTE (C1646-C1671):

CPU VCCPLL DECOUPLING

0603

1%

1/4W

MF

0.010

R1601

1 2

10%

X5R

10V

1UF

402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

C160Y

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1632

1

2

NOSTUFF

CRITICAL

20% 4V X5R 402

2.2UF

C1633

1

2

CRITICAL

20% 4V

2.2UF

X5R 402

C1607

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1608

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1634

1

2

CRITICAL

20% 4V

2.2UF

402

X5R

C1635

1

2

CRITICAL

20% X5R

402

4V

2.2UF

C1609

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1610

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1636

1

2

10V

10%

402

X5R

1UF

C1698

1

2

CRITICAL

20%

2.2UF

4V X5R 402

NOSTUFF

C1611

1

2

CRITICAL

20%

402

2.2UF

4V X5R

C1637

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1612

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1638

1

2

2.2UF

CRITICAL

20% 4V X5R 402

C1613

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1639

1

2

20% 4V X5R 402

2.2UF

CRITICAL

C1640

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1614

1

2

CRITICAL

20% 4V

402

2.2UF

X5R

C1615

1

2

10% 10V

402

1UF

X5R

C1699

1

2

2.2UF

20%

402

CRITICAL

4V X5R

C1641

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1642

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1616

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1617

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1643

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1644

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1618

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1619

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1645

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1620

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1646

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1647

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1621

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1622

1

2

CRITICAL

20% 4V X5R

2.2UF

402

C1648

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1649

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1623

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1624

1

2

330UF-0.006OHM

20% 2V POLY CASE-D2-SM

C167D

1

2

CASE-D2-SM

330UF-0.006OHM

POLY

20% 2V

C167E

1

2

PLACE_NEAR=U1000.AK61:5mm

20%

CASE-D2-SM

2V POLY

330UF-0.006OHM

C160Z

1

2

Place near U1000 on bottom side

603

X5R

10UF

6.3V

20%

C161E

1

2

10UF

CERM-X5R

6.3V

Place near U1000 on bottom side

20%

0402-1

C162A

1

2

Place near U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

C162B

1

2

Place near U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

C162C

1

2

Place near U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

C162D

1

2

402

1UF

10V

10% X5R

C169A

1

2

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R

20%

0402-1

C162E

1

2

Place near U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

C167A

1

2

Place near U1000 on bottom side

0402-1

10UF

CERM-X5R

6.3V

20%

C167B

1

2

Place near U1000 on bottom side

10UF

0402-1

20%

6.3V CERM-X5R

C167C

1

2

10% 10V X5R 402

1UF

C169B

1

2

10% X5R

10V

1UF

402

C169C

1

2

Place on bottom side of U1000

10% 10V

1UF

402

X5R

C1684

1

2

Place near inductors on bottom side.

470UF-4MOHM

20%

D2T-SM

POLY-TANT

2.0V

C1680

1

23

10%

1UF

10V X5R

Place on bottom side of U100.

402

C1685

1

2

10% 10V X5R

Place on bottom side of U1000

1UF

402

C1686

1

2

20%

Place near inductors on bottom side.

D2T-SM

2.0V

470UF-4MOHM

POLY-TANT

C1681

1

23

Place close to U1000 on bottom side.

CRITICAL

OMIT

X5R-CERM-1

20%

6.3V

22UF

603

C1667

1

2

Place close to U1000 on top side.

CRITICAL

OMIT

X5R-CERM-1

22UF

20%

6.3V 603

C1655

1

2

NOSTUFF

CRITICAL

X5R-CERM-1

20%

6.3V

22UF

603

C1668

1

2

NOSTUFF

CRITICAL

20%

6.3V

22UF

X5R-CERM-1 603

C1669

1

2

NOSTUFF

CRITICAL

22UF

20%

6.3V X5R-CERM-1 603

C1656

1

2

NOSTUFF

CRITICAL

X5R-CERM-1 603

20%

6.3V

22UF

C1657

1

2

10% X5R

1UF

10V

Place on bottom side of U1000

402

C1687

1

2

1UF

10V X5R

10%

402

C1688

1

2

470UF-4MOHM

20%

Place near inductors on bottom side.

2.0V

D2T-SM

POLY-TANT

C1682

1

23

10% X5R

10V

1UF

402

C1689

1

2

20%

Place near inductors on bottom side.

D2T-SM

2.0V

470UF-4MOHM

POLY-TANT

C1683

1

23

CRITICAL

OMIT

20%

6.3V

22UF

603

X5R-CERM-1

C1670

1

2

NOSTUFF

CRITICAL

20%

6.3V 603

X5R-CERM-1

22UF

C1658

1

2

CRITICAL

OMIT

20%

6.3V

22UF

603

X5R-CERM-1

C1671

1

2

10%

1UF

10V X5R 402

C167F

1

2

NOSTUFF

CRITICAL

20%

6.3V

22UF

603

X5R-CERM-1

C1672

1

2

NOSTUFF

CRITICAL

20%

6.3V

22UF

603

X5R-CERM-1

C1659

1

2

CRITICAL

OMIT

20%

6.3V

22UF

603

X5R-CERM-1

C1660

1

2

4V X5R 402

CRITICAL

2.2UF

20%

C1650

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1625

1

2

CRITICAL

20% X5R

4V 402

2.2UF

C1600

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1651

1

2

CRITICAL

NOSTUFF

2.2UF

20% X5R

4V 402

C1626

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1652

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1627

1

2

X5R 402

CRITICAL

20% 4V

2.2UF

NOSTUFF

C1601

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1602

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1653

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1628

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1654

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1629

1

2

20%

CRITICAL

4V X5R 402

2.2UF

NOSTUFF

C1603

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1604

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1630

1

2

CRITICAL

20% 4V X5R 402

2.2UF

C1631

1

2

CRITICAL

20% 4V X5R 402

2.2UF

NOSTUFF

C1605

1

2

CRITICAL

20% X5R

402

2.2UF

4V

C1606

1

2

402

10% X5R

10V

1UF

C169D

1

2

10% 10V X5R

1UF

402

C169E

1

2

10% X5R

10V

1UF

402

C169F

1

2

10% X5R

10V 402

1UF

C161A

1

2

10% X5R

10V

1UF

402

C161B

1

2

10% 10V X5R

1UF

402

C161C

1

2

10% X5R

10V

1UF

402

C161D

1

2

402

10% X5R

1UF

10V

C1690

1

2

10%

1UF

X5R

10V

402

C1691

1

2

10% 10V X5R

1UF

402

C1692

1

2

10% X5R

10V

1UF

402

C1693

1

2

X5R

10V 402

1UF

10%

C1697

1

2

NOSTUFF

CRITICAL

20%

6.3V

22UF

603

X5R-CERM-1

C1673

1

2

CRITICAL

OMIT

20%

6.3V 603

22UF

X5R-CERM-1

C1674

1

2

CRITICAL

OMIT

20%

6.3V

22UF

603

X5R-CERM-1

C1661

1

2

CRITICAL

OMIT

20%

6.3V

22UF

603

X5R-CERM-1

C1662

1

2

NOSTUFF

CRITICAL

6.3V

20%

22UF

603

X5R-CERM-1

C1675

1

2

22UF

CRITICAL

OMIT

20%

6.3V 603

X5R-CERM-1

C1663

1

2

402

X5R

10V

1UF

10%

C1694

1

2

10%

1UF

10V X5R 402

C1695

1

2

10% 10V X5R

1UF

402

C1696

1

2

CRITICAL

OMIT

20%

6.3V

22UF

603

X5R-CERM-1

C1676

1

2

Place near U1000 on bottom side

0402-1

20%

6.3V CERM-X5R

10UF

C161F

1

2

CRITICAL

OMIT

20%

6.3V

22UF

603

X5R-CERM-1

C1677

1

2

X5R-CERM-1

CRITICAL

OMIT

20%

6.3V

22UF

603

C1664

1

2

CRITICAL

OMIT

20%

6.3V

22UF

603

X5R-CERM-1

C1665

1

2

CRITICAL

OMIT

20%

6.3V

22UF

603

X5R-CERM-1

C1678

1

2

CRITICAL

OMIT

20%

6.3V

22UF

X5R-CERM-1 603

C1666

1

2

CRITICAL

OMIT

20%

6.3V

22UF

603

X5R-CERM-1

C1679

1

2

1/16W

0

MF-LF

5%

402

R1600

1 2

10% 10V

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

X5R

Place near U1000 on top side

1UF

402

C160X

1

2

C1655,C1660,C1661,C1662,C1663,C1664,C1665,C1666,C1667,C1670,C1671,C1674,C1676,C1677,C1678,C1679

16

CRITICAL

CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG

138S0691

SYNC_DATE=06/28/2010

SYNC_MASTER=JACK_K90I

CPU DECOUPLING-I

PPVCORE_S0_CPU

PP1V05_S0

PP1V05_S0_CPU_VCCPQE

PP1V8_S0

PP1V8_S0_CPU_VCCPLL_R

16 OF 109

14 OF 86

6 7 9

12 49 69

6 7 9

10 12

16 17 20 22

23 36 40 45

68 70 73

7

10 12

6 7

17 20 22 26 71

7

12

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Intel recommendation (Section 6.5): 10x 1uF, 8x 10uF, 1x 330uF

PLACEMENT_NOTE (C1723-C1724):

PLACEMENT_NOTE (C1717-C1722):

PLACEMENT_NOTE (C1758-C1762):

VAXG DECOUPLING

PLACEMENT_NOTE (C1711-C1716):

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

PLACEMENT_NOTE (C1700-C1710):

CPU VCCSA DECOUPLING

PLACEMENT_NOTE (C1738-C1747):

Intel recommendation (Section 6.6): 6x 1uf, 5x 10uf, 1x 330uf

Intel recommendation (section 6.3): 21x 1uF, 6x 10uF, 6x 22uF, 2x 470uF

0603

MF

1/4W

1%

0.010

R1702

1 2

1UF

10% 10V X5R

Place on bottom side of U1000

402

C1740

1

2

CASE-D2-SM

2V POLY

20%

330UF-0.006OHM

C1756

1

2

CASE-D2-SM

2V POLY

330UF-0.006OHM

20%

C1768

1

2

CERM-X5R

10UF

0402-1

20%

6.3V

CRITICAL

C1711

1

2

CERM-X5R 0402-1

6.3V

20%

10UF

CRITICAL

C1712

1

2

0402-1

20%

CERM-X5R

10UF

6.3V

CRITICAL

C1713

1

2

0402-1

20%

6.3V CERM-X5R

10UF

CRITICAL

C1714

1

2

0402-1

20%

6.3V CERM-X5R

10UF

CRITICAL

C1715

1

2

Place near inductors on bottom side.

D2T-SM

POLY-TANT

2.0V

20%

470UF-4MOHM

C1723

1

23

10UF

CERM-X5R

6.3V

20%

0402-1

CRITICAL

C1716

1

2

0402-1

6.3V CERM-X5R

20%

10UF

Place close to U1000 on bottom side

C1748

1

2

20%

6.3V 603

22UF

X5R-CERM-1

CRITICAL

OMIT

C1717

1

2

0402-1

20%

CERM-X5R

10UF

Place close to U1000 on bottom side

6.3V

C1749

1

2

603

X5R

Place close to U1000 on bottom side

10UF

6.3V

20%

C1750

1

2

0402-1

20%

6.3V CERM-X5R

10UF

Place close to U1000 on bottom side

C1751

1

2

0402-1

20%

6.3V CERM-X5R

10UF

Place close to U1000 on bottom side

C1752

1

2

0402-1

20%

6.3V CERM-X5R

10UF

Place close to U1000 on bottom side

C1753

1

2

603

X5R

Place close to U1000 on bottom side

10UF

6.3V

20%

C1754

1

2

0402-1

20%

6.3V CERM-X5R

10UF

Place close to U1000 on bottom side

C1755

1

2

0402-1

20%

6.3V CERM-X5R

10UF

C1763

1

2

0402-1

20%

6.3V CERM-X5R

10UF

C1764

1

2

0402-1

20%

6.3V CERM-X5R

10UF

C1765

1

2

20%

6.3V 603

22UF

X5R-CERM-1

CRITICAL

OMIT

C1718

1

2

0402-1

20%

6.3V CERM-X5R

10UF

C1766

1

2

10UF

CERM-X5R

6.3V

20%

0402-1

C1767

1

2

POLY-TANT

20%

2.0V

D2T-SM

470UF-4MOHM

Place near inductors on bottom side.

C1724

1

23

22UF

20%

6.3V X5R-CERM-1 603

CRITICAL

OMIT

C1719

1

2

Place on bottom side of U1000

X5R 402

1UF

10% 10V

C1741

1

2

10V

10%

402

X5R

1UF

C1742

1

2

X5R

10%

1UF

402

10V

C1743

1

2

402

10V

10%

1UF

X5R

C1744

1

2

22UF

20%

6.3V 603

X5R-CERM-1

CRITICAL

OMIT

C1720

1

2

22UF

20%

6.3V X5R-CERM-1 603

CRITICAL

OMIT

C1721

1

2

22UF

20%

6.3V X5R-CERM-1 603

CRITICAL

OMIT

C1722

1

2

10% X5R

10V

402

1UF

C1745

1

2

402

1UF

X5R

10V

10%

C1746

1

2

10V

402

X5R

10%

1UF

C1747

1

2

1UF

10% X5R

10V 402

Place on bottom side of U1000

CRITICAL

C1700

1

2

10% X5R

Place on bottom side of U100.

10V

1UF

402

CRITICAL

C1701

1

2

Place on bottom side of U1000

1UF

10% 10V

402

X5R

CRITICAL

C1702

1

2

10V X5R

10%

402

1UF

CRITICAL

C1704

1

2

X5R 402

10V

10%

1UF

CRITICAL

C1705

1

2

402

X5R

1UF

10% 10V

CRITICAL

C1706

1

2

1UF

402

10V

10%

X5R

C1757

1

2

X5R

10V

10%

1UF

CRITICAL

402

C1707

1

2

10% 10V X5R 402

1UF

CRITICAL

C1708

1

2

402

X5R

10V

10%

1UF

CRITICAL

C1709

1

2

Place on bottom side of U1000

1UF

10% 10V X5R 402

C1758

1

2

10% X5R

402

10V

Place on bottom side of U100.

1UF

C1759

1

2

X5R

1UF

10% 10V

402

Place on bottom side of U1000

C1760

1

2

X5R

10%

402

10V

Place on bottom side of U1000

1UF

C1761

1

2

10V X5R

10%

1UF

402

C1762

1

2

10V

10% X5R

402

1UF

CRITICAL

C1710

1

2

Place on bottom side of U1000

X5R

1UF

402

10% 10V

CRITICAL

C1703

1

2

402

X5R

10%

Place on bottom side of U1000

10V

1UF

C1738

1

2

10% 10V

Place on bottom side of U100.

X5R 402

1UF

C1739

1

2

CRITICAL138S0691

CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG

6

C1717,C1718,C1719,C1720,C1721,C1722

SYNC_DATE=06/28/2010

CPU DECOUPLING-II

SYNC_MASTER=JACK_K90I

PP1V5_S3RS0

PPVCORE_S0_AXG

PP1V5_S3_CPU_VCCDQ

PPVCCSA_S0_CPU

17 OF 109

15 OF 86

6 7

10 12 30 72 73 85

6 7 9

12 49 69

7

12

6 7

12 65

IN

OUT

IN

BI

OUT

BI

IN

IN OUT OUT

IN IN

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT

OUT

IN

IN IN

IN

OUT

BI

OUT

BI

IN IN OUT OUT

OUT

BI

IN

OUT

SATA1RXN

SATA0TXP

SATA0TXN

SATA2RXN SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

HDA_RST*

SPKR

HDA_SDIN0 HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSI

SPI_MISO

FWH0/LAD0

RTCX1 RTCX2

SATA1TXP

SATA0RXN

SERIRQ

LDRQ1*/GPIO23

FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME*

SATA1RXP SATA1TXN

SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5TXN SATA5TXP

SATAICOMPO SATAICOMPI

SATALED*

SATA0GP/GPIO21 SATA1GP/GPIO19

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

JTAG

SPI

SATA

LPC

IHDA

RTC

(1 OF 10)

(2 OF 10)

PCI-E*

PEG

FROM CLK BUFFER

CLOCK

FLEX

SMBUS

PEG_B_CLKRQ*/GPIO56

PEG_A_CLKRQ*/GPIO47

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

PCIECLKRQ1*/GPIO18

PCIECLKRQ0*/GPIO73

PERN3

PETP2

PETN2

PERP1

CL_RST1*

CL_DATA1

CL_CLK1

CLKIN_GND1_P

CLKIN_GND1_N

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

XCLK_RCOMP

XTAL25_OUT

XTAL25_IN

CLKIN_PCILOOPBACK

REFCLK14IN

CLKIN_SATA_N CLKIN_SATA_P

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_DMI_P

CLKIN_DMI_N

CLKOUT_DP_N CLKOUT_DP_P

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

CLKOUT_PCIE5P

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE4P

CLKOUT_PCIE5N

CLKOUT_PCIE3P

CLKOUT_PCIE4N

CLKOUT_PCIE3N

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1N CLKOUT_PCIE1P

CLKOUT_PCIE0N CLKOUT_PCIE0P

PETN1

PERN1

SMBCLK

SMBALERT*/GPIO11

PETP8

PERP8 PETN8

PETP7

PERN8

PETN7

PERP7

PERN7

PETN6 PETP6

PERP6

PERN6

PETP5

PETN5

PERP5

PETP4

PERN5

PETN4

PERP4

PETP3

PERN4

PETN3

PERP3

PERN2 PERP2

PETP1

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0ALERT*/GPIO60

SML0CLK

SMBDATA

IN IN IN

IN

OUT OUT

IN

OUT

OUT OUT

NC

OUT

IN

IN OUT OUT

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Pullup needed for SPI_DESCRIPTOR_OVERRIDE_L? PD needed for BCM_MEDIA_SENSE?

(IPU)

1.5V -> 1.1V

DOES THIS NEED LENGTH MATCH???

PLACE THIS RESISTOR NEAR THE PCH PIN

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

26 81

57 81

47 81

6

45 47 81

6

45 47 81

6

45 47 81

6

45 47 81

6

45 47 81

6

45 47

42 80

37 81

32 81

39 81

37 81

32 81

39 81

37 81

32 81

39 81

16 23 40

10 78

8

81

8

81

8

25 80

26 80

48 81

23 27 29 31 42 48 62 77 81

8

5%

330K

MF

1/20W

201

R1800

1

2

402

MF-LF

1/16W

1M

5%

R1801

1

2

1/16W

402

MF-LF

5%

20K

R1802

1

2

20K

5% 1/16W MF-LF 402

R1803

1

2

10%

402

X5R

10V

1UF

C1803

1

2

1UF

402

X5R

10V

10%

C1802

1

2

PLACE_NEAR=U1800.Y11:2.54mm

MF-LF

402

37.4

1%

1/16W

R1830

1

2

MF-LF 402

5% 1/16W

10K

R1820

1

2

MF-LF

402

1%

1/16W

90.9

PLACE_NEAR=U1800.Y47:2.54mm

R1890

1

2

PLACE_NEAR=U1800.N34:1.27mm

5%

33

MF

1/20W

201

R1810

1 2

33

5%

PLACE_NEAR=U1800.L34:1.27mm

MF

1/20W

201

R1811

1 2

PLACE_NEAR=U1800.K34:1.27mm

33

5%

MF

1/20W

201

R1812

1 2

5%

PLACE_NEAR=U1800.A36:1.27mm

33

MF

1/20W

201

R1813

1 2

57 81

48 81

5%

10K

MF

1/20W

201

R1853

1

2

10K

5%

MF

1/20W

201

R1854

1

2

10K

5%

MF

1/20W

201

R1855

1

2

16 34

1/16W

5%

33

402

MF-LF

R1860

1 2

MF-LF33402

5%

1/16W

R1861

1 2

1/16W

33

402

MF-LF

5%

R1862

1 2

5%

1/16W

33

402

MF-LF

R1863

1 2

1/16W

5%

33

402

MF-LF

R1864

1 2

1/16W

750

402

1%

MF-LF

PLACE_NEAR=U1800.AH1:2.54mm

R1832

1

2

49.9

402

1% 1/16W MF-LF

PLACE_NEAR=U1800.AB12:2.54mm

R1831

1

2

10K

MF-LF

1/16W

5%

402

R1870

1

2

10K

402

MF-LF

5% 1/16W

R1871

1

2

201

1/20W

MF

5%

0

NOSTUFF

R1841

1 2

201

1/20W

MF

NOSTUFF

5%

0

R1840

1 2

45

201

1/20W

MF

PLACE_NEAR=R1813.1:2.54mm

NOSTUFF

0

5%

R1880

1 2

OMIT

MOBILE

COUGAR-POINT

FCBGA

U1800

C38 A38

B37

C37

D36

N34

C36

N32

K34

E34 G34

C34

A34

A36

L34

K22

C17

J3

K5

H1

H7

E36

K36

D20

A20 C20

V14

AM3 AM1

AP7

AP5

P1

AM10

AM8

AP11 AP10

AD7

AD5

AH5 AH4

AB13

AH1

AB12

AB8

AB10 AF3

AF1

Y7

Y5 AD3

AD1

Y3

Y1 AB3

AB1

Y10

Y11

P3

V5

T3

Y14

T1

U3

V4

T10

G22

MOBILE

COUGAR-POINT

OMIT

FCBGA

U1800

M7

T11

P10

BF18

BE18

G24

E24

BJ30

BG30

H45

AK7

AK5

AV22 AU22

AM12 AM13

AK14 AK13

Y40

Y39

AB49 AB47

AA48

AA47

Y37 Y36

Y43

Y45

V45

V46

AB37

AB38

AB42 AB40

K43

F47

H47

K49

J2

M1

V10

A8

L12

L14

M10

E6

BG34

BE34

BG36

BF36

BG37

BJ38

BG40

BE38

BJ34

BF34

BJ36

BE36

BH37

BG38

BJ40

BC38

AV32

BB32

AV34

AY34

AY36

AU36

AY40

AW38

AU32

AY32

AU34

BB34

BB36

AV36

BB40

AY38

K45

E12

H14 C9

A12

C8 G12

C13

E14 M16

Y47

V47 V49

16 37

16 23 32

16

8

81

8

81

1/16W

402

5%

4.7K

MF-LF

R1877

1

2

5%

10K

MF

1/20W

201

R1876

1

2

201

1/20W

MF

NOSTUFF

10K

5%

R1866

1

2

5%

10K

MF

1/20W

201

R1869

1

2

16 36

23

MF

5%

10K

201

1/20W

R1844

1

2

5%

10K

MF

201

1/20W

R1845

1

2

5%

10K

MF

1/20W

201

R1846

1

2

34 81

37 81

MF

5%

10K

201

1/20W

R1847

1

2

1/20W

MF

10K

5%

201

R1848

1

2

5%

402

MF-LF

1/16W

4.7K

R1878

1

2

5%

10K

MF

201

1/20W

R1843

1

2

5%

MF

1/20W

201

10K

R1842

1

2

1/20W

MF

10K

5%

201

NOSTUFF

R1833

1

2

1/20W

5%

10K

201

MF

R1834

1

2

201

1/20W

MF

NOSTUFF

5%

10K

R1849

1

2

604

PLACE_NEAR=U1800.V47:5.1mm

1/16W MF-LF

1%

402

R1885

1 2

26 81

1K

1/16W

1%

402

MF-LF

PLACE_NEAR=R1885.1:2.54mm

R1886

1

2

42 80

36

201

1/20W

MF

5%

0

NOSTUFF

R1888

1 2

19 45

PCH SATA/PCIE/CLK/LPC/SPI

SYNC_MASTER=K91_MLB

SYNC_DATE=06/18/2010

XDP_PCH_TMS

PCH_SPKR

HDA_BIT_CLK_R

HDA_SYNC_R

ENET_MEDIA_SENSE_RDIV

XDP_PCH_TCK

NC_SATA_E_D2RP

PCH_SATALED_L

AP_CLKREQ_L

SPI_CS0_R_L

TP_SPI_CS1_L

ENET_CLKREQ_L

TP_LPC_DREQ0_L

HDA_SDIN0

PCH_INTVRMEN_L

PCH_INTRUDER_L

PP3V3_S0

DP_AUXCH_ISOL SATARDRVR_EN

PCH_INTRUDER_L

PEG_B_CLKRQ_L_GPIO56

PCIECLKRQ5_L_GPIO44

NC_SATA_E_R2D_CP

NC_SATA_F_D2RP

NC_SATA_F_R2D_CN

T29_CLKREQ_L

EXCARD_CLKREQ_L

PEG_CLKREQ_L

HDA_SDOUT_R

FW_CLKREQ_L

PCH_SATA3RBIAS

LPC_R_AD<2>

PP3V3_SUS

RTC_RESET_L

SMC_SCI_L

PP3V3_SUS

SML_PCH_1_ALERT_L

ITPCPU_CLK100M_N

SML_PCH_0_ALERT_L

PCH_GPIO11

NC_PEG_CLK100MP

NC_PEG_CLK100MN

T29_PWR_EN

SATA_HDD_D2R_P

LPC_R_AD<1>

LPC_FRAME_R_L

NC_SATA_B_D2RP NC_SATA_B_R2D_CN

NC_SATA_B_R2D_CP

NC_SATA_E_R2D_CN

SATA_ODD_R2D_C_P

SATA_ODD_D2R_P SATA_ODD_R2D_C_N

SATA_ODD_D2R_N

NC_SATA_D_R2D_CN

SATA_HDD_R2D_C_N

NC_SATA_D_R2D_CP

EXCARD_CLKREQ_L

SPI_MOSI_R

XDP_PCH_TDO

SPI_MISO

NC_SATA_D_D2RP

NC_PCIE_5_R2D_CP

ITPCPU_CLK100M_P

PCIE_CLK100M_T29_P

HDA_SYNC_R

PP1V5_S0

PP1V05_S0

RTC_RESET_L

SYSCLK_CLK32K_RTC

NC_SATA_F_D2RN

NC_SATA_E_D2RN

NC_PCIE_CLK100M_PEBP

NC_SATA_F_R2D_CP

ITPXDP_CLK100M_N

NC_PCIE_8_D2RN

NC_PCIE_7_R2D_CP

NC_PCIE_7_D2RP

NC_PCIE_7_D2RN

NC_PCIE_6_D2RP

NC_PCIE_6_D2RN

NC_PCIE_EXCARD_R2D_CN

NC_PCIE_EXCARD_D2RP

NC_PCH_GPIO66_CLKOUTFLEX2

PCIE_FW_R2D_C_P

NC_PCIE_8_R2D_CP

PP1V05_S0

PCIE_ENET_D2R_P

PCIE_ENET_R2D_C_P

ITPXDP_CLK100M_N

LPC_R_AD<3>

PCH_CLK96M_DOT_N

HDA_BIT_CLK

HDA_BIT_CLK_R

LPC_AD<2>

HDA_RST_R_L

LPC_AD<0>

LPC_AD<3>

NC_CLINK_DATA

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_ENET_R2D_C_N

PCH_GPIO11

SMBUS_PCH_CLK

SML_PCH_1_ALERT_L

SML_PCH_1_CLK

SML_PCH_1_DATA

DMI_CLK100M_CPU_N

DMI_CLK100M_CPU_P

NC_PCH_CLKOUT_DPN

PCIE_CLK100M_PCH_P

PCH_CLK14P3M_REFCLK

PCIE_CLK100M_PCH_N

HDA_SDOUT

HDA_RST_L

LPC_AD<1>

SML_PCH_0_ALERT_L

SML_PCH_0_CLK

SML_PCH_0_DATA

HDA_SYNC

SMBUS_PCH_DATA

HDA_SDOUT_R

PCH_CLKIN_GNDN1

PP1V05_S0

LPC_FRAME_L

PP3V3_S0

NC_PCIE_EXCARD_D2RN

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_ENET_D2R_N

NC_HDA_SDIN3

HDA_SDOUT_R

NC_PCIE_7_R2D_CN

NC_HDA_SDIN1

HDA_SDOUT_R

NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P

ITPXDP_CLK100M_P

PCIE_CLK100M_AP_N

PCIE_CLK100M_ENET_P

NC_PCIE_5_D2RN

PEG_B_CLKRQ_L_GPIO56

NC_PCIE_CLK100M_PEBN

NC_PCIE_8_R2D_CN

HDA_SYNC_R

NC_SATA_D_D2RN

T29_CLKREQ_L

NC_PCIE_5_R2D_CN

NC_PCIE_5_D2RP

NC_CLINK_CLK

NC_CLINK_RESET_L

ITPXDP_CLK100M_P

NC_PCH_GPIO67_CLKOUTFLEX3

PCH_CLKIN_GNDP1

PCH_CLK33M_PCIIN

PCH_CLK96M_DOT_P

NC_PCH_CLKOUT_DPP

SYSCLK_CLK25M_SB_R

NC_PCH_GPIO65_CLKOUTFLEX1

NC_PCIE_8_D2RP

PCIE_CLK100M_ENET_N

PCIE_CLK100M_AP_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_FW_P

NC_PCIE_CLK100M_EXCARDN NC_PCIE_CLK100M_EXCARDP

PEG_CLKREQ_L

PCH_CLK100M_SATA_N

PCH_CLK100M_SATA_P

NC_PCH_GPIO64_CLKOUTFLEX0

PCH_XCLK_RCOMP

SYSCLK_CLK25M_SB

SPI_DESCRIPTOR_OVERRIDE_L

SATARDRVR_EN

PCH_SATALED_L

PCH_SATAICOMP

LPC_R_AD<0>

NC_PCIE_6_R2D_CP

NC_PCIE_6_R2D_CN

JTAG_T29_TMS

XDP_PCH_TDI

SPI_CLK_R

PPVRTC_G3H

PCH_INTVRMEN_L

PCH_SRTCRST_L

NC_PCIE_EXCARD_R2D_CP

PP3V3_T29

SATA_HDD_D2R_N

SATA_HDD_R2D_C_P

NC_SATA_B_D2RN

LPC_SERIRQ

FW_CLKREQ_L

PCIE_CLK100M_T29_N

PCIECLKRQ5_L_GPIO44

ENET_CLKREQ_L

AP_CLKREQ_L

PCH_SATA3COMP

DP_AUXCH_ISOL

HDA_RST_R_L

PP3V3_S0

PCH_SPKR

JTAG_T29_TMS

PCH_SRTCRST_L

NC_HDA_SDIN2

18 OF 109

16 OF 86

16

16 81

26

6

16

16 23 32

16 37

16

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

16 23 75

16 23 42

16

6

16 36

16

16 81

16 23 40

7

16 17 18

19 20 22 46 71 72 73

16

7

16 17 18 19 20 22 46 71 72

73

16

10 78

16

6

10 78

16 81

7

20 22 26 42 57 71

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

16

6

16 23 78

6

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

16 23 78

16 81

6

16

16 81

6 7 9

10 12 14 16 17 20

22 23 36 40 45 68 70 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50

51 52 54 57 61 62 71 72 73

74

75 77 85

6

16 81

6

16 81

6

16 23 78

16

6

16 81

6

16 23 78

6

81

6

16 23 42

16

80

7

17 20 26

16

7

19 26 34 35 36

6

16

16 23 75

16 81

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

16

16 34

16

6

IN

OUT

OUT OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

(3 OF 10)

MANAGEMENT

SYSTEM POWER

DMI

FDI

DMI1RXN

DMI2RBIAS

FDI_RXP6

DMI3RXN

DMI0RXN

FDI_RXN5

FDI_RXN4

FDI_RXN2 FDI_RXN3

FDI_RXN1

FDI_RXN0

RI*

BATLOW*/GPIO72

PWROK

SYS_PWROK

SYS_RESET*

DMI_ZCOMP

DMI3TXP

DMI2TXP

DMI1TXP

DMI3TXN

DMI0TXP

DMI1TXN DMI2TXN

SUSACK*

SLP_SUS*

DSWVRMEN

DF_TVS

PMSYNCH

TP23

SLP_LAN*/GPIO29

SLP_A*

SLP_S4*

SLP_S5*/GPIO63

SUS_STAT*/GPIO61

SUSCLK/GPIO62

CLKRUN*/GPIO32

WAKE*

FDI_LSYNC1

FDI_FSYNC1

FDI_LSYNC0

FDI_FSYNC0

FDI_INT

FDI_RXP7

FDI_RXP4 FDI_RXP5

FDI_RXP2

FDI_RXP1

FDI_RXP3

FDI_RXP0

FDI_RXN7

FDI_RXN6

DRAMPWROK

DMI2RXN

DMI0TXN

DMI_IRCOMP

SLP_S3*

PWRBTN*

APWROK

RSMRST*

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DPWROK

SUSWARN*/SUSPWRDNACK/GPIO30

ACPRESENT/GPIO31

(4 OF 10)

DIGITAL DISPLAY INTERFACE

CRT

RSVD

DDPD_3P

DDPD_2P DDPD_3N

DDPD_2N

DDPD_1P

DDPD_1N

DDPD_0P

DDPD_0N

DDPD_HPD

DDPD_AUXN DDPD_AUXP

DDPD_CTRLDATA

DDPD_CTRLCLK

DDPC_3N DDPC_3P

DDPC_2N DDPC_2P

DDPC_1N

DDPC_0P

DDPC_1P

DDPC_0N

DDPC_HPD

DDPC_AUXP

DDPC_AUXN

DDPC_CTRLDATA

DDPC_CTRLCLK

DDPB_3P

DDPB_3N

DDPB_2N DDPB_2P

DDPB_1P

DDPB_1N

DDPB_0P

DDPB_HPD

DDPB_0N

DDPB_AUXP

DDPB_AUXN

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVO_INTN SDVO_INTP

SDVO_STALLN SDVO_STALLP

SDVO_TVCLKINN SDVO_TVCLKINP

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

CRT_IRTN

DAC_IREF

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Set to Vcc when High

DF_TVS:DMI & FDI Term Voltage

Set to Vss when Low

9

78

9

78

9

78

9

78

9

78

9

78

49.9

402

1/16W MF-LF

1%

PLACE_NEAR=U1800.BJ24:12.7mm

R1900

1

2

6

17 26 32

6

17 45 47

46

45 73

6

30 45 73

6

30 45 73

10 30 78

73

17 23 45

17 46

17 26

45

23 26

26 45

9

78

9

78

9

78

9

78

9

78

9

78

9

78

9

78

9

78

9

78

9

78

9

78

9

78

9

78

9

78

10K

5%

1/20W

MF

201

R1905

1

2

10 78

6

45 47

PLACE_NEAR=U1800.T43:2.54mm

402

1K

5%

MF-LF

1/16W

R1951

1

2

201

1/20W

MF

5%

100K

R1909

1

2

1/16W

402

1%

MF-LF

750

PLACE_NEAR=U1800.BH21:2.54mm

R1920

1

2

5%

0

1/20W

MF

201

R1986

12

402

5%

1/16W

2.2K

MF-LF

R1981

1

2

1/16W

1K

402

MF-LF5%

R1980

12

MOBILE

COUGAR-POINT

OMIT

FCBGA

U1800

H20

L10

E10

N3

AY1

BC24

BE24

AW24

AY24

BE20

BC20

AW20

AY20

BH21

BG18

BJ18

BB18

AY18

BG20

BJ20

AV18

AU18

BG25

BJ24

E22

B13

A18

AV12 BC10

AW16

AV14

BB10

BJ14

AY14

BE14 BH13

BC12

BJ12 BG10

BG9

BG14

BB14 BF14

BG13 BE12

BG12

BJ10 BH9

AP14

E20

L22

A10

C21

G10

K14

F4

H4

D10

G16

G8

C12

N14

K16

P12

K3

AY16

B9

FCBGA

MOBILE

OMIT

COUGAR-POINT

U1800

N48

T39

M40

P49

M47

T42

T49

M49

T43

AV42

AV40

AV45 AV46

AU48 AU47

AV47

AV49

AT49

AT47 AT40

AY47

AY49 AY43

AY45 BA47

BA48

BB47 BB49

AP47 AP49

P46

P42

AT38

BB43

BB45

BF44 BE44

BF42

BE42 BJ42

BG42

AT45

AT43

M43 M36

BH41

AT1

AT10 AT12

AT3

AT4 AT5

AT8

AU2

AU3 AV1

AV10

AV3 AV5

AV7

AY3

AY5

AY7 BA2

BA3

BB1 BB3

BB5 BB7

BC8

BD4 BE8

BF3

BF6 BG4

P38 M39

AP39 AP40

AM42

AM40

AP43

AP45

5%

1/20W

MF

201

390K

R1915

1

2

MF-LF

5% 1/16W

402

8.2K

R1991

1

2

5%

NOSTUFF

MF

201

1/20W

10K

R1984

1

2

MF-LF

402

5%

10K

1/16W

R1982

1

2

1%

1K

MF

1/20W

201

R1925

1

2

45 46 73

17

MF-LF

402

5%

10K

1/16W

R1983

1

2

17 26

MF 201

1%

1K

1/20W

R1985

1

2

17

75

PCH DMI/FDI/GRAPHICS

DMI_S2N_P<1>

DMI_S2N_N<0>

PP3V3_SUS

PP1V05_S0

DMI_N2S_N<0>

PM_PCH_SYS_PWROK

PM_PWRBTN_L

PM_BATLOW_L

PM_RSMRST_L

PM_MEM_PWRGD

PM_DSW_PWRGD

PCH_DAC_IREF

NC_CRT_IG_HSYNC

PCH_SUSACK_L

PCH_SUSWARN_L

SMC_ADAPTER_EN

PM_SYSRST_L

DMI_S2N_P<3>

PM_PCH_PWROK

PCH_SUSACK_L

DMI_S2N_P<2>

TP_PM_SLP_A_L

GPIO29_SLP_LAN_L

PCH_DF_TVS

PM_SLP_S3_L

FDI_LSYNC<1>

FDI_LSYNC<0>

FDI_FSYNC<1>

FDI_FSYNC<0>

FDI_INT

FDI_DATA_P<7>

FDI_DATA_P<6>

FDI_DATA_P<5>

FDI_DATA_P<4>

FDI_DATA_P<3>

PP3V3_S0

NC_CRT_IG_VSYNC

PM_CLKRUN_L

TP_DP_IG_C_MLP<2>

NC_CRT_IG_BLUE NC_CRT_IG_GREEN

NC_CRT_IG_RED

NC_CRT_IG_DDC_CLK

CPU_PROC_SEL_L

TP_DP_IG_C_MLN<3>

TP_DP_IG_C_MLP<3>

TP_DP_IG_B_MLN<3>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLP<1>

DMI_N2S_N<3>

PM_SLP_SUS_L

DMI_N2S_P<3>

DP_IG_C_CTRL_CLK DP_IG_C_CTRL_DATA

DP_T29SNK0_AUXCH_C_P

DP_T29SNK0_HPD

TP_DP_IG_C_MLN<0> TP_DP_IG_C_MLP<0>

DP_EXTA_DDC_DATA

TP_DP_IG_B_MLN<0>

TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLP<0>

DP_EXTA_AUXCH_C_N

DP_EXTA_DDC_CLK

NC_SDVO_INTP

NC_SDVO_INTN

NC_SDVO_STALLP

NC_SDVO_STALLN

FDI_DATA_N<5>

FDI_DATA_N<2>

FDI_DATA_N<3>

FDI_DATA_N<1>

FDI_DATA_N<0>

FDI_DATA_P<2>

FDI_DATA_N<7>

FDI_DATA_N<6>

TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1>

DP_T29SNK0_AUXCH_C_N

DP_T29SNK1_AUXCH_C_N

TP_DP_IG_D_MLP<2>

TP_DP_IG_C_MLN<2>

NC_SDVO_TVCLKINN

NC_SDVO_TVCLKINP

TP_DP_IG_D_MLP<3>

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<0>

DP_T29SNK1_HPD

DP_T29SNK1_AUXCH_C_P

TP_DP_IG_C_MLP<1>

DP_IG_D_CTRL_DATA

DP_IG_D_CTRL_CLK

TP_DP_IG_C_MLN<1>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLN<2>

FDI_DATA_P<1>

DMI_N2S_P<0>

DMI_N2S_N<2>

DMI_S2N_N<3>

DP_EXTA_AUXCH_C_P DP_EXTA_HPD

TP_DP_IG_B_MLP<3>

FDI_DATA_P<0>

FDI_DATA_N<4>

PCH_SUSWARN_L

PCH_DMI_COMP

PCH_RI_L

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_N<1>

PP1V8_S0

NC_CRT_IG_DDC_DATA

PCH_DSWVRMEN

TP_PCH_TP23

PPVRTC_G3H

DMI_S2N_N<1>

DMI_S2N_N<2>

DMI_S2N_P<0>

PCH_DMI2RBIAS

PCH_SUSWARN_L

PP3V3_SUS

PM_BATLOW_L

GPIO29_SLP_LAN_L

PCIE_WAKE_L

PM_PWRBTN_L

PM_CLK32K_SUSCLK_R

PM_CLKRUN_L

PP3V3_S5 PP3V3_SUS

PM_SYNC

PM_SLP_S5_L

PM_SLP_S4_L

PCIE_WAKE_L

=T29_WAKE_L

LPC_PWRDWN_L

19 OF 109

17 OF 86

7

16 17 18 19 20 22 46 71 72 73

6 7 9

10 12 14 16 20 22 23 36

40 45 68 70 73

6

17

9

78

9

78

9

78

9

78

9

78

6 7 8

12 16 18 19 20 22 23 26

27 29 33 36 37 40 41 42 46 48

49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6

17 45 47

8

6

10

8

73

8

34 83

8

34

8

75

8

75 80 81

8

75

6

9

78

9

78

9

78

9

78

9

78

9

78

9

78

9

78

8

34 83

8

34 83

8

6

8

34

8

34 83

8

9

78

8

75 80 81

8

75

8

9

78

9

78

17

6 7 14 20 22 26 71

6

7

16 20 26

17

7

16 17 18 19 20 22 46 71 72

73

17 46

17

6

17 26 32

17 23 45

6 7 8

19 20 22 23 24 26 30 46

56 66 72 73 74 76 85 7

16 17 18 19 20 22 46 71 72

73

OUT

USBP2N

USBP1N USBP1P

USBP0N USBP0P

OC7*/GPIO14

OC6*/GPIO10

OC5*/GPIO9

OC4*/GPIO43

OC3*/GPIO42

OC2*/GPIO41

OC1*/GPIO40

OC0*/GPIO59

USBRBIAS*

USBRBIAS

USBP13P

USBP13N

USBP12P

USBP12N

USBP11P

USBP11N

USBP10P

USBP10N

USBP9P

USBP9N

USBP8P

USBP8N

USBP7N USBP7P

USBP6N USBP6P

USBP5N USBP5P

USBP4P

USBP4N

USBP3P

USBP3N

USBP2P

PIRQA* PIRQB* PIRQC* PIRQD*

REQ1*/GPIO50

REQ3*/GPIO54

REQ2*/GPIO52

GNT2*/GPIO53

GNT1*/GPIO51

GNT3*/GPIO55

PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5

PME*

CLKOUT_PCI0

PLTRST*

CLKOUT_PCI2

CLKOUT_PCI1

CLKOUT_PCI3 CLKOUT_PCI4

LVDSA_DATA2*

LVDSA_DATA1*

LVDSA_DATA0*

LVDSA_DATA3*

LVDSA_DATA0

LVDSA_DATA2

LVDSA_DATA1

LVDSA_CLK*

LVDSA_DATA3

LVDSA_CLK

LVDSB_DATA0* LVDSB_DATA1* LVDSB_DATA2* LVDSB_DATA3*

LVDSB_DATA1

LVDSB_DATA0

LVDSB_DATA2 LVDSB_DATA3

LVDSB_CLK* LVDSB_CLK

L_BKLTEN

L_BKLTCTL

LVD_VREFL

LVD_VREFH

LVD_VBG

LVD_IBG

L_VDD_EN

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

L_CTRL_CLK

(5 OF 10)

USB

PCI

LVDS

OUT OUT OUT

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT OUT OUT

OUT OUT

IN

BI BI

IN IN

BI BI

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

USB HUB 2

Unused

Camera

Unused

PUs TO S0 INSTEAD?

Unused

USB HUB 1

Unused

6

74 80

MOBILE

COUGAR-POINT

OMIT

FCBGA

U1800

H49 H43

J48

K42 H40

D47 E42

F46

P45

J47

T45

P39 T40

K47

M45

AF37

AF36

AE48 AE47

AK40

AK39

AN47

AN48

AM49

AM47

AK49

AK47

AJ47

AJ48

AF39

AF40

AH43

AH45

AH49

AH47

AF47

AF49

AF43

AF45

A14

K20 B17

C16

L16 A16

D14

C14

K40

K38

H38 G38

G42

G40 C42

D44

C6

K10

C46 C44

E40

C24

A24

C30

A30

L32 K32

G32

E32

C32

A32

C25

B25

C26

A26

K28

H28

E28 D28

C28

A28

C29 B29

N28

M28

L30

K30

G30 E30

B33

C33

6

74 80

6

74 80

8

80

6

74 80

6

74 80

6

74 80

8

80

74 80

8

6 8

80

6 8

80

8

1%

MF-LF

1/16W

402

2.37K

PLACE_NEAR=U1800.AF37:2.54mm

R2050

1

2

201

1/20W

MF

NOSTUFF

10K

5%

R2054

1

2

201

1/20W

MF

10K

NOSTUFF

5%

R2053

1

2

201

1/20W

MF

10K

5%

NOSTUFF

R2052

1

2

8

77

8

77

8

74

6 8

74

6 8

74

10K

5%

1/16W

402

MF-LF

R2015

1 2

5%

10K

MF

1/20W

201

R2065

1

2

5%

201

MF

1/20W

10K

R2067

1

2

10K

5%

MF

201

1/20W

R2069

1

2

100K

402

1/16W

5%

MF-LF

R2055

1

2

62

32 80

75

10K

5%

1/16W

402

MF-LF

R2031

1 2

62

24 80

5%

10K

MF

1/20W

201

R2064

1

2

10K

5%

MF

1/20W

201

R2062

1

2

10K

5%

MF

1/20W

201

R2061

1

2

PLACE_NEAR=U1800.B33:2.54mm

1%

22.6

MF

1/20W

201

R2070

1

2

10K

MF-LF1/16W

5%

402

R2010

1 2

MF-LF

5%

10K

402

1/16W

R2011

1 2

MF-LF1/16W

10K

402

5%

R2012

1 2

MF-LF

402

5%

10K

1/16W

R2013

1 2

10K

1/16W5%MF-LF

402

R2016

1 2

402

MF-LF1/16W

10K

5%

R2017

1 2

5%

10K

MF-LF1/16W

402

R2018

1 2

26 30 33 36 40

26

26 81

26

10K

5%

1/16W

402

MF-LF

R2030

1 2

5%

10K

MF

1/20W

201

R2068

1

2

10K

5%

MF

1/20W

201

R2060

1

2

SYNC_MASTER=K91_MLB

PCH PCI/FLASHCACHE/USB

SYNC_DATE=06/10/2010

PCH_PCI_GNT1_L

PCH_PCI_GNT2_L

PCH_PCI_GNT3_L

PP3V3_S3

PP3V3_SUS

USB_HUB_SOFT_RESET_L

SDCONN_STATE_RST_L

ENET_PWR_EN

AP_PWR_EN

PCI_REQ3_L

LPC_CLK33M_LPCPLUS_R

LVDS_DDC_DATA

LCD_BKLT_EN

TP_LVDS_IG_B_CLKP

TP_LVDS_IG_B_CLKN

NC_LVDS_IG_B_DATAP<3>

NC_LVDS_IG_B_DATAP<2>

NC_LVDS_IG_B_DATAP<0>

NC_LVDS_IG_B_DATAP<1>

NC_LVDS_IG_B_DATAN<3>

NC_LVDS_IG_B_DATAN<2>

NC_LVDS_IG_B_DATAN<1>

NC_LVDS_IG_A_DATAP<3>

LVDS_IG_A_DATA_P<2>

NC_LVDS_IG_A_DATAN<3>

LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_N<2>

PCH_CLK33M_PCIOUT

NC_PCI_CLK33M_OUT3

PLT_RESET_L

LPC_CLK33M_SMC_R

AUD_IP_PERIPHERAL_DET

PCH_PCI_GNT3_L

PCI_INTD_L

NC_USB_4P

NC_USB_12N

NC_USB_12P

PCH_GPIO43_OC4_L

SDCONN_STATE_CHANGE

USB_HUB1_UP_P

USB_HUB1_UP_N

NC_USB_1P

NC_USB_1N

NC_USB_2N

PCH_PCI_GNT1_L

PCH_PCI_GNT2_L

USB_HUB2_UP_P

TP_PCI_CLK33M_OUT2

NC_LVDS_IG_B_DATAN<0>

NC_USB_13N

NC_USB_11P

NC_USB_7N

NC_USB_6P

NC_USB_6N

NC_USB_5P

NC_USB_5N

NC_USB_4N

NC_USB_3P

NC_USB_3N

NC_USB_2P

NC_USB_10N

USB_HUB2_UP_N

NC_USB_7P

NC_USB_10P

LVDS_IG_A_DATA_N<0>

USB_CAMERA_P

USB_CAMERA_N

LCD_IG_PWR_EN

PCH_LVDS_IBG

PCH_USB_RBIAS

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

NC_USB_11N

JTAG_GMUX_TMS

NC_LVDS_IG_CTRL_DATA

NC_LVDS_IG_CTRL_CLK

LCD_BKLT_PWM

NC_PCH_LVDS_VBG

T29_A_HV_EN_L

PCI_INTA_L

PCI_INTB_L PCI_INTC_L

NC_PCI_PME_L

PCI_INTE_L

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_DATA_P<1>

T29_MCU_INT_L

AUD_I2C_INT_L

LVDS_DDC_CLK

PP3V3_S0

PCH_GPIO10_OC6_L PCH_GPIO14_OC7_L

NC_USB_13P

20 OF 109

18 OF 86

18

6 7 8

24 26 30 31 32 33 48 50

54 55 72 73

7

16 17 19 20 22 46 71 72 73

23 24

23

32 73

6

18

23

23 33

18

80

6

6 7 8

12 16 17 19 20 22 23 26

27 29 33 36 37 40 41 42 46 48

49 50 51 52 54 57 61 62 71 72

73 74 75 77 85

23

OUT

BI

IN

CPU

NCTF

MISC

(6 OF 10)

GPIO

RSVD

TP38

SATA3GP/GPIO37

TACH5/GPIO69

TP18

STP_PCI*/GPIO34

GPIO15

SATA4GP/GPIO16

CLKOUT_PCIE7P

A20GATE

TACH3/GPIO7

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

TACH0/GPIO17

GPIO24/MEM_LED

SCLOCK/GPIO22

GPIO27

GPIO28

GPIO35

SATA2GP/GPIO36

SLOAD/GPIO38

SDATAOUT0/GPIO39

PCIECLKRQ6*/GPIO45

PCIECLKRQ7*/GPIO46

SATA5GP/GPIO49

SDATAOUT1/GPIO48

TACH4/GPIO68

GPIO57

TACH6/GPIO70

TACH7/GPIO71

CLKOUT_PCIE6N

CLKOUT_PCIE7N

CLKOUT_PCIE6P

BMBUSY*/GPIO0

TACH2/GPIO6

TACH1/GPIO1

PECI

RCIN*

THRMTRIP*

PROCPWRGD

TP1

TP2

TP3

TP4

TP6

TP5

TP7

TP8

TP9

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP19

TP20

TP21

TP22

TP24

TP25

TP26

TP27

TP29

TP28

TP30

TP31

TP32

TP33

TP34

TP35

TP36

NC_1

INIT3_3V*

TP40

TP39

TP37

VSS_NCTF

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

TS_VSS1 TS_VSS2 TS_VSS3

VSSADAC

TS_VSS4

IN

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC

IN

OUT

IN

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ALL RSVD TPs NC-ed per INTEL approval

(NC-ed per Intel chklist)

(IPU)

This has internal pull up and should not pulled low.

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(PU necessary?)

(PUs necessary?)

(PU necessary?)

10 23 78

402

5%

MF-LF

10K

1/16W

R2155

1

2

10K

5% 1/16W MF-LF

402

R2150

1

2

23 30

MF-LF

1/16W

5%

100K

402

R2190

1

2

6

47

5%

1/16W MF-LF

402

43

NOSTUFF

R2170

1 2

5%

402

MF-LF

0

1/16W

R2140

1 2

19 23

MOBILE

FCBGA

OMIT

COUGAR-POINT

U1800

P4

T7

V40

V42

V38

V37

G2

E8

E16

P8

K4

D6

C10

T14

C4

P37

T13

K12

AU16

AY11

P5

V8

M5

U2

V3

T5

M3

V13

N2

K1

D40

A42

H36

E38

C40

B41

C41

A40

AY10

BG26

C18

N30

H3

AH12

AM4

AM5

Y13

K24

L24

AB46

BJ26

AB45

B21

M20

BG46

BE28

BC30

BE32

BJ32

BC28

BH25

BE30

BF32

BG32

AV26

BB26

AU28

AY30

AU26

AY26

AV28

BJ16

AW30

BG16

AH38

AH37

AK43

AK45

AH8 AK11

AH10

AK10

A4

A44

BE1 BE49

BF1 BF49

BG2

BG48

BH3

BH47

BJ4 BJ44

A45

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

A46

F1

F49

A5 A6

B3

B47

BD1

BD49

U47

19

5%

1K

NOSTUFF

MF

1/20W

201

R2130

1

2

10K

5%

NOSTUFF

MF

1/20W

201

R2197

1

2

5%

10K

MF

1/20W

201

R2196

1

2

10K

5% 1/16W MF-LF

402

R2199

1

2

10K

5%

MF

1/20W

201

R2198

1

2

201

1/20W

MF

10K

5%

R2186

1

2

201

1/20W

MF

10K

5%

R2185

1

2

201

1/20W

MF

5%

10K

R2184

1

2

10K

5%

201

1/20W

MF

R2160

1

2

8

19 40

20K

5%

402

MF-LF

1/16W

R2111

1

2

23 62

19 42

8

19 23 34

8

19 34

6

19 47 56

NOSTUFF

10K

5%

MF

1/20W

201

R2110

1

2

10 78

402

MF-LF

390

1/16W

5%

R2156

1 2

16 19 45

MF

1/20W

201

10K

5%

R2191

1

2

19 45 46

5%

10K

201

1/20W

MF

R2192

1

2

100K

5%

1/20W

MF

201

R2193

1

2

10K

MF

1/20W

5%

201

R2194

1

2

10K

5%

201

1/20W

MF

R2114

1

2

MF

1/20W

201

5%

10K

R2115

1

2

201

1/20W

MF

5%

10K

R2175

1

2

10K

5%

201

1/20W

MF

R2174

1

2

10K

5%

201

1/20W

MF

R2173

1

2

MF

1/20W

201

5%

10K

R2172

1

2

1/20W

10K

201

MF

5%

R2112

1

2

201

10K

5%

MF

1/20W

R2113

1

2

46

PCH MISC

SYNC_MASTER=K91_MLB

SYNC_DATE=06/18/2010

PM_THRMTRIP_L_R

PM_THRMTRIP_L

NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P

PCH_A20GATE

PCH_RCIN_L

CPU_PECI

JTAG_ISP_TCK

NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P

JTAG_ISP_TDI

PCH_GPIO36_SATA2GP

ENET_LOW_PWR

PP3V3_SUS

T29_SW_RESET_L

SMC_RUNTIME_SCI_L

PCH_GPIO12

PP3V3_S0

NC_GPIO8

NC_GPIO35

SMC_SCI_L

NC_GPIO15

AUD_IPHS_SWITCH_EN

LPCPLUS_GPIO

ODD_PWR_EN_L

ISOLATE_CPU_MEM_L

PCH_GPIO24

JTAG_ISP_TCK

JTAG_ISP_TDI

FW_PLUG_DET_L

PP3V3_S0

FW_PLUG_DET_L

SMC_IG_THROTTLE_L

GMUX_INT

PCH_PECI

FW_PWR_EN

GMUX_INT

PP3V3_S0

SPIROM_USE_MLB

PCH_GPIO68_TACH4

PP3V3_S0

PCH_GPIO71_TACH7

PCH_INIT3V3_L

PCH_GPIO36_SATA2GP

PCH_GPIO70_TACH6

PCH_PROCPWRGD

PCH_GPIO69_TACH5

CPU_PWRGD

SMC_RUNTIME_SCI_L

PCH_GPIO46

JTAG_ISP_TDO

PP3V3_T29

T29_SW_RESET_L

SMC_SCI_L

PCH_GPIO24

SPIROM_USE_MLB

PCH_GPIO12

SMC_IG_THROTTLE_L

WOL_EN

PCH_GPIO46

PP3V3_SUS

PCH_GPIO71_TACH7

PCH_GPIO70_TACH6

PCH_GPIO69_TACH5

PCH_GPIO68_TACH4

PP3V3_S0

PCH_INIT3V3_L

JTAG_ISP_TDO

ENET_LOW_PWR

PP3V3_S5

PP3V3_T29

ODD_PWR_EN_L

FW_PWR_EN

WOL_EN

21 OF 109

19 OF 86

6

10 45 78

8

19 23 34

6

8

19 34

19 23

19 23 33 37

7

16 17 18 19

20 22 46 71 72

73

19 36

19

6 7 8

12 16 17 18

19 20 22 23

26 27 29

33 36 37 40

41 42 46

48 49 50 51

52 54 57

61 62 71 72

73 74 75

77 85

19

8

19 34

8

19 40

6 7 8

12 16 17 18 19

20 22 23 26 27 29 33 36 37 40

41 42 46 48 49 50 51

52 54 57 61 62 71 72 73 74

75 77 85

19 40

19

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57

61 62 71 72 73 74 75 77 85

19

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

19

19 23

19

19 45 46

19 23

7

16 19 26 34 35 36

19 36

16 19 45

19

6

19 47 56

19

19 23

19 73

19 23

7

16 17 18 19 20 22 46

71 72 73

19

6 7 8

12

16 17 18

19 20 22 23 26

27 29 33

36 37 40 41 42

46 48 49

50 51 52 54 57

61 62 71

72 73 74 75 77

85

19

8

19 34

19 23 33 37

6 7 8

17 20 22 23 24

26 30 46 56 66

72 73 74 76

85

19 42

19 40

19 73

VSSALVDS

VCCTX_LVDS

VCCDFTERM

VCCALVDS

VCCVRM_3_DMI

VCC3_3_7_HVCMOS

VCC3_3_5_PCI

VCCDFTERM

VCCSPI

VCCDFTERM

VCC3_3_6_HVCMOS

VCCIO_18_FDI

VCCIO_21_PCIE

VCCIO_20_PCIE

VCCIO_11_PLLPCIE

VCCIO_25_PCIE

VCCIO_24_PCIE

VCCCLKDMI

VCCCORE

VCCIO_27_DP

VCCIO_26_PCIE

VCCIO_19_PCIE

VCCIO_22_PCIE

VCCIO_10_PLLFDI

VCCIO_23_PCIE

VCCIO_17_FDI

VCCIO_28_DP

VCCDMI_0_FDI

VCCAPLLEXP

VCCCORE

VCCDMI_1_DMI

VCCCORE VCCCORE VCCCORE

VCCAFDIPLL

VCCCORE

VCCVRM_2_FDI

VCCADAC

VCCCORE

FDI CRT

DFT/SPI

DMI

HVCMOS

VCCIO

VCC CORE

LVDS

(7 OF 10)

VCCSUSHDA

VCCSUS3_3_3_USB VCCSUS3_3_4_USB

VCCSUS3_3_2_USB

VCCSUS3_3_1_USB

VCCIO_4_USB

VCCIO_2_USB VCCIO_3_USB

VCCIO_1_USB

VCCIO_0_USB

VCCASW_0_MISC

VCCASW_2_MISC VCCASW_1_MISC

VCCIO_8_SATA

VCCIO_6_SATA VCCIO_7_SATA

VCCAPLLSATA

VCCVRM_1_SATA

VCCIO_9_PLLSATA3

VCCIO_15_SATA3 VCCIO_16_SATA3

VCC3_3_0_SATA

VCCIO_5_PLLSATA

VCC3_3_2_GPIO VCC3_3_3_GPIO VCC3_3_1_GPIO

VCCSUS3_3_7_GPIO VCCSUS3_3_8_GPIO

VCCSUS3_3_5_GPIO VCCSUS3_3_6_GPIO

V5REF

VCCRTC

V_PROC_IO

DCPSUSBYP

VCCACLK

DCPRTC

VCCADPLLA VCCADPLLB

DCPSST

DCPSUS_2_CLK

DCPSUS_1_CLK

VCCDIFFCLKN_2

VCCDIFFCLKN_1

VCCDIFFCLKN_0

VCCDSW3_3

VCCIO_13_CLK

VCC3_3_4_CLK

VCCASW_4_CLK VCCASW_5_CLK VCCASW_6_CLK VCCASW_7_CLK VCCASW_8_CLK

VCCAPLLDMI2

VCCASW_20_CLK

VCCASW_10_CLK VCCASW_11_CLK VCCASW_12_CLK VCCASW_13_CLK VCCASW_14_CLK VCCASW_15_CLK VCCASW_16_CLK VCCASW_17_CLK VCCASW_18_CLK VCCASW_19_CLK

VCCASW_9_CLK

VCCVRM_0_CLK

VCCASW_22_CLK

VCCASW_21_CLK

VCCSSC

VCCSUS3_3_9_USB

VCCIO_14_PLLUSB

V5REF_SUS

VCCSUS3_3_0_SUS

DCPSUS_3_SUS

VCCASW_3_CLK

DCPSUS_0_CLK

VCCIO_12_PLLCLK

CPURTC

HDA

USB

MISC

SATA

PCI/GPIO/

LPC

CLK/MISC

(8 OF 10)

NC

NC NC

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC-ed per DG

VCCAFDIPLL pin left as NC per DG

1.44 A Max, 474mA Idle

VCCAPLLSATA pin left as NC per DG

10 mA Max, 1mA Idle

VCCACLK pin left as NC per DG

AL24 left as NC per DG

55mA Max, 5mA Idle

NC-ed per DG

PCH output, for decoupling only

VCCAPLLDMI2 pin left as NC per DG

68 mA

(PCH DPLLA PWR)

PCH VCCADPLLA Filter

PCH VCCADPLLB Filter (PCH DPLLB PWR)

69 mA

MOBILE

OMIT

FCBGA

COUGAR-POINT

U1800

BH29

V33 V34

U48

BG6

AK36

BJ22

AB36

AA23

AC23

AG27 AG29

AJ23 AJ26

AJ27

AJ29 AJ31

AD21

AD23

AF21 AF23

AG21

AG23 AG24

AG26

AG16

AG17 AJ16

AJ17

AU20

AT20

AP17

AN19

AN16 AN17

AN21

AN26 AN27

AP21

AP23 AP24

AP26

AT24

AN33 AN34

V1

AM37 AM38

AP36

AP37

AP16

AT16

AK37

MOBILE

FCBGA

OMIT

COUGAR-POINT

U1800

N16

V16

AL24

T17

V19

AN23

V12

P34

M26

BJ8

AJ2

T34

AA16

W16

T38

AD49

BD47 BF47

BH23

AK1

T19

AC26

AC27 AC29

AC31

AD29 AD31

W21

W23 W24

W26

V21

W29 W31

W33

T21

AA19 AA21

AA24

AA26 AA27

AA29

AA31

AF33

AF34

AG34

T16

N26

AL29

AF17

T26

AH13 AH14

P26 P28

T27

T29

AF13

AC16

AC17 AD17

AF14

A22

AG33

AN24

T23 T24

V23

V24

N20

N22

P20 P22

P24

P32

Y49

AF11

10%

0201

X5R-CERM

16V

PLACE_NEAR=U1800.A22:2.54mm

0.1UF

C2232

1

2

PLACE_NEAR=U1800.A22:2.54mm

402

CERM

6.3V

10%

1UF

C2231

1

2

0.1UF

PLACE_NEAR=U1800.V16:2.54mm

20% 10V

402

CERM

C2222

1

2

PLACE_NEAR=U1800.N16:2.54mm

10V

402

20%

CERM

0.1UF

C2210

1

2

5%

0

MF-LF

1/16W

402

R2260

1 2

1/16W MF-LF

402

0

5%

R2265

1 2

10%

0201

X5R-CERM

16V

PLACE_NEAR=U1800.A22:2.54mm

0.1UF

C2233

1

2

CERM

PLACE_NEAR=U1800.BD47:2.54MM

10%

402

6.3V

1UF

C2261

1

2

402

PLACE_NEAR=U1800.BF47:2.54MM

10%

6.3V

1UF

CERM

C2266

1

2

10V

0.1UF

CERM 402

20%

C2260

1

2

20%

402

CERM

10V

0.1UF

C2265

1

2

PCH POWER

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V

PP1V05_S0

PP1V05_S0_PCH_VCCADPLLA

PP1V05_S0

PP5V_SUS_PCH_V5REFSUS

PP1V05_S0

PP1V8_S0

PP3V3_S0_PCH_VCC3_3_CLK_F

PP1V05_S0

PP3V3_S5

PP1V05_S0_PCH_VCCADPLLB

MIN_LINE_WIDTH=0.2 mm

PPVOUT_G3_PCH_DCPRTC

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

TP_PPVOUT_PCH_DCPSUSBYP

PP5V_S0_PCH_V5REF

PP3V3_S0

PP1V8_S0

PP3V3_S0_PCH_VCCA_DAC_F

PP1V8_S0

PP1V05_S0

TP_1V05_S0_PCH_VCCAPLLEXP

PP1V05_S0

PP1V05_S0_PCH_VCCCLKDMI_F

PP1V05_S0

PP3V3_S5

PP3V3_S0

PP1V8_S0

PP3V3_S0

PPVRTC_G3H

PP1V05_S0

PP3V3_S0

PP3V3_SUS

PP1V05_S0

PP1V8_S0

PP3V3_S0

PP1V8_S0_PCH_VCCTX_LVDS_F

PP1V5_S0

PP3V3_SUS

PP1V05_S0

PP3V3_SUS

PP1V05_S0_PCH_VCCADPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLA

PP1V05_S0_PCH_VCCADPLLB

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

22 OF 109

20 OF 86

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

20

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

22

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7

14 17 20 22 26 71

22

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

20

22

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7

14 17 20 22 26 71

22

6 7

14 17 20 22 26 71

6 7 9

10 12 14 16 17 20 22

23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22

23 36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22

23 36 40 45 68 70 73

22

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 8

17 19 20 22 23 24 26

30 46 56 66 72 73 74 76 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7

14 17 20 22 26 71

6 7 8

12 16 17 18 19 20 22

23 26 27 29 33 36 37 40 41

42 46 48 49 50 51 52 54 57

61 62 71 72 73 74 75 77 85

7

16 17 26

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

7

16 17 18 19 20 22 46 71 72 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7

14 17 20 22 26 71

6 7 8

12 16 17 18 19 20 22

23 26 27 29 33 36 37 40 41

42 46 48 49 50 51 52 54 57

61 62 71 72 73 74 75 77 85

22

7

16 22 26 42 57 71

7

16 17 18 19 20 22 46 71 72 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

7

16 17 18 19 20 22 46 71 72 73

7

71 20

20

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

VSS

(9 OF 10)

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

(10 OF 10)

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

COUGAR-POINT

MOBILE

FCBGA

OMIT

U1800

AJ3

N24

AB14

AL48

AM11 AM14

AM36

AM39 AM43

AM45

AM46 AM7

AN2

AB39

AN29 AN3

AN31 AP12

AP13

AP19 AP28

AP30

AP32 AP38

AB4

AP4

AP42 AP46

AP8 AR2

AR48

AT11 AT13

AT18

AT22

AB43

AT26

AT28

AT30 AT32

AT34 AT39

AT42

AT46 AT7

AU24

AB5

AU30 AV11

AV16

AV20 AV24

AV30 AV38

AV4

AV43 AV8

AB7

AW14

AW18 AW2

AW22

AW26 AW28

AW32 AW34

AW36

AW40

AC19

AW48

AY12

AY22 AY28

AY4

AY42 AY46

AY8 B11

B15

AC2

B19 B23

B27

B31

AC21

AC24

BG29

AC33 AC34

AC48

AD10 AD11

AD12 AD13

AD14

AD16 AD19

H5

AD24

AD26 AD27

AD33

AD34 AD36

AD37 AD38

AD39

AD4

AA17

AD40

AD42

AD43 AD45

AD46

AD47

AD8

AE2 AE3

AF10

AA2

AF12 AF16

AF19

AF24 AF26

AF27

AF29 AF31

AF38

AF4

AA3

AF42

AF46

AF5

AF7

AF8

AG19

AG2

AG31 AG48

AH11

AA33

AH3

AH36

AH39 AH40

AH42

AH46

AH7

AJ19

AJ21 AJ24

AA34

AJ33 AJ34

AK12

AK3

AK38

AK4

AK42

AK46

AK8 AL16

AB11

AL17 AL19

AL2

AL21 AL23

AL26

AL27 AL31

AL33

AL34

MOBILE

COUGAR-POINT

FCBGA

OMIT

U1800

B35

B39 B43

B7

BB12 BB16

BB20

BB22 BB24

BB28

BB30 BB38

BB4 BB46

BC14

BC18

BC2

BC22

BC26 BC32

BC34

BC36 BC40

BC42 BC48

BD3

BD46

BD5

BE10

BE22 BE26

BE40

BF10 BF12

BF16 BF20

BF22

BF24 BF26

BF28

BF30 BF38

BF40

BF8 BG17

BG21 BG22

BG24

BG33 BG41

BG44

BG8 BH11

BH15

BH17 BH19

BH27 BH31

BH33

BH35 BH39

BH43

BH7

C22

D12

D16

D18

D22

D24

D26

D3 D30

D32

D34 D38

D42

D8 E18

E26

F3

F45

G14 G18

G20

G26 G28

G36

G48

H10 H12

H16

H18 H22

H24

H26 H30

H32

H34 H46

K18 K26

K39

K46 K7

L18

L2 L20

L26

L28 L36

L48 M12

M14

M18 M22

M24

M30 M32

M34

M38 M4

M42 M46

M8

N18 N47

P11

P16 P18

P30

P40 P43

P47 P7

R2

R48 T12

T31

T33 T36

T37

T4 T46

T47 T8

V11

V26 V27

V29

V31 V36

V39

V43 V7

W17 W19

W2

W27 W34

W48

Y12 Y38

Y4

Y42 Y46

Y8 V17

AP3

AP1 BE16

BC16

BG28 BJ28

PCH GROUNDS

SYNC_DATE=05/27/2010

SYNC_MASTER=K91_MLB

23 OF 109

21 OF 86

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1 mA S0-S5

PCH VCCIO BYPASS

NEED PWR CONSTRAINT

PCH V5REF_SUS Filter & Follower

<1 MA S0-S5

PCH VCCSUS3_3 BYPASS

1 mA

<1 MA

(PCH 1.05V CORE PWR)

PCH VCCSUSHDA BYPASS

NEED PWR CONSTRAINT

(PCH SUSPEND USB 3.3V PWR)

PCH VCCCORE BYPASS

PCH VCCIO BYPASS

(PCH USB 1.05V PWR)

(PCH HD Audio 3.3V/1.5V PWR)

PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)

(PCH Reference for 5V Tolerance on USB)

(PCH PCI 3.3V PWR)

PCH VCC3_3 BYPASS

1UF

402

10V X5R

10%

PLACE_NEAR=U1800.P34:2.54mm

C2439

1

2

100

5%

402

1/16W MF-LF

R2405

2

1

20%

402

CERM

10V

PLACE_NEAR=U1800.M26:2.54mm

0.1UF

C2438

1

2

BAT54DW-X-G

SOT-363

D2400

1

6

5

1/16W

5%

10

402

MF-LF

R2404

2

1

SOT-363

BAT54DW-X-G

D2400

4

3

2

402

X5R

0.1UF

16V

10%

PLACE_NEAR=U1800.AJ2:2.54mm

C2423

1

2

PLACE_NEAR=U1800.AJ16:2.54mm

0.1UF

20%

CERM 402

10V

C2440

1

2

PLACE_NEAR=U1800.P32:2.54mm

0.1UF

20%

CERM

10V

402

C2441

1

2

402

CERM

10%

1UF

6.3V

PLACE_NEAR=U1800.AT20:2.54mm

C2419

1

2

402

0.1UF

16V X5R

10%

PLACE_NEAR=U1800.BH29:2.54mm

C2421

1

2

PLACE_NEAR=U1800.V24:2.54mm

0.1UF

10%

402

16V X5R

C2413

1

2

10%

X5R

16V

0.1UF

402

PLACE_NEAR=U1800.BJ8:2.54mm

C2417

1

2

X5R 402

6.3V

4.7UF

20%

PLACE_NEAR=U1800.BJ8:2.54mm

C2416

1

2

X5R

16V

402

0.1UF

10%

PLACE_NEAR=U1800.P24:2.54mm

C2484

1

2

0.1UF

PLACE_NEAR=U1800.AA16:2.54mm

402

X5R

10% 25V

C2485

1

2

CERM

10%

1UF

402

6.3V

PLACE_NEAR=U1800.AN27:2.54mm

C2463

1

2

PLACE_NEAR=U1800.AG33:2.54mm

1UF

402

CERM

6.3V

10%

C2475

1

2

PLACE_NEAR=U1800.AF34:2.54mm

1UF

10%

CERM 402

6.3V

C2434

1

2

PLACE_NEAR=U1800.AF17:2.54mm

CERM

6.3V

402

1UF

10%

C2469

1

2

1UF

10%

402

6.3V CERM

PLACE_NEAR=U1800.AN27:2.54mm

C2414

1

2

PLACE_NEAR=U1800.AN27:2.54mm

10UF

6.3V

20%

X5R 603

C2401

1

2

6.3V CERM 402

PLACE_NEAR=U1800.AC17:2.54mm

1UF

10%

C2452

1

2

0.1UF

PLACE_NEAR=U1800.T16:2.54mm

402

20%

CERM

10V

C2499

1

2

CERM

1UF

402

6.3V

10%

PLACE_NEAR=U1800.V1:2.54mm

C2442

1

2

PLACE_NEAR=U1800.T34:2.54mm

25V

0.1UF

10%

X5R 402

C2486

1

2

PLACE_NEAR=U1800.AH13:2.54mm

10%

6.3V

402

CERM

1UF

C2444

1

2

10%

6.3V

1UF

CERM 402

PLACE_NEAR=U1800.P28:2.54mm

C2446

1

2

402

PLACE_NEAR=U1800.V33:2.54mm

16V X5R

10%

0.1UF

C2424

1

2

PLACE_NEAR=U1800.AG26:2.54mm

20%

10UF

6.3V X5R 603

C2460

1

2

402

1UF

10%

CERM

6.3V

PLACE_NEAR=U1800.AG24:2.54mm

C2482

1

2

10%

CERM

1UF

PLACE_NEAR=U1800.AD21:2.54mm

6.3V

402

C2481

1

2

10%

1UF

CERM

6.3V

PLACE_NEAR=U1800.AJ27:2.54mm

402

C2483

1

2

10%

402

1UF

CERM

6.3V

PLACE_NEAR=U1800.AN27:2.54mm

C2407

1

2

1UF

CERM

10%

402

6.3V

PLACE_NEAR=U1800.AN27:2.54mm

C2429

1

2

6.3V

20%

CERM

805

22UF

PLACE_NEAR=U1800.AC27:2.54mm

C2420

1

2

PLACE_NEAR=U1800.AC27:2.54mm

6.3V

10%

1UF

CERM 402

C2496

1

2

PLACE_NEAR=U1800.AC27:2.54mm

CERM

1UF

402

6.3V

10%

C2456

1

2

PLACE_NEAR=U1800.AC27:2.54mm

1UF

CERM

6.3V

10%

402

C2426

1

2

402

1/16W

5%

1

MF-LF

R2415

1 2

10UF

20%

CERM-X5R

PLACE_NEAR=U1800.AB36:2.54mm

0402-1

6.3V

C2411

1

2

PLACE_NEAR=U1800.BJ8:2.54mm

402

16V

10%

X5R

0.1UF

C2430

1

2

PLACE_NEAR=U1800.AC27:2.54mm

22UF

20%

6.3V

805

CERM

C2428

1

2

16V

402

CERM

10%

0.01UF

PLACE_NEAR=U1800.AM37:2.54mm

C2406

1

2

PLACE_NEAR=U1800.AM37:2.54mm

CERM

805

6.3V

20%

22UF

C2400

1

2

16V

0.01UF

CERM

402

10%

PLACE_NEAR=U1800.AM37:2.54mm

C2408

1

2

0805

0.1UH

L2407

1 2

1/16W MF-LF

5%

0

402

R2450

1 2

PLACE_NEAR=U1800.U48:2.54mm

0.01UF

10% 16V

402

CERM

C2455

1

2

PLACE_NEAR=U1800.U48:2.54mm

402

0.1UF

X5R

10% 16V

C2451

1

2

402

MF-LF

1/16W

1

5%

R2451

1 2

PLACE_NEAR=U1800.T38:2.54mm

1UF

402

10V

10%

X5R

C2454

1

2

0603

10UH-0.12A-0.36OHM

L2451

1 2

CERM 402

1UF

10%

PLACE_NEAR=U1800.P22:2.54mm

6.3V

C2476

1

2

0603

10UH-0.12A-0.36OHM

L2406

1 2

20%

6.3V

10UF

PLACE_NEAR=U1800.U48:2.54mm

X5R 603

C2450

1

2

10UF

20%

PLACE_NEAR=U1800.T38:2.54mm

0402-1

6.3V

CERM-X5R

C2453

1

2

SYNC_MASTER=K91_MLB

SYNC_DATE=06/25/2010

PCH DECOUPLING

PP3V3_S0_PCH_VCC3_3_CLK_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP1V8_S0

PP3V3_S0

MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM

PP1V05_S0_PCH_VCCCLKDMI_R

PP1V8_S0_PCH_VCCTX_LVDS_F

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25MM

PP3V3_S0

PP1V05_S0

PP3V3_S5

PP3V3_S0

PP1V05_S0

PP3V3_SUS

PP1V8_S0

PP3V3_S0

PP5V_SUS_PCH_V5REFSUS

PP1V05_S0

PP5V_S0_PCH_V5REF

PP3V3_S5

PP1V5_S0

PP1V05_S0

PP3V3_SUS

PP1V05_S0

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_F

PP3V3_S0

PP1V05_S0

MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S0_PCH_V5REF

MAKE_BASE=TRUE

PP5V_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_S0_PCH_VCCA_DAC_F

PP1V05_S0

PP3V3_S0

VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3MM

PP5V_SUS_PCH_V5REFSUS

MIN_NECK_WIDTH=0.25MM

PP5V_SUS

PP3V3_SUS

24 OF 109

22 OF 86

20

6 7

14 17 20 22

26 71

6 7 8 12 16

17 18

19 20

22 23

26 27

29 33

36 37

40 41

42 46

48 49

50 51

52 54

57 61

62 71

72 73

74 75

77 85

20

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42

46 48 49 50 51 52 54 57 61

62 71 72 73 74 75 77 85

6 7 9

10 12 14 16 17

20 22 23 36 40

45 68 70 73

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

7

16 17 18 19 20 22 46 71 72

73

6 7

14 17 20 22 26 71

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

20 22

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

20 22

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

7

16 20 26 42 57 71

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

7

16 17 18 19 20 22 46 71 72

73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

20

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

20 22

6 7

42 47 52 54 65 68 70 72

73 77

20

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

20 22

7

72

7

16 17 18 19 20 22 46 71 72

73

IN

IN IN

IN

IN IN IN IN

IN IN IN

OUT

IN

OUT OUT

NC

IN

OUT

IN

BI IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT OUT

IN IN

NC

BI

IN

IN IN

BI IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OBSFN_C0

OBSFN_C1

OBSDATA_C0

OBSDATA_C3

VCC_OBS_CD

RESET#/HOOK6 DBR#/HOOK7

1K series R on PCH Support P. 28

OBSDATA_C1

OBSDATA_C2

OBSFN_D0

OBSFN_D1

OBSDATA_D0

PCH MINI XDP

OBSDATA_B2

HOOK2

OBSDATA_C0

OBSDATA_A1

OBSDATA_D1

VCC_OBS_AB

517S0774

OBSDATA_B2 OBSDATA_B3

TMS

517S0774

OBSDATA_C1

OBSDATA_C2

DESIGN NOTE:

SNB XDP CONN

TRSTn

TDI

SDA

TCK0

TDI

OBSDATA_C3

TRSTn

OBSFN_D0

OBSDATA_D1

OBSDATA_D0

TCK0

PLACEMENT NOTE: PLACE TCK/TDI/TMS/TRST*

TERM NEAR CPU

PLACEMENT NOTE:

TERM NEAR PCH

PLACE TCK/TDI/TMS/TRST*

PLACE TDO TERM NEAR

OBSFN_B0

OBSDATA_A1

TDO

TCK1

PLACEMENT NOTE:

PCH XDP CONN

OBSFN_C1

HOOK3

TDO

ITPCLK#/HOOK5

TMS

ODT AVAILABLE ON JTAG

HOOK1

OBSFN_B0

OBSFN_D1

OBSDATA_D2

OBSDATA_A2

OBSDATA_A3

OBSFN_B1

OBSDATA_B0

PWRGD/HOOK0

SCL

OBSDATA_D3

OBSDATA_A0

OBSFN_A0

OBSFN_A1

XDP_PRESENT#

HOOK2

XDP_PRESENT#

PWRGD/HOOK0

RESET#/HOOK6

VCC_OBS_CD

DBR#/HOOK7

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

VCC_OBS_AB

SDA

HOOK3

ITPCLK#/HOOK5

OBSDATA_A3

OBSDATA_A0

OBSFN_A1

OBSFN_A0

ITPCLK/HOOK4

OBSDATA_D3OBSDATA_B3

OBSDATA_B0

OBSDATA_B1

OBSDATA_A2

OBSDATA_D2

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

SCL

OBSFN_B1

ITPCLK/HOOK4

OBSDATA_B1

OBSFN_C0

PROCESSOR MINI XDP

TCK1

PLACE TDO TERM NEAR

PLACEMENT NOTE:

HOOK1

9

10 26

10 78

9

78

10

9

78

9

78

9

78

402

MF-LF

XDP

1K

5%

1/16W

PLACE_NEAR=U100.B50:2.54MM

R2501

1 2

9

23 78

16 40

16 32

9

78

19 62

1/16W

5%

0

402

MF-LF

XDP

PLACE_NEAR=U1800.V10:2.54MM

R2576

1 2

XDP

5% MF-LF

402

1/16W

0

PLACE_NEAR=U1800.M1:2.54MM

R2577

1 2

19

16 42

MF-LF

5%

1/16W

0

402

XDP

PLACE_NEAR=U1800.U2:2.54MM

R2579

1 2

8

19 34

19 33 37

9

78

26

16 23

9

78

XDP

1/16W

0

5% MF-LF

402

PLACE_NEAR=U1800.K20:2.54MM

R2580

1 2

18

16 23

9

78

18 24

F-ST-SM-HF

XDP_CONN

CRITICAL

DF40C-60DS-0.4V

J2550

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

7 8

9

PLACE_NEAR=U1800.J3:2.54MM

402

5%

51

XDP

MF-LF

1/16W

R2556

1

2

16 23 27 29 31 42 48 62 77 81

10 23 26 78

XDP

10%

X5R 402

16V

0.1uF

C2580

1

2

XDP

0.1uF

X5R

10%

402

16V

C2581

1

2

19

PLACE_NEAR=U4900.D10:2.54MM

402

5%

1/16W

0

XDP

MF-LF

R2502

1 2

17 23 45

5%

1/16W

0

XDP

402

PLACE_NEAR=U4900.D10:2.54MM

MF-LF

R2585

1 2

17 23 45

MF-LF

402

5%

XDP

1/16W

910

R2504

1 2

17 26

18

1K

402

XDP

5% MF-LF

1/16W

PLACE_NEAR=J2550.39:2.54MM

R2584

1 2

26 45 73

1/16W

MF-LF

XDP

0

5%

402

PLACE_NEAR=U1800.A16:2.54MM

R2581

1 2

18 33

10 23 78

10 23 26 78

MF-LF

XDP

1/16W

402

5%

0

PLACE_NEAR=U1800.K12:2.54MM

R2582

1 2

19

5%

402

0

XDP

MF-LF

1/16W

PLACE_NEAR=U1800.P8:2.54MM

R2578

1 2

19 30

5% MF-LF

1/16W

402

XDP

PLACE_NEAR=U1800.B17:2.54MM

0

R2586

1 2

XDP

MF-LF

0

1/16W

5%

PLACE_NEAR=U1800.C16:2.54MM

402

R2587

1 2

18

9

10 23 78

16 78

402

MF-LF

5%

XDP

1/16W

PLACE_NEAR=R1841.1:2.54MM

0

R2515

1 2

XDP

0

402

MF-LF

5%

1/16W

PLACE_NEAR=R1840.1:2.54MM

R2516

1 2

XDP

5%

MF-LF

1K

402

PLACE_NEAR=R1125.1:2.54MM

1/16W

R2505

1 2

16 75

PLACE_NEAR=J2550.52:2.54MM.

402

5%

MF-LF

1/16W

XDP

51

R2550

1

2

10 23 78

PLACE_NEAR=U1800.K5:2.54MM

5%

XDP

1/16W

402

MF-LF

51

R2551

1

2

PLACE_NEAR=U1800.H7:2.54MM

51

XDP

1/16W

5%

402

MF-LF

R2552

1

2

5%

0

402

MF-LF

1/16W

XDP_CPU:BPM

R2560

1 2

402

0

1/16W

MF-LF

5%

XDP_CPU:BPM

R2561

1 2

1/16W

0

MF-LF

XDP_CPU:BPM

5%

402

R2562

1 2

MF-LF

1/16W

5%

0

402

XDP_CPU:BPM

R2563

1 2

5%

MF-LF

1/16W

XDP_CPU:CFG

0

402

R2564

1 2

10 23 78

402

5%

0

MF-LF

XDP_CPU:CFG

1/16W

R2566

1 2

1/16W

402

MF-LF

0

5%

XDP_CPU:CFG

R2567

1 2

XDP_CPU:CFG

1/16W

402

0

MF-LF

5%

R2565

1 2

1K

NOSTUFF

5%

MF-LF

1/16W

402

R2540

1

2

9

23 78

0.1uF

402

X5R

10%

XDP

16V

C2501

1

2

9

78

16V

XDP

X5R

0.1uF

10%

402

C2500

1

2

10 78

9

78

9

78

9

78

9

78

16 23 27 29

31 42

48 62 77 81

16 23 27 29 31 42 48 62

77 81

10 23 78

5%

PLACE_NEAR=U1000.B46:1MM

MF-LF

402

1/16W

1K

XDP

R2500

1 2

9

78

10 19 78

9

78

F-ST-SM-HF

CRITICAL

XDP_CONN

DF40C-60DS-0.4V

J2500

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

7 8

9

PLACE_NEAR=U1000.L59:2.54MM

5%

MF-LF

1/16W

XDP

51

402

R2510

1

2

402

MF-LF

1/16W

5%

51

XDP

PLACE_NEAR=U1000.M60

R2511

1

2

51

5%

1/16W

XDP

MF-LF

402

PLACE_NEAR=U1000.L55:2.54MM

R2512

1

2

5%

MF-LF

402

XDP

1/16W

51

PLACE_NEAR=U1000.J58:2.54MM

R2513

1

2

402

5%

MF-LF

51

XDP

1/16W

PLACE_NEAR=U1000.L56:2.54MM

R2514

1

2

10 78

CPU & PCH XDP

SYNC_MASTER=ANNE_K90I

SYNC_DATE=06/22/2010

XDP_PCH_SDCONN_STATE_RST_L

XDP_PCH_SDCONN_DET_L

XDP_CPU_PWRGD

CPU_CFG<14>

PP1V05_S0

CPU_CFG<9>

CPU_CFG<7>

AP_CLKREQ_L

FW_CLKREQ_L

ISOLATE_CPU_MEM_L

PCH_GPIO46

USB_HUB_SOFT_RESET_L

ALL_SYS_PWRGD

XDP_BPM_L<3>

CPU_CFG<11>

XDP_OBSDATA_B<2> XDP_OBSDATA_B<3>

XDP_CPU_TCK XDP_CPU_TRST_L

PP1V05_S0

XDP_CPU_TDO XDP_CPU_TDI XDP_CPU_TMS

CPU_CFG<13>

XDP_OBSDATA_B<1>

CPU_CFG<0>

XDP_CPU_CFG<0>

XDP_CPU_PWRBTN_L

XDP_CPU_TRST_L

XDP_CPU_TDO

SMBUS_PCH_CLK

SDCONN_STATE_RST_L

PM_PWRBTN_L

AUD_IPHS_SWITCH_EN

ITPXDP_CLK100M_N

CPU_CFG<12>

XDP_BPM_L<5>

CPU_CFG<2>

CPU_CFG<17>

XDP_CPU_CLK100M_P

PCH_GPIO43_OC4_L

XDP_PCH_PWRBTN_L

NC_TP_XDP_PCH_OBSFN_B<0>

SMBUS_PCH_DATA

XDP_PCH_TCK

XDP_PCH_TMS

XDP_PCH_TDI

XDP_CPU_PRDY_L

XDP_CPU_TCK XDP_CPU_TMS

XDP_DBRESET_L

CPU_CFG<6>

CPU_CFG<5>

CPU_CFG<4>

CPU_CFG<8>

XDP_PCH_TDO XDP_PCH_TDI

XDP_BPM_L<2>

CPU_CFG<10>

XDP_OBSDATA_B<0>

NC_TP_XDP_PCH_OBSFN_A<1>

XDP_PCH_TMS

TP_XDP_PCH_TRST_L

XDPPCH_PLTRST_L

XDP_PCH_TCK

ITPXDP_CLK100M_P

XDP_BPM_L<0>

CPU_CFG<0>

CPU_CFG<3>

CPU_CFG<1>

PLT_RST_BUF_L

SDCONN_STATE_CHANGE

ENET_PWR_EN

NC_TP_XDP_PCH_OBSFN_A<0>

SMBUS_PCH_CLK

NC_TP_XDPPCH_HOOK2 NC_TP_XDPPCH_HOOK3

XDP_DBRESET_L

XDP_PCH_TDO

XDP_PCH_S5_PWRGD

PCH_GPIO36_SATA2GP

PCH_GPIO14_OC7_L

PCH_GPIO10_OC6_L

XDP_PCH_ENET_PWR_EN

NC_TP_XDP_PCH_OBSFN_B<1>

XDP_PCH_USB_HUB_SOFT_RST_L

XDP_PCH_GPIO46

CPU_PWRGD

XDP_BPM_L<7>

SMBUS_PCH_DATA

XDP_CPU_CLK100M_N

XDP_CPU_TDI

NC_TP_XDP_PCH_HOOK5

NC_TP_XDP_PCH_HOOK4

CPU_CFG<16>

XDP_CPURST_L

XDP_VR_READY

PP3V3_S0

PM_PCH_SYS_PWROK

PM_PWRBTN_L

CPU_CFG<15>

XDP_BPM_L<6>

XDP_BPM_L<4>

XDP_FW_CLKREQ_L

NC_TP_XDP_PCH_OBSFN_D<0>

XDP_AP_CLKREQ_L

SMC_IG_THROTTLE_L

ENET_LOW_PWR

XDP_PCH_AUD_IPHS_SWITCH_EN

JTAG_ISP_TCK

NC_TP_XDP_PCH_OBSFN_D<1>

SATARDRVR_EN

DP_AUXCH_ISOL

PP3V3_S5

XDP_PCH_ISOLATE_CPU_MEM_L

PP1V05_SUS

XDP_BPM_L<1>

XDP_CPU_PREQ_L

25 OF 109

23 OF 86

6

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70

73

10 23 78

6 7 9

10 12

14 16 17 20

22 23 36 40

45 68 70 73

10 23 78

78

6

16 23

6

78

6

78

6 7 8

12 16 17 18 19 20 22 26

27 29 33 36 37 40 41 42 46 48

49 50 51 52 54 57 61 62 71 72

73 74 75 77 85

6

6 7 8

17 19 20 22 24 26 30 46

56 66 72 73 74 76 85

6

7

71

G

D

S

G

D

S

BI

IN

BI BI

BI

BI BI

BI

IN

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1* OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NC NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2*

SYM VER 1

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1* OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NC NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2*

SYM VER 1

BI

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1 0 Port 1 and 2 are non removable

BOM TABLE

0 0 All ports are removable

NON_REM1 NON_REM0 DESCRIPTION

0 1 Port 1 is non removable

SD Card/Express Card

IPU IPU

IPU

Trackpad/Keyboard

External A

IPU

Bluetooth

1 1 Port 1, 2, and 3 are non removable

External B

T29

External C

IR Receiver

10K

1/16W MF-LF 402

5%

R2641

1

2

2N7002DW-X-G

SOT-363

Q2640

3

5

4

MF-LF

1/16W

20K

5%

402

R2640

1 2

2N7002DW-X-G

SOT-363

Q2640

6

2

1

NOSTUFF

100PF

402

CERM

50V

5%

C2641

1

2

0.47UF

CERM-X5R 402

6.3V

10%

C2640

1

2

18PF

402

CERM

50V

5%

CRITICAL

C2619

1

2

1M

1/16W MF-LF

5%

CRITICAL

402

R2630

1 2

5X3.2X1.4-SM

CRITICAL

24.000M-60PPM-16PF

Y2600

1 2

402

5% 50V CERM

18PF

CRITICAL

C2620

1

2

4.7UF

603

X5R

6.3V

20%

BYPASS=U2600.23::5mm

C2607

1

2

1M

1/16W MF-LF

5%

CRITICAL

402

R2680

1 2

CRITICAL

12K

1%

MF

1/16W

402

R2600

1

2

8

80

8

80

43 80

18 80

43 80

44 80

0.1UF

16V

10%

402

X7R-CERM

C2615

1

2

X5R 402

10% 16V

1UF

C2616

1

2

10K

402

5% 1/16W MF-LF

R2620

1

2

X7R-CERM 402

10% 16V

0.1UF

C2617

1

2

402

X5R

10%

1UF

16V

C2618

1

2

X7R-CERM

16V

10%

402

0.1UF

BYPASS=U2600.29::2mm

C2608

1

2

4.7UF

6.3V X5R

20%

603

BYPASS=U2600.5::5mm

C2602

1

2

402

10% 16V

X7R-CERM

0.1UF

BYPASS=U2600.5::2mm

C2609

1

2

BYPASS=U2600.10::2mm

402

0.1UF

X7R-CERM

16V

10%

C2610

1

2

X7R-CERM

402

0.1UF

16V

10%

BYPASS=U2600.34::2mm

C2603

1

2

18 23

100K

5%

1/16W

402

MF-LF

R2642

1

2

8

43

402

100

1/16W

5%

MF-LF

R2605

1 2

BAT54XV2T1

SOD-523

D2600

12

402

10K

5% 1/16W MF-LF

R2606

1

2

10K

5%

402

1/16W MF-LF

R2607

1

2

MF-LF

1/16W

10K

402

5%

HUB1_NONREM0_0

R2604

1

2

402

HUB1_NONREM0_1

10K

5%

MF-LF

1/16W

R2603

1

2

5%

10K

402

MF-LF

1/16W

HUB1_NONREM1_1

R2601

1

2

1/16W

HUB1_NONREM1_0

402

5%

MF-LF

10K

R2602

1

2

X5R

16V

10%

1UF

402

C2668

1

2

402

10% 16V X7R-CERM

0.1UF

C2667

1

2

1UF

16V

10%

402

X5R

C2666

1

2

402

0.1UF

16V

10%

X7R-CERM

C2665

1

2

X7R-CERM

16V

402

10%

0.1UF

BYPASS=U2650.5::2mm

C2660

1

2

5%

402

MF-LF

10K

1/16W

R2670

1

2

1/16W

CRITICAL

MF

1%

402

12K

R2650

1

2

18 80

16V

X7R-CERM

402

10%

0.1UF

BYPASS=U2650.34::2mm

C2661

1

2

4.7UF

20%

6.3V X5R 603

BYPASS=U2650.5::5mm

C2652

1

2

0.1UF

X7R-CERM

402

10% 16V

BYPASS=U2650.29::2mm

C2659

1

2

0.1UF

16V

X7R-CERM

402

10%

BYPASS=U2650.10::2mm

C2658

1

2

4.7UF

20%

603

X5R

6.3V

BYPASS=U2650.23::5mm

C2657

1

2

5%

1/16W

402

MF-LF

100

R2655

1 2

5% 50V CERM

18PF

402

CRITICAL

C2670

1

2

CRITICAL

402

18PF

CERM

50V

5%

C2669

1

2

5%

402

1/16W MF-LF

10K

R2657

1

2

5% 1/16W MF-LF

10K

402

R2656

1

2

1/16W

402

5%

HUB2_NONREM0_1

MF-LF

10K

R2653

1

2

HUB2_NONREM1_1

5%

402

MF-LF

1/16W

10K

R2651

1

2

HUB2_NONREM0_0

MF-LF

1/16W

10K

402

5%

R2654

1

2

HUB2_NONREM1_0

5%

402

10K

1/16W MF-LF

R2652

1

2

5X3.2X1.4-SM

24.000M-60PPM-16PF

CRITICAL

Y2650

1 2

53 80

6

32 80

6

32 80

8

43 80

8

43

QFN

USB2513B

OMIT

U2600

14

25

8 9

20

21

13 17 19

34

12 16 18

35

26

24

22

28

11

37

1

3

6

30

2

4

7

31

27

510152329

36

33 32

QFN

USB2513B

OMIT

U2650

14

25

8 9

20

21

13 17 19

34

12 16 18

35

26

24

22

28

11

37

1

3

6

30

2

4

7

31

27

510152329

36

33 32

0.1UF

X7R-CERM

402

16V

10%

BYPASS=U2600.23::2mm

C2611

1

2

402

X7R-CERM

16V

10%

0.1UF

BYPASS=U2600.15::2mm

C2612

1

2

0.1UF

10% 16V

X7R-CERM

402

BYPASS=U2650.15::2mm

C2662

1

2

0.1UF

402

X7R-CERM

16V

10%

BYPASS=U2650.23::2mm

C2653

1

2

8

80

8

80

USB HUBS

SYNC_DATE=06/08/2010

SYNC_MASTER=K91_MLB

U2600,U2650

CRITICAL

2

SMSC USX2513B

338S0923

USBHUB_2513B

HUB1_1NONREM

HUB1_NONREM1_0,HUB1_NONREM0_1

HUB2_3NONREM

HUB2_NONREM1_1,HUB2_NONREM0_1

338S0720

2

SMSC USB2514

CRITICAL

USBHUB_2514

U2600,U2650

SMSC USB2514B

338S0824

2

CRITICAL

USBHUB_2514B

U2600,U2650

HUB2_ALLREM

HUB2_NONREM1_0,HUB2_NONREM0_0

HUB1_3NONREM

HUB1_NONREM1_1,HUB1_NONREM0_1

HUB1_2NONREM

HUB1_NONREM1_1,HUB1_NONREM0_0

HUB1_ALLREM

HUB1_NONREM1_0,HUB1_NONREM0_0

HUB2_NONREM1_1,HUB2_NONREM0_0

HUB2_2NONREM

HUB2_1NONREM

HUB2_NONREM1_0,HUB2_NONREM0_1

USB_EXTC_P

USB_T29A_N USB_T29A_P

NC_USB_HUB1_PRTPWR2

NC_USB_HUB1_PRTPWR4

USB_HUB2_XTAL1

TP_USB_HUB1_OCS1

USB_EXTC_N

USB_EXTB_OC_L

PPUSB_HUB1_PLLFILT

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

USB_EXTB_P

USB_HUB2_TEST

USB_HUB2_CFG_SEL0

USB_HUB1_NONREM1

USB_HUB1_XTAL1

NC_USB_HUB2_PRTPWR2 NC_USB_HUB2_PRTPWR3 NC_USB_HUB2_PRTPWR4

TP_USB_HUB2_OCS1

TP_USB_HUB2_PRTPWR1

USB_BT_N USB_BT_P

USB_TPAD_N USB_TPAD_P

USB_EXTA_N USB_EXTA_P

PU_USB_HUB2_PRT4_P

PU_USB_HUB2_PRT4_N

NC_USB_HUB2_OCS4

USB_HUB2_VBUS_DET

USB_HUB2_RBIAS

USB_HUB2_UP_N

NC_USB_HUB2_OCS2

USB_EXTA_OC_L

USB_HUB2_UP_P

USB_HUB_RESET_L

USB_HUB2_XTAL2

USB_HUB2_CFG_SEL1

USB_HUB2_NONREM0

TP_USB_HUB1_PRTPWR1

NC_USB_HUB1_PRTPWR3

USB_IR_N USB_IR_P

USB_EXTB_N

NC_USB_HUB1_OCS4

USB_HUB1_VBUS_DET

USB_HUB1_RBIAS

USB_HUB1_UP_N

NC_USB_HUB1_OCS2

USB_HUB1_UP_P

USB_HUB_RESET_L

USB_HUB1_TEST

USB_HUB1_XTAL2

USB_HUB1_CFG_SEL1

USB_HUB1_CFG_SEL0

USB_HUB1_NONREM0

PP3V3_S3

USB_HUB_SOFT_RESET_L

PP3V3_S5

USB_HUB_RESET

USB_HUB_RESET_L

P3V3S3_EN_RC

PPUSB_HUB2_CRFILT

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

PP3V3_S3

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB1_CRFILT

PP3V3_S3

PPUSB_HUB2_PLLFILT

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

VOLTAGE=1.8V

USB_HUB2_NONREM1

PP3V3_S3

26 OF 109

24 OF 86

24

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

6 7 8

17 19 20 22 23 26 30 46

56 66 72 73 74 76 85

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

6 7 8

18 24 26 30 31

32 33 48 50 54 55 72 73

6 7 8

18 24 26 30 31 32

33 48 50 54 55 72 73

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

UNUSED clock terminations for FCIM MODE

10K

5%

MF-LF

1/16W

402

R2757

1

2

10K

5%

MF-LF

1/16W

402

R2751

1

2

10K

5%

MF-LF

1/16W

402

R2752

1

2

10K

5%

MF-LF

1/16W

402

R2753

1

2

10K

5%

MF-LF

1/16W

402

R2754

1

2

10K

5%

MF-LF

1/16W

402

R2755

1

2

10K

5%

MF-LF

1/16W

402

R2756

1

2

SYNC_DATE=06/21/2010

SYNC_MASTER=K91_MLB

Clock (CK505)

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_N

PCH_CLK100M_SATA_P

PCH_CLK100M_SATA_N

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

PCH_CLK14P3M_REFCLK

27 OF 109

25 OF 86

16 80

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

D

GS

OUT

IN

OUT

OUT OUT OUT

NC NC

NC

OUT

VBAT

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRM

GND

32KHZ_A

PAD

OUT

D

SG

IN

D

SG

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH S0 PWRGD

Coin-Cell & No G3Hot: 3.3V S5

SB XTAL Power

VBAT and +V3.3A are

GreenClk 25MHz Power

Ethernet XTAL Power

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

Coin-Cell: VBAT (300-ohm & 10uF RC)

internally ORed to

available ~3.3V power

For SB RTC Power

Platform Reset Connections

Series R is R3803

Series R is R4283

VTT voltage divider on CPU page

Buffered

Unbuffered

PCH Reset Button

T29 XTAL Power

to reduce VBAT draw.

No bypass necessary

No Coin-Cell: 3.3V S5

+V3.3A should be first

create VDD_RTC_OUT.

NOTE: 30 PPM crystal required

Ethernet WAKE# Isolation

ENET_MEDIA_SENSE ISOLATION CIRCUIT

System RTC Power Source & 32kHz / 25MHz Clock Generator

10 23 78

XDP

MF-LF

5%

0

402

1/16W

R2896

1 2

5%

1/16W

402

MF-LF

33

R2883

1 2

5%

402

MF-LF

33

1/16W

R2881

1 2

6

26 47 81

45

32

18 26 30 33 36 40

PLACE_NEAR=U1800.H43:5.1mm

22

5% 1/16W MF-LF

402

R2826

1 2

5%

1/16W

402

22

MF-LF

PLACE_NEAR=U1800.H49:5.1mm

R2827

1 2

18 81

31

1/16W

5%

0

MF-LF

402

R2871

1 2

10V

0.1UF

CERM

20%

402

C2850

1

2

23 45 73

68

6

47 81

45 81

MC74VHC1G08

SC70-HF

U2850

3

2

1

4

5

18

23

MF-LF

1/16W

402

5%

1K

XDP

R2889

1 2

402

MF-LF

1/16W

5%

0

R2888

1 2

0.1UF

402

10V

20%

CERM

C2880

1

2

1/16W MF-LF

5%

100K

402

R2880

1

2

1K

402

MF-LF

1/16W

5%

R2850

1

2

18 26 30 33 36 40

16 80

5%

402

22

1/16W MF-LF

PLACE_NEAR=U1800.H40:2.54MM:5.1mm

R2829

1 2

18

SILK_PART=SYS RESET

MF-LF

1/16W

402

5%

0

OMIT

R2897

1

2

6

26 47 81

77

402

1/16W MF-LF

5%

0

R2893

1 2

10K

MF-LF

1/16W

402

5%

R2895

1

2

17 45

18 26 30 33 36 40

SOD-VESM-HF

SSM3K15FV

Q2830

3

1

2

6

17 32 26 37

MF-LF

1/16W

402

5%

10K

R2830

1

2

10 23 26

18 26 30 33 36 40

17 23

402

5%

MF-LF

1/16W

0

NO STUFF

R2863

1 2

402

CERM

10V

0.1UF

20%

C2860

1

2

3.0K

402

MF-LF

1/16W

5%

R2862

1 2

17 26

0

5% 1/16W MF-LF

PLACE_NEAR=U1800.L22:5.54mm

402

NO STUFF

R2861

1

2

5%

MF-LF

1/16W

402

0

R2860

1 2

SC70-HF

MC74VHC1G08

U2860

3

2

1

4

5

16 81

37 81

34 81

6.3V CERM

1UF

10%

402

C2810

1

2

10%

X5R

1UF

10V

402-1

C2802

1

2

1M

5%

NO STUFF

MF

1/20W

201

R2806

1

2

0.1UF

10%

0201

X5R-CERM

16V

C2824

1

2

0

5%

MF

1/20W

201

R2805

1 2

SM-3.2X2.5MM

25.000MHZ-12PF-30PPM

CRITICAL

Y2805

2 4

1 3

12PF

402

CERM

50V

5%

C2805

12

402

50V

5%

12PF

CERM

C2806

1 2

SC70

74LVC1G07

U2880

2

31

5

4

17 26

CRITICAL

TQFN

SLG3NB148V

U2800

9 8 15

12

71016217

13

5

1

11

6

14

4

3

0.1UF

10%

0201

X5R-CERM

16V

C2822

1

2

16V

X5R-CERM

0201

10%

0.1UF

C2820

1

2

16

PLACE_NEAR=U1800.N32:5mm

201

10K

5%

MF

1/20W

R2819

1

2

SOT563

SSM6N37FEAPE

CRITICAL

Q2810

3

5

4

402

12K

MF-LF 1/16W

5%

R2810

1 2

37

201

1/20W

MF

5%

100K

R2811

1

2

SOT563

SSM6N37FEAPE

Q2810

6

2

1

402

0

1/16W

MF-LF

5%

R2812

1

2

Chipset Support

SYNC_MASTER=LINDA_K90I

SYNC_DATE=07/08/2010

PP1V8_S0

ENET_MEDIA_SENSE

ENET_MEDIA_SENSE_EN

PP1V5_S0

PP3V3_S3

ENET_MEDIA_SENSE_EN_L

ENET_MEDIA_SENSE_RDIV

ENET_WAKE_L

PP3V3_ENET

SMC_DELAYED_PWRGD

SYSCLK_CLK25M_X1

PPVRTC_G3H

SYSCLK_CLK32K_RTC

PP3V42_G3H

PP3V3_S5

PP3V3_T29

SYSCLK_CLK25M_T29

SYSCLK_CLK25M_ENET

SYSCLK_CLK25M_SB

SYSCLK_CLK25M_X2_R

PM_PCH_SYS_PWROK

LPC_CLK33M_SMC

PCH_CLK33M_PCIIN

LPCPLUS_RESET_L

MAKE_BASE=TRUE

ENET_WAKE_L

PLT_RESET_L

SMC_LRESET_L

XDPPCH_PLTRST_L

BKLT_PLT_RST_L

PLT_RESET_L

PLT_RST_BUF_L

LPCPLUS_RESET_L

AP_RESET_L

LPC_CLK33M_LPCPLUS

PLT_RESET_L

PP3V3_ENET

PP3V3_S0

PM_SYSRST_L

XDP_DBRESET_L

PP3V3_S0

PCH_CLK33M_PCIOUT

PCA9557D_RESET_L

SYSCLK_CLK25M_X2

PLT_RST_BUF_L

MAKE_BASE=TRUE

LPC_CLK33M_LPCPLUS_R

PP3V3_S0

PLT_RESET_L

MAKE_BASE=TRUE

LPC_CLK33M_SMC_R

PCIE_WAKE_L

PP3V3_S5

PM_PCH_PWROK

PM_S0_PGOOD

SYS_PWROK_R

MAKE_BASE=TRUE

PM_PCH_PWROK

ALL_SYS_PWRGD

CPUIMVP_PGOOD

28 OF 109

26 OF 86

6 7

14 17 20 22

71

7

16 20 22 42 57 71

6 7 8

18 24 30 31 32 33 48 50

54

55 72 73

6 7 26 37 71 73

36 45

7

16 17 20

6 7

43 45 46 47 48 53 63 64

73

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

7

16 19 34 35

36

26 37

6 7

26 37 71 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

10 23

26

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26

30 46 56 66 72 73 74 76 85

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4* DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI BI

IN

BI

IN

BI BI

BI

IN

BI BI

BI

OUT

BI IN

IN

IN IN

BI BI

BI

IN

BI

BI BI

IN

BI BI

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Page Notes

Power aliases required by this page:

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

BOM options provided by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

SPD ADDR=0xA0(WR)/0xA1(RD)

(NONE)

"Factory" (top) slot

516-0229

F-RT-THB

DDR3-SODIMM-DUAL-K6

J2900

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101

103

102

104

73 74

136

153

170

187

129

131

141 143

130

132

140

142

147 149

157

159

146

148

158

160

163 165

175 177

164 166

174

176

181 183

191 193

180

182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

28

10V

20%

402

CERM

0.1UF

C2931

1

2

2.2UF

20%

402-LF

CERM

6.3V

C2930

1

2

28

11 79

11 28 79

28

29 30

28

F-RT-THB

DDR3-SODIMM-DUAL-K6

CRITICAL

J2900

11

28

46

63

5

7

33

35

22

24

34

36

39

41

51 53

15

40

42

50

52

57 59

67

69

56

58

17

68

70

4 6

16

18

21

23

12

10

29

27

47

45

64

62

30

1 2

3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

28

11 79

28

11 79

11 28 79

28

0.1UF

CERM 402

20% 10V

C2936

1

2

CERM

2.2UF

6.3V

20%

402-LF

C2935

1

2

28

29 45

16 23 29 31 42 48 62 77 81

11 79

28

MF-LF

1/16W

402

5%

10K

R2941

1

2

402

5% 1/16W MF-LF

10K

R2940

1

2

6.3V

402-LF

CERM

20%

2.2UF

C2940

1

2

603

6.3V X5R

20%

10UF

C2900

1

2

20%

603

X5R

10UF

6.3V

C2901

1

2

0.1UF

20% 10V

402

CERM

C2910

1

2

10V

20%

CERM 402

0.1UF

C2911

1

2

402

10V

20%

0.1UF

CERM

C2912

1

2

0.1UF

20% 10V CERM 402

C2913

1

2

0.1UF

20%

CERM 402

10V

C2914

1

2

10V CERM 402

20%

0.1UF

C2915

1

2

CERM 402

20%

0.1UF

10V

C2916

1

2

CERM 402

20%

0.1UF

10V

C2917

1

2

CERM 402

20%

0.1UF

10V

C2918

1

2

CERM 402

20%

0.1UF

10V

C2919

1

2

0.1UF

CERM 402

20% 10V

C2920

1

2

CERM 402

20%

0.1UF

10V

C2921

1

2

CERM 402

20%

0.1UF

10V

C2922

1

2

CERM 402

20%

0.1UF

10V

C2923

1

2

402

X5R

1UF

10V

10%

C2953

1

2

402

X5R

1UF

10V

10%

C2952

1

2

402

X5R

1UF

10V

10%

C2951

1

2

402

X5R

1UF

10V

10%

C2950

1

2

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

DDR3 SO-DIMM Connector A

MEM_A_A<4>

=MEM_A_DQ<27>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<5>

=MEM_A_DQ<33>

MEM_A_A<10>

MEM_A_SA<1>

=MEM_A_DQS_N<4>

=MEM_A_DQS_P<4>

=MEM_A_DQ<35>

MEM_A_CLK_N<0>

MEM_A_SA<0>

=MEM_A_DQ<58>

=MEM_A_DQ<59>

GND

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<50>

=MEM_A_DQ<51>

=MEM_A_DQS_N<6>

=MEM_A_DQS_P<6>

=MEM_A_DQ<48>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

SMBUS_PCH_CLK

=MEM_A_DQ<62>

=MEM_A_DQ<63>

=MEM_A_DQ<60>

=MEM_A_DQ<61>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

GND

=MEM_A_DQ<53>

=MEM_A_DQ<52>

=MEM_A_DQ<47>

=MEM_A_DQS_P<5>

=MEM_A_DQ<46>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DQ<34>

=MEM_A_DQ<32>

MEM_A_CS_L<1>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_BA<0>

MEM_A_CLK_P<0>

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BA<2>

MEM_A_CKE<0>

=MEM_A_DQS_N<5>

=MEM_A_DQ<44>

=MEM_A_DQ<45>

=MEM_A_DQ<39>

=MEM_A_DQ<38>

GND

MEM_A_DQ<37>

=MEM_A_DQ<36>

MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_BA<1>

MEM_A_RAS_L

MEM_A_CLK_N<1>

MEM_A_A<0>

MEM_A_CLK_P<1>

MEM_A_A<2>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_CKE<1>

PP3V3_S0

=MEM_A_DQ<16>

GND

=MEM_A_DQ<26>

=MEM_A_DQ<4>

=MEM_A_DQ<31>

=MEM_A_DQ<30>

=MEM_A_DQS_P<3>

=MEM_A_DQS_N<3>

=MEM_A_DQ<29>

=MEM_A_DQ<28>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

GND

=MEM_A_DQ<21>

=MEM_A_DQ<20>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

MEM_RESET_L

GND

=MEM_A_DQ<13>

=MEM_A_DQ<12>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

=MEM_A_DQ<5>

=MEM_A_DQ<24>

=MEM_A_DQ<25>

=MEM_A_DQ<19>

=MEM_A_DQ<18>

=MEM_A_DQS_P<2>

=MEM_A_DQS_N<2>

=MEM_A_DQ<17>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQS_P<1>

=MEM_A_DQS_N<1>

=MEM_A_DQ<8> =MEM_A_DQ<9>

GND

=MEM_A_DQ<0>

=MEM_A_DQ<1>

PP0V75_S3_MEM_VREFDQ_A

=MEM_A_DQ<3>

=MEM_A_DQ<2>

PP0V75_S3_MEM_VREFCA_A

PP1V5_S3

=MEM_A_DQ<49>

GND

PP0V75_S0_DDRVTT

SMBUS_PCH_DATA

MEM_EVENT_L

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<7>

29 OF 109

27 OF 86

6 7 8

12 16 17

18 19 20 22 23 26 29 33

36 37 40 41 42

46 48 49 50 51 52 54 57

61 62 71 72 73

74 75 77 85

9

31

6 7

29 30 67 72

7

29 30 67

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU CHANNEL B DQS 7 -> DIMM B DQS 7

CPU CHANNEL B DQS 3 -> DIMM B DQS 3

CPU CHANNEL B DQS 0 -> DIMM B DQS 0

CPU CHANNEL B DQS 1 -> DIMM B DQS 1

CPU CHANNEL A DQS 6 -> DIMM A DQS 6

CPU CHANNEL A DQS 3 -> DIMM A DQS 3

CPU CHANNEL B DQS 2 -> DIMM B DQS 2

CPU CHANNEL B DQS 4 -> DIMM B DQS 4

CPU CHANNEL B DQS 6 -> DIMM B DQS 6

CPU CHANNEL A DQS 5 -> DIMM A DQS 5

CPU CHANNEL A DQS 4 -> DIMM A DQS 4

CPU CHANNEL B DQS 5 -> DIMM B DQS 5

CPU CHANNEL A DQS 7 -> DIMM A DQS 7

NOTE: Sandybridge does not use DM signals per doc 438297 Huron River SFF DG rev1.0 Section 2.6.13

CPU CHANNEL A DQS 1 -> DIMM A DQS 1

CPU CHANNEL A DQS 2 -> DIMM A DQS 2

CPU CHANNEL A DQS 0 -> DIMM A DQS 0

SYNC_DATE=06/22/2010

SYNC_MASTER=ANNE_K90I

DDR3 Byte/Bit Swaps

MEM_A_DQ<52>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DQ<51> MEM_A_DQ<50>

MAKE_BASE=TRUE

=MEM_A_DQ<55> =MEM_A_DQ<48> =MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQ<48>

MEM_B_DQS_P<3>

MAKE_BASE=TRUE

MEM_B_DQ<31>

MAKE_BASE=TRUE

MEM_B_DQ<30>

MAKE_BASE=TRUE

MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MAKE_BASE=TRUE

MEM_B_DQ<27>

MEM_B_DQS_N<3>

MAKE_BASE=TRUE

MEM_B_DQ<16>

MAKE_BASE=TRUE

MEM_B_DQ<19>

MAKE_BASE=TRUE

MEM_B_DQ<20>

MAKE_BASE=TRUE

MEM_B_DQ<17>

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

MEM_B_DQ<6>

MAKE_BASE=TRUE

MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MAKE_BASE=TRUE

MEM_B_DQ<0>

MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_B_DQS_N<0>

MEM_A_DQ<31>

MAKE_BASE=TRUE

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_A_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<10>

MAKE_BASE=TRUE

MEM_B_DQ<8>

MAKE_BASE=TRUE

MEM_B_DQ<23>

MAKE_BASE=TRUE

MEM_B_DQ<22>

MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<30>

MAKE_BASE=TRUE

MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQS_P<2>

MEM_B_DQ<9>

MAKE_BASE=TRUE

MEM_B_DQ<42>

MAKE_BASE=TRUE

MEM_B_DQ<47>MEM_A_DQ<47>

MAKE_BASE=TRUE

MEM_A_DQ<35>

MAKE_BASE=TRUE

MEM_A_DQ<24>

MAKE_BASE=TRUE

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<45>

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_A_DQ<18>

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MAKE_BASE=TRUE

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DQ<40>

MEM_A_DQ<55>

MAKE_BASE=TRUE

MEM_A_DQ<54>

MEM_A_DQ<27>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MEM_A_DQ<37>

MAKE_BASE=TRUE

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<36>

MAKE_BASE=TRUE

MEM_A_DQ<32>

MAKE_BASE=TRUE

MEM_A_DQ<33>

MAKE_BASE=TRUE

MEM_A_DQS_N<5> MEM_A_DQS_P<5>

MAKE_BASE=TRUE

MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQ<17>

MAKE_BASE=TRUE

MEM_B_DQ<11>

MAKE_BASE=TRUE

MEM_B_DQ<18>

MAKE_BASE=TRUE

MEM_B_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

MAKE_BASE=TRUE

MEM_B_DQ<39>

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQ<38>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<32>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<43>

MAKE_BASE=TRUE

MEM_B_DQ<40>

MEM_B_DQ<41>

MAKE_BASE=TRUE

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

MEM_B_DQ<55>

MAKE_BASE=TRUE

MEM_B_DQ<54>

MAKE_BASE=TRUE

MEM_B_DQ<53>

MAKE_BASE=TRUE

MEM_B_DQ<52>

MAKE_BASE=TRUE

MEM_B_DQ<51>

MAKE_BASE=TRUE

MEM_B_DQ<50>

MAKE_BASE=TRUE

MEM_B_DQ<49>

MAKE_BASE=TRUE

MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MEM_B_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_B_DQ<63>

MAKE_BASE=TRUE

MEM_B_DQ<60>

MAKE_BASE=TRUE

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<59>

MAKE_BASE=TRUE

MEM_B_DQ<57>

MAKE_BASE=TRUE

MEM_B_DQ<58>

MAKE_BASE=TRUE

MEM_B_DQ<56>

MAKE_BASE=TRUE

MEM_B_DQ<14>

MAKE_BASE=TRUE

MEM_B_DQ<21>

MAKE_BASE=TRUE

MEM_B_DQ<15>

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

MEM_B_DQ<12>

MAKE_BASE=TRUE

MEM_B_DQ<24>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MEM_A_DQ<34>

MAKE_BASE=TRUE

MEM_A_DQ<25>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MEM_A_DQ<62>

MAKE_BASE=TRUE

MEM_A_DQ<48>

MAKE_BASE=TRUE

MEM_A_DQ<49>

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<5> MEM_A_DQ<4>

MAKE_BASE=TRUE

MEM_A_DQ<3> MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_A_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQ<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQS_N<2>

MAKE_BASE=TRUE

MEM_A_DQ<14> MEM_A_DQ<13>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MAKE_BASE=TRUE

MEM_A_DQ<11>

MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MEM_A_DQ<23>

MAKE_BASE=TRUE

MEM_A_DQS_P<2>

MAKE_BASE=TRUE

MEM_A_DQ<8>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<15>

=MEM_A_DQ<18>

=MEM_A_DQ<16>

=MEM_A_DQ<19>

=MEM_A_DQ<20>

=MEM_A_DQ<21>

=MEM_A_DQS_P<6>

=MEM_A_DQ<51>

=MEM_A_DQ<3>

=MEM_A_DQS_N<2>

=MEM_A_DQ<23> =MEM_A_DQ<22>

=MEM_A_DQ<11> =MEM_A_DQ<10> =MEM_A_DQ<12>

=MEM_A_DQ<15> =MEM_A_DQ<14> =MEM_A_DQ<13>

=MEM_B_DQ<25>

=MEM_B_DQ<32>

=MEM_B_DQ<35>

=MEM_B_DQ<34>

=MEM_B_DQ<26>

=MEM_B_DQS_P<3>

=MEM_B_DQ<20>

MEM_B_DQS_N<0>

=MEM_B_DQ<27>

=MEM_B_DQ<62>

=MEM_B_DQ<57>

=MEM_B_DQ<63>

=MEM_B_DQ<61> =MEM_B_DQ<60>

=MEM_B_DQ<56> =MEM_B_DQ<59>

=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>

=MEM_B_DQ<48>

=MEM_B_DQ<50>

=MEM_B_DQ<51>

=MEM_B_DQ<49>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

=MEM_B_DQS_P<6>

=MEM_B_DQS_N<6>

=MEM_B_DQ<41>

=MEM_B_DQ<43>

=MEM_B_DQS_P<5>

=MEM_B_DQS_N<5>

=MEM_B_DQ<36>

=MEM_B_DQ<37>

MEM_B_DQ<37>

=MEM_B_DQ<39>

=MEM_B_DQS_P<4>

=MEM_B_DQ<38>

=MEM_B_DQS_N<4>

=MEM_B_DQ<24>

=MEM_B_DQ<30>

=MEM_B_DQS_N<3>

=MEM_B_DQ<21>

=MEM_B_DQS_P<1>

=MEM_A_DQ<4>

=MEM_A_DQS_P<1>

=MEM_A_DQ<0>

=MEM_A_DQ<2>

=MEM_A_DQ<5>

=MEM_A_DQ<8>

=MEM_A_DQ<9>

=MEM_A_DQS_N<1>

=MEM_A_DQ<7>

=MEM_A_DQ<1>

=MEM_A_DQS_N<6>

=MEM_A_DQ<44>

=MEM_A_DQ<40>

=MEM_A_DQ<42>

=MEM_A_DQ<45>

=MEM_A_DQ<46>

=MEM_A_DQ<36>

=MEM_A_DQ<35>

=MEM_A_DQS_P<2>

=MEM_A_DQ<56>

=MEM_A_DQ<63> =MEM_A_DQ<62> =MEM_A_DQ<61>

=MEM_A_DQ<57>

=MEM_A_DQ<60>

=MEM_A_DQ<58> =MEM_A_DQ<59>

=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>

=MEM_A_DQ<50>

=MEM_A_DQ<49> =MEM_A_DQ<53>

=MEM_A_DQ<47>

=MEM_A_DQ<41>

=MEM_A_DQ<43>

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<5>

=MEM_A_DQ<34>

=MEM_A_DQ<33>

=MEM_A_DQ<39> MEM_A_DQ<37>

=MEM_A_DQS_P<4>

=MEM_A_DQ<38>

=MEM_A_DQS_N<4>

=MEM_A_DQ<29>

=MEM_A_DQ<30>

=MEM_A_DQ<25> =MEM_A_DQ<31> =MEM_A_DQ<27>

=MEM_A_DQ<24> =MEM_A_DQ<28>

=MEM_A_DQS_P<3>

=MEM_A_DQS_N<3>

MEM_A_DQS_N<0>

=MEM_A_DQ<17>

=MEM_A_DQ<26>

=MEM_B_DQ<31>

=MEM_B_DQ<52>

=MEM_B_DQ<53>

=MEM_B_DQ<58>

=MEM_B_DQ<42>

=MEM_B_DQ<47>

=MEM_B_DQ<45>

=MEM_B_DQ<40>

=MEM_B_DQ<44>

=MEM_B_DQ<46>

=MEM_A_DQ<32>

MEM_B_DQS_P<0>

=MEM_B_DQ<3>

MEM_A_DQS_P<0>

=MEM_B_DQ<16>

=MEM_B_DQ<19>

=MEM_B_DQ<22>

=MEM_B_DQ<17>

=MEM_B_DQ<18>

=MEM_B_DQ<23>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

=MEM_B_DQ<9>

=MEM_B_DQ<12>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<8>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

=MEM_B_DQ<15>

=MEM_B_DQ<1>

=MEM_B_DQ<2>

=MEM_B_DQ<5>

=MEM_B_DQS_N<1>

=MEM_A_DQ<54>

=MEM_B_DQ<6>

=MEM_B_DQ<7>

=MEM_B_DQ<4>

=MEM_B_DQ<0>

=MEM_B_DQ<28> =MEM_B_DQ<29>

=MEM_A_DQ<6>

GND

30 OF 109

28 OF 86

11 79

11 79 27

27

11 27 28 79

11 79

11 28 29 79

11 79

11 28 29 79

11 79

11 79 11 79

11 79

11 27 28 79

11 79

11 28 29 79

11 79

27

29

11 28 29 79

29

11 28 29 79

29

27

11 27 28 79

27

11 27 28 79

27

29

27

11 28 29 79

29

11 27 28 79

29

27

29

27

IN

BI

BI BI

OUT

BI IN

IN

IN IN

IN

IN IN

BI BI

BI

IN

BI BI

IN

BI BI

NC

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

BI

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

IN

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI BI

IN

BI BI

IN

BI BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Page Notes

- =PP1V5_S0_MEM_B

SPD ADDR=0xA4(WR)/0xA5(RD)

516S0806

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =PP1V5_S3_MEM_B

"Expansion" (bottom) slot

Signal aliases required by this page:

- =I2C_SODIMMB_SDA

BOM options provided by this page:

(NONE)

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

- =I2C_SODIMMB_SCL

Power aliases required by this page:

11 79

28

27 45

16 23 27 31 42 48 62 77 81

0.1UF

CERM 402

20% 10V

C3131

1

2

11 79

28

11 28 79

28

2.2UF

20%

6.3V

402-LF

CERM

C3130

1

2

1/16W

10K

402

MF-LF

5%

R3141

1

2

10K

5%

402

1/16W MF-LF

R3140

1

2

20%

CERM 402-LF

6.3V

2.2UF

C3140

1

2

10UF

20%

X5R

6.3V

603

C3100

1

2

6.3V

10UF

X5R 603

20%

C3101

1

2

CERM 402

10V

20%

0.1UF

C3110

1

2

0.1UF

402

CERM

10V

20%

C3111

1

2

CERM

0.1UF

20% 10V

402

C3112

1

2

CERM 402

0.1UF

10V

20%

C3113

1

2

28

0.1UF

10V

402

CERM

20%

C3114

1

2

10V CERM

0.1UF

20%

402

C3115

1

2

10V

0.1UF

20%

402

CERM

C3116

1

2

10V

0.1UF

20%

402

CERM

C3117

1

2

10V

0.1UF

20%

402

CERM

C3118

1

2

10V

0.1UF

20%

402

CERM

C3119

1

2

10V

20%

402

CERM

0.1UF

C3120

1

2

10V

0.1UF

20%

402

CERM

C3121

1

2

10V

0.1UF

20%

402

CERM

C3122

1

2

10V

0.1UF

20%

402

CERM

C3123

1

2

28

1UF

402

X5R

10V

10%

C3153

1

2

1UF

402

X5R

10V

10%

C3152

1

2

402

X5R

1UF

10V

10%

C3151

1

2

402

X5R

1UF

10V

10%

C3150

1

2

11 79

DDR3-SODIMM

F-RT-BGA6

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101

103

102

104

73 74

136

153

170

187

129

131

141 143

130

132

140

142

147 149

157

159

146

148

158

160

163 165

175 177

164 166

174

176

181 183

191 193

180

182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

205 206 207 208

209 210 211 212

203 204

113

11 28 79

28

27 30

28

CRITICAL

DDR3-SODIMM

F-RT-BGA6

J3100

11

28

46

63

5

7

33

35

22

24

34

36

39

41

51 53

15

40

42

50

52

57 59

67

69

56

58

17

68

70

4 6

16

18

21

23

12

10

29

27

47

45

64

62

30

1 2

3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

28

11 79

28

11 79

28

11 79

28

20%

0.1UF

10V

402

CERM

C3136

1

2

402-LF

20%

CERM

6.3V

2.2UF

C3135

1

2

28

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

DDR3 SO-DIMM Connector B

PP0V75_S0_DDRVTT

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>

PP3V3_S0

MEM_B_SA<0>

GND

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<62>

=MEM_B_DQ<50>

=MEM_B_DQ<16>

GND

=MEM_B_DQ<26>

=MEM_B_DQ<27>

=MEM_B_DQ<4>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQS_N<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

GND

=MEM_B_DQ<21>

=MEM_B_DQ<20>

=MEM_B_DQ<15>

=MEM_B_DQ<14>

MEM_RESET_L

GND

=MEM_B_DQ<12>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

=MEM_B_DQ<5>

=MEM_B_DQ<24>

=MEM_B_DQ<25>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

=MEM_B_DQ<17>

=MEM_B_DQ<11>

=MEM_B_DQ<10>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_B_DQ<8> =MEM_B_DQ<9>

GND

=MEM_B_DQ<0>

=MEM_B_DQ<1>

PP0V75_S3_MEM_VREFDQ_B

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=MEM_B_DQ<58>

MEM_B_SA<1>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

GND

MEM_B_CAS_L

=MEM_B_DQ<35>

MEM_B_CLK_N<0>

MEM_B_A<10>

=MEM_B_DQ<51>

=MEM_B_DQS_N<6>

=MEM_B_DQS_P<6>

SMBUS_PCH_DATA SMBUS_PCH_CLK

MEM_EVENT_L

=MEM_B_DQ<63>

=MEM_B_DQ<60>

=MEM_B_DQ<61>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

GND

=MEM_B_DQ<53>

=MEM_B_DQ<52>

=MEM_B_DQ<47>

=MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<40>

=MEM_B_DQ<32>

MEM_B_DQ<37>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_WE_L

MEM_B_BA<0>

MEM_B_CLK_P<0>

MEM_B_BA<2>

MEM_B_CKE<0>

=MEM_B_DQS_N<5>

=MEM_B_DQ<44>

=MEM_B_DQ<45>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

GND

=MEM_B_DQ<37>

=MEM_B_DQ<36>

PP0V75_S3_MEM_VREFCA_B

MEM_B_CS_L<0>

MEM_B_BA<1>

MEM_B_CLK_N<1>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

=MEM_B_DQS_N<4>

=MEM_B_DQ<41>

=MEM_B_DQ<49>

=MEM_B_DQ<48>

=MEM_B_DQ<43>

=MEM_B_DQ<42>

MEM_B_A<12> MEM_B_A<9>

MEM_B_A<8> MEM_B_A<5>

MEM_B_A<1>

PP1V5_S3

=MEM_B_DQ<13>

=MEM_B_DQ<59>

MEM_B_ODT<0>

MEM_B_RAS_L

MEM_B_CLK_P<1>

MEM_B_ODT<1>

MEM_B_A<3>

31 OF 109

29 OF 86

7

27 30 67

6 7 8

12 16 17 18

19 20 22 23 26 27 33 36 37

40 41 42 46 48 49

50 51 52 54 57 61 62 71 72

73 74 75 77 85

9

31

6 7

27 30 67 72

IN IN

IN

OUT

D

SG

D

S G

D

SG

D

S G

D

SG

D

S G

D

S G

D

SG

OUT

IN

D

SG

D

SG

IN

G

D

S

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1 0 1 1 1 1 1 1 1

4 0 0 1 1 X 1 0 1

3 0 0 0 1 X 1 0 0

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

2 0 0 1 1 1 1 0 1

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals. WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

6 0 1 1 1 1 1 1 1

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

1V5 S0 "PGOOD" for CPU

MEMVTT Clamp

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

75mA max load @ 0.75V

5 0 1 1 1 0 (*) 1 1 1

S0

to

S3

to

S0

60mW max power

Ensures CKE signals are held low in S3

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

19 23

6

17 45 73

18 26 33 36 40

1/16W

5%

MF-LF

100K

402

CPUMEM_S0

R3202

1

2

8

30 67

CPUMEM_S0

10K

1/16W

5%

402

MF-LF

R3210

1

2

CPUMEM_S0

100K

MF-LF

402

5%

1/16W

R3215

1

2

27 29

402

CPUMEM_S0

20K

MF-LF

5% 1/16W

R3216

1

2

SSM6N37FEAPE

CPUMEM_S0

SOT563

Q3200

3

5

4

SSM6N37FEAPE

SOT563

CPUMEM_S0

Q3205

3

5

4

CPUMEM_S0

SOT563

SSM6N37FEAPE

Q3210

6

2

1

SSM6N37FEAPE

SOT563

CPUMEM_S0

Q3210

3

5

4

CPUMEM_S0

SSM6N37FEAPE

SOT563

Q3200

6

2

1

SOT563

SSM6N37FEAPE

CPUMEM_S0

Q3215

6

2

1

CPUMEM_S0

SSM6N37FEAPE

SOT563

Q3215

3

5

4

SSM6N37FEAPE

CPUMEM_S0

SOT563

Q3205

6

2

1

72

10K

1/16W

5%

402

MF-LF

CPUMEM_S0

R3205

1

2

6

17 45 73

100K

5%

402

MF-LF

CPUMEM_S0

1/16W

R3201

1

2

8

30 67

SSM6N37FEAPE

CPUMEM_S0

SOT563

Q3250

3

5

4

1/16W MF-LF

5%

100K

402

CPUMEM_S0

R3251

1

2

402

NO STUFF

50V

0.001UF

20%

CERM

C3251

1

2

SSM6N37FEAPE

CPUMEM_S0

SOT563

Q3250

6

2

1

MF-LF

10

5%

603

1/10W

CPUMEM_S0

R3250

1

2

MF-LF

1/16W

5%

402

0

CPUMEM_S3

R3217

1 2

10 30

MF-LF

1%

33.2K

402

1/16W

R3221

1

2

402

27.4K

1% 1/16W MF-LF

R3220

1

2

SOT-563

DMB53D0UV

CRITICAL

Q3220

5

3

4

MF-LF

1/16W

5%

10K

402

R3222

1

2

SOT-563

CRITICAL

DMB53D0UV

Q3220

6

2

1

10 17 78

0.001UF

20% 50V

402

NO STUFF

CERM

C3220

1

2

402

16V X5R

10%

0.1UF

CPUMEM_S0

C3216

1

2

SYNC_MASTER=ANNE_K90I

SYNC_DATE=06/22/2010

CPU Memory S3 Support

MAKE_BASE=TRUE

CPU_MEM_RESET_LCPU_MEM_RESET_L

MEMVTT_EN

P1V5CPU_EN

P1V5CPU_EN_L

PP0V75_S0_DDRVTT

VTTCLAMP_L

VTTCLAMP_EN

PP5V_S3

MEMVTT_EN

MEMVTT_EN_L

MEMRESET_ISOL_LS5V_L

PM_SLP_S4_L

PP1V5_S3RS0

PP3V3_S5

PM_MEM_PWRGD_L

PM_MEM_PWRGD

PM_SLP_S3_L

P1V5_S0_DIV

PLT_RESET_L

PP3V3_S3

MEM_RESET_L

PP1V5_S3

ISOLATE_CPU_MEM_L

PP5V_S3

32 OF 109

30 OF 86

10

30

7

27 29 67

6 7

30 32 42 43 44 46 57 59

60 61 66 67 72

6 7

10 12 15 72 73 85

6 7 8

17 19 20 22 23 24 26 46

56 66 72 73 74 76 85

6 7 8

18 24 26 31 32 33 48 50

54 55 72 73

6 7

27 29 67 72

6 7

30 32 42 43 44 46 57 59

60 61 66 67 72

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

IN

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1.51mV / step @ output

+6.0mA - -5.0mA (- = sourced)

0.000V - 3.300V (0x00 - 0xFF)

GPU Frame Buffer (1.8V, 70% VRef)

D

1.267V (DAC: 0x8B)

1.056V - 1.442V (+/- 180mV)

8.59mV / step @ output

+33uA - -33uA (- = sourced)

0.000V - 1.501V (0x00 - 0x74)

1.998V - 1.002V (+/- 498mV)

1.5V (DAC: 0x3A)

5

BOM options provided by this page:

NOTE: Margining will be disabled across all

Required zero ohm resistors when no VREF margining circuit stuffed

Addr=0x98(WR)/0x99(RD)

MEM B VREF CA

C

both at the same time!

NOTE: MEMVREG and FRAMEBUF share a DAC output, cannot enable

0.000V - 1.501V (0x00 - 0x74) +3.4mA - -3.4mA (- = sourced)

(OD)

watchdog will disable margining.

10mA max load

Signal aliases required by this page:

VREFMRGN_NOT - Bypasses VREF Margining

VREFMRGN - Stuffs VREF Margining

Power aliases required by this page:

Page Notes

- =PPVTT_S3_DDR_BUF

Circuitry.

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SDA

- =I2C_VREFDACS_SCL

- =PP3V3_S3_VREFMRGN

4

MEM A VREF CA

3

C

7.69mV / step @ output

0.300V - 1.200V (+/- 450mV)

MEM B VREF DQ

A 1 2

B

Margined target:

VRef current: DAC step size:

DAC range:

PCA9557D Pin:

DAC Channel:

D

MEM VREG

buffers at once or VRef source may be overloaded.

NOTE: Must not enable more than two SO-DIMM margining

0.75V (DAC: 0x3A)

6

soft-resets and sleep/wake cycles.

RST* on ’platform reset’ so that system

Addr=0x30(WR)/0x31(RD)

Nominal value

MEM A VREF DQ

67

VREFMRGN

0.1UF

CERM

402

20% 10V

C3302

1

2

PLACE_NEAR=R7315.2:1mm

MF-LF

402

1%

1/16W

VREFMRGN

33.2K

R3314

1 2

402

5%

MF-LF

1/16W

100K

VREFMRGN

R3313

1

2

VREFMRGN

5% 1/16W MF-LF 402

100K

R3315

1

2

VREFMRGN

MAX4253

UCSP

U3302

C3

C2

C1

C4

B1

B4

VREFMRGN

UCSP

MAX4253

U3303

A3

A2

A1

A4

B1

B4

MAX4253

UCSP

VREFMRGN

U3302

A3

A2

A1

A4

B1

B4

UCSP

MAX4253

VREFMRGN

U3303

C3

C2

C1

C4

B1

B4

VREFMRGN

UCSP

MAX4253

U3304

A3

A2

A1

A4

B1

B4

UCSP

MAX4253

VREFMRGN

U3304

C3

C2

C1

C4

B1

B4

PLACE_NEAR=J2900.126:2.54mm

1/16W

1%

402

MF-LF

200

VREFMRGN

R3309

1 2

PLACE_NEAR=J3100.126:2.54mm

200

MF-LF

402

1%

1/16W

VREFMRGN

R3311

1 2

SHORT

NONE

402

NONE NONE

OMIT

R3318

1 2

NONE

402

NONE

SHORT

OMIT

NONE

R3319

1 2

26

200

MF-LF

402

1%

1/16W

VREFMRGN

PLACE_NEAR=J2900.1:2.54mm

R3303

1 2

133

PLACE_NEAR=R3303.2:1mm

1/16W

1%

402

MF-LF

VREFMRGN

R3304

1 2

VREFMRGN

200

MF-LF

402

1%

1/16W

PLACE_NEAR=J3100.1:2.54mm

R3305

1 2

133

PLACE_NEAR=R3305.2:1mm

VREFMRGN

1/16W

1%

MF-LF

402

R3306

1 2

5% 1/16W MF-LF 402

VREFMRGN

100K

R3302

1

2

MF-LF

1/16W

5%

100K

402

VREFMRGN

R3301

1

2

133

PLACE_NEAR=R3309.2:1mm

VREFMRGN

MF-LF

402

1%

1/16W

R3310

1 2

402

MF-LF

1/16W

5%

100K

VREFMRGN

R3307

1

2

PCA9557

QFN

VREFMRGN

CRITICAL

U3301

3

4

5

8

6 7

9

10 11

12

13 14

15

1 2

17

16

10V

VREFMRGN

0.1UF

CERM

402

20%

C3304

1

2

133

MF-LF

402

1%

1/16W

PLACE_NEAR=R3311.2:1mm

VREFMRGN

R3312

1 2

MF-LF 402

100K

5% 1/16W

VREFMRGN

R3308

1

2

16 23 27 29 31 42 48 62 77 81

CRITICAL

MSOP

VREFMRGN

DAC5574

U3300

9

10

3

6

7

8

1

2

4

5

16 23 27 29 31 42 48 62 77 81

10V

20%

402

CERM

0.1UF

VREFMRGN

C3301

1

2

6.3V

20%

402-LF

CERM

2.2UF

VREFMRGN

C3300

1

2

CERM

20%

0.1UF

402

10V

VREFMRGN

C3305

1

2

VREFMRGN

402

CERM

20% 10V

0.1UF

C3303

1

2

SYNC_DATE=06/01/2010

SYNC_MASTER=K91_MLB

FSB/DDR3/FRAMEBUF Vref Margining

VREFMRGN_NOT

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

2

R3309,R3311

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

2

VREFMRGN_NOT

R3303,R3305

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_DQ_SODIMMA_BUF

DDRREG_FB

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

PCA9557D_RESET_L

SMBUS_PCH_CLK

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_SODIMMB_DQ

VREFMRGN_SODIMMA_DQ

VREFMRGN_MEMVREG_BUF

VREFMRGN_FRAMEBUF_EN

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_MEMVREG_FBVREF

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_DAC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_CTRL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_A

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PPVTTDDR_S3

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_MEMVREG_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_SODIMMS_CA

PP3V3_S3

VREFMRGN_CA_SODIMMA_BUF

33 OF 109

31 OF 86

9

27

9

29

27

29

7

67

6 7 8

18 24 26 30 32 33 48 50

54 55 72 73

BI

IN

BI

SYM_VER-1

IN

OUT

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN IN

S

G

D

IN

BI

SYM_VER-1

BI

IN

OUT

OUT OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AIRPORT

206 mA nominal max

LOADING

MOSFET

275 mA peak

ALS CAMERA

518S0815

20-30 MOHM @2.5V

0.727 A (EDP)

TPCP8102

P-TYPE

3V S3 WLAN FET

CHANNEL

RDS(ON)

Supervisor & CLKFREG # ISolation

Delay = 60 ms +/- 20%

155S0367

606 MA NOMINAL MAX

BLUETOOTH

516S0582

727 MA PEAK

FERR-120-OHM-1.5A

0402-LF

PLACE_NEAR=J3402.6:2.54MM

L3408

12

CERM

20% 10V

402

0.1uF

C3452

1

2

18 80

6

45 48 54 55 84

6

45 48 54 55 84

CRITICAL

90-OHM DLP0NS

PLACE_NEAR=J3402.2:2.54MM

L3407

1 2

34

F-RT-SM1

819Q-3506-K281

CRITICAL

J3402

7

8

1

2

3

4

5

6

73

MF-LF

5%

10K

1/16W

402

R3451

1

2

402

MF-LF

1/16W

33K

5%

R3450

1 2

26

18 73

16 23

20% 10V

0.1uF

CERM 402

C3440

1

2

CRITICAL

TDFN

SLG4AP016V

U3440

6

5

7

3

8

4

2

9

1

402

MF-LF

1/16W

1%

232K

R3454

1

2

100K

1%

402

MF-LF

1/16W

R3453

1

2

402

MF-LF

1/16W

1%

100K

R3455

1

2

16 81

0201X5R-CERM

PLACE_NEAR=J3401.15:2.54mm

0.1UF

10% 16V

C3431

1 2

0201

0.1UF

10% 16V

PLACE_NEAR=J3401.17:2.54mm

X5R-CERM

C3430

1 2

0201

0.6NH+/-0.1NH-0.85A

OMIT

L3470

1 2

OMIT

0201

0.6NH+/-0.1NH-0.85A

L3471

1 2

0.033UF

16V X5R 402

10%

C3451

1

2

CRITICAL

TPCP8102

23V1K-SM

Q3450

5 6 7 8

4

1 2 3

16V X5R

402-1

0.1UF

10%

C3450

1 2

PLACE_NEAR=Q3450.6:2.54mm

10V

20%

805

10UF

X5R

C3420

1

2

CERM

10V

20%

402

0.1uF

C3421

1

2

FERR-120-OHM-3A

0603

L3404

1 2

10V

20%

CERM

402

0.1uF

PLACE_NEAR=J3401.29:2.54mm

C3422

1

2

16 81

6

24 80

6

24 80

90-OHM-100MA

DLP11S

PLACE_NEAR=J3401.11:2.54mm

CRITICAL

L3401

1 2

34

0402-LF

PLACE_NEAR=J3401.27:2.54mm

FERR-120-OHM-1.5A

L3406

12

CERM

0.01UF

16V

402

10%

C3432

1

2

6

45 48 51 84

6

45 48 51 84

45 46

6

17 26

0

5%

MF-LF

402

1/16W

R3400

1 2

0

5%

1/16W MF-LF

402

R3401

1 2

0

5%

1/16W MF-LF

402

R3402

1 2

500913-0302

F-ST-SM

CRITICAL

J3401

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

OMIT

0201

0.6NH+/-0.1NH-0.85A

L3472

1 2

0201

10%

0.1UF

X5R-CERM

16V

NOSTUFF

C3475

1

2

OMIT

0.6NH+/-0.1NH-0.85A

0201

L3473

1 2

X5R-CERM

0.1UF

10%

0201

16V

NOSTUFF

C3477

1

2

16V

X5R-CERM

0201

10%

0.1UF

NOSTUFF

C3474

1

2

0201

16V

X5R-CERM

0.1UF

10%

NOSTUFF

C3476

1

2

16 81

201

1.0PF

+/-0.1PF 25V C0G

NOSTUFF

C3470

1

2

201

1.0PF

25V C0G

+/-0.1PF

NOSTUFF

C3471

1

2

201

+/-0.1PF 25V C0G

1.0PF

NOSTUFF

C3472

1

2

C0G

25V

+/-0.1PF

1.0PF

201

NOSTUFF

C3473

1

2

RES, 0ohm, 0201

117S0002 4

L3470,L3471,L3472,L3473

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

X19/ALS/CAMERA CONNECTOR

PCIE_AP_R2D_PI_N

PCIE_AP_R2D_N

PCIE_AP_R2D_P

PCIE_AP_D2R_PI_P

PCIE_AP_D2R_PI_N

PCIE_AP_D2R_P

SMBUS_SMC_0_S0_SDA

PP3V3_WLAN_F

AP_CLKREQ_Q_L

PCIE_CLK100M_AP_P

PCIE_WAKE_L

WIFI_EVENT_L_R

AP_TEMP_SMB_SCL_R

AP_TEMP_SMB_SDA_R

SMBUS_SMC_0_S0_SCL

WIFI_EVENT_L

PP3V3_S3

PCIE_CLK100M_AP_N

PP3V3_WLAN_F

MIN_NECK_WIDTH=0.4 mm MIN_LINE_WIDTH=1 mm

P3V3WLAN_SS

PP3V3_S3

PCIE_AP_R2D_C_P

P3V3WLAN_VMON

AP_RESET_L

AP_PWR_EN

AP_CLKREQ_L

PP3V3_S3

PM_WLAN_EN_L

USB_CAMERA_CONN_P

SMBUS_SMC_A_S3_SCL

PP5V_S3

USB_CAMERA_P

USB_CAMERA_N

PP5V_S3_ALSCAMERA_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PCIE_AP_R2D_C_N

PCIE_CLK100M_AP_CONN_N

MIN_NECK_WIDTH=0.2 mm

PP3V3_S3_BT_F

MIN_LINE_WIDTH=0.5 mm

SMBUS_SMC_A_S3_SDA

USB_CAMERA_CONN_N

PCIE_CLK100M_AP_CONN_P

AP_RESET_CONN_L

USB_BT_P

USB_BT_N

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_WLAN

PCIE_AP_D2R_N

PCIE_AP_R2D_PI_P

34 OF 109

32 OF 86

81

6

81

6

81

6

81

6

81

32

6

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

32

6 7 8

18 24 26

30 31 32 33 48

50 54 55 72 73

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

6

80

6 7

30 42 43 44 46 57 59 60 61

66 67 72

6

85

6

80

6

85

6

46

81

OUT

BI

OUT

BI

BI BI

IN

BI

OC*

OUT2

OUT1

OUT0

THRM

GND

EN

IN1

IN0

PAD

VDD

WRITE_PROTECT_SW

CARD_DETECT_SW CARD_DETECT_GND

DAT6 DAT7

DAT1

CD/DAT3

DAT2

DAT4

DAT5

VSS

CLK CMD

DAT0

SHLD_PIN

SHLD_PIN SHLD_PIN

SHLD_PIN

OUT

IN

DET_OUT

DET_IN

RST_IN*

DET_CHNGD*

LOW_PWR

RST_OUT*

VDD

THRM

GND PAD

(IPU)

(OD)

DLY

XOR

LOGIC

RST

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

516-0225

(CARD INSERTED = OPEN)

MAKES THE ACTIVE-HIGH CASE UNUSABLE.

CAESAR-IV CARD DETECT IS PROGRAMMABLE, BUT A SILICON BUG

FROM SD CONN ->

SD CARD 3.3V OVERCURRENT PROTECTION CHIP WITH ACTIVE LOAD DISCHARGE

-> TO PCH GPIO

353S0004

TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.

-> TO ENET CHIP

-> FROM PCH GPIO

regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms

SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION.

SD CARD CONNECTOR

DLY block is 20ms nominal

(SDCONN_STATE_RST_L will be required with LATCH)

*** Need to confirm with SW whether LATCH is required.

37 82

37

37 82

DGN

CRITICAL

TPS2065-1

U3500

4

1

2 3

5

6 7 8

9

603

X5R

6.3V

20%

10UF

C3502

1

2

16V

10%

402

X7R-CERM

0.1UF

C3503

1

2

5% MF-LF

NOSTUFF

1/16W 402

47K

R3500

1

2

603

6.3V X5R

20%

10UF

C3500

1

2

10% 16V

402

X7R-CERM

0.1UF

C3501

1

2

0

5%

1/16W

402

MF-LF

R3502

1 2

MF-LF

1/16W

402

5%

10K

R3501

1

2

SD-CARD-K19-K24

F-RT-TH

J3500

15

14

1

5

2

7

8

9

10

11

12

13

17

18

19

20

4

3

6

16

33

402

MF-LF

PLACE_NEAR=U3900.26:5.1MM

1/16W

5%

R3561

1 2

33

1/16W

5%

402

MF-LF

PLACE_NEAR=U3900.25:5.1MM

R3571

1 2

PLACE_NEAR=U3900.24:5.1MM

33

MF-LF

5%

1/16W

402

R3572

1 2

33

1/16W

402

5%

MF-LF

PLACE_NEAR=U3900.23:5.1MM

R3573

1 2

33

PLACE_NEAR=U3900.22:5.1MM

402

MF-LF1/16W

5%

R3574

1 2

33

PLACE_NEAR=U3900.52:5.1MM

5%

402

1/16W MF-LF

R3575

1 2

PLACE_NEAR=U3900.53:5.1MM

33

5%

1/16W

402

MF-LF

R3576

1 2

1/16W33MF-LF

402

5%

PLACE_NEAR=U3900.55:5.1MM

R3577

1 2

33

402

MF-LF1/16W

5%

PLACE_NEAR=U3900.55:5.1MM

R3578

1 2

37 82

402

1/16W MF-LF

0

5%

R3514

1 2

18 23

37

X5R

10V

1UF

10%

402-1

C3510

1

2

19 23 37

NOSTUFF

5% 1/16W MF-LF

402

10K

R3510

1

2

402

MF-LF

1/16W

0

5%

R3511

1 2

18 26 30 36 40

CRITICAL

SLG4AP014V

TDFN

U3511

8

6

7

5

2

3

4

9

1

NOSTUFF

0

1/16W

402

5%

MF-LF

R3512

1

2

402

CERM

50V

+/-0.25PF

8.2PF

C3570

1

2

50V CERM 402

8.2PF

+/-0.25PF

C3571

1

2

NOSTUFF

10PF

5% 50V COG-CERM 0201

C3572

1

2

47NH-1.3OHM

0402

L3500

1 2

NOSTUFF

5% 50V

10PF

COG-CERM 0201

C3574

1

2

5%

0201

NOSTUFF

10PF

50V COG-CERM

C3576

1

2

NOSTUFF

COG-CERM

10PF

5% 50V

0201

C3578

1

2

NOSTUFF

10PF

5% 50V COG-CERM 0201

C3580

1

2

50V

5%

10PF

NOSTUFF

COG-CERM 0201

C3581

1

2

NOSTUFF

50V

5%

10PF

COG-CERM 0201

C3579

1

2

NOSTUFF

10PF

COG-CERM 0201

50V

5%

C3577

1

2

NOSTUFF

50V

5%

10PF

COG-CERM 0201

C3575

1

2

0201

50V

5%

10PF

NOSTUFF

COG-CERM

C3573

1

2

FERR-10-OHM-300MA

CRITICAL

0402

L3579

1 2

SD READER CONNECTOR

SYNC_MASTER=K91_MLB

SYNC_DATE=05/26/2010

PLT_RESET_L

ENET_CR_CMD

SDCONN_CMD

SDCONN_CLK_L

SDCONN_DATA<2>

SDCONN_DATA<6>

ENET_CR_DETECT_L

ENET_CR_CLK

ENET_CR_DATA<1>

ENET_CR_DATA<4>

ENET_CR_DATA<7>

SDCONN_OC_L_R

PP3V3_S3

SDCONN_STATE_CHANGE

ENET_RESET_L

ENET_CR_PWREN

PP3V3_S0_SW_SD_PWR

PP3V3_S0

SDCONN_OC_L

SLG_ENET_RESET_R_L

ENET_LOW_PWR

SLG_ENET_RESET_L

SDCONN_DETECT

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP3V3_S0_SW_SD_PWR

VOLTAGE=3.3V

PP3V3_S0

SDCONN_CLK

SDCONN_DATA<0> SDCONN_DATA<1>

SDCONN_DATA<3> SDCONN_DATA<4> SDCONN_DATA<5>

SDCONN_DATA<7> SDCONN_DETECT

PP3V3_S0_SW_SD_PWR

ENET_CR_DATA<0>

ENET_CR_DATA<2> ENET_CR_DATA<3>

ENET_CR_DATA<6>

ENET_CR_DATA<5>

SDCONN_WP

35 OF 109

33 OF 86

82

6 7 8

18 24 26 30 31 32 48 50

54 55 72 73

37

33

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

33

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

82

33

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN

OUT

IN IN

OUT

BI

DPSNK0_ML_LANE_3P DPSNK0_ML_LANE_3N

DPSNK0_ML_LANE_2P

DPSRC0_HOT_PLUG_DET

TEST_POINT_2 TEST_POINT_3

DPSNK0_HOT_PLUG_DET

DPSNK0_AUX_CHN

DPSNK0_AUX_CHP

DPSNK0_ML_LANE_0N

DPSNK0_ML_LANE_0P

DPSNK0_ML_LANE_1N

DPSNK0_ML_LANE_1P

DPSNK0_ML_LANE_2N

TEST_POINT_0

TEST_EN

THERM_DP

EE_CLK

EE_CS*

EE_DO

EE_DI

PCIE_CLKREQ_3*

PCIE_CLKREQ_2*

PCIE_CLKREQ_1*

PCIE_CLKREQ_0*

DPSNK1_ML_LANE_1P

DPSNK1_ML_LANE_2N

DPSNK1_ML_LANE_2P

DPSNK1_ML_LANE_3N

DPSNK1_ML_LANE_3P

DP_RES_1

DP_RES_0

DP_ATEST

DPSRC0_AUX_CHN

DPSRC0_AUX_CHP

DPSRC0_ML_LANE_0N

DPSRC0_ML_LANE_0P

DPSRC0_ML_LANE_1N

DPSRC0_ML_LANE_1P

DPSRC0_ML_LANE_2N

DPSRC0_ML_LANE_2P

DPSRC0_ML_LANE_3N

DPSRC0_ML_LANE_3P

TMU_CLK_OUT

TMU_CLK_IN

XTAL_25_IN

XTAL_25_OUT

REFCLK_100_IN_P REFCLK_100_IN_N

TDO

TCK

TMS

TDI

PCIE_RST_3*

PCIE_RST_1* PCIE_RST_2*

PCIE_RST_0*

RBIAS

RSENSE

PERST*

WAKE*

PER_1_P

PER_2_P

PER_3_P

MONDC0

MONOBSN

MONOBSP

MONDC1

PER_3_N

PER_2_N

PER_0_N

PER_0_P

PET_3_P PET_3_N

PET_2_N

PET_2_P

PET_1_P PET_1_N

PET_0_N

PET_0_P

TEST_POINT_1

DPSNK1_ML_LANE_0N

PER_1_N

DPSNK1_ML_LANE_0P

DPSNK1_ML_LANE_1N

DPSNK1_AUX_CHP

DPSNK1_HOT_PLUG_DET

DPSNK1_AUX_CHN

PRT0_T29T_N

PRT0_T29R_P PRT0_T29R_N

T29_0_LSEO T29_0_LSOE

PRT1_T29T_P PRT1_T29T_N

PRT1_T29R_P PRT1_T29R_N

T29_1_LSEO T29_1_LSOE

T29_SDA T29_SCL

PRT2_T29T_P PRT2_T29T_N

PRT2_T29R_P PRT2_T29R_N

T29_2_LSEO T29_2_LSOE

PRT3_T29T_P PRT3_T29T_N

PRT3_T29R_P PRT3_T29R_N

T29_3_LSEO T29_3_LSOE

PRT0_T29T_P

PORT2

PCIE GEN2

RECEIVE

TRANSMIT

PORTS

(SYM 1 OF 2)

JTAG

POWER ON RESET

MISC

CLOCKS

SOURCE PORT 0

DISPLAY

PORT3

PORT0PORT1

CLK REQUEST

EEPROM

TEST PORT

SINK PORT 0SINK PORT 1

BI

IN

BI

IN IN IN

OUT

IN

D

VCC

THM

VSS

PAD

Q

C

S_L

W_L

HOLD_L

OUT IN

OUT

IN

OUT

IN IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DEBUG: For monitoring current/voltage

DEBUG: For monitoring clock

together. Other signals okay to float (TP/NC).

(T29_SPI_CS_L)

(T29_SPI_CLK)

NOTE: All unused LSOE/EO pairs should be aliased

Use B1 GND ball for THERM_DN

Not used in host mode.

(T29_SPI_MISO)(T29_SPI_MOSI)

SNK1 AC Coupling

SNK0 AC Coupling

100pF SRF > 40MHz

1/16W

5%

402

MF-LF

3.3K

R3690

1

2

402

1/16W

1%

MF-LF

14.0K

R3685

1

2

402

100PF

BYPASS=U3600.Y19::2mm

5%

50V

CERM

C3685

1

2

BYPASS=U3600.Y19::5.08mm

0.01UF

402

CERM

16V

10%

C3686

1

2

8

17

8

17

402

MF-LF

1/16W

5%

0

R3625

1

2

MF-LF 402

100K

1/16W

5%

R3632

1

2

75

75 83

75

75 83

8

402

MF-LF

100K

1/16W

5%

R3630

1

2

1/16W

402

100K

MF-LF

5%

R3631

1

2

5%

10K

402

NO STUFF

MF-LF

1/16W

R3699

1

2

48 75 83

OMIT_TABLE

T29

FCBGA

CRITICAL

U3600

Y19 Y21 AA20

W2

V1

V5

Y9

AA10

Y7

AA8

Y5

AA6

Y3

AA4

U6

V7

U4

U14

V15

U12

V13

U10

V11

U8

V9

U16

W16

V3

Y11

AA12

Y13

AA14

Y15

AA16

Y17

AA18

L2

N2

P1 M1

B21

A20

M17

K17

P3 N4 M3 L4

K1 J2 K3 J4

T19

V19

M19

P19

H19

K19

D19

F19

E6

T21

V21

M21

P21

H21

K21

D21

F21

C2

C4

A4

A6

C6

C8

A8

A10

C10

C12

A12

A14

C14

C16

A16

A18

E16

G16

H17

E14

J6 K5

G6 H5

G4 H3

G2 H1

F5

F3

R2

T3

T1

E4 P5 N6 M5 L6

A2

R4

E2

U2

F1

P17 R16

MF-LF

5%

0

402

1/16W

R3629

1

2

1/16W MF-LF 402

5%

3.3K

R3693

1

2

1/16W

5%

10K

402

MF-LF

R3698

1

2

402

5% 1/16W MF-LF

10K

R3623

1

2

MF-LF

10K

1/16W 402

5%

R3622

1

2

1/16W

5%

10K

MF-LF 402

R3621

1

2

8

17 83

8

17 83

8

83

8

83

8

83

8

83

8

83

8

83

8

83

8

83

1.0K

0.5% 1/16W MF-LF

603

R3655

1

2

0.1UF

X5R-CERM

0201

16V10%

C3620

1 2

8

83

8

83

8

83

8

83

8

83

8

83

8

83

8

83

CERM

10%

1UF

6.3V 402

C3690

1

2

8

17 83

8

17 83

201

1/20W

MF5%

10K

R3651

2 1

8

19

16

8

19 23

8

19

1K

402

5% 1/16W MF-LF

R3696

1

2

1%

806

402

1/16W MF-LF

R3695

1 2

26 81

2KX8-1.8V

M95160

OMIT_TABLE

MLP

CRITICAL

U3690

6

5

7

2

1

9

8

4

3

75

8

X5R-CERM

0201

0.1UF

16V10%

C3621

1 2

X5R-CERM

0201

0.1UF

16V10%

C3622

1 2

X5R-CERM

0201

0.1UF

16V10%

C3623

1 2

X5R-CERM

0201

0.1UF

16V10%

C3624

1 2

X5R-CERM

0201

0.1UF

16V10%

C3625

1 2

X5R-CERM

0201

0.1UF

16V10%

C3626

1 2

X5R-CERM

0201

0.1UF

16V10%

C3627

1 2

X5R-CERM

0201

0.1UF

16V10%

C3628

1 2

X5R-CERM

0201

0.1UF

16V10%

C3629

1 2

X5R-CERM

0201

0.1UF

16V10%

C3630

1 2

X5R-CERM

0201

0.1UF

16V10%

C3631

1 2

X5R-CERM

0201

0.1UF

16V10%

C3632

1 2

X5R-CERM

0201

0.1UF

16V10%

C3633

1 2

X5R-CERM

0201

0.1UF

16V10%

C3634

1 2

X5R-CERM

0201

0.1UF

16V10%

C3635

1 2

X5R-CERM

0201

0.1UF

16V10%

C3636

1 2

X5R-CERM

0201

0.1UF

16V10%

C3637

1 2

X5R-CERM

0201

0.1UF

16V10%

C3638

1 2

10% 16V

0.1UF

0201

X5R-CERM

C3639

1 2

0.1UF

0201

16V10%

X5R-CERM

C3641

1 2

10%

0201

16V

X5R-CERM

0.1UF

C3642

1 2

0201

16V10%

X5R-CERM

0.1UF

C3643

1 2

0201

16V10%

X5R-CERM

0.1UF

C3644

1 2

0201

16V10%

X5R-CERM

0.1UF

C3645

1 2

0.1UF

10%

0201

16V

X5R-CERM

C3646

1 2

10%

0.1UF

X5R-CERM

16V

0201

C3647

1 2

0.1UF

0201

16V10%

X5R-CERM

C3601

1 2

0.1UF

0201

16V10%

X5R-CERM

C3602

1 2

0.1UF

0201

16V10%

X5R-CERM

C3603

1 2

0201

16V10%

X5R-CERM

0.1UF

C3604

1 2

0.1UF

0201

16V10%

X5R-CERM

C3605

1 2

0.1UF

0201

16V10%

X5R-CERM

C3606

1 2

16V

X5R-CERM

0.1UF

10%

0201

C3607

1 2

36

16 81

0.1UF

0201

16V10%

X5R-CERM

C3600

1 2

0.1UF

NO STUFF

10%

0201

16V

X5R-CERM

C3615

1 2

10%

0201

16V

0.1UF

X5R-CERM

NO STUFF

C3616

1 2

1/16W

5%

3.3K

402

MF-LF

R3692

1

2

2015%

1/20W

MF

0

NO STUFF

R3611

1 2

0

NO STUFF

201

1/20W

MF5%

R3610

1 2

0201

16V10%

X5R-CERM

0.1UF

C3640

1 2

3.3K

402

MF-LF

5% 1/16W

R3691

1

2

36

8

81

8

81

8

81

8

81

8

81

8

81

8

81

8

81

8

81

8

81

8

81

8

81

8

81

8

81

8

81

8

81

SYNC_MASTER=T29

SYNC_DATE=10/12/2010

T29 Host (1 of 2)

T29_MONOBSN

PCIE_T29_R2D_N<3>

T29_MONOBSP

T29_MONDC1

PCIE_T29_D2R_C_P<3>

T29_RSENSE

PCIE_T29_R2D_C_N<3>

PCIE_T29_R2D_C_P<2>

PCIE_T29_R2D_C_P<3>

PCIE_T29_R2D_P<3>

PCIE_T29_R2D_C_N<2>

PCIE_T29_R2D_N<2>

PCIE_T29_R2D_P<2>

PCIE_T29_R2D_C_N<1>

PCIE_T29_R2D_N<1>

PCIE_T29_R2D_C_P<1>

PCIE_T29_R2D_P<1>

PCIE_T29_R2D_C_N<0>

PCIE_T29_R2D_N<0>

PCIE_T29_D2R_C_N<3>

PCIE_T29_D2R_N<3>

PCIE_T29_D2R_P<3>

PCIE_T29_D2R_C_N<2>

PCIE_T29_D2R_N<2>

PCIE_T29_D2R_C_P<2>

PCIE_T29_D2R_P<2>

PCIE_T29_D2R_C_N<1>

PCIE_T29_D2R_N<1>

PCIE_T29_D2R_C_P<1>

PCIE_T29_D2R_P<1>

PCIE_T29_D2R_C_N<0>

PCIE_T29_D2R_N<0>

DP_T29SNK1_AUXCH_P

TP_DP_T29SRC_ML_CN<1>

DP_T29SNK0_ML_P<1>

DP_T29SNK0_ML_N<1>

DP_T29SNK0_ML_P<2>

DP_T29SNK0_AUXCH_P

DP_T29SNK0_ML_N<0>

DP_T29SNK0_AUXCH_N

DP_T29SNK1_AUXCH_C_N

DP_T29SNK1_AUXCH_N

DP_T29SNK1_AUXCH_C_P

DP_T29SNK1_ML_C_N<3>

DP_T29SNK1_ML_N<3>

DP_T29SNK1_ML_C_P<3>

DP_T29SNK1_ML_P<3>

DP_T29SNK1_ML_C_N<2>

DP_T29SNK1_ML_N<2>

DP_T29SNK1_ML_C_P<2>

DP_T29SNK1_ML_P<2>

DP_T29SNK1_ML_C_N<1>

DP_T29SNK1_ML_N<1>

DP_T29SNK1_ML_C_P<1>

DP_T29SNK1_ML_P<1>

DP_T29SNK1_ML_C_N<0>

DP_T29SNK1_ML_N<0>

DP_T29SNK1_ML_C_P<0>

DP_T29SNK1_ML_P<0>

DP_T29SNK0_AUXCH_C_N

DP_T29SNK0_AUXCH_C_P

DP_T29SNK0_ML_C_N<3>

DP_T29SNK0_ML_N<3>

DP_T29SNK0_ML_C_P<3>

DP_T29SNK0_ML_P<3>

DP_T29SNK0_ML_C_N<2>

DP_T29SNK0_ML_N<2>

DP_T29SNK0_ML_C_P<2>

DP_T29SNK0_ML_C_N<1>

DP_T29SNK0_ML_C_P<1>

DP_T29SNK0_ML_C_N<0>

DP_T29SNK0_ML_C_P<0>

T29_SPI_MOSI

T29_SPI_CLK

DP_T29SNK1_HPD

T29_LSOE<1>

T29_LSEO<1>

T29_PCIE_WAKE_L

DP_T29SNK0_ML_P<2>

DP_T29SRC_HPD

TP_T29_TEST_POINT_2 T29_TEST_POINT_3

DP_T29SNK0_HPD

DP_T29SNK0_AUXCH_N

DP_T29SNK0_AUXCH_P

DP_T29SNK0_ML_N<0>

DP_T29SNK0_ML_P<0>

DP_T29SNK0_ML_N<1>

DP_T29SNK0_ML_P<1>

DP_T29SNK0_ML_N<2>

TP_T29_TEST_POINT_0

T29_TEST_EN

T29_THERMD_P

T29_RSVD

T29_GPIO<2>

T29_GPIO<1>

T29_CLKREQ_ISOL_L

DP_T29SNK1_ML_P<1>

DP_T29SNK1_ML_N<2>

DP_T29SNK1_ML_P<2>

DP_T29SNK1_ML_N<3>

DP_T29SNK1_ML_P<3>

T29_DP_RES

T29_DP_ATEST

TP_DP_T29SRC_AUXCH_CN

TP_DP_T29SRC_AUXCH_CP

TP_DP_T29SRC_ML_CN<0>

TP_DP_T29SRC_ML_CP<0>

TP_DP_T29SRC_ML_CP<1>

TP_DP_T29SRC_ML_CN<2>

TP_DP_T29SRC_ML_CP<2>

TP_DP_T29SRC_ML_CN<3>

TP_DP_T29SRC_ML_CP<3>

T29_TMU_CLK_OUT T29_TMU_CLK_IN

SYSCLK_CLK25M_T29_R TP_T29_XTAL25OUT

PCIE_CLK100M_T29_P PCIE_CLK100M_T29_N

JTAG_ISP_TDO

JTAG_ISP_TCK

JTAG_T29_TMS

JTAG_ISP_TDI

TP_T29_PCIE_RESET3_L

TP_T29_PCIE_RESET1_L TP_T29_PCIE_RESET2_L

TP_T29_PCIE_RESET0_L

T29_RBIAS

T29_RESET_L

T29_MONDC0

PCIE_T29_R2D_P<0>

TP_T29_TEST_POINT_1

DP_T29SNK1_ML_N<0>

DP_T29SNK1_ML_P<0>

DP_T29SNK1_ML_N<1>

DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N

T29_R2D_C_N<0> T29_D2R_P<0>

T29_D2R_N<0> T29_LSEO<0>

T29_LSOE<0>

T29_R2D_C_P<1> T29_R2D_C_N<1>

T29_D2R_P<1> T29_D2R_N<1>

NC_T29_R2D_CP<2> NC_T29_R2D_CN<2>

NC_T29_D2RP<2> NC_T29_D2RN<2>

NC_T29_R2D_CP<3> NC_T29_R2D_CN<3>

NC_T29_D2RP<3> NC_T29_D2RN<3>

T29_R2D_C_P<0>

DP_T29SNK0_ML_P<0>

PCIE_T29_D2R_P<0>

PCIE_T29_R2D_C_P<0>

TP_T29_MONOBSN

TP_T29_MONOBSP

SYSCLK_CLK25M_T29

TP_T29_MONDC1

PP3V3_T29

TP_T29_MONDC0

PP3V3_T29

T29ROM_WP_L T29ROM_HOLD_L

I2C_T29_SDA I2C_T29_SCL

T29_SPI_MISO

T29_LSEO<2> T29_LSOE<2>

T29_LSOE<3>

T29_LSEO<3>

PCIE_T29_D2R_C_P<0>

PP3V3_T29

T29_SPI_CS_L

DP_T29SNK0_ML_N<3>

DP_T29SNK0_ML_P<3>

36 OF 109

34 OF 86

81

81 81

81

34 83

83

34 83

51 85

34 83

81

34 83

7

16 19 26 34 35 36

7

16 19 26 34 35 36

83

81

7

16 19 26 34 35 36

83

34 83

VCC3P3_DP_RX1 VCC3P3_DP_RX1

VCC3P3_DP_TXRX VCC3P3_DP_TXRX

VDD3P3DP_PLL

VCC3P3_DP_TXRXBIAS

VSSDP

VSSDP VSSDP VSSDP

VSSDP

VSSDP_PLL

VSSDP

VSSPE

VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE

VCC1P0

VCC1P0 VCC1P0

VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE

VDD1P0_DP_TXRX

VDD1P0_DP_RX1

VDD1P0_DP_TXRX

VDD1P0_DP_PLL

VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VCC1P0_PE

VCC3P3 VCC3P3 VCC3P3

VCC3P3_T29 VCC3P3_T29

GND VCC

(SYM 2 OF 2)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.

0-ohms are placeholders for now, replace

2100 mA (Single Port) 2250 mA (Dual Port) EDP: 3000 mA

135 mA (Single-Port)

with proper values after characterization.

152 mA (Dual-Port) EDP: 200 mA

FERR-120-OHM-1.5A

0402

L3730

1 2

10%

402

CERM

1UF

6.3V

C3712

1

2

CERM 402

10%

6.3V

1UF

C3713

1

2

402

5%

MF-LF

1/16W

0

R3720

1 2

1UF

CERM 402

10%

6.3V

C3714

1

2

402-LF

2.2UF

20%

6.3V CERM

C3730

1

2

1UF

CERM 402

10%

6.3V

C3720

1

2

1UF

CERM 402

10%

6.3V

C3721

1

2

1UF

CERM 402

10%

6.3V

C3722

1

2

6.3V

10% 402

CERM

1UF

C3708

1

2

6.3V

20% 603

X5R

10UF

C3700

1

2

10UF

X5R 603

20%

6.3V

C3701

1

2

1UF

CERM

402

10%

6.3V

C3753

1

2

1UF

CERM

402

10%

6.3V

C3752

1

2

1UF

CERM

402

10%

6.3V

C3744

1

2

1UF

CERM

402

10%

6.3V

C3743

1

2

6.3V

10% 402

CERM

1UF

C3709

1

2

402-LF

2.2UF

20%

CERM

6.3V

C3770

1

2

402-LF

2.2UF

20%

6.3V CERM

C3760

1

2

0402

FERR-120-OHM-1.5A

L3770

1 2

1UF

402

10%

6.3V CERM

C3751

1

2

6.3V

10%

402

1UF

CERM

C3750

1

2

1/16W

5%

402

0

MF-LF

R3760

1 2

1/16W

5%

402

0

MF-LF

R3750

1 2

6.3V

10%

402

CERM

1UF

C3745

1

2

X5R

10UF

20%

6.3V 603

C3746

1

2

10UF

X5R 603

20%

6.3V

C3747

1

2

CERM

1UF

402

10%

6.3V

C3710

1

2

6.3V

10%

402

CERM

1UF

C3711

1

2

T29

CRITICAL

OMIT_TABLE

FCBGA

U3600

H9 H11 H13

K9 K11 K13

M9 M11 M13

H15 K15 M15

E8 E10 E12 G14

H7 M7 K7

P7 R6

P9 P11

P15

G10 G12

R14

R8 R10 R12

P13

G8

J8

N10 N12 N14

J10 J12 J14

L8 L10 L12 L14

N8

T5 T7

W10 W12 W14 Y1 AA2

T9 T11 T15 T17 V17 W4 W6 W8

T13

B1

B3

C18 C20

D1

D3

D5

D7

D9 D11 D13 D15

B5

D17 E18 E20

F7

F9 F11 F13 F15 F17 G18

B7

G20 J16 J18 J20 L16 L18 L20 N16 N18 N20

B9

R18 R20 U18 U20 W18 W20

B11 B13 B15 B17 B19

CERM 402

10%

6.3V

1UF

C3705

1

2

1UF

6.3V

10% 402

CERM

C3706

1

2

1UF

6.3V

10% 402

CERM

C3707

1

2

T29 Host (2 of 2)

SYNC_DATE=10/12/2010

SYNC_MASTER=T29

PP3V3_T29

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PP1V05_T29_VDD_DPPLL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PP1V05_T29_VDD_DP

PP1V05_T29

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_T29_DPBIAS

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_T29_PLL

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_T29_DP

37 OF 109

35 OF 86

7

16 19 26 34 36

7

36

GND

VOUT

ON

VIN

GND

VOUT

ON

VIN

OUT

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

GND

VOUT

ON

VIN

IN

D

G S

D

S G

D

S G

IN

SGD

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO = 4.55V (falling), 4.95 (rising)

Load Switch

U3816.A2:

T29BST:Y - Stuffs 18V boost circuitry.

- =PP18V_T29_REG (18V Boost Output)

BOM options provided by this page:

- =PP3V3_S0_T29PWRCTL

- =T29_CLKREQ_L

- =T29_RESET_L

- =PP1V05_T29_P1V05T29FET (1.05V FET Input)

- =PP1V05_T29_FET (1.05V FET Output) Signal aliases required by this page:

- =PP3V3_T29_P3V3T29FET (3.3V FET Input)

- =PP3V3_T29_FET (3.3V FET Output)

<R2>

Vgs(th): -1.4V

Id(max): 3.7A @ 70C

Vgs(max): +/-12V

SI8409DB: Vds(max): -30V

Rds(on): 46mOhm @ 4.5V Vgs

Voltage not specified here, add property on another page.

<R1>

Max Vgs: 10V

GND inside package,

<Rb>

<Ra>

Max Current = 0.8A

Power aliases required by this page:

Supervisor & CLKREQ# Isolation

Page Notes

1.05V T29 Switch

Open-Drain GPIO

Platform (PCIe) Reset

Pull-up provided by SB page.

Type

Part

R(on)

Max Current = 1.7A (85C)

Max Current = 3.4A (85C)

DLY = 60 ms +/- 20%

Max Output: 2A per IC

U3810 & U3815/U3816

TPS22924C

50 mOhm Max

18 mOhm Typ

3.3V T29 Switch

- =PPVIN_SW_T29BST (8-13V Boost Input)

8-13V Input Changes required for 2S.

Pull-up provided by SB page.

T29 15V Boost Regulator

Vout = 1.6V * (1 + Ra / Rb)

no XW necessary.

SGND shorted to

Freq = 300KHz

Vout = 18.3V

CRITICAL

CSP

TPS22924

U3810

C1

C2

A2 B2

A1 B1

TPS22924

CRITICAL

CSP

U3815

C1

C2

A2 B2

A1 B1

34

10K

5%

MF-LF

402

1/16W

R3803

2

1

16

402

25V X5R

10%

0.1UF

C3800

1

2

18 26 30 33 40

34 36

6.3V

10%

1UF

CERM

402

C3810

1

2

402

CERM

6.3V

10%

1UF

C3815

1

2

TDFN

CRITICAL

SLG4AP016V

U3800

6

5

7

3

8

4

2

9

1

100K

5% 1/16W MF-LF 402

R3807

1

2

19

PLACE_NEAR=U3815.B2:3 mm

CSP

CRITICAL

TPS22924

U3816

C1

C2

A2 B2

A1 B1

16

8

75 76

T29BST:Y

402

5%

MF-LF

1/16W

330K

R3881

1

2

T29BST:Y

MF-LF

402

5%

1/16W

470K

R3880

1

2

T29BST:Y

402

0.1UF

25V

10% X5R

C3880

1

2

T29BST:Y

SSM3K15FV

SOD-VESM-HF

Q3805

3

1

2

T29BST:Y

MF-LF

1/16W

1%

402

73.2K

R3892

1

2

330K

5%

T29BST:Y

MF 201

1/20W

R3887

1

2

SOT563

SSM6N37FEAPE

T29BST:Y

Q3888

3

5

4

T29BST:Y

SSM6N37FEAPE

SOT563

Q3888

6

2

1

T29BST:Y

1/16W

402

MF-LF

41.2K

1%

R3894

1

2

T29BST:Y

0.33UF

6.3V CERM-X5R 402

10%

C3894

1

2

330K

5%

T29BST:Y

MF

1/20W 201

R3888

1

2

26 45

NO STUFF

402

5%

100PF

CERM

50V

C3889

1

2

T29BST:Y

15.8K

1/16W

402

1%

MF-LF

R3896

1

2

X7R-CERM

10%

4.7UF

50V 1206

T29BST:Y

C3895

1

2

T29BST:Y

10%

4.7UF

1206

X7R-CERM

50V

C3896

1

2

T29BST:Y

50V

10%

4.7UF

X7R-CERM 1206

C3897

1

2

50V

5%

100PF

NO STUFF

402

CERM

C3887

1

2

T29BST:Y

10% 10V X5R

4.7UF

805

C3892

1

2

T29BST:Y

CRITICAL

SI8409DB

BGA

Q3880

2 3

1

4

T29BST:Y

10K

1%

1/16W

402

MF-LF

R3893

1

2

T29BST:Y

MF-LF

1/16W

200K

1%

402

R3891

1

2

T29BST:Y

10UF

25V 805

X5R

10%

C3890

1

2

T29BST:Y

25V

10%

10UF

X5R 805

C3891

1

2

T29BST:Y

PCMB063T-100MS

CRITICAL

10UH-4A-68-MOHM

L3895

1 2

50V

100PF

5%

402

NO STUFF

CERM

C3888

1

2

T29BST:Y

CRITICAL

QFN

LT3957

U3890

25

31

1213141516

17

28

1 2 10 35 36

33

6

3

42324

37

32

8

9

202138

34

30

27

1/16W

402

MF-LF

1%

T29BST:Y

137K

R3895

1

2

SM

PLACE_NEAR=C3895.1:2 mm

XW3895

12

T29BST:Y

0

5%

MF-LF

402

1/16W

R3889

1

2

CRITICAL

POWERDI-123

DFLS230L

T29BST:Y

D3895

1

2

T29BST:Y

50V

X7R-CERM

4.7UF

10%

1206

C3898

1

2

T29BST:Y

50V X7R 402

0.001UF

10%

C3899

1

2

T29BST:Y

50V X7R 402

0.01UF

10%

C3893

1

2

SYNC_DATE=10/12/2010

SYNC_MASTER=T29

T29 Power Support

PP15V_T29

T29BST_VSNS

T29BST_SNS2

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVIN_SW_T29BST

T29BST_EN_UVLO

T29BST_RT

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

GND_T29BST_SGND

T29BST_INTVCC

PP1V05_S0

PPBUS_G3H

PP3V3_T29

PP1V05_T29

PP3V3_S0

T29_CLKREQ_ISOL_L

MAKE_BASE=TRUE

PP3V3_S0

PP1V05_T29

T29_CLKREQ_ISOL_L

T29_RESET_L

T29_SW_RESET_L

PLT_RESET_L

T29_CLKREQ_L

T29_PWR_EN

PP3V3_T29

T29BST_SNS1

T29BST_VC_RC

T29BST_PWREN_L

T29BST_FBX

T29BST_BOOST

SWITCH_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

T29BST_VC

T29BST_PWREN_DIV_L

T29BST_SHDN_DIV

T29BST_SS

SMC_DELAYED_PWRGD

T29_A_HV_EN

38 OF 109

36 OF 86

7 8

76

7

6 7 9

10 12 14 16 17

20 22 23 40 45

68 70 73

6 7 8

40 49 50 63 64 77

7

16 19 26 34 35 36

7

35 36

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

34 36

6 7 8

12 16 17 18 19

20 22 23 26 27

29 33 36 37 40

41 42 46 48 49

50 51 52 54 57

61 62 71 72 73

74 75 77 85

7

35 36

7

16 19 26 34 35 36

IN

OUT

IN

OUT

IN

BI

BI BI

BI BI BI BI BI

NC

BI

BI BI

OUT

IN

OUT

VDDC

SR_LX

PCIE_PLLVDDL

SR_VFB

SR_VDDP

SR_VDD

SCLK SI/LINKLED*

CS*

SO

SPD100LED*/SERIAL_DO TRAFFICLED*/SERIAL_DI

TRD0_P

TRD1_P

TRD0_N

TRD1_N

TRD2_N

TRD2_P

TRD3_N

TRD3_P

GPIO_1/CR_BUS_PWR

GPIO_0

RE*/GPIO_2

VMAIN_PRSNT

PCIE_TXD_N PCIE_TXD_P

PCIE_RXD_N

PCIE_RXD_P

PCIE_REFCLK_N

PCIE_REFCLK_P

PERST*

CLKREQ*

WAKE*

LOW_PWR

SD_DETECT/WE*

CR_CMD/CLE

CR_CLK/RY_BY*

CR_DATA0 CR_DATA1

CR_DATA3

CR_DATA2

CR_DATA4 CR_DATA5 CR_DATA6

CE*/MS_INS*

CR_DATA7

CR_LED/ALE

XD_DETECT

THRM_PAD

XTALI XTALO

RDAC

GPHY_PLLVDDL

AVDDH

VDDO

XTALVDDH

BIASVDDH

AVDDL

SMD_DATA

SMB_CLK

CR_WP*/XD_WP*

OUT

IN

OUT

IN

OUT

BI

BI BI

IN

BI

BI BI

NC

RESET*

CS*

SCK

SO

WP*

SI

GND

VCC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPD)

NOTE: Pull-down on SO plus internal pull-ups on other 3 SPI pins configures ENET for the Atmel AT45DB011D (1Mbit) ROM. If a different ROM is used then the straps must change. NOTE: ENETM requires SI pull-down instead of SO.

ENET 1.2V SR IS ENABLED IF SR_DISABLE is PULLed-DOWN.

NOTE: "IPx" == Programmable pull-up/down

(IPU)

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

If PHY is always powered then alias

Internal 1.2V Switching Regulator pins.

281mA (1000base-T max power, Caesar IV)

is powered-down in S3/S5. Standard

PHY Non-Volatile Memory

BCM requests SD CR[0:7], CMD, CLK termination.

ENET supports both active-levels for WP.

Required for proper PHY operation.

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

Special Star routing needed on these pins. Decoupling on Pg 37.

ENET_CR Signals

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.

???mA (1000base-T, Caesar V)

Must isolate from PCIe WAKE# if PHY

ROM contains MAC address, PCIe config

(IPD)

=ENET_WAKE_L to PCIE_WAKE_L.

(Required ROM size TBD)

info as well as code for Bonjour proxy.

(See note)

N-channel FET isolation suggested.

(OD)

Connect only to U3900 pin 20.

the card reader on-chip I/O.

(OD)

WAKE#

Resistor

VDD for Card Reader I/O

If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.

Control signal to light LED or control SD bus power.

No MS (Memory Stick) Insert feature needed.

Limiting

Current

(IPD)

(OD)

(IPD)

(IPU)

(IPx)

SD_DETECT can only be used active low due to errata.

(IPU)

o

0.1UF

10% 16V

402

X7R-CERM

C3921

1

2

6.3V

805

10%

10UF

X5R

C3935

1

2

4.7UF

6.3V

10%

603

X5R-CERM

C3925

1

2

FERR-600-OHM-0.5A

CRITICAL

SM

L3925

1 2

4.7UF

X5R-CERM

6.3V

10%

603

C3920

1

2

CRITICAL

FERR-600-OHM-0.5A

SM

L3920

1 2

FERR-600-OHM-0.5A

SM

CRITICAL

L3900

1 2

CRITICAL

SM

FERR-600-OHM-0.5A

L3905

1 2

5%

402

1K

MF-LF

1/16W

R3942

1

2

16 81

33 82

16

26

19 23 33

26 81

402

16V

0.1uF

X5R

10%

C3951

1 2

0.1uF

10% 16V X5R 402

C3950

1 2

0.1uF

16V

10%

X5R 402

C3956

1 2

402

X5R

16V

10%

0.1uF

C3955

1 2

1.24K

1/16W

1%

402

MF-LF

R3965

1

2

16 81

38 82

1/16W

4.7K

MF-LF

5%

402

R3941

1

2

5%

4.7K

1/16W MF-LF

402

R3940

1

2

33 82

33

5%

MF-LF

1/16W

402

0

R3943

1 2

1/16W

NOSTUFF

MF-LF

5%

402

4.7K

R3990

1

2

33 82

33

4.7UF

603

6.3V

10% X5R-CERM

C3970

1

2

10%

0.1UF

X7R-CERM 402

16V

C3971

1

2

0.1UF

X7R-CERM

16V

10%

402

C3972

1

2

26

1/16W

5%

4.7K

402

MF-LF

R3910

1

2

OMIT

QFN-8X8

BCM57765

U3900

42

48

394551

37

59

12

21

26

25 24 23 22 52 53 54 55

60 57

63

36

5 8

4

29

32

30

31

34

33

27 28

11

38

9

66

1

64

6

10

65

2

161415

13

69

67

41

40

43

44

47

46

49

50

35

61

72056

62

58

3

68

18 19

17

1K

402

1/16W5%MF-LF

R3980

1 2

8

37

33

SM

CRITICAL

FERR-600-OHM-0.5A

L3910

1 2

37

33 82

0.1UF

X7R-CERM 402

10% 16V

C3910

1

2

33 82

0.1UF

10% 16V

X7R-CERM

402

C3900

1

2

0.1UF

402

10% 16V X7R-CERM

C3911

1

2

X7R-CERM

16V 402

0.1UF

10%

C3990

1

2

10%

0.1UF

16V X7R-CERM 402

C3905

1

2

4.7UF

10%

6.3V X5R-CERM 603

C3930

1

2

X7R-CERM

0.1UF

402

16V

10%

C3931

1

2

CRITICAL

FERR-600-OHM-0.5A

SM

L3930

1 2

4.7UF

603

6.3V

10%

X5R-CERM

C3915

1

2

X7R-CERM 402

16V

10%

0.1UF

C3916

1

2

SOIC-8S1

AT45DB011D

OMIT

U3990

4

7

3

2 1

8

6

5

4.7K

MF-LF 402

5% 1/16W

R3997

1

2

402

X7R-CERM

16V

10%

0.1UF

C3936

1

2

402

16V

10%

X7R-CERM

0.1UF

C3926

1

2

ETHERNET PHY (CAESAR IV)

SYNC_MASTER=K91_MLB

SYNC_DATE=05/26/2010

ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2>

ENET_MDI_N<3>

ENET_MEDIA_SENSE

TP_BCM57765_SPD100LED_L

PP1V2_S3_ENET_INTREG

ENET_MDI_P<0>

ENET_CR_DATA<0>

ENET_CR_DATA<4> ENET_CR_DATA<5>

ENET_CR_DATA<7>

ENET_MDI_P<1>

PCIE_ENET_D2R_C_P

BCM57765_WAKE_R_L

BCM57765_MOSI BCM57765_CS_L

ENET_MDI_N<0>

ENET_CR_DATA<3>

ENET_CR_CLK

PP3V3R1V8_ENET_LR_OUT_REG

ENET_SR_VFB

ENET_SR_LX

ENET_MDI_P<3>

PP3V3_ENET

ENET_WAKE_L

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_N

BCM57765_SCLK

BCM57765_CS_L

BCM57765_MISO

BCM57765_MOSI

PCIE_ENET_R2D_N

PCIE_CLK100M_ENET_P

ENET_RESET_L

ENET_LOW_PWR

ENET_CLKREQ_L

PCIE_ENET_D2R_P

PP3V3R1V8_ENET_LR_OUT_REG

ENET_CR_DATA<2>

ENET_CR_DATA<1>

BDM57765_SR_DISABLE

SDCONN_WP

ENET_CR_PWREN

PP3V3_ENET

PCIE_CLK100M_ENET_N

PP3V3_S0

PCIE_ENET_D2R_C_N

BCM57765_VMAIN_PRSNT

PCIE_ENET_R2D_P

SYSCLK_CLK25M_ENET

BCM57765_RDAC

PP3V3_S3_ENET_PHY_BIASVDDH

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S3_ENET_PHY_XTALVDDH

MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

NC_BCM57765_CE_L_MS_INS_L

NO_TEST=TRUE

PP3V3_S3_ENET_PHY_AVDDH

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V2_ENET_PHY_AVDDL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=1.8V

PP3V3R1V8_ENET_LR_OUT_REG

MIN_NECK_WIDTH=0.2 mm

ENET_CR_DATA<6>

TP_BCM57765_TRAFFICLED_L

BCM57765_MISO

BCM57765_SCLK

BCM57765_SMB_DATA

BCM57765_SMB_CLK

PP1V2_ENET_PHY_PCIEPLL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

PP1V2_ENET_PHY_GPHYPLL

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

ENET_CR_DETECT_L

ENET_CR_CMD

37 OF 86

39 OF 109

6

71

81

37

71

6 7

26 37 71 73

81

37

6 7

26 37 71 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 40 41 42 46 48

49 50 51 52 54 57 61 62 71 72

73 74 75 77 85

81

8

37

BI

RX

TX

BI

RX

TX

BI

IONCNC

IONCIO

IO

NC

GND

IONCNC

IONCIO

IO

NC

GND

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Page Notes

sides of the board

mirrored on opposite

BOM options provided by this page:

Signal aliases required by this page:

Transformers should be

Power aliases required by this page:

514-0636

(NONE)

Place one of 0.1uf cap close to each centertap pin of transformer

37 82

SM

CRITICAL

TLA-6T213HF

T4000

1

10

11

12

2

3

4

5

6 7

8

9

402

1/16W

5%

75

MF-LF

R4000

1

2

402

1/16W

5%

MF-LF

75

R4001

1

2

402

1/16W

5% MF-LF

75

R4002

1

2

402

1/16W MF-LF

75

5%

R4003

1

2

1000PF

CRITICAL

CERM 1206

2KV

10%

C4008

1 2

37 82

16V

0.1UF

10% X5R-CERM

0201

C4006

1

2

0.1UF

16V

10% X5R-CERM

0201

C4004

1

2

0.1UF

16V

10% X5R-CERM

0201

C4002

1

2

CRITICAL

SM

TLA-6T213HF

T4001

1

10

11

12

2

3

4

5

6 7

8

9

0.1UF

16V

10% X5R-CERM

0201

C4000

1

2

37 82

F-RT-TH

RJ45-M97-3

CRITICAL

J4000

1

10

11

12

2

3

4

5

6

7

8

9

SLP2510P8

CRITICAL

RCLAMP0524P

PLACE_NEAR=T4001.1:5mm

NOSTUFF

D4001

3

5 4 2 16 7 9

10

SLP2510P8

CRITICAL

RCLAMP0524P

PLACE_NEAR=T4000.5:5mm

NOSTUFF

D4000

3

5 4 2 16 7 9

10

37 82

Ethernet Connector

SYNC_MASTER=K91_MLB

SYNC_DATE=05/26/2010

ENET_MDI_N<2>

ENET_MDI_P<2>

MIN_NECK_WIDTH=0.25 mm

ENET_BOB_SMITH_CAP

MIN_LINE_WIDTH=0.6 mm

ENET_CTAP2

ENETCONN_N<3>

ENET_CTAP3

ENET_MDI_N<3>

ENET_CTAP1

ENET_CTAP0

ENETCONN_CTAP

ENETCONN_N<2>

ENETCONN_P<3>

ENETCONN_P<2>

ENET_MDI_P<3>

ENETCONN_P<1>

ENETCONN_N<1>

ENET_MDI_P<1>

ENET_MDI_N<1>

ENET_MDI_N<0>

ENET_MDI_P<0>

ENETCONN_N<0>

ENETCONN_P<0>

40 OF 109

38 OF 86

85

DS2

ATBUSH ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620* JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK SCIFDAIN SCIFDOUT

SCIFMC

SCL SDA

SE SM

TDO

TPA1N

TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P

TPBIAS0 TPBIAS1 TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH

VP

VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33

VDD10

VREG_VSS

VSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NC NC NC

NC

IN IN

IN

OUT

IN IN IN

BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

IN

NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

135 mA

114 mA FireWire PHY

(IPD) NT-2

17 mA PCIe SerDes

0 mA VReg PWR

1394B physical plug detect.

(OD)

NT-12 (IPD)

(IPD)

(IPD) NT-1

(IPU)

(IPD) (IPD)

(IPD) NT-11

NT-15 (IPD)

NT-14 (IPD)

NT-16 (IPD)

(IPD) NT-4

(IPD) NT-3

138 mA

7 mA I/O

25 mA PCIe SerDes

NT-7 NT-6

NT-5

NT-OUT

(Reserved)

NT-9

(IPU) NT-8

NOTE: NT-xx notes show NAND tree order.

NT-17

(IPU)

NT-19 (IPU)

NT-10 (IPD)

FIXME!!! - TYPO IN SYMBOL REGCTL

NT-20 (IPU)

NT-21 (IPU)

NT-13

- TP (or NC) PME#

- Gate CLKREQ# based on PHY power

isolated for systems that use

NOTE: FW_PME_L and FW_CLKREQ_L are

- Alias both signals to drop = prefix

NT-18 (IPU)

WITH PLUG DETECT:

WITHOUT PLUG DETECT:

110 mA Digital Core

402

MF-LF

1/16W

1%

191

R4170

1

2

10%

402

6.3V

0.33UF

CERM-X5R

C4162

1

2

470K

MF-LF

402

5%

1/16W

R4162

1

2

FW643E

CRITICAL

BGA

OMIT

U4100

B13

A13

A11

A10

L13

L2

F12 E12

E13

D12

K13

D1

J2

K1

J12 J13

N8

N7

N5 N6

N4

B11

N9

N10

D13

L8

G2

G1 H1

F2

N12

M11

M13 N13

M4 N2

M1

M3

B8 A8

B5

A5 B3

A3

B9 A9

B6 A6

B4

A4

B7 C3

A2

B10

N1

E1

D2

H13

A1

B1

M12N3N11

B12

C13E2E10H2H12K2L1

C1

C12F1G12J1L3

L11M2A12D5D6D8L5

L10L6L9

K12

L12

B2

D4

F7

F8

F10

G4G6G7

G8

G10

H4

H6D7H7

H8

H10

J4J5J9

J10

K4K5K7D9K8K9L7

K6

K10

D10

E4E5E9F4F6

C2

G13

F13

402

50V

5%

22PF

CERM

C4151

1 2

402

CERM

22PF

5%

50V

C4150

1 2

402

1/16W MF-LF

200K

1%

R4160

1

2

412

MF-LF

1%

1/16W

402

R4150

1 2

402

1/16W

5%

MF-LF

10K

R4163

1

2

402

5%

MF-LF

10K

1/16W

R4164

1

2

402

10K

MF-LF

5%

1/16W

FW643_LDO

R4165

1

2

402

1/16W

5%

MF-LF

10K

R4166

1

2

10%

1UF

402

6.3V CERM

C4130

1

2

10%

1UF

402

6.3V CERM

C4131

1

2

10%

1UF

402

6.3V CERM

C4100

1

2

10%

1UF

402

6.3V CERM

C4101

1

2

10%

402

6.3V CERM

1UF

C4132

1

2

10%

1UF

6.3V CERM 402

C4102

1

2

10%

1UF

402

6.3V CERM

C4103

1

2

10%

1UF

402

6.3V CERM

C4135

1

2

10%

1UF

402

6.3V CERM

C4136

1

2

10%

1UF

402

6.3V CERM

C4104

1

2

10%

1UF

402

6.3V CERM

C4110

1

2

10%

1UF

402

6.3V CERM

C4105

1

2

10%

1UF

402

6.3V CERM

C4106

1

2

10%

1UF

402

6.3V CERM

C4120

1

2

402

10%

1UF

6.3V CERM

C4121

1

2

10%

1UF

402

6.3V CERM

C4122

1

2

10%

1UF

402

6.3V CERM

C4123

1

2

10%

1UF

402

6.3V CERM

C4124

1

2

0.1UF

10V

20%

CERM

402

C4141

1

2

10%

1UF

402

6.3V CERM

C4111

1

2

1UF

CERM

6.3V

402

10%

C4140

1

2

16 81

8

40

MF-LF

2.94K

402

1/16W

1%

R4161

1

2

41

41 82

6

41 82

6

41

6

41

6

41 82

6

41 82

6

41

6

41

40 41

6

41

120-OHM-0.3A-EMI

0402-LF

L4130

1 2

0402-LF

120-OHM-0.3A-EMI

L4135

1 2

40

120-OHM-0.3A-EMI

0402-LF

L4110

1 2

CRITICAL

SM-3.2X2.5MM

24.576MHZ

Y4150

2 4

1 3

PLACEMENT_NOTE=Place C4170 close to U1400

10% 402X5R16V

0.1UF

C4170

1 2

PLACEMENT_NOTE=Place C4171 close to U1400

10%

0.1UF

402X5R16V

C4171

1 2

PLACEMENT_NOTE=Place C4175 close to U4100

10%

0.1UF

402X5R16V

C4175

1 2

PLACEMENT_NOTE=Place C4176 close to U4100

10% 402X5R16V

0.1UF

C4176

1 2

SYNC_DATE=07/20/2009

SYNC_MASTER=T27_MLB

FireWire LLC/PHY (FW643E)

PP1V0_FW_FWPHY_AVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY_VP25

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY_VDDA

FW_PORT1_TPB_N

FW643_R0 FW643_TPCPS

FW_CLK24P576M_XO_R

PPVP_FW_CPS

NC_FW643_TCK NC_FW643_TDI

NC_FW643_VBUF

TP_FW643_JASI_EN

FW643_REXT

TP_FW643_SCIFDAIN

NC_FW643_TMS

FW643_TRST_L

FW643_WAKE_L FW643_REGCTL FW643_VAUX_DETECT TP_FW643_VAUX_ENABLE

FW643_SCL

FW_RESET_L

FW643_PU_RST_L

NC_FW0_TPAN NC_FW0_TPAP

NC_FW0_TPBP

FW_P1_TPBIAS

FWPHY_DS1

PP3V3_FW_FWPHY

FWPHY_DS0

FWPHY_DS2

NC_FW2_TPBIAS

NC_FW0_TPBIAS

NC_FW2_TPBP

NC_FW2_TPBN

FW_PORT1_TPB_P

NC_FW0_TPBN

NC_FW2_TPAP

NC_FW2_TPAN

FW_PORT1_TPA_N FW_PORT1_TPA_P

TP_FW643_TDO

NC_FW643_SM

TP_FW643_SE

NC_FW643_SDA

TP_FW643_SCIFDOUT

PCIE_CLK100M_FW_P

TP_FW643_NAND_TREE

TP_FW643_MODE_A

NC_FW643_FW620_L

TP_FW643_CE

NC_FW643_AVREG

PCIE_CLK100M_FW_N

NC_FW643_OCR10_CTL

FW_CLK24P576M_XO

TP_FW643_SCIFMC

FW_CLKREQ_PHY_L

TP_FW643_SCIFCLK

PCIE_FW_R2D_P

PCIE_FW_R2D_C_P

PCIE_FW_R2D_N

PCIE_FW_R2D_C_N

PCIE_FW_D2R_C_N

PCIE_FW_D2R_N

PCIE_FW_D2R_C_P

PCIE_FW_D2R_P

FW_CLK24P576M_XI

PP3V3_FW_FWPHY

PP1V0_FW_FWPHY

41 OF 109

39 OF 86

41

6

7

39 40 41

6

81

7

39 40 41

7

40

G

D

S

IN

G

D

S

OUT

IN

S

G

D

(SYM-VER2)

G

S

(SYM-VER1)

D

GND

VOUT

ON

VIN

GND

VOUT

ON

VIN

IN

OUT

IN

OUT

IN

D

G S

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DLY = 60 ms +/- 20%

3.3V FW Switch

Supervisor & CLKREQ# Isolation

Pull-up provided by another page.

TEXT NOTE FOR 3.3V RAIL CURRENT CHANGED TO EDP NUMBER.

EDP = 0.14A (85C)

When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.

FireWire PHY WAKE# Support

1.0V FW Switch

U4201 & U4202

Type

to reduce voltage.

TPS22924C

18 mOhm Typ

R(on)

Max Output: 2A

Part

Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)

- =PP3V3_S0_FWPWRCTL

- =PP1V0_FW_FWPHY (PHY 1.0V)

BOM options provided by this page:

- =PP1V05_FW_P1V0FWFET (1.0V FET Input)

- =PP3V3_FW_P3V3FWFET (3.3V FET Input)

- =PP3V3_FW_FET (3.3V FET Output)

- =PP3V3_FW_FWPHY (PHY 3.3V Power)

- =PP1V05_S0_FWPWRCTL (5KPD Bias Rail)

(NONE)

- =PP1V0_FW_FET_R (1.0V FET Output)

- =PP3V3_S0_FWLATEVG

Page Notes

Power aliases required by this page:

- =PPBUS_S5_FWPWRSW (FW VP FET Input)

- =PPBUS_FW_FET (FW VP FET Output)

Current source only active when FW_PWR_EN is low.

All FireWire devices require 5K pull-down on TPB pair. Host can detect as load on TPBIAS signal.

FireWire Port 5K Pull-Down Detect

Dual-purpose output:

1) 5K Pull-down Detect when FW_PWR_EN is low.

Pull-up provided on another page.

- =FW_PME_L

- =FW_CLKREQ_L

Signal aliases required by this page:

2) FW643 WAKE# (PME#) when PHY is powered.

FireWire Port Power Switch

50 mOhm Max

Load Switch

1.05V is used with a series R

To avoid an extra power supply,

LSI FireWire PHY requires 1.0V.

402

25V X5R

10%

0.1UF

C4260

1

2

1/16W

5%

402

MF-LF

300K

R4260

1

2

470K

1/16W

5%

402

MF-LF

R4261

1

2

1.1A-24V

MINISMDC110H24

CRITICAL

F4260

1 2

CRITICAL

CRS08-1.5A-30V

SM

D4260

1 2

CRITICAL

SOT563

BC847CDXV6TXG

Q4270

2

6

1

SOT563

BC847CDXV6TXG

CRITICAL

Q4270

5

3

4

MF-LF

5%

402

1/16W

330K

R4270

1

2

56K

MF-LF

402

5%

1/16W

R4271

1

2

5% 1/16W MF-LF

402

12K

R4273

1

2

PLACE_NEAR=C4360.1:2 mm

MF-LF

402

5%

1K

1/16W

R4272

1

2

CRITICAL

DMB53D0UV

SOT-563

Q4275

6

2

1

CRITICAL

SOT-563

DMB53D0UV

Q4275

5

3

4

10%

0.1UF

402

X5R

16V

C4270

1

2

39 41

1/16W MF-LF

5%

1K

402

R4275

1

2

19 40

DMB53D0UV

SOT-563

CRITICAL

Q4276

5

3

4

CRITICAL

DMB53D0UV

SOT-563

Q4276

6

2

1

5% 1/16W MF-LF 402

100K

R4276

1

2

NO STUFF

0.1UF

10% 16V X5R 402

C4276

1

2

MF-LF

5%

1/16W

402

10K

R4277

1

2

8

19

8

39 40

SOT-363

BSS8402DW

Q4262

3

5

4

402

1/16W

5%

MF-LF

10K

R4262

1

2

BSS8402DW

SOT-363

Q4262

6

2

1

402

25V X5R

10%

0.1UF

NO STUFF

C4261

1

2

10

5% 1/16W MF-LF

402

R4263

1

2

TPS22924

CRITICAL

CSP

U4201

C1

C2

A2 B2

A1 B1

TPS22924

CRITICAL

CSP

U4202

C1

C2

A2 B2

A1 B1

41

402

MF

1/16W

1%

0.549

R4202

1

2

39

1/16W 402

MF-LF

5%

10K

R4283

2

1

19 40

16 23

402

25V X5R

10%

0.1UF

C4290

1

2

18 26 30 33 36

39 40

FDC638P_G

SM

CRITICAL

Q4260

1

2

5

6

3

4

SOD-VESM-HF

SSM3K15FV

Q4261

3

1

2

402

CERM

6.3V

10%

1UF

C4201

1

2

402

CERM

6.3V

10%

1UF

C4202

1

2

CRITICAL

SLG4AP016V

TDFN

U4290

6

5

7

3

8

4

2

9

1

1/16W MF-LF 402

5%

100K

R4290

1

2

SYNC_MASTER=T27_MLB

SYNC_DATE=12/15/2009

FireWire Port & PHY Power

MAKE_BASE=TRUE

FW_5KPD_DET_L

PP1V05_FW_FET

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MAKE_BASE=TRUE

FW643_WAKE_L

MIN_NECK_WIDTH=0.25 mm

PPBUS_FW_FWPWRSW_F

MIN_LINE_WIDTH=0.5 mm VOLTAGE=12.6V VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

PPBUS_FW_FWPWRSW_D

MIN_LINE_WIDTH=0.5 mm

FW_CLKREQ_PHY_L

MAKE_BASE=TRUE

PP1V05_S0

PP3V3_S0

PP1V0_FW_FWPHY

PPVP_FW

FWDET_MIRROR

FW_PWR_EN_L

FWDET_EMIT

FW_P1_TPBIAS_R

PP1V05_S0

FW_5KPD_DET_RC

PP3V3_FW_FWPHY

FW_WAKE

FW_P1_TPBIAS

FW_PWR_EN

FW_PLUG_DET_L

FW643_WAKE_L

FWPORT_PWREN_L_DIV

FWPORT_FASTOFF_L

PP3V3_S0

PPBUS_G3H

FWPORT_FASTOFF_L_DIV

FWPORT_PWREN_L

FWPORT_PWR_EN

PP3V3_FW_FWPHY

FW_CLKREQ_PHY_L

PP1V0_FW_FWPHY

PP3V3_S0

FW_RESET_R_L

PLT_RESET_L

FW_CLKREQ_L

FW_PWR_EN

FW_RESET_L

42 OF 109

40 OF 86

39 40

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 70 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

7

39 40

7

41

6 7 9

10 12 14 16 17

20 22 23 36 40 45 68 70

73

7

39 40 41

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 8

36 49 50 63 64 77

7

39 40 41

7

39 40

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

SC/NC

TPA+

TPA(R)

VG

VPTPB+

TPB(R)

TPB-

TPA-

CHASSIS

GND

SGD

(SYM-VER2)

G

S

(SYM-VER1)

D

NC

VCC

VCLMP

D1-

GND

D2-

D2+

D1+

FWPWR_EN

OUT

BI

IN

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AREF needs to be isolated from all local grounds per 1394b spec

When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue)

- =FW_PHY_DS0

NOTE: This page is expected to contain

appropriate connectors and/or to

(PINS 5/6 AND 7/8 ARE

SWAPPED FOR BETTER ROUTING)

"Snapback" & "Late VG" Protection

(FW_PORT1_TPA_N)

(FW_PORT1_TPB_P)

(FW_PORT1_TPA_P)

(FW_PORT1_TPB_P)

FireWire Design Guide (FWDG 0.6, 5/14/03)

Termination

Place close to FireWire PHY

(FW_PORT1_TPB_N)

(GND)

Cable Power

(FW_PORT1_TPB_N)

(FW_PORT1_TPA_P)

(FW_PORT1_TPA_N)

Note: Trace PPVP_FW_PORT1 must handle up to 5A

(FW_PORT1_BREF)

ground for speed signaling and connection

BREF should be hard-connected to logic

514S0605

TPA<R>

TPA+

TPA-

VG

BILINGUAL

TPB+

VP

NC

TPB<R>

TPB-

INPUT

OUTPUT

PORT 1

1394b implementation based on Apple

(NONE)

BOM options provided by this page:

- =FW_PHY_DS2

- =FW_PHY_DS1

- =PP3V3_FW_FWPHY

- =PP3V3_S0_FWLATEVG

- =PPVP_FW_PHY_CPS (To PHY)

From Port

To FW643

- =PPVP_FW_PORT1 FET blocks current to TPCPS until VDD33 is powered.

FW643 TPCPS Leakage Protection

(All unused port signals TP/NC)

Disabled per LSI instructions

Unused FireWire Ports

- Port "1" Bilingual (1394B)

Configures PHY for:

FireWire PHY Config Straps

properly terminate unused signals.

the necessary aliases to map the

Signal aliases required by this page:

- =PPVP_FW_PHY_CPS_FET (From Port)

Page Notes

Power aliases required by this page:

FireWire TPA/TPB pairs to their

FW643 has internal leakage path from TPCPS pin to VDD33.

CANNOT SYNC THIS PAGE FROM T27, TPA AND TPB FOR U4350 IS SWAPPED

SIGNAL_MODEL=EMPTY

56.2

MF-LF

402

1%

1/16W

R4363

1

2

4.99K

MF-LF

402

1%

1/16W

R4364

1

2

1/16W

1%

402

MF-LF

56.2

SIGNAL_MODEL=EMPTY

R4362

1

2

5%

402

CERM

220pF

25V

C4364

1

2

1%

SIGNAL_MODEL=EMPTY

1/16W

402

MF-LF

56.2

R4361

1

2

6.3V

10%

402

CERM-X5R

0.33UF

C4360

1

2

1/16W

SIGNAL_MODEL=EMPTY

56.2

MF-LF 402

1%

R4360

1

2

0.1uF

X7R

603-1

10% 50V

PLACE_NEAR=J4310.5:2 mm

C4319

1

2

1/16W

5%

402

1M

MF-LF

R4319

1

2

0.01UF

X7R 402

10% 50V

C4314

1

2

CRITICAL

SM

FERR-250-OHM

L4310

1 2

CRITICAL

1394B-M97

F-RT-TH

J4310

1

10 11

12

13

2

3

4

5

6

7

8

9

1/16W

1%

402

MF-LF

10K

R4381

1

2

10K

MF-LF

402

1%

1/16W

R4382

1

2

1/16W

1%

402

MF-LF

10K

R4380

1

2

BSS8402DW

SOT-363

Q4300

3

5

4

BSS8402DW

SOT-363

Q4300

6

2

1

330K

MF-LF

402

5%

1/16W

R4312

1

2

470K

MF-LF

402

5%

1/16W

R4311

1

2

TPD4S1394

LLP

CRITICAL

U4350

7

8

5

6

4

2 1

3

PLACE_NEAR=U4350.1:2 mm

402

10%

X5R

16V

0.1UF

C4350

1

2

1/16W

100K

5%

MF-LF

402

R4350

1

2

40

39 41

6

39 41 82

6

39 41 82

6

39 41 82

6

39 41

6

39 41

6

39 41

6

39 41

6

39 41

39 41 82

39 40

SYNC_MASTER=T27_MLB

SYNC_DATE=07/28/2009

FireWire Connector

MAKE_BASE=TRUE

FW_PORT1_TPB_P

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FWPHY_DS0

MAKE_BASE=TRUE

FWPHY_DS2

MAKE_BASE=TRUE

FWPHY_DS1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW0_TPBIAS

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW0_TPAP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW0_TPAN

NO_TEST=TRUE

NC_FW0_TPBP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW0_TPBN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW2_TPBIAS

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW2_TPAP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW2_TPAN

NO_TEST=TRUE

NC_FW2_TPBP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW2_TPBN

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE

PPVP_FW_CPS

PPVP_FW_PORT1_F

VOLTAGE=33V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVP_FW

PP3V3_FW_FWPHY

FWPHY_DS0

FWPHY_DS2

FWPHY_DS1

NC_FW0_TPBIAS

NC_FW0_TPBP

NC_FW0_TPAN

NC_FW0_TPAP

NC_FW2_TPBIAS

NC_FW2_TPAP

NC_FW0_TPBN

NC_FW2_TPBN

NC_FW2_TPBP

NC_FW2_TPAN

CPS_EN_L

PP3V3_FW_FWPHY

CPS_EN_L_DIV

PPVP_FW_CPS

PPVP_FW

FW_PORT1_TPB_C

FW_PORT1_TPA_P

FW_PORT1_TPA_N

FW_PORT1_TPB_P

FW_PORT1_TPB_N

FW_P1_TPBIAS

TP_FWLATEVG_VCLMP

FWPORT_PWR_EN

PP3V3_S0

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_AREF

FW_PORT1_TPB_N

MAKE_BASE=TRUE

43 OF 109

41 OF 86

39

41 82

39

41 82

39 41

39

41

39 41

6

39 41 82

6

39 41 82

6

39 41 82

6

39 41

6

39 41

6

39 41

6

39 41

6

39 41

7

40 41

7

39 40 41

7

39 40 41

39 41

7

40 41

6 7 8

12 16 17 18

19 20 22 23 26 27 29 33

36 37 40 42 46 48 49 50

51 52 54 57 61 62 71 72

73 74 75 77 85

39

41 82

39

41 82

S

G

D

OUT

IN

OUT

IN

BI

IN

EN

A_INN

A_INP

TEST

B_PRE0/I2C_ADDR0

APRE0/I2C_ADDR1

I2C_EN*

A_OUTP

B_INN

A_OUTN

B_INP

REXT

B_PRE1/SDA_CTL

A_PRE1/SCL_CTL

VDD

THRM

GND

B_OUTP

B_OUTN

PAD

IN

NC

D

SG

D

SG

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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PAGE TITLE

C

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D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SATA HDD / IR / SIL Connector

SATA ODD Connector

ODD Power Control

ensure the drive is unpowered in S3/S5.

Indicates disc presence

(All 4 C’s)

338S0907

Internally PD ~150K

Address (W/R)

0x96/0x97 0x98/0x99 0xB6/0xB7 0xB8/0xB9

Write:0xB6 Read:0xB7

ADDR1

H H

L H

HL

L

ADD0

L

516S0687

NOTE: 3.3V must be S0 if 5V is S3 or S5 to

516S0616

R2D values for 3dB de-emphasis

D2R values for 3dB de-emphasis

CRITICAL

TPCP8102

23V1K-SM

Q4590

5 6 7 8

4

1 2 3

0.01UF

10%

CERM

40216V

C4525

1 2

10% 402

CERM

0.01UF

16V

C4526

1 2

402

CERM

16V10%

0.01UF

C4520

1 2

40216V

CERM

10%

0.01UF

C4521

1 2

16 80

6

45

1/16W

5%

33K

402

MF-LF

R4590

1

2

F-ST-SM

54722-0164

CRITICAL

J4500

1

10

1112

1314

1516

2

34

56

78

9

16 80

16 23 27 29 31 48 62 77 81

4.7K

402

1/16W MF-LF

5%

R4515

1

2

1/16W MF-LF

5%

402

4.7K

NO STUFF

R4513

1

2

GND_VOID=TRUE

402

CERM

10% 16V

0.01UF

C4518

1 2

GND_VOID=TRUE

402

0.01UF

CERM

10% 16V

C4517

1 2

GND_VOID=TRUE

0.01UF

40216V10%

CERM

C4513

1 2

GND_VOID=TRUE

40216V10%

CERM

0.01UF

C4512

1 2

19

16V

20%

CERM 402

0.01UF

C4519

1

2

402

20% 10V CERM

0.1UF

C4514

1

2

MF-LF

402

1%

4.99K

1/16W

R4512

1

2

MF-LF

5%

1/16W

402

4.7K

NO STUFF

R4510

1

2

PLACE_SIDE=TOP

TQFN

PS8521A

CRITICAL

U4510

2

1

14

15

19

9

12 11

4 5

8

17

7

3

13

10

20

18

21

6

16

5% 1/16W

0

402

MF-LF

R4511

1

2

10%

0.01UF

GND_VOID=TRUE

16V

CERM

402

C4516

1 2

GND_VOID=TRUE

0.01UF

CERM

16V 40210%

C4515

1 2

16 23

16V10%

CERM

402

GND_VOID=TRUE

0.01UF

C4510

1 2

0.01UF

402

CERM

10% 16V

GND_VOID=TRUE

C4511

1 2

CERM

0.1UF

10V

402

PLACE_NEAR=L4500.2:2mm

20%

C4502

2

1

FERR-70-OHM-4A

0603

CRITICAL

PLACE_NEAR=J4501.9:3mm

L4500

1 2

402

CERM

10V

PLACE_NEAR=L4500.1:2mm

0.1UF

20%

C4501

2

1

50V

0.001UF

402

CERM

10%

C4531

1

2

402

4.7

5%

MF-LF

1/16W

R4531

12

F-ST-SM

54722-0224

CRITICAL

J4501

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

3 4

5 6

7 8

9

10% 16V X7R-CERM

0.1UF

402

C4532

1

2

10

MF-LF

1/16W

5%

402

R4532

12

402

1/16W

MF-LF

GND_VOID=TRUE

41.2

1%

R4534

1 2

402

CERM

50V

5%

GND_VOID=TRUE

15PF

C4534

1 2

402

GND_VOID=TRUE

1/16W

MF-LF

41.2

1%

R4533

1 2

402 50V

CERM 5%

GND_VOID=TRUE

15PF

C4533

1 2

5%

GND_VOID=TRUE

402

CERM

50V

15PF

C4536

1 2

GND_VOID=TRUE

402

MF-LF

1/16W

1%

41.2

R4536

1 2

MF-LF

GND_VOID=TRUE

402

1/16W

41.2

1%

R4535

1 2

402

CERM

50V

GND_VOID=TRUE

5%

15PF

C4535

1 2

SOT563

SSM6N37FEAPE

Q4596

3

5

4

402

100K

5%

MF-LF

1/16W

R4597

1

2

SOT563

SSM6N37FEAPE

Q4596

6

2

1

402

1/16W

5%

MF-LF

100K

R4596

1

2

1/16W

402

MF-LF

100K

5%

R4595

1 2

10V

10%

402

0.068UF

CERM

C4595

1

2

16V

10%

CERM

402

0.01UF

C4596

1 2

SATA/IR/SIL Connectors

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

PP5V_S0_HDD_FLT

SATA_HDD_D2R_RC_P

SATA_HDD_D2R_RC_N

SATARDRVR_I2C_ADDR1

SATARDRVR_TEST

SATA_HDD_R2D_N

SATARDRVR_REXT

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SATA_HDD_R2D_RDRVR_IN_P

ODD_PWR_EN

MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

MIN_LINE_WIDTH=0.6mm

PP5V_SW_ODD

SATARDRVR_I2C_EN_L

SATA_HDD_R2D_RDRVR_IN_N

SATA_HDD_R2D_C_P

SATA_HDD_D2R_N

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

ODD_PWR_SS

PP3V3_S0

SATA_ODD_R2D_P

SATA_ODD_D2R_UF_P

SYS_LED_ANODE_R

MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm VOLTAGE=5V

PP5V_S3_IR_R

IR_RX_OUT

SYS_LED_ANODE

PP5V_S3

SATA_HDD_D2R_RDRVR_OUT_N

SATA_ODD_R2D_N

SATARDRVR_I2C_ADDR0

SATARDRVR_I2C_ADDR1

PP1V5_S0

ODD_PWR_EN_LS5V_L

PP5V_S3

SATA_ODD_D2R_UF_N

SATA_HDD_D2R_RDRVR_OUT_P

PP1V5_S0

SMC_ODD_DETECT

ODD_PWR_EN_L

PP5V_S0

SATA_HDD_D2R_RDRVR_IN_N

SATA_HDD_R2D_RDRVR_OUT_N

SATA_HDD_D2R_C_P

SATARDRVR_I2C_ADDR0

SATARDRVR_EN

SATA_HDD_R2D_RC_P

SATA_HDD_R2D_RC_N

SATA_HDD_R2D_RDRVR_OUT_P

SATA_HDD_D2R_RDRVR_IN_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_P

45 OF 109

42 OF 86

6

80

42

6

80

85

6

85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62

71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6

80

6

85

6

44

46

6 7

30 32 42 43 44 46 57 59

60 61 66 67 72

85

6

80

42

7

16 20 22 26 42 57 71

6 7

30 32 42 43 44 46 57 59

60 61 66 67 72

6

85

7

16 20 22 26 42 57 71

7

16 20 22 26 42 57 71

6 7

22 47 52 54 65 68 70 72 73

77

85

6

80

42

80

85

6

80

6

80

OUT

BI

SYM_VER-1

IN OUT

IN

SYM_VER-1

BI

OUT

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

GND

THRM

OUT2

OUT1

ILIM

IN_0 IN_1

EN2

FAULT1* FAULT2*

EN1

PAD

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

USB Port Power Switch

Left USB Port A

Left USB Port B

We can add protection to 5V if we want, but leaving NC for now

Place L4605 and L4615 at connector pin

SEL=0 Choose SMC

USB/SMC Debug Mux

SEL=1 Choose USB

Current limit per port (R4600): 2.18A min / 2.63A max

CRITICAL

FERR-120-OHM-3A

0603

L4605

1 2

10UF

6.3V X5R 603

20%

C4695

1

2

402

CERM

10V

20%

0.1UF

C4691

1

2

24

24 80

CERM

402

10V

0.1UF

SMC_DEBUG_YES

20%

C4650

1

2

SMC_DEBUG_YES

MF-LF

5%

10K

402

1/16W

R4650

1

2

CRITICAL

DLP11S

90-OHM-100MA

L4600

1 2

34

6

45 46 47

6

45 46 47

45

1/16W MF-LF

0

5%

402

SMC_DEBUG_NO

R4651

1 2

SMC_DEBUG_NO

0

402

5% 1/16W MF-LF

R4652

1 2

16V

402

0.01uF

CERM

20%

C4605

1

2

20%

0.01uF

16V

CERM

402

C4615

1

2

CRITICAL

FERR-120-OHM-3A

0603

L4615

1 2

DLP11S

CRITICAL

90-OHM-100MA

L4610

1 2

34

20%

603

10UF

X5R

6.3V

C4617

1

2

24 80

24

RCLAMP0502N

CRITICAL

SLP1210N6

D4600

1

5 42 3

6

SLP1210N6

RCLAMP0502N

CRITICAL

D4610

1

5 42 3

6

603

10UF

X5R

6.3V

20%

C4690

1

2

F-RT-TH-M97-4

CRITICAL

USB

J4600

1

2

3

4

5

6

7

8

F-RT-TH-M97-4

CRITICAL

USB

J4610

1

2

3

4

5

6

7

8

SON

TPS2561DR

CRITICAL

U4600

4 5

10

6

1

7

2

3

9

8

11

SMC_DEBUG_YES

TQFN

CRITICAL

PI3USB102ZLE

U4650

6

7

3

4

5

8

10

9

2

1

402

MF-LF

1/16W

1%

23.2K

R4600

1

2

CRITICAL

220UF-35MOHM

POLY-TANT

6.3V

20%

CASE-B2-SM

C4696

1

2

External USB Connectors

SYNC_DATE=06/01/2010

SYNC_MASTER=K91_MLB

PP5V_S3

USB_EXTA_OC_L

MIN_NECK_WIDTH=0.375 mm

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

VOLTAGE=5V

PP5V_S3_RTUSB_B_F

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm

USB2_LT1_P

USB2_LT1_N

USB_ILIM

USB_DEBUGPRT_EN_L

PP3V42_G3H

USB_EXTB_N

USB_LT2_N

USB_EXTB_P

USB_LT2_P

USB_EXTA_N

USB_EXTA_P

VOLTAGE=5V

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_RTUSB_B_ILIM

SMC_RX_L

PP5V_S3_RTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

MIN_NECK_WIDTH=0.375 mm

DDRREG_EN

USB_EXTB_OC_L

USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_P

SMC_TX_L

46 OF 109

43 OF 86

6 7

30 32 42 44 46 57 59 60

61 66 67 72

85

6 7

26 45 46 47

48 53 63 64 73

85

67 73

85

BI BI

VCC

P1.0/D+ P1.1/DP1.2/VREG P1.3/SSEL P1.4/SCLK

P1.5/SMOSI

P1.6/SMISO

P0.0

P0.1 INT0/P0.2 INT1/P0.3

TIO1/P0.6

NC

TIO0/P0.5

INT2/P0.4

VSSPAD

THRML

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

IR SUPPORT

24 80

1UF

X5R 402-1

10% 10V

C4803

1

2

CY7C63803-LQXC

QFN

OMIT

CRITICAL

U4800

5

4

3

8

9 10

20

21 22

23 24

7

6

12

13 15

16

17 18

19

25

2

1

14

11

X7R-CERM

10%

0.1UF

402

16V

C4801

1

2

0.001UF

CERM 402

10% 50V

C4804

1

2

100

MF-LF

402

5%

1/16W

R4800

1 2

6

42

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

Front Flex Support

USB_IR_P

DIFFERENTIAL_PAIR=USB2_IR

USB_IR_N

DIFFERENTIAL_PAIR=USB2_IR

IR_RX_OUT_RC

IR_RX_OUT

IR_VREF_FILTER

PP5V_S3

48 OF 109

P/N 338S0633

44 OF 86

6 7

30 32 42 43 46 57 59 60

61 66 67 72

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

BI BI BI BI BI BI

OUT OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

IN

OUT

P11

P82 P83

P35

P96

P95

P94

P93

P92

P91

P90

P86

P85

P84

P81

P80

P77

P67

P52

P51

P50

P47

P46

P45

P44

P43

P42

P41

P40

P37

P36

P34

P33

P32

P31

P30

P27

P26

P25

P24

P23

P21

P17

P12

P66P16

P15

P14

P13

P22

P20

P63

P61

P60

P65

P64

P62

P70 P71 P72 P73 P74 P75 P76

P97

P10

(1 OF 3)

PEVREF/PH4

PECI/PH3

PH2

PG5

PG4

PG3

PG2

PG1

PG0

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

PE4

PE3

PE2

PE1

PE0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PA7

PA6

PA3

PA2

PA1

PA0

PA4 PA5

PG6 PG7

PH0 PH1

PEVSTP/PH5

(2 OF 3)

EXTAL

XTAL

RES*

VSS

AVSS

ETRST*

NMI

MD2

MD1

NC

AVCC

VCC

VCL

AVREF

(3 OF 3)

OUT

NC

INBI

OUT

IN

OUT

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(OC)

NOTE: Unused pins have "SMC_Pxx" names. Unused

(OC)

(OC) (OC) (OC) (OC) (OC)

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

pins designed as outputs can be left floating,

(OC)

those designated as inputs require pull-ups.

(OC)

6.3V

20%

805

CERM

22UF

C4902

1

2

6

17 47

46 47 64

46 53

PLACE_NEAR=U4900.E1:3mm

6.3V

10%

402

CERM-X5R

0.47UF

C4907

1

2

0.1UF

CERM

10V

20%

402

C4903

1

2

PLACE_NEAR=U4900.M12:3mm

0.1UF

CERM

402

20% 10V

C4920

1

2

PLACE_NEAR=U4900.M12:3mm

402

1/16W

5%

MF-LF

4.7

R4999

1 2

10V

20%

402

CERM

0.1UF

C4904

1

2

SM

PLACE_NEAR=U4900.L3:4mm

XW4900

12

17 23

26 36

10V

20%

402

CERM

0.1UF

C4905

1

2

17

73

23 26 73

46

10V

20%

402

CERM

0.1UF

C4906

1

2

46 49

46

46 49

46

46 49

46 49 63 64

6

43 45 46 47

6

43 45 46 47

6

73

48 84

402

1/16W

5%

MF-LF

10K

R4909

1

2

47

6

47

1/16W

5%

402

MF-LF

10K

R4901

1

2

1/16W

5%

402

MF-LF

10K

R4902

1

2

NO STUFF

0

MF-LF 402

5% 1/16W

R4903

1

2

1/16W

5%

MF-LF

10K

402

R4998

1

2

43

63

46 73

6

42

46

52

46

52

46

46 49

46 50

46

46 50

6

46 47

46

6

46 47

6

46 47

6

46 47

46 53 63

6

48 63 64 84

6

48 63 64 84

6

32 48 54 55 84

6

32 48 54 55 84

48 51 84

46

46 49

6

43 45 46 47

6

43 45 46 47

46 55

46

6

16 47

27 29

17 26

6

47

16 19

6

17 47

46

17 46 73

6

46 63

46

TLP-145V

OMIT

DF2117RVPLP20HV

U4900

B12

A13 A12

B13 D11

C13

C12 D10

D13

E11

D12 F11

E13 E12

F13

E10

A9 D9

C8

B7 A8

D8

D7 D6

D4

A5 B4

A1

C2 B2

C1

C3

G2 F3

E4

L13

K12 K11

J12 K13

J10

J11 H12

N10

M11

L10 N11

N12 M13

N13

L12

A7 B6

C7

D5 A6

B5

C6

J4

G3

H2 G1

H4

G4 F4

F1

OMIT

TLP-145V

DF2117RVPLP20HV

U4900

N3

N1

M3 M2

N2 L1

K3

L2

B8 C9

B9

A10 C10

B10

C11 A11

G11

G13 F12

H13

G10 G12

H11

J13

M10

N9

K10

L8

M9

N8 K9

L7

K1

J3

K2 J1

K4

A4 B3

C4

K5

N5

M6

L5 M5

N4

L4 M4

M8

N7 K8

K7

K6 N6

M7

L6

E2 F2

J2

TLP-145V

DF2117RVPLP20HV

OMIT

U4900

M12

L11

L9

H3

A2

D1 H1

E5

E3

D3

B1M1H10

E1

D2

L3

F10

B11

C5

A3

16

46 32 46

402

5%

MF-LF

1/16W

43

R4910

1 2

0

1/16W MF-LF

5%

402

R4911

1 2

1/16W

5%

MF-LF

0

402

R4912

1 2

10V

CERM

0.1UF

20%

402

C4910

1

2

8

46 73 76

46 53

19 46

6

16 47 81

6

16 47 81

6

16 47 81

6

16 47 81

6

16 47 81

26

26 81

54

6

32 48 51 84

6

17 30 73

6

17 30 73

17 73

46

6

32 48 51 84

48 84

46

SMC

SYNC_MASTER=LINDA_K90I

SYNC_DATE=07/07/2010

SMS_INT_L

PM_SYSRST_L

SMC_GFX_OVERTEMP_L

SMC_FAN_0_CTL

SMC_FAN_0_TACH

NC_SMC_FAN_3_TACH

PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L SMBUS_SMC_MGMT_SCL

SMC_BC_ACOK SMC_PME_S4_WAKE_L PM_SLP_S3_L

PM_SLP_S5_L

PM_SLP_S4_L

SMBUS_SMC_0_S0_SDA

PP1V05_S0

PM_PECI_PWRGD

TP_SMC_PF5

SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL

PVCCIO_S0_SMC_R

SMBUS_SMC_A_S3_SCL

SMC_SYS_LED

SMC_ADAPTER_EN

SMC_OTHER_HI_ISENSE

CPU_PECI

PP3V3_S5_AVREF_SMC

SMC_VCL

PP3V42_G3H

SMC_MD1

SMC_KBC_MDE

SMC_NMI

SMC_TRST_L

SMC_RESET_L

SMC_XTAL SMC_EXTAL

TP_SMC_P41

LPC_AD<3>

LPC_CLK33M_SMC

SMBUS_SMC_MGMT_SDA

TP_SMC_P43

TP_SMC_GFX_THROTTLE_L SMC_SYS_KBDLED

PM_PECI_PWRGD_R

CPU_PECI_R

SMC_THRMTRIP

SMC_PROCHOT

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_A_S3_SDA

SMC_LID

G3_POWERON_L

SMC_TDO

SMC_TCK

SMC_CASE_OPEN

TP_SMC_ADC3

SMC_PROCHOT_3_3_L

SMC_LRESET_L

LPC_SERIRQ

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=3.3V

PP3V3_S5_SMC_AVCC

MIN_NECK_WIDTH=0.1 MM

SMC_TDI

SMBUS_SMC_B_S0_SCL

SMC_PM_G2_EN

TP_SMC_P1V5S3_ISENSE

TP_SMC_P10 TP_SMC_RSTGATE_L ALL_SYS_PWRGD

PM_DSW_PWRGD

NC_SMC_FAN_2_CTL

SMC_TMS

SMC_GFX_VSENSE SMC_GFX_ISENSE

NC_SMC_FAN_1_CTL

SMC_ONOFF_L

TP_SMC_P24

SMC_BMON_MUX_SEL

LPC_FRAME_L

LPC_AD<2>

PM_PWRBTN_L

LPC_AD<1>

LPC_AD<0>

SMC_DELAYED_PWRGD

S5_PWRGD

TP_SMC_P20

NC_SMC_FAN_3_CTL

WIFI_EVENT_L

SMC_CPUVCCIO_ISENSE

SMC_SCI_L

SMC_BIL_BUTTON_L

SMC_CPU_VSENSE SMC_CPU_ISENSE TP_SMC_ADC2

GND_SMC_AVSS

SMC_CLK32K

SMBUS_SMC_0_S0_SCL

SMC_RX_L

SMC_TX_L

TP_SMC_ADC14

SMC_CPU_HI_ISENSE

SMC_BMON_ISENSE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_DCIN_VSENSE

TP_SMC_SA_ISENSE

NC_SMC_FAN_2_TACH

NC_SMC_FAN_1_TACH

SMC_S4_WAKESRC_EN

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

SMC_DP_HPD_L

SYS_ONEWIRE

MEM_EVENT_L

USB_DEBUGPRT_EN_L

SPI_DESCRIPTOR_OVERRIDE_L

SMC_PA0_PU

SMC_PB4

SMC_BATLOW_L

49 OF 109

45 OF 86

6 7 9

10 12 14 16 17 20 22 23

36 40 68 70 73

73

46

10 19 78

46

6 7

26 43 46 47 48 53 63 64

73

46

46 50

46

46 49 50

46

D

S G

IN

OUT

BI

IN

D

S G

IN

E

Q2

C

BD

Q1

GS

OUT

G

D

S

OUT

IN

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

OUT

IN

OUT

IN

OUT

D

G S

IN

OUT

D

GS

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BATLOW# Isolation

confirm if K90 needs Isense on DDR rail

Desktops: 5V Mobiles: 3.42V

SMC Crystal Circuit

TO SMC

SMC FSB to 3.3V Level Shifting

(IPU)

MR1* and MR2* must both be low to cause manual reset.

(IPU)

NOTE: Internal pull-ups are to VIN, not V+.

Used on mobiles to support SMC reset via keyboard.

System (Sleep) LED Circuit

Debug Power "Buttons"

TO CPU

SMC Reset "Button", Supervisor & AVREF Supply

Below connections are different from K91

Internal 20K pull-up on PM_BATLOW_L in PCH.

SOT563

SSM6N37FEAPE

Q5059

3

5

4

MF-LF

10K

402

5%

1/16W

R5070

1 2

100K

MF-LF1/16W

5%

402

R5071

1 2

5%

402

10K

MF-LF1/16W

R5073

1 2

1/16W

5%

402

MF-LF

100K

R5074

1 2

MF-LF

10K

402

5%

1/16W

R5077

1 2

10K

MF-LF

402

5%

1/16W

R5078

1 2

10K

402

MF-LF1/16W

5%

R5079

1 2

10K

MF-LF

402

5%

1/16W

R5080

1 2

1/16W

5%

402

10K

MF-LF

R5085

1 2

10K

5%

1/16W MF-LF

402

R5086

1 2

1/16W

5%

402

MF-LF

10K

R5088

1 2

45

19

PLACE_SIDE=TOP

5%

603

OMIT

0

MF-LF

1/10W

SILK_PART=PWR_BTN

R5015

1

2

1/16W

5%

402

MF-LF

3.3K

R5062

1 2

10 68 78

45

SOT563

SSM6N37FEAPE

Q5059

6

2

1

MF-LF

402

1/16W

5%

100K

R5091

1 2

MF-LF

402

10K

5%

1/16W

R5089

1 2

MF-LF

5%

1/16W

402

10K

R5081

1 2

0

MF-LF

402

5%

1/16W

R5010

1 2

5X3.2-SM

20.00MHZ

CRITICAL

Y5010

1

2

15pF

CERM

402

5%

50V

C5011

1 2

50V

CERM

15pF

402

5%

C5010

1 2

5%

402

MF-LF1/16W

470K

R5087

1 2

MF-LF

NOSTUFF

402

1/16W

5%

10K

R5093

1 2

10K

1/16W

402

MF-LF

5%

R5072

1 2

45

1.47K

MF-LF

402

1%

1/16W

R5032

1

2

402

523

MF-LF

1%

1/16W

R5031

1

2

1/16W MF-LF

20

402

1%

R5030

1

2

CRITICAL

DMB54D0UV

SOT-563

Q5030

5

3

6 4

21

42

SOT-563

DMB53D0UV

Q5060

5

3

4

100K

MF-LF 402

5% 1/16W

R5061

1

2

SOT-563

DMB53D0UV

Q5060

6

2

1

1/16W

5%

402

MF-LF

10K

R5060

1

2

45

PLACE_SIDE=BOTTOM

SILK_PART=PWR_BTN

0

5%

1/10W

603

MF-LF

OMIT

R5016

1

2

PLACEMENT_NOTE=Place R5001 on BOTTOM side

OMIT

0

MF-LF 603

5% 1/10W

SILK_PART=SMC_RST

R5001

1

2

45 46 53

53

CERM

402

10% 16V

0.01UF

C5001

1

2

CERM-X5R

402

10%

6.3V

0.47UF

C5020

1

2

VREF-3.3V-VDET-3.0V

DFN

U5010

4

2

6

7

8

5

9

1

3

603

6.3V X5R

20%

10uF

C5025

1

2

10% 16V CERM

0.01UF

402

C5026

1

2

1/16W MF-LF

5%

402

100K

R5000

1

2

45 47 64

17

1/16W MF-LF

402

5%

22

PLACE_NEAR=U1800.N14:5.1mm

R5012

1 2

45

MF-LF5%402

1/16W

10K

R5095

1 2

75

45

1/16W

5%

MF-LF 402

100K

R5020

1

2

SOD-VESM-HF

SSM3K15FV

Q5020

3

1

2

1/16W5%MF-LF

100K

402

R5090

1 2

1/16W

5%

MF-LF 402

100K

R5076

1

2

45 46 53 45 46 53

1/16W

1M

402

5%

MF-LF

NO STUFF

R5011

1

2

402

100K

5%

1/16W MF-LF

NOSTUFF

R5094

1 2

17

MF

1/20W

5%

100K

201

R5040

1

2

NOSTUFF

402

MF-LF

1/16W

5%

0

R5041

1 2

CRITICAL

SSM3K15FV

SOD-VESM-HF

Q5040

3

1

2

45 73

45 46 53

SYNC_DATE=07/08/2010

SYNC_MASTER=LINDA_K90I

SMC Support

PP3V42_G3H

SMC_MANUAL_RST_L

SYS_LED_ANODE

SMC_BATLOW_L

PM_BATLOW_L

PP3V3_S5

PP3V3_SUS

TP_SMC_GFX_THROTTLE_L TP_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_L

TP_SMC_ADC3 TP_SMC_ADC3

MAKE_BASE=TRUE

TP_SMC_ADC14 TP_SMC_ADC14

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH NC_SMC_FAN_1_TACH

MAKE_BASE=TRUE

TP_SMC_ADC2 TP_SMC_ADC2

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL NC_SMC_FAN_1_CTL

MAKE_BASE=TRUE

PP3V42_G3H

SMC_PME_S4_WAKE_L

DP_A_EXT_HPD

SMC_CLK32K

TP_SMC_P24

SMC_BMON_MUX_SEL

TP_SMC_P41

TP_SMC_PF5

SYS_LED_L_VDIV

SMC_BIL_BUTTON_L SMC_BC_ACOK

SMS_INT_L

SYS_LED_ILIM

SMC_RUNTIME_SCI_L

TP_SMC_PF5

MAKE_BASE=TRUE

TP_SMC_P20

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

SMC_ONOFF_L

SMC_LID

PP3V42_G3H

SMC_SYS_LED

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

SMC_XTAL

SMC_EXTAL

PP5V_S3

MAKE_BASE=TRUE

SMC_CPU_VSENSE

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

TP_SMC_P43

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V

PP3V3_S5_AVREF_SMC

MIN_NECK_WIDTH=0.1 mm

MAKE_BASE=TRUE

TP_SMC_SA_ISENSE

TP_SMC_P41

MAKE_BASE=TRUE

SMC_GFX_ISENSE

MAKE_BASE=TRUE

TP_SMC_P1V5S3_ISENSE

MAKE_BASE=TRUE

SMC_CPUVCCIO_ISENSE

MAKE_BASE=TRUE

GND_SMC_AVSS

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=0V

SMC_GFX_VSENSE

SMC_GFX_ISENSE

SMC_CPUVCCIO_ISENSE

SMC_PBUS_VSENSE

SMC_BMON_ISENSE

SMC_CPU_ISENSE

SMC_RESET_L

TP_SMC_P10

PM_THRMTRIP_L_R

TP_SMC_P43

SMC_DCIN_VSENSE

SMC_OTHER_HI_ISENSE

SYS_LED_L

NC_SMC_FAN_2_TACH

NC_SMC_FAN_3_TACH

SMC_TPAD_RST_L

SMC_XTAL_R

NC_SMC_FAN_3_CTL

TP_SMC_RSTGATE_L

TP_SMC_SA_ISENSE

CPU_PROCHOT_BUF

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

CPU_PROCHOT_L_R

SMC_PROCHOT_3_3_L

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

G3_POWERON_L

TP_SMC_P20

MAKE_BASE=TRUE

TP_SMC_P10

MAKE_BASE=TRUE

SMC_GFX_VSENSE

MAKE_BASE=TRUE

PM_CLK32K_SUSCLK_R

TP_SMC_P1V5S3_ISENSE

PP3V3_S0

SMC_ONOFF_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

SMC_BC_ACOK

SMS_INT_L

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

NC_SMC_FAN_2_TACH

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

PP3V3_WLAN

WIFI_EVENT_L

SMC_S4_WAKESRC_EN

SMC_PB4

SMC_CASE_OPEN

SMC_TMS SMC_TDO

SMC_RX_L

SMC_TX_L

SMC_DCIN_ISENSE

SMC_THRMTRIP

SMC_ADAPTER_EN

SMC_TCK

SMC_TDI

SMC_PA0_PU

SMC_ONOFF_L

SMC_PROCHOT

PP3V42_G3H

SMS_INT_L

SMC_BC_ACOK

CPU_PROCHOT_L

PP3V3_S4

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

SMC_DP_HPD_L

50 OF 109

46 OF 86

6 7

26 43 45 46 47 48 53

63 64 73

6 7 8

17 19 20 22 23 24 26 30

56 66 72 73 74 76 85

7

16 17 18 19 20 22 71 72 73

45 46 45 46

45

45 46 45 46

6 7

26 43 45 46 47 48 53 63

64 73

45 46

45 46 50

45 46

6

45 63

45 46 49 63 64

45 46 55

19 45

45 46

45 46 50

45 46 53

45 53 63

6 7

26 43 45 46 47 48 53 63

64 73

45 46

45

6 7 30 32 42 43

44 57 59 60

61 66 67 72

45 46 49

45 46

45 46 49

45 46 50

45 46 49

45 46 50

45 46

45

45 46

45 46 49

45 46

45 46 49

45 49 50

45 46 49

45 46 50

45 46 49

45 46

45 46 49

45 46 50

45 46

45 46 50

45 46 49

45

45 46

45 46 49

45 46

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 48

49 50 51 52 54 57 61 62 71 72

73 74 75 77 85

45 46

45 46 49 63 64

45 46 55

45 46 50

45 46

45 46 50

6

32

32 45

8

45 73 76

45

6

45 47

6

45 47

6

43 45 47

6

43 45 47

45 46 50

17 45 73

6

45 47

6

45 47

45

6 7

26 43 45 46 47 48 53

63 64 73

45 46 55

45 46 49 63 64

7

46 53 54 72

7

46 53 54 72

OUT

IN

IN OUT

OUT

OUT IN

OUT IN OUT

IN

BI BI

OUT

IN

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

516S0573

SPI Bus Series Termination

LPC+SPI Connector

PLACE_NEAR=J5100.12:5mm

47

402

MF-LF

1/16W

5%

LPCPLUS

R5126

1

2

56

PLACE_NEAR=R5127.2:5mm

47

MF-LF

5%

1/16W

402

R5122

1 2

PLACE_NEAR=U1800.V4:5mm

5% 1/16W MF-LF

402

15

R5112

1 2

16 81

PLACE_NEAR=J5100.9:5mm

47

LPCPLUS

5% 1/16W MF-LF 402

R5127

1

2

0

402

MF-LF

1/16W

5%

LPCPLUS

PLACE_NEAR=J5100.11:5mm

R5128

1

2

6

43 45 46

6

45

6

45

6

45 46

55909-0374

CRITICAL

LPCPLUS

M-ST-SM

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

6

19

6

43 45 46

45

45 46 64

6

45 46

6

45 46

6

26 81

6

47

6

16 45 81

6

17 45

6

47

6

16 45 81

6

16 45 81

6

45 46

6

17 45

6

16 45

6

47

6

47

6

19 56

6

16 45 81

6

16 45 81

6

26 81

56

PLACE_NEAR=U1800.Y14:5mm

402

MF-LF

1/16W

5%

15

R5110

1 2

16 81

56

PLACE_NEAR=U1800.T3:5mm

1/16W

5%

MF-LF

402

15

R5111

1 2

16 81

56

MF-LF

PLACE_NEAR=U6100.2:5mm

15

402

5%

1/16W

R5123

1 2

16 81

PLACE_NEAR=R5125.2:5mm

47

402

1/16W

5%

MF-LF

R5120

1 2

PLACE_NEAR=J5100.14:5mm

47

402

MF-LF

1/16W

5%

LPCPLUS

R5125

1

2

PLACE_NEAR=R5126.2:5mm

1/16W

47

MF-LF

5%

402

R5121

1 2

LPC+SPI Debug Connector

SYNC_DATE=05/15/2010

SYNC_MASTER=K91_MLB

SPI_MOSI_R

SPI_MISO SPI_MLB_MISO

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MOSI

SPI_ALT_CS_L

SPI_ALT_CLK

SPI_ALT_MOSI

SPI_ALT_MISO

SPI_CS0_L

SPI_CS0_R_L

SPI_CLK_R

SPI_CLK

SPI_MOSI

PP3V42_G3H PP5V_S0

LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3>

SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO

LPC_AD<0> LPC_AD<1>

SPI_ALT_MOSI SPI_ALT_MISO

PM_CLKRUN_L

LPC_FRAME_L

SMC_TMS

SMC_TDO

LPCPLUS_RESET_L

SMC_MD1

SMC_TRST_L

SMC_TX_L

SPIROM_USE_MLB

SPI_ALT_CLK

51 OF 109

47 OF 86

6

47

6

47

6

47

6

47

81

6 7

26 43 45 46 48 53 63 64

73 6 7

22 42 52 54 65 68 70 72

73 77

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: SMC RMT bus remains powered and may be active in S3 state

(Write: 0xA4 Read: 0xA5)

SMC "Battery A" SMBus Connections

SMC "0" SMBus Connections

J3100

PCH "SMLink 0" Connections

(MASTER)

U4900

SMC

EMC1414-A: U5570

CPU Temp

(Write: 0x98 Read: 0x99)

(Write: 0x94 Read: 0x95)

U9310

DP Re-driver

T29 Plug uC

(Write: 0xA0 Read: 0xA1)

J9400U3600

(MASTER)

actual CDR(s) in plug.

Microcontroller abstracts

(Write: 0x98 Read: 0x99)

Cougar-Point

Margin Control

(Write: 0x30 Read: 0x31)

Mikey

SMC "A" SMBus Connections

(Write: 0x72 Read: 0x73)

(Write: 0x88 Read: 0x89)

(MASTER)

XDP Connectors

J2600 & J2650

(WRITE: 0x58 READ: 0x59)

U4900

(Write: 0xA0 Read: 0xA1)

access PCH & CPU via PECI.

(Write: 0x72 Read: 0x73)

J3402

Cougar-Point

U3301

U3300

U1800

(MASTER)

PCH "SMLink 1" Connections

SMLink 1 is slave port to

SMC "Management" SMBus Connections

SO-DIMM "B"

(Write: 0x90 Read: 0x91)

X19

(Write: 0x30 Read: 0x31)

Battery LED Driver - (Write: 0x36 Read: 0x37)

PCH SMBus "0" Connections

SMC

U4900

(MASTER)

Digital SMS

Trackpad

J5800

ALS

(Write: 0x90 Read: 0x91)

LIS331DLH: U5920

(See Table)

(Write: 0x12 Read: 0x13)

U4900

SMC

J2900

U1800

Battery

(MASTER)

SMC

(MASTER)

U4900

J6955

ISL6258 - U7000

Battery

Battery Charger

(MASTER)

U1800

SMC

VRef DACs

SO-DIMM "A"

U9701

U6800

LED BACKLIGHT

(MASTER)

(Write: 0x98 Read: 0x99)

Battery Temp - (Write: 0x90 Read: 0x91)

Battery Manager - (Write: 0x16 Read: 0x17)

EMC1414-A: U5520

T29 Temp

U4510

T29 IC

SATA_Redriver

(Write: 0xB6 Read: 0xB7)

SMC "B" SMBus Connections

For Compliance Testing

T29 I2C Connections

4.7K

MF-LF 402

5% 1/16W

R5291

1

2

4.7K

MF-LF

402

5%

1/16W

R5290

1

2

5%

MF-LF

1/16W

4.7K

402

R5261

1

2

4.7K

1/16W

402

5%

MF-LF

R5260

1

2

2.0K

5% 1/16W MF-LF

402

R5280

1

2

2.0K

5% 1/16W MF-LF 402

R5281

1

2

1/16W

5%

MF-LF

402

1K

R5270

1

2

1K

5% 1/16W MF-LF 402

R5271

1

2

402

MF-LF

1/16W

5%

4.7K

R5251

1

2

5%

MF-LF

402

1/16W

4.7K

R5250

1

2

MF-LF

402

5%

1/16W

8.2K

R5210

1

2

8.2K

1/16W

402

5% MF-LF

R5211

1

2

5%

MF-LF 402

1/16W

NO STUFF

8.2K

R5221

1

2

402

5%

1/16W

8.2K

MF-LF

NO STUFF

R5220

1

2

402

0

5% 1/16W MF-LF

R5223

1 2

0

5%

MF-LF

402

1/16W

R5222

1 2

MF-LF 402

1/16W

5%

1K

R5201

1

2

5%

MF-LF

1K

1/16W

402

R5200

1

2

4.7K

402

MF-LF

5%

1/16W

R5230

1

2

4.7K

402

MF-LF

1/16W

5%

R5231

1

2

201

1/20W MF

5%

0

SDRVI2C:MCU

R5235

1

2

201

1/20W

MF

5%

0

SDRVI2C:MCU

R5234

1

2

201

SDRVI2C:SB

1/20W

MF

0

5%

R5236

1 2

SDRVI2C:SB

201

1/20W

MF

5%

0

R5237

1 2

SYNC_DATE=05/26/2010

SYNC_MASTER=K91_MLB

SMBus Connections

PP3V3_S0

I2C_T29_SCL

MAKE_BASE=TRUE

I2C_T29_SCL

MAKE_BASE=TRUE

I2C_T29_SDA

SMBUS_PCH_DATA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK

PP3V42_G3H

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCL

SMBUS_PCH_CLK

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL

SMBUS_PCH_CLK

SMBUS_SMC_BSA_SDASMBUS_SMC_BSA_SDA

PP3V3_S0

SMBUS_SMC_BSA_SCL

PP3V3_S0

PP3V3_S3

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SCL

SMBUS_SMC_0_S0_SCL

PP3V3_S0

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SML_PCH_0_DATA

MAKE_BASE=TRUE

SML_PCH_0_CLK

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

SMBUS_PCH_DATA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

PP3V3_S3

SML_PCH_1_CLK

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

SMBUS_PCH_DATA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

I2C_T29_SDA

I2C_DPSDRVA_SCL

I2C_DPSDRVA_SDA

MAKE_BASE=TRUE

PP3V3_S0

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SML_PCH_1_DATA

SMBUS_PCH_DATA

MAKE_BASE=TRUE

SMBUS_PCH_CLK

MAKE_BASE=TRUE

I2C_DPSDRVA_SCL

52 OF 109

48 OF 86

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

34 48 75 83 34

48

75

83

34 48 75 83

16 23 27 29 31 42

48 62 77

81

6

32

45 48 51

84

6

32

45 48 51

84

6

32

45 48 51

84

6

32

45 48 51

84

16 23 27 29 31 42

48 62 77

81 16 23 27

29 31 42

48 62 77

81

16 23 27 29 31 42

48 62 77

81

16 23 27 29 31 42

48 62 77

81

16 23 27 29 31 42

48 62 77

81

6 7

26 43 45 46 47 53 63 64

73

45 48 84

16 23 27 29 31 42

48 62 77

81

6

45 48

63 64 84

6

45 48

63 64 84

6

45 48

63 64 84

16 23 27 29 31 42

48 62 77

81

16 23 27 29 31 42

48 62 77

81

6

45 48

63 64 84

6

45 48 63

64 84

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62

71 72 73 74 75 77 85

6

45 48 63

64 84

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62

71 72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62

71 72 73 74 75 77 85

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

16 23 27 29 31 42

48 62 77

81

16 23 27 29 31 42

48 62 77

81

6

32

45 48 54

55 84

6

32

45 48 54

55 84

6

32

45 48 54

55 84

6

32 45 48

54 55 84

6

32

45 48 54

55 84

6

32 45 48

51 84

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62

71 72 73 74 75 77 85

6

32

45 48 54

55 84

6

32

45 48 54

55 84

16 81

45

48 84

45

48 84

16 23 27 29 31 42

48 62 77

81

16 23 27 29 31 42

48 62 77

81

6

32 45 48

51 84

6 7 8

18 24 26 30 31 32 33 48

50 54 55 72 73

16 81

16 23 27 29 31 42 48 62

77 81

16 23 27 29 31 42 48 62

77 81

6

32 45 48

54 55 84

16 23 27 29 31 42

48 62 77

81

34 48

75

83

48 75

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62

71 72 73 74 75 77 85

45

48 51 84

45

48 51 84

45 48 51 84

16 81

16 23 27 29 31 42 48 62

77 81

16 23 27 29 31 42 48 62

77 81

48 75

OUT

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

IN

OUT

IN

V+

REFIN+

IN-

OUT

GND

OUT

IN

V+ V-

THRM

V+ V-

THRM

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Max VOut: 3.3V at 19.77V Input

PBUS Voltage Sense Enable & Filter

DC-In Voltage Sense Enable & Filter

Scale: 16.48A / V Max VOut: 3.3V at 54.4A

Gain:161.765x

EDP: 17.5A TDP :13.1A

CPU 1.05V VCCIO Current Sense / Filter

divider when AC present.

divider when in S0.

Enables PBUS VSense

(200V/V)

Sense R is R7640, 1mOhm

Max VOut: 3.3V at 16.5A

Scale: 5A / V

Gain: 200x

RTHEVENIN = 4573 Ohms

CPU Vcore Voltage Sense / Filter

Enables DC-In VSense

RTHEVENIN = 4573 Ohms

GFX/IG Vcore Voltage Sense / Filter

(Effective Sense R is 0.375mOhm

Sense R is 0.75mOhm

EDP: 53A TDP :36A

Sense R is R7510 & R7520

Max VOut: 3.3V at 27.2A

Scale: 8.24A / V

Gain:161.765x

Sense R is 0.75mOhm EDP: 26A TDP: 21.5A

Sense R is R7550

GFX/IG VCore Load Side Current Sense / Filter

Max VOut: 3.3V at 19.77V Input

due to averaging of the 2 cores)

CPU VCore Load Side Current Sense / Filter

45 46

0.22UF

X5R 402

20%

6.3V

PLACE_NEAR=U4900.N12:5MM

C5330

1

2

4.53K

MF-LF

402

1%

1/16W

PLACE_NEAR=U4900.N12:5MM

R5330

1 2

72 73

MF-LF

402

1%

1/16W

100K

R5302

1

2

100K

MF-LF

402

1%

1/16W

R5301

1

2

45 46

0.22UF

20%

6.3V 402

X5R

PLACE_NEAR=U4900.L8:5MM

C5304

1

2

27.4K

MF-LF

402

1%

PLACE_NEAR=U4900.L8:5MM

1/16W

R5303

1

2

MF-LF

1%

1/16W

402

PLACE_NEAR=U4900.L8:5MM

5.49K

R5304

1

2

NTUD3169CZ

SOT-963

Q5300

6

3

2

5

1

4

45 46

27.4K

MF-LF

402

1%

1/16W

PLACE_NEAR=U4900.N9:5MM

R5313

1

2

MF-LF

402

1%

1/16W

100K

R5312

1

2

NTUD3169CZ

SOT-963

Q5310

6

3

2

5

1

4

PLACE_NEAR=U4900.N9:5MM

0.22UF

X5R 402

20%

6.3V

C5314

1

2

5.49K

402

1/16W

PLACE_NEAR=U4900.N9:5MM

MF-LF

1%

R5314

1

2

100K

MF-LF

402

1%

1/16W

R5311

1

2

45 46 63 64

45 46

PLACE_NEAR=U4900.L12:5MM

4.53K

MF-LF

402

1%

1/16W

R5361

1 2

PLACE_NEAR=U4900.L12:5MM

0.22UF

X5R 402

20%

6.3V

C5361

1

2

0.1uF

CERM 402

20% 10V

C5360

1

2

70 85

PLACE_NEAR=R7640.4:5MM

INA210

SC70

CRITICAL

U5360

2

5

4

6

1

3

IMVPISNS_ENG

PLACE_NEAR=U4900.M11:5MM

4.53K

MF-LF

402

1/16W

1%

R5341

1 2

45 46

IMVPISNS_ENG

0.22UF

X5R 402

20%

PLACE_NEAR=U4900.M11:5MM

6.3V

C5341

1

2

IMVPISNS_ENG

X5R 402

20%

6.3V

0.22UF

PLACE_NEAR=U4900.M13:5MM

C5351

1

2

IMVPISNS_ENG

PLACE_NEAR=U5340.5:3MM

10V

20%

402

CERM

0.1UF

C5340

1

2

0.1%

1/16W

MF

IMVPISNS_ENG

2.21K

0402

R5343

1 2

IMVPISNS_ENG

MF-LF

402

1%

1/16W

PLACE_NEAR=U4900.M13:5MM

4.53K

R5351

1 2

715K

0.1% MF

402

1/16W

IMVPISNS_ENG

R5344

1

2

69 85

IMVPISNS_ENG

1/16W

MF

0.1%

2.21K

0402

R5342

1 2

IMVPISNS_ENG

1/16W

0.1%

0402

MF

4.42K

R5352

1 2

4.42K

MF

0402

0.1%

1/16W

IMVPISNS_ENG

R5353

1 2

MF 402

IMVPISNS_ENG

715K

1/16W

0.1%

R5354

1

2

IMVPISNS_ENG

715K

MF

402

0.1%

1/16W

SIGNAL_MODEL=EMPTY

R5355

1 2

PLACE_NEAR=R7510.4:5MM

0402

MF

0.1%

1/16W

4.42K

IMVPISNS_ENG

R5346

1 2

IMVPISNS_ENG

1/16W

0.1% MF

4.42K

0402

PLACE_NEAR=R7520.3:5MM

R5347

1 2

68 69 85

69 85

OPA2333

DFN

IMVPISNS_ENG

CRITICAL

U5340

3

2

1

9

4

8

IMVPISNS_ENG

CRITICAL

OPA2333

DFN

U5340

5

6

7

9

4

8

470PF

CERM

50V 402

10%

NOSTUFF

C5344

1

2

IMVPISNS_ENG

SIGNAL_MODEL=EMPTY

1/16W

0.1%

402

MF

715K

R5345

1 2

SIGNAL_MODEL=EMPTY

50V

CERM

470PF

NOSTUFF

402

10%

C5345

1 2

NOSTUFF

470PF

50V

10%

CERM

402

C5354

1

2

NOSTUFF

SIGNAL_MODEL=EMPTY

10% 50V

CERM

470PF

402

C5355

1 2

PLACE_NEAR=R7510.3:5MM

1/16W

0.1%

4.42K

MF

0402

IMVPISNS_ENG

R5348

1 2

MF

4.42K

0.1%

1/16W

0402

IMVPISNS_ENG

R5349

1 2

SM

PLACE_NEAR=R7550.2:5 MM

XW5330

1 2

45 46

PLACE_NEAR=U4900.N10:5MM

4.53K

MF-LF

402

1%

1/16W

R5320

1 2

PLACE_NEAR=U4900.N10:5MM

0.22UF

X5R 402

20%

6.3V

C5320

1

2

PLACE_NEAR=R7510.2:5 MM

SM

XW5320

1 2

SYNC_DATE=10/22/2010

SYNC_MASTER=LINDA_K90I

Voltage & Load Side Current Sensing

PP3V3_S0

CPUIMVP_ISNS2_N

CPUIMVP_ISNS_N

CPUIMVP_ISUM_R_P

CPUIMVP_ISUM_R_N

CPUIMVP_ISUMG_R_N

CPUIMVP_ISNS1G_N

CPUIMVP_ISNS1G_P

SMC_GFX_ISENSE

CPUIMVP_ISUMG_R_P

CPUIMVP_ISUMG_IOUT

GND_SMC_AVSS

CPUIMVP_ISUM_IOUT

GND_SMC_AVSS

CPUIMVP_ISNS1_N

CPUIMVP_ISNS_P

CPUIMVP_ISNS2_P

CPUIMVP_ISNS1_P

SMC_CPU_ISENSE

SMC_PBUS_VSENSE

PPBUS_G3H

CPUVSENSE_IN

SMC_DCIN_VSENSE

GND_SMC_AVSS

PPVCORE_S0_AXG

PPVCORE_S0_CPU

PPDCIN_G3H

SMC_BC_ACOK

PDCINVSENS_EN_L_DIV

CPUVCCIOS0_CS_P

GND_SMC_AVSS

GFXVSENSE_IN

SMC_CPU_VSENSE

CPUVCCIO_IOUT

SMC_CPUVCCIO_ISENSE

PP3V3_S0

GND_SMC_AVSS

PM_SLP_S3_R_L

GND_SMC_AVSS

PBUS_S0_VSENSE

DCINVSENS_EN_L

PBUSVSENS_EN_L_DIV

SMC_GFX_VSENSE

GND_SMC_AVSS

CPUVCCIOS0_CS_N

PBUSVSENS_EN_L

DCIN_S5_VSENSE

53 OF 109

49 OF 86

6 7 8

12 16 17 18 19 20

22 23 26 27 29 33 36 37

40 41 42 46 48 49 50 51 52 54

57 61 62 71 72 73 74 75

77 85

85

45 46 49 50

85

6 7 8

36 40 50 63 64 77

45 46 49 50

6 7 9

12 15 69

6 7 9

12 14 69

7

63 64

45 46 49 50

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

45 46 49 50

V+

REFIN+

IN-

OUT

GND

IN

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

IN

OUT

V+

REFIN+

IN-

OUT

GND

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter

DC-In AMON ISL6259 Gain: 20x

Scale: 2.5A / V Max VOut: 3.3V at 8.25A

Sense R is R7020, 20mOhm

Sense R is R7050, 10mOhm

INA Solution

DC-IN (AMON) Current Sense Filter

Charger BMON (Production) Solution

Max VOut: 3.3V at 9.167A

Scale: 2.78A / V

ISL6259 Gain: 36x

across R7050

battery to PBUS (battery discharge)

From charger

NOTE: Monitoring current from

Scale: 2A / V

Max VOut: 3.3V at 6.6A

Gain: 50x

For engineering, stuff BMON_ENG For production, stuff BMON_PROD

Max VOut: 3.3V at 6.6A

Scale: 2A / V

Gain: 50x

(50V/V)

Charger/Load side

OTHER High Side Current Sense / Filter

Battery side

EDP: 10.0A TDP :5.2A

Gain: 50x

Max VOut: 3.3V at 6.6A

Scale: 2A / V

Gain: 50x

INA (Engineering) Solution

EDP: 15.5A TDP :11.1A

Scale: 4A / V

COMPUTING High Side Current Sense / Filter

Max VOut: 3.3V at 13.2A

CERM

10V

0.1uF

20%

BMON:ENG

402

C5420

1

2

SC70

INA213

PLACE_NEAR=R7050.3:5MM

CRITICAL

BMON:ENG

U5420

2

5

4

6

1

3

64

BMON:PROD

402

MF-LF

5%

1/16W

0

PLACE_NEAR=U5421.1:5MM

R5420

2 1

0.1uF

CERM

402

20% 10V

BMON:ENG

C5421

1

2

45 46

BMON:ENG

NC7SB3157P6XG

SC70

U5421

43

1

2

6

5

45 46

64 85

45 46

X5R

PLACE_NEAR=U4900.K10:5MM

6.3V

20%

402

0.22UF

C5431

1

2

PLACE_NEAR=U4900.K10:5MM

4.53K

MF-LF

402

1%

1/16W

R5431

1 2

64

20%

0.22UF

6.3V X5R 402

PLACE_NEAR=U4900.N8:5MM

C5403

1

2

402

1%

1/16W

4.53K

MF-LF

PLACE_NEAR=U4900.N8:5MM

R5403

1 2

45 46

MF-LF

PLACE_NEAR=U4900.L7:5MM

4.53K

1%

1/16W

402

R5413

1 2

PLACE_NEAR=U4900.L7:5MM

402

X5R

6.3V

0.22UF

20%

C5413

1

2

45 46

45.3K

PLACE_NEAR=U4900.M9:5MM

402

1/16W

1%

MF-LF

R5422

1 2

10%

0.022UF

CERM-X5R

16V

PLACE_NEAR=U4900.M9:5MM

402

C5422

1

2

BMON:ENG

1/16W

5%

402

MF-LF

100K

R5423

1

2

CRITICAL

SC70

INA213

U5400

2

5

4

6

1

3

6 7 8

36 40 49

50 63 64 77

7

65 67 68 69 70

10%

0201

X5R-CERM

16V

0.1UF

C5401

1

2

402

0.1UF

CERM

20% 10V

C5411

1

2

7

66

INA213

SC70

CRITICAL

U5410

2

5

4

6

1

3

CRITICAL

1W MF

0.01

0.5%

0612-3

R5410

123

4

6 7 8

36 40 49 50 63 64 77

CRITICAL

1%

1W

0612

0.005

MF

R5400

123

4

SYNC_DATE=10/22/2010

SYNC_MASTER=LINDA_K90I

High Side Current Sensing

PP3V3_S0

GND_SMC_AVSS

PPBUS_S5_HS_COMPUTING_ISNS

PPBUS_G3H

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

CHGR_CSO_R_P

PP3V3_S0

HS_OTHER_IOUT

BMON_AMUX_OUT

PPBUS_G3H

SMC_OTHER_HI_ISENSE

GND_SMC_AVSS

CHGR_CSO_R_N

SMC_BMON_ISENSE

GND_SMC_AVSS

PPBUS_S5_HS_OTHER_ISNS

HS_COMPUTING_IOUT

ISNS_HS_OTHER_P

ISNS_HS_OTHER_N

PP3V3_S3

CHGR_BMON

SMC_CPU_HI_ISENSE

GND_SMC_AVSS

SMC_DCIN_ISENSE

CHGR_AMON

BMON_INA_OUT

SMC_BMON_MUX_SEL

54 OF 109

50 OF 86

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

45 46 49 50

85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

45 46 49 50

85

6 7 8

18 24 26 30 31 32 33 48

54 55 72 73

45 46 49 50

BI

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

BI

THERM*/ADDR

ALERT*

GND

VDD

DN

DP

SMDATA SMCLK

THRM

PAD

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Placement note:

Use GND pin B1 on U3600 for N leg

Write Address: 0x98

Detect T29 Die Temperature

T29 Die

Placement note:

Detect Fin Stack Temperature

Read Address: 0x99

Placement note:

Place U5520 between PCH and T29 on TOP side

Placement note:

CPU Proximity/CPU Die/5V-3.3V Proximity

Detect CPU Die Temperature

Place U5510 under CPU

Detect DDR/5V/3.3V Proximity Temperature

Place Q5510 next to DDR/5V/3.3V supply on TOP side

PCH-T29 Proximity/FinStack

Place Q5520 on BOTTOM side close to finstack

Read Address: 0x99

Write Address: 0x98

10K

5% 1/16W MF-LF 402

R5512

1

2

402

5%

MF-LF

10K

1/16W

R5511

1

2

SOT732-3

BC846BMXXH

Q5510

1

3

2

PLACE_NEAR=U5510.3:5mm

CERM

402

50V

10%

0.0022uF

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5510.2:5mm

C5511

1

2

9

85

9

85

DFN

CRITICAL

EMC1413

U5510

83

5

2

4

6

10

9

7

11

1

BC846BMXXH

SOT732-3

Q5520

1

3

2

34 51 85

PLACE_NEAR=U5520.3:5mm

PLACE_NEAR=U5520.2:5mm

SIGNAL_MODEL=EMPTY

CERM

50V

10%

402

0.0022uF

C5522

1

2

1/16W MF-LF

402

5%

47

R5520

1 2

CERM

0.1uF

20% 10V

402

C5520

1

2

402

5%

MF-LF

10K

1/16W

R5521

1

2

10K

5% 1/16W MF-LF 402

R5522

1

2

PLACE_NEAR=U3600.B1:2mm

SM

XW5520

1 2

EMC1412-A

CRITICAL

TQFN

U5520

6

3

2

5

8

7

4

9

1

PLACE_SIDE=BOTTOM

NOSTUFF

603

1/10W

5%

MF-LF

10K

R5523

1

2

6

32 45 48 84

6

32 45 48 84

45 48 84

0.1uF

20% 10V CERM 402

C5510

1

2

1/16W MF-LF

402

5%

47

R5510

1 2

0.0022uF

402

10% 50V

CERM

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5510.4:5mm

PLACE_NEAR=U5510.5:5mm

C5512

1

2

Thermal Sensors

SYNC_DATE=10/22/2010

SYNC_MASTER=LINDA_K90I

T29THMSNS_D2_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

CPU_THERMD_N

CPUTHMSNS_D2_N

CPUTHMSNS_ALERT_L

CPUTHMSNS_THM_L

CPU_THERMD_P

PP3V3_S0

CPUTHMSNS_D2_P

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

PP3V3_S0_T29THMSNS_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

T29THMSNS_ALERT_L

T29THMSNS_THM_L

T29_THERMD_P

MAKE_BASE=TRUE

T29_THERMD_N

T29_THERMD_P

T29THMSNS_D2_P

PP3V3_S0

55 OF 109

51 OF 86

85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

85

34 51 85

85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

D

GS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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SIZE

D

R

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PAGE TITLE

C

A

D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NC

518S0521

GND

MOTOR CONTROL

TACH

5V DC

47K

1/16W

5%

MF-LF

402

R5665

1 2

5%

402

MF-LF

1/16W

47K

R5660

1

2

5% 1/16W MF-LF

402

100K

R5661

1

2

SSM3K15FV

SOD-VESM-HF

Q5660

3

1

2

CRITICAL

78171-0004

M-RT-SM

J5601

5

6

1 2 3 4

Fan

SYNC_MASTER=K24_MLB

SYNC_DATE=07/20/2009

FAN_RT_PWM

PP5V_S0 PP3V3_S0

SMC_FAN_0_CTL

FAN_RT_TACH

SMC_FAN_0_TACH

56 OF 109

52 OF 86

6

6 7

22 42 47 54 65 68 70 72

73 77

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 54 57 61 62 71

72 73 74 75 77 85

45

6

45

D

G S

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSSD+D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER2)

P0_1

IN

NC

OUT

IN_A1

OUT_B

IN_A3_B2

GND

THRM

OUT_A

VDD

IN_A2

IN_B1

PAD

(IPD)

OUT

D

G S

IN_B1

IN_A2

VDD

THRM

GND

IN_A3_B2

OUT_B

IN_A1

OUT_A*

(IPD)

PAD

OUT

IN

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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SIZE

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PAGE TITLE

C

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D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- TRACKPAD PICK BUTTONS

SMC Manual Reset & Isolation

Left shift, option & control keys combined with power button cause SMC RESET# assertion. Keys ANDed with PSOC power to isolate when PSOC is not powered.

1.5 OHM

Keyboard Connector

LID CLOSE => SMC_LID_LC < 0.50V

PLACE THESE COMPONENTS CLOSE TO J5800

THE TPAD BUTTONS WILL BE DISABLE

LID OPEN => SMC_LID_LC ~ 3.42V

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

PIN NAME

36E-3 W

518S0637

- KEYBOARD SCANNER

WHEN THE LID IS CLOSED

TPAD Buttons Disable

96E-6 W

75.2E-6 W

294E-6 W

0.72E-3 W

16.32E-6 W

0.255E-6 W

4.7 OHM

0.2 OHM

10 OHM

2.55 KOHM

14MA (MAX) 4MA (MAX)

8MA (TYP)

60MA (MAX)

VDD VOUT

80UA

V+

TMP102

- USB INTERFACES TO MLB

10UA

IC

CURRENT

R_SNS V_SNS POWER

0.0255 V

0.204 V

0.012 V

0.021 V

0.0188 V

VIN

VDD

ISSP SDATA/I2C SDA

(PP3V3_S3_PSOC)

ISSP SCLK/I2C SCL

337S2983

18V BOOSTER

PSOC

3V3 LDO

0.6 V

- SPI HOST TO Z2

PSOC USB CONTROLLER

SOD-VESM-HF

SSM3K15FV

Q5701

3

1

2

4.7UF

BYPASS=U5701.49:50:11 mm

603

X5R

6.3V

20%

C5706

1

2

BYPASS=U5701.49:50:8 mm

0.1UF

402

X7R-CERM

16V

10%

C5705

1

2

50V

100PF

BYPASS=U5701.49:50:5 mm

5% CERM

402

C5704

1

2

0.1UF

402

X7R-CERM

16V

10%

BYPASS=U5701.22:19:8 mm

C5703

1

2

100PF

BYPASS=U5701.22:19:5 mm

402

CERM

50V

5%

C5702

1

2

BYPASS=U5701.22:19:11 mm

20%

6.3V 603

4.7UF

X5R

C5701

1

2

24

1/16W MF-LF

5%

402

R5702

1 2

CRITICAL

OMIT

CY8C24794

MLF

U5701

20

21

45544653475248

51

25182617271628

15

41

2

42

1

435644

55

3310

34

9

35

8

36

7

37

6

38

5

39

4

40

3

2914

3013

3112

3211

24

235722 49

19

50

402

5%

MF-LF

1/16W

24

R5701

1 2

45 46 63

20%

0.1UF

PLACEMENT_NOTE=NEAR J5713

402

10V

CERM

C5710

1

2

1K

402

5%

MF-LF

1/16W

R5710

1 2

1/16W MF-LF

1%

402

470

R5714

1 2

402

1%

MF-LF

1/16W

10K

R5715

1 2

CRITICAL

FF14-30A-R11B-B-3H

F-RT-SM

J5713

31

32

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

45 46

402

5%

MF-LF

1/16W

1.5

R5704

2 1

0.1UF

X7R-CERM

16V

10%

402

C5755

1

2

X7R-CERM

16V

10%

402

0.1UF

C5750

1

2

SLG4AP006

TDFN

CRITICAL

U5750

5

2

3

7

6

4

8

9

1

5%

1/16W

402

MF-LF

0

R5720

1 2

46

SOD-VESM-HF

SSM3K15FV

NO STUFF

Q5702

3

1

2

TDFN

CRITICAL

SLG4AP015V

U5755

5

2

3

7

6

4

8

9

1

45 46

73

5%

220K

MF-LF

402

1/16W

R5703

1

2

SYNC_DATE=07/12/2010

SYNC_MASTER=LINDA_K90I

WELLSPRING 1

PP3V3_S3_PSOC

MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.50MM

PICKB_L

SMC_PME_S4_WAKE_L

WS_KBD23

NC_PSOC_P1_3

TP_PSOC_SDA

Z2_MOSI

WS_CONTROL_KEY

PSOC_VBUS_EN

Z2_RESET

WS_KBD19

WS_KBD22

BUTTON_DISABLE

WS_KBD20

Z2_HOST_INTN

WS_LEFT_OPTION_KEY

PSOC_F_CS_L PSOC_MOSI

WS_LEFT_SHIFT_KEY

PSOC_MISO

SMC_TPAD_RST_L

PSOC_SCLK

TP_PSOC_SCL

TP_ISSP_SCLK_P1_1

USB_TPAD_R_N

TP_P7_7

Z2_DEBUG3

Z2_KEY_ACT_L

WS_KBD6

SMC_ONOFF_L

USB_TPAD_R_P

WS_KBD9

WS_CONTROL_KBD

WS_LEFT_SHIFT_KBD

WS_KBD_ONOFF_L

Z2_CLKIN

SMC_LID

BUTTON_DISABLE

USB_TPAD_N

USB_TPAD_P

WS_KBD3

WS_KBD2

WS_KBD1

WS_KBD7

WS_KBD8

WS_KBD10

WS_KBD11

WS_KBD13 WS_KBD12

WS_KBD14

WS_KBD16N

WS_KBD17

WS_KBD6

WS_KBD4 WS_KBD5

WS_KBD18

WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5

WS_KBD18

WS_KBD17

WS_KBD14

WS_KBD13

WS_KBD11 WS_KBD12

WS_KBD10

WS_KBD9

WS_KBD21

WS_KBD20

WS_KBD19

WS_KBD22 WS_KBD23

WS_KBD7 WS_KBD8

WS_KBD15_CAP

WS_KBD16N

WS_KBD15_C

WS_KBD16_NUM

WS_LEFT_OPTION_KEY

TP_ISSP_SDATA_P1_0

WS_LEFT_OPTION_KBD

WS_KBD15_C

SMC_TPAD_RST

WS_CONTROL_KEY

WS_CONTROL_KBD

PP3V42_G3H

WS_LEFT_OPTION_KBD

PP3V42_G3H

PP3V3_S4

WS_KBD21

PP3V3_S4

WS_LEFT_SHIFT_KBD

PP3V3_S4

WS_LEFT_SHIFT_KEY

Z2_MISO Z2_CS_L

Z2_SCLK

57 OF 109

53 OF 86

6

54

6

53

6

54

53

6

54

6

53

6

53

6

53

6

54

53

6

54

6

54

53

6

54

6

54

8

85

6

54

6

54

6

53

85

6

53

6

53

6

53

6

54

53

24 80

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

8

6

53

6

53

6 7

26 43 45 46 47 48 53 63

64 73

6

53

6 7

26 43 45 46 47 48 53 63

64 73

7

46 53 54 72

6

53

7

46 53 54 72

6

53

7

46 53 54 72

53

6

54

6

54

6

54

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD

GND

BI

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BOOSTER DESIGN CONSIDERATION:

(SMC_KBDLED_PRESENT_L)

If LOW, keyboard backlight present

- STARTUP TIME LESS THAN 2MS

Keyboard Backlight Connector

J5815 pin 1 is grounded on keyboard backlight flex

518S0691

grounded when KB BL flex connected.

R5853 always stuffed, R5854 only

If HIGH, keyboard backlight not present

To detect Keyboard backlight, SMC will

516S0689

- R5812,R5813,C5818 MODIFIED

- RIPPLE TO MEET ERS

IPD Flex Connector

- 100-300 KHZ CLEAN SPECTRUM

- DROOP LINE REGULATION

CONFRIM IF THIS CAN BE CONNECTED TO S3!!

- POWER CONSUMPTION

BOOSTER +18.5VDC FOR SENSORS

K6 NOTES : C5850 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNC’ED FROM T27

tristate and read SMC_SYS_KBDLED:

Keyboard Backlight Driver & Detection

CRITICAL

55560-0228

M-ST-SM

J5800

1

10

1112 1314 1516 1718 19

2

20

2122

34 56 78 9

B0520WSXG

SOD-323

CRITICAL

D5802

1 2

1UF

25V

603-1

X5R

10%

C5819

1

2

1/16W MF-LF

5%

402

0

R5806

1 2

10%

X7R-CERM

402

0.1UF

16V

C5816

1

2

0

1/16W MF-LF

5%

402

R5805

2 1

16V

2.2UF

603

X5R

10%

C5817

1

2

TPS61045

QFN

CRITICAL

U5805

5

3

4

6

1

7

8

9

2

VLF3010AT-SM-HF

3.3UH-870MA

CRITICAL

L5801

1 2

402

MF-LF

1/16W

1%

100K

R5811

1

2

45

4.7K

KB_BL

402

MF-LF

1/16W

5%

R5854

1

2

MF-LF

470K

5%

1/16W

402

R5853

1

2

LT3491

DFN

CRITICAL

KB_BL

U5850

4

6

2

5

3

7

1

1/16W

5%

NO STUFF

402

MF-LF

10K

R5852

1

2

BYPASS=U5850.1:2:2 MM

10% X5R

402-1

1UF

10V

KB_BL

C5850

1

2

KB_BL

402

1% MF-LF

1/16W

10

R5855

1

2

CRITICAL

KB_BL

1098AS-SM

10UH-0.58A-0.35OHM

L5850

1 2

KB_BL

35V

1UF

603

X5R

10%

C5855

1

2

CRITICAL

KB_BL

FF18-4A-R11AD-B-3H

F-RT-SM

J5815

1 2 3 4

5%

CERM

402

39PF

50V

C5818

1

2

402

MF-LF

1/16W

1%

1M

R5812

1

2

71.5K

1% 1/16W MF-LF 402

R5813

1

2

NO STUFF

1/16W

5%

0

MF-LF

402

R5800

1 2

WELLSPRING 2

SYNC_DATE=07/12/2010

SYNC_MASTER=LINDA_K90I

PP18V5_S5

SMBUS_SMC_A_S3_SCL

PP3V3_S4

P3V3_S3_TPAD

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

Z2_CLKIN

PP3V3_S3

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM SWITCH_NODE=TRUE

KBDLED_SW

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

KBDLED_CAP

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

KBDLED_ANODE

PP5V_S3_P18V5S5

MIN_LINE_WIDTH=0.50MM VOLTAGE=5V

MIN_NECK_WIDTH=0.20MM

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP18V5_S5

PP5V_S3_P18V5S5_VIN

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM VOLTAGE=5V

PP18V5_S5_R

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V

P18V5S5_FB

PSOC_F_CS_L PICKB_L PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SDA

Z2_KEY_ACT_L

Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN

Z2_BOOST_EN

PP3V3_S0

PP5V_S5

SMC_KDBLED_PRESENT_L

PP5V_S0

SMC_SYS_KBDLED

Z2_RESET

P18V5S5_SW

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

58 OF 109

54 OF 86

6

54

6

32 45 48 55 84

7

46 53 72

6

53

6 7 8

18 24 26 30 31 32 33 48

50 55 72 73

6

54

6

53

6

53

6

53

6

53

6

53

6

32 45 48 55 84

6

53

6

53

6

53

6

53

6

53

6

53

6

54

6

53

6

54

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 57 61 62 71 72

73 74 75 77 85

7

66 72

6

6 7

22 42 47 52 65 68 70 72

73 77

6

53

INT2

VDD

VDD_IO

SDO

GND

NC

RESERVED

INT1CSSDA/SDI/SDO

SCL/SPC

NC NC

OUT

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: SDA and SCL have internal pull-ups to VDD_IO.

in correct orientation

SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)

SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)

Front of system

338S0687

Circle indicates pin 1 location when placed

Desired orientation when placed on top-side:

+Z (up)

+Y

+X

PLACE_SIDE=TOP

PLACEMENT_NOTE=See schematic for orientation.

LGA

LIS331DLH

CRITICAL

U5920

8

5

121316

11

9

2 3

10

15

4

6

7

14

1

BYPASS=U5920.14:13:8 mm

402

16V

10%

X5R

0.1UF

C5922

1

2

BYPASS=U5920.14:13:8 mm

603

X5R

6.3V

10UF

20%

C5926

1

2

10K

402

1/16W MF-LF

5%

R5920

1

2

402

1/16W MF-LF

5%

10K

R5921

1

2

402

1/16W MF-LF

0

5%

R5922

1 2

402

1/16W MF-LF

5%

0

R5923

1 2

10K

1/16W

402

MF-LF

5%

R5924

1

2

45 46

6

32 45 48 54 84

6

32 45 48 54 84

SYNC_MASTER=LINDA_K90I

SYNC_DATE=07/08/2010

Digital Accelerometer

SMS_I2C_SEL

PP3V3_S3

I2C_SMC_SMS_SCL_R

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

SMS_ADDR_SELECT I2C_SMC_SMS_SDA_R

SMS_INT_L TP_SMS_INT2

59 OF 109

55 OF 86

6 7 8

18 24 26 30 31 32 33 48

50 54 72 73

OUT

IN

IN IN

IN

WP*

SI

HOLD*

VSS

SCK

CE*

VDD

SO

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

C

A

D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: If HOLD* is asserted ROM will ignore SPI cycles.

402

20%

CERM

0.1UF

10V

C6100

1

2

402

3.3K

5% MF-LF

1/16W

R6101

1

2

47

47 47

6

19 47

OMIT

CRITICAL

SOIC

64MBIT

SST25VF064C

U6100

1

7

6

5

2

8

4

3

SPI ROM

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

SPI_MLB_CLK

SPI_WP_L

SPI_MLB_CS_L

PP3V3_S5

SPIROM_USE_MLB

SPI_MLB_MISO

SPI_MLB_MOSI

61 OF 109

56 OF 86

6 7 8

17 19 20 22 23 24 26 30

46 66 72 73 74 76 85

IN

OUT

IN

OUT

OUT OUT

OUT

IN IN IN IN

IN

OUT

IN

OUT

NR/FB

NC

IN

EN

GND

OUT

OUT OUT

IN IN IN

OUT

IN

OUT

/SPDIF_OUT2

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+ MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

RT. SPKR AMP. SIG. SOURCE

NC

DAC2/3 FSOUTPUTSE= 1.34VRMS

SE FSINPUT= 1.22VRMS

APPLE P/N 353S2456

DIFF FSINPUT= 2.45VRMS

BI MIC CODEC INPUT

EXT MIC CODEC INPUT

LFT. SPKR AMP. SIG. SOURCE

FR SPKR AMP. SIG. SOURCE

NC

APPLE P/N 353S2355

4.5V POWER SUPPLY FOR CODEC

GPIO1 = HP AMP CONTROL

GPIO2 = ANALOG SW CONTROL

U6201 CONSUMES ?MA MAX. FROM 1.5V RAIL

DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS

NOTES ON CODEC I/O

Digial Mic

GPIO3 = SPKR AMP SHDN CONTROL

AUDIO CODEC

603-1

X5R

20%

CRITICAL

6.3V

10UF

C6221

1

2

SM

XW6201

1 2

6.3V

20%

CERM 402-LF

2.2UF

C6222

1

2

6.3V CERM

20%

2.2UF

402-LF

C6223

1

2

X5R

603-1

6.3V

20%

10UF

CRITICAL

C6220

1

2

16V

20%

TANT

1UF

0603-SM

C6224

1

2

X5R-1

4.7UF

20%

402

4V

C6210

1

2

16 81

62

60

59

60 85

62

20%

603-1

X5R

6.3V

10UF

CRITICAL

C6213

1

2

402

X5R

10V

10%

1UF

C6201

1

2

1UF

X5R 402

10V

10%

C6203

1

2

0402

FERR-220-OHM

L6200

1 2

2.21K

1/16W

402

MF-LF

1%

R6200

1 2

402

X5R

10V

10%

1UF

C6200

1

2

16V X5R 402

0.1UF

10%

C6215

1

2

402

0.1UF

X5R

16V

10%

C6211

1

2

X5R

0.1UF

16V

10%

402

C6214

1

2

1%

MF-LF 402

1/16W

2.67K

R6210

1

2

NOSTUFF

MF-LF

5%

402

1/16W

100K

R6213

1

2

402

MF-LF

1/16W

5%

22

R6211

1 2

16V

0.1UF

X5R

10%

402

C6218

1

2

10UF

16V

2012-LLP

20%

TANT-POLY

C6225

1

2

10UF

16V

20%

TANT-POLY 2012-LLP

C6217

1

2

TANT-POLY

16V

2012-LLP

10UF

20%

C6219

1

2

6 7

30 32 42 43 44 46 57 59

60 61 66 67 72

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42

46 48 49 50 51 52 54 57 61

62 71 72 73 74 75 77 85

61

6

57

7

16 20 22 26 42 57 71

6

57

61

6

57

X5R 402-1

10V

10%

1UF

C6216

1

2

TPS71745

SON

CRITICAL

U6200

4

2

6

5

3

1

402

X7R-CERM

16V

10%

0.1UF

C6202

1

2

60 85

SM

XW6200

1 2

NOSTUFF

5%

MF-LF

0

1/16W

402

R6201

1 2

FERR-220-OHM

0402

L6201

1 2

402

1/16W

5%

39

MF-LF

R6212

1 2

58

59

16V X5R

10%

0.1UF

402

C6226

1

2

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42

46 48 49 50 51 52 54 57 61

62 71 72 73 74 75 77 85

MF-LF

22

402

5%

1/16W

R6214

1 2

61

CS4206B

CRITICAL

QFN

U6201

26

6

7

4

43 42

45

2

12

14 15

38 40

39

22

21

23

34

35

30

31

37

36

33

32

16

17

18

20

19

11

8 5

13

47 48

10

49

25

46

24

29

28

9

41

44

3

1

27

AUDIO: CODEC/REGULATOR

SYNC_DATE=08/10/2010

SYNC_MASTER=LENG_K90I

AUD_SENSE_A

AUD_GPIO_1

TP_AUD_DMIC_SDATA

CS4206_FP

AUD_GPIO_2

HDA_RST_L

TP_AUD_LO1_N_L

VBIAS_DAC

CS4206_FLYP

PP4V5_AUDIO_ANALOG

VOLTAGE=1.5V

PP1V8R1V5_S0_AUDIO_DIG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 MM

AUD_GPIO_3

CS4206_FN

AUD_LO1_N_R

AUD_LO1_P_R

AUD_LO2_N_R

AUD_SPDIF_OUT_CHIP

AUD_LI_REF

CS4206_FLYC

CS4206_FLYN

TP_AUD_SPDIF_IN

TP_AUD_LO1_P_L

MIN_LINE_WIDTH=0.5MM

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

GND_AUDIO_CODEC

PP5V_S3

AUD_HP_PORT_R

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_REF

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

CS4206_VCOM

AUD_LI_P_R

AUD_LI_P_L

AUD_MIC_INP_L AUD_MIC_INN_L

AUD_CODEC_MICBIAS

HDA_SYNC

AUD_DMIC_SCL

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_L

AUD_SDI_R

HDA_SDOUT

PP3V3_S0

HDA_BIT_CLK

AUD_MIC_INN_R

AUD_MIC_INP_R

CS4206_VREF_ADC

AUD_LO2_P_L AUD_LO2_N_L AUD_LO2_P_R

TP_AUD_DMIC_CLK TP_AUD_DMIC_CLK

MAKE_BASE=TRUE

TP_AUD_DMIC_SDATA

MAKE_BASE=TRUE

TP_AUD_DMIC_SDATA

TP_AUD_DMIC_CLK

GND_AUDIO_CODEC

PP3V3_S0

PP5V_S3

4V5_REG_IN

VOLTAGE=5V

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM

GND_AUDIO_HP_AMP

VOLTAGE=4.5V

MIN_NECK_WIDTH=0.10MM

PP4V5_AUDIO_ANALOG

MIN_LINE_WIDTH=0.15MM

VOLTAGE=0V

GND_AUDIO_HP_AMP

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

PP1V5_S0

4V5_NR

4V5_REG_EN

HDA_SDIN0

AUD_SPDIF_OUT

PP4V5_AUDIO_ANALOG

PP1V5_S0

GND_AUDIO_HP_AMP

62 OF 109

57 OF 86

57

57 58 61 62

6 7

30 32 42 43 44 46 57 59 60

61 66 67 72

81

57 57

57

57 58 61 62

57 59 61

7

16 20 22 26 42 57 71

57 59 61

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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SIZE

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PAGE TITLE

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A

D

2 1

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

D

B

8 7 5 4 2 1

VIN = 2VRMS, CODEC VIN = 1.14 VRMS

LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS FC_HP = 3.6 HZ

NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS) FC_LP = 43KHZ

61

57

57 61 62

20%

X5R-CERM

CRITICAL

2.2UF

10V 402

C6301

1 2

CRITICAL

402

X5R-CERM

2.2UF

10V

20%

C6302

1 2

X5R-CERM

CRITICAL

2.2UF

10V 402

20%

C6312

1 2

CRITICAL

X5R-CERM

20% 10V

402

2.2UF

C6311

1 2

7.87K

1%

402

1/16W MF-LF

R6301

1 2

7.87K

1%

402

1/16W MF-LF

R6311

1 2

21.5K

1%

402

1/16W MF-LF

R6302

1

2

21.5K

1%

402

1/16W MF-LF

R6312

1

2

10%

820PF

402

CERM

50V

NOSTUFF

C6303

1

2

10%

820PF

402

CERM

50V

NOSTUFF

C6313

1

2

1/16W MF-LF 402

1%

10

R6300

1

2

AUDIO: LINE INPUT FILTER

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_REF

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_GND

AUD_LI_L_DIV

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_P_L

AUD_LI_R

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_P_R

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_L

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_R_DIV

GND_AUDIO_CODEC

63 OF 109

58 OF 86

SVSS

INL

SHDN*

INR

VDD

PVSS

PGND

SGND

THRM

OUTR

OUTL

C1P C1N

PAD

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

APN: 353S1637

MAX9724 GAIN/FILTER COMPONENTS

NC

FOR PROTO2, STUFF R6521 AND NO STUFF R6520 AND R6522 UNTIL

HP/LO AMP

AV_PB = -1V/V, FC_LPF = 35.2KHZ

NC

RE-TASKABLE IO SW SUPPORT AVAILABLE (FORCES IO INTO OUTPUT MODE).

16V

CRITICAL

X7R-CERM

402

10%

0.1UF

C6500

1

2

5% 1/16W MF-LF

402

39

R6500

1

2

CRITICAL

402

X7R-CERM

16V

10%

0.1UF

C6510

1

2

1/16W MF-LF

402

39

5%

R6510

1

2

CRITICAL

TQFN

MAX9724A

U6500

3

1

6

8

11

10

247

5

9

13

12

CRITICAL

10%

1UF

X5R

10V

402

C6522

1

2

10V

10%

1UF

CRITICAL

X5R 402

C6523

1

2

CRITICAL

10V X5R

10%

1UF

402

C6524

1

2

6.3V

20%

10UF

X5R 603

C6521

1

2

10%

X7R-CERM

0.1UF

16V

402

C6520

1

2

FERR-120-OHM-1.5A

0402-LF

L6520

1 2

5%

MF-LF

1/16W

100K

402

R6522

1

2

1/16W MF-LF

13.7K

1%

402

R6531

1 2

1/16W

1%

13.7K

MF-LF

402

R6530

1 2

MF-LF

1/16W

13.7K

1%

402

R6533

1 2

MF-LF

1/16W

13.7K

1%

402

R6532

1 2

5%

330PF

CRITICAL

COG

50V

402

C6530

1 2

50V COG

330PF

5%

CRITICAL

402

C6531

1 2

0

MF-LF

402

1/16W

5%

R6520

1 2

0

MF-LF

1/16W

NO STUFF

5%

402

R6521

1

2

57 59

57

59 61

1%

2.21K

1/16W MF-LF 402

R6523

1

2

1%

2.21K

1/16W MF-LF 402

R6524

1

2

57 59

57 59 61

57 59

SYNC_DATE=08/10/2010

SYNC_MASTER=LENG_K90I

AUDIO: HEADPHONE FILTER

GND_AUDIO_HP_AMP

AUD_GPIO_1_R

AUD_LO_AMP_INR_M

MAX9724_SVSS

MAX9724_C1N

MAX9724_C1P

AUD_LO_AMP_INR_M

AUD_HP_ZOBEL_L

AUD_HP_PORT_L

AUD_HP_PORT_R

AUD_HP_ZOBEL_R

GND_AUDIO_HP_AMP

AUD_LO_AMP_OUTR

AUD_HP_PORT_R

AUD_HP_PORT_L

AUD_LO_AMP_INL_M

PP5V_S3

AUD_LO_AMP_OUTL

AUD_LO_AMP_INL_M

AUD_GPIO_1

AUD_LO_AMP_OUTL

MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM

AUD_LO_AMP_OUTR

AUD_PP5V_F

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

65 OF 109

59 OF 86

57 59 61

59

6 7

30 32 42 43 44 46 57 60

61 66 67 72

59

IN

IN-

IN+

OUT+ OUT-

GAIN

SHDN*

PVDD

NC

PGND

IN-

IN+

OUT+ OUT-

GAINSHDN*

PVDD

NC

PGND

IN-

IN+

OUT+ OUT-

GAIN

SHDN*

PVDD

NC

PGND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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SIZE

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

GAIN

SUB

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

SATELLITE & SUB TWEETER AMPLIFIER

APN:353S2888

SATELLITE

3DB

80 HZ < FC < 132 HZ

169 HZ < FC < 282 HZ

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

0.0047UF

25V

CRITICAL

CERM

402

10%

C6610

1 2

57 85

X5R

10%

0.1UF

16V

402

C6607

1

2

FERR-1000-OHM

0402

L6620

1 2

FERR-1000-OHM

0402

L6610

1 2

FERR-1000-OHM

0402

L6630

1 2

57 85

402

10% X5R

0.1UF

16V

C6609

1

2

X5R

10%

0.1UF

16V

402

C6608

1

2

2012-LLP

47UF

TANT1

6.3V

20%

CRITICAL

C6601

1

2

20%

100UF

6.3V TANT CASE-AL1

CRITICAL

C6603

1

2

TANT1

47UF

20%

6.3V

2012-LLP

CRITICAL

C6605

1

2

5%

1/16W

402

MF-LF

0

R6610

1 2

57

402

5% 1/16W

100K

MF-LF

R6611

1

2

0402

FERR-1000-OHM

L6611

1 2

57 85

FERR-1000-OHM

0402

L6621

1 2

57 85

FERR-1000-OHM

0402

L6631

1 2

57 85

0.0047UF

25V

CRITICAL

10% CERM

402

C6611

1 2

0.0047UF

25V

CRITICAL

CERM

10%

402

C6630

1 2

0.0047UF

25V

CRITICAL

10%

CERM 402

C6631

1 2

CRITICAL

0402

25V

X7R

0.022UF

10%

C6621

1 2

10%

0402

0.022UF

X7R

25V

CRITICAL

C6620

1 2

MAX98300

CRITICAL

WLP

U6610

C3

B3

A3

B2

C1

B1

A2

A1

C2

MF-LF

100K

1/16W

5%

402

R6612

1

2

MF-LF

100K

1/16W

5%

SPKAMP2_GAIN

402

R6622

1

2

CRITICAL

MAX98300

WLP

U6620

C3

B3

A3

B2

C1

B1

A2

A1

C2

MAX98300

CRITICAL

WLP

U6630

C3

B3

A3

B2

C1

B1

A2

A1

C2

MF-LF

100K

1/16W

5%

402

R6632

1

2

AUDI0: SPEAKER AMP

SYNC_DATE=08/10/2010

SYNC_MASTER=LENG_K90I

SSM2315_R_P

PP5V_S3

AUD_GPIO_3

SPKRAMP_SHDN

PP5V_S3

SPKRAMP_INR_P

AUD_LO1_P_R

SPKRAMP_SHDN

AUD_LO1_N_R

AUD_LO2_P_L

SPKRAMP_INL_P

MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_P_OUT

MIN_LINE_WIDTH=0.30 mm

SPKAMP3_GAIN

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_N_OUT

SPKRAMP_SHDN

SSM2315_L_N

SPKRAMP_INL_N

SSM2315_L_P

SSM2315_SUB_N

AUD_LO2_N_L

MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_P_OUT

MIN_LINE_WIDTH=0.30 mm

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_R_N_OUT

SPKRAMP_SUB_N_OUT

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_SUB_P_OUT

MIN_NECK_WIDTH=0.20 MM

SSM2315_SUB_P

AUD_LO2_P_R

SPKRAMP_INSUB_P

SSM2315_R_N

SPKRAMP_INSUB_N

AUD_LO2_N_R

SPKRAMP_INR_N

SPKAMP1_GAIN

66 OF 109

60 OF 86

85

6 7

30 32 42 43 44 46 57 59

60 61 66 67 72

60

6 7

30 32 42 43 44 46 57 59

60 61 66 67 72

6 7

30 32 42 43 44 46 57 59

60 61 66 67 72

85

60

85

6

61 85

6

61 85

60

85

6

61 85

6

61 85

6

61 85

6

61 85

85

IN

IN IN

IN

OUT

BI

RIGHT

MIC

AUDIO

GND

LEFT

SWITCH

DETECT

B - VCC

POF

SHIELD

SHELL

PINS

C - GND

A - VIN

OPERATING VOLTAGE 3.3

IN

OUT

IN

VCC

COM1

COM2

EN*

NC1

CB

NO1

NEG

GND

NO2

NC2

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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A

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX

ANALOG MIC CONNECTOR

APN:518S0521

C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES

SPEAKER CONNECTOR

ANALOG AUDIO IO SWITCH

APN: 353S2803

GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED

APN:518S0519

APN:518S0520

APN:514-0671

CHASSIS GND STITCHES

GND STUFFING OPTIONS FOR CMOS SWITCH

GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED

(AUD_CONN_GND)

CERM

6.3V

10%

402

1UF

C6700

1

2

6

60 85

6

60 85

6

60 85

6

60 85

6

60 85

6

60 85

CRITICAL

M-RT-SM

78171-0004

J6703

5

6

1

2

3

4

78171-0002

M-RT-SM

CRITICAL

J6702

3

4

1

2

CRITICAL

6.8V-100PF

402

DZ6704

1

2

402

6.8V-100PF

CRITICAL

DZ6703

1

2

6.8V-100PF

CRITICAL

402

DZ6700

1

2

CRITICAL

402

6.8V-100PF

DZ6705

1

2

M-RT-SM

78171-0003

CRITICAL

J6701

4

5

1

2

3

NO STUFF

33PF

50V

402

5%

CERM

C6761

1

2

NO STUFF

5%

402

33PF

50V CERM

C6760

1

2

NO STUFF

50V

5%

33PF

402

CERM

C6762

1

2

33PF

402

CERM

50V

5%

NO STUFF

C6763

1

2

MF-LF

1/16W

5%

0

402

R6760

1 2

FERR-1000-OHM

0402

L6702

1 2

FERR-1000-OHM

0402

L6701

1 2

62

402

6.8V-100PF

CRITICAL

DZ6701

1

2

57

10%

0.0033UF

50V CERM

402

C6711

1

2

SM

XW6700

1 2

SM

XW6701

1 2

61

0

5% 1/16W MF-LF

402

R6714

1 2

1/16W MF-LF

402

0

5%

R6715

1 2

SM

XW6711

1 2

SM

XW6710

1 2

0

5% 1/16W MF-LF

402

R6717

1 2

0

5%

1/16W

402

MF-LF

R6718

1 2

402

5%

0

1/16W MF-LF

R6719

1 2

MF-LF

1/16W

5%

0

402

R6716

1 2

61

100K

1/16W MF-LF

5%

402

R6721

1

2

402

X5R

1UF

10V

10%

C6710

1

2

F-RT-TH

CRITICAL

SPDIF-TXRX-K24

J6700

5

4

10 11

12 13

7

8 9

1

6

3

2

1/16W

24K

MF-LF

5%

402

R6712

1

2

5%

24K

MF-LF

1/16W

402

R6713

1

2

NOSTUFF

MF-LF

5%

0

1/16W

402

R6727

1 2

58

59

57

SM

XW6702

1 2

MAX14560EWC+

WLP

CRITICAL

U6700

C2

B4

B1

B2

B3

C3

C4 C1

A2

A4 A1

A3

57

FERR-120-OHM-1.5A

0402-LF

CRITICAL

L6703

1 2

FERR-220-OHM

CRITICAL

0402

L6705

1 2

CRITICAL

0402

FERR-220-OHM

L6704

1 2

62

10K

402

5%

MF-LF

1/16W

R6700

1 2

1/16W

5%

MF-LF

4.7

402

R6701

1 2

100PF

402

5% CERM

50V

C6701

1

2

SYNC_MASTER=LENG_K90I

AUDIO: JACK

SYNC_DATE=08/10/2010

VOLTAGE=0V

GND_CHASSIS_AUDIO_JACK

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM

AUD_GPIO_2

VOLTAGE=0V

AUD_SWITCH_GND

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_CONNJ1_SLEEVEDET

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

AUD_CONN_GND

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM

AUD_CONN_R

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.2MM

AUD_CONN_L

SPKRAMP_SUB_P_OUT

AUD_LI_L_SWITCH

SWITCH_CP

AUD_LI_R_SWITCH

AUD_LO_AMP_OUTR_SWITCH

AUD_CONNJ1_MIC

SPKRAMP_SUB_N_OUT

SPKRAMP_L_N_OUT

HS_MIC_HI

BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI

AUD_CONN_GND

AUD_LI_GND

SPKRAMP_L_P_OUT

SPKRAMP_R_P_OUT

GND_AUDIO_HP_AMP

AUD_HP_PORT_REF

AUD_J1_TIPDET_R

GND_AUDIO_CODEC

AUD_LO_AMP_OUTL_SWITCH

AUD_CONNJ1_TIPDET

AUD_CONN_L

AUD_LI_R

AUD_LI_L

AUD_J1_SLEEVEDET_R

AUD_CONNJ1_RING

PP3V3_S0

SPKRAMP_R_N_OUT

AUD_LO_AMP_OUTL

AUD_LO_AMP_OUTR

PP5V_S3

AUD_CONNJ1_SLEEVE

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_CONN_R

AUD_CONNJ1_TIP

HS_MIC_LO

AUD_SPDIF_OUT

67 OF 109

61 OF 86

61

6

62

6

62

6

62

61

58

57 59

57 58 62

6 7 8

12 16 17 18 19 20

22 23 26 27 29 33 36 37

40 41 42 46 48 49 50 51

52 54 57 62 71 72 73 74

75 77 85

6 7

30 32 42 43 44 46 57 59

60 66 67 72

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

IN

OUT

IN

OUT

IN

BI

IN

OUT

IN

D

SG

D

SG

CS

HDET

AGND

DGND

ENABLE

AVDD

SDA

BYPASS

DETECT

MICBIAS

INT*

SCL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

0X0D (13,B,RIGHT)

PULLUPS ON MCP PAGE

PORT A DETECT (HEADPHONES)

NC

APN:376S0613

HP=80HZ, LP=8.82KHZ

HP=80HZ

NC

PORT B RIGHT(BUILT-IN MIC)

N/A N/A 0X0D (B)

0X09 (A)AND UI ELEMENT

0X09 (A)

DET ASSIGNMENT

N/A MIKEY

DET ASSIGNMENT

MUTE CONTROL

GPIO_3

N/A

PIN COMPLEX 0X09 (9,A)

0X0A (10) 0X10 (16)

0X0B (11)

N/A

VOLUME

0X02 (2)

0X03 (03)

0X04 (4)

0X08 (8)

VREF MIC_BIAS (80%)

PIN COMPLEX

0X0D (13,V22,B,LEFT)

COUGAR_POINT GPIO5/PIRQH COUGAR_POINT GPIO3/PIRQH

SYSTEM INTERRUPT N/A

N/A

0X06 (6)

AUD_IPHS_SWITCH_EN

AUD_IP_PERIPHERAL_DET

SOUTHBRIDGE RESOURCES

CODEC INPUT SIGNAL PATHS

SATELLITES SUB SPDIF OUT

HP/LINE OUT LINE IN

FUNCTION

AUD_I2C_INT_L

FUNCTION BUILT-IN MIC HEADSET MIC

N/A

COUGAR_POINT GPIO16

SYSTEM GPIO

0X06 (6)

CONVERTER

PORT B DETECT(SPDIF DELEGATE)

0X03 (3)

0X04 (4)

0X05 (5)

0X02 (2)

0X05 (5)

0X0C (12)

GPIO_2 AND GPIO_1

CONVERTER

CODEC OUTPUT SIGNAL PATHS

PORT B LEFT(HEADSET MIC)

APN:353S2640

WCSP MIKEY 1A

MIKEY

PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA

EXTRACTION NOTIFICATION CKT

10V

20% CERM 402

0.1UF

C6801

1

2

5%

402

MF-LF

1/16W

47K

R6802

1 2

61 62

MF-LF

1% 1/16W

39.2K

402

R6806

1

2

MF-LF

402

220K

5%

1/16W

R6803

1 2

220K

5% 1/16W

402

MF-LF

R6804

1

2

16V CERM

0.01UF

402

10%

C6802

1

2

57

61 62

402

1%

MF-LF

1/16W

20.0K

R6805

1

2

SOT563

SSM6N37FEAPE

Q6800

3

5

4

SOT563

SSM6N37FEAPE

Q6800

6

2

1

SOT563

SSM6N37FEAPE

Q6801

3

5

4

SOT563

SSM6N37FEAPE

Q6801

6

2

1

MF

402-1

1%

1/16W

2.4K

R6851

1 2

CRITICAL

50V

27PF

5%

402CERM

C6854

1

2

X5R

0.1UF

CRITICAL

402

25V

10%

C6850

1 2

0.001UF

10%

CRITICAL

CERM

50V 402

C6853

1

2

MF-LF

1/16W

5%

100K

402

R6852

1

2

SM

XW6851

1 2

57

6

61

6

61

6

61

20%

TANT

6.3V

2.2UF

CRITICAL

402-1

C6852

1

2

0402

FERR-1000-OHM

L6851

1 2

0402

FERR-1000-OHM

L6850

1 2

61

MIKEY

2.2K

5%

402

1/16W MF-LF

R6882

1

2

CRITICAL

MIKEY

27PF

5%

50V 402CERM

C6885

1

2

MIKEY

X7R

CRITICAL

0.0082UF

10%

402

25V

C6884

1

2

MIKEY

1/16W MF-LF 402

100K

5%

R6883

1

2

CRITICAL

MIKEY

402

25V

10%

0.1UF

X5R

C6883

1 2

SM

XW6880

1 2

57

MIKEY

1/16W

1K

MF-LF

1%

402

R6881

1

2

1/16W

5%

402

MF-LF

100K

R6880

1

2

MIKEY

CERM402

10%

16V

0.01UF

C6881

1

2

FERR-1000-OHM

MIKEY

0402

L6880

1 2

MIKEY

CRITICAL

20%

2.2UF

6.3V TANT 402-1

C6882

1

2

18

16 23 27 29 31 42 48 77 81

19 23

MF-LF

402

MIKEY

2.2K

5%

1/16W

R6884

1 2

MIKEY

402

25V

10%

X5R

0.1UF

CRITICAL

C6886

1 2

57

10%

402

X5R

25V

0.1UF

CRITICAL

C6851

1 2

100

402

1% 1/16W MF-LF

R6850

1 2

402-1

1/16W

1%

MF

2.4K

R6853

1 2

18

1/16W

0

MF-LF

5%

402

R6861

1 2

10V

20%

402

0.1UF

CERM

C6861

1

2

0402

FERR-1000-OHM

L6862

1 2

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42

46 48 49 50 51 52 54 57 61

62 71 72 73 74 75 77 85

X5R

CRITICAL

MIKEY

10V

10%

1UF

402

C6880

1

2

SOT563

SSM6N37FEAPE

Q6802

6

2

1

SOT563

SSM6N37FEAPE

Q6802

3

5

4

402

MF-LF

1/16W

15K

5%

R6860

1 2

402

20%

0.1UF

CERM

10V

C6860

1

2

402

MF-LF

1/16W

5%

220K

R6864

1

2

MF-LF 402

100K

5% 1/16W

R6865

1

2

300K

402

MF-LF

1/16W

5%

R6801

1

2

WCSP

CD3282A1

MIKEY

CRITICAL

U6880

D2

A2

D1

B2

B1

C2

A3 A1

D3

C1

C3 B3

5%

1/16W

NOSTUFF

402

MF-LF

0

R6885

1 2

SYNC_DATE=08/10/2010

SYNC_MASTER=LENG_K90I

AUDIO: JACK TRANSLATORS

AUD_OUTJACK_INSERT_L

AUD_PERPH_DET_R

GND_AUDIO_CODEC

HS_MIC_HI_RC

MIKEY_HDET

AUD_MIC_INN_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM

PP3V3_S0_AUDIO_F

AUD_J1_TIPDET_R

BI_MIC_HI_F

BI_MIC_SHIELD

PP3V3_S0

GND_AUDIO_CODEC

AUD_PORTB_DET_L

HS_MIC_BIAS

GND_AUDIO_CODEC

AUD_IPHS_SWITCH_EN

HS_MIC_LO

SMBUS_PCH_CLK

AUD_I2C_INT_L

AUD_J1_TIPDET_R

PP3V3_S0_AUDIO_F

AUD_J1_SLEEVEDET_INV

AUD_J1_TIPDET_INV

AUD_SENSE_A

AUD_J1_SLEEVEDET_R

GND_AUDIO_CODEC

HS_SW_DET

MIC_BIAS_FILT

BI_MIC_LO_F

AUD_J1_DET_RC

BI_MIC_HI

GND_AUDIO_CODEC

AUD_CODEC_MICBIAS

AUD_MIC_INN_R

AUD_MIC_INP_R

BI_MIC_LO

GND_AUDIO_CODEC

TIPDET_FILT

PP3V3_S0_AUDIO_F

AUD_PORTA_DET_L

HS_MIC_HI

GND_AUDIO_CODEC

AUD_MIC_INP_L

PP3V3_S0

HS_RX_BP

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.10MM

PP3V3_S0_HS_RX

AUD_IP_PERIPHERAL_DET

SMBUS_PCH_DATA

68 OF 109

62 OF 86

57 58 61 62

62

61 62

57 58 61 62

57 58 61 62 61 62

62

61 62

57 58 61 62

62

57 58 61 62

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

VCC

EXTINT

NC

GND

BI

Y

B

A

BI BI

P3 P4 P5 P6 P7 P8

P1 P2

P9

SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN

NC

BYP

GND

REF

TON

SW

FB

EN

REF3

THRM

VIN

VCC

PAD

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MagSafe DC Power Jack

3.425V "G3Hot" Supply

BATTERY CONNECTOR

1-Wire OverVoltage Protection

TO SMC

NC

516S0523

BIL CONNECTOR

NC

300mA max output

f = 470 kHz

Vout = 3.425

518S0656

353S2776

Supply needs to guarantee 3.31V delivered to SMC VRef generator

518-0375

50V

0.01UF

603

20%

CERM

C6905

1

2

CRITICAL

78048-0573

M-RT-SM

J6900

1

2

3

4

5

CERM

10%

402

0.001UF

50V

C6954

1

2

0.1UF

25V

10%

402

X5R

C6950

1

2

0.1UF

X5R

10% 25V

402

C6951

1

2

CRITICAL

6AMP-24V

1206-1

F6905

1 2

SC-75

CRITICAL

RCLAMP2402B

D6950

3

1

2

20% 10V CERM 402

0.1UF

PLACE_NEAR=U6901.5:1mm

C6908

1

2

MAX9940

SC70-5

U6900

5

2

4

3

1

45

SOT665

TC7SZ08AFEAPE

U6901

2

1

3

5

4

10K

5%

1/16W

402

MF-LF

R6950

1

2

CRITICAL

CPB6312-0101F

F-ST-SM

J6955

1

10

1112

1314

1516

2

34

56

78

9

CERM

402

5%

50V

47PF

C6952

1

2

47PF

5%

50V

CERM

402

C6953

1

2

6

45 48 63 64 84

6

45 48 63 64 84

50V

402

0.001UF

10%

CERM

C6955

1

2

402

1/16W

5%

100

MF-LF

R6961

1 2

BAT-K90-K91-K92

CRITICAL

M-RT-TH

J6950

10

11

12 13

1

2 3

4

5 6

7

8 9

2.0K

402

5%

1/16W

MF-LF

R6929

1 2

NOSTUFF

MF-LF

402

5%

1/16W

100K

R6900

1

2

1UF

603-1

25V X5R

10%

C6960

1

2

47

1%

1/3W

MF

805

R6990

1 2

SOT-323

BAT30CWFILM

D6990

1

2

3

1/8W MF-LF 805

1%

1.00M

R6995

1

2

25V

1UF

X5R

10%

603-1

C6991

1

2

16V

402-1

10%

0.1UF

X5R

C6994

1

2

CRITICAL

DFN

PM6640

U6990

9

4

2

5

1

10

6

11

3

8

7

CRITICAL

33UH-20%-0.44A-0.455OHM

D52LC-SM

L6995

1 2

603

X5R-CERM-1

22UF

20%

6.3V

C6999

1

2

10% 35V

X5R-CERM

4.7UF

0805

C6990

1

2

402-1

16V X5R

0.1UF

10%

C6996

1

2

SYNC_MASTER=JACK_K90I

SYNC_DATE=08/20/2010

DC-In & Battery Connectors

SMBUS_SMC_BSA_SCL

PPVBAT_G3H_CONN

P3V42G3H_REF3

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V

P3V42G3H_FB

ADAPTER_SENSE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20mm

MIN_LINE_WIDTH=1mm

PP18V5_DCIN_FUSE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

PPDCIN_S5_P3V42G3H

P3V42G3H_SW

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

DIDT=TRUE

SMC_BC_ACOK

PPDCIN_G3H

SYS_ONEWIRE

SMBUS_SMC_BSA_SDA

SYS_DETECT_L

P3V42G3H_TON

PPDCIN_G3H

SMC_LID_R

SMC_LID

SMC_BIL_BUTTON_L

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SMC_BC_ACOK_VCC

PP3V42_G3H

PPBUS_G3H

PP3V42_G3H

69 OF 109

63 OF 86

6

45 48 63 64 84

6

64

6

45 46 49 64

7

49 63 64

6 45 48 63 64 84

6

7

49 63 64

6

45 46 53

6

45

46

6 7

26 43 45 46 47 48 53 63 64

73

6 7 8

36 40 49 50

64 77

6 7

26 43 45 46 47 48 53 63 64

73

IN

BI

IN

OUT

OUT OUT

AMON BMON ACOK

LGATE

PHASE

BOOT

SGATE AGATE

CSIP CSIN

DCIN

VNEG CSOP CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE ICOMP VCOMP

ACIN

SDA VFRQ CELL

VHST

SCL

SMB_RST_N

G

D

S

G

D

S

G

D

SYM-VER-2

S

G

D

S

G

D

S

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

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A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

36V/V

(OD)

20V/V

Inrush Limiter

TO SYSTEM

Max Current = 8A

(L7030 limit)

ACIN pin threshold is 3.2V, +/- 50mV

f = 400 kHz

K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT

Input impedance of ~40K meets

(CHGR_CSO_N)

(GND)

(CHGR_CSO_P)

(PPVBAT_G3H_CHGR_R) (PPVBAT_G3H_CHGR_R)

(CHGR_BGATE)

TO/FROM BATTERY

(CHGR_DCIN)

sparkitecture requirements

(CHGR_AGATE)

353S2929

Divider sets ACIN threshold at 13.55V

(AGND)

30mA max load

Float CELL for 1S

FROM ADAPTER

(CHGR_SGATE)

Reverse-Current Protection

0.068UF

10%

402

10V CERM

C7042

1

2

45 46

47

10% 402

X5R

1UF

10V

C7002

1

2

10%

402

16V

0.01UF

CERM

C7011

1

2

10% X5R

1UF

10V 402-1

C7000

1

2

PLACE_NEAR=U7000.29:1mm PLACE_NEAR=U7000.22:1mm

SM

XW7000

1 2

X5R

25V 603

0.22UF

20%

C7005

1

2

10%

402

X5R

16V

1UF

C7050

1

2

73

6

45 48 63 84

6

45 48 63 84

470PF

CERM 402

10% 50V

C7016

1

2

1/16W

402

MF-LF

0

5%

R7000

1 2

NO STUFF

100K

402

5% MF-LF

1/16W

R7002

1

2

402

MF-LF

1/16W

5%

4.7

R7001

1 2

5%

MF-LF

20

402

1/16W

R7005

1 2

402

X5R

10V

10%

1UF

C7001

1

2

SOT-323

CRITICAL

BAT30CWFILM

D7005

1

2

3

X5R

10%

0.1UF

402

25V

C7085

1

2

MF-LF

470K

1/16W

402

1%

R7085

1

2

1K

BATT_2S

MF-LF

402

1/16W

1%

R7013

1

2

1%

332K

MF-LF

402

1/16W

R7086

1

2

45 46 49 63

50

10%

402

0.001UF

CERM

50V

C7026

1

2

402

1/16W5%MF-LF

2.2

R7051

1 2

402

0

1/16W5%MF-LF

R7052

1 2

1/16W MF-LF

9.31K

402

1%

R7011

1

2

CERM

10% 10V

402

PLACE_NEAR=U7000.25:2mm

0.22UF

C7025

1

2

10%

0.1UF

402

X5R

25V

C7022

1

2

10%

0.047UF

10V 402

CERM

C7020

1

2

402

10% X5R

25V

0.1UF

C7021

1

2

402

5%

MF-LF

1/16W

10

R7022

1 2

402

1/16W

5%

MF-LF

10

R7021

1 2

NO STUFF

470PF

402

CERM

50V

10%

C7039

1

2

603

5%

MF-LF

1/10W

180

NO STUFF

R7039

1

2

10% X5R

25V

1UF

603-1

C7055

1

2

10%

0.1UF

402-1

X5R

16V

C7056

1

2

402

16V

0.01uF

10%

CERM

C7057

1

2

22UF

CASE-D2-SM

20%

CRITICAL

25V POLY-TANT

C7040

1

2

CRITICAL

20% 25V

CASE-D2-SM

POLY-TANT

22UF

C7030

1

2

CRITICAL

22UF

25V POLY-TANT

20%

CASE-D2-SM

C7031

1

2

3.01K

MF-LF

1/16W

402

1%

R7016

1

2

603-1

X5R

10%

1UF

25V

C7035

1

2

0.001UF

10% 402

X7R

50V

C7045

1

2

1206

8AMP-24V

CRITICAL

F7040

1 2

10% X5R

603-1

1UF

25V

C7036

1

2

10% 402

X7R

0.001UF

50V

C7037

1

2

62K

1/16W MF-LF 402

5%

R7081

1

2

1/16W MF-LF 402

100K

5%

R7080

1

2

IHLP4040DZ-SM

4.7UH-9.5A

CRITICAL

L7030

1 2

CRITICAL

TQFN

ISL6259

U7000

3

14

1

9

16

15

25

6

27

28

17

18

2

5

21

22

23

11 10

26

13

29

24

7

19

20

4

12

8

MF

1W

0.5%

0.02

0612-1

CRITICAL

R7020

123

4

MF-LF

1/16W

402

5%

0

R7025

1

2

BATT_3S

0.5%

0.01

1W MF

0612-3

CRITICAL

R7050

1 2 3 4

402

1/16W MF-LF

1%

30.1K

R7010

1

2

402

MF-LF

1/16W

100K

1%

R7015

1

2

5%

330PF

COG

50V 402

C7015

1

2

OMIT

CRITICAL

AON6405L

DFN5X6

Q7085

5

4

123

DFN5X6

AON6405L

CRITICAL

OMIT

Q7080

5

4

123

OMIT

DFN5X6

CRITICAL

AON6403L

Q7055

5

4

1

2

3

OMIT

CRITICAL

RJK03E1DNS

HWSON-8

Q7030

5

4

1 2 3

RJK03E1DNS

HWSON-8

CRITICAL

OMIT

Q7035

5

4

1 2 3

BATT_3S

402

1/16W

1K

MF-LF

1%

R7012

1

2

CRITICAL

1

Q7035

376S0966

RJK03E1DNS

SYNC_DATE=10/11/2010

SYNC_MASTER=JACK_K90I

PBus Supply & Battery Charger

SI7149DP

Q7085

1

376S0845 CRITICAL

SI7149DP

Q7080

1

CRITICAL376S0845

1

R7050

CRITICAL107S0129

BATT_2S

RES,5MOHM,1%,1W,0612,4-TERM

SI7137DP

Q7055

1

CRITICAL376S0761

CRITICAL

1

Q7030

RJK03E1DNS

376S0966

MIN_NECK_WIDTH=0.4 mm

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.6V

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

CHGR_LGATE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

GND_CHGR_AGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V

PPVBAT_G3H_CHGR_R

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H_CHGR

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_SGATE_DIV

CHGR_BOOT

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.2 mm

CHGR_PHASE_RC

DIDT=TRUE

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V

PPDCIN_G3H_INRUSH_FET

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

CHGR_VCOMP_R

CHGR_VNEG

CHGR_VCOMP

CHGR_CELL CHGR_ACIN

PP3V42_G3H

CHGR_VNEG_R

PP5V1_CHGR_VDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=5.1V

SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA

CHGR_AMON

CHGR_CSO_P

GND_CHGR_AGND

SMC_RESET_L

CHGR_CSI_R_N

CHGR_CSI_R_P

CHGR_VFRQ

CHGR_CSO_R_P CHGR_CSO_R_N

CHGR_DCIN_D_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

CHGR_BOOT_R

VOLTAGE=5.1V

MIN_NECK_WIDTH=0.2 mm

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm

CHGR_CSI_P

CHGR_AGATE

CHGR_SGATE

PPDCIN_G3H

PPBUS_G3H

CHGR_RST_L

SMC_BC_ACOK

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_PHASE

CHGR_DCIN

CHGR_UGATE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

CHGR_CSI_N

CHGR_BGATE

CHGR_BMON

CHGR_CSO_N

CHGR_ICOMP

70 OF 109

64 OF 86

64

6

63

6 7

26 43 45 46 47 48 53 63

73

84

64

85

50 85

84

7

49 63

6 7 8

36 40 49 50 63 77

84

OUT

IN

FB

EN

PVCC

VCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGND

GND

SET0

SET1

VID0

VID1

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

System Agent Power Supply

6A Max Output f = 300 kHz

(VCCSAS0_VO)

(VCCSAS0_OCSET)

1000PF

25V NP0-C0G

5% 402

C7105

1

2

402

16V

10%

0.022UF

CERM-X5R

C7103

1

2

73

5%

402

0

MF-LF

1/16W

R7103

1

2

603

20% X5R

10V

10UF

C7101

1

2

402

MF-LF

1/16W

47.5K

1%

R7148

1

2

402

1K

1% 1/16W MF-LF

R7142

1

2

402

1K

1% 1/16W MF-LF

R7141

1

2

25V

5%

402

NP0-C0G

1000PF

C7140

12

2.2

1/10W MF-LF

5%

603

R7130

1

2

1UF

402

X5R

10% 16V

C7130

1

2

39UF-0.027OHM

20%

POLY

CRITICAL

B1A-SM

16V

C7120

1

2

FDV0630H-SM

1.0UH-7.7A

CRITICAL

L7100

1 2

0.001

1% 1W

0612

MF-1

CRITICAL

R7140

21 43

402

25V X5R

0.1UF

10%

C7121

1

2

1000PF

PLACE_NEAR=Q7100.2:1.5mm

402

NP0-C0G

5% 25V

C7122

1

2

1/16W MF-LF 402

2.2

5%

R7101

1

2

UTQFN

CRITICAL

ISL95870AH

U7100

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

SIZ700DT

POWERPAIR-6X3.7

CRITICAL

Q7100

1

6

4 5

2 3 7

8

140K

1/16W MF-LF

1%

402

R7147

1

2

113K

MF-LF

1/16W

1%

402

R7146

1

2

12

2.2UF

10% 16V

603

X5R

C7102

1

2

SYNC_DATE=08/19/2010

SYNC_MASTER=JACK_K90I

System Agent Supply

PPBUS_S5_HS_COMPUTING_ISNS

CPU_VCCSASENSE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VCCSAS0_LL

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

VCCSAS0_DRVH

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

VCCSAS0_DRVL

GATE_NODE=TRUE DIDT=TRUE

PVCCSA_EN

VCCSAS0_FSEL

VCCSAS0_CS_N

VCCSAS0_CS_P

MIN_LINE_WIDTH=0.3 mm

VCCSAS0_BOOT_RC

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

PPVCCSA_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVCCSA_S0_CPU

VCCSAS0_SET0

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

VCCSAS0_VBST

MIN_LINE_WIDTH=0.3 mm

PP5V_S0

PVCCSA_PGOOD

VCCSAS0_OCSET

VCCSAS0_VO

VCCSAS0_SREF

MIN_LINE_WIDTH=0.6 mm VOLTAGE=5V

PP5V_S0_VCCSAS0_VCC

MIN_NECK_WIDTH=0.2 mm

CPU_VCCSA_VID<1>

VCCSAS0_SET1

VCCSAS0_FB

71 OF 109

65 OF 86

7

50 67 68 69 70

12

85

6 7

12 15

6 7

22 42 47 52 54 68 70 72

73 77

IN

D

SG

D

SG

D1

G1

S2

G2

S1/D2

NC

G

D

S

G

D

S

DRVH1

SKIPSEL

VBST1

GND

THRM_PAD

ENTRIP1

VFB1

VO1

DRVL1

LL1

EN0

VCLK

ENTRIP2

PGOOD

VO2

VFB2

DRVL2

LL2

DRVH2

VBST2

VREG5

VREG3

VREF

VIN

TONSEL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PWM FREQ. = 375 KHZ

VOUT = (2 * RC / RD) + 2

SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.

PWM FREQ. = 300 KHZ

MAX CURRENT = 12.947A

MAX CURRENT = 7.45A

VOUT = (2 * RA / RB) + 2

5V_S3/3.3V_S5 POWER SUPPLY

<RB>

6.3V X5R

20%

603

10UF

C7273

1

2

SM

PLACE_NEAR=U7200.25:1 MM

XW7201

1 2

73

SSM6N37FEAPE

SOT563

Q7221

6

2

1

SSM6N37FEAPE

SOT563

Q7221

3

5

4

PLACE_NEAR=C7291.1:1 MM

SM

XW7202

12

PLACE_NEAR=L7260.1:1 MM

SM

XW7203

12

PLACE_NEAR=C7251.1:1 MM

SM

XW7205

12

PLACE_NEAR=L7220.2:1 MM

SM

XW7204

12

402

5%

1/16W MF-LF

100K

R7273

1

2

402

X5R

16V

10%

0.1UF

C7220

12

CERM

0.001UF

20%

402

50V

C7282

1

2

402

CERM

20% 50V

0.001UF

C7242

1

2

0.001UF

402

20% CERM

50V

C7293

1

2

20%

402

CERM

50V

0.001UF

C7253

1

2

CRITICAL

B1A-SM

20% 16V POLY

39UF-0.027OHM

C7240

1

2

220UF

20%

6.3V ELEC D1A-SM

CRITICAL

C7291

1

2

CRITICAL

B1A-SM

150UF

20%

6.3V POLY

C7251

1

2

39UF-0.027OHM

B1A-SM

POLY

16V

20%

CRITICAL

C7280

1

2

MF-LF

0

1/16W

5%

402

R7220

1 2

IHLP2525CZ

4.7UH-5.5A

CRITICAL

L7220

1 2

PCMB104E4R7-SM

CRITICAL

4.7UH-13A-15MOHM

L7260

1 2

5%01/16W

402

MF-LF

R7260

1 2

RJK0384DPA

WPAK

CRITICAL

Q7220

2

1

6

7

345

1%

88.7K

1/16W MF-LF 402

R7271

1

2

OMIT

CRITICAL

HWSON-8

RJK03E1DNS

Q7260

5

4

123

HWSON-8

RJK03E0DNS

CRITICAL

OMIT

Q7261

5

4

123

6.3V 603

X5R

20%

10UF

C7250

1

2

1/16W MF-LF 402

1%

6.49K

R7270

1 2

10K

1/16W MF-LF

1%

402

R7269

1 2

1UF

25V

10% X5R

603-1

C7241

1

2

X5R

0.1UF

16V

10%

402

C7260

12

15.0K

1% MF-LF

1/16W 402

R7267

1 2

1/16W MF-LF 402

1%

10K

R7268

1 2

603-1

25V X5R

10%

1UF

C7281

1

2

20%

10UF

X5R

10V 603

C7290

1

2

P3V3S5_VFB

QFN

TPS51125

CRITICAL

U7200

21 10

19 12

13

1 6

15

20 11

23

14

25

4

22

9

18

2 5

16

24

7

3

8

17

MF-LF

1% 1/16W

402

75K

R7272

1

2

1UF

25V 603-1

X5R

10%

C7272

1

2

10V 603

20% CERM

1UF

C7270

1

2

CERM

10V 402

10%

0.22UF

C7271

1

2

5V/3.3V SUPPLY

SYNC_MASTER=JACK_K90I

SYNC_DATE=10/04/2010

Q7261

1

CRITICAL

RJK03E0DNS

376S0895

Q7260

CRITICAL

1

RJK03E1DNS

376S0966

P5VS3_EN_L

MIN_NECK_WIDTH=0.2 MM

GND_5V3V3S5_SGND

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=0V

P5VS3_VO1

PPBUS_S5_HS_OTHER_ISNS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

P5VS3_DRVL

P5VS3_LL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

PP5V_S3

PPBUS_S5_HS_OTHER_ISNS

P5VS3_DRVH

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

P3V3S5_VBST_R

P5VS3_VBST_R

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

P5VS3_VBST

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

P3V3S5_VBST

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

P3V3S5_DRVL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

P3V3S5_DRVH

P3V3S5_LL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

PP3V3_S5

P3V3S5_VO2

PPBUS_S5_HS_OTHER_ISNS

P3V3S5_ENTRIP

P5V3V3_PGOOD

5V3V3_REG_EN

P5VP3V3_REG3

P5V3V3_REG_EN

P5VS3_VFB

PP5V_S5

P5VP3V3_VREF

5V_S3_VFB_XW7203

3V3S5_VFB_R7270

P3V3S5_EN_L

P5VS3_ENTRIP

72 OF 109

66 OF 86

7

50 66

6 7

30 32 42 43

44 46 57 59 60 61

67 72

7

50 66

6 7 8

17 19 20 22 23

24 26 30 46 56 72 73

74 76 85

73

7

54 72

IN

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

IN

G

D

S

G

D

S

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

14.1A max output (Q7335 limit)

VTT Enable

f = 400 kHz

Vout = 1.5V

(DDRREG_DRVL)

10mA max load

(DDRREG_VDDQSNS)

(DDRREG_DRVH)

C7360, C7361 close to memory

VDDQ/VTTREF Enable

(DDRREG_LL)

PLACE_NEAR=U7300.12:1mm

10V

10UF

X5R

20%

603

C7300

1

2

25V

10%

603-1

X5R

1UF

C7332

1

2

10%

0.1UF

X5R

25V 402

C7325

1 2

50V

10% X7R

0.001UF

402

C7333

1

2

CRITICAL

20%

270UF

TANT

2V

CASE-B4-SM

C7340

1

2

CASE-B4-SM

2V

TANT

270UF

20%

CRITICAL

C7341

1

2

6.3V

20%

603

X5R

10UF

C7345

1

2

0.001UF

X7R 402

10% 50V

C7346

1

2

PLACE_NEAR=L7330.2:1mm

SM

XW7301

1

2

43 73

TPS51916

QFN

CRITICAL

U7300

14

11

7

19

10

20

8

17

16

13

21

18

12 15

9

2

6

3

4

5

1

8

SM

PLACE_NEAR=C7361.1:3mm

XW7360

1 2

PLACE_NEAR=U7300.21:1mm

SM

XW7300

1

2

10%

402

0.22UF

CERM

10V

C7350

1

2

PLACE_NEAR=C3101.1:1mm

603

CRITICAL

6.3V

20%

10UF

X5R

C7360

1

2

8

30

0.1UF

PLACE_NEAR=U7300.6:1mm

402

10% 16V X5R

C7315

1

2

PLACE_NEAR=C3101.1:3mm

20%

6.3V

CRITICAL

10UF

X5R 603

C7361

1

2

PLACE_NEAR=U7300.19:3mm

200K

1%

402

1/16W MF-LF

R7317

1

2

20.0K

1/16W MF-LF 402

1%

PLACE_NEAR=U7300.8:5mm

R7315

1

2

100K

MF-LF 402

1% 1/16W

PLACE_NEAR=U7300.8:5mm

R7316

1

2

0.01UF

10% 16V CERM

PLACE_NEAR=U7300.8:1mm

402

C7316

1

2

16V

20%

B1A-SM

POLY

39UF-0.027OHM

CRITICAL

C7331

1

2

10UF

PLACE_NEAR=U7300.2:1mm

603

20% X5R

10V

C7301

1

2

1/16W

0

5%

MF-LF

402

R7325

1 2

PLACE_NEAR=U7300.18:3mm

95.3K

402

MF-LF

1/16W

1%

R7318

1

2

0.88UH-20%-19A-2.3MOHM

CRITICAL

MPCG1040LR88-SM

L7330

1 2

NO STUFF

CASED2E-SM

CRITICAL

16V POLY-TANT

33UF

20%

C7334

1

2

CRITICAL

39UF-0.027OHM

20% 16V POLY B1A-SM

C7330

1

2

3.3X3.3-QFN-COMBO

CSD58858Q3

CRITICAL

OMIT

Q7330

5

4

1 2 3

CRITICAL

3.3X3.3-QFN-COMBO

CSD58858Q3

OMIT

Q7335

5

4

1 2 3

CRITICAL

Q7335

FDMC2514SDC

1

376S0928

1

CRITICAL

Q7330

CSDS58858Q3

376S0790

SYNC_DATE=10/11/2010

SYNC_MASTER=JACK_K90I

1.5V DDR3 Supply

ALL

128S0218128S0299

ALL

128S0218128S0093

DDRREG_LL

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.17 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DDRREG_DRVL

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

DDRREG_VDDQSNS

PP1V5_S3

GATE_NODE=TRUE

DDRREG_DRVH

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DDRREG_FB

PPBUS_S5_HS_COMPUTING_ISNS

MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST

MIN_LINE_WIDTH=0.6 mm

PP0V75_S0_DDRVTT

DDRREG_1V8_VREF

PP5V_S3

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST_RC

TP_DDRREG_PGOOD

PP1V5_S3

DDRREG_VTTSNS

DDRREG_TRIP

DDRREG_MODE

PPVTTDDR_S3

DDRREG_EN

MEMVTT_EN

GND_DDRREG_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

73 OF 109

67 OF 86

6 7

27 29 30 67 72

31

7

50 65 68 69 70

6 7

30 32 42 43 44 46 57 59

60 61 66 72

6 7

27 29 30 67 72

IN IN IN

EN

VDIO

VDDA

IMAXA

VDDB

DRVPWMA

VCC

POKB

TON

BSTA1

DHA1 LXA1 DLA1

CSPA1

CSPAAVE

FBA

CSNA

BSTA2

CSPA2

DHA2 LXA2 DLA2

BSTB

LXB

DHB

CSPB1

DLB

CSNB

FBB

POKA

CSPA3 VRHOT*

CLK ALERT*

THERMA THERMB

SR

IMAXB

THRM

GNDSA

GNDSB

PAD

OUT OUT

IN

OUT

OUT OUT OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT

OUT

IN

OUT

NC

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Need symbol to be re-drawn to clean up this page

1/16W MF-LF

5%

10

402

R7401

1 2

20%

2.2UF

X5R-CERM

10V

402

C7401

1

2

PLACE_NEAR=U7400.24:2mm

2.2UF

20%

X5R-CERM

10V

402

C7402

1

2

12 78

50V CERM

100PF

402

NO STUFF

5%

C7414

1

2

MF-LF

5%

402

300

1/16W

R7406

1 2

402

1/16W

1

MF-LF

5%

R7410

1 2

NO STUFF

0.039UF

10V

10%

X5R-CERM

0402

C7408

1 2

NO STUFF

1%

MF-LF

1/16W

40.2K

402

R7409

1 2

QFN

MAX17511

CRITICAL

OMIT

U7400

17

20

28

11

18

37

9

36

38

39

35

8

22

26

13

23

25

14

31

1

4

6

3

7

29 30

21

27

12

19

10

32

33 34

41

2

402415

16

5

26

73

10 46 78

69

69 85

SM

XW7400

12

X5R-CERM

10V

20%

2.2UF

402

PLACE_NEAR=U7400.15:2mm

C7403

1

2

NO STUFF

200K

MF-LF

1%

402

1/16W

R7464

1

2

402

5%

100PF

CERM

50V

NO STUFF

C7415

1

2

NO STUFF

402

50V CERM

5%

100PF

C7416

1

2

69

MF-LF

1/16W

5%

10

402

R7440

1 2

1/16W

402

MF-LF

10

5%

R7441

1 2

12 78

5% 25V

402

1000PF

NP0-C0G

C7440

1

2

1000PF

5%

402

NP0-C0G

25V

C7441

1

2

25V NP0-C0G

1000PF

5%

402

C7412

1

2

5% 1/16W MF-LF

10

402

R7413

1 2

12 78

25V

NP0-C0G

1000PF

5%

402

C7422

1

2

10

MF-LF

1/16W

5%

402

R7423

1 2

49 69 85

CERM

5%

100PF

NO STUFF

402

50V

C7419

1

2

NO STUFF

402

5% 50V CERM

100PF

C7418

1

2

69 85

NOSTUFF

402

NONE NONE NONE

OMIT

C7442

1

2

NOSTUFF

OMIT

402

NONE

C7443

1

2

PLACE_NEAR=U7400.18:2mm

402

MF-LF

1/16W

54.9

1%

R7479

1

2

PLACE_NEAR=U7400.16:2mm

130

1/16W MF-LF 402

1%

R7480

1

2

300

MF-LF

5%

1/16W

402

R7407

1 2

69

1%

154K

1/16W MF-LF 402

R7462

1

2

1%

107K

1/16W MF-LF 402

R7463

1

2

1%

215K

1/16W MF-LF 402

R7460

1

2

1%

137K

1/16W MF-LF 402

R7461

1

2

1%

8.45K

1/16W MF-LF

402

R7412

1 2

1%

8.66K

1/16W MF-LF

402

R7422

1 2

90.9K

1/16W MF-LF

402

1%

R7402

1 2

402

MF-LF

1/16W

200K

1%

R7465

1

2

402

MF-LF

1/16W

5.76K

1%

R7468

1

2

1%

5.76K

1/16W MF-LF 402

R7466

1

2

NO STUFF

402

50V CERM

0.0022UF

10%

C7407

1

2

402

50V CERM

0.0022UF

10%

C7404

1

2

402

50V CERM

0.0022UF

10%

C7405

1

2

100KOHM-1%-100MW

CRITICAL

0603

R7469

1

2

0603

CRITICAL

100KOHM-1%-100MW

R7467

1

2

5%

470PF

NP0-C0G

50V 402

C7409

1 2

353S3259 U7400 CRITICAL1

IC,MAX15092,3+1PH CPU REG,IMVP7,5X5QFN40

SYNC_DATE=10/14/2010

CPU IMVP7 & AXG VCore Regulator

SYNC_MASTER=JACK_K90I

CPUIMVP_PHASE1

CPUIMVP_ISUM_N

CPUIMVP_ISUM

VOLTAGE=0V

CPU_VCCSENSE_R

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

GND_CPUIMVP_SGND

CPUIMVP_FBB_R

CPUIMVP_FBA_R

CPU_VCCSENSE_N

VOLTAGE=0V

CPU_AXG_SENSE_R

CPUIMVP_ISUM_R

CPUIMVP_ISUM1_P

CPUIMVP_ISUM2_P

CPUIMVP_ISUMG_P

CPUIMVP_NTC

CPU_VIDSOUT

CPUIMVP_FBA

CPUIMVP_VR_ON

CPU_VIDSCLK

CPUIMVP_LGATE2

CPUIMVP_LGATE1

CPUIMVP_BOOT1

CPUIMVP_FBB

CPUIMVP_LGATE1G

CPU_AXG_SENSE_P

CPU_AXG_SENSE_N

CPUIMVP_ISNS2_P

CPUIMVP_ISNS1_P

CPUIMVP_PGOOD

CPUIMVP_BOOT1G

CPU_VIDALERT_L

CPU_VCCSENSE_P

CPUIMVP_UGATE1

PP1V05_S0

CPU_PROCHOT_L

CPUIMVP_PHASE2

CPUIMVP_FBA

CPUIMVP_FBB

CPUIMVP_UGATE2

CPUIMVP_BOOT2

CPUIMVP_AXG_PGOOD

CPUIMVP_IMAXA

CPUIMVP_SLEW

CPUIMVP_IMAXB

CPUIMVP_PHASE1G

CPUIMVP_UGATE1G

CPUIMVP_TON

PPBUS_S5_HS_COMPUTING_ISNS

PP5V_S0

CPUIMVP_NTCG

CPUIMVP_ISUMG_N

P5V_S0_CPUIMVP_VDD

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

74 OF 109

68 OF 86

68

6 7 9

10 12 14 16 17 20 22 23

36 40 45 70 73

68

7

50 65 67 69 70

6 7

22 42 47 52 54 65 70 72 73

77

IN

VSW

PGND

TGR

TG

BG

VIN

VSW

PGND

TGR

TG

BG

VIN

VSW

PGND

TGR

TG

BG

VIN

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

376S0906

AXG PHASE

152S1271

THESE TWO CAPS ARE FOR EMC

376S0906

PHASE 2

PHASE 1

152S1271

THESE TWO CAPS ARE FOR EMC

152S1271

Removed snubber with EMC’s comment

NOSTUFF

0.001UF

402

10% CERM

50V

C7512

1

2

0.36UH-20%-35A-0.00081OHM

FCUL1040-SM

CRITICAL

L7510

1 2

CRITICAL

0805

10% X5R-CERM

16V

10UF

C7515

1

2

CRITICAL

10UF

16V

10% X5R-CERM

0805

C7516

1

2

X5R 402

1UF

10% 16V

C7517

1

2

0.001UF

402

10% 50V X7R

C7518

1

2

402

X7R

50V

10%

0.001UF

C7519

1

2

68

20%

39UF-0.027OHM

POLY

CRITICAL

16V

B1A-SM

C7514

1

2

68

FCUL1040-SM

CRITICAL

0.36UH-20%-35A-0.00081OHM

L7520

1 2

20%

POLY B1A-SM

16V

39UF-0.027OHM

CRITICAL

C7524

1

2

10UF

CRITICAL

16V

0805

X5R-CERM

10%

C7525

1

2

CRITICAL

10UF

10% 16V X5R-CERM 0805

C7526

1

2

402

1UF

10% X5R

16V

C7527

1

2

402

10% 50V X7R

0.001UF

C7528

1

2

402

0.001UF

X7R

50V

10%

C7529

1

2

0.22UF

402

10% CERM

10V

C7521

1

2

5%

MF-LF

0

1/16W

402

R7521

1

2

0

MF-LF

1/16W

402

5%

R7511

1

2

10V CERM

10%

402

0.22UF

C7511

1

2

10% 50V X7R

0.001UF

402

C7559

1

2

50V

10%

0.001UF

X7R 402

C7558

1

2

X5R

10%

1UF

402

16V

C7557

1

2

16V

10%

0805

X5R-CERM

10UF

CRITICAL

C7556

1

2

POLY

16V

B1A-SM

20%

39UF-0.027OHM

CRITICAL

C7554

1

2

NOSTUFF

603

MF-LF

1/10W

5%

2.2

R7552

1

2

50V CERM

10%

402

NOSTUFF

0.001UF

C7552

1

2

402

10%

CERM

10V

0.22UF

C7551

1

2

5%

0

402

1/16W MF-LF

R7551

1

2

68

1/16W

1%

10

MF-LF 402

R7514

1

2

1%

10

1/16W MF-LF 402

R7524

1

2

1%

402

1/16W MF-LF

10

R7554

1

2

CRITICAL

SON5X6

CSD58864Q5D

Q7550

5

9

3

4

1

6

7

8

10% X5R-CERM

16V

CRITICAL

0805

10UF

C7555

1

2

FCUL1040-SM

CRITICAL

0.36UH-20%-35A-0.00081OHM

L7550

1 2

CRITICAL

SON5X6

CSD58864Q5D

Q7510

5

9

3

4

1

6

7 8

CSD58864Q5D

CRITICAL

SON5X6

Q7520

5

9

3

4

1

6 7

8

68 69

68

68 69

68

68 85

49 68 85

CASED2E-SM

POLY-TANT

16V

20%

33UF

CRITICAL

C7540

1

2

CRITICAL

CASED2E-SM

POLY-TANT

16V

20%

33UF

C7530

1

2

CRITICAL

CASED2E-SM

POLY-TANT

16V

20%

33UF

C7560

1

2

4.7

5% 1/16W MF-LF

402

R7515

1 2

4.7

5% 1/16W MF-LF

402

R7525

1 2

4.7

5%

MF-LF

402

1/16W

R7555

1 2

CRITICAL

B6S-SM

ELEC

16V

20%

82UF

C7513

1

2

B6S-SM

ELEC

16V

20%

82UF

CRITICAL

C7523

1

2

B6S-SM

ELEC

16V

20%

82UF

C7553

1

2

CRITICAL

0612

MF

1W

0.00075

1%

R7510

12 34

CRITICAL

0612

MF

1W

0.00075

1%

R7520

1 2 3 4

CRITICAL

0612

MF

1W

0.00075

1%

R7550

1 2 3 4

402

MF-LF

1/16W

46.4

1%

R7553

1

2

402

MF-LF

1/16W

46.4

1%

R7523

1

2

402

MF-LF

1/16W

46.4

1%

R7513

1

2

NO STUFF

0.0022UF

10% 50V CERM 402

C7571

1

2

NO STUFF

402

50V CERM

0.0022UF

10%

C7572

1

2

10%

0.001UF

X7R

50V 402

C7574

1

2

1/10W

603

2.2

MF-LF

5%

NOSTUFF

R7512

1

2

SYNC_DATE=09/03/2010

SYNC_MASTER=JACK_K90I

CPU IMVP7 & AXG VCore Output

CPUIMVP_BOOT1G_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

CPUIMVP_UGATE1G_R

DIDT=TRUE

GATE_NODE=TRUE

PPBUS_S5_HS_COMPUTING_ISNS

CPUIMVP_AXG_SNUB

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

DIDT=TRUE

CPUIMVP_VSWG

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

SWITCH_NODE=TRUE

DIDT=TRUE

PPBUS_S5_HS_COMPUTING_ISNS

VOLTAGE=1.25V

PPVCORE_S0_CPU_PH2_L

DIDT=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

SWITCH_NODE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

PPVCORE_S0_AXG_R

PPVCORE_S0_AXG

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

PPVCORE_S0_CPU_PH2

CPUIMVP_ISUMG_P

CPUIMVP_ISUMG_N

PPBUS_S5_HS_COMPUTING_ISNS

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1_RC

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_ISUM1_P

CPUIMVP_ISUM_N

CPUIMVP_ISNS2_P

CPUIMVP_ISUM2_P

CPUIMVP_ISUM_N

CPUIMVP_ISNS1_P

CPUIMVP_ISNS1G_P

CPUIMVP_ISNS1_N

VOLTAGE=1.25V

PPVCORE_S0_CPU_PH1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_CPU

CPUIMVP_ISNS2_N

PPVCORE_S0_CPU

CPUIMVP_ISNS1G_N

PPVCORE_S0_CPU_PH1_L

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

SWITCH_NODE=TRUE

DIDT=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1G

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE2

SWITCH_NODE=TRUE

DIDT=TRUE

CPUIMVP_LGATE2

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=1.5 MM

CPUIMVP_PHASE1G

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

CPUIMVP_LGATE1

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE1G

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_UGATE2_R

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

CPUIMVP_UGATE2

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_UGATE1_R

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

CPUIMVP_BOOT2_RC

MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT2

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_LGATE1G

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_PH1_SNUB

DIDT=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUIMVP_BOOT1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.5 MM

DIDT=TRUE

SWITCH_NODE=TRUE

CPUIMVP_PHASE1

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_UGATE1

75 OF 109

69 OF 86

7

50 65 67 68 69 70

7

50 65 67 68 69 70

6 7 9

12 15 49

7

50 65 67 68 69 70

49 85

6 7 9

12 14 49 69

49 85

6 7 9

12 14 49 69

49 85

OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

f = 300 kHz

Vout = 0.5V * (1 + Ra / Rb)

(CPUVCCIOS0_OCSET)

CPU VCCIO (1.05V S0) Regulator

Vout = 1.05V 18A Max Output

<Ra>

<Rb>

OCP = 22.695A

(CPUVCCIOS0_VO)

OCP = R7641 x 8.5uA / R7640

10% 16V X7R

0.047UF

402

C7603

1

2

603

10%

X5R

2.2UF

16V

C7602

1

2

0

1/16W

402

MF-LF

5%

R7603

1

2

73

71 73

SM

PLACE_NEAR=U7600.1:1mm

XW7600

1 2

ISL95870

CRITICAL

UTQFN

U7600

12

3

6

5

1

15

7

16

9

10

14

2

4

11

13

8

10UF

20%

X5R

10V

603

C7601

1

2

10%

402

16V

1UF

X5R

C7630

1

2

25V

1000PF

5%

402

NP0-C0G

C7640

12

PCMB103T

0.68UH-18A-3.3MOHM

CRITICAL

L7630

1 2

5%

402

NP0-C0G

25V

1000PF

C7623

1

2

PLACE_NEAR=Q7630.1:1.5mm

NP0-C0G

25V

5%

1000PF

402

C7622

1

2

2.74K

1/16W MF-LF

402

1%

R7605

1

2

3.01K

402

1% 1/16W MF-LF

R7644

1

2

20%

39UF-0.027OHM

CRITICAL

B1A-SM

16V POLY

C7620

1

2

B1A-SM

20% 16V POLY

39UF-0.027OHM

CRITICAL

C7621

1

2 MF-LF 402

1/16W

0

5%

R7630

1

2

1% 1W

0612

MF-1

CRITICAL

0.001

R7640

21 43

1%

402

1/16W MF-LF

2.74K

R7645

1

2

10%

402

CERM

50V

NOSTUFF

0.001UF

C7631

1

2

MF-LF

1/10W

2.2

5%

603

NOSTUFF

R7631

12

402

MF-LF

1/16W

2.67K

1%

R7641

1

2

402

MF-LF

1/16W

2.67K

1%

R7642

1

2

MF-LF

402

1/16W

2.2

5%

R7601

1

2

CRITICAL

POWER56

FDMS3602S

Q7630

2

1

6

7

3 4 5

5%

402

50V

CERM

47PF

C7604

1

2

5%

402

50V CERM

47PF

C7605

1

2

MF-LF

1%

402

1/16W

3.01K

R7604

1

2

SYNC_DATE=08/19/2010

CPUVCCIO (1.05V) Power Supply

SYNC_MASTER=JACK_K90I

MIN_LINE_WIDTH=0.6 mm

CPUVCCIOS0_AGND

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

CPU_VCCIOSENSE_P

CPUVCCIOS0_RTN

CPUVCCIOS0_FB

PP5V_S0_CPUVCCIOS0_VCC

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm

CPUVCCIOS0_VBST

MIN_NECK_WIDTH=0.2 mm

CPUVCCIOS0_OCSET

CPUVCCIOS0_VO

CPU_VCCIOSENSE_N

CPUVCCIOS0_SREF

CPUVCCIOS0_PGOOD

CPUVCCIOS0_CS_N

CPUVCCIOS0_CS_P

CPUVCCIOS0_EN

CPUVCCIOS0_FSEL

PP1V05_S0

DIDT=TRUE

CPUVCCSAS0_SNUB

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PPCPUVCCIO_S0_REG_R

PP5V_S0

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

CPUVCCIOS0_VBST_RC

DIDT=TRUE

CPUVCCIOS0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

CPUVCCIOS0_DRVH

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_LINE_WIDTH=1.5 mm SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

CPUVCCIOS0_LL

DIDT=TRUE

PPBUS_S5_HS_COMPUTING_ISNS

76 OF 109

70 OF 86

12 78

49 85

6 7 9

10 12 14 16 17 20 22 23

36 40 45 68 73

6 7

22 42 47 52 54 65 68 72

73 77

7

50 65 67 68 69

IN

BIAS

NC

OUT

THRM

EN

PAD

GND

NC

LX

PGOOD

IN

SS/REFIN

FB

COMP

EN

SKIP

GND

OUT

IN

VI

SW

EN

FB

GND

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Max Current = 0.35A

70mA is required to support pull-ups. Alternative is strong voltage

F = 1MHZ

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

CAESAR IV 1.2V INT.VR CMPTS

Vout = 1.05V

1.05V S5 LDO

Vout = 1.05V

MAX CURRENT = 0.3A

Vout = 1.5V

F = 1MHZ

MAX CURRENT = 2A

Vout = 1.8V

1.8V S0 Switcher

1.5V S0 Switcher

Pull-ups (3) must be 51 ohms to support XDP (not required in production).

Cougar Point requires JTAG pull-ups to be powered at 1.05V in S5.

Max Current = 0.35A

1.05V S0 LDO

73

1UF

402

CERM

6.3V

10%

XDP_PCH

C7740

1

2

XDP_PCH

TPS720105

CRITICAL

SON

U7740

4

3

5

6

2

1

7

X5R 402

XDP_PCH

6.3V

10%

2.2UF

C7741

1

2

MAX15053EWL

WLP

CRITICAL

U7760

B1

B3

C1

A1

A3

A2

C3

B2

C2

20.0K

1% 1/16W MF-LF 402

R7760

1

2

MF-LF

10K

1/16W

1%

402

R7761

1

2

3.24K

1%

402

1/16W MF-LF

R7765

1 2

X7R

1500PF

402

10% 25V

C7765

1

2

805

20%

6.3V CERM-X5R

22UF

C7760

1

2

402-1

0.1UF

10% 16V X5R

C7761

1

2

0.1UF

10% 16V X5R 402-1

C7763

1

2

100PF

402

50V CERM

5%

C7766

1

2

402

NOSTUFF

50V

5%

100PF

CERM

C7767

1

2

NOSTUFF

10K

1% 1/16W MF-LF 402

R7767

1

2

PLACE_NEAR=L7700.1:3mm

402

0.1UF

16V X5R

10%

C7726

1

2

PLACE_NEAR=L7700.1:1mm

603-2

10UF

X5R

20%

6.3V

C7725

1

2

0.1UF

10% X5R

16V

PLACE_NEAR=U3900.14:1mm

402

C7718

1

2

CERM 603

PLACE_NEAR=U3900.14:3mm

20%

6.3V

4.7UF

C7717

1

2

CERM-X5R 402

0.022UF

10% 16V

C7764

1

2

PIC0503H-SM

1.0UH-20%-11A-0.013OHM

CRITICAL

L7760

1 2

73

PLACE_NEAR=U3900.16:1mm

CRITICAL

4.7UH-0.91A

PLE031B-SM

L7700

1 2

PLACE_NEAR=C7725.1:1mm

SM

XW7700

1 2

73

X5R

6.3V

20%

10uF

603

C7770

1

2

CRITICAL

10UH-0.55A-330MOHM

PCAA031B-SM

L7770

1

2

X5R

6.3V

20%

603

10uF

C7773

1

2

SOT23-5

TPS62201

CRITICAL

U7770

3

4

2

5

1

2.2UF

10%

6.3V 402

X5R

C7781

1

2

SON

TPS720105

CRITICAL

U7780

4

3

5

6

2

1

7

PLACE_NEAR=U7780.6:1mm

10%

1UF

402

CERM

6.3V

C7780

1

2

603

X5R-CERM-1

20%

22UF

6.3V

C7762

1

2

603

X5R-CERM-1

20%

22UF

6.3V

C7772

1

2

PLACE_NEAR=U7780.4:1mm

10%

6.3V CERM

402

1UF

C7782

1

2

Misc Power Supplies

SYNC_DATE=08/19/2010

SYNC_MASTER=JACK_K90I

PP1V8_S0

PP1V8_S0 CPUVCCIOS0_EN

PP1V05_SUS

PP3V3_S0

PP1V2_S3_ENET_INTREG

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.25MM

MAKE_BASE=TRUE

P1V8_S0_COMP_RC

P1V8S0_SS

PP1V05_S0_PCH_VCCADPLL

P1V8_S0_RC

PP3V3_SUS

PP3V3_S0

P1V5S0_EN P1V5S0_SW

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.4 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

ENET_SR_VFB

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.2MM

ENET_SR_LX

MIN_LINE_WIDTH=0.4MM

DIDT=TRUE

SWITCH_NODE=TRUE

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

PP3V3_ENET

PP1V2_S3_ENET_INTREG

P1V8S0_PGOOD

P1V8S0_EN

MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

P1V8S0_SW

MIN_LINE_WIDTH=0.4 mm

P1V8S0_COMP

PP1V5_S0

P1V8SO_FB

77 OF 109

71 OF 86

6 7

14 17 20 22 26 71

6 7

14 17 20 22 26 71

70 73

7

23

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6

37 71

7

16 17 18 19 20 22 46 72 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

37

6 7

26 37 73

6

37 71

7

16 20 22 26 42 57

IN

D

SG

D

SG

IN

S

G

D

THRM

GND

G

PG

SHDN*

D

VCC

S

ON

PAD

OUT

IN

D

SG

IN

D

SG

D

SG

D

SG

D

S

G

D

S

G

D

S

G

D

S

G

S

D

G

D

S

G

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

3.3V S3 FET

3.3V SUS FET

5V SUS FET

MOSFET

5V_SUS FET

MOSFET

1.5V S3/S0 FET

LOADING

CHANNEL

3.3V S0 FET

18 MOHM @4.5V

P-TYPE

TPCP8102MOSFET

5.0V S0 FET

LOADING

CHANNEL

LOADING

RDS(ON)

1.678 A (EDP)

CHANNEL

MOSFET

P-TYPE 8V/5V

RDS(ON)

3.3V S0 FET

N-TYPE

3.2 A (EDP)

3.3V_SUS FET

1.35 A (EDP)

CHANNEL

APN 376S0928

RDS(ON)

MOSFET

LOADING

5 A (EDP)

RDS(ON)

3.3V S4 FET

P-TYPE 8V/5V

SiA427

6 mOhm @4.5V

SI7108DN

SiA427

26 mOhm @1.8V

P-TYPE 8V/5V

100? mA (EDP)

RDS(ON)

CHANNEL

LOADING

P-TYPE 8V/5V

100? mA (EDP)

LOADING

RDS(ON)

CHANNEL

MOSFET

SiA427

26 mOhm @1.8V

SiA427

16 mOhm @4.5V

26 mOhm @1.8V

LOADING

5.0V S0 FET

1.5V S3/S0 FET

RDS(ON)

P-TYPE 8V/5V

SiA427

CHANNEL

MOSFET

1.608 A (EDP)

31 mOhm @1.8V

3.3V S3 FET

3.3V S4 FET

30

16V

CERM

10%

0.01UF

402

C7810

1 2

10%

402

X5R

0.033UF

16V

C7811

1

2

MF-LF

1/16W

5%

47K

402

R7810

1 2

0.01UF

402

16V

10%

CERM

C7830

1 2

402

16V

0.033UF

10%

X5R

C7831

1

2

73

49 72 73

SOT563

SSM6N37FEAPE

Q7812

6

2

1

SOT563

SSM6N37FEAPE

Q7812

3

5

4

49 72 73

10K

402

MF-LF

1/16W

5%

R7860

1 2

402

16V

0.033UF

X5R

10%

C7861

1

2

0.01UF

10%

402

CERM

16V

C7860

1 2

TPCP8102

23V1K-SM

CRITICAL

Q7860

5 6 7 8

4

1 2 3

CRITICAL

TDFN

SLG5AP020

U7801

5

7

4

2

8

6

3

9

1

402

20%

0.1UF

10V

CERM

C7801

1

2

1/16W

402

MF-LF

0

5%

R7801

1 2

4.7UF

10%

X5R-CERM

6.3V 603

NO STUFF

C7802

1

2

8

73

SOT563

SSM6N37FEAPE

Q7802

6

2

1

0.033UF

NO STUFF

10%

X5R 402

16V

C7809

1

2

NO STUFF

402

16V

10%

CERM

0.01UF

C7800

1 2

72 73

SOT563

SSM6N37FEAPE

Q7822

6

2

1

10% 16V

402

X5R

0.033UF

C7841

1

2

10% 16V

402

X5R

0.033UF

C7821

1

2

0.01UF

10% 16V

CERM

402

C7840

1 2

0.01UF

10% 16V

CERM

402

C7820

1 2

SOT563

SSM6N37FEAPE

Q7822

3

5

4

SOT563

SSM6N37FEAPE

Q7802

3

5

4

402

100K

MF-LF

1/16W

5%

R7812

1

2

NO STUFF

402

MF-LF

1/16W

5.1K

5%

R7800

1 2

402

MF-LF

1/16W

12K

5%

R7820

1 2

402

3.3K

1/16W MF-LF

5%

R7840

1 2

402

MF-LF

1/16W

220K

5%

R7862

1

2

CRITICAL

SIA427DJ

NO STUFF

SC70-6L

Q7800

1

3

4 7

SC70-6L

SIA427DJ

CRITICAL

Q7830

1

3

4 7

SC70-6L

CRITICAL

SIA427DJ

Q7820

1

3

4 7

SC70-6L

CRITICAL

SIA427DJ

Q7810

1

3

4 7

CRITICAL

SI7108DN

PWRPK-1212-8-HF

Q7801

5

4

1 2 3

402

MF-LF

1/16W

91K

5%

R7830

1 2

402

MF-LF

1/16W

10K

5%

R7832

1

2

NO STUFF

5%

220K

1/16W MF-LF 402

R7802

1

2

5%

220K

1/16W MF-LF 402

R7842

1

2

5% 1/16W MF-LF

100K

402

R7822

1

2

CRITICAL

SIA413DJ

SC70-6L

Q7840

1

3

4 7

603

0

5% 1/10W MF-LF

R7803

1 2

SYNC_DATE=10/22/2010

SYNC_MASTER=JACK_K90I

Power FETs

PP3V3_S5

PP3V3_S4

P3V3S3_EN_L

P5VSUS_SS

PP5V_SUS

PP5V_S5

PP3V3_S5

P3V3SUS_SS

PP5V_S0

P5VSUS_EN_L

PP3V3_S5

P3V3SUS_EN_L

P3V3S4_EN_L

P3V3S0_EN_L

PP3V3_S5

P3V3S0_SS

P1V5S0FET_GATE_R

PP1V5_S3

PP1V5_S3RS0

PP5V_S3

P5V0S0_SS

P3V3S3_SS

PP3V3_S3

P3V3S4_GATE

PP3V3_S0

PP3V3_SUS

P5V0S0_EN_L

PM_SUS_EN

PM_SLP_S3_R_L

P1V5S0FET_GATE

P1V5CPU_EN

P3V3_S4_EN

P3V3S3_EN

PM_SLP_S3_R_L

TP_P1V5S3RS0_RAMP_DONE

PM_SUS_EN

PP5V_S5

78 OF 109

72 OF 86

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

7

46 53 54

7

22

7

54 66 72

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7

22 42 47 52 54 65 68 70 73

77

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76 85

6 7

27 29 30 67

6 7

10 12 15 30 73 85

6 7

30 32 42 43 44 46 57 59 60

61 66 67

6 7 8

18 24 26 30 31 32 33 48

50 54 55 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

73 74 75 77 85

7

16 17 18 19 20 22 46 71 73

7

54 66 72

G

D

S

IN

G

D

S

IN

OUT

G

DS

OUT

IN

OUT

D

G S

IN

OUT

IN

NC

Q3

Q2

Q4

Q1

OUTIN

SENSE

CT

VDD

GND

RESET*

MR*

IN

G

D

S

G

D

S

OUT

VDD

MR*

RST*

V4MON

V3MON

V2MON

GND

THRM_PAD

D

G S

OUT

IN

VDD

OUT_A*

OUT_A

THRM

GND

IN_A

DLY_1C

IN_B

OUT_B

DLY

(OD,IPU)

(IPD)

1.3V

PAD

2:1

-

+

OUT

D

G S

IN

OUT

NC

VCC

A

Y

GND

B

C

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Delete R when pull-down added to PCH page

3.3V S4 ENABLE

(ISL Version in development)

Thresholds:

S5 Rail Enables & PGOOD

Threshold: ??

Delete R when pull-down added to PCH page

Internal pull-ups 100K +/- 20%

00

(PM_SLP_S3_R_L)

S0 ENABLE

Delete R when pull-down added to PCH page

3.3V,5V S3 ENABLE

VFRQ High: Variable Frequency

CHGR VFRQ Generation

353S2310

353S2809

WLAN Enable Generation

Deep Sleep (S4)

PP1V5_S3RS0

343S0497

Battery Off (G3Hot)

State

Run (S0)

Deep Sleep (S5)

0

1

0 0

1 1

0

(PM_SLP_S3_L)

(AC_EN_L)

3.3V ENET FET

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")

P1V5S0_PGOOD from U7710

(IPU)

SMC-->PM_DSW_PWRGD

PM_SLP_S3_LPM_SLP_S5_L

SMC_PM_G2_ENABLE

Q3: 0.640V

Q4: 0.660V

DLY > 10 ms

VFRQ Low: Fix Frequency

S0 Rail PGOOD (BJT Version)

1

PM_SLP_S4_L

0

1

Sleep (S3)

1

CPUVCORE ENABLE

V4MON: 0.572V-0.630V

V3MON: 0.572V-0.630V

V2MON: 2.815V-3.099V

VDD: 2.734V-3.010V

S0 Rail PGOOD Circuitry

Q2: 0.XXXV

3.3V w/Divider: 2.345V

Worst-Case Thresholds:

ENET Enable Generation

DP S4 Power Enable

PSOC USB Power Enable

PM_RSMRST_L goes to U1800.C21

(90K IPU)

3.3V SUS Detect

U7930 Sense input

Min delay time

No stuff C7931, 12ms

threhold is 3.07V

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

Delete R when pull-down added to PCH page

SMC_BATLOW_L:100K pull up on SMC page

3.3V/5.0V Sus ENABLE

2N7002DW-X-G

SOT-363

Q7920

6

2

1

17 45 46

19

6 17 30 45 73

10K

402

5%

MF-LF

1/16W

R7921

1

2

5%

MF-LF

100K

1/16W

402

R7922

1 2

2N7002DW-X-G

SOT-363

Q7925

6

2

1

18 32

32

10% 16V

402

X5R

0.033UF

C7921

1

2

SOT-23-HF

NTR4101P

CRITICAL

Q7922

3

1

2

0.01UF

10% 16V

CERM

402

C7922

12

66 73

43 67 73

72 73

PLACE_NEAR=Q7812.2:6mm

CERM-X5R

10%

402

0.47UF

6.3V

C7912

1

2

68

1/16W MF-LF

5%

0

402

PLACE_NEAR=U7400.7:5mm

R7974

1 2

49 72 73

70 71 73

71 73

65 73

1/16W

5%

402

5.1K

PLACE_NEAR=U7300.16:6mm

MF-LF

R7911

1

2

PLACE_NEAR=U7300.16:6mm

0.47UF

10%

6.3V CERM-X5R 402

C7910

1

2

6 17 30 45

0.47UF

10%

CERM-X5R 402

6.3V

PLACE_NEAR=U7760.B3:6mm

C7986

1

2

5%

402

1/16W

5.1K

MF-LF

PLACE_NEAR=U7760.B3:6mm

R7986

1

2

PLACE_NEAR=U7600.3:6mm

402

CERM-X5R

0.47UF

10%

6.3V

C7981

1

2

0.47UF

CERM-X5R

6.3V

10%

402

PLACE_NEAR=U7100.15:6mm

C7987

1

2

PLACE_NEAR=U7100.15:6mm

1/16W

33K

402

5%

MF-LF

R7987

1

2

100K

MF-LF

402

1/16W

5%

PLACE_NEAR=U1800.P12:5mm

R7979

1

2

MF-LF 402

10K

1/16W

5%

R7931

1 2

64

SSM3K15FV

SOD-VESM-HF

Q7931

3

1

2

6 17 30 45 73

8 45 46 73 76

402

0

5% 1/16W MF-LF

PLACE_NEAR=U7400.7:5mm

R7975

1 2

45

PLACE_NEAR=U7400.7:5mm

NO STUFF

MF-LF

5%

0

402

1/16W

R7976

1 2

NO STUFF

MF-LF

402

5%

0

1/16W

R7929

1

2

10K

MF-LF

1/16W

5%

402

R7967

1

2

23 26 45 73

5%

100

402

MF-LF

1/16W

R7957

1

2

402

5% 1/16W MF-LF

100

R7966

1 2

MF-LF

1/16W

5%

402

100

R7964

1 2

402

MF-LF

1/16W

5%

100

R7965

1 2

71

66

5% 1/16W MF-LF

402

100

R7963

1 2

330

5%

1/16W

402

MF-LF

S0PGOOD_ISL

R7962

1 2

70 73

65

150K

1/16W

1%

402

MF-LF

R7956

1

2

S0PGOOD_ISL

0.1uF

402

CERM

10V

20%

C7960

1

2

MF-LF

1/16W

1K

5%

402

R7953

1 2

15.0K

402

1/16W

1% MF-LF

R7951

1

2

1/16W 402

MF-LF

1%

7.15K

R7952

1

2

ASMCC0179

DFN2015H4-8

CRITICAL

Q7950

5

7

1

6

4

8

2

3

MF-LF

402

1/16W

5%

1K

R7954

1 2

402

5%

MF-LF

1/16W

1K

R7955

1 2

72 73

PLACE_NEAR=U1800.G18:5mm

402

NO STUFF

5%

1/16W

0

MF-LF

R7916

1 2

17 45

CRITICAL

SOT23-6

TPS3808G33DBVRG4

U7930

4

2

3

15

6

NO STUFF

0.001UF

402

CERM

20% 50V

C7931

1

2

1/16W

5%

100K

MF-LF

402

R7933

1

2

402

10V

20%

CERM

0.1uF

PLACE_NEAR=U7930.6:2.3mm

C7930

1

2

NO STUFF

5%

402

MF-LF

1/16W

100

R7968

1 2

68

2N7002DW-X-G

SOT-363

Q7920

3

5

4

SOT-363

2N7002DW-X-G

Q7925

3

5

4

100

MF-LF

1/16W

5%

402

R7978

1 2

71 73

PLACE_NEAR=U7770.3:6mm

0.47UF

6.3V CERM-X5R

10%

402

C7988

1

2

17

MF-LF

402

1/16W

5%

100K

R7910

1

2

MF-LF

1/16W

5%

402

100K

R7915

1

2

S0PGOOD_ISL

TDFN

CRITICAL

ISL88042IRTEZ

U7960

4

1

8

9

3 5 6

2

7

S0PGOOD_ISL

402

15.0K

MF-LF

1/16W

1%

R7973

1

2

10K

1%

1/16W

MF-LF

402

S0PGOOD_ISL

R7971

1

2

S0PGOOD_ISL

15.0K

402

1/16W

MF-LF

1%

R7961

1

2

S0PGOOD_ISL

1/16W MF-LF

402

10K

1%

R7970

1

2

402

6.04K

S0PGOOD_ISL

MF-LF

1%

1/16W

R7972

1

2

402

1/16W

1%

MF-LF

S0PGOOD_ISL

6.04K

R7960

1

2

SOD-VESM-HF

SSM3K15FV

Q7921

3

1

2

66 73

X5R

16V 402

0.033UF

10%

NO STUFF

C7942

1

2

402

100

MF-LF

5%

1/16W

R7941

1 2

45

0.1uF

20% 402

CERM

10V

C7940

1

2

6 45

CRITICAL

SLG4AP012

TDFN

U7941

7

5

2

6

3

4

8

9

1

CERM 402

5% 25V

220PF

C7941

1

2

43 67 73

SSM3K15FV

SOD-VESM-HF

Q7911

3

1

2

1/16W

402

68K

5%

MF-LF

R7913

1 2

10%

402

0.068UF

CERM

10V

NO STUFF

C7913

1

2

8 45 46 73 76

70 71 73

PLACE_NEAR=U5701.3:6mm

3.3K

402

1/16W MF-LF

5%

R7914

1 2

53 73

PLACE_NEAR=U7600.3:6mm

1/16W MF-LF 402

20K

5%

R7981

1

2

402

NO STUFF

5%

0

MF-LF

1/16W

R7917

1 2

SOT891

74AUP1G3208

U7940

1

3

6

2

5

4

PLACE_NEAR=U7940.1:2.3mm

402

10V

CERM

20%

0.1uF

C7943

1

2

17

45 46

MF-LF

PLACE_NEAR=U1800.G16:5mm

402

1/16W

5%

100K

R7918

1

2

72 73

PLACE_NEAR=U7770.3:6mm

402

MF-LF

1/16W

5%

39K

R7988

1

2

5%

402

MF-LF

1/16W

9.1K

PLACE_NEAR=Q7812.2:6mm

R7912

1

2

NO STUFF

5%

1/16W

402

0

MF-LF

PLACE_NEAR=U1800.G18:5mm

R7919

1 2

SYNC_DATE=10/22/2010

SYNC_MASTER=JACK_K90I

Power Control 1/ENABLE

SMC_BATLOW_L

PM_SLP_SUS_L

S4_PGOOD_CT

PP3V3_SUS

PM_RSMRST_L

PP3V3_S5

PP3V3_SUS

PP3V3_S3

P5V3V3_REG_EN

P1V8S0_PGOOD

P5V3V3_PGOOD

PVCCSA_PGOOD

ALL_SYS_PWRGD_R

CPUVCCIOS0_PGOOD

CPUIMVP_VR_ON

P5V_DIV_VMON

MAKE_BASE=TRUE

P5VS3_EN_L

PP3V42_G3H

P3V3S3_EN

PSOC_VBUS_EN

MAKE_BASE=TRUE

P5VS3_EN_L

DDRREG_EN

CPUIMVP_AXG_PGOOD

CPUVCCIOS0_PGOOD

VMON_Q2_BASE

CPUVCCIOS0_EN

PM_SLP_S3_R_L

P1V8S0_EN

S5PGOOD_DLY

P1V5_DIV_VMON

P1V05_DIV_VMON

PP3V3_S0

ALL_SYS_PWRGD

PP3V3_S0

CHGR_VFRQ

PM_PECI_PWRGD

PVCCSA_EN

PP3V3_ENET

PP1V5_S3RS0

PP1V05_S0

ALL_SYS_PWRGD

PP5V_S0

PM_SLP_S3_L

SMC_ADAPTER_EN

PM_SLP_S3_L

PM_SLP_S3_R_L

P3V3ENET_SS

CPUVCCIOS0_EN

P1V5S0_EN

PP3V42_G3H

MAKE_BASE=TRUE

P3V3S5_EN_L_R

P3V3S5_EN_L

PP3V3_S5

MAKE_BASE=TRUE

S5_PWRGD

SMC_PM_G2_EN

MAKE_BASE=TRUE

S0PGD_C

S0PGD_BJT_GND_R

VMON_Q4_BASE

PP3V3_S5

PP3V3_S0

VMON_Q3_BASE

PP1V5_S3RS0

PP1V05_S0

MAKE_BASE=TRUE

P3V3S5_EN_L

AC_EN_L

PM_WLAN_EN_L

AP_PWR_EN

WOL_EN

MAKE_BASE=TRUE

P5V3V3_REG_EN

PM_ENET_EN_L

CPUVCCIOS0_EN

MAKE_BASE=TRUE

PVCCSA_EN

MAKE_BASE=TRUE

P1V8S0_EN

P1V5S0_EN

MAKE_BASE=TRUE

PM_SLP_S3_R_L

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

PSOC_VBUS_EN

MAKE_BASE=TRUE

PM_SLP_S4_L

P3V3S3_EN

MAKE_BASE=TRUE

PP3V42_G3H

VMON_3V3_DIV

ALL_SYS_PWRGD

PP3V3_S5

PM_SLP_S5_L

P3V3_S4_EN

PM_SUS_ENPM_SUS_EN

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

MAKE_BASE=TRUE

P3V3_S4_EN

79 OF 109

73 OF 86

7 16 17 18 19 20 22 46 71 72 73

6 7 8 17 19 20 22 23 24 26 30 46 56 66 72 73 74 76 85

7 16 17 18 19 20 22 46 71 72 73

6 7 8 18 24 26 30 31 32 33 48 50 54 55 72

70 73

6 7 26 43 45 46 47 48 53 63 64 73

53 73

6 7 8 12 16 17 18 19 20 22 23 26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62

71 72 73 74 75 77 85

6 7 8 12 16 17 18 19 20 22 23 26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 77 85

6 7 26 37 71

6 7 10 12 15 30 72 73 85

23 26 45 73

6 7 22 42 47 52 54 65 68 70 72 77

6 7 26

43

45

46

47

48

53

63

64

73

6 7 8 17 19 20 22

23 24 26 30 46 56

66 72 73 74 76 85

6 7 8 17 19 20 22 23 24 26 30 46 56 66 72 73 74 76 85

6 7 8 12 16 17

18

19 20 22 23

26

27 29 33 36

37

40 41 42 46

48 49

50 51 52 54

57

61 62 71 72

73 74

75 77 85

6 7 10 12 15 30 72 73 85

6 7 9 10 12 14 16 17 20 22 23 36 40 45 68 70 73

66 73

70 71 73

65 73

71 73

43 67 73

72 73

6 7 26 43 45 46 47 48 53 63 64 73

23 26 45 73

6 7 8 17 19 20 22 23 24 26 30 46 56 66 72 73 74 76 85

72 73

8 45 46 73 76

72

73

SYM_VER-1

NC

FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED

ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LVDS I/F

LVDS CONNECTOR:518S0650

(LVDS DDC POWER)

LED BKLT I/F

LCD CONNECTOR

20%

6.3V X5R 603

10UF

C9012

1

2

402

X5R

16V

0.1UF

10%

C9011

1

2

CRITICAL

0402-LF

120-OHM-0.3A-EMI

L9008

1 2

5% 1/16W

402

MF-LF

100K

R9014

1

2

402

X7R

10%

0.001UF

50V

C9015

1

2

402

50V X7R

10%

0.001UF

C9010

1

2

CRITICAL

AMC2012-SM

90-OHM-200MA

L9080

1

23

4

0.1UF

X5R

16V

402

10%

C9009

1

2

402

X7R

50V

10%

0.001UF

C9020

1

2

20474-030E-11

F-RT-SM

CRITICAL

J9000

31 32

33 34

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30

4 5 6 7 8 9

MFET-2X2-8IN

CRITICAL

FPF1009

U9000

617

2

3

4

5

5%

MF-LF

1/16W 402

2.2K

R9009

1

2

1/16W

5% MF-LF

402

2.2K

R9008

1

2

FERR-120-OHM-1.5A

0402-LF

L9004

1 2

SYNC_DATE=07/20/2009

LVDS CONNECTOR

SYNC_MASTER=K24_MLB

LVDS_DDC_CLK

LED_RETURN_5

LED_RETURN_4

LED_RETURN_6

LED_RETURN_3

LED_RETURN_2

LED_RETURN_1

PP3V3_S0

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<0>

BKL_VSYNC

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

PPVOUT_SW_LCDBKLT

LVDS_CONN_A_CLK_F_P

LVDS_CONN_A_CLK_F_N

LVDS_DDC_DATA

PP3V3_S5

LCD_IG_PWR_EN

PP3V3_LCDVDD_SW_F

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

PP3V3_S0_LCD_F

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

VOLTAGE=3.3V

PP3V3_LCDVDD_SW

MIN_NECK_WIDTH=0.20 MM

90 OF 109

74 OF 86

6 8

18

6

77

6

77

6

77

6

77

6

77

6

77

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 75 77 85

6

18 80

6

18 80

6

77

6

18 80

6

18 80

6

18 80

6

18 80

6

77

6

85

6

85

6 8

18

6 7 8

17 19 20 22

23 24 26 30 46 56 66 72 73

76 85

8

18

6

OUT OUT

BI

OUT

IN

IN IN

OUT OUT

IN

IN BI

BI

NC

IN BI

THMPAD

GND

VDD

OUT_D0P OUT_D0N

OUT_D1P

OUT_D2P

OUT_D1N

OUT_D3P

OUT_D2N

OUT_D3N

AC_AUXP AC_AUXN

OUT_HPD

CEXT

IN_D0P IN_D0N

IN_D1N

IN_D2N

IN_D3P

IN_SDA

IN_AUXP IN_AUXN

IN_HPD

I2C_CTL_EN

I2C_ADDR0 I2C_ADDR1

SCL_CTL SDA_CTL

REXT

AUXDDC_OFF

PD

CA_DET

IN_SCL

IN_D3N

IN_D2P

IN_D1P

OUT_AUXN_SDA

OUT_AUXP_SCL

BI BI

IN

BI

OUT

IN

OUT

VDD

PIO1_8/CT16B1_CAP0

PIO1_7/TXD

XTALIN

PIO1_4/AD5/WAKEUP

PIO1_6/RXD

SWDIO/PIO1_3/AD4

R/PIO1_2/AD3

R/PIO1_1/AD2

R/PIO1_0/AD1

RESET#/PIO0_0 PIO0_1/CLKOUT

SWCLK/PIO0_10/SCK/CT16B0_MAT2

PIO0_9/MOSI/CT16B0_MAT1

PIO0_8/MISO/CT16B0_MAT0

PIO0_2/SSEL/CT16B0_CAP0

R/PIO0_11/AD0

PIO0_7/CTS#

PIO0_6/SCK

PIO0_4/SCL PIO0_5/SDA

VSS

THRM

PAD

BI

OUT OUT

IN

AUX-

AUX+

DOUT_1+ DOUT_1-

NC

GND

THMPAD

GPU_SEL

HPD_2

AUX2-

AUX2+

DIN2_1-

DIN2_1+

DIN2_0-

HPD_1

AUX1-

AUX1+

DIN1_1-

DOUT_0-

DIN1_0+ DIN1_0-

DIN1_1+

HPD_IN

DOUT_0+

DIN2_0+

VDD

AUX_SEL

OUT

IN

IN IN

OUT OUT

IN IN

OUT OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

R9330 provides pads for programming/debug of MCU, please make accessible.

=T29_WAKE_L: Desktops use PCIe WAKE#

Mobiles use S4 WAKE#

If project has space for 10-pin programming header it should be used.

PS8301 has internal ~150K pull-down on PD pin. Okay to drive this pin even when VCC=0V per Parade (pin is 5V-tolerant).

(C9380/C9381)

DP Path Biasing

Both R’s must connect

Note: Other Parade

0 1 0xB6/0xB7

If GPU uses common pins for AUX_CH and DDC, alias nets together at GPU.

SWCLK

T29 signals are P/N-swapped after AC caps to improve layout.

R9308/R9309 maintain bias on C9308/C9309

transitions from high to low.

(Both L’s)

(D9382/D9383)

Both R’s:

DP/T29 A Low-Speed MUX

IC supports input

(DP_SDRVA_HPD)

(DP_SDRVA_AUXCH_N)

T29: TX_1

D9372/D9373:

LO=Port A

(D9360.2)

T29: TX_0

(D9361.2)

(D9364.2)

AUXCH Snoop Port, used by PS8301 during training.

(T29_A_LSX_R2P)

I2C Addr:

detection of DP Source.

R2P = Receptacle to Plug

0x26/0x27 (Wr/Rd)

Must be 3.3V DP A port power

(IPU)

(OD)

T29: LSX_A_R2P/P2R (P/N)

T29: Unused

T29: RX_1 Bias Sink

HI=Port B

10 for ML and HPD, Pericom uses

(IPD)

(IPU)

(IPD)

PS8301 I2C Addresses: A1 A0 Addr (W/R)

1 0 0x94/0x95

0 0 0x96/0x97

used for this part.

devices use 96/B6, so only 94/B4 are

1 1 0xB4/0xB5

(IPD)

(T29_A_LSX_P2R)

(D9365.2)

(D9372/D9373)

(All 4 D’s)

Must be 3.3V DP A port power

(C9370/C9371)

(All 4 D’s)

P2R = Plug to Receptacle

pin 10 for ML and pin 11 for HPD.

Display can detect host T29 support using I2C

because 100-ohm pull-downs would defeat DP Sink’s

pull-ups on ML<3>. U9390 AUX defaults to DP mode

Note: U9390 ML/HPD defaults to T29 mode so that DP/T29

PI3vEDP212 (353S3055) are

CBTL04DP081 (353S3151) and

similar pinouts. NXP uses pin

footprint-compatible parts with

(D9360/D9361)

(DP_SDRVA_AUXCH_P)

(OD)

(D9382/D9383)

to C in star topology.

T29 A High-Speed Signals

(C9372.2)

(C9373.2)

(C9383.2)

(IPD)

Port A MCU

SWDIO

T29 Path

Biasing

D9364/D9365:

DP A Super-Driver

(Both L’s)

(C9383.2)

to prevent spikes when U9310 AUXDDC_OFF

high while Vcc = 0V.

34 83

76 83

402

MF-LF

1/16W

1K

5%

R9312

1

2

1/16W

1%

402

MF-LF

4.22K

R9319

1

2

8

17

NO STUFF

MF-LF

5%

402

1/16W

1K

R9311

1

2

5%

402

MF-LF

1/16W

1K

R9310

1

2

10% X5R-CERM

0201

16V

0.1UF

C9311

1

2

10%

0201

16V

0.1UF

X5R-CERM

C9312

1

2

20%

6.3V CERM

402-LF

2.2UF

PLACE_NEAR=U9310.11:2 mm

C9319

1

2

34 83

8

81

8

81

8

81

8

81

8

81

8

81

10% 16V

0.1UF

X5R-CERM

0201

C9300

1 2

8

81

8

81

48

8

17 80 81

8

17 80 81

5%

100K

MF

1/20W 201

R9399

1

2

100K

5% MF

1/20W 201

R9398

1

2

8

17

8

17

CRITICAL

QFN

PS8301TQFN40GTR-A2

U9310

19

20

39

32

11

6

33

36 35

26

15

16

2

1

5

4

8

7

10

9

3

14 13

17

18

29

30

27

28

24

25

22

23

31

34

12

38 37

41

21

40

2.2UF

6.3V

402-LF

CERM

20%

C9310

1

2

76 83

0201

0.1UF

X5R-CERM

10% 16V

C9363

1 2

10% 16V X5R-CERM

0201

0.1UF

C9362

1 2

0.1UF

16V10%

X5R-CERM

0201

C9367

1 2

10% 16V X5R-CERM

0201

0.1UF

C9366

1 2

75

76 83

46 75

10% 16V X5R-CERM

0.1UF

0201

C9369

1 2

10% 16V X5R-CERM

0201

0.1UF

C9368

1 2

18

17

34

HVQFN25

CRITICAL

OMIT_TABLE

LPC1112A

U9330

2 7

8

9 10 11 12 13

20

23 24

6

15

16 17 18

1

14

19

25

5

22

3

21

4

34 48 83

76

34

34 48 83

34

402

MF-LF

1K

5% 1/16W

R9335

1

2

402

MF-LF

1/16W

10K

5%

R9336

1

2

CERM

10V

20%

0.1UF

402

C9330

1

2

34

76

0.1UF

20% 10V CERM 402

C9331

1

2

5% 1/20W

1K

201

MF

R9397

21

5% MF

1/20W

1K

201

R9396

21

1M

402

1/16W MF-LF

5%

R9339

1

2

10K

402

1/16W MF-LF

5%

R9338

1

2

76

5%

MF-LF

1/16W

402

OMIT

0

R9330

1

2

51

MF

1/20W

5%

201

R9393

1

2

5%

51

MF

1/20W

201

R9392

1

2

SIGNAL_MODEL=T29DP_MUX

CRITICAL

CBTL04DP081

HVQFN

CKPLUS_WAIVE=NdifPr_badTerm

OMIT_TABLE

U9390

18

19

14

15

7

6

32

30

31

26

27

24

25

22

23

2

1

5

4

21

28

10

17

13

8

11

33

39121620

29

8

36 76

10K

402

5% 1/16W MF-LF

R9334

1 2

16 23

5%

0

SDRV_PD

MF

1/20W

201

R9318

21

201

1/20W

MF

1M

5%

R9308

1 2

201

1/20W

1M

5% MF

R9309

1 2

76 83

TSLP-2-7

GND_VOID=TRUE

BAR90-02LRH

SIGNAL_MODEL=EMPTY

CRITICAL

D9364

1 2

BAR90-02LRH

GND_VOID=TRUE

TSLP-2-7

CRITICAL

SIGNAL_MODEL=T29PIN

D9373

1 2

GND_VOID=TRUE

TSLP-2-7

CRITICAL

SIGNAL_MODEL=T29PIN

BAR90-02LRH

D9372

1 2

TSLP-2-7

GND_VOID=TRUE

BAR90-02LRH

CRITICAL

SIGNAL_MODEL=EMPTY

D9365

1 2

GND_VOID=TRUE

BAR90-02LRH

CRITICAL

TSLP-2-7

SIGNAL_MODEL=EMPTY

D9360

1 2

SIGNAL_MODEL=T29PIN

BAR90-02LRH

CRITICAL

TSLP-2-7

GND_VOID=TRUE

D9382

1 2

BAR90-02LRH

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

TSLP-2-7

CRITICAL

D9383

1 2

TSLP-2-7

BAR90-02LRH

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

CRITICAL

D9361

1 2

0.47UF

20%

201

GND_VOID=TRUE

CERM-X5R-1

4V

C9370

1 2

1.5K

MF

1/20W

201

5%

GND_VOID=TRUE

R9372

1 2

1.5K

MF

1/20W

GND_VOID=TRUE

5%

201

R9373

1 2

1.5K

MF

GND_VOID=TRUE

201

1/20W

5%

R9382

1 2

1.5K

GND_VOID=TRUE

1/20W

5%

201MF

R9383

1 2

0.47UF

CERM-X5R-1

4V

20%

GND_VOID=TRUE

201

C9373

1 2

GND_VOID=TRUE

201

4V

20%

0.47UF

CERM-X5R-1

C9372

1 2

0.47UF

20%

201

GND_VOID=TRUE

4V

CERM-X5R-1

C9371

1 2

0.47UF

20%

4V

CERM-X5R-1

201

GND_VOID=TRUE

C9381

1 2

201

20%

GND_VOID=TRUE

4V

CERM-X5R-1

0.47UF

C9380

1 2

201

20% CERM-X5R-1

4V

GND_VOID=TRUE

0.47UF

C9382

1 2

201

4V

20%

0.47UF

CERM-X5R-1

GND_VOID=TRUE

C9383

1 2

0.22UF

20%

6.3V

X5R 201

C9364

1 2

0.22UF

20% X5R

6.3V 201

C9365

1 2

0.22UF

6.3V

X5R

20%

201

C9361

1 2

0.22UF

6.3V

20% X5R 201

C9360

1 2

1.5K

201MF

GND_VOID=TRUE

5%

1/20W

R9385

1 2

1.5K

201MF

GND_VOID=TRUE

5%

1/20W

R9384

1 2

76 83

1.5K

5% MF

201

1/20W

GND_VOID=TRUE

R9375

1 2

1.5K

5%MF1/20W

201

GND_VOID=TRUE

R9374

1 2

30

201MF

5%

1/20W

R9355

1 2

30

201MF

5%

1/20W

R9354

1 2

30

201MF

5%

1/20W

R9350

1 2

30

MF

5%

1/20W

201

R9351

1 2

0.1UF

CERM 402

10V

20%

C9390

1

2

402

CERM

0.1UF

10V

20%

C9391

1

2

1.5K

5%

201MF

1/20W

R9360

1 2

1.5K

201

1/20W

5% MF

R9361

1 2

1.5K

5%

1/20W

MF 201

R9364

1 2

1.5K

5% MF

201

1/20W

R9365

1 2

CRITICAL

74LVC1G04DBDCK

SC70

U9359

2

3

5

4

10%

0.1UF

X5R

16V 402

C9359

1

2

10% 16V

0.1UF

X5R-CERM

0201

C9301

1 2

10% 16V

0.1UF

X5R-CERM

0201

C9302

1 2

10% 16V

0.1UF

X5R-CERM

0201

C9303

1 2

10% 16V

0.1UF

X5R-CERM

0201

C9304

1 2

0.1UF

10% 16V X5R-CERM

0201

C9305

1 2

10% 16V

0.1UF

X5R-CERM

0201

C9306

1 2

0.1UF

10% 16V X5R-CERM

0201

C9307

1 2

0.1UF

10% 16V X5R-CERM

0201

C9308

1 2

0201

X5R-CERM

16V10%

0.1UF

C9309

1 2

201

MF

5% 1/20W

270

R9353

1

2

201

1/20W

270

5% MF

R9352

1

2

PLACE_NEAR=C9361.1:2mm

51

5%

1/20W

MF

201

R9363

1

2

10% 16V X5R 402

0.1uF

C9358

1 2

PLACE_NEAR=C9361.1:2mm

51

5% 1/20W MF 201

R9362

1

2

8

1.0NH+/-0.1NH

0201-1

OVERSIZE_PAD=0.875 mm^2

L9372

1 2

OVERSIZE_PAD=0.875 mm^2

1.0NH+/-0.1NH

0201-1

L9373

1 2

1.0NH+/-0.1NH

0201-1

OVERSIZE_PAD=0.875 mm^2

L9382

1 2

0201-1

OVERSIZE_PAD=0.875 mm^2

1.0NH+/-0.1NH

L9383

1 2

SYNC_DATE=10/16/2010

SYNC_MASTER=T29

DisplayPort/T29 A MUXing

PP3V3_SW_DPAPWR

DP_SDRVA_AUXCH_N

DP_SDRVA_ML_P<1>

DP_SDRVA_ML_N<3>

DP_A_PWRDWN

DP_SDRVA_ML_C_P<2>

DP_SDRVA_ML_R_P<0> DP_SDRVA_ML_R_N<0>

T29_R2D_C_F_N<1> T29_R2D_C_F_P<1>

DP_SDRVA_ML_R_N<2>

DP_SDRVA_ML_R_P<2>

DP_SDRVA_ML_N<0>

T29_D2R_P<1>

DP_EXTA_ML_N<1>

DP_EXTA_DDC_DATA

DPSDRVA_I2C_CTL_EN

DPSDRVA_REXT

T29_D2R_C_N<1>

T29_D2R_C_P<1>

T29_A_BIAS_R2DN1

DP_SDRVA_ML_N<2>

T29_D2R_C_P<0>

T29_R2D_N<0>

I2C_T29_SDA

T29_LSOE<1>

T29DPA_HPD T29_A_BIAS_R

T29_MCU_INT_L

DP_SDRVA_ML_C_N<1>

PP3V3_S0

T29_LSOE<0>

T29_D2R_N<0>

I2C_DPSDRVA_SDA

DP_EXTA_ML_C_N<3>

DP_SDRVA_ML_N<1>

T29_A_LSX_P2R T29_A_LSX_R2P

T29_A_RSVD_N

DP_A_PWRDWN T29_A_BIAS

DP_SDRVA_AUXCH_P

T29_A_RSVD_P

DP_SDRVA_HPD

I2C_DPSDRVA_SCL

PP3V3_SW_DPAPWR

DP_EXTA_ML_P<0>

T29_LSEO<0> I2C_T29_SCL

T29DPA_ML_C_N<0>

T29DPA_ML_C_P<0>

DP_EXTA_ML_N<0>

DP_EXTA_DDC_CLK

DP_EXTA_ML_P<1>

DP_EXTA_ML_P<2>

DP_EXTA_ML_N<3>

DP_EXTA_ML_P<3>

DP_EXTA_ML_N<2>

DPSDRVA_CEXT

T29DPA_ML_N<3>

DP_A_EXT_HPD

T29DPA_ML_P<3>

T29DPA_ML_P<1>

T29DPA_ML_N<1>

DP_A_EXT_AUXCH_N

DP_A_EXT_AUXCH_P

DP_A_CA_DET

T29DPA_CONFIG1_RC T29DPA_CONFIG2_RC

T29_A_UC_ADDR

T29_LSEO<1>

T29_A_HV_EN

DP_A_EXT_HPD

T29_A_HV_EN_R

DP_SDRVA_ML_C_N<3>

T29DPA_ML_C_N<2>

DP_EXTA_AUXCH_P

T29_D2R1_BIASN

T29_D2R1_BIASP

DP_EXTA_ML_P<2>

DP_EXTA_ML_N<2>

DP_EXTA_ML_C_N<2>

DP_EXTA_ML_P<3>

DP_EXTA_ML_C_P<3>

DP_EXTA_AUXCH_P

DP_EXTA_AUXCH_C_P

DP_EXTA_AUXCH_N

DP_EXTA_AUXCH_C_N

DP_EXTA_ML_N<0>

DP_EXTA_ML_P<1>

DP_EXTA_ML_N<1>

DP_EXTA_ML_N<3>

DP_A_CA_DET

DP_A_BIAS2

VOLTAGE=3.3V

DP_EXTA_ML_P<0>

DP_AUXCH_ISOL

T29_R2D_C_F_N<0>

T29_R2D_C_N<0> T29_R2D_C_P<0>

T29_R2D_C_N<1>

DP_EXTA_AUXCH_N DP_EXTA_HPD

T29_A_UC_ADDR

DP_EXTA_ML_C_N<1>

DP_EXTA_ML_C_N<0>

DP_EXTA_ML_C_P<0>

DP_EXTA_ML_C_P<1>

DP_EXTA_ML_C_P<2>

DP_SDRVA_ML_C_P<0> DP_SDRVA_ML_C_N<0>

DP_SDRVA_ML_C_N<2>

T29DPA_ML_C_P<2>

T29_R2D_P<1>

T29_A_BIAS_R2DP0

T29_D2R_P<0>

T29_A_BIAS_R2DP1

DP_A_BIAS

T29_A_BIAS_R2DN0

T29_D2R_C_N<0>

T29_R2D_P<0>

DP_SDRVA_ML_C_P<1>

DP_SDRVA_ML_C_P<3>

DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N

T29_R2D_C_P<1>

T29_R2D_C_F_P<0>

T29_D2R_N<1>

VOLTAGE=3.3V

DP_A_BIAS0

DP_SDRVA_ML_P<3>

DP_SDRVA_ML_P<0>

DP_SDRVA_ML_P<2>

T29_R2D_N<1>

PP3V3_S0

=T29_WAKE_L

DP_A_PWRDWN_R

DPSDRVA_I2C_ADDR1

DPSDRVA_I2C_ADDR0

PP3V3_S0

DP_A_PWRDWN

93 OF 109

75 OF 86

8

75 76

83

75

83

75 81

83

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52

54 57 61 62 71 72 73 74 75 77

85

83

8

80

75

8

76

83

8

80

8

75 76

75 81

75

46 75

83

75 81

8

75 81

83

75 81

75

83

8

83

6 7 8

12

16 17 18 19 20 22

23 26 27

29 33 36 37 40 41

42 46 48

49 50 51 52 54 57

61 62 71

72 73 74 75 77 85

6 7 8

12 16 17 18

19 20 22 23

26 27 29 33

36 37 40 41

42 46 48 49

50 51 52 54

57 61 62 71

72 73 74 75

77 85

75

OUT

IN IN

BI

IN

OUT OUT

BI BI

BI

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

DP_PWR

ML_LANE2P

AUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P ML_LANE3N

ML_LANE2N

CONFIG1 CONFIG2

BOT ROW TOP ROW

TH PINS SM PINS

SHIELD PINS

IN

OC*

OUT

EN

GND

IN

D

SG

D

S G

G

D

S

D

G S

OUT

BI

IN

GND

PGND

OUT

FB

IN

SGD

GND

PGND

OUT

FB

IN

CT

EN*

RTRY*

VIN

THRM

GND

IFLT

ILIM

FLT*

VOUT

PAD

IN IN

IN

IN IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

3.3V/HV Power MUX

for 2.9V mode.

3.3V Always

B1100 chosen for high Vf

Vds(max): -30V Vgs(max): +/-12V Vgs(th): -1.4V Rds(on): 65mOhm @ 2.5V Vgs Id(max): 3.7A @ 70C

is LOW.

TFLT = CCT * 38900

on AC-coupled signals.

DP_PWR must be S4 to support wake from T29 devices.

T29: TX_0

DP Dir

(Both C’s)

T29: LSX_R2P/P2R (P/N)

T29: TX_1

(3, 5, 17 & 19):

DP Dir

T29 Dir

<RLIM>

(IPU-Weak!)

20V Max

IFLT = 200k / RFLT = 885mA

T29: Unused

Low: 0 - 0.8V

Sink HPD range:

DP Source must pull

greater than or equal to 100K (DPv1.1a).

down HPD input with

High: 2.0 - 5.0V

<CT>

For J9400 T29 SMT pads

470k R’s for ESD protection

TSD = CCT * 100000

ILIM = 201k / RLIM = 935mA

(Both C’s)

T29 Dir

HIGH and T29_A_HV_EN

DPAPWRSW_HV_DET is

TSD 470ms 235ms 724ms

IFLT 885mA 876mA 894mA (*)

Nominal Min Max

Note: Bleeder active when

<RFLT>

2.5V / 249 ohm = 10mA

Bleeder Resistor

P = ~27mW

(Both L’s)

SI8409DB:

or HV_EN high.

when Source >3.4V

Blocking FET, off

3.3V/HV MUXed

(*) U9410 tolerance unknown

TFLT 18.3ms 13.4ms 26.7ms

ILIM 935mA 925mA 944mA (*)

Port A HV Power Switch

Circuit threshold range: 2.877-2.941V (2.903V nominal)

DisplayPort/T29 A Connector

Circuit threshold range: 3.363-3.439V (3.395V nominal)

ZXRE060A REF range: 0.595-0.605V (0.600V nominal)

Port A 3.3V Power Switch

10% 50V X7R 402

0.01UF

C9400

1

2

75 83

12

GND_VOID=TRUE

5% MF

1/20W

201

R9407

1 2

5%

12

MF

1/20W

201

GND_VOID=TRUE

R9403

1 2

12

GND_VOID=TRUE

5% MF

1/20W

201

R9404

1 2

GND_VOID=TRUE

5%

12

MF

1/20W

201

R9405

1 2

12

5%

GND_VOID=TRUE

MF

1/20W

201

R9406

1 2

5%

12

MF

1/20W

201

R9408

1 2

0.01UF

10% 50V X7R 402

C9402

1

2

0603

FERR-120-OHM-3A

L9408

1 2

12

5% MF

1/20W

201

R9402

1 2

12

5% MF

1/20W

201

R9401

1 2

50V X7R 402

10%

0.01UF

C9401

1

2

201

1/20W

MF

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

5%

1K

R9494

1

2

201

MF

5%

1K

1/20W

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

R9495

1

2

CERM

402

5%

50V

30PF

C9498

1

2

5% CERM

30PF

50V 402

C9499

1

2

402

1/16W MF-LF

5%

100K

R9441

1

2

CRITICAL

0603

650NH-5%-0.430MA-0.052OHM

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

L9498

12

CRITICAL

0603

650NH-5%-0.430MA-0.052OHM

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

L9499

12

75 83

402

1/16W MF-LF

4.7K

5%

R9425

1

2

GND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUE

F-RT-THSM

CRITICAL

DSPLYPRT-M97-1

J9400

18

16

4 6

20

1

78

1314

2

2122

5

3

11

9

17

15

12

10

19

20%

603

6.3V X5R

10UF

C9486

1

2

CRITICAL

SOT23

TPS2051B

U9480

4

2

5

3

1

CERM

20%

0.1UF

402

10V

C9485

1

2

0.1UF

20% 10V

CERM

402

C9481

1

2

603

X5R-CERM-1

22UF

6.3V

20%

CRITICAL

C9480

1

2

20%

100UF

POLY-TANT CASE-B2-SM

6.3V

CRITICAL

C9487

1

2

MMDT3946XG

SOT363

Q9426

2

5

631

4

1/16W MF-LF 402

5%

4.7K

R9430

1

2

5%

402

1/16W MF-LF

1K

R9426

1

2

1/16W MF-LF

10K

5%

402

R9432

1

2

MF-LF

5% 1/16W

402

4.7K

R9429

1

2

1/16W

100K

402

MF-LF

1%

R9427

1

2

MF-LF

1/16W

21.5K

402

1%

R9428

1

2

8

45 46 73

SOT563

SSM6N37FEAPE

Q9430

3

5

4

SOT563

SSM6N37FEAPE

Q9430

6

2

1

5%

MF-LF

402

1/16W

1M

R9452

1

2

402

1/16W

1M

MF-LF

5%

R9451

1

2

330PF

402

CERM

10% 50V

C9494

1

2

10% CERM

330PF

50V 402

C9495

1

2

5%

2.2K

1/20W

MF

201

GND_VOID=TRUE

R9498

1

2

201

1/20W MF

5%

2.2K

GND_VOID=TRUE

R9499

1

2

402

470K

5%

MF-LF

1/16W

R9416

1

2

DMB53D0UV

SOT-563

Q9419

5

3

4

1/16W MF-LF

5%

402

1K

R9418

1 2

SOT-563

DMB53D0UV

Q9419

6

2

1

SOD-VESM-HF

SSM3K15FV

Q9415

3

1

2

402

249

1/16W MF-LF

1%

R9419

2 1

0603

FERR-120-OHM-3A

L9400

1 2

75

75 83

8

36 75 76

SOT353

ZXRE060A

CRITICAL

U9426

4

2

3

5

1

BGA

SI8409DB

CRITICAL

Q9425

2 3

1

4

CERM

10V

20%

0.1UF

402

NO STUFF

C9429

1

2

20%

402

CERM

10V

0.1UF

C9426

1

2

ZXRE060A

SOT353

CRITICAL

U9435

4

2

3

5

1

10V 402

0.1UF

20% CERM

C9435

1

2

MF-LF

100K

1%

402

1/16W

R9435

1

2

402

MF-LF

1/16W

1%

24.9K

R9436

1

2

402

10V

10% X5R

1UF

C9436

1

2

1/16W

402

5%

MF-LF

220

R9433

1

2

6.3V CERM-X5R

0.47UF

10% 402

C9412

1

2

MF-LF

402

1/16W

1%

100K

R9410

1

2

200K

MF-LF

1/16W 402

1%

R9411

1

2

0.1UF

50V X7R

603-1

10%

C9410

1

2

CRITICAL

TPS2590

QFN

U9410

9

16 15

5

13

14

8

76

17

1 2 3 4

10 11 12

0.1UF

603-1

X7R

10% 50V

C9411

1

2

TSLP-2-7

BAR90-02LRH

CRITICAL

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

D9499

1 2

TSLP-2-7

CRITICAL

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

BAR90-02LRH

D9498

1 2

201

1/20W MF

GND_VOID=TRUE

5%

470K

R9470

1

2

201

1/20W MF

GND_VOID=TRUE

5%

470K

R9471

1

2

GND_VOID=TRUE

0.47UF

201

20% CERM-X5R-1

4V

C9471

1 2

201

CERM-X5R-1

4V

0.47UF

20%

GND_VOID=TRUE

C9470

1 2

75 83

201

CERM-X5R-1

20%

4V

0.47UF

GND_VOID=TRUE

C9472

1 2

20% CERM-X5R-1

201

0.47UF

4V

GND_VOID=TRUE

C9473

1 2

201

1/20W MF

GND_VOID=TRUE

5%

470K

R9473

1

2

201

1/20W MF

GND_VOID=TRUE

5%

470K

R9472

1

2

0.1uF

402

X5R

16V

10%

C9490

1 2

MF

1/20W

201

5%

51

R9491

1

2

75

8

75 76

5%

402

MF-LF

1/16W

82

R9437

1

2

10% 10V

402

X5R

0.47UF

C9424

1

2

MF-LF

5%

402

1/16W

22

R9424

1

2

SM

STPS2L30AF

CRITICAL

D9410

1 2

DFLS1100

POWERDI-123

CRITICAL

D9425

12

SYNC_DATE=10/16/2010

SYNC_MASTER=T29

DisplayPort/T29 A Connector

SMC_S4_WAKESRC_EN

PP3V3_S5

DPAPWRSW_P3V3_ON

DPAPWRSW_P3V3_ON_L

MIN_NECK_WIDTH=0.20 MM

PP3V3_SW_DPAPWR

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM

DPAPWRSW_HV_DET_R_L

VOLTAGE=18V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3RHV_SW_DPAPWR

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_1

DPAPWR_FB_DIV

DPAPWRSW_IFLT

PP15V_T29

DPAPWRSW_VREF

DPAPWRSW_HV_DET_L

T29DPA_CONFIG1_RC

T29DPA_HPD

T29DPA_CONFIG2_RC

DP_A_EXT_AUXCH_P

T29DPA_ML_N<3>

T29DPA_ML_P<3>

DPAPWRSW_ILIM

T29_D2R_C_N<0>

DPAPWRSW_HV_DET

T29_D2R_C_P<0>

DPAPWRSW_ON_L_C

DPAPWRSW_ON_C

T29_A_HV_EN

T29DPA_ML_P<0>

T29DPA_ML_C_P<0>

DPAPWRSW_HVEN_L_R TP_DPAPWRSW_FLT_L

VOLTAGE=18V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PPHV_SW_DPAPWR

T29_A_HV_EN

DPAPWRSW_NPN_E

DPAPWRSW_CT

T29DPA_ML_P<1>

T29DPA_ML_N<2>

T29DPA_ML_C_N<2>

T29DPA_ML_C_P<2>

T29DPA_ML_N<0>

T29DPA_ML_N<1>

T29_A_BIAS

DPAPWR_BLDR_E

MIN_LINE_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM

VOLTAGE=18V

DPACONN_20_RC

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

T29_D2R_C_N<1>

T29_D2R_C_P<1>

DP_A_EXT_AUXCH_N

T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_19

T29DPA_ML_P<2>

T29DPA_HPD_R

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_8

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

GND_DPACONN_13

GND_DPACONN_7

MIN_LINE_WIDTH=0.38 MM VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

T29DPA_ML_C_N<0>

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

GND_DPACONN_14

T29_A_BIAS_R

T29_A_BIAS_D2RP1

T29_A_BIAS

VOLTAGE=3.3V

T29_A_BIAS_D2RN1

DPAPWR_BLDR_B

VOLTAGE=18V

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_SW_DPAPWR_UF

MIN_NECK_WIDTH=0.20 MM

T29_A_HV_EN

94 OF 109

76 OF 86

6 7 8

17 19 20

22 23 24 26 30

46 56 66 72 73

74 85

8

75

7 8

36

8 36

75

76

83

8

75 76

83

8

36 75 76

IN

VDDIO

VIN

VLDO

SW_0 SW_1

FB

OUT3

OUT2

OUT1

OUT4 OUT5 OUT6

GND_SW

GND_S

GND_L

GND_SW

VSYNC

ISET

FILTER

FSET

SCLK

PWM

SDA

FAULT

EN

IN

D

SG

D

SG

OUT

IN

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

PPBUS S0 LCDBkLT FET

Addr: 0x58(Wr)/0x59(Rd)

(EEPROM should set EN_I_RES=1)

I_LED=369/Riset

I_LED=22.7mA

see spec for others

measurement on LED strings.

10.2 ohm resistors for current

ON THE SENSOR PAGE

AND PPBUS_SW_BKL

PPBUS_SW_LCDBKLT_PWR

THERE IS A SENSE RESISTOR BETWEEN

LOADING

0.65 A (EDP)

Fpwm=9.62kHz

P-TYPE

MOSFET

CHANNEL

FDC638APZ

43 mOhm @4.5V

RDS(ON)

402

MF-LF

1/16W

10K

5%

R9755

1

2

1/16W

10K

5%

MF-LF

402

R9741

1 2

PLACE_NEAR=D9701.2:5mm

1210-1

50V X5R

CRITICAL

10%

10UF

C9799

1

2

1210-1

10UF

10% 50V

CRITICAL

X5R

PLACE_NEAR=D9701.2:3mm

C9797

1

2

10% X5R

NO STUFF

1UF

402

6.3V

C9741

1 2

CRITICAL

33UH-1.8A-110MOHM

1217AS-2SM

L9701

1 2

20%

10UF

6.3V X5R 603

NO STUFF

C9740

1 2

1/16W MF-LF

402

5%

33

R9704

1 2

6

74

LP8550

25-BUMP-MICRO

CRITICAL

U9701

A3

C3

A5

C2

B4

E4B5A1

A2

B3

E5 D5 C5 E3 E2 E1

A4

D3 D4

B1 B2

C4C1D1

D2

26

8

18

SOT563

SSM6N15FEAPE

Q9707

3

5

4

147K

402

MF-LF

1/16W

1%

R9789

1

2

SOT563

SSM6N15FEAPE

Q9707

6

2

1

3AMP-32V-467

603-HF

BOTTOM

F9700

1 2

402

MF-LF

301K

1/16W

1%

R9788

1

2

10% 16V

0.1UF

402

X5R

C9782

1

2

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

Q9706

1 2 5 6

3

4

SM

PLACE_NEAR=C9797.1:5mm

XW9720

1 2

1/16W

5%

0

MF-LF

402

R9757

1 2

CRITICAL

10UF

805

X5R

10% 25V

PLACE_NEAR=L9701.1:3mm

C9712

1

2

PLACE_NEAR=L9701.1:3mm

25V

10% 402

0.1UF

X5R

C9713

1

2

10% 50V

402

PLACE_NEAR=U9701.A5:3mm

X7R-CERM

220PF

C9796

1

2

PLACE_NEAR=L9701.2:3mm

SOD-123

CRITICAL

RB160M-60G

D9701

1 2

0

1/16W MF-LF

5%

402

BKLT:PROD

PLACE_NEAR=U9701.E1:10mm

BOTTOM

R9722

1 2

0

1/16W MF-LF

5%

402

BKLT:PROD

PLACE_NEAR=U9701.E2:10mm

BOTTOM

R9721

1 2

402

5%

MF-LF

1/16W

BKLT:PROD

0

BOTTOM

PLACE_NEAR=U9701.E3:10mm

R9720

1 2

6

74

6

74

0

MF-LF

5%

1/16W

402

R9753

1 2

6

74

6

74

6

74

6

74

0

5%

MF-LF

402

1/16W

BKLT:PROD

PLACE_NEAR=U9701.D5:10mm

BOTTOM

R9718

1 2

BKLT:PROD

1/16W MF-LF

402

5%

0

PLACE_NEAR=U9701.C5:10mm

BOTTOM

R9719

1 2

0

1/16W

5%

402

MF-LF

BKLT:PROD

PLACE_NEAR=U9701.E5:10mm

BOTTOM

R9717

1 2

100K

402

1% MF-LF

1/16W

R9715

2

1

301K

402

MF-LF

1/16W

1%

R9731

1 2

603-1

10%

1UF

25V X5R

PLACE_NEAR=U9701.D1:5mm

C9710

1

2

16V 402

X5R

0.1UF

10%

PLACE_NEAR=U9701.C4:4mm

C9711

1

2

SM

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

XW9710

1 2

10% 402

CERM

16V

0.01UF

PLACE_NEAR=U9701.D1:3mm

C9714

1

2

8

18

CERM

5%

402

50V

33PF

C9704

1

2

MF-LF

1/16W

1%

16.2K

402

R9714

1

2

16 23 27 29 31 42 48 62 81

MF-LF

402

1/16W

1%

NO STUFF

47.0K

R9740

1 2

90.9K

1% 1/16W MF-LF

402

R9716

1

2

1/16W MF-LF

5%

0

402

NO STUFF

R9754

1

2

BKLT:ENG

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

3

R9720,R9721,R9722

103S0198

BKLT:ENG3

R9717,R9718,R9719

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

103S0198

SYNC_DATE=06/25/2010

SYNC_MASTER=VEMURI_K90I

LCD Backlight Driver

BKL_FSET

SMBUS_PCH_CLK

LCD_BKLT_PWM

SMBUS_PCH_DATA

BKL_VSYNC

LCDBKLT_EN_L

BKLT_PLT_RST_L

LCD_BKLT_EN

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_5

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_1

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

VOLTAGE=12.6V

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm

BKL_FLTR_R

BKL_SCL

VOLTAGE=50V

MIN_NECK_WIDTH=0.375 MM

PPVOUT_SW_LCDBKLT

MIN_LINE_WIDTH=0.5 MM

PP5V_S0

PPBUS_SW_LCDBKLT_PWR_SW

SWITCH_NODE=TRUE DIDT=TRUE

VOLTAGE=50V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM

PP3V3_S0

BKL_EN

BKL_PWM

BKL_VSYNC_R

LCDBKLT_EN_DIV

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

PPBUS_S0_LCDBKLT_FUSED

TP_BKL_FAULT

PLACE_SIDE=BOTTOM

BKL_ISET

GND_BKL_SGND

MIN_LINE_WIDTH=0.4 MM VOLTAGE=0V

MIN_NECK_WIDTH=0.2 MM

PPBUS_G3H

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN5 BKL_ISEN6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PPVOUT_SW_LCDBKLT_FB

VOLTAGE=50V

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.1 MM

PPBUS_SW_BKL

BKL_SDA

BKL_FLTR

LCDBKLT_DISABLE

97 OF 109

77 OF 86

8

77

8

77

6

74

6 7

22 42 47 52 54 65 68 70

72 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50 51 52 54 57 61 62 71

72 73 74 75 85

6 7 8

36 40

49 50 63 64

8

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SPACING

PHYSICAL

NET_TYPE

Most CPU signals with impedance requirements are 50-ohm single-ended.

(FSB_CPURST_L)

SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7

ELECTRICAL_CONSTRAINT_SET

CPU Net Properties

PCI-Express

SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7

Some signals require 27.4-ohm single-ended impedance.

CPU_VCCSA_VID<0> CPU_VCCSA_VID<1>

CPU Signal Constraints

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

I115 I116

I117

I118 I119

I120

I121

I122 I123

I124

I125

I126 I127

I128

=STANDARD =STANDARD

=55_OHM_SE=55_OHM_SE

CPU_55S

*

=55_OHM_SE =55_OHM_SE

=50_OHM_SE =50_OHM_SE

*

=STANDARD

CPU_50S

=STANDARD

=50_OHM_SE =50_OHM_SE

=27P4_OHM_SE

7 MIL

=27P4_OHM_SE

7 MIL

=27P4_OHM_SE

*

CPU_27P4S

=27P4_OHM_SE

?*

20 MIL

CPU_COMP

=85_OHM_DIFF

PCIE_85D

=85_OHM_DIFF

*

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

*

CLK_PCIE

?

20 MIL

=90_OHM_DIFF=90_OHM_DIFFCLK_PCIE_90D

*

=90_OHM_DIFF

TOP,BOTTOM

=4X_DIELECTRIC

?

PCIE

*

PCIE

?

=3X_DIELECTRIC

CPU_AGTL

?*

=STANDARD

?

25 MIL

*

CPU_VCCSENSE

?

CPU_ITP

*

=2:1_SPACING

CPU_AGTL

?

=2x_DIELECTRIC

TOP,BOTTOM

?

CPU_8MIL

*

8 MIL

SYNC_MASTER=ANNE_K90I

SYNC_DATE=06/08/2010

CPU Constraints

CPU_VCCAXG_SENSE

CPU_VCCSENSE_P

CPU_27P4S

CPU_VCCSENSE

CPU_VCCAXG_SENSE

CPU_VCCSENSE_N

CPU_27P4S

CPU_VCCSENSE

CPU_VALSENSE

CPU_27P4S

CPU_VDDQ_SENSE_N

CPU_VCCSENSE

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

XDP_CPU_CLK100M_P

CLK_PCIE

CLK_PCIE_90D

ITPCPU_CLK100M

ITPCPU_CLK100M_P

CPU_AGTL

CPU_50S

CPU_VCCIO_SEL

CPU_AGTL

PM_EXT_TS_L<1>

CPU_50S

CPU_ITP

XDP_CPU_PRDY_L

CPU_50S

PM_MEM_PWRGD

CPU_AGTL

CPU_50S

PM_MEM_PWRGD

CPU_AGTL

CPU_50SPM_SYNC

PM_SYNC

PCIE

CPU_PECI

CPU_50S

CPU_ITP

XDP_BPM_L

CPU_50S

XDP_BPM_L<3..0>

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCIOSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCIOSENSE_N

CPU_VCCAXG_SENSE

CPU_VCCSENSE

CPU_27P4S

CPU_AXG_SENSE_P

CPU_VCCAXG_SENSE

CPU_AXG_SENSE_N

CPU_VCCSENSE

CPU_27P4S

CPU_VALSENSE

CPU_VDDQ_SENSE_P

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

CPU_VALSENSE

CPU_VCC_VALSENSE_N

CPU_VCCSENSE

CPU_50S CPU_ITPXDP_TDO

XDP_CPU_TDO

CPU_50SXDP_TCK CPU_ITP

XDP_CPU_TCK

CPU_50S CPU_ITP

XDP_TRST_L

XDP_CPU_TRST_L

CLK_PCIE

CLK_PCIE_90D

ITPCPU_CLK100M

ITPXDP_CLK100M_P

CPU_AGTL

CPU_CATERR_L

CPU_50S

CPU_CATERR_L

CPU_AGTL

PM_EXT_TS_L<0>

CPU_50S

CPU_ITP

XDP_CPU_PREQ_L

CPU_50S

CPU_AGTL

FDI_LSYNC<1..0>

CPU_50S

CPU_AGTL

FDI_FSYNC<1..0>

CLK_PCIE

CLK_PCIE_90D

ITPCPU_CLK100M

ITPXDP_CLK100M_N

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_90D

XDP_CPU_CLK100M_N

CPU_27P4S

CPU_COMP

CPU_PEG_COMP

ITPCPU_CLK100M_N

CLK_PCIE

CLK_PCIE_90D

ITPCPU_CLK100M

PCIE_85DFDI_DATA

PCIE

FDI_DATA_P<7:0>

DMI_S2N

PCIE_85D

PCIE

DMI_S2N_N<3:0>

CPU_ITP

XDP_CPURST_L

CPU_50S

XDP_BPM_R_L

CPU_ITPCPU_50S

CPU_CFG<15..12>

CPU_50S CPU_ITPXDP_TMS

XDP_CPU_TMS

CPU_ITPCPU_50S

XDP_CPU_TDI

XDP_TDI

DMI_S2N_P<3:0>

PCIE

PCIE_85D

DMI_S2N

CLK_PCIE_90D

CLK_PCIE

DMI_CLK100M

DMI_CLK100M_CPU_N

DMI_CLK100M

CLK_PCIE_90D

CLK_PCIE

DMI_CLK100M_CPU_P

CPU_PROCHOT_L

CPU_AGTL

CPU_50S

CPU_PROCHOT_L

CPU_AGTL

CPU_PWRGD

CPU_50S

CPU_PWRGD

PM_THRMTRIP_L

CPU_8MIL

CPU_50S

PM_THRMTRIP_L

CPU_ITPCPU_50S

CPU_CFG<11..0>

CPU_COMP

CPU_SM_RCOMP

CPU_27P4S

CPU_SM_RCOMP<2>

CPU_27P4S

CPU_COMP

CPU_SM_RCOMP

CPU_SM_RCOMP<1>

CPU_SM_RCOMP

CPU_COMP

CPU_27P4S

CPU_SM_RCOMP<0>

PCIE

PCIE_85D

PEG_D2R_C_N<15..0>

PCIE

PCIE_85D

PEG_D2R_C_P<15..0>

PCIE

PCIE_85D

PEG_R2D_P<15..0> PEG_R2D_N<15..0>

PCIE_85D

PCIE

PCIE_85D

PEG_R2D_C_N<15..0>

PEG_D2R

PCIE

PCIE_85D

PEG_D2R_P<15..0>

PCIE

PEG_D2R_N<15..0>

PCIE_85D

CPU_COMP

CPU_27P4S

EDP_COMP

CPU_COMP

CPU_50S

CPU_VIDSOUT

CPU_SVIDSOUT

CPU_VIDSCLK

CPU_COMP

CPU_50S

CPU_SVIDSCLK

XDP_DBRESET_L

CPU_ITPCPU_50S

DMI_N2S

PCIE_85D

PCIE

DMI_N2S_N<3:0>

DMI_N2S

PCIE

PCIE_85D

DMI_N2S_P<3:0>

PCIE_85DFDI_DATA

PCIE

FDI_DATA_N<7:0>

CPU_AGTL

CPU_50S

FDI_INT

PEG_R2D

PCIE

PCIE_85D

PEG_R2D_C_P<15..0>

CPU_VIDALERT_L

CPU_COMP

CPU_50S

CPU_SVIDALERT_L

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCC_VALSENSE_P

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_AXG_VALSENSE_N

CPU_VALSENSE

CPU_AXG_VALSENSE_P

CPU_27P4S

CPU_VCCSENSE

100 OF 109

78 OF 86

12 68

12

23

10 16

12

10 23

10 17 30

10 17

10 19 45

10 23

12 70

12 68

12

9

10 23

16 23

10

10 23

9

17

9

17

16 23

23

9

10 16

9

17

9

17

23

9

23

10 23

9

17

10 16

10 46 68

10 19 23

10 19

9

23

10

8

9

12 68

10 23 26

9

17

9

17

9

17

9

17

8

12 68

9

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

D

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8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

Memory Bus Spacing Group Assignments

Need to support MEM_*-style wildcards!

Sandybridge SFF 2C when routed on Type-3 (Through hole) should follow rPGA guidelines

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm]. CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm.

A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to each other should match within 5.08mm. DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric. Maximum length of any signal from die pad to SODIMM pad is 119.83mm, from procesor ball to SODIMM pad is 88.9mm. SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5

SPACING

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

per Huron River SFF DG rev1.0 (#438297).

CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs.

DQ to DQS matching per byte lane should be within 0.127mm.

DDR3:

NET_TYPE

Memory Bus Constraints

ISL10

N

=85_OHM_DIFF =85_OHM_DIFF

MEM_85D

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

ISL3,ISL4,ISL9

Y

=50_OHM_SE =50_OHM_SE

=STANDARD =STANDARD

=50_OHM_SE

MEM_50S

=85_OHM_DIFF

Y

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

MEM_85D

=85_OHM_DIFF

TOP,BOTTOM

=STANDARD

=37_OHM_SE=37_OHM_SE =37_OHM_SE =37_OHM_SE

MEM_37S

=STANDARD

*

=40_OHM_SE=40_OHM_SE=40_OHM_SE =40_OHM_SE

=STANDARD

*

=STANDARD

MEM_40S

MEM_CLK2MEM

MEM_DATA

MEM_CLK

*

MEM_CTRL

*

MEM_CTRL2CTRL

MEM_CTRL

MEM_CMD2MEM

*

MEM_CMD

MEM_CMD2MEM

*

MEM_CMD MEM_CLK

MEM_CMD2CMD

MEM_CMD

*

MEM_CMD

*

MEM_CMD2MEM

MEM_CMD MEM_DQS

MEM_DATA

MEM_CMD2MEM

*

MEM_CMD

MEM_DATA2MEM

MEM_CMD

*

MEM_DATA

MEM_DATA2MEM

MEM_CTRL

*

MEM_DATA

*

MEM_DATA2MEM

MEM_DATA

MEM_CLK

MEM_DATA

*

MEM_DATA2DATA

MEM_DATA

MEM_DQS

*

MEM_DATA

MEM_DATA2MEM

* *

MEM_CLK

MEM_2OTHER

MEM_CTRL

**

MEM_2OTHER

MEM_CTRL

*

MEM_CLK

MEM_CLK2MEM

MEM_CLK

*

MEM_CLK2MEM

MEM_CLK

MEM_CMD

*

MEM_CLK

MEM_CLK2MEM

*

MEM_CLK

MEM_CLK2MEM

MEM_DQS

*

MEM_CTRL2MEM

MEM_CTRL

MEM_CMD

*

MEM_CTRL2MEM

MEM_CTRL MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_DQS

MEM_DATA2MEM =3:1_SPACING

?*

MEM_CTRL2MEM

MEM_CLK

*

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS MEM_CLK

MEM_DQS2MEM

*

MEM_DQS

MEM_CTRL

* *

MEM_CMD

MEM_2OTHER

* *

MEM_2OTHER

MEM_DQS

**

MEM_2OTHER

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS MEM_DQS

*

MEM_DATA

MEM_DQS

MEM_DQS2MEM

*

MEM_CMD

MEM_DQS2MEM

MEM_DQS

ISL10

N

=50_OHM_SE =50_OHM_SE

=STANDARD =STANDARD

=50_OHM_SE

MEM_50S

ISL3,ISL4,ISL9

=85_OHM_DIFF =85_OHM_DIFF

MEM_85D

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

Y

MEM_2OTHER

* ?

25 MILS

MEM_DQS2MEM

=3:1_SPACING

* ?

=1.5:1_SPACING

MEM_DATA2DATA

* ?

MEM_CMD2MEM

=3:1_SPACING

?*

MEM_CMD2CMD

=1.5:1_SPACING

?*

=2.5:1_SPACING

MEM_CTRL2MEM

?*

=3:1_SPACING

MEM_CTRL2CTRL

* ?

=4:1_SPACING

MEM_CLK2MEM

?*

=72_OHM_DIFF

MEM_72D

=72_OHM_DIFF

*

=72_OHM_DIFF

=72_OHM_DIFF =72_OHM_DIFF

MEM_50S

TOP,BOTTOM

Y

=50_OHM_SE =50_OHM_SE

=STANDARD=STANDARD

=50_OHM_SE

Memory Constraints

SYNC_MASTER=ANNE_K90I

SYNC_DATE=05/28/2010

MEM_A_DQS6

MEM_DQS

MEM_A_DQS_P<6>

MEM_85D

MEM_DQS

MEM_A_DQS_N<5>

MEM_A_DQS5

MEM_85D

MEM_DQS

MEM_A_DQS_N<6>

MEM_A_DQS6

MEM_85D

MEM_DQS

MEM_A_DQS_N<7>

MEM_A_DQS7

MEM_85D

MEM_B_CLK

MEM_72D MEM_CLK

MEM_B_CLK_P<5..0>

MEM_DQS

MEM_B_DQS_P<1>

MEM_B_DQS1

MEM_85D

MEM_DQS

MEM_B_DQS_P<3>

MEM_B_DQS3

MEM_85D

MEM_85D MEM_DQS

MEM_B_DQS_N<3>

MEM_B_DQS3

MEM_DQS

MEM_B_DQS_N<2>

MEM_B_DQS2

MEM_85D

MEM_85D MEM_DQS

MEM_B_DQS_P<2>

MEM_B_DQS2

MEM_DQS

MEM_B_DQS_N<1>

MEM_B_DQS1

MEM_85D

MEM_DQS

MEM_B_DQS_N<0>

MEM_B_DQS0

MEM_85D

MEM_DQS

MEM_B_DQS_P<0>

MEM_B_DQS0

MEM_85D

MEM_DATA

MEM_B_DQ<55..48>

MEM_B_DQ_BYTE6 MEM_50S

MEM_DATA

MEM_B_DQ<39..32>

MEM_B_DQ_BYTE4 MEM_50S

MEM_B_DQ<31..24>

MEM_DATA

MEM_B_DQ_BYTE3 MEM_50S

MEM_DATA

MEM_B_DQ<23..16>

MEM_B_DQ_BYTE2 MEM_50S

MEM_DATA

MEM_B_DQ<15..8>

MEM_B_DQ_BYTE1 MEM_50S

MEM_DATA

MEM_B_DQ<7..0>

MEM_B_DQ_BYTE0 MEM_50S

MEM_40S MEM_CMD

MEM_B_WE_L

MEM_B_CMD

MEM_DQS

MEM_A_DQS_P<7>

MEM_A_DQS7

MEM_85D

MEM_A_DQS5

MEM_DQS

MEM_A_DQS_P<5>

MEM_85D

MEM_DQS

MEM_A_DQS_N<3>

MEM_A_DQS3

MEM_85D

MEM_DQS

MEM_A_DQS_P<3>

MEM_A_DQS3

MEM_85D

MEM_DQS

MEM_A_DQS_N<2>

MEM_A_DQS2

MEM_85D

MEM_DQS

MEM_A_DQS_N<4>

MEM_A_DQS4

MEM_85D

MEM_DQS

MEM_A_DQS_P<4>

MEM_A_DQS4

MEM_85D

MEM_DQS

MEM_A_DQS1

MEM_A_DQS_P<1>

MEM_85D

MEM_50S

MEM_A_DQ<47..40>

MEM_A_DQ_BYTE5

MEM_DATA

MEM_A_DQ_BYTE3

MEM_A_DQ<31..24>

MEM_50S

MEM_B_DQS5

MEM_DQS

MEM_B_DQS_N<5>

MEM_85D

MEM_DQS

MEM_B_DQS_N<4>

MEM_B_DQS4

MEM_85D

MEM_B_DQS5

MEM_DQS

MEM_B_DQS_P<5>

MEM_85D

MEM_DQS

MEM_B_DQS_P<6>

MEM_B_DQS6

MEM_85D

MEM_DQS

MEM_B_DQS_P<7>

MEM_B_DQS7

MEM_85D

MEM_B_DQS6

MEM_DQS

MEM_B_DQS_N<6>

MEM_85D

MEM_DATA

MEM_B_DQ<63..56>

MEM_B_DQ_BYTE7 MEM_50S

MEM_DATA

MEM_A_DQ<23..16>

MEM_A_DQ_BYTE2 MEM_50S

MEM_DATA

MEM_A_DQ<63..56>

MEM_A_DQ_BYTE7 MEM_50S

MEM_40S MEM_CMD

MEM_B_RAS_L

MEM_B_CMD

MEM_DQS

MEM_B_DQS7

MEM_B_DQS_N<7>

MEM_85D

MEM_DQS

MEM_B_DQS_P<4>

MEM_B_DQS4

MEM_85D

MEM_40S

MEM_B_A<15..0>

MEM_CMD

MEM_B_CMD

MEM_37S

MEM_CTRL

MEM_B_CNTL

MEM_B_CS_L<3..0>

MEM_B_DQ<47..40>

MEM_DATA

MEM_B_DQ_BYTE5 MEM_50S

MEM_40S MEM_CMD

MEM_B_CAS_L

MEM_B_CMD

MEM_CMDMEM_40S

MEM_B_BA<2..0>

MEM_B_CMD

MEM_37S

MEM_CTRL

MEM_B_CNTL

MEM_B_ODT<3..0>

MEM_B_CNTL

MEM_37S

MEM_CTRL

MEM_B_CKE<3..0>

MEM_B_CLK

MEM_72D

MEM_B_CLK_N<5..0>

MEM_CLK

MEM_50S

MEM_A_DQ<7..0>

MEM_A_DQ_BYTE0

MEM_DATA

MEM_40S MEM_CMD

MEM_A_WE_L

MEM_A_CMD

MEM_40S

MEM_A_CAS_L

MEM_CMD

MEM_A_CMD

MEM_CMDMEM_40S

MEM_A_BA<2..0>

MEM_CTRL

MEM_37S

MEM_A_ODT<3..0>

MEM_A_CNTL

MEM_CTRL

MEM_37S

MEM_A_CS_L<3..0>

MEM_A_CNTL

MEM_CTRL

MEM_A_CKE<3..0>

MEM_37S

MEM_A_CNTL

MEM_A_CLK

MEM_72D MEM_CLK

MEM_A_CLK_P<5..0>

MEM_CLK

MEM_A_CLK_N<5..0>

MEM_72D

MEM_A_CLK

MEM_A_CMD

MEM_40S MEM_CMD

MEM_A_A<15..0>

MEM_40S MEM_CMD

MEM_A_CMD

MEM_A_RAS_L

MEM_A_DQ_BYTE4

MEM_DATA

MEM_A_DQ<39..32>

MEM_50S

MEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_DATA

MEM_50S

MEM_A_DQS2

MEM_DQS

MEM_A_DQS_P<2>

MEM_85D

MEM_DQS

MEM_A_DQS_N<1>

MEM_A_DQS1

MEM_85D

MEM_DQS

MEM_A_DQS_N<0>

MEM_A_DQS0

MEM_85D

MEM_A_DQS_P<0>

MEM_DQS

MEM_A_DQS0

MEM_85D

MEM_A_DQ<15..8>

MEM_A_DQ_BYTE1

MEM_DATA

MEM_50S

101 OF 109

79 OF 86

11 28

11 29

11 28

11 28 29

11 28

11 28 29

11 28

11 29

11 28

11 29

11 28

11 29

11 28

11 29

11 28

11 27

11 27 28

11 28

11 27 28

11 28

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

Digital Video Signal Constraints

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

SATA Interface Constraints

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

PCH Net Properties

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB 2.0 Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

SPACING

PHYSICAL

I213 I214

I215 I216

I217

I218

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

DP_85D

*

=85_OHM_DIFF

LVDS

* ?

=3x_DIELECTRIC

=85_OHM_DIFF

*

USB_85D

=85_OHM_DIFF

USB

?

TOP,BOTTOM

=4x_DIELECTRIC

=3x_DIELECTRIC

SATA

TOP,BOTTOM

?

?*

8 MIL

SATA_ICOMP

* ?

=2x_DIELECTRIC

USB

=STANDARD

PCH_USB_RBIAS

=STANDARD

*

8 MIL

=STANDARD

8 MIL

=STANDARD

DISPLAYPORT

?

=4x_DIELECTRIC

TOP,BOTTOM

=4x_DIELECTRIC

LVDS

?

*

SATA

?

=4x_DIELECTRIC

=3x_DIELECTRIC

?*

DISPLAYPORT

LVDS_90D

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF

*

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF

SATA_90D

=90_OHM_DIFF

PCH Constraints 1

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

USB_85D

USB

USB_SDCARD_N

PCIE_CLK100M_PCH_N

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

NC_FSB_CLK133M_PCH_P

CLK_PCIE_90D

CLK_PCIE

PCH_CLK100M_SATA_P

PCH_DIFFCLK_UNUSED_

CLK_PCIE

CLK_PCIE_90D

PCH_CLK100M_SATA_N

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

PCH_CLK14P3M_REFCLK

CPU_50S

LPC_CLK33M

PCH_CLK33M_PCIIN

CLK_PCIE

CPU_50S

GFX_CLK_DPLLSS

GFX_CLK120M_DPLLSS_P

CLK_PCIE

CLK_PCIE_90D

GFX_CLK_DPLLSS

GFX_CLK120M_DPLLSS_N

CLK_PCIE

CLK_PCIE_90D

PCH_DIFFCLK_UNUSED_

PCH_CLK96M_DOT_P

CLK_PCIE_90D

CLK_PCIE

PCH_SATAICOMP

SATA_ICOMP

PCH_SATA_ICOMP

USB_HUB1_UP

USB_HUB1_UP_P

USB

USB_85D

USB_HUB1_UP_N

USB_85D

USB

USB_85D

USB_IR_P

USB_IR

USB

USB_SDCARD_P

USB_85D

USB

USB_SDCARD

PCH_CLK96M_DOT_N

PCH_DIFFCLK_UNUSED_

CLK_PCIE

CLK_PCIE_90D

LVDS_90D

LVDS

TP_LVDS_IG_B_CLKP

LVDS_90D

LVDS

TP_LVDS_IG_B_CLKN

LVDS_IG_A_CLK_P

LVDS

LVDS_90D

LVDS_IG_A_CLK

DP_85D

DP_ML

DP_IG_ML_P<3..0>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_ML

DP_IG_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_EXTA_AUXCH_C_N

DP_EXTA_AUXCH

LVDS_90D

LVDS

NC_LVDS_IG_A_DATAP<3>

LVDS

LVDS_90D

LVDS_IG_A_DATA_P<2..0>

LVDS_IG_A_DATA

DP_EXTA_AUXCH

DP_EXTA_AUXCH_C_P

DISPLAYPORT

DP_85D

USB_IR_N

USB_85D

USB

USB_EXTA_N

USB_85D

USB_EXTA

USB

NC_FSB_CLK133M_PCH_N

CLK_PCIE_90D

CLK_PCIE

USB_85D

USB_TPAD_N

USB

USB_EXTA

USB_85D

USB

USB_EXTA_P

USB_HUB2_UP_P

USB_HUB2_UP

USB

USB_85D

PCH_DIFFCLK_UNUSED_

PCIE_CLK100M_PCH_P

CLK_PCIE

CLK_PCIE_90D

PCH_USB_RBIAS

PCH_USB_RBIAS PCH_USB_RBIAS

USB_85D

USB_BRCRYPT_N

USB

USB_BRCRYPT

USB_85D

USB_BRCRYPT_P

USB

USB_TPAD_P

USB_85D

USB_TPAD

USB_BT_N

USB

USB_BT

USB_85D

USB_BT_P

USB_BT

USB_85D

USB

USB_CAMERA_CONN_N

USB_85D

USB

USB_CAMERA_CONN_P

USB_CAMERA

USB_85D

USB

USB_85D

T29_A_RSVD_N

USB

USB_CAMERA_N

USB_85D

USB

USB_CAMERA_P

USB_CAMERA

USB_85D

T29_A_RSVD_P

USB_85D

USB

USB_85D

USB

USB_EXTB_N

USB_85D

USB_EXTB

USB

USB_EXTB_P

USB_HUB2_UP_N

USB

USB_85D

USB_EXTC_N

USB

USB_85D

USB

USB_EXTC_P

USB_EXTC

USB_T29A_N

USB

USB_85D

USB_EXTD

USB_T29A_P

USB

USB_85D

LVDS

LVDS_90D

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK

LVDS

LVDS_IG_A_DATA

LVDS_90D

LVDS_IG_A_DATA_N<2..0>

LVDS_90D

LVDS

NC_LVDS_IG_A_DATAN<3>

LVDS_90D

LVDS_IG_B_DATA_P<3..0>

LVDS

LVDS_90D

LVDS_IG_B_DATA_N<3..0>

LVDS

SATA_HDD_R2D

SATA

SATA_90D

SATA_HDD_R2D_C_P

SATA_HDD_R2D

SATA

SATA_90D

SATA_HDD_R2D_C_N

SATA

SATA_90D

SATA_HDD_R2D_P

SATA_HDD_R2D_CONN SATA_HDD_R2D_CONN

SATA

SATA_90D

SATA_HDD_R2D_N

SATA_HDD_D2R

SATA

SATA_90D

SATA_HDD_D2R_P

SATA_HDD_D2R

SATA

SATA_90D

SATA_HDD_D2R_N

SATA_HDD_D2R_CONN

SATA

SATA_90D

SATA_HDD_D2R_C_P

SATA

SATA_90D

SATA_HDD_D2R_C_N

SATA_HDD_D2R_CONN SATA_ODD_R2D

SATA_90D

SATA

SATA_ODD_R2D_C_P

SATA

SATA_90D

SATA_ODD_R2D_C_N

SATA_ODD_R2D

SATA_HDD_D2R_RC_N

SATA_90D

SATA

SATA_HDD_D2R_CONN

SATA

SATA_90D

SATA_HDD_D2R_RC_P

SATA_HDD_D2R_CONN

SATA

SATA_90D

SATA_ODD_D2R_N

SATA_ODD_D2R

SATA

SATA_90D

SATA_HDD_R2D_RC_N

SATA_HDD_R2D_CONN

SATA

SATA_90D

SATA_HDD_R2D_CONN

SATA_HDD_R2D_RC_P

SATA_ODD_D2R

SATA

SATA_90D

SATA_ODD_D2R_P

SATA

SATA_90D

SATA_ODD_R2D_N

SATA_ODD_R2D

SATA

SATA_90D

SATA_ODD_R2D_P

SATA_ODD_R2D

102 OF 109

80 OF 86

16 25

8

16 25

16 26

16 25

16

18 24

24 44

16 25

6 8

18

6 8

18

18 74

8

17 75 81

8

18

6

18 74

8

17 75 81

24 44

24 43

8

24 53

24 43

18 24

16 25

18

24 53

6

24 32

6

24 32

6

32

6

32

8

75

18 32

8

75

24 43

18 24

8

24

8

24

8

24

8

24

18 74

6

18 74

8

18

8

16 42

6

42

6

42

16 42

6

42

6

42

16 42

42

16 42

42

16 42

6

42

6

42

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Clock Net Properties

NOTE: 25MHz system clocks very sensitive to noise.

PHYSICAL

NET_TYPE

SPACING

Chipset Net Properties

SPACING

PHYSICAL

PCH Net Properties

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

System Clock Signal Constraints

PCI-Express Signal Constraints

DisplayPort Signal Constraints

SIO Signal Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SPI Interface Constraints

SMBus Interface Constraints

LPC Bus Constraints

HD Audio Interface Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

ELECTRICAL_CONSTRAINT_SET

I235

I236

I237

I238

I239

I240

I241

I242

I243

I244

I245

I246

I247

I248

I249

I250

I251

I252

I253

I254

I255

I256

I257

I258

I267

I268 I269

I270

I271

I272

I273

I274

I275

I276

I277

I278

I279 I280

I281

I282 I283

I284

I285 I286

I287

=50_OHM_SE

=STANDARD =STANDARD

HDA_50S

=50_OHM_SE=50_OHM_SE=50_OHM_SE

*

?

6 MIL

LPC

*

?*

8 MIL

CLK_LPC

=STANDARD

=50_OHM_SE

=STANDARD

*

LPC_50S

=50_OHM_SE =50_OHM_SE =50_OHM_SE

=STANDARD

=50_OHM_SE

=STANDARD

*

CLK_LPC_50S

=50_OHM_SE =50_OHM_SE =50_OHM_SE

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=STANDARD

*

=STANDARD

=50_OHM_SE

SMB_50S

=2x_DIELECTRIC

SMB

?*

*

HDA

=2x_DIELECTRIC

?

CLK_SLOW

*

8 MIL

=STANDARD

CLK_SLOW_55S

=55_OHM_SE

*

=STANDARD

=55_OHM_SE=55_OHM_SE =55_OHM_SE

=55_OHM_SE =55_OHM_SE =55_OHM_SE

SPI_55S

=55_OHM_SE

=STANDARD=STANDARD

*

SPI

?

8 MIL

TOP,BOTTOM

=4x_DIELECTRIC

?

DISPLAYPORT

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

*

=85_OHM_DIFF

DP_85D

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

*

=85_OHM_DIFF

PCIE_85D

?*

=3x_DIELECTRIC

DISPLAYPORT

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF

*

CLK_PCIE_90D =90_OHM_DIFF

=90_OHM_DIFF

CLK_25M_55S

*

=55_OHM_SE=55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

PCIE

?*

=3X_DIELECTRIC

*

CLK_PCIE

20 MIL

?

CLK_SLOW_55S

=STANDARD=STANDARD

=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

*

=2x_DIELECTRIC

CLK_SLOW

?*

=5x_DIELECTRICCLK_25M

* ?

PCIE

?

=4X_DIELECTRIC

TOP,BOTTOM

PCH Constraints 2

SYNC_DATE=05/15/2010

SYNC_MASTER=K91_MLB

PCH_VSS_NCTF<2>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<1>

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<5>

PCIE_AP_R2D_C_P

PCIE

PCIE_85D

PCIE_AP_R2D

HDA_SDOUT_R

HDA

HDA_50S

HDA

HDA_SYNC

HDA_50S

HDA_SYNC

CLK_LPC

LPC_CLK33M_SMC_R

CLK_LPC_50S

LPC_CLK33M

CLK_LPC

LPC_CLK33M_SMC

CLK_LPC_50S

LPC_CLK33M

CLK_LPC

LPC_CLK33M_LPCPLUS

CLK_LPC_50S

LPC_CLK33M

SMB

SMBUS_PCH_CLK

SMB_50S

PCIE_CLK100M_T29 CLK_PCIE

CLK_PCIE_90D

PCIE_CLK100M_T29_P

SYSCLK_CLK32K_RTC

CLK_SLOW_55S

CLK_SLOW

SYSCLK_CLK25M_SB

CLK_25M

SYSCLK_CLK25M_SB

CLK_25M_55S

SYSCLK_CLK25M_ENET

CLK_25M_55S

CLK_25M

PCH_VSS_NCTF<19>

CPU_27P4S

CPU_COMP

DP_85D

DP_EXTA_AUXCH_C_N

DISPLAYPORT

DP_EXTA_AUXCH

DP_EXTA_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_EXTA_AUXCH

DP_85D

DISPLAYPORT

DP_EXTA_ML_C_P<3..0>

DP_EXTA_ML

DP_INT_ML_C_N<3..0>

DP_INT_ML

DISPLAYPORT

DP_85D

DP_EXTA_ML

DISPLAYPORT

DP_EXTA_ML_C_N<3..0>

DP_85D

DISPLAYPORT

DP_EXTA_ML_P<3..0>

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH_N

DP_EXTA_ML_N<3..0>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH_P

PCIE_85D

PCIE

PCIE_T29_D2R

PCIE_T29_D2R_N<3..0>

PCIE_CLK100M_T29 CLK_PCIE

CLK_PCIE_90D

PCIE_CLK100M_T29_N

PCIE_85D

PCIE

PCIE_T29_D2R

PCIE_T29_D2R_P<3..0>

PCIE

PCIE_85D

PCIE_T29_R2D_P<3..0>

PCIE

PCIE_85D

PCIE_T29_R2D_N<3..0>

PCIE_85D

PCIE

PCIE_T29_R2D

PCIE_T29_R2D_C_N<3..0>

DP_INT_AUXCH_C_N

DP_INT_AUXCH DP_85D

DISPLAYPORT

LPC_AD<3..0>

LPC

LPC_AD

LPC_50S

LPC_FRAME_L

LPC

LPC_50S

LPC_FRAME_L

LPC_RESET_L

LPCPLUS_RESET_L

LPC

LPC_50S

SMB

SMB_50S

SMBUS_PCH_DATA

SMB

SMB_50S

SML_PCH_1_CLK

SMBUS_PCH_1_CLK

SMB

SMB_50S

SML_PCH_1_DATA

SMBUS_PCH_1_DATA

HDA_BIT_CLK

HDA

HDA_50S

HDA_BIT_CLK

HDA

HDA_BIT_CLK_R

HDA_50S

HDA_SYNC_R

HDA

HDA_50S

HDA_RST_L

HDA

HDA_RST_R_L

HDA_50S

HDA_RST_L

HDA

HDA_50S

HDA_SDIN0

HDA

HDA_50S

HDA_SDIN0

HDA_SDOUT

HDA

HDA_50S

HDA_SDOUT

AUD_SDI_R

HDA

HDA_50S

PM_CLK32K_SUSCLK

CLK_SLOW_55S

CLK_SLOW

PM_SUS_CLK

SPI

SPI_CLK SPI_55S

SPI_CLK_R

SPI

SPI_55S

SPI_CLK

SPI

SPI_MOSI_R

SPI_55S

SPI_MOSI

SPI

SPI_MOSI

SPI_55S

PCIE

PCIE_85D

PCIE_AP_D2R_N

PCIE_FW_R2D_P

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE_FW_R2D_N

PCIE_FW_R2D_C_N

PCIE_85D

PCIE

PCIE_FW_D2R_P

PCIE_85D

PCIE

PCIE_FW_D2R

PCIE_FW_D2R_N

PCIE_85D

PCIE

PCIE_FW_D2R_C_P

PCIE_85D

PCIE

CLK_PCIE_90D

NC_PEG_CLK100MP

CLK_PCIE

PCIE_CLK100M_AP_P

CLK_PCIE_90D

MCP_PE1_REFCLK

PCIE_CLK100M_ENET_N

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_AP_N

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_FW_N

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_FW_P

CLK_PCIE_90D

MCP_PE2_REFCLK

NC_PCIE_CLK100M_EXCARDP

CLK_PCIE

CLK_PCIE_90D

PCH_VSS_NCTF<9>

CPU_27P4S

CPU_COMP

CPU_27P4S

TP_PCH_VSS_NCTF<7>

PCH_VSS_NCTF<9>

CPU_27P4S

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<17>

CPU_COMP

PCH_VSS_NCTF<21>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<22>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<27>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<25>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<29>

CPU_27P4S

PCH_VSS_NCTF<12>

CPU_COMP

PCH_VSS_NCTF<11>

CPU_27P4S

CPU_COMP

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET

PCIE_85D

PCIE

PCIE_T29_R2D

PCIE_T29_R2D_C_P<3..0>

DP_INT_AUXCH_C_P

DP_INT_AUXCH DP_85D

DISPLAYPORT

DP_INT_ML_C_P<3..0>

DP_INT_ML

DISPLAYPORT

DP_85D

SML_PCH_0_DATA

SMB_50S

SMB

SMBUS_PCH_0_DATA

SML_PCH_0_CLK

SMB

SMBUS_PCH_0_CLK

SMB_50S

SPI_MISO

SPI

SPI_55S

SPI_MISO

PCIE

PCIE_85D

PCIE_T29_D2R_C_P<3..0>

CLK_25M_55S

SYSCLK_CLK25M_SB_R

CLK_25M

PCIE_ENET_D2R_P

PCIE_85D

PCIE

PCIE_ENET_D2R

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_ENET_R

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_T29

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_T29_R

PCIE

PCIE_85D

PCIE_T29_D2R_C_N<3..0>

SPI_CS0_R_L

SPI_55S

SPI

SPI_CS0

SPI_CS0_L

SPI_55S

SPI

PCIE_ENET_R2D_P

PCIE

PCIE_85D

PCIE

PCIE_AP_R2D_PI_N

PCIE_85D

PCIE

PCIE_AP_R2D_PI_P

PCIE_AP_R2D

PCIE

PCIE_85D

PCIE_AP_D2R_PI_N

PCIE_AP_D2R

PCIE

PCIE_85D

PCIE_AP_D2R_PI_P

PCIE_FW_D2R_C_N

PCIE

PCIE_85D

PCIE_FW_R2D_C_P

PCIE_85D

PCIE

PCIE_FW_R2D

PCIE

PCIE_85D

PCIE_AP_R2D_C_N

PCIE_AP_R2D_N

PCIE_85D

PCIE

PCIE_AP_R2D_P

PCIE_85D

PCIE

PCIE_ENET_D2R_C_N

PCIE_85D

PCIE

PCIE_ENET_D2R_C_P

PCIE_85D

PCIE

PCIE_ENET_D2R_N

PCIE_85D

PCIE

PCIE_ENET_R2D_C_N

PCIE_85D

PCIE

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D

PCIE_85D

PCIE

PCIE_ENET_R2D_N

PCIE_85D

PCIE

PCIE_AP_D2R_P

PCIE_85D

PCIE

PCIE_AP_D2R

CLK_PCIE_90D

CLK_PCIE

NC_PEG_CLK100MN

CLK_PCIE

CLK_PCIE_90D

NC_PCIE_CLK100M_EXCARDN

CPU_27P4S

PCH_VSS_NCTF<15>

CPU_COMP

103 OF 109

81 OF 86

6

16 32

16

16 57

18 26

26 45

6

26 47

16 23 27 29 31 42 48 62 77

16 34

16 26

26 37

6

8

17 75

80

8

17 75

80

8

75

8

75

8

34

16 34

8

34

8

34

6

16 45 47

6

16 45 47

6

26 47

16 23 27 29 31 42 48 62 77

16 48

16 57

16

16 57

57

16 47

47

16 47

47

16 32

39

16 39

39

8

16

16 32

16 37

16 32

16 39

8

16

6

81

6

81

6

16 37

8

34

16 48

16 47

34

16

16 37

26 34

34

16 47

47

37

32

6

32

6

32

39

16 39

16 32

6

32

6

32

37

16 37

37

16 32

8

16

8

16

6

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

PAGE

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A

B

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345678

D

B

8 7 5 4 2 1

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SPACING

FireWire Interface Constraints

SOURCE: Broadcom 5764-DS04-RDS Page 38

CAESAR IV (Ethernet PHY) Constraints

CAESAR IV (Ethernet) Constraints

PHYSICAL

SPACING

NET_TYPE

PHYSICAL

Port 2 Not Used

ELECTRICAL_CONSTRAINT_SET

FireWire Net Properties

Ethernet Net Properties

I158

I159

I160 I161

I162

I163 I164

I165

I166 I167

I168

I169 I170

I171

I172

SYNC_DATE=05/15/2010

SYNC_MASTER=K91_MLB

Ethernet/FW Constraints

=50_OHM_SE

ENET_50S

=50_OHM_SE

=50_OHM_SE =50_OHM_SE

=STANDARD =STANDARD

*

FW_TP

*

=3:1_SPACING

?

ENET_100D

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

=100_OHM_DIFF

* ?

ENET_CR_DATA

8MIL

ENET_MDI

0.6 MM

* ?

ENET_3X

?*

=3:1_SPACING

FW_110D

=110_OHM_DIFF=110_OHM_DIFF

=110_OHM_DIFF

*

=110_OHM_DIFF

SDCONN_CLK_L

CR_CLK

ENET_50S

ENET_CR_DATA

ENET_3X

BCM5764_CLK25M_XTALI

ENET_50S

ENET_MDI

ENET_100D

ENET_MDI

ENET_MDI_P<3..0>

ENET_CR_DATA

ENET_CR_CLK

CR_CLK

ENET_50S

CR_DATA

SDCONN_CMD

ENET_50S

ENET_CR_DATA

CR_CLK

ENET_50S

ENET_CR_DATA

SDCONN_CLK

ENET_50S

ENET_RESET_L

ENET_3X

NC_FW0_TPAP

FW_110D

FW_TP

FW_P0_TPA

NC_FW0_TPAN

FW_TP

FW_110D

NC_FW0_TPBP

FW_TP

FW_110D

FW_P0_TPB

FW_P1_TPA

FW_TP

FW_110D

FW_PORT1_TPA_P

FW_P1_TPA

FW_TP

FW_110D

FW_PORT1_TPA_N

FW_P1_TPB

FW_TP

FW_110D

FW_PORT1_TPB_P

FW_P1_TPB

FW_TP

FW_110D

FW_PORT1_TPB_N

NC_FW0_TPBN

FW_TP

FW_110D

FW_P0_TPB

ENET_CR_DATA<7..0>

CR_DATA

ENET_50S

ENET_CR_DATA

ENET_CR_CMD

CR_DATA

ENET_50S

ENET_CR_DATA

ENET_3X

ENET_50S

BCM5764_CLK25M_XTALO

ENET_100D

ENET_MDI

ENET_MDI_N<3..0>

SDCONN_DATA<7..0>

ENET_50S

CR_DATA

ENET_CR_DATA

104 OF 109

82 OF 86

33

37 38

33 37

33

33 37

6

39 41

6

39 41

6

39 41

33 37

37 38

33

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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8 7 5 4 2 1

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

T29 IC Net Properties

SOURCE: Bill Cornelius’s T29 Routing Notes

DisplayPort Signal Constraints T29 I2C Signal Constraints

T29/DP Connector Signal Constraints

T29 SPI Signal Constraints

Only used on hosts supporting T29 video-in

Only used on dual-port hosts.

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

T29/DP Net Properties

SPACING

I1

I10 I11

I12

I13

I14

I15

I16

I17

I18

I19

I2

I20

I21

I22 I23

I24

I25 I26

I27

I28

I29

I3

I30

I31

I32

I33

I34

I35 I36

I37

I38

I39

I4

I40

I41 I42

I43

I44

I45

I46

I47 I48

I49

I5

I50 I51

I52

I53 I54

I55

I56 I57

I58

I59

I6

I60

I61

I62

I63

I64 I65

I66

I67 I68

I69

I7

I70

I71 I72

I73

I74

I75

I76

I77 I78

I79

I8

I80

I81

I82

I83 I84

I85

I86

I87

I88 I89

I9

I90

T29_I2C_55S

* =STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

=STANDARD

T29_I2C

*

?

=2x_DIELECTRIC

T29_SPI =2x_DIELECTRIC

*

?

T29_SPI_55S

=55_OHM_SE =55_OHM_SE=55_OHM_SE

* =STANDARD =STANDARD

=55_OHM_SE

T29DP

?

=7x_DIELECTRIC

TOP,BOTTOMT29DP

?

*

=5x_DIELECTRIC

T29DP_80D

*

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

=80_OHM_DIFF =80_OHM_DIFF

=80_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

T29DP_100D

*

SYNC_MASTER=Master

T29 Constraints

SYNC_DATE=06/21/2010

T29DP_100D

T29DP

T29DPA_D2R1_AUXCH_N

T29DP_100D

T29DP

T29DPA_D2R1_AUXCH_P

T29DP_100D

T29DP

T29_D2R1

T29_D2R_C_N<1>

T29DP_100D

T29DP

T29_D2R1

T29_D2R_C_P<1>

T29DP_100D

T29_D2R_C_N<0>

T29_D2R0

T29DP

T29DP_100D

T29_D2R_C_P<0>

T29_D2R0

T29DP

T29DP_80D

DP_SDRVA_ML_ODD

T29DP

DP_SDRVA_ML_N<3..1:2>

T29DP

DP_SDRVA_ML_P<3..1:2>

T29DP_80D

DP_SDRVA_ML_ODD

DP_SDRVA_ML_EVEN

T29DP

DP_SDRVA_ML_N<2..0:2>

T29DP_80D

T29DP

T29DP_80D

DP_SDRVA_ML_P<2..0:2>

DP_SDRVA_ML_EVEN

DP_SDRVA_ML_C_N<3..0>

T29DP_80D

T29DP

DP_SDRVA_ML_R_P<3..0>

T29DP_80D

T29DP

T29DP_80D

T29DP

DP_SDRVA_ML_R_N<3..0>

DP_SDRVA_ML_C_P<3..0>

T29DP_80D

T29DP

T29DP_80D

T29_R2D_C_F_N<1..0>

T29DP

T29DP_80D

T29_R2D_C_F_P<1..0>

T29_R2D1

T29DP

T29DP_80D

T29_R2D_P<1>

T29_R2D1

T29DP

T29DP_80D

T29_R2D_N<1>

T29_R2D0

T29DP

T29DP_80D

T29_R2D_N<0>

T29_R2D0

T29DP

T29DP_80D

T29_R2D_P<0>

T29DP_100D

T29DPB_D2R3_AUXCH_N

T29DP

T29DP_100D

T29DPB_D2R3_AUXCH_P

T29DP

T29DP_100D

T29_D2R_C_N<3>

T29_D2R3

T29DP

T29DP_100D

T29_D2R3

T29DP

T29_D2R_C_P<3>

T29DP_100D

T29_D2R2

T29DP

T29_D2R_C_N<2>

T29DP_100D

T29_D2R_C_P<2>

T29_D2R2

T29DP

T29DP_80D

T29DPA_ML_C_P<3..0>

T29DP

T29DP_80D

T29DPA_ML_C_N<3..0>

T29DP_80D

T29DP

DP_A_EXT_AUXCH_N

DP_SDRVA_AUXCH

DP_SDRVA_AUXCH_P

T29DP

T29DP_80D

T29_R2D_N<3>

T29DP_80D

T29DP

T29_R2D3

T29DP_80D

T29DP

T29DPB_ML_C_N<3..0>

T29DP_80D

T29DP

T29DPB_ML_C_P<3..0>

DP_B_EXT_AUXCH_N

T29DP

T29DP_80D

DP_B_EXT_AUXCH_P

T29DP

T29DP_80D

T29DPA_ML_P<3..0>

T29DP_80D

T29DP

T29DP_80D

T29DP

T29DPA_ML_N<3..0>

T29DPB_ML_N<3..0>

T29DP_80D

T29DP

T29DPB_ML_P<3..0>

T29DP_80D

T29DP

T29DP_80D

T29DP

DP_SDRVB_AUXCH_C_N

T29DP_80D

T29DP

DP_SDRVB_AUXCH

DP_SDRVB_AUXCH_N

T29DP_80D

T29DP

DP_SDRVB_AUXCH_C_P

T29DP_80D

T29DP

DP_SDRVB_AUXCH

DP_SDRVB_AUXCH_P

DP_SDRVB_ML_N<3..1:2>

T29DP_80D

T29DP

DP_SDRVB_ML_ODD

DP_SDRVB_ML_P<3..1:2>

T29DP_80D

T29DP

DP_SDRVB_ML_ODD

DP_SDRVB_ML_P<2..0:2>

T29DP_80D

T29DP

DP_SDRVB_ML_EVEN

DP_SDRVB_ML_N<2..0:2>

T29DP_80D

T29DP

DP_SDRVB_ML_EVEN

T29DP

T29DP_80D

DP_SDRVB_ML_R_N<3..0>

DP_SDRVB_ML_C_N<3..0>

T29DP

T29DP_80D

T29DP

T29DP_80D

DP_SDRVB_ML_R_P<3..0>

DP_SDRVB_ML_C_P<3..0>

T29DP

T29DP_80D

T29_R2D_C_F_P<3..2>

T29DP_80D

T29DP

T29_R2D_C_F_N<3..2>

T29DP_80D

T29DP

T29_R2D_N<2>

T29DP_80D

T29DP

T29_R2D2

T29DP_80D

T29DP

T29_R2D3

T29_R2D_P<3>

T29_R2D_P<2>

T29DP_80D

T29DP

T29_R2D2

T29DP_80D

T29DP

DP_A_EXT_AUXCH_P

DP_SDRVA_AUXCH_C_P

T29DP

T29DP_80D

DP_SDRVA_AUXCH

DP_SDRVA_AUXCH_N

T29DP

T29DP_80D

DP_SDRVA_AUXCH_C_N

T29DP

T29DP_100D

T29DP

T29_D2R_N<3..0>

T29DP_100D

T29DP

T29_D2R_P<3..0>

DP_T29SRC_ML_C_P<3..0>

DP_85D

DISPLAYPORT

T29_SPI_CLK

T29_SPI_CLK T29_SPI_55S

T29_SPI

T29_SPI_MISO

T29_SPI_55S

T29_SPI

T29_R2D_C_P<3..0>

T29DP_80D

T29DP

I2C_T29_SDA

T29_I2C

T29_I2C_55S

I2C_T29_SCL

T29_I2C

T29_I2C_55S

DP_T29SRC_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_T29SRC_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_T29SNK1_AUXCH

DP_T29SNK1_AUXCH_P

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_T29SNK1_ML

DP_T29SNK1_ML_N<3..0>

DP_T29SNK1_ML_P<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK1_ML

DP_T29SNK1_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK1_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH_N

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH

DP_T29SNK0_AUXCH_P

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_T29SNK0_ML

DP_T29SNK0_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK0_ML

DP_T29SNK0_ML_P<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK0_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK0_ML_C_N<3..0>

T29_SPI_MOSI

T29_SPI_55S

T29_SPI

T29_SPI_MOSI

T29_R2D_C_N<3..0>

T29DP_80D

T29DP

T29_SPI_CS_L

T29_SPI_55S

T29_SPI

DP_T29SRC_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH_N

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH_C_N

105 OF 109

83 OF 86

76

75 76

75

75 83

75

75 76

75

75 76

83

75 76

75

8

34 75

8

34 75

34

8

34 75

34 48 75

34

8

17 34

34

8

34

8

34

8

17 34

8

17 34

34

8

34

8

34

8

34 75

34

8

17 34

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

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8 7 5 4 2 1

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SYNC_DATE=05/15/2010

SYNC_MASTER=K91_MLB

SMC Constraints

1TO1_DIFFPAIR

=STANDARD =STANDARD

*

0.1 MM0.1 MM

=STANDARD=STANDARD

SMB_50S

SMBUS_SMC_B_S0_SDA

SMB

SMB_50S

SMB

SMBUS_SMC_0_S0_SCL

SMB_50S

SMB

SMBUS_SMC_0_S0_SDA

SMB_50S

SMBUS_SMC_BSA_SCL

SMB

SMB_50S

SMBUS_SMC_MGMT_SCL

SMB

SMB_50S

SMBUS_SMC_MGMT_SDA

SMB

SMB_50S

SMB

SMBUS_SMC_BSA_SDA

1TO1_DIFFPAIR

CHGR_CSI_N

CHGR_CSI

1TO1_DIFFPAIR

CHGR_CSI_P

CHGR_CSO

1TO1_DIFFPAIR

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO_N

SMB_50S

SMBUS_SMC_B_S0_SCL

SMB

SMB_50S

SMB

SMBUS_SMC_A_S3_SDA

SMB_50S

SMBUS_SMC_A_S3_SCL

SMB

SMBUS_SMC_A_S3_SCL

106 OF 109

84 OF 86

45 48 51

6

32 45 48 51

6

32 45 48 51

6

45 48 63 64

45 48

6

45 48 63 64

64

45 48 51

6

32 45 48 54 55

6

32 45 48 54 55

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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SIZE

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PAGE TITLE

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A

B

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D

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8 7 5 4 2 1

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

ELECTRICAL_CONSTRAINT_SET

(USB_EXTA)

K90i Specific Net Properties

Memory Constraint Relaxations

K90i Specific Net Properties

PHYSICAL

NET_TYPE

SPACING SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

I249

I250

I251

I252

I253

I254

I255

I256

I281

I282

I283

I284

I285

I286

I287

I288

I291

I292

I293 I294

I295

I296

I297

I298

I299

I300

I301

I302

I303

I304

I305

I306

I307

I308

I309

I310

I311 I312

I313 I314

I315

I316

*

THERM_1TO1_55S

=55_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE =55_OHM_SE

DIFFPAIR

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR=1:1_DIFFPAIR

*

MEM_72D 400 MIL0.09 MM

*

0.09 MM 400 MILMEM_37S

*

MEM_85D 0.09 MM 400 MIL

*

10 mm

0.076 MMPCIE_85D

MEM_72D 6.35 MM

0.127 MM

BOTTOM

*

GND_P2MM

GND

ENET_MDI

GND_P2MM

GND

*

CPU_VCCSENSE

*

=1:1_DIFFPAIR

=55_OHM_SE

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE

SENSE_1TO1_55S

=55_OHM_SE

CLK_PCIE_90D

400 MIL

TOP

0.09 MM

400 MIL

TOP

0.09 MM

CPU_27P4S

SB_POWER

*

PWR_P2MM

SATA

GND_P2MMCLK_PCIE

*

GND

GND_P2MM

PCIE

*

GND

GND_P2MM

*

SATA

MEM_85D

0.1 MM

TOP

6.35 MM

CPU_COMP

*

GND

GND_P2MM

ENETCONN

*

?

25 MILS

GND

=STANDARD

?

*

SB_POWER PWR_P2MMCLK_PCIE

GND_P2MM

*

GNDUSB

1000

*

0.20 MM

GND_P2MM

0.20 MM

1000

*

PWR_P2MM

GND

*

GND_P2MM

MEM_CLK

MEM_CTRL

*

GND_P2MM

GND

MEM_DATA

GND

*

GND_P2MM

MEM_DQS

GND

*

GND_P2MM

GND

*

LVDS

GND_P2MM

GND

*

MEM_CMD

USB

SB_POWER

*

PWR_P2MM

*

?

AUDIO

=2:1_SPACING

*

?

THERM

=2:1_SPACING

*

?

SENSE

=2:1_SPACING

TOP

500 MIL

0.1 MM

USB_85D

MEM_40S

*

400 MIL0.09 MM

SYNC_DATE=06/08/2010

SYNC_MASTER=ANNE_K90I

Project Specific Constraints

SENSE_1TO1_55S

SENSE

ISNS_LCDBKLT_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_LCDBKLT_N

ISNS_HDD_R_P

SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS1G_N

SENSE

SENSE_1TO1_55S

CPUIMVP_ISUM_R_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

CPUIMVP_ISUMG_R_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS_N

SENSE_1TO1_55S

SENSE

CPUIMVP_ISUMG_N

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

CPUIMVP_ISUMG_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_CPU_N

ISNS_CPU_P

SENSE_1TO1_55S

SENSE

ISNS_HDD_N

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_HDD_P

SENSE

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

VCCSAS0_CS_P

SENSE

SENSE_1TO1_55S

VCCSAS0_CS_N

ISNS_HDD_R_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_ODD_N

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_ODD_P

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

SENSE

ISNS_ODD_R_P

ISNS_P1V8GPU_N

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE

ISNS_P1V8GPU_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_P1V8GPU_R_N

CPUIMVP_ISUM_R_N

SENSE

SENSE_1TO1_55S

CPUIMVP_ISUMG_R_N

SENSE

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

CPUIMVP_ISNS_P

AUDIO

AUD_DIFF

SPKRAMP_INSUB_P

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

SPKRAMP_INSUB_N

1TO1_DIFFPAIR

AUD_DIFF

AUDIO

SPKRAMP_INR_P

1TO1_DIFFPAIR

SPKRAMP_INR_N

AUD_DIFF

AUDIO

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

SPKRAMP_INL_N

1TO1_DIFFPAIR

AUD_LO2_P_L

AUDIO

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

SPKRAMP_INL_P

1TO1_DIFFPAIR

AUD_LO2_N_L

AUDIO

AUD_DIFF

1TO1_DIFFPAIR

AUD_LO1_P_R

AUDIO

AUD_DIFF

1TO1_DIFFPAIR

AUD_LO1_N_R

AUDIO

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

AUD_LO2_N_R

AUD_DIFF

1TO1_DIFFPAIR

AUD_LO2_P_R

AUDIO

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SSM2315_R_P

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SSM2315_R_N

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SSM2315_L_P

AUD_DIFF

1TO1_DIFFPAIR

SSM2315_L_N

AUDIO

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SSM2315_SUB_P

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SSM2315_SUB_N

AUD_DIFF

1TO1_DIFFPAIR

DIFFPAIR

SPKRAMP_R_N_OUT

AUDIO

SPK_OUT

DIFFPAIR

SPK_OUT

AUDIO

SPKRAMP_R_P_OUT

DIFFPAIR

SPK_OUT

AUDIO

SPKRAMP_SUB_P_OUT

DIFFPAIR

SPK_OUT

AUDIO

SPKRAMP_SUB_N_OUT

DIFFPAIR

SPK_OUT

AUDIO

SPKRAMP_L_N_OUT

USB_TPAD_R_N

USB

USB_85D

USB

USB_85D

USB_TPAD_R_P

LVDS

LVDS_CONN_A_CLK_F_N

LVDS_90D

LVDS

LVDS_CONN_A_CLK_F_P

LVDS_90D

ISNS_ODD_R_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

CPUVCCIOS0_CS_P

CPUIMVP_ISNS1_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

CPUIMVP_ISNS2_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS2_N

SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS1G_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS1_N

SENSE

SENSE_1TO1_55S

SENSE_DIFFPAIR THERM_1TO1_55S

CPU_THERMD_P

THERM

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_HS_OTHER_N

SENSE

ISNS_HS_OTHER_P

SENSE_1TO1_55S

ISNS_P1V8GPU_R_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

CPUVCCIOS0_CS_N

PP3V3_S5

SB_POWER

THERM

THERM_1TO1_55S

CPUTHMSNS_D2_P

SENSE_DIFFPAIR

ENETCONN_N<3..0>

ENETCONN

ENET_100D

ENETCONN_P<3..0>

ENET_100D

ENETCONN

SATA_90D

SATA_ODD_D2R_UF_P

SATA SATA

SATA_90D

SATA_ODD_D2R_UF_N

SATA

SATA_90D

SATA_HDD_R2D_RDRVR_IN_P

SATA

SATA_90D

SATA_HDD_D2R_RDRVR_OUT_P

SATA_90D

SATA

SATA_HDD_R2D_RDRVR_OUT_N

SATA_90D

SATA

SATA_HDD_R2D_RDRVR_OUT_P

PP1V5_S3RS0

SB_POWER

PP3V3_S0

SB_POWER

1TO1_DIFFPAIR

CHGR_CSI_R_N CHGR_CSO_R_P

1TO1_DIFFPAIR

CLK_PCIE_90D

PCIE_CLK100M_AP_CONN_N

CLK_PCIE

THERM_1TO1_55S

THERM

CPUTHMSNS_D2_N

SATA_90D

SATA

SATA_HDD_D2R_RDRVR_IN_N

SATA_90D

SATA

SATA_HDD_D2R_RDRVR_IN_P

THERM

SENSE_DIFFPAIR THERM_1TO1_55S

T29THMSNS_D2_P

T29_THERMD_N

THERM

THERM_1TO1_55S

ISNS_HS_COMPUTING_N

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_HS_COMPUTING_P

SATA

SATA_90D

SATA_HDD_R2D_RDRVR_IN_N

PCIE_CLK100M_AP

PCIE_CLK100M_AP_CONN_P

CLK_PCIE

CLK_PCIE_90D

CHGR_CSI_R_P

1TO1_DIFFPAIR

USB

USB2_EXTA_MUXED_N

USB_85D

USB2_LT1_P

USB

USB_85D

USB

USB2_LT1_N

USB_85D

THERM

THERM_1TO1_55S

CPU_THERMD_N

T29_THERMD_P

THERM

SENSE_DIFFPAIR THERM_1TO1_55S

T29THMSNS_D2_N

THERM

THERM_1TO1_55S

USB_LT2_P

USB

USB_85D

CONN_USB2_BT_N

USB

USB_85D

USB

USB2_EXTA_MUXED_P

USB_85D

CHGR_CSO_R_N

1TO1_DIFFPAIR

SATA

SATA_90D

SATA_HDD_D2R_RDRVR_OUT_N

CONN_USB2_BT_P

USB

USB_85D

USB_LT2_N

USB

USB_85D

DISPLAYPORT

DP_85D

DP_IG_AUX_CH_C_P

DP_85D

DISPLAYPORT

DP_IG_AUX_CH_C_N

DIFFPAIR

SPKRAMP_L_P_OUT

SPK_OUT

AUDIO

GND

108 OF 109

85 OF 86

49 69

49

68 69

65

49

60

57 60

60

57 60

60

6

60 61

6

60 61

6

60 61

6

60 61

6

60 61

53

6

74

6

74

49 70

49 68 69

49 69

9

51

50

49 70

6 7 8

17 19 20 22 23 24 26 30

46 56 66 72 73 74 76

51

38

6

42

6

42

6 7

10 12 15 30 72 73

6 7 8

12 16 17 18 19 20 22 23

26 27 29 33 36 37 40 41 42 46

48 49 50

51 52 54 57 61 62 71 72 73 74

75

77

64

50 64

6

32

51

42

51

50

42

6

32

64

43

9

51

34 51

51

43

50 64

42

43

6

60 61

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

K90i Board-Specific Spacing & Physical Constraints

NOTE: 85_DIFF_BGA is 85-ohms differential impedance on outer layers and 80-ohms on inner layers.

NOTE: These are Intel recommended impedances for PEG, unused on K90i.

NOTE: 90_DIFF_BGA is 90-ohms differential impedance on outer layers and 85-ohms on inner layers.

NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers.

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

27P4_OHM_SE

0.2 MM

=STANDARD =STANDARD

=STANDARD

0.235 MM

Y*

ISL9,ISL10

0.115 MM

Y

0.180 MM0.180 MM

0.115 MM

80_OHM_DIFF

ISL9,ISL10

100_DIFF_BGA

0.075 MM

0.125 MM

Y

0.075 MM

0.125 MM

ISL3,ISL4

90_DIFF_BGA

0.125 MM0.125 MM

0.075 MM0.075 MM

Y

ISL9,ISL10

90_DIFF_BGA

0.125 MM0.125 MM

0.075 MM0.075 MM

Y

100_DIFF_BGA

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

*

ISL3,ISL4

100_DIFF_BGA

0.075 MM

0.125 MM 0.125 MM

Y

0.075 MM

0.140 MM

0.190 MM0.190 MM

0.140 MM

80_OHM_DIFF

TOP,BOTTOM

Y

0.070 MM

ISL9,ISL10

Y

110_OHM_DIFF

0.330 MM0.330 MM

0.070 MM

ISL3,ISL4

100_OHM_DIFF

Y

0.076 MM

0.250 MM0.250 MM

0.076 MM

TOP,BOTTOM

0.200 MM 0.200 MM

0.111 MM

90_OHM_DIFF

Y

0.111 MM

0.090 MM0.090 MM

=STANDARD

*

=STANDARD

Y

=STANDARD

48_OHM_SE

ISL3,ISL4

0.115 MM

0.180 MM0.180 MM

0.115 MM

80_OHM_DIFF

Y

0.085 MM

0.250 MM

Y

TOP,BOTTOM

110_OHM_DIFF

0.250 MM

0.085 MM

ISL3,ISL4

0.330 MM

Y

110_OHM_DIFF

0.330 MM

0.070 MM 0.070 MM

ISL9,ISL10

100_OHM_DIFF

Y

0.076 MM

0.250 MM0.250 MM

0.076 MM

MEM_CLK

*

BGA

BGA_P2MM

CLK_PCIE

*

BGA

BGA_P2MM

*

BGA

*

BGA_P1MM

BGA

CLK_SLOW BGA_P2MM

*

0.490 MM

7X_DIELECTRIC

?*

=STANDARD

80_OHM_DIFF

=STANDARD

N

=STANDARD

*

=STANDARD

48_OHM_SE

0.165 MM

TOP,BOTTOM

0.165 MM

Y

=STANDARD

* N

=STANDARD

110_OHM_DIFF

TOP,BOTTOM

Y

100_OHM_DIFF

0.085 MM

0.200 MM0.200 MM

0.085 MM

=STANDARD

100_OHM_DIFF

=STANDARD

N*

=STANDARD

=STANDARD=STANDARD

N*

40_OHM_SE

?

=DEFAULT

*

BGA_P2MM

?

=DEFAULT

*

STANDARD

=90_OHM_DIFF

*

90_DIFF_BGA

=90_OHM_DIFF=90_OHM_DIFF

0.075 MM

Y

ISL9,ISL10

85_DIFF_BGA

0.075 MM

0.125 MM 0.125 MM

0.075 MM

Y

ISL3,ISL4

85_DIFF_BGA

0.075 MM

0.125 MM 0.125 MM

=STANDARD

Y

1:1_DIFFPAIR

*

=STANDARD

0.1 MM 0.1 MM

=STANDARD

=STANDARD=STANDARD

=STANDARD=STANDARD=STANDARD

N

85_OHM_DIFF

*

0.090 MM0.090 MM

Y

TOP,BOTTOM

55_OHM_SE

=85_OHM_DIFF

*

=85_OHM_DIFF

85_DIFF_BGA

=85_OHM_DIFF =85_OHM_DIFF

TOP,BOTTOM

0.1 MM

0.190 MM 0.190 MM

0.125 MM

Y

85_OHM_DIFF

0.1 MM

0.170 MM 0.170 MM

0.101 MM

Y

ISL9,ISL10

85_OHM_DIFF

0.1 MM

ISL3,ISL4

0.170 MM 0.170 MM

0.101 MM

Y

85_OHM_DIFF

=STANDARD

=STANDARD=STANDARD

0.070 MM0.070 MM

Y*

55_OHM_SE

ISL9,ISL10

Y

0.180 MM 0.180 MM

0.091 MM

90_OHM_DIFF

0.091 MM

ISL3,ISL4

Y

0.180 MM 0.180 MM

0.091 MM

90_OHM_DIFF

0.091 MM

=STANDARD=STANDARD

=STANDARD=STANDARD=STANDARD

N*

90_OHM_DIFF

TOP,BOTTOM

0.200 MM0.200 MM

0.175 MM0.175 MM

Y

72_OHM_DIFF

0.2 MM

0.310 MM

Y

TOP,BOTTOM

27P4_OHM_SE

0.1 MM

0.145 MM

ISL10

=STANDARD=STANDARD

=STANDARD

N

37_OHM_SE

15.5.1

MM

NO_TYPE,BGA

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

0 MM0 MM

10 MM

=50_OHM_SE=50_OHM_SE

Y*

DEFAULT

=DEFAULT

=DEFAULT=DEFAULT

10 MM

=DEFAULT

Y*

STANDARD

0.090 MM

TOP,BOTTOM

0.110 MM

Y

50_OHM_SE

0.080 MM

=STANDARD=STANDARD

=STANDARD

0.080 MM

Y*

50_OHM_SE

40_OHM_SE

0.165 MM0.165 MM

Y

TOP,BOTTOM

40_OHM_SE =STANDARD

0.126 MM

=STANDARD=STANDARD

0.126 MM

N

ISL10

=STANDARD

0.126 MM

=STANDARD=STANDARD

0.126 MM

Y

ISL3,ISL4,ISL9

40_OHM_SE

0.1 MM

0.190 MM

Y

TOP,BOTTOM

37_OHM_SE

Y

0.1 MM

=STANDARD=STANDARD

=STANDARD

0.145 MM

ISL3,ISL4,ISL9

37_OHM_SE

=STANDARD=STANDARD

=STANDARD=STANDARD=STANDARD

N*

37_OHM_SE

72_OHM_DIFF

0.190 MM

N

0.190 MM

0.140 MM

0.140MM

ISL10

72_OHM_DIFF

0.190 MM0.190 MM

0.140 MM0.140 MM

Y

ISL3,ISL4,ISL9

72_OHM_DIFF

=STANDARD =STANDARD

=STANDARD=STANDARD=STANDARD

N*

SYNC_MASTER=ANNE_K90I

SYNC_DATE=06/08/2010

PCB Rule Definitions

?

=DEFAULT

*

BGA_P1MM

DEFAULT

?

0.1 MM

*

2X_DIELECTRIC

?

0.140 MM

0.210 MM

* ?

3X_DIELECTRIC

4X_DIELECTRIC

0.280 MM

* ?

5X_DIELECTRIC

0.350 MM

?*

4:1_SPACING

?

0.4 MM

*

3:1_SPACING

?

0.3 MM

*

2.5:1_SPACING

*

?

0.25 MM

2:1_SPACING

?

0.2 MM

*

1.5:1_SPACING

?

0.15 MM

*

109 OF 109

86 OF 86

Apple K90i Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual