Apple K6 Schematic

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

3456

ECNREV

DESCRIPTION OF REVISION

12

CK
APPD

DATE

2010-03-18

SCHEMATIC,MLB

D

(.csa)

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

10

TABLE_TABLEOFCONTENTS_ITEM

11

TABLE_TABLEOFCONTENTS_ITEM

12

TABLE_TABLEOFCONTENTS_ITEM

13

C

B

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

1

1
2
3
4
5
6
7
8
9

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

BOM Configuration

5

Revision History

7

FUNC TEST

8

Power Aliases

9

SIGNAL ALIAS

10

CPU FSB

11

CPU Power & Ground

12

CPU Decoupling

13

eXtended Debug Port (mini-XDP)

14

MCP CPU Interface

15

MCP Memory Interface

16

MCP PCIe Interfaces

17

MCP Graphics

18

MCP SATA, USB & Ethernet

19

MCP HDA, LPC & MISC

20

MCP Power & Ground

23

MCP89 Memory Rail Gating

24

MCP89 GFX Core Rail Gating

25

MCP Standard Decoupling

26

MCP Graphics Support

28

SB Misc

29

DDR3 SO-DIMM Connector A

31

DDR3 SO-DIMM Connector B

32

DDR3 BYTE/BIT SWAPS-K6

33

FSB/DDR3 Vref Margining

34

RIGHT CLUTCH CONNECTOR

35

SecureDigital Card Reader

39

Ethernet PHY (Caesar II/IV)

40

Ethernet Connector

41

FireWire LLC/PHY (FW643E)

42

FireWire Port & PHY Power

43

FireWire Connector

45

SATA Connectors

46

External USB Connectors

48

Internal USB Support

49

SMC

50

SMC Support

51

LPC+SPI Debug Connector

52

K6 SMBUS CONNECTIONS

53

Voltage Sensing

54

Current Sensing

55

Thermal Sensors

Contents

PVT, 3/18/10

Date

Sync

K17_MLB

K69_MLB

K69_MLB

K24_MLB

K24_MLB

K24_MLB

K24_MLB

K24_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

K18_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

05/20/2009

08/19/2009

08/19/2009

07/20/2009

07/20/2009

07/20/2009

07/22/2009

07/20/2009

08/27/2009

07/20/2009

11/23/2009

07/28/2009

11/05/2009

08/06/2009

11/05/2009

11/05/2009

11/23/2009

11/23/2009

08/06/2009

11/23/2009

11/23/2009

08/15/2009

08/06/2009

07/28/2009

07/28/2009

07/28/2009

06/19/2009

09/29/2009

07/28/2009

09/30/2009

08/20/2009

07/28/2009

07/20/2009

12/15/2009

07/28/2009

08/06/2009

08/27/2009

08/27/2009

09/02/2009

09/02/2009

08/27/2009

08/21/2009

08/27/2009

09/30/2009

08/27/2009

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

47
48
49

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

(.csa)

56

Fan46

57

WELLSPRING 1

58

WELLSPRING 2

59

Sudden Motion Sensor (SMS)

61

SPI ROM50

62

AUDIO: CODEC/REGULATOR

63

AUDIO: LINE INPUT FILTER

65

AUDIO: HEADPHONE FILTER

66

AUDI0: SPEAKER AMP

67

AUDIO: JACK

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

72

5V/3.3V SUPPLY

73

1.5V/1.35V LVDDR3 Supply

74

IMVP6 CPU VCore Regulator

75

MCP VCore Regulator

76

CPU VTT(1.05V) SUPPLY

77

Misc Power Supplies

78

Power Sequencing

79

Power FETs

90

LVDS CONNECTOR

93

DISPLAYPORT SUPPORT

94

DisplayPort Connector

97

LCD Backlight Driver

98

LCD Backlight Support

100

CPU/FSB Constraints

101

Memory Constraints

102

MCP Constraints 1

103

MCP Constraints 2

104

Ethernet Constraints

105

FireWire Constraints

106

SMC Constraints

108

K6/K69 Specific Constraints

109

K6/K69 PCB Rule Definitions

Contents

K24_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

K24_MLB

T27_MLB

K24_MLB

T27_MLB

K24_MLB

T27_MLB

K24_MLB

T27_MLB

T27_MLB

T27_MLB

K24_MLB

K69_MLB

K24_MLB

K69_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

Date

SyncPage

07/20/2009

08/15/2009

08/03/2009

07/20/2009

10/21/2009

08/31/2009

07/17/2009

07/17/2009

07/17/2009

08/25/2009

08/27/2009

07/20/2009

07/29/2009

07/20/2009

08/06/2009

07/20/2009

08/18/2009

07/20/2009

09/30/2009

11/24/2009

08/27/2009

07/20/2009

08/12/2009

07/20/2009

08/27/2009

07/28/2009

08/03/2009

08/03/2009

08/03/2009

08/27/2009

11/23/2009

07/20/2009

07/28/2009

09/08/2009

08/06/2009

D

C

B

A

8 7 6 5 4 2 1

3

DRAWING TITLE

SCHEM,MLB_LDO,K6

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

1 OF 109

SHEET

1 OF 80

SIZE

A

D

U1000

INTEL CPU

2.X OR 3.X GHZ
PENRYN

PG 9

J1300

XDP CONN

PG 12

345678

2 1

FSB

MCP

64-Bit

1067/1333 MHz

PCI

MAIN

MEMORY

DDR3-1067/1333MHZ

PG 14

Misc

PG 18

SPI

PG 18

LPC

PG 18

PWR

CTRL

Bluetooth

11
10

9
8
7
6

USB

PG 17

4
3
2

(UP TO 12 DEVICES)

10 5

SMB

PG 18

HDA

PG 18

2 UDIMMs

PG 29

J2900

DIMM

PG 25,26

U6100

SPI

Boot ROM

PG 51

TRACKPAD/

KEYBOARD

U4900

B,0 BSB

SMC

PG 39

J3401

IR

PG 38PG 47 PG30 PG38

CAMERA

J1300

D

PG 10

MAC

PG 17

FSB INTERFACE

NVIDIA

U1400

GPIOs

PG 18

CLK

SYNTH

J4501

SATA
Conn

PG 38

HD

J4500

SATA
Conn

PG 38

C

ODD

J9000

1.05V/3GHZ.

1.05V/3GHZ.

PG 15,18

SATA

PG 17

LVDS
CONN

PG 68

J9400

DISPLAY PORT

CONN

PG 70

J3401

AIR PORT

B

PG 29

LVDS OUT

RGB OUT

DP OUT

HDMI OUT

DVI OUT

TMDS OUT

PG 16

UP TO 20 LANES3

PCI-E

PG 15

J6950,U7000

U5535,U5515

CPU,MCP,TEMP SENSOR

POWER SENSE

J5601

FAN CONN AND CONTROL

Ser

FanADC

Prt

J4600, J4610

EXTERNAL

USB

Connectors

PG 37PG 29

SMB

CONN

PG 12

DC/BATT

PG 58,59

PG 45

PG 50

PG 46

J5100

LPC+SPI Conn

PG 46

J3500U5701J3401 J4890

Card reader

D

POWER SUPPLY

C

J4890

Blue Ray dec

B

U6201

U3900

BMC5764M

J4000

GB

E-NET

PG 31

E-NET

Conn

PG 32

A

J3401

PCI-E

AirPort

PG 29

Line In

Filter

PG 53

HEADPHONE

Filter

PG 54

J6750,6700

8 7 5 4 2 1

Audio
Codec

PG 52

U6880

Audio
Conns

PG 56

Mic
Amp

U6633, U6623, U6613

Speaker

Amps

PG 55PG 53

SIZE

A

D

SYNC_MASTER=K69_MLB

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/19/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

2 OF 109

SHEET

2 OF 80

36

345678

2 1

D

(9 TO 12.6V)

C

B

A

AC

ADAPTER

IN

3S2P

MCP89

PM_SLP_S4_L

PM_SLP_S3_L

DELAY

DELAY

DELAY

DELAY

PP18V5_DCIN_CONN

POWER SYSTEM ARCHITECTURE

Q7080

PPDCIN_G3H_OR_PBUS

J6950

DCIN(16.5V)

PPVBAT_G3H_CONN

F6905

6A FUSE

SMC_DCIN_ISENSE

01

A

R7020

Q7055

CHGR_EN
(S5)

ENABLES

VIN

PBUS SUPPLY/
BATTERY CHARGER

ISL6259

U7000

PPVBAT_G3H_CHGR_R

VOUT

Q7085

PPVBAT_G3H_CHGR_REG

R7050

SMC_BATT_ISENSE

A

01

IMVP_VR_ON_R

8A FUSE

F7040

02

25

CPU VCORE

VIN

ISL9504B

VR_ON

PBUS_VSENSE

PPBUS_G3H

VOUT

PGOOD

U7100

U1400

AP_PWR_EN

11

15

Q7890

11-1

11-3

RC
DELAY

11-2

RC
DELAY

PM_WLAN_EN_L

P3V3S3_EN

DDRREG_EN

P5VS3_EN_L

16

CHGR_BGATE

SMC

P16

U4900

P60

BKLT_EN

PPBUS_G3H

04

SMC_PM_G2_EN

(S5)

02

VIN

LP8545

U9701

ENA

U7840

PPVOUT_SW_LCDBKLT

VOUT

P5VS3_EN_L

05

P3V3S5_EN_L

02

VIN

EN1

(RT)

EN2

TPS51125

U7201

PGOOD1,2

P5V3V3_PGOOD

EN

ISL8009B

U7750

5V

3.3V

VIN

VOUT1

VOUT2

VREG3

VOUT

Q7890,Q7891

PM_SLP_S3_L

RC

RC

RC

RC

PM_SLP_S3_L

P1V8S0_EN

P1V5S0_EN

CPUVTTS0_EN

DDRVTT_EN

MCPCORES0_EN

16-3

16-4

16-6

16-5

SMC_ADAPTER_EN

PBUSVSENSE_EN

(S0)

P5VS0_EN

(S0)

RC

P3V3S0_EN

DELAY

16-1

16-1

16-2

04-1

=DDRREG_EN

=DDTVTT_EN

02

VIN

1.5V

S5
S3

0.75V

TPS51116

U7300

MCPCORES0_EN

VOUT1

VOUT2

02

14

Q7930

MCPDDROUT

MCP_CORE

EN

VIN

ISL9563A

U7500

PP1V5R1V35_SW_MCP

(12A MAX CURRENT)

(1A MAX CURRENT)

PPMCPCORE_S0_R

VOUT

(25A MAX CURRENT)

PP1V5_S3_REG

PP0V75_S0_REG

8 7 5 4 2 1

02

Q5315

V

PBUS_G3H_VSENSE

CPUVTTS0_EN
(S0)

V

SMC_CPU_ISENSE

VR_PWRGOOD_DELAY

PP5V_S3_REG

(13A MAX CURRENT)

PP3V3_S5_REG

(5.5A MAX

PP0V9_S5_REG

21

20

CURRENT)

P3V3S3_EN

P3V3S0_EN

R7525

ENABLE

3.425V G3HOT
LT3470

VOUT

U6990

02

VIN

EN_PSV

VOUT

CPUVTT

(1.05V)

TPS51117

U7600

PGOOD

CPUVTTS0_PGOOD

SMC_CPU_VSENSE

PPVCORE_S0_CPU

(44A MAX CURRENT)

28

Q7910

Q7930

ST1S12G12R

PPMCPCORE_S0_REG

PP3V42_G3H_REG

PP1V05_S0

(8A MAX CURRENT)

1.2V

U7720

1.8V

TPS62202

U7760

1.5V

ISL8009B

U7710

PP1V8_S0_REG

PP1V5_S0_REG

1.05V

TPS7470

U7740

PP1V2_ENET_REG

03

26

Q3450

P3V3ENET_EN_L

PP3V3_S0_FET

PP1V05_S0_MCP_PLL_REG

PP3V3_S0
PP1V5_S0
PP1V05_S0

SMC PWRGD

RN5VD30A-F

U5010

4.5V AUDIO
MAX8840

VIN

U6200

EN

PP3V3_S3_FET

P3V3_S3_WLAN

18

MCPPLLDO_PGOOD

S0PGOOD_RST_L

V1
V2
V3

36

04

PP4V5_AUDIO_ANALOG

VOUT

P1V5S0_PGOOD

P5V3V3_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

RST*

ISL88042

U7870

MCP_PS_PWRGD

U2850

17

07

13

24

ALL_SYS_PWRGD

RSMRST_PWRGD

09

SMC_ONOFF_L

05

MCP89

PWRBTN*

PLTRST*

RSMRST*

PWRGD

29

CPUPWRGD(GPIO49)

CPU_RESET#

U1400

CPU

PWRGOOD

U1000

Q7940

PP5V_S0_FET

P5VS0_EN

SMC

RSMRST_OUT(P15)

SLP_S5_L
SLP_S4_L
SLP_S3_L

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)
SLP_S4_L(P94)
SLP_S3_L(P93)

99ms DLY

IMVP_VR_ON(P16)

PLT_RST*

P17(BTN_OUT)

U4900

SYNC_MASTER=K69_MLB

PAGE TITLE

Power Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

RESET*

RST*

06-1

31

LPC_RESET_L

CPU_PWRGD

30

FSB_CPURST_L

32

PM_RSMRST_L

IMVP_VR_ON_R

PM_PWRBTN_L
SMC_RESET_L

10

25

SYNC_DATE=08/19/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

3 OF 109

SHEET

3 OF 80

SIZE

D

C

B

A

D

345678

2 1

D

C

BOM Variants

BOM NUMBER

639-1120
639-1119
085-1634

BOM NAME

PCBA,MLB_LDO,BETTER,K6

PCBA,MLB_LDO,BEST,K6

K6 MLB_LDO DEVELOPMENT BOM

BOM Groups

BOM GROUP

K6_COMMON

K6_MISC
K6_PROGPARTS
K6_DEVEL:ENG
K6_DEVEL:PVT
K6_DEBUG:ENG
K6_DEBUG:PVT

K6_DEBUG:PROD

COMMON,ALTERNATE,K6_MISC,K6_DEBUG:PROD,KB_BL,K6_PROGPARTS,RDRV:NO,SPI:25MHZ,CPU_CAP:15

DP_ESD,MIKEY,BCM5764M,GL137,ENET_ESD,VFRQ:SLPS3,LVDDR3:YES,MCPPLL_R:REG,S0PGOOD_BJT,BOOST_VOL:LOW,HDA:1.5V

BOOTROM:UNLOCKED,SMC:PROG,IR:PROG,WELLSPRING:PROG

BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,RDRV:IN_DEVEL

LPCPLUS,XDP_CONN

DEVEL_BOM,SMC_DEBUG:YES,XDP

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO

BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO,LPCPLUS,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES

Module Parts

PART NUMBER

337S3769
337S3680
337S3756
337S3761
337S3797 CRITICAL
337S3866

QTY

1
1
1
1
1
1

1
1

338S0753
353S2896

1
1

DESCRIPTION

PDC,SLGVT,PRQ,2.26,25W,1066,R0,3M,BGA,P7550

PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA

PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA

PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA

IC,MCP89M-A01,31X31MM,BGA1168

IC,MCP89M-A01,31X31MM,BGA1168

IC,1MBIT,SPI FLASH,K17/18

IC,ASIC,BCM5764M,ENET CONTROLLER, 8x8, 64QFN

IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12

IC,LP8545,LED BKLT CTRLR,LLP24

REFERENCE DES

U1000
U1000
U1000
U1000
U1400
U1400
U3990
U3900
U4100
U9701

Programmable Parts

1

338S0563
341T0240
335S0610 CRITICAL
341T0238
341S2589
338S0633
341S2384
337S2983
341S2616

IC,SMC,HS8/2117,9X9MM,TLP,HF

1

1

1

1

1

IC,CYPRS,CY7C63803-LQXC,4X4MM,USB,24-QFN

1

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

1

1

SMC EXTERNAL,K6

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

EFI UNLOCKED,K6/K69

IC,EFI,LOCKED,K6

IC,ENCORE II,CY7C63803-LQXC

IC,TP PSOC,K17,K18

U4900
U4900
U6100
U6100
U6100
U4800
U4800
U5701
U5701

BOM OPTIONS

K6_COMMON,CPU:2.4GHZ,MCP89M:A02,EEEE:DD24

K6_COMMON,CPU:2.66GHZ,MCP89M:A02,EEEE:DD23

K6_DEVEL:PVT

BOM OPTIONS

CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL

CRITICAL

CRITICAL343S0493 BCM5764M
CRITICAL
CRITICAL

CRITICAL
CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

BOM OPTION

CPU:2.26GHZ

CPU:2.4GHZ
CPU:2.53GHZ
CPU:2.66GHZ

MCP89M:A01

MCP89M:A02

BCM5764MCRITICAL341S2731

SMC:BLANK

SMC:PROG

BOOTROM:BLANK

BOOTROM:UNLOCKED

BOOTROM:LOCKED

IR:BLANK

IR:PROG

WELLSPRING:BLANK

WELLSPRING:PROG

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Bar Code Labels / EEE #’s

PART NUMBER

826-4393
826-4393

QTY

1
1

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM

REFERENCE DES

[EEEE_DD23]
[EEEE_DD24]

CRITICAL

CRITICAL
CRITICAL

BOM OPTION

EEEE:DD23
EEEE:DD24

Top

2
3
4

5
6
7
8
9

10
11

BOTTOM

K6 BOARD STACK-UP

SIGNAL
GROUND

SIGNAL(High Speed)

SIGNAL(High Speed)
GROUND
POWER
POWER

GROUND

SIGNAL(High Speed)

SIGNAL(High Speed)
GROUND
SIGNAL

D

C

B

PART NUMBER

152S0874 152S0516

152S1025

337S3769

152S1135

516-0213

516S0790

ALTERNATE FOR
PART NUMBER

152S0778152S0693

152S0685152S0796

157S0055157S0058

104S0023104S0018

128S0218128S0093

152S0586152S0847

152S1024

337S3704

152S0586

516-0201

516S0706

376S0360376S0699

BOM OPTION

REF DES

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

COMMENTS:

CYNTEC AS ALTERNATE

CYNTEC AS ALTERNATE

DELTA AS ALTERNATE

DALE/VISHAY AS ALTERNATE

KEMET AS ALTERNATE

MAGLAYERS AS ALTERNATE

MAGLAYERS AS ALTERNATE

TOKO AS ALTERNATE

INTEL P7550 CPU AS ALTERNATE

TOKO AS ALTERNATE

MOLEX AS ALTERNATE

MOLEX AS ALTERNATE

SSM6P15FE AS ALTERNATE

A

Schematic / PCB #’s

PART NUMBER

051-8563

820-2879

DRAWING

LAST_MODIFIED=Thu Mar 18 17:53:39 2010

TITLE=MLB
ABBREV=DRAWING

QTY

1

DESCRIPTION

SCHEM,MLB_LDO,K6

PCBF,MLB_LDO,K6

8 7 5 4 2 1

TABLE_ALT_HEAD

DEVELOPMENT BOM

TABLE_ALT_ITEM

PART NUMBER

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

085-1634

REFERENCE DES

SCH1

PCB

QTY

1

CRITICAL

CRITICAL

CRITICAL

DESCRIPTION

K6 MLB_LDO DEVELOPMENT BOM

BOM OPTION

REFERENCE DES

DEVEL

CRITICAL

CRITICAL

BOM OPTION

DEVEL_BOM

SYNC_MASTER=K24_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM Configuration

Apple Inc.

R

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

4 OF 109

SHEET

4 OF 80

36

Alternate Parts

SIZE

B

A

D

Revision History

345678

2 1

D

C

D

C

B

A

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

8 7 5 4 2 1

B

SIZE

A

D

SYNC_MASTER=K24_MLB

PAGE TITLE

Revision History

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

5 OF 109

SHEET

5 OF 80

36

Functional Test Points

345678

2 1

Fan Connectors

I12

D

I15

I16

TRUE
TRUE
TRUE

MIC FUNC_TEST

TRUE

I238

TRUE

I237

TRUE

I239

SPEAKER FUNC_TEST

I227

I226

I228

I230

I229

I231

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

LVDS FUNC_TEST

I259

I258

C

I260

I245

I407

I262

I261

I256

I257

I255

I252

I253

I254

I250

I251

I313

I246

I247

I248

I249

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

SATA ODD CONN

I264

I268

B

I269

I267

I265

I266

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

SATA HDD/IR/SIL

I319

I314

I315

I318

I317

I307

I309

I311

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP5V_S0
FAN_RT_PWM
FAN_RT_TACH

(NEED TO ADD 3 GND TP)

BI_MIC_LO
BI_MIC_HI
BI_MIC_SHIELD

SPKRAMP_L_N_OUT
SPKRAMP_L_P_OUT
SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_SUB_P_OUT

PP3V3_LCDVDD_SW_F
PP3V3_S0_LCD_F
PPVOUT_SW_LCDBKLT
BKL_VSYNC
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
LVDS_CONN_A_CLK_F_N

LVDS_CONN_A_CLK_F_P
LED_RETURN_1
BKL_ISEN2
BKL_ISEN3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6

(NEED TO ADD 5 GND TP)

PP5V_SW_ODD

SMC_ODD_DETECT

SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N

(NEED TO ADD 4 GND TP)

PP5V_S0_HDD_FLT
SATA_HDD_R2D_P

SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SYS_LED_ANODE_R

IR_RX_OUT
PP5V_S3_IR_R

(NEED TO ADD 5 GND TP)

(NEED 2 TP)

(NEED 4 TP)

6 7

65

46

46

55 56

55 56

55 56

54 55

54 55

54 55

54 55

54 55

54 55

6

67

6

67

67 70

67 70

8

67

8

67

8

67 74

8

67 74

8

67 74

8

67 74

8

67 74

8

67 74

67 79

67 79

67 70

70

70

67 70

67 70

67 70

6 8

36 39

36 79

36 79

36 74

36 74

(NEED 3 TP)

6

36

36 74

36 74

36 74

36 74

36

36 38

36

I303

I301

I302

I300

I299

I298

I293

I297

I294

I288

I292

I296

I291

I295

I290

I271

I289

I375

I374

I372

I370

I371

I369

I368

I361

I366

I365

I363

I364

I362

I360

I359

I357

I358

I377

I378

I354

I355

I344

I345

I346

I347

I349

I348

I350

I352

I351

I353

I327

I328

I329

I343

I342

I341

I339

I340

I338

I336

I337

I333

I335

I334

I332

I330

I331

RIGHT CLUTCH CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

IPD_FLEX_CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

KEYBOARD CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP5V_S3_BTCAMERA_F
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
PP5V_WLAN
PCIE_WAKE_L
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
USB_BT_CONN_P
USB_BT_CONN_N
AP_CLKREQ_Q_L
AP_RESET_CONN_L

(NEED TO ADD 6 GND TP)

PP3V3_S3
PP18V5_S3
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
PSOC_F_CS_L
PICKB_L

(NEED TO ADD 2 GND TP)

PP3V3_S3
PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD

(NEED TO ADD 2 GND TP)

29

15 29 74

15 29 74

29 74

29 74

29 79

29 79

29 79

29 79

6

29

15 24 29

6

42 78

6

42 78

29 79

29 79

29

29

6 7

48

6

47 48

47 48

47 48

47 48

47 48

48

47 48

47 48

47 48

47 48

47 48

47 48

47 48

6

42 78

6

42 78

47 48

47 48

6 7

6 7

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

(NEED 2 TP)

I287

I285

I414

I280

I281

I282

I283

I376

I278

I270

I416

I273

I274

I275

I417

I392

I391

I390

I388

I418

I386

I383

I419

I382

I381

I380

I421

I422
I423

I424
I425

I426

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

DC POWER CONN

I312

I304

TRUE
TRUE

FSB SIGNALS WITH NOTEST

I396

I399
I398

I397

I403
I402

I400

I401
I404

I406

I405

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

DEBUG VOLTAGE

PPVCORE_S0_CPU
PPVCORE_S0_MCP
PP1V2_ENET
PP1V05_S0

PP1V5_S0
PP1V8_S0
PP3V3_S0
PP5V_S0
PP3V3_S3

PP5V_S3

PP0V9_S5
PP3V3_S5
PP3V42_G3H

PPBUS_G3H

PP3V3_ENET

PP5V_WLAN
PP5V_SW_ODD

PP5V_S0_HDD_FLT

PP18V5_S3

PP3V3_S0_LCD_F
PP3V3_LCDVDD_SW_F

PP4V5_AUDIO_ANALOG

PP1V5R1V35_S3

SMC_PM_G2_EN

PM_SLP_S4_L

PM_SLP_S3_L

(NEED TO ADD 6 GND TP)

SPI DEBUG CONN

PP3V42_G3H

SPI_CS0_L
SPI_CLK

SPI_MOSI
SPI_MISO

SPIROM_USE_MLB

PP18V5_DCIN_FUSE
ADAPTER_SENSE

(NEED TO ADD 4 GND TP)

FSB_A_L<35..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>
FSB_D_L<63..0>
FSB_DINV_L<3..0>
FSB_DSTB_L_N<3..0>
FSB_DSTB_L_P<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>

(NEED 3 TP)

7

43

7

43

7

7

65

7

65 79

7

7

65 79

6 7

65

6 7

6 7

7

7

65 79

6 7

7

43

7

6

29

6 8

6

36

6

48

6

67

6

67

51

7

79

39 65

18 39 40 65

18 39 65 69

6 7

41 75

41 75

41 75

18 41 75

18 41 50

57

57

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

D

C

B

BATT POWER CONN

I322

I321

I320

A

I305

TRUE
TRUE
TRUE
TRUE

SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SYS_DETECT_L
PPVBAT_G3H_CONN

(NEED 3 TP)
(NEED TO ADD 4 GND TP)

6

6

57

57 58

42 78

42 78

I356

I394

BIL CONN

I326

I323

I324

I325

I308

TRUE
TRUE
TRUE
TRUE
TRUE

PP3V42_G3H
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMC_BIL_BUTTON_L
SMC_LID_R

(NEED TO ADD 4 GND TP)

6 7

6

42 78

6

42 78

39 40 57

57

I408

I409

I410
I411

I413
I412

8 7 5 4 2 1

KBD BACKLIGHT CONN

TRUE

TRUE

KBDLED_ANODE

SMC_KDBLED_PRESENT_L

T57 CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP5V_S3
PP3V3_S3
T57_PWR_EN
T57_RESET
USB_T57_N
USB_T57_P

(NEED TO ADD 1 GND TP)

(NEED TO ADD 5 GND TP)

48

48

6 7

6 7

18

18

38 75

38 75

SIZE

A

D

SYNC_MASTER=K24_MLB

PAGE TITLE

FUNC TEST

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

7 OF 109

SHEET

6 OF 80

36

345678

2 1

"S0,S0M" RAILS

=PPVCORE_S0_CPU_REG

(CPU VCORE PWR)

=PPCPUVTT_S0_REG

63

D

=PPMCPCORE_S0_REG

62

(MCP VCORE AFTER SENSE RES)

LVDDR VRef/VTT (0.75V/0.675V) Rails

=PPVTT_S0_DDR_LDO

60

C

=PPVTT_S3_DDR_BUF

28 60

=PP1V5_S0_REG

64

=PP1V8_S0_REG

64

B

=PP1V05_S0_MCP_PLL_OR

64

UNUSED MCP PE0[3:0] AVDD/DVDD

=PP1V05_S0_MCP_PE_DVDD0

19

=PP1V05_S0_MCP_PE_AVDD0

19

(SINCE PE0[3:0] IS NOT USED ON K6)

(CONNECTS TO MCP BALLS)

(CONNECTS TO MCP BALLS)

=PP1V05_S0_MCP_PE_DVDD1

19

=PP1V05_S0_MCP_PE_AVDD1

19

A

8 7 5 4 2 1

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PPVCORE_S0_CPU

PP1V05_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_CPU
=PP1V05_S0_MCP_FSB
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_PLL_UF_R
=PP1V05_FW_P1V0FWFET
=PP1V05_S0_FWPWRCTL

=PP1V05_SW_MCP_FSB
=PP1V05_S0_MCP_PE_DVDD
=PP1V05_S0_MCP_M2CLK_DLL
=PP1V05_S0_MCP_PLL_IFP
=PP1V05_S0_MCP_DP0_VDD

PPVCORE_S0_MCP

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PPVCORE_S0_MCP
=PPVCORE_S0_MCPGFXFET

PPDDRVTT_S0

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

=PPDDRVTT_S0_MEM_A
=PPDDRVTT_S0_MEM_B

PPDDRVREF_S3

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0_CPU
=PP1V5_S0_SATARDRVR
=PP1V5_S0_MCP_PLL_VLDO

=PP1V8R1V5_S0_AUDIO

=PP1V5_S0_MCP_HDA_R
=PP1V5_S0_AUDIO_R

PP1V8_S0

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP3V3R1V8_S0_MCP_IFP_VDD
=PP1V8_S0_AUDIO

PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_PE_DVDD

PP1V05_S0_MCP_PE_AVDD

MAKE_BASE=TRUE

6

43 61

10 11

6

65

9

10 11 12 61

13 19 22

22

19 22

64

34

34

19 22

7

22

14 22

16 23

16 23

6

43

19 22

21

25

26

6

65 79

10 11

36

51

8

8

6

16 23

22

(CONNECTS TO THE DECAPS)

7
22

(CONNECTS TO THE DECAPS)

22

=PP5V_S0_FET

66

=PP3V3_S0_FET

=PP3V3_ENET_FET_R

8

400mA

(BCM5764M)

=PP1V2_ENET_REG

64

700 mA max output

=PP1V2_ENET_PHY_REG

64

(BCM57765)

=PP0V9_ENET_FET

66

PP5V_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_HDD
=PP5V_S0_LPCPLUS
=PP5V_S0_FAN_RT

=PP5V_S0_CPU_IMVP

=PP5V_S0_KBDLED
=PP5VR3V3_S0_DPCADET
=PP5V_S0_CPUVTTS0
=PP5V_S0_BKL
=PP5V_S0_MCPREG
=PP5V_S0_MCPFSBFET

PP3V3_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S0_XDP
=PP3V3_S0_MCP
=PP3V3_S0_P1V5S0
=PP3V3_S0_DEBUGROM
=PP3V3_S0_ODD
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_MCP_0
=PP3V3_S0_FAN_RT
=PP3V3_S0_AUDIO

=PP3V3_S0_IMVP

=PP3V3_S0_LCD
=PP3V3_S0_MCP_GPIO

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP_HVDD
=PP3V3_S0_SMC
=PP3V3_S0_MCPTHMSNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_DPCONN
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_PWRCTL
=PP3V3_S0_ENETPHY
=PP3V3_S0_CPUVTTISNS
=PP3V3_S0_TPAD
=PP3V3_S0_SMBUS_MCP_1
=PP3V3_S0_P1V8S0
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_MCPDDRISNS
=PP3V3_S0_MCP_PLL_VLDO
=PP3V3_S0_FWPWRCTL
=PP3V3_S0_FWLATEVG
=PP3V3_S0_SDCONN
=PP3V3_S0_MCPCOREISNS

=PP3V3_S0_MCP_HDA_R
=PP3V3_S0_AUDIO_R

=PP3V3_S0_OPA333

"ENET" RAILS

PP3V3_ENET

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

300mA

~100mA

~400mA

=PP3V3_ENET_MCP_RMGT
=PP3V3_ENET_MCP_PLL_MAC
=PP3V3_ENET_PHY
=PP3V3_ENET_PWRCTL

PP1V2_ENET

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PP1V2_ENET_PHY

PP0V9_ENET

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PP0V9_ENET_MCP_RMGT

6

17 19 22

22

24 31 64

65

6

31

19 22

6

65

36

41

46

61

48

69

63

70

62

21

6

65 79 66

12

19 22

64

41

36

42

42

42

46

51 55 56

61

67

16 17 18

22

19 22

40

45

45

69

25

26

65

31

44

48

42

64

70

44

34

34 35

30

44

8

8

22

60

59

=PP3V3_S5_REG

59

64

=PPDDR_S3_REG

66

=PP3V3_S3_FET

=PP5V_S3_REG

=PP0V9_S5_REG

LVDDR (1.5V/1.35V) Rails

PP1V5R1V35_S3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PPLVDDR_S3_MEM_A
=PPLVDDR_S3_MEM_B

0 mA

4250 mA

=PP1V5R1V35_S3_MCP_MEM
=PP1V5R1V35_S0_MCPDDRFET
=PPVIN_S0_DDRREG_LDO

PP3V3_S3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_PDCISENS

=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_TPAD
=PP3V3_S3_SMS
=PP3V3_S3_CARDREADER
=PP3V3_S3_T57
=PP3V3_ENET_P1V2ENET

PP5V_S3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S3_RTUSB
=PP5V_S3_IR
=PP5V_S3_MCPDDRFET
=PP5V_S3_SYSLED
=PP5V_S3_TPAD

=PP5V_S3_WLAN

=PP5V_S3_DDRREG
=PP5V_S3_AUDIO
=PP5V_S3_AUDIO_AMP
=PP5V_S3_P5VS0FET
=PP5V_S0_ODD

=PP5V_S3_BTCAMERA
=PP5V_S3_T57

"S5" RAILS

PP3V3_S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S5_MCP_GPIO
=PP3V3_S5_ROM
=PP3V3_S5_LCD
=PP3V3_S5_MCP
=PP3V3_S5_MCPPWRGD
=PP3V3_S5_P3V3S3FET
=PP3V3_S5_P3V3S0FET
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_DP_PORT_PWR
=PP3V3_S5_P0V9S5
=PP3V3_FW_P3V3FWFET
=PP3V3_S5_P0V9ENETFET

=PP3V3_S5_VMON
=PP3V3_S5_SMBUS_SMC_MGMT

0.9V Rails

105 mA/241 mA
139 mA/ 0 mA

PP0V9_S5

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PP0V9_S5_MCP_VDD_AUXC
=PP0V9_ENET_P0V9ENETFET

(OR 1.35V)

36

6

19 22

66

6

17 18

50

67

19 22

24

66

66

66

69

64

34

66

65

42

29

38

65 79

6

42

60

28

29

18

47 48

49

30

38

64

6

37

36 38

20

40

48

29

60

51 53 55

54

66

36

=PP3V42_G3H_REG

57

6

79

25

26

14

20

60

=PP18V5_DCIN_CONN

57

=PPBUS_G3H

58

=PPBUS_S5_CPUREGS_ISNS

44

(AFTER HIGH SIDE CPU VCORE

& CPU VTT SENSING RES.)

=PP3V3_FW_FET

34

=PPBUS_FW_FET

34

=PP1V0_FW_FET_R

34

SYNC_MASTER=K24_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

"S3" RAILS

"G3H" RAILS

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE

=PPVIN_S5_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_CHGR
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PP3V42_G3H_BATT

=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PP3V42_G3H_BMON_ISNS
=PP3V42_G3H_ONEWIRE

I1086

PP3V3_G3_RTC
=PP3V42_G3H_OPA330

PPDCIN_S5_S5

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPBUS_S0_LCDBKLT
=PPVIN_S0_MCPCORE
=PPVIN_S3_DDRREG
=PPVIN_S5_3V3S5
=PPVIN_S3_5VS3
=PPBUS_S5_FWPWRSW

=PPBUS_S5_CPUREGS_ISNS_R

(BEFORE HIGH SIDE SENSING RES.)

PPBUS_S5_IMVP_VTT_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVIN_S0_CPUVTTS0
=PPVIN_S5_CPU_IMVP

"FIREWIRE" RAILS

PP3V3_FW

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_FW_FWPHY

PPVP_FW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET

PP1V05_FW

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V0_FW_FWPHY

Power Aliases

Apple Inc.

R

39 40

41

44

57

18 19 22

22

33 34 35

35

35

33 34

SYNC_DATE=07/22/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

8 OF 109

SHEET

7 OF 80

6

40

42

65

58 65

37

47

57

58

6

71

62

60

59

59

34

44

63

61

D

43

C

B

A

SIZE

D

345678

PCI-E ALIASES

=PEG_D2R_N<3:0>

66

121

5%

2

15

=PEG_D2R_P<3:0>

15

=PEG_R2D_C_N<3:0>

15

=PEG_R2D_C_P<3:0>

15

PEG_CLK100M_P

15 74

PEG_CLK100M_N

15 74

PEG_CLKREQ_L

15

USB_EXTC_P

17 75

USB_EXTC_N

17 75

USB_EXTD_P

17 75

USB_EXTD_N

17 75

USB_WM_P

17 75

USB_WM_N

17 75

USB_MINI_P

17 75

USB_MINI_N

17 75

PP3V3_ENET_FET

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_ENET_FET

ENET_RXD_PD

MAKE_BASE=TRUE

ENET_RXCLK_PD

MAKE_BASE=TRUE

R0981

10K

5%
1/16W
MF-LF
402

10K

5%
1/16W
MF-LF

402

2

HEATSINK STANDOFFS

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902

1

STDOFF-4.5OD.98H-1.1-3.48-TH

LEFT OF CPU

D

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0903

1

STDOFF-4.5OD.98H-1.1-3.48-TH

BELOW MCP

Z0901

1

ABOVE CPU

Z0904

1

BELOW CPU

FAN STANDOFF

STDOFF-4.5OD.98H-1.1-3.48-TH

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

Z0905

1

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

OMITOMIT

Z0906

3R2P5

Z0907

3R2P5

11

C

MLB MOUNTING (TO TOPCASE) SCREW HOLES

OMIT

Z0908

3R2P5

1

OMIT

Z0911

3R2P5

1

OMIT

Z0909

3R2P5

1

OMIT

Z0912

3R2P5

1

OMIT

Z0910

3R2P5

1

R0980

1/16W
MF-LF

10K

402

UNUSED GPU LANES

USB ALIASES

UNUSED USB PORTS

ETHERNET ALIASES

PLACE_NEAR=U7980.A1:5MM

R0984

121

R0983R0982

10K

5%
1/16W
MF-LF
402

1/16W
MF-LF

10K

R0911

0

1 2

5%
1/16W
MF-LF

402

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>

ENET_CLK125M_RXCLK

ENET_RX_CTRL

ENET_MDIO

MCP_RGMII_VREF
ENET_LOW_PWR

NO STUFF

1

R0986

10K

5%

5%

1/16W

MF-LF

402

402

2

NC_PEG_D2R_N<3:0>

NO_TEST=TRUE

NC_PEG_D2R_P<3:0>

NO_TEST=TRUE

NC_PEG_R2D_C_N<3:0>

NO_TEST=TRUE

NC_PEG_R2D_C_P<3:0>

NO_TEST=TRUE

TP_PEG_CLK100M_P
TP_PEG_CLK100M_N
TP_PEG_CLKREQ_L

TP_USB_EXTCP
TP_USB_EXTCN
TP_USB_EXTDP
TP_USB_EXTDN
TP_USB_WMP
TP_USB_WMN

TP_USB_MINIP
TP_USB_MININ

=PP3V3_ENET_FET_R

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MCP_TV_DAC_RSET

74

MCP_TV_DAC_VREF

74

MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT
CRT_IG_R_C_PR

74

CRT_IG_G_Y_Y

74

CRT_IG_B_COMP_PB

74

CRT_IG_HSYNC

74

CRT_IG_VSYNC

74

=MCP_IFPA_TXC_P

16

=MCP_IFPA_TXC_N

16

=MCP_IFPA_TXD_P<0..2>

16

=MCP_IFPA_TXD_N<0..2>

16

=MCP_IFPA_TXD_P<3>

16

=MCP_IFPA_TXD_N<3>

16

=MCP_IFPB_TXC_P

16

=MCP_IFPB_TXC_N

16

=MCP_IFPB_TXD_P<0..3>

16

=MCP_IFPB_TXD_N<0..3>

16

LCD_IG_BKLT_PWM

7

OUT

17 76

OUT

17 76

OUT

17 76

OUT

17 76

OUT

17 76

OUT

17 76

OUT

17 76

BI

16

17

OUT

16

18 31

OUT

16

LCD_IG_BKLT_EN

16

=MCP_IFPAB_DDC_CLK

16

=MCP_IFPAB_DDC_DATA

16

DP_IG_ML0_P<0..3>
DP_IG_ML0_N<0..3>

DP_IG_HPD0
DP_IG_AUX_CH0_P

16

DP_IG_AUX_CH0_N

16

DP_AUX_CH_C_N

68

DP_AUX_CH_C_P

68

DP_CA_DET

68

DP_IG_ML1_P<0..3>

16

DP_IG_ML1_N<0..3>

16

DP_IG_AUX_CH1_P

16

DP_IG_AUX_CH1_N

16

DP_IG_HPD1

16

B

DACS ALIASES

UNUSED CRT & TV-OUT INTERFACE

NC_MCP_TV_DAC_RSET

NO_TEST=TRUE

NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

NC_MCP_CLK27M_XTALIN

NO_TEST=TRUE

NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE

NC_CRT_IG_R_C_PR

NO_TEST=TRUE

NC_CRT_IG_G_Y_Y

NO_TEST=TRUE

NC_CRT_IG_B_COMP_PB

NO_TEST=TRUE

NC_CRT_IG_HSYNC

NO_TEST=TRUE

NC_CRT_IG_VSYNC

NO_TEST=TRUE

LVDS ALIASES

LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<0..2>
LVDS_IG_A_DATA_N<0..2>

NC_LVDS_IG_A_DATAP<3>
NC_LVDS_IG_A_DATAN<3>
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_DATAP<0..3>
NC_LVDS_IG_B_DATAN<0..3>

LCD_BKLT_PWM
LCD_BKLT_EN

LVDS_DDC_CLK
LVDS_DDC_DATA

DISPLAY PORT ALIASES

DP_IG_ML_P<0..3>

74

DP_IG_ML_N<0..3>

74

402

R0920

1 2

100K

5%

MF-LF

1/16W

DP_EXT_HPD
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N

DP_EXT_AUX_CH_C_N
DP_EXT_AUX_CH_C_P

DP_EXT_CA_DET

TP_DP_IG_ML1P<0..3>
TP_DP_IG_ML1N<0..3>
TP_DP_IG_AUX_CH1P
TP_DP_IG_AUX_CH1N

AUDIO ALIASES

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_EXT_ML_P<0..3>
DP_EXT_ML_N<0..3>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

67 74

67 74

6

6

70

71

6

6

69 16

68 74

68 74

69 79

69 79

69

67 74

67 74

67

67

MAKE_BASE=TRUE

MAKE_BASE=TRUE

CPU_BSEL<0:2>

9

72

MAKE_BASE=TRUE

CPU_PECI_MCP

13

TP_MCP_RGB_RED

16

TP_MCP_RGB_GREEN

16

TP_MCP_RGB_BLUE

16

TP_MCP_RGB_HSYNC

16

TP_MCP_RGB_VSYNC

16

TP_MCP_RGB_DAC_RSET

16

TP_MCP_RGB_DAC_VREF

16

PP5V_SW_ODD

6

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.4 MM
VOLTAGE=5V

BACKLIGHT CONTROLLER ALIASES

PPBUS_SW_LCDBKLT_PWR

70 71

69 79

69 79

=CHGR_ACOK

IN

MCPCORES0_VO

MCPCORES0_ISP_R

62

2 1

CPU ALIASES

=MCP_BSEL<0:2>

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

MCP89 ALIASES

NC_MCP_RGB_RED

MAKE_BASE=TRUE

NC_MCP_RGB_GREEN

MAKE_BASE=TRUE

NC_MCP_RGB_BLUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF

MAKE_BASE=TRUE

5V ODD ALIASES

=PP5V_SW_ODD
=PP5V_SW_ODD_FET

R0910

1 2

PLACE_NEAR=L9701.1:5MM

5%
1/16W
MF-LF

402

0

PPBUS_SW_BKL

=PPBUS_SW_BKL

CHARGER SIGNAL

SMC_BC_ACOK

MAKE_BASE=TRUE

MCPCOREISNS SIGNAL

MCPCOREISNS_N

MAKE_BASE=TRUE

MCPCOREISNS_P

MAKE_BASE=TRUE

13

BSEL<2..0>

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE

=MCPCOREISNS_N

=MCPCOREISNS_P

0 0 0
0 0 1
0 1 0
0 1 1 (166)
1 0 0
1 0 1

1 1 1

36

36

OUT

FSB MHZ

266
133
200

333

100
(400)1 1 0
(RSVD)

D

C

70

39 40 57 58

44 62

44

B

EMI IO (SHORT) POGO PINS

HDA:1.5V

1.4DIA-SHORT-EMI-MLB-K19-K24

1.4DIA-SHORT-EMI-MLB-K19-K24

ZS0900

SM SM

1 1 1

ZS0903 ZS0908

SM

1 1 1

1.4DIA-SHORT-EMI-MLB-K19-K24

1.4DIA-SHORT-EMI-MLB-K19-K24

A

ZS0904

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0901 ZS0902

SM SM

1.4DIA-SHORT-EMI-MLB-K19-K24

1.4DIA-SHORT-EMI-MLB-K19-K24

SM

ZS0909

EMI TALL POGO PINS

ZS0905

SM

1 11 1

2.0DIA-TALL-EMI-MLB-M97-M982.0DIA-TALL-EMI-MLB-M97-M98

ZS0906

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0907

SM

=PP1V5_S0_AUDIO_R

7

=PP3V3_S0_AUDIO_R

7

=PP1V5_S0_MCP_HDA_R

7

=PP3V3_S0_MCP_HDA_R

7

R0912

HDA:3.3V

R0913

HDA:1.5V

R0914

HDA:3.3V

R0915

8 7 5 4 2 1

1 2

40205%

0

1 2

402

5%

1/16W

0

1 2

4025%1/16W MF-LF

0

1 2

402

1/16W MF-LF

5%

PP3V3R1V5_S0_AUDIO

PP3V3R1V5_S0_MCP_HDA

MAKE_BASE=TRUE

MF-LF1/16W

VOLTAGE=1.5V

=PP3V3R1V5_S0_AUDIO

MF-LF

MAKE_BASE=TRUE
VOLTAGE=1.5V

=PP3V3R1V5_S0_MCP_HDA

36

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

51

18 22

SYNC_MASTER=K24_MLB

PAGE TITLE

SIGNAL ALIAS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

9 OF 109

SHEET

8 OF 80

SIZE

A

D

345678

2 1

OMIT

ADS*
BNR*

BPRI*

DEFER*

DRDY*
DBSY*

BR0*

IERR*
INIT*

LOCK*

RESET*

RS0*
RS1*
RS2*

TRDY*

HIT*

HITM*

BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*

TRST*

DBR*

PROCHOT*

THERMDA
THERMDC

BCLK0
BCLK1

TCK
TDI
TDO
TMS

H1

FSB_ADS_L

E2

FSB_BNR_L

G5

FSB_BPRI_L

H5

FSB_DEFER_L

F21

FSB_DRDY_L

E1

FSB_DBSY_L

F1

FSB_BREQ0_L

D20

CPU_IERR_L

72

B3

CPU_INIT_L

H4

FSB_LOCK_L

C1

FSB_CPURST_L

F3

FSB_RS_L<0>

F4

FSB_RS_L<1>

G3

FSB_RS_L<2>

G2

FSB_TRDY_L

G6

FSB_HIT_L

E4

FSB_HITM_L

AD4

XDP_BPM_L<0>

AD3

XDP_BPM_L<1>

AD1

XDP_BPM_L<2>

AC4

XDP_BPM_L<3>

AC2

XDP_BPM_L<4>

AC1

XDP_BPM_L<5>

AC5

XDP_TCK

AA6

XDP_TDI

AB3

XDP_TDO

AB5

XDP_TMS

AB6

XDP_TRST_L

C20

XDP_DBRESET_L

D21

CPU_PROCHOT_L

A24

CPU_THERMD_P

B25

CPU_THERMD_N

C7

PM_THRMTRIP_L

A22

FSB_CLK_CPU_P

A21

FSB_CLK_CPU_N

IN

IN
IN
IN
IN
IN

IN
IN

OUT

IN
IN

OUT

OUT
OUT

OUT

IN
IN

CPU JTAG Support

XDP_TMS

9

12 72

XDP_TDI

9

12 72

XDP_TDO

9

12 72

PLACE_NEAR=J1300.51:12.7 mm

XDP_TCK

9

12 72

XDP_TRST_L

9

12 72

BI
BI
BI

BI
BI
BI

BI

BI

BI
BI

BI
BI
BI
BI
BI

6

13 72

13 72

13 72

13 72

13 72

13 72

13 72

13 72

6

13 72

12 13 72

13 72

13 72

13 72

13 72

6

13 72

6

13 72

12 72

12 72

12 72

12 72

12 72

9

12 72

9

12 72

9

12 72

9

12 72

9

12 72

12 24

45 79

45 79

13 40 72

13 72

13 72

R1091

54.9

1 2

1/16W
MF-LF

R1094

1 2

1/16W
MF-LF

1%

402

649

1%

402

R1000

54.9

R1001

54.9

R1002

R1090

54.9

1 2

1%
1/16W
MF-LF

402

R1092

54.9

1 2

1%
1/16W
MF-LF

402

R1093

54.9

1 2

1%
1/16W
MF-LF

402

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

=PP1V05_S0_CPU

1

1%

402

2

7

10 11 12 61

D

FSB_D_L<0>

6

13 72

BI

FSB_D_L<1>

6

13 72

1

1%

402

2

1

68

5%

402

2

BI

OUT

1

R1005

1K

1%
1/16W
MF-LF
402

2

1

R1006

2.0K

1%
1/16W
MF-LF
402

2

NO STUFF

R1011

12 72

13 40 61 72

PLACE_NEARs:

R1005.2:
R1006.1:
C1014.1:

NO STUFF

R1010

1 2

1

1K

5%
1/16W
MF-LF

402

2

U1000.AD26:12.7 mm
U1000.AD26:12.7 mm
U1000.AF26:12.7 mm

NO STUFF

C1014

0

5%
1/16W
MF-LF

402

NO STUFF

1

R1012

1K

5%
1/16W
MF-LF
402

2

0.1uF

1

10%
16V

2

X5R
402

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

28 72

8

72

OUT

8

72

OUT

8

72

OUT

FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>

FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>

CPU_GTLREF
CPU_TEST1

CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6

TP_CPU_TEST7

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

AD26

C23
D25
C24

AF26

AF1
A26

B22
B23
C21

C3

D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*

D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2

U1000

PENRYN

FCBGA

2 OF 4

DATA GRP 0DATA GRP 1

MISC

DATA GRP 3 DATA GRP 2

OMIT

D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*

D47*
DSTBN2*
DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*
DSTBN3*
DSTBP3*

DINV3*

COMP0
COMP1
COMP2
COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

Y22

FSB_D_L<32>

AB24

FSB_D_L<33>

V24

FSB_D_L<34>

V26

FSB_D_L<35>

V23

FSB_D_L<36>

T22

FSB_D_L<37>

U25

FSB_D_L<38>

U23

FSB_D_L<39>

Y25

FSB_D_L<40>

W22

FSB_D_L<41>

Y23

FSB_D_L<42>

W24

FSB_D_L<43>

W25

FSB_D_L<44>

AA23

FSB_D_L<45>

AA24

FSB_D_L<46>

AB25

FSB_D_L<47>

Y26

FSB_DSTB_L_N<2>

AA26

FSB_DSTB_L_P<2>

U22

FSB_DINV_L<2>

AE24

FSB_D_L<48>

AD24

FSB_D_L<49>

AA21

FSB_D_L<50>

AB22

FSB_D_L<51>

AB21

FSB_D_L<52>

AC26

FSB_D_L<53>

AD20

FSB_D_L<54>

AE22

FSB_D_L<55>

AF23

FSB_D_L<56>

AC25

FSB_D_L<57>

AE21

FSB_D_L<58>

AD21

FSB_D_L<59>

AC22

FSB_D_L<60>

AD23

FSB_D_L<61>

AF22

FSB_D_L<62>

AC23

FSB_D_L<63>

AE25

FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>

AF24

FSB_DINV_L<3>

AC20

R26

CPU_COMP<0>

72

U26

CPU_COMP<1>

72

AA1

CPU_COMP<2>

72

CPU_COMP<3>

72

Y1

E5

CPU_DPRSTP_L

B5

CPU_DPSLP_L

D24

FSB_DPWR_L

D6

CPU_PWRGD

D7

FSB_CPUSLP_L

AE6

CPU_PSI_L

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

13 61 72

IN

13 72

IN

13 72

IN

12 13 72

IN

13 72

IN

61

OUT

R1023

54.9

1/16W
MF-LF

1

1%

402

2

1

2

R1021

54.9

1/16W
MF-LF

R1022

27.4

1%
1/16W
MF-LF
402

1

1%

402

2

1

R1020

27.4

1%
1/16W
MF-LF
402

2

C

B

PLACE_NEARs:

R1020.1:

U1000.R26:12.7 mm
U1000.U26:12.7 mm

R1021.1:
R1022.1:

U1000.AA1:12.7 mm

R1023.1:

U1000.Y1:12.7 mm

AA4
AB2
AA3

D22

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

K3
H2
K2
J3
L1

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3

V1

A6
A5
C4

D5
C6
B4
A3

M4
N5
T2
V3
B2
F6
D2

D3

A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*

REQ0*
REQ1*
REQ2*
REQ3*
REQ4*

A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*

A20M*
FERR*
IGNNE*

STPCLK*
LINT0
LINT1
SMI*

RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8

U1000

PENRYN

FCBGA

1 OF 4

ADDR GROUP0

ADDR GROUP1

ICH

RESERVED

CONTROL

XDP/ITP SIGNALS

THERMAL

THERMTRIP*

H CLK

FSB_A_L<3>

6

13 72

BI

FSB_A_L<4>

6

13 72

BI

FSB_A_L<5>

6

13 72

BI

FSB_A_L<6>

6

13 72

BI

FSB_A_L<7>

6

13 72

BI

FSB_A_L<8>

6

13 72

BI

FSB_A_L<9>

6

13 72

BI

FSB_A_L<10>

6

13 72

BI

FSB_A_L<11>

6

13 72

BI

FSB_A_L<12>

6

13 72

BI

FSB_A_L<13>

6

13 72

D

C

BI

FSB_A_L<14>

6

13 72

BI

FSB_A_L<15>

6

13 72

BI

FSB_A_L<16>

6

13 72

BI

FSB_ADSTB_L<0>

6

13 72

BI

FSB_REQ_L<0>

6

13 72

BI

FSB_REQ_L<1>

6

13 72

BI

FSB_REQ_L<2>

6

13 72

BI

FSB_REQ_L<3>

6

13 72

BI

FSB_REQ_L<4>

6

13 72

BI

FSB_A_L<17>

6

13 72

BI

FSB_A_L<18>

6

13 72

BI

FSB_A_L<19>

6

13 72

BI

FSB_A_L<20>

6

13 72

BI

FSB_A_L<21>

6

13 72

BI

FSB_A_L<22>

6

13 72

BI

FSB_A_L<23>

6

13 72

BI

FSB_A_L<24>

6

13 72

BI

FSB_A_L<25>

6

13 72

BI

FSB_A_L<26>

6

13 72

BI

FSB_A_L<27>

6

13 72

BI

FSB_A_L<28>

6

13 72

BI

FSB_A_L<29>

6

13 72

BI

FSB_A_L<30>

6

13 72

BI

FSB_A_L<31>

6

13 72

BI

FSB_A_L<32>

6

13 72

BI

FSB_A_L<33>

6

13 72

BI

FSB_A_L<34>

6

13 72

BI

FSB_A_L<35>

6

13 72

BI

FSB_ADSTB_L<1>

6

13 72

BI

CPU_A20M_L

13 72

IN

CPU_FERR_L

13 72

OUT

CPU_IGNNE_L

13 72

IN

CPU_STPCLK_L

13 72

IN

CPU_INTR

13 72

IN

CPU_NMI

13 72

IN

CPU_SMI_L

13 72

IN

TP_CPU_RSVD_M4
TP_CPU_RSVD_N5
TP_CPU_RSVD_T2
TP_CPU_RSVD_V3
TP_CPU_RSVD_B2
TP_CPU_RSVD_F6
TP_CPU_RSVD_D2
TP_CPU_RSVD_D22
TP_CPU_RSVD_D3

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU FSB

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

10 OF 109

SHEET

9 OF 80

SIZE

A

D

345678

2 1

A4

(CPU CORE POWER)
=PPVCORE_S0_CPU

AA10

AA12

AA13
AA15

AA17

AA18
AA20

AC10
AB10

AB12
AB14

AB15

AB17
AB18

A7

A9

A10
A12

A13

A15
A17

A18
A20

B7

B9
B10

B12

B14
B15

B17

B18
B20

C9
C10

C12

C13
C15

C17

C18

D9

D10

D12
D14

D15

VCC

D17

D18

E7

E9

E10

E12
E13

E15

E17
E18

E20

F7

F9

F10
F12

F14

F15
F17

F18

F20
AA7

(BR1#)

AA9

AB9

OMIT

U1000

PENRYN

FCBGA

3 OF 4

VCCSENSE

VSSSENSE

D

C

B

VCC

VCCP

VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

AB20

AB7

AC7
AC9

AC12

AC13
AC15

AC17
AC18

AD7

AD9
AD10

AD12

AD14
AD15

AD17

AD18
AE9

AE10
AE12

AE13

AE15
AE17

AE18

AE20
AF9
AF10

AF12

AF14
AF15

AF17

AF18
AF20

G21
V6

J6
K6

M6

J21
K21

M21

N21
N6

R21

R6

T21
T6

V21

W21

B26
C26

AD6
AF5

AE5

AF4
AE3

AF3

AE2

AF7

AE7

(CPU IO POWER 1.05V)

=PP1V05_S0_CPU

(CPU INTERNAL PLL POWER 1.5V)
=PP1V5_S0_CPU

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

7

10 11

44 A (SV Design Target)
41 A (SV HFM)

30.4 A (SV LFM)
23 A (LV Design Target)

7 9

11 12 61

4500 mA (before VCC stable)
2500 mA (after VCC stable)

7

11

130 mA

61 72

OUT

61 72

OUT

61 72

OUT

61 72

OUT

61 72

OUT

61 72

OUT

61 72

OUT

=PPVCORE_S0_CPU

1

R1100

100

1%
1/16W
MF-LF
402

2

61 72

OUT

PLACE_NEAR=U1000.AF7:25.4 mm

PLACE_NEAR=U1000.AE7:25.4 mm

61 72

OUT

1

R1101

100

1%
1/16W
MF-LF
402

2

7

10 11

A8

A11
A14

A16

A19
A23

AF2

B6
B8

B11

B13
B16

B19
B21

B24

C5
C8

C11

C14
C16

C19

C2
C22

C25

D1

D4

D8
D11

D13

D16
D19

D23

D26

E3

E6

E8

E11
E14

VSS VSS

E16
E19

E21
E24

F5

F8
F11

F13
F16

F19

F2
F22

F25

G4

G1

G23

G26

H3

H6
H21

H24

J2

J5

J22

J25

K1

K4

K23
K26

L3

L6

L21

L24

M2

M5

M22
M25

N1

N4
N23

N26

P3

B1

(Socket-P KEY)

OMIT

U1000

PENRYN

FCBGA

4 OF 4

T26

U3
U6

U21
U24

V2

V5

V22
V25

W1

W4
W23

W26
Y3

Y6
Y21

Y24

AA2
AA5

AA8

AA11
AA14

AA16

AA19
AA22

AA25
AB1

AB4

AB8
AB11

AB13

AB16
AB19

AB23

AB26
AC3

AC6

AC8

AC11
AC14

AC16
AC19

AC21

AC24
AD2
AD5
AD8

AD11
AD13

AD16

AD19
AD22

AD25

AE1

AE4
AE8

AE11

AE14
AE16

AE19

AE23
AE26

A2
AF6

AF8

AF11
AF13

AF16

AF19
AF21

A25

AF25

P6

P21
P24

R2

R5
R22

R25
T1

T4

T23

D

C

B

A

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU Power & Ground

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

11 OF 109

SHEET

10 OF 80

36

345678

2 1

CPU VCore HF and Bulk Decoupling

4X 330UF. 20X 22UF 0805

PLACEMENT_NOTE (C1200-C1219):

=PPVCORE_S0_CPU

7

D

10

CPU_CAP:15&CPU_CAP:12

CRITICAL

1

C1200

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

CRITICAL

1

C1210

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

NO STUFF
CRITICAL

1

C1201

22UF

20%

6.3V

2

X5R-CERM
603

1

2

CPU_CAP:15&CPU_CAP:12

NO STUFF
CRITICAL

1

C1211

22UF

20%

6.3V

2

X5R-CERM
603

1

2

NO STUFF

CRITICAL

C1202

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1212

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

1

C1203

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

CRITICAL

1

C1213

22UF

20%

6.3V

2

X5R-CERM
603

NO STUFF
CRITICAL

1

C1204

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

CPU_CAP:15&CPU_CAP:12

CRITICAL

1

C1214

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

CPU_CAP:15

CRITICAL

1

C1205

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1215

22UF

20%

6.3V

2

X5R-CERM
603

1

2

CPU_CAP:15

1

2

NO STUFF

CRITICAL

C1206

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

1

C1207

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

CRITICAL

C1216

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

1

C1217

22UF

20%

6.3V

2

X5R-CERM
603

NO STUFF
CRITICAL

1

C1208

22UF

20%

6.3V

2

X5R-CERM
603

1

2

CPU_CAP:15&CPU_CAP:12

CPU_CAP:15&CPU_CAP:12

CRITICAL

1

C1218

22UF

20%

6.3V

2

X5R-CERM
603

1

2

NO STUFF
CRITICAL

C1209

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1219

22UF

20%

6.3V
X5R-CERM
603

PLACEMENT_NOTE (C1240-C1243):

CPU_CAP:15&CPU_CAP:12

Place inside socket cavity on secondary side.

NO STUFF
CRITICAL

1

C1220

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1221

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15

CRITICAL

1

C1222

22UF

20%

6.3V

2

X5R-CERM
603

C

Place on secondary side.

Place on secondary side.

Place on secondary side.

Place on secondary side.

CRITICAL
NO STUFF

1

C1240

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT
D2T-SM

CRITICAL

1

C1241

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT
D2T-SM

CRITICAL

1

C1242

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT
D2T-SM

CRITICAL

1

C1243

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT
D2T-SM

D

C

VCCA (CPU AVdd) DECOUPLING

=PP1V5_S0_CPU

7

10

B

1x 10uF, 1x 0.01uF

BYPASS=U1000.B26::4 mm

1

1

C1251C1250

10uF

6.3V

20%
X5R

603

0.01UF

10%
16V

2

2

CERM
402

B

VCCP (CPU I/O) DECOUPLING

=PP1V05_S0_CPU

7 9

10 12 61

CRITICAL

C1260

POLY-TANT

A

8 7 5 4 2 1

1x 330uF, 6x 0.1uF 0402

PLACEMENT_NOTE=Place C1260 between CPU & NB.

1

330UF

2.0V

D2T-SM2

1

C1261

0.1UF

20%

20%
10V

32

2

CERM
402

1

C1262

0.1UF

20%
10V

2

CERM
402

1

2

C1263

0.1UF

20%
10V
CERM
402

1

C1264

0.1UF

20%
10V

2

CERM
402

1

C1265

0.1UF

20%
10V

2

CERM
402

1

C1266

0.1UF

20%
10V

2

CERM
402

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

12 OF 109

SHEET

11 OF 80

36

345678

2 1

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

D

Use with 920-0620 adapter board to support CPU, MCP debugging.

D

MCP89-specific pinout

=PP3V3_S0_XDP

7

=PP1V05_S0_CPU

7 9

10 11 61

XDP

1

R1315

54.9

1%
1/16W
MF-LF

402

2

XDP_BPM_L<5>

9

72

BI

XDP_BPM_L<4>

9

72

BI

XDP_BPM_L<3>

9

72

BI

XDP_BPM_L<2>

9

72

IN

XDP_BPM_L<1>

9

72

IN

XDP_BPM_L<0>

9

72

IN

C

XDP

R1399

1K

CPU_PWRGD

9

13 72

IN

1 2

5%
1/16W
MF-LF

402

18

IN

18

OUT

18 42 75

BI

18 42 75

BI

9

72

OUT

TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3

XDP_PWRGD

PM_LATRIGGER_L
JTAG_MCP_TCK

SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK

XDP_TCK

XDP_OBS20

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_A1

OBSDATA_A2

OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

C1300

0.1uF

HOOK1

HOOK2

HOOK3

TCK1
TCK0

XDP

SDA

SCL

1

10%
16V

2

X5R
402

B

CRITICAL

XDP_CONN

J1300

LTH-030-01-G-D-NOPEGS

F-ST-SM

2

1

4 3

6

5

8

10

12
14

16
18

20

22
24

26

28
30

32

34
36

38
40

42

44
46

48

50
52

54

56

NC

58

60

7

9

11
13

15
17

19

21
23

25

27
29

31

33
35

37
39

41

43
45

47

49
51

53

55
57

59

998-1571

OBSFN_C0

OBSFN_C1

OBSDATA_C0

OBSDATA_C1

OBSDATA_C2

OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5

VCC_OBS_CD
RESET#/HOOK6

DBR#/HOOK7

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
TDO

TRSTn

TDI
TMS

XDP_PRESENT#

XDP

1

C1301

0.1uF

10%
16V

2

X5R
402

JTAG_MCP_TDO
JTAG_MCP_TRST_L

TP_XDP_OBSDATA_C0
TP_XDP_OBSDATA_C1

TP_XDP_OBSDATA_C2
TP_XDP_OBSDATA_C3

JTAG_MCP_TDI
JTAG_MCP_TMS

TP_XDP_OBSDATA_D0
TP_XDP_OBSDATA_D1

TP_XDP_OBSDATA_D2
TP_XDP_OBSDATA_D3

FSB_CLK_ITP_P
FSB_CLK_ITP_N

XDP_CPURST_L

72

XDP_DBRESET_L

XDP_TDO
XDP_TRST_L
XDP_TDI
XDP_TMS

18

IN

18

OUT

18

OUT

18

OUT

13 72

IN

13 72

IN

9

24

OUT

9

72

IN

9

72

OUT

9

72

OUT

9

72

OUT

XDP

R1303

1K

1 2

FSB_CPURST_L

5%

PLACEMENT_NOTE=Place close to CPU to minimize stub.

1/16W
MF-LF

402

9

13 72

IN

C

B

Direction of XDP module

Please avoid any obstructions

on even-numbered side of J1300

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

eXtended Debug Port (mini-XDP)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

13 OF 109

SHEET

12 OF 80

SIZE

A

D

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

FSB_DSTB_L_P<0>

6 9

72

BI

FSB_DSTB_L_N<0>

6 9

72

BI

FSB_DINV_L<0>

6 9

72

BI

FSB_DSTB_L_P<1>

6 9

72

BI

FSB_DSTB_L_N<1>

6 9

72

BI

FSB_DINV_L<1>

6 9

72

BI

FSB_DSTB_L_P<2>

6 9

72

D

C

B

=PP1V05_S0_MCP_FSB

7

13 19 22

1

1

9

40 72

IN

9

72

IN

8

IN

8

IN

8

IN

R1410

PM_THRMTRIP_L
CPU_FERR_L

=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>

54.9

1%
1/16W
MF-LF

402

R1430

49.9

1/16W
MF-LF

2

402

1%

121

R1415

62

5%
1/16W
MF-LF
402

2

R1435

49.9

1%
1/16W
MF-LF
402

2

A

121

R1431

49.9

1/16W
MF-LF

R1436

49.9

1%

1%

1/16W
MF-LF
402

402

2

BI

FSB_DSTB_L_N<2>

6 9

72

BI

FSB_DINV_L<2>

6 9

72

BI

FSB_DSTB_L_P<3>

6 9

72

BI

FSB_DSTB_L_N<3>

6 9

72

BI

FSB_DINV_L<3>

6 9

72

BI

FSB_A_L<3>

6 9

72

BI

FSB_A_L<4>

6 9

72

BI

FSB_A_L<5>

6 9

72

BI

FSB_A_L<6>

6 9

72

BI

FSB_A_L<7>

6 9

72

BI

FSB_A_L<8>

6 9

72

BI

FSB_A_L<9>

6 9

72

BI

FSB_A_L<10>

6 9

72

BI

FSB_A_L<11>

6 9

72

BI

FSB_A_L<12>

6 9

72

BI

FSB_A_L<13>

6 9

72

BI

FSB_A_L<14>

6 9

72

BI

FSB_A_L<15>

6 9

72

BI

FSB_A_L<16>

6 9

72

BI

FSB_A_L<17>

6 9

72

BI

FSB_A_L<18>

6 9

72

BI

FSB_A_L<19>

6 9

72

BI

FSB_A_L<20>

6 9

72

BI

FSB_A_L<21>

6 9

72

BI

FSB_A_L<22>

6 9

72

BI

FSB_A_L<23>

6 9

72

BI

FSB_A_L<24>

6 9

72

BI

FSB_A_L<25>

6 9

72

BI

FSB_A_L<26>

6 9

72

BI

FSB_A_L<27>

6 9

72

BI

FSB_A_L<28>

6 9

72

BI

FSB_A_L<29>

6 9

72

BI

FSB_A_L<30>

6 9

72

BI

FSB_A_L<31>

6 9

72

BI

FSB_A_L<32>

6 9

72

BI

FSB_A_L<33>

6 9

72

BI

FSB_A_L<34>

6 9

72

BI

FSB_A_L<35>

6 9

72

BI

FSB_ADSTB_L<0>

6 9

72

BI

FSB_ADSTB_L<1>

6 9

72

BI

FSB_REQ_L<0>

6 9

72

BI

FSB_REQ_L<1>

6 9

72

BI

FSB_REQ_L<2>

6 9

72

BI

FSB_REQ_L<3>

6 9

72

BI

FSB_REQ_L<4>

6 9

72

BI

FSB_ADS_L

6 9

72

IN

FSB_BNR_L

9

72

IN

FSB_BREQ0_L

9

72

IN

FSB_DBSY_L

9

72

IN

FSB_DRDY_L

9

72

IN

FSB_HIT_L

6 9

72

IN

FSB_HITM_L

6 9

72

IN

FSB_LOCK_L

6 9

72

IN

FSB_TRDY_L

9

72

BI

CPU_PECI_MCP

8

OUT

CPU_PROCHOT_L

40 61 72

9

OUT

FSB_RS_L<0>

9

72

OUT

FSB_RS_L<1>

9

72

OUT

FSB_RS_L<2>

9

72

OUT

MCP_BCLK_VML_COMP_VDD

72

MCP_BCLK_VML_COMP_GND

72

MCP_CPU_COMP_VCC

72

MCP_CPU_COMP_GND

72

K34

CPU_DSTBP0*

K35

CPU_DSTBN0*

L37

CPU_DBI0*

T31

CPU_DSTBP1*

T30

CPU_DSTBN1*

P28

CPU_DBI1*

K33

CPU_DSTBP2*

K32

CPU_DSTBN2*

N35

CPU_DBI2*

C36

CPU_DSTBP3*

D36

CPU_DSTBN3*

A35

CPU_DBI3*

U38

CPU_A3*

U34

CPU_A4*

U35

CPU_A5*

T34

CPU_A6*

W37

CPU_A7*

W38

CPU_A8*

T37

CPU_A9*

Y38

CPU_A10*

W35

CPU_A11*

Y36

CPU_A12*

U33

CPU_A13*

W34

CPU_A14*

Y37

CPU_A15*

Y35

CPU_A16*

AF38

CPU_A17*

AB35

CPU_A18*

Y34

CPU_A19*

AE38

CPU_A20*

AC36

CPU_A21*

AF36

CPU_A22*

AC38

CPU_A23*

AB36

CPU_A24*

AB38

CPU_A25*

AB37

CPU_A26*

AC34

CPU_A27*

AE36

CPU_A28*

AF37

CPU_A29*

AC37

CPU_A30*

AC35

CPU_A31*

AE37

CPU_A32*

AE35

CPU_A33*

AE33

CPU_A34*

AE34

CPU_A35*

W36

CPU_ADSTB0*

AB34

CPU_ADSTB1*

U36

CPU_REQ0*

T36

CPU_REQ1*

U37

CPU_REQ2*

T38

CPU_REQ3*

T35

CPU_REQ4*

AE31

CPU_ADS*

AE32

CPU_BNR*

AE30

CPU_BR0*

AE29

CPU_DBSY*

U29

CPU_DRDY*

W32

CPU_HIT*

AB31

CPU_HITM*

AC32

CPU_LOCK*

AC29

CPU_TRDY*

AH34

CPU_PECI

U28

CPU_PROCHOT*

W33

CPU_THERMTRIP*

AB32

CPU_FERR*

B34

CPU_BSEL2

C34

CPU_BSEL1

A34

CPU_BSEL0

AB29

CPU_RS0*

AC33

CPU_RS1*

AC31

CPU_RS2*

AH37

BCLK_VML_COMP_VDD

AH38

BCLK_VML_COMP_GND

AH36

CPU_COMP_VCC

AH35

CPU_COMP_GND

8 7 5 4 2 1

(1 OF 11)

FSB

CPU_D0*
CPU_D1*
CPU_D2*
CPU_D3*
CPU_D4*
CPU_D5*
CPU_D6*
CPU_D7*
CPU_D8*

CPU_D9*
CPU_D10*
CPU_D11*
CPU_D12*
CPU_D13*
CPU_D14*
CPU_D15*
CPU_D16*
CPU_D17*
CPU_D18*
CPU_D19*
CPU_D20*
CPU_D21*
CPU_D22*
CPU_D23*
CPU_D24*
CPU_D25*
CPU_D26*
CPU_D27*
CPU_D28*
CPU_D29*
CPU_D30*
CPU_D31*
CPU_D32*
CPU_D33*
CPU_D34*
CPU_D35*
CPU_D36*
CPU_D37*
CPU_D38*
CPU_D39*
CPU_D40*
CPU_D41*
CPU_D42*
CPU_D43*
CPU_D44*
CPU_D45*
CPU_D46*
CPU_D47*
CPU_D48*
CPU_D49*
CPU_D50*
CPU_D51*
CPU_D52*
CPU_D53*
CPU_D54*
CPU_D55*
CPU_D56*
CPU_D57*
CPU_D58*
CPU_D59*
CPU_D60*
CPU_D61*
CPU_D62*
CPU_D63*

CPU_BPRI*

CPU_DEFER*

BCLK_OUT_CPU_N
BCLK_OUT_CPU_P

BCLK_OUT_ITP_N
BCLK_OUT_ITP_P

BCLK_OUT_NB_N
BCLK_OUT_NB_P

BCLK_IN_P
BCLK_IN_N

CPU_A20M*

CPU_IGNNE*

CPU_INIT*

CPU_INTR

CPU_NMI
CPU_SMI*

CPU_PWRGD

CPU_RESET*

CPU_DPRSLPVR

CPU_SLP*

CPU_DPSLP*

CPU_DPWR*
CPU_STPCLK*
CPU_DPRSTP*

N38
N36
P36
L36
N34
L35
P37
P38
H36
L34
K37
K36
K38
N37
H37
L38
N28
U30
N29
P34
T29
T32
U32
T33
P31
P30
N30
P33
N31
T28
P35
P29
H33
G34
L30
L31
L33
P32
N32
N33
H35
K31
H34
K30
L32
G33
H32
G35
C37
D37
H38
G38
G37
G36
B35
E35
B36
E36
C35
D34
E38
D38
E34
E37

Y31
Y30

AF32
AF33

AF35
AF34

AF28
AF29

AF30
AF31

W30
AB30
AB28
W31
AC30
AC28
Y32
AE28
G1
Y33
AB33
U31
Y29
W29

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

FSB_BPRI_L
FSB_DEFER_L

FSB_CLK_CPU_N
FSB_CLK_CPU_P

FSB_CLK_ITP_N
FSB_CLK_ITP_P

FSB_CLK_MCP_N

72

FSB_CLK_MCP_P

72

CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
PM_DPRSLPVR
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

9

72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

12 72

OUT

12 72

OUT

Loop-back clock for delay matching.

9

72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

9

12 72

OUT

61 72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

9

61 72

OUT

=PP1V05_S0_MCP_FSB

NO STUFF

1

R1440

150

5%
1/16W
MF-LF
402

2

9

12 72

OUT

36

7

13 19 22

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP CPU Interface

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/05/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

14 OF 109

SHEET

13 OF 80

SIZE

D

C

B

A

D

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0

MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0

(2 OF 11)

MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N

MEMORY PARTITION 0

+VIO_M2CLK_DLL_1
+VIO_M2CLK_DLL_2

+VIO_PLL_MEM_1
+VIO_PLL_MEM_2

+VIO_PLL_FSB_1
+VIO_PLL_FSB_2

+VIO_PLL_CPU_1
+VIO_PLL_CPU_2
+VIO_PLL_CPU_3
+VIO_PLL_CPU_4

MCLK0A_1_P
MCLK0A_1_N

MCLK0A_0_P
MCLK0A_0_N

AK11
AL11
AH13
AH14
AL10
AK10
AN11
AJ13
AK13
AK14
AJ16
AH16
AJ14
AL13
AM14
AN14
AK17
AL17
AN17
AJ19
AH17
AJ17
AM16
AM17
AN26
AH29
AK29
AL29
AM25
AM26
AL28
AK28
AM28
AP29
AL31
AN32
AP28
AN28
AN31
AM31
AR34
AM32
AL33
AL35
AP32
AP33
AM35
AL32
AJ35
AJ31
AH32
AH33
AJ34
AL34
AJ33
AJ32

AM11
AL14
AN16
AJ29
AP31
AM34
AJ30

AP5
AP7
AR8
AP8
AR4
AR5
AM8
AN8

AR7

MEM_A_DQ<63>

27 73

BI

MEM_A_DQ<62>

27 73

BI

MEM_A_DQ<61>

27 73

BI

MEM_A_DQ<60>

27 73

BI

MEM_A_DQ<59>

27 73

D

C

B

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

OUT

27 73

OUT

27 73

OUT

27 73

OUT

27 73

OUT

27 73

OUT

27 73

OUT

27 73

OUT

MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>

MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>

MRAS0*
MCAS0*

MWE0*

MBA0_2
MBA0_1
MBA0_0

MA0_15
MA0_14
MA0_13
MA0_12
MA0_11
MA0_10

MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0

MCS0A_1*
MCS0A_0*

MODT0A_1
MODT0A_0

MCKE0A_1
MCKE0A_0

AN7
AM7
AN10
AM10
AN13
AM13
AL16
AK16
AH28
AJ28
AM29
AN29
AP34
AP35
AH31
AG31

AN19
AL19
AL20

AL25
AN20
AM19

AK26
AK25
AJ20
AJ26
AH25
AM20
AH26
AN23
AJ25
AM22
AM23
AN22
AL23
AK22
AK23
AL22

AF24
AG25

AF25
AG26

AF26
AG28

AC26
AD26
AE26
AF27

AH23
AJ23

AJ22
AH22

AH19
AK20

AH20
AK19

AL26
AN25

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>

MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>

=PP1V05_S0_MCP_M2CLK_DLL

PP1V05_S0_MCP_PLL_FSBMEM

20 mA

25 mA

25 mA

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_ODT<1>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CKE<0>

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73 26 73

OUT OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

7

70 mA

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

22

25 73

25 73

25 73

25 73

25 73

25 73

25 73

25 73

20 25 73

20 25 73

22

=PP1V5R1V35_SW_MCP_MEM

19 20 22

1

R1510

40.2

1%
1/16W
MF-LF

402

2

1

R1511

40.2

1%
1/16W
MF-LF

402

2

550 mA

MEM_B_DQ<63>

27 73

BI

MEM_B_DQ<62>

27 73

BI

MEM_B_DQ<61>

27 73

BI

MEM_B_DQ<60>

27 73

BI

MEM_B_DQ<59>

27 73

BI

MEM_B_DQ<58>

27 73

BI

MEM_B_DQ<57>

27 73

BI

MEM_B_DQ<56>

27 73

BI

MEM_B_DQ<55>

27 73

BI

MEM_B_DQ<54>

27 73

BI

MEM_B_DQ<53>

27 73

BI

MEM_B_DQ<52>

27 73

BI

MEM_B_DQ<51>

27 73

BI

MEM_B_DQ<50>

27 73

BI

MEM_B_DQ<49>

27 73

BI

MEM_B_DQ<48>

27 73

BI

MEM_B_DQ<47>

27 73

BI

MEM_B_DQ<46>

27 73

BI

MEM_B_DQ<45>

27 73

BI

MEM_B_DQ<44>

27 73

BI

MEM_B_DQ<43>

27 73

BI

MEM_B_DQ<42>

27 73

BI

MEM_B_DQ<41>

27 73

BI

MEM_B_DQ<40>

27 73

BI

MEM_B_DQ<39>

27 73

BI

MEM_B_DQ<38>

27 73

BI

MEM_B_DQ<37>

27 73

BI

MEM_B_DQ<36>

27 73

BI

MEM_B_DQ<35>

27 73

BI

MEM_B_DQ<34>

27 73

BI

MEM_B_DQ<33>

27 73

BI

MEM_B_DQ<32>

27 73

BI

MEM_B_DQ<31>

27 73

BI

MEM_B_DQ<30>

27 73

BI

MEM_B_DQ<29>

27 73

BI

MEM_B_DQ<28>

27 73

BI

MEM_B_DQ<27>

27 73

BI

MEM_B_DQ<26>

27 73

BI

MEM_B_DQ<25>

27 73

BI

MEM_B_DQ<24>

27 73

BI

MEM_B_DQ<23>

27 73

BI

MEM_B_DQ<22>

27 73

BI

MEM_B_DQ<21>

27 73

BI

MEM_B_DQ<20>

27 73

BI

MEM_B_DQ<19>

27 73

BI

MEM_B_DQ<18>

27 73

BI

MEM_B_DQ<17>

27 73

BI

MEM_B_DQ<16>

27 73

BI

MEM_B_DQ<15>

27 73

BI

MEM_B_DQ<14>

27 73

BI

MEM_B_DQ<13>

27 73

BI

MEM_B_DQ<12>

27 73

BI

MEM_B_DQ<11>

27 73

BI

MEM_B_DQ<10>

27 73

BI

MEM_B_DQ<9>

27 73

BI

MEM_B_DQ<8>

27 73

BI

MEM_B_DQ<7>

27 73

BI

MEM_B_DQ<6>

27 73

BI

MEM_B_DQ<5>

27 73

BI

MEM_B_DQ<4>

27 73

BI

MEM_B_DQ<3>

27 73

BI

MEM_B_DQ<2>

27 73

BI

MEM_B_DQ<1>

27 73

BI

MEM_B_DQ<0>

27 73

BI

MEM_B_DM<7>

27 73

OUT

MEM_B_DM<6>

27 73

OUT

MEM_B_DM<5>

27 73

OUT

MEM_B_DM<4>

27 73

OUT

MEM_B_DM<3>

27 73

OUT

MEM_B_DM<2>

27 73

OUT

MEM_B_DM<1>

27 73

OUT

MEM_B_DM<0>

27 73

OUT

MCP_MEM_COMP_GND

73

MCP_MEM_COMP_VDD

73

AP1
AR3
AV4
AU4
AP3
AP2
AU3
AT4
AT5
AT7
AU8

AR10

AV5
AU5

AP10

AT8
AT10
AU10
AR13
AR14
AR11
AP11
AT11
AP13
AV14
AU14
AR17
AP17
AP14
AT13
AP16
AR16
AU26
AT26
AU29
AT29
AV25
AV26
AV28
AV29
AT31
AR32
AT34
AU34
AR29
AR31
AU32
AT32
AV35
AT35
AR37
AP38
AV34
AU35
AR36
AR38
AM36
AM37
AJ36
AL36
AP37
AP36
AJ38
AJ37

AT2

AU7
AV10
AT14
AR28
AV32
AT37
AM38

AG23
AG22

MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0

MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0

MEM_COMP_GND
MEM_COMP_VDD

OMIT

U1400

MCP89M-A01

FBGA

(3 OF 11)

MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N

MRAS1*
MCAS1*

MWE1*

MBA1_2
MBA1_1
MBA1_0

MA1_15
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10

MA1_9
MA1_8
MA1_7
MA1_6

MEMORY PARTITION 1

MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

MRESET0*

MCLK1A_1_P
MCLK1A_1_N

MCLK1A_0_P
MCLK1A_0_N

MCS1A_1*
MCS1A_0*

MODT1A_1
MODT1A_0

MCKE1A_1
MCKE1A_0

AR2
AR1
AV7
AV8
AU11
AV11
AU13
AV13
AT28
AU28
AU31
AV31
AU36
AT36
AL38
AL37

AR19
AU17
AT17

AR25
AT19
AR20

AP26
AR26
AV16
AP25
AT23
AP20
AU23
AV22
AV23
AT22
AU22
AP23
AR23
AP22
AR22
AT20

AP4

AU20
AV20

AU19
AV19

AU16
AP19

AT16
AV17

AU25
AT25

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>

MEM_B_A<15>
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>

=PP1V5R1V35_S3_MCP_MEM

1

R1520

1K

5%
1/16W
MF-LF
402

2

MEM_RESET_L

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_ODT<1>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CKE<0>

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

7

25 26

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

20 26 73

OUT

20 26 73

OUT

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Memory Interface

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/06/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

15 OF 109

SHEET

14 OF 80

36

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

PEG_CLKREQ_L

8

IN

AP_CLKREQ_L

29

D

C

IN

ENET_CLKREQ_L

31

IN

FW_CLKREQ_L

34

IN

FW_PWR_EN

34

OUT

FW_PME_L

34

IN

PCIE_WAKE_L

6

24 29

IN

=PEG_D2R_P<0>

8

IN

=PEG_D2R_N<0>

8

IN

=PEG_D2R_P<1>

8

IN

=PEG_D2R_N<1>

8

IN

=PEG_D2R_P<2>

8

IN

=PEG_D2R_N<2>

8

IN

=PEG_D2R_P<3>

8

IN

=PEG_D2R_N<3>

8

IN

TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN

PCIE_FW_D2R_P

33 74

IN

PCIE_FW_D2R_N

33 74

IN

PCIE_AP_D2R_P

6

29 74

IN

PCIE_AP_D2R_N

6

29 74

IN

PCIE_ENET_D2R_P

31 74

IN

PCIE_ENET_D2R_N

31 74

IN

PP3V3_S0_MCP_PLL_HVDD

22

50 mA

PP1V05_S0_MCP_PLL_PEXSATA

22

325 mA

100 mA

80 mA

120 mA

25 mA

W4

PEA_CLKREQ*/GPIO_49

(IPU)

W5

PEB_CLKREQ*/GPIO_50

(IPU)

W7

PEC_CLKREQ*/GPIO_51

(IPU)

W8

PED_CLKREQ*/GPIO_52

(IPU)

W6

PEE_CLKREQ*/GPIO_53

(IPU)

W9

PEF_CLKREQ*/GPIO_54

(IPU)

U3

PE_WAKE*

(IPU-S5)

AC1

PE0_RX0_P

AB1

PE0_RX0_N

AC5

PE0_RX1_P

AC4

PE0_RX1_N

AC10

PE0_RX2_P

AC11

PE0_RX2_N

AB7

PE0_RX3_P

AB6

PE0_RX3_N

AB9

PE0_RX4_P

AB8

PE0_RX4_N

Y2

PE0_RX5_P

Y3

PE0_RX5_N

AB11

PE1_RX0_P

AB10

PE1_RX0_N

Y10

PE1_RX1_P

Y11

PE1_RX1_N

V11

+3.3V_PLL_HVDD_1

V13

+3.3V_PLL_HVDD_2

AH10

+VIO_PLL_PE

AG11

+VIO_PLL_XREF_XS_1

AF12

+VIO_PLL_XREF_XS_2

AF13

+VIO_PLL_XREF_XS_3

AH8

+VIO_PLL_SATA_1

AH9

+VIO_PLL_SATA_2

AH11

+VIO_PLL_H

(4 OF 11)

PE0_REFCLK_P
PE0_REFCLK_N

PE1_REFCLK_P
PE1_REFCLK_N

PE2_REFCLK_P
PE2_REFCLK_N

PE3_REFCLK_P
PE3_REFCLK_N

PE4_REFCLK_P
PE4_REFCLK_N

PE5_REFCLK_P
PE5_REFCLK_N

PCI EXPRESS

(IPD)

PEX0_TERM_P

PE0_TX0_P
PE0_TX0_N

PE0_TX1_P
PE0_TX1_N

PE0_TX2_P
PE0_TX2_N

PE0_TX3_P
PE0_TX3_N

PE0_TX4_P
PE0_TX4_N

PE0_TX5_P
PE0_TX5_N

PE1_TX0_P
PE1_TX0_N

PE1_TX1_P
PE1_TX1_N

B

PEX_RST*

Y1
W1

W3
W2

U4
U5

U7
U6

U9
U8

W10
W11

AC3
AC2

AB2
AB3

AC6
AC7

AC8
AC9

AB4
AB5

Y5
Y4

Y7
Y6

Y9
Y8

U1

U2

PEG_CLK100M_P
PEG_CLK100M_N

PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N

PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N

PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N

TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N

=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>

=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>

=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>

=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>

TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN

PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N

PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N

PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N

PCIE_RESET_L

NO STUFF

1

R1600

10K

5%
1/16W
MF-LF
402

2

MCP_PEX0_TERMP

74

PLACE_NEAR=U1400.U2:12.7 mm

R1610

2.49K

1/16W
MF-LF

8

74

OUT

8

74

OUT

29 74

OUT

29 74

OUT

31 74

OUT

31 74

OUT

33 74

OUT

33 74

OUT

PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1
PE1 ports are Gen1-only. 2 RCs: x1, x1

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

33 74

OUT

33 74

OUT

29 74

OUT

29 74

OUT

31 74

OUT

31 74

OUT

18 24

OUT

1

1%

402

2

If PE0[3:0] are not used,
+VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND

If PE0[4:5] and PE1[0:1] are not used,
+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP PCIe Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/05/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

16 OF 109

SHEET

15 OF 80

36

345678

2 1

OMIT

D

PP3V3_S0_MCP_DAC

23

140 mA

TP_MCP_RGB_DAC_RSET

8

TP_MCP_RGB_DAC_VREF

8

DP_IG_ML0_P<3>

8

OUT

DP_IG_ML0_N<3>

8

OUT

DP_IG_ML0_P<2>

8

OUT

DP_IG_ML0_N<2>

8

OUT

DP_IG_ML0_P<1>

8

OUT

DP_IG_ML0_N<1>

8

OUT

DP_IG_ML0_P<0>

8

OUT

DP_IG_ML0_N<0>

8

OUT

DP_IG_ML1_P<3>

8

OUT

DP_IG_ML1_N<3>

8

OUT

DP_IG_ML1_P<2>

8

OUT

DP_IG_ML1_N<2>

8

C

NOTE: 100K pull-downs required if
HPLUG_DET0/HPLUG_DET1 are not used.

OUT

DP_IG_ML1_P<1>

8

OUT

DP_IG_ML1_N<1>

8

OUT

DP_IG_ML1_P<0>

8

OUT

DP_IG_ML1_N<0>

8

OUT

DP_IG_HPD0

8

IN

DP_IG_HPD1

8

IN

SATARDRVR_A_EN

16 36

OUT

DP_IG_AUX_CH0_P

8

16

BI

DP_IG_AUX_CH0_N

16

8

BI

DP_IG_AUX_CH1_P

8

BI

DP_IG_AUX_CH1_N

8

BI

PP3V3_S0_MCP_PLL_DP_USB

22

210 mA

180 mA

30 mA

=PP1V05_S0_MCP_PLL_IFP

7

23

60 mA

PP1V05_S0_MCP_PLL_CORE

22

160 mA

B

=PP3V3R1V8_S0_MCP_IFP_VDD

7

23

180 mA

=PP1V05_S0_MCP_DP0_VDD

23

7

160 mA

40 mA
60 mA

40 mA
20 mA

B29

+3.3V_RGBDAC

C29

RGB_DAC_RSET

D29

RGB_DAC_VREF

D26

DP0_3_P/TMDS0_TXC_P

E26

DP0_3_N/TMDS0_TXC_N

G26

DP0_2_P/TMDS0_TX0_P

F26

DP0_2_N/TMDS0_TX0_N

F25

DP0_1_P/TMDS0_TX1_P

G25

DP0_1_N/TMDS0_TX1_N

E25

DP0_0_P/TMDS0_TX2_P

D25

DP0_0_N/TMDS0_TX2_N

F28

DP1_3_P/TMDS0B_TXC_P

G28

DP1_3_N/TMDS0B_TXC_N

E28

DP1_2_P/TMDS0_TX3_P

D28

DP1_2_N/TMDS0_TX3_N

A28

DP1_1_P/TMDS0_TX4_P

A29

DP1_1_N/TMDS0_TX4_N

C28

DP1_0_P/TMDS0_TX5_P

B28

DP1_0_N/TMDS0_TX5_N

H26

HPLUG_DET0/GPIO_20

J26

HPLUG_DET1/GPIO_21

J25

HPLUG_DET2/GPIO_22

L28

DDC_CLK2/DP_AUX_CH0_P

K28

DDC_DATA2/DP_AUX_CH0_N

K25

DDC_CLK3/DP_AUX_CH1_P

K26

DDC_DATA3/DP_AUX_CH1_N

M23

+3.3V_PLL_DP0_1

N22

+3.3V_PLL_DP0_2

N21

+3.3V_PLL_USB_1

M22

+3.3V_PLL_USB_2

N23

+VIO_PLL_IFPAB_1

L24

+VIO_PLL_IFPAB_2

M25

+VIO_PLL_CORE_LEG

N25

+VIO_PLL_SPPLL0_1

L26

+VIO_PLL_SPPLL0_2

M26

+VIO_PLL_V

N24

+VIO_PLL_NV_1

L25

+VIO_PLL_NV_2

A22

+VDD_IFPA

A23

+VDD_IFPB

A26

+VIO_DP0_1

B26

+VIO_DP0_2

C26

+VIO_DP0_3

U1400

MCP89M-A01

FBGA

(5 OF 11)

RGB

LCD_BKL_CTL/GPIO_57

LCD_PANEL_PWR/GPIO_58

DDC_CLK0/GPIO_38

DDC_DATA0/GPIO_39

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC
RGB_DAC_VSYNC

IFPA_TXC_P
IFPA_TXC_N

IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N

FLAT PANEL

IFPB_TXD7_P
IFPB_TXD7_N

DDC_CLK1/GPIO_40

DDC_DATA1/GPIO_41

LCD_BKL_ON/GPIO_59

IFPAB_VPROBE

IFPAB_RSET

TMDS0_VPROBE

TMDS0_RSET

F29
H25

C31
B31
A31

D31
E31

K22
L22

C22
B22
E22
D22
F22
G22
H22
J22

B23
C23

L23
K23
J23
H23
G23
F23
D23
E23

J28
G29

A25
B25
C25

L20

K20

H28

F31

AUD_IP_PERIPHERAL_DET
MIKEY_MIC_LOAD_DET

TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC

=MCP_IFPA_TXC_P
=MCP_IFPA_TXC_N

=MCP_IFPA_TXD_P<0>
=MCP_IFPA_TXD_N<0>
=MCP_IFPA_TXD_P<1>
=MCP_IFPA_TXD_N<1>
=MCP_IFPA_TXD_P<2>
=MCP_IFPA_TXD_N<2>
=MCP_IFPA_TXD_P<3>
=MCP_IFPA_TXD_N<3>

=MCP_IFPB_TXC_P
=MCP_IFPB_TXC_N

=MCP_IFPB_TXD_P<0>
=MCP_IFPB_TXD_N<0>
=MCP_IFPB_TXD_P<1>
=MCP_IFPB_TXD_N<1>
=MCP_IFPB_TXD_P<2>
=MCP_IFPB_TXD_N<2>
=MCP_IFPB_TXD_P<3>
=MCP_IFPB_TXD_N<3>

=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA

(GMUX_INT)
LCD_IG_BKLT_PWM
LCD_IG_BKLT_EN
LCD_IG_PWR_EN

MCP_IFPAB_VPROBE
MCP_IFPAB_RSET

MCP_TMDS0_VPROBE
MCP_TMDS0_RSET

16 56

IN

16

IN

8

8

8

8

8

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

BI

8

OUT

8

OUT

67

OUT

23 74

OUT

23 74

OUT

23 74

OUT

23 74

OUT

RGB DAC Disable:
Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).
Connect +3.3V_RGBDAC pin to GND.

NOTE: No Composite/S-Video/Component Video support on MCP89

Interface Mode
MCP Signal
=MCP_IFPA_TXC_P/N

=MCP_IFPA_TXD_P/N<0>
=MCP_IFPA_TXD_P/N<1>
=MCP_IFPA_TXD_P/N<2>
=MCP_IFPA_TXD_P/N<3>
=MCP_IFPB_TXC_P/N
=MCP_IFPB_TXD_P/N<0>
=MCP_IFPB_TXD_P/N<1>
=MCP_IFPB_TXD_P/N<2>
=MCP_IFPB_TXD_P/N<3>
=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA

LVDS: Power +VDD_IFPx at 1.8V
TMDS: Power +VDD_IFPx at 3.3V

TMDS/HDMI
TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
(UNUSED)
(UNUSED)
TMDS_IG_TXD_P/N<3>
TMDS_IG_TXD_P/N<4>
TMDS_IG_TXD_P/N<5>
(UNUSED)
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA

LVDS
LVDS_IG_A_CLK_P/N

LVDS_IG_A_DATA_P/N<0>
LVDS_IG_A_DATA_P/N<1>
LVDS_IG_A_DATA_P/N<2>
LVDS_IG_A_DATA_P/N<3>
LVDS_IG_B_CLK_P/N
LVDS_IG_B_DATA_P/N<0>
LVDS_IG_B_DATA_P/N<1>
LVDS_IG_B_DATA_P/N<2>
LVDS_IG_B_DATA_P/N<3>
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA

D

C

B

DDC Mode Pull-downs

NOTE: DP_AUX_CH1 also requires pull-downs if used for
dual-mode DisplayPort (DP++). If unused no pulls
are necessary, if used for TMDS/HDMI only then
only pull-ups are necessary.

100K
100K

1 2
1 2

5%
5%

1/16W

MF-LF

MF-LF

1/16W

DP_IG_AUX_CH0_P

402

DP_IG_AUX_CH0_N

402

8

16

8

16

R1710
R1711

A

GPIO Pull-Ups

=PP3V3_S0_MCP_GPIO

10K

R1780
R1781
R1782

10K
10K

1 2
1 2
1 2

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

7

17 18

MF-LF

1/16W

5%
5%
5%

1/16W
1/16W

MF-LF
MF-LF

SATARDRVR_A_EN

402

AUD_IP_PERIPHERAL_DET

402

MIKEY_MIC_LOAD_DET

402

16 36

16 56

16

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Graphics

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/05/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

17 OF 109

SHEET

16 OF 80

36

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

SATA_HDD_R2D_C_P

36 74

OUT

SATA_HDD_R2D_C_N

36 74

OUT

SATA_HDD_D2R_N

36 74

IN

SATA_HDD_D2R_P

36 74

D

=PP3V3_S0_MCP_GPIO

7

16 18

1

R1800

100K

5%
1/16W
MF-LF

R1810

49.9

1/16W
MF-LF

402

2

1

1%

402

2

C

MXM_GOOD_L

=PP3V3_ENET_MCP_RMGT

7

19 22

B

1

R1811

49.9

1%
1/16W
MF-LF

402

2

IN

SATA_ODD_R2D_C_P

36 74

OUT

SATA_ODD_R2D_C_N

36 74

OUT

SATA_ODD_D2R_N

36 74

IN

SATA_ODD_D2R_P

36 74

IN

TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN

TP_SATA_C_D2RN
TP_SATA_C_D2RP

TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN

TP_SATA_D_D2RN
TP_SATA_D_D2RP

74

MCP_SATA_TERMP

1

R1805

2.49K

1%
1/16W
MF-LF
402

2

ENET_RXD<0>

8

76

IN

ENET_RXD<1>

8

76

IN

ENET_RXD<2>

8

76

IN

ENET_RXD<3>

8

76

IN

ENET_CLK125M_RXCLK

8

76

IN

ENET_RX_CTRL

8

76

IN

ENET_ENERGY_DET

31

IN

PP3V3_ENET_MCP_PLL_MAC

22

20 mA

76

MCP_MII_COMP_VDD

76

MCP_MII_COMP_GND

AH4

SATA_A0_TX_P

AH5

SATA_A0_TX_N

AJ4

SATA_A0_RX_N

AJ5

SATA_A0_RX_P

AJ3

SATA_A1_TX_P

AJ2

SATA_A1_TX_N

AH2

SATA_A1_RX_N

AH3

SATA_A1_RX_P

AJ6

SATA_B0_TX_P

AJ7

SATA_B0_TX_N

AH7

SATA_B0_RX_N

AH6

SATA_B0_RX_P

AL4

SATA_B1_TX_P

AL3

SATA_B1_TX_N

AL1

SATA_B1_RX_N

AL2

SATA_B1_RX_P

AH1

SATA_LED*/GPIO_30

AJ1

SATA_TERMP

G4

NC_1

NC

E7

NC_2

NC

F7

NC_3

NC

F4

NC_4

NC

B14

RGMII_RXD0

C14

RGMII_RXD1

D16

RGMII_RXD2

F16

RGMII_RXD3

E16

RGMII_RXCLK

A14

RGMII_RXCTL

H14

RGMII_INTR/GPIO_35

M16

+3.3V_PLL_MAC_DUAL

D13

RGMII_COMP_VDD

E13

RGMII_COMP_GND

Internal MAC Disable:
Connect RGMII_RXD<0:3> together to 10K pull-down.

Connect RGMII_RXCLK to 10K pull-down.
Connect RGMII_RXCTL to 10K pull-down.
Connect RGMII_INTR to 10K pull-down (if not used as GPIO).
+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail.
RGMII_COMP_VDD/_GND must remain connected as shown.
Connect RGMII_VREF to 10K pull-down.
Connect RGMII_MDIO to 10K pull-down.
All other pins can be left TP or NC.

(6 OF 11)

USB

SATA

Internal 19.5K Pull-Downs on all USB pairs

USB JTAG in S3/S4/S5.

Only USB8-11 support nV

USB_OC0*/GPIO_25

USB_OC1*/GPIO_26
USB_OC2*/GPIO_27_MGPIO_0
USB_OC3*/GPIO_28_MGPIO_1

USB_RBIAS_GND

RGMII_TXCLK
RGMII_TXCTL

LAN

RGMII_RESET*

USB0_N
USB0_P

USB1_P
USB1_N

USB2_P
USB2_N

USB3_P
USB3_N

OHCI0/EHCI0OHCI1/EHCI1

USB4_P
USB4_N

USB5_P
USB5_N

USB6_P
USB6_N

USB7_P
USB7_N

USB8_P
USB8_N

USB9_P
USB9_N

USB10_P
USB10_N

USB11_N
USB11_P

RGMII_VREF

RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3

RGMII_MDC

RGMII_MDIO

BUF_25MHZ

External A

C20
B20

J20
H20

C19
B19

G20
F20

E20
D20

E19
D19

G19
F19

J17
H17

J19
H19

C17
B17

E17
D17

G17
F17

A17
L17
K17
K19

L19

C13

G13
H13
F14
D14

G14
E14

F13
K13

J13

J14

USB_EXTA_N
USB_EXTA_P

AirPort (PCIe Mini-Card)

USB_MINI_P
USB_MINI_N

T57

NC_USB_T57_P
NC_USB_T57_N

External C

USB_EXTC_P
USB_EXTC_N

Watermelon

USB_WM_P
USB_WM_N

Camera/External E

USB_CAMERA_P
USB_CAMERA_N

SD Card/ExpressCard

USB_SDCARD_P
USB_SDCARD_N

External D

USB_EXTD_P
USB_EXTD_N

Geyser Trackpad/Keyboard

USB_TPAD_P
USB_TPAD_N

External B

USB_EXTB_P
USB_EXTB_N

IR

USB_IR_P
USB_IR_N

Bluetooth

USB_BT_N
USB_BT_P

75

MCP_USB_RBIAS_GND

MCP_RGMII_VREF

TP_ENET_TXD<0>
TP_ENET_TXD<1>
TP_ENET_TXD<2>
TP_ENET_TXD<3>

TP_ENET_CLK125M_TXCLK
TP_ENET_TX_CTRL

TP_ENET_MDC
ENET_MDIO

TP_MCP_CLK25M_BUF0_R

TP_ENET_RESET_L

37 75

BI

37 75

BI

8

75

BI

8

75

BI

BI
BI

8

75

BI

8

75

BI

8

75

BI

8

75

BI

29 75

BI

29 75

BI

30 75

BI

30 75

BI

8

75

BI

8

75

BI

47 75

BI

47 75

BI

37 75

BI

37 75

BI

38 75

BI

38 75

BI

29 75

BI

29 75

BI

8

IN

BI

R1850

8.2K

1/16W
MF-LF

8

76

1

R1851

8.2K

5%
1/16W
MF-LF
402

2

1

R1852

5%

402

2

8.2K

1/16W
MF-LF

1

R1853

8.2K

2

1

5%

402

2

1

R1860

887

2

=PP3V3_S5_MCP_GPIO

5%
1/16W
MF-LF
402

USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
USB_EXTD_OC_L

OC2# Also for EXTE
OC3# Also for EXCARD

1%
1/16W
MF-LF
402

37

37

7

18

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP SATA, USB & Ethernet

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

BRANCH

PAGE

18 OF 109

SHEET

17 OF 80

A.13.0

36

345678

2 1

=PP3V3R1V5_S0_MCP_HDA

8

D

C

HDA Output Caps

For EMI Reduction on HDA interface

HDA_SDOUT_R
HDA_BIT_CLK_R

HDA_RST_R_L
HDA_SYNC_R

B

C1950

10PF

CERM

1

5%

50V
402

C1952

2

1

C1951

10PF

2

5%
50V
CERM
402

10PF

CERM

1

5%

50V

2

402

1

C1953

10PF

5%
50V

2

CERM
402

GPIO Pull-Ups/Downs

=PP3V3_S5_MCP_GPIO
=PP3V3_S3_MCP_GPIO
=PP3V3_S0_MCP_GPIO

PCIE_RESET_L

R1980
R1981
R1999
R1986

R1983
R1984
R1985
R1987

R1988
R1989
R1990

A

R1991
R1992

R1993
R1994
R1995

R1996
R1997
R1998

10K

10K
100K
100K

10K

10K
100K
100K

10K

10K

10K

10K
100K

100K
100K
100K

10K
100K

20K

1 2
1 2

1 2

1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2

1 2

1 2

22

70 mA

LPC_AD<0>

39 41 75

BI

LPC_AD<1>

39 41 75

BI

LPC_AD<2>

39 41 75

BI

LPC_AD<3>

39 41 75

BI

NOTE: MCP89 A01 has strong (~10K)
pull-downs on these pins.

18 75

18 75

18 75

18 75

17

7

7

7

16 17 18

15 24

5%
5%
5%
5%

5%
5%
5%
5%

5% 402
5%
5%

5% 402

5%

5%

5% 402

MF-LF

1/16W

MF-LF

1/16W
1/16W MF-LF

MF-LF1/16W

1/16W MF-LF
1/16W MF-LF
1/16W MF-LF
1/16W

MF-LF

MF-LF1/16W

1/16W

MF-LF
1/16W MF-LF
1/16W MF-LF

1/16W MF-LF
1/16W MF-LF
1/16W MF-LF

MF-LF1/16W

1/16W

MF-LF

1/16W

MF-LF

MF-LF1/16W

R1910
R1911
R1912
R1913

PP3V3_G3_RTC

7

19 22

SDCARD_RESET

402

T57_RESET

402

GFXVCORE_PWR_EN

402

SPIROM_USE_MLB

402

MCP_CPU_VTT_EN_L

402

MLB_RAM_VENDOR

402

T57_PWR_EN

402

LPCPLUS_GPIO

402

ODD_PWR_EN_L
MEM_EVENT_L

402

ENET_LOW_PWR

402

SMC_IG_THROTTLE_L

4025%

MCP_VID<0>

4025%

MCP_VID<1>

4025%

MCP_VID<2>

4025%

MCP_VID<3>
AP_PWR_EN

402

ARB_DETECT_L

402

SPI_MISO

22
22

R1920

49.9K

1/16W
MF-LF

1%

402

R1900

49.9

1/16W
MF-LF

1 2
1 2
1 2
1 2

121

2

1

1%

402

2

5%
5%
5%221/16W MF-LF
5%221/16W MF-LF

R1921

49.9K

1%
1/16W
MF-LF
402

18 30

6

18

18 21

6

18 41 50

18

18

6

18

18 41

18 36

18 25 26 39

8

18 31

18 40

18 62

18 62

18 62

18 62

18 29 65

18

6

18 41 75

1/16W MF-LF

MF-LF1/16W

HDA_SDIN0

51 75

IN

AUD_IPHS_SWITCH_EN

56

OUT

Output limited to +VDD_HDA.
Confirmed OK for this signal.

MCP_HDA_PULLDN_COMP

75 18 75

LPC_AD_R<0>

402

LPC_AD_R<1>

402

LPC_AD_R<2>

402

LPC_AD_R<3>

402

TP_MLB_RAM_SIZE

PM_CLKRUN_L

39 41 24 75

IN

SMC_WAKE_SCI_L

39

IN

PM_LATRIGGER_L

12

OUT

AUD_I2C_INT_L

56

IN

SMC_RUNTIME_SCI_L

39

IN

PM_PWRBTN_L

39

IN

PM_SYSRST_DEBOUNCE_L

24

IN

RTC_RST_L

PM_RSMRST_L

39

IN

MCP_PS_PWRGD

24

IN

MCP_WAKE_REQ_L

40

OUT

PM_BATLOW_L

39

IN

MCP_MEM_VDD_EN

20 65

OUT

MCP_MEM_VTT_EN

20

OUT

SM_INTRUDER_L

SMC_IG_THROTTLE_L

18 40

OUT

T57_RESET

6

18

OUT

GFXVCORE_PWR_EN

18 21

OUT

SPIROM_USE_MLB

6

18 41 50

BI

JTAG_MCP_TDI

12

IN

JTAG_MCP_TDO

12

OUT

JTAG_MCP_TMS

12

IN

JTAG_MCP_TRST_L

12

IN

JTAG_MCP_TCK

12

IN

MCP_CLK25M_XTALIN

24

IN

MCP_CLK25M_XTALOUT

24

OUT

RTC_CLK32K_XTALIN

24

IN

RTC_CLK32K_XTALOUT

24

OUT

121

R1930

10K

5%
1/16W
MF-LF

402

D6

70 mA

R1931

100K

5%
1/16W
MF-LF
402

2

+VDD_HDA

E2

HDA_SDATA_IN0

(IPD)

E3

HDA_SDATA_IN1/GPIO_2

(IPD)

D3

HDA_PULLDN_COMP

K1

LPC_AD0

L1

LPC_AD1

L2

LPC_AD2

L3

LPC_AD3

K2

LPC_DRQ0*/GPIO_43

(IPU)

L6

LPC_CLKRUN*/GPIO_42

D11

SIO_PME*/GPIO_31

G11

EXT_SMI*/GPIO_32

B3

A20GATE/GPIO_55

H2

KBRDRSTIN*/GPIO_56

J10

PWRBTN*

F10

RSTBTN*

G16

RTC_RST*

C11

PWRGD_SB

C2

PWRGD

H16

MCP_WAKE_REQ*

A7

MCP_WAKE_DIS*

(IPU-S5)

B7

MCP_MEMVDD_EN/GPIO_44

G10

MEMVTT_EN/GPIO_45

J16

INTRUDER*

G5

MGPU_PIO0/GPIO_6

H5

MGPU_PIO1/GPIO_7

H10

MGPU_PIO2/GPIO_23

J11

MGPU_PIO3/GPIO_24

C10

JTAG_TDI

D10

JTAG_TDO

B10

JTAG_TMS

E10

JTAG_TRST*

A10

JTAG_TCK

A11

XTALIN

B11

XTALOUT

B16

XTALIN_RTC

C16

XTALOUT_RTC

Platform-Specific Connections

LPC_RESET_L

IN

PM_SLP_S4_L

6

18 39 40 65 39

IN

MAKE_BASE=TRUE

NOTE: MCP SLP_S5# signal has the
behavior of Intel’s SLP_S4# signal.

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

(IPU)
(IPU)
(IPU)
(IPU)

(IPU-S5)
(IPU-S5)

(IPU)

(IPU)

(IPD)

OMIT

U1400

MCP89M-A01

FBGA

(7 OF 11)

HDA

(IPU)

(IPU-S5)

MISC_VDDEN0/GPIO_47
MISC_VDDEN1/GPIO_48

(IPU)

MISC_VDDEN2/GPIO_17
MISC_VDDEN3/GPIO_18
MISC_VDDEN4/GPIO_19
MEM_VDD_SEL/GPIO_46

FANRPM0/GPIO_60/MGPIO_2

FANRPM1/GPIO_63/MGPIO_3

MISC LPC

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

BUF_SIO_CLK/GPIO_33

R1965

33

1 2

5%
1/16W
MF-LF

402

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET*

HDA_SYNC

LPC_SERIRQ

(IPU)

LPC_FRAME*

LPC_RESET*

(IPD)

LPC_CLK0

FANCTL0/GPIO_61

FANCTL1/GPIO_62

(IPD)

SLP_S3*

SLP_RMGT*

(IPD)

SLP_S5*

(IPD)

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15
MCP_VID3/GPIO_16

SPI_CS0*/GPIO_10

SPI_CLK/GPIO_11

SPI_DI/GPIO_08
SPI_DO/GPIO_09

SPKR/GPIO_1

THERM_DIODE_P
THERM_DIODE_N

SMB_CLK0

SMB_DATA0

SUS_CLK/GPIO_34

TEST_MODE_EN

PKG_TEST

PKG_TEST2

LPC_PWRDWN_L

PM_SLP_S5_L

E1

E4

D1

D2

L8

L7

K7

L5

K10
C8
A8
D8
G8
C7

H7
H6
G6
H4

C4
K9
D5

K3
K4
K5
K6

E11
D7
F11
B8

H3

G3
G2

A4
B4
A5
B5
C5

H1

H11

D4
L16
K16

=PP3V3_S0_MCP_GPIO

2

R1961

10K

5%
1/16W
MF-LF
402

1

HDA_SDOUT_R

18 75

18 75

HDA_BIT_CLK_R

18 75

HDA_RST_R_L

HDA_SYNC_R

LPC_SERIRQ

LPC_FRAME_R_L

LPC_RESET_L
LPC_CLK33M_SMC_R

MCP_CPU_VTT_EN_L
MLB_RAM_VENDOR
T57_PWR_EN
SMC_ADAPTER_EN
LPCPLUS_GPIO
MCP_MEM_VDD_SEL_1V5

ODD_PWR_EN_L
MEM_EVENT_L
ENET_LOW_PWR
SDCARD_RESET

PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
MCP_VID<3>

SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R

MCP_SPKR
MCP_THMDIODE_P

MCP_THMDIODE_N
SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN

ARB_DETECT_L
PM_CLK32K_SUSCLK_R

7

16 17 18

R1951

22

1 2

5%
1/16W
MF-LF

402

R1953

22

1 2

5%
1/16W
MF-LF

402

18

18

BI

IN

BI

OUT

OUT

IN

OUT

IN

OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

IN

OUT

OUT
OUT

OUT

BI

OUT

BI

OUT

18

OUT

R1950

22

1 2

5%
1/16W
MF-LF

402

R1952

22

1 2

5%
1/16W
MF-LF

402

R1960

22

1 2

5%
1/16W
MF-LF

402

6

18

39 40 65

18 41

60

18 36

18 25 26 39

8

18 31

18 30

6

39 65 69

65

6

18 39 40 65

18 62

18 62

18 62

18 62

41 75

41 75

6

18 41 75

41 75

45 79

45 79

12 42 75

12 42 75

42 75

42 75

18 29 65

24 75

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

HDA_SYNC

LPC_FRAME_L

NOTE: MCP89 A01 has
strong (~10K)
pull-downs on
these pins.

OUT

1

R1970

10K

5%
1/16W
MF-LF
402

2

51 75

OUT

51 75

OUT

51 75

OUT

51 75

OUT

39 41

BI

39 41 75

OUT

18 24 75

OUT

OUT

BUF_SIO_CLK Frequency

Frequency

24 MHz

14.31818 MHz

BIOS Boot Select

I/F
LPC
SPI

NOTE: MCP89 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.

SPI Frequency Select

Frequency0SPI_DO

25.0 MHz

31.2 MHz

42.7 MHz

62.5 MHz

NOTE: 42 & 62 MHz use FAST_READ command.

40

MCP_SPKR:
0 = USER mode (Normal boot mode)

1 = SAFE mode (For ROMSIP recovery)
Connects to SMC for automatic recovery.

Straps not provided on this page.

HDA_SYNC

LPC_FRAME#

0
1

SPI_CLK

0
1
1

D

1
0

C

0
1
0
1

B

MCP_TEST_MODE_EN

1

R1959

10K

5%
1/16W
MF-LF
402

2

39 41 18 24 75

OUT

OUT

NO STUFF

1

R1966

10K

5%
1/16W
MF-LF
402

2

1

R1975

1K

1%
1/16W
MF-LF
402

2

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP HDA, LPC & MISC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

19 OF 109

SHEET

18 OF 80

SIZE

A

D

36

NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.

OMIT

U1400

MCP89M-A01

=PP1V05_SW_MCP_FSB

7

22

2000 mA 4300 mA

D

=PP1V05_S0_MCP_FSB

7

13 22

200 mA

C

G32
K29
D32
L29
Y26
V26
P27
T27
J29
N27
P26
F32
A32
H29
W26
U27
G31
C32
E32
M28
H30
U26
T26
H31
B32
R26
N26

W27
W28
Y27
Y28

+VTT_CPU_1
+VTT_CPU_2
+VTT_CPU_3
+VTT_CPU_4
+VTT_CPU_5
+VTT_CPU_6
+VTT_CPU_7
+VTT_CPU_8
+VTT_CPU_9
+VTT_CPU_10
+VTT_CPU_11
+VTT_CPU_12
+VTT_CPU_13
+VTT_CPU_14
+VTT_CPU_15
+VTT_CPU_16
+VTT_CPU_17
+VTT_CPU_18
+VTT_CPU_19
+VTT_CPU_20
+VTT_CPU_21
+VTT_CPU_22
+VTT_CPU_23
+VTT_CPU_24
+VTT_CPU_25
+VTT_CPU_26
+VTT_CPU_27

+VTT_CPU2_1
+VTT_CPU2_2
+VTT_CPU2_3
+VTT_CPU2_4

FBGA

(8 OF 11)

+VDD_MEM_1
+VDD_MEM_2
+VDD_MEM_3
+VDD_MEM_4
+VDD_MEM_5
+VDD_MEM_6
+VDD_MEM_7
+VDD_MEM_8

+VDD_MEM_9
+VDD_MEM_10
+VDD_MEM_11
+VDD_MEM_12
+VDD_MEM_13
+VDD_MEM_14
+VDD_MEM_15
+VDD_MEM_16
+VDD_MEM_17
+VDD_MEM_18
+VDD_MEM_19

POWER I

+VDD_MEM_20
+VDD_MEM_21
+VDD_MEM_22
+VDD_MEM_23
+VDD_MEM_24
+VDD_MEM_25
+VDD_MEM_26
+VDD_MEM_27
+VDD_MEM_28
+VDD_MEM_29
+VDD_MEM_30
+VDD_MEM_31

=PP1V5R1V35_SW_MCP_MEM

AG14
AL7
AF18
AF21
AM1
AM4
AK8
AG13
AF16
AF22
AG20
AM5
AG19
AF23
AJ9
AF19
AG17
AL6
AG16
AH12
AM2
AF15
AM3
AL5
AL8
AF17
AJ11
AJ8
AF14
AJ10
AF20

14 20 22

NOTE: VDD_COREx_SENSE signals should NOT
be used for remote sensing unless
COREA/COREB are powered by separate
regulators.
Instead connect regulator sense point
as close to COREB FET as possible.

=PPVCORE_S0_MCP

7

22

8450 mA (0.85V)

TP_MCP_VDDCOREA_SENSEP
TP_MCP_VDDCOREA_SENSEN

=PP1V05_S0_MCP_PE_DVDD0

7

200 mA (DVDD0 & DVDD1)
(PE0[3:0])

=PP1V05_S0_MCP_PE_DVDD1

7

200 mA (DVDD0 & DVDD1)
(PE0[5:4], PE1[1:0])

=PP1V05_S0_MCP_PE_AVDD0

7

500 mA (AVDD0 & AVDD1)
(PE0[3:0])

=PP1V05_S0_MCP_PE_AVDD1

7

500 mA (AVDD0 & AVDD1)
(PE0[5:4], PE1[1:0])

B

=PP3V3_S0_MCP_HVDD

7

22

30 mA

=PP3V3_S0_MCP

7

22

250 mA

=PP0V9_S5_MCP_VDD_AUXC

7

22

150 mA

PP3V3_G3_RTC

7

18 22

?? uA (G3)
5 mA (S0)

AB22
AB20

R13

T13
R11

AB17

R10

AB18

AB21

AB19

P13

U22
V22
W22
Y22

AA22

P12
P10
P11

L10

AF7
AF8
AE9

AE10

AE6
AE7
AE8

AC13
AB12
AC12
AD11
AD13
AB13

Y12
Y13

AA13

W12
W13

T11
T12
U13

U11
U12

E29

L11
M17
M20

A16

T3

R7
T6

T1
T2

R4

R2
T8
R8
T4
R5
T7
T5
T9

L9

F5

E5

MCP89M-A01

+VDD_COREA_1
+VDD_COREA_2
+VDD_COREA_3
+VDD_COREA_4
+VDD_COREA_5
+VDD_COREA_6
+VDD_COREA_7
+VDD_COREA_8
+VDD_COREA_9
+VDD_COREA_10
+VDD_COREA_11
+VDD_COREA_12
+VDD_COREA_13
+VDD_COREA_14
+VDD_COREA_15
+VDD_COREA_16
+VDD_COREA_17
+VDD_COREA_18
+VDD_COREA_19
+VDD_COREA_20
+VDD_COREA_21
+VDD_COREA_22
+VDD_COREA_23
+VDD_COREA_24
+VDD_COREA_25
+VDD_COREA_26
+VDD_COREA_27
+VDD_COREA_28
+VDD_COREA_29
+VDD_COREA_30
+VDD_COREA_31
+VDD_COREA_32
+VDD_COREA_33

+VDD_COREA_SENSE
GND_COREA_SENSE

+VIO_PE_DVDD0_1
+VIO_PE_DVDD0_2
+VIO_PE_DVDD0_3
+VIO_PE_DVDD0_4

+VIO_PE_DVDD1_1
+VIO_PE_DVDD1_2
+VIO_PE_DVDD1_3

+VIO_PE_AVDD0_1
+VIO_PE_AVDD0_2
+VIO_PE_AVDD0_3
+VIO_PE_AVDD0_4
+VIO_PE_AVDD0_5
+VIO_PE_AVDD0_6

+VIO_PE_AVDD1_1
+VIO_PE_AVDD1_2
+VIO_PE_AVDD1_3
+VIO_PE_AVDD1_4
+VIO_PE_AVDD1_5

+3.3V_HVDD_1
+3.3V_HVDD_2
+3.3V_HVDD_3

+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5

+VDD_DUAL_AUXC_1
+VDD_DUAL_AUXC_2
+VDD_DUAL_AUXC_3

+3.3V_VBAT

OMIT

U1400

FBGA

(9 OF 11)

POWER II

+VDD_COREB_SENSE

+VIO_SATA_AVDD_1
+VIO_SATA_AVDD_2
+VIO_SATA_AVDD_3
+VIO_SATA_AVDD_4
+VIO_SATA_AVDD_5

+VIO_SATA_DVDD_1
+VIO_SATA_DVDD_2
+VIO_SATA_DVDD_3
+VIO_SATA_DVDD_4
+VIO_SATA_DVDD_5
+VIO_SATA_DVDD_6
+VIO_SATA_DVDD_7
+VIO_SATA_DVDD_8

+VIO_SATA_DVDD_9
+VIO_SATA_DVDD_10
+VIO_SATA_DVDD_11
+VIO_SATA_DVDD_12

+VDD_DUAL_RMGT_1

+VDD_DUAL_RMGT_2

+3.3V_DUAL_RMGT_1
+3.3V_DUAL_RMGT_2

+3.3V_DUAL_USB_1

+3.3V_DUAL_USB_2

+VDD_COREB_1
+VDD_COREB_2
+VDD_COREB_3
+VDD_COREB_4
+VDD_COREB_5
+VDD_COREB_6
+VDD_COREB_7
+VDD_COREB_8

+VDD_COREB_9
+VDD_COREB_10
+VDD_COREB_11
+VDD_COREB_12
+VDD_COREB_13
+VDD_COREB_14
+VDD_COREB_15
+VDD_COREB_16
+VDD_COREB_17
+VDD_COREB_18
+VDD_COREB_19
+VDD_COREB_20
+VDD_COREB_21
+VDD_COREB_22
+VDD_COREB_23
+VDD_COREB_24
+VDD_COREB_25
+VDD_COREB_26
+VDD_COREB_27
+VDD_COREB_28
+VDD_COREB_29
+VDD_COREB_30
+VDD_COREB_31
+VDD_COREB_32
+VDD_COREB_33
+VDD_COREB_34
+VDD_COREB_35
+VDD_COREB_36
+VDD_COREB_37
+VDD_COREB_38
+VDD_COREB_39
+VDD_COREB_40
+VDD_COREB_41
+VDD_COREB_42

GND_COREB_SENSE

+3.3V_DUAL_1

+3.3V_DUAL_2

=PPVCORE_SW_MCP_GFX

M4
M2
P4
N12
N4
N14
V20
N10
P3
P1
N11
N6
P6
N2
N9
N8
M10
N3
N1
M5
M7
P2
M8
M11
V19
N7
N16
P5
N5
N13
N15
P9
V17
V18
M14
M13
Y19
Y20
Y17
Y18
P7
P8

U10

TP_MCP_VDDCOREB_SENSEP

T10

TP_MCP_VDDCOREB_SENSEN
PP1V05_S0_MCP_SATA_AVDD

AE1
AE2
AE3
AE4
AE5

=PP1V05_S0_MCP_SATA_DVDD

AF1
AF2
AF3
AF4
AF5
AF6
AF9
AF10
AF11
AE11
AE12
AE13

=PP0V9_ENET_MCP_RMGT

L12
L13

=PP3V3_ENET_MCP_RMGT

A13
B13

=PP3V3_S5_MCP

A20

200 mA

A19

F8

40 mA

E8

345678

15350 mA (0.85V)

300 mA

100 mA

140 mA

300 mA

240 mA

21 23

22

7

7

7

7

22

22

17 22

22

AP21

M37
AM21
AU37
AC27

D18

AD5

AT1
AM30

AT3
AP24
AM33
AE27
AJ24
AH18

AA8
AM18

J32
AJ21
AK35

H15

D33

B18

M32

K18
AN34
AD10

F34

R35

AR9

AA2
AA10

R32
AG29

AP12
AM12
AH21

V32
AR33

AA32
AG34
AK37

K24

K21

AG8

AN5

AD32

AD2

D15

AG2

L15
AK32
AR12
AN35
AN37

B1

J2

C1

B6

B2
E6
J5

V8

H8

J7

J8

V2

2 1

OMIT

U1400

MCP89M-A01

FBGA

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67

(10 OF 11)

GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134

AD7
B12
D12
E12
G12
A2
AL12
AM6
AD37
AG32
H12
AR35
H9
G24
V10
V5
AL30
G7
V29
AP15
AN2
AJ12
AR15
N20
D21
E21
G21
H21
AR27
AM27
AP27
AM15
AA31
AM9
AH24
K12
J31
E30
AK7
V7
M31
AU12
AP6
B37
A36
F35
L27
D35
AL24
AP30
AH15
B21
AV3
AT38
B38
AA21
AD4
A37
AP18
AN4
B24
D30
V4
AA7
AD34
AK4
R37

AU24
AU15

AG5
AD35
AJ18
AL18
AR24

AA5

G18

AU9
AM24

H24

B30
AR21

D24
AU30

AK5

N18

E24

K15

M19
AH27

E18
AA34
AK31

K11
AU21

V34
AL21
AA11

M34

B27

V28

C38

D27

R34

J35
AK34

E15
AR30
AU33

J34
AH30

AU27

AU1
AG10

E27

L21
AU38

H18

B15

AA4
AJ15

L18

G15
AL27
AV37

N19

H27

B9

J4

E9

A3

D9
L4

OMIT

U1400

MCP89M-A01

FBGA

(11 OF 11)
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199

GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217
GND_218
GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226
GND_227
GND_228
GND_229
GND_230

GND

GND_231
GND_232
GND_233
GND_234
GND_235
GND_236
GND_237
GND_238
GND_239
GND_240
GND_241
GND_242
GND_243
GND_244
GND_245
GND_246
GND_247
GND_248
GND_249
GND_250
GND_251
GND_252
GND_253
GND_254
GND_255
GND_256
GND_257
GND_258
GND_259
GND_260
GND_261
GND_262
GND_263
GND_264

E33
M35
AV2
AK2
AU6
F37
C3
J37
V35
G27
AA35
AU18
AR6
AV36
B33
AJ27
G9
AG35
AG7
AD8
AU2
AP9
AD31
V37
AA37
AG37
AL15
AR18
L14
K14
F2
K27
AL9
AB26
M29
G30
R28
R29
R31
U17
K8
Y21
V31
U18
W21
U19
W18
U20
W17
V21
AA28
AA29
N17
AD28
AD29
AG4
W19
W20
AA26
AB27
AA17
AA18
AA19
AA20
U21

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Power & Ground

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/06/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

20 OF 109

SHEET

19 OF 80

36

345678

2 1

D

C2300 helps reduce input rail
droop during Q2300 turn-on.

=PP1V5R1V35_S0_MCPDDRFET

7

=PP5V_S3_MCPDDRFET

7

20

C

MCP_MEM_VDD_EN

18 65

IN

MCPMEM_CNFG

1

R2305

560K

1%
1/16W
MF
402

2

SLG5AP031

2

EN

3

CNFG

U2305

CRITICAL

GND

4

<R1>

Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)

PLACE_NEAR=Q2300.9:2 mm

1

VCC

TDFN

G

S

DONE

THRM

PAD

9

1

C2305

0.1UF

20%
10V

2

CERM
402

5

D

7

MCPMEM_GATE
(G driven to VCC)

6

8

TP_MCPMEM_DONE

CRITICAL

C2300

100UF

CERM-X5R

1206-1

6.3V

1

20%

2

4

G

7

CRITICAL

9

STMFS485NST1G

Q2300

D

DFN

KELVIN

S

SENSE

321 5

8

NC

NC

6

MCPDDRFET_KELVIN

K1

NC

MCPDDRFET_SENSE

PP1V5R1V35_SW_MCP

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5R1V35_SW_MCP_MEM

NV Requirements:

- Min Ramp-Up Time: 20 uS (10% to 90%)

- Max Ramp-Up Time: 65 uS (ENABLE to 90%)

- FET Ron <= 3.8 mOhms

Part
Type
Rds(on)
Loading

(OR 1.35V)

Q2300

STMFS4854N
N-Channel
10 mOhm @3.2V

4.3 A (EDP)

OUT

OUT

4250 mA

44

44

14 19 22

NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.

D

C

Gated Rail Savings: 120mW

DIMM CKE Clamps

CKE must be held low to keep memory in self-refresh.

B

=PP5V_S3_MCPDDRFET

7

20

MCP_MEM_VTT_EN

18

IN

R2350

Q2350

SSM3K15FV

SOD-VESM-HF

1

10K

5%
1/16W
MF-LF

402

G S

1

2

MEMVTT_EN_L

3

D

2

A

CRITICAL

Q2355

NTUD3170NZXXG

SOT-963

G

5

4

G

2

1

CRITICAL

Q2356

NTUD3170NZXXG

SOT-963

G

5

4

G

2

1

D

S

D

S

D

S

D

S

8 7 5 4 2 1

Clamps enable before MCP89 MEMVDD rail switched off.
Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.
Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.
Q2355/Q2356 chosen for low output capacitance.

3

MEM_A_CKE<0>

6

MEM_A_CKE<1>

14 25 73

BI

14 25 73

BI

NO STUBS on CKE signals!

3

MEM_B_CKE<0>

6

MEM_B_CKE<1>

14 26 73

BI

14 26 73

BI

36

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP89 Memory Rail Gating

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

BRANCH

PAGE

23 OF 109

SHEET

20 OF 80

A.13.0

SIZE

B

A

D

345678

2 1

D

C2400 helps reduce input rail
droop during Q2400 turn-on.

=PPVCORE_S0_MCPGFXFET

7

1

2

=PP5V_S0_MCPFSBFET

7

5 6 7 8

1

C

GFXVCORE_PWR_EN

18

IN

MCPGFX_CNFG

1

2

C2406

820PF

10%
50V
CERM
402

2

3

VCC

U2405

SLG5AP033

TDFN

EN

CRITICAL

CNFG

GND

4

THRM

PAD

DONE

9

1

2

5

D

7

G

6

S

8

C2405

0.1UF

20%
10V
CERM
402

MCPGFX_GATE
(G driven to VCC)

TP_MCPGFX_DONE

4

G

<C1>

Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)

CRITICAL

D

Q2400

SI4838BDY

SO-8

S

31 2

NV Requirements:

- Min Ramp-Up Time: 100 uS (10% to 90%)

- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)

- FET Ron <= 2.5 mOhms
NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.

PLACE_NEAR=C2400.1:1 mm

XW2400

SM

CRITICAL

C2400

100UF

20%

6.3V
CERM-X5R
1206-1

1 2

PLACE_NEAR=Q2400.5:2 mm

XW2401

SM

1 2

PLACE_NEAR=C2400.2:1 mm

Part
Type
Rds(on)
Loading

PPVCORE_SW_MCP_GFX

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PPVCORE_SW_MCP_GFX

MCPCORES0_VSEN_P

MCPCORES0_VSEN_N

Q2400

Si4838BDY
N-Channel

3.2 mOhm @2.5V

15.35 A (EDP)

19 23

62 79

OUT

62 79

OUT

D

C

Gated Rail Savings: 860mW

SIZE

B

A

D

B

A

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP89 GFX Core Rail Gating

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

24 OF 109

SHEET

21 OF 80

345678

2 1

MCP Non-GFX Core Power

=PPVCORE_S0_MCP

19

7

8450 mA (0.85V)

1

212

1

2

C2501

4.7UF

20%
4V
X5R
402

1

C2511

0.1UF

20%
10V

2

CERM
402

C2500

10UF

20%

6.3V
X5R

603-1

D

MCP Memory Power

=PP1V5R1V35_SW_MCP_MEM

20 19 14

4300 mA (1.5V)

C2510

4.7UF

20%

4V
X5R
402

1

C2502

1UF

10%
10V

2

X5R
402-1

1

C2512

0.1UF

20%
10V

2

CERM
402

MCP CPU FSB (VTT) Power

=PP1V05_SW_MCP_FSB

19

7

2000 mA

C2520

10UF

6.3V

603-1

20%
X5R

212

1

C2521

4.7UF

20%
4V
X5R
402

1

C2522

1UF

10%
10V

2

X5R
402-1

MCP 0.9V AUX Core Power

=PP0V9_S5_MCP_VDD_AUXC

19

7

1

C

C2526

0.1uF

20%
10V

2

CERM
402

1

C2527

0.1uF

20%
10V

2

CERM
402

MCP 1.05V PCIE Digital Power

=PP1V05_S0_MCP_PE_DVDD

7

200 mA

4.7UF

1

1

C2531

1UF 1UF

20%

4V
X5R
402

10%
10V

2

2

X5R
402-1

1

C2532

10%
10V

2

X5R
402-1

MCP 1.05V Memory DLL Power

=PP1V05_S0_MCP_M2CLK_DLL

14

7

550 mA

4.7UF

1

20%

4V

2

X5R
402

1

C2503

0.22UF

20%

6.3V

2

X5R
402

1

C2513

0.1UF

20%
10V

2

CERM
402

1

1UF

10%
10V

2

X5R
402-1

1

C2533

0.1uF

20%
10V

2

CERM
402

1

C2504

0.1UF

20%
10V

2

CERM
402

1

C2514

0.1UF

20%
10V

2

CERM
402

1

C2534

0.1uF

20%
10V

2

CERM
402

1

C2505

0.1UF

20%
10V

2

CERM
402

1

C2515

0.1UF

20%
10V

2

CERM
402

1

C2506

0.1UF

20%
10V

2

CERM
402

1

C2516

0.1UF

20%
10V

2

CERM
402

1

C2507

0.1UF

20%
10V

2

CERM
402

1

C2517

0.1UF

20%
10V

2

CERM
402

MCP S0 FSB (VTT) Power

=PP1V05_S0_MCP_FSB

19 13

7

200 mA

MCP 0.9V MAC/SMU Power

=PP0V9_ENET_MCP_RMGT

19

7

140 mA150 mA

MCP 1.05V SATA Digital Power

=PP1V05_S0_MCP_SATA_DVDD

19

7

100 mA

1

C2535

0.1uF

20%
10V

2

CERM
402

MCP 3.3V PCIe/SATA I/O PLL Power

=PP3V3_S0_MCP_HVDD

19

7

30 mA

C2524

4.7UF

C2528

4.7uF

C2536C2530

4.7UF

C2541

4.7UF

6.3V
CERM

1

C2508

0.1UF

20%
10V

2

CERM
402

1

C2518

0.1UF

20%
10V

2

CERM
402

1

1

C2525C2523

1UF

20%

4V
X5R
402

20%

4V
X5R
402

20%

4V
X5R
402

20%

603

10%
10V

2

2

X5R
402-1

1

1

C2529

0.1uF

20%
10V

2

2

CERM
402

1

1

C2537

0.1uF

20%
10V

2

2

CERM
402

1

1

C2542C2540

0.1uF

20%
10V

2

2

CERM
402

B

MCP 3.3V I/O Power

=PP3V3_S0_MCP

19

7

250 mA

C2543

4.7uF

6.3V
CERM

20%

603

212

1

C2544

0.1uF

20%
10V
CERM
402

1

C2545

0.1uF

20%
10V

2

CERM
402

1

C2546

0.1uF

20%
10V

2

CERM
402

1

C2547

0.1uF

20%
10V

2

CERM
402

MCP 3.3V AUX/USB Power

=PP3V3_S5_MCP

19

7

240 mA

1

4.7uF

6.3V
CERM

4.7uF

6.3V
CERM

1

C2551

20%

603

0.1uF

20%
10V

2

2

CERM
402

MCP 3.3V MAC PLL Power

=PP3V3_ENET_MCP_PLL_MAC

7

1

1

C2554

20%

603

0.1uF

20%
10V

2

2

CERM
402

20 mA

C2550

MCP 3.3V MAC/SMU Power

=PP3V3_ENET_MCP_RMGT

19 17

A

7

300 mA

C2553

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

MCP 3.3V/1.5V HDA Power

=PP3V3R1V5_S0_MCP_HDA

18

8

70 mA

C2548

4.7UF

MCP 2.0V-3.3V RTC Power

PP3V3_G3_RTC

19 18

7

? uA (G3)
5 mA (S0)

CRITICAL

L2555

FERR-240-OHM-200MA

0402

C2555

4.7UF

6.3V
CERM

21

20%

603

1

1

C2549

20%

6.3V
CERM

603 402

1

2

0.1uF

20%
10V

2

2

CERM

C2552

1

4.7UF

20%

6.3V
2

CERM

603

PP3V3_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2556

0.1UF

20%
10V

2

CERM
402

MCPHVDD:P2V5

8 7 5 4 2 1

1

C2519

0.1UF

20%
10V

2

CERM
402

=PP3V3_S0_MCP_PLL_UF

7

260 mA

1

R2592

10K

5%
1/16W
MF-LF

402

2

17

20 mA

PART NUMBER

353S2971
353S2979
116S0004

L2560

=PP1V05_S0_MCP_AVDD_UF

7

800 mA 500 mA

=PP1V05_S0_MCP_PLL_UF

7

555 mA

PLACE_NEAR=R2570.1:50 mil

PLACE_NEAR=R2575.1:50 mil

PLACE_NEAR=R2580.1:50 mil

=PP3V42_G3H_OPA330

7

MCPHVDD:P3V3

R2593

0

PP3V3_S0_LDO_R

MIN_LINE_WIDTH=0.4 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=3.3V

MF-LF

402

SC70

5

VOUT

4

NC

GND

2

CRITICAL

L2595

220-OHM-2.2A

PLACE_NEAR=R2595.1:50 mil

DESCRIPTION

RES,0402,0,5%,1/16W

MCPHVDD:P2V5

1

C2593

1UF

10%
10V

2

X5R
402

QTY

1
1
1

1 2

CRITICAL

OMIT_TABLE

U2592

MIC5365-2.5V

1

VIN

3

EN

IC,LDO,MIC5365,2.5V,150MA,2%,SC70-5,HFLF

IC,LDO,TPS717,ADJ,150MA,3%,SC70,HFLF

30-OHM-5A

0603

C2560

10UF

L2567

30-OHM-5A

0603

C2567

10UF

CRITICAL

L2570

220-OHM-2.2A

0603

C2570

4.7UF

GND_MCP_PLL_FSB

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=0V

LDO:ADJ

LDO_ADJMCP_PLL_LD0_EN

LDO:ADJ

0603

CRITICAL

L2575

220-OHM-2.2A

0603

C2575

CRITICAL

L2580

220-OHM-2.2A

0603

C2580

HTOL_SENSE:YES

1

C2599

0.1UF

20%

2

10V
CERM
402

1

R2594

10K

5%
1/16W
MF-LF

402

2

1

R2591

10K

5%
1/16W
MF-LF

402

2

21

4.7UF

4.7UF

MCPHVDD:P2V5

1

2

C2595

GND_MCP_PLL_DP_USB

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=0V

REFERENCE DES

21

20%

6.3V
212

X5R

603-1

21

20% 20%

6.3V
212

X5R

603-1

21

1

20%

4V

2

X5R
402

21

1

20%

4V

2

X5R
402

21

1

20%

4V

2

X5R
402

HTOL_SENSE:YES

HTOL_SENSE:YES

C2592

1UF

10%
10V
X5R
402

39

IN

HTOL_SENSE:YES

1

4.7UF

20%

6.3V

2

CERM

603

U2592
U2592
R2596

1

4.7UF

20%
4V
X5R
402

1

C2568

4.7UF

4V
X5R
402

R2570

0.33

1 2

5%

1/16W

MF

0402

R2597

1K

1%
1/16W
MF-LF

402

=PP3V3_S0_OPA333

7

R2596

1K

1 2

CRITICAL

1%

1/16W

Q2592

MF-LF

NTZD3152P

402

HTOL_SENSE:YES

S

1

SMC_P10

R2599

100K

5%
1/16W
MF-LF

402

R2595

0.33

1 2

5%

1/16W

MF

0402

CRITICAL

CRITICAL
CRITICAL
CRITICAL

1

C2562C2561

1UF

10%
10V

2

X5R
402-1

MCP 1.05V SATA Analog Power

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2569

0.1UF

20%
10V

2

CERM
402

1

C2571 C2572

0.1UF

20%
10V

2

CERM
402

1

C2576

0.1UF

20%
10V

2

CERM
402

1

C2581

0.1UF

20%
10V

2

CERM
402

1

2

1

2

1

C2577

0.1uF

20%
10V

2

CERM
402

1

C2582

0.1uF

20%
10V

2

CERM
402

SMC_N_MIRROR

2

3

-IN

V-

1

V+

+IN

C2563

1UF

10%
10V
X5R
402-1

0.1uF

20%
10V
CERM
402

4

SC70-5

OPA330

5

U2593

CRITICAL

HTOL_SENSE:YES

HTOL_SENSE:YES

SOT-563-HF

G

2

D

6

1

C2596

0.1UF

20%
10V

2

CERM
402

1

HTOL_SENSE:YES

C2594

2

0.1UF

20%
10V
CERM
402

FERR-240-OHM-200MA

PP3V3_S0_MCP_HVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

MCP 3.3V DP & USB PLL Power

PP3V3_S0_MCP_PLL_DP_USB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2597

0.1uF

20%
10V

2

CERM
402

BOM OPTION

LDO:FIXED

LDO:ADJ

HTOL_SENSE:NO

1

2

300 mA

C2564

0.1UF

20%
10V
CERM
402

1

C2565

0.1UF

20%
10V

2

CERM
402

19

MCP 1.05V CPU/FSB/MEM PLL Power

PP1V05_S0_MCP_PLL_FSBMEM

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2573

0.1UF

20%
10V

2

CERM
402

MCP 1.05V PCIe/SATA PLL Power

PP1V05_S0_MCP_PLL_PEXSATA

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

C2579

1

C2578

0.1UF

20%
10V

2

CERM
402

1

C2583

0.1UF

20%
10V

2

CERM
402

R2590

100K

1 2

1%
1/16W
MF-LF

402

CRITICAL

5

G

SMC_P_FOLLOW

L2590

0402

0.1UF

1

20%
10V
CERM
402

2

MCP 1.05V Core/Misc PLL Power

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

C2584

0.1UF

1

20%
10V
CERM
402

2

4

S

HTOL_SENSE:YES

SOT-563-HF

NTZD3152P

Q2592

CRITICAL

D

3

21

C2590

4.7UF

210 mA

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Standard Decoupling

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

MCP 1.05V PCIe Analog Power

PP1V05_S0_MCP_PE_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2566

0.1UF

20%
10V

2

CERM
402

14

70 mA

HTOL_SENSE:YES

CRITICAL

U2594

OPA330

SC70-5

5

1

+IN

V+

3

-IN

SMC_N_FOLLOW

4

V-

2

PP3V3_S0_MCP_PLL_HVDD

1

1

C2591

20%

6.3V
CERM

603

Apple Inc.

R

0.1UF

20%

2

2

10V
CERM
402

15

325 mA

16

160 mA

PLACEMENT_NOTEs:
Place close to SMC

Place close to SMC

(For R and C)

HTOL_SENSE:YES

R2598

4.53K

1 2

1%
1/16W
MF-LF

402

SMC_NB_MISC_ISENSE

HTOL_SENSE:YES

C2598

1

0.22UF

20%

6.3V
X5R

2

402

GND_SMC_AVSS

MCP 3.3V PLL Power

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

SYNC_DATE=08/15/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

25 OF 109

SHEET

22 OF 80

36

7

39

50 mA

D

C

B

OUT

43
39
40
44

15

A

SIZE

D

345678

2 1

MCP GFX Core Power

=PPVCORE_SW_MCP_GFX

19 21

15350 mA (0.85V)

MCP 3.3V RGBDAC Power

PP3V3_S0_MCP_DAC

140 mA

16

D

212

1

C2601

4.7UF

20%
4V
X5R
402

C2600

10UF

6.3V

603-1

20%
X5R

D

1

C2602

1UF

10%
10V

2

X5R
402-1

1

C2603

1UF

10%
10V

2

X5R
402-1

1

C2604

0.22UF

20%

6.3V

2

X5R
402

1

C2605

0.22UF

20%

6.3V

2

X5R
402

1

C2606

0.1UF

20%
10V

2

CERM
402

1

C2607

0.1UF

20%
10V

2

CERM
402

1

C2608

0.1UF

20%
10V

2

CERM
402

1

C2609

0.1UF

20%
10V

2

CERM
402

1

C2610

0.1UF

20%
10V

2

CERM
402

1

C2611

0.1UF

20%
10V

2

CERM
402

1

C2612

0.1UF

20%
10V

2

CERM
402

R2670

1/16W
MF-LF

402

GND_MCP_DAC_P3V3

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

1

VOLTAGE=0V
MAKE_BASE=TRUE

0

5%

If RGBDAC is used, requires ferrite (155S0382)

2

plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap.
If RGBDAC is not used, tie to GND.

MCP 3.3V/1.8V IFP Interface Power

=PP3V3R1V8_S0_MCP_IFP_VDD

7

16

180 mA (1.8V LVDS)

C2620

4.7uF

6.3V
CERM

20%
603

212

1

C2621

0.1uF

20%
10V
CERM
402

MCP 1.05V IFP PLL Power

=PP1V05_S0_MCP_PLL_IFP

7

16

60 mA

C2630

4.7uF

20%
X5R

402

1

1

C2631

0.1uF

4V

20%
10V

2

2

CERM
402

MCP 1.05V DisplayPort Power

=PP1V05_S0_MCP_DP0_VDD

7

16

160 mA

1

C2640

4.7UF

20%
X5R

402

C

MCP_TMDS0_RSET

16 74

MCP_TMDS0_VPROBE

16 74

NO STUFF

C2650

0.1UF

20%
10V

CERM

402

1

C2641

0.1uF

4V

20%
10V

2

2

CERM
402

C

MCP_IFPAB_RSET

16 74

MCP_IFPAB_VPROBE

1

R2650

1

1K

1%
1/16W
MF-LF
402

2

2

16 74

NO STUFF

C2655

0.1UF

20%
10V

CERM

402

NO STUFF

1

R2655

1

1K

1%
1/16W
MF-LF

2

402

2

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

B

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Graphics Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/06/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

26 OF 109

SHEET

23 OF 80

36

345678

2 1

RTC Crystal

R2810

0

1/16W
MF-LF

10M

1 2

1

5%

402

2

1/16W
MF-LF

5%

402

RTC_CLK32K_XTALOUT_R

CRITICAL

Y2810

32.768K

7X1.5X1.4-SM

41

RTC_CLK32K_XTALOUT

18

IN

NO STUFF

R2811

D

RTC_CLK32K_XTALIN

18

OUT

C2810

12pF

1 2

5%

50V

CERM

402

C2811

12pF

1 2

5%

50V

CERM

402

18 75

IN

LPC_RESET_L

MCP 25MHz Crystal

C2815

12pF

1 2

5%

50V

CERM

402

NC

2 4

NC

C2816

12pF

1 2

5%

50V

CERM

402

15 18

IN

MAKE_BASE=TRUE

PCIE_RESET_L

18

IN

18

OUT

MCP_CLK25M_XTALOUT

MCP_CLK25M_XTALIN

NO STUFF

R2816

1/16W
MF-LF

R2815

0

1 2

1

1M

5%

402

2

1/16W
MF-LF

5%

402

MCP_CLK25M_XTALOUT_R

CRITICAL

Y2815

25.0000M

SM-3.2X2.5MM

31

Caesar II (ENET) 25MHz Crystal

R2820

C

BCM5764_CLK25M_XTALO

31

IN

BCM5764_CLK25M_XTALI

31

OUT

NO STUFF

R2821

10M

1/16W
MF-LF

200

1 2

1

5%

402

2

1/16W
MF-LF

5%

402

BCM5764_CLK25M_XTALO_R

CRITICAL

Y2820

25.0000M

SM-3.2X2.5MM

31

C2820

27pF

1 2

5%

50V

CERM

402

NC

2 4

NC

C2821

27pF

1 2

5%

50V

CERM

402

Platform Reset Connections

LPC Reset (Unbuffered)

R2881

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

PCIE Reset (Unbuffered)

33

1 2

5%
1/16W
MF-LF

402

R2893

0

1 2

5%
1/16W
MF-LF

402

R2895

0

1 2

5%
1/16W
MF-LF

402

R2883

33

1 2

5%
1/16W
MF-LF

402

R2891

0

1 2

5%
1/16W
MF-LF

402

R2894

0

1 2

5%
1/16W
MF-LF

402

R2892

0

1 2

5%
1/16W
MF-LF

402

LPCPLUS_RESET_L

SMC_LRESET_L

=FW_RESET_L

PCA9557D_RESET_L

BKLT_PLT_RST_L

AP_RESET_L

SDCARD_PLT_RST_L

ENET_RESET_L

41

OUT

D

39

OUT

34

OUT

28

OUT

71

OUT

29

OUT

30

OUT

31 76

OUT

C

R2825

18 75

IN

LPC_CLK33M_SMC_R

PLACEMENT_NOTE=Place close to U1400

Ethernet WAKE# Isolation

B

Q2830

SSM3K15FV

SOD-VESM-HF

PCIE_WAKE_L

6

15 29

OUT

D

3

1

GS

2

=PP3V3_ENET_PHY

1

R2830

10K

5%
1/16W
MF-LF
402

2

ENET_WAKE_L

MAKE_BASE=TRUE

7

31 64

=ENET_WAKE_L

PM_CLK32K_SUSCLK_R

18 75

IN

31

IN

PLACEMENT_NOTE=Place close to U1400

33

1 2

5%
1/16W
MF-LF

402

R2829

22

1 2

5%
1/16W
MF-LF

402

R2826

33

1 2

5%
1/16W
MF-LF

402

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

PLACEMENT_NOTE=Place close to U1400

PM_CLK32K_SUSCLK

39 75

OUT

41 75

OUT

B

39 75

OUT

MCP S0 PWRGD & CPU_VLD

=PP3V3_S5_MCPPWRGD

7

1

C2850

0.1UF

20%
10V

2

U2850

5

Y

3

CERM
402

74LVC1G08GW

SOT353

4

MCP_PS_PWRGD

18

OUT

A

39 65

IN

61

IN

ALL_SYS_PWRGD

VR_PWRGOOD_DELAY

1

B

2

A

PM_SYSRST_L

39

IN

XDP_DBRESET_L

9

12 18

IN

PLACEMENT_NOTE=Place R2897 on BOTTOM

8 7 5 4 2 1

System Reset Circuit

XDP

R2896

0

1 2

5%
1/16W
MF-LF

R2897

402

SILK_PART=SYS RST

OMIT

1/16W
MF-LF

R2899

1 2

1

0

5%

402

2

10K pull-up to 3.3V S0 inside MCP

1/16W
MF-LF

33

5%

402

PM_SYSRST_DEBOUNCE_L

NO STUFF

1

C2899

1UF

10%
10V

2

X5R
402

SIZE

A

D

OUT

SYNC_MASTER=T27_MLB

PAGE TITLE

SB Misc

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

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