Apple K6 Schematic

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

3456

ECNREV

DESCRIPTION OF REVISION

12

CK
APPD

DATE

2010-03-18

SCHEMATIC,MLB

D

(.csa)

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

10

TABLE_TABLEOFCONTENTS_ITEM

11

TABLE_TABLEOFCONTENTS_ITEM

12

TABLE_TABLEOFCONTENTS_ITEM

13

C

B

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

1

1
2
3
4
5
6
7
8
9

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

BOM Configuration

5

Revision History

7

FUNC TEST

8

Power Aliases

9

SIGNAL ALIAS

10

CPU FSB

11

CPU Power & Ground

12

CPU Decoupling

13

eXtended Debug Port (mini-XDP)

14

MCP CPU Interface

15

MCP Memory Interface

16

MCP PCIe Interfaces

17

MCP Graphics

18

MCP SATA, USB & Ethernet

19

MCP HDA, LPC & MISC

20

MCP Power & Ground

23

MCP89 Memory Rail Gating

24

MCP89 GFX Core Rail Gating

25

MCP Standard Decoupling

26

MCP Graphics Support

28

SB Misc

29

DDR3 SO-DIMM Connector A

31

DDR3 SO-DIMM Connector B

32

DDR3 BYTE/BIT SWAPS-K6

33

FSB/DDR3 Vref Margining

34

RIGHT CLUTCH CONNECTOR

35

SecureDigital Card Reader

39

Ethernet PHY (Caesar II/IV)

40

Ethernet Connector

41

FireWire LLC/PHY (FW643E)

42

FireWire Port & PHY Power

43

FireWire Connector

45

SATA Connectors

46

External USB Connectors

48

Internal USB Support

49

SMC

50

SMC Support

51

LPC+SPI Debug Connector

52

K6 SMBUS CONNECTIONS

53

Voltage Sensing

54

Current Sensing

55

Thermal Sensors

Contents

PVT, 3/18/10

Date

Sync

K17_MLB

K69_MLB

K69_MLB

K24_MLB

K24_MLB

K24_MLB

K24_MLB

K24_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

K18_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

05/20/2009

08/19/2009

08/19/2009

07/20/2009

07/20/2009

07/20/2009

07/22/2009

07/20/2009

08/27/2009

07/20/2009

11/23/2009

07/28/2009

11/05/2009

08/06/2009

11/05/2009

11/05/2009

11/23/2009

11/23/2009

08/06/2009

11/23/2009

11/23/2009

08/15/2009

08/06/2009

07/28/2009

07/28/2009

07/28/2009

06/19/2009

09/29/2009

07/28/2009

09/30/2009

08/20/2009

07/28/2009

07/20/2009

12/15/2009

07/28/2009

08/06/2009

08/27/2009

08/27/2009

09/02/2009

09/02/2009

08/27/2009

08/21/2009

08/27/2009

09/30/2009

08/27/2009

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

47
48
49

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

(.csa)

56

Fan46

57

WELLSPRING 1

58

WELLSPRING 2

59

Sudden Motion Sensor (SMS)

61

SPI ROM50

62

AUDIO: CODEC/REGULATOR

63

AUDIO: LINE INPUT FILTER

65

AUDIO: HEADPHONE FILTER

66

AUDI0: SPEAKER AMP

67

AUDIO: JACK

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

72

5V/3.3V SUPPLY

73

1.5V/1.35V LVDDR3 Supply

74

IMVP6 CPU VCore Regulator

75

MCP VCore Regulator

76

CPU VTT(1.05V) SUPPLY

77

Misc Power Supplies

78

Power Sequencing

79

Power FETs

90

LVDS CONNECTOR

93

DISPLAYPORT SUPPORT

94

DisplayPort Connector

97

LCD Backlight Driver

98

LCD Backlight Support

100

CPU/FSB Constraints

101

Memory Constraints

102

MCP Constraints 1

103

MCP Constraints 2

104

Ethernet Constraints

105

FireWire Constraints

106

SMC Constraints

108

K6/K69 Specific Constraints

109

K6/K69 PCB Rule Definitions

Contents

K24_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

K24_MLB

T27_MLB

K24_MLB

T27_MLB

K24_MLB

T27_MLB

K24_MLB

T27_MLB

T27_MLB

T27_MLB

K24_MLB

K69_MLB

K24_MLB

K69_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

T27_MLB

Date

SyncPage

07/20/2009

08/15/2009

08/03/2009

07/20/2009

10/21/2009

08/31/2009

07/17/2009

07/17/2009

07/17/2009

08/25/2009

08/27/2009

07/20/2009

07/29/2009

07/20/2009

08/06/2009

07/20/2009

08/18/2009

07/20/2009

09/30/2009

11/24/2009

08/27/2009

07/20/2009

08/12/2009

07/20/2009

08/27/2009

07/28/2009

08/03/2009

08/03/2009

08/03/2009

08/27/2009

11/23/2009

07/20/2009

07/28/2009

09/08/2009

08/06/2009

D

C

B

A

8 7 6 5 4 2 1

3

DRAWING TITLE

SCHEM,MLB_LDO,K6

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

1 OF 109

SHEET

1 OF 80

SIZE

A

D

U1000

INTEL CPU

2.X OR 3.X GHZ
PENRYN

PG 9

J1300

XDP CONN

PG 12

345678

2 1

FSB

MCP

64-Bit

1067/1333 MHz

PCI

MAIN

MEMORY

DDR3-1067/1333MHZ

PG 14

Misc

PG 18

SPI

PG 18

LPC

PG 18

PWR

CTRL

Bluetooth

11
10

9
8
7
6

USB

PG 17

4
3
2

(UP TO 12 DEVICES)

10 5

SMB

PG 18

HDA

PG 18

2 UDIMMs

PG 29

J2900

DIMM

PG 25,26

U6100

SPI

Boot ROM

PG 51

TRACKPAD/

KEYBOARD

U4900

B,0 BSB

SMC

PG 39

J3401

IR

PG 38PG 47 PG30 PG38

CAMERA

J1300

D

PG 10

MAC

PG 17

FSB INTERFACE

NVIDIA

U1400

GPIOs

PG 18

CLK

SYNTH

J4501

SATA
Conn

PG 38

HD

J4500

SATA
Conn

PG 38

C

ODD

J9000

1.05V/3GHZ.

1.05V/3GHZ.

PG 15,18

SATA

PG 17

LVDS
CONN

PG 68

J9400

DISPLAY PORT

CONN

PG 70

J3401

AIR PORT

B

PG 29

LVDS OUT

RGB OUT

DP OUT

HDMI OUT

DVI OUT

TMDS OUT

PG 16

UP TO 20 LANES3

PCI-E

PG 15

J6950,U7000

U5535,U5515

CPU,MCP,TEMP SENSOR

POWER SENSE

J5601

FAN CONN AND CONTROL

Ser

FanADC

Prt

J4600, J4610

EXTERNAL

USB

Connectors

PG 37PG 29

SMB

CONN

PG 12

DC/BATT

PG 58,59

PG 45

PG 50

PG 46

J5100

LPC+SPI Conn

PG 46

J3500U5701J3401 J4890

Card reader

D

POWER SUPPLY

C

J4890

Blue Ray dec

B

U6201

U3900

BMC5764M

J4000

GB

E-NET

PG 31

E-NET

Conn

PG 32

A

J3401

PCI-E

AirPort

PG 29

Line In

Filter

PG 53

HEADPHONE

Filter

PG 54

J6750,6700

8 7 5 4 2 1

Audio
Codec

PG 52

U6880

Audio
Conns

PG 56

Mic
Amp

U6633, U6623, U6613

Speaker

Amps

PG 55PG 53

SIZE

A

D

SYNC_MASTER=K69_MLB

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/19/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

2 OF 109

SHEET

2 OF 80

36

345678

2 1

D

(9 TO 12.6V)

C

B

A

AC

ADAPTER

IN

3S2P

MCP89

PM_SLP_S4_L

PM_SLP_S3_L

DELAY

DELAY

DELAY

DELAY

PP18V5_DCIN_CONN

POWER SYSTEM ARCHITECTURE

Q7080

PPDCIN_G3H_OR_PBUS

J6950

DCIN(16.5V)

PPVBAT_G3H_CONN

F6905

6A FUSE

SMC_DCIN_ISENSE

01

A

R7020

Q7055

CHGR_EN
(S5)

ENABLES

VIN

PBUS SUPPLY/
BATTERY CHARGER

ISL6259

U7000

PPVBAT_G3H_CHGR_R

VOUT

Q7085

PPVBAT_G3H_CHGR_REG

R7050

SMC_BATT_ISENSE

A

01

IMVP_VR_ON_R

8A FUSE

F7040

02

25

CPU VCORE

VIN

ISL9504B

VR_ON

PBUS_VSENSE

PPBUS_G3H

VOUT

PGOOD

U7100

U1400

AP_PWR_EN

11

15

Q7890

11-1

11-3

RC
DELAY

11-2

RC
DELAY

PM_WLAN_EN_L

P3V3S3_EN

DDRREG_EN

P5VS3_EN_L

16

CHGR_BGATE

SMC

P16

U4900

P60

BKLT_EN

PPBUS_G3H

04

SMC_PM_G2_EN

(S5)

02

VIN

LP8545

U9701

ENA

U7840

PPVOUT_SW_LCDBKLT

VOUT

P5VS3_EN_L

05

P3V3S5_EN_L

02

VIN

EN1

(RT)

EN2

TPS51125

U7201

PGOOD1,2

P5V3V3_PGOOD

EN

ISL8009B

U7750

5V

3.3V

VIN

VOUT1

VOUT2

VREG3

VOUT

Q7890,Q7891

PM_SLP_S3_L

RC

RC

RC

RC

PM_SLP_S3_L

P1V8S0_EN

P1V5S0_EN

CPUVTTS0_EN

DDRVTT_EN

MCPCORES0_EN

16-3

16-4

16-6

16-5

SMC_ADAPTER_EN

PBUSVSENSE_EN

(S0)

P5VS0_EN

(S0)

RC

P3V3S0_EN

DELAY

16-1

16-1

16-2

04-1

=DDRREG_EN

=DDTVTT_EN

02

VIN

1.5V

S5
S3

0.75V

TPS51116

U7300

MCPCORES0_EN

VOUT1

VOUT2

02

14

Q7930

MCPDDROUT

MCP_CORE

EN

VIN

ISL9563A

U7500

PP1V5R1V35_SW_MCP

(12A MAX CURRENT)

(1A MAX CURRENT)

PPMCPCORE_S0_R

VOUT

(25A MAX CURRENT)

PP1V5_S3_REG

PP0V75_S0_REG

8 7 5 4 2 1

02

Q5315

V

PBUS_G3H_VSENSE

CPUVTTS0_EN
(S0)

V

SMC_CPU_ISENSE

VR_PWRGOOD_DELAY

PP5V_S3_REG

(13A MAX CURRENT)

PP3V3_S5_REG

(5.5A MAX

PP0V9_S5_REG

21

20

CURRENT)

P3V3S3_EN

P3V3S0_EN

R7525

ENABLE

3.425V G3HOT
LT3470

VOUT

U6990

02

VIN

EN_PSV

VOUT

CPUVTT

(1.05V)

TPS51117

U7600

PGOOD

CPUVTTS0_PGOOD

SMC_CPU_VSENSE

PPVCORE_S0_CPU

(44A MAX CURRENT)

28

Q7910

Q7930

ST1S12G12R

PPMCPCORE_S0_REG

PP3V42_G3H_REG

PP1V05_S0

(8A MAX CURRENT)

1.2V

U7720

1.8V

TPS62202

U7760

1.5V

ISL8009B

U7710

PP1V8_S0_REG

PP1V5_S0_REG

1.05V

TPS7470

U7740

PP1V2_ENET_REG

03

26

Q3450

P3V3ENET_EN_L

PP3V3_S0_FET

PP1V05_S0_MCP_PLL_REG

PP3V3_S0
PP1V5_S0
PP1V05_S0

SMC PWRGD

RN5VD30A-F

U5010

4.5V AUDIO
MAX8840

VIN

U6200

EN

PP3V3_S3_FET

P3V3_S3_WLAN

18

MCPPLLDO_PGOOD

S0PGOOD_RST_L

V1
V2
V3

36

04

PP4V5_AUDIO_ANALOG

VOUT

P1V5S0_PGOOD

P5V3V3_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

RST*

ISL88042

U7870

MCP_PS_PWRGD

U2850

17

07

13

24

ALL_SYS_PWRGD

RSMRST_PWRGD

09

SMC_ONOFF_L

05

MCP89

PWRBTN*

PLTRST*

RSMRST*

PWRGD

29

CPUPWRGD(GPIO49)

CPU_RESET#

U1400

CPU

PWRGOOD

U1000

Q7940

PP5V_S0_FET

P5VS0_EN

SMC

RSMRST_OUT(P15)

SLP_S5_L
SLP_S4_L
SLP_S3_L

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)
SLP_S4_L(P94)
SLP_S3_L(P93)

99ms DLY

IMVP_VR_ON(P16)

PLT_RST*

P17(BTN_OUT)

U4900

SYNC_MASTER=K69_MLB

PAGE TITLE

Power Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

RESET*

RST*

06-1

31

LPC_RESET_L

CPU_PWRGD

30

FSB_CPURST_L

32

PM_RSMRST_L

IMVP_VR_ON_R

PM_PWRBTN_L
SMC_RESET_L

10

25

SYNC_DATE=08/19/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

3 OF 109

SHEET

3 OF 80

SIZE

D

C

B

A

D

345678

2 1

D

C

BOM Variants

BOM NUMBER

639-1120
639-1119
085-1634

BOM NAME

PCBA,MLB_LDO,BETTER,K6

PCBA,MLB_LDO,BEST,K6

K6 MLB_LDO DEVELOPMENT BOM

BOM Groups

BOM GROUP

K6_COMMON

K6_MISC
K6_PROGPARTS
K6_DEVEL:ENG
K6_DEVEL:PVT
K6_DEBUG:ENG
K6_DEBUG:PVT

K6_DEBUG:PROD

COMMON,ALTERNATE,K6_MISC,K6_DEBUG:PROD,KB_BL,K6_PROGPARTS,RDRV:NO,SPI:25MHZ,CPU_CAP:15

DP_ESD,MIKEY,BCM5764M,GL137,ENET_ESD,VFRQ:SLPS3,LVDDR3:YES,MCPPLL_R:REG,S0PGOOD_BJT,BOOST_VOL:LOW,HDA:1.5V

BOOTROM:UNLOCKED,SMC:PROG,IR:PROG,WELLSPRING:PROG

BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,RDRV:IN_DEVEL

LPCPLUS,XDP_CONN

DEVEL_BOM,SMC_DEBUG:YES,XDP

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO

BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO,LPCPLUS,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES

Module Parts

PART NUMBER

337S3769
337S3680
337S3756
337S3761
337S3797 CRITICAL
337S3866

QTY

1
1
1
1
1
1

1
1

338S0753
353S2896

1
1

DESCRIPTION

PDC,SLGVT,PRQ,2.26,25W,1066,R0,3M,BGA,P7550

PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA

PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA

PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA

IC,MCP89M-A01,31X31MM,BGA1168

IC,MCP89M-A01,31X31MM,BGA1168

IC,1MBIT,SPI FLASH,K17/18

IC,ASIC,BCM5764M,ENET CONTROLLER, 8x8, 64QFN

IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12

IC,LP8545,LED BKLT CTRLR,LLP24

REFERENCE DES

U1000
U1000
U1000
U1000
U1400
U1400
U3990
U3900
U4100
U9701

Programmable Parts

1

338S0563
341T0240
335S0610 CRITICAL
341T0238
341S2589
338S0633
341S2384
337S2983
341S2616

IC,SMC,HS8/2117,9X9MM,TLP,HF

1

1

1

1

1

IC,CYPRS,CY7C63803-LQXC,4X4MM,USB,24-QFN

1

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

1

1

SMC EXTERNAL,K6

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

EFI UNLOCKED,K6/K69

IC,EFI,LOCKED,K6

IC,ENCORE II,CY7C63803-LQXC

IC,TP PSOC,K17,K18

U4900
U4900
U6100
U6100
U6100
U4800
U4800
U5701
U5701

BOM OPTIONS

K6_COMMON,CPU:2.4GHZ,MCP89M:A02,EEEE:DD24

K6_COMMON,CPU:2.66GHZ,MCP89M:A02,EEEE:DD23

K6_DEVEL:PVT

BOM OPTIONS

CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL

CRITICAL

CRITICAL343S0493 BCM5764M
CRITICAL
CRITICAL

CRITICAL
CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

BOM OPTION

CPU:2.26GHZ

CPU:2.4GHZ
CPU:2.53GHZ
CPU:2.66GHZ

MCP89M:A01

MCP89M:A02

BCM5764MCRITICAL341S2731

SMC:BLANK

SMC:PROG

BOOTROM:BLANK

BOOTROM:UNLOCKED

BOOTROM:LOCKED

IR:BLANK

IR:PROG

WELLSPRING:BLANK

WELLSPRING:PROG

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Bar Code Labels / EEE #’s

PART NUMBER

826-4393
826-4393

QTY

1
1

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM

REFERENCE DES

[EEEE_DD23]
[EEEE_DD24]

CRITICAL

CRITICAL
CRITICAL

BOM OPTION

EEEE:DD23
EEEE:DD24

Top

2
3
4

5
6
7
8
9

10
11

BOTTOM

K6 BOARD STACK-UP

SIGNAL
GROUND

SIGNAL(High Speed)

SIGNAL(High Speed)
GROUND
POWER
POWER

GROUND

SIGNAL(High Speed)

SIGNAL(High Speed)
GROUND
SIGNAL

D

C

B

PART NUMBER

152S0874 152S0516

152S1025

337S3769

152S1135

516-0213

516S0790

ALTERNATE FOR
PART NUMBER

152S0778152S0693

152S0685152S0796

157S0055157S0058

104S0023104S0018

128S0218128S0093

152S0586152S0847

152S1024

337S3704

152S0586

516-0201

516S0706

376S0360376S0699

BOM OPTION

REF DES

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

COMMENTS:

CYNTEC AS ALTERNATE

CYNTEC AS ALTERNATE

DELTA AS ALTERNATE

DALE/VISHAY AS ALTERNATE

KEMET AS ALTERNATE

MAGLAYERS AS ALTERNATE

MAGLAYERS AS ALTERNATE

TOKO AS ALTERNATE

INTEL P7550 CPU AS ALTERNATE

TOKO AS ALTERNATE

MOLEX AS ALTERNATE

MOLEX AS ALTERNATE

SSM6P15FE AS ALTERNATE

A

Schematic / PCB #’s

PART NUMBER

051-8563

820-2879

DRAWING

LAST_MODIFIED=Thu Mar 18 17:53:39 2010

TITLE=MLB
ABBREV=DRAWING

QTY

1

DESCRIPTION

SCHEM,MLB_LDO,K6

PCBF,MLB_LDO,K6

8 7 5 4 2 1

TABLE_ALT_HEAD

DEVELOPMENT BOM

TABLE_ALT_ITEM

PART NUMBER

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

085-1634

REFERENCE DES

SCH1

PCB

QTY

1

CRITICAL

CRITICAL

CRITICAL

DESCRIPTION

K6 MLB_LDO DEVELOPMENT BOM

BOM OPTION

REFERENCE DES

DEVEL

CRITICAL

CRITICAL

BOM OPTION

DEVEL_BOM

SYNC_MASTER=K24_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM Configuration

Apple Inc.

R

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

4 OF 109

SHEET

4 OF 80

36

Alternate Parts

SIZE

B

A

D

Revision History

345678

2 1

D

C

D

C

B

A

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

8 7 5 4 2 1

B

SIZE

A

D

SYNC_MASTER=K24_MLB

PAGE TITLE

Revision History

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

5 OF 109

SHEET

5 OF 80

36

Functional Test Points

345678

2 1

Fan Connectors

I12

D

I15

I16

TRUE
TRUE
TRUE

MIC FUNC_TEST

TRUE

I238

TRUE

I237

TRUE

I239

SPEAKER FUNC_TEST

I227

I226

I228

I230

I229

I231

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

LVDS FUNC_TEST

I259

I258

C

I260

I245

I407

I262

I261

I256

I257

I255

I252

I253

I254

I250

I251

I313

I246

I247

I248

I249

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

SATA ODD CONN

I264

I268

B

I269

I267

I265

I266

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

SATA HDD/IR/SIL

I319

I314

I315

I318

I317

I307

I309

I311

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP5V_S0
FAN_RT_PWM
FAN_RT_TACH

(NEED TO ADD 3 GND TP)

BI_MIC_LO
BI_MIC_HI
BI_MIC_SHIELD

SPKRAMP_L_N_OUT
SPKRAMP_L_P_OUT
SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_SUB_P_OUT

PP3V3_LCDVDD_SW_F
PP3V3_S0_LCD_F
PPVOUT_SW_LCDBKLT
BKL_VSYNC
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
LVDS_CONN_A_CLK_F_N

LVDS_CONN_A_CLK_F_P
LED_RETURN_1
BKL_ISEN2
BKL_ISEN3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6

(NEED TO ADD 5 GND TP)

PP5V_SW_ODD

SMC_ODD_DETECT

SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N

(NEED TO ADD 4 GND TP)

PP5V_S0_HDD_FLT
SATA_HDD_R2D_P

SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SYS_LED_ANODE_R

IR_RX_OUT
PP5V_S3_IR_R

(NEED TO ADD 5 GND TP)

(NEED 2 TP)

(NEED 4 TP)

6 7

65

46

46

55 56

55 56

55 56

54 55

54 55

54 55

54 55

54 55

54 55

6

67

6

67

67 70

67 70

8

67

8

67

8

67 74

8

67 74

8

67 74

8

67 74

8

67 74

8

67 74

67 79

67 79

67 70

70

70

67 70

67 70

67 70

6 8

36 39

36 79

36 79

36 74

36 74

(NEED 3 TP)

6

36

36 74

36 74

36 74

36 74

36

36 38

36

I303

I301

I302

I300

I299

I298

I293

I297

I294

I288

I292

I296

I291

I295

I290

I271

I289

I375

I374

I372

I370

I371

I369

I368

I361

I366

I365

I363

I364

I362

I360

I359

I357

I358

I377

I378

I354

I355

I344

I345

I346

I347

I349

I348

I350

I352

I351

I353

I327

I328

I329

I343

I342

I341

I339

I340

I338

I336

I337

I333

I335

I334

I332

I330

I331

RIGHT CLUTCH CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

IPD_FLEX_CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

KEYBOARD CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP5V_S3_BTCAMERA_F
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
PP5V_WLAN
PCIE_WAKE_L
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
USB_BT_CONN_P
USB_BT_CONN_N
AP_CLKREQ_Q_L
AP_RESET_CONN_L

(NEED TO ADD 6 GND TP)

PP3V3_S3
PP18V5_S3
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
PSOC_F_CS_L
PICKB_L

(NEED TO ADD 2 GND TP)

PP3V3_S3
PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD

(NEED TO ADD 2 GND TP)

29

15 29 74

15 29 74

29 74

29 74

29 79

29 79

29 79

29 79

6

29

15 24 29

6

42 78

6

42 78

29 79

29 79

29

29

6 7

48

6

47 48

47 48

47 48

47 48

47 48

48

47 48

47 48

47 48

47 48

47 48

47 48

47 48

6

42 78

6

42 78

47 48

47 48

6 7

6 7

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

(NEED 2 TP)

I287

I285

I414

I280

I281

I282

I283

I376

I278

I270

I416

I273

I274

I275

I417

I392

I391

I390

I388

I418

I386

I383

I419

I382

I381

I380

I421

I422
I423

I424
I425

I426

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

DC POWER CONN

I312

I304

TRUE
TRUE

FSB SIGNALS WITH NOTEST

I396

I399
I398

I397

I403
I402

I400

I401
I404

I406

I405

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

DEBUG VOLTAGE

PPVCORE_S0_CPU
PPVCORE_S0_MCP
PP1V2_ENET
PP1V05_S0

PP1V5_S0
PP1V8_S0
PP3V3_S0
PP5V_S0
PP3V3_S3

PP5V_S3

PP0V9_S5
PP3V3_S5
PP3V42_G3H

PPBUS_G3H

PP3V3_ENET

PP5V_WLAN
PP5V_SW_ODD

PP5V_S0_HDD_FLT

PP18V5_S3

PP3V3_S0_LCD_F
PP3V3_LCDVDD_SW_F

PP4V5_AUDIO_ANALOG

PP1V5R1V35_S3

SMC_PM_G2_EN

PM_SLP_S4_L

PM_SLP_S3_L

(NEED TO ADD 6 GND TP)

SPI DEBUG CONN

PP3V42_G3H

SPI_CS0_L
SPI_CLK

SPI_MOSI
SPI_MISO

SPIROM_USE_MLB

PP18V5_DCIN_FUSE
ADAPTER_SENSE

(NEED TO ADD 4 GND TP)

FSB_A_L<35..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>
FSB_D_L<63..0>
FSB_DINV_L<3..0>
FSB_DSTB_L_N<3..0>
FSB_DSTB_L_P<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>

(NEED 3 TP)

7

43

7

43

7

7

65

7

65 79

7

7

65 79

6 7

65

6 7

6 7

7

7

65 79

6 7

7

43

7

6

29

6 8

6

36

6

48

6

67

6

67

51

7

79

39 65

18 39 40 65

18 39 65 69

6 7

41 75

41 75

41 75

18 41 75

18 41 50

57

57

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

D

C

B

BATT POWER CONN

I322

I321

I320

A

I305

TRUE
TRUE
TRUE
TRUE

SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SYS_DETECT_L
PPVBAT_G3H_CONN

(NEED 3 TP)
(NEED TO ADD 4 GND TP)

6

6

57

57 58

42 78

42 78

I356

I394

BIL CONN

I326

I323

I324

I325

I308

TRUE
TRUE
TRUE
TRUE
TRUE

PP3V42_G3H
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMC_BIL_BUTTON_L
SMC_LID_R

(NEED TO ADD 4 GND TP)

6 7

6

42 78

6

42 78

39 40 57

57

I408

I409

I410
I411

I413
I412

8 7 5 4 2 1

KBD BACKLIGHT CONN

TRUE

TRUE

KBDLED_ANODE

SMC_KDBLED_PRESENT_L

T57 CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP5V_S3
PP3V3_S3
T57_PWR_EN
T57_RESET
USB_T57_N
USB_T57_P

(NEED TO ADD 1 GND TP)

(NEED TO ADD 5 GND TP)

48

48

6 7

6 7

18

18

38 75

38 75

SIZE

A

D

SYNC_MASTER=K24_MLB

PAGE TITLE

FUNC TEST

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

7 OF 109

SHEET

6 OF 80

36

345678

2 1

"S0,S0M" RAILS

=PPVCORE_S0_CPU_REG

(CPU VCORE PWR)

=PPCPUVTT_S0_REG

63

D

=PPMCPCORE_S0_REG

62

(MCP VCORE AFTER SENSE RES)

LVDDR VRef/VTT (0.75V/0.675V) Rails

=PPVTT_S0_DDR_LDO

60

C

=PPVTT_S3_DDR_BUF

28 60

=PP1V5_S0_REG

64

=PP1V8_S0_REG

64

B

=PP1V05_S0_MCP_PLL_OR

64

UNUSED MCP PE0[3:0] AVDD/DVDD

=PP1V05_S0_MCP_PE_DVDD0

19

=PP1V05_S0_MCP_PE_AVDD0

19

(SINCE PE0[3:0] IS NOT USED ON K6)

(CONNECTS TO MCP BALLS)

(CONNECTS TO MCP BALLS)

=PP1V05_S0_MCP_PE_DVDD1

19

=PP1V05_S0_MCP_PE_AVDD1

19

A

8 7 5 4 2 1

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PPVCORE_S0_CPU

PP1V05_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_CPU
=PP1V05_S0_MCP_FSB
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_PLL_UF_R
=PP1V05_FW_P1V0FWFET
=PP1V05_S0_FWPWRCTL

=PP1V05_SW_MCP_FSB
=PP1V05_S0_MCP_PE_DVDD
=PP1V05_S0_MCP_M2CLK_DLL
=PP1V05_S0_MCP_PLL_IFP
=PP1V05_S0_MCP_DP0_VDD

PPVCORE_S0_MCP

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PPVCORE_S0_MCP
=PPVCORE_S0_MCPGFXFET

PPDDRVTT_S0

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

=PPDDRVTT_S0_MEM_A
=PPDDRVTT_S0_MEM_B

PPDDRVREF_S3

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0_CPU
=PP1V5_S0_SATARDRVR
=PP1V5_S0_MCP_PLL_VLDO

=PP1V8R1V5_S0_AUDIO

=PP1V5_S0_MCP_HDA_R
=PP1V5_S0_AUDIO_R

PP1V8_S0

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP3V3R1V8_S0_MCP_IFP_VDD
=PP1V8_S0_AUDIO

PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_PE_DVDD

PP1V05_S0_MCP_PE_AVDD

MAKE_BASE=TRUE

6

43 61

10 11

6

65

9

10 11 12 61

13 19 22

22

19 22

64

34

34

19 22

7

22

14 22

16 23

16 23

6

43

19 22

21

25

26

6

65 79

10 11

36

51

8

8

6

16 23

22

(CONNECTS TO THE DECAPS)

7
22

(CONNECTS TO THE DECAPS)

22

=PP5V_S0_FET

66

=PP3V3_S0_FET

=PP3V3_ENET_FET_R

8

400mA

(BCM5764M)

=PP1V2_ENET_REG

64

700 mA max output

=PP1V2_ENET_PHY_REG

64

(BCM57765)

=PP0V9_ENET_FET

66

PP5V_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_HDD
=PP5V_S0_LPCPLUS
=PP5V_S0_FAN_RT

=PP5V_S0_CPU_IMVP

=PP5V_S0_KBDLED
=PP5VR3V3_S0_DPCADET
=PP5V_S0_CPUVTTS0
=PP5V_S0_BKL
=PP5V_S0_MCPREG
=PP5V_S0_MCPFSBFET

PP3V3_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S0_XDP
=PP3V3_S0_MCP
=PP3V3_S0_P1V5S0
=PP3V3_S0_DEBUGROM
=PP3V3_S0_ODD
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_MCP_0
=PP3V3_S0_FAN_RT
=PP3V3_S0_AUDIO

=PP3V3_S0_IMVP

=PP3V3_S0_LCD
=PP3V3_S0_MCP_GPIO

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP_HVDD
=PP3V3_S0_SMC
=PP3V3_S0_MCPTHMSNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_DPCONN
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_PWRCTL
=PP3V3_S0_ENETPHY
=PP3V3_S0_CPUVTTISNS
=PP3V3_S0_TPAD
=PP3V3_S0_SMBUS_MCP_1
=PP3V3_S0_P1V8S0
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_MCPDDRISNS
=PP3V3_S0_MCP_PLL_VLDO
=PP3V3_S0_FWPWRCTL
=PP3V3_S0_FWLATEVG
=PP3V3_S0_SDCONN
=PP3V3_S0_MCPCOREISNS

=PP3V3_S0_MCP_HDA_R
=PP3V3_S0_AUDIO_R

=PP3V3_S0_OPA333

"ENET" RAILS

PP3V3_ENET

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

300mA

~100mA

~400mA

=PP3V3_ENET_MCP_RMGT
=PP3V3_ENET_MCP_PLL_MAC
=PP3V3_ENET_PHY
=PP3V3_ENET_PWRCTL

PP1V2_ENET

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PP1V2_ENET_PHY

PP0V9_ENET

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PP0V9_ENET_MCP_RMGT

6

17 19 22

22

24 31 64

65

6

31

19 22

6

65

36

41

46

61

48

69

63

70

62

21

6

65 79 66

12

19 22

64

41

36

42

42

42

46

51 55 56

61

67

16 17 18

22

19 22

40

45

45

69

25

26

65

31

44

48

42

64

70

44

34

34 35

30

44

8

8

22

60

59

=PP3V3_S5_REG

59

64

=PPDDR_S3_REG

66

=PP3V3_S3_FET

=PP5V_S3_REG

=PP0V9_S5_REG

LVDDR (1.5V/1.35V) Rails

PP1V5R1V35_S3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PPLVDDR_S3_MEM_A
=PPLVDDR_S3_MEM_B

0 mA

4250 mA

=PP1V5R1V35_S3_MCP_MEM
=PP1V5R1V35_S0_MCPDDRFET
=PPVIN_S0_DDRREG_LDO

PP3V3_S3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_PDCISENS

=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_TPAD
=PP3V3_S3_SMS
=PP3V3_S3_CARDREADER
=PP3V3_S3_T57
=PP3V3_ENET_P1V2ENET

PP5V_S3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S3_RTUSB
=PP5V_S3_IR
=PP5V_S3_MCPDDRFET
=PP5V_S3_SYSLED
=PP5V_S3_TPAD

=PP5V_S3_WLAN

=PP5V_S3_DDRREG
=PP5V_S3_AUDIO
=PP5V_S3_AUDIO_AMP
=PP5V_S3_P5VS0FET
=PP5V_S0_ODD

=PP5V_S3_BTCAMERA
=PP5V_S3_T57

"S5" RAILS

PP3V3_S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S5_MCP_GPIO
=PP3V3_S5_ROM
=PP3V3_S5_LCD
=PP3V3_S5_MCP
=PP3V3_S5_MCPPWRGD
=PP3V3_S5_P3V3S3FET
=PP3V3_S5_P3V3S0FET
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_DP_PORT_PWR
=PP3V3_S5_P0V9S5
=PP3V3_FW_P3V3FWFET
=PP3V3_S5_P0V9ENETFET

=PP3V3_S5_VMON
=PP3V3_S5_SMBUS_SMC_MGMT

0.9V Rails

105 mA/241 mA
139 mA/ 0 mA

PP0V9_S5

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PP0V9_S5_MCP_VDD_AUXC
=PP0V9_ENET_P0V9ENETFET

(OR 1.35V)

36

6

19 22

66

6

17 18

50

67

19 22

24

66

66

66

69

64

34

66

65

42

29

38

65 79

6

42

60

28

29

18

47 48

49

30

38

64

6

37

36 38

20

40

48

29

60

51 53 55

54

66

36

=PP3V42_G3H_REG

57

6

79

25

26

14

20

60

=PP18V5_DCIN_CONN

57

=PPBUS_G3H

58

=PPBUS_S5_CPUREGS_ISNS

44

(AFTER HIGH SIDE CPU VCORE

& CPU VTT SENSING RES.)

=PP3V3_FW_FET

34

=PPBUS_FW_FET

34

=PP1V0_FW_FET_R

34

SYNC_MASTER=K24_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

"S3" RAILS

"G3H" RAILS

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE

=PPVIN_S5_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_CHGR
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PP3V42_G3H_BATT

=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PP3V42_G3H_BMON_ISNS
=PP3V42_G3H_ONEWIRE

I1086

PP3V3_G3_RTC
=PP3V42_G3H_OPA330

PPDCIN_S5_S5

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPBUS_S0_LCDBKLT
=PPVIN_S0_MCPCORE
=PPVIN_S3_DDRREG
=PPVIN_S5_3V3S5
=PPVIN_S3_5VS3
=PPBUS_S5_FWPWRSW

=PPBUS_S5_CPUREGS_ISNS_R

(BEFORE HIGH SIDE SENSING RES.)

PPBUS_S5_IMVP_VTT_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVIN_S0_CPUVTTS0
=PPVIN_S5_CPU_IMVP

"FIREWIRE" RAILS

PP3V3_FW

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_FW_FWPHY

PPVP_FW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET

PP1V05_FW

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V0_FW_FWPHY

Power Aliases

Apple Inc.

R

39 40

41

44

57

18 19 22

22

33 34 35

35

35

33 34

SYNC_DATE=07/22/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

8 OF 109

SHEET

7 OF 80

6

40

42

65

58 65

37

47

57

58

6

71

62

60

59

59

34

44

63

61

D

43

C

B

A

SIZE

D

345678

PCI-E ALIASES

=PEG_D2R_N<3:0>

66

121

5%

2

15

=PEG_D2R_P<3:0>

15

=PEG_R2D_C_N<3:0>

15

=PEG_R2D_C_P<3:0>

15

PEG_CLK100M_P

15 74

PEG_CLK100M_N

15 74

PEG_CLKREQ_L

15

USB_EXTC_P

17 75

USB_EXTC_N

17 75

USB_EXTD_P

17 75

USB_EXTD_N

17 75

USB_WM_P

17 75

USB_WM_N

17 75

USB_MINI_P

17 75

USB_MINI_N

17 75

PP3V3_ENET_FET

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_ENET_FET

ENET_RXD_PD

MAKE_BASE=TRUE

ENET_RXCLK_PD

MAKE_BASE=TRUE

R0981

10K

5%
1/16W
MF-LF
402

10K

5%
1/16W
MF-LF

402

2

HEATSINK STANDOFFS

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902

1

STDOFF-4.5OD.98H-1.1-3.48-TH

LEFT OF CPU

D

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0903

1

STDOFF-4.5OD.98H-1.1-3.48-TH

BELOW MCP

Z0901

1

ABOVE CPU

Z0904

1

BELOW CPU

FAN STANDOFF

STDOFF-4.5OD.98H-1.1-3.48-TH

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

Z0905

1

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

OMITOMIT

Z0906

3R2P5

Z0907

3R2P5

11

C

MLB MOUNTING (TO TOPCASE) SCREW HOLES

OMIT

Z0908

3R2P5

1

OMIT

Z0911

3R2P5

1

OMIT

Z0909

3R2P5

1

OMIT

Z0912

3R2P5

1

OMIT

Z0910

3R2P5

1

R0980

1/16W
MF-LF

10K

402

UNUSED GPU LANES

USB ALIASES

UNUSED USB PORTS

ETHERNET ALIASES

PLACE_NEAR=U7980.A1:5MM

R0984

121

R0983R0982

10K

5%
1/16W
MF-LF
402

1/16W
MF-LF

10K

R0911

0

1 2

5%
1/16W
MF-LF

402

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>

ENET_CLK125M_RXCLK

ENET_RX_CTRL

ENET_MDIO

MCP_RGMII_VREF
ENET_LOW_PWR

NO STUFF

1

R0986

10K

5%

5%

1/16W

MF-LF

402

402

2

NC_PEG_D2R_N<3:0>

NO_TEST=TRUE

NC_PEG_D2R_P<3:0>

NO_TEST=TRUE

NC_PEG_R2D_C_N<3:0>

NO_TEST=TRUE

NC_PEG_R2D_C_P<3:0>

NO_TEST=TRUE

TP_PEG_CLK100M_P
TP_PEG_CLK100M_N
TP_PEG_CLKREQ_L

TP_USB_EXTCP
TP_USB_EXTCN
TP_USB_EXTDP
TP_USB_EXTDN
TP_USB_WMP
TP_USB_WMN

TP_USB_MINIP
TP_USB_MININ

=PP3V3_ENET_FET_R

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MCP_TV_DAC_RSET

74

MCP_TV_DAC_VREF

74

MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT
CRT_IG_R_C_PR

74

CRT_IG_G_Y_Y

74

CRT_IG_B_COMP_PB

74

CRT_IG_HSYNC

74

CRT_IG_VSYNC

74

=MCP_IFPA_TXC_P

16

=MCP_IFPA_TXC_N

16

=MCP_IFPA_TXD_P<0..2>

16

=MCP_IFPA_TXD_N<0..2>

16

=MCP_IFPA_TXD_P<3>

16

=MCP_IFPA_TXD_N<3>

16

=MCP_IFPB_TXC_P

16

=MCP_IFPB_TXC_N

16

=MCP_IFPB_TXD_P<0..3>

16

=MCP_IFPB_TXD_N<0..3>

16

LCD_IG_BKLT_PWM

7

OUT

17 76

OUT

17 76

OUT

17 76

OUT

17 76

OUT

17 76

OUT

17 76

OUT

17 76

BI

16

17

OUT

16

18 31

OUT

16

LCD_IG_BKLT_EN

16

=MCP_IFPAB_DDC_CLK

16

=MCP_IFPAB_DDC_DATA

16

DP_IG_ML0_P<0..3>
DP_IG_ML0_N<0..3>

DP_IG_HPD0
DP_IG_AUX_CH0_P

16

DP_IG_AUX_CH0_N

16

DP_AUX_CH_C_N

68

DP_AUX_CH_C_P

68

DP_CA_DET

68

DP_IG_ML1_P<0..3>

16

DP_IG_ML1_N<0..3>

16

DP_IG_AUX_CH1_P

16

DP_IG_AUX_CH1_N

16

DP_IG_HPD1

16

B

DACS ALIASES

UNUSED CRT & TV-OUT INTERFACE

NC_MCP_TV_DAC_RSET

NO_TEST=TRUE

NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

NC_MCP_CLK27M_XTALIN

NO_TEST=TRUE

NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE

NC_CRT_IG_R_C_PR

NO_TEST=TRUE

NC_CRT_IG_G_Y_Y

NO_TEST=TRUE

NC_CRT_IG_B_COMP_PB

NO_TEST=TRUE

NC_CRT_IG_HSYNC

NO_TEST=TRUE

NC_CRT_IG_VSYNC

NO_TEST=TRUE

LVDS ALIASES

LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<0..2>
LVDS_IG_A_DATA_N<0..2>

NC_LVDS_IG_A_DATAP<3>
NC_LVDS_IG_A_DATAN<3>
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_DATAP<0..3>
NC_LVDS_IG_B_DATAN<0..3>

LCD_BKLT_PWM
LCD_BKLT_EN

LVDS_DDC_CLK
LVDS_DDC_DATA

DISPLAY PORT ALIASES

DP_IG_ML_P<0..3>

74

DP_IG_ML_N<0..3>

74

402

R0920

1 2

100K

5%

MF-LF

1/16W

DP_EXT_HPD
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N

DP_EXT_AUX_CH_C_N
DP_EXT_AUX_CH_C_P

DP_EXT_CA_DET

TP_DP_IG_ML1P<0..3>
TP_DP_IG_ML1N<0..3>
TP_DP_IG_AUX_CH1P
TP_DP_IG_AUX_CH1N

AUDIO ALIASES

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_EXT_ML_P<0..3>
DP_EXT_ML_N<0..3>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

67 74

67 74

6

6

70

71

6

6

69 16

68 74

68 74

69 79

69 79

69

67 74

67 74

67

67

MAKE_BASE=TRUE

MAKE_BASE=TRUE

CPU_BSEL<0:2>

9

72

MAKE_BASE=TRUE

CPU_PECI_MCP

13

TP_MCP_RGB_RED

16

TP_MCP_RGB_GREEN

16

TP_MCP_RGB_BLUE

16

TP_MCP_RGB_HSYNC

16

TP_MCP_RGB_VSYNC

16

TP_MCP_RGB_DAC_RSET

16

TP_MCP_RGB_DAC_VREF

16

PP5V_SW_ODD

6

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.4 MM
VOLTAGE=5V

BACKLIGHT CONTROLLER ALIASES

PPBUS_SW_LCDBKLT_PWR

70 71

69 79

69 79

=CHGR_ACOK

IN

MCPCORES0_VO

MCPCORES0_ISP_R

62

2 1

CPU ALIASES

=MCP_BSEL<0:2>

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

MCP89 ALIASES

NC_MCP_RGB_RED

MAKE_BASE=TRUE

NC_MCP_RGB_GREEN

MAKE_BASE=TRUE

NC_MCP_RGB_BLUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF

MAKE_BASE=TRUE

5V ODD ALIASES

=PP5V_SW_ODD
=PP5V_SW_ODD_FET

R0910

1 2

PLACE_NEAR=L9701.1:5MM

5%
1/16W
MF-LF

402

0

PPBUS_SW_BKL

=PPBUS_SW_BKL

CHARGER SIGNAL

SMC_BC_ACOK

MAKE_BASE=TRUE

MCPCOREISNS SIGNAL

MCPCOREISNS_N

MAKE_BASE=TRUE

MCPCOREISNS_P

MAKE_BASE=TRUE

13

BSEL<2..0>

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE

=MCPCOREISNS_N

=MCPCOREISNS_P

0 0 0
0 0 1
0 1 0
0 1 1 (166)
1 0 0
1 0 1

1 1 1

36

36

OUT

FSB MHZ

266
133
200

333

100
(400)1 1 0
(RSVD)

D

C

70

39 40 57 58

44 62

44

B

EMI IO (SHORT) POGO PINS

HDA:1.5V

1.4DIA-SHORT-EMI-MLB-K19-K24

1.4DIA-SHORT-EMI-MLB-K19-K24

ZS0900

SM SM

1 1 1

ZS0903 ZS0908

SM

1 1 1

1.4DIA-SHORT-EMI-MLB-K19-K24

1.4DIA-SHORT-EMI-MLB-K19-K24

A

ZS0904

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0901 ZS0902

SM SM

1.4DIA-SHORT-EMI-MLB-K19-K24

1.4DIA-SHORT-EMI-MLB-K19-K24

SM

ZS0909

EMI TALL POGO PINS

ZS0905

SM

1 11 1

2.0DIA-TALL-EMI-MLB-M97-M982.0DIA-TALL-EMI-MLB-M97-M98

ZS0906

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0907

SM

=PP1V5_S0_AUDIO_R

7

=PP3V3_S0_AUDIO_R

7

=PP1V5_S0_MCP_HDA_R

7

=PP3V3_S0_MCP_HDA_R

7

R0912

HDA:3.3V

R0913

HDA:1.5V

R0914

HDA:3.3V

R0915

8 7 5 4 2 1

1 2

40205%

0

1 2

402

5%

1/16W

0

1 2

4025%1/16W MF-LF

0

1 2

402

1/16W MF-LF

5%

PP3V3R1V5_S0_AUDIO

PP3V3R1V5_S0_MCP_HDA

MAKE_BASE=TRUE

MF-LF1/16W

VOLTAGE=1.5V

=PP3V3R1V5_S0_AUDIO

MF-LF

MAKE_BASE=TRUE
VOLTAGE=1.5V

=PP3V3R1V5_S0_MCP_HDA

36

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

51

18 22

SYNC_MASTER=K24_MLB

PAGE TITLE

SIGNAL ALIAS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

9 OF 109

SHEET

8 OF 80

SIZE

A

D

345678

2 1

OMIT

ADS*
BNR*

BPRI*

DEFER*

DRDY*
DBSY*

BR0*

IERR*
INIT*

LOCK*

RESET*

RS0*
RS1*
RS2*

TRDY*

HIT*

HITM*

BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*

TRST*

DBR*

PROCHOT*

THERMDA
THERMDC

BCLK0
BCLK1

TCK
TDI
TDO
TMS

H1

FSB_ADS_L

E2

FSB_BNR_L

G5

FSB_BPRI_L

H5

FSB_DEFER_L

F21

FSB_DRDY_L

E1

FSB_DBSY_L

F1

FSB_BREQ0_L

D20

CPU_IERR_L

72

B3

CPU_INIT_L

H4

FSB_LOCK_L

C1

FSB_CPURST_L

F3

FSB_RS_L<0>

F4

FSB_RS_L<1>

G3

FSB_RS_L<2>

G2

FSB_TRDY_L

G6

FSB_HIT_L

E4

FSB_HITM_L

AD4

XDP_BPM_L<0>

AD3

XDP_BPM_L<1>

AD1

XDP_BPM_L<2>

AC4

XDP_BPM_L<3>

AC2

XDP_BPM_L<4>

AC1

XDP_BPM_L<5>

AC5

XDP_TCK

AA6

XDP_TDI

AB3

XDP_TDO

AB5

XDP_TMS

AB6

XDP_TRST_L

C20

XDP_DBRESET_L

D21

CPU_PROCHOT_L

A24

CPU_THERMD_P

B25

CPU_THERMD_N

C7

PM_THRMTRIP_L

A22

FSB_CLK_CPU_P

A21

FSB_CLK_CPU_N

IN

IN
IN
IN
IN
IN

IN
IN

OUT

IN
IN

OUT

OUT
OUT

OUT

IN
IN

CPU JTAG Support

XDP_TMS

9

12 72

XDP_TDI

9

12 72

XDP_TDO

9

12 72

PLACE_NEAR=J1300.51:12.7 mm

XDP_TCK

9

12 72

XDP_TRST_L

9

12 72

BI
BI
BI

BI
BI
BI

BI

BI

BI
BI

BI
BI
BI
BI
BI

6

13 72

13 72

13 72

13 72

13 72

13 72

13 72

13 72

6

13 72

12 13 72

13 72

13 72

13 72

13 72

6

13 72

6

13 72

12 72

12 72

12 72

12 72

12 72

9

12 72

9

12 72

9

12 72

9

12 72

9

12 72

12 24

45 79

45 79

13 40 72

13 72

13 72

R1091

54.9

1 2

1/16W
MF-LF

R1094

1 2

1/16W
MF-LF

1%

402

649

1%

402

R1000

54.9

R1001

54.9

R1002

R1090

54.9

1 2

1%
1/16W
MF-LF

402

R1092

54.9

1 2

1%
1/16W
MF-LF

402

R1093

54.9

1 2

1%
1/16W
MF-LF

402

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

=PP1V05_S0_CPU

1

1%

402

2

7

10 11 12 61

D

FSB_D_L<0>

6

13 72

BI

FSB_D_L<1>

6

13 72

1

1%

402

2

1

68

5%

402

2

BI

OUT

1

R1005

1K

1%
1/16W
MF-LF
402

2

1

R1006

2.0K

1%
1/16W
MF-LF
402

2

NO STUFF

R1011

12 72

13 40 61 72

PLACE_NEARs:

R1005.2:
R1006.1:
C1014.1:

NO STUFF

R1010

1 2

1

1K

5%
1/16W
MF-LF

402

2

U1000.AD26:12.7 mm
U1000.AD26:12.7 mm
U1000.AF26:12.7 mm

NO STUFF

C1014

0

5%
1/16W
MF-LF

402

NO STUFF

1

R1012

1K

5%
1/16W
MF-LF
402

2

0.1uF

1

10%
16V

2

X5R
402

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

28 72

8

72

OUT

8

72

OUT

8

72

OUT

FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>

FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>

CPU_GTLREF
CPU_TEST1

CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6

TP_CPU_TEST7

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

AD26

C23
D25
C24

AF26

AF1
A26

B22
B23
C21

C3

D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*

D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2

U1000

PENRYN

FCBGA

2 OF 4

DATA GRP 0DATA GRP 1

MISC

DATA GRP 3 DATA GRP 2

OMIT

D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*

D47*
DSTBN2*
DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*
DSTBN3*
DSTBP3*

DINV3*

COMP0
COMP1
COMP2
COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

Y22

FSB_D_L<32>

AB24

FSB_D_L<33>

V24

FSB_D_L<34>

V26

FSB_D_L<35>

V23

FSB_D_L<36>

T22

FSB_D_L<37>

U25

FSB_D_L<38>

U23

FSB_D_L<39>

Y25

FSB_D_L<40>

W22

FSB_D_L<41>

Y23

FSB_D_L<42>

W24

FSB_D_L<43>

W25

FSB_D_L<44>

AA23

FSB_D_L<45>

AA24

FSB_D_L<46>

AB25

FSB_D_L<47>

Y26

FSB_DSTB_L_N<2>

AA26

FSB_DSTB_L_P<2>

U22

FSB_DINV_L<2>

AE24

FSB_D_L<48>

AD24

FSB_D_L<49>

AA21

FSB_D_L<50>

AB22

FSB_D_L<51>

AB21

FSB_D_L<52>

AC26

FSB_D_L<53>

AD20

FSB_D_L<54>

AE22

FSB_D_L<55>

AF23

FSB_D_L<56>

AC25

FSB_D_L<57>

AE21

FSB_D_L<58>

AD21

FSB_D_L<59>

AC22

FSB_D_L<60>

AD23

FSB_D_L<61>

AF22

FSB_D_L<62>

AC23

FSB_D_L<63>

AE25

FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>

AF24

FSB_DINV_L<3>

AC20

R26

CPU_COMP<0>

72

U26

CPU_COMP<1>

72

AA1

CPU_COMP<2>

72

CPU_COMP<3>

72

Y1

E5

CPU_DPRSTP_L

B5

CPU_DPSLP_L

D24

FSB_DPWR_L

D6

CPU_PWRGD

D7

FSB_CPUSLP_L

AE6

CPU_PSI_L

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

6

13 72

BI

13 61 72

IN

13 72

IN

13 72

IN

12 13 72

IN

13 72

IN

61

OUT

R1023

54.9

1/16W
MF-LF

1

1%

402

2

1

2

R1021

54.9

1/16W
MF-LF

R1022

27.4

1%
1/16W
MF-LF
402

1

1%

402

2

1

R1020

27.4

1%
1/16W
MF-LF
402

2

C

B

PLACE_NEARs:

R1020.1:

U1000.R26:12.7 mm
U1000.U26:12.7 mm

R1021.1:
R1022.1:

U1000.AA1:12.7 mm

R1023.1:

U1000.Y1:12.7 mm

AA4
AB2
AA3

D22

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

K3
H2
K2
J3
L1

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3

V1

A6
A5
C4

D5
C6
B4
A3

M4
N5
T2
V3
B2
F6
D2

D3

A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*

REQ0*
REQ1*
REQ2*
REQ3*
REQ4*

A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*

A20M*
FERR*
IGNNE*

STPCLK*
LINT0
LINT1
SMI*

RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8

U1000

PENRYN

FCBGA

1 OF 4

ADDR GROUP0

ADDR GROUP1

ICH

RESERVED

CONTROL

XDP/ITP SIGNALS

THERMAL

THERMTRIP*

H CLK

FSB_A_L<3>

6

13 72

BI

FSB_A_L<4>

6

13 72

BI

FSB_A_L<5>

6

13 72

BI

FSB_A_L<6>

6

13 72

BI

FSB_A_L<7>

6

13 72

BI

FSB_A_L<8>

6

13 72

BI

FSB_A_L<9>

6

13 72

BI

FSB_A_L<10>

6

13 72

BI

FSB_A_L<11>

6

13 72

BI

FSB_A_L<12>

6

13 72

BI

FSB_A_L<13>

6

13 72

D

C

BI

FSB_A_L<14>

6

13 72

BI

FSB_A_L<15>

6

13 72

BI

FSB_A_L<16>

6

13 72

BI

FSB_ADSTB_L<0>

6

13 72

BI

FSB_REQ_L<0>

6

13 72

BI

FSB_REQ_L<1>

6

13 72

BI

FSB_REQ_L<2>

6

13 72

BI

FSB_REQ_L<3>

6

13 72

BI

FSB_REQ_L<4>

6

13 72

BI

FSB_A_L<17>

6

13 72

BI

FSB_A_L<18>

6

13 72

BI

FSB_A_L<19>

6

13 72

BI

FSB_A_L<20>

6

13 72

BI

FSB_A_L<21>

6

13 72

BI

FSB_A_L<22>

6

13 72

BI

FSB_A_L<23>

6

13 72

BI

FSB_A_L<24>

6

13 72

BI

FSB_A_L<25>

6

13 72

BI

FSB_A_L<26>

6

13 72

BI

FSB_A_L<27>

6

13 72

BI

FSB_A_L<28>

6

13 72

BI

FSB_A_L<29>

6

13 72

BI

FSB_A_L<30>

6

13 72

BI

FSB_A_L<31>

6

13 72

BI

FSB_A_L<32>

6

13 72

BI

FSB_A_L<33>

6

13 72

BI

FSB_A_L<34>

6

13 72

BI

FSB_A_L<35>

6

13 72

BI

FSB_ADSTB_L<1>

6

13 72

BI

CPU_A20M_L

13 72

IN

CPU_FERR_L

13 72

OUT

CPU_IGNNE_L

13 72

IN

CPU_STPCLK_L

13 72

IN

CPU_INTR

13 72

IN

CPU_NMI

13 72

IN

CPU_SMI_L

13 72

IN

TP_CPU_RSVD_M4
TP_CPU_RSVD_N5
TP_CPU_RSVD_T2
TP_CPU_RSVD_V3
TP_CPU_RSVD_B2
TP_CPU_RSVD_F6
TP_CPU_RSVD_D2
TP_CPU_RSVD_D22
TP_CPU_RSVD_D3

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU FSB

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

10 OF 109

SHEET

9 OF 80

SIZE

A

D

345678

2 1

A4

(CPU CORE POWER)
=PPVCORE_S0_CPU

AA10

AA12

AA13
AA15

AA17

AA18
AA20

AC10
AB10

AB12
AB14

AB15

AB17
AB18

A7

A9

A10
A12

A13

A15
A17

A18
A20

B7

B9
B10

B12

B14
B15

B17

B18
B20

C9
C10

C12

C13
C15

C17

C18

D9

D10

D12
D14

D15

VCC

D17

D18

E7

E9

E10

E12
E13

E15

E17
E18

E20

F7

F9

F10
F12

F14

F15
F17

F18

F20
AA7

(BR1#)

AA9

AB9

OMIT

U1000

PENRYN

FCBGA

3 OF 4

VCCSENSE

VSSSENSE

D

C

B

VCC

VCCP

VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

AB20

AB7

AC7
AC9

AC12

AC13
AC15

AC17
AC18

AD7

AD9
AD10

AD12

AD14
AD15

AD17

AD18
AE9

AE10
AE12

AE13

AE15
AE17

AE18

AE20
AF9
AF10

AF12

AF14
AF15

AF17

AF18
AF20

G21
V6

J6
K6

M6

J21
K21

M21

N21
N6

R21

R6

T21
T6

V21

W21

B26
C26

AD6
AF5

AE5

AF4
AE3

AF3

AE2

AF7

AE7

(CPU IO POWER 1.05V)

=PP1V05_S0_CPU

(CPU INTERNAL PLL POWER 1.5V)
=PP1V5_S0_CPU

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

7

10 11

44 A (SV Design Target)
41 A (SV HFM)

30.4 A (SV LFM)
23 A (LV Design Target)

7 9

11 12 61

4500 mA (before VCC stable)
2500 mA (after VCC stable)

7

11

130 mA

61 72

OUT

61 72

OUT

61 72

OUT

61 72

OUT

61 72

OUT

61 72

OUT

61 72

OUT

=PPVCORE_S0_CPU

1

R1100

100

1%
1/16W
MF-LF
402

2

61 72

OUT

PLACE_NEAR=U1000.AF7:25.4 mm

PLACE_NEAR=U1000.AE7:25.4 mm

61 72

OUT

1

R1101

100

1%
1/16W
MF-LF
402

2

7

10 11

A8

A11
A14

A16

A19
A23

AF2

B6
B8

B11

B13
B16

B19
B21

B24

C5
C8

C11

C14
C16

C19

C2
C22

C25

D1

D4

D8
D11

D13

D16
D19

D23

D26

E3

E6

E8

E11
E14

VSS VSS

E16
E19

E21
E24

F5

F8
F11

F13
F16

F19

F2
F22

F25

G4

G1

G23

G26

H3

H6
H21

H24

J2

J5

J22

J25

K1

K4

K23
K26

L3

L6

L21

L24

M2

M5

M22
M25

N1

N4
N23

N26

P3

B1

(Socket-P KEY)

OMIT

U1000

PENRYN

FCBGA

4 OF 4

T26

U3
U6

U21
U24

V2

V5

V22
V25

W1

W4
W23

W26
Y3

Y6
Y21

Y24

AA2
AA5

AA8

AA11
AA14

AA16

AA19
AA22

AA25
AB1

AB4

AB8
AB11

AB13

AB16
AB19

AB23

AB26
AC3

AC6

AC8

AC11
AC14

AC16
AC19

AC21

AC24
AD2
AD5
AD8

AD11
AD13

AD16

AD19
AD22

AD25

AE1

AE4
AE8

AE11

AE14
AE16

AE19

AE23
AE26

A2
AF6

AF8

AF11
AF13

AF16

AF19
AF21

A25

AF25

P6

P21
P24

R2

R5
R22

R25
T1

T4

T23

D

C

B

A

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU Power & Ground

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

11 OF 109

SHEET

10 OF 80

36

345678

2 1

CPU VCore HF and Bulk Decoupling

4X 330UF. 20X 22UF 0805

PLACEMENT_NOTE (C1200-C1219):

=PPVCORE_S0_CPU

7

D

10

CPU_CAP:15&CPU_CAP:12

CRITICAL

1

C1200

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

CRITICAL

1

C1210

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

NO STUFF
CRITICAL

1

C1201

22UF

20%

6.3V

2

X5R-CERM
603

1

2

CPU_CAP:15&CPU_CAP:12

NO STUFF
CRITICAL

1

C1211

22UF

20%

6.3V

2

X5R-CERM
603

1

2

NO STUFF

CRITICAL

C1202

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1212

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

1

C1203

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

CRITICAL

1

C1213

22UF

20%

6.3V

2

X5R-CERM
603

NO STUFF
CRITICAL

1

C1204

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

CPU_CAP:15&CPU_CAP:12

CRITICAL

1

C1214

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

CPU_CAP:15

CRITICAL

1

C1205

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1215

22UF

20%

6.3V

2

X5R-CERM
603

1

2

CPU_CAP:15

1

2

NO STUFF

CRITICAL

C1206

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

1

C1207

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15&CPU_CAP:12

CRITICAL

C1216

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

1

C1217

22UF

20%

6.3V

2

X5R-CERM
603

NO STUFF
CRITICAL

1

C1208

22UF

20%

6.3V

2

X5R-CERM
603

1

2

CPU_CAP:15&CPU_CAP:12

CPU_CAP:15&CPU_CAP:12

CRITICAL

1

C1218

22UF

20%

6.3V

2

X5R-CERM
603

1

2

NO STUFF
CRITICAL

C1209

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1219

22UF

20%

6.3V
X5R-CERM
603

PLACEMENT_NOTE (C1240-C1243):

CPU_CAP:15&CPU_CAP:12

Place inside socket cavity on secondary side.

NO STUFF
CRITICAL

1

C1220

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

1

C1221

22UF

20%

6.3V

2

X5R-CERM
603

CPU_CAP:15

CRITICAL

1

C1222

22UF

20%

6.3V

2

X5R-CERM
603

C

Place on secondary side.

Place on secondary side.

Place on secondary side.

Place on secondary side.

CRITICAL
NO STUFF

1

C1240

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT
D2T-SM

CRITICAL

1

C1241

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT
D2T-SM

CRITICAL

1

C1242

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT
D2T-SM

CRITICAL

1

C1243

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT
D2T-SM

D

C

VCCA (CPU AVdd) DECOUPLING

=PP1V5_S0_CPU

7

10

B

1x 10uF, 1x 0.01uF

BYPASS=U1000.B26::4 mm

1

1

C1251C1250

10uF

6.3V

20%
X5R

603

0.01UF

10%
16V

2

2

CERM
402

B

VCCP (CPU I/O) DECOUPLING

=PP1V05_S0_CPU

7 9

10 12 61

CRITICAL

C1260

POLY-TANT

A

8 7 5 4 2 1

1x 330uF, 6x 0.1uF 0402

PLACEMENT_NOTE=Place C1260 between CPU & NB.

1

330UF

2.0V

D2T-SM2

1

C1261

0.1UF

20%

20%
10V

32

2

CERM
402

1

C1262

0.1UF

20%
10V

2

CERM
402

1

2

C1263

0.1UF

20%
10V
CERM
402

1

C1264

0.1UF

20%
10V

2

CERM
402

1

C1265

0.1UF

20%
10V

2

CERM
402

1

C1266

0.1UF

20%
10V

2

CERM
402

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

12 OF 109

SHEET

11 OF 80

36

345678

2 1

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

D

Use with 920-0620 adapter board to support CPU, MCP debugging.

D

MCP89-specific pinout

=PP3V3_S0_XDP

7

=PP1V05_S0_CPU

7 9

10 11 61

XDP

1

R1315

54.9

1%
1/16W
MF-LF

402

2

XDP_BPM_L<5>

9

72

BI

XDP_BPM_L<4>

9

72

BI

XDP_BPM_L<3>

9

72

BI

XDP_BPM_L<2>

9

72

IN

XDP_BPM_L<1>

9

72

IN

XDP_BPM_L<0>

9

72

IN

C

XDP

R1399

1K

CPU_PWRGD

9

13 72

IN

1 2

5%
1/16W
MF-LF

402

18

IN

18

OUT

18 42 75

BI

18 42 75

BI

9

72

OUT

TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3

XDP_PWRGD

PM_LATRIGGER_L
JTAG_MCP_TCK

SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK

XDP_TCK

XDP_OBS20

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_A1

OBSDATA_A2

OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

C1300

0.1uF

HOOK1

HOOK2

HOOK3

TCK1
TCK0

XDP

SDA

SCL

1

10%
16V

2

X5R
402

B

CRITICAL

XDP_CONN

J1300

LTH-030-01-G-D-NOPEGS

F-ST-SM

2

1

4 3

6

5

8

10

12
14

16
18

20

22
24

26

28
30

32

34
36

38
40

42

44
46

48

50
52

54

56

NC

58

60

7

9

11
13

15
17

19

21
23

25

27
29

31

33
35

37
39

41

43
45

47

49
51

53

55
57

59

998-1571

OBSFN_C0

OBSFN_C1

OBSDATA_C0

OBSDATA_C1

OBSDATA_C2

OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5

VCC_OBS_CD
RESET#/HOOK6

DBR#/HOOK7

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
TDO

TRSTn

TDI
TMS

XDP_PRESENT#

XDP

1

C1301

0.1uF

10%
16V

2

X5R
402

JTAG_MCP_TDO
JTAG_MCP_TRST_L

TP_XDP_OBSDATA_C0
TP_XDP_OBSDATA_C1

TP_XDP_OBSDATA_C2
TP_XDP_OBSDATA_C3

JTAG_MCP_TDI
JTAG_MCP_TMS

TP_XDP_OBSDATA_D0
TP_XDP_OBSDATA_D1

TP_XDP_OBSDATA_D2
TP_XDP_OBSDATA_D3

FSB_CLK_ITP_P
FSB_CLK_ITP_N

XDP_CPURST_L

72

XDP_DBRESET_L

XDP_TDO
XDP_TRST_L
XDP_TDI
XDP_TMS

18

IN

18

OUT

18

OUT

18

OUT

13 72

IN

13 72

IN

9

24

OUT

9

72

IN

9

72

OUT

9

72

OUT

9

72

OUT

XDP

R1303

1K

1 2

FSB_CPURST_L

5%

PLACEMENT_NOTE=Place close to CPU to minimize stub.

1/16W
MF-LF

402

9

13 72

IN

C

B

Direction of XDP module

Please avoid any obstructions

on even-numbered side of J1300

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

eXtended Debug Port (mini-XDP)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

13 OF 109

SHEET

12 OF 80

SIZE

A

D

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

FSB_DSTB_L_P<0>

6 9

72

BI

FSB_DSTB_L_N<0>

6 9

72

BI

FSB_DINV_L<0>

6 9

72

BI

FSB_DSTB_L_P<1>

6 9

72

BI

FSB_DSTB_L_N<1>

6 9

72

BI

FSB_DINV_L<1>

6 9

72

BI

FSB_DSTB_L_P<2>

6 9

72

D

C

B

=PP1V05_S0_MCP_FSB

7

13 19 22

1

1

9

40 72

IN

9

72

IN

8

IN

8

IN

8

IN

R1410

PM_THRMTRIP_L
CPU_FERR_L

=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>

54.9

1%
1/16W
MF-LF

402

R1430

49.9

1/16W
MF-LF

2

402

1%

121

R1415

62

5%
1/16W
MF-LF
402

2

R1435

49.9

1%
1/16W
MF-LF
402

2

A

121

R1431

49.9

1/16W
MF-LF

R1436

49.9

1%

1%

1/16W
MF-LF
402

402

2

BI

FSB_DSTB_L_N<2>

6 9

72

BI

FSB_DINV_L<2>

6 9

72

BI

FSB_DSTB_L_P<3>

6 9

72

BI

FSB_DSTB_L_N<3>

6 9

72

BI

FSB_DINV_L<3>

6 9

72

BI

FSB_A_L<3>

6 9

72

BI

FSB_A_L<4>

6 9

72

BI

FSB_A_L<5>

6 9

72

BI

FSB_A_L<6>

6 9

72

BI

FSB_A_L<7>

6 9

72

BI

FSB_A_L<8>

6 9

72

BI

FSB_A_L<9>

6 9

72

BI

FSB_A_L<10>

6 9

72

BI

FSB_A_L<11>

6 9

72

BI

FSB_A_L<12>

6 9

72

BI

FSB_A_L<13>

6 9

72

BI

FSB_A_L<14>

6 9

72

BI

FSB_A_L<15>

6 9

72

BI

FSB_A_L<16>

6 9

72

BI

FSB_A_L<17>

6 9

72

BI

FSB_A_L<18>

6 9

72

BI

FSB_A_L<19>

6 9

72

BI

FSB_A_L<20>

6 9

72

BI

FSB_A_L<21>

6 9

72

BI

FSB_A_L<22>

6 9

72

BI

FSB_A_L<23>

6 9

72

BI

FSB_A_L<24>

6 9

72

BI

FSB_A_L<25>

6 9

72

BI

FSB_A_L<26>

6 9

72

BI

FSB_A_L<27>

6 9

72

BI

FSB_A_L<28>

6 9

72

BI

FSB_A_L<29>

6 9

72

BI

FSB_A_L<30>

6 9

72

BI

FSB_A_L<31>

6 9

72

BI

FSB_A_L<32>

6 9

72

BI

FSB_A_L<33>

6 9

72

BI

FSB_A_L<34>

6 9

72

BI

FSB_A_L<35>

6 9

72

BI

FSB_ADSTB_L<0>

6 9

72

BI

FSB_ADSTB_L<1>

6 9

72

BI

FSB_REQ_L<0>

6 9

72

BI

FSB_REQ_L<1>

6 9

72

BI

FSB_REQ_L<2>

6 9

72

BI

FSB_REQ_L<3>

6 9

72

BI

FSB_REQ_L<4>

6 9

72

BI

FSB_ADS_L

6 9

72

IN

FSB_BNR_L

9

72

IN

FSB_BREQ0_L

9

72

IN

FSB_DBSY_L

9

72

IN

FSB_DRDY_L

9

72

IN

FSB_HIT_L

6 9

72

IN

FSB_HITM_L

6 9

72

IN

FSB_LOCK_L

6 9

72

IN

FSB_TRDY_L

9

72

BI

CPU_PECI_MCP

8

OUT

CPU_PROCHOT_L

40 61 72

9

OUT

FSB_RS_L<0>

9

72

OUT

FSB_RS_L<1>

9

72

OUT

FSB_RS_L<2>

9

72

OUT

MCP_BCLK_VML_COMP_VDD

72

MCP_BCLK_VML_COMP_GND

72

MCP_CPU_COMP_VCC

72

MCP_CPU_COMP_GND

72

K34

CPU_DSTBP0*

K35

CPU_DSTBN0*

L37

CPU_DBI0*

T31

CPU_DSTBP1*

T30

CPU_DSTBN1*

P28

CPU_DBI1*

K33

CPU_DSTBP2*

K32

CPU_DSTBN2*

N35

CPU_DBI2*

C36

CPU_DSTBP3*

D36

CPU_DSTBN3*

A35

CPU_DBI3*

U38

CPU_A3*

U34

CPU_A4*

U35

CPU_A5*

T34

CPU_A6*

W37

CPU_A7*

W38

CPU_A8*

T37

CPU_A9*

Y38

CPU_A10*

W35

CPU_A11*

Y36

CPU_A12*

U33

CPU_A13*

W34

CPU_A14*

Y37

CPU_A15*

Y35

CPU_A16*

AF38

CPU_A17*

AB35

CPU_A18*

Y34

CPU_A19*

AE38

CPU_A20*

AC36

CPU_A21*

AF36

CPU_A22*

AC38

CPU_A23*

AB36

CPU_A24*

AB38

CPU_A25*

AB37

CPU_A26*

AC34

CPU_A27*

AE36

CPU_A28*

AF37

CPU_A29*

AC37

CPU_A30*

AC35

CPU_A31*

AE37

CPU_A32*

AE35

CPU_A33*

AE33

CPU_A34*

AE34

CPU_A35*

W36

CPU_ADSTB0*

AB34

CPU_ADSTB1*

U36

CPU_REQ0*

T36

CPU_REQ1*

U37

CPU_REQ2*

T38

CPU_REQ3*

T35

CPU_REQ4*

AE31

CPU_ADS*

AE32

CPU_BNR*

AE30

CPU_BR0*

AE29

CPU_DBSY*

U29

CPU_DRDY*

W32

CPU_HIT*

AB31

CPU_HITM*

AC32

CPU_LOCK*

AC29

CPU_TRDY*

AH34

CPU_PECI

U28

CPU_PROCHOT*

W33

CPU_THERMTRIP*

AB32

CPU_FERR*

B34

CPU_BSEL2

C34

CPU_BSEL1

A34

CPU_BSEL0

AB29

CPU_RS0*

AC33

CPU_RS1*

AC31

CPU_RS2*

AH37

BCLK_VML_COMP_VDD

AH38

BCLK_VML_COMP_GND

AH36

CPU_COMP_VCC

AH35

CPU_COMP_GND

8 7 5 4 2 1

(1 OF 11)

FSB

CPU_D0*
CPU_D1*
CPU_D2*
CPU_D3*
CPU_D4*
CPU_D5*
CPU_D6*
CPU_D7*
CPU_D8*

CPU_D9*
CPU_D10*
CPU_D11*
CPU_D12*
CPU_D13*
CPU_D14*
CPU_D15*
CPU_D16*
CPU_D17*
CPU_D18*
CPU_D19*
CPU_D20*
CPU_D21*
CPU_D22*
CPU_D23*
CPU_D24*
CPU_D25*
CPU_D26*
CPU_D27*
CPU_D28*
CPU_D29*
CPU_D30*
CPU_D31*
CPU_D32*
CPU_D33*
CPU_D34*
CPU_D35*
CPU_D36*
CPU_D37*
CPU_D38*
CPU_D39*
CPU_D40*
CPU_D41*
CPU_D42*
CPU_D43*
CPU_D44*
CPU_D45*
CPU_D46*
CPU_D47*
CPU_D48*
CPU_D49*
CPU_D50*
CPU_D51*
CPU_D52*
CPU_D53*
CPU_D54*
CPU_D55*
CPU_D56*
CPU_D57*
CPU_D58*
CPU_D59*
CPU_D60*
CPU_D61*
CPU_D62*
CPU_D63*

CPU_BPRI*

CPU_DEFER*

BCLK_OUT_CPU_N
BCLK_OUT_CPU_P

BCLK_OUT_ITP_N
BCLK_OUT_ITP_P

BCLK_OUT_NB_N
BCLK_OUT_NB_P

BCLK_IN_P
BCLK_IN_N

CPU_A20M*

CPU_IGNNE*

CPU_INIT*

CPU_INTR

CPU_NMI
CPU_SMI*

CPU_PWRGD

CPU_RESET*

CPU_DPRSLPVR

CPU_SLP*

CPU_DPSLP*

CPU_DPWR*
CPU_STPCLK*
CPU_DPRSTP*

N38
N36
P36
L36
N34
L35
P37
P38
H36
L34
K37
K36
K38
N37
H37
L38
N28
U30
N29
P34
T29
T32
U32
T33
P31
P30
N30
P33
N31
T28
P35
P29
H33
G34
L30
L31
L33
P32
N32
N33
H35
K31
H34
K30
L32
G33
H32
G35
C37
D37
H38
G38
G37
G36
B35
E35
B36
E36
C35
D34
E38
D38
E34
E37

Y31
Y30

AF32
AF33

AF35
AF34

AF28
AF29

AF30
AF31

W30
AB30
AB28
W31
AC30
AC28
Y32
AE28
G1
Y33
AB33
U31
Y29
W29

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

FSB_BPRI_L
FSB_DEFER_L

FSB_CLK_CPU_N
FSB_CLK_CPU_P

FSB_CLK_ITP_N
FSB_CLK_ITP_P

FSB_CLK_MCP_N

72

FSB_CLK_MCP_P

72

CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
PM_DPRSLPVR
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

6 9

72

BI

9

72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

12 72

OUT

12 72

OUT

Loop-back clock for delay matching.

9

72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

9

12 72

OUT

61 72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

9

72

OUT

9

61 72

OUT

=PP1V05_S0_MCP_FSB

NO STUFF

1

R1440

150

5%
1/16W
MF-LF
402

2

9

12 72

OUT

36

7

13 19 22

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP CPU Interface

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/05/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

14 OF 109

SHEET

13 OF 80

SIZE

D

C

B

A

D

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0

MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0

(2 OF 11)

MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N

MEMORY PARTITION 0

+VIO_M2CLK_DLL_1
+VIO_M2CLK_DLL_2

+VIO_PLL_MEM_1
+VIO_PLL_MEM_2

+VIO_PLL_FSB_1
+VIO_PLL_FSB_2

+VIO_PLL_CPU_1
+VIO_PLL_CPU_2
+VIO_PLL_CPU_3
+VIO_PLL_CPU_4

MCLK0A_1_P
MCLK0A_1_N

MCLK0A_0_P
MCLK0A_0_N

AK11
AL11
AH13
AH14
AL10
AK10
AN11
AJ13
AK13
AK14
AJ16
AH16
AJ14
AL13
AM14
AN14
AK17
AL17
AN17
AJ19
AH17
AJ17
AM16
AM17
AN26
AH29
AK29
AL29
AM25
AM26
AL28
AK28
AM28
AP29
AL31
AN32
AP28
AN28
AN31
AM31
AR34
AM32
AL33
AL35
AP32
AP33
AM35
AL32
AJ35
AJ31
AH32
AH33
AJ34
AL34
AJ33
AJ32

AM11
AL14
AN16
AJ29
AP31
AM34
AJ30

AP5
AP7
AR8
AP8
AR4
AR5
AM8
AN8

AR7

MEM_A_DQ<63>

27 73

BI

MEM_A_DQ<62>

27 73

BI

MEM_A_DQ<61>

27 73

BI

MEM_A_DQ<60>

27 73

BI

MEM_A_DQ<59>

27 73

D

C

B

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

OUT

27 73

OUT

27 73

OUT

27 73

OUT

27 73

OUT

27 73

OUT

27 73

OUT

27 73

OUT

MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>

MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>

MRAS0*
MCAS0*

MWE0*

MBA0_2
MBA0_1
MBA0_0

MA0_15
MA0_14
MA0_13
MA0_12
MA0_11
MA0_10

MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0

MCS0A_1*
MCS0A_0*

MODT0A_1
MODT0A_0

MCKE0A_1
MCKE0A_0

AN7
AM7
AN10
AM10
AN13
AM13
AL16
AK16
AH28
AJ28
AM29
AN29
AP34
AP35
AH31
AG31

AN19
AL19
AL20

AL25
AN20
AM19

AK26
AK25
AJ20
AJ26
AH25
AM20
AH26
AN23
AJ25
AM22
AM23
AN22
AL23
AK22
AK23
AL22

AF24
AG25

AF25
AG26

AF26
AG28

AC26
AD26
AE26
AF27

AH23
AJ23

AJ22
AH22

AH19
AK20

AH20
AK19

AL26
AN25

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>

MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>

=PP1V05_S0_MCP_M2CLK_DLL

PP1V05_S0_MCP_PLL_FSBMEM

20 mA

25 mA

25 mA

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_ODT<1>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CKE<0>

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73 26 73

OUT OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

25 73

OUT

7

70 mA

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

22

25 73

25 73

25 73

25 73

25 73

25 73

25 73

25 73

20 25 73

20 25 73

22

=PP1V5R1V35_SW_MCP_MEM

19 20 22

1

R1510

40.2

1%
1/16W
MF-LF

402

2

1

R1511

40.2

1%
1/16W
MF-LF

402

2

550 mA

MEM_B_DQ<63>

27 73

BI

MEM_B_DQ<62>

27 73

BI

MEM_B_DQ<61>

27 73

BI

MEM_B_DQ<60>

27 73

BI

MEM_B_DQ<59>

27 73

BI

MEM_B_DQ<58>

27 73

BI

MEM_B_DQ<57>

27 73

BI

MEM_B_DQ<56>

27 73

BI

MEM_B_DQ<55>

27 73

BI

MEM_B_DQ<54>

27 73

BI

MEM_B_DQ<53>

27 73

BI

MEM_B_DQ<52>

27 73

BI

MEM_B_DQ<51>

27 73

BI

MEM_B_DQ<50>

27 73

BI

MEM_B_DQ<49>

27 73

BI

MEM_B_DQ<48>

27 73

BI

MEM_B_DQ<47>

27 73

BI

MEM_B_DQ<46>

27 73

BI

MEM_B_DQ<45>

27 73

BI

MEM_B_DQ<44>

27 73

BI

MEM_B_DQ<43>

27 73

BI

MEM_B_DQ<42>

27 73

BI

MEM_B_DQ<41>

27 73

BI

MEM_B_DQ<40>

27 73

BI

MEM_B_DQ<39>

27 73

BI

MEM_B_DQ<38>

27 73

BI

MEM_B_DQ<37>

27 73

BI

MEM_B_DQ<36>

27 73

BI

MEM_B_DQ<35>

27 73

BI

MEM_B_DQ<34>

27 73

BI

MEM_B_DQ<33>

27 73

BI

MEM_B_DQ<32>

27 73

BI

MEM_B_DQ<31>

27 73

BI

MEM_B_DQ<30>

27 73

BI

MEM_B_DQ<29>

27 73

BI

MEM_B_DQ<28>

27 73

BI

MEM_B_DQ<27>

27 73

BI

MEM_B_DQ<26>

27 73

BI

MEM_B_DQ<25>

27 73

BI

MEM_B_DQ<24>

27 73

BI

MEM_B_DQ<23>

27 73

BI

MEM_B_DQ<22>

27 73

BI

MEM_B_DQ<21>

27 73

BI

MEM_B_DQ<20>

27 73

BI

MEM_B_DQ<19>

27 73

BI

MEM_B_DQ<18>

27 73

BI

MEM_B_DQ<17>

27 73

BI

MEM_B_DQ<16>

27 73

BI

MEM_B_DQ<15>

27 73

BI

MEM_B_DQ<14>

27 73

BI

MEM_B_DQ<13>

27 73

BI

MEM_B_DQ<12>

27 73

BI

MEM_B_DQ<11>

27 73

BI

MEM_B_DQ<10>

27 73

BI

MEM_B_DQ<9>

27 73

BI

MEM_B_DQ<8>

27 73

BI

MEM_B_DQ<7>

27 73

BI

MEM_B_DQ<6>

27 73

BI

MEM_B_DQ<5>

27 73

BI

MEM_B_DQ<4>

27 73

BI

MEM_B_DQ<3>

27 73

BI

MEM_B_DQ<2>

27 73

BI

MEM_B_DQ<1>

27 73

BI

MEM_B_DQ<0>

27 73

BI

MEM_B_DM<7>

27 73

OUT

MEM_B_DM<6>

27 73

OUT

MEM_B_DM<5>

27 73

OUT

MEM_B_DM<4>

27 73

OUT

MEM_B_DM<3>

27 73

OUT

MEM_B_DM<2>

27 73

OUT

MEM_B_DM<1>

27 73

OUT

MEM_B_DM<0>

27 73

OUT

MCP_MEM_COMP_GND

73

MCP_MEM_COMP_VDD

73

AP1
AR3
AV4
AU4
AP3
AP2
AU3
AT4
AT5
AT7
AU8

AR10

AV5
AU5

AP10

AT8
AT10
AU10
AR13
AR14
AR11
AP11
AT11
AP13
AV14
AU14
AR17
AP17
AP14
AT13
AP16
AR16
AU26
AT26
AU29
AT29
AV25
AV26
AV28
AV29
AT31
AR32
AT34
AU34
AR29
AR31
AU32
AT32
AV35
AT35
AR37
AP38
AV34
AU35
AR36
AR38
AM36
AM37
AJ36
AL36
AP37
AP36
AJ38
AJ37

AT2

AU7
AV10
AT14
AR28
AV32
AT37
AM38

AG23
AG22

MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0

MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0

MEM_COMP_GND
MEM_COMP_VDD

OMIT

U1400

MCP89M-A01

FBGA

(3 OF 11)

MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N

MRAS1*
MCAS1*

MWE1*

MBA1_2
MBA1_1
MBA1_0

MA1_15
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10

MA1_9
MA1_8
MA1_7
MA1_6

MEMORY PARTITION 1

MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

MRESET0*

MCLK1A_1_P
MCLK1A_1_N

MCLK1A_0_P
MCLK1A_0_N

MCS1A_1*
MCS1A_0*

MODT1A_1
MODT1A_0

MCKE1A_1
MCKE1A_0

AR2
AR1
AV7
AV8
AU11
AV11
AU13
AV13
AT28
AU28
AU31
AV31
AU36
AT36
AL38
AL37

AR19
AU17
AT17

AR25
AT19
AR20

AP26
AR26
AV16
AP25
AT23
AP20
AU23
AV22
AV23
AT22
AU22
AP23
AR23
AP22
AR22
AT20

AP4

AU20
AV20

AU19
AV19

AU16
AP19

AT16
AV17

AU25
AT25

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>

MEM_B_A<15>
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>

=PP1V5R1V35_S3_MCP_MEM

1

R1520

1K

5%
1/16W
MF-LF
402

2

MEM_RESET_L

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_ODT<1>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CKE<0>

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

27 73

BI

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

7

25 26

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

26 73

OUT

20 26 73

OUT

20 26 73

OUT

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Memory Interface

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/06/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

15 OF 109

SHEET

14 OF 80

36

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

PEG_CLKREQ_L

8

IN

AP_CLKREQ_L

29

D

C

IN

ENET_CLKREQ_L

31

IN

FW_CLKREQ_L

34

IN

FW_PWR_EN

34

OUT

FW_PME_L

34

IN

PCIE_WAKE_L

6

24 29

IN

=PEG_D2R_P<0>

8

IN

=PEG_D2R_N<0>

8

IN

=PEG_D2R_P<1>

8

IN

=PEG_D2R_N<1>

8

IN

=PEG_D2R_P<2>

8

IN

=PEG_D2R_N<2>

8

IN

=PEG_D2R_P<3>

8

IN

=PEG_D2R_N<3>

8

IN

TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN

PCIE_FW_D2R_P

33 74

IN

PCIE_FW_D2R_N

33 74

IN

PCIE_AP_D2R_P

6

29 74

IN

PCIE_AP_D2R_N

6

29 74

IN

PCIE_ENET_D2R_P

31 74

IN

PCIE_ENET_D2R_N

31 74

IN

PP3V3_S0_MCP_PLL_HVDD

22

50 mA

PP1V05_S0_MCP_PLL_PEXSATA

22

325 mA

100 mA

80 mA

120 mA

25 mA

W4

PEA_CLKREQ*/GPIO_49

(IPU)

W5

PEB_CLKREQ*/GPIO_50

(IPU)

W7

PEC_CLKREQ*/GPIO_51

(IPU)

W8

PED_CLKREQ*/GPIO_52

(IPU)

W6

PEE_CLKREQ*/GPIO_53

(IPU)

W9

PEF_CLKREQ*/GPIO_54

(IPU)

U3

PE_WAKE*

(IPU-S5)

AC1

PE0_RX0_P

AB1

PE0_RX0_N

AC5

PE0_RX1_P

AC4

PE0_RX1_N

AC10

PE0_RX2_P

AC11

PE0_RX2_N

AB7

PE0_RX3_P

AB6

PE0_RX3_N

AB9

PE0_RX4_P

AB8

PE0_RX4_N

Y2

PE0_RX5_P

Y3

PE0_RX5_N

AB11

PE1_RX0_P

AB10

PE1_RX0_N

Y10

PE1_RX1_P

Y11

PE1_RX1_N

V11

+3.3V_PLL_HVDD_1

V13

+3.3V_PLL_HVDD_2

AH10

+VIO_PLL_PE

AG11

+VIO_PLL_XREF_XS_1

AF12

+VIO_PLL_XREF_XS_2

AF13

+VIO_PLL_XREF_XS_3

AH8

+VIO_PLL_SATA_1

AH9

+VIO_PLL_SATA_2

AH11

+VIO_PLL_H

(4 OF 11)

PE0_REFCLK_P
PE0_REFCLK_N

PE1_REFCLK_P
PE1_REFCLK_N

PE2_REFCLK_P
PE2_REFCLK_N

PE3_REFCLK_P
PE3_REFCLK_N

PE4_REFCLK_P
PE4_REFCLK_N

PE5_REFCLK_P
PE5_REFCLK_N

PCI EXPRESS

(IPD)

PEX0_TERM_P

PE0_TX0_P
PE0_TX0_N

PE0_TX1_P
PE0_TX1_N

PE0_TX2_P
PE0_TX2_N

PE0_TX3_P
PE0_TX3_N

PE0_TX4_P
PE0_TX4_N

PE0_TX5_P
PE0_TX5_N

PE1_TX0_P
PE1_TX0_N

PE1_TX1_P
PE1_TX1_N

B

PEX_RST*

Y1
W1

W3
W2

U4
U5

U7
U6

U9
U8

W10
W11

AC3
AC2

AB2
AB3

AC6
AC7

AC8
AC9

AB4
AB5

Y5
Y4

Y7
Y6

Y9
Y8

U1

U2

PEG_CLK100M_P
PEG_CLK100M_N

PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N

PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N

PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N

TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N

=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>

=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>

=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>

=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>

TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN

PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N

PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N

PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N

PCIE_RESET_L

NO STUFF

1

R1600

10K

5%
1/16W
MF-LF
402

2

MCP_PEX0_TERMP

74

PLACE_NEAR=U1400.U2:12.7 mm

R1610

2.49K

1/16W
MF-LF

8

74

OUT

8

74

OUT

29 74

OUT

29 74

OUT

31 74

OUT

31 74

OUT

33 74

OUT

33 74

OUT

PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1
PE1 ports are Gen1-only. 2 RCs: x1, x1

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

33 74

OUT

33 74

OUT

29 74

OUT

29 74

OUT

31 74

OUT

31 74

OUT

18 24

OUT

1

1%

402

2

If PE0[3:0] are not used,
+VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND

If PE0[4:5] and PE1[0:1] are not used,
+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP PCIe Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/05/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

16 OF 109

SHEET

15 OF 80

36

345678

2 1

OMIT

D

PP3V3_S0_MCP_DAC

23

140 mA

TP_MCP_RGB_DAC_RSET

8

TP_MCP_RGB_DAC_VREF

8

DP_IG_ML0_P<3>

8

OUT

DP_IG_ML0_N<3>

8

OUT

DP_IG_ML0_P<2>

8

OUT

DP_IG_ML0_N<2>

8

OUT

DP_IG_ML0_P<1>

8

OUT

DP_IG_ML0_N<1>

8

OUT

DP_IG_ML0_P<0>

8

OUT

DP_IG_ML0_N<0>

8

OUT

DP_IG_ML1_P<3>

8

OUT

DP_IG_ML1_N<3>

8

OUT

DP_IG_ML1_P<2>

8

OUT

DP_IG_ML1_N<2>

8

C

NOTE: 100K pull-downs required if
HPLUG_DET0/HPLUG_DET1 are not used.

OUT

DP_IG_ML1_P<1>

8

OUT

DP_IG_ML1_N<1>

8

OUT

DP_IG_ML1_P<0>

8

OUT

DP_IG_ML1_N<0>

8

OUT

DP_IG_HPD0

8

IN

DP_IG_HPD1

8

IN

SATARDRVR_A_EN

16 36

OUT

DP_IG_AUX_CH0_P

8

16

BI

DP_IG_AUX_CH0_N

16

8

BI

DP_IG_AUX_CH1_P

8

BI

DP_IG_AUX_CH1_N

8

BI

PP3V3_S0_MCP_PLL_DP_USB

22

210 mA

180 mA

30 mA

=PP1V05_S0_MCP_PLL_IFP

7

23

60 mA

PP1V05_S0_MCP_PLL_CORE

22

160 mA

B

=PP3V3R1V8_S0_MCP_IFP_VDD

7

23

180 mA

=PP1V05_S0_MCP_DP0_VDD

23

7

160 mA

40 mA
60 mA

40 mA
20 mA

B29

+3.3V_RGBDAC

C29

RGB_DAC_RSET

D29

RGB_DAC_VREF

D26

DP0_3_P/TMDS0_TXC_P

E26

DP0_3_N/TMDS0_TXC_N

G26

DP0_2_P/TMDS0_TX0_P

F26

DP0_2_N/TMDS0_TX0_N

F25

DP0_1_P/TMDS0_TX1_P

G25

DP0_1_N/TMDS0_TX1_N

E25

DP0_0_P/TMDS0_TX2_P

D25

DP0_0_N/TMDS0_TX2_N

F28

DP1_3_P/TMDS0B_TXC_P

G28

DP1_3_N/TMDS0B_TXC_N

E28

DP1_2_P/TMDS0_TX3_P

D28

DP1_2_N/TMDS0_TX3_N

A28

DP1_1_P/TMDS0_TX4_P

A29

DP1_1_N/TMDS0_TX4_N

C28

DP1_0_P/TMDS0_TX5_P

B28

DP1_0_N/TMDS0_TX5_N

H26

HPLUG_DET0/GPIO_20

J26

HPLUG_DET1/GPIO_21

J25

HPLUG_DET2/GPIO_22

L28

DDC_CLK2/DP_AUX_CH0_P

K28

DDC_DATA2/DP_AUX_CH0_N

K25

DDC_CLK3/DP_AUX_CH1_P

K26

DDC_DATA3/DP_AUX_CH1_N

M23

+3.3V_PLL_DP0_1

N22

+3.3V_PLL_DP0_2

N21

+3.3V_PLL_USB_1

M22

+3.3V_PLL_USB_2

N23

+VIO_PLL_IFPAB_1

L24

+VIO_PLL_IFPAB_2

M25

+VIO_PLL_CORE_LEG

N25

+VIO_PLL_SPPLL0_1

L26

+VIO_PLL_SPPLL0_2

M26

+VIO_PLL_V

N24

+VIO_PLL_NV_1

L25

+VIO_PLL_NV_2

A22

+VDD_IFPA

A23

+VDD_IFPB

A26

+VIO_DP0_1

B26

+VIO_DP0_2

C26

+VIO_DP0_3

U1400

MCP89M-A01

FBGA

(5 OF 11)

RGB

LCD_BKL_CTL/GPIO_57

LCD_PANEL_PWR/GPIO_58

DDC_CLK0/GPIO_38

DDC_DATA0/GPIO_39

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC
RGB_DAC_VSYNC

IFPA_TXC_P
IFPA_TXC_N

IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N

FLAT PANEL

IFPB_TXD7_P
IFPB_TXD7_N

DDC_CLK1/GPIO_40

DDC_DATA1/GPIO_41

LCD_BKL_ON/GPIO_59

IFPAB_VPROBE

IFPAB_RSET

TMDS0_VPROBE

TMDS0_RSET

F29
H25

C31
B31
A31

D31
E31

K22
L22

C22
B22
E22
D22
F22
G22
H22
J22

B23
C23

L23
K23
J23
H23
G23
F23
D23
E23

J28
G29

A25
B25
C25

L20

K20

H28

F31

AUD_IP_PERIPHERAL_DET
MIKEY_MIC_LOAD_DET

TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC

=MCP_IFPA_TXC_P
=MCP_IFPA_TXC_N

=MCP_IFPA_TXD_P<0>
=MCP_IFPA_TXD_N<0>
=MCP_IFPA_TXD_P<1>
=MCP_IFPA_TXD_N<1>
=MCP_IFPA_TXD_P<2>
=MCP_IFPA_TXD_N<2>
=MCP_IFPA_TXD_P<3>
=MCP_IFPA_TXD_N<3>

=MCP_IFPB_TXC_P
=MCP_IFPB_TXC_N

=MCP_IFPB_TXD_P<0>
=MCP_IFPB_TXD_N<0>
=MCP_IFPB_TXD_P<1>
=MCP_IFPB_TXD_N<1>
=MCP_IFPB_TXD_P<2>
=MCP_IFPB_TXD_N<2>
=MCP_IFPB_TXD_P<3>
=MCP_IFPB_TXD_N<3>

=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA

(GMUX_INT)
LCD_IG_BKLT_PWM
LCD_IG_BKLT_EN
LCD_IG_PWR_EN

MCP_IFPAB_VPROBE
MCP_IFPAB_RSET

MCP_TMDS0_VPROBE
MCP_TMDS0_RSET

16 56

IN

16

IN

8

8

8

8

8

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

BI

8

OUT

8

OUT

67

OUT

23 74

OUT

23 74

OUT

23 74

OUT

23 74

OUT

RGB DAC Disable:
Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).
Connect +3.3V_RGBDAC pin to GND.

NOTE: No Composite/S-Video/Component Video support on MCP89

Interface Mode
MCP Signal
=MCP_IFPA_TXC_P/N

=MCP_IFPA_TXD_P/N<0>
=MCP_IFPA_TXD_P/N<1>
=MCP_IFPA_TXD_P/N<2>
=MCP_IFPA_TXD_P/N<3>
=MCP_IFPB_TXC_P/N
=MCP_IFPB_TXD_P/N<0>
=MCP_IFPB_TXD_P/N<1>
=MCP_IFPB_TXD_P/N<2>
=MCP_IFPB_TXD_P/N<3>
=MCP_IFPAB_DDC_CLK
=MCP_IFPAB_DDC_DATA

LVDS: Power +VDD_IFPx at 1.8V
TMDS: Power +VDD_IFPx at 3.3V

TMDS/HDMI
TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
(UNUSED)
(UNUSED)
TMDS_IG_TXD_P/N<3>
TMDS_IG_TXD_P/N<4>
TMDS_IG_TXD_P/N<5>
(UNUSED)
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA

LVDS
LVDS_IG_A_CLK_P/N

LVDS_IG_A_DATA_P/N<0>
LVDS_IG_A_DATA_P/N<1>
LVDS_IG_A_DATA_P/N<2>
LVDS_IG_A_DATA_P/N<3>
LVDS_IG_B_CLK_P/N
LVDS_IG_B_DATA_P/N<0>
LVDS_IG_B_DATA_P/N<1>
LVDS_IG_B_DATA_P/N<2>
LVDS_IG_B_DATA_P/N<3>
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA

D

C

B

DDC Mode Pull-downs

NOTE: DP_AUX_CH1 also requires pull-downs if used for
dual-mode DisplayPort (DP++). If unused no pulls
are necessary, if used for TMDS/HDMI only then
only pull-ups are necessary.

100K
100K

1 2
1 2

5%
5%

1/16W

MF-LF

MF-LF

1/16W

DP_IG_AUX_CH0_P

402

DP_IG_AUX_CH0_N

402

8

16

8

16

R1710
R1711

A

GPIO Pull-Ups

=PP3V3_S0_MCP_GPIO

10K

R1780
R1781
R1782

10K
10K

1 2
1 2
1 2

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

7

17 18

MF-LF

1/16W

5%
5%
5%

1/16W
1/16W

MF-LF
MF-LF

SATARDRVR_A_EN

402

AUD_IP_PERIPHERAL_DET

402

MIKEY_MIC_LOAD_DET

402

16 36

16 56

16

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Graphics

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/05/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

17 OF 109

SHEET

16 OF 80

36

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

SATA_HDD_R2D_C_P

36 74

OUT

SATA_HDD_R2D_C_N

36 74

OUT

SATA_HDD_D2R_N

36 74

IN

SATA_HDD_D2R_P

36 74

D

=PP3V3_S0_MCP_GPIO

7

16 18

1

R1800

100K

5%
1/16W
MF-LF

R1810

49.9

1/16W
MF-LF

402

2

1

1%

402

2

C

MXM_GOOD_L

=PP3V3_ENET_MCP_RMGT

7

19 22

B

1

R1811

49.9

1%
1/16W
MF-LF

402

2

IN

SATA_ODD_R2D_C_P

36 74

OUT

SATA_ODD_R2D_C_N

36 74

OUT

SATA_ODD_D2R_N

36 74

IN

SATA_ODD_D2R_P

36 74

IN

TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN

TP_SATA_C_D2RN
TP_SATA_C_D2RP

TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN

TP_SATA_D_D2RN
TP_SATA_D_D2RP

74

MCP_SATA_TERMP

1

R1805

2.49K

1%
1/16W
MF-LF
402

2

ENET_RXD<0>

8

76

IN

ENET_RXD<1>

8

76

IN

ENET_RXD<2>

8

76

IN

ENET_RXD<3>

8

76

IN

ENET_CLK125M_RXCLK

8

76

IN

ENET_RX_CTRL

8

76

IN

ENET_ENERGY_DET

31

IN

PP3V3_ENET_MCP_PLL_MAC

22

20 mA

76

MCP_MII_COMP_VDD

76

MCP_MII_COMP_GND

AH4

SATA_A0_TX_P

AH5

SATA_A0_TX_N

AJ4

SATA_A0_RX_N

AJ5

SATA_A0_RX_P

AJ3

SATA_A1_TX_P

AJ2

SATA_A1_TX_N

AH2

SATA_A1_RX_N

AH3

SATA_A1_RX_P

AJ6

SATA_B0_TX_P

AJ7

SATA_B0_TX_N

AH7

SATA_B0_RX_N

AH6

SATA_B0_RX_P

AL4

SATA_B1_TX_P

AL3

SATA_B1_TX_N

AL1

SATA_B1_RX_N

AL2

SATA_B1_RX_P

AH1

SATA_LED*/GPIO_30

AJ1

SATA_TERMP

G4

NC_1

NC

E7

NC_2

NC

F7

NC_3

NC

F4

NC_4

NC

B14

RGMII_RXD0

C14

RGMII_RXD1

D16

RGMII_RXD2

F16

RGMII_RXD3

E16

RGMII_RXCLK

A14

RGMII_RXCTL

H14

RGMII_INTR/GPIO_35

M16

+3.3V_PLL_MAC_DUAL

D13

RGMII_COMP_VDD

E13

RGMII_COMP_GND

Internal MAC Disable:
Connect RGMII_RXD<0:3> together to 10K pull-down.

Connect RGMII_RXCLK to 10K pull-down.
Connect RGMII_RXCTL to 10K pull-down.
Connect RGMII_INTR to 10K pull-down (if not used as GPIO).
+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail.
RGMII_COMP_VDD/_GND must remain connected as shown.
Connect RGMII_VREF to 10K pull-down.
Connect RGMII_MDIO to 10K pull-down.
All other pins can be left TP or NC.

(6 OF 11)

USB

SATA

Internal 19.5K Pull-Downs on all USB pairs

USB JTAG in S3/S4/S5.

Only USB8-11 support nV

USB_OC0*/GPIO_25

USB_OC1*/GPIO_26
USB_OC2*/GPIO_27_MGPIO_0
USB_OC3*/GPIO_28_MGPIO_1

USB_RBIAS_GND

RGMII_TXCLK
RGMII_TXCTL

LAN

RGMII_RESET*

USB0_N
USB0_P

USB1_P
USB1_N

USB2_P
USB2_N

USB3_P
USB3_N

OHCI0/EHCI0OHCI1/EHCI1

USB4_P
USB4_N

USB5_P
USB5_N

USB6_P
USB6_N

USB7_P
USB7_N

USB8_P
USB8_N

USB9_P
USB9_N

USB10_P
USB10_N

USB11_N
USB11_P

RGMII_VREF

RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3

RGMII_MDC

RGMII_MDIO

BUF_25MHZ

External A

C20
B20

J20
H20

C19
B19

G20
F20

E20
D20

E19
D19

G19
F19

J17
H17

J19
H19

C17
B17

E17
D17

G17
F17

A17
L17
K17
K19

L19

C13

G13
H13
F14
D14

G14
E14

F13
K13

J13

J14

USB_EXTA_N
USB_EXTA_P

AirPort (PCIe Mini-Card)

USB_MINI_P
USB_MINI_N

T57

NC_USB_T57_P
NC_USB_T57_N

External C

USB_EXTC_P
USB_EXTC_N

Watermelon

USB_WM_P
USB_WM_N

Camera/External E

USB_CAMERA_P
USB_CAMERA_N

SD Card/ExpressCard

USB_SDCARD_P
USB_SDCARD_N

External D

USB_EXTD_P
USB_EXTD_N

Geyser Trackpad/Keyboard

USB_TPAD_P
USB_TPAD_N

External B

USB_EXTB_P
USB_EXTB_N

IR

USB_IR_P
USB_IR_N

Bluetooth

USB_BT_N
USB_BT_P

75

MCP_USB_RBIAS_GND

MCP_RGMII_VREF

TP_ENET_TXD<0>
TP_ENET_TXD<1>
TP_ENET_TXD<2>
TP_ENET_TXD<3>

TP_ENET_CLK125M_TXCLK
TP_ENET_TX_CTRL

TP_ENET_MDC
ENET_MDIO

TP_MCP_CLK25M_BUF0_R

TP_ENET_RESET_L

37 75

BI

37 75

BI

8

75

BI

8

75

BI

BI
BI

8

75

BI

8

75

BI

8

75

BI

8

75

BI

29 75

BI

29 75

BI

30 75

BI

30 75

BI

8

75

BI

8

75

BI

47 75

BI

47 75

BI

37 75

BI

37 75

BI

38 75

BI

38 75

BI

29 75

BI

29 75

BI

8

IN

BI

R1850

8.2K

1/16W
MF-LF

8

76

1

R1851

8.2K

5%
1/16W
MF-LF
402

2

1

R1852

5%

402

2

8.2K

1/16W
MF-LF

1

R1853

8.2K

2

1

5%

402

2

1

R1860

887

2

=PP3V3_S5_MCP_GPIO

5%
1/16W
MF-LF
402

USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
USB_EXTD_OC_L

OC2# Also for EXTE
OC3# Also for EXCARD

1%
1/16W
MF-LF
402

37

37

7

18

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP SATA, USB & Ethernet

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

BRANCH

PAGE

18 OF 109

SHEET

17 OF 80

A.13.0

36

345678

2 1

=PP3V3R1V5_S0_MCP_HDA

8

D

C

HDA Output Caps

For EMI Reduction on HDA interface

HDA_SDOUT_R
HDA_BIT_CLK_R

HDA_RST_R_L
HDA_SYNC_R

B

C1950

10PF

CERM

1

5%

50V
402

C1952

2

1

C1951

10PF

2

5%
50V
CERM
402

10PF

CERM

1

5%

50V

2

402

1

C1953

10PF

5%
50V

2

CERM
402

GPIO Pull-Ups/Downs

=PP3V3_S5_MCP_GPIO
=PP3V3_S3_MCP_GPIO
=PP3V3_S0_MCP_GPIO

PCIE_RESET_L

R1980
R1981
R1999
R1986

R1983
R1984
R1985
R1987

R1988
R1989
R1990

A

R1991
R1992

R1993
R1994
R1995

R1996
R1997
R1998

10K

10K
100K
100K

10K

10K
100K
100K

10K

10K

10K

10K
100K

100K
100K
100K

10K
100K

20K

1 2
1 2

1 2

1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2

1 2

1 2

22

70 mA

LPC_AD<0>

39 41 75

BI

LPC_AD<1>

39 41 75

BI

LPC_AD<2>

39 41 75

BI

LPC_AD<3>

39 41 75

BI

NOTE: MCP89 A01 has strong (~10K)
pull-downs on these pins.

18 75

18 75

18 75

18 75

17

7

7

7

16 17 18

15 24

5%
5%
5%
5%

5%
5%
5%
5%

5% 402
5%
5%

5% 402

5%

5%

5% 402

MF-LF

1/16W

MF-LF

1/16W
1/16W MF-LF

MF-LF1/16W

1/16W MF-LF
1/16W MF-LF
1/16W MF-LF
1/16W

MF-LF

MF-LF1/16W

1/16W

MF-LF
1/16W MF-LF
1/16W MF-LF

1/16W MF-LF
1/16W MF-LF
1/16W MF-LF

MF-LF1/16W

1/16W

MF-LF

1/16W

MF-LF

MF-LF1/16W

R1910
R1911
R1912
R1913

PP3V3_G3_RTC

7

19 22

SDCARD_RESET

402

T57_RESET

402

GFXVCORE_PWR_EN

402

SPIROM_USE_MLB

402

MCP_CPU_VTT_EN_L

402

MLB_RAM_VENDOR

402

T57_PWR_EN

402

LPCPLUS_GPIO

402

ODD_PWR_EN_L
MEM_EVENT_L

402

ENET_LOW_PWR

402

SMC_IG_THROTTLE_L

4025%

MCP_VID<0>

4025%

MCP_VID<1>

4025%

MCP_VID<2>

4025%

MCP_VID<3>
AP_PWR_EN

402

ARB_DETECT_L

402

SPI_MISO

22
22

R1920

49.9K

1/16W
MF-LF

1%

402

R1900

49.9

1/16W
MF-LF

1 2
1 2
1 2
1 2

121

2

1

1%

402

2

5%
5%
5%221/16W MF-LF
5%221/16W MF-LF

R1921

49.9K

1%
1/16W
MF-LF
402

18 30

6

18

18 21

6

18 41 50

18

18

6

18

18 41

18 36

18 25 26 39

8

18 31

18 40

18 62

18 62

18 62

18 62

18 29 65

18

6

18 41 75

1/16W MF-LF

MF-LF1/16W

HDA_SDIN0

51 75

IN

AUD_IPHS_SWITCH_EN

56

OUT

Output limited to +VDD_HDA.
Confirmed OK for this signal.

MCP_HDA_PULLDN_COMP

75 18 75

LPC_AD_R<0>

402

LPC_AD_R<1>

402

LPC_AD_R<2>

402

LPC_AD_R<3>

402

TP_MLB_RAM_SIZE

PM_CLKRUN_L

39 41 24 75

IN

SMC_WAKE_SCI_L

39

IN

PM_LATRIGGER_L

12

OUT

AUD_I2C_INT_L

56

IN

SMC_RUNTIME_SCI_L

39

IN

PM_PWRBTN_L

39

IN

PM_SYSRST_DEBOUNCE_L

24

IN

RTC_RST_L

PM_RSMRST_L

39

IN

MCP_PS_PWRGD

24

IN

MCP_WAKE_REQ_L

40

OUT

PM_BATLOW_L

39

IN

MCP_MEM_VDD_EN

20 65

OUT

MCP_MEM_VTT_EN

20

OUT

SM_INTRUDER_L

SMC_IG_THROTTLE_L

18 40

OUT

T57_RESET

6

18

OUT

GFXVCORE_PWR_EN

18 21

OUT

SPIROM_USE_MLB

6

18 41 50

BI

JTAG_MCP_TDI

12

IN

JTAG_MCP_TDO

12

OUT

JTAG_MCP_TMS

12

IN

JTAG_MCP_TRST_L

12

IN

JTAG_MCP_TCK

12

IN

MCP_CLK25M_XTALIN

24

IN

MCP_CLK25M_XTALOUT

24

OUT

RTC_CLK32K_XTALIN

24

IN

RTC_CLK32K_XTALOUT

24

OUT

121

R1930

10K

5%
1/16W
MF-LF

402

D6

70 mA

R1931

100K

5%
1/16W
MF-LF
402

2

+VDD_HDA

E2

HDA_SDATA_IN0

(IPD)

E3

HDA_SDATA_IN1/GPIO_2

(IPD)

D3

HDA_PULLDN_COMP

K1

LPC_AD0

L1

LPC_AD1

L2

LPC_AD2

L3

LPC_AD3

K2

LPC_DRQ0*/GPIO_43

(IPU)

L6

LPC_CLKRUN*/GPIO_42

D11

SIO_PME*/GPIO_31

G11

EXT_SMI*/GPIO_32

B3

A20GATE/GPIO_55

H2

KBRDRSTIN*/GPIO_56

J10

PWRBTN*

F10

RSTBTN*

G16

RTC_RST*

C11

PWRGD_SB

C2

PWRGD

H16

MCP_WAKE_REQ*

A7

MCP_WAKE_DIS*

(IPU-S5)

B7

MCP_MEMVDD_EN/GPIO_44

G10

MEMVTT_EN/GPIO_45

J16

INTRUDER*

G5

MGPU_PIO0/GPIO_6

H5

MGPU_PIO1/GPIO_7

H10

MGPU_PIO2/GPIO_23

J11

MGPU_PIO3/GPIO_24

C10

JTAG_TDI

D10

JTAG_TDO

B10

JTAG_TMS

E10

JTAG_TRST*

A10

JTAG_TCK

A11

XTALIN

B11

XTALOUT

B16

XTALIN_RTC

C16

XTALOUT_RTC

Platform-Specific Connections

LPC_RESET_L

IN

PM_SLP_S4_L

6

18 39 40 65 39

IN

MAKE_BASE=TRUE

NOTE: MCP SLP_S5# signal has the
behavior of Intel’s SLP_S4# signal.

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

(IPU)
(IPU)
(IPU)
(IPU)

(IPU-S5)
(IPU-S5)

(IPU)

(IPU)

(IPD)

OMIT

U1400

MCP89M-A01

FBGA

(7 OF 11)

HDA

(IPU)

(IPU-S5)

MISC_VDDEN0/GPIO_47
MISC_VDDEN1/GPIO_48

(IPU)

MISC_VDDEN2/GPIO_17
MISC_VDDEN3/GPIO_18
MISC_VDDEN4/GPIO_19
MEM_VDD_SEL/GPIO_46

FANRPM0/GPIO_60/MGPIO_2

FANRPM1/GPIO_63/MGPIO_3

MISC LPC

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

BUF_SIO_CLK/GPIO_33

R1965

33

1 2

5%
1/16W
MF-LF

402

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET*

HDA_SYNC

LPC_SERIRQ

(IPU)

LPC_FRAME*

LPC_RESET*

(IPD)

LPC_CLK0

FANCTL0/GPIO_61

FANCTL1/GPIO_62

(IPD)

SLP_S3*

SLP_RMGT*

(IPD)

SLP_S5*

(IPD)

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15
MCP_VID3/GPIO_16

SPI_CS0*/GPIO_10

SPI_CLK/GPIO_11

SPI_DI/GPIO_08
SPI_DO/GPIO_09

SPKR/GPIO_1

THERM_DIODE_P
THERM_DIODE_N

SMB_CLK0

SMB_DATA0

SUS_CLK/GPIO_34

TEST_MODE_EN

PKG_TEST

PKG_TEST2

LPC_PWRDWN_L

PM_SLP_S5_L

E1

E4

D1

D2

L8

L7

K7

L5

K10
C8
A8
D8
G8
C7

H7
H6
G6
H4

C4
K9
D5

K3
K4
K5
K6

E11
D7
F11
B8

H3

G3
G2

A4
B4
A5
B5
C5

H1

H11

D4
L16
K16

=PP3V3_S0_MCP_GPIO

2

R1961

10K

5%
1/16W
MF-LF
402

1

HDA_SDOUT_R

18 75

18 75

HDA_BIT_CLK_R

18 75

HDA_RST_R_L

HDA_SYNC_R

LPC_SERIRQ

LPC_FRAME_R_L

LPC_RESET_L
LPC_CLK33M_SMC_R

MCP_CPU_VTT_EN_L
MLB_RAM_VENDOR
T57_PWR_EN
SMC_ADAPTER_EN
LPCPLUS_GPIO
MCP_MEM_VDD_SEL_1V5

ODD_PWR_EN_L
MEM_EVENT_L
ENET_LOW_PWR
SDCARD_RESET

PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
MCP_VID<3>

SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R

MCP_SPKR
MCP_THMDIODE_P

MCP_THMDIODE_N
SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN

ARB_DETECT_L
PM_CLK32K_SUSCLK_R

7

16 17 18

R1951

22

1 2

5%
1/16W
MF-LF

402

R1953

22

1 2

5%
1/16W
MF-LF

402

18

18

BI

IN

BI

OUT

OUT

IN

OUT

IN

OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT

IN

OUT

OUT
OUT

OUT

BI

OUT

BI

OUT

18

OUT

R1950

22

1 2

5%
1/16W
MF-LF

402

R1952

22

1 2

5%
1/16W
MF-LF

402

R1960

22

1 2

5%
1/16W
MF-LF

402

6

18

39 40 65

18 41

60

18 36

18 25 26 39

8

18 31

18 30

6

39 65 69

65

6

18 39 40 65

18 62

18 62

18 62

18 62

41 75

41 75

6

18 41 75

41 75

45 79

45 79

12 42 75

12 42 75

42 75

42 75

18 29 65

24 75

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

HDA_SYNC

LPC_FRAME_L

NOTE: MCP89 A01 has
strong (~10K)
pull-downs on
these pins.

OUT

1

R1970

10K

5%
1/16W
MF-LF
402

2

51 75

OUT

51 75

OUT

51 75

OUT

51 75

OUT

39 41

BI

39 41 75

OUT

18 24 75

OUT

OUT

BUF_SIO_CLK Frequency

Frequency

24 MHz

14.31818 MHz

BIOS Boot Select

I/F
LPC
SPI

NOTE: MCP89 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.

SPI Frequency Select

Frequency0SPI_DO

25.0 MHz

31.2 MHz

42.7 MHz

62.5 MHz

NOTE: 42 & 62 MHz use FAST_READ command.

40

MCP_SPKR:
0 = USER mode (Normal boot mode)

1 = SAFE mode (For ROMSIP recovery)
Connects to SMC for automatic recovery.

Straps not provided on this page.

HDA_SYNC

LPC_FRAME#

0
1

SPI_CLK

0
1
1

D

1
0

C

0
1
0
1

B

MCP_TEST_MODE_EN

1

R1959

10K

5%
1/16W
MF-LF
402

2

39 41 18 24 75

OUT

OUT

NO STUFF

1

R1966

10K

5%
1/16W
MF-LF
402

2

1

R1975

1K

1%
1/16W
MF-LF
402

2

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP HDA, LPC & MISC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

19 OF 109

SHEET

18 OF 80

SIZE

A

D

36

NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.

OMIT

U1400

MCP89M-A01

=PP1V05_SW_MCP_FSB

7

22

2000 mA 4300 mA

D

=PP1V05_S0_MCP_FSB

7

13 22

200 mA

C

G32
K29
D32
L29
Y26
V26
P27
T27
J29
N27
P26
F32
A32
H29
W26
U27
G31
C32
E32
M28
H30
U26
T26
H31
B32
R26
N26

W27
W28
Y27
Y28

+VTT_CPU_1
+VTT_CPU_2
+VTT_CPU_3
+VTT_CPU_4
+VTT_CPU_5
+VTT_CPU_6
+VTT_CPU_7
+VTT_CPU_8
+VTT_CPU_9
+VTT_CPU_10
+VTT_CPU_11
+VTT_CPU_12
+VTT_CPU_13
+VTT_CPU_14
+VTT_CPU_15
+VTT_CPU_16
+VTT_CPU_17
+VTT_CPU_18
+VTT_CPU_19
+VTT_CPU_20
+VTT_CPU_21
+VTT_CPU_22
+VTT_CPU_23
+VTT_CPU_24
+VTT_CPU_25
+VTT_CPU_26
+VTT_CPU_27

+VTT_CPU2_1
+VTT_CPU2_2
+VTT_CPU2_3
+VTT_CPU2_4

FBGA

(8 OF 11)

+VDD_MEM_1
+VDD_MEM_2
+VDD_MEM_3
+VDD_MEM_4
+VDD_MEM_5
+VDD_MEM_6
+VDD_MEM_7
+VDD_MEM_8

+VDD_MEM_9
+VDD_MEM_10
+VDD_MEM_11
+VDD_MEM_12
+VDD_MEM_13
+VDD_MEM_14
+VDD_MEM_15
+VDD_MEM_16
+VDD_MEM_17
+VDD_MEM_18
+VDD_MEM_19

POWER I

+VDD_MEM_20
+VDD_MEM_21
+VDD_MEM_22
+VDD_MEM_23
+VDD_MEM_24
+VDD_MEM_25
+VDD_MEM_26
+VDD_MEM_27
+VDD_MEM_28
+VDD_MEM_29
+VDD_MEM_30
+VDD_MEM_31

=PP1V5R1V35_SW_MCP_MEM

AG14
AL7
AF18
AF21
AM1
AM4
AK8
AG13
AF16
AF22
AG20
AM5
AG19
AF23
AJ9
AF19
AG17
AL6
AG16
AH12
AM2
AF15
AM3
AL5
AL8
AF17
AJ11
AJ8
AF14
AJ10
AF20

14 20 22

NOTE: VDD_COREx_SENSE signals should NOT
be used for remote sensing unless
COREA/COREB are powered by separate
regulators.
Instead connect regulator sense point
as close to COREB FET as possible.

=PPVCORE_S0_MCP

7

22

8450 mA (0.85V)

TP_MCP_VDDCOREA_SENSEP
TP_MCP_VDDCOREA_SENSEN

=PP1V05_S0_MCP_PE_DVDD0

7

200 mA (DVDD0 & DVDD1)
(PE0[3:0])

=PP1V05_S0_MCP_PE_DVDD1

7

200 mA (DVDD0 & DVDD1)
(PE0[5:4], PE1[1:0])

=PP1V05_S0_MCP_PE_AVDD0

7

500 mA (AVDD0 & AVDD1)
(PE0[3:0])

=PP1V05_S0_MCP_PE_AVDD1

7

500 mA (AVDD0 & AVDD1)
(PE0[5:4], PE1[1:0])

B

=PP3V3_S0_MCP_HVDD

7

22

30 mA

=PP3V3_S0_MCP

7

22

250 mA

=PP0V9_S5_MCP_VDD_AUXC

7

22

150 mA

PP3V3_G3_RTC

7

18 22

?? uA (G3)
5 mA (S0)

AB22
AB20

R13

T13
R11

AB17

R10

AB18

AB21

AB19

P13

U22
V22
W22
Y22

AA22

P12
P10
P11

L10

AF7
AF8
AE9

AE10

AE6
AE7
AE8

AC13
AB12
AC12
AD11
AD13
AB13

Y12
Y13

AA13

W12
W13

T11
T12
U13

U11
U12

E29

L11
M17
M20

A16

T3

R7
T6

T1
T2

R4

R2
T8
R8
T4
R5
T7
T5
T9

L9

F5

E5

MCP89M-A01

+VDD_COREA_1
+VDD_COREA_2
+VDD_COREA_3
+VDD_COREA_4
+VDD_COREA_5
+VDD_COREA_6
+VDD_COREA_7
+VDD_COREA_8
+VDD_COREA_9
+VDD_COREA_10
+VDD_COREA_11
+VDD_COREA_12
+VDD_COREA_13
+VDD_COREA_14
+VDD_COREA_15
+VDD_COREA_16
+VDD_COREA_17
+VDD_COREA_18
+VDD_COREA_19
+VDD_COREA_20
+VDD_COREA_21
+VDD_COREA_22
+VDD_COREA_23
+VDD_COREA_24
+VDD_COREA_25
+VDD_COREA_26
+VDD_COREA_27
+VDD_COREA_28
+VDD_COREA_29
+VDD_COREA_30
+VDD_COREA_31
+VDD_COREA_32
+VDD_COREA_33

+VDD_COREA_SENSE
GND_COREA_SENSE

+VIO_PE_DVDD0_1
+VIO_PE_DVDD0_2
+VIO_PE_DVDD0_3
+VIO_PE_DVDD0_4

+VIO_PE_DVDD1_1
+VIO_PE_DVDD1_2
+VIO_PE_DVDD1_3

+VIO_PE_AVDD0_1
+VIO_PE_AVDD0_2
+VIO_PE_AVDD0_3
+VIO_PE_AVDD0_4
+VIO_PE_AVDD0_5
+VIO_PE_AVDD0_6

+VIO_PE_AVDD1_1
+VIO_PE_AVDD1_2
+VIO_PE_AVDD1_3
+VIO_PE_AVDD1_4
+VIO_PE_AVDD1_5

+3.3V_HVDD_1
+3.3V_HVDD_2
+3.3V_HVDD_3

+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5

+VDD_DUAL_AUXC_1
+VDD_DUAL_AUXC_2
+VDD_DUAL_AUXC_3

+3.3V_VBAT

OMIT

U1400

FBGA

(9 OF 11)

POWER II

+VDD_COREB_SENSE

+VIO_SATA_AVDD_1
+VIO_SATA_AVDD_2
+VIO_SATA_AVDD_3
+VIO_SATA_AVDD_4
+VIO_SATA_AVDD_5

+VIO_SATA_DVDD_1
+VIO_SATA_DVDD_2
+VIO_SATA_DVDD_3
+VIO_SATA_DVDD_4
+VIO_SATA_DVDD_5
+VIO_SATA_DVDD_6
+VIO_SATA_DVDD_7
+VIO_SATA_DVDD_8

+VIO_SATA_DVDD_9
+VIO_SATA_DVDD_10
+VIO_SATA_DVDD_11
+VIO_SATA_DVDD_12

+VDD_DUAL_RMGT_1

+VDD_DUAL_RMGT_2

+3.3V_DUAL_RMGT_1
+3.3V_DUAL_RMGT_2

+3.3V_DUAL_USB_1

+3.3V_DUAL_USB_2

+VDD_COREB_1
+VDD_COREB_2
+VDD_COREB_3
+VDD_COREB_4
+VDD_COREB_5
+VDD_COREB_6
+VDD_COREB_7
+VDD_COREB_8

+VDD_COREB_9
+VDD_COREB_10
+VDD_COREB_11
+VDD_COREB_12
+VDD_COREB_13
+VDD_COREB_14
+VDD_COREB_15
+VDD_COREB_16
+VDD_COREB_17
+VDD_COREB_18
+VDD_COREB_19
+VDD_COREB_20
+VDD_COREB_21
+VDD_COREB_22
+VDD_COREB_23
+VDD_COREB_24
+VDD_COREB_25
+VDD_COREB_26
+VDD_COREB_27
+VDD_COREB_28
+VDD_COREB_29
+VDD_COREB_30
+VDD_COREB_31
+VDD_COREB_32
+VDD_COREB_33
+VDD_COREB_34
+VDD_COREB_35
+VDD_COREB_36
+VDD_COREB_37
+VDD_COREB_38
+VDD_COREB_39
+VDD_COREB_40
+VDD_COREB_41
+VDD_COREB_42

GND_COREB_SENSE

+3.3V_DUAL_1

+3.3V_DUAL_2

=PPVCORE_SW_MCP_GFX

M4
M2
P4
N12
N4
N14
V20
N10
P3
P1
N11
N6
P6
N2
N9
N8
M10
N3
N1
M5
M7
P2
M8
M11
V19
N7
N16
P5
N5
N13
N15
P9
V17
V18
M14
M13
Y19
Y20
Y17
Y18
P7
P8

U10

TP_MCP_VDDCOREB_SENSEP

T10

TP_MCP_VDDCOREB_SENSEN
PP1V05_S0_MCP_SATA_AVDD

AE1
AE2
AE3
AE4
AE5

=PP1V05_S0_MCP_SATA_DVDD

AF1
AF2
AF3
AF4
AF5
AF6
AF9
AF10
AF11
AE11
AE12
AE13

=PP0V9_ENET_MCP_RMGT

L12
L13

=PP3V3_ENET_MCP_RMGT

A13
B13

=PP3V3_S5_MCP

A20

200 mA

A19

F8

40 mA

E8

345678

15350 mA (0.85V)

300 mA

100 mA

140 mA

300 mA

240 mA

21 23

22

7

7

7

7

22

22

17 22

22

AP21

M37
AM21
AU37
AC27

D18

AD5

AT1
AM30

AT3
AP24
AM33
AE27
AJ24
AH18

AA8
AM18

J32
AJ21
AK35

H15

D33

B18

M32

K18
AN34
AD10

F34

R35

AR9

AA2
AA10

R32
AG29

AP12
AM12
AH21

V32
AR33

AA32
AG34
AK37

K24

K21

AG8

AN5

AD32

AD2

D15

AG2

L15
AK32
AR12
AN35
AN37

B1

J2

C1

B6

B2
E6
J5

V8

H8

J7

J8

V2

2 1

OMIT

U1400

MCP89M-A01

FBGA

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67

(10 OF 11)

GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134

AD7
B12
D12
E12
G12
A2
AL12
AM6
AD37
AG32
H12
AR35
H9
G24
V10
V5
AL30
G7
V29
AP15
AN2
AJ12
AR15
N20
D21
E21
G21
H21
AR27
AM27
AP27
AM15
AA31
AM9
AH24
K12
J31
E30
AK7
V7
M31
AU12
AP6
B37
A36
F35
L27
D35
AL24
AP30
AH15
B21
AV3
AT38
B38
AA21
AD4
A37
AP18
AN4
B24
D30
V4
AA7
AD34
AK4
R37

AU24
AU15

AG5
AD35
AJ18
AL18
AR24

AA5

G18

AU9
AM24

H24

B30
AR21

D24
AU30

AK5

N18

E24

K15

M19
AH27

E18
AA34
AK31

K11
AU21

V34
AL21
AA11

M34

B27

V28

C38

D27

R34

J35
AK34

E15
AR30
AU33

J34
AH30

AU27

AU1
AG10

E27

L21
AU38

H18

B15

AA4
AJ15

L18

G15
AL27
AV37

N19

H27

B9

J4

E9

A3

D9
L4

OMIT

U1400

MCP89M-A01

FBGA

(11 OF 11)
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199

GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217
GND_218
GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226
GND_227
GND_228
GND_229
GND_230

GND

GND_231
GND_232
GND_233
GND_234
GND_235
GND_236
GND_237
GND_238
GND_239
GND_240
GND_241
GND_242
GND_243
GND_244
GND_245
GND_246
GND_247
GND_248
GND_249
GND_250
GND_251
GND_252
GND_253
GND_254
GND_255
GND_256
GND_257
GND_258
GND_259
GND_260
GND_261
GND_262
GND_263
GND_264

E33
M35
AV2
AK2
AU6
F37
C3
J37
V35
G27
AA35
AU18
AR6
AV36
B33
AJ27
G9
AG35
AG7
AD8
AU2
AP9
AD31
V37
AA37
AG37
AL15
AR18
L14
K14
F2
K27
AL9
AB26
M29
G30
R28
R29
R31
U17
K8
Y21
V31
U18
W21
U19
W18
U20
W17
V21
AA28
AA29
N17
AD28
AD29
AG4
W19
W20
AA26
AB27
AA17
AA18
AA19
AA20
U21

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Power & Ground

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/06/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

20 OF 109

SHEET

19 OF 80

36

345678

2 1

D

C2300 helps reduce input rail
droop during Q2300 turn-on.

=PP1V5R1V35_S0_MCPDDRFET

7

=PP5V_S3_MCPDDRFET

7

20

C

MCP_MEM_VDD_EN

18 65

IN

MCPMEM_CNFG

1

R2305

560K

1%
1/16W
MF
402

2

SLG5AP031

2

EN

3

CNFG

U2305

CRITICAL

GND

4

<R1>

Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)

PLACE_NEAR=Q2300.9:2 mm

1

VCC

TDFN

G

S

DONE

THRM

PAD

9

1

C2305

0.1UF

20%
10V

2

CERM
402

5

D

7

MCPMEM_GATE
(G driven to VCC)

6

8

TP_MCPMEM_DONE

CRITICAL

C2300

100UF

CERM-X5R

1206-1

6.3V

1

20%

2

4

G

7

CRITICAL

9

STMFS485NST1G

Q2300

D

DFN

KELVIN

S

SENSE

321 5

8

NC

NC

6

MCPDDRFET_KELVIN

K1

NC

MCPDDRFET_SENSE

PP1V5R1V35_SW_MCP

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5R1V35_SW_MCP_MEM

NV Requirements:

- Min Ramp-Up Time: 20 uS (10% to 90%)

- Max Ramp-Up Time: 65 uS (ENABLE to 90%)

- FET Ron <= 3.8 mOhms

Part
Type
Rds(on)
Loading

(OR 1.35V)

Q2300

STMFS4854N
N-Channel
10 mOhm @3.2V

4.3 A (EDP)

OUT

OUT

4250 mA

44

44

14 19 22

NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.

D

C

Gated Rail Savings: 120mW

DIMM CKE Clamps

CKE must be held low to keep memory in self-refresh.

B

=PP5V_S3_MCPDDRFET

7

20

MCP_MEM_VTT_EN

18

IN

R2350

Q2350

SSM3K15FV

SOD-VESM-HF

1

10K

5%
1/16W
MF-LF

402

G S

1

2

MEMVTT_EN_L

3

D

2

A

CRITICAL

Q2355

NTUD3170NZXXG

SOT-963

G

5

4

G

2

1

CRITICAL

Q2356

NTUD3170NZXXG

SOT-963

G

5

4

G

2

1

D

S

D

S

D

S

D

S

8 7 5 4 2 1

Clamps enable before MCP89 MEMVDD rail switched off.
Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.
Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.
Q2355/Q2356 chosen for low output capacitance.

3

MEM_A_CKE<0>

6

MEM_A_CKE<1>

14 25 73

BI

14 25 73

BI

NO STUBS on CKE signals!

3

MEM_B_CKE<0>

6

MEM_B_CKE<1>

14 26 73

BI

14 26 73

BI

36

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP89 Memory Rail Gating

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

BRANCH

PAGE

23 OF 109

SHEET

20 OF 80

A.13.0

SIZE

B

A

D

345678

2 1

D

C2400 helps reduce input rail
droop during Q2400 turn-on.

=PPVCORE_S0_MCPGFXFET

7

1

2

=PP5V_S0_MCPFSBFET

7

5 6 7 8

1

C

GFXVCORE_PWR_EN

18

IN

MCPGFX_CNFG

1

2

C2406

820PF

10%
50V
CERM
402

2

3

VCC

U2405

SLG5AP033

TDFN

EN

CRITICAL

CNFG

GND

4

THRM

PAD

DONE

9

1

2

5

D

7

G

6

S

8

C2405

0.1UF

20%
10V
CERM
402

MCPGFX_GATE
(G driven to VCC)

TP_MCPGFX_DONE

4

G

<C1>

Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)

CRITICAL

D

Q2400

SI4838BDY

SO-8

S

31 2

NV Requirements:

- Min Ramp-Up Time: 100 uS (10% to 90%)

- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)

- FET Ron <= 2.5 mOhms
NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.

PLACE_NEAR=C2400.1:1 mm

XW2400

SM

CRITICAL

C2400

100UF

20%

6.3V
CERM-X5R
1206-1

1 2

PLACE_NEAR=Q2400.5:2 mm

XW2401

SM

1 2

PLACE_NEAR=C2400.2:1 mm

Part
Type
Rds(on)
Loading

PPVCORE_SW_MCP_GFX

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PPVCORE_SW_MCP_GFX

MCPCORES0_VSEN_P

MCPCORES0_VSEN_N

Q2400

Si4838BDY
N-Channel

3.2 mOhm @2.5V

15.35 A (EDP)

19 23

62 79

OUT

62 79

OUT

D

C

Gated Rail Savings: 860mW

SIZE

B

A

D

B

A

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP89 GFX Core Rail Gating

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

24 OF 109

SHEET

21 OF 80

345678

2 1

MCP Non-GFX Core Power

=PPVCORE_S0_MCP

19

7

8450 mA (0.85V)

1

212

1

2

C2501

4.7UF

20%
4V
X5R
402

1

C2511

0.1UF

20%
10V

2

CERM
402

C2500

10UF

20%

6.3V
X5R

603-1

D

MCP Memory Power

=PP1V5R1V35_SW_MCP_MEM

20 19 14

4300 mA (1.5V)

C2510

4.7UF

20%

4V
X5R
402

1

C2502

1UF

10%
10V

2

X5R
402-1

1

C2512

0.1UF

20%
10V

2

CERM
402

MCP CPU FSB (VTT) Power

=PP1V05_SW_MCP_FSB

19

7

2000 mA

C2520

10UF

6.3V

603-1

20%
X5R

212

1

C2521

4.7UF

20%
4V
X5R
402

1

C2522

1UF

10%
10V

2

X5R
402-1

MCP 0.9V AUX Core Power

=PP0V9_S5_MCP_VDD_AUXC

19

7

1

C

C2526

0.1uF

20%
10V

2

CERM
402

1

C2527

0.1uF

20%
10V

2

CERM
402

MCP 1.05V PCIE Digital Power

=PP1V05_S0_MCP_PE_DVDD

7

200 mA

4.7UF

1

1

C2531

1UF 1UF

20%

4V
X5R
402

10%
10V

2

2

X5R
402-1

1

C2532

10%
10V

2

X5R
402-1

MCP 1.05V Memory DLL Power

=PP1V05_S0_MCP_M2CLK_DLL

14

7

550 mA

4.7UF

1

20%

4V

2

X5R
402

1

C2503

0.22UF

20%

6.3V

2

X5R
402

1

C2513

0.1UF

20%
10V

2

CERM
402

1

1UF

10%
10V

2

X5R
402-1

1

C2533

0.1uF

20%
10V

2

CERM
402

1

C2504

0.1UF

20%
10V

2

CERM
402

1

C2514

0.1UF

20%
10V

2

CERM
402

1

C2534

0.1uF

20%
10V

2

CERM
402

1

C2505

0.1UF

20%
10V

2

CERM
402

1

C2515

0.1UF

20%
10V

2

CERM
402

1

C2506

0.1UF

20%
10V

2

CERM
402

1

C2516

0.1UF

20%
10V

2

CERM
402

1

C2507

0.1UF

20%
10V

2

CERM
402

1

C2517

0.1UF

20%
10V

2

CERM
402

MCP S0 FSB (VTT) Power

=PP1V05_S0_MCP_FSB

19 13

7

200 mA

MCP 0.9V MAC/SMU Power

=PP0V9_ENET_MCP_RMGT

19

7

140 mA150 mA

MCP 1.05V SATA Digital Power

=PP1V05_S0_MCP_SATA_DVDD

19

7

100 mA

1

C2535

0.1uF

20%
10V

2

CERM
402

MCP 3.3V PCIe/SATA I/O PLL Power

=PP3V3_S0_MCP_HVDD

19

7

30 mA

C2524

4.7UF

C2528

4.7uF

C2536C2530

4.7UF

C2541

4.7UF

6.3V
CERM

1

C2508

0.1UF

20%
10V

2

CERM
402

1

C2518

0.1UF

20%
10V

2

CERM
402

1

1

C2525C2523

1UF

20%

4V
X5R
402

20%

4V
X5R
402

20%

4V
X5R
402

20%

603

10%
10V

2

2

X5R
402-1

1

1

C2529

0.1uF

20%
10V

2

2

CERM
402

1

1

C2537

0.1uF

20%
10V

2

2

CERM
402

1

1

C2542C2540

0.1uF

20%
10V

2

2

CERM
402

B

MCP 3.3V I/O Power

=PP3V3_S0_MCP

19

7

250 mA

C2543

4.7uF

6.3V
CERM

20%

603

212

1

C2544

0.1uF

20%
10V
CERM
402

1

C2545

0.1uF

20%
10V

2

CERM
402

1

C2546

0.1uF

20%
10V

2

CERM
402

1

C2547

0.1uF

20%
10V

2

CERM
402

MCP 3.3V AUX/USB Power

=PP3V3_S5_MCP

19

7

240 mA

1

4.7uF

6.3V
CERM

4.7uF

6.3V
CERM

1

C2551

20%

603

0.1uF

20%
10V

2

2

CERM
402

MCP 3.3V MAC PLL Power

=PP3V3_ENET_MCP_PLL_MAC

7

1

1

C2554

20%

603

0.1uF

20%
10V

2

2

CERM
402

20 mA

C2550

MCP 3.3V MAC/SMU Power

=PP3V3_ENET_MCP_RMGT

19 17

A

7

300 mA

C2553

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

MCP 3.3V/1.5V HDA Power

=PP3V3R1V5_S0_MCP_HDA

18

8

70 mA

C2548

4.7UF

MCP 2.0V-3.3V RTC Power

PP3V3_G3_RTC

19 18

7

? uA (G3)
5 mA (S0)

CRITICAL

L2555

FERR-240-OHM-200MA

0402

C2555

4.7UF

6.3V
CERM

21

20%

603

1

1

C2549

20%

6.3V
CERM

603 402

1

2

0.1uF

20%
10V

2

2

CERM

C2552

1

4.7UF

20%

6.3V
2

CERM

603

PP3V3_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2556

0.1UF

20%
10V

2

CERM
402

MCPHVDD:P2V5

8 7 5 4 2 1

1

C2519

0.1UF

20%
10V

2

CERM
402

=PP3V3_S0_MCP_PLL_UF

7

260 mA

1

R2592

10K

5%
1/16W
MF-LF

402

2

17

20 mA

PART NUMBER

353S2971
353S2979
116S0004

L2560

=PP1V05_S0_MCP_AVDD_UF

7

800 mA 500 mA

=PP1V05_S0_MCP_PLL_UF

7

555 mA

PLACE_NEAR=R2570.1:50 mil

PLACE_NEAR=R2575.1:50 mil

PLACE_NEAR=R2580.1:50 mil

=PP3V42_G3H_OPA330

7

MCPHVDD:P3V3

R2593

0

PP3V3_S0_LDO_R

MIN_LINE_WIDTH=0.4 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=3.3V

MF-LF

402

SC70

5

VOUT

4

NC

GND

2

CRITICAL

L2595

220-OHM-2.2A

PLACE_NEAR=R2595.1:50 mil

DESCRIPTION

RES,0402,0,5%,1/16W

MCPHVDD:P2V5

1

C2593

1UF

10%
10V

2

X5R
402

QTY

1
1
1

1 2

CRITICAL

OMIT_TABLE

U2592

MIC5365-2.5V

1

VIN

3

EN

IC,LDO,MIC5365,2.5V,150MA,2%,SC70-5,HFLF

IC,LDO,TPS717,ADJ,150MA,3%,SC70,HFLF

30-OHM-5A

0603

C2560

10UF

L2567

30-OHM-5A

0603

C2567

10UF

CRITICAL

L2570

220-OHM-2.2A

0603

C2570

4.7UF

GND_MCP_PLL_FSB

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=0V

LDO:ADJ

LDO_ADJMCP_PLL_LD0_EN

LDO:ADJ

0603

CRITICAL

L2575

220-OHM-2.2A

0603

C2575

CRITICAL

L2580

220-OHM-2.2A

0603

C2580

HTOL_SENSE:YES

1

C2599

0.1UF

20%

2

10V
CERM
402

1

R2594

10K

5%
1/16W
MF-LF

402

2

1

R2591

10K

5%
1/16W
MF-LF

402

2

21

4.7UF

4.7UF

MCPHVDD:P2V5

1

2

C2595

GND_MCP_PLL_DP_USB

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=0V

REFERENCE DES

21

20%

6.3V
212

X5R

603-1

21

20% 20%

6.3V
212

X5R

603-1

21

1

20%

4V

2

X5R
402

21

1

20%

4V

2

X5R
402

21

1

20%

4V

2

X5R
402

HTOL_SENSE:YES

HTOL_SENSE:YES

C2592

1UF

10%
10V
X5R
402

39

IN

HTOL_SENSE:YES

1

4.7UF

20%

6.3V

2

CERM

603

U2592
U2592
R2596

1

4.7UF

20%
4V
X5R
402

1

C2568

4.7UF

4V
X5R
402

R2570

0.33

1 2

5%

1/16W

MF

0402

R2597

1K

1%
1/16W
MF-LF

402

=PP3V3_S0_OPA333

7

R2596

1K

1 2

CRITICAL

1%

1/16W

Q2592

MF-LF

NTZD3152P

402

HTOL_SENSE:YES

S

1

SMC_P10

R2599

100K

5%
1/16W
MF-LF

402

R2595

0.33

1 2

5%

1/16W

MF

0402

CRITICAL

CRITICAL
CRITICAL
CRITICAL

1

C2562C2561

1UF

10%
10V

2

X5R
402-1

MCP 1.05V SATA Analog Power

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2569

0.1UF

20%
10V

2

CERM
402

1

C2571 C2572

0.1UF

20%
10V

2

CERM
402

1

C2576

0.1UF

20%
10V

2

CERM
402

1

C2581

0.1UF

20%
10V

2

CERM
402

1

2

1

2

1

C2577

0.1uF

20%
10V

2

CERM
402

1

C2582

0.1uF

20%
10V

2

CERM
402

SMC_N_MIRROR

2

3

-IN

V-

1

V+

+IN

C2563

1UF

10%
10V
X5R
402-1

0.1uF

20%
10V
CERM
402

4

SC70-5

OPA330

5

U2593

CRITICAL

HTOL_SENSE:YES

HTOL_SENSE:YES

SOT-563-HF

G

2

D

6

1

C2596

0.1UF

20%
10V

2

CERM
402

1

HTOL_SENSE:YES

C2594

2

0.1UF

20%
10V
CERM
402

FERR-240-OHM-200MA

PP3V3_S0_MCP_HVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

MCP 3.3V DP & USB PLL Power

PP3V3_S0_MCP_PLL_DP_USB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2597

0.1uF

20%
10V

2

CERM
402

BOM OPTION

LDO:FIXED

LDO:ADJ

HTOL_SENSE:NO

1

2

300 mA

C2564

0.1UF

20%
10V
CERM
402

1

C2565

0.1UF

20%
10V

2

CERM
402

19

MCP 1.05V CPU/FSB/MEM PLL Power

PP1V05_S0_MCP_PLL_FSBMEM

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2573

0.1UF

20%
10V

2

CERM
402

MCP 1.05V PCIe/SATA PLL Power

PP1V05_S0_MCP_PLL_PEXSATA

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

C2579

1

C2578

0.1UF

20%
10V

2

CERM
402

1

C2583

0.1UF

20%
10V

2

CERM
402

R2590

100K

1 2

1%
1/16W
MF-LF

402

CRITICAL

5

G

SMC_P_FOLLOW

L2590

0402

0.1UF

1

20%
10V
CERM
402

2

MCP 1.05V Core/Misc PLL Power

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

C2584

0.1UF

1

20%
10V
CERM
402

2

4

S

HTOL_SENSE:YES

SOT-563-HF

NTZD3152P

Q2592

CRITICAL

D

3

21

C2590

4.7UF

210 mA

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Standard Decoupling

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

MCP 1.05V PCIe Analog Power

PP1V05_S0_MCP_PE_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2566

0.1UF

20%
10V

2

CERM
402

14

70 mA

HTOL_SENSE:YES

CRITICAL

U2594

OPA330

SC70-5

5

1

+IN

V+

3

-IN

SMC_N_FOLLOW

4

V-

2

PP3V3_S0_MCP_PLL_HVDD

1

1

C2591

20%

6.3V
CERM

603

Apple Inc.

R

0.1UF

20%

2

2

10V
CERM
402

15

325 mA

16

160 mA

PLACEMENT_NOTEs:
Place close to SMC

Place close to SMC

(For R and C)

HTOL_SENSE:YES

R2598

4.53K

1 2

1%
1/16W
MF-LF

402

SMC_NB_MISC_ISENSE

HTOL_SENSE:YES

C2598

1

0.22UF

20%

6.3V
X5R

2

402

GND_SMC_AVSS

MCP 3.3V PLL Power

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

SYNC_DATE=08/15/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

25 OF 109

SHEET

22 OF 80

36

7

39

50 mA

D

C

B

OUT

43
39
40
44

15

A

SIZE

D

345678

2 1

MCP GFX Core Power

=PPVCORE_SW_MCP_GFX

19 21

15350 mA (0.85V)

MCP 3.3V RGBDAC Power

PP3V3_S0_MCP_DAC

140 mA

16

D

212

1

C2601

4.7UF

20%
4V
X5R
402

C2600

10UF

6.3V

603-1

20%
X5R

D

1

C2602

1UF

10%
10V

2

X5R
402-1

1

C2603

1UF

10%
10V

2

X5R
402-1

1

C2604

0.22UF

20%

6.3V

2

X5R
402

1

C2605

0.22UF

20%

6.3V

2

X5R
402

1

C2606

0.1UF

20%
10V

2

CERM
402

1

C2607

0.1UF

20%
10V

2

CERM
402

1

C2608

0.1UF

20%
10V

2

CERM
402

1

C2609

0.1UF

20%
10V

2

CERM
402

1

C2610

0.1UF

20%
10V

2

CERM
402

1

C2611

0.1UF

20%
10V

2

CERM
402

1

C2612

0.1UF

20%
10V

2

CERM
402

R2670

1/16W
MF-LF

402

GND_MCP_DAC_P3V3

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

1

VOLTAGE=0V
MAKE_BASE=TRUE

0

5%

If RGBDAC is used, requires ferrite (155S0382)

2

plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap.
If RGBDAC is not used, tie to GND.

MCP 3.3V/1.8V IFP Interface Power

=PP3V3R1V8_S0_MCP_IFP_VDD

7

16

180 mA (1.8V LVDS)

C2620

4.7uF

6.3V
CERM

20%
603

212

1

C2621

0.1uF

20%
10V
CERM
402

MCP 1.05V IFP PLL Power

=PP1V05_S0_MCP_PLL_IFP

7

16

60 mA

C2630

4.7uF

20%
X5R

402

1

1

C2631

0.1uF

4V

20%
10V

2

2

CERM
402

MCP 1.05V DisplayPort Power

=PP1V05_S0_MCP_DP0_VDD

7

16

160 mA

1

C2640

4.7UF

20%
X5R

402

C

MCP_TMDS0_RSET

16 74

MCP_TMDS0_VPROBE

16 74

NO STUFF

C2650

0.1UF

20%
10V

CERM

402

1

C2641

0.1uF

4V

20%
10V

2

2

CERM
402

C

MCP_IFPAB_RSET

16 74

MCP_IFPAB_VPROBE

1

R2650

1

1K

1%
1/16W
MF-LF
402

2

2

16 74

NO STUFF

C2655

0.1UF

20%
10V

CERM

402

NO STUFF

1

R2655

1

1K

1%
1/16W
MF-LF

2

402

2

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

B

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Graphics Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/06/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

26 OF 109

SHEET

23 OF 80

36

345678

2 1

RTC Crystal

R2810

0

1/16W
MF-LF

10M

1 2

1

5%

402

2

1/16W
MF-LF

5%

402

RTC_CLK32K_XTALOUT_R

CRITICAL

Y2810

32.768K

7X1.5X1.4-SM

41

RTC_CLK32K_XTALOUT

18

IN

NO STUFF

R2811

D

RTC_CLK32K_XTALIN

18

OUT

C2810

12pF

1 2

5%

50V

CERM

402

C2811

12pF

1 2

5%

50V

CERM

402

18 75

IN

LPC_RESET_L

MCP 25MHz Crystal

C2815

12pF

1 2

5%

50V

CERM

402

NC

2 4

NC

C2816

12pF

1 2

5%

50V

CERM

402

15 18

IN

MAKE_BASE=TRUE

PCIE_RESET_L

18

IN

18

OUT

MCP_CLK25M_XTALOUT

MCP_CLK25M_XTALIN

NO STUFF

R2816

1/16W
MF-LF

R2815

0

1 2

1

1M

5%

402

2

1/16W
MF-LF

5%

402

MCP_CLK25M_XTALOUT_R

CRITICAL

Y2815

25.0000M

SM-3.2X2.5MM

31

Caesar II (ENET) 25MHz Crystal

R2820

C

BCM5764_CLK25M_XTALO

31

IN

BCM5764_CLK25M_XTALI

31

OUT

NO STUFF

R2821

10M

1/16W
MF-LF

200

1 2

1

5%

402

2

1/16W
MF-LF

5%

402

BCM5764_CLK25M_XTALO_R

CRITICAL

Y2820

25.0000M

SM-3.2X2.5MM

31

C2820

27pF

1 2

5%

50V

CERM

402

NC

2 4

NC

C2821

27pF

1 2

5%

50V

CERM

402

Platform Reset Connections

LPC Reset (Unbuffered)

R2881

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

PCIE Reset (Unbuffered)

33

1 2

5%
1/16W
MF-LF

402

R2893

0

1 2

5%
1/16W
MF-LF

402

R2895

0

1 2

5%
1/16W
MF-LF

402

R2883

33

1 2

5%
1/16W
MF-LF

402

R2891

0

1 2

5%
1/16W
MF-LF

402

R2894

0

1 2

5%
1/16W
MF-LF

402

R2892

0

1 2

5%
1/16W
MF-LF

402

LPCPLUS_RESET_L

SMC_LRESET_L

=FW_RESET_L

PCA9557D_RESET_L

BKLT_PLT_RST_L

AP_RESET_L

SDCARD_PLT_RST_L

ENET_RESET_L

41

OUT

D

39

OUT

34

OUT

28

OUT

71

OUT

29

OUT

30

OUT

31 76

OUT

C

R2825

18 75

IN

LPC_CLK33M_SMC_R

PLACEMENT_NOTE=Place close to U1400

Ethernet WAKE# Isolation

B

Q2830

SSM3K15FV

SOD-VESM-HF

PCIE_WAKE_L

6

15 29

OUT

D

3

1

GS

2

=PP3V3_ENET_PHY

1

R2830

10K

5%
1/16W
MF-LF
402

2

ENET_WAKE_L

MAKE_BASE=TRUE

7

31 64

=ENET_WAKE_L

PM_CLK32K_SUSCLK_R

18 75

IN

31

IN

PLACEMENT_NOTE=Place close to U1400

33

1 2

5%
1/16W
MF-LF

402

R2829

22

1 2

5%
1/16W
MF-LF

402

R2826

33

1 2

5%
1/16W
MF-LF

402

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

PLACEMENT_NOTE=Place close to U1400

PM_CLK32K_SUSCLK

39 75

OUT

41 75

OUT

B

39 75

OUT

MCP S0 PWRGD & CPU_VLD

=PP3V3_S5_MCPPWRGD

7

1

C2850

0.1UF

20%
10V

2

U2850

5

Y

3

CERM
402

74LVC1G08GW

SOT353

4

MCP_PS_PWRGD

18

OUT

A

39 65

IN

61

IN

ALL_SYS_PWRGD

VR_PWRGOOD_DELAY

1

B

2

A

PM_SYSRST_L

39

IN

XDP_DBRESET_L

9

12 18

IN

PLACEMENT_NOTE=Place R2897 on BOTTOM

8 7 5 4 2 1

System Reset Circuit

XDP

R2896

0

1 2

5%
1/16W
MF-LF

R2897

402

SILK_PART=SYS RST

OMIT

1/16W
MF-LF

R2899

1 2

1

0

5%

402

2

10K pull-up to 3.3V S0 inside MCP

1/16W
MF-LF

33

5%

402

PM_SYSRST_DEBOUNCE_L

NO STUFF

1

C2899

1UF

10%
10V

2

X5R
402

SIZE

A

D

OUT

SYNC_MASTER=T27_MLB

PAGE TITLE

SB Misc

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

28 OF 109

SHEET

24 OF 80

36

Page Notes

Power aliases required by this page:

- =PPLVDDR_S3_MEM_A

- =PPDDRVTT_S0_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

BOM options provided by this page:
(NONE)

D

C

B

=PPSPD_S0_MEM_A

7

A

8 7 5 4 2 1

C2940

2.2UF

6.3V
CERM

402-LF

2 1

2

C2921

1

0.1UF

20%
10V
CERM
402

2

1

C2922

0.1UF

20%
10V
CERM
402

2

C2923

1

0.1UF

20%
10V
CERM
402

D

=PPDDRVTT_S0_MEM_A

7

=PPLVDDR_S3_MEM_A

7

C2900

10UF

6.3V

345678

DDR3 Plane Stitching Caps (Space evenly across plane split)

1

20%

2

X5R
603

C2901

10UF

6.3V

1

2

C2910

20%

2

X5R
603

1

0.1UF

20%
10V
CERM
402

2

C2911

0.1UF

1

20%
10V
CERM
402

2

C2912

1

0.1UF

20%
10V
CERM
402

2

C2913

1

0.1UF

20%
10V
CERM
402

2

C2914

0.1UF

20%
10V

1 1

CERM
402

2

C2915

0.1UF

20%
10V
CERM
402

2

C2916

0.1UF

1

20%
10V
CERM
402

2

1

C2917

0.1UF

20%
10V
CERM
402

2

C2918

0.1UF

1

20%
10V
CERM
402

2

C2919

0.1UF

1

20%
10V
CERM
402

2

1

C2920

0.1UF

20%
10V
CERM
402

"Factory" (top) slot

PPVREF_S3_MEM_VREFDQ_A

C2936

0.1UF

CERM

20%
10V

402

28

PPVREF_S3_MEM_VREFCA_A

1

C2935

2.2UF

20%

6.3V

212

CERM
402-LF

C2930

2.2UF

402-LF

6.3V
CERM

1

VREFDQ

3

1

1

C2931

0.1UF

20%

20%
10V

2

2

CERM

402

28

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

BI
BI

IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

=MEM_A_DQ<0>
=MEM_A_DQ<1>

=MEM_A_DM<0>

=MEM_A_DQ<2>
=MEM_A_DQ<3>

=MEM_A_DQ<8>
=MEM_A_DQ<9>

=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>

=MEM_A_DQ<10>
=MEM_A_DQ<11>

=MEM_A_DQ<16>
=MEM_A_DQ<17>

=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>

=MEM_A_DQ<18>
=MEM_A_DQ<19>

=MEM_A_DQ<24>
=MEM_A_DQ<25>

=MEM_A_DM<3>

=MEM_A_DQ<26>
=MEM_A_DQ<27>

VSS

5

DQ0

7

DQ1

VSS

DM0

VSS
DQ2
DQ3

VSS
DQ8
DQ9

VSS
DQS1*
DQS1

VSS
DQ10
DQ11

VSS
DQ16
DQ17

VSS
DQS2*
DQS2

VSS
DQ18
DQ19

VSS
DQ24
DQ25

VSS
DM3

VSS
DQ26
DQ27

VSS

CRITICAL

J2900

F-RT-THB

(SYMBOL 1 OF 2)

RESET*

DDR3-SODIMM-DUAL-M97-3

KEY

9
11

13

15
17

19

21
23

25
27

29

31
33

35

37
39

41

43
45

47
49

51

53
55

57

59
61

63

65
67

69
71

DQ4
DQ5

DQS0*

DQS0

VSS

DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3*

DQS3

VSS
DQ30
DQ31

VSS

VSS

VSS

2

4
6

8

10
12

14

16
18

20

22
24

26
28

30

32
34

36

38
40

42

44
46

48
50

52

54
56

58

60
62

64

66
68

70
72

=MEM_A_DQ<4>
=MEM_A_DQ<5>

=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>

=MEM_A_DQ<6>
=MEM_A_DQ<7>

=MEM_A_DQ<12>
=MEM_A_DQ<13>

=MEM_A_DM<1>
MEM_RESET_L

=MEM_A_DQ<14>
=MEM_A_DQ<15>

=MEM_A_DQ<20>
=MEM_A_DQ<21>

=MEM_A_DM<2>

=MEM_A_DQ<22>
=MEM_A_DQ<23>

=MEM_A_DQ<28>
=MEM_A_DQ<29>

=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>

=MEM_A_DQ<30>
=MEM_A_DQ<31>

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

IN

14 26

IN

27

BI

27

BI

27

BI

27

BI

27

IN

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

C

516-0201

B

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

DDR3 SO-DIMM Connector A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

29 OF 109

SHEET

25 OF 80

CKE0

VDD
NC

BA2

VDD
A12/BC*
A9

VDD
A8
A5

VDD
A3
A1

VDD
CK0
CK0*

VDD
A10/AP
BA0

VDD
WE*
CAS*

VDD
A13
S1*

VDD
TEST

VSS
DQ32
DQ33

VSS
DQS4*
DQS4

VSS
DQ34
DQ35

VSS
DQ40
DQ41

VSS
DM5

VSS
DQ42
DQ43

VSS
DQ48
DQ49

VSS
DQS6*
DQS6

VSS
DQ50
DQ51

VSS
DQ56
DQ57

VSS
DM7

VSS
DQ58
DQ59

VSS
SA0
VDDSPD
SA1

VTT

KEY

CRITICAL

J2900

F-RT-THB

(SYMBOL 2 OF 2)

DDR3-SODIMM-DUAL-M97-3

VREFCA

EVENT*

516-0201

MEM_A_CKE<0>

14 20 73

IN

MEM_A_BA<2>

14 73

IN

MEM_A_A<12>

14 73

IN

MEM_A_A<9>

14 73

IN

MEM_A_A<8>

14 73

IN

MEM_A_A<5>

14 73

IN

MEM_A_A<3>

14 73

IN

MEM_A_A<1>

14 73

IN

MEM_A_CLK_P<0>

14 73

IN

MEM_A_CLK_N<0>

14 73

IN

MEM_A_A<10>

14 73

IN

MEM_A_BA<0>

14 73

IN

MEM_A_WE_L

14 73

IN

MEM_A_CAS_L

14 73

IN

MEM_A_A<13>

14 73

IN

MEM_A_CS_L<1>

14 73

IN

=MEM_A_DQ<32>

27

BI

=MEM_A_DQ<33>

27

BI

=MEM_A_DQS_N<4>

27

BI

=MEM_A_DQS_P<4>

27

BI

=MEM_A_DQ<34>

27

BI

=MEM_A_DQ<35>

27

BI

=MEM_A_DQ<40>

27

BI

=MEM_A_DQ<41>

27

BI

=MEM_A_DM<5>

27

IN

=MEM_A_DQ<42>

27

BI

=MEM_A_DQ<43>

27

BI

=MEM_A_DQ<48>

27

BI

=MEM_A_DQ<49>

27

BI

=MEM_A_DQS_N<6>

27

BI

=MEM_A_DQS_P<6>

27

BI

=MEM_A_DQ<50>

27

BI

=MEM_A_DQ<51>

27

BI

=MEM_A_DQ<56>

27

BI

=MEM_A_DQ<57>

27

BI

=MEM_A_DM<7>

27

IN

=MEM_A_DQ<58>

27

BI

=MEM_A_DQ<59>

27

BI

MEM_A_SA<0>

MEM_A_SA<1>

121

10K

R2941

10K

5%

5%

1/16W
MF-LF
402

402

2

R2940

1

20%

1/16W

2

MF-LF

73

75
77

NC

79

81
83

85

87
89

91

93
95

97
99

101

103
105

107

109
111

113

115
117

119
121

123

125

NC

127

129

131
133

135

137
139

141
143

145

147
149

151

153
155

157

159
161

163
165

167

169
171

173

175
177

179

181
183

185
187

189

191
193

195

197
199

201

203

CKE1

VDD

VDD

VDD

VDD

CK1*

VDD

RAS*

VDD

ODT0

VDD

ODT1

VDD

VSS
DQ36
DQ37

VSS

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5*

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7*

DQS7

VSS
DQ62
DQ63

VSS

VTT

A15
A14

A11

CK1

BA1

S0*

DM4

DM6

SDA
SCL

VDD

74

76
78

80

82
84

86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100

102

104
106

108

110
112

114

116
118

120
122

NC

124

126
128

130

132
134

136

138
140

142
144

146

148
150

152

154
156

158

160
162

164
166

168

170
172

174

176
178

180

182
184

186
188

190

192
194

196

198
200

202

204

NC

MEM_A_CKE<1>

MEM_A_A<15>
MEM_A_A<14>

MEM_A_A<11>
MEM_A_A<7>

MEM_A_A<6>
MEM_A_A<4>

MEM_A_A<2>
MEM_A_A<0>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_BA<1>
MEM_A_RAS_L

MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_ODT<1>

=MEM_A_DQ<36>
=MEM_A_DQ<37>

=MEM_A_DM<4>

=MEM_A_DQ<38>
=MEM_A_DQ<39>

=MEM_A_DQ<44>
=MEM_A_DQ<45>

=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>

=MEM_A_DQ<46>
=MEM_A_DQ<47>

=MEM_A_DQ<52>
=MEM_A_DQ<53>

=MEM_A_DM<6>

=MEM_A_DQ<54>
=MEM_A_DQ<55>

=MEM_A_DQ<60>
=MEM_A_DQ<61>

=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>

=MEM_A_DQ<62>
=MEM_A_DQ<63>

MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

14 20 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

27

BI

27

BI

27

IN

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

IN

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

18 26 39

OUT

42

BI

42

IN

SPD Addr: 0xA0(Wr)/0xA1(Rd)

36

Page Notes

Power aliases required by this page:

- =PPLVDDR_S3_MEM_B

- =PPDDRVTT_S0_MEM_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

BOM options provided by this page:
(NONE)

D

C

B

=PPSPD_S0_MEM_B

7

A

8 7 5 4 2 1

C3140

2.2UF

6.3V
CERM

402-LF

2 1

2

C3121

1

0.1UF

20%
10V
CERM
402

2

1

C3122

0.1UF

20%
10V
CERM
402

2

C3123

1

0.1UF

20%
10V
CERM
402

D

=PPDDRVTT_S0_MEM_B

7

=PPLVDDR_S3_MEM_B

7

C3100

10UF

6.3V

345678

DDR3 Plane Stitching Caps (Space evenly across plane split)

1

20%

2

X5R
603

C3101

10UF

6.3V

1

2

C3110

20%

2

X5R
603

1

0.1UF

20%
10V
CERM
402

2

C3111

0.1UF

1

20%
10V
CERM
402

2

C3112

1

0.1UF

20%
10V
CERM
402

2

C3113

1

0.1UF

20%
10V
CERM
402

2

1

C3114

0.1UF

20%
10V
CERM
402

2

C3115

0.1UF

20%
10V

1

CERM
402

2

C3116

0.1UF

1

20%
10V
CERM
402

2

1

C3117

0.1UF

20%
10V
CERM
402

2

C3118

0.1UF

1

20%
10V
CERM
402

2

C3119

0.1UF

1

20%
10V
CERM
402

2

1

C3120

0.1UF

20%
10V
CERM
402

"Expansion" (bottom) slot

PPVREF_S3_MEM_VREFDQ_B

C3136

0.1UF

CERM

20%
10V

402

28

PPVREF_S3_MEM_VREFCA_B

1

C3135

2.2UF

20%

6.3V

212

CERM
402-LF

C3130

2.2UF

402-LF

6.3V
CERM

1

VREFDQ

3

VSS

1

1

C3131

0.1UF

20%

20%
10V

2

2

CERM
402

28

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

BI
BI

IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

=MEM_B_DQ<0>
=MEM_B_DQ<1>

=MEM_B_DM<0>

=MEM_B_DQ<2>
=MEM_B_DQ<3>

=MEM_B_DQ<8>
=MEM_B_DQ<9>

=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>

=MEM_B_DQ<10>
=MEM_B_DQ<11>

=MEM_B_DQ<16>
=MEM_B_DQ<17>

=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>

=MEM_B_DQ<18>
=MEM_B_DQ<19>

=MEM_B_DQ<24>
=MEM_B_DQ<25>

=MEM_B_DM<3>

=MEM_B_DQ<26>
=MEM_B_DQ<27>

5

DQ0

7

DQ1

VSS

DM0

VSS
DQ2
DQ3

VSS
DQ8
DQ9

VSS
DQS1*
DQS1

VSS
DQ10
DQ11

VSS
DQ16
DQ17

VSS
DQS2*
DQS2

VSS
DQ18
DQ19

VSS
DQ24
DQ25

VSS
DM3

VSS
DQ26
DQ27

VSS

CRITICAL

J3100

F-RT-BGA3

DDR3-SODIMM

KEY

(1 OF 2)

RESET*

9
11

13

15
17

19

21
23

25
27

29

31
33

35

37
39

41

43
45

47
49

51

53
55

57

59
61

63

65
67

69
71

DQ4
DQ5

DQS0*

DQS0

VSS

DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3*

DQS3

VSS
DQ30
DQ31

VSS

VSS

VSS

2

4
6

8

10
12

14

16
18

20

22
24

26
28

30

32
34

36

38
40

42

44
46

48
50

52

54
56

58

60
62

64

66
68

70
72

=MEM_B_DQ<4>
=MEM_B_DQ<5>

=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>

=MEM_B_DQ<6>
=MEM_B_DQ<7>

=MEM_B_DQ<12>
=MEM_B_DQ<13>

=MEM_B_DM<1>
MEM_RESET_L

=MEM_B_DQ<14>
=MEM_B_DQ<15>

=MEM_B_DQ<20>
=MEM_B_DQ<21>

=MEM_B_DM<2>

=MEM_B_DQ<22>
=MEM_B_DQ<23>

=MEM_B_DQ<28>
=MEM_B_DQ<29>

=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>

=MEM_B_DQ<30>
=MEM_B_DQ<31>

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

IN

14 25

IN

27

BI

27

BI

27

BI

27

BI

27

IN

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

C

516s0706

B

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

DDR3 SO-DIMM Connector B

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

31 OF 109

SHEET

26 OF 80

MEM_B_CKE<0>

14 20 73

IN

MEM_B_BA<2>

14 73

IN

MEM_B_A<12>

14 73

IN

MEM_B_A<9>

14 73

IN

MEM_B_A<8>

14 73

IN

MEM_B_A<5>

14 73

IN

MEM_B_A<3>

14 73

IN

MEM_B_A<1>

14 73

IN

MEM_B_CLK_P<0>

14 73

IN

MEM_B_CLK_N<0>

14 73

IN

MEM_B_A<10>

14 73

IN

MEM_B_BA<0>

14 73

IN

MEM_B_WE_L

14 73

IN

MEM_B_CAS_L

14 73

IN

MEM_B_A<13>

14 73

IN

MEM_B_CS_L<1>

14 73

IN

=MEM_B_DQ<32>

27

BI

=MEM_B_DQ<33>

27

BI

=MEM_B_DQS_N<4>

27

BI

=MEM_B_DQS_P<4>

27

BI

=MEM_B_DQ<34>

27

BI

=MEM_B_DQ<35>

27

BI

=MEM_B_DQ<40>

27

BI

=MEM_B_DQ<41>

27

BI

=MEM_B_DM<5>

27

IN

=MEM_B_DQ<42>

27

BI

=MEM_B_DQ<43>

27

BI

=MEM_B_DQ<48>

27

BI

=MEM_B_DQ<49>

27

BI

=MEM_B_DQS_N<6>

27

BI

=MEM_B_DQS_P<6>

27

BI

=MEM_B_DQ<50>

27

BI

=MEM_B_DQ<51>

27

BI

=MEM_B_DQ<56>

27

BI

=MEM_B_DQ<57>

27

BI

=MEM_B_DM<7>

27

27

27

IN

BI
BI

MEM_B_SA<0>

=MEM_B_DQ<58>
=MEM_B_DQ<59>

2

R3140

10K

5%
1/16W
MF-LF
402

1

MEM_B_SA<1>

1

R3141

1

10K

20%

5%
1/16W

2

MF-LF
402

2

73

75
77

NC

79

81
83

85

87
89

91

93
95

97
99

101

103
105

107

109
111

113

115
117

119
121

123

125

NC

127

129

131
133

135

137
139

141
143

145

147
149

151

153
155

157

159
161

163
165

167

169
171

173

175
177

179

181
183

185
187

189

191
193

195

197
199

201

203

205

209 210
211 212

SPD Addr: 0xA2(Wr)/0xA3(Rd)

KEY

CKE0

VDD
NC

CRITICAL

BA2

J3100

F-RT-BGA3

VDD
A12/BC*
A9

VDD
A8
A5

VDD
A3
A1

VDD
CK0
CK0*

VDD
A10/AP
BA0

VDD
WE*
CAS*

VDD
A13
S1*

VDD
TEST

VSS
DQ32
DQ33

VSS
DQS4*
DQS4

VSS
DQ34
DQ35

VSS
DQ40
DQ41

VSS
DM5

VSS
DQ42
DQ43

VSS
DQ48
DQ49

VSS
DQS6*
DQS6

VSS
DQ50
DQ51

VSS
DQ56
DQ57

VSS
DM7

VSS
DQ58
DQ59

VSS
SA0
VDDSPD
SA1

VTT

MTG PIN

MTG PIN

MTG PIN MTG PIN

MTG PIN

MTG PINS

(2 OF 2)

DDR3-SODIMM

VREFCA

EVENT*

MTG PIN

MTG PIN

MTG PIN

516s0706

CKE1

VDD

VDD

VDD

VDD

CK1*

VDD

RAS*

VDD

ODT0

VDD

ODT1

VDD

VSS
DQ36
DQ37

VSS

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5*

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7*

DQS7

VSS
DQ62
DQ63

VSS

VTT

A15
A14

A11

CK1

BA1

S0*

DM4

DM6

SDA
SCL

VDD

74

76
78

80

82
84

86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100

102

104
106

108

110
112

114

116
118

120
122

NC

124

126
128

130

132
134

136

138
140

142
144

146

148
150

152

154
156

158

160
162

164
166

168

170
172

174

176
178

180

182
184

186
188

190

192
194

196

198
200

202

204

206
208207

NC

MEM_B_CKE<1>

MEM_B_A<15>
MEM_B_A<14>

MEM_B_A<11>
MEM_B_A<7>

MEM_B_A<6>
MEM_B_A<4>

MEM_B_A<2>
MEM_B_A<0>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_BA<1>
MEM_B_RAS_L

MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_ODT<1>

=MEM_B_DQ<36>
=MEM_B_DQ<37>

=MEM_B_DM<4>

=MEM_B_DQ<38>
=MEM_B_DQ<39>

=MEM_B_DQ<44>
=MEM_B_DQ<45>

=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>

=MEM_B_DQ<46>
=MEM_B_DQ<47>

=MEM_B_DQ<52>
=MEM_B_DQ<53>

=MEM_B_DM<6>

=MEM_B_DQ<54>
=MEM_B_DQ<55>

=MEM_B_DQ<60>
=MEM_B_DQ<61>

=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>

=MEM_B_DQ<62>
=MEM_B_DQ<63>

MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL

14 20 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

14 73

IN

27

BI

27

BI

27

IN

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

IN

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

18 25 39

OUT

42

BI

42

IN

36

345678

2 1

MCP CHANNEL A DQS 0 -> DIMM A DQS 0

MEM_A_DQ<0>

14 73

MEM_A_DQ<1>

14 73

MEM_A_DQ<2>

14 73

MEM_A_DQ<3>

14 73

MEM_A_DQ<4>

14 73

MEM_A_DQ<5>

14 73

MEM_A_DQ<6>

14 73

MEM_A_DQ<7>

14 73

MEM_A_DM<0>

14 73

MEM_A_DQS_N<0>

14 73

MEM_A_DQS_P<0>

D

C

B

A

14 73

MCP CHANNEL A DQS 1 -> DIMM A DQS 1

MEM_A_DQ<8>

14 73

MEM_A_DQ<9>

14 73

MEM_A_DQ<10>

14 73

MEM_A_DQ<11>

14 73

MEM_A_DQ<12>

14 73

MEM_A_DQ<13>

14 73

MEM_A_DQ<14>

14 73

MEM_A_DQ<15>

14 73

MEM_A_DM<1>

14 73

MEM_A_DQS_N<1>

14 73

MEM_A_DQS_P<1>

14 73

MCP CHANNEL A DQS 2 -> DIMM A DQS 2

MEM_A_DQ<16>

14 73

MEM_A_DQ<17>

14 73

MEM_A_DQ<18>

14 73

MEM_A_DQ<19>

14 73

MEM_A_DQ<20>

14 73

MEM_A_DQ<21>

14 73

MEM_A_DQ<22>

14 73

MEM_A_DQ<23>

14 73

MEM_A_DM<2>

14 73

MEM_A_DQS_N<2>

14 73

MEM_A_DQS_P<2>

14 73

MCP CHANNEL A DQS 3 -> DIMM A DQS 3

MEM_A_DQ<24>

14 73

MEM_A_DQ<25>

14 73

MEM_A_DQ<26>

14 73

MEM_A_DQ<27>

14 73

MEM_A_DQ<28>

14 73

MEM_A_DQ<29>

14 73

MEM_A_DQ<30>

14 73

MEM_A_DQ<31>

14 73

MEM_A_DM<3>

14 73

MEM_A_DQS_N<3>

14 73

MEM_A_DQS_P<3>

14 73

MCP CHANNEL A DQS 4 -> DIMM A DQS 4

MEM_A_DQ<32>

14 73

MEM_A_DQ<33>

14 73

MEM_A_DQ<34>

14 73

MEM_A_DQ<35>

14 73

MEM_A_DQ<36>

14 73

MEM_A_DQ<37>

14 73

MEM_A_DQ<38>

14 73

MEM_A_DQ<39>

14 73

MEM_A_DM<4>

14 73

MEM_A_DQS_N<4>

14 73

MEM_A_DQS_P<4>

14 73

MCP CHANNEL A DQS 5 -> DIMM A DQS 5

MEM_A_DQ<40>

14 73

MEM_A_DQ<41>

14 73

MEM_A_DQ<42>

14 73

MEM_A_DQ<43>

14 73

MEM_A_DQ<44>

14 73

MEM_A_DQ<45>

14 73

MEM_A_DQ<46>

14 73

MEM_A_DQ<47>

14 73

MEM_A_DM<5>

14 73

MEM_A_DQS_N<5>

14 73

MEM_A_DQS_P<5>

14 73

MCP CHANNEL A DQS 6 -> DIMM A DQS 6

MEM_A_DQ<48>

14 73

MEM_A_DQ<49>

14 73

MEM_A_DQ<50>

14 73

MEM_A_DQ<51>

14 73

MEM_A_DQ<52>

14 73

MEM_A_DQ<53>

14 73

MEM_A_DQ<54>

14 73

MEM_A_DQ<55>

14 73

MEM_A_DM<6>

14 73

MEM_A_DQS_N<6>

14 73

MEM_A_DQS_P<6>

14 73

MCP CHANNEL A DQS 7 -> DIMM A DQS 7

MEM_A_DQ<56>

14 73

MEM_A_DQ<57>

14 73

MEM_A_DQ<58>

14 73

MEM_A_DQ<59>

14 73

MEM_A_DQ<60>

14 73

MEM_A_DQ<61>

14 73

MEM_A_DQ<62>

14 73

MEM_A_DQ<63>

14 73

MEM_A_DM<7>

14 73

MEM_A_DQS_N<7>

14 73

MEM_A_DQS_P<7>

14 73

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_A_DQ<7>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<5>
=MEM_A_DQ<1>
=MEM_A_DQ<0>
=MEM_A_DQ<6>
=MEM_A_DQ<4>
=MEM_A_DM<0>
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>

=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQ<14>
=MEM_A_DQ<10>
=MEM_A_DQ<13>
=MEM_A_DQ<12>
=MEM_A_DQ<15>
=MEM_A_DQ<11>
=MEM_A_DM<1>
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>

=MEM_A_DQ<17>
=MEM_A_DQ<20>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<21>
=MEM_A_DQ<16>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DM<2>
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>

=MEM_A_DQ<29>
=MEM_A_DQ<26>
=MEM_A_DQ<31>
=MEM_A_DQ<27>
=MEM_A_DQ<28>
=MEM_A_DQ<25>
=MEM_A_DQ<24>
=MEM_A_DQ<30>
=MEM_A_DM<3>
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>

=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<35>
=MEM_A_DQ<32>
=MEM_A_DQ<36>
=MEM_A_DQ<34>
=MEM_A_DQ<33>
=MEM_A_DQ<37>
=MEM_A_DM<4>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>

=MEM_A_DQ<44>
=MEM_A_DQ<45>
=MEM_A_DQ<47>
=MEM_A_DQ<43>
=MEM_A_DQ<42>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DQ<46>
=MEM_A_DM<5>
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>

=MEM_A_DQ<51>
=MEM_A_DQ<53>
=MEM_A_DQ<50>
=MEM_A_DQ<54>
=MEM_A_DQ<48>
=MEM_A_DQ<49>
=MEM_A_DQ<55>
=MEM_A_DQ<52>
=MEM_A_DM<6>
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>

=MEM_A_DQ<56>
=MEM_A_DQ<61>
=MEM_A_DQ<62>
=MEM_A_DQ<59>
=MEM_A_DQ<57>
=MEM_A_DQ<60>
=MEM_A_DQ<63>
=MEM_A_DQ<58>
=MEM_A_DM<7>
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

8 7 5 4 2 1

MCP CHANNEL B DQS 0 -> DIMM B DQS 0

MEM_B_DQ<0>

14 73

MEM_B_DQ<1>

14 73

MEM_B_DQ<2>

14 73

MEM_B_DQ<3>

14 73

MEM_B_DQ<4>

14 73

MEM_B_DQ<5>

14 73

MEM_B_DQ<6>

14 73

MEM_B_DQ<7>

14 73

MEM_B_DM<0>

14 73

MEM_B_DQS_N<0>

14 73

MEM_B_DQS_P<0>

14 73

MCP CHANNEL B DQS 1 -> DIMM B DQS 2

MEM_B_DQ<8>

14 73

MEM_B_DQ<9>

14 73

MEM_B_DQ<10>

14 73

MEM_B_DQ<11>

14 73

MEM_B_DQ<12>

14 73

MEM_B_DQ<13>

14 73

MEM_B_DQ<14>

14 73

MEM_B_DQ<15>

14 73

MEM_B_DM<1>

14 73

MEM_B_DQS_N<1>

14 73

MEM_B_DQS_P<1>

14 73

MCP CHANNEL B DQS 2 -> DIMM B DQS 1

MEM_B_DQ<16>

14 73

MEM_B_DQ<17>

14 73

MEM_B_DQ<18>

14 73

MEM_B_DQ<19>

14 73

MEM_B_DQ<20>

14 73

MEM_B_DQ<21>

14 73

MEM_B_DQ<22>

14 73

MEM_B_DQ<23>

14 73

MEM_B_DM<2>

14 73

MEM_B_DQS_N<2>

14 73

MEM_B_DQS_P<2>

14 73

MCP CHANNEL B DQS 3 -> DIMM B DQS 3

MEM_B_DQ<24>

14 73

MEM_B_DQ<25>

14 73

MEM_B_DQ<26>

14 73

MEM_B_DQ<27>

14 73

MEM_B_DQ<28>

14 73

MEM_B_DQ<29>

14 73

MEM_B_DQ<30>

14 73

MEM_B_DQ<31>

14 73

MEM_B_DM<3>

14 73

MEM_B_DQS_N<3>

14 73

MEM_B_DQS_P<3>

14 73

MCP CHANNEL B DQS 4 -> DIMM B DQS 4

MEM_B_DQ<32>

14 73

MEM_B_DQ<33>

14 73

MEM_B_DQ<34>

14 73

MEM_B_DQ<35>

14 73

MEM_B_DQ<36>

14 73

MEM_B_DQ<37>

14 73

MEM_B_DQ<38>

14 73

MEM_B_DQ<39>

14 73

MEM_B_DM<4>

14 73

MEM_B_DQS_N<4>

14 73

MEM_B_DQS_P<4>

14 73

MCP CHANNEL B DQS 5 -> DIMM B DQS 5

MEM_B_DQ<40>

14 73

MEM_B_DQ<41>

14 73

MEM_B_DQ<42>

14 73

MEM_B_DQ<43>

14 73

MEM_B_DQ<44>

14 73

MEM_B_DQ<45>

14 73

MEM_B_DQ<46>

14 73

MEM_B_DQ<47>

14 73

MEM_B_DM<5>

14 73

MEM_B_DQS_N<5>

14 73

MEM_B_DQS_P<5>

14 73

MCP CHANNEL B DQS 6 -> DIMM B DQS 6

MEM_B_DQ<48>

14 73

MEM_B_DQ<49>

14 73

MEM_B_DQ<50>

14 73

MEM_B_DQ<51>

14 73

MEM_B_DQ<52>

14 73

MEM_B_DQ<53>

14 73

MEM_B_DQ<54>

14 73

MEM_B_DQ<55>

14 73

MEM_B_DM<6>

14 73

MEM_B_DQS_N<6>

14 73

MEM_B_DQS_P<6>

14 73

MCP CHANNEL B DQS 7 -> DIMM B DQS 7

MEM_B_DQ<56>

14 73

MEM_B_DQ<57>

14 73

MEM_B_DQ<58>

14 73

MEM_B_DQ<59>

14 73

MEM_B_DQ<60>

14 73

MEM_B_DQ<61>

14 73

MEM_B_DQ<62>

14 73

MEM_B_DQ<63>

14 73

MEM_B_DM<7>

14 73

MEM_B_DQS_N<7>

14 73

MEM_B_DQS_P<7>

14 73

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQ<5>
=MEM_B_DQ<4>
=MEM_B_DQ<3>
=MEM_B_DQ<7>
=MEM_B_DQ<1>
=MEM_B_DQ<0>
=MEM_B_DQ<6>
=MEM_B_DQ<2>
=MEM_B_DM<0>
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>

=MEM_B_DQ<21>
=MEM_B_DQ<20>
=MEM_B_DQ<18>
=MEM_B_DQ<19>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQ<22>
=MEM_B_DQ<23>
=MEM_B_DM<2>
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>

=MEM_B_DQ<14>
=MEM_B_DQ<11>
=MEM_B_DQ<12>
=MEM_B_DQ<8>
=MEM_B_DQ<10>
=MEM_B_DQ<15>
=MEM_B_DQ<13>
=MEM_B_DQ<9>
=MEM_B_DM<1>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>

=MEM_B_DQ<28>
=MEM_B_DQ<24>
=MEM_B_DQ<26>
=MEM_B_DQ<30>
=MEM_B_DQ<25>
=MEM_B_DQ<29>
=MEM_B_DQ<31>
=MEM_B_DQ<27>
=MEM_B_DM<3>
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>

=MEM_B_DQ<32>
=MEM_B_DQ<37>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<36>
=MEM_B_DQ<33>
=MEM_B_DQ<39>
=MEM_B_DQ<38>
=MEM_B_DM<4>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>

=MEM_B_DQ<42>
=MEM_B_DQ<44>
=MEM_B_DQ<41>
=MEM_B_DQ<40>
=MEM_B_DQ<47>
=MEM_B_DQ<45>
=MEM_B_DQ<46>
=MEM_B_DQ<43>
=MEM_B_DM<5>
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>

=MEM_B_DQ<49>
=MEM_B_DQ<53>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<52>
=MEM_B_DQ<48>
=MEM_B_DQ<55>
=MEM_B_DQ<54>
=MEM_B_DM<6>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>

=MEM_B_DQ<62>
=MEM_B_DQ<63>
=MEM_B_DQ<56>
=MEM_B_DQ<60>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DQ<57>
=MEM_B_DQ<61>
=MEM_B_DM<7>
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

26

SYNC_MASTER=K18_MLB

PAGE TITLE

DDR3 BYTE/BIT SWAPS-K6

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/19/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

32 OF 109

SHEET

27 OF 80

SIZE

D

C

B

A

D

36

345678

2 1

=PP3V3_S3_VREFMRGN

7

OMIT

R3300

SHORT

1 2

D

OMIT

R3310

SHORT

1 2

C

Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

116S0004

B

116S0004

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm

NONE

MIN_NECK_WIDTH=0.2 mm

NONE

VOLTAGE=3.3V

NONE

402

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm

NONE

MIN_NECK_WIDTH=0.2 mm

NONE

VOLTAGE=3.3V

NONE

402

QTY

2
2

VREFMRGN:YESVREFMRGN:YES

1

1

2

C3310

0.1UF

CERM

C3301

0.1UF

20%
10V

2

CERM
402

20%
10V

402

7

9

10

1

2

3
4
5

1
2

REFERENCE DES

8
VDD

SCL

MSOP

SDA

A0

A1

GND

3

VCC

U3310

PCA9557

QFN

A0
A1
A2

SCL
SDA

THRM

GND

PAD

17

R3321,R3323
R3331,R3333

C3300

2.2UF

20%

6.3V
CERM

402-LF

=I2C_VREFDACS_SCL

42

IN

=I2C_VREFDACS_SDA

42

BI

Addr=0x98(WR)/0x99(RD)

VREFMRGN:YES

Addr=0x30(WR)/0x31(RD)

=I2C_PCA9557D_SCL

42

IN

=I2C_PCA9557D_SDA

42

BI

PCA9557D_RESET_L

24

IN

RST* on ’platform reset’ so that system
watchdog will disable margining.

NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.

DESCRIPTION

RES,MTL FILM,0,5%,0402,SM,LF
RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL

VREFMRGN:YES

U3300

16

VOUTA

2

VOUTB

4

VOUTC

5

VOUTD

DAC5574

CRITICAL

VREFMRGN:YES

16

6

(OD)

P0

7

P1

9

P2

10

P3

11

P4

12

P5

13

P6

14

P7

15

RESET*

8

VREFMRGN_SODIMMA_DQ
VREFMRGN_SODIMMB_DQ
VREFMRGN_SODIMMS_CA
VREFMRGN_MEMVREG_FBVREF

NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable
both at the same time!

NC

VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_MEMVREG_EN

(RSVD for FBVREF)

NC

VREFMRGN_CPUGTLREF_EN

CRITICAL

CRITICAL
CRITICAL

BOM OPTION

VREFMRGN:NO
VREFMRGN:NO

VREFMRGN:YES

VREFMRGN:YES

1

R3320

100K

5%
1/16W
MF-LF
402

2

VREFMRGN:YES

1

R3325

100K

5%
1/16W
MF-LF
402

VREFMRGN:YES

2

VREFMRGN:YES

1

R3330

100K

5%
1/16W
MF-LF
402

2

VREFMRGN:YES

1

R3335

100K

5%

VREFMRGN:YES

1/16W
MF-LF
402

2

C3320

0.1UF

CERM

C3330

0.1UF

CERM

C3340

0.1UF

20%
10V

402

20%
10V

402

CERM

20%
10V

402

1

2

1

2

1

2

B1

V+

V-

B4

B1

V+

V-

B4

B1

V+

V-

B4

B1

V+

V-

B4

B1

V+

V-

B4

U3320

MAX4253

UCSP

A1

A4

VREFMRGN:YES

U3320

MAX4253

UCSP

C1

VREFMRGN:YES

C4

U3330

MAX4253

UCSP

A1

VREFMRGN:YES

A4

U3330

MAX4253

UCSP

C1

VREFMRGN:YES

C4

U3340

MAX4253

UCSP

C1

VREFMRGN:YES

C4

A2

A3

C2

C3

A2

A3

C2

C3

C2

C3

NOTE: Must not enable more than two SO-DIMM margining
buffers at once or VRef source may be overloaded.

VREFMRGN:YES

=PPVTT_S3_DDR_BUF

7

60

10mA max load

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_MEMVREG_BUF

R3321

200

1 2

1%
1/16W
MF-LF

402

VREFMRGN:YES

R3322

133

1 2

1%
1/16W
MF-LF

402

VREFMRGN:YES

R3323

200

1 2

1%
1/16W
MF-LF

402

VREFMRGN:YES

R3324

133

1 2

1%
1/16W
MF-LF

402

VREFMRGN:YES

R3331

200

1 2

1%
1/16W
MF-LF

402

VREFMRGN:YES

R3332

133

1 2

1%
1/16W
MF-LF

402

VREFMRGN:YES

R3333

200

1 2

1%
1/16W
MF-LF

402

VREFMRGN:YES

R3334

133

1 2

1%
1/16W
MF-LF

402

VREFMRGN:YES

R3342

22.6K

1 2

1%
1/16W
MF-LF

402

PLACE_NEAR=J2900.1:2.54mm

PPVREF_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

PLACE_NEAR=R3321.2:1mm

PLACE_NEAR=J3100.1:2.54mm

PPVREF_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

PLACE_NEAR=R3323.2:1mm

PLACE_NEAR=J2900.126:2.54mm

PPVREF_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

PLACE_NEAR=R3331.2:1mm

PLACE_NEAR=J3100.126:2.54mm

PPVREF_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

PLACE_NEAR=R3333.2:1mm

DDRREG_FB

PLACE_NEAR=R7320.2:1mm

25

D

26

25

26

60

OUT

C

B

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA
BOM options provided by this page:

VREFMRGN:YES - Stuffs VREF Margining
Circuitry.
VREFMRGN:NO - Bypasses VREF Margining
Circuitry.

A

DAC Channel:
PCA9557D Pin:
Nominal value
Margined target:
DAC range:
VRef current:
DAC step size:

8 7 5 4 2 1

MEM A VREF DQ

A
1 2

MEM B VREF DQ

B

MEM A VREF CA

C
3

0.75V (DAC: 0x3A)

0.300V - 1.200V (+/- 450mV)

0.000V - 1.501V (0x00 - 0x74)
+3.4mA - -3.4mA (- = sourced)

7.69mV / step @ output

MEM B VREF CA

C
4

VREFMRGN:YES

1

R3340

100K

5%
1/16W
MF-LF
402

2

VREFMRGN:YES

1

R3345

100K

5%
1/16W
MF-LF
402

2

MEM VREG

D
5

1.5V (DAC: 0x3A)

1.998V - 1.002V (+/- 498mV)

0.000V - 1.501V (0x00 - 0x74)

0.7V (DAC: 0x8B)

0.200V - 1.050V (+/- 500mV)

0.000V - 1.191V (0x00 - 0x5C)

B1

V+

V-

B4

U3340

MAX4253

UCSP

A1

VREFMRGN:YES

A4

A2

A3

CPU GTLREF (FSB)

D
7

VREFMRGN_CPUGTLREF_BUF

+33uA - -33uA (- = sourced) +750uA - -528uA (- = sourced)

8.59mV / step @ output

9.24mV / step @ output

36

VREFMRGN:YES

R3344

267

1 2

1%
1/16W
MF-LF

402

CPU_GTLREF

PLACE_NEAR=R1005.2:1mm

SYNC_MASTER=T27_MLB

PAGE TITLE

FSB/DDR3 Vref Margining

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

9

72

OUT

SYNC_DATE=09/29/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

33 OF 109

SHEET

28 OF 80

SIZE

A

D

5V S3 WLAN FET

MOSFET

CHANNEL

RDS(ON)

LOADING

345678

2 1

TPCP8102

P-TYPE

26 mOhm @4.5V

0.8 A (EDP)

D

L3404

CRITICAL
518S0610

J3401

20347-325E-12

F-RT-SM

31

1
2
3
4
5
6
7
8
9
10
11
12
13
14

C

15

NC

16

NC

17
18
19
20
21
22
23
24
25

26
27
28
29
30

32

(AP_CLKREQ_Q_L)

(AP_RESET_CONN_L)

PCIE_AP_D2R_P
PCIE_AP_D2R_N

PCIE_AP_R2D_P

6

74

PCIE_AP_R2D_N

6

74

OUT
OUT

PCIE_CLK100M_AP_CONN_P

6

79

PCIE_CLK100M_AP_CONN_N

6

79

PCIE_WAKE_L

PP5V_S3_BTCAMERA_F

6

I2C_ALS_SDA
I2C_ALS_SCL

USB_CAMERA_CONN_P

6

79

USB_CAMERA_CONN_N

79

6

USB_BT_CONN_P

6

79

USB_BT_CONN_N

6

79

6

15 74

6

15 74

1 2

16V

C3430

6

15 24

OUT

42

BI

42

IN

PLACEMENT_NOTE=Place close to J3401.

C3431

1 2

0.1uF

10%

0.1uF

402X5R10%

PLACEMENT_NOTE=Place close to J3401.

90-OHM-100MA

4 3

1 2

PLACEMENT_NOTE=Place close to J3401.

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

4 3

1 2

PLACEMENT_NOTE=Place close to J3401.

4 3

1 2

16V X5R

CRITICAL

L3401

DLP11S

SYM_VER-1

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

CRITICAL

L3402

90-OHM
DLP0NS

SYM_VER-1

CRITICAL

L3403

90-OHM
DLP0NS

SYM_VER-1

PLACEMENT_NOTE=Place close to J3401.

PCIE_AP_R2D_C_P

402

PCIE_AP_R2D_C_N

AIRPORT

ALS
CAMERA

USB_CAMERA_P

USB_CAMERA_N

BLUETOOTH

USB_BT_P

USB_BT_N

1000 mA peak

750 mA nominal max

15 74

IN

15 74

IN

IN

IN

275 mA peak

206 mA nominal max

OUT

OUT

15 74

15 74

C3452

17 75

17 75

BI

BI

PP5V_WLAN

6

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

0.1uF

20%
10V

CERM

402

17 75

17 75

1

2

FERR-120-OHM-1.5A

C3422

0.1uF

20%
10V

CERM

402

PLACEMENT_NOTE=Place close to J3401.

0402-LF

2 1

1

2

L3405

2 1

FERR-120-OHM-1.5A

0402-LF

1

1

C3421

0.1uF

20%
10V

CERM

402

PLACEMENT_NOTE=Place close to Q3450.

C3420

10UF

20%
10V

2

2

X5R
805

PLACEMENT_NOTE=Place close to Q3450.

=PP5V_S3_BTCAMERA

PP5V_WLAN_F

29

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

7

7 85 6

C3450

0.1UF

1 2

10%
16V
X5R
402

CRITICAL

Q3450

TPCP8102

23V1K-SM

D

S

G

4

P5VWLAN_SS

31 2

C3451

0.033UF

=PP5V_S3_WLAN

1

1

10%
16V

2

X5R
402

R3450

33K

1 2

5%
1/16W
MF-LF

402

R3451

10K

5%
1/16W
MF-LF
402

2

PM_WLAN_EN_L

7

65

IN

B

PP5V_WLAN_F

29

D

C

B

Supervisor & CLKREQ# Isolation

=PP3V3_S3_WLAN

7

1

3

6
8

C3440

0.1uF

20%
10V

2

CERM
402

AP_RESET_L

AP_PWR_EN
AP_CLKREQ_L

24

IN

18 65

IN

15

OUT

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

RIGHT CLUTCH CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

34 OF 109

SHEET

29 OF 80

36

121

5%

402

2

R3453

392K

1%
1/16W
MF-LF
402

P3V3WLAN_VMON

WF: Need pull-up?

AP_RESET_CONN_L

6

R3440

100K

1/16W
MF-LF

DLY = 60 ms +/- 20%

AP_CLKREQ_Q_L

6

1

R3454

A

97.6K

1%
1/16W
MF-LF
402

2

CRITICAL

2

4

7

1

VDD

U3440

SLG4AP016V

TDFN

SENSE

+

-

0.7V

THRM

PAD

DLY

GND

9

RESET*

IN

MR*

EN

OUT

(OD)

5

8 7 5 4 2 1

345678

2 1

Caesar IV Support

BCM57765

0

SDCONN_DATA<0>

31 76

BI

SDCONN_DATA<1>

31 76

D

=PP3V3_S3_CARDREADER

7

GL137

R3511

0

1 2

5%
1/16W
MF-LF

402

PP3V3_S3_CARDREADER_DVDD

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

2

GL137

L3500

0.22UH

0805-1

1

PP3V3_S3_CARDREADER_AVDD

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

GL137

C3500

10UF

6.3V

GL137

C3514

10UF

6.3V

20%
X5R

603

20%
X5R

603

212

1

2

BYPASS=U3500.15:16:5 mm

GL137

1

C3501

0.1UF

20%

10V

CERM
402

BYPASS=U3500.6:5:5 mm

GL137

1

C3504

0.1UF

20%

10V

2

CERM
402

BYPASS=U3500.26:27:5 mm

GL137

1

C3502 C3503

0.1UF

20%

10V

2

CERM
402

BYPASS=U3500.11:12:5 mm

GL137

1

C3508

0.1UF

20%

10V

2

CERM
402

BYPASS=U3500.35:34:5 mm

GL137

1

0.1UF

20%

10V

2

CERM
402

BI

SDCONN_DATA<2>

31 76

BI

SDCONN_DATA<3>

31 76

BI

SDCONN_DATA<4..7>

31 76

BI

SDCONN_CLK

31 76

IN

SDCONN_CMD

31 76

OUT

SDCONN_WP

31

OUT

SDCONN_CD

31

OUT

=PP3V3_S0_SDCONN

7

Keep this net short!

BYPASS=U3500.4:5:5 mm

C

GL137

R3507

10K

1/16W
MF-LF

NO STUFF

R3509

10K

1/16W
MF-LF

402

402

5%

5%

121

121

NO STUFF

R3508

10K

5%
1/16W
MF-LF
402

2

GL137

R3510

10K

5%
1/16W
MF-LF
402

2

GL137

C3506

0.1UF

17 75

17 75

NO STUFF

R3503

1M

1 2

5%
1/16W
MF-LF

402

CRITICAL

GL137

Y3500

12.000M-100PPM

B

GL137

C3511

33PF

1 2

50V

CERM

8X4.5X1.4-SM

5%

402

21

GL137

C3512

33PF

1 2

5%

50V

CERM

402

18

GL137

R3506

SDCARD_RESET

IN

715

1/16W
MF-LF

SSM6N15FEAPE

GL137

1

1

R3502

0

5%

1%

1/16W
MF-LF
402

402

2

2

GL137

Q3500

SOT563

5

PP1V8_S3_CARDREADER

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=1.8V

1

20%

10V

2

CERM

402

USB_SDCARD_N

BI

USB_SDCARD_P

BI

GL137_GPIO1
GL137_GPIO2

GL137_CLK12M_X1
GL137_CLK12M_X2

GL137_RREF
GL137_TESTMOD
GL137_RESET_L

3

D

SG

4

SDCARD_PLT_RST

SSM6N15FEAPE

NO STUFF

C3513

GL137

Q3500

SOT563

0.1UF

10V

CERM

1

GL137

R3504

0

1 2

5%
1/16W
MF-LF

402

R3505

39K

5%
1/16W
MF-LF
402

2

1

2

NO STUFF

C3515

10PF

5%

50V

CERM
402-1

1

1

C3505

0.1UF

20%

10V

2

2

CERM
402

10K

1/16W
MF-LF

10K

1/16W
MF-LF

C3507

2.2UF

20%

6.3V

1

CERM1

5%

402

5%

402

603

2

1

2

NC

364325

35

11

6

26

15

4

AVDD

DVDD

PMOSO

LQFP

GL137

GND

12

(IPD)
(IPD)
(IPU)
(IPU)

(IPU)

(IPD)
(IPD)
(IPD)

(IPU)
(IPD)

VDD5V

342716

SD_WP

SD_CMD

PDMOD

SD_CDZ

XD_CDZ

XD_CE

XD_WEZ
XD_RBZ
XD_WPZ

MS_INS

MS_BS

CLK

D0
D1
D2
D3
D4
D5
D6
D7

40

37
29
28
30
32
38

39

SD_CLK_R

76

3
41
2

GL137_PDMOD

23

1

NC

31

NC

42

NC

44

NC

45

NC

24

NC

33

NC

VDD18O

(IPD)

U3500

GL137A

CRITICAL

(IPD)

(IPU)

9

5

7

DM

8

DP

48

GPIO1

47

GPIO2

46

GPIO3

NC

19

SK

NC

20

CS

NC

21

DO

NC

22

DI

NC

13

X1

14

X2

10

RREF

17

TESTMOD

18

EXTRSTZ*

1

20%

2

402

6

D

GL137

R3512

NO STUFF

R3513

PDMOD: POWER DOWN MODES
NC = DISABLE (DEFAULT)
10K LOW = POWER SAVING MODE ENABLE
10K HIGH = REMOTE WAKE UP ENABLE

R3550
R3551
R3552
R3553

R3554

R3556

PP3V3_SW_SD_PWR

MIN_LINE_WIDTH=0.80 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

MAX CURRENT = 800 MA

SD_CLK

30 76

SD_CMD

30 76

SD_D<0>

30 76

SD_D<1>

30 76

SD_D<2>

30 76

SD_D<3>

30 76

SD_D<4>

30 76

SD_D<5>

30 76

SD_D<6>

30 76

SD_D<7>

30 76

SD_WP

30

SD_CD_L

30

BCM57765

0

BCM57765

0

BCM57765

0

BCM57765

0

BCM57765

0

1 2

BCM57765

R3555

1 2

1 2

1 2

1 2

1 2

0

1 2

5%
1/10W
MF-LF

603

5%

1/16W MF-LF

5% 402

5%

5%

1/16W

5%

1/16W

SD-CARD-K19-K24

MF-LF1/16W

MF-LF1/16W

MF-LF1/16W

MF-LF

MF-LF

CRITICAL

J3500

F-RT-TH

3
6
5
2
7
8
9

1
10
11
12
13
14
15
16

4

17
18
19
20

402

4025%

402

402

402

VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2
CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD

SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN

516-0225

SD_D<0>

SD_D<1>

SD_D<2>

SD_D<3>

SD_D<4..7>

MAKE_BASE=TRUE

SD_CLK

SD_CMD

MAKE_BASE=TRUE

SD_WP

MAKE_BASE=TRUE

SD_CD_L

MAKE_BASE=TRUE

30 76

30 76

30 76

30 76

30 76

30 76

30 76

30

30

D

C

B

A

ADDED SERIES RESISTOR TO SD_CMD, MAX CURRENT NUMBER CHANGED TO 800MA

8 7 5 4 2 1

SDCARD_PLT_RST_L

24

IN

2

SG

1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

SecureDigital Card Reader

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/30/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

35 OF 109

SHEET

30 OF 80

36

345678

BCM57765 SR pins are internal 1.2V switching regulator.
If unused: Okay to float all 4 pins. (Broadcom not so sure now)
If used: VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor, VFB to =PP1V2_ENET_PHY

BCM57765

=PP3V3_ENET_PHY

7

86mA (1000base-T, Caesar II)

D

24 31 64

CRITICAL

L3900

FERR-600-OHM-0.5A

CRITICAL

L3905

FERR-600-OHM-0.5A

CRITICAL

L3910

FERR-600-OHM-0.5A

21

PP3V3_ENET_PHY_XTALVDDH

31 31

SM

SM

SM

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

21

PP3V3_ENET_PHY_BIASVDDH

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

21

PP3V3_ENET_PHY_AVDDH

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

R3915

C3900

0.1UF

X7R-CERM

R3910

4.7K

1/16W
MF-LF

0

1 2

5%
1/16W
MF-LF

402

10%
16V

402

1

5%

402

2

BCM57765

R3900

1

2

1

C3910

0.1UF

10%
16V

2

X7R-CERM
402

1 2

TP_BCM57765_SR_VDDP
BCM57765_SR_VDD

31 64

BCM57765_VDDO_PIN20

31

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

0

BCM57765_XTALVDDH

MIN_LINE_WIDTH=0.4 mm

5%

MIN_NECK_WIDTH=0.2 mm

1/16W

VOLTAGE=3.3V

MF-LF

402

1

2

1

2

C3905

0.1UF

10%
16V
X7R-CERM
402

C3911

0.1UF

10%
16V
X7R-CERM
402

BCM57765_SR_LX
BCM57765_SR_VFB

31 64 64

31 64

C3921

0.1UF

X7R-CERM

C3926

0.1UF

X7R-CERM

C3931

0.1UF

X7R-CERM

10%
16V

402

10%
16V

402

10%
16V

402

PP1V2_ENET_PHY_AVDDL

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

1

1

C3920

4.7UF

10%

6.3V

2

2

X5R-CERM
603

PP1V2_ENET_PHY_PCIEPLL

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

1

1

C3925

4.7UF

10%

6.3V

2

2

X5R-CERM
603

PP1V2_ENET_PHY_GPHYPLL

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

1

1

C3930

4.7UF

10%

6.3V

2

2

X5R-CERM
603

CRITICAL

L3920

FERR-600-OHM-0.5A

CRITICAL

L3925

FERR-600-OHM-0.5A

CRITICAL

L3930

FERR-600-OHM-0.5A

21

SM

21

SM

21

SM

2 1

=PP1V2_ENET_PHY

396mA (1000base-T, Caesar II)

7

31

D

BCM57765

R3940

4.7K

1/16W

=PP3V3_S0_ENETPHY

7

C

PCIE_ENET_D2R_N

15 74

OUT

PCIE_ENET_D2R_P

15 74

OUT

PCIE_ENET_R2D_C_P

15 74

IN

PCIE_ENET_R2D_C_N

15 74

IN

=ENET_WAKE_L

24 31

OUT

(See note)
WAKE#
Must isolate from PCIe WAKE# if PHY

is powered-down in S3/S5. Standard
N-channel FET isolation suggested.

B

If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.

31

C3955

BCM57765

R3943

1 2

C3950

0.1uF

1 2

10%
16V
X5R
402

0.1uF

1 2

10%
16V
X5R
402

0

5%
1/16W
MF-LF

402

C3951

0.1uF

1 2

10%
16V
X5R
402

C3956

0.1uF

1 2

10%
16V
X5R
402

1

2

BCM57765

R3942

1K

5%
1/16W
MF-LF
402

15 74

15 74

24 76

15

18

24

24

MF-LF

IN
IN

IN

OUT

8

IN

IN

OUT

PHY Non-Volatile Memory

ROM contains MAC address, PCIe config
info as well as code for Bonjour proxy.
Required for proper PHY operation.

=PP3V3_ENET_PHY

7

24 31 64

BCM5764_SCLK

A

31

BCM5764_CS_L

31

(Required ROM size TBD)

6

VCC

U3990

AT45DB011D

SCK

CS*

WP*

RESET*

SOIC-8S1

OMIT

GND

7

SI

SO

2

4

5

3

1

C3990

0.1UF

10%
16V

2

X7R-CERM
402

1

8

BCM57765

1

R3990

4.7K

5%
1/16W
MF-LF
402

2

BCM5764_MOSI

BCM5764_MISO

BCM5764M

1

R3997

4.7K

5%
1/16W
MF-LF
402

2

NOTE: Pull-down on SO plus internal pull-ups on
other 3 SPI pins configures BCM57765 for the
Atmel AT45DB011D (1Mbit) ROM. If a different
ROM is used then the straps must change.
NOTE: BCM5764M requires SI pull-down instead of SO.

8 7 5 4 2 1

BCM57765

121

R3941

4.7K

5%

5%

1/16W
MF-LF
402

402

2

BCM57765_VMAIN_PRSNT

31

PCIE_ENET_D2R_C_N

74

74

PCIE_ENET_D2R_C_P
PCIE_ENET_R2D_P

74

74

PCIE_ENET_R2D_N
PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

C3915

4.7UF

6.3V

X5R-CERM

10%

603

ENET_RESET_L
ENET_CLKREQ_L
BCM57765_WAKE_L

ENET_LOW_PWR

31

BCM57765_SMB_CLK
BCM57765_SMB_DATA

BCM5764_SCLK

31

BCM5764_MISO

31

BCM5764_MOSI

31

BCM5764_CS_L

31

TP_BCM5764_SPD100LED_L
TP_BCM5764_TRAFFICLED_L

BCM5764_CLK25M_XTALI
BCM5764_CLK25M_XTALO

BCM5764_RDAC

1

R3965

1.24K

1%
1/16W
MF-LF
402

2

31

31

212

1

C3916

0.1UF

10%
16V
X7R-CERM
402

4248371772062

AVDDH

58 40

SMB_DATA

27

PCIE_TXD_N

28

PCIE_TXD_P

33

PCIE_RXD_P

34

PCIE_RXD_N

31

PCIE_REFCLK_P

30

PCIE_REFCLK_N

11

PERST*

12

CLKREQ*

3

LINKLED*

4

LOW_PWR

6

VDDC

10

UART_MODE

66

SCLK

64

SI

65

SO

63

CS*

2

SPD100LED*

67

TRAFFICLED*

18

XTALI

19

XTALO

38

RDAC

VDDC

VDDIO

BIASVDDH

(IPD)

(IPD)
(OD)
(OD)

(IPD)

(IPD-BCM5764M)

(IPU)

56

VDDIO

VDDIO

XTALVDDH

14

VDDC

CRITICAL

BCM5764M

13

15

16

WAKE*

VDDIO

REGCTL12

OMIT

U3900

QFN-8X8

VERSION 2

THRM_PAD

69

BCM5764M pin-function
60-ENERGY_DET

394551

AVDDL

(IPD)

13-WAKE*
53-VMAIN_PRSNT
59-SMB_CLK

58-SMB_DATA
54-VAUX_PRSNT
16-VDDIO

20-XTALVDDH
55-VDDC

17-VDDC
14-VDDC
06-VDDC

26-PCIE_VDDL

61

35

293236

VDDC

GPHY_PLLVDDL

PCIE_PLLVDDL

TRD0_P
TRD0_N
TRD1_P
TRD1_N
TRD2_P
TRD2_N
TRD3_P
TRD3_N

GPIO_0/SERIAL_DO
GPIO_1/SERIAL_DI

GPIO_2

PCIE_VDDL

VMAIN_PRSNT

VAUX_PRSNT

SMB_CLK

ENERGY_DET

SPD1000LED*

Keep net short,
with no stubs.

C3936

0.1UF

10%
16V

X7R-CERM

VDDC

NC

DC0

DC4
DC3
DC2
DC1

NC

VDDC

DC5

BCM57765_CR_LED

31

BCM57765_SR_VFB

31 64 24 31

BCM57765_CR_DATA<5>

31 76

BCM57765_CE_L_MS_INS_L

31

BCM57765_VMAIN_PRSNT

31

BCM57765_CR_DATA<6>

31 76

BCM57765_SR_LX

31 64

BCM57765_VDDO_PIN20

31

BCM57765_CR_DATA<7>

31 76

BCM57765_XTALVDDH

31

BCM57765_SR_VDD

31 64

BCM57765_SMB_CLK

31

BCM57765_CR_CMD

31 76

402

41
44
43
46
47
50
49

5

NC

8
9

1

26

31 76

21

25
24
23
22
52

76
76

53

31
76

54

31
76

55

31

59
60
57
68

PLACE_NEAR=U3900.26:1 mm

1

1

C3935

10UF

10%

6.3V

2

2

X5R
805

ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>

PP3V3R1V8_SW_SD_VIO

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

BCM57765_MEDIA_SENSE

BCM57765_SD_DETECT
BCM57765_CR_CMD

BCM57765_CR_DATA<4>
BCM57765_CR_DATA<5>
BCM57765_CR_DATA<6>
BCM57765_CR_DATA<7>

BCM57765_CE_L_MS_INS_L
BCM57765_CR_LED

TP_BCM57765_XD_DET

BCM5764M Support

All parts below BOMOPTIONed BCM5764M

R3980
R3981
R3982
R3983

R3984
R3985
R3986

R3987
R3988

R3989
R3998
R3999

PLACE_NEAR=U3900.26:2 mm

BCM5764M

C3999

0.1UF

X7R-CERM

10%
16V

402

1

2

32 76

BI

32 76

BI

32 76

BI

32 76

BI

32 76

BI

32 76

BI

32 76

BI

32 76

BI

R3972
R3973

R3974

PLACE_NEAR=L3999.1:1 mm

R3975
R3976
R3977
R3978

31

31

BCM5764M

BCM5764M

BCM5764M

BCM5764M

BCM5764M

BCM5764M

BCM5764M

BCM5764M

BCM5764M

BCM5764M

BCM5764M

BCM5764M

BCM5764M

0

1 2

0

1 2

1K

1 2

4.7K

1 2

4.7K

1 2

1K

1 2

0

1 2

0

1 2

0

1 2

0

1 2

0

1 2

0

1 2

L3999

FERR-600-OHM-0.5A

BCM5764M

1

C3998

4.7UF

10%

6.3V

2

X5R-CERM
603

PLACE_NEAR=L3999.1:1 mm

SM

BCM57765

0

1 2

BCM57765

BCM57765

0

1 2

0

1 2

0

1 2

0

1 2

0

1 2

0

1 2

BCM57765

BCM57765

BCM57765

BCM57765

5%

5%

5%

5%
5%
5%
5%

5%

5%
5%
5%
5%

21

CRITICAL

CR_BUS_PWR is not for SD Card power,
just decoupling for BCM57765 CR I/Os.

BCM57765

C3970

4.7UF

10%

6.3V

X5R-CERM

603

5%

5%

5%

5%
5% 402
5%
5%

MF-LF1/16W

1/16W MF-LF

MF-LF1/16W

MF-LF1/16W

1/16W

MF-LF
MF-LF

1/16W

MF-LF

1/16W

212

BCM57765

1

C3971

0.1UF

10%
16V
X7R-CERM
402

ENET_ENERGY_DET

402

SDCONN_CD

402

SDCONN_CMD

402

SDCONN_CLK
SDCONN_DATA<0>

SDCONN_DATA<1>
SDCONN_DATA<2>
SDCONN_DATA<3>
SDCONN_DATA<4>

402

SDCONN_DATA<5>
SDCONN_DATA<6>

402

SDCONN_DATA<7>

402

BCM57765

1

C3972

0.1UF

10%
16V

2

X7R-CERM
402

All resistors above BOMOPTIONed BCM57765

BCM57765 supports both active-levels for WP.

ENET_ENERGY_DET

402

MF-LF1/16W

MF-LF1/16W

1/16W MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF
MF-LF1/16W

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

=ENET_WAKE_L

402

=PP3V3_S0_ENETPHY

402

=PP3V3_ENET_PHY

402
402
402
402

PP3V3_ENET_PHY_XTALVDDH

402

=PP1V2_ENET_PHY

402
402
402
402

SDCONN_WP

(See note)

SYNC_MASTER=T27_MLB

PAGE TITLE

Ethernet PHY (Caesar II/IV)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

OUT

IN

IN

OUT

BI
BI
BI
BI
BI
BI
BI
BI

IN

17 31

7

7

31

7

17 31

30

30 76

30 76

30 76

30 76

30 76

30 76

30 76

30 76

30 76

30 76

30

31

24 31 64

31

SYNC_DATE=08/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

39 OF 109

SHEET

31 OF 80

SIZE

C

B

A

D

36

Page Notes

Power aliases required by this page:
(NONE)

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
(NONE)

345678

2 1

D

ENETCONN_CTAP

PLACE_NEAR=T4000.3:2.54 mm

1

C4000

0.1UF

10%
16V

2

X5R
402

PLACE_NEAR=T4000.4:2.54 mm

1

2

C4002

0.1UF

10%
16V
X5R
402

PLACE_NEAR=T4001.3:2.54 mm

1

C4004

0.1UF

10%
16V

2

X5R
402

PLACE_NEAR=T4001.4:2.54 mm

1

C4006

0.1UF

10%
16V

2

X5R
402

D

CRITICAL

T4000

ENET_MDI_P<0>

31 76

BI

ENET_MDI_N<0>

31 76

BI

C

ENET_MDI_N<1>

31 76

BI

ENET_MDI_P<1>

31 76

BI

ENET_MDI_N<2>

31 76

BI

ENET_MDI_P<2>

31 76

BI

ENET_MDI_N<3>

31 76

BI

ENET_MDI_P<3>

31 76

BI

10

2945 76 1102945 76

1

IONCNC

IONCIO

IO

NC

IONCNC

IONCIO

IO

NC

B

D4000

RCLAMP0524P

SLP2510P8

ENET_ESD
CRITICAL

GND

3

D4001

RCLAMP0524P

SLP2510P8

ENET_ESD
CRITICAL

GND

3

1

2

3

4

5

6

1

2

3

4

5

6

Transformers should be
mirrored on opposite
sides of the board

D4000.1:
D4000.5:

D4001.1:
D4001.5:

SM

TX

TLA-6T213HF

RX

12

11

10

9

8

7

CRITICAL

T4001

SM

TX

TLA-6T213HF

RX

PLACE_NEAR=T4000.6:4 mm
PLACE_NEAR=T4000.1:4 mm

PLACE_NEAR=T4001.6:4 mm
PLACE_NEAR=T4001.1:4 mm

12

11

10

9

8

7

ENETCONN_P<0>

79

ENETCONN_N<0>

79

ENET_CTAP0

ENET_CTAP1

79

ENETCONN_N<1>

79

ENETCONN_P<1>

79

ENETCONN_N<2>

ENETCONN_P<2>

79

ENET_CTAP2

ENET_CTAP3

79

ENETCONN_N<3>

79

ENETCONN_P<3>

R4000

1/16W
MF-LF

CRITICAL

J4000

RJ45-M97-3

F-RT-TH

9

10

1
2

3

4
5

6
7

8

11

12

C

514-0636

1

75

5%

402

2

R4001

1/16W
MF-LF

75

402

5%

121

R4002

75

5%
1/16W
MF-LF
402

2

1

R4003

75

5%
1/16W
MF-LF
402

2

ENET_BOB_SMITH_CAP

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

CRITICAL

C4008

1000PF

1 2

10%

2KV
CERM
1206

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

Ethernet Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

40 OF 109

SHEET

32 OF 80

SIZE

A

D

345678

2 1

21

2121

=PP3V3_FW_FWPHY

PLACEMENT_NOTE=Place C4170 close to U1400
PLACEMENT_NOTE=Place C4171 close to U1400

C4170

C4171

C4175

C4176

1 2

0.1UF

1 2

0.1UF

1 2

0.1UF

1 2

0.1UF

PLACEMENT_NOTE=Place C4175 close to U4100
PLACEMENT_NOTE=Place C4176 close to U4100

FW643_LDO

1

R4164

10K

5%
1/16W
MF-LF
402

2

7 mA I/O

1

C4120

1UF

10%

6.3V
2

CERM

402

D

L4110

=PP1V0_FW_FWPHY

7

34

135 mA

120-OHM-0.3A-EMI

0402-LF

110 mA Digital Core

1

C4100

2

1UF

10%

6.3V
CERM
402

1

2

C4101

1UF

10%

6.3V
CERM
402

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V

1

C4102

1UF

10%

6.3V

2

CERM
402

1

C4103

1UF

10%

6.3V

2

CERM
402

1

C4104

1UF

10%

6.3V

2

CERM
402

25 mA PCIe SerDes

1

C4110

1UF

10%

6.3V

2

CERM
402

1

C4105

1UF

10%

6.3V

2

CERM
402

1

C4111

2

1

C4106

2

1UF

10%

6.3V
CERM
402

1UF

10%

6.3V
CERM
402

C4121

C4130

1

1UF

10%

6.3V
2

CERM

402

114 mA FireWire PHY

1

1UF

10%

6.3V
2

CERM

402

17 mA PCIe SerDes

C4122

1UF

6.3V
CERM

C4131

1UF

6.3V
CERM

C4135

1UF

6.3V
CERM

10%

402

10%

402

10%

402

1

C4123

2

1

C4132

2

1

C4136

2

0 mA VReg PWR

C4141

0.1UF

20%
10V

CERM

402

6.3V
CERM

6.3V
CERM

6.3V
CERM

1

2

1UF

1UF

1UF

10%

402

10%

402

10%

402

1

2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

2

1

2

1

C4124

1UF

10%

6.3V
2

CERM

402

PP3V3_FW_FWPHY_VDDA

PP3V3_FW_FWPHY_VP25PP1V0_FW_FWPHY_AVDD

C4140

1UF

10%

6.3V
CERM
402

L4130

120-OHM-0.3A-EMI

0402-LF

L4135

120-OHM-0.3A-EMI

0402-LF

C

A1

B1

B13

ATBUSB

NC

A13

ATBUSH

NC

A11

ATBUSN

NC

=FW_PHY_DS0

35

IN

=FW_PHY_DS1

35

IN

=FW_PHY_DS2

35

IN

FW_P0_TPA_N

35 77

BI

FW_P0_TPA_P

35 77

BI

FW_P1_TPA_N

35 77

BI

FW_P1_TPA_P

35 77

BI

FW_P2_TPA_N

35

BI

FW_P2_TPA_P

35

BI

FW_P0_TPB_N

35 77

BI

FW_P0_TPB_P

35 77

BI

FW_P1_TPB_N

35 77

BI

FW_P1_TPB_P

35 77

BI

FW_P2_TPB_N

35

=PPVP_FW_PHY_CPS

35

1

R4160

B

C4150

22PF

1 2

5%

50V

CERM

402

C4151

22PF

1 2

5%

50V

CERM

402

2 4

NC
NC

FW_CLK24P576M_XO

CRITICAL

Y4150

24.576MHZ

SM-3.2X2.5MM

31

R4150

412

1 2

1%
1/16W
MF-LF

402

200K

1%
1/16W
MF-LF

402

R4161

2.94K

R4162

2

1/16W
MF-LF

470K

1/16W
MF-LF

1

1

R4170

191

1%

1%

1/16W
MF-LF
402

402

2

2

1

1

C4162

0.33UF

5%

10%

6.3V

2

402

CERM-X5R
402

2

BI

35

BI

35

BI

34 35

BI

35

BI

FW_P2_TPB_P

FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS

FW643_R0
FW643_TPCPS

TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI

TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L

TP_FW643_OCR10_CTL

F12

DS0

(IPD) NT-2

E12

DS1

(IPD) NT-3

E13

(IPD) NT-4

DS2

B8

TPA0N

A8

TPA0P

B5

TPA1N

A5

TPA1P

B3

TPA2N

A3

TPA2P

B9

TPB0N

A9

TPB0P

B6

TPB1N

A6

TPB1P

B4

TPB2N

A4

TPB2P

B7

TPBIAS0

C3

TPBIAS1

A2

TPBIAS2

B11

R0

B10

TPCPS

K1

NAND_TREE

L8

REXT

F13

XO

G13

XI

NT-9

M13

(IPD)

SE

N13

(IPD)

SM

J2

MODE_A
CE

(IPD)

(IPU)

FW620*
JASI_EN
AVREG
VBUF
FW_RESET*

OCR_CTL_V10
OCR_CTL_V12

B2

D4

(IPD) NT-1

(IPD) NT-11

L13
D12

D1

A10
H13

K13

J12
J13

NC

H2

E2

B12

E10

C13

VDD10

NT-OUT

NOTE: NT-xx notes show
NAND tree order.

(IPU) NT-8

(Reserved)

E5

E4

D9

D10

K2

H12

E9F4F6

L1

M12

F7

N3

C1

N11

1394 PHY

MISCELLANEOUS

G6

F8

G4

F10

F1

C12J1G12

VDD33

G8

G7

L3

OMIT

CRITICAL

U4100

FW643E

BGA

VSS

H4

G10

H6D7H7

M2

L11

D8

D5D6L5

A12

VDDH

PCI EXPRESS PHY

TEST CONTROLLER

FIXME!!! - TYPO IN SYMBOL REGCTL

POWER MANAGEMENT

NT-12 (IPD)

SCIF

SERIAL EEPROM
CONTROLLER

CHIP RESET

J9

J5

H8

J4

H10

J10

L10

VP

NT-13

K4K5K7

L6

VP25

L9

K12

VREG_PWR

NT-21 (IPU)
NT-20 (IPU)

NT-18 (IPU)

NT-19 (IPU)

NT-10 (IPD)

NT-16 (IPD)
NT-14 (IPD)

NT-17

NT-15 (IPD)

K6

L7K9K8

K10

PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P

REFCLKN
REFCLKP

(IPU)

TRST*

(OD)

WAKE*

REGCLT

VAUX_DETECT

VAUX_DISABLE

CLKREQN

(OD)

SCIFCLK
SCIFDAIN
SCIFDOUT

SCIFMC

NT-7
NT-6

PERST*

NT-5

VREG_VSS

L12

TCK
TDI
TDO
TMS

SCL
SDA

N8

74

N7

N5
N6

N9

N10

M4
N2

M1

M3

N1

C2
D13

E1

D2
L2

G2

G1
H1

F2

N12

M11

N4

PCIE_FW_R2D_N
PCIE_FW_R2D_P

74

74

PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P

74

PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P

TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS

FW643_TRST_L

=FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
=FW_CLKREQ_L

TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC

FW643_SCL
TP_FW643_SDA

FW_RESET_L

1

R4163

10K

5%
1/16W
MF-LF
402

2

15 74

IN

15 74

IN

34

OUT

34

OUT

34

IN

7

33 34 35

138 mA

PCIE_FW_R2D_C_N

10% 402X5R16V

PCIE_FW_R2D_C_P

10%

PCIE_FW_D2R_N

10%

PCIE_FW_D2R_P

10% 402X5R16V

402X5R16V

402X5R16V

=PP3V3_FW_FWPHY

121

R4165

1/16W
MF-LF

R4166

10K

10K

5%

5%
1/16W
MF-LF

402

402

2

NOTE: FW_PME_L and FW_CLKREQ_L are
isolated for systems that use
1394B physical plug detect.

WITH PLUG DETECT:

- Gate CLKREQ# based on PHY power

- TP (or NC) PME#

WITHOUT PLUG DETECT:

- Alias both signals to drop = prefix

D

C

15 74

IN

15 74

IN

15 74

OUT

15 74

OUT

7

33 34 35

B

A

SYNC_MASTER=T27_MLB

PAGE TITLE

FireWire LLC/PHY (FW643E)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

41 OF 109

SHEET

33 OF 80

SIZE

A

D

345678

2 1

Page Notes

Power aliases required by this page:

- =PPBUS_S5_FWPWRSW (FW VP FET Input)

- =PPBUS_FW_FET (FW VP FET Output)

- =PP3V3_FW_P3V3FWFET (3.3V FET Input)

- =PP3V3_FW_FET (3.3V FET Output)

- =PP3V3_FW_FWPHY (PHY 3.3V Power)

- =PP3V3_S0_FWLATEVG

- =PP3V3_S0_FWPWRCTL

- =PP1V05_S0_FWPWRCTL (5KPD Bias Rail)

- =PP1V05_FW_P1V0FWFET (1.0V FET Input)

- =PP1V0_FW_FET_R (1.0V FET Output)

D

- =PP1V0_FW_FWPHY (PHY 1.0V)
Signal aliases required by this page:

- =FW_CLKREQ_L

- =FW_PME_L
BOM options provided by this page:

(NONE)

C

=PPBUS_S5_FWPWRSW

7

Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)

1

R4262

10K

5%
1/16W
MF-LF

402

2

FWPORT_FASTOFF_L_DIV

1

R4263

10

5%

1/16W
MF-LF

402

2

FWPORT_FASTOFF_L

=PP3V3_S0_FWLATEVG

7

35

35

IN

FWPORT_PWR_EN

FireWire Port Power Switch

CRITICAL

Q4260

FDC638P_G

SM

6

PPBUS_FW_FWPWRSW_F

MIN_LINE_WIDTH=0.5 mm

5

4

1

R4260

300K

5%

4

(SYM-VER2)

SOT-363

S

5

G

6

D

2

G

S

1

BSS8402DW

Q4262

D

3

Q4262

BSS8402DW

SOT-363

(SYM-VER1)

Q4261

SSM3K15FV

SOD-VESM-HF

1

1/16W
MF-LF
402

2

FWPORT_PWREN_L_DIV

1

R4261

470K

5%
1/16W
MF-LF
402

2

FWPORT_PWREN_L

3

D

G S

2

NO STUFF

C4261

0.1UF

C4260

0.1UF

1

10%
25V

2

X5R
402

10%
25V
X5R
402

1

2

3

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

2
1

24

IN

15 34

IN

15

OUT

=FW_RESET_L

FW_PWR_EN
FW_CLKREQ_L

Pull-up provided by another page.

CRITICAL

F4260

1.1A-24V

MINISMDC110H24

21 1 2

PPBUS_FW_FWPWRSW_D

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

CRITICAL

D4260

SM

CRS08-1.5A-30V

=PPBUS_FW_FET

Supervisor & CLKREQ# Isolation

=PP3V3_S0_FWPWRCTL

7

C4290

2

R4283

10K

5%
1/16W
MF-LF
402

1

FW_RESET_R_L

0.1UF

10%
25V
X5R
402

1

2

U4290

SLG4AP016V

TDFN

DLY

3

MR*

6

EN

8

OUT

(OD)

GND

5

VDD

1

+

-

THRM

CRITICAL

SENSE

0.7V

RESET*

PAD

9

1

R4290

100K

5%
1/16W
MF-LF
402

2

2

4

FW_RESET_L

DLY = 60 ms +/- 20%

7

IN

=PP1V0_FW_FWPHY

=FW_CLKREQ_L
FW_CLKREQ_PHY_L

MAKE_BASE=TRUE

7

D

7

33

33

OUT

33

IN

C

=PP1V05_S0_FWPWRCTL

7

1

R4275

1K

5%
1/16W
MF-LF

402

G

15 34

IN

FW_PWR_EN

2

B

All FireWire devices require 5K pull-down on TPB pair.
Host can detect as load on TPBIAS signal.
Current source only active when FW_PWR_EN is low.

2

FW_PWR_EN_L

6

CRITICAL

D

Q4275

DMB53D0UV

SOT-563

S

BC847CDXV6TXG

1

A

TEXT NOTE FOR 3.3V RAIL CURRENT CHANGED TO EDP NUMBER.

8 7 5 4 2 1

FireWire Port 5K Pull-Down Detect

CRITICAL

Q4270

SOT563

1

R4270

330K

5%
1/16W
MF-LF
402

2

3

5

4

FW_P1_TPBIAS_R

PLACE_NEAR=C4360.1:2 mm

FW_P1_TPBIAS

33 35

IN

FWDET_MIRROR

1

R4272

1K

5%
1/16W
MF-LF

402

2

R4271

56K

1/16W
MF-LF

402

2

1

5%

2

FW_5KPD_DET_RC

CRITICAL

6

Q4270

BC847CDXV6TXG
SOT563

1

FWDET_EMIT

R4273

12K

1/16W
MF-LF

402

C4270

0.1UF

1

5%

2

FireWire PHY WAKE# Support

When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.

=PP3V3_FW_FWPHY

7

33 35

1

R4277

10K

5%
1/16W
MF-LF

402

2

33

IN

=FW_PME_L

FW643_WAKE_L

MAKE_BASE=TRUE

2

3.3V FW Switch

U4201

=PP3V3_FW_P3V3FWFET

FW_5KPD_DET_L

MAKE_BASE=TRUE

3

CRITICAL

Q4275

5

DMB53D0UV

1

10%
16V

2

X5R
402

4

SOT-563

7

1UF

6.3V
CERM

1

10%

2

402

C4201

TPS22924

A2

VIN

B2

CRITICAL

C2

ON

CSP

VOUT

GND

C1

1.0V FW Switch

U4202

=PP1V05_FW_P1V0FWFET

7

C4202

1UF

6.3V
CERM

1

10%

2

402

TPS22924

A2

VIN

B2

CRITICAL

C2

ON

CSP

VOUT

GND

C1

=PP3V3_FW_FET

EDP = 0.14A (85C)

A1
B1

PP1V05_FW_FET

MIN_LINE_WIDTH=0.4 mm

A1

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

B1

1

R4202

0.549

1%
1/16W
MF
402

2

=PP1V0_FW_FET_R

7

U4201 & U4202

Part
Type
R(on)

Max Output: 2A

LSI FireWire PHY requires 1.0V.
To avoid an extra power supply,

1.05V is used with a series R
to reduce voltage.

7

TPS22924C
Load Switch
18 mOhm Typ

50 mOhm Max

B

Dual-purpose output:

1) 5K Pull-down Detect when FW_PWR_EN is low.

1

R4276

100K

5%
1/16W
MF-LF
402

2

FW_WAKE

NO STUFF

6

C4276

D

G

S
1

CRITICAL

Q4276

DMB53D0UV

SOT-563

0.1UF

1

10%
16V

2

X5R
402

2) FW643 WAKE# (PME#) when PHY is powered.
FW_PME_L

Pull-up provided on another page.

3

CRITICAL

Q4276

5

DMB53D0UV

SOT-563

4

15

OUT

SYNC_MASTER=T27_MLB

PAGE TITLE

FireWire Port & PHY Power

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/15/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

42 OF 109

SHEET

34 OF 80

SIZE

A

D

36

345678

2 1

Page Notes

Power aliases required by this page:

- =PPVP_FW_PORT1

- =PPVP_FW_PHY_CPS_FET (From Port)

- =PPVP_FW_PHY_CPS (To PHY)

- =PP3V3_FW_FWPHY

- =PP3V3_S0_FWLATEVG

Signal aliases required by this page:

- =FW_PHY_DS0

- =FW_PHY_DS1

- =FW_PHY_DS2

D

NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.

BOM options provided by this page:
(NONE)

1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)

C

FW643 TPCPS Leakage Protection

FW643 has internal leakage path from TPCPS pin to VDD33.
FET blocks current to TPCPS until VDD33 is powered.

SOT-363

BSS8402DW

Q4300

=PPVP_FW_PHY_CPS_FET

7

From Port

=PP3V3_FW_FWPHY

7

33 34 35

R4311

470K

1/16W
MF-LF

5%

402

(SYM-VER2)

SGD

4

1

5

2

CPS_EN_L_DIV

CPS_EN_L

6

D

G

2

S

1

3

Q4300

BSS8402DW

SOT-363

(SYM-VER1)

R4312

330K

1/16W
MF-LF

5%

402

PPVP_FW_CPS

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVP_FW_PHY_CPS

1

2

To FW643

Unused FireWire Ports

Disabled per LSI instructions
(All unused port signals TP/NC)

FW_P0_TPBIAS

33

IN

FW_P0_TPA_P

33 77

BI

FW_P0_TPA_N

33 77

BI

FW_P0_TPB_P

33 77

BI

FW_P0_TPB_N

33 77

33

33

33

33

33

BI

IN

BI

BI

BI

BI

FW_P2_TPBIAS

FW_P2_TPA_P

FW_P2_TPA_N

FW_P2_TPB_P

FW_P2_TPB_N

33

NC_FW0_TPBIAS

MAKE_BASE=TRUE

NC_FW0_TPAP

MAKE_BASE=TRUE

NC_FW0_TPAN

MAKE_BASE=TRUE

NC_FW0_TPBP

MAKE_BASE=TRUE

NC_FW0_TPBN

MAKE_BASE=TRUE

NC_FW2_TPBIAS

MAKE_BASE=TRUE

NC_FW2_TPAP

MAKE_BASE=TRUE

NC_FW2_TPAN

MAKE_BASE=TRUE

NC_FW2_TPBP

MAKE_BASE=TRUE

NC_FW2_TPBN

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

Configures PHY for:

- Port "1" Bilingual (1394B)
=PP3V3_FW_FWPHY

7

33 34 35

FireWire PHY Config Straps

121

R4382

1/16W
MF-LF

10K

R4380

10K

1%

1%
1/16W
MF-LF

402

402

2

FWPHY_DS0

MAKE_BASE=TRUE

FWPHY_DS1

MAKE_BASE=TRUE

FWPHY_DS2

MAKE_BASE=TRUE

1

R4381

10K

1%
1/16W
MF-LF
402

2

=FW_PHY_DS0

=FW_PHY_DS1

=FW_PHY_DS2

33

OUT

33

OUT

33

OUT

D

C

FERR-250-OHM

1

C4314

0.01UF

10%
50V

2

X7R
402

CRITICAL

L4310

SM

C4319

0.1uF

1

R4319

1M

5%
1/16W
MF-LF
402

2

Note: Trace PPVP_FW_PORT1 must handle up to 5A

21

PPVP_FW_PORT1_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

(FW_PORT1_TPB_N)
(FW_PORT1_BREF)
(FW_PORT1_TPB_P)

(GND)
(FW_PORT1_TPA_N)

FW_PORT1_AREF

(FW_PORT1_TPA_P)

PLACE_NOTE=J4310.5:2 mm

1

10%
50V

2

X7R

603-1

AREF needs to be isolated from all
local grounds per 1394b spec

When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)

BREF should be hard-connected to logic
ground for speed signaling and connection

NC

PORT 1

BILINGUAL

CRITICAL

J4310

1394B-M97

F-RT-TH

TPB-

1

9

2
8

7

6

TPA-

3

5

TPA+

4

10
11

12

13

514S0605

CHASSIS

GND

TPB(R)

VPTPB+

SC/NC

VG

TPA(R)

TPB-

TPB<R>

TPB+

VP

NC

VG

TPA-

TPA<R>

TPA+

OUTPUT

B

INPUT

D1+
D1-

D2+
D2-

Cable Power

=PPVP_FW_PORT1

7

8

7

6

5

Termination

Place close to FireWire PHY

FW_P1_TPBIAS

33 34

IN

1

C4360

0.33UF

10%

6.3V

2

CERM-X5R
402

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

1

R4360

56.2

1%
1/16W
MF-LF
402

FW_P1_TPA_P

33 77

BI

FW_P1_TPA_N

33 77

BI

B

33 77

33 77

BI

BI

FW_P1_TPB_P

FW_P1_TPB_N

2

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

1

R4362

56.2

1%
1/16W
MF-LF
402

2

FW_PORT1_TPB_C

1

C4364

220pF

5%
25V

2

CERM
402

R4361

56.2

1/16W
MF-LF

R4363

56.2

1/16W
MF-LF

R4364

4.99K

1/16W
MF-LF

1

1%

402

2

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

1

1%

402

2

1

1%

402

2

"Snapback" & "Late VG" Protection

=PP3V3_S0_FWLATEVG

7

34

TP_FWLATEVG_VCLMP

FWPORT_PWR_EN

34

OUT

(FW_PORT1_TPA_P)
(FW_PORT1_TPA_N)

PLACE_NEAR=U4350.1:2 mm

C4350

0.1UF

R4350

100K

5%
1/16W
MF-LF

402

(FW_PORT1_TPB_P)
(FW_PORT1_TPB_N)

1

10%
16V

2

X5R
402

3

VCLMP

4

FWPWR_EN

1

2

1

VCC

U4350

TPD4S1394

LLP

CRITICAL

GND

2

(PINS 5/6 AND 7/8 ARE

SWAPPED FOR BETTER ROUTING)

A

CANNOT SYNC THIS PAGE FROM T27, TPA AND TPB FOR U4350 IS SWAPPED

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

FireWire Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

43 OF 109

SHEET

35 OF 80

SIZE

A

D

345678

2 1

ODD Power Control

=PP5V_S0_ODD

7

1

R4596

100K

5%
1/16W
MF-LF

402

2

NOTE: 3.3V must be S0 if 5V is S3 or S5 to

D

ensure the drive is unpowered in S3/S5.

=PP3V3_S0_ODD

36

7

R4597

Q4596

18

IN

SSM6N15FEAPE

ODD_PWR_EN_L

SOT563

100K

5

1/16W
MF-LF

402

1

5%

2

D

SG

SSM6N15FEAPE

ODD_PWR_EN

3

4

Q4596

SOT563

2

ODD_PWR_EN_LS5V_L

6

D

SG

1

C

PLACE_NEAR=J4501.9:3mm

CRITICAL

L4500

FERR-70-OHM-4A

2

C4501

0.1UF

20%
10V

1

CERM
402

SATA_HDD_D2R_C_N

6

74

SATA_HDD_D2R_C_P

6

74

SATA_HDD_R2D_N
SATA_HDD_R2D_P

0603

CRITICAL

FL4501

90-OHM-100MA

B

SYS_LED_ANODE

40

=PP5V_S3_IR

7

38

R4531

4.7

5%
1/16W
MF-LF

402

R4532

10

5%
1/16W
MF-LF

402

12

SYS_LED_ANODE_R

1

C4531

0.001UF

10%
50V

2

CERM

402

6

38

PP5V_S3_IR_R

6

12

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=5V

1

C4532

0.1UF

10%
16V

2

X7R-CERM
402

PLACE_NEAR=L4500.1:2mm

IR_RX_OUT

PP5V_S0_HDD_FLT

6

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V

CRITICAL

J4501

54722-0224

F-ST-SM

1
3
5
7

9
11
13
15

NC

17
19
21

516S0687

2
4
6
8
10
12

6

74

14

6

74

16
18
20
22

SATA HDD Port

A

J5401 PINOUTS ARE DIFFERENT FOR K6, DO NOT SYNC THIS PAGE FROM T27 DIRECTLY

8 7 5 4 2 1

=PP5V_S0_HDD

21

PLACE_NEAR=L4500.2:2mm

2

C4502

0.1UF

20%
10V

1

CERM
402

DLP11S

SYM_VER-1

43

12

C4595

0.068UF

R4595

1 2

79

79

1

10%
10V

2

CERM

402

100K

5%
1/16W
MF-LF

402

ODD_PWR_SS

7

SATA_HDD_R2D_UF_N

SATA_HDD_R2D_UF_P

U4510 ADD NO STUFF IN PRODUCTION!!!!

CRITICAL

Q4590

TPCP8102

31 2

23V1K-SM

S

G

4

D

C4596

0.01UF

1 2

10%
16V

CERM

402

=PP5V_SW_ODD_FET
J4500 connection separated to

7 85 6

support debug sense resistor.
Alias together if no sense R.

36

6

39

OUT

8

=PP5V_SW_ODD

8

=PP3V3_S0_ODD

7

SMC_ODD_DETECT

R4590

33K

1/16W
MF-LF

402

1

5%

2

SATA ODD Port

CRITICAL

J4500

54722-0164

F-ST-SM
2
4
6
8

10
12
14
16

516S0616

Indicates disc presence

PART NUMBER

QTY

338S0769 1 U4510 CRITICAL

BOMOPTIONs:

- RDRV:8511 stuffs PS8511A & associated parts (STRAPS TBD!!!)

- RDRV:8515 stuffs PS8515A & associated parts

- RDRV:NO stuffs bypass path (neither IC or associated parts stuffed)

DESCRIPTION

SATA 3GB/S REDRIVER, LOW POWER

REFERENCE DES

SATA Redriver

=PP1V5_S0_SATARDRVR

RDRV:IN_DEVEL

CRITICAL

6

16

VDD

U4510

TQFN

A_OUTP
A_OUTN

(IPD)

THRM

GND

PAD

13321

RDRV:8511&RDRV:8515

RDRV:8511&RDRV:8515

RDRV:8511&RDRV:8515

RDRV:8511&RDRV:8515

(All 4 C’s)

C4516

C4515

C4511

C4510

C4580
C4581

C4585

C4586

0.01UF

0.01UF

0.01UF

0.01UF

(All 4 C’s)

RDRV:NO

RDRV:NO

RDRV:NO

RDRV:NO

0.01UF

0.01UF

0.01UF

0.01UF

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

10%

CERM

10%

CERM

CERM

10%

CERM

10%

CERM

10%

CERM

10%

CERM

10%

CERM

16V
402

16V
402

16V10%
402

16V
402

16V
402

16V
402

16V
402

16V
402

PLACE_NEAR=U4510.16:3mm

PLACE_NEAR=U4510.16:3mm

RDRV:8511&RDRV:8515

RDRV:8511&RDRV:8515

RDRV:8511&RDRV:8515

(C4514,

C4519 & R4510)

2

R4510

10K

5%
1/16W
MF-LF
402

1

SATA_HDD_D2R_RDRV_IN_P

79

SATA_HDD_D2R_RDRV_IN_N

79

SATA_HDD_R2D_RDRV_OUT_N

79

SATA_HDD_R2D_RDRV_OUT_P

79

16

IN

C4514

SATARDRVR_A_EN

SATARDRVR_A_AUTOPWR_EN

SATARDRVR_A_I2C_EN

36

SATARDRVR_A_I2C_ADDR

36

SATARDRVR_A_I2C_SCL

36

SATARDRVR_A_I2C_SDA

36

1UF

6.3V

CERM-X5R

10%

402

1

1

C4519

0.01UF

10%
16V

2

2

CERM
402

1
2 14

4
5

7

17

10

8

19
18

NOTE: Internal pulls are ~150K

Redriver Bypass Path

SATA_HDD_R2D_NORDRV_P

79

SATA_HDD_R2D_NORDRV_N

79

SATA_HDD_D2R_NORDRV_N

79

SATA_HDD_D2R_NORDRV_P

79

PS8515A-A2

A_INP
A_INN

B_OUTN
B_OUTP

EN

(IPU)

AUTOPW_EN
(IPD)

I2C_EN
I2C_ADDR

(IPD)
SCL_CTL
SDA_CTL

1
3
5
7
9
11
13
15

CRITICAL

6

74

SATA_ODD_R2D_P
SATA_ODD_R2D_N

6

74

SATA_ODD_D2R_UF_N

6

79

SATA_ODD_D2R_UF_P

6

79

BOM OPTION

RDRV:8511

=I2C_HDD_A_SCL

42

IN

=I2C_HDD_A_SDA

42

IN

7

36

SATA_HDD_D2R_RDRV_OUT_P

79 79

15

SATA_HDD_D2R_RDRV_OUT_N

79

12

B_INN

11

SATA_HDD_R2D_RDRV_IN_N

B_INP

A_SD
B_SD

338S0778 (PS8515A)

Addr: 0x94(Wr)/0x95(Rd)

79

SATA_HDD_R2D_RDRV_IN_P

79

20

SATARDRVR_A_A_SD

9

SATARDRVR_A_B_SD

PS8515A:
x_SD pins are outputs (Signal Detect)

CRITICAL

FL4520

90-OHM-100MA

DLP11S

SYM_VER-1

43

79

12

PLACE_NEAR=J4500.5:4mm

CRITICAL

FL4525

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

1 2

PLACE_NEAR=J4500.9:4MM

79

SATA_ODD_D2R_C_P

74

SATA_ODD_D2R_C_N

74

SATA_ODD_R2D_UF_N

SATA_ODD_R2D_UF_P

C4520
C4521

C4525
C4526

PS8511A / PS8515A Straps

=PP1V5_S0_SATARDRVR

7

36

RDRV:8515

2

2

R4515

10K

5%

5%

1/16W
MF-LF
402

402

1

1

NO STUFF

2

2

R4516

10K

5%

5%

1/16W
MF-LF
402

402

1

1

SATA Connectors

R

36

36

36

NO STUFF

R4519

1/16W
MF-LF

RDRV:8515

R4513

0

12

5%

RDRV:8515

1/16W
MF-LF

R4514

402

1/16W
MF-LF

(All 4 C’s)

RDRV:8511&RDRV:8515

RDRV:8511&RDRV:8515

RDRV:8511&RDRV:8515

RDRV:8511&RDRV:8515

C4518

0.01UF

C4517

0.01UF

C4513

0.01UF

C4512

0.01UF

(ALL 4 R’S & C’S)

RDRV:NO

RDRV:NO

RDRV:NO

RDRV:NO

R4580

1 2

0

R4581

1 2

0

R4585

1 2

34

R4586

1 2

34

C4587

47PF

C4588

47PF

10K

5%

402

PS8511A:

PIN NAME
9 A_PRE (IPD)
8 B_PRE (IPD)
20 A_BST# (IPU)
10 B_BST# (IPU)

NO STUFF

121

R4520

5%

402

2

19 A_EQ (IPD)

0

18 B_EQ (IPD)

12

1 2

10%

CERM

10%

CERM

1 2

10%

CERM

1 2

10%

CERM

5%

MF-LF

5%

MF-LF

1%

MF-LF

1%

MF-LF

1 2

50V

5%

402

CERM

1 2

50V

5%

CERM

402

10K

5%
1/16W
MF-LF
402

16V
402

16V
402

16V
402

16V
402

1/16W

1/16W

1/16W

1/16W

SATA_HDD_D2R_UF_P

SATA_HDD_D2R_UF_N

79

402

402

402

402

NO STUFF

R4511

10K

1/16W
MF-LF

RDRV:8515

R4512

10K

1/16W
MF-LF

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

SYNC_MASTER=T27_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1 2

0.01UF

1 2

0.01UF

1 2

0.01UF

1 2

0.01UF

CRITICAL

FL4502

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

1 21 2

Apple Inc.

SATA_ODD_R2D_C_N

402

CERM

16V10%

SATA_ODD_R2D_C_P

40216V

CERM

10%

SATA_ODD_D2R_P

10%

CERM

40216V

SATA_ODD_D2R_N

10% 402

CERM

16V

NO STUFF

2

R4517

10K

5%
1/16W
MF-LF
402

1

SATARDRVR_A_B_SD
SATARDRVR_A_I2C_ADDR
SATARDRVR_A_A_SD
SATARDRVR_A_I2C_EN

NO STUFF

2

R4518

10K

5%
1/16W
MF-LF
402

1

SATARDRVR_A_I2C_SCL

SATARDRVR_A_I2C_SDA

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SYNC_DATE=08/06/2009

DRAWING NUMBER

051-8563

REVISION

BRANCH

PAGE

SHEET

17 74

IN

17 74

IN

17 74

OUT

OUT

36

36

36

36

36

36

OUT

OUT

17 74

IN

17 74

IN

A.13.0

45 OF 109

36 OF 80

17 74

17 74

17 74

SIZE

D

C

B

A

D

345678

2 1

D

D

Port Power Switch

CRITICAL

1

C4691

0.1UF

20%
10V

2

CERM
402

Q4690

TPS2064DGN

2

IN

MSOP

8

OC1*

3

EN1

5

OC2*

4

EN2

TPAD

GND

91

OUT1

OUT2

7

6

C4695

10UF

6.3V

PP5V_S3_RTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

PP5V_S3_RTUSB_B_ILIM

CRITICAL

1

1

C4696

20%
X5R

603

100UF

20%

6.3V

22

POLY-TANT
CASE-B2-SM

C4617

10UF

6.3V

20%
X5R

603

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

CRITICAL

1 1

C4616

100UF

20%

6.3V

2

2

POLY-TANT
CASE-B2-SM

USB_EXTA_MUXED_N

75 79

USB_EXTA_MUXED_P

75 79

C4605

0.01uF

20%
16V

CERM

402

PLACE_NEAR=D4600.3:2 mm

=PP5V_S3_RTUSB

7

USB_EXTA_OC_L

17

OUT

=USB_PWR_EN

65

IN

USB_EXTB_OC_L

17

OUT

1

C4690

10UF

20%

6.3V

2

X5R
603

C

USB/SMC Debug Mux

=PP3V42_G3H_SMCUSBMUX

7

39 40 41

39 40 41

17 75

17 75

IN

OUT

BI
BI

SMC_DEBUG:YES

SMC_RX_L
SMC_TX_L

USB_EXTA_P
USB_EXTA_N

C4650

0.1UF

CERM

20%
10V

402

1

2

5

M+

4

M-

U4650

PI3USB102ZLE

7

D+

6

D-

8

CRITICAL

93

SMC_DEBUG:YES

VCC

TQFN

GND

1

Y+

2

Y-

10

SELOE*

SIGNAL_MODEL=USB_MUX

B

1

R4650

10K

5%
1/16W
MF-LF
402

2

(USB_EXTA_MUXED_N)
(USB_EXTA_MUXED_P)

USB_DEBUGPRT_EN_L
SEL=0 Choose SMC
SEL=1 Choose USB

SMC_DEBUG:NO

R4651

0

1 2

5%
1/16W
MF-LF

402

SMC_DEBUG:NO

R4652

0

1 2

5%
1/16W
MF-LF

402

C4615

0.01uF

20%
16V

CERM

39

IN

17 75

BI

17 75

BI

402

USB_EXTB_N

USB_EXTB_P

PLACE_NEAR=D4610.3:2 mm

CRITICAL

L4605

FERR-220-OHM-2.5A

1

2

1

2

0603

CRITICAL

L4600

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

1 2

CRITICAL

L4615

FERR-220-OHM-2.5A

0603

CRITICAL

L4610

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

1 2

21

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

PLACE_NEAR=J4600.1:3 mm

PLACE_NEAR=D4600.2:2 mm

USB_LT1_N

79

USB_LT1_P

79

RCLAMP0502N

21

PP5V_S3_RTUSB_B_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

PLACE_NEAR=J4610.1:3 mm

PLACE_NEAR=D4610.2:2 mm

USB_LT2_N

79

USB_LT2_P

79

RCLAMP0502N

Left USB Port A

CRITICAL

J4600

USB

F-RT-TH-M97-4

5
6

1
2
3
4

2534
IOIONC

D4600

SLP1210N6

CRITICAL

NC

VBUS

GND

6

1

D4600.4
D4600.5

7
8

514-0638

PLACE_NEAR=J4600.3:2 mm
PLACE_NEAR=J4600.2:2 mm

Left USB Port B

CRITICAL

J4610

USB

F-RT-TH-M97-4

5
6

1
2
3
4

7
2534
IOIONC

D4610

SLP1210N6

CRITICAL

NC

VBUS

GND

6

1

D4610.4
D4610.5

8

514-0638

PLACE_NEAR=J4610.3:2 mm

PLACE_NEAR=J4610.2:2 mm

C

B

A

SYNC_MASTER=T27_MLB

PAGE TITLE

External USB Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

46 OF 109

SHEET

37 OF 80

SIZE

A

D

345678

2 1

IR Support

=PP5V_S3_IR

7

36

D

USB_IR_P

17 75

BI

USB_IR_N

17 75

BI

IR_VREF_FILTER

1

C4803

1UF

10%
10V

2

X5R
402-1

C4801

0.1UF

X7R-CERM

10%
16V

402

1

2

CY7C63803-LQXC

12

P1.0/D+

13

P1.1/D-

15

P1.2/VREG

16

P1.3/SSEL

NC

17

P1.4/SCLK

NC

18

P1.5/SMOSI

NC

19

P1.6/SMISO

NC

8

NC

9

NC

10

NC

20

NC

NC

21

NC

22

NC

23

NC

24

NC

VCC

U4800

QFN

OMIT

CRITICAL

THRML

25

14

P0.0

P0.1
INT0/P0.2
INT1/P0.3
INT2/P0.4
TIO0/P0.5
TIO1/P0.6

VSSPAD

11

7

NC

6

NC

5

NC

4

NC

3

NC

2

IR_RX_OUT_RC

1

NC

C4804

0.001UF

CERM

10%
50V

402

1

2

R4800

100

1 2

5%
1/16W
MF-LF

402

IR_RX_OUT

6

36

IN

D

C

C

T57 Connector

T57

BS4890

STDOFF-3.6OD3.4H-SM

1

860-1287

CRITICAL

=PP3V3_S3_T57

7

T57

0.01uF

20%
16V

CERM

402

2 5 3 4

NC

D4890

SLP1210N6

T57

CRITICAL

1

2

IOIONC

STDOFF-3.6OD3.4H-SM

C4895

B

USB_T57_P

6

75

BI

USB_T57_N

6

75

BI

NC_T57_RESET

IN

6

VBUS

1

GND

RCLAMP0502N

J4890

AXK720427G

F-ST-SM

21

1
3
5

NC

7

9
11
13
15
17

NC

19

22

516S0824

BS4891

1

T57

2
4
6
8
10
12
14
16
18
20

T57

860-1287

NC_T57_PWR_EN

NC

NC

NC
NC

=PP5V_S3_T57

T57

1

C4896

0.01uF

20%
16V

2

CERM
402

IN

7

B

A

K6 NOTES : D4890 CONNECTION IS DIFFERENT,CANNOT DIRECTLY SYNC FROM T27

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

Internal USB Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

48 OF 109

SHEET

38 OF 80

SIZE

A

D

NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

D

SMC_P10

(EXCARD_PWR_EN)

C

22

SMC_RSTGATE_L

40

OUT

ALL_SYS_PWRGD

24 65

IN

RSMRST_PWRGD

65

IN

PM_RSMRST_L

18

OUT

IMVP_VR_ON

61

OUT

PM_PWRBTN_L

18

OUT

SMC_P20

40

SMC_P24

40

SMC_BMON_MUX_SEL

44

LPC_AD<0>

18 41 75

BI

LPC_AD<1>

18 41 75

BI

LPC_AD<2>

18 41 75

BI

LPC_AD<3>

18 41 75

BI

LPC_FRAME_L

18 41 75

IN

SMC_LRESET_L

24

IN

LPC_CLK33M_SMC

24 75

IN

LPC_SERIRQ

18 41

BI

SMC_P41

40

SMB_MGMT_DATA

42

BI

SMS_ONOFF_L

49

OUT

SMC_GFX_THROTTLE_L

40

OUT

SMC_SYS_KBDLED

48

OUT

SMC_TX_L

37 39 40 41

OUT

SMC_RX_L

37 39 40 41

IN

SMB_0_S0_CLK

42

BI

(OC)

(OC)

345678

PP3V3_S5_AVREF_SMC

40

=PP3V3_S5_SMC

7

40

1

C4902

22UF

20%

6.3V
CERM

B12

P10

A13

P11

A12

P12

B13

P13

D11

NC

NC
NC
NC

NC

NC

NC

NC
NC

P14

C13

P15

C12 J11

P16 P66

D10

P17

D13

P20

E11

P21

D12

P22

F11

P23

E13

P24

E12

P25

F13

P26

E10

P27

A9

P30

D9

P31

C8

P32

B7

P33

A8

P34

D8

P35

D7

P36

D6

P37

D4

P40

A5

P41

B4

P42

A1

P43

C2

P44

B2

P45

C1

P46

C3

P47

G2

P50

F3

P51

E4

P52

U4900

H8S2117

LGA-HF

(1 OF 3)

OMIT

P60
P61
P62
P63
P64
P65

P67

P70
P71
P72
P73
P74
P75
P76
P77

P80
P81
P82
P83
P84
P85
P86

P90
P91
P92
P93
P94
P95
P96
P97

L13
K12
K11
J12
K13
J10

H12

N10
M11
L10
N11
N12
M13
N13
L12

A7
B6
C7
D5
A6
B5
C6

J4
G3
H2
G1
H4
G4
F4
F1

SMC_PM_G2_EN

NC
NC
NC

SMC_ADAPTER_EN

NC

SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L

SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE

SMC_WAKE_SCI_L

NC

PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK

(OC)

SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA

(OC)

OUT

OUT

IN
IN

IN
IN
IN
IN
IN
IN
IN
IN

OUT

OUT

IN

OUT

IN

BI

IN
IN
IN
IN
IN
IN
IN

BI

6

65

18 40 65

40

6

40 57

44

43

40

40

44

43

44

22

18

18 41

18 41

37 39 40 41

37 39 40 41

42

40 47

8

40 57

40

6

18 65 69

6

18 40 65

18

24 75

42

NOTE: P94 and P95 are shorted in some platforms.

805

1

C4903

0.1UF

20%

2

10V

2

CERM
402

R4999

4.7

1 2

5%
1/16W
MF-LF

402

1

C4904

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=C4920.1:2 mm

PP3V3_S5_SMC_AVCC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.10 MM
VOLTAGE=3.3V

BYPASS=U4900.M12:L9:5 mm

40 41 58

IN

40

40

1

2

C4920

0.1UF

SMC_RESET_L
SMC_XTAL

SMC_EXTAL

C4905

0.1UF

20%
10V
CERM
402

20%
10V

CERM

402

1

C4906

0.1UF

20%
10V

2

CERM
402

1

2

M12

AVCC

D3

RES*

A3

XTAL

A2

EXTAL

VSS

L3

D2

F10

H10

M1

B1

U4900

H8S2117

LGA-HF

(3 OF 3)

OMIT

C5

B11

E1

L11

VCLVCC

AVREF

ETRST

XW4900

SM

2 1

BYPASS=U4900.E1:D2:5 mm

SMC_VCL

1

C4907

0.47UF

10%

6.3V
2

CERM-X5R

402

R4909

10K

1/16W
MF-LF

1

R4998

10K

5%
1/16W
MF-LF
402

2

22 40 43 44

5%

402

AVSS

MD1
MD2

NMI

E5

NC

NC

D1

SMC_KBC_MDE

H1

E3

H3

L9

1

R4902

10K

5%
1/16W
MF-LF
402

12

2

GND_SMC_AVSS

121

R4901

10K

5%
1/16W
MF-LF
402

2

SMC_MD1

SMC_NMI

SMC_TRST_L

NO STUFF

1

R4903

0

5%
1/16W
MF-LF
402

2

D

41

IN

41

IN

41

IN

C

(DEBUG_SW_1)
(DEBUG_SW_2)

B

(EXCARD_CP)

(EXCARD_OC_L)

A

40

40

PM_SYSRST_L

24

OUT

USB_DEBUGPRT_EN_L

37

OUT

MEM_EVENT_L

18 25 26

BI

40

SYS_ONEWIRE

57

BI

PM_BATLOW_L

18

OUT

SMC_RUNTIME_SCI_L

18

OUT

SMC_ODD_DETECT

6

36

IN

40

40

40

SMC_GFX_OVERTEMP_L

40

IN

SMC_FAN_0_CTL

46

OUT

SMC_FAN_1_CTL

40

OUT

SMC_FAN_2_CTL

40

OUT

SMC_FAN_3_CTL

40

OUT

SMC_FAN_0_TACH

46

IN

SMC_FAN_1_TACH

40

IN

SMC_FAN_2_TACH

40

IN

SMC_FAN_3_TACH

40

IN

SMS_X_AXIS

49

IN

SMS_Y_AXIS

49

IN

SMS_Z_AXIS

49

IN

SMC_ANALOG_ID

40

IN

SMC_NB_CORE_ISENSE

40

IN

SMC_NB_DDR_ISENSE

40

IN

SMC_ADC14

40

IN

SMC_ADC15

40

IN

SMC_PA0
SMC_PA1

SMC_PA5

SMC_PB3
SMC_PB4

SMC_PB6

(OC)
(OC)
(OC)
(OC)
(OC)
(OC)

(See below)

NC

NC

A10
C10
B10
C11
A11

G11
G13
F12
H13
G10
G12
H11
J13

M10

K10

N3

PA0

N1

PA1

M3

PA2

M2

PA3

N2

PA4

L1

PA5

K3

PA6

L2

PA7

B8

PB0

C9

PB1

B9

PB2
PB3
PB4
PB5
PB6
PB7

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

PD0

N9

PD1
PD2

L8

PD3

M9

PD4

N8

PD5

K9

PD6

L7

PD7

SMC_PB3:
SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay.

8 7 5 4 2 1

U4900

H8S2117

LGA-HF

(2 OF 3)

OMIT

PE0
PE1
PE2
PE3
PE4
PF0

PF1
PF2
PF3
PF4
PF5
PF6
PF7

PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7

PH0
PH1
PH2
PH3
PH4
PH5

K1
J3
K2
J1
K4
K5

N5
M6
L5
M5
N4
L4
M4

M8
N7
K8
K7
K6
N6
M7
L6

E2
F2
J2
A4
B3
C4

SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_G3H_POWERON_L

SMC_SYS_LED
SMC_LID

NC
NC

SMC_MCP_SAFE_MODE

NC
NC

NC

=SMC_SMS_INT
SMB_BSA_DATA

(OC)

SMB_BSA_CLK

(OC)

SMB_A_S3_DATA

(OC)

SMB_A_S3_CLK

(OC)

SMB_B_S0_DATA

(OC)

SMB_B_S0_CLK

(OC)

SMC_PROCHOT
SMC_THRMTRIP

NC

SMC_PH3

NC
NC

40

IN

40 41

IN

40 41

IN

40 41

OUT

40 41

IN

40

IN

40

OUT

40 47 57

IN

40

OUT

40

IN

42

BI

42

BI

42

BI

42

BI

42

BI

42

BI

40

OUT

40

OUT

40

NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.

H8S2117-R:
(SMC_PECI)
(SMC_PECI_VREF)
(SMC_PECI_VSTP)

SYNC_MASTER=T27_MLB

PAGE TITLE

SYNC_DATE=09/02/2009

SMC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

36

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

49 OF 109

SHEET

39 OF 80

SIZE

B

A

D

345678

2 1

SMC Reset "Button", Supervisor & AVREF Supply

=PP3V3_S5_SMC

7

39 40

=PPVIN_S5_SMCVREF

7

Desktops: 5V
Mobiles: 3.42V

1

C5020

0.47UF

10%

6.3V
2

CERM-X5R

C5001

0.01UF

CERM

10%
16V

402

402

1

2

SMC_TPAD_RST_L

47

D

IN

SMC_ONOFF_L

39 40 47

IN

SMC_MANUAL_RST_L

OMIT

1

R5001

0

5%
1/10W
MF-LF
603

2

SILK_PART=SMC_RST

1
V+

U5010

VREF-3.3V-VDET-3.0V

6

MR1*

(IPU)

MR2*

DELAY

GND

(IPU)

2

SN0903048

7

4

3

VIN

DFN

RESET*

REFOUT

THRM

PAD

9

PLACEMENT_NOTE=Place R5001 on BOTTOM side
MR1* and MR2* must both be low to cause manual reset.

Used on mobiles to support SMC reset via keyboard.
NOTE: Internal pull-ups are to VIN, not V+.

Debug Power "Buttons"

SMC_ONOFF_L

603

OMIT

1

1

R5015

0

0

5%

5%

1/10W
MF-LF
603

2

2

SILK_PART=PWR_BTN
PLACEMENT_NOTEs:

Place R5014 on TOP side
Place R5015 on BOTTOM side

OMIT

R5014

1/10W
MF-LF

SILK_PART=PWR_BTN

C

SMC Crystal Circuit

R5010

0

SMC_XTAL

39

SMC_EXTAL

39

1 2

5%
1/16W
MF-LF

402

SMC_XTAL_R

CRITICAL

Y5010

20.00MHZ

5X3.2-SM

B

System (Sleep) LED Circuit

5

8

C5025

10uF

20%

6.3V
X5R
603

OUT

1

2

1

R5000

1K

5%
1/16W
MF-LF
402

2

SMC_RESET_L
PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V

1

1

C5026

0.01UF

10%
16V

2

2

CERM
402

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V

39 40 47

C5010

15pF

1 2

5%

50V

CERM

402

C5011

15pF

1 2

5%

50V

CERM

402

39

22 39 43 44

39 41 58

OUT

TO CPU

CPU_PROCHOT_L

9

13 61 72

BI

PM_THRMTRIP_L

9

13 72

OUT

SMC Aliases

SMC_MCP_VSENSE

43

MAKE_BASE=TRUE

SMC_CPU_FSB_ISENSE

44

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

44

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

44

MAKE_BASE=TRUE

TP_SMC_GPU_1V8_ISENSE

MAKE_BASE=TRUE

TP_SMC_GPU_ISENSE

MAKE_BASE=TRUE

TP_SMC_GPU_VSENSE

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_L

39 18

IN

SMS_INT_L

40

MAKE_BASE=TRUE

MCP_WAKE_REQ_L

18

IN

SMC_MCP_SAFE_MODE

39 18

IN

SMC_ADC14
SMC_ADC15
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE

SMC_ANALOG_ID
SMC_GPU_ISENSE
SMC_GPU_VSENSE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

=SMC_SMS_INT

SMC_G3H_POWERON_L

MAKE_BASE=TRUE

R5096

0

1 2

5%
1/16W
MF-LF

402

MCP_SPKR

39

OUT

39

OUT

39

OUT

39

OUT

OUT

39

OUT

39

OUT

39

OUT

OUT

39

39 40

OUT

OUT

SMC FSB to 3.3V Level Shifting

=PP3V3_S0_SMC

7

40

1

R5061

100K

5%
1/16W
MF-LF
402

2

CPU_PROCHOT_BUF

3

Q5060

5

DMB53D0UV

SOT-563

4

6

1

3

4

R5062

1 2

D

S G

D

S G

3.3K
CPU_PROCHOT_L_R

5%
1/16W
MF-LF

402

Q5059

SSM6N15FEAPE

SOT563

2

SMC_PROCHOT

Q5059

SSM6N15FEAPE

SOT563

5

SMC_THRMTRIP

SMC Pull-ups

SMC_PA0

39

SMC_PA1

39

SMC_PB4

39

SMC_PB6

39

SMC_ONOFF_L

39 40 47

SMC_LID

39 47 57

SMC_TX_L

37 39 41

SMC_RX_L

37 39 41

SMC_TMS

39 41

SMC_TDO

39 41

SMC_TDI

39 41

SMC_TCK

39 41

SMC_BIL_BUTTON_L

6

39 57

SMC_BC_ACOK

8

39 57

SMS_INT_L

40

SMC_GFX_OVERTEMP_L

39

SMC_G3H_POWERON_L

39 40

SMC_PA5

39

R5091
R5092
R5088
R5095

R5070
R5071
R5073
R5074

R5077
R5078
R5079
R5080
R5081
R5087
R5093
R5094
R5098

R5089

G

2

100K
100K

10K
10K

10K

100K

10K

100K

10K
10K
10K
10K
10K

470K

10K
10K

100K

10K

1

R5060

10K

5%
1/16W
MF-LF
402

2

SMC_PROCHOT_3_3_L

6
D

Q5060

DMB53D0UV

SOT-563

S
1

=PP3V3_S5_SMC

7

39 40

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

5% 402
5% 402

5%

12

5%

=PP3V3_S0_SMC

7

40

5% 402

1/16W
1/16W
1/16W
1/16W

1/16W
1/16W
1/16W
1/16W

1/16W
1/16W
1/16W
1/16W
1/16W
1/16W

1/16W
1/16W

1/16W

TO SMC

MF-LF
MF-LF
MF-LF
MF-LF

MF-LF
MF-LF
MF-LF
MF-LF

MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF1/16W
MF-LF
MF-LF

MF-LF

4025%
4025%
4025%
4025%

4025%
4025%

4025%
4025%
4025%
4025%
4025%
4025%
402
4025%
402

39

OUT

D

39

IN

39

IN

C

B

=PP5V_S3_SYSLED

7

SMC_BS_ALRT_L

121

R5031

523

1/16W
MF-LF

R5032

1.47K

1/16W
MF-LF

A

1%

402

SYS_LED_L_VDIV

1

1%

402

2

SYS_LED_L

39

IN

R5030

20

1%
1/16W
MF-LF
402

2

SYS_LED_ILIM

SMC_SYS_LED

5 46
BD

Q1

GS

1 2 3

E

Q5030

DMB54D0UV

SOT-563

Q2

C

SYS_LED_ANODE

SMC_FAN_1_CTL

39

IN

TP_SMC_FAN_1_TACH

MAKE_BASE=TRUE

SMC_FAN_2_CTL

39

IN

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

SMC_FAN_3_CTL

39

IN

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

SMC_RSTGATE_L

39

IN

SMC_P20

39

IN

SMC_P24

39

IN

SMC_P41

39

IN

SMC_PB3

39

IN

SMC_PH3

39

36

OUT

IN

8 7 5 4 2 1

Unused Pins

TP_SMC_FAN_1_CTL

MAKE_BASE=TRUE

SMC_FAN_1_TACH

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

SMC_FAN_2_TACH

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

SMC_FAN_3_TACH

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

TP_SMC_P20

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

TP_SMC_PB3

MAKE_BASE=TRUE

TP_SMC_PH3

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

39

OUT

39

OUT

39

OUT

36

39

SMC_ADAPTER_EN

18 39 65

SMC_CASE_OPEN

39

PM_SLP_S4_L

6

18 39 65

SMC Pull-downs

R5076
R5085
R5086
R5090

SYNC_MASTER=T27_MLB

PAGE TITLE

100K

10K
10K

100K

1 2
1 2
1 2
1 2

SMC Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

MF-LF
MF-LF1/16W
MF-LF
MF-LF

402
4025%
4025%
402

1/16W

5%

1/16W
1/16W

5%

SYNC_DATE=09/02/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

50 OF 109

SHEET

40 OF 80

SIZE

A

D

345678

2 1

LPC+SPI Connector

CRITICAL

NO STUFF

J5100

D

=PP3V3_S5_LPCPLUS

7

=PP5V_S0_LPCPLUS

7

LPC_AD<0>

18 39 75

BI

LPC_AD<1>

18 39 75

BI

SPI_ALT_MOSI

41 75

SPI_ALT_MISO

41 75

LPC_FRAME_L

18 39 75

IN

PM_CLKRUN_L

18 39

OUT

SMC_TMS

39 40

OUT

LPCPLUS_RESET_L

24

IN

SMC_TDO

39 40

OUT

SMC_TRST_L

39

IN

SMC_MD1

39

OUT

SMC_TX_L

37 39 40

IN

55909-0374

M-ST-SM

31

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29

33

32

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

34

LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>

SPIROM_USE_MLB
SPI_ALT_CLK

SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO

OUT

41 75

41 75

OUT
OUT
OUT
OUT
OUT
OUT

24 75

IN

18 39 75

BI

18 39 75

BI

6

18 50

18 39

BI

18 39

IN

39 40

39 40

39 40 58

39

37 39 40

18

516S0573

D

C

C

SPI Bus Series Termination

SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK

47

5%

402

SPI_ALT_CS_L

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MOSI

SPI_MLB_MISO

47

5%
1/16W
MF-LF

402

LPCPLUS

1

R5126

47

5%
1/16W
MF-LF
402

2

R5121

47

1 2

5%
1/16W
MF-LF

402

LPCPLUS

1

R5125

47

5%
1/16W
MF-LF
402

2

R5120

1 2

1/16W
MF-LF

15

5%
1/16W
MF-LF

402

LPCPLUS

1

R5127

47

5%
1/16W
MF-LF
402

2

R5122

1 2

LPCPLUS

1

R5128

0

5%
1/16W
MF-LF
402

2

R5110

15

402

1 2

1/16W

15

5%

MF-LF

SPI_CS0_R_L

18 75

IN

R5111

402

1 2

1/16W

15

5%

MF-LF

SPI_CLK_R

18 75

IN

R5112

SPI_MOSI_R

18 75

IN

B

18 75

SPI_MISO

6

OUT

1 2

1/16W
MF-LF

402

5%

SPI_CS0_L

SPI_CLK

6

75

SPI_MOSI

6

75

R5123

1 2

41 75

41 75

41 75

41 75

OUT

OUT

OUT

50 75

50 75

50 75

50 75

IN

B

EFI Debug ROM

=PP3V3_S0_DEBUGROM

7

EFI_DEBUG

R5101

1/16W
MF-LF

A

NO STUFF

R5102

1/16W
MF-LF

8 7 5 4 2 1

EFI_DEBUG

1

1

R5103

0

0

5%

5%
1/16W

402

402

MF-LF
402

2

2

DEBUGROM_E2
DEBUGROM_E1

NO STUFF

121

R5104

0

0

5%

5%

1/16W
MF-LF
402

2

Write: 0xAC/0xAE
Read: 0xAD/0xAF

EFI_DEBUG

C5101

0.1UF

CERM

1

20%
10V

2

402

3

E2

2

E1

7

WC*

EFI_DEBUG

8

VCC

U5101

M24M01-R

SO8N

CRITICAL

VSS

4

E0/NC0

5

=I2C_DEBUGROM_SDA

SDA

6

=I2C_DEBUGROM_SCL

SCL

1

NC

42

BI

42

IN

SYNC_MASTER=T27_MLB

PAGE TITLE

LPC+SPI Debug Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

51 OF 109

SHEET

41 OF 80

SIZE

A

D

36

345678

2 1

MCP89 SMBus "0" Connections

=PP3V3_S0_SMBUS_MCP_0

7

121

MCP89

(MASTER)

SMBUS_MCP_0_CLK

12 18 75

D

C

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

12 18 75

MAKE_BASE=TRUE

Vref DACs

(Write: 0x98 Read: 0x99)

Margin Control

(Write: 0x30 Read: 0x31)

EFI Debug Serial

U3300

=I2C_VREFDACS_SCL

28

=I2C_VREFDACS_SDA

28

U3310

=I2C_PCA9557D_SCL

28

=I2C_PCA9557D_SDA

28

U5101
(Write: 0xAC/0xAE
Read: 0xAD/0xAF)

=I2C_DEBUGROM_SCL

41

=I2C_DEBUGROM_SDA

41

R5200

1/16W
MF-LF

402

R5201

1K

1K

5%

5%
1/16W

MF-LF

402

2

SO-DIMM "A"

(Write: 0xA0 Read: 0xA1)

=I2C_SODIMMA_SCL
=I2C_SODIMMA_SDA

SO-DIMM "B"

(Write: 0xA2 Read: 0xA3)

=I2C_SODIMMB_SCL

NBC

=I2C_SODIMMB_SDA

(Write: 0x72 Read: 0x73)

=I2C_MIKEY_SCL
=I2C_MIKEY_SDA

LP8545 (Bklt)

(Write: 0x58 Read: 0x59)

=I2C_BKL_1_SCL
=I2C_BKL_1_SDA

J3100

Mikey

U6880

U9701

25

25

26

26

56

56

70

70

SMC "0" SMBus Connections

=PP3V3_S0_SMBUS_SMC_0_S0

7

121

402

402

R5251

4.7K

5%

5%

1/16W
MF-LF
402

2

121

R5271

1K

1K

5%

5%

1/16W
MF-LF
402

2

MCP Temp

EMC1412-A: U5535

(WRITE: 0X98 READ: 0X99)

=I2C_MCPTHMSNS_SCLSMB_0_S0_CLK
=I2C_MCPTHMSNS_SDA

Trackpad

(Write: 0x90 Read: 0x91)

J5800

=I2C_TPAD_SCL
=I2C_TPAD_SDA

ALS

(Write: 0x52 Read: 0x53)

J3401

I2C_ALS_SCL
I2C_ALS_SDA

45 39

45

48

48

29

29

SMC

U4900U1400 J2900

(MASTER)

SMBUS_SMC_0_S0_SCL

78

SMB_0_S0_DATA

39 39

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC

U4900

(MASTER)

SMB_A_S3_CLK

39

SMB_A_S3_DATA

39

=PP3V3_S3_SMBUS_SMC_A_S3

7

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

78

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

6

78

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

6

78

MAKE_BASE=TRUE

R5250

4.7K

1/16W
MF-LF

R5270

1/16W
MF-LF

SMC "Battery A" SMBus Connections

=PP3V42_G3H_SMBUS_SMC_BSA

7

121

SMC

U4900

(MASTER)

SMB_BSA_CLK

39

SMB_BSA_DATA

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

R5280

2.61K

1/16W
MF-LF

Battery

Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)

SMC "Management" SMBus Connections

=PP3V3_S5_SMBUS_SMC_MGMT

7

SMC

U4900

(MASTER)

SMB_MGMT_CLK

39

SMB_MGMT_DATA

39

SMBUS_SMC_MGMT_SCL

78

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

78

MAKE_BASE=TRUE

R5290

4.7K

1/16W
MF-LF

402

R5281

2.61K

1%

1%
1/16W
MF-LF
402

2

Battery Charger

ISL6259 - U7000

(Write: 0x12 Read: 0x13)

=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA

Battery & BIL

J6950 & J6955

(See Table)

=SMBUS_BATT_SCL
=SMBUS_BATT_SDA

The bus formerly known as "Battery B"

1

1

R5291

4.7K

5%

5%

1/16W
MF-LF
402

402

2

2

58

58

57

57

D

C

MCP89 SMBus "1" Connections

=PP3V3_S0_SMBUS_MCP_1

B

MCP89

(Write: 0x?? Read: 0x??)

MCP89 SMBus 1 is slave port to
access internal thermal diodes.

U1400

SMBUS_MCP_1_CLK

18 75

SMBUS_MCP_1_DATA

18 75

MAKE_BASE=TRUE

NOTE:
R5280/81 WAS 2K ON K24, VALUE NEEDS TO BE CHECKED

R5290/91 (VREF DAC, MARGIN CONTROL)WAS 4.7K ON K24, VALUE NEEDS TO BE CHECKED

A

8 7 5 4 2 1

7

402

402

NO STUFF

121

R5231

2.0K

5%

5%

1/16W
MF-LF
402

2

121

R5236

0

0

5%

5%

1/16W
MF-LF
402

2

NO STUFF

R5230

2.0K

1/16W
MF-LF

R5235

1/16W
MF-LF

HDD Margin Ctrl.

(Write: 0x94 Read: 0x95)

=I2C_HDD_A_SCL
=I2C_HDD_A_SDA

U4510

36

36

SMC "B" SMBus Connections

=PP3V3_S0_SMBUS_SMC_B_S0

SMC

U4900

(MASTER)

SMB_B_S0_CLK

39

SMB_B_S0_DATA

39

7

121

SMBUS_SMC_B_S0_SCL

78

MAKE_BASE=TRUEMAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

78

MAKE_BASE=TRUE

R5260

4.7K

1/16W
MF-LF

402

R5261

4.7K

5%

5%

1/16W
MF-LF
402

2

CPU Temp

EMC1413: U5515

(Write: 0x98 Read: 0x99)

=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA

45

45

SYNC_MASTER=T27_MLB

PAGE TITLE

K6 SMBUS CONNECTIONS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/21/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

52 OF 109

SHEET

42 OF 80

36

SIZE

B

A

D

345678

2 1

CPU Voltage Sense / Filter

PPVCORE_S0_CPU

6 7

XW5309

SM

1 2

PLACE_NEAR=L7400.2:5 MM

CPUVSENSE_IN

D

R5309

4.53K

1 2

1%
1/16W
MF-LF

402

Place RC close to SMC

SMC_CPU_VSENSE

1

C5309

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

OUT

22 39 40 43 44

39

D

MCP Voltage Sense / Filter

PPVCORE_S0_MCP

6 7

XW5359

SM

1 2

PLACE_NEAR=R7525.2:5 MM

MCPVSENSE_IN

R5359

4.53K

1 2

1%
1/16W
MF-LF

402

Place RC close to SMC

SMC_MCP_VSENSE

1

C5359

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

OUT

22 39 40 43 44

40

C

C

PBUS Voltage Sense Enable & Filter

Q5315

NTUD3169CZ

SOT-963

N-CHANNEL

G

=PBUSVSENS_EN

65

IN

Enables PBUS VSense
divider when high.

PPBUS_G3H

6 7

B

R5315

100K

1/16W
MF-LF

1

1%

402

2

2

1

G

5

4

P-CHANNEL

PBUSVSENS_EN_L_DIV

6

D

S

D

S

PBUSVSENS_EN_L

3

PBUS_G3H_VSENSE

R5316

100K

1/16W
MF-LF

1

1%

402

2

1

R5385

27.4K

1%
1/16W
MF-LF

RTHEVENIN = 4573 Ohms

402

2

R5386

5.49K

1/16W
MF-LF

SMC_PBUS_VSENSE

1

1

C5385

0.22UF

1%

20%

6.3V

2

2

X5R
402

GND_SMC_AVSS

22 39 40 43 44

402

39

OUT

B

Place RC close to SMC

A

SYNC_MASTER=T27_MLB

PAGE TITLE

Voltage Sensing

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

53 OF 109

SHEET

43 OF 80

SIZE

A

D

345678

2 1

MCP MEM VDD Current Sense / Filter

=PP3V3_S0_MCPDDRISNS

7

=PP3V3_S0_MCPCOREISNS

1

C5400

0.1uF

20%

R5410

1/16W
MF-LF

R5412

118

1/16W
MF-LF

402

402

5%

1%

10V

CERM

402

0

1

2

2

3

1

2

2

1

+IN

3

-IN

MCPDDR_SENSE_E

Q5401

2SA2154MFV-YAE

SOD
1

MCPDDR_SENSE_B

MCPDDR_SENSE_C

U5400

OPA330

5

SC70-5

V+

4

V-

2

MCPDDR_SENSE_AMP

PLACEMENT_NOTEs:
Place close to SMC

Place close to SMC
(For R and C)

NO STUFF

1

C5434

0.1UF

10%
16V

2

X5R
402

R5417

4.53K

1 2

1%
1/16W
MF-LF

402

2

R5411

0

5%
1/16W
MF-LF

402

1

SMC_MCP_DDR_ISENSE

1

C5435

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

22 39 40 43 44

40

OUT

D

MCPDDRFET_KELVIN

20

IN

MCPDDRFET_SENSE

20

IN

C

MCP/CPU 1.05V AND CPU VCore High-Side Current Sense / Filter

=PP3V3_S0_CPUVTTISNS

7

=PPBUS_S5_CPUREGS_ISNS_R

7

=PPBUS_S5_CPUREGS_ISNS

7

CRITICAL

R5492

0.01

0.5%
MF

0612-1

3

V+

1W

79

4 3

2 1

79

ISNS_CPUVTT_N

ISNS_CPUVTT_P

5

IN-

U5402

INA213

SC70

(50V/V)

GND

2

OUT

1

C5417

0.1uF

20%
10V

2

CERM
402

6

CPUVTT_IOUT

14

REFIN+

PLACEMENT_NOTEs:
Place close to SMC

Place close to SMC
(For R and C)

R5418

4.53K

1 2

1%
1/16W
MF-LF

402

SMC_CPU_FSB_ISENSE

1

C5436

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

7

(Sense R "output")

=MCPCOREISNS_N

8

IN

=MCPCOREISNS_P

8

IN

(Sense R "input")

Sense R is R7525, 1mOhm
Max Vdiff = 24.8mV

40

OUT

22 39 40 43 44

3

V+

U5420

INA214

5

SC70

IN-

4 1

IN+ REF

(100V/V)

GND

OUT

2

1

C5420

0.1uF

20%
10V

2

CERM
402

6

MCPCORE_IOUT

Gain: 100x

Scale: 10A / V
Max VOut: 2.48V

CPU VCore Load Side Current Sense / Filter

B

MCP VCore Current Sense Filter

R5416

4.53K

61

MCPCORES0_IMON

62

IN

IMVP6_IMON

IN

PLACEMENT_NOTEs:
Place close to SMC

Place close to SMC

Place close to SMC
(For R’s and C)

1 2

1%
1/16W
MF-LF

402

R5415

0

1 2

5%
1/16W
MF-LF

402

NOTE: Do not stuff R5415 and
R7593 at the same time!

R5471

6.19K

1 2

1%
1/16W
MF-LF

R5480

402

17.4K

1/16W
MF-LF

402

SMC_MCP_CORE_ISENSE

1

C5472

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

PLACEMENT_NOTEs:
Place close to SMC

Place close to SMC
(For R and C)

SMC_CPU_ISENSE

1

1

C5470

0.22UF

1%

20%

6.3V

2

X5R
402

2

GND_SMC_AVSS

22 39 40 43 44

OUT

22 39 40 43 44

40

OUT

D

C

39

B

=PP3V42_G3H_BMON_ISNS

7

PLACEMENT_NOTE=Place near sense resistor

Charger/Load side

CHGR_CSO_R_P BMON_INA_OUT

58 78

IN

CHGR_CSO_R_N

58 78

IN

Battery side

NOTE: Monitoring current from
battery to PBUS (battery discharge)
across R7008

CHGR_BMON

58

A

IN

From charger

8 7 5 4 2 1

Battery (BMON) Current Sense, MUX & Filter

BMON:ENG

1

3

V+

U5403

INA213

5

SC70

IN-

BMON:ENG

(50V/V)

For engineering, stuff BMON_ENG
For production, stuff BMON_PROD

GND

OUT

REFIN+

2

C5418

0.1uF

20%
10V

2

CERM
402

6

14

BMON:ENG

C5459

0.1uF

CERM

20%
10V

402

1

2

BMON:ENG

U5413

NC7SB3157P6XG

SC70

1

B1

1

2

GND

0

3

B0

VER 1

6

SEL

5

VCC

4

A

BMON:PROD

R5431

0

12

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=Place R5431 next to U5413

1

2

SMC_BMON_MUX_SEL

BMON_AMUX_OUT

BMON:ENG

R5423

100K

5%
1/16W
MF-LF
402

PLACEMENT_NOTEs:
Place close to SMC

Place close to SMC
(For R and C)

39

IN

R5401

45.3K

1 2

1%
1/16W
MF-LF

402

ISL6259 Gain: 36x
INA213 Gain: 50x

SMC_BATT_ISENSE

1

C5490

0.022UF

10%
16V

2

CERM-X5R
402

GND_SMC_AVSS

22 39 40 43 44

DC-IN (AMON) Current Sense Filter

R5481

4.53K

CHGR_AMON

IN

PLACEMENT_NOTEs:
Place close to SMC

Place close to SMC
(For R and C)

39

OUT

1 2

1%
1/16W
MF-LF

402

SMC_DCIN_ISENSE

1

C5487

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

SYNC_MASTER=T27_MLB

PAGE TITLE

Current Sensing

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

OUT

22 39 40 43 44

Apple Inc.

39 58

SIZE

A

D

SYNC_DATE=09/30/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

54 OF 109

SHEET

44 OF 80

36

345678

2 1

CPU T-Diode Thermal Sensor

D

=PP3V3_S0_CPUTHMSNS

7

9

79

BI

CPU_THERMD_P

CPU Thermal Diode

CPU_THERMD_N

9

79

BI

Fin-Stack Temperature

CRITICAL

Q5501

BC846BMXXH

SOT732-3

3

2

CPUTHMSNS_D2_P

1

CPUTHMSNS_D2_N

79

R5515

47

1 2

5%
1/16W
MF-LF

402

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

1

C5521

0.0022uF

10%
50V

2

CERM

402

1

C5520

0.0022uF

10%
50V

2

CERM

402

1

VDD

U5515

EMC1413

DP1

CRITICAL

DN1

DP2/DN3

DN2/DP3

GND

6

DFN

THERM*/ADDR

ALERT*

SMDATA

SMCLK

THRM_PAD

11

PLACEMENT_NOTE=Place U5515 near CPU

Local sensor for CPU Proximity

2 7

3

4

5

1

C5515

0.1uF

20%
10V

2

CERM
402

CPUTHMSNS_THERM_L

8

CPUTHMSNS_ALERT_L

9

=I2C_CPUTHMSNS_SDA

10

=I2C_CPUTHMSNS_SCL

R5516

10K

1/16W
MF-LF

121

R5517

10K

5%

1%

1/16W
MF-LF
402

402

2

42

BI

Addr: 0x98(Wr)/0x99(Rd)

42

BI

PLACEMENT_NOTE=Place Q5501 near Fin Stack

D

C

C

MCP T-Diode Thermal Sensor

=PP3V3_S0_MCPTHMSNS

7

MCP_THMDIODE_P

18 79

BI

B

Addr: 0x98(Wr)/0x99(Rd)

MCP Thermal Diode

MCP_THMDIODE_N

18 79

BI

42

BI

42

BI

R5535

47

1 2

1/16W
MF-LF

=I2C_MCPTHMSNS_SDA
=I2C_MCPTHMSNS_SCL

PP3V3_S0_MCPTHMSNS_R

MIN_LINE_WIDTH=0.25 mm

5%

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

402

C5522

0.0022uF

10%
50V

CERM

402

1

C5535

0.1uF

20%
10V

2

1

DP
DN

SMDATA
SMCLK

VDD

U5535

EMC1412-A

MSOP

THERM*/ADDR

ALERT*

CRITICAL

GND

5

PLACEMENT_NOTE=Place U5535 near MCP

Local sensor for MCP Proximity

1

2

2
3

7
8

CERM
402

MCPTHMSNS_THERM_L

4

MCPTHMSNS_ALERT_L

6

R5536

1/16W
MF-LF

10K

1

1

R5537

1%

402

10K

5%
1/16W
MF-LF
402

2

2

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

Thermal Sensors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

55 OF 109

SHEET

45 OF 80

SIZE

A

D

345678

2 1

D

=PP5V_S0_FAN_RT

7

=PP3V3_S0_FAN_RT

7

CRITICAL

J5601

78171-0004

M-RT-SM
5

NC

1
2
3
4

6

NC

518S0521

5V DC
TACH

MOTOR CONTROL
GND

47K

1/16W
MF-LF

1

5%

2

402

C

R5660

R5665

47K

SMC_FAN_0_TACH

39

SMC_FAN_0_CTL

39

R5661

100K

1/16W
MF-LF

402

1 2

1

5%

1

GS

2

2

5%
1/16W
MF-LF

402

FAN_RT_TACH

6

Q5660

SSM3K15FV

SOD-VESM-HF

D

FAN_RT_PWM

6

3

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=K24_MLB

PAGE TITLE

Fan

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

56 OF 109

SHEET

46 OF 80

345678

2 1

OUT_A

OUT_B

OUT_B

POWERV_SNSR_SNS

0.255E-6 W

16.32E-6 W
36E-3 W

0.72E-3 W
96E-6 W

294E-6 W

75.2E-6 W

1

C5750

0.1UF

10%
16V

2

X7R-CERM
402

4

WS_LEFT_SHIFT_KEY

8

WS_LEFT_OPTION_KEY

1

C5755

0.1UF

10%
16V

2

X7R-CERM
402

SMC_TPAD_RST

4

8

WS_CONTROL_KEY

NO STUFF

Q5702

SSM3K15FV

SOD-VESM-HF

36

1

39 40

G S

47

47

SMC_ONOFF_L

OUT

PLACEMENT_NOTE=NEAR J5713

47

47

SMC_TPAD_RST_L

3

D

2

47

Keyboard Connector

=PP3V3_S3_TPAD

7

47 48

=PP3V42_G3H_TPAD

7

47

WS_KBD1

6

47

WS_KBD2

6

47

WS_KBD3

6

47

WS_KBD4

6

47

WS_KBD5

6

47

WS_KBD6

6

47

WS_KBD7

6

47

WS_KBD8

6

47

WS_KBD9

6

47

WS_KBD10

6

47

WS_KBD11

6

WS_KBD15_C

WS_KBD16N

C5710

0.1UF

20%
10V

CERM

402

R5720

0

1 2

5%
1/16W
MF-LF

402

1

2

R5714

470

1 2

1%
1/16W
MF-LF

402

R5715

10K

1 2

1%
1/16W
MF-LF

402

R5710

1K

1 2

5%
1/16W
MF-LF

402

47

WS_KBD12

6

47

WS_KBD13

6

47

WS_KBD14

6

47

WS_KBD15_CAP

6

WS_KBD16_NUM

6

WS_KBD17

6

47

WS_KBD18

6

47

WS_KBD19

6

47

WS_KBD20

6

47

WS_KBD21

6

47

WS_KBD22

6

47

WS_KBD23

6

47

WS_KBD_ONOFF_L

6

WS_LEFT_SHIFT_KBD

6

47

WS_LEFT_OPTION_KBD

6

47

WS_CONTROL_KBD

6

47

40

OUT

SYNC_MASTER=T27_MLB

PAGE TITLE

WELLSPRING 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

32

NC

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

31

NC

FF14-30A-R11B-B-3H

F-RT-SM

J5713

CRITICAL

518S0637

SYNC_DATE=08/15/2009

DRAWING NUMBER

051-8563

REVISION

BRANCH

PAGE

57 OF 109

SHEET

47 OF 80

A.13.0

SIZE

D

C

B

A

D

PSOC USB CONTROLLER

- USB INTERFACES TO MLB

- SPI HOST TO Z2

- TRACKPAD PICK BUTTONS

- KEYBOARD SCANNER

=PP3V3_S3_TPAD

7

47 48

D

PICKB_L

6

48

BUTTON_DISABLE

47

Z2_HOST_INTN

6

48

WS_LEFT_SHIFT_KEY

47

WS_LEFT_OPTION_KEY

47

WS_CONTROL_KEY

47

Z2_KEY_ACT_L

6

48

TP_P4_5
Z2_DEBUG3

6

48

Z2_RESET

6

48

PSOC_MISO

6

48

PSOC_F_CS_L

6

48

PSOC_MOSI

6

C

48

PSOC_SCLK

6

48

Z2_MISO

6

48

Z2_CS_L

6

48

Z2_MOSI

6

48

Z2_SCLK

6

48

TP_PSOC_SCL
TP_PSOC_SDA
TP_PSOC_P1_3
TP_ISSP_SCLK_P1_1

ISSP SCLK/I2C SCL

USB_TPAD_P

17 75

USB_TPAD_N

17 75

R5704

1.5

5%
1/16W
MF-LF

402

NC

R5701

24

1 2

5%
1/16W
MF-LF

402

R5702

24

1 2

5%
1/16W
MF-LF

402

12

PP3V3_S3_PSOC

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

56

1

P2_5

P2_3

2

P2_1

3

P4_7

4

P4_5

5

P4_3

6

P4_1

7

P3_7

8

P3_5

9

P3_3

10

P3_1

11

P5_7

12

P5_5

13

P5_3

14

P5_1

USB_TPAD_R_P

79

USB_TPAD_R_N

79

P2_7

P1_5

P1_7

NC

525150

535455

VSS

P0_3

P0_5

P0_7

P0_1

CRITICAL

OMIT

U5701

CY8C24794

MLF

(SYM-VER2)

337S2983

D+

D-

P1_1

P1_3

VSS

BYPASS=U5701.49:50:5 mm

1

C5704

100PF

5%
50V

2

CERM
402

44

47

48

49

454643

VDD

VDD

P0_6

P7_7

1

2

P2_4

P2_6

P0_4

P0_2

P0_0

P7_0

P1_0

P1_2

P1_4

P1_6

282627

2524232221201918171615

100PF

5%
50V
CERM
402

BYPASS=U5701.22:19:5 mm

BYPASS=U5701.49:50:8 mm

1

C5705

0.1UF

10%
16V

2

X7R-CERM
402

P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0

THRML

PAD

TP_ISSP_SDATA_P1_0

ISSP SDATA/I2C SDA

1

C5703C5702

0.1UF

10%
16V

2

X7R-CERM
402

BYPASS=U5701.22:19:8 mm

BYPASS=U5701.49:50:11 mm

1

2

WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18

42

WS_KBD17

41

WS_KBD16N

40

WS_KBD15_C

39

WS_KBD14

38

WS_KBD13

37

WS_KBD12

36

WS_KBD11

35

WS_KBD10

34

WS_KBD9

33

WS_KBD8

32

WS_KBD7

31

WS_KBD1

30

WS_KBD2

29

WS_KBD3

57

WS_KBD4
WS_KBD5
WS_KBD6

Z2_CLKIN
TP_P7_7

(PP3V3_S3_PSOC)

1

C5701

4.7UF

20%

6.3V

2

X5R
603

BYPASS=U5701.22:19:11 mm

C5706

4.7UF

20%

6.3V
X5R
603

6

47

6

47

6

47

6

47

6

47

6

47

6

47

47

47

6

47

6

47

6

47

6

47

6

47

6

47

6

47

6

47

6

47

6

47

6

47

6

47

6

47

6

47

6

48

IC

TMP102

3V3 LDO

PSOC

18V BOOSTER

SMC Manual Reset & Isolation

Left shift, option & control keys combined with power button cause SMC RESET# assertion.
Keys ANDed with PSOC power to isolate when PSOC is not powered.

PIN NAME

V+

VDD
VOUT

VDD

VIN

=PP3V42_G3H_TPAD

7

47

=PP3V3_S3_TPAD

7

47 48

B

WS_LEFT_SHIFT_KBD

6

47

TPAD Buttons Disable

WS_LEFT_OPTION_KBD

6

BUTTON_DISABLE

47

39 40 57

IN

Q5701

SSM3K15FV

SOD-VESM-HF

SMC_LID

1

G S

PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

3

D

THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED

2

LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V

A

47

WS_CONTROL_KBD

6

47

CURRENT

10UA
80UA

60MA (MAX)
60MA (MAX)

8MA (TYP)
14MA (MAX)

4MA (MAX)

2.55 KOHM

10 OHM

0.2 OHM

1.5 OHM

4.7 OHM

CRITICAL

2

IN_A1

(IPD)

3

IN_A2

(IPD)

7

IN_A3_B2

(IPD)

6

IN_B1

(IPD)

CRITICAL

2

IN_A1

(IPD)

3

IN_A2

(IPD)

7

IN_A3_B2

(IPD)

6

IN_B1

(IPD)

0.0255 V

0.204 V

0.6 V

0.012 V

0.012 V

0.021 V

0.0188 V

1

VDD

U5750

SLG4AP006

TDFN

THRM

GND

PAD

5

9

1

VDD

U5755

SLG4AP015V

TDFN

OUT_A*

THRM

GND

PAD

9

5

8 7 5 4 2 1

345678

2 1

D

=PP5V_S3_TPAD

7

C

R5805

2 1

1/16W
MF-LF

C5816

X7R-CERM

BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION

- DROOP LINE REGULATION

- RIPPLE TO MEET ERS

- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS

- R5812,R5813,C5818 MODIFIED

0

5%

402

0.1UF

16V

10%

402

PP5V_S3_P18V5S3

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V

PP5V_S3_P18V5S3_VIN

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V

1

C5817

2.2UF

10%

16V

212

X5R
603

CRITICAL

L5801

3.3UH-870MA

VLF3010AT-SM-HF

2

VIN

1

U5805

L

TPS61045

QFN

3

DO

NC

CRITICAL

THRML

PAD

7

9

PGND

CTRL

6

GND

21

4

FB

5

8

SW

P18V5S3_SW

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
SWITCH_NODE=TRUE

P18V5S3_FB

Z2_BOOST_EN

1

R5811

100K

1%
1/16W
MF-LF
402

2

CRITICAL

D5802

B0520WSXG

C5818

6

48

SOD-323

1 2

39PF

50V

CERM

IPD Flex Connector

R5806

0

1UF

25V

603-1

1 2

5%
1/16W
MF-LF

402

1

10%

2

X5R

PP18V5_S3_R

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V

1

R5812

1

1M

1%

5%

1/16W

2

MF-LF

402

402

2

1

R5813

71.5K

1%
1/16W
MF-LF
402

2

C5819

PP18V5_S3

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V

6

48

=PP3V3_S3_TPAD

7

47

Z2_CS_L

6

47

Z2_DEBUG3

6

47

Z2_MOSI

6

47

Z2_MISO

6

47

Z2_SCLK

6

47

Z2_BOOST_EN

6

48

Z2_HOST_INTN

6

47

Z2_CLKIN

6

47

CRITICAL

J5800

55560-0228

M-ST-SM
2
4
6

8

10
12
14
16
18

NC

20
22

1

PP18V5_S3

3
5
7
9
11
13
15
17
19
21

Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SDA
=I2C_TPAD_SCL

6

48

6

47

6

47

6

47

6

47

6

47

6

47

6

47

42

42

D

C

516S0689

B

39

To detect Keyboard backlight, SMC will
tristate and read SMC_SYS_KBDLED:

If LOW, keyboard backlight present
If HIGH, keyboard backlight not present

R5853 always stuffed, R5854 only
grounded when KB BL flex connected.

BI

A

K6 NOTES : C5850 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNC’ED FROM T27

8 7 5 4 2 1

Keyboard Backlight Driver & Detection

7

BYPASS=U5850.1:2:2 MM

=PP3V3_S0_TPAD

7

R5853

SMC_SYS_KBDLED

=PP5V_S0_KBDLED

KB_BL

1

1/16W
MF-LF

5%

402

2

KB_BL

1

R5854

4.7K

5%
1/16W
MF-LF
402

2

C5850

470K

NO STUFF

R5852

10K

1/16W
MF-LF

402

1UF

10V

402-1

5%

CRITICAL

KB_BL

L5850

10UH-0.58A-0.35OHM

1

10%

2

X5R

1

2

6

CTRL

CRITICAL

U5850

LT3491

GND

1

VIN

KB_BL

DFN

2

THRML

PAD

7

1098AS-SM

SW

LED

CAP

21

KBDLED_SW

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE

3

5

KB_BL

1

R5855

10

1%
1/16W
MF-LF
402

2

4

KBDLED_CAP

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

KBDLED_ANODE

6

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

1

2

KB_BL

C5855

1UF

10%

35V

X5R
603

Keyboard Backlight Connector

CRITICAL

KB_BL

J5815

FF18-4A-R11AD-B-3H

F-RT-SM

SMC_KDBLED_PRESENT_L

6

1
2
3
4

518S0691

J5815 pin 1 is grounded
on keyboard backlight flex

B

(SMC_KBDLED_PRESENT_L)

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

WELLSPRING 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/03/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

58 OF 109

SHEET

48 OF 80

36

345678

2 1

D

C

D

C

Analog SMS

=PP3V3_S3_SMS

7

1

SMS_PWRDN

MAKE_BASE=TRUE

R5921

1/16W
MF-LF

10K

C5926

5%

402

10UF

2

SMS_SELFTEST

1

R5922

10K

5%
1/16W
MF-LF
402

2

B

R5921 pulls up SMS_PWRDN
to turn off SMS when pin
is not being driven by SMC

SMS_ONOFF_L

39

IN

20%

4V
X5R
603

212

1

C5922

0.1UF

10%
16V
X5R
402

15

NC
NC

NC
NC

A

8 7 5 4 2 1

14

VDD

U5920

AP344ALH

LGA

1

FS

5

PD

2

ST

RES

4

RES

3

NC

6

NC

9

NC

CRITICAL

GND

7

VOUTX

VOUTY

VOUTZ

SMS_X_AXIS

12

10

SMS_Y_AXIS

8

SMS_Z_AXIS

C5924

0.01UF

CERM

1

C5925

0.01UF

10%
16V

2

402

CERM

10%
16V

402

1

C5923

0.01UF

11

NC

NC

13

NC

NC

16

NC

NC

CERM

10%
16V

2

402

39

OUT

39

OUT

39

OUT

1

2

Desired orientation when
placed on board top-side:

+Y

Front of system

+Z (up)

Circle indicates pin 1 location when placed
in correct orientation

+X

SYNC_MASTER=T27_MLB

PAGE TITLE

Sudden Motion Sensor (SMS)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

59 OF 109

SHEET

49 OF 80

SIZE

B

A

D

36

345678

2 1

D

=PP3V3_S5_ROM

7

SPI:31MHZ&SPI:62MHZ

R6150

C

NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.

1/16W
MF-LF

41 75 41 75

IN IN

41 75

IN

6

18 41

IN

1

1

R6101

10K

3.3K

5%

5%

1/16W
MF-LF
402

402

2

2

SPI_MLB_CLK

SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB

SPI:25MHZ&SPI:41MHZ

C6100

0.1UF

R6152

10K

1/16W
MF-LF

1

20%
10V

2

CERM

402

6

SCLK

1

CE*

3

WP*/ACC

7

HOLD*

1

5%

402

2

CRITICAL

VCC

U6100

32MBIT

SOP

OMIT

GND

4 8

SI/SIO0

SO/SIO1

MX25L3205DM2I-12G

5

2

SPI:41MHZ&SPI:62MHZ

1

R6151

10K

5%
1/16W
MF-LF
402

2

SPI_MLB_MOSI

SPI_MLB_MISO

SPI:25MHZ&SPI:31MHZ

1

R6153

10K

5%
1/16W
MF-LF
402

2

41 75

OUT

D

C

MCP89 SPI Frequency Select

Frequency

25.0 MHz

31.2 MHz

B

41.7 MHz

62.5 MHz

NOTE: 42 & 62 MHz use FAST_READ command.

A

8 7 5 4 2 1

SPI_MOSI

0
0
1
1

SPI_CLK

0
1
0
1

B

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

SPI ROM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/21/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

61 OF 109

SHEET

50 OF 80

36

345678

AUDIO CODEC

L6201

7

IN

=PP1V8R1V5_S0_AUDIO

FERR-220-OHM

0402

D

GND_AUDIO_HP_AMP

51 53 55

PP4V5_AUDIO_ANALOG

6

51

IN

GPIO0 = ANALOG SW CONTROL

GPIO1 = HP AMP CONTROL

GPIO3 = SPKR AMP SHDN CONTROL

55

53

54

56

7

51 55 56

AUD_GPIO_0

OUT

AUD_GPIO_1

OUT

TP_AUD_GPIO_2

NC

AUD_GPIO_3

OUT

AUD_SENSE_A

IN

=PP3V3_S0_AUDIO

IN

U6201 CONSUMES ?MA MAX. FROM 1.5V RAIL

21

1

1

2

1

2

C6226

0.1UF

10%
16V
X5R
402

C6211

2

0.1UF

10%
16V
X5R
402

C6221

10UF

20%

6.3V
X5R
603-1

CRITICAL

C6210

1

R6210

2.67K

1%
1/16W
MF-LF
402

2

4.7UF

20%
4V
X5R-1
402

PP1V8R1V5_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V

CRITICAL

1

1

C6220

10UF

20%

6.3V

2

2

C6222

2.2UF

20%

6.3V
CERM
402-LF

X5R

603-1

212

C6219

TANT-POLY

2012-LLP

CS4206_FP
CS4206_FN

CS4206_FLYP
CS4206_FLYC

1

C6223

CS4206_FLYN

10UF

2.2UF

402-LF

20%
16V

20%

6.3V
CERM

1

2

VBIAS_DAC

C

HDA_BIT_CLK

18 75

IN

HDA_SYNC

18 75

IN

HDA_SDIN0

18 75

OUT

HDA_SDOUT

18 75

IN

HDA_RST_L

18 75

IN

TP_AUD_SPDIF_IN

NC

AUD_SPDIF_OUT

55

OUT

B

GND_AUDIO_CODEC

51 52 55 56

R6211

22

1 2

5%
1/16W
MF-LF

402

AUD_SDI_R

1 2

R6212

39

5%
1/16W
MF-LF

402

AUD_SPDIF_OUT_CHIP

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

APPLE P/N 353S2355

9

VA_REF

VD

29

VBIAS_DAC

44

VHP_FILT+

41

VHP_FILT-

2

GPIO0/DMIC_SDA1

12

GPIO1/DMIC_SDA2

/SPDIF_OUT2

14

GPIO2

15

GPIO3

13

SENSE_A

45

FLYP

43

FLYC

42

FLYN

3

VL_HD

1

VL_IF

6

BITCLK

10

SYNC

8

SDI

5

SDO

11

RESET*

47

SPDIF_IN

48

SPDIF_OUT

THRM_PAD

DGND

7

24

VA_HP

U6201

CS4206ACNZC

QFN

CRITICAL

AGND

49

46

25

VA

HPOUT_L
HPOUT_R

HPREF

LINEOUT_L1+
LINEOUT_L1­LINEOUT_R1+
LINEOUT_R1-

LINEOUT_L2+
LINEOUT_L2­LINEOUT_R2+
LINEOUT_R2-

MICBIAS

VCOM

LINEIN_L+
LINEIN_C­LINEIN_R+

MICIN_L+
MICIN_L­MICIN_R+
MICIN_R-

VREF+_ADC

DMIC_SCL

26

C6218

0.1UF

1

10%
16V

2

X5R
402

38

40

39

35
34

36

37

31
30

32

33

16

CS4206_VCOM

28

21

22
23

18

17
19

20

27

4

C6224

0603-SM

1UF

TANT

=PP5V_S3_AUDIO

=PP3V3R1V5_S0_AUDIO

PP4V5_AUDIO_ANALOG

1

C6217

10UF

2

20%
16V
TANT-POLY
2012-LLP

C6216

1UF

10%
10V
X5R
402-1

1

2

C6215

0.1UF

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

1

10%
16V

2

X5R
402

C6214

0.1UF

1

1

C6213

10UF

CRITICAL

10%
16V
X5R
402

20%

6.3V

2

2

X5R
603-1

GND_AUDIO_HP_AMP

GND_AUDIO_CODEC

AUD_HP_PORT_L
AUD_HP_PORT_R

AUD_HP_PORT_REF

TP_AUD_LO1_P_L
TP_AUD_LO1_N_L
AUD_LO1_P_R
AUD_LO1_N_R

AUD_LO2_P_L
AUD_LO2_N_L
AUD_LO2_P_R
AUD_LO2_N_R

AUD_CODEC_MICBIAS

AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R

CS4206_VREF_ADC

TP_AUD_DMIC_CLK

1

1

C6225

20%
16V

10UF

20%
16V

2

2

TANT-POLY
2012-LLP

NC

NC

NOSTUFF

1

R6213

100K

5%
1/16W
MF-LF
402

2

2 1

7

51 53 55

8

6

51

IN

51 53 55

51 52 55 56

53

OUT

53

OUT

55

IN

NC
NC

54

OUT

FR SPKR AMP. SIG. SOURCE

54

OUT

54

OUT

LFT. SPKR AMP. SIG. SOURCE

54

OUT

54

OUT

RT. SPKR AMP. SIG. SOURCE

54

OUT

56

OUT

AUD_LI_P_L
AUD_LI_REF
AUD_LI_P_R

52

IN

52

IN

52

IN

56

IN

56

IN

56

IN

56

IN

EXT MIC CODEC INPUT

BI MIC CODEC INPUT

D

C

B

4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2456

L6200

51 53 55

51 55 56

7

IN

7

IN

=PP5V_S3_AUDIO

=PP3V3_S0_AUDIO

FERR-220-OHM

0402

R6200

2.21K

1 2

1%
1/16W
MF-LF

402

A

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM

VOLTAGE=5V

21

4V5_REG_IN

4V5_REG_EN

1

C6200

1UF

10%
10V

2

X5R
402

XW6200

SM

1 2

NOSTUFF

R6201

0

1 2

5%
1/16W
MF-LF

402

XW6201

SM

1 2

1

2

6

4

C6201

1UF

10%
10V
X5R
402

IN

EN

U6200

TPS71745

SON

CRITICAL

GND

2

OUT

NR/FB

NC

1

3

4V5_NR

5

1

C6202

0.1UF

10%
16V

2

X7R-CERM

402

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

1

C6203

1UF

10%
10V

2

X5R
402

GND_AUDIO_CODEC

GND_AUDIO_HP_AMP

OUT

6

51

51 52 55 56

51 53 55

8 7 5 4 2 1

NOTES ON CODEC I/O

DIFF FSINPUT= 2.45VRMS
SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS

36

SYNC_MASTER=AUDIO

PAGE TITLE

AUDIO: CODEC/REGULATOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/31/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

62 OF 109

SHEET

51 OF 80

SIZE

A

D

345678

2 1

D

D

LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS
NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)
FC_HP = 3.6 HZ
FC_LP = 43KHZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS

CRITICAL

R6301

7.87K

55

IN

AUD_LI_L

MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

1 2

1%
1/16W
MF-LF

402

AUD_LI_L_DIV

MIN_LINE_WIDTH=.1MM

C

NOSTUFF

1

C6303

820PF

10%
50V

2

CERM
402

MIN_LINE_WIDTH=.1MM

AUD_LI_GND

55

IN

GND_AUDIO_CODEC

51 55 56

IN

B

R6311

7.87K

55

IN

AUD_LI_R

MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

1 2

1%
1/16W
MF-LF

402

MIN_NECK_WIDTH=.1MM

1

R6300

10

1%
1/16W
MF-LF
402

2

AUD_LI_R_DIV

MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

NOSTUFF

1

C6313

820PF

10%
50V

2

CERM
402

1

R6302

21.5K

1%
1/16W
MF-LF
402

2

1

R6312

21.5K

1%
1/16W
MF-LF
402

2

C6301

2.2UF

1 2

20%
10V

X5R-CERM

402

CRITICAL

C6302

2.2UF

1 2

20%
10V

X5R-CERM

402

CRITICAL

C6312

2.2UF

1 2

20%
10V

X5R-CERM

402

CRITICAL

C6311

2.2UF

1 2

20%
10V

X5R-CERM

402

AUD_LI_P_L

MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

AUD_LI_REF

MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

AUD_LI_P_R

MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

51

OUT

C

51

OUT

B

51

OUT

A

8 7 5 4 2 1

36

PAGE TITLE

AUDIO: LINE INPUT FILTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-8563

REVISION

BRANCH

PAGE

63 OF 109

SHEET

52 OF 80

A.13.0

SIZE

A

D

345678

FOR PROTO2, STUFF R6521 AND NO STUFF R6520 AND R6522 UNTIL
RE-TASKABLE IO SW SUPPORT AVAILABLE (FORCES IO INTO OUTPUT MODE).

2 1

D

21

1

2

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

AUD_PP5V_F

1

2

C6521

10UF

20%

6.3V
X5R
603

C6520

0.1UF

10%
16V
X7R-CERM
402

1

R6522

100K

5%
1/16W
MF-LF
402

2

R6530

13.7K

1 2

1%
1/16W
MF-LF

402

NO STUFF

1

R6521

0

5%
1/16W
MF-LF
402

2

L6520

=PP5V_S3_AUDIO

7

51 55

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

R6520

0

AUD_GPIO_1

51

AUD_HP_PORT_L

51 53

IN

AUD_HP_ZOBEL_L

NC

C

GND_AUDIO_HP_AMP

51 53 55

IN

AUD_HP_ZOBEL_R

NC

AUD_HP_PORT_R

51 53

IN

CRITICAL

CRITICAL

R6510

C6510

0.1UF

X7R-CERM

C6500

0.1UF

X7R-CERM

R6500

1/16W
MF-LF

10%
16V

402

1

10%
16V

2

402

1

39

5%
1/16W
MF-LF

402

2

1

39

5%

402

2

1

2

IN

1 2

5%
1/16W
MF-LF

402

B

FERR-120-OHM-1.5A

AUD_LO_AMP_INL_M

53

AUD_LO_AMP_INR_M

53

AUD_GPIO_1_R

GND_AUDIO_HP_AMP

51 53 55

0402-LF

51 53

IN

HP/LO AMP

APN: 353S1637

12

VDD

CRITICAL

6

INL

8

INR

MAX9724A

5

SHDN*

PAD

SGND

THRM

7

13

MAX9724 GAIN/FILTER COMPONENTS

AV_PB = -1V/V, FC_LPF = 35.2KHZ

AUD_LO_AMP_INL_M

U6500

TQFN

PGND

2

SVSS

9

OUTL
OUTR

C1P
C1N

11

10

1

3

PVSS

4

MAX9724_SVSS

CRITICAL

1

C6522

1UF

10%
10V

2

X5R
402

CRITICAL

C6530

330PF

1 2

5%
50V
COG
402

R6531

13.7K

1 2

1%

1/16W
MF-LF

402

53

MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM

MAX9724_C1P

MAX9724_C1N

CRITICAL

1

C6523

1UF

10%
10V

2

X5R
402

CRITICAL

1

C6524

2

1UF

10%
10V
X5R
402

AUD_LO_AMP_OUTL

1

R6523

2.21K

1%
1/16W
MF-LF
402

2 1

AUD_LO_AMP_OUTL

AUD_LO_AMP_OUTR

R6524

2.21K

1%
1/16W
MF-LF
402

2

53 55

OUT

53 55

OUT

53 55

OUT

D

C

B

51 53

IN

AUD_HP_PORT_R

R6532

13.7K

1 2

1%
1/16W
MF-LF

402

A

8 7 5 4 2 1

AUD_LO_AMP_INR_M

36

53

R6533

13.7K

1 2

1%
1/16W
MF-LF

402

CRITICAL

C6531

330PF

1 2

5%
50V
COG
402

AUD_LO_AMP_OUTR

SYNC_MASTER=AUDIO

PAGE TITLE

53 55

OUT

AUDIO: HEADPHONE FILTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/17/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

65 OF 109

SHEET

53 OF 80

SIZE

A

D

SATELLITE & SUB TWEETER AMPLIFIER

APN:353S2524

345678

2 1

SATELLITE

D

SUB
GAIN

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

=PP5V_S3_AUDIO_AMP

7

54

C6611

1 2

10%

50V

CERM

402

C6620

0.022UF

1 2

10%

25V

X7R

0402

CRITICAL

C6610

0.0027UF

1 2

10%

50V

CERM

402

CRITICAL

C6621

0.022UF

1 2

10%

25V

X7R

0402

R6610

0

1 2

5%
1/16W
MF-LF

402

L6610

51

AUD_LO2_N_R

IN

FERR-1000-OHM

FERR-1000-OHM

51

AUD_LO2_P_R

IN

C

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

51

IN

SPKRAMP_SHDN

54

54

7

AUD_GPIO_3

=PP5V_S3_AUDIO_AMP

FERR-1000-OHM

51

AUD_LO1_N_R

IN

51

AUD_LO1_P_R

IN

SPKRAMP_SHDN

54

0402

L6611

0402

L6620

0402

21

SPKRAMP_INR_N

21

SPKRAMP_INR_P

21

SPKRAMP_INSUB_N

L6621

FERR-1000-OHM

0402

21

SPKRAMP_INSUB_P

CRITICAL

0.0027UF

CRITICAL

169 HZ < FC < 282 HZ

80 HZ < FC < 132 HZ
6DB

1

C6607

1UF

10%

10V

2

X5R
402

SSM2315_R_N
SSM2315_R_P

1

R6611

100K

5%
1/16W
MF-LF
402

2

1

C6608

1UF

10%

10V

2

X5R

SSM2315_SUB_N
SSM2315_SUB_P

402

D

CRITICAL

1

B2

PVDD

VDD

U6610

SSM2315

WLCSP

C1

IN-

A1

IN+

CRITICAL

C2

SD*

OUT+
OUT_

C3
A3

C6601

47UF

20%

6.3V

2

TANT1
2012-LLP

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_N_OUT

6

55

6

55

GND

A2B1B3

C

CRITICAL

1

C6603

100UF

B2

PVDD

VDD

U6620

SSM2315

WLCSP

C1

IN-

A1

IN+

CRITICAL

C2

SD*

OUT+
OUT_

C3
A3

2

20%

6.3V
TANT
CASE-AL1

GND

A2B1B3

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_P_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_N_OUT

6

55

6

55

SIZE

B

A

D

B

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

=PP5V_S3_AUDIO_AMP

7

54

CRITICAL

1

C6605

47UF

20%

6.3V

2

TANT1
2012-LLP

51

IN

51

IN

SPKRAMP_SHDN

54

AUD_LO2_N_L

AUD_LO2_P_L

L6630

FERR-1000-OHM

0402

21

SPKRAMP_INL_N

L6631

FERR-1000-OHM

0402

21

SPKRAMP_INL_P

CRITICAL

C6630

0.0027UF

1 2

10%

50V

CERM

402

CRITICAL

C6631

0.0027UF

1 2

10%

50V

CERM

402

SSM2315_L_N
SSM2315_L_P

C6609

1UF

1

10%

10V

2

X5R
402

C1

IN-

A1

IN+

C2

SD*

VDD

U6630

SSM2315

WLCSP

CRITICAL

PVDD

B2

OUT+
OUT_

C3
A3

GND

A2B1B3

A

8 7 5 4 2 1

36

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_P_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT

6

55

6

55

SYNC_MASTER=AUDIO

PAGE TITLE

AUDI0: SPEAKER AMP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/17/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

66 OF 109

SHEET

54 OF 80

345678

2 1

AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX

AUD_SPDIF_OUT

L6701

FERR-1000-OHM

=PP3V3_S0_AUDIO

7

51 56

FERR-1000-OHM

D

APN:514-0671

J6700

SPDIF-TXRX-K24

F-RT-TH

CRITICAL

DETECT
SWITCH

LEFT

RIGHT

MIC

GND

6

5

2
1

3
4

AUD_CONNJ1_MIC

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

AUD_CONNJ1_SLEEVE

AUD_CONNJ1_SLEEVEDET
AUD_CONNJ1_TIPDET

AUD_CONNJ1_TIP
AUD_CONNJ1_RING

AUDIO

PINS

7

8
9

1

1/16W
MF-LF

SM

SM

0

5%

402

OUT

OUT

IN

IN

IN

AUD_GPIO_0

C6700

1UF

10%

6.3V

2

CERM
402

AUD_LO_AMP_OUTL

AUD_LO_AMP_OUTR

AUD_LI_L

AUD_LI_R

10
11

12
13

CHASSIS GND STITCHES

XW6710

1 2

XW6711

1 2

R6760

1 2

53

53

52

52

51

GND STUFFING OPTIONS FOR CMOS SWITCH

AUD_CONN_GND

55

R6718

1 2

GND_AUDIO_CODEC

51 52 56

R6716

1 2

1/16W
MF-LF

402

R6717

0

1 2

5%
1/16W
MF-LF

402

0

5%
1/16W
MF-LF

402

R6719

0

1 2

5%
1/16W
MF-LF

402

0

5%

CRITICAL

DZ6701

6.8V-100PF

402

=PP5V_S3_AUDIO

7

51 53

AUD_LO_AMP_OUTL_SWITCH

AUD_LO_AMP_OUTR_SWITCH

AUD_LI_L_SWITCH

AUD_LI_R_SWITCH

R6715

0

1/16W
MF-LF

5%

402

AUD_SWITCH_GND

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

R6714

1 2

5%
1/16W
MF-LF

402

1 2

CRITICAL

DZ6705

6.8V-100PF

1

C6710

1UF

10%
10V

2

X5R
402

0.0033UF

402

C6711

1

10%
50V
CERM

2

1

1

1

R6721

100K

5%
1/16W
MF-LF
402

2

DZ6704

6.8V-100PF

402

CRITICAL

2

0

CRITICAL

2

2

DZ6703

6.8V-100PF

402

1

CRITICAL

DZ6700

6.8V-100PF

2

402

1

1

C6701

100PF

2

5%

50V

CERM
402

APN: 353S2803

A3

VCC

U6700

SWITCH_CP

MAX14560EWC+

C4

NC1

C1

NC2

A4

NO1

A1

NO2

C2

CB

A2

NEG

WLP

CRITICAL

COM1

COM2

EN*

B4

B1

B2

GND

1

2

402

C3

B3

ANALOG AUDIO IO SWITCH

NOSTUFF

R6727

0

1 2

5%
1/16W
MF-LF

402

A - VIN
B - VCC

OPERATING VOLTAGE 3.3

C - GND

POF

SHELL

SHIELD

C

GND_CHASSIS_AUDIO_JACK

VOLTAGE=0V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM

B

A

CRITICAL

FERR-120-OHM-1.5A

CRITICAL

FERR-220-OHM

CRITICAL

FERR-220-OHM

1 2

1 2

GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED
GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED

0402

L6702

0402

L6703

0402-LF

L6704

0402

L6705

0402

R6700

10K

5%
1/16W
MF-LF

402

R6701

4.7

5%
1/16W
MF-LF

402

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM

21

21

21

21

21

AUD_J1_SLEEVEDET_R

HS_MIC_HI

HS_MIC_LO

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

AUD_CONN_GND

AUD_CONN_L

AUD_CONN_R

AUD_J1_TIPDET_R

1

R6713

24K

5%
1/16W
MF-LF
402

2

AUD_CONN_L

1

R6712

24K

5%
1/16W
MF-LF
402

2

AUD_CONN_R

8 7 5 4 2 1

51

IN

56

OUT

56

OUT

XW6702

SM

1 2

AUD_HP_PORT_REF

XW6700

SM

GND_AUDIO_HP_AMP

1 2

XW6701

SM

1 2

55

BI

55

BI

56

OUT

56

OUT

AUD_LI_GND

(AUD_CONN_GND)

SPEAKER CONNECTOR

55

BI

55

BI

C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES

51

OUT

51 53

52

55

MIC CONNECTOR

APN:518S0520

BI_MIC_LO

6

56

BI_MIC_SHIELD

6

56

BI_MIC_HI

6

56

APN:518S0519

6

54

IN

6

54

IN

SPKRAMP_SUB_P_OUT

6

54

IN

SPKRAMP_SUB_N_OUT

6

54

IN

SPKRAMP_R_P_OUT

6

54

IN

SPKRAMP_R_N_OUT

6

54

IN

SYNC_MASTER=AUDIO

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT

NO STUFF

1

C6760

2

NO STUFF

1

C6761

2

NO STUFF

1

C6762

2

NO STUFF

1

C6763

2

Apple Inc.

R

CRITICAL

78171-0003

33PF

5%
50V
CERM
402

33PF

5%
50V
CERM
402

33PF

5%
50V
CERM
402

33PF

5%
50V
CERM
402

APN:518S0521

AUDIO: JACK

J6701

M-RT-SM

4

1

2

3

5

78171-0002

78171-0004

CRITICAL

CRITICAL

J6702

M-RT-SM

3

1

2

4

J6703

M-RT-SM

5

1

2

3

4

6

SYNC_DATE=08/25/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

67 OF 109

SHEET

55 OF 80

SIZE

D

C

B

A

D

36

345678

2 1

CODEC OUTPUT SIGNAL PATHS

FUNCTION
HP/LINE OUT
LINE IN
SATELLITES
SUB
SPDIF OUT N/A

VOLUME
0X02 (2)
0X05 (5)
0X04 (4)
0X03 (3)

CONVERTER
0X02 (2)
0X05 (5)
0X04 (4)
0X03 (03)
0X08 (8)

PIN COMPLEX
0X09 (9,A)
0X0C (12)
0X0B (11)
0X0A (10) N/A
0X10 (16)

CODEC INPUT SIGNAL PATHS

APN:376S0613

Q6800

SOT563

5

SOT563

2

PIN COMPLEX
0X0D (13,B,RIGHT)
0X0D (13,V22,B,LEFT)

AUD_OUTJACK_INSERT_L

3

D

SG

4

6

D

SG

1

55 56

51

IN

FUNCTION
BUILT-IN MIC
HEADSET MIC

AUD_SENSE_A

OUT

PP3V3_S0_AUDIO_F

56

AUD_J1_TIPDET_R

1

R6801

300K

5%
1/16W
MF-LF
402

2

R6802

1 2

47K

5%
1/16W
MF-LF

402

D

C

GND_AUDIO_CODEC

51 52 55 56

PP3V3_S0_AUDIO_F

55 56

56

AUD_J1_SLEEVEDET_R

IN

GND_AUDIO_CODEC

51 52 55 56

1

2

R6804

220K

5%
1/16W
MF-LF
402

AUD_J1_DET_RC

1

C6802

0.01UF

10%
16V

2

CERM
402

CONVERTER
0X06 (6)
0X06 (6)

1

2

R6803

220K

1 2

5%
1/16W
MF-LF

402

SSM6N15FEAPE

C6801

0.1UF

10V

20%

402

CERM

AUD_J1_SLEEVEDET_INV

SSM6N15FEAPE

Q6800

B

MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM

PP3V3_S0_AUDIO_F

56

VOLTAGE=3.3V

=PP3V3_S0_AUDIO

7

51 55 56

IN

PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA

AUD_J1_TIPDET_R

55 56

L6862

FERR-1000-OHM

0402

10V
402

21

C6861

0.1UF

1

20%

2

CERM

A

GND_AUDIO_CODEC

51 52 55 56

EXTRACTION NOTIFICATION CKT

R6860

TIPDET_FILT

15K

1 2

5%
1/16W
MF-LF

402

Q6802

SSM6N15FEAPE

SOT563

1

C6860

0.1UF

20%
10V

2

CERM
402

2

8 7 5 4 2 1

MUTE CONTROL
GPIO_0 AND GPIO_1
GPIO_0 AND GPIO_1
GPIO_3
GPIO_3
N/A

VREF
MIC_BIAS (80%)
MIKEY

PORT A DETECT (HEADPHONES)

3

D

Q6801

SSM6N15FEAPE

SOT563 SOT563

5

SG

AUD_J1_SLEEVEDET_R

55 56

1

R6864

220K

5%
1/16W
MF-LF
402

2

6

D

SG

1

AUD_J1_TIPDET_INV

1

R6806

39.2K

1%
1/16W
MF-LF
402

2

4

SSM6N15FEAPE

DET ASSIGNMENT
0X09 (A)
0X09 (A)AND UI ELEMENT
N/A

0X0D (B)

DET ASSIGNMENT
N/A
MIKEY

SSM6N15FEAPE

SOT563

D

5

SG

Q6802

PORT B DETECT(SPDIF DELEGATE)

1

R6805

20.0K

1%
1/16W
MF-LF
402

2

AUD_PORTB_DET_LAUD_PORTA_DET_L

NC

6

D

Q6801

2

SG

1

1

R6865

100K

5%
1/16W
MF-LF
402

2

AUD_PERPH_DET_R

3

4

R6861

1 2

5%
1/16W
MF-LF

402

0

NC

AUD_IP_PERIPHERAL_DET

PORT B LEFT(HEADSET MIC)

0.1UF

1 2

10%
25V
X5R
402

C6880

NOSTUFF

HP=80HZ, LP=8.82KHZ

MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V

PP3V3_S0_HS_RX

CRITICAL

MIKEY

1UF

10%

6.3V

CERM
402

R6880

100K

5%
1/16W
MF-LF

402

MIKEY

CRITICAL

C6883

1 2

XW6880

1 2

0.1UF

SM

1

2

1

2

10%
25V
X5R
402

6

SCL

5

SDA

7

INT*

8

ENABLE

HS_MIC_HI_RC

1

R6883

100K

5%
1/16W
MF-LF
402

2

3

AVDD

U6880

CD3275

DRC

MICBIAS

GND THM

9

4

MIKEY

MIKEY

DETECT

BYPASS

11

1

2

DRC MIKEY

APN:353S2256

1

HS_MIC_BIAS

2

HS_SW_DET

10

HS_RX_BP

MIKEY

1

C6881

0.01UF

16V

10%

2

402

CERM

MIKEY

R6884

1 2

MIKEY

C6884

0.0082UF

25V

10%
X7R

402

CRITICAL

2.2K

1/16W
MF-LF

D

MIKEY

CRITICAL

1

C6882

2.2UF

20%

6.3V

2

TANT
402

GND_AUDIO_CODEC

MIKEY

R6881

1/16W
MF-LF

5%

402

MIKEY

1

1

R6882

2.2K

1K

5%

1%

1/16W
MF-LF
402

402

2

2

HS_MIC_HI

MIKEY

1

C6885

27PF

50V

5%

2

CERM

402

CRITICAL

HS_MIC_LO

IN

IN

51 52 55 56

55

C

55

7

51 55 56

=PP3V3_S0_AUDIO

FERR-1000-OHM

PULLUPS ON MCP PAGE

42

IN

42

BI

18

OUT

18

IN

51

OUT

51

OUT

GND_AUDIO_CODEC

51 52 55 56

MIKEY

L6880

0402

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

AUD_I2C_INT_L

AUD_IPHS_SWITCH_EN

GND_AUDIO_CODEC

51 52 55 56

AUD_MIC_INP_L

AUD_MIC_INN_L

21

NOSTUFF

1

R6885

10K

5%
1/16W
MF-LF
402

2

CRITICAL

MIKEY

C6886

PORT B RIGHT(BUILT-IN MIC)

CRITICAL

C6853

0.001UF

50V
402

R6851

2.4K

1 2

1%

1/16W

MF

402-1

1

10%

2

CERM

1

2

CRITICAL

C6854

27PF

5%
CERM

L6850

FERR-1000-OHM

50V
402

FERR-1000-OHM

0402

L6851

0402

21

BI_MIC_HI

21

BI_MIC_LO

BI_MIC_SHIELD

6

55

IN

6

55

IN

6

55

IN

B

51

IN

51 52 55 56

51

OUT

51

OUT

GND_AUDIO_CODEC

51 52 55 56

AUD_CODEC_MICBIAS

GND_AUDIO_CODEC

AUD_MIC_INP_R

AUD_MIC_INN_R

XW6851

SM

1 2

CRITICAL

C6851

0.1UF

1 2

10%
25V
X5R
402

R6850

100

1 2

1%
1/16W
MF-LF

402

CRITICAL

C6850

0.1UF

1 2

10%
25V
X5R
402

R6853

2.4K

1 2

1%

1/16W

MF

402-1

MIC_BIAS_FILT

CRITICAL

1

C6852

2.2UF

20%

6.3V

2

TANT
402

BI_MIC_HI_F

1

R6852

100K

5%
1/16W
MF-LF
402

2

BI_MIC_LO_F

HP=80HZ

16

OUT

SIZE

A

D

SYNC_MASTER=AUDIO

PAGE TITLE

AUDIO: JACK TRANSLATORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

68 OF 109

SHEET

56 OF 80

36

345678

2 1

MagSafe DC Power Jack

CRITICAL

J6900

78048-0573

M-RT-SM

1

2

3

4

D

5

518S0656

ADAPTER_SENSE

6

R6900

100K

1/16W
MF-LF

1

NOSTUFF

5%

402

2

PP18V5_DCIN_FUSE

6

MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V

1

C6905

0.01UF

20%
50V

2

CERM
603

CRITICAL

F6905

6AMP-24V

1206-1

21

=PP3V42_G3H_ONEWIRE

1

C6908

0.1UF

20%
10V

2

CERM
402

R6929

2.0K

402

MF-LF
1/16W

5%

1 2

SYS_ONEWIRE

39

BI

1

VCC

U6900

MAX9940

SC70-5

GND

2

SMC_BC_ACOK_VCC

54

EXTINT

NC

3

NC

4

Y

5

U6901

3

SOT665

TC7SZ08AFEAPE

2

A

1

B

SMC_BC_ACOK

=PP18V5_DCIN_CONN

7

PLACEMENT_NOTE=PLACE NEAR U6901

39 40

8

7

D

1-Wire OverVoltage Protection

3.425V "G3Hot" Supply

C

Supply needs to guarantee 3.31V delivered to SMC VRef generator

R6905

PPDCIN_G3H_OR_PBUS

58

1

1 2

5%

1/8W

MF-LF

805

PPDCIN_G3H_OR_PBUS_R

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V

BYPASS=U6990.6:5:2 MM

C6990

10UF

P3V42G3H_BOOST

DIDT=TRUE

3

1

10%
25V

2

X5R
805

NC

6

BOOST

VIN

U6990

LT3470A

8

SHDN*

DFN

CRITICAL

7

NC

GND

5

BIAS

THRM

PAD

4

1

2

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

P3V42G3H_FB

SW

FB

9

DIDT=TRUE

C6994

0.22uF

1

2

C6995

22pF

5%
50V
CERM
402

CRITICAL

L6995

33UH

CDPH4D19FHF-SM

R6995

348K

1/16W
MF-LF

R6996

200K

1/16W
MF-LF

21

<Ra>

1%

402

<Rb>

1%

402

1

1

2

2

1

2

=PP3V42_G3H_REG

Vout = 3.425V

250MA MAX OUTPUT

(Switcher limit)

CRITICAL

C6999

22UF

20%

6.3V
CERM
805

7

=SMBUS_BATT_SDA

42 57

BI

=SMBUS_BATT_SCL

42 57

BI

40

SMC_BIL_BUTTON_L

6

39

TO SMC

C6954

0.001UF

1

10%
50V

2

CERM

402

C6953

47PF

1

5%

50V

2

CERM

402

20%

6.3V
X5R
402

1

2

BIL CONNECTOR

1

C6952

47PF

5%

50V

2

CERM

402

516S0523

CRITICAL

J6955

CPB6312-0101F

F-ST-SM

14 13

4 3

6 5

8

10

12 11

NC

12

7

9

NC

1516

=PP3V42_G3H_BATT

7

6

SMC_LID_R

C6951

0.1UF

1

10%
25V

2

X5R
402

1

2

C6955

0.001UF

10%
50V
CERM
402

1 2

1/16W

R6961

MF-LF

100

SMC_LID

402

5%

39 40 47

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

Vout = 1.25V * (1 + Ra / Rb)

SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN

518-0359

CRITICAL

J6950

BAT-K24

M-RT-TH

1

P1

2

P2

3

P3

4

P4

5

P5

6

P6

7

P7

8

P8

9

P9

10

11

12
13

=SMBUS_BATT_SCL
SYS_DETECT_L

6

=SMBUS_BATT_SDA

PPVBAT_G3H_CONN

6

58

C6950

0.1UF

BATTERY CONNECTOR

1

10%
25V
X5R
402

C6960

2

603-1

1UF

RCLAMP2402B

1

10%
25V

2

X5R

CRITICAL

D6950

SC-75

42 57

42 57

R6950

1

10K

5%
1/16W
MF-LF

402

2

SYNC_MASTER=K24_MLB

PAGE TITLE

DC-In & Battery Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

69 OF 109

SHEET

57 OF 80

2

1

3

36

345678

This node is powered

Reverse-Current Protection

FROM ADAPTER

=PPDCIN_S5_CHGR

7

D

CRITICAL

BAT30CWFILM

ACIN pin threshold is 3.2V, +/- 50mV

Divider sets ACIN threshold at 13.55V

Input impedance of ~40K meets
sparkitecture requirements

=PP3V42_G3H_CHGR

7

65

1

C

R7010

30.1K

1%
1/16W
MF-LF
402

2

R7012

1/16W
MF-LF

1

1K

1%

402

2

C7002

1UF

39 40 41

10%
10V
X5R
402

IN

1

2

GND_CHGR_AGND

SMC_RESET_L

58

R7000

0

1 2

5%
1/16W
MF-LF

402

Float CELL for 1S

NO STUFF

1

R7013

1K

1%
1/16W
MF-LF

402

1

R7011

9.31K

1%
1/16W
MF-LF
402

2

B

1

R7015

2

220K

5%
1/16W
MF-LF
402

2

CHGR_VCOMP_R

1

C7015

470PF

10%
50V

2

CERM

402

1

R7016

3.01K

1%
1/16W
MF-LF

402

CHGR_VNEG_R

1

C7016

470PF

10%
50V

2

CERM
402

2

NO STUFF

42

42

65

IN
BI
IN

30mA max load

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=5.1V

1

R7002

100K

5%
1/16W
MF-LF
402

2

CHGR_RST_L
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
CHGR_VFRQ
CHGR_CELL

CHGR_ACIN

CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG

78

CHGR_CSO_P
CHGR_CSO_N

78

1

C7050

1UF

10%
16V

2

X5R
402

D7005

SOT-323

1

2

5

Q7080

SO-8

D

3

CRITICAL

S

3
21

G

4

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

1

R7081

62K

5%
1/16W
MF-LF
402

2

CHGR_DCIN_D_R

12

VHST

13

SMB_RST_N

11

SCL

10

SDA

4

VFRQ

6

CELL

3

ACIN

5

ICOMP

7

VCOMP

8

VNEG

18

CSOP

17

CSON

R7001

4.7

1 2

5%
1/16W
MF-LF

402

19

VDDP

VDD

CRITICAL

U7000

TQFN

ISL6259

3% TOLERANCE

20V/V

36V/V

(OD)

(AGND)

THRM_PAD

29

XW7000

SM

1 2

PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm

1

R7080

100K

5%
1/16W
MF-LF
402

2

R7005

20

1 2

5%
1/16W
MF-LF

402

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

20

DCIN

SGATE
AGATE

CSIP
CSIN

BOOT
UGATE
PHASE

LGATE

BGATE

AMON

BMON

ACOK

PGND

353S2929

22

through body diodes:
* DCIN through Q7080.
* PBUS through Q7085,
Charger TOP FETs and
Q7055.

PPDCIN_G3H_OR_PBUS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

(CHGR_SGATE)

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

(CHGR_DCIN)

C7001

2

CHGR_DCIN

26

CHGR_SGATE

1

CHGR_AGATE

28

78

CHGR_CSI_P

27

78

CHGR_CSI_N

25

CHGR_BOOT

24

CHGR_UGATE

23

CHGR_PHASE

21

CHGR_LGATE

16

CHGR_BGATE

9

CHGR_AMON

15

CHGR_BMON

14

=CHGR_ACOK

(GND)

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

C7085

0.1UF

1UF

10%
10V
X5R
402

57

1

R7085

1

470K

2

2

GATE_NODE=TRUE

GATE_NODE=TRUE

OUT
OUT
OUT

1%

1/16W
MF-LF

402

1

C7020

0.047UF

10%
10V

2

CERM
402

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

44

44

8

10%
25V
X5R
402

1

2

Inrush Limiter

Q7085

SO-8

SI7149DPSI7149DP

S

3
21

G

4

(CHGR_AGATE)

1

C7022

0.1UF

10%
25V

2

X5R
402

PLACE_NEAR=U7000.25:2mm

1

C7025

0.22UF

10%
10V

2

CERM
402

4

CRITICAL

D

5

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

R7021

10

1 2

5%
1/16W
MF-LF

402

R7022

10

1 2

5%
1/16W
MF-LF

402

1

C7021

0.1UF

10%
25V

2

X5R
402

5

1 2 3

R7051
R7052

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

CHGR_CSI_R_P

78

CHGR_CSI_R_N

78

5

D

4

G

S

CRITICAL

Q7035

RJK0305DPB

LFPAK-HF

2.2

0

R7086

332K

1/16W
MF-LF

CRITICAL

Q7030

RJK0332DPB-01

LFPAK-SM

321

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

DIDT=TRUE

1 2

1 2

1

1%

402

2

CHGR_PHASE_RC

DIDT=TRUE

NO STUFF

1

C7039

470PF

10%
50V

2

CERM
402

CHGR_CSO_R_P

44 78

5%

1/16W MF-LF

CHGR_CSO_R_N

44 78

1/16W5%MF-LF

(PPVBAT_G3H_CHGR_R)

CRITICAL

R7020

0.020

0.5%
1W
MF-LF
0612

2134

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

Max Current = 8A

f = 400 kHz

NO STUFF

R7039

180

1/10W
MF-LF

603

402

402

1

5%

2

CRITICAL

1

C7030

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

CRITICAL

L7030

4.7UH-9.5A

IHLP4040DZ-SM

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

R7050

0.01

0612-1

21

0.5%
1W
MF

21
43

CRITICAL

1

C7031

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

1

C7035 C7036

1UF

10%
25V

2

X5R
603-1

CRITICAL

1

C7040

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

1

1UF

10%
25V

2

X5R
603-1

1

C7045

0.001UF

10%
50V

2

X7R
402

2 1

1

C7037

0.001UF

10%
50V

2

X7R
402

CRITICAL

F7040

8AMP-24V

1206

21

3

21

CRITICAL

Q7055

SI7137DP

SO-8

S

G

4

TO SYSTEM

=PPBUS_G3H

TO/FROM BATTERY

D

PPVBAT_G3H_CONN

5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

D

C

7

B

6

57

(CHGR_BGATE)

1

C7042

0.033UF

10%
16V

2

X5R
402

C7011

0.01UF

CERM

10%
16V

402

1

1

C7000

1UF

10%
10V

2

2

X5R
402-1

C7005

0.22UF

1

20%
25V

2

X5R
603

58

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

C7026

0.001UF

CERM

1

10%
50V

2

402

* R7051 HAS 2.2OHM TO COMPENSATE UNVALANCED VOLTAGE
DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

A

K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

PBus Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/29/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

70 OF 109

SHEET

58 OF 80

36

345678

2 1

5V_S3/3.3V_S5 POWER SUPPLY

D

D

C

MAX CURRENT = 13.3A

PWM FREQ. = 300 KHZ

B

=PP5V_S3_REG

7

1

C7293

0.001UF

20%
50V

2

CERM
402

1

C7290

10UF

20%

6.3V

2

X5R
603

ROUTING NOTE:

Place XW7203 by Pin1 OF L7260.

ROUTING NOTE:

Place XW7202 by C7292.

=PPVIN_S3_5VS3

7

59

1

C7282

0.001UF

20%
50V

2

CERM
402

1

C7291

220UF

20%

6.3V

2

ELEC
D1A-SM

CRITICAL

CRITICAL

1

C7280

39UF-0.027OHM

20%
16V

2

POLY
B1A-SM

=PPVIN_S3_5VS3

7

59

CRITICAL

Q7260

SIS424DN

PWRPK-1212-8-SM

L7260

CRITICAL

4.7UH-13A-15MOHM

PCMB104E4R7-SM

SIS426DN

PWRPK-12128

VOUT = (2 * RA / RB) + 2

XW7203

SM

5V_S3_VFB_XW7203

12

XW7202

SM

12

1

C7281

1UF

10%
25V

2

X5R
603-1

CRITICAL

Q7261

5

D

G

S

3 2 1

21

5

D

S

13 2

C7260

0.1UF

10%
16V
X5R
402

4

12

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

4

G

DIDT=TRUE

<RA>

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

R7267 R7268

<RB>

15.0K

1%
1/16W
MF-LF
402

1 2 1 2

5VS3_3V3S5_VREF

1

C7271

0.22UF

10%
10V

2

CERM
402

5V_S3_VBST

DIDT=TRUE

5V_S3_DRVH

5V_S3_LL

5V_S3_DRVL

5V_S3_VO1

5V_S3_VFB

5V_S3_ENTRIP

R7271

1

86.6K

1%

1/16W
MF-LF

402

2

10K

1%
1/16W
MF-LF
402

=P5V3V3_REG_EN

65

1

C7272

1UF

10%
25V

2

X5R
603-1

14

SKIPSEL

4

TONSEL

22

VBST1

21

DRVH1

20

LL1

19

DRVL1

24

VO1

2

VFB1

1

ENTRIP1

<RD>

GND_5V3V3S5_SGND

16

VIN

CRITICAL

U7200

QFN

TPS51125

GND

THRM_PAD

15

VREF

3

25

ENTRIP2

VOUT = (2 * RC / RD) + 2

<RC>

R7269

10K

1%
1/16W
MF-LF
402

59

100K

5%

1/16W
MF-LF

402

PP5V_S5_LDO

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V

3V3S5_VBST

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

3V3S5_DRVH

3V3S5_LL

3V3S5DRVL

3V3S5VO2

3V3S5_VFB

3V3S5_ENTRIP

NC

5V3V3_REG_EN

1

2

5V3V3S5_REG3

VREG3

VREG5

VBST2

DRVH2

LL2

DRVL2

VO2

VFB2

VCLK

PGOOD

EN0

R7273

8

17

9

10

11

12

7

5

6

18

23

13

R7220

402

1 2

1

C7273

10UF

20%

6.3V

2

X5R
603

5%

0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

R7270

6.49K

1%
1/16W
MF-LF
402

1 21 2

1

C7270

1UF

20%
10V

2

CERM
603

MF-LF1/16W

3V3S5_VBST_R

DIDT=TRUE

1

2

C7220

0.1UF

DIDT=TRUE

DIDT=TRUE

R7272

75K

1%
1/16W
MF-LF

402

3V3S5_VFB_R7270

10%
16V
X5R

12

402

XW7204

SM

12

XW7205

SM

12

=PPVIN_S5_3V3S5

7

2

D1

G1

1

S1/D2

G2

6

S2

345

ROUTING NOTE:

Place XW7204 by Pin 2 of L7220.

ROUTING NOTE:

Place XW7205 by C7252.

1

C7241

1UF

10%
25V

2

X5R
603-1

Q7220

RJK0384DPA

WPAK

CRITICAL

7

1

2

L7220

CRITICAL

4.7UH-10A

PCMC063T-SM

CRITICAL

C7240

39UF-0.027OHM

20%
16V
POLY
B1A-SM

C

1

C7242

0.001UF

20%
50V

2

CERM
402

PWM FREQ. = 375 KHZ

21

MAX CURRENT = 9.1A

B

CRITICAL

1

C7251

150UF

20%

6.3V

2

POLY
B1A-SM

1

C7250

10UF

20%

6.3V

2

X5R
603

=PP3V3_S5_REG

1

C7253

0.001UF

20%
50V

2

CERM
402

7

GND_5V3V3S5_SGND

59

VOLTAGE=0V
MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

6

D

65

=P5VS3_EN_L

IN

2

SG

A

Q7221

SSM6N15FEAPE

SOT563

1

65

IN

=P3V3S5_EN_L

5

Q7221

3

D

SG

SSM6N15FEAPE

SOT563

4

PLACE_NEAR=U7200.25:1 MM

SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.

NOTE: DONT SYNC THIS PAGE FROM T27

8 7 5 4 2 1

1 2

XW7201

SM

P5V3V3_PGOOD

ROUTING NOTE:

Place XW7201 between Pin 15 and Pin 25 of U7200.

36

65

SIZE

A

D

SYNC_MASTER=K24_MLB

PAGE TITLE

5V/3.3V SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

72 OF 109

SHEET

59 OF 80

345678

2 1

D

=PPVIN_S3_DDRREG

=PPVIN_S0_DDRREG_LDO

7

C7355

10UF

10%
10V
X5R
805

R7305

1 2

1

C7305

2

C7350

0.033UF

4.7

5%
1/16W
MF-LF

402

10%

16V

X5R

402

1

1UF

10%
10V

2

X5R

402-1

NC
NC

1

2

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0V

PP5V_S3_DDRREG_V5FILT

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=5V

15

V5IN

COMP

10

S3

5

2

7

S5
PGOOD

VTTREF

VTT

VTTSNS

NC0
NC1

VTTGND

VTT Enable
VDDQ/VTTREF Enable
VDDQ PGOOD

THRM_PAD

1

25

11
13

24

12

PLACE_NEAR=U7300.3:1 mm

14

CRITICAL

U7300

TPS51116

QFN

SYM (2 OF 2)

GND

3

XW7300

1 2

SM

=PP5V_S3_DDRREG

7

=PP3V3_S3_PDCISENS

7

C7300

1

R7380

100K

5%
1/16W
MF-LF

402

C

=DDRVTT_EN

65

IN

=DDRREG_EN

65

IN

DDRREG_PGOOD

OUT

=PPVTT_S3_DDR_BUF

7

28

=PPVTT_S0_DDR_LDO

7

2

XW7360

1 2

PLACE_NEAR=C7360.1:1 mm

CRITICAL

C7360

22UF

20%

6.3V

X5R-CERM

603

1

2

CRITICAL

1

C7361

22UF

20%

6.3V

2

X5R-CERM
603

4.7UF

10mA max load
Vout = VDDQSNS/2

Vout = VTTREF

SM

DDRREG_VTTSNS

B

7

1

20%

6.3V
2

X5R
603

23

VLDOINV5FILT

86

VDDQSNS

4

MODE

22

VBST

21

DRVH

20

LL

19

DRVL

16

CS

9

VDDQSET

CS_GND

PGND

17

18

PLACE_NEAR=U7300.25:1 mm

1

2

DDRREG_VDDQSNS

DDRREG_VBST

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE
DIDT=TRUE

SWITCH_NODE=TRUE
DIDT=TRUE

GATE_NODE=TRUE
DIDT=TRUE

28

MIN_NECK_WIDTH=0.17 mm

DDRREG_DRVH

DDRREG_LL

DDRREG_DRVL

DDRREG_CS

DDRREG_FB

DDRREG_CSGND

CRITICAL

C7330

39UF-0.027OHM

20%
16V
POLY
B1A-SM

1

R7310

10K

1%
1/16W
MF-LF

402

2

CRITICAL

1

C7331

39UF-0.027OHM

20%
16V

2

POLY
B1A-SM

(DDRREG_DRVH)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

R7325

0

1 2

1/16W
MF-LF

(DDRREG_LL)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

(DDRREG_DRVL)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

(DDRREG_CSGND)

MIN_LINE_WIDTH=0.1 mm
MIN_NECK_WIDTH=0.1 mm

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm

(DDRREG_FB)

DDRREG_VBST_R

MIN_NECK_WIDTH=0.17 mm

5%

MIN_LINE_WIDTH=0.6 mm

402

DIDT=TRUE

1

C7332

1UF

10%
25V

2

X5R
603-1

PLACE_NEAR=Q7335.1:1 mm

1

C7333

0.001UF

10%
50V

2

X7R
402

C7325

0.1UF

1 2

10%
16V
X5R
402

XW7335

SM

1 2

4

5

CRITICAL

D

G

4

G

Q7330

SIS424DN

PWRPK-1212-8-SM

S

CRITICAL

321

1.0UH-13A-5.6MOHM

5

D

Q7335

SIS426DN

PWRPK-12128

S

CRITICAL

1 32

L7330

PCMB065T-SM

21

CRITICAL

1

C7340

330UF

20%

2.5V

2

TANT
CASE-B2-SM

CRITICAL

C7341

330UF

CASE-B2-SM

2.5V
TANT

20%

Vout = 0.75V * (1 + Ra / Req)
SEL_1V5=0: Req = Rb
SEL_1V5=1: Req = Rb || Rc

LVDDR3:YES

Q7322

SSM3K15FV

SOD-VESM-HF

1

2

1

2

DDRREG_P1V5_L

3

D

C7346

0.001UF

10%
50V
X7R
402

C7345

10UF

6.3V

=PPDDR_S3_REG
Vout = 1.501V / 1.352V
19A MAX OUTPUT

f = 400 kHz

PLACE_NEAR=L7330.2:1 MM

1

2

2

<Rc>

XW7345

SM

1

1

R7320

15.0K

1%
1/16W
MF-LF
402

2

<Ra>

LVDDR3:YES

1

R7322

75K

1%
1/16W
MF-LF
402

2

20%
X5R

603

7

1

C7320

0.001UF

10%
50V

2

X7R
402

LVDDR3:YES

R7321

18.7K

1/16W
MF-LF

1

1%

402

2

LVDDR3:YES

<Rb>

D

C

B

1

G S

2

MCP_MEM_VDD_SEL_1V5

18

IN

(GND_DDRREG_SGND)

Use LVDDR3 for 1.5V/1.35V support or LVDDR3_NOT for fixed 1.5V operation.

PART NUMBER

QTY

DESCRIPTION

RES,15K,1%,1/16W,MF-LF,0402

A

NOTE: DONT SYNC THIS PAGE FROM T27. C7330 AND C7331 IS CHANGED TO OSCON CAPS

8 7 5 4 2 1

36

REFERENCE DES

CRITICAL

R73211114S0331

SYNC_MASTER=T27_MLB

PAGE TITLE

1.5V/1.35V LVDDR3 Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM OPTION

LVDDR3:NO

SYNC_DATE=08/06/2009

DRAWING NUMBER

051-8563

REVISION

BRANCH

PAGE

73 OF 109

SHEET

60 OF 80

A.13.0

SIZE

A

D

345678

2 1

=PP5V_S0_CPU_IMVP

7

1 2

R7412

10

5%
1/16W
MF-LF

D

C

B

=PPVIN_S5_CPU_IMVP

7

61

PM_DPRSLPVR

13 72

IN

=PP3V3_S0_IMVP

7

GND_IMVP6_SGND

61

1

2

CPU_NTC:YES

R7427

4.02K

1%
1/16W
MF-LF
402

1 2

CPU_NTC:YES

C7410

0.01uF

10%
16V
CERM
402

1 2

CPU_NTC:YES

CPU_PROCHOT_L

9

13 40
72

1 2

C7405

0.015uF

10%
16V
X7R
402

1

R7409

1K

1%
1/16W
MF-LF
402

2

C7414

470PF

10%
50V
CERM
402

IMVP6_COMP_RC

1

R7414

97.6K

1%
1/16W
MF-LF
402

2

NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.

402

1 2

R7421

10

5%
1/16W
MF-LF
402

CPU_NTC:YES

R7426

470K

402

ERT-J0EV474J

IMVP6_NTC_R

R7406

0

5%
1/16W
MF-LF
402

1 2

R7408

147K

1%
1/16W
MF-LF
402

1 2

C7406

1

0.001UF

10%
50V
CERM

2

402

IMVP6_VDIFF_RC

1

R7411

255

1%
1/16W
MF-LF
402

2

10

11 12

1

2

CRITICAL

21

7 9

1

2

=PP1V05_S0_CPU

CPU_NTC:YES

(IMVP6_FB)

C7413

220PF

5%
25V
CERM
402

(IMVP6_COMP)

C7426

1UF

10%
16V
X5R
402

1 2

R7420

10

5%
1/16W
MF-LF
402

1

R7445

499

1%
1/16W

MF-LF
402

2

R7499

1 2

R7413

1K

1%
1/16W
MF-LF
402

1

2

13 72

IMVP_DPRSLPVR

72

1

68

5%
1/16W
MF-LF

402

2

C7430

1UF

10%
10V
X5R
402

9

IN

9

IN

OUT

FROM SMC

C7496

1UF

10%
16V
X5R
402

10 72

10 72

10 72

10 72

10 72

10 72

10 72

CPU_VID<6>
CPU_VID<5>
CPU_VID<4>
CPU_VID<3>
CPU_VID<2>
CPU_VID<1>
CPU_VID<0>

CPU_DPRSTP_L

CPU_PSI_L

44

1

2

IMVP6 CPU VCORE REGULATOR

A

IMVP6_PHASE1

61

IMVP6_BOOT1

61

IMVP6_UGATE1

61

IMVP6_LGATE1

61

IMVP6_ISEN1

61

K6 NOTES : Q7400-Q7403 CHANGED BACK TO K24 FETS DUE TO LAYOUT
K6 NOTES : BOM OPTION ADDED TO NTC

MIN_LINE_WIDTH MIN_NECK_WIDTH

1.5 MM

0.25 MM 0.25 MM

1.5 MM

1.5 MM

0.25 MM

MIN_NECK_WIDTH

0.25 MM

0.25 MM

0.25 MM

0.20 MM

PP5V_S0_IMVP6_VDD

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=12.6V

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_IMVP6_3V3

1

2

IMVP6_IMON

39

IMVP_VR_ON

IN

VR_PWRGOOD_DELAY

24

OUT

IMVP6_VR_TT

IMVP6_NTC

IMVP6_SOFT

61

61

IMVP6_RBIAS

IMVP6_VDIFF

61

61

IMVP6_FB2
IMVP6_FB

61

IMVP6_COMP

61

61

IMVP6_VW

GND_IMVP6_SGND

61

VOLTAGE=0V

(IMVP6_VW)

C7407

0.001UF

10%
50V
CERM
402

1

R7447

2.0K

5%
1/16W

MF-LF
402

1

2

2

R7410

6.81K

1%
1/16W
MF-LF
402

(NC)

43
42

41
40

39

38
37

46
45

48
47

44

13

12
11

10

25

2

3

1
5

6

7

4

9

VIN VDD

VID6
VID5
VID4
VID3
VID2
VID1
VID0

DPRSTP*
DPRSLPVR
PSI*
IMON

3V3
CLK_EN*
VR_ON
PGOOD
VR_TT*
NTC

SOFT

RBIAS

VDIFF

FB2
FB
COMP
VW

NC

PLACE_NEAR=U7400.21:1 MM

OMIT

XW7400

SM

IMVP6_PHASE2

61

IMVP6_BOOT2

61

IMVP6_UGATE2

61

IMVP6_LGATE2

61

IMVP6_ISEN2

61

20 22 31

CRITICAL

U7400

QFN

ISL9504BCRZ

GND

2

1

PVCC

BOOT1
BOOT2

UGATE1

PHASE1

LGATE1

PGND1

ISEN1

UGATE2

PHASE2

LGATE2

PGND2

ISEN2

VSUM

OCSET

DROOP

DFB

VSEN

RTN

TPAD

4921

1 2

C7432

0.001UF

10%
CERM
402
50V

1 2

C7433

0.001UF

50V
CERM
402
10%

1 2

C7421

0.22uF

10%

6.3V
CERM-X5R
402

VO

1

2

36
26

35

34

32

33

24

27

28

30

29

23

19

8
18

16

17

14

15

C7435

4.7UF

10%
10V
X5R
805

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

DIDT=TRUE

IMVP6_BOOT1
IMVP6_BOOT2

DIDT=TRUE

IMVP6_UGATE1

IMVP6_PHASE1

IMVP6_LGATE1

(GND)

IMVP6_ISEN1

IMVP6_UGATE2

IMVP6_PHASE2

IMVP6_LGATE2

(GND)

IMVP6_ISEN2

IMVP6_VSUM
IMVP6_OCSET

IMVP6_VO

IMVP6_DROOP

IMVP6_DFB

1 2

C7431

0.001UF

10%
50V
CERM

IMVP6_RTN

402

1

R7423

10

1%
1/16W
MF-LF
402

2

MIN_LINE_WIDTH

DPRSLPVR

DPRSTP*

0
0
1
1

1 2

R7424

0

5%
1/16W
MF-LF
402

1 2

R7425

0

5%
1/16W
MF-LF
402

1
1
0
0

IMVP6_BOOT1_RC

DIDT=TRUE

IMVP6_BOOT2_RC

DIDT=TRUE

C7427

1

0.1UF

10%
25V

2

X5R
402

PSI*

1
0
1
0

OPERATION MODE

2-PHASE CCM

1-PHASE CCM

1-PHASE DCM

1-PHASE DCM

C7415

1

0.1UF

10%
25V

2

X5R
402

(KEEP THIS NET AS SHORT AS POSSIBLE)

(KEEP THIS NET AS SHORT AS POSSIBLE)

NO STUFF

C7416

0.001UF

10%
50V
CERM

402

1

R7416

13.7K

1%
1/16W
MF-LF
402

2

1

2

IMVP6_VO_R

1

2

ERT-J1VR103J

R7430

2.61K

1%
1/16W
MF-LF
402

CRITICAL

R7431

10KOHM-5%

0603-LF

61

1

R7418

1K

1%
1/16W
MF-LF
402

2

IMVP6_VSEN

1

2

(IMVP6_VO)

C7434

0.033UF

10%
16V
X5R
402

1 2

R7417

4.02K

1%
1/16W
MF-LF
402

1

2

C7428

0.22UF

10%
10V
CERM
402

1

C7429

2

180pF

5%
50V
CERM

402

1

2

R7415

11K

1%
1/16W
MF-LF
402

R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED

1

R7422

10

1%
1/16W
MF-LF
402

2

CPU_VCCSENSE_P
CPU_VCCSENSE_N

0.25 MM

0.25 MM 0.25 MM

0.25 MM

0.25 MM0.25 MM

0.20 MM

0.25 MM0.25 MM

0.20 MM

10 72

10 72

IMVP6_OCSET

61

IMVP6_VSUM

61

GND_IMVP6_SGND

61

IMVP6_VO

61

IMVP6_DROOP

61

IMVP6_DFB

61

IMVP6_SOFT

61

IMVP6_RBIAS

61

IMVP6_VDIFF

61

IMVP6_FB2

61

IMVP6_FB

61

IMVP6_COMP

61

IMVP6_VW

61

IMVP6_RTN

61

IMVP6_VSEN

61

8 7 5 4 2 1

=PPVIN_S5_CPU_IMVP

7

61

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

4

(THIS NET SHOULD CONNECT

TO U7400.33 WITH MIN LOOP AREA)

RJK0365DPA-02

1

2

TO U7400.29 WITH MIN LOOP AREA)

DIDT=TRUE

DIDT=TRUE

(THIS NET SHOULD CONNECT

5

D

G

4

S

5

CRITICAL

D

G

Q7401

RJK0208DPA

WPAK

S

321

CRITICAL

Q7402

DIDT=TRUE

WPAK

4

5

D

G

4

S

MIN_LINE_WIDTH

0.25 MM 0.20 MM

0.25 MM

0.50 MM 0.20 MM

0.25 MM

0.25 MM 0.20 MM

0.25 MM

0.25 MM 0.20 MM

0.25 MM

0.25 MM 0.20 MM

0.25 MM 0.20 MM

0.25 MM

CRITICAL

Q7400

RJK0365DPA-02

WPAK

321

5

D

G

S

CRITICAL

Q7403

RJK0208DPA

WPAK

321

7

61

321

MIN_NECK_WIDTH

0.20 MM

0.20 MM

0.20 MM

0.20 MM0.25 MM

0.20 MM0.25 MM

0.20 MM

0.20 MM0.25 MM

0.20 MM0.25 MM

0.20 MM

36

CRITICAL

C7409

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

(IMVP6_PHASE1)

(IMVP6_ISEN1)

=PPVIN_S5_CPU_IMVP

CRITICAL

C7401

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

C7408

68UF

(IMVP6_PHASE2)

(IMVP6_ISEN2)

(IMVP6_VSUM)

(IMVP6_VO)

CRITICAL

C7417

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

CRITICAL

20%
16V
POLY-TANT
CASE-D2E-SM

C7418

1

1UF

10%
25V
X5R

2

603-1

0.36UH-26A-1.05MOHM

PLACE_NEAR=L7400.1:1MM

XW7410

IMVP_VSUM1

1 2

R7400

10K

1%
1/16W
MF-LF
402

C7411

1

2

1

1UF

10%
25V
X5R

2

603-1

0.36UH-26A-1.05MOHM

PLACE_NEAR=L7401.1:1MM

SM

1

XW7412

IMVP_VSUM2

1 2

R7405

10K

1%
1/16W
MF-LF
402

1

R7443

3.65K

1%
1/16W
MF-LF
402

2

SYNC_MASTER=K24_MLB

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

C7419

1

0.001UF

10%
50V

CERM

2

PWM FREQ. = 300 KHZ

402

MAX CURRENT = 65.2A

LOAD LINE SLOPE = -2.1 MV/A

L7400

MPCG1040-SM

CRITICAL

SM

1

C7422

0.001UF

10%
50V

CERM

402

21

2

1 2

C7403

0.22UF

10%
10V
CERM
402

1

R7401

3.65K

1%
1/16W
MF-LF
402

2

=PPVCORE_S0_CPU_REG

PLACE_NEAR=L7400.2:1MM

SM

2

1

XW7411

IMVP_VO1

2

402
MF-LF
1/16W
5%

1

R7404

1

L7401

1 2

C7404

0.22UF

10%
10V
CERM
402

21

PLACE_NEAR=L7401.2:1MM

SM

1

XW7413

2

1

MPCG1040-SM

CRITICAL

2

IMVP6 CPU VCore Regulator

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:

2

IMVP_VO2

402
MF-LF
1/16W
5%

1

R7407

C7420

1

0.001UF

10%
50V

CERM

2

402

1

0.001UF

2

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

74 OF 109

SHEET

61 OF 80

C7423

10%
50V

CERM

402

D

7

C

B

A

SIZE

D

345678

=PPVIN_S0_MCPCORE

7

=PP5V_S0_MCPREG

D

PP5V_S0_MCPREG_VDD

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

1

R7561

1/16W
MF-LF

NO STUFF

20

1%
1/16W
MF-LF

402

20

1%
1/16W
MF-LF

402

0

1 2

1 2
1 2
1 2
1 2

5%01/16W

5%
5%01/16W

0
0

1

2

R7563

100

1%
1/16W
MF-LF
402

(MCPCORES0_VSEN)

1

C7570

0.001UF

10%
50V

2

X7R
402

(MCPCORES0_RTN)

1

R7571

100

1%
1/16W
MF-LF
402

2

1

C7579

0.001UF

10%
50V

2

X7R
402

C7581

100PF

1 2

5%

50V

CERM

402

C7582

4700PF

1 2

10%
100V
CERM

402

MF-LF

MF-LF
MF-LF

MF-LF

R7572

4025%

402
4025%
402
402

150K

1/16W
MF-LF

1%

402

1/16W

1/16W
1/16W MF-LF

(MCPCORES0_VW)

1

R7576

6.98K

1%
1/16W
MF-LF
402

2

(MCPCORES0_COMP)

(MCPCORES0_FB)

(MCPCORES0_VDIFF)

1

2

44

OUT

65

OUT

18

IN

18

IN

18

IN

18

IN

65

IN

MCPCORES0_IMON
MCPCORES0_PGOOD

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
MCP_VID<3>

=MCPCORES0_EN

=PPMCPCORE_S0_REG

7

62

R7593

R7590
R7591
R7592
R7594

C

R7566

MCPCORES0_VSEN_P

21 79

IN

MCPCORES0_VSEN_N

21 79

IN

B

R7577

150K

1 2

1%
1/16W
MF-LF

402

R7578

200

1 2

1%
1/16W
MF-LF

402

MCPCORES0_COMP_C

MCPCORES0_VDIF_C

1 2

R7568

1 2

C7580

330PF

1 2

5%
50V
COG
402

R7579

3.01K

1 2

1%
1/16W
MF-LF

402

402

1

1K

5%

C7550

1UF

10%
16V

2

X5R
402

2

MCPCORES0_RBIAS
MCPCORES0_SOFT

MCPCORES0_IMON_R

MCP_VID0_REG
MCP_VID1_REG
MCP_VID2_REG
MCP_VID3_REG

NC

MCPCORES0_FDE

MCPCORES0_VSEN
MCPCORES0_RTN

MCPCORES0_VW

MCPCORES0_COMP

MCPCORES0_FB
MCPCORES0_VDIFF

1

C7577

1

C7576

0.1UF

10%
16V

2

X7R-CERM
402

GND_MCPCORES0_AGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

0.001UF

10%
50V

2

X7R
402

1

C7578

0.001UF

10%
50V

2

X7R
402

7

R7560

2.2

1 2

5%
1/10W
MF-LF

603

16

22

VDD

PVCC

U7500

QFN

ISL9563B

THRM_PAD

15

XW7561

SM

1 2

VIN

UGATE

BOOT

LGATE

OCSET

ICOMP

33

ISP
ISN

VO

RBIAS

2

SOFT

28

IMON

31 19

PGOOD PHASE

24

VID0

25

VID1

26

VID2

CRITICAL

27

VID3

23

NC

29

VR_ON

30

AF_EN

32

FDE

8

VSEN

9

RTN

4

VW

5

COMP

6

FB

7

VDIFF

PGND

VSS

20

PLACE_NEAR=U7500.33:1mm

VID<3:0> VOLTAGE
1100 0.9750V

1101 0.9625V
1110 0.9500V
1111 0.9375V
0000 0.9250V
0001 0.9125V
0010 0.9000V

1

C7562

1UF

10%
16V

2

X5R
402

141

18

MCPCORES0_UGATE

17

MCPCORES0_BOOT

DIDT=TRUE

MCPCORES0_PHASE

SWITCH_NODE=TRUE
DIDT=TRUE

21

MCPCORES0_LGATE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
DIDT=TRUE

12

MCPCORES0_VO

8

3

MCPCORES0_OCSET

13

MCPCORES0_ISP

11

MCPCORES0_ISN

10

MCPCORES0_ICOMP

MCPCORES0_BOOT_R

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

2

R7565

0

5%
1/10W
MF-LF
603

1

(MCPCORES0_UGATE)

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

(MCPCORES0_PHASE)

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

C7564

0.22UF

CERM-X7R

4

R7569

9.76K

1 2

1%
1/16W
MF-LF

402

(MCPCORES0_ISN)

(MCPCORES0_ICOMP)

CRITICAL

C7540

1

5%

10V

2

603

4

5

CRITICAL

D

S

Q7565

RJK0208DPA

WPAK

321

G

POLY-TANT

CASE-D2E-SM

5

CRITICAL

D

G

S

321

CRITICAL

1

68UF 68UF

Q7560

RJK0365DPA-02

WPAK

C7541

20%
16V

2

POLY-TANT

CASE-D2E-SM

CRITICAL

L7560

0.56UH-31A

FDU1040D-SM

CRITICAL

1

68UF

C7560

20%
16V

2

POLY-TANT

CASE-D2E-SM

21

PPMCPCORE_S0_R

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1V

1

1

C7561

1UF

2

10%
25V

2

X5R
603-1

CRITICAL

R7525

0.001

20%
16V

(MCPCORES0_VO)

1

R7573

10K

1%
1/16W
MF-LF
402

2

1

R7575

22.1K

1%
1/16W
MF-LF
402

2

C7573

47PF

5%

50V

CERM

402

C7575

47PF

CERM

50V
402

1

2

R7500

100

1 2

1/16W
MF-LF

1

5%

2

1%

402

MCPCORES0_ISP_R

8

2 1

1

C7563

0.001UF

10%
50V

2

X7R
402

1%
1W
MF

0612

21
43

1

C7566

10UF

20%
4V

2

X5R
603

C7567

10UF

20%

4V
X5R
603

1

2

CRITICAL

1

C7565

270UF

20%
2V

2

TANT
CASE-B4-SM

CRITICAL

C7568

270UF

CASE-B4-SM

TANT

20%

=PPMCPCORE_S0_REG

MAX CURRENT: 30.4A
(Q7560 Limit)
f = 300 kHz

1

1

C7569

0.001UF

10%

2V

50V

2

2

X7R
402

D

7

62

C

B

0011 0.8875V
0100 0.8750V
0101 0.8625V
0110 0.8500V
0111 0.8375V
1000 0.8250V

A

K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27

8 7 5 4 2 1

1001 0.8125V
1010 0.8000V
1011 0.7875V

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP VCore Regulator

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/18/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

75 OF 109

SHEET

62 OF 80

36

345678

2 1

D

C

=PP5V_S0_CPUVTTS0

7

R7601

301

1 2

B

1%
1/16W
MF-LF

402

PP5V_S0_CPUVTTS0_V5FILT

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

=CPUVTTS0_EN

65

IN

CPUVTTS0_PGOOD

65

OUT

(=PPCPUVTT_S0_REG)

CPUVTTS0_VFB

CPUVTTS0_TRIP

1

R7604

8.87K

1%
1/16W
MF-LF
402

2

CPUVTTS0_VOUT

CPUVTT POWER SUPPLY

=PPVIN_S0_CPUVTTS0

7

C7601

402-1

CRITICAL

1

C7630

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

TON

LL

2

14

13

12

9

1

C7604

4.7UF

10%
10V

2

X5R
805

CPUVTTS0_TON

CPUVTTS0_VBST

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

CPUVTTS0_DRVH

GATE_NODE=TRUE

CPUVTTS0_LL

SWITCH_NODE=TRUE

CPUVTTS0_DRVL

GATE_NODE=TRUE

(GND)

GND_CPUVTTS0_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

(CPUVTTS0_VFB)

(=PPCPUVTT_S0_REG)

R7680

1 2

DIDT=TRUE

1/16W
MF-LF

402

0

5%

1

1UF

10%
10V

2

X5R

4

V5FILT

CRITICAL

U7600

TPS51117RGY_QFN14

SYM 2

1

6

3

5

11

EN_PSV

PGOOD

VOUT

VFB

TRIP

QFN

GND

THRM_PAD

7

15

XW7600

SM

1 2

PLACE_NEAR=U7600.15:1MM

PLACE_NEAR=U7600.7:1MM

V5DRV

10

PGND

VBST

DRVH

DRVL

8

CPUVTTS0_VBST_R

MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

1

2

C7695

1UF

10%
25V
X5R
603-1

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

1

2

C7603

0.1UF

1 2

10%
16V
X5R
402

0.001UF

CERM

R7603

226K

1/16W
MF-LF

C7696

20%
50V

402

1

1%

402

2

2

D1

G1

1

G2

6

S2

345

S1/D2

1

2

<Ra>

1

2

<Rb>

Q7620

RJK0384DPA

WPAK

7

2.2UH-8.0A

CPUVTTS0_VSNS

R7670

8.45K

1%
1/16W
MF-LF
402

R7671

20.0K

1%
1/16W
MF-LF
402

L7620

PCMB065T-SM

NO STUFF

XW7665

C7670

100PF

CERM

CRITICAL

21

PLACEMENT_NOTE=Place XW7665 next to L7620

1

2

SM

1

1

5%

50V

2

402

C7665

2

CASE-B2-SM

10UF

20%

6.3V
X5R
603

CRITICAL

C7660

330UF

20%

2.5V
TANT

1

2

2

SM

1

=PPCPUVTT_S0_REG

C7661

1

0.001UF

20%
50V

CERM

2

402

XW7601

ROUTING NOTE:

Place XW7601 by C7660.

VOUT = 1.066V
15A MAX OUTPUT
F = 360 KHZ

7

Vout = 0.75V * (1 + Ra / Rb)

D

C

B

A

K6 NOTES : Q7620 CHANGED BACK TO K24 FETS DUE TO LAYOUT

8 7 5 4 2 1

36

SYNC_MASTER=K24_MLB

PAGE TITLE

CPU VTT(1.05V) SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

76 OF 109

SHEET

63 OF 80

SIZE

A

D

345678

2 1

1.2V ENET Switcher

CRITICAL

=PP3V3_ENET_P1V2ENET

7

CRITICAL
BCM5764M

D

=P1V2ENET_EN

65

IN

PLACE_NEAR=U7720.4:10 mm

BCM5764M

C7720

22UF

6.3V
CERM

20%

805

1

5

1

2

4

VIN

U7720

ST1S12G12R

TSOT23-5L

EN SW

FB/VO

GND

2

P1V2ENET_SW

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

3

P1V2ENET_FB

PLACE_NEAR=L7720.2:1 mm

BCM5764M

L7720

2.2UH-1.2A

PCAA031B-SM

XW7721

SM

1 2

=PP1V2_ENET_REG

21

Vout = 1.2V
Max Current = 0.7A
F = 1.7MHZ

BCM5764M

1

C7721

22UF

20%

6.3V

2

CERM
805

7

=PP3V3_ENET_PHY

7

24 31

BCM57765

C7730

4.7UF

BCM57765 Internal Switcher Support

(This may be required to use BCM57765)

31

BCM57765_SR_LX

31

MIN_LINE_WIDTH=0.4 mm

31

MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

PLACE_NEAR=L7735.2:2 mm

PLACEHOLDER!

CRITICAL
BCM57765

L7735

2.2UH-1.2A

PCAA031B-SM

BCM57765

C7735

10uF

20%

6.3V
X5R
603

6.3V
CERM

BCM57765

R7730

0

1 2

5%
1/16W
MF-LF

402

BCM57765

R7731

0

1 2

5%
1/16W
MF-LF

402

BCM57765

1

1

C7731

0.1UF

20%

603

20%
10V

2

2

CERM
402

PP3V3_ENET_PHY_VDD

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

BCM57765_SR_VDD

PP3V3_ENET_PHY_VDDP

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

TP_BCM57765_SR_VDDP

21

212

BCM57765

R7735

0

1 2

5%
1/16W
MF-LF

402

BCM57765

1

C7736

0.1UF

20%
10V
CERM
402

=PP1V2_ENET_PHY_REG

PP1V2_ENET_PHY_VFB

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE

BCM57765_SR_VFB

7

31

D

353S2769

1.05V S0 MCP PLL LDO

=PP1V05_S0_MCP_PLL_UF_R

7

C

MCPPLL_R:REG

R7745

0

1 2

5%
1/16W
MF-LF

402

=PP1V05_S0_MCP_PLL_OR

7

C

1.5V S0 Regulator

=PP3V3_S0_P1V5S0

7

U7710

ISL8009B

=P1V5S0_EN

65

IN

P1V5S0_PGOOD

65

OUT

B

2

EN

3

POR

4

SKIP

CRITICAL

GND

7 9

BYPASS=U7710.1:9:2 MM

CRITICAL

1

C7710

22UF

20%

CERM

2

6.3V
805

1

VIN

DFN

LX

VFB

RSI

THRM_PAD

P1V5S0_SW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

8

6

P1V5S0_FB

5

Vout = 0.8V * (1 + Ra / Rb)

CRITICAL

L7710

2.2UH-3.25A

IHLP1616BZ-SM

C7711

47PF

CERM

50V
402

21

1

5%

2

1.8V S0 Switcher

=PP1V8_S0_REG

=PP3V3_S0_P1V8S0

7

10uF

6.3V

1

20%

2

X5R
603

C7760

A

65

=P1V8S0_EN

IN

CRITICAL

1

VI

U7760

TPS62202

SOT23-5

4

FB

3 5

EN

GND

SW

2

10UH-0.55A-330MOHM

P1V8S0_SW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

CRITICAL

L7760

PCAA031B-SM

K6 NOTES : C7710 AND C7750 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNC’ED FROM T27

8 7 5 4 2 1

Vout = 1.8V

1

MAX CURRENT = 0.3A
F = 1MHZ

1

C7762

10uF

20%

2

6.3V

2

X5R
603

1

R7711

100K

1%
1/16W
MF-LF
402

2

<Ra>

1

R7712

113K

1%
1/16W
MF-LF
402

2

<Rb>

=PP1V5_S0_REG

7

Vout = 1.508V
MAX CURRENT = 1.5A
f = 1.6MHZ

CRITICAL

1

C7715

22UF

20%

6.3V

2

CERM
805

=PP3V3_S5_P0V9S5

7

7

65

IN

65

OUT

BOMOPTIONs:

MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER.
MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY.

TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE.
TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE.

MCP 0.9V S5 (AUXC) Switcher

BYPASS=U7750.1:9:2 MM

CRITICAL

1

C7750

=P0V9S5_EN
P0V9S5_PGOOD

2

EN

3

POR

4

SKIP

1

VIN

U7750

ISL8009B

DFN

CRITICAL

GND

THRM_PAD

7 9

22UF

6.3V

2

20%

CERM

805

P0V9S5_SW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

8

LX

6

VFB

RSI

P0V9S5_FB

5

Vout = 0.8V * (1 + Ra / Rb)

CRITICAL

L7750

2.2UH-3.25A

IHLP1616BZ-SM

C7751

47PF

CERM

21

5%

50V
402

B

=PP0V9_S5_REG

Vout = 0.902V

1

R7751

1

25.5K

1%
1/16W
MF-LF

2

402

2

<Ra>

1

R7752

200K

1%
1/16W
MF-LF
402

2

<Rb>

MAX CURRENT = 1.5A
f = 1.6MHZ

CRITICAL

1

C7755

22UF

20%

6.3V

2

CERM
805

7

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

Misc Power Supplies

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/30/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

77 OF 109

SHEET

64 OF 80

36

345678

2 1

S5 Rail Enables & PGOOD

=PP3V42_G3H_PWRCTL

7

65

1

C7840

0.1uF

20%
10V

2

CERM

402

=P5V3V3_REG_EN

59

D

OUT

6

39

IN

79

SMC_PM_G2_EN

MAKE_BASE=TRUE

PP3V3_S5

6 7

Threshold: ??

DLY > 10 ms
S5PGOOD_DLY

1

C7841

220PF

5%
25V

2

CERM
402

P0V9S5_PGOOD

IN

2

6

7

IN_A

(IPD)

IN_B

2:1

1.3V

DLY_1C

U7840

SLG4AP012

+

-

DLY

GND

5

S3 Rail Enables

=PP3V42_G3H_PWRCTL

7

65

2

R7813

68K

SOT563

1/16W
MF-LF

402

5%
1/16W
MF-LF

402

1

3

D

5

SG

4

R7812

0

1 2

5%
1/16W
MF-LF

402

R7811

5.1K

1 2

5%

1

5%

2

1/16W
MF-LF

402

C

Q7891

SSM6N15FEAPE

PM_SLP_S4_L

6

18 39 40 65

IN

R7810

100K

B

S0 Rail Enables

R7859

100

PM_SLP_S3_L

6

18 39 65

IN

69

A

5%
1/16W
MF-LF

402

R7879

100K

1/16W
MF-LF

12

2

R7881

33K

5%
1/16W

1

MF-LF
402

1

5%

402

2

1

C7881

0.47UF

10%

6.3V

2

CERM-X5R
402

2

R7880

22K

5%
1/16W
MF-LF
402

1

1

C7880

0.47UF

10%

6.3V

2

CERM-X5R
402

VTT Rail Enable

MCP_MEM_VDD_EN

18 20

IN

MAKE_BASE=TRUE

K6 HAS A PULL UP ON DDRREG_PGOOD. REMOVED ALIAS TO TP SIGNAL

8 7 5 4 2 1

CRITICAL

1

VDD

TDFN

OUT_A*

THRM

PAD

9

P5VS3_EN_L

MAKE_BASE=TRUE

NO STUFF

1

C7813

0.068UF

10%
10V

2

CERM
402

P3V3S3_EN

MAKE_BASE=TRUE

NO STUFF

1

C7812

0.47UF

10%

6.3V

2

CERM-X5R
402

DDRREG_EN

MAKE_BASE=TRUE

1

C7810

0.47UF

10%

6.3V

2

CERM-X5R
402

Internal pull-ups 100K +/- 20%

4

(OD,IPU)

OUT_A

(OD,IPU)

OUT_B

(OD,IPU)

P3V3S5_EN_L

MAKE_BASE=TRUE

3

P0V9S5_EN

MAKE_BASE=TRUE

8

RSMRST_PWRGD

MAKE_BASE=TRUE

=P5VS3_EN_L

=P3V3S3_EN

=DDRREG_EN
=USB_PWR_EN

2

R7882

15K

5%
1/16W
MF-LF
402

1

1

C7882

0.47UF

10%

6.3V

2

CERM-X5R
402

2

R7883

10K

5%
1/16W
MF-LF
402

1

1

C7883

0.47UF

10%

6.3V

2

CERM-X5R
402

=P3V3S5_EN_L
=P0V9S5_EN

1

C7801

0.033UF

10%
16V

2

X5R
402

39 64

OUT

PM_SLP_S3_R_L

MAKE_BASE=TRUE

2

R7884

5.1K

5%
1/16W
MF-LF
402

1

P3V3S0_EN

MAKE_BASE=TRUE

P1V8S0_EN

MAKE_BASE=TRUE

P1V5S0_EN

MAKE_BASE=TRUE

MCPCORES0_EN

MAKE_BASE=TRUE

CPUVTTS0_EN

MAKE_BASE=TRUE

1

C7884

0.47UF

10%

6.3V

2

CERM-X5R
402

Power Control Signals

State
Run (S0)
Sleep (S3)
Soft-Off (S5)

Battery Off (G3Hot)

59

OUT

64

OUT

SMC_PM_G2_ENABLE

1
1
1
0

1
1
0
0

PM_SLP_S3_LPM_SLP_S4_L

1
0
0
0

ISL6259 Frequency Select

=PP3V42_G3H_CHGR

7

58

VFRQ:SLPS4&VFRQ:SLPS3

Q7860

SSM3K15FV

SOD-VESM-HF

CHGR_VFRQ_GATE

R7861

10K

1/16W
MF-LF

1

G S

1

5%

402

2

3

D

2

PM_SLP_S4_L

6

18 39 40 65

PM_SLP_S3_L

6

18 39 65 69

VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH

VFRQ:SLPS4

R7864

0

1 2

5%
1/16W
MF-LF

402

VFRQ:SLPS3

R7863

0

1 2

5%
1/16W
MF-LF

402

CHGR_VFRQ

VFRQ:LOW

1

R7860

10K

5%
1/16W
MF-LF
402

2

58

OUT

D

WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

PM_WLAN_EN_L

Pull-up is with power FET.

6

Q7890

SSM6N15FEAPE

AP_PWR_EN

18 29

IN

SSM6N15FEAPE

59

OUT

SMC_ADAPTER_EN

18 39 40

IN

PM_SLP_S3_L

6

18 39 65 69

IN

66

OUT

SOT563

Q7890

SOT563

D

2

SG

1

AC_OR_S0_L

3

D

5

SG

4

6

1

OUT

D

S G

29

Q7891

SSM6N15FEAPE

SOT563

2

PP5V_S0

S0PGOOD_ISL

R7870

10K

1%
1/16W
MF-LF

402

S0PGOOD_ISL

R7871

20.0K

1%
1/16W
MF-LF

402

PP3V3_S0

6 7

65 79

PP1V5_S0

6 7

65 79

PP1V05_S0

6 7

65

Worst-Case Thresholds:
VDD: 2.9140V
V2MON: 3.000V
V3MON: 0.610V
V4MON: 0.610V

ENET Rail Enables

PM_SLP_RMGT_L

18

IN

MAKE_BASE=TRUE

=PP3V3_ENET_PWRCTL

7

60

OUT

37

OUT

=P5VS0_EN
=PBUSVSENS_EN

=P3V3S0_EN
=P1V8S0_EN
=P1V5S0_EN
=MCPCORES0_EN
=CPUVTTS0_EN

VTT rail must ramp up in about
the same time as MEMVDD rail (Q2300).

=DDRVTT_EN

OUT

66

OUT

43

OUT

66

OUT

64

OUT

64

OUT

62

OUT

63

OUT

60

R7850

15K

1/16W
MF-LF

R7851

15K

1/16W
MF-LF

1

5%

402

2

1

5%

402

2

=P3V3ENET_EN
=P0V9ENET_EN

P1V2ENET_EN

MAKE_BASE=TRUE

=P1V2ENET_EN

66

OUT

66

OUT

PP3V3_S0

6 7

65 79

64

OUT

PP1V5_S0

6 7

65 79

PP1V05_S0

6 7

65

S0 Rail PGOOD Circuitry

1

S0 Rail PGOOD (ISL Version)

2

PP3V3_S0_VMON

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

2

S0PGOOD_ISL

C7870

0.1uF

CERM

1

20%
10V

2

402

3
5
6 8

ISL88042IRTJJZ

V2MON
V3MON
V4MON

S0 Rail PGOOD (BJT Version)

=PP3V3_S5_VMON

7

S0PGOOD_BJT

R7823

1K

1 2

5%
1/16W
MF-LF

402

R7826

S0PGOOD_BJT

1

R7821

15.0K

1%
1/16W
MF-LF
402

2

S0PGOOD_BJT

S0PGOOD_BJT

R7824

1K

1 2

5%
1/16W
MF-LF

402

S0PGOOD_BJT

R7825

1K

1 2

S0PGOOD_BJT

1

R7822

7.15K

1%
1/16W
MF-LF
402

2

5%
1/16W
MF-LF

402

36

CRITICAL
S0PGOOD_ISL

2

7

VDD

VDDA

U7870

TDFN

(IPU)

1

MR*

NC

S0PGOOD_RST_L

RST*

THRM_PAD

GND

9

4

353S2718

1

150K

1%
1/16W
MF-LF

402

2

S0PGOOD_BJT_L

VMON_Q2_BASEVMON_3V3_DIV

VMON_Q3_BASE

VMON_Q4_BASE

Worst-Case Thresholds:
Q2: 0.XXXV
Q3: 0.640V
Q4: 0.660V

3.3V w/Divider: 2.345V

NC

NC

6

5

Q2

8

7

Q3

2

1

Q4

=PP3V3_S0_PWRCTL

7 6 7

R7820

P5V3V3_PGOOD

59

IN

P1V5S0_PGOOD

64

IN

MCPCORES0_PGOOD

62

IN

CPUVTTS0_PGOOD

63

IN

MCPPLLLDO_PGOOD

IN

NO STUFF

R7872

10

1 2

5%
1/16W
MF-LF

402

S0PGOOD_BJT

R7828

10

100

1 2

5%
1/16W
MF-LF

402

1

5%

402

2

S0PGOOD_BJT

4

Q1

CRITICAL
S0PGOOD_BJT

Q7820

ASMCC0179

DFN2015H4-8

3

353S2809

VMON_EMITTER

S0PGOOD_BJT

R7827

SYNC_MASTER=T27_MLB

PAGE TITLE

1/16W
MF-LF

Power Sequencing

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

10K

1/16W
MF-LF

1

5%

402

2

ALL_SYS_PWRGD

MAKE_BASE=TRUE

SYNC_DATE=11/24/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

78 OF 109

SHEET

65 OF 80

C

24 39

OUT

B

A

SIZE

D

345678

2 1

3.3V S3 FET

=PP3V3_S5_P3V3S3FET

7

1

R7912

10K

5%

1/16W

Q7903

SOD-VESM-HF

1

MF-LF

402

G S

2

P3V3S3_EN_L

3

D

2

R7910

47K

1 2

1/16W
MF-LF

D

SSM3K15FV

=P3V3S3_EN

65

IN

1

C7911

0.033UF

10%
16V

2

X5R
402

5%

402

P3V3S3_SS

3.3V S0 FET

=PP3V3_S5_P3V3S0FET

7

1

R7932

100K

5%
1/16W
MF-LF

1

402

G S

2

P3V3S0_EN_L

3

D

2

R7930

47K

1 2

1/16W
MF-LF

C

Q7905

SSM3K15FV

SOD-VESM-HF

=P3V3S0_EN

65

IN

1

C7931

0.033UF

10%
16V

2

X5R
402

5%

402

P3V3S0_SS

CRITICAL

Q7910

FDC638P_G

4

Q7930

FDC606P_G

SOT-6

4

SM

3

C7910

0.01UF

1 2

CERM

CRITICAL

SGD

3

C7930

0.01UF

1 2

CERM

=PP3V3_S3_FET

6
5
2
1

MOSFET
Type
Rds(on)
ID(max)

10%
16V

402

6521

Loading

=PP3V3_S0_FET

7

Q7910

FDC638P
P-Channel
65 mOhm @2.5V

2.0 A @85C

0.606 A (EDP)

7

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P0V9ENETFET

7

Q7930

MOSFET
Type
Rds(on)
ID(max)

10%
16V

402

Loading

FDC606P
P-Channel
35 mOhm @2.5V

2.7 A @85C

1.895 A (EDP)

65

IN

SSM6N15FEAPE

=P0V9ENET_EN

3.3V ENET Switch

U7980

TPS22924

CSP

65

IN

=P3V3ENET_EN

C7980

1UF

6.3V
CERM

A2
B2

C2

1

10%

2

402

VIN

CRITICAL

ON

GND

VOUT

C1

0.9V ENET FET

=PP0V9_ENET_P0V9ENETFET

7

R7990

100K

1 2

5%

1/16W

R7992

Q7991

SOT563

69.8K

1/16W
MF-LF

5

1

1%

402

2

P0V9ENET_EN_L

3

D

SG

4

MF-LF

402

SSM6N15FEAPE

R7991

10K

1 2

1/16W
MF-LF

=PP3V3_ENET_FET

A1
B1

C7990

0.1UF

P0V9ENET_SS

Q7991

SOT563

1%

402

U7980

1

2

D

SG

TPS22924C
Load Switch
18 mOhm Typ

50 mOhm Max
2 A

0.4 A (EDP)

1

6

C7991

1

0.01UF

Part
Type
R(on)

I(max)
Loading

20%
10V

CERM

402

2

P0V9ENET_EN_L_RC

8 7

D

3

CRITICAL

D

Q7990

CERM

S

2

1

10%
16V

2

402

SI2312BDS

SOT23

=PP0V9_ENET_FET

Q7990

MOSFET
Type
Rds(on)
ID(max)
Loading

7

SI2312BDS
N-Channel
37 mOhm @2.5V

3.25 A @85C

0.140 A (EDP)

C

G

5V S0 FET

=PP5V_S3_P5VS0FET

7

1

1

R7942

47K

5%
1/16W

Q7945

SOD-VESM-HF

1

MF-LF

402

G S

2

P5VS0_EN_L

3

D

2

B

SSM3K15FV

=P5VS0_EN

65

IN

A

8 7 5 4 2 1

C7941

0.033UF

R7940

47K

1 2

5%
1/16W
MF-LF

402

10%
16V

2

X5R
402

P5VS0_SS

CRITICAL

Q7940

TPCP8102

31 2

23V1K-SM

S

G

4

C7940

0.01UF

D

1 2

10%
16V

CERM

402

7 85 6

=PP5V_S0_FET

Q7940

Part
Type
Rds(on)
Loading

7

TPCP8102
P-Channel
14 mOhm @4.5V

1.675 A (EDP)

B

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

Power FETs

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

79 OF 109

SHEET

66 OF 80

36

345678

2 1

D

D

LCD CONNECTOR

LCD_IG_PWR_EN

16

1

R9014

1K

5%
1/16W
MF-LF
402

2

=PP3V3_S5_LCD

7

1

C9009

C

0.1UF

10%
16V

2

X5R
402

1

2

3

ON

VIN_1

VIN_2

CRITICAL

U9000

FPF1009

MFET-2X2-8IN

GND

6 7

VOUT_1

VOUT_2
THRM

PAD

L9004

4

5

1

C9011

0.1UF

10%
16V

2

X5R
402

1

C9012

10UF

20%

6.3V

2

X5R
603

PP3V3_LCDVDD_SW

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

LVDS_DDC_CLK

6 8

LVDS_DDC_DATA

6 8

=PP3V3_S0_LCD

7

1

R9008

100K

5%
1/16W
MF-LF
402

2

FERR-120-OHM-1.5A

1

R9009

100K

5%
1/16W
MF-LF
402

2

0402-LF

21

L9008

120-OHM-0.3A-EMI

0402-LF

(LVDS DDC POWER)

CRITICAL

21

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20 MM

LVDS_IG_A_CLK_N

8

74

LVDS_IG_A_CLK_P

8

74

C9015

0.001UF

PP3V3_S0_LCD_F

6

VOLTAGE=3.3V

4

3 2

10%
50V
X7R
402

MIN_NECK_WIDTH=0.20 MM

CRITICAL

L9080

90-OHM-200MA

AMC2012-SM

SYM_VER-1

1

2

1

70

70

70

70

C9010

0.001UF

10%
50V
X7R
402

LED_RETURN_1

6

LED_RETURN_2

70

LED_RETURN_3

70

LED_RETURN_4

6

LED_RETURN_5

6

LED_RETURN_6

6

1

2

PP3V3_LCDVDD_SW_F

6

VOLTAGE=3.3V

6

70

LVDS_CONN_A_CLK_F_N

6

79

6

79

LVDS_CONN_A_CLK_F_P

PPVOUT_SW_LCDBKLT

6

70

BKL_VSYNC

LVDS_IG_A_DATA_N<0>

6 8

74

LVDS_IG_A_DATA_P<0>

6 8

74

LVDS_IG_A_DATA_N<1>

6 8

74

LVDS_IG_A_DATA_P<1>

6 8

74

LVDS_IG_A_DATA_N<2>

6 8

74

LVDS_IG_A_DATA_P<2>

6 8

74

C9020

0.001UF

10%
50V
X7R
402

MIN_LINE_WIDTH=0.30 MM

1

2

B

LVDS CONNECTOR:518S0650

FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED

ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY

NC

NC

NC

CRITICAL

J9000

20474-030E-11

F-RT-SM

31
32

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

LVDS I/F

18
19
20
21
22
23
24

LED BKLT I/F

25
26
27
28
29
30

33
34

C

B

A

SYNC_MASTER=K24_MLB

PAGE TITLE

LVDS CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

90 OF 109

SHEET

67 OF 80

SIZE

A

D

345678

2 1

D

C9300

DP_IG_AUX_CH_P

74

3

SIGNAL_MODEL=DP_AUXCH_FET

D

OMIT

Q9300

SSM6N16FE

SOT563

DP_IG_AUX_CH_N

8

74

3

C

SIGNAL_MODEL=DP_AUXCH_FET

D

OMIT

Q9302

SSM6N16FE

SOT563

4

G S

5

4

G S

5

0.1UF

1 2

10%
16V
X5R
402

DP_EXT_DDC_CLK

C9303

0.0033UF

10%
50V
CERM
402

C9301

0.1UF

1 2

10%
16V
X5R
402

DP_EXT_DDC_DATA

1

GS

OMIT

2

Q9300

SSM6N16FE

SOT563

1

GS

OMIT

2

Q9302

SSM6N16FE

SOT563

6

D

SIGNAL_MODEL=DP_AUXCH_FET

376S0857

6

D

SIGNAL_MODEL=DP_AUXCH_FET

376S0857

DP_AUX_CH_C_P

DP_AUX_CH_C_N

8 8

8

D

C

DP_CA_DET

B

PART NUMBER

QTY

2

DESCRIPTION

XSTR,FT,N-CH,DUAL,SOT-563

REFERENCE DES

Q9300,Q9302

A

8 7 5 4 2 1

8

IN

CRITICAL

CRITICAL376S0859

BOM OPTION

B

SIZE

A

D

SYNC_MASTER=K69_MLB

PAGE TITLE

DISPLAYPORT SUPPORT

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/12/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

93 OF 109

SHEET

68 OF 80

36

D

=PP3V3_S5_DP_PORT_PWR

7

6

18 39 65

IN

C

8

79

8

79

79

79

DP_EXT_ML_P<3>

IN

DP_EXT_ML_N<3>

IN

DP_EXT_AUX_CH_C_P

8

BI

DP_EXT_AUX_CH_C_N

8

BI

=PP3V3_S0_DPCONN

7

69

=PP5VR3V3_S0_DPCADET

7

DP_EXT_CA_DET

8

OUT

C9414

C9415

0.1uF

0.1uF

B

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

PM_SLP_S3_L

1

2

1 2

79

1 2

79

Port Power Switch

CRITICAL

C9480

22UF

20%

6.3V
X5R-CERM-1
603

DP_EXT_ML_C_P<3>

16V

DP_EXT_ML_C_N<3>

16V

2N7002DW-X-G

X5R10% 402

R9443

100K

Q9440

SOT-363

1

C9481

0.1UF

20%
10V

2

CERM
402

40210% X5R

1

5%
1/16W
MF-LF

402

2

6

D

S

1

G

1

2

2

DP_CA_DET_Q_L

2N7002DW-X-G

CRITICAL

C9487

100UF

20%

6.3V
POLY-TANT
CASE-B2-SM

R9442

Q9440

SOT-363

345678

DP_ESD

CRITICAL

1

2

C9400

0.01UF

20%
16V
CERM
402

L9400

FERR-120-OHM-3A

0603

21

PP3V3_S0_DPPWR

MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

CRITICAL

J9400

DSPLYPRT-M97-1

BOT ROW TOP ROW

TH PINS SM PINS

2

HOT_PLUG_DETECT

4

CONFIG1

6

CONFIG2

8

GND

10

ML_LANE3P

12

ML_LANE3N

14

GND
AUX_CHP

18

AUX_CHN

20

DP_PWR

SHIELD PINS

DP_ESD

CRITICAL

D9400

RCLAMP0504F

SC70-6-1

6

1

2 5

4

3

F-RT-THSM

22

ML_LANE0P
ML_LANE0N

ML_LANE1P
ML_LANE1N

ML_LANE2P
ML_LANE2N

RETURN

21

514-0637

GND

GND

GND

1

3

5

7

9

79

11

79

13

1516

17

19

DP_EXT_ML_F_P<1>
DP_EXT_ML_F_N<1>

U9480

TPS2051B

SOT23

GND

2

G

1

OUT

3

OC*

FL9403

12-OHM-100MA

TCM1210-4SM

SYM_VER-2

4

3 2

5

1

2

C9485

0.1UF

20%
10V
CERM
402

1

TP_DPPWR_OC_L

1

C9486

10UF

20%

6.3V

2

X5R
603

1

R9420

100K

5%
1/16W
MF-LF

402

2

1

R9421

100K

5%
1/16W
MF-LF

402

2

DP_CA_DET_Q

R9422

1/16W
MF-LF

PP3V3_S0_DPILIM

MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

DP_EXT_ML_F_P<3>

79

DP_EXT_ML_F_N<3>

79

2

9

DP to DVI/HDMI

1

Cable Adapter

1M

(CA) has 100k

5%

pull-up to DP_PWR.

402

2

1

2

DP_ESD

CRITICAL

D9411

RCLAMP0524P

SLP2510P8

IO
NC NC

GND

3

HDMI_CEC

R9425

1M

5%
1/16W
MF-LF
402

1

IO

10

5

IN

4

EN

1

100K

5%
1/16W
MF-LF

402

2

3

D

S

4

CRITICAL

D9410

RCLAMP0524P

SLP2510P8

2

IO

9

NC NC

GND

3

DP_EXT_ML_F_P<0>

DP_EXT_ML_F_N<0>

79

79

79

FL9401

12-OHM-100MA

TCM1210-4SM

1

DP_EXT_ML_F_P<2>

DP_EXT_ML_F_N<2>

DP_ESD

CRITICAL

D9411

RCLAMP0524P

SLP2510P8

5

IO

6

NC NC

GND

3

1

IO

10

DP_EXT_ML_F_P<0>

79

SYM_VER-2

4

32

4

IO

7

DP_ESD

CRITICAL

D9410

RCLAMP0524P

SLP2510P8

5

IO

6

NC NC

3

FL9402

12-OHM-100MA

TCM1210-4SM

SYM_VER-2

1

GND

4

IO

7

FL9400

12-OHM-100MA

TCM1210-4SM

SYM_VER-2

1

4

32

4

79

32

2 1

DP_EXT_ML_C_P<0>

DP_EXT_ML_C_N<0>

79

DP_EXT_ML_C_P<1>

79

DP_EXT_ML_C_N<1>

79

DP_EXT_ML_C_P<2>

79

DP_EXT_ML_C_N<2>

79

C9410

C9411

C9412

C9413

C9416

C9417

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

1 2

1 2

1 2

1 2

1 2

1 2

DP_EXT_ML_P<0>

DP_EXT_ML_N<0>

DP_EXT_ML_P<1>

10% X5R 40216V

DP_EXT_ML_N<1>

DP_EXT_ML_P<2>

DP_EXT_ML_N<2>

10% 16V

D

8

X5R 40210% 16V

X5R

40216V10%

X5R 40210% 16V

40216V

X5R10%

402X5R

IN

8

IN

8

IN

8

IN

8

IN

8

IN

C

79

79

79

79

79

79

B

=PP3V3_S0_DPCONN

7

69

DP_EXT_HPD

8

OUT

2N7002DW-X-G

A

8 7 5 4 2 1

R9445

Q9441

SOT-363

1

10K

5%
1/16W
MF-LF

402

2

6

D

2

G

S

DP_HPD_Q_L

1

2N7002DW-X-G

R9444

Q9441

SOT-363

1

10K

5%
1/16W
MF-LF

402

2

3

D

5

G

S

4

DP_HPD_Q

R9423

100K

5%
1/16W
MF-LF

402

DP Source must pull

1

down HPD input with
greater than or equal

to 100K (DPv1.1a).

2

SYNC_MASTER=K24_MLB

PAGE TITLE

DisplayPort Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

94 OF 109

SHEET

69 OF 80

SIZE

A

D

36

*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

345678

2 1

SIZE

D

C

B

A

D

D

=PPBUS_SW_BKL

8

CRITICAL

C9712

1UF

10%

6.3V
X5R
402

10K

402

C9711

5%

PLACE_NEAR=U9701.22:3mm

0.1UF

NO STUFF

R9740

1

2

PLACE_NEAR=U9701.8:4mm

=PP3V3_S0_BKL_VDDIO

7

NO STUFF

1%

402

C9741

1 2

BKL_FLTR_R

R9741

1 2

1/16W
MF-LF

2

R9715

100K

1%
1/16W
MF-LF
402

1

C

NO STUFF

C9740

10UF

1 2

20%

6.3V
X5R
603

R9753

0

402

33

402

1 2

5%
1/16W
MF-LF

0

5%

5%

402

1

C9704

33PF

5%
50V

2

CERM
402

R9731

301K

1 2

1/16W
MF-LF

=I2C_BKL_1_SCL

42

IN

=I2C_BKL_1_SDA

42

BI

Addr: 0x58(Wr)/0x59(Rd)

PPBUS_SW_LCDBKLT_PWR

8

71

LCD_BKLT_PWM

8

IN

R9757

1 2

1/16W
MF-LF

R9704

1/16W
MF-LF

B

see spec for others

FOR LP8543:
STUFF R9741
NO STUFF R9740, C9740, C9741, R9754

PART NUMBER

103S0198 BKLT:ENG3

A

138S0673 CRITICAL

QTY

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

1371S0580

SCHOTTKY BARRIER DIODE RB160M-40

CAP, 50V, 1210, X5R, 10UF+/-10%

2

PLACE_NEAR=L9701.1:3mm

10UF

10%
25V

212

X5R
805

1

C9710

10%
16V

2

X5R
402

47.0K

1 2

1%
1/16W
MF-LF

402

TP_BKL_FAULT

NO STUFF

C9723

0.1UF

10%
25V
X5R
402

Fpwm=9.62kHz

DESCRIPTION

PLACE_NEAR=L9701.1:3mm

1

C9713

603-1

R9716

0.1UF

10%
25V
X5R
402

1UF

10%
25V
X5R

90.9K

1/16W
MF-LF

=PP5V_S0_BKL

7

NO STUFF

1

R9703

0

5%
1/16W
MF-LF
402

2

PPVIN_SW_BKL_R

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

PP5V_S0_BKL_VLDO

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

PLACE_NEAR=U9701.22:5mm

1

1

C9714

0.01UF

10%
16V

2

2

CERM
402

BKL_FSET
BKL_FLTR
BKL_ISET
BKL_SCL
BKL_SDA

BKL_PWM

BKL_EN

1

1

R9714

16.2K

1%

1%

402

2

I_LED=23.2mA

1/16W
MF-LF
402

2

GND_BKL_SGND

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

I_LED=610*1.23/Riset
(EEPROM should set EN_I_RES=1)

REFERENCE DES

R9717,R9718,R9719

R9720,R9721,R9722

C9797,C9799

8 7 5 4 2 1

D9701

NC

R9701

0

1 2

5%
1/16W
MF-LF

402

R9702

1/16W
MF-LF

402

VDDIO VLDO

6

GD

5

FSET

20

FILTER

3

ISET

11

SDA

2

PWM

7

FAULT

4

EN

33UH-1.8A-110MOHM

1

0

5%

2

22

8

U9701

LLP

LP8545SQX

VSYNC

OMIT

CRITICAL

THRM

GND_L

GND_SW

GND_S

1

9

15

XW9710

SM

1 2

CRITICAL

CRITICAL

L9701

1217AS-2SM

23

VIN

24

SW

21

FB

12

OUT1

13

OUT2

1410

OUT3SCLK

16

OUT4

17

OUT5

18

OUT6

19

PAD

25

BOOST_VOL:LOW

21

BKL_ISEN1
BKL_ISEN2

6

BKL_ISEN3

6

BKL_ISEN4
BKL_ISEN5
BKL_ISEN6
BKL_VSYNC_R

1

R9755

10K

5%
1/16W
MF-LF
402

2

BOM OPTION

BKLT:ENG103S0198 3

BOOST_VOL:HI

CRITICAL

D9701

SOD-123

PPBUS_SW_LCDBKLT_PWR_SW

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V
SWITCH_NODE=TRUE
DIDT=TRUE

NO STUFF

1

R9754

0

5%
1/16W
MF-LF
402

2

BKL_VSYNC

6

IN

67

1 2

RB160M-60G

10.2 ohm resistors for current
measurement on LED strings.

PLACE_NEAR=U9701.21:3mm

1

C9796

220PF

10%
50V

2

X7R-CERM
402

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

36

OMIT

1

C9797

10UF

10%
50V

2

X5R
1210

BKLT:PROD

R9717

0

1 2

5%
1/16W
MF-LF

402

BKLT:PROD

R9718

0

1 2

5%
1/16W
MF-LF

402

BKLT:PROD

R9719

0

1 2

5%
1/16W
MF-LF

402

BKLT:PROD

R9720

0

1 2

5%
1/16W
MF-LF

402

BKLT:PROD

R9721

0

1 2

5%
1/16W
MF-LF

402

BKLT:PROD

R9722

0

1 2

5%
1/16W
MF-LF

402

PPVOUT_SW_LCDBKLT

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V

OMIT

1

C9799

10UF

10%
50V

2

X5R
1210

LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

6

67

6

67

OUT

67

OUT

67

OUT

6

67

OUT

6

67

OUT

6

67

OUT

SYNC_MASTER=K69_MLB

PAGE TITLE

LCD Backlight Driver

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

97 OF 109

SHEET

70 OF 80

345678

2 1

D

=PPBUS_S0_LCDBKLT

7

C

2AMP-32V

8

24

F9800

0402-HF

LCD_BKLT_EN

IN

BKLT_PLT_RST_L

IN

21

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

1

R9808

301K

1%
1/16W
MF-LF
402

2

LCDBKLT_EN_DIV

1

R9809

147K

1%
1/16W
MF-LF
402

2

LCDBKLT_EN_L

SSM6N15FEAPE

Q9807

SOT563

C9802

0.1UF

10%
16V
X5R
402

3

D

5

SG

4

LCDBKLT_DISABLE

SSM6N15FEAPE

FDC638APZ_SBMS001

1

2

Q9807

SOT563

2

4

CRITICAL

Q9806

SSOT6-HF

3

6

D

SG

1

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

1 2 5 6

MOSFET

CHANNEL

RDS(ON)

LOADING

PPBUS S0 LCDBkLT FET

FDC638APZ

P-TYPE

43 mOhm @4.5V

0.65 A (EDP)

8

70

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

LCD Backlight Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

.

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

98 OF 109

SHEET

71 OF 80

345678

2 1

FSB (Front-Side Bus) Constraints

D

FSB_50S

FSB_DSTB_50S

SPACING_RULE_SET

FSB_DATA
FSB_DSTB
FSB_ADDR

FSB_ADSTB

FSB_1X

LAYER

LAYER

*

*
*
*
*
*

ALLOW ROUTE
ON LAYER?

=50_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC
=3x_DIELECTRIC

=2x_DIELECTRIC

=STANDARD

=STANDARD

MINIMUM LINE WIDTH

WEIGHT

?
?
?
?
?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

FSB_DATA
FSB_DSTB
FSB_ADDR

FSB_ADSTB

FSB_1X

MAXIMUM NECK LENGTH

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE
=50_OHM_SE=50_OHM_SE=50_OHM_SE

LAYER

TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=1:1_DIFFPAIR =1:1_DIFFPAIR

LINE-TO-LINE SPACING

WEIGHT

=4x_DIELECTRIC
=5x_DIELECTRIC
=3x_DIELECTRIC
=4x_DIELECTRIC
=3x_DIELECTRIC

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD*

TABLE_PHYSICAL_RULE_ITEM

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 4X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

CPU Signal Constraints

LAYER

CPU_50S

CPU_27P4S

C

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

SPACING_RULE_SET

LAYER

CPU_AGTL
CPU_8MIL
CPU_COMP

CPU_GTLREF

CPU_ITP

CPU_VCCSENSE

Most CPU signals with impedance requirements are 55-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

ALLOW ROUTE
ON LAYER?

* =STANDARD =STANDARD

=27P4_OHM_SE*

LINE-TO-LINE SPACING

*
*
*
*
*

=2:1_SPACING

*

=STANDARD

8 MIL
25 MIL
25 MIL

25 MIL

MINIMUM LINE WIDTH

=27P4_OHM_SE

WEIGHT

?
?
?
?
?
?

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE

=27P4_OHM_SE =27P4_OHM_SE

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

CPU_AGTL

SR DG recommends at least 25 mils, >50 mils preferred

LAYER

TOP,BOTTOM

LINE-TO-LINE SPACING

=2x_DIELECTRIC

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

MCP FSB COMP Signal Constraints

LAYER

MCP_50S

SPACING_RULE_SET

MCP_FSB_COMP

B

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4

LAYER

ALLOW ROUTE
ON LAYER?

* =STANDARD =STANDARD

LINE-TO-LINE SPACING

*

8 MIL

MINIMUM LINE WIDTH

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

FSB Clock Constraints

CLK_FSB_100D

SPACING_RULE_SET

CLK_FSB

LAYER

LAYER

*

*

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

LINE-TO-LINE SPACING

=3x_DIELECTRIC

MINIMUM LINE WIDTH

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRICCLK_FSB

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

7 MIL7 MIL

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

A

8 7 5 4 2 1

CPU / FSB Net Properties

ELECTRICAL_CONSTRAINT_SET

FSB_DATA_GROUP0
FSB_DATA_GROUP0
FSB_DSTB0
FSB_DSTB0

FSB_DATA_GROUP1
FSB_DATA_GROUP1
FSB_DSTB1
FSB_DSTB1

FSB_DATA_GROUP2
FSB_DATA_GROUP2
FSB_DSTB2
FSB_DSTB2

FSB 4X Signal Groups

FSB 2X

Signals

FSB 1X Signals

FSB_DATA_GROUP3
FSB_DATA_GROUP3
FSB_DSTB3
FSB_DSTB3

FSB_ADDR_GROUP0
FSB_ADDR_GROUP0
FSB_ADSTB0

FSB_ADDR_GROUP1
FSB_ADSTB1

FSB_1X FSB_1X
FSB_BREQ0_L

FSB_1X
FSB_1X
FSB_1X
FSB_1X

FSB_CPURST_L
FSB_1X
FSB_1X FSB_1X

CPU_ASYNC
CPU_BSEL
CPU_FERR_L
CPU_ASYNC
CPU_INIT_L
CPU_ASYNC_R
CPU_ASYNC_R
CPU_PROCHOT_L
CPU_PWRGD
CPU_ASYNC
CPU_ASYNC
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_FROM_SB
CPU_DPRSTP_L
CPU_ASYNC

FSB_CLK_CPU
FSB_CLK_CPU
FSB_CLK_ITP
FSB_CLK_ITP
FSB_CLK_MCP
FSB_CLK_MCP

CPU_IERR_L

PM_DPRSLPVR

(See above)

MCP_CPU_COMP MCP_FSB_COMP
MCP_CPU_COMP MCP_FSB_COMP
MCP_CPU_COMP MCP_FSB_COMP
MCP_CPU_COMP MCP_FSB_COMP

CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP CPU_COMP

XDP_TRST_L
XDP_BPM_L
XDP_BPM_L5

(FSB_CPURST_L)

CPU_VCCSENSE
CPU_VCCSENSE

(CPU_VCCSENSE)
(CPU_VCCSENSE)

NET_TYPE

PHYSICAL

FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S

FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S

FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S FSB_DSTB

FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S FSB_DSTB

FSB_50S
FSB_50S
FSB_50S

FSB_50S
FSB_50S

FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S

CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S

CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D

CPU_50S

CPU_50S
CPU_50S

MCP_50S
MCP_50S
MCP_50S
MCP_50S

CPU_50S
CPU_50S
CPU_27P4S
CPU_50S
CPU_27P4S

CPU_50SXDP_TDI CPU_ITP
CPU_50SXDP_TDO CPU_ITP
CPU_50SXDP_TMS CPU_ITP
CPU_50SXDP_TCK CPU_ITP
CPU_50S
CPU_50S
CPU_50S
CPU_50S

CPU_50S
CPU_50S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S

SPACING

FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB

FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB

FSB_DATA
FSB_DATA
FSB_DSTB

FSB_DATA
FSB_DATA
FSB_DSTB

FSB_ADDR
FSB_ADDR
FSB_ADSTB

FSB_ADDR
FSB_ADSTB

FSB_1X
FSB_1XFSB_1X
FSB_1XFSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1XFSB_1X
FSB_1XFSB_1X
FSB_1X
FSB_1X

CPU_AGTL
CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL

CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB

CPU_AGTL
CPU_AGTL

CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP

CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP

CPU_8MIL
CPU_8MIL
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE

FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>

FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>

FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>

FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>

FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>

FSB_A_L<35..17>
FSB_ADSTB_L<1>

FSB_ADS_L
FSB_BREQ0_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L

CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DPWR_L

FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N

CPU_IERR_L
PM_DPRSLPVR

IMVP_DPRSLPVR

MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND

CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>

XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CPURST_L

CPU_VID<6..0>
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N

36

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

6 9

9

13

9

13

9

13

9

13

9

13

9

13

6 9

6 9

6 9

9

12 13

9

13

9

13

13

9

8 9

9

13

9

13

9

13

9

13

9

13

9

13 40 61

9

12 13

9

13

9

13

9

13 40

9

13

9

13

9

13 61

9

13

9

13

9

13

12 13

12 13

13

13

9

13 61

61

13

13

13

13

9

28

9

9

9

9

9

12

9

12

9

12

9

12

9

12

9

12

9

12

12

10 61

10 61

10 61

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

D

C

B

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU/FSB Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/03/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

100 OF 109

SHEET

72 OF 80

345678

2 1

Memory Bus Constraints

LAYER

MEM_40S
MEM_70D

SPACING_RULE_SET

LAYER

MEM_CLK2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM

D

MEM_CMD2CMD
MEM_CMD2MEM

MEM_DATA2DATA

MEM_DATA2MEM =3:1_SPACING

MEM_DQS2MEM

MEM_2OTHER

ALLOW ROUTE
ON LAYER?

=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

=70_OHM_DIFF

* =70_OHM_DIFF =70_OHM_DIFF

LINE-TO-LINE SPACING

*
*
*
*
*
*

=4:1_SPACING

=2:1_SPACING
=2.5:1_SPACING
=1.5:1_SPACING

=3:1_SPACING
=1.5:1_SPACING

*
*

=3:1_SPACING

*

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK MEM_CLK
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CTRL

C

MEM_CTRL
MEM_CTRL
MEM_CTRL MEM_DATA
MEM_CTRL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DQS MEM_CLK
MEM_DQS

MEM_DQS

DDR3:

DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
CMD/CTRL signals should be matched within 150 ps.
All memory signals maximum length is 1.030 ps.

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

B

MCP MEM COMP Signal Constraints

MCP_MEM_COMP

SPACING_RULE_SET

MCP_MEM_COMP

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.2

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DQS

MEM_CTRL

MEM_CMDMEM_DQS

MEM_DATA

MEM_DQSMEM_DQS

LAYER

LAYER

*

ALLOW ROUTE
ON LAYER?

LINE-TO-LINE SPACING

=2x_DIELECTRIC

25 MIL

AREA_TYPE

*
*
*
*
*

AREA_TYPE

*
*
*
*
*

AREA_TYPE

*
*
*
*
*

MINIMUM LINE WIDTH

=70_OHM_DIFF

WEIGHT

?
?
?
?
?
?
?
?
?

SPACING_RULE_SET

MEM_CLK2MEM
MEM_CLK2MEM
MEM_CLK2MEM
MEM_CLK2MEM
MEM_CLK2MEM

SPACING_RULE_SET

MEM_CTRL2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM
MEM_CTRL2MEM
MEM_CTRL2MEM

SPACING_RULE_SET

MEM_DQS2MEM
MEM_DQS2MEM
MEM_DQS2MEM
MEM_DQS2MEM
MEM_DQS2MEM

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=70_OHM_DIFF =70_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

NV DG says 3x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 4x inner, 5x outer

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD
MEM_CMD

MEM_CLK

MEM_CTRL
MEM_CMD MEM_CMD
MEM_CMD
MEM_CMD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DATA
MEM_DATA
MEM_DATA

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMD
MEM_DATA MEM_DATA
MEM_DATA

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DQS

MEM_CLK

MEM_CTRL

* *

MEM_CMD

MEM_DATA

MEM_DQS

* *
* *

Need to support MEM_*-style wildcards!

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MAXIMUM NECK LENGTH

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE

A

MEM_A/B_CKE EC SET NAME IS CHANGED ON K6, CANNOT SYNC THIS PAGE FROM T27

8 7 5 4 2 1

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD* =STANDARD

AREA_TYPE

AREA_TYPE

AREA_TYPE

*
*
*
*
*

*
*
*
*
*

**

SPACING_RULE_SET

MEM_CMD2MEM
MEM_CMD2MEM
MEM_CMD2CMD
MEM_CMD2MEM
MEM_CMD2MEM

SPACING_RULE_SET

MEM_DATA2MEM
MEM_DATA2MEM
MEM_DATA2MEM

MEM_DATA2DATA

MEM_DATA2MEM

SPACING_RULE_SET

MEM_2OTHER
MEM_2OTHER
MEM_2OTHER

**

MEM_2OTHER
MEM_2OTHER

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD*

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK
MEM_A_CLK

MEM_A_CKE
MEM_A_CNTL
MEM_A_CNTL

MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD

MEM_A_DQ_BYTE0 MEM_40S
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3 MEM_40S
MEM_A_DQ_BYTE4 MEM_40S
MEM_A_DQ_BYTE5 MEM_40S
MEM_A_DQ_BYTE6 MEM_40S
MEM_A_DQ_BYTE7 MEM_40S

MEM_A_DQ_BYTE0 MEM_40S
MEM_A_DQ_BYTE1 MEM_40S
MEM_A_DQ_BYTE2 MEM_40S
MEM_A_DQ_BYTE3 MEM_40S
MEM_A_DQ_BYTE4 MEM_40S
MEM_A_DQ_BYTE5 MEM_40S

MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7

MEM_B_CLK
MEM_B_CLK

MEM_B_CKE
MEM_B_CNTL
MEM_B_CNTL

MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD

MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3

MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7

MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7

MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7

NET_TYPE

PHYSICAL

MEM_70D MEM_CLK
MEM_70D MEM_CLK

MEM_40S
MEM_40S
MEM_40S

MEM_40S
MEM_40S MEM_CMD
MEM_40S MEM_CMD
MEM_40S MEM_CMD
MEM_40S

MEM_40S
MEM_40S

MEM_40SMEM_A_DQ_BYTE6
MEM_40SMEM_A_DQ_BYTE7

MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D
MEM_70D
MEM_70D MEM_DQS

MEM_70D
MEM_70D

MEM_40S
MEM_40S
MEM_40S

MEM_40S
MEM_40S MEM_CMD
MEM_40S MEM_CMD
MEM_40S MEM_CMD
MEM_40S MEM_CMD

MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40SMEM_B_DQ_BYTE4
MEM_40S
MEM_40S
MEM_40S

MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S

MEM_70D

MEM_70D

MEM_CTRL
MEM_CTRL
MEM_CTRL

MEM_CMD

MEM_CMD

MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA

MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA

MEM_DQS

MEM_DQS

MEM_DQS

MEM_DQS
MEM_DQS

MEM_DQSMEM_70D

MEM_CLK
MEM_CLK

MEM_CTRL
MEM_CTRL
MEM_CTRL

MEM_CMD

MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA

MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA

MEM_DQSMEM_70D
MEM_DQS
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQS
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQSMEM_70D

MCP_MEM_COMPMCP_MEM_COMP MCP_MEM_COMP
MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

SPACING

MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>

MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>

MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>

MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>

MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>

MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>

MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>

MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>

MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND

36

14 25

14 25

14 20 25

14 25

14 25

14 25

14 25

14 25

14 25

14 25

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 26

14 26

14 20 26

14 26

14 26

14 26

14 26

14 26

14 26

14 26

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14 27

14

14

SYNC_MASTER=T27_MLB

PAGE TITLE

Memory Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/03/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

101 OF 109

SHEET

73 OF 80

SIZE

D

C

B

A

D

345678

2 1

PCI-Express

*

*
*
*

ALLOW ROUTE
ON LAYER?

=90_OHM_DIFF

=100_OHM_DIFF

LINE-TO-LINE SPACING

=3X_DIELECTRIC

LAYER

PCIE_90D

CLK_PCIE_100D =100_OHM_DIFF

SPACING_RULE_SET

LAYER

PCIE

CLK_PCIE

MCP_PEX_COMP

D

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.3

20 MIL

8 MIL

MINIMUM LINE WIDTH

=90_OHM_DIFF

=100_OHM_DIFF

WEIGHT

?
?
?

MINIMUM NECK WIDTH

=90_OHM_DIFF =90_OHM_DIFF

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

PCIE

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=90_OHM_DIFF =90_OHM_DIFF*

=100_OHM_DIFF =100_OHM_DIFF

LINE-TO-LINE SPACING

=4X_DIELECTRIC

NEED PCIe Gen1/Gen2 notes!

Analog Video Signal Constraints

LAYER

CRT_50S

SPACING_RULE_SET

LAYER

CRT
CRT_2CRT
CRT_2CLK

CRT_2SWITCHER

CRT_SYNC

MCP_DAC_COMP

C

CRT signal single-ended impedence varies by location:

- 37.5-ohm from MCP to first termination resistor.

- 50-ohm from first to second termination resistor.

- 75-ohm from output of three-pole filter to connector (if possible).
R/G/B signals should be matched as close as possible and < 10 inches.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1.

Digital Video Signal Constraints

LAYER

DP_90D

LVDS_100D

MCP_DV_COMP

SPACING_RULE_SET

LAYER

DISPLAYPORT

LVDS

LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils.
NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps.
DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max trace length: LVDS 10 inches, DP 8.5 inches.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.2

B

SATA Interface Constraints

LAYER

SATA_90D

SPACING_RULE_SET

LAYER

SATA

SATA_TERMP 8 MIL

SATA intra-pair matching should be 1 ps.
Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.6

A

8 7 5 4 2 1

*
*
*
*
*
*

*
*

*
*

*

*
*

ALLOW ROUTE
ON LAYER?

LINE-TO-LINE SPACING

20 MIL
15 MIL
50 MIL

250 MIL
=4x_DIELECTRIC
=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=90_OHM_DIFF*

=100_OHM_DIFF

Y

LINE-TO-LINE SPACING

=3x_DIELECTRIC
=3x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=90_OHM_DIFF

LINE-TO-LINE SPACING

=3x_DIELECTRIC

MINIMUM LINE WIDTH

=50_OHM_SE

MINIMUM LINE WIDTH

WEIGHT

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE

CRTCRT

MAXIMUM NECK LENGTH

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

20 MIL 20 MIL

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM LINE WIDTH

=100_OHM_DIFF=100_OHM_DIFF

SPACING_RULE_SET

DISPLAYPORT

LVDS

MINIMUM NECK WIDTH

=100_OHM_DIFF

=STANDARD

LAYER

TOP,BOTTOM
TOP,BOTTOM

MAXIMUM NECK LENGTH

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

WEIGHT

?
?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

SATA

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

AREA_TYPE

*

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF

=STANDARD =STANDARD

LINE-TO-LINE SPACING

=4x_DIELECTRIC
=4x_DIELECTRIC

DIFFPAIR PRIMARY GAP

=90_OHM_DIFF =90_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

CRT_2CRT

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

SPACING_RULE_SET

=90_OHM_DIFF=90_OHM_DIFF

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD* =STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MCP89 Net Properties

ELECTRICAL_CONSTRAINT_SET

PEG_R2D

PEG_D2R

PCIE_AP_R2D

NET_TYPENET_TYPE

PHYSICAL

PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE

PCIE_90D PCIE

PCIE_AP_D2R

PCIE_ENET_R2D

PCIE_ENET_D2R

PCIE_FW_R2D

PCIE_FW_D2R

MCP_PE0_REFCLK

MCP_PE1_REFCLK

MCP_PE2_REFCLK

MCP_PE3_REFCLK

MCP_PEX_CLK_COMP

CRT_GREEN
CRT_BLUE
CRT_SYNC

TMDS_IG_TXC
TMDS_IG_TXD
TMDS_IG_TXD DISPLAYPORT

DP_EXT_ML
DP_EXT_ML
DP_EXT_AUX_CH
DP_EXT_AUX_CH

MCP_TMDS0_RSET
MCP_TMDS0_VPROBE

LVDS_IG_A_CLK
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_IG_A_DATA
LVDS_IG_A_DATA3
LVDS_IG_A_DATA3
LVDS_IG_B_CLK
LVDS_IG_B_CLK
LVDS_IG_B_DATA
LVDS_IG_B_DATA
LVDS_IG_B_DATA3
LVDS_IG_B_DATA3

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D

CRT_50SCRT_RED
CRT_50S
CRT_50S
CRT_50S
CRT_50S

DP_90D
DP_90D
DP_90D
DP_90D

DP_90D
DP_90D
DP_90D
DP_90D

MCP_DV_COMP

LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D

MCP_DV_COMP

SATA_90D

SATA_HDD_D2R SATA_90D

SATA_90D

SATA_90D
SATA_90D
SATA_90D

SATA_90D
SATA_90D
SATA_90D

SATA_90D
SATA_90D

MCP_SATA_TERMP

SPACING

PCIEPCIE_90D
PCIEPCIE_90D

PCIEPCIE_90D
PCIEPCIE_90D

PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D

PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D

PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D
PCIEPCIE_90D

CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
MCP_PEX_COMP

CRT
CRT
CRT
CRT_SYNC
CRT_SYNCCRT_SYNC
MCP_DAC_COMPMCP_DAC_RSET
MCP_DAC_COMPMCP_DAC_VREF

DISPLAYPORTTMDS_IG_TXC
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS

SATASATA_HDD_R2D SATA_90D
SATA
SATASATA_90D
SATA
SATA
SATA
SATA
SATA
SATASATA_ODD_R2D SATA_90D
SATA
SATA
SATA
SATASATA_ODD_D2R SATA_90D
SATA
SATA
SATASATA_90D

SATA_TERMP

PEG_R2D_P<15..0>
PEG_R2D_N<15..0>
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
PEG_D2R_C_P<15..0>
PEG_D2R_C_N<15..0>

PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N

PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N

PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N

PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
MCP_PEX0_TERMP

CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
CRT_IG_HSYNC
CRT_IG_VSYNC
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF

TMDS_IG_TXC_P
TMDS_IG_TXC_N
TMDS_IG_TXD_P<5..0>
TMDS_IG_TXD_N<5..0>

DP_IG_ML_P<3..0>
DP_IG_ML_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N

MCP_TMDS0_RSET
MCP_TMDS0_VPROBE

LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<2..0>
LVDS_IG_B_DATA_N<2..0>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N

MCP_SATA_TERMP

6

6

15 29

15 29

6

6

31

31

15 31

15 31

15 31

15 31

31

31

33

33

15 33

15 33

15 33

15 33

33

33

8

8

15 29

15 29

15 31

15 31

15 33

15 33

15

8

8

8

8

8

8

8

8

8

8

8

16 23

16 23

8

8

6 8

6 8

16 23

16 23

17 36

17 36

6

6

17 36

17 36

6

6

17 36

17 36

6

6

17 36

17 36

36

36

17

29

29

15 29

15 29

15

15

68

68

67

67

36

36

36

36

36

36

D

C

B

67

67

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Constraints 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/03/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

102 OF 109

SHEET

74 OF 80

36

345678

2 1

LPC Bus Constraints

LAYER

LPC_55S

CLK_LPC_55S

SPACING_RULE_SET

LAYER

LPC

CLK_LPC

D

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.7

ALLOW ROUTE
ON LAYER?

* =STANDARD
*

LINE-TO-LINE SPACING

*

=1.5x_DIELECTRIC

*

=2x_DIELECTRIC

MINIMUM LINE WIDTH

WEIGHT

?
?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

USB 2.0 Interface Constraints

ALLOW ROUTE
ON LAYER?

*

=STANDARD

* =90_OHM_DIFF =90_OHM_DIFF

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*

MCP_USB_RBIAS

USB_90D

SPACING_RULE_SET

USB

LAYER

LAYER

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.8

MINIMUM LINE WIDTH

8 MIL

=90_OHM_DIFF

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SMBus Interface Constraints

*

ALLOW ROUTE
ON LAYER?

=55_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

SMB_55S

SPACING_RULE_SET

SMB

LAYER

LAYER

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.9

HD Audio Interface Constraints

C

LAYER

ALLOW ROUTE
ON LAYER?

HDA_55S

*
*

LINE-TO-LINE SPACING

=2x_DIELECTRIC

SPACING_RULE_SET

HDA

MCP_HDA_COMP

LAYER

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.10

8 MIL

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM LINE WIDTH

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE

WEIGHT

?
?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SIO Signal Constraints

CLK_SLOW_55S

SPACING_RULE_SET

CLK_SLOW

LAYER

LAYER

*

*

ALLOW ROUTE
ON LAYER?

LINE-TO-LINE SPACING

=1.5x_DIELECTRIC

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.11

MINIMUM LINE WIDTH

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SPI Interface Constraints

ALLOW ROUTE
ON LAYER?

* =STANDARD =STANDARD

LINE-TO-LINE SPACING

*

=1.5x_DIELECTRIC

B

SPI_55S

SPACING_RULE_SET

SPI

LAYER

LAYER

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.12

MINIMUM LINE WIDTH

=55_OHM_SE

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE

MINIMUM NECK WIDTH

8 MIL

=90_OHM_DIFF

SPACING_RULE_SET

USB

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=55_OHM_SE
=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

=STANDARD

=90_OHM_DIFF

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD*

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=90_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD
=STANDARD=STANDARD

=STANDARD=STANDARD

=STANDARD=STANDARD*

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MCP89 Net Properties

ELECTRICAL_CONSTRAINT_SET

LPC_AD
LPC_FRAME_L
LPC_RESET_L

MCP_LPC_CLK0

USB_EXTA

USB_MINI

USB_EXTD

USB_CAMERA

USB_BT

USB_TPAD

USB_IR

USB_EXTB

USB_T57

USB_EXTC

USB_SDCARD

USB_WM

PHYSICAL

LPC_55S
LPC_55S
LPC_55S

CLK_LPC_55S
CLK_LPC_55S
CLK_LPC_55S

USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D

NET_TYPE

MCP_USB_RBIASMCP_USB_RBIAS

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA
(SMBUS_SMC_MGMT_SCL)
(SMBUS_SMC_MGMT_SDA)

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

SMB_55S
SMB_55S
SMB_55S
SMB_55S

HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S

MCP_HDA_PULLDN_COMP

MCP_SUS_CLK

SPI_CLK SPI_55S

SPI_MOSI

SPI_MISO

SPI_CS0 SPI_55S

CLK_SLOW_55S CLK_SLOW

SPI_55S
SPI_55S
SPI_55S
SPI_55S

SPI_55S

SPI_55S
SPI_55S
SPI_55S
SPI_55S

SPI_55S
SPI_55S
SPI_55S
SPI_55S

SPACING

LPC
LPC
LPC

CLK_LPC
CLK_LPC
CLK_LPC

USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB

SMB
SMB
SMB
SMB

HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA

MCP_HDA_COMP

CLK_SLOWCLK_SLOW_55S

SPI
SPI
SPI
SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI

SPI
SPI
SPI
SPI

LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L

LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS

USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_MINI_P
USB_MINI_N
USB_EXTD_P
USB_EXTD_N
USB_CAMERA_P
USB_CAMERA_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_EXTB_P
USB_EXTB_N
USB_T57_P
USB_T57_N
USB_EXTC_P
USB_EXTC_N
USB_SDCARD_P
USB_SDCARD_N
USB_WM_P
USB_WM_N

MCP_USB_RBIAS_GND
SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA

HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDIN_CODEC
HDA_SDOUT
HDA_SDOUT_R

MCP_HDA_PULLDN_COMP
PM_CLK32K_SUSCLK_R

PM_CLK32K_SUSCLK
SPI_CLK_R

SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L

SPI_MLB_CLK
SPI_MLB_MOSI
SPI_MLB_MISO
SPI_MLB_CS_L

SPI_ALT_CLK
SPI_ALT_MOSI
SPI_ALT_MISO
SPI_ALT_CS_L

18 39 41

18 39 41

18 24

18 24

24 39

24 41

17 37

17 37

37 79

37 79

8

17

8

17

8

17

8

17

17 29

17 29

17 29

17 29

17 47

17 47

17 38

17 38

17 37

17 37

6

38

6

38

8

17

8

17

17 30

17 30

8

17

8

17

17

12 18 42

12 18 42

18 42

18 42

18 51

18

18 51

18

18

18 51

18 51

18 51

18

18

18 24

24 39

18 41

6

41

18 41

6

41

6

18 41

18 41

6

41

41 50

41 50

41 50

41 50

41

41

41

41

D

C

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Constraints 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/27/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

103 OF 109

SHEET

75 OF 80

SIZE

A

D

345678

2 1

MCP RGMII (Ethernet) Constraints

LAYER

MCP_MII_COMP
ENET_MII_55S

SPACING_RULE_SET

MCP_BUF0_CLK

ENET_MII

D

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

LAYER

ALLOW ROUTE
ON LAYER?

* =STANDARD
* =STANDARD=STANDARD

=55_OHM_SE

LINE-TO-LINE SPACING

*
*

=3:1_SPACING

MINIMUM LINE WIDTH

7.5 MIL

=55_OHM_SE =55_OHM_SE =55_OHM_SE

12 MIL

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

7.5 MIL

88E1116R (Ethernet PHY) Constraints

ENET_MDI_100D

SPACING_RULE_SET

ENET_MDI

LAYER

LAYER

*

*

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

LINE-TO-LINE SPACING

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

25 MIL

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SD Card Interface Constraints

SD_55S

SPACING_RULE_SET

SD_INTERFACE

LAYER

LAYER

ALLOW ROUTE
ON LAYER?

=55_OHM_SE =55_OHM_SE

*

LINE-TO-LINE SPACING

*

=3X_DIELECTRIC

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM NECK WIDTH

=55_OHM_SE

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

C

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

MAXIMUM NECK LENGTH

=55_OHM_SE

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF =100_OHM_DIFF

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

RGMII Net Properties

ELECTRICAL_CONSTRAINT_SET

MCP_MII_COMP MCP_MII_COMP
MCP_MII_COMP MCP_MII_COMP

MCP_CLK25M_BUF0

ENET_INTR_L
ENET_MDIO
ENET_MDC ENET_MII_55S
ENET_PWRDWN_L

ENET_RXCLK

ENET_RXD_STRAP
ENET_RXD_STRAP

ENET_TXCLK

Ethernet Net Properties

ELECTRICAL_CONSTRAINT_SET

ENET_MDI

SD Card Net Properties

ELECTRICAL_CONSTRAINT_SET

SD_DATA

SD_DATA_R

SD_CLK SD_55S

NOTE: SD_D<7..5> are different to support
BCM5764M/BCM57765 co-layout.

NET_TYPE

PHYSICAL

ENET_MII_55S

ENET_MII_55S
ENET_MII_55S

ENET_MII_55S

ENET_MII_55S ENET_MII
ENET_MII_55S
ENET_MII_55S

ENET_MII_55S ENET_MIIENET_RXD

ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S ENET_MIIENET_TXD

PHYSICAL

ENET_MDI_100D
ENET_MDI_100D

PHYSICAL

SD_55S
SD_55S
SD_55S

SD_55S
SD_55S
SD_55S

SD_55S
SD_55S

SD_55SSD_CMD
SD_55S
SD_55S

NET_TYPE

NET_TYPE

SPACING

MCP_BUF0_CLK
MCP_BUF0_CLKENET_MII_55S

ENET_MII
ENET_MII
ENET_MII
ENET_MII

ENET_MIIENET_MII_55S

ENET_MII
ENET_MII
ENET_MIIENET_MII_55S

ENET_MII
ENET_MIIENET_TXD
ENET_MIIENET_TXD

ENET_MIIENET_MII_55S

SPACING

ENET_MDI
ENET_MDI

SPACING

SD_INTERFACE
SD_INTERFACE
SD_INTERFACE

SD_INTERFACE
SD_INTERFACE
SD_INTERFACE

SD_INTERFACE
SD_INTERFACE
SD_INTERFACE

SD_INTERFACE
SD_INTERFACE
SD_INTERFACE

MCP_MII_COMP_VDD
MCP_MII_COMP_GND

MCP_CLK25M_BUF0_R
RTL8211_CLK25M_CKXTAL1

ENET_INTR_L
ENET_MDIO
ENET_MDC
ENET_PWRDWN_L

ENET_CLK125M_RXCLK_R
ENET_CLK125M_RXCLK
ENET_RXD_R<3..0>
ENET_RXD<0>
ENET_RXD<3..1>
ENET_RX_CTRL

ENET_CLK125M_TXCLK
ENET_TXD<0>
ENET_TXD<3..1>
ENET_TX_CTRL

ENET_RESET_L

ENET_MDI_P<3..0>
ENET_MDI_N<3..0>

SD_D<4..0>
SDCONN_DATA<4..0>
BCM57765_CR_DATA<4>

SD_D<7..5>
SDCONN_DATA<7..5>
BCM57765_CR_DATA<7..5>

SD_CLK
SD_CLK_R
SDCONN_CLK

SD_CMD
SDCONN_CMD
BCM57765_CR_CMD

17

17

8

8

8

8

8

24 31

31 32

31 32

30

30 31

31

30

30 31

31

30

30

30 31

30

30 31

31

17

D

17

17

17

17

C

SIZE

B

A

D

B

A

SYNC_MASTER=T27_MLB

PAGE TITLE

Ethernet Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 7 5 4 2 1

36

SYNC_DATE=11/23/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

104 OF 109

SHEET

76 OF 80

345678

2 1

FireWire Interface Constraints

FW_100D

SPACING_RULE_SET

FW_TP

LAYER

LAYER

*

*

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

LINE-TO-LINE SPACING

=3:1_SPACING

D

C

MINIMUM LINE WIDTH

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF=100_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

FireWire Net Properties

ELECTRICAL_CONSTRAINT_SET

FW_P0_TPA
FW_P0_TPA

FW_P0_TPB
FW_P0_TPB

FW_P1_TPA

FW_P1_TPA
FW_P1_TPB

FW_P1_TPB

Port 2 Not Used

FW_100D
FW_100D

FW_100D
FW_100D

FW_100D

FW_100D
FW_100D

FW_100D

PHYSICAL

NET_TYPE

FW_TP
FW_TP

FW_TP
FW_TP

FW_TP

FW_TP
FW_TP

FW_TP

SPACING

FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P1_TPB_P
FW_P1_TPB_N

33 35

33 35

33 35

33 35

33 35

33 35

33 35

33 35

D

C

SIZE

B

A

D

B

A

CANNOT SYNC THIS PAGE FROM T27, FW CONSTRAINTS CHANGED TO 100OHM DIFF

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

FireWire Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/20/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

105 OF 109

SHEET

77 OF 80

345678

2 1

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

1TO1_DIFFPAIR

LAYER

ALLOW ROUTE
ON LAYER?

*

MINIMUM LINE WIDTH

=STANDARD=STANDARD

MINIMUM NECK WIDTH

=STANDARD =STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

D

C

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA

SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA

SMB_55S
SMB_55S

SMB_55S
SMB_55S

SMB_55S

SMB_55S
SMB_55S

SMB_55S

SMB_55S
SMB_55S

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

CHGR_CSI

CHGR_CSO

1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR
1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR

1TO1_DIFFPAIR
1TO1_DIFFPAIR

PHYSICAL

PHYSICAL

NET_TYPE

NET_TYPE

SMB
SMB

SMB
SMB

SMB

SMB
SMB

SMB

SMB
SMB

SPACING

SPACING

SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA

CHGR_CSI_P
CHGR_CSI_N
CHGR_CSI_R_P
CHGR_CSI_R_N

CHGR_CSO_P
CHGR_CSO_N
CHGR_CSO_R_P
CHGR_CSO_R_N

6

6

42

42

42

42

6

6

42

42

58

58

58

58

58

58

44 58

44 58

42

42

42

42

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

SMC Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/28/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

106 OF 109

SHEET

78 OF 80

345678

2 1

SENSE_1TO1_55S
THERM_1TO1_55S

DIFFPAIR

SPACING_RULE_SET

D

SENSE
THERM
AUDIO

SPACING_RULE_SET

ENETCONN

SPACING_RULE_SET

GND

MEM_POWER

SPACING_RULE_SET

GND_P2MM
PWR_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK
MEM_CMD

C

MEM_CTRL GND_P2MM
MEM_DATA GND_P2MM

MEM_DQS

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PCIE
SATA

USB

SATA

USB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

LVDS

*
*
*

*
*
*

ALLOW ROUTE
ON LAYER?

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

LINE-TO-LINE SPACING

=2:1_SPACING
=2:1_SPACING
=2:1_SPACING

LINE-TO-LINE SPACING

LAYER

LAYER

LAYER

*

LAYER

LINE-TO-LINE SPACING

*
*

LAYER

LINE-TO-LINE SPACING

*
*

GND
GND
GND
GND
GND

GND
GND
GND

GND
SB_POWER PWR_P2MMCLK_PCIE
SB_POWER PWR_P2MM
SB_POWER PWR_P2MM

GND

25 MILS

=STANDARD
=STANDARD

0.20 MM

0.20 MM

AREA_TYPE

*
*
*
*
*

AREA_TYPE

*
*
*
*
*
*
*

AREA_TYPE

*

MINIMUM LINE WIDTH

=55_OHM_SE
=55_OHM_SE

WEIGHT

?
?
?

WEIGHT

?

WEIGHT

?
?

WEIGHT

1000
1000

SPACING_RULE_SET

GND_P2MM
GND_P2MM

GND_P2MM

SPACING_RULE_SET

GND_P2MMCLK_PCIE
GND_P2MM
GND_P2MM
GND_P2MM

SPACING_RULE_SET

GND_P2MM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

=55_OHM_SE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_GTLREF

CPU_VCCSENSE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

B

MCP Fanout Constraint Relaxations

LAYER

MEM_40S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_DV_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_MEM_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_MII_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_USB_RBIAS

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_DV_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

ALLOW ROUTE
ON LAYER?

*

TOP

TOP 0.1 MM

TOP

TOP 0.1 MM

*

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.09 MM

0.1 MM

0.1 MM

0.25 MM

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE
=55_OHM_SE

=1:1_DIFFPAIR

MEM_CLK

MEM_CMD
MEM_CTRL
MEM_DATA

MEM_DQS

MEM_POWER
MEM_POWER
MEM_POWER
MEM_POWER
MEM_POWER

CLK_FSB
CPU_COMP GND_P2MM

MAXIMUM NECK LENGTH

GND
GND
GND
GND

GND

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR =1:1_DIFFPAIR

AREA_TYPE

AREA_TYPE

*
*
*
*
*

*

SPACING_RULE_SET

PWR_P2MM
PWR_P2MM
PWR_P2MM
PWR_P2MM
PWR_P2MM

SPACING_RULE_SET

GND_P2MM
*
*
*

AREA_TYPE

*

DIFFPAIR PRIMARY GAP

GND_P2MM

GND_P2MM

SPACING_RULE_SET

GND_P2MMENET_MDI

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

5.8 MM

500 MIL

500 MIL

500 MIL

500 MIL

250 MIL

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Misc Net Properties

ELECTRICAL_CONSTRAINT_SET

(PCIE_AP)

(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
(USB_TPAD)
(USB_TPAD)
(USB_CAMERA)
(USB_CAMERA)

CLK_PCIE_100D
CLK_PCIE_100D

USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D

ENET_MDI_100D
ENET_MDI_100D

SATA_90D

SATA_90D

SATA_90D SATA
SATA_90D

SATA_90D
SATA_90D
SATA_90D
SATA_90D

SATA_90D
SATA_90D
SATA_90D SATA
SATA_90D SATA

SATA_90D SATA

Graphics Net Properties

ELECTRICAL_CONSTRAINT_SET

LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D

(DP_EXT_ML)

(DP_EXT_AUX_CH)

DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D
DP_90D

PHYSICAL

PHYSICAL

NET_TYPE

NET_TYPE

LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

SPACING

CLK_PCIE
CLK_PCIE

USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB

ENETCONN
ENETCONN

SATA
SATASATA_90D
SATASATA_90D
SATASATA_90D

SATA
SATASATA_90D

SATA

SATASATA_90D
SATA
SATA
SATA
SATA
SATASATA_90D
SATA
SATA

SATASATA_90D

SPACING

PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N

USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_LT1_P
USB_LT1_N
USB_TPAD_R_P
USB_TPAD_R_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_CONN_P
USB_BT_CONN_N
USB_LT2_P
USB_LT2_N

ENETCONN_P<3..0>
ENETCONN_N<3..0>

SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N

SATA_HDD_D2R_UF_P
SATA_HDD_D2R_UF_N
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_UF_N

SATA_HDD_D2R_RDRV_IN_P
SATA_HDD_D2R_RDRV_IN_N
SATA_HDD_R2D_RDRV_IN_P
SATA_HDD_R2D_RDRV_IN_N
SATA_HDD_D2R_RDRV_OUT_P
SATA_HDD_D2R_RDRV_OUT_N
SATA_HDD_R2D_RDRV_OUT_P
SATA_HDD_R2D_RDRV_OUT_N
SATA_HDD_D2R_NORDRV_P
SATA_HDD_D2R_NORDRV_N
SATA_HDD_R2D_NORDRV_P
SATA_HDD_R2D_NORDRV_N

LVDS_CONN_A_CLK_P
LVDS_CONN_A_CLK_N
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_DATA_P<2..0>
LVDS_CONN_A_DATA_N<2..0>
LVDS_CONN_B_CLK_P
LVDS_CONN_B_CLK_N
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
LVDS_CONN_B_DATA_P<2..0>
LVDS_CONN_B_DATA_N<2..0>

DP_EXT_ML_P<3..0>
DP_EXT_ML_N<3..0>
DP_EXT_ML_C_P<3..0>
DP_EXT_ML_C_N<3..0>
DP_EXT_ML_F_P<3..0>
DP_EXT_ML_F_N<3..0>
DP_EXT_AUX_CH_C_P
DP_EXT_AUX_CH_C_N
DP_AUX_CH_SW_P
DP_AUX_CH_SW_N

6

6

37 75

37 75

37

37

47

47

6

6

6

6

37

37

32

32

36

36

6

6

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

6

6

8

8

69

69

69

69

8

8

Power Net Properties

ELECTRICAL_CONSTRAINT_SET

29

29

CPUTHMSNS_D2

CPU_THERMD

MCPTHMSNS_D2

MCP_THMDIODE

29

29

29

29

36

36

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_DIFFPAIR

I277

THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S

SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S

SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S

Audio Net Properties

ELECTRICAL_CONSTRAINT_SET

DIFFPAIR

67

67

69

69

SPK_OUT

SPK_OUT

69

69

SPK_OUT

DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR

DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR

DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR

DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR

PHYSICAL

PHYSICAL

NET_TYPE

NET_TYPE

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO

SPACING

THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE

MEM_POWER

SB_POWER
SB_POWER
SB_POWER
GND

SPACING

CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N
MCPTHMSNS_D2_P
MCPTHMSNS_D2_N
MCP_THMDIODE_P

MCP_THMDIODE_N
ISNS_1V5_S3_P
ISNS_1V5_S3_N
ISNS_1V5_S3_R_P
ISNS_1V5_S3_R_N
ISNS_AIRPORT_P
ISNS_AIRPORT_N
ISNS_AIRPORT_R_P
ISNS_AIRPORT_R_N
ISNS_HDD_P
ISNS_HDD_N
ISNS_HDD_R_P
ISNS_HDD_R_N
ISNS_LCDBKLT_P
ISNS_LCDBKLT_N
ISNS_LCDBKLT_R_P
ISNS_LCDBKLT_R_N
ISNS_ODD_P
ISNS_ODD_N
ISNS_ODD_R_P
ISNS_ODD_R_N
ISNS_CPUVTT_P
ISNS_CPUVTT_N

MCPCORES0_VSEN_P

MCPCORES0_VSEN_N

PP1V5R1V35_S3

PP3V3_S5

PP3V3_S0

PP1V5_S0
GND

AUD_SPKRAMP_LIN_P

AUD_SPKRAMP_LIN_N

AUD_SPKRAMP_SUBIN_P

AUD_SPKRAMP_SUBIN_N

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_RIN_N

SSM2315L_P

SSM2315L_N

SSM2315S_P

SSM2315S_N

SSM2315R_P

SSM2315R_N

SPKRCONN_L_OUT_P

SPKRCONN_L_OUT_N

SPKRCONN_S_OUT_P

SPKRCONN_S_OUT_N

SPKRCONN_R_OUT_P

SPKRCONN_R_OUT_N

BI_MIC_P

BI_MIC_N

HS_MIC_P

HS_MIC_N

45

45

9

9

18 45

18 45

44

44

21 62

21 62

6 7

6 7

6 7

6 7

45

45

D

65

65

65

C

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

K6/K69 Specific Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/08/2009

DRAWING NUMBER

051-8563

REVISION

A.13.0

BRANCH

PAGE

108 OF 109

SHEET

79 OF 80

SIZE

A

D

345678

2 1

K6/K69 Board-Specific Physical & Spacing Constraints

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

STANDARD

D

55_OHM_SE

LAYER

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

*
*

Y
Y

ALLOW ROUTE
ON LAYER?

Y
Y*

ALLOW ROUTE
ON LAYER?

Y

*

Y

ALLOW ROUTE
ON LAYER?

Y

*

Y

ALLOW ROUTE
ON LAYER?

50_OHM_SE

40_OHM_SE

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

LAYER

27P4_OHM_SEYTOP,BOTTOM

C

27P4_OHM_SE

70_OHM_DIFF
70_OHM_DIFF
70_OHM_DIFF

90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF

100_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF

110_OHM_DIFF
110_OHM_DIFF
110_OHM_DIFF

*

LAYER

*

ISL3,ISL4,ISL9,ISL10

TOP,BOTTOM

LAYER

*

ISL3,ISL4,ISL9,ISL10

TOP,BOTTOM

LAYER

* =STANDARD

ISL3,ISL4,ISL9,ISL10

TOP,BOTTOM

LAYER

*

ISL3,ISL4,ISL9,ISL10

TOP,BOTTOM

Y

ALLOW ROUTE
ON LAYER?

N
Y
Y

ALLOW ROUTE
ON LAYER?

N
Y
Y

ALLOW ROUTE
ON LAYER?

N
Y
Y

ALLOW ROUTE
ON LAYER?

N
Y
Y

MINIMUM LINE WIDTH

=50_OHM_SE

=DEFAULT

MINIMUM LINE WIDTH

0.090 MM

0.076 MM

MINIMUM LINE WIDTH

0.115 MM

0.076 MM

MINIMUM LINE WIDTH

0.165 MM

0.126 MM

MINIMUM LINE WIDTH

0.310 MM

0.222 MM

MINIMUM LINE WIDTH

=STANDARD

0.151 MM

0.185 MM

MINIMUM LINE WIDTH

=STANDARD

0.095 MM

0.112 MM

MINIMUM LINE WIDTH

=STANDARD

0.075 MM

0.091 MM

MINIMUM LINE WIDTH

=STANDARD

0.075 MM

0.077 MM

MINIMUM NECK WIDTH

0.080 MM
=DEFAULT

MINIMUM NECK WIDTH

0.090 MM

0.076 MM

MINIMUM NECK WIDTH

0.115 MM

0.076 MM

MINIMUM NECK WIDTH

0.100 MM

0.100 MM

MINIMUM NECK WIDTH

0.310 MM

0.222 MM

MINIMUM NECK WIDTH

=STANDARD

0.109 MM

0.185 MM

MINIMUM NECK WIDTH

=STANDARD =STANDARD

0.095 MM

0.112 MM

MINIMUM NECK WIDTH

=STANDARD

0.075 MM

0.091 MM

MINIMUM NECK WIDTH

0.075 MM

0.077 MM

BOARD AREAS

NO_TYPE,BGA

MAXIMUM NECK LENGTH

12.7 MMDEFAULT

12.7 MM

MAXIMUM NECK LENGTH

=STANDARD55_OHM_SE

MAXIMUM NECK LENGTH

=STANDARD50_OHM_SE

MAXIMUM NECK LENGTH

=STANDARD40_OHM_SE

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD
=STANDARD

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

0.224 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

0.244 MM

0.230 MM 0.230 MM

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

0.330 MM 0.330 MM

0.330 MM 0.330 MM

BOARD UNITS
(MIL or MM)

MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=DEFAULT=DEFAULT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

0.090 MM

0.200 MM0.200 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

0.234 MM0.234 MM

0.220 MM0.220 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

0.244 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_BOARD_INFO

ALLEGRO
VERSION

15.2

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0 MM0 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SPACING_RULE_SET

DEFAULT
STANDARD
BGA_P1MM
BGA_P2MM
BGA_P3MM

SPACING_RULE_SET

1.5:1_SPACING
2:1_SPACING

2.5:1_SPACING
3:1_SPACING
4:1_SPACING

SPACING_RULE_SET

2X_DIELECTRIC
3X_DIELECTRIC
4X_DIELECTRIC
5X_DIELECTRIC

LAYER

LAYER

LAYER

TOP,BOTTOM1.5X_DIELECTRIC
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM

1.5X_DIELECTRIC
2X_DIELECTRIC

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

3X_DIELECTRIC
4X_DIELECTRIC
5X_DIELECTRIC

*
*
*
*
*

*
*
*
*
*

*
*
*
*
*

LINE-TO-LINE SPACING

0.1 MM

=DEFAULT

0.1 MM

0.2 MM

0.3 MM

LINE-TO-LINE SPACING

0.15 MM

0.2 MM

0.25 MM

0.3 MM

0.4 MM

LINE-TO-LINE SPACING

0.105 MM

0.140 MM

0.210 MM

0.280 MM

0.350 MM

0.095 MM

0.126 MM

0.189 MM

0.252 MM

0.315 MM

WEIGHT

WEIGHT

WEIGHT

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

*
MEM_CLK
CLK_FSB
CLK_LPC

CLK_PCIE BGA_P2MM
CLK_SLOW BGA_P2MM
FSB_DSTB BGA_P3MM

*
*
*
*
*
*

FSB_DSTB

AREA_TYPE

BGA
BGA
BGA
BGA
BGA
BGA
BGA

SPACING_RULE_SET

BGA_P1MM
BGA_P2MM
BGA_P2MM
BGA_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

NET_PHYSICAL_TYPE

MEM_40S

AREA_TYPE

BGA

STANDARD

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

D

C

B

A

1:1_DIFFPAIR

LAYER

ALLOW ROUTE
ON LAYER?

*

Y

MINIMUM LINE WIDTH

=STANDARD

MINIMUM NECK WIDTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

8 7 5 4 2 1

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SYNC_MASTER=T27_MLB

PAGE TITLE

K6/K69 PCB Rule Definitions

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/06/2009

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

36

051-8563

A.13.0

109 OF 109

80 OF 80

SIZE

B

A

D